110 lines
2.9 KiB
C
110 lines
2.9 KiB
C
/* @(#)devaddr.h 1.1 94/10/31 SMI */
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/*
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* Copyright (c) 1990 by Sun Microsystems, Inc.
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*/
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/*
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* This file contains device addresses for the architecture.
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*/
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#ifndef _sun4m_devaddr_h
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#define _sun4m_devaddr_h
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/*
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* Fixed virtual addresses.
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* Allocated from the top of the
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* available virtual address space
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* and working down. Note that MP
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* systems use 0xFD[0123]..... and
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* 0xFC0...... for per-cpu mappings;
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* it is convenient to place some
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* devices that are per-cpu into this
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* mapping scheme.
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* We may be able to lower COUNTER_PGS
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* and INT_REGS_PGS to zero, if we decide
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* to use the per-cpu mappings to the
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* devices.
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*/
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#define PERCPU_SHIFT 20
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#define PERCPUSIZE 0x00100000
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/*
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* NOTE: NCPU is actually the number of
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* sets of counter/timer and interrupt
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* registers supported by the Sun-4M
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* archetecture specification. A better
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* name might be nice, since we may want
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* to support fewer "CPUs" while still
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* doing the right thing with the mappings.
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*/
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/* #define NCPU 4 */ /* moved to sun4m/param.h */
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#define V_WKBASE_ADDR 0xFEFE0000
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#define V_IOMMU_ADDR (V_WKBASE_ADDR+0x0000)
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#define V_IOMMU_PGS 1
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/* page 0x2-0x9 spare */
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#define V_SBUSCTL_ADDR (V_WKBASE_ADDR+0xA000)
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#define V_SBUSCTL_PGS 1
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/* page 0xC-0xE spare */
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#define V_MEMERR_ADDR (V_WKBASE_ADDR+0xF000)
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#define V_MEMERR_PGS 1
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#define V_AUXIO_ADDR (V_WKBASE_ADDR+0x10000)
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#define V_AUXIO_PGS 1
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#define V_VMECTL_ADDR (V_WKBASE_ADDR+0x11000)
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#define V_VMECTL_PGS 2
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#define V_INTERRUPT_ADDR (V_WKBASE_ADDR+0x14000)
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#define V_INTERRUPT_PGS 5
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#define V_COUNTER_ADDR (V_WKBASE_ADDR+0x19000)
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#define V_COUNTER_PGS 5
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#define V_EEPROM_ADDR (V_WKBASE_ADDR+0x1E000)
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#define V_EEPROM_PGS 2
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/* compatibility */
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#define EEPROM_ADDR 0xFEFFE000 /* need EEPROM_PGS pages */
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#define V_CLK1ADDR 0xFEFFFFF8
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#define COUNTER_ADDR 0xFEFF9000 /* need COUNTER_PGS pages */
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#define V_INT_REGS 0xFEFF4000 /* need INT_REGS_PGS pages */
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#define V_SYSCTL_REG 0xFEFF3000
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#define V_VMEBUS_VEC 0xFEFF2000 /* vme interface vec reg */
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#define V_VMEBUS_ICR 0xFEFF1000 /* vme interface ctl reg */
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#define AUXIO_ADDR 0xFEFF0000
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#define MEMERR_ADDR 0xFEFEF000
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/*
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* See "genpercpu.c" and various "percpu.h" files
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* for mapping layouts.
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*/
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#define VA_PERCPU 0xFE000000 /* base of per-cpu mapping area */
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#define VA_PERCPUME 0xFD000000 /* base of cpu-me mapping area */
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#define EEPROM_PGS 0x2 /* Pages needed for EEPROM */
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#define INT_REGS_PGS 0x5 /* Pages needed for inter. reg */
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#define COUNTER_PGS 0x5 /* Pages needed for timers reg */
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#define SBUS_PGS 0x3 /* Pages needed for sbus control regs */
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/* Physical addresses to be used with bypass mode (ASI_MMUPASS or ASI_CTL) */
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#define DIAGREG 0xF1600000
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/* VMEbus Interface control register mask defines */
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#define VMEICP_IOC 0x80000000 /* IOCache enable */
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#ifndef LOCORE
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#define VMEBUS_ICR (u_int *) V_VMEBUS_ICR
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#endif !LOCORE
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#endif /*!_sun4m_devaddr_h*/
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