128 lines
3.1 KiB
ArmAsm
128 lines
3.1 KiB
ArmAsm
/* @(#)proc_init.s 1.1 94/10/31 SMI */
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/*
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* Copyright (c) 1988 by Sun Microsystems, Inc.
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*/
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#ifdef MULTIPROCESSOR
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#include <sys/param.h>
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#include <machine/vmparam.h>
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#include <sys/errno.h>
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#include <machine/asm_linkage.h>
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#include <machine/cpu.h>
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#include <machine/intreg.h>
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#include <machine/mmu.h>
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#include <machine/pcb.h>
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#include <machine/psl.h>
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#include <machine/pte.h>
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#include <machine/reg.h>
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#include <machine/trap.h>
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#include <machine/scb.h>
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#include "percpu_def.h"
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#include "assym.s"
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/*
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* Processor initialization
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*
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* The boot prom turns control over to us with the MMU
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* turned on and the context table set to whatever the
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* master asked for. How nice!
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*/
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ENTRY(cpuX_startup)
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set RMMU_CTP_REG, %g1 ! read ctp register
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lda [%g1]ASI_MOD, %g1 ! just to verify it.
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set PSR_S|PSR_PIL, %g1
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mov %g1, %psr ! setup psr, disable traps
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nop ; nop
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mov 0x02, %wim ! setup wim
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mov 0, %fp ! setup frame
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set ekernstack - SA(MINFRAME + REGSIZE), %g1
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mov %g1, %sp ! set stack pointer
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#ifndef PC_vscb
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set scb, %g1
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#else PC_vscb
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sethi %hi(_cpuid), %g2
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ld [%g2+%lo(_cpuid)], %g2
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set VA_PERCPU+PC_vscb, %g1
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sll %g2, PERCPU_SHIFT, %g2
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or %g1, %g2, %g1
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#endif PC_vscb
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mov %g1, %tbr ! set trap base
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set _idleuarea, %l0 ! point uunix at idleuarea
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sethi %hi(_uunix), %l1 ! must be before traps are enabled.
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st %l0, [%l1+%lo(_uunix)];
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!
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! Dummy up fake user registers on the stack.
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!
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set USRSTACK-WINDOWSIZE, %g1
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st %g1, [%sp + MINFRAME + SP*4] ! user stack pointer
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set PSL_USER, %l0
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st %l0, [%sp + MINFRAME + PSR*4] ! psr
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set USRTEXT, %g1
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st %g1, [%sp + MINFRAME + PC*4] ! pc
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add %g1, 4, %g1
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st %g1, [%sp + MINFRAME + nPC*4] ! npc
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! invalidate the dual (one-to-one) mapping for low memory,
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! we do not need it any more.
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sethi %hi(_cache), %l0
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ld [%l0 + %lo(_cache)], %l0
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cmp %l0, CACHE_PAC_E !CC mode?
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bne 1f !No, don't cache the
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set RMMU_CTP_REG, %l0
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!
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! We need to set the AC bit.
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!
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lda [%l0]ASI_MOD, %l0 ! get context table ptr
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sll %l0, 4, %l0 ! convert to paddr
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lda [%g0]ASI_MOD, %l1 ! get MMU CSR
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set CPU_VIK_AC, %l2 ! AC bit
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or %l1, %l2, %l2 ! or in AC bit
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sta %l2, [%g0]ASI_MOD ! store new CSR
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lda [%l0]ASI_MEM, %l0 ! get level 1 table ptr
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srl %l0, 4, %l0 ! mask off dont-cares
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sll %l0, 8, %l0 ! convert to paddr
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sta %g0, [%l0]ASI_MEM ! zero out the entry
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call _mmu_flushall ! flush the MMU
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sta %l1, [%g0]ASI_MOD ! restore CSR;
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b 2f
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nop
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1: lda [%l0]ASI_MOD, %l0 ! get context table ptr
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sll %l0, 4, %l0 ! convert to paddr
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lda [%l0]ASI_MEM, %l0 ! get level 1 table ptr
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srl %l0, 4, %l0 ! mask off dont-cares
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sll %l0, 8, %l0 ! convert to paddr
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call _mmu_flushall ! flush the MMU, after
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sta %g0, [%l0]ASI_MEM ! zeroing out the entry
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2: mov %psr, %g1
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wr %g1, PSR_ET, %psr ! enable traps
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nop ; nop
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! Call pxmain, which will return as the idle process
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! for our appropriate CPU
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call _pxmain
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add %sp, MINFRAME, %o0
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!
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! Proceed as if this was a normal user trap.
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! Safety; won't be here anyways
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!
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b,a _idlework
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#endif MULTIPROCESSOR
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