227 lines
6.3 KiB
Plaintext
227 lines
6.3 KiB
Plaintext
|* @(#)misc.u 1.1 94/10/31 Copyright Sun Microsystems, Inc. 1988
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|*
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|* Initialize Instruction
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|*
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|* In FPA-3, used to load bits 4-11 of the MODE register/.
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|* These set up the frequency and flowthrough mode.
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|* They do not exist or are needed in the FPA-3X, so we just
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|* Do a dummy routine, so that FPA-3 binaries don't break :-)
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routine c.init 001001011110 ; ; ;
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call idle1; ; ; ;
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|*
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|* Restore STATUS register
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|*
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|* This instruction will: 1) set the valid bit, 2) reset the unimplemented
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|* instruction bit, 3) set all other bits according to bits 11:8 in the
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|* operand.
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routine c.rest.wstat 001001010110 ; ; ;
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cstat; ; restore; ;
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call idle1; ; ; ;
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|*
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|* Update Shadow registers.
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|* This routine is here for backwards compatibility.
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routine c.update 001001110001 ; ; ;
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; ; ; ptr1; lpreg!8
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usr.loop:
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; ; regtotmp; rcsmsw ptr1; lpreg-
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; ; ; ;
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; ; tmptoreg; rcsmsw ptr1;
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; ; regtotmp; rcslsw ptr1;
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; ; ; ;
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jloop usr.loop; ; tmptoreg; rcslsw ptr1;
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; ; ; ptr1; ptr1+
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call idle1; ; ; ;
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|*
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|* Load MODE control bits 3-0
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|*
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routine c.ld3.0 00100011010x enra halt; adtoti; ;
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|* Check to see that operand is > 0. If not, error.
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; ; ; ptr5; ptr5!szero
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; scmp enrb halt; regtoti; rcssp ptr5;
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; ; ; ; ptr5!c_smaxmode
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jlt hang cstat; halt; ; ptr5;
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|* Check to see that operand <= c_smaxmode (or operand > c_smaxmode)
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; scmp enrb halt; regtoti; rcssp ptr5;
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; ; ; ; ptr5!c_dmode
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jgt hang cstat; halt; ; ptr5;
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|* Write the new mode3-0 value into c_dmode. Only the msw needs to be loaded, though.
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; ; ; ptr5;
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; ; adtoreg; rcsmsw ptr5; mreg!0x10
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|* Load mode3-0 from the pipeline
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call idle1; ; ; ;
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|*
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|* Read Register MSW via the Load Pointer
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|*
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routine c.rdregmsw 1011101000x0 halt; ; lptr;
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call idle1; halt; readreg; rcsmsw lptr;
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|*
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|* Read Register LSW via the Load Pointer
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|*
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routine c.rdreglsw 1011101000x1 halt; ; lptr;
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call idle1; halt; readreg; rcslsw lptr;
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|*
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|* Write Register MSW via the Load Pointer
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|*
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routine c.wrregmsw 0011101000x0 halt; ; lptr;
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call idle1; halt; adtoreg; rcsmsw lptr;
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|*
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|* Write Register LSW via the Load Pointer
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|*
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routine c.wrreglsw 0011101000x1 halt; ; lptr;
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call idle1; halt; adtoreg; rcslsw lptr;
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|*
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|* Read Register Access (MSW)
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|*
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routine reg_read_msw 101100xxxxx0 halt; readreg; rcsmsw imm2;
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pipe idl1; snop halt; ; imm2;
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|*
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|* Read Register Access (LSW)
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|*
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routine reg_read_lsw 101100xxxxx1 halt; readreg; rcslsw imm2;
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pipe idl1; snop halt; ; imm2;
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|*
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|* Write Register Access (MSW)
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|*
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routine reg_write_msw 001100xxxxx0 halt; adtoreg; rcsmsw imm2;
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routine shadow_write_msw 00111000xxx0 halt; adtoreg; rcsmsw imm2;
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pipe idl1; snop halt; ; imm2;
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|*
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|* Write Register Access (LSW)
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|*
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routine reg_write_lsw 001100xxxxx1 halt; adtoreg; rcslsw imm2;
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routine shadow_write_lsw 00111000xxx1 halt; adtoreg; rcslsw imm2;
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pipe idl1; snop halt; ; imm2;
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|*
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|* IDLE1 Routine
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|*
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idle1:
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pipe idl1; snop halt; ; imm2;
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|*
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|* Clear Pipe Clean-up Routines
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|*
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clp2:
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clp:
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clp1:
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call idle1; halt; ; ;
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|*
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|* TI Error Routines
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|*
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|* Whenever the TI chip gets an error, we hang. For instructions that have
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|* written to reg 1, we must restore it from the temp register.
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|*
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|* Double Precision - restore from temp to ptr4 register
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der4:
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; halt; ; ptr4;
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call hang; halt; tmptoreg; rcslsw ptr4;
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|* Double Precision - restore from temp to ptr2 register
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der2:
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; halt; ; ptr2;
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call hang; halt; tmptoreg; rcslsw ptr2;
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|*
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|* Double Precision - restore from temp to ptr1 register
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der1:
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; halt; ; ptr1;
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call hang; halt; tmptoreg; rcslsw ptr1;
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|*
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|* Single Precision - restore from temp to ptr2 register
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ser2:
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; halt; ; ptr2;
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call hang; halt; tmptoreg; rcssp ptr2;
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|*
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|* Single Precision - restore from temp to ptr1 register
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ser1:
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; halt; ; ptr1;
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call hang; halt; tmptoreg; rcssp ptr1;
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|*
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|*
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tierr:
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call hang; halt; ; ;
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|*
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hang:
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hng; ; ; ;
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call idle1; ; ; ;
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|*
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|*
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|* Invalid Instructions
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|*
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|* Shadow Ram Accesses
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routine inv.h1 10111000xxxx
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|* Other Register Accesses
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routine inv.r1 x01111xxxxxx
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|* Register Accesses Via the Load Pointer
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routine inv.l1 x011101001xx
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routine inv.l2 x01110101xxx
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|* NOTE: 00111011111x is Defined as an invalid instruction forever more
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|* (it's used in the O.S. to generate the unimplimented status.)
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routine inv.l3 x0111011xxxx
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|* Single Precision
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routine inv.s1 100xxxxxxxx0
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|* Command
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routine inv.c1 1010xxxxxxxx
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routine inv.c2 00101001010x
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routine inv.c3 00101001100x
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routine inv.c4 00101011010x
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routine inv.c5 00101100010x
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routine inv.c6 00101100110x
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routine inv.c7 00101101010x
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routine inv.c8 001011011x0x
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routine inv.c9 00101110110x
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routine inv.ca 00101111110x
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routine inv.cb 0010000101x0
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routine inv.cc 001000011xx0
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routine inv.cd 00100011011x
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routine inv.ce 001000111xxx
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routine inv.cf 00100110111x
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routine inv.cg1 001001110000
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routine inv.cg3 0010011101xx
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routine inv.cg4 001001111xxx
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routine inv.ch1 001001011111
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routine inv.ch 00100101110x
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routine inv.ci 001001011011
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routine inv.ci2 00100101100x
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routine inv.cj 00100101010x
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routine inv.ck 0010010100xx
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routine inv.cl 00100100xxx0
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routine inv.cm 001001010111
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|routine inv.cn 00100001001x
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routine inv.stan 001000000100
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routine inv.dtan 001000000101
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|* Write Weitek Status
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routine inv.w1 10111001xxxx
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|* Not Used (some detected by hardware)
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routine inv.nu1 x01101xxxxxx
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|routine inv.nu2 001110010101
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|routine inv.nu3 001110010110
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routine inv.nu4 001110010111
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|routine inv.nu5 001110011001
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|routine inv.nu6 001110011010
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|routine inv.nu7 001110011011
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|routine inv.nu8 001110011100
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|routine inv.nu9 001110011101
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routine inv.nua 001110011110
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routine inv.nub 001110011111
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invalid:
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; ; ; ;
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cstat unimpl; ; ; ;
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hng; ; ; ;
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call idle1; ; ; ;
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routine inv.x1 110000000000
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routine inv.x2 01000xxxxxx1
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routine inv.x3 010010xxxxx1
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|routine inv.x4 01011xxxxxxx
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routine inv.x4a 0101110xxxx0
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routine inv.x4b 0101111xxxx0
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routine inv.x5 0111011xxxxx
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|routine inv.x6 01111xxxxxxx
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routine inv.x6a 0111100xxxx0
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routine inv.x6b 0111101xxxx0
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routine inv.x6c 0111110xxxx0
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routine inv.x6d 0111111xxxx0
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invalid2:
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; ; ; ;
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jclr clp idl2; ; ; ;
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cstat unimpl; ; ; ;
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hng; ; ; ;
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call idle1; ; ; ;
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