112 lines
4.0 KiB
C
112 lines
4.0 KiB
C
/* @(#)gtconfig.h 1.1 94/10/31 */
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/*
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* Copyright (c) 1990 by Sun Microsystem, Inc.
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*/
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#define FBNAME "/dev/gt"
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#define WCS_DATE 0
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#define WCS_VERSION 1
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#define EXEC_VERSION 2
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#define KERNEL_MCB_PTR 3
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/* SU addresses */
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#define SU_CSR_ADDR 0x00080000 /* SU processor CSR */
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#define SU_DSP_RUN_SHIFT 0 /* Shift value for run bits */
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#define SU_DSP_RUN_MASK 0x00000007 /* Run bits for 3 DSPs */
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#define SU_DSP_RUN_0 0x00000001 /* Run bit for DSP 0 */
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#define SU_DSP_RUN_1 0x00000002 /* Run bit for DSP 1 */
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#define SU_DSP_RUN_2 0x00000004 /* Run bit for DSP 2 */
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#define SU_DSP_DISABLE_SHIFT 3 /* Shift value for disable */
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#define SU_DSP_DISABLE_MASK 0x00000038 /* Disable bits for 3 DSPs */
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#define SU_DSP_DISABLE_0 0x00000008 /* Disable bit for DSP 0 */
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#define SU_DSP_DISABLE_1 0x00000010 /* Disable bit for DSP 1 */
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#define SU_DSP_DISABLE_2 0x00000020 /* Disable bit for DSP 2 */
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#define SU_INPUT_DATA_READY 0x00000800 /* Data ready at input FIFO */
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#define SU_OUTPUT_DATA_READY 0x00001000 /* Data ready at output FIFO */
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#define SU_FIFO_NOT_FULL 0x00002000 /* SU fifo NOT full */
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#define SU_FIFO_FULL_INT_ENA 0x00004000 /* SU full interrupt enable */
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/* Edge Walker addresses */
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#define EW_CSR_ADDR 0x00080010 /* EW CSR */
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#define EW_CSR_AA 0x00000001 /* Antialiasing on */
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#define EW_CSR_SF 0x00000002 /* Semaphore flag */
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#define EW_CSR_RESET 0x00000004 /* Hold EW in reset state */
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#define EW_CSR_HELD 0x00000008 /* EW Held by SI */
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#define EW_CSR_ODR 0x00000010 /* Output data ready */
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#define EW_CSR_AD 0x00000020 /* Accepting data */
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#define EW_CSR_ISE 0x00000040 /* Input sequence error */
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#define EW_CSR_CFIFO 0x00000F80 /* Command FIFO */
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#define EW_CSR_ISE_INT_ENA 0x40000000 /* Enable interrupt for ISE */
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/* Span Interpolator addresses */
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#define SI_CSR1_ADDR 0x00080014 /* SI CSR 1 */
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#define SI_CSR1_SF 0x00000001 /* Semaphore flag */
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#define SI_CSR1_ICM 0x00000002 /* Indexed color mode */
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#define SI_CSR1_RESET 0x00000004 /* Hold SI in reset state */
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#define SI_CSR1_HELD 0x00000008 /* SI Held by PBM */
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#define SI_CSR1_AD 0x00000020 /* Accepting data */
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#define SI_CSR1_ISE 0x00000040 /* Input sequence error */
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/* Ignore other fields here */
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#define SI_CSR1_XMSIP_AF 0x10000000 /* X MSIP almost full */
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#define SI_CSR1_ZMSIP_AF 0x20000000 /* Z MSIP almost full */
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#define SI_CSR1_ISE_INT_ENA 0x40000000 /* Enable interrupt for ISE */
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#define SI_CSR2_ADDR 0x00080018 /* SI CSR 2 */
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#define SI_CSR2_EF 0x0000001F /* Endpoint Filter (diag) */
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#define SI_CSR2_LWF 0x000007E0 /* Line Width Filter (diag) */
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#define SI_CSR2_F_ENA 0x80000000 /* Enable normal filtering */
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/* Pixel Bus Mux addresses */
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#define PBM_FEFBAS_ADDR 0x0008001c /* FE FB address space */
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#define PBM_FECSR_ADDR 0x00080020 /* FE PBM CSR */
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#define HKPBM_FECS_AFBSS 0x00000001 /* FE state set 1 */
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#define HKAS_IMAGE_DEPTH 0x00000007 /* Pixel image/depth */
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#define HKAS_DEPTH 0x00000005 /* Pixel depth */
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#define HKAS_IMAGE 0x00000004 /* Pixel image */
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/* See hk_fb_regs.h HKPBM_FECS for these bit definitions */
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#define PBM_HFBAS_ADDR 0x00090000 /* Host FB address space */
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#define PBM_HCSR_ADDR 0x00090004 /* Host PBM CSR */
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/* Global types */
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typedef struct fbinit_type fbinit_type;
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struct fbinit_type {
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unsigned offset; /* MS+/Sbus offset of a reg */
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unsigned ppdata; /* data sent to PP */
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};
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#define MS_OFFSET_MASK 0x00ffffff
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#define HKPBM_HCS_HSRP 0x00000010 /* Host stalling RP */
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#define HKPBM_FECS_SILE 0x00000080 /* SI loopback enable */
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/*
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* GT addressability
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*/
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struct gt_ctrl {
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int flags;
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int fd; /* file descriptor for GT */
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u_char *baseaddr; /* base addr of dev */
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rp_host *rp_host_regs; /* ptr to RP host ctrl regs */
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fbi_reg *fbi_regs; /* ptr to FBI ctrl regs */
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fbi_pfgo *fbi_pfgo_regs; /* ptr to PF ctrl regs */
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fe_ctrl_sp *fe_ctrl_regs; /* ptr to FE ctrl regs */
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fe_i860_sp *fe_i860_ctrl_regs; /* ptr to i860 ctrl regs */
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fbo_screen_ctrl *fbo_screen_ctrl_regs; /* ptr to FBO ctrl regs */
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};
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