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https://github.com/DoctorWkt/unix-jun72.git
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523 lines
17 KiB
C
523 lines
17 KiB
C
/* pdp11_dl.c: PDP-11 multiple terminal interface simulator
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Copyright (c) 1993-2006, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior wridcen authorization from Robert M Supnik.
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dcix,dcox DL11 terminal input/output
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*/
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#if defined (VM_PDP10) /* PDP10 version */
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#error "DC11 is not supported on the PDP-10!"
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#elif defined (VM_VAX) /* VAX version */
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#error "DC11 is not supported on the VAX!"
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#else /* PDP-11 version */
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#include "pdp11_defs.h"
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#endif
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#include "sim_sock.h"
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#include "sim_tmxr.h"
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#define DCX_MASK (DCX_LINES - 1)
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#define DCIXCSR_IMP (CSR_DONE + CSR_IE) /* terminal input */
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#define DCIXCSR_RW (CSR_IE)
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#define DCIXCSR_CD 004 /* carrier detect */
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#define DCIXBUF_ERR 0100000
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#define DCIXBUF_OVR 0040000
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#define DCIXBUF_RBRK 0020000
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#define DCOXCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */
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#define DCOXCSR_RW (CSR_IE)
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extern int32 int_req[IPL_HLVL];
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extern int32 tmxr_poll;
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uint16 dcix_csr[DCX_LINES] = { 0 }; /* control/status */
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uint16 dcix_buf[DCX_LINES] = { 0 };
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uint32 dcix_ireq = 0;
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uint16 dcox_csr[DCX_LINES] = { 0 }; /* control/status */
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uint8 dcox_buf[DCX_LINES] = { 0 };
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uint32 dcox_ireq = 0;
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TMLN dcx_ldsc[DCX_LINES] = { 0 }; /* line descriptors */
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TMXR dcx_desc = { DCX_LINES, 0, 0, dcx_ldsc }; /* mux descriptor */
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t_stat dcx_rd (int32 *data, int32 PA, int32 access);
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t_stat dcx_wr (int32 data, int32 PA, int32 access);
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t_stat dcx_reset (DEVICE *dptr);
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t_stat dcix_svc (UNIT *uptr);
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t_stat dcox_svc (UNIT *uptr);
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t_stat dcx_adcach (UNIT *uptr, char *cptr);
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t_stat dcx_detach (UNIT *uptr);
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t_stat dcx_summ (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dcx_show (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dcx_show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dcx_set_lines (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat dcx_show_lines (FILE *st, UNIT *uptr, int32 val, void *desc);
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void dcx_enbdis (int32 dis);
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void dcix_clr_int (uint32 ln);
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void dcix_set_int (int32 ln);
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int32 dcix_iack (void);
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void dcox_clr_int (int32 ln);
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void dcox_set_int (int32 ln);
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int32 dcox_iack (void);
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void dcx_reset_ln (uint32 ln);
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/* DCIX data structures
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dcix_dev DCIX device descriptor
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dcix_unit DCIX unit descriptor
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dcix_reg DCIX register list
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*/
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DIB dcix_dib = {
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IOBA_DCIX, IOLN_DCIX, &dcx_rd, &dcx_wr,
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2, IVCL (DCIX), VEC_DCIX, { &dcix_iack, &dcox_iack }
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};
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UNIT dcix_unit = { UDATA (&dcix_svc, 0, 0), KBD_POLL_WAIT };
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REG dcix_reg[] = {
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{ BRDATA (BUF, dcix_buf, DEV_RDX, 16, DCX_LINES) },
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{ BRDATA (CSR, dcix_csr, DEV_RDX, 16, DCX_LINES) },
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{ GRDATA (IREQ, dcix_ireq, DEV_RDX, DCX_LINES, 0) },
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{ DRDATA (LINES, dcx_desc.lines, 6), REG_HRO },
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{ GRDATA (DEVADDR, dcix_dib.ba, DEV_RDX, 32, 0), REG_HRO },
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{ GRDATA (DEVVEC, dcix_dib.vec, DEV_RDX, 16, 0), REG_HRO },
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{ NULL }
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};
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MTAB dcix_mod[] = {
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{ UNIT_ATT, UNIT_ATT, "summary", NULL, NULL, &dcx_summ },
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{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
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&tmxr_dscln, NULL, &dcx_desc },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
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NULL, &dcx_show, NULL },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
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NULL, &dcx_show, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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&set_addr, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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&set_vec, &dcx_show_vec, NULL },
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{ MTAB_XTD | MTAB_VDV, 0, "lines", "LINES",
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&dcx_set_lines, &dcx_show_lines },
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{ 0 }
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};
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DEVICE dcix_dev = {
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"DCIX", &dcix_unit, dcix_reg, dcix_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &dcx_reset,
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NULL, &dcx_adcach, &dcx_detach,
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&dcix_dib, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS
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};
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/* DCOX data structures
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dcox_dev DCOX device descriptor
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dcox_unit DCOX unit descriptor
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dcox_reg DCOX register list
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*/
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UNIT dcox_unit[] = {
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dcox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT }
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};
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REG dcox_reg[] = {
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{ BRDATA (BUF, dcox_buf, DEV_RDX, 8, DCX_LINES) },
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{ BRDATA (CSR, dcox_csr, DEV_RDX, 16, DCX_LINES) },
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{ GRDATA (IREQ, dcox_ireq, DEV_RDX, DCX_LINES, 0) },
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{ URDATA (TIME, dcox_unit[0].wait, 10, 31, 0,
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DCX_LINES, PV_LEFT) },
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{ NULL }
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};
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MTAB dcox_mod[] = {
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{ TT_MODE, TT_MODE_UC, "UC", "UC", NULL },
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
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{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
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{ MTAB_XTD|MTAB_VUN, 0, NULL, "DISCONNECT",
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&tmxr_dscln, NULL, &dcx_desc },
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{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",
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&tmxr_set_log, &tmxr_show_log, &dcx_desc },
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{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",
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&tmxr_set_nolog, NULL, &dcx_desc },
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{ 0 }
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};
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DEVICE dcox_dev = {
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"DCOX", dcox_unit, dcox_reg, dcox_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &dcx_reset,
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NULL, NULL, NULL,
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NULL, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS
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};
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/* Terminal input routines */
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t_stat dcx_rd (int32 *data, int32 PA, int32 access)
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{
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uint32 ln = ((PA - dcix_dib.ba) >> 3) & DCX_MASK;
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switch ((PA >> 1) & 03) { /* decode PA<2:1> */
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case 00: /* dci csr */
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*data = (dcix_csr[ln] & DCIXCSR_IMP) | DCIXCSR_CD;
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return SCPE_OK;
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case 01: /* dci buf */
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dcix_csr[ln] &= ~CSR_DONE;
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dcix_clr_int (ln);
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*data = dcix_buf[ln];
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return SCPE_OK;
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case 02: /* dco csr */
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*data = dcox_csr[ln] & DCOXCSR_IMP;
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return SCPE_OK;
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case 03: /* dco buf */
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*data = dcox_buf[ln];
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return SCPE_OK;
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} /* end switch PA */
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return SCPE_NXM;
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}
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t_stat dcx_wr (int32 data, int32 PA, int32 access)
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{
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uint32 ln = ((PA - dcix_dib.ba) >> 3) & DCX_MASK;
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switch ((PA >> 1) & 03) { /* decode PA<2:1> */
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case 00: /* dci csr */
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if (PA & 1) return SCPE_OK;
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if ((data & CSR_IE) == 0)
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dcix_clr_int (ln);
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else if ((dcix_csr[ln] & (CSR_DONE + CSR_IE)) == CSR_DONE)
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dcix_set_int (ln);
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dcix_csr[ln] = (uint16) ((dcix_csr[ln] & ~DCIXCSR_RW) | (data & DCIXCSR_RW));
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return SCPE_OK;
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case 01: /* dci buf */
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return SCPE_OK;
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case 02: /* dco csr */
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if (PA & 1) return SCPE_OK;
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if ((data & CSR_IE) == 0)
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dcox_clr_int (ln);
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else if ((dcox_csr[ln] & (CSR_DONE + CSR_IE)) == CSR_DONE)
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dcox_set_int (ln);
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dcox_csr[ln] = (uint16) ((dcox_csr[ln] & ~DCOXCSR_RW) | (data & DCOXCSR_RW));
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return SCPE_OK;
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case 03: /* dco buf */
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if ((PA & 1) == 0)
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dcox_buf[ln] = data & 0377;
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dcox_csr[ln] &= ~CSR_DONE;
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dcox_clr_int (ln);
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sim_activate (&dcox_unit[ln], dcox_unit[ln].wait);
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return SCPE_OK;
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} /* end switch PA */
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return SCPE_NXM;
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}
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/* Terminal input service */
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t_stat dcix_svc (UNIT *uptr)
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{
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int32 ln, c, temp;
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if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK; /* adcached? */
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sim_activate (uptr, tmxr_poll); /* continue poll */
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ln = tmxr_poll_conn (&dcx_desc); /* look for connect */
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if (ln >= 0) dcx_ldsc[ln].rcve = 1; /* got one? rcv enb */
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tmxr_poll_rx (&dcx_desc); /* poll for input */
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for (ln = 0; ln < DCX_LINES; ln++) { /* loop thru lines */
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if (dcx_ldsc[ln].conn) { /* connected? */
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if (temp = tmxr_getc_ln (&dcx_ldsc[ln])) { /* get char */
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if (temp & SCPE_BREAK) /* break? */
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c = DCIXBUF_ERR|DCIXBUF_RBRK;
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else c = sim_tt_inpcvt (temp, TT_GET_MODE (dcox_unit[ln].flags));
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if (dcix_csr[ln] & CSR_DONE)
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c |= DCIXBUF_ERR|DCIXBUF_OVR;
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else {
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dcix_csr[ln] |= CSR_DONE;
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if (dcix_csr[ln] & CSR_IE) dcix_set_int (ln);
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}
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dcix_buf[ln] = c;
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}
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}
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}
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return SCPE_OK;
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}
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/* Terminal output service */
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t_stat dcox_svc (UNIT *uptr)
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{
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int32 c;
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uint32 ln = uptr - dcox_unit; /* line # */
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if (dcx_ldsc[ln].conn) { /* connected? */
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if (dcx_ldsc[ln].xmte) { /* tx enabled? */
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TMLN *lp = &dcx_ldsc[ln]; /* get line */
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c = sim_tt_outcvt (dcox_buf[ln], TT_GET_MODE (dcox_unit[ln].flags));
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if (c >= 0) tmxr_putc_ln (lp, c); /* output char */
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tmxr_poll_tx (&dcx_desc); /* poll xmt */
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}
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else {
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tmxr_poll_tx (&dcx_desc); /* poll xmt */
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sim_activate (uptr, dcox_unit[ln].wait); /* wait */
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return SCPE_OK;
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}
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}
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dcox_csr[ln] |= CSR_DONE; /* set done */
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if (dcox_csr[ln] & CSR_IE) dcox_set_int (ln);
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return SCPE_OK;
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}
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/* Interrupt routines */
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void dcix_clr_int (uint32 ln)
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{
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dcix_ireq &= ~(1 << ln); /* clr mux rcv int */
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if (dcix_ireq == 0) CLR_INT (DCIX); /* all clr? */
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else SET_INT (DCIX); /* no, set intr */
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return;
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}
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void dcix_set_int (int32 ln)
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{
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dcix_ireq |= (1 << ln); /* clr mux rcv int */
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SET_INT (DCIX); /* set master intr */
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return;
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}
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int32 dcix_iack (void)
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{
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int32 ln;
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for (ln = 0; ln < DCX_LINES; ln++) { /* find 1st line */
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if (dcix_ireq & (1 << ln)) {
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dcix_clr_int (ln); /* clear intr */
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return (dcix_dib.vec + (ln * 010)); /* return vector */
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}
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}
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return 0;
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}
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void dcox_clr_int (int32 ln)
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{
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dcox_ireq &= ~(1 << ln); /* clr mux rcv int */
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if (dcox_ireq == 0) CLR_INT (DCOX); /* all clr? */
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else SET_INT (DCOX); /* no, set intr */
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return;
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}
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void dcox_set_int (int32 ln)
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{
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dcox_ireq |= (1 << ln); /* clr mux rcv int */
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SET_INT (DCOX); /* set master intr */
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return;
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}
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int32 dcox_iack (void)
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{
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int32 ln;
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for (ln = 0; ln < DCX_LINES; ln++) { /* find 1st line */
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if (dcox_ireq & (1 << ln)) {
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dcox_clr_int (ln); /* clear intr */
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return (dcix_dib.vec + (ln * 010) + 4); /* return vector */
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}
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}
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return 0;
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}
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/* Reset */
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t_stat dcx_reset (DEVICE *dptr)
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{
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int32 ln;
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dcx_enbdis (dptr->flags & DEV_DIS); /* sync enables */
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sim_cancel (&dcix_unit); /* assume stop */
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if (dcix_unit.flags & UNIT_ATT) /* if adcached, */
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sim_activate (&dcix_unit, tmxr_poll); /* activate */
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for (ln = 0; ln < DCX_LINES; ln++) /* for all lines */
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dcx_reset_ln (ln);
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return auto_config (dcix_dev.name, dcx_desc.lines); /* auto config */
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}
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/* Reset individual line */
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void dcx_reset_ln (uint32 ln)
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{
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dcix_buf[ln] = 0; /* clear buf, */
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dcix_csr[ln] = CSR_DONE;
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dcox_buf[ln] = 0; /* clear buf */
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dcox_csr[ln] = CSR_DONE;
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sim_cancel (&dcox_unit[ln]); /* deactivate */
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dcix_clr_int (ln);
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dcox_clr_int (ln);
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return;
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}
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/* Adcach master unit */
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t_stat dcx_adcach (UNIT *uptr, char *cptr)
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{
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t_stat r;
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r = tmxr_attach (&dcx_desc, uptr, cptr); /* adcach */
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if (r != SCPE_OK) return r; /* error */
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sim_activate (uptr, tmxr_poll); /* start poll */
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return SCPE_OK;
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}
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/* Detach master unit */
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t_stat dcx_detach (UNIT *uptr)
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{
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int32 i;
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t_stat r;
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r = tmxr_detach (&dcx_desc, uptr); /* detach */
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for (i = 0; i < DCX_LINES; i++) /* all lines, */
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dcx_ldsc[i].rcve = 0; /* disable rcv */
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sim_cancel (uptr); /* stop poll */
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return r;
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}
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/* Show summary processor */
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t_stat dcx_summ (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
int32 i, t;
|
|
|
|
for (i = t = 0; i < DCX_LINES; i++) t = t + (dcx_ldsc[i].conn != 0);
|
|
if (t == 1) fprintf (st, "1 connection");
|
|
else fprintf (st, "%d connections", t);
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* SHOW CONN/STAT processor */
|
|
|
|
t_stat dcx_show (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
int32 i, t;
|
|
|
|
for (i = t = 0; i < DCX_LINES; i++) t = t + (dcx_ldsc[i].conn != 0);
|
|
if (t) {
|
|
for (i = 0; i < DCX_LINES; i++) {
|
|
if (dcx_ldsc[i].conn) {
|
|
if (val) tmxr_fconns (st, &dcx_ldsc[i], i);
|
|
else tmxr_fstats (st, &dcx_ldsc[i], i);
|
|
}
|
|
}
|
|
}
|
|
else fprintf (st, "all disconnected\n");
|
|
return SCPE_OK;
|
|
}
|
|
|
|
/* Enable/disable device */
|
|
|
|
void dcx_enbdis (int32 dis)
|
|
{
|
|
if (dis) {
|
|
dcix_dev.flags = dcox_dev.flags | DEV_DIS;
|
|
dcox_dev.flags = dcox_dev.flags | DEV_DIS;
|
|
}
|
|
else {
|
|
dcix_dev.flags = dcix_dev.flags & ~DEV_DIS;
|
|
dcox_dev.flags = dcox_dev.flags & ~DEV_DIS;
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* SHOW VECTOR processor */
|
|
|
|
t_stat dcx_show_vec (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
return show_vec (st, uptr, dcx_desc.lines * 2, desc);
|
|
}
|
|
|
|
/* Change number of lines */
|
|
|
|
t_stat dcx_set_lines (UNIT *uptr, int32 val, char *cptr, void *desc)
|
|
{
|
|
int32 newln, i, t;
|
|
t_stat r;
|
|
|
|
if (cptr == NULL) return SCPE_ARG;
|
|
newln = get_uint (cptr, 10, DCX_LINES, &r);
|
|
if ((r != SCPE_OK) || (newln == dcx_desc.lines)) return r;
|
|
if (newln == 0) return SCPE_ARG;
|
|
if (newln < dcx_desc.lines) {
|
|
for (i = newln, t = 0; i < dcx_desc.lines; i++) t = t | dcx_ldsc[i].conn;
|
|
if (t && !get_yn ("This will disconnect users; proceed [N]?", FALSE))
|
|
return SCPE_OK;
|
|
for (i = newln; i < dcx_desc.lines; i++) {
|
|
if (dcx_ldsc[i].conn) {
|
|
tmxr_linemsg (&dcx_ldsc[i], "\r\nOperator disconnected line\r\n");
|
|
tmxr_reset_ln (&dcx_ldsc[i]); /* reset line */
|
|
}
|
|
dcox_unit[i].flags |= UNIT_DIS;
|
|
dcx_reset_ln (i);
|
|
}
|
|
}
|
|
else {
|
|
for (i = dcx_desc.lines; i < newln; i++) {
|
|
dcox_unit[i].flags &= ~UNIT_DIS;
|
|
dcx_reset_ln (i);
|
|
}
|
|
}
|
|
dcx_desc.lines = newln;
|
|
return auto_config (dcix_dev.name, newln); /* auto config */
|
|
}
|
|
|
|
/* Show number of lines */
|
|
|
|
t_stat dcx_show_lines (FILE *st, UNIT *uptr, int32 val, void *desc)
|
|
{
|
|
fprintf (st, "lines=%d", dcx_desc.lines);
|
|
return SCPE_OK;
|
|
}
|