From 0090d10e11d9d0282e9fafe85b7179328dedc293 Mon Sep 17 00:00:00 2001 From: Marcel Date: Mon, 23 Nov 2020 17:37:43 +0100 Subject: [PATCH] Reduce SDRAM Clock --- .../Konami TimePilot84/TimePilot84.qsf | 4 +- .../Konami TimePilot84/rtl/TimePilot84_CPU.sv | 9 ++--- .../rtl/TimePilot84_MiST.sv | 7 ++-- Arcade_MiST/Konami TimePilot84/rtl/pll.v | 40 +++---------------- 4 files changed, 14 insertions(+), 46 deletions(-) diff --git a/Arcade_MiST/Konami TimePilot84/TimePilot84.qsf b/Arcade_MiST/Konami TimePilot84/TimePilot84.qsf index bfd4f94a..a52b2117 100644 --- a/Arcade_MiST/Konami TimePilot84/TimePilot84.qsf +++ b/Arcade_MiST/Konami TimePilot84/TimePilot84.qsf @@ -246,10 +246,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(TimePilot84_MiST) -# ---------------------------- \ No newline at end of file +# ---------------------------- +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Konami TimePilot84/rtl/TimePilot84_CPU.sv b/Arcade_MiST/Konami TimePilot84/rtl/TimePilot84_CPU.sv index 78a578e9..e49b8fa3 100644 --- a/Arcade_MiST/Konami TimePilot84/rtl/TimePilot84_CPU.sv +++ b/Arcade_MiST/Konami TimePilot84/rtl/TimePilot84_CPU.sv @@ -43,10 +43,7 @@ module TimePilot84_CPU( output [12:0] sub_cpu_rom_addr, input [7:0] sub_cpu_rom_do, output [12:0] sp_rom_addr, - input [31:0] sp_rom_do -// input [24:0] ioctl_addr, -// input [7:0] ioctl_data, -// input ioctl_wr + input [31:0] sp_rom_do ); //Assign active high HBlank and VBlank outputs @@ -1357,7 +1354,7 @@ assign sub_cpu_rom_addr = sA[12:0]; //The PCB connects these signals directly to the chip enable signals on the EPROMs at 2J (character) and 12A/13A (sprite) and //invert them through one inverter at 6F (character) and 13F (sprite) for the second set of character ROMs (3J) and sprite //ROMs (14A/15A). -wire [7:0] charrom_D = ~n_charrom0_ce ? eprom7_D : eprom8_D; +wire [7:0] charrom_D = ~n_charrom0_ce ? eprom7_D : eprom8_D; wire [12:0] charrom_A; wire [7:0] eprom7_D; wire [7:0] eprom8_D; @@ -1376,7 +1373,7 @@ char_rom2 u1J( //Sprite ROM //wire [15:0] spriterom_D = ~n_spriterom0_en ? {eprom11_D, eprom9_D} : {eprom12_D, eprom10_D}; assign sp_rom_addr = spriterom_A; -wire [15:0] spriterom_D = ~n_spriterom0_en ? sp_rom_do[15:0] : sp_rom_do[31:16]; +wire [15:0] spriterom_D = ~n_spriterom0_en ? sp_rom_do[15:0] : sp_rom_do[31:16]; //Sprite ROM 1/4 wire [12:0] spriterom_A; diff --git a/Arcade_MiST/Konami TimePilot84/rtl/TimePilot84_MiST.sv b/Arcade_MiST/Konami TimePilot84/rtl/TimePilot84_MiST.sv index 75e2652c..ed25bc0e 100644 --- a/Arcade_MiST/Konami TimePilot84/rtl/TimePilot84_MiST.sv +++ b/Arcade_MiST/Konami TimePilot84/rtl/TimePilot84_MiST.sv @@ -49,16 +49,15 @@ wire service = status[7]; wire [1:0] orientation = 2'b11; assign LED = ~ioctl_downl; -assign SDRAM_CLK = clock_sd; +assign SDRAM_CLK = clock_48; assign SDRAM_CKE = 1; assign AUDIO_R = AUDIO_L; -wire clock_48, clock_14, clock_sd, pll_locked; +wire clock_48, clock_14, pll_locked; pll pll( .inclk0(CLOCK_27), .c0(clock_48),//49.152MHz .c1(clock_14),//14.31818MHz - .c2(clock_sd), .locked(pll_locked) ); @@ -109,7 +108,7 @@ reg port1_req, port2_req; sdram sdram( .*, .init_n ( pll_locked ), - .clk ( clock_sd ), + .clk ( clock_48 ), .port1_req ( port1_req ), .port1_ack ( ), diff --git a/Arcade_MiST/Konami TimePilot84/rtl/pll.v b/Arcade_MiST/Konami TimePilot84/rtl/pll.v index 270cca93..900c0e3a 100644 --- a/Arcade_MiST/Konami TimePilot84/rtl/pll.v +++ b/Arcade_MiST/Konami TimePilot84/rtl/pll.v @@ -41,14 +41,12 @@ module pll ( inclk0, c0, c1, - c2, locked); input areset; input inclk0; output c0; output c1; - output c2; output locked; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off @@ -60,20 +58,18 @@ module pll ( wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire7 = 1'h0; - wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire6 = 1'h0; wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; wire locked = sub_wire2; wire c0 = sub_wire3; - wire c2 = sub_wire4; - wire sub_wire5 = inclk0; - wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; altpll altpll_component ( .areset (areset), - .inclk (sub_wire6), + .inclk (sub_wire5), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -119,10 +115,6 @@ module pll ( altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 191, altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 70, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 191, - altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -157,7 +149,7 @@ module pll ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -198,13 +190,10 @@ endmodule // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "105" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "360" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "70" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "49.114285" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.325000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "73.671425" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -226,33 +215,25 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "191" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "191" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "49.15200000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31818000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "73.72800000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -276,16 +257,13 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -298,10 +276,6 @@ endmodule // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "191" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "70" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "191" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -335,7 +309,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -355,7 +329,6 @@ endmodule // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 @@ -363,7 +336,6 @@ endmodule // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE