From 00d76447ca8a4ac2afbc0ebf33dca8aaa7a93862 Mon Sep 17 00:00:00 2001
From: Gyorgy Szombathelyi <gyurco@freemail.hu>
Date: Mon, 27 Jan 2020 19:06:27 +0100
Subject: [PATCH] Crazy Climber HW: use common T80 and inputs, CPU clock
 enable, and some random tweaks

---
 .../CannonBall_MiST/CannonBall.qsf            |   41 +-
 .../CannonBall_MiST/CannonBall.sdc            |  134 ++
 .../CannonBall_MiST/CannonBall.srf            |    9 -
 .../CannonBall_MiST/rtl/T80/T80.vhd           | 1073 ---------
 .../CannonBall_MiST/rtl/T80/T80_ALU.vhd       |  351 ---
 .../CannonBall_MiST/rtl/T80/T80_MCode.vhd     | 1934 -----------------
 .../CannonBall_MiST/rtl/T80/T80_Pack.vhd      |  208 --
 .../CannonBall_MiST/rtl/T80/T80_Reg.vhd       |  105 -
 .../CannonBall_MiST/rtl/T80/T80s.vhd          |  190 --
 .../CannonBall_MiST/rtl/cball_mist.sv         |  101 +-
 .../CannonBall_MiST/rtl/ckong.vhd             |    3 +-
 .../{ => rom}/ckong_big_sprite_palette.vhd    |    0
 .../{ => rom}/ckong_big_sprite_tile_bit0.vhd  |    0
 .../{ => rom}/ckong_big_sprite_tile_bit1.vhd  |    0
 .../rtl/{ => rom}/ckong_palette.vhd           |    0
 .../rtl/{ => rom}/ckong_program.vhd           |    0
 .../rtl/{ => rom}/ckong_programP.vhd          |    0
 .../rtl/{ => rom}/ckong_samples.vhd           |    0
 .../rtl/{ => rom}/ckong_sound.vhd             |    0
 .../rtl/{ => rom}/ckong_tile_bit0.vhd         |    0
 .../rtl/{ => rom}/ckong_tile_bit1.vhd         |    0
 .../CannonBall_MiST/rtl/rom/rom/cannonb2.zip  |  Bin 21993 -> 0 bytes
 .../rtl/rom/rom/ckong_big_sprite_palette.vhd  |   24 -
 .../rom/rom/ckong_big_sprite_tile_bit0.vhd    |  150 --
 .../rom/rom/ckong_big_sprite_tile_bit1.vhd    |  150 --
 .../rtl/rom/rom/ckong_palette.vhd             |   26 -
 .../rtl/rom/rom/ckong_program.vhd             | 1046 ---------
 .../rtl/rom/rom/make_cannonballb2_proms.bat   |   27 -
 .../rtl/rom/rom/make_vhdl_prom.exe            |  Bin 119861 -> 0 bytes
 .../rtl/rom/romb3/cannonb3.zip                |  Bin 22187 -> 0 bytes
 .../rtl/rom/romb3/make_cannonballb3_proms.bat |   27 -
 .../rtl/rom/romb3/make_vhdl_prom.exe          |  Bin 119861 -> 0 bytes
 .../CrazyClimber_MiST/CClimber.qsf            |   32 +-
 .../CrazyClimber_MiST/CClimber.sdc            |  134 ++
 .../CrazyClimber_MiST/rtl/CClimber_mist.sv    |  179 +-
 .../CrazyClimber_MiST/rtl/T80/T80.vhd         | 1073 ---------
 .../CrazyClimber_MiST/rtl/T80/T80_ALU.vhd     |  351 ---
 .../CrazyClimber_MiST/rtl/T80/T80_MCode.vhd   | 1934 -----------------
 .../CrazyClimber_MiST/rtl/T80/T80_Pack.vhd    |  208 --
 .../CrazyClimber_MiST/rtl/T80/T80_Reg.vhd     |  105 -
 .../CrazyClimber_MiST/rtl/T80/T80s.vhd        |  190 --
 .../CrazyClimber_MiST/rtl/crazy_climber.vhd   |   22 +-
 .../rtl/crazy_climber_sound.vhd               |   26 +-
 .../CrazyClimber_MiST/rtl/dac.sv              |   33 -
 .../CrazyClimber_MiST/rtl/hq2x.sv             |  454 ----
 .../CrazyClimber_MiST/rtl/mist_io.sv          |  530 -----
 .../CrazyClimber_MiST/rtl/osd.sv              |  194 --
 .../{ => rom}/cclimber_big_sprite_palette.vhd |    0
 .../cclimber_big_sprite_tile_bit0.vhd         |    0
 .../cclimber_big_sprite_tile_bit1.vhd         |    0
 .../rtl/{ => rom}/cclimber_palette.vhd        |    0
 .../rtl/{ => rom}/cclimber_program.vhd        |    0
 .../rtl/{ => rom}/cclimber_samples.vhd        |    0
 .../rtl/{ => rom}/cclimber_tile_bit0.vhd      |    0
 .../rtl/{ => rom}/cclimber_tile_bit1.vhd      |    0
 .../CrazyClimber_MiST/rtl/scandoubler.sv      |  195 --
 .../CrazyClimber_MiST/rtl/video_gen.vhd       |   16 +-
 .../CrazyClimber_MiST/rtl/video_mixer.sv      |  243 ---
 .../CrazyKong_MiST/CrazyKong.qsf              |   49 +-
 .../CrazyKong_MiST/CrazyKong.sdc              |  134 ++
 .../CrazyKong_MiST/CrazyKong.srf              |    9 -
 .../CrazyKong_MiST/rtl/T80/T80.vhd            | 1073 ---------
 .../CrazyKong_MiST/rtl/T80/T80_ALU.vhd        |  351 ---
 .../CrazyKong_MiST/rtl/T80/T80_MCode.vhd      | 1934 -----------------
 .../CrazyKong_MiST/rtl/T80/T80_Pack.vhd       |  208 --
 .../CrazyKong_MiST/rtl/T80/T80_Reg.vhd        |  105 -
 .../CrazyKong_MiST/rtl/T80/T80s.vhd           |  190 --
 .../CrazyKong_MiST/rtl/ckong.vhd              |   18 +-
 .../CrazyKong_MiST/rtl/ckong_mist.sv          |  105 +-
 .../CrazyKong_MiST/rtl/ckong_samples.vhd      |  534 -----
 .../CrazyKong_MiST/rtl/ckong_sound.vhd        |   26 +-
 .../{ => rom}/ckong_big_sprite_palette.vhd    |    0
 .../{ => rom}/ckong_big_sprite_tile_bit0.vhd  |    0
 .../{ => rom}/ckong_big_sprite_tile_bit1.vhd  |    0
 .../rtl/{ => rom}/ckong_palette.vhd           |    0
 .../rtl/{ => rom}/ckong_program.vhd           |    0
 .../rtl}/rom/ckong_samples.vhd                |    0
 .../rtl/{ => rom}/ckong_tile_bit0.vhd         |    0
 .../rtl/{ => rom}/ckong_tile_bit1.vhd         |    0
 .../CrazyKong_MiST/rtl/video_gen.vhd          |    4 +-
 .../River Patrol_MiST/RiverPatrol.qsf         |    9 +-
 .../River Patrol_MiST/RiverPatrol.sdc         |  134 ++
 .../River Patrol_MiST/rtl/RiverPatrol_mist.sv |   91 +-
 .../River Patrol_MiST/rtl/T80/T80.vhd         | 1073 ---------
 .../River Patrol_MiST/rtl/T80/T80_ALU.vhd     |  351 ---
 .../River Patrol_MiST/rtl/T80/T80_MCode.vhd   | 1934 -----------------
 .../River Patrol_MiST/rtl/T80/T80_Pack.vhd    |  208 --
 .../River Patrol_MiST/rtl/T80/T80_Reg.vhd     |  105 -
 .../River Patrol_MiST/rtl/T80/T80s.vhd        |  190 --
 .../River Patrol_MiST/rtl/crazy_climber.vhd   |   22 +-
 .../rtl/crazy_climber_sound.vhd               |   27 +-
 .../River Patrol_MiST/rtl/video_gen.vhd       |   16 +-
 .../Silver Land_MiST/SilverLand.qsf           |    9 +-
 .../Silver Land_MiST/SilverLand.sdc           |  134 ++
 .../Silver Land_MiST/SilverLand.srf           |    7 -
 .../Silver Land_MiST/rtl/SilverLand_mist.sv   |   93 +-
 .../Silver Land_MiST/rtl/T80/T80.vhd          | 1073 ---------
 .../Silver Land_MiST/rtl/T80/T80_ALU.vhd      |  351 ---
 .../Silver Land_MiST/rtl/T80/T80_MCode.vhd    | 1934 -----------------
 .../Silver Land_MiST/rtl/T80/T80_Pack.vhd     |  208 --
 .../Silver Land_MiST/rtl/T80/T80_Reg.vhd      |  105 -
 .../Silver Land_MiST/rtl/T80/T80s.vhd         |  190 --
 .../Silver Land_MiST/rtl/build_id.tcl         |    2 +-
 .../Silver Land_MiST/rtl/crazy_climber.vhd    |   20 +-
 .../Silver Land_MiST/rtl/video_gen.vhd        |   16 +-
 105 files changed, 1117 insertions(+), 23443 deletions(-)
 create mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.sdc
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.srf
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80s.vhd
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_big_sprite_palette.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_big_sprite_tile_bit0.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_big_sprite_tile_bit1.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_palette.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_program.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_programP.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_samples.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_sound.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_tile_bit0.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/{ => rom}/ckong_tile_bit1.vhd (100%)
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/cannonb2.zip
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_palette.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_tile_bit0.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_tile_bit1.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_palette.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_program.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/make_cannonballb2_proms.bat
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/make_vhdl_prom.exe
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/romb3/cannonb3.zip
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/romb3/make_cannonballb3_proms.bat
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/romb3/make_vhdl_prom.exe
 create mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/CClimber.sdc
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80s.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/dac.sv
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/mist_io.sv
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/osd.sv
 rename Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/{ => rom}/cclimber_big_sprite_palette.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/{ => rom}/cclimber_big_sprite_tile_bit0.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/{ => rom}/cclimber_big_sprite_tile_bit1.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/{ => rom}/cclimber_palette.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/{ => rom}/cclimber_program.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/{ => rom}/cclimber_samples.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/{ => rom}/cclimber_tile_bit0.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/{ => rom}/cclimber_tile_bit1.vhd (100%)
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/scandoubler.sv
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/video_mixer.sv
 create mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.sdc
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.srf
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80s.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_samples.vhd
 rename Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/{ => rom}/ckong_big_sprite_palette.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/{ => rom}/ckong_big_sprite_tile_bit0.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/{ => rom}/ckong_big_sprite_tile_bit1.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/{ => rom}/ckong_palette.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/{ => rom}/ckong_program.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/{CannonBall_MiST/rtl/rom => CrazyKong_MiST/rtl}/rom/ckong_samples.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/{ => rom}/ckong_tile_bit0.vhd (100%)
 rename Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/{ => rom}/ckong_tile_bit1.vhd (100%)
 create mode 100644 Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/RiverPatrol.sdc
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80s.vhd
 create mode 100644 Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.sdc
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.srf
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80s.vhd

diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.qsf b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.qsf
index 63d001fc..ff077b2e 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.qsf	
+++ b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.qsf	
@@ -40,32 +40,10 @@
 # Project-Wide Assignments
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cball_mist.sv
-set_global_assignment -name VHDL_FILE rtl/ckong.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_tile_bit1.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_tile_bit0.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_samples.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_program.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_tile_bit1.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_tile_bit0.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_sound.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
-set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -167,4 +145,21 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/cball_mist.sv
+set_global_assignment -name VHDL_FILE rtl/ckong.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_tile_bit1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_tile_bit0.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_sound.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_samples.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_program.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_palette.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_big_sprite_tile_bit1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_big_sprite_tile_bit0.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_big_sprite_palette.vhd
+set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
+set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.sdc b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.sdc
new file mode 100644
index 00000000..fc76f46c
--- /dev/null
+++ b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.sdc	
@@ -0,0 +1,134 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk   "pll|altpll_component|auto_generated|pll1|clk[0]"
+set vid_clk   "pll|altpll_component|auto_generated|pll1|clk[1]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $vid_clk]  1.000 [get_ports {VGA_*}]
+
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.srf b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.srf
deleted file mode 100644
index 4174c086..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/CannonBall.srf	
+++ /dev/null
@@ -1,9 +0,0 @@
-{ "" "" "" "Inferred dual-clock RAM node \"mist_video:mist_video\|osd:osd\|osd_buffer_rtl_0\" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." {  } {  } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "6 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Design contains 1 input pin(s) that do not drive logic" {  } {  } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "PLL \"pll:pll\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" {  } {  } 0 15899 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "TimeQuest Timing Analyzer is analyzing 2 combinational loops as latches." {  } {  } 0 335093 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "8192 out of 32768 addresses are uninitialized. The Quartus II software will initialize them to \"0\". There are 1 warnings found, and 1 warnings are reported." {  } {  } 0 113028 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Output pins are stuck at VCC or GND" {  } {  } 0 13024 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index 398fa0df..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1073 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed wait and halt
---
---	0211 : Fixed Refresh addition and IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---	0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---	0237 : Changed 8080 I/O address output, added IntE output
---
---	0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---	0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---	0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F			: std_logic_vector(7 downto 0);
-	signal Ap, Fp			: std_logic_vector(7 downto 0);
-	signal I				: std_logic_vector(7 downto 0);
-	signal R				: unsigned(7 downto 0);
-	signal SP, PC			: unsigned(15 downto 0);
-	signal RegDIH			: std_logic_vector(7 downto 0);
-	signal RegDIL			: std_logic_vector(7 downto 0);
-	signal RegBusA			: std_logic_vector(15 downto 0);
-	signal RegBusB			: std_logic_vector(15 downto 0);
-	signal RegBusC			: std_logic_vector(15 downto 0);
-	signal RegAddrA_r		: std_logic_vector(2 downto 0);
-	signal RegAddrA			: std_logic_vector(2 downto 0);
-	signal RegAddrB_r		: std_logic_vector(2 downto 0);
-	signal RegAddrB			: std_logic_vector(2 downto 0);
-	signal RegAddrC			: std_logic_vector(2 downto 0);
-	signal RegWEH			: std_logic;
-	signal RegWEL			: std_logic;
-	signal Alternate		: std_logic;
-
-	-- Help Registers
-	signal TmpAddr			: std_logic_vector(15 downto 0);	-- Temporary address register
-	signal IR				: std_logic_vector(7 downto 0);		-- Instruction register
-	signal ISet				: std_logic_vector(1 downto 0);		-- Instruction set selector
-	signal RegBusA_r		: std_logic_vector(15 downto 0);
-
-	signal ID16				: signed(15 downto 0);
-	signal Save_Mux			: std_logic_vector(7 downto 0);
-
-	signal TState			: unsigned(2 downto 0);
-	signal MCycle			: std_logic_vector(2 downto 0);
-	signal IntE_FF1			: std_logic;
-	signal IntE_FF2			: std_logic;
-	signal Halt_FF			: std_logic;
-	signal BusReq_s			: std_logic;
-	signal BusAck			: std_logic;
-	signal ClkEn			: std_logic;
-	signal NMI_s			: std_logic;
-	signal INT_s			: std_logic;
-	signal IStatus			: std_logic_vector(1 downto 0);
-
-	signal DI_Reg			: std_logic_vector(7 downto 0);
-	signal T_Res			: std_logic;
-	signal XY_State			: std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M		: std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch	: std_logic;
-	signal XY_Ind			: std_logic;
-	signal No_BTR			: std_logic;
-	signal BTR_r			: std_logic;
-	signal Auto_Wait		: std_logic;
-	signal Auto_Wait_t1		: std_logic;
-	signal Auto_Wait_t2		: std_logic;
-	signal IncDecZ			: std_logic;
-
-	-- ALU signals
-	signal BusB				: std_logic_vector(7 downto 0);
-	signal BusA				: std_logic_vector(7 downto 0);
-	signal ALU_Q			: std_logic_vector(7 downto 0);
-	signal F_Out			: std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r	: std_logic_vector(4 downto 0);
-	signal Arith16_r		: std_logic;
-	signal Z16_r			: std_logic;
-	signal ALU_Op_r			: std_logic_vector(3 downto 0);
-	signal Save_ALU_r		: std_logic;
-	signal PreserveC_r		: std_logic;
-	signal MCycles			: std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d		: std_logic_vector(2 downto 0);
-	signal TStates			: std_logic_vector(2 downto 0);
-	signal IntCycle			: std_logic;
-	signal NMICycle			: std_logic;
-	signal Inc_PC			: std_logic;
-	signal Inc_WZ			: std_logic;
-	signal IncDec_16		: std_logic_vector(3 downto 0);
-	signal Prefix			: std_logic_vector(1 downto 0);
-	signal Read_To_Acc		: std_logic;
-	signal Read_To_Reg		: std_logic;
-	signal Set_BusB_To		: std_logic_vector(3 downto 0);
-	signal Set_BusA_To		: std_logic_vector(3 downto 0);
-	signal ALU_Op			: std_logic_vector(3 downto 0);
-	signal Save_ALU			: std_logic;
-	signal PreserveC		: std_logic;
-	signal Arith16			: std_logic;
-	signal Set_Addr_To		: std_logic_vector(2 downto 0);
-	signal Jump				: std_logic;
-	signal JumpE			: std_logic;
-	signal JumpXY			: std_logic;
-	signal Call				: std_logic;
-	signal RstP				: std_logic;
-	signal LDZ				: std_logic;
-	signal LDW				: std_logic;
-	signal LDSPHL			: std_logic;
-	signal IORQ_i			: std_logic;
-	signal Special_LD		: std_logic_vector(2 downto 0);
-	signal ExchangeDH		: std_logic;
-	signal ExchangeRp		: std_logic;
-	signal ExchangeAF		: std_logic;
-	signal ExchangeRS		: std_logic;
-	signal I_DJNZ			: std_logic;
-	signal I_CPL			: std_logic;
-	signal I_CCF			: std_logic;
-	signal I_SCF			: std_logic;
-	signal I_RETN			: std_logic;
-	signal I_BT				: std_logic;
-	signal I_BC				: std_logic;
-	signal I_BTR			: std_logic;
-	signal I_RLD			: std_logic;
-	signal I_RRD			: std_logic;
-	signal I_INRC			: std_logic;
-	signal SetDI			: std_logic;
-	signal SetEI			: std_logic;
-	signal IMode			: std_logic_vector(1 downto 0);
-	signal Halt				: std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR => IR,
-			ISet => ISet,
-			MCycle => MCycle,
-			F => F,
-			NMICycle => NMICycle,
-			IntCycle => IntCycle,
-			MCycles => MCycles_d,
-			TStates => TStates,
-			Prefix => Prefix,
-			Inc_PC => Inc_PC,
-			Inc_WZ => Inc_WZ,
-			IncDec_16 => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op => ALU_Op,
-			Save_ALU => Save_ALU,
-			PreserveC => PreserveC,
-			Arith16 => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ => IORQ_i,
-			Jump => Jump,
-			JumpE => JumpE,
-			JumpXY => JumpXY,
-			Call => Call,
-			RstP => RstP,
-			LDZ => LDZ,
-			LDW => LDW,
-			LDSPHL => LDSPHL,
-			Special_LD => Special_LD,
-			ExchangeDH => ExchangeDH,
-			ExchangeRp => ExchangeRp,
-			ExchangeAF => ExchangeAF,
-			ExchangeRS => ExchangeRS,
-			I_DJNZ => I_DJNZ,
-			I_CPL => I_CPL,
-			I_CCF => I_CCF,
-			I_SCF => I_SCF,
-			I_RETN => I_RETN,
-			I_BT => I_BT,
-			I_BC => I_BC,
-			I_BTR => I_BTR,
-			I_RLD => I_RLD,
-			I_RRD => I_RRD,
-			I_INRC => I_INRC,
-			SetDI => SetDI,
-			SetEI => SetEI,
-			IMode => IMode,
-			Halt => Halt,
-			NoRead => NoRead,
-			Write => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16 => Z16_r,
-			ALU_Op => ALU_Op_r,
-			IR => IR(5 downto 0),
-			ISet => ISet,
-			BusA => BusA,
-			BusB => BusB,
-			F_In => F,
-			Q => ALU_Q,
-			F_Out => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 and Auto_Wait_t1 = '0' then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if T_Res = '1' then
-				Auto_Wait_t1 <= '0';
-			else
-				Auto_Wait_t1 <= Auto_Wait or IORQ_i;
-			end if;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
-						(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 86fddce7..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0238 : Fixed zero flag for 16 bit SBC and ADC
---
---	0240 : Added GB operations
---
---	0242 : Cleanup
---
---	0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A : std_logic_vector;
-					B : std_logic_vector;
-					Sub : std_logic;
-					Carry_In : std_logic;
-					signal Res : out std_logic_vector;
-					signal Carry : out std_logic) is
-		variable B_i		: unsigned(A'length - 1 downto 0);
-		variable Res_i		: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i := unsigned(B);
-		end if;
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal	UseCarry		: std_logic;
-	signal	Carry7_v		: std_logic;
-	signal	Overflow_v		: std_logic;
-	signal	HalfCarry_v		: std_logic;
-	signal	Carry_v			: std_logic;
-	signal	Q_v				: std_logic_vector(7 downto 0);
-
-	signal	BitMask			: std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-									"00000010" when "001",
-									"00000100" when "010",
-									"00001000" when "011",
-									"00010000" when "100",
-									"00100000" when "101",
-									"01000000" when "110",
-									"10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);	-- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 4cc30f35..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1934 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0235 : Added IM 2 fix by Mike Johnson
---
---	0238 : Added NoRead signal
---
---	0238b: Fixed instruction timing for POP and DJNZ
---
---	0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
---	0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
---	constant aNone	: std_logic_vector(2 downto 0) := "000";
---	constant aXY	: std_logic_vector(2 downto 0) := "001";
---	constant aIOA	: std_logic_vector(2 downto 0) := "010";
---	constant aSP	: std_logic_vector(2 downto 0) := "011";
---	constant aBC	: std_logic_vector(2 downto 0) := "100";
---	constant aDE	: std_logic_vector(2 downto 0) := "101";
---	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---	Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To	<= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To	<= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";	-- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n	-- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To	<= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---	CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-					Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others =>
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---	ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)	<= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index ac7d34da..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,208 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80s.vhd
deleted file mode 100644
index 5b612110..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/T80/T80s.vhd	
+++ /dev/null
@@ -1,190 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed read with wait
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0236 : Added T2Write generic
---
---	0237 : Fixed T2Write with wait state
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80s is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
-		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80s;
-
-architecture rtl of T80s is
-
-	signal CEN			: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => IOWait)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_n,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => RESET_n,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK_n,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			if MCycle = "001" then
-				if TState = "001" or (TState = "010" and Wait_n = '0') then
-					RD_n <= not IntCycle_n;
-					MREQ_n <= not IntCycle_n;
-					IORQ_n <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					MREQ_n <= '0';
-				end if;
-			else
-				if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
-					RD_n <= '0';
-					IORQ_n <= not IORQ;
-					MREQ_n <= IORQ;
-				end if;
-				if T2Write = 0 then
-					if TState = "010" and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				end if;
-			end if;
-			if TState = "010" and Wait_n = '1' then
-				DI_Reg <= DI;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/cball_mist.sv b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/cball_mist.sv
index 3aa38252..6de29276 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/cball_mist.sv	
+++ b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/cball_mist.sv	
@@ -22,10 +22,15 @@ localparam CONF_STR = {
 	"CannonBall;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
+	"O5,Blend,Off,On;",
+	"T0,Reset;",
 	"V,v1.21.",`BUILD_DATE
 };
 
+wire       rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire       blend = status[5];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
@@ -40,12 +45,13 @@ pll pll(
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [9:0] kbjoy;
 wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
 wire [15:0] audio;
 wire hs, vs;
 wire blankn;
@@ -54,7 +60,7 @@ wire [1:0] 	b;
 
 ckong ckong(
 	.clock_12(clock_12),
-	.reset(status[0] | status[6] | buttons[1]),
+	.reset(status[0] | buttons[1]),
 	.video_r(r),
 	.video_g(g),
 	.video_b(b),
@@ -62,21 +68,21 @@ ckong ckong(
 	.video_vs(vs),
 	.blankn(blankn),
 	.audio_out(audio),
-	.start2(btn_two_players),//used for select
-	.start1(btn_one_player),
-	.coin1(btn_coin),
-	.fire1(m_fire),
+	.start2(m_two_players),//used for select
+	.start1(m_one_player),
+	.coin1(m_coin1),
+	.fire1(m_fireA),
 	.right1(m_right),
 	.left1(m_left),
 	.down1(m_down),
-	.up1(m_up),
-	.fire2(m_fire),
-	.right2(m_right),
-	.left2(m_left),
-	.down2(m_down),
-	.up2(m_up)
+	.up1(m_up2),
+	.fire2(m_fire2A),
+	.right2(m_right2),
+	.left2(m_left2),
+	.down2(m_down2),
+	.up2(m_up2)
 	);
-	
+
 mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
 	.clk_sys(clock_24),
 	.SPI_SCK(SPI_SCK),
@@ -93,8 +99,9 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
 	.ce_divider(1'b0),
-	.rotate({1'b1,status[2]}),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
+	.rotate({1'b1,rotate}),
+	.blend(blend),
+	.scanlines(scanlines),
 	.scandoubler_disable(scandoublerD),
 	.ypbpr(ypbpr)
 	);
@@ -102,7 +109,7 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clock_24       ),
+	.clk_sys        (clock_12       ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -121,48 +128,32 @@ user_io(
 	);
 
 dac #(
-	.C_bits(15))
+	.C_bits(16))
 dac(
-	.clk_i(clock_24),
+	.clk_i(clock_12),
 	.res_n_i(1),
 	.dac_i({~audio[15],audio[14:0]}),
 	.dac_o(AUDIO_L)
 	);
 
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
-wire       key_pressed;
-wire [7:0] key_code;
-wire       key_strobe;
-
-always @(posedge clock_24) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up         	<= key_pressed; // up
-			'h72: btn_down        	<= key_pressed; // down
-			'h6B: btn_left      	<= key_pressed; // left
-			'h74: btn_right       	<= key_pressed; // right
-			'h76: btn_coin			<= key_pressed; // ESC
-			'h05: btn_one_player   	<= key_pressed; // F1
-			'h06: btn_two_players  	<= key_pressed; // F2
-			'h29: btn_fire1   		<= key_pressed; // Space
-		endcase
-	end
-end
-
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+ 
+arcade_inputs inputs (
+        .clk         ( clock_12    ),
+        .key_strobe  ( key_strobe  ),
+        .key_pressed ( key_pressed ),
+        .key_code    ( key_code    ),
+        .joystick_0  ( joystick_0  ),
+        .joystick_1  ( joystick_1  ),
+        .rotate      ( rotate      ),
+        .orientation ( 2'b11       ),
+        .joyswap     ( 1'b0        ),
+        .oneplayer   ( 1'b1        ),
+        .controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+        .player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+        .player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule 
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong.vhd
index 7784461b..c7a9488f 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong.vhd	
@@ -638,11 +638,12 @@ port map (
 );
 
 -- Z80
-Z80 : entity work.T80s
+Z80 : entity work.T80se
 generic map(Mode => 0, T2Write => 1, IOWait => 1)
 port map(
   RESET_n => reset_n,
   CLK_n   => cpu_clock,
+  CLKEN   => '1',
   WAIT_n  => '1',
   INT_n   => '1',
   NMI_n   => cpu_int_n,
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_big_sprite_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_big_sprite_palette.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_big_sprite_palette.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_big_sprite_palette.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_big_sprite_tile_bit0.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_big_sprite_tile_bit0.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_big_sprite_tile_bit0.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_big_sprite_tile_bit0.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_big_sprite_tile_bit1.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_big_sprite_tile_bit1.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_big_sprite_tile_bit1.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_big_sprite_tile_bit1.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_palette.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_palette.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_palette.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_program.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_program.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_program.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_program.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_programP.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_programP.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_programP.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_programP.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_samples.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_samples.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_samples.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_samples.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_sound.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_sound.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_sound.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_sound.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_tile_bit0.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_tile_bit0.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_tile_bit0.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_tile_bit0.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_tile_bit1.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_tile_bit1.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/ckong_tile_bit1.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/ckong_tile_bit1.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/cannonb2.zip b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/cannonb2.zip
deleted file mode 100644
index 8aab35d077a3c150dc04b13a7edc49476fa40c6d..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_palette.vhd
deleted file mode 100644
index 386fb6aa..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_palette.vhd	
+++ /dev/null
@@ -1,24 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity ckong_big_sprite_palette is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(4 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of ckong_big_sprite_palette is
-	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"00",X"FF",X"18",X"C0",X"00",X"FF",X"C6",X"8F",X"00",X"0F",X"FF",X"1F",X"00",X"FF",X"C0",X"67",
-		X"00",X"47",X"7F",X"88",X"00",X"88",X"47",X"7F",X"00",X"7F",X"88",X"47",X"00",X"40",X"08",X"FF");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_tile_bit0.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_tile_bit0.vhd
deleted file mode 100644
index a2f5fa8c..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_tile_bit0.vhd	
+++ /dev/null
@@ -1,150 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity ckong_big_sprite_tile_bit0 is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(10 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of ckong_big_sprite_tile_bit0 is
-	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"1F",X"3F",X"7F",X"FF",X"FF",X"BF",X"9E",X"C1",X"33",X"39",X"78",X"7E",X"7E",X"7E",X"7E",X"7E",
-		X"E1",X"C6",X"8F",X"CF",X"E6",X"73",X"1F",X"00",X"7E",X"7E",X"7E",X"7E",X"7C",X"3D",X"19",X"03",
-		X"1F",X"3F",X"7F",X"FF",X"FF",X"BF",X"9E",X"C1",X"33",X"39",X"78",X"7E",X"7E",X"7E",X"7E",X"7E",
-		X"E1",X"C6",X"8F",X"CF",X"E6",X"73",X"1F",X"00",X"7E",X"7E",X"7E",X"7E",X"7C",X"3D",X"19",X"03",
-		X"1F",X"3F",X"7F",X"FF",X"FF",X"BF",X"9E",X"C1",X"33",X"39",X"78",X"7E",X"7E",X"7E",X"7E",X"7E",
-		X"E1",X"C6",X"8F",X"CF",X"E6",X"73",X"1F",X"00",X"7E",X"7E",X"7E",X"7E",X"7C",X"3D",X"19",X"03",
-		X"00",X"1E",X"36",X"60",X"C0",X"CC",X"ED",X"F1",X"1F",X"27",X"47",X"43",X"43",X"43",X"43",X"43",
-		X"ED",X"CC",X"C0",X"60",X"36",X"1E",X"0E",X"00",X"43",X"43",X"43",X"43",X"47",X"27",X"1F",X"1F",
-		X"00",X"1E",X"36",X"60",X"C0",X"CC",X"ED",X"F1",X"6F",X"F7",X"F7",X"73",X"7B",X"7B",X"7B",X"73",
-		X"ED",X"CC",X"C0",X"60",X"36",X"1E",X"0E",X"00",X"7B",X"7B",X"7B",X"73",X"F7",X"F7",X"67",X"0F",
-		X"FE",X"47",X"87",X"14",X"85",X"04",X"89",X"F0",X"00",X"00",X"C0",X"C0",X"40",X"C0",X"C0",X"40",
-		X"F0",X"89",X"04",X"85",X"14",X"87",X"47",X"FE",X"C0",X"40",X"C0",X"40",X"C0",X"C0",X"00",X"00",
-		X"00",X"01",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"E0",X"E0",X"E0",X"E0",X"F0",X"F8",X"F8",X"F8",
-		X"0F",X"07",X"07",X"03",X"00",X"00",X"00",X"00",X"F8",X"F4",X"F0",X"F0",X"28",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"01",X"03",X"87",X"FF",X"00",X"01",X"02",X"E4",X"F8",X"FA",X"FC",X"FC",
-		X"FF",X"FF",X"FF",X"FF",X"01",X"00",X"00",X"00",X"FC",X"F8",X"FA",X"FC",X"F8",X"F8",X"30",X"20",
-		X"01",X"0F",X"07",X"0F",X"07",X"23",X"13",X"09",X"C0",X"E0",X"F0",X"F0",X"F8",X"FC",X"FC",X"FE",
-		X"51",X"31",X"11",X"01",X"01",X"03",X"01",X"01",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"1F",
-		X"00",X"00",X"00",X"00",X"00",X"11",X"1F",X"1F",X"00",X"05",X"02",X"07",X"0F",X"FF",X"FF",X"FF",
-		X"1F",X"0F",X"0F",X"07",X"03",X"03",X"01",X"00",X"FF",X"FF",X"FE",X"FE",X"FE",X"FC",X"F8",X"F0",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"3F",X"7F",X"FF",
-		X"01",X"03",X"07",X"07",X"07",X"03",X"01",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"1F",
-		X"00",X"00",X"00",X"00",X"C0",X"F8",X"FE",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"FF",X"FF",X"FF",X"EE",X"FF",X"FC",X"F0",X"00",X"C0",X"C0",X"60",X"B0",X"40",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"00",X"CC",
-		X"00",X"00",X"01",X"01",X"0F",X"1F",X"3F",X"7F",X"F8",X"FE",X"FD",X"FC",X"F9",X"F8",X"F8",X"F8",
-		X"F4",X"F9",X"FD",X"FE",X"FF",X"FF",X"FF",X"FF",X"FC",X"F8",X"FC",X"FC",X"32",X"84",X"C3",X"F0",
-		X"3F",X"0F",X"07",X"01",X"00",X"00",X"00",X"00",X"F8",X"F0",X"F0",X"A0",X"04",X"02",X"00",X"00",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"F8",X"F8",X"F8",X"F0",X"E0",X"E0",X"E0",X"E0",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"E6",X"E2",X"E0",X"E0",X"E0",X"E6",X"FC",X"78",X"F8",X"FC",
-		X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"00",X"01",X"07",X"3F",X"FF",X"FF",X"FF",X"FF",
-		X"07",X"0F",X"0F",X"0F",X"1F",X"1F",X"1F",X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"3C",X"78",X"78",X"FC",X"F7",X"E3",X"E1",X"C0",X"FF",X"FF",X"3F",X"9F",X"CF",X"E3",X"C1",X"80",
-		X"CC",X"4C",X"00",X"04",X"04",X"00",X"00",X"00",X"08",X"10",X"20",X"20",X"20",X"20",X"20",X"00",
-		X"00",X"00",X"01",X"01",X"03",X"03",X"03",X"07",X"60",X"F0",X"F8",X"FC",X"FC",X"FE",X"FC",X"EC",
-		X"07",X"07",X"0F",X"0F",X"0F",X"0F",X"0C",X"08",X"CE",X"CE",X"C0",X"C0",X"E0",X"E0",X"00",X"00",
-		X"FF",X"FF",X"FF",X"7F",X"7F",X"3F",X"0F",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"0B",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"00",X"00",X"00",X"00",X"00",X"0B",X"FF",X"FF",
-		X"07",X"0F",X"3F",X"7F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"00",X"20",X"5C",X"7F",X"FF",X"7F",X"7F",X"1F",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"FF",
-		X"0F",X"07",X"01",X"00",X"00",X"00",X"00",X"00",X"FE",X"FC",X"F0",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"01",X"03",X"03",X"07",X"07",X"07",X"0F",X"F0",X"F8",X"FC",X"FE",X"FE",X"FF",X"FF",X"FF",
-		X"0F",X"07",X"07",X"0B",X"00",X"00",X"00",X"00",X"FF",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",
-		X"FC",X"FC",X"FE",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"18",X"30",X"F6",X"F7",X"F7",X"F3",X"FB",
-		X"FF",X"FF",X"FF",X"7F",X"1F",X"0E",X"00",X"00",X"F9",X"FC",X"E4",X"C2",X"00",X"00",X"00",X"00",
-		X"00",X"1C",X"3E",X"7F",X"FF",X"FF",X"FF",X"FE",X"00",X"00",X"00",X"00",X"90",X"30",X"70",X"F0",
-		X"FE",X"FE",X"FF",X"FF",X"FE",X"FE",X"FE",X"FE",X"F0",X"E0",X"40",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"10",X"08",X"04",X"00",X"00",X"00",X"00",X"80",X"49",X"2A",X"08",X"7E",X"08",X"2A",X"49",
-		X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"00",X"80",X"00",X"02",X"09",X"80",X"08",X"00",X"00",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"00",X"00",X"40",X"61",X"63",X"66",X"6C",X"7A",X"00",X"00",X"81",X"C3",X"E3",X"33",X"1B",X"AF",
-		X"7A",X"6C",X"66",X"63",X"61",X"40",X"00",X"00",X"AF",X"1B",X"33",X"E3",X"C3",X"81",X"00",X"00",
-		X"00",X"00",X"04",X"06",X"06",X"06",X"06",X"07",X"20",X"70",X"71",X"53",X"DB",X"8B",X"8B",X"FF",
-		X"07",X"06",X"06",X"06",X"06",X"04",X"00",X"00",X"FF",X"8B",X"8B",X"DB",X"53",X"71",X"70",X"20",
-		X"00",X"10",X"08",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"78",X"FC",X"CC",
-		X"00",X"21",X"00",X"00",X"04",X"00",X"00",X"00",X"FC",X"FC",X"CC",X"78",X"00",X"00",X"00",X"00",
-		X"08",X"00",X"00",X"00",X"00",X"01",X"23",X"03",X"00",X"00",X"00",X"00",X"78",X"FC",X"FE",X"CE",
-		X"05",X"01",X"02",X"00",X"10",X"02",X"00",X"00",X"FE",X"FE",X"CC",X"FC",X"78",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"01",X"07",X"06",X"03",X"00",X"00",X"3C",X"FE",X"FE",X"FB",X"F7",X"EF",X"AF",
-		X"10",X"0C",X"20",X"10",X"08",X"00",X"00",X"00",X"1F",X"3F",X"3F",X"3F",X"3F",X"7F",X"33",X"61",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",
-		X"C0",X"E0",X"F0",X"F8",X"FC",X"FF",X"FF",X"FF",X"03",X"07",X"0F",X"1F",X"3F",X"FF",X"FF",X"FF",
-		X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"E2",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"F2",X"F8",X"FC",X"F8",X"FA",X"FC",X"F8",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"0F",X"1C",X"38",X"78",X"63",X"E7",X"F3",X"F8",X"CC",X"DE",X"1E",X"3E",X"0E",X"1E",X"1E",X"1E",
-		X"F8",X"F3",X"E7",X"E3",X"78",X"78",X"3C",X"1F",X"5E",X"1E",X"1E",X"3E",X"3E",X"1E",X"1E",X"0C",
-		X"F0",X"F3",X"E0",X"E0",X"E0",X"E4",X"F0",X"7F",X"3F",X"9F",X"8F",X"73",X"18",X"17",X"15",X"F5",
-		X"7C",X"78",X"F0",X"E0",X"E0",X"E0",X"E0",X"F3",X"E3",X"63",X"21",X"31",X"17",X"16",X"A0",X"D9",
-		X"E0",X"C0",X"C0",X"C0",X"C0",X"40",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"80",X"00",X"80",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"61",X"33",X"7F",X"1F",X"0F",X"07",X"03",X"03",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"F7",X"E7",X"CF",X"CF",X"DF",X"DF",X"BE",X"7E",X"A3",X"4F",X"3F",X"FF",X"3F",X"3F",X"3F",X"3F",
-		X"FE",X"FC",X"FC",X"78",X"70",X"00",X"00",X"00",X"3F",X"3F",X"1F",X"04",X"00",X"00",X"00",X"00",
-		X"80",X"C0",X"E0",X"F0",X"F0",X"F0",X"F0",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"E4",X"C0",X"C0",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_tile_bit1.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_tile_bit1.vhd
deleted file mode 100644
index c596ff02..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_big_sprite_tile_bit1.vhd	
+++ /dev/null
@@ -1,150 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity ckong_big_sprite_tile_bit1 is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(10 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of ckong_big_sprite_tile_bit1 is
-	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"00",X"1E",X"3F",X"3F",X"3F",X"7D",X"7F",X"3E",X"CC",X"E6",X"EF",X"C3",X"E7",X"E7",X"E7",X"C3",
-		X"1E",X"3F",X"7D",X"3F",X"1F",X"0C",X"00",X"0F",X"F7",X"F7",X"E7",X"C3",X"E7",X"F6",X"E6",X"FC",
-		X"00",X"1E",X"3F",X"3F",X"3F",X"6F",X"7F",X"3E",X"CC",X"E6",X"EF",X"C3",X"E7",X"E7",X"E7",X"C3",
-		X"1E",X"3F",X"7F",X"3F",X"1B",X"0C",X"00",X"0F",X"F7",X"F7",X"E7",X"C3",X"E7",X"F6",X"E6",X"FC",
-		X"00",X"1E",X"3B",X"3F",X"3F",X"7F",X"7F",X"3E",X"CC",X"E6",X"EF",X"C3",X"E7",X"E7",X"E7",X"C3",
-		X"1E",X"3F",X"77",X"3F",X"1F",X"0C",X"00",X"0F",X"F7",X"F7",X"E7",X"C3",X"E7",X"F6",X"E6",X"FC",
-		X"0F",X"01",X"09",X"1F",X"3F",X"3F",X"1A",X"0E",X"E0",X"D8",X"B8",X"BC",X"BC",X"BC",X"BC",X"BC",
-		X"1A",X"3F",X"3F",X"1F",X"09",X"01",X"01",X"0F",X"BC",X"BC",X"BC",X"BC",X"B8",X"D8",X"E0",X"E0",
-		X"0F",X"01",X"09",X"1F",X"3F",X"3F",X"1A",X"0E",X"D0",X"F8",X"D8",X"8C",X"DC",X"FC",X"DC",X"8C",
-		X"1A",X"3F",X"3F",X"1F",X"09",X"01",X"01",X"0F",X"DC",X"FC",X"DC",X"8C",X"D8",X"F8",X"D8",X"F0",
-		X"38",X"FC",X"FF",X"EF",X"FF",X"FF",X"FF",X"7F",X"00",X"00",X"40",X"80",X"80",X"C0",X"00",X"80",
-		X"7F",X"FF",X"FF",X"FF",X"EF",X"FF",X"FC",X"38",X"C0",X"80",X"C0",X"80",X"80",X"40",X"00",X"00",
-		X"00",X"00",X"09",X"00",X"00",X"08",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"04",
-		X"08",X"04",X"04",X"03",X"00",X"00",X"00",X"00",X"04",X"08",X"0C",X"0C",X"14",X"1C",X"1C",X"0C",
-		X"00",X"00",X"00",X"00",X"01",X"02",X"04",X"08",X"01",X"03",X"07",X"E3",X"07",X"05",X"03",X"03",
-		X"00",X"00",X"48",X"B4",X"00",X"00",X"00",X"00",X"03",X"07",X"05",X"03",X"06",X"00",X"00",X"00",
-		X"00",X"00",X"38",X"3C",X"7C",X"7F",X"FF",X"FC",X"00",X"00",X"00",X"00",X"40",X"80",X"00",X"00",
-		X"FC",X"FC",X"78",X"20",X"00",X"00",X"06",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E0",
-		X"00",X"00",X"00",X"00",X"00",X"EE",X"60",X"00",X"0E",X"1A",X"1D",X"18",X"00",X"10",X"30",X"30",
-		X"10",X"08",X"08",X"04",X"02",X"02",X"01",X"00",X"60",X"40",X"80",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"3C",X"60",X"C0",
-		X"01",X"03",X"06",X"04",X"04",X"01",X"06",X"0E",X"80",X"00",X"00",X"00",X"00",X"01",X"03",X"E0",
-		X"00",X"00",X"00",X"00",X"C0",X"78",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"17",X"E7",X"87",X"06",X"06",X"00",X"40",X"E0",X"70",X"B0",X"F8",X"18",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"FE",X"33",
-		X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"40",X"07",X"81",X"83",X"03",X"03",X"01",X"00",X"00",
-		X"0F",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"07",X"03",X"03",X"05",X"07",X"07",X"03",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"0E",X"5E",X"FF",X"FF",X"CF",X"C6",
-		X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"E0",X"E0",
-		X"01",X"01",X"03",X"03",X"87",X"C7",X"7F",X"3F",X"E0",X"E0",X"C0",X"C1",X"83",X"87",X"07",X"03",
-		X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"04",X"00",X"01",X"07",X"3C",X"C0",X"00",X"00",X"00",
-		X"04",X"08",X"09",X"09",X"08",X"10",X"10",X"10",X"00",X"00",X"FC",X"07",X"01",X"00",X"00",X"00",
-		X"03",X"07",X"07",X"03",X"08",X"1C",X"1E",X"3F",X"00",X"00",X"C0",X"60",X"30",X"1C",X"3E",X"7E",
-		X"3F",X"3B",X"1F",X"03",X"03",X"03",X"01",X"00",X"F6",X"EE",X"DC",X"DC",X"DC",X"D8",X"D0",X"60",
-		X"00",X"00",X"01",X"01",X"02",X"02",X"02",X"04",X"40",X"80",X"00",X"00",X"00",X"42",X"33",X"07",
-		X"04",X"04",X"08",X"08",X"08",X"08",X"08",X"08",X"07",X"07",X"07",X"07",X"00",X"00",X"00",X"00",
-		X"00",X"80",X"C0",X"40",X"61",X"3A",X"0E",X"07",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",
-		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"04",X"0A",X"32",X"41",X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",
-		X"60",X"F0",X"A0",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"60",X"20",X"20",
-		X"00",X"08",X"08",X"04",X"0E",X"08",X"00",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"0C",X"0C",X"06",X"06",X"06",X"04",X"08",X"10",X"00",X"00",X"0C",X"0E",X"0F",X"0F",X"0F",X"07",
-		X"20",X"00",X"80",X"60",X"18",X"0C",X"00",X"00",X"07",X"03",X"03",X"01",X"00",X"00",X"00",X"00",
-		X"00",X"18",X"20",X"40",X"80",X"00",X"00",X"21",X"00",X"00",X"10",X"70",X"70",X"F0",X"F0",X"F0",
-		X"11",X"09",X"04",X"04",X"06",X"06",X"06",X"06",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"00",X"00",X"00",X"01",X"03",X"06",X"0C",X"15",X"00",X"00",X"80",X"40",X"E0",X"30",X"18",X"54",
-		X"15",X"0C",X"06",X"03",X"01",X"00",X"00",X"00",X"54",X"18",X"30",X"E0",X"40",X"80",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"20",X"50",X"70",X"50",X"D8",X"88",X"88",X"04",
-		X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"88",X"88",X"D8",X"50",X"70",X"50",X"20",
-		X"00",X"44",X"02",X"01",X"05",X"43",X"0F",X"16",X"00",X"00",X"00",X"78",X"FE",X"86",X"03",X"73",
-		X"03",X"0E",X"5B",X"21",X"00",X"00",X"00",X"00",X"7B",X"3B",X"33",X"86",X"FE",X"3C",X"00",X"00",
-		X"00",X"00",X"28",X"87",X"33",X"1E",X"0C",X"44",X"00",X"80",X"78",X"FC",X"86",X"03",X"71",X"F9",
-		X"32",X"1E",X"0D",X"03",X"01",X"00",X"00",X"00",X"F9",X"79",X"7B",X"32",X"86",X"FC",X"38",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"19",X"3C",X"7F",X"00",X"00",X"00",X"00",X"04",X"08",X"10",X"50",
-		X"EF",X"F2",X"DC",X"6C",X"30",X"18",X"03",X"07",X"E0",X"00",X"00",X"00",X"00",X"00",X"CC",X"9E",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"04",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"08",X"10",X"20",X"40",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"03",X"05",X"07",X"87",X"05",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"05",X"07",X"03",X"07",X"05",X"03",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"03",X"07",X"07",X"1F",X"1F",X"0C",X"07",X"3A",X"3B",X"FB",X"C1",X"FB",X"FB",X"E1",X"BB",
-		X"07",X"0C",X"1F",X"1F",X"07",X"07",X"03",X"00",X"BB",X"E1",X"FB",X"FB",X"C1",X"FB",X"3B",X"3A",
-		X"0F",X"0C",X"1F",X"1F",X"1F",X"1B",X"0F",X"80",X"C0",X"60",X"70",X"8C",X"E7",X"E8",X"EA",X"0A",
-		X"83",X"87",X"0F",X"1F",X"1F",X"1F",X"1F",X"0C",X"1C",X"1C",X"DE",X"CE",X"E8",X"E9",X"5F",X"26",
-		X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"80",X"00",X"80",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"01",X"07",X"03",X"00",X"00",X"00",X"00",X"00",X"9E",X"CC",X"80",X"20",X"10",X"08",X"04",X"04",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"01",X"00",X"00",X"00",X"00",X"00",
-		X"08",X"18",X"30",X"30",X"20",X"40",X"40",X"80",X"5C",X"B0",X"C0",X"00",X"C0",X"40",X"40",X"40",
-		X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"40",X"40",X"20",X"38",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"08",X"0C",X"0C",X"0C",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"18",X"3C",X"3C",X"2C",X"2C",X"3C",X"1C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
-		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_palette.vhd
deleted file mode 100644
index 3e192c4e..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_palette.vhd	
+++ /dev/null
@@ -1,26 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity ckong_palette is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(5 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of ckong_palette is
-	type rom is array(0 to  63) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"00",X"79",X"04",X"87",X"00",X"B7",X"FF",X"5F",X"00",X"C0",X"E8",X"F4",X"00",X"3F",X"04",X"38",
-		X"00",X"0D",X"7A",X"B7",X"00",X"07",X"26",X"02",X"00",X"27",X"16",X"30",X"00",X"B7",X"F4",X"0C",
-		X"00",X"2F",X"C0",X"16",X"00",X"07",X"27",X"D0",X"00",X"17",X"27",X"E8",X"80",X"07",X"1F",X"FF",
-		X"00",X"E8",X"D8",X"07",X"00",X"3D",X"FF",X"E8",X"00",X"07",X"3F",X"D2",X"00",X"FF",X"D0",X"FF");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_program.vhd b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_program.vhd
deleted file mode 100644
index 6d9de4bb..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_program.vhd	
+++ /dev/null
@@ -1,1046 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity ckong_program is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(13 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of ckong_program is
-	type rom is array(0 to  16383) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AF",X"C3",X"00",X"30",X"FF",X"FF",X"FF",X"FF",X"F1",X"C5",X"D5",X"DD",X"E5",X"FD",X"E5",X"E5",
-		X"E5",X"21",X"44",X"11",X"E3",X"F5",X"C9",X"00",X"E7",X"CA",X"34",X"0F",X"C3",X"3A",X"0F",X"00",
-		X"FD",X"21",X"40",X"0F",X"C3",X"28",X"0F",X"00",X"FD",X"21",X"58",X"0F",X"C3",X"28",X"0F",X"00",
-		X"FD",X"21",X"70",X"0F",X"C3",X"28",X"0F",X"00",X"08",X"D9",X"DD",X"E5",X"FD",X"E5",X"AF",X"32",
-		X"00",X"A0",X"ED",X"57",X"DD",X"21",X"56",X"30",X"87",X"5F",X"16",X"00",X"DD",X"19",X"DD",X"6E",
-		X"00",X"DD",X"66",X"01",X"E9",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"C3",X"38",X"00",X"FF",X"FF",X"FF",X"FF",X"CD",X"73",X"00",
-		X"C3",X"9A",X"01",X"CD",X"4C",X"11",X"3A",X"24",X"60",X"32",X"45",X"50",X"3A",X"25",X"60",X"32",
-		X"4A",X"50",X"3A",X"26",X"60",X"32",X"4F",X"50",X"01",X"10",X"00",X"11",X"50",X"50",X"21",X"14",
-		X"60",X"ED",X"B0",X"21",X"C3",X"60",X"11",X"00",X"6B",X"01",X"0A",X"00",X"C5",X"D5",X"3A",X"5F",
-		X"66",X"B7",X"20",X"04",X"ED",X"B0",X"18",X"14",X"06",X"05",X"7E",X"ED",X"44",X"C6",X"0E",X"12",
-		X"23",X"13",X"7E",X"ED",X"44",X"C6",X"10",X"12",X"23",X"13",X"10",X"EE",X"E1",X"C1",X"CD",X"00",
-		X"31",X"00",X"00",X"2A",X"09",X"60",X"7C",X"B5",X"CA",X"17",X"11",X"2B",X"22",X"09",X"60",X"C3",
-		X"17",X"11",X"CD",X"73",X"00",X"21",X"BF",X"60",X"34",X"7E",X"E6",X"0F",X"F5",X"CC",X"7F",X"03",
-		X"F1",X"FE",X"01",X"20",X"0E",X"11",X"01",X"00",X"DD",X"21",X"B2",X"93",X"FD",X"21",X"FC",X"60",
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-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/make_cannonballb2_proms.bat b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/make_cannonballb2_proms.bat
deleted file mode 100644
index 69c54935..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/make_cannonballb2_proms.bat	
+++ /dev/null
@@ -1,27 +0,0 @@
-
-copy /B cb1.bin + cb2.bin + cb3.bin + cb4.bin prog.bin
-copy /B v6.bin + u6.bin ckong_palette.bin
-
-copy /B cb10part1.bin + emty2k.bin + cb10part2.bin  + emty2k.bin ckong_tile0.bin
-copy /B cb9part1.bin + emty2k.bin + cb9part2.bin  + emty2k.bin ckong_tile1.bin
-
-#copy /B tile0.bin ckong_tile0.bin
-#copy /B tile1.bin ckong_tile1.bin
-copy /B cb6.bin + cb5.bin ckong_samples.bin
-
-make_vhdl_prom prog.bin ckong_program.vhd
-make_vhdl_prom ckong_tile0.bin ckong_tile_bit0.vhd
-make_vhdl_prom ckong_tile1.bin ckong_tile_bit1.vhd
-
-make_vhdl_prom cb7.bin ckong_big_sprite_tile_bit0.vhd
-make_vhdl_prom cb8.bin ckong_big_sprite_tile_bit1.vhd
-
-make_vhdl_prom ckong_palette.bin ckong_palette.vhd
-make_vhdl_prom t6.bin ckong_big_sprite_palette.vhd
-make_vhdl_prom ckong_samples.bin ckong_samples.vhd
-
-
-
-
-
-
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/make_vhdl_prom.exe b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/make_vhdl_prom.exe
deleted file mode 100644
index 1e5618bf9417eaeb90556e3021a78e9860a815e8..0000000000000000000000000000000000000000
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diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/romb3/make_cannonballb3_proms.bat b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/romb3/make_cannonballb3_proms.bat
deleted file mode 100644
index 5e017cdf..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/romb3/make_cannonballb3_proms.bat	
+++ /dev/null
@@ -1,27 +0,0 @@
-
-copy /B 1pose5.bin + 2posf5.bin + 3posh5.bin + 4posk5.bin prog.bin
-copy /B cposv6.bin + bposu6.bin ckong_palette.bin
-
-copy /B bposn11part1.bin + emty2k.bin + bposn11part2.bin  + emty2k.bin ckong_tile0.bin
-copy /B bposk11part1.bin + emty2k.bin + bposk11part2.bin  + emty2k.bin  ckong_tile1.bin
-
-#copy /B tile0.bin ckong_tile0.bin
-#copy /B tile1.bin ckong_tile1.bin
-copy /B ck14poss5.bin + ck13posr5.bin ckong_samples.bin
-
-make_vhdl_prom prog.bin ckong_program.vhd
-make_vhdl_prom ckong_tile0.bin ckong_tile_bit0.vhd
-make_vhdl_prom ckong_tile1.bin ckong_tile_bit1.vhd
-
-make_vhdl_prom ck2posc11.bin ckong_big_sprite_tile_bit0.vhd
-make_vhdl_prom ck1posa11.bin ckong_big_sprite_tile_bit1.vhd
-
-make_vhdl_prom ckong_palette.bin ckong_palette.vhd
-make_vhdl_prom apost6.bin ckong_big_sprite_palette.vhd
-make_vhdl_prom ckong_samples.bin ckong_samples.vhd
-
-
-
-
-
-
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/romb3/make_vhdl_prom.exe b/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/romb3/make_vhdl_prom.exe
deleted file mode 100644
index 1e5618bf9417eaeb90556e3021a78e9860a815e8..0000000000000000000000000000000000000000
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H%=`ZUgl<H8

diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/CClimber.qsf b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/CClimber.qsf
index 3daac05f..1cf77768 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/CClimber.qsf	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/CClimber.qsf	
@@ -40,7 +40,7 @@
 # Project-Wide Assignments
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
@@ -148,28 +148,18 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/CClimber_mist.sv
 set_global_assignment -name VHDL_FILE rtl/crazy_climber.vhd
 set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
-set_global_assignment -name VHDL_FILE rtl/cclimber_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/cclimber_big_sprite_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/cclimber_big_sprite_tile_bit0.vhd
-set_global_assignment -name VHDL_FILE rtl/cclimber_big_sprite_tile_bit1.vhd
-set_global_assignment -name VHDL_FILE rtl/cclimber_program.vhd
-set_global_assignment -name VHDL_FILE rtl/cclimber_samples.vhd
-set_global_assignment -name VHDL_FILE rtl/cclimber_tile_bit0.vhd
-set_global_assignment -name VHDL_FILE rtl/cclimber_tile_bit1.vhd
 set_global_assignment -name VHDL_FILE rtl/crazy_climber_sound.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
 set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
 set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv
 set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
+set_global_assignment -name VHDL_FILE rtl/rom/cclimber_tile_bit1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/cclimber_tile_bit0.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/cclimber_samples.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/cclimber_program.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/cclimber_palette.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/cclimber_big_sprite_tile_bit1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/cclimber_big_sprite_tile_bit0.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/cclimber_big_sprite_palette.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/CClimber.sdc b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/CClimber.sdc
new file mode 100644
index 00000000..fc76f46c
--- /dev/null
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/CClimber.sdc	
@@ -0,0 +1,134 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk   "pll|altpll_component|auto_generated|pll1|clk[0]"
+set vid_clk   "pll|altpll_component|auto_generated|pll1|clk[1]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $vid_clk]  1.000 [get_ports {VGA_*}]
+
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/CClimber_mist.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/CClimber_mist.sv
index 3a872bca..d50fc8c6 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/CClimber_mist.sv	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/CClimber_mist.sv	
@@ -20,20 +20,25 @@ module CClimber_mist (
 
 localparam CONF_STR = {
 	"CClimber;;",
+	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
+	"O5,Blend,Off,On;",
+	"T0,Reset;",
+	"V,v1.21.",`BUILD_DATE
 };
 
+wire       rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire       blend = status[5];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-wire clock_24, clock_12, clock_6;
+wire clock_24, clock_12;
 pll pll(
 	.inclk0(CLOCK_27),
-	.c0(clock_24),//48.784
-	.c1(clock_12),//12.196
-	.c2(clock_6)
+	.c0(clock_24),
+	.c1(clock_12)
 	);
 
 wire [31:0] status;
@@ -43,7 +48,9 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
 wire [15:0] audio;
 wire hs, vs;
 wire hb, vb;
@@ -54,7 +61,7 @@ wire [1:0] b;
 
 crazy_climber crazy_climber (
 	.clock_12(clock_12),
-	.reset(status[0] | status[6] | buttons[1]),
+	.reset(status[0] | buttons[1]),
 	.video_r(r),
 	.video_g(g),
 	.video_b(b),
@@ -63,39 +70,37 @@ crazy_climber crazy_climber (
 	.video_hs(hs),
 	.video_vs(vs),
 	.audio_out(audio),
-	.start2(btn_two_players),
-	.start1(btn_one_player),
-	.coin1(btn_coin),
+	.start2(m_two_players),
+	.start1(m_one_player),
+	.coin1(m_coin1),
 
-	.r_right1(m_right1),//right Arrow
-	.r_left1(m_left1),//left Arrow
-	.r_down1(m_down1),//down Arrow
-	.r_up1(m_up1),//up Arrow
+	.r_right1(m_right),//right Arrow
+	.r_left1(m_left),//left Arrow
+	.r_down1(m_down),//down Arrow
+	.r_up1(m_up),//up Arrow
 	.l_right1(m_right2),//D
 	.l_left1(m_left2),//A
 	.l_down1(m_down2),//S
 	.l_up1(m_up2),////W
   
-	.r_right2(m_right1),//right Arrow
-	.r_left2(m_left1),//left Arrow
-	.r_down2(m_down1),//down Arrow
-	.r_up2(m_up1),//up Arrow
+	.r_right2(m_right),//right Arrow
+	.r_left2(m_left),//left Arrow
+	.r_down2(m_down),//down Arrow
+	.r_up2(m_up),//up Arrow
 	.l_right2(m_right2),//D
 	.l_left2(m_left2),//A
 	.l_down2(m_down2),//S
-	.l_up2(m_up2),////W
+	.l_up2(m_up2)////W
 	);
 
-video_mixer video_mixer(
+mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
 	.clk_sys(clock_24),
-	.ce_pix(clock_6),
-	.ce_pix_actual(clock_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R(blankn ? {r} : "000"),
-	.G(blankn ? {g} : "000"),
-	.B(blankn ? {b,1'b0} : "000"),
+	.R(blankn ? r : 0),
+	.G(blankn ? g : 0),
+	.B(blankn ? {b,b[1]} : 0),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -103,98 +108,62 @@ video_mixer video_mixer(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
+	.ce_divider(1'b1),
+	.rotate({1'b1,rotate}),
+	.blend(blend),
+	.scanlines(scanlines),
+	.scandoubler_disable(scandoublerD),
+	.ypbpr(ypbpr)
 	);
 
-mist_io #(
+user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clock_24       ),
+user_io(
+	.clk_sys        (clock_12       ),
 	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
 	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
 	.joystick_1     (joystick_1     ),
 	.status         (status         )
 	);
 
 dac #(
-	.MSBI(15),
-	.INV(1'b1))
+	.C_bits(16))
 dac(
-	.CLK(clock_24),
-	.RESET(0),
-	.DACin(audio),
-	.DACout(AUDIO_L)
+	.clk_i(clock_12),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
 	);
 
-wire m_up1     = btn_up1 | joystick_0[3];
-wire m_down1   = btn_down1 | joystick_0[2];
-wire m_left1   = btn_left1 | joystick_0[1];
-wire m_right1  = btn_right1 | joystick_0[0];
-
-wire m_up2     = btn_up2 | joystick_1[3];
-wire m_down2   = btn_down2 | joystick_1[2];
-wire m_left2   = btn_left2 | joystick_1[1];
-wire m_right2  = btn_right2 | joystick_1[0];
-
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-//wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left1 = 0;
-reg btn_right1 = 0;
-reg btn_down1 = 0;
-reg btn_up1 = 0;
-reg btn_left2 = 0;
-reg btn_right2 = 0;
-reg btn_down2 = 0;
-reg btn_up2 = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clock_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up1         	<= pressed; // up
-			'h72: btn_down1        	<= pressed; // down
-			'h6B: btn_left1      	<= pressed; // left
-			'h74: btn_right1       	<= pressed; // right
-			
-			'h1D: btn_up2         	<= pressed; // W
-			'h1B: btn_down2        	<= pressed; // S
-			'h1C: btn_left2      	<= pressed; // A
-			'h23: btn_right2       	<= pressed; // D
-			
-			
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
  
+arcade_inputs inputs (
+        .clk         ( clock_12    ),
+        .key_strobe  ( key_strobe  ),
+        .key_pressed ( key_pressed ),
+        .key_code    ( key_code    ),
+        .joystick_0  ( joystick_0  ),
+        .joystick_1  ( joystick_1  ),
+        .rotate      ( rotate      ),
+        .orientation ( 2'b10       ),
+        .joyswap     ( 1'b0        ),
+        .oneplayer   ( 1'b1        ),
+        .controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+        .player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+        .player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
+
 endmodule
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index 398fa0df..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1073 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed wait and halt
---
---	0211 : Fixed Refresh addition and IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---	0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---	0237 : Changed 8080 I/O address output, added IntE output
---
---	0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---	0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---	0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F			: std_logic_vector(7 downto 0);
-	signal Ap, Fp			: std_logic_vector(7 downto 0);
-	signal I				: std_logic_vector(7 downto 0);
-	signal R				: unsigned(7 downto 0);
-	signal SP, PC			: unsigned(15 downto 0);
-	signal RegDIH			: std_logic_vector(7 downto 0);
-	signal RegDIL			: std_logic_vector(7 downto 0);
-	signal RegBusA			: std_logic_vector(15 downto 0);
-	signal RegBusB			: std_logic_vector(15 downto 0);
-	signal RegBusC			: std_logic_vector(15 downto 0);
-	signal RegAddrA_r		: std_logic_vector(2 downto 0);
-	signal RegAddrA			: std_logic_vector(2 downto 0);
-	signal RegAddrB_r		: std_logic_vector(2 downto 0);
-	signal RegAddrB			: std_logic_vector(2 downto 0);
-	signal RegAddrC			: std_logic_vector(2 downto 0);
-	signal RegWEH			: std_logic;
-	signal RegWEL			: std_logic;
-	signal Alternate		: std_logic;
-
-	-- Help Registers
-	signal TmpAddr			: std_logic_vector(15 downto 0);	-- Temporary address register
-	signal IR				: std_logic_vector(7 downto 0);		-- Instruction register
-	signal ISet				: std_logic_vector(1 downto 0);		-- Instruction set selector
-	signal RegBusA_r		: std_logic_vector(15 downto 0);
-
-	signal ID16				: signed(15 downto 0);
-	signal Save_Mux			: std_logic_vector(7 downto 0);
-
-	signal TState			: unsigned(2 downto 0);
-	signal MCycle			: std_logic_vector(2 downto 0);
-	signal IntE_FF1			: std_logic;
-	signal IntE_FF2			: std_logic;
-	signal Halt_FF			: std_logic;
-	signal BusReq_s			: std_logic;
-	signal BusAck			: std_logic;
-	signal ClkEn			: std_logic;
-	signal NMI_s			: std_logic;
-	signal INT_s			: std_logic;
-	signal IStatus			: std_logic_vector(1 downto 0);
-
-	signal DI_Reg			: std_logic_vector(7 downto 0);
-	signal T_Res			: std_logic;
-	signal XY_State			: std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M		: std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch	: std_logic;
-	signal XY_Ind			: std_logic;
-	signal No_BTR			: std_logic;
-	signal BTR_r			: std_logic;
-	signal Auto_Wait		: std_logic;
-	signal Auto_Wait_t1		: std_logic;
-	signal Auto_Wait_t2		: std_logic;
-	signal IncDecZ			: std_logic;
-
-	-- ALU signals
-	signal BusB				: std_logic_vector(7 downto 0);
-	signal BusA				: std_logic_vector(7 downto 0);
-	signal ALU_Q			: std_logic_vector(7 downto 0);
-	signal F_Out			: std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r	: std_logic_vector(4 downto 0);
-	signal Arith16_r		: std_logic;
-	signal Z16_r			: std_logic;
-	signal ALU_Op_r			: std_logic_vector(3 downto 0);
-	signal Save_ALU_r		: std_logic;
-	signal PreserveC_r		: std_logic;
-	signal MCycles			: std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d		: std_logic_vector(2 downto 0);
-	signal TStates			: std_logic_vector(2 downto 0);
-	signal IntCycle			: std_logic;
-	signal NMICycle			: std_logic;
-	signal Inc_PC			: std_logic;
-	signal Inc_WZ			: std_logic;
-	signal IncDec_16		: std_logic_vector(3 downto 0);
-	signal Prefix			: std_logic_vector(1 downto 0);
-	signal Read_To_Acc		: std_logic;
-	signal Read_To_Reg		: std_logic;
-	signal Set_BusB_To		: std_logic_vector(3 downto 0);
-	signal Set_BusA_To		: std_logic_vector(3 downto 0);
-	signal ALU_Op			: std_logic_vector(3 downto 0);
-	signal Save_ALU			: std_logic;
-	signal PreserveC		: std_logic;
-	signal Arith16			: std_logic;
-	signal Set_Addr_To		: std_logic_vector(2 downto 0);
-	signal Jump				: std_logic;
-	signal JumpE			: std_logic;
-	signal JumpXY			: std_logic;
-	signal Call				: std_logic;
-	signal RstP				: std_logic;
-	signal LDZ				: std_logic;
-	signal LDW				: std_logic;
-	signal LDSPHL			: std_logic;
-	signal IORQ_i			: std_logic;
-	signal Special_LD		: std_logic_vector(2 downto 0);
-	signal ExchangeDH		: std_logic;
-	signal ExchangeRp		: std_logic;
-	signal ExchangeAF		: std_logic;
-	signal ExchangeRS		: std_logic;
-	signal I_DJNZ			: std_logic;
-	signal I_CPL			: std_logic;
-	signal I_CCF			: std_logic;
-	signal I_SCF			: std_logic;
-	signal I_RETN			: std_logic;
-	signal I_BT				: std_logic;
-	signal I_BC				: std_logic;
-	signal I_BTR			: std_logic;
-	signal I_RLD			: std_logic;
-	signal I_RRD			: std_logic;
-	signal I_INRC			: std_logic;
-	signal SetDI			: std_logic;
-	signal SetEI			: std_logic;
-	signal IMode			: std_logic_vector(1 downto 0);
-	signal Halt				: std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR => IR,
-			ISet => ISet,
-			MCycle => MCycle,
-			F => F,
-			NMICycle => NMICycle,
-			IntCycle => IntCycle,
-			MCycles => MCycles_d,
-			TStates => TStates,
-			Prefix => Prefix,
-			Inc_PC => Inc_PC,
-			Inc_WZ => Inc_WZ,
-			IncDec_16 => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op => ALU_Op,
-			Save_ALU => Save_ALU,
-			PreserveC => PreserveC,
-			Arith16 => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ => IORQ_i,
-			Jump => Jump,
-			JumpE => JumpE,
-			JumpXY => JumpXY,
-			Call => Call,
-			RstP => RstP,
-			LDZ => LDZ,
-			LDW => LDW,
-			LDSPHL => LDSPHL,
-			Special_LD => Special_LD,
-			ExchangeDH => ExchangeDH,
-			ExchangeRp => ExchangeRp,
-			ExchangeAF => ExchangeAF,
-			ExchangeRS => ExchangeRS,
-			I_DJNZ => I_DJNZ,
-			I_CPL => I_CPL,
-			I_CCF => I_CCF,
-			I_SCF => I_SCF,
-			I_RETN => I_RETN,
-			I_BT => I_BT,
-			I_BC => I_BC,
-			I_BTR => I_BTR,
-			I_RLD => I_RLD,
-			I_RRD => I_RRD,
-			I_INRC => I_INRC,
-			SetDI => SetDI,
-			SetEI => SetEI,
-			IMode => IMode,
-			Halt => Halt,
-			NoRead => NoRead,
-			Write => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16 => Z16_r,
-			ALU_Op => ALU_Op_r,
-			IR => IR(5 downto 0),
-			ISet => ISet,
-			BusA => BusA,
-			BusB => BusB,
-			F_In => F,
-			Q => ALU_Q,
-			F_Out => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 and Auto_Wait_t1 = '0' then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if T_Res = '1' then
-				Auto_Wait_t1 <= '0';
-			else
-				Auto_Wait_t1 <= Auto_Wait or IORQ_i;
-			end if;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
-						(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 86fddce7..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0238 : Fixed zero flag for 16 bit SBC and ADC
---
---	0240 : Added GB operations
---
---	0242 : Cleanup
---
---	0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A : std_logic_vector;
-					B : std_logic_vector;
-					Sub : std_logic;
-					Carry_In : std_logic;
-					signal Res : out std_logic_vector;
-					signal Carry : out std_logic) is
-		variable B_i		: unsigned(A'length - 1 downto 0);
-		variable Res_i		: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i := unsigned(B);
-		end if;
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal	UseCarry		: std_logic;
-	signal	Carry7_v		: std_logic;
-	signal	Overflow_v		: std_logic;
-	signal	HalfCarry_v		: std_logic;
-	signal	Carry_v			: std_logic;
-	signal	Q_v				: std_logic_vector(7 downto 0);
-
-	signal	BitMask			: std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-									"00000010" when "001",
-									"00000100" when "010",
-									"00001000" when "011",
-									"00010000" when "100",
-									"00100000" when "101",
-									"01000000" when "110",
-									"10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);	-- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 4cc30f35..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1934 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0235 : Added IM 2 fix by Mike Johnson
---
---	0238 : Added NoRead signal
---
---	0238b: Fixed instruction timing for POP and DJNZ
---
---	0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
---	0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
---	constant aNone	: std_logic_vector(2 downto 0) := "000";
---	constant aXY	: std_logic_vector(2 downto 0) := "001";
---	constant aIOA	: std_logic_vector(2 downto 0) := "010";
---	constant aSP	: std_logic_vector(2 downto 0) := "011";
---	constant aBC	: std_logic_vector(2 downto 0) := "100";
---	constant aDE	: std_logic_vector(2 downto 0) := "101";
---	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---	Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To	<= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To	<= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";	-- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n	-- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To	<= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---	CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-					Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others =>
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---	ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)	<= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index ac7d34da..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,208 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80s.vhd
deleted file mode 100644
index 5b612110..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/T80/T80s.vhd	
+++ /dev/null
@@ -1,190 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed read with wait
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0236 : Added T2Write generic
---
---	0237 : Fixed T2Write with wait state
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80s is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
-		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80s;
-
-architecture rtl of T80s is
-
-	signal CEN			: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => IOWait)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_n,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => RESET_n,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK_n,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			if MCycle = "001" then
-				if TState = "001" or (TState = "010" and Wait_n = '0') then
-					RD_n <= not IntCycle_n;
-					MREQ_n <= not IntCycle_n;
-					IORQ_n <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					MREQ_n <= '0';
-				end if;
-			else
-				if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
-					RD_n <= '0';
-					IORQ_n <= not IORQ;
-					MREQ_n <= IORQ;
-				end if;
-				if T2Write = 0 then
-					if TState = "010" and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				end if;
-			end if;
-			if TState = "010" and Wait_n = '1' then
-				DI_Reg <= DI;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/crazy_climber.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/crazy_climber.vhd
index 13fcf7b6..6b80a7b4 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/crazy_climber.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/crazy_climber.vhd	
@@ -131,6 +131,7 @@ signal video_mux              : std_logic_vector(7 downto 0);
 
 -- Z80 interface 
 signal cpu_clock  : std_logic;
+signal cpu_clock_en: std_logic;
 signal cpu_wr_n   : std_logic;
 signal cpu_addr   : std_logic_vector(15 downto 0);
 signal cpu_do     : std_logic_vector(7 downto 0);
@@ -263,13 +264,13 @@ reg6_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto
 ---------------------------
 -- enable/disable interrupt
 ---------------------------
-process (cpu_clock)
+process (clock_12)
 begin
-	if falling_edge(cpu_clock) then
-		if cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then
+	if rising_edge(clock_12) then
+		if cpu_clock_en = '1' and cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then
 			raz_int_n <= cpu_do(0);
 		end if;
-end if;
+	end if;
 end process;
 
 -------------------------------
@@ -661,8 +662,9 @@ port map (
   y_tile     => y_tile,
   x_pixel    => x_pixel,
   y_pixel    => y_pixel,
-	
-  cpu_clock  => cpu_clock
+
+  cpu_clock  => cpu_clock,
+  cpu_clock_en => cpu_clock_en
 );
 
 -- sprite palette rom
@@ -682,11 +684,12 @@ port map (
 );
 
 -- Z80
-Z80 : entity work.T80s
+Z80 : entity work.T80se
 generic map(Mode => 0, T2Write => 1, IOWait => 1)
 port map(
   RESET_n => reset_n,
-  CLK_n   => cpu_clock,
+  CLK_n   => clock_12,
+  CLKEN   => cpu_clock_en,
   WAIT_n  => '1',
   INT_n   => '1',
   NMI_n   => cpu_int_n,
@@ -806,7 +809,8 @@ port map (
 -- sound
 cclimber_sound : entity work.crazy_climber_sound
 port map(
-  cpu_clock    => cpu_clock,
+  clock_12     => clock_12,
+  cpu_clock_en => cpu_clock_en,
   cpu_addr     => cpu_addr,
   cpu_data     => cpu_do,
   cpu_iorq_n   => cpu_iorq_n,
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/crazy_climber_sound.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/crazy_climber_sound.vhd
index 6eba7c6b..c9c898a0 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/crazy_climber_sound.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/crazy_climber_sound.vhd	
@@ -6,7 +6,8 @@ use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
 entity crazy_climber_sound is
 port	(
-	cpu_clock    : in std_logic;
+	clock_12     : in std_logic;
+	cpu_clock_en : in std_logic;
 	cpu_addr     : in std_logic_vector(15 downto 0);
 	cpu_data     : in std_logic_vector( 7 downto 0);
 	cpu_iorq_n   : in std_logic;
@@ -23,6 +24,8 @@ architecture struct of crazy_climber_sound is
 signal hdiv         : std_logic_vector(1 downto 0);
 signal clock_1_5mhz : std_logic; -- 1.50Mhz
 signal clock_750khz : std_logic; -- 0.75MHz
+signal clock_1_5mhz_en : std_logic; -- 1.50Mhz
+signal clock_750khz_en : std_logic; -- 0.75MHz
 
 signal ym_2149_audio : std_logic_vector(7 downto 0);
 
@@ -42,12 +45,15 @@ signal sample_data     : std_logic_vector(3 downto 0);
 
 begin
 
-clock_1_5mhz <= hdiv(0);
-clock_750khz <= hdiv(1);
+--clock_1_5mhz <= hdiv(0);
+--clock_750khz <= hdiv(1);
 
-process(cpu_clock)
+clock_1_5mhz_en <= cpu_clock_en and hdiv(0);
+clock_750khz_en <= '1' when cpu_clock_en = '1' and hdiv="01" else '0';
+
+process(clock_12, cpu_clock_en)
 begin
-	if falling_edge(cpu_clock) then
+	if rising_edge(clock_12) and cpu_clock_en = '1' then
 
 		if hdiv = "11" then
 			hdiv <= "00";
@@ -76,9 +82,9 @@ end process;
 
 -- Sample machine
 
-process(clock_750khz)
+process(clock_12, clock_750khz_en)
 begin
-	if rising_edge(clock_750khz) then
+	if rising_edge(clock_12) and clock_750khz_en = '1' then
 		if frequency_cnt = "11111111" then
 			frequency_cnt   <= frequency_div;
 			frequency_tick  <= '1';
@@ -114,7 +120,7 @@ sound_sample <= std_logic_vector(( unsigned(ym_2149_audio) & unsigned(ym_2149_au
 sample_rom : entity work.cclimber_samples
 port map (
 	addr  => sample_rom_addr,
-	clk   => cpu_clock, 
+	clk   => clock_12, 
 	data  => sound_data
 );
 
@@ -142,9 +148,9 @@ port map (
 	O_IOB           => sample_start2, --: out std_logic_vector(7 downto 0);
 	O_IOB_OE_L      => open,          --: out std_logic;
 
-	ENA             => '1',           --: in  std_logic; -- clock enable for higher speed operation
+	ENA             => clock_1_5mhz_en,--: in  std_logic; -- clock enable for higher speed operation
 	RESET_L         => '1',           --: in  std_logic;
-	CLK             => clock_1_5mhz   --: in  std_logic  -- note 6 Mhz!
+	CLK             => clock_12       --: in  std_logic
 );
 
 end architecture;
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/dac.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/dac.sv
deleted file mode 100644
index 5dea333e..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/dac.sv	
+++ /dev/null
@@ -1,33 +0,0 @@
-//
-// PWM DAC
-//
-// MSBI is the highest bit number. NOT amount of bits!
-//
-module dac #(parameter MSBI=15, parameter INV=1'b1)
-(
-   output reg      DACout, //Average Output feeding analog lowpass
-   input  [MSBI:0] DACin,  //DAC input (excess 2**MSBI)
-   input           CLK,
-   input           RESET
-);
-
-reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
-reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
-reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
-reg [MSBI+2:0] DeltaB;     //B input of Delta Adder
-
-always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
-always @(*) DeltaAdder = DACin + DeltaB;
-always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
-
-always @(posedge CLK or posedge RESET) begin
-   if(RESET) begin
-      SigmaLatch <= 1'b1 << (MSBI+1);
-      DACout <= INV;
-   end else begin
-      SigmaLatch <= SigmaAdder;
-      DACout <= SigmaLatch[MSBI+2] ^ INV;
-   end
-end
-
-endmodule
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/hq2x.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/mist_io.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/mist_io.sv
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/mist_io.sv	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/osd.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/osd.sv
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/osd.sv	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_big_sprite_palette.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_palette.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_big_sprite_palette.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_big_sprite_tile_bit0.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_big_sprite_tile_bit0.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_big_sprite_tile_bit1.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_big_sprite_tile_bit1.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_palette.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_palette.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_palette.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_program.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_program.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_program.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_program.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_samples.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_samples.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_samples.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_samples.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit0.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_tile_bit0.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit0.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_tile_bit0.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit1.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_tile_bit1.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit1.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/rom/cclimber_tile_bit1.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/scandoubler.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/scandoubler.sv
deleted file mode 100644
index 0213d20c..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/scandoubler.sv	
+++ /dev/null
@@ -1,195 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/video_gen.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/video_gen.vhd
index 2abe45d1..94c0dcd0 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/video_gen.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/video_gen.vhd	
@@ -11,8 +11,8 @@ port(
 	hsync       : out std_logic;
 	vsync       : out std_logic;
 	csync       : out std_logic;
-	hblank       : out std_logic;
-	vblank       : out std_logic;
+	hblank      : out std_logic;
+	vblank      : out std_logic;
 
 	is_sprite   : out std_logic;
 	sprite      : out std_logic_vector(2 downto 0);
@@ -21,7 +21,8 @@ port(
 	x_pixel     : out std_logic_vector(2 downto 0);
 	y_pixel     : out std_logic_vector(2 downto 0);
 
-	cpu_clock   : out std_logic
+	cpu_clock   : out std_logic;
+	cpu_clock_en: out std_logic
 );
 end video_gen;
 
@@ -39,6 +40,7 @@ signal enable_clk : std_logic := '0';
 begin
 
 cpu_clock  <= not hcnt(0);
+cpu_clock_en <= ena_pixel and hcnt(0);
 is_sprite  <= not hcnt(8);
 sprite     <= std_logic_vector(hcnt(6 downto 4));
 x_tile     <= std_logic_vector(hcnt(7 downto 3));
@@ -113,14 +115,14 @@ begin
 			end if;
 
 			if    vcnt = 511 then vsync <= '0';
-			elsif vcnt = 250 then vsync <= '1';--
+			elsif vcnt = 250 then vsync <= '1';
 			end if;    
 
-			if    hcnt = (127+8+1) then hblank <= '1'; -- +8 = retard du shift_register + 1 pixel--
-			elsif hcnt = (255+8+1) then hblank <= '0'; -- +8 = retard du shift_register + 1 pixel--
+			if    hcnt = (127+8+1) then hblank <= '1'; -- +8 = retard du shift_register + 1 pixel
+			elsif hcnt = (255+8+1) then hblank <= '0'; -- +8 = retard du shift_register + 1 pixel
 			end if;    
 
-			if    vcnt = (495+1+0) then vblank <= '1';
+			if    vcnt = (495+1+1) then vblank <= '1';
 			elsif vcnt = (271+1+1) then vblank <= '0';
 			end if;   
 
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/video_mixer.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyClimber_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.qsf b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.qsf
index fb7f9b54..a886c867 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.qsf	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.qsf	
@@ -40,32 +40,10 @@
 # Project-Wide Assignments
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/ckong_mist.sv
-set_global_assignment -name VHDL_FILE rtl/ckong.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_tile_bit1.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_tile_bit0.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_samples.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_program.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_tile_bit1.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_tile_bit0.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_big_sprite_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/ckong_sound.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
-set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 
 # Pin & Location Assignments
 # ==========================
@@ -167,4 +145,29 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(ckong_mist)
 # ----------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/ckong_mist.sv
+set_global_assignment -name VHDL_FILE rtl/ckong.vhd
+set_global_assignment -name VHDL_FILE rtl/ckong_sound.vhd
+set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
+set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_tile_bit1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_tile_bit0.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_samples.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_program.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_palette.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_big_sprite_tile_bit1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_big_sprite_tile_bit0.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ckong_big_sprite_palette.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.sdc b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.sdc
new file mode 100644
index 00000000..b9b92495
--- /dev/null
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.sdc	
@@ -0,0 +1,134 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk   "pll|altpll_component|auto_generated|pll1|clk[0]"
+set vid_clk   "pll|altpll_component|auto_generated|pll1|clk[0]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $vid_clk]  1.000 [get_ports {VGA_*}]
+
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.srf b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.srf
deleted file mode 100644
index 4174c086..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.srf	
+++ /dev/null
@@ -1,9 +0,0 @@
-{ "" "" "" "Inferred dual-clock RAM node \"mist_video:mist_video\|osd:osd\|osd_buffer_rtl_0\" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." {  } {  } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "6 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Design contains 1 input pin(s) that do not drive logic" {  } {  } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "PLL \"pll:pll\|altpll:altpll_component\|pll_altpll:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" {  } {  } 0 15899 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "TimeQuest Timing Analyzer is analyzing 2 combinational loops as latches." {  } {  } 0 335093 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "8192 out of 32768 addresses are uninitialized. The Quartus II software will initialize them to \"0\". There are 1 warnings found, and 1 warnings are reported." {  } {  } 0 113028 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Output pins are stuck at VCC or GND" {  } {  } 0 13024 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index 398fa0df..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1073 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed wait and halt
---
---	0211 : Fixed Refresh addition and IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---	0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---	0237 : Changed 8080 I/O address output, added IntE output
---
---	0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---	0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---	0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F			: std_logic_vector(7 downto 0);
-	signal Ap, Fp			: std_logic_vector(7 downto 0);
-	signal I				: std_logic_vector(7 downto 0);
-	signal R				: unsigned(7 downto 0);
-	signal SP, PC			: unsigned(15 downto 0);
-	signal RegDIH			: std_logic_vector(7 downto 0);
-	signal RegDIL			: std_logic_vector(7 downto 0);
-	signal RegBusA			: std_logic_vector(15 downto 0);
-	signal RegBusB			: std_logic_vector(15 downto 0);
-	signal RegBusC			: std_logic_vector(15 downto 0);
-	signal RegAddrA_r		: std_logic_vector(2 downto 0);
-	signal RegAddrA			: std_logic_vector(2 downto 0);
-	signal RegAddrB_r		: std_logic_vector(2 downto 0);
-	signal RegAddrB			: std_logic_vector(2 downto 0);
-	signal RegAddrC			: std_logic_vector(2 downto 0);
-	signal RegWEH			: std_logic;
-	signal RegWEL			: std_logic;
-	signal Alternate		: std_logic;
-
-	-- Help Registers
-	signal TmpAddr			: std_logic_vector(15 downto 0);	-- Temporary address register
-	signal IR				: std_logic_vector(7 downto 0);		-- Instruction register
-	signal ISet				: std_logic_vector(1 downto 0);		-- Instruction set selector
-	signal RegBusA_r		: std_logic_vector(15 downto 0);
-
-	signal ID16				: signed(15 downto 0);
-	signal Save_Mux			: std_logic_vector(7 downto 0);
-
-	signal TState			: unsigned(2 downto 0);
-	signal MCycle			: std_logic_vector(2 downto 0);
-	signal IntE_FF1			: std_logic;
-	signal IntE_FF2			: std_logic;
-	signal Halt_FF			: std_logic;
-	signal BusReq_s			: std_logic;
-	signal BusAck			: std_logic;
-	signal ClkEn			: std_logic;
-	signal NMI_s			: std_logic;
-	signal INT_s			: std_logic;
-	signal IStatus			: std_logic_vector(1 downto 0);
-
-	signal DI_Reg			: std_logic_vector(7 downto 0);
-	signal T_Res			: std_logic;
-	signal XY_State			: std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M		: std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch	: std_logic;
-	signal XY_Ind			: std_logic;
-	signal No_BTR			: std_logic;
-	signal BTR_r			: std_logic;
-	signal Auto_Wait		: std_logic;
-	signal Auto_Wait_t1		: std_logic;
-	signal Auto_Wait_t2		: std_logic;
-	signal IncDecZ			: std_logic;
-
-	-- ALU signals
-	signal BusB				: std_logic_vector(7 downto 0);
-	signal BusA				: std_logic_vector(7 downto 0);
-	signal ALU_Q			: std_logic_vector(7 downto 0);
-	signal F_Out			: std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r	: std_logic_vector(4 downto 0);
-	signal Arith16_r		: std_logic;
-	signal Z16_r			: std_logic;
-	signal ALU_Op_r			: std_logic_vector(3 downto 0);
-	signal Save_ALU_r		: std_logic;
-	signal PreserveC_r		: std_logic;
-	signal MCycles			: std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d		: std_logic_vector(2 downto 0);
-	signal TStates			: std_logic_vector(2 downto 0);
-	signal IntCycle			: std_logic;
-	signal NMICycle			: std_logic;
-	signal Inc_PC			: std_logic;
-	signal Inc_WZ			: std_logic;
-	signal IncDec_16		: std_logic_vector(3 downto 0);
-	signal Prefix			: std_logic_vector(1 downto 0);
-	signal Read_To_Acc		: std_logic;
-	signal Read_To_Reg		: std_logic;
-	signal Set_BusB_To		: std_logic_vector(3 downto 0);
-	signal Set_BusA_To		: std_logic_vector(3 downto 0);
-	signal ALU_Op			: std_logic_vector(3 downto 0);
-	signal Save_ALU			: std_logic;
-	signal PreserveC		: std_logic;
-	signal Arith16			: std_logic;
-	signal Set_Addr_To		: std_logic_vector(2 downto 0);
-	signal Jump				: std_logic;
-	signal JumpE			: std_logic;
-	signal JumpXY			: std_logic;
-	signal Call				: std_logic;
-	signal RstP				: std_logic;
-	signal LDZ				: std_logic;
-	signal LDW				: std_logic;
-	signal LDSPHL			: std_logic;
-	signal IORQ_i			: std_logic;
-	signal Special_LD		: std_logic_vector(2 downto 0);
-	signal ExchangeDH		: std_logic;
-	signal ExchangeRp		: std_logic;
-	signal ExchangeAF		: std_logic;
-	signal ExchangeRS		: std_logic;
-	signal I_DJNZ			: std_logic;
-	signal I_CPL			: std_logic;
-	signal I_CCF			: std_logic;
-	signal I_SCF			: std_logic;
-	signal I_RETN			: std_logic;
-	signal I_BT				: std_logic;
-	signal I_BC				: std_logic;
-	signal I_BTR			: std_logic;
-	signal I_RLD			: std_logic;
-	signal I_RRD			: std_logic;
-	signal I_INRC			: std_logic;
-	signal SetDI			: std_logic;
-	signal SetEI			: std_logic;
-	signal IMode			: std_logic_vector(1 downto 0);
-	signal Halt				: std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR => IR,
-			ISet => ISet,
-			MCycle => MCycle,
-			F => F,
-			NMICycle => NMICycle,
-			IntCycle => IntCycle,
-			MCycles => MCycles_d,
-			TStates => TStates,
-			Prefix => Prefix,
-			Inc_PC => Inc_PC,
-			Inc_WZ => Inc_WZ,
-			IncDec_16 => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op => ALU_Op,
-			Save_ALU => Save_ALU,
-			PreserveC => PreserveC,
-			Arith16 => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ => IORQ_i,
-			Jump => Jump,
-			JumpE => JumpE,
-			JumpXY => JumpXY,
-			Call => Call,
-			RstP => RstP,
-			LDZ => LDZ,
-			LDW => LDW,
-			LDSPHL => LDSPHL,
-			Special_LD => Special_LD,
-			ExchangeDH => ExchangeDH,
-			ExchangeRp => ExchangeRp,
-			ExchangeAF => ExchangeAF,
-			ExchangeRS => ExchangeRS,
-			I_DJNZ => I_DJNZ,
-			I_CPL => I_CPL,
-			I_CCF => I_CCF,
-			I_SCF => I_SCF,
-			I_RETN => I_RETN,
-			I_BT => I_BT,
-			I_BC => I_BC,
-			I_BTR => I_BTR,
-			I_RLD => I_RLD,
-			I_RRD => I_RRD,
-			I_INRC => I_INRC,
-			SetDI => SetDI,
-			SetEI => SetEI,
-			IMode => IMode,
-			Halt => Halt,
-			NoRead => NoRead,
-			Write => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16 => Z16_r,
-			ALU_Op => ALU_Op_r,
-			IR => IR(5 downto 0),
-			ISet => ISet,
-			BusA => BusA,
-			BusB => BusB,
-			F_In => F,
-			Q => ALU_Q,
-			F_Out => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 and Auto_Wait_t1 = '0' then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if T_Res = '1' then
-				Auto_Wait_t1 <= '0';
-			else
-				Auto_Wait_t1 <= Auto_Wait or IORQ_i;
-			end if;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
-						(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 86fddce7..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0238 : Fixed zero flag for 16 bit SBC and ADC
---
---	0240 : Added GB operations
---
---	0242 : Cleanup
---
---	0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A : std_logic_vector;
-					B : std_logic_vector;
-					Sub : std_logic;
-					Carry_In : std_logic;
-					signal Res : out std_logic_vector;
-					signal Carry : out std_logic) is
-		variable B_i		: unsigned(A'length - 1 downto 0);
-		variable Res_i		: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i := unsigned(B);
-		end if;
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal	UseCarry		: std_logic;
-	signal	Carry7_v		: std_logic;
-	signal	Overflow_v		: std_logic;
-	signal	HalfCarry_v		: std_logic;
-	signal	Carry_v			: std_logic;
-	signal	Q_v				: std_logic_vector(7 downto 0);
-
-	signal	BitMask			: std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-									"00000010" when "001",
-									"00000100" when "010",
-									"00001000" when "011",
-									"00010000" when "100",
-									"00100000" when "101",
-									"01000000" when "110",
-									"10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);	-- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 4cc30f35..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1934 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0235 : Added IM 2 fix by Mike Johnson
---
---	0238 : Added NoRead signal
---
---	0238b: Fixed instruction timing for POP and DJNZ
---
---	0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
---	0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
---	constant aNone	: std_logic_vector(2 downto 0) := "000";
---	constant aXY	: std_logic_vector(2 downto 0) := "001";
---	constant aIOA	: std_logic_vector(2 downto 0) := "010";
---	constant aSP	: std_logic_vector(2 downto 0) := "011";
---	constant aBC	: std_logic_vector(2 downto 0) := "100";
---	constant aDE	: std_logic_vector(2 downto 0) := "101";
---	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---	Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To	<= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To	<= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";	-- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n	-- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To	<= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---	CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-					Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others =>
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---	ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)	<= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index ac7d34da..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,208 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80s.vhd
deleted file mode 100644
index 5b612110..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80s.vhd	
+++ /dev/null
@@ -1,190 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed read with wait
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0236 : Added T2Write generic
---
---	0237 : Fixed T2Write with wait state
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80s is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
-		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80s;
-
-architecture rtl of T80s is
-
-	signal CEN			: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => IOWait)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_n,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => RESET_n,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK_n,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			if MCycle = "001" then
-				if TState = "001" or (TState = "010" and Wait_n = '0') then
-					RD_n <= not IntCycle_n;
-					MREQ_n <= not IntCycle_n;
-					IORQ_n <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					MREQ_n <= '0';
-				end if;
-			else
-				if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
-					RD_n <= '0';
-					IORQ_n <= not IORQ;
-					MREQ_n <= IORQ;
-				end if;
-				if T2Write = 0 then
-					if TState = "010" and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				end if;
-			end if;
-			if TState = "010" and Wait_n = '1' then
-				DI_Reg <= DI;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong.vhd
index dde9c67a..9b9400a6 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong.vhd	
@@ -120,6 +120,7 @@ signal video_mux              : std_logic_vector(7 downto 0);
 
 -- Z80 interface 
 signal cpu_clock  : std_logic;
+signal cpu_clock_en: std_logic;
 signal cpu_wr_n   : std_logic;
 signal cpu_addr   : std_logic_vector(15 downto 0);
 signal cpu_do     : std_logic_vector(7 downto 0);
@@ -231,10 +232,10 @@ reg6_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto
 ---------------------------
 -- enable/disable interrupt
 ---------------------------
-process (cpu_clock)
+process (clock_12)
 begin
-	if falling_edge(cpu_clock) then
-		if cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then
+	if rising_edge(clock_12) then
+		if cpu_clock_en = '1' and cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then
 			raz_int_n <= cpu_do(0);
 		end if;
 end if;
@@ -615,7 +616,8 @@ port map (
   x_pixel    => x_pixel,
   y_pixel    => y_pixel,
 	
-  cpu_clock  => cpu_clock
+  cpu_clock  => cpu_clock,
+  cpu_clock_en => cpu_clock_en
 );
 
 -- sprite palette rom
@@ -635,11 +637,12 @@ port map (
 );
 
 -- Z80
-Z80 : entity work.T80s
+Z80 : entity work.T80se
 generic map(Mode => 0, T2Write => 1, IOWait => 1)
 port map(
   RESET_n => reset_n,
-  CLK_n   => cpu_clock,
+  CLK_n   => clock_12,
+  CLKEN   => cpu_clock_en,
   WAIT_n  => '1',
   INT_n   => '1',
   NMI_n   => cpu_int_n,
@@ -756,7 +759,8 @@ port map (
 -- sound
 ckong_sound : entity work.ckong_sound
 port map(
-  cpu_clock    => cpu_clock,
+  clock_12     => clock_12,
+  cpu_clock_en => cpu_clock_en,
   cpu_addr     => cpu_addr,
   cpu_data     => cpu_do,
   cpu_iorq_n   => cpu_iorq_n,
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_mist.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_mist.sv
index 81bbea61..03ed9aaf 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_mist.sv	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_mist.sv	
@@ -22,10 +22,15 @@ localparam CONF_STR = {
 	"CrazyKong;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
+	"O5,Blend,Off,On;",
+	"T0,Reset;",
 	"V,v1.21.",`BUILD_DATE
 };
 
+wire       rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire       blend = status[5];
+
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
@@ -40,12 +45,13 @@ pll pll(
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [9:0] kbjoy;
 wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
 wire [15:0] audio;
 wire hs, vs;
 wire blankn;
@@ -54,7 +60,7 @@ wire [1:0] 	b;
 
 ckong ckong(
 	.clock_12(clock_12),
-	.reset(status[0] | status[6] | buttons[1]),
+	.reset(status[0] | buttons[1]),
 	.video_r(r),
 	.video_g(g),
 	.video_b(b),
@@ -62,23 +68,23 @@ ckong ckong(
 	.video_vs(vs),
 	.blankn(blankn),
 	.audio_out(audio),
-	.start2(btn_two_players),
-	.start1(btn_one_player),
-	.coin1(btn_coin),
-	.fire1(m_fire),
+	.start2(m_two_players),
+	.start1(m_one_player),
+	.coin1(m_coin1),
+	.fire1(m_fireA),
 	.right1(m_right),
 	.left1(m_left),
 	.down1(m_down),
 	.up1(m_up),
-	.fire2(m_fire),
-	.right2(m_right),
-	.left2(m_left),
-	.down2(m_down),
-	.up2(m_up)
+	.fire2(m_fire2A),
+	.right2(m_right2),
+	.left2(m_left2),
+	.down2(m_down2),
+	.up2(m_up2)
 	);
-	
+
 mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
-	.clk_sys(clock_24),
+	.clk_sys(clock_12), // Just not enough BRAM for clock_24 and HCNT_WIDTH(10)
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -92,9 +98,10 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.ce_divider(1'b0),
-	.rotate({1'b1,status[2]}),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
+	.ce_divider(1'b1),
+	.rotate({1'b1,rotate}),
+	.blend(blend),
+	.scanlines(scanlines),
 	.scandoubler_disable(scandoublerD),
 	.ypbpr(ypbpr)
 	);
@@ -102,7 +109,7 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clock_24       ),
+	.clk_sys        (clock_12       ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -121,48 +128,32 @@ user_io(
 	);
 
 dac #(
-	.C_bits(15))
+	.C_bits(16))
 dac(
-	.clk_i(clock_24),
+	.clk_i(clock_12),
 	.res_n_i(1),
-	.dac_i({~audio[15],audio[14:0]}),
+	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
-wire       key_pressed;
-wire [7:0] key_code;
-wire       key_strobe;
-
-always @(posedge clock_24) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up         	<= key_pressed; // up
-			'h72: btn_down        	<= key_pressed; // down
-			'h6B: btn_left      	<= key_pressed; // left
-			'h74: btn_right       	<= key_pressed; // right
-			'h76: btn_coin			<= key_pressed; // ESC
-			'h05: btn_one_player   	<= key_pressed; // F1
-			'h06: btn_two_players  	<= key_pressed; // F2
-			'h29: btn_fire1   		<= key_pressed; // Space
-		endcase
-	end
-end
-
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+ 
+arcade_inputs inputs (
+        .clk         ( clock_12    ),
+        .key_strobe  ( key_strobe  ),
+        .key_pressed ( key_pressed ),
+        .key_code    ( key_code    ),
+        .joystick_0  ( joystick_0  ),
+        .joystick_1  ( joystick_1  ),
+        .rotate      ( rotate      ),
+        .orientation ( 2'b10       ),
+        .joyswap     ( 1'b0        ),
+        .oneplayer   ( 1'b1        ),
+        .controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+        .player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+        .player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule 
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_samples.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_samples.vhd
deleted file mode 100644
index 647926bc..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_samples.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity ckong_samples is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of ckong_samples is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"99",X"99",X"99",X"87",X"55",X"68",X"99",X"AB",X"BB",X"BA",X"85",X"33",X"68",X"99",X"9B",X"BB",
-		X"BA",X"74",X"23",X"79",X"99",X"9B",X"CC",X"BB",X"94",X"12",X"59",X"A9",X"9A",X"BC",X"CB",X"94",
-		X"12",X"69",X"99",X"89",X"BC",X"CC",X"B6",X"20",X"27",X"9A",X"99",X"BC",X"CD",X"B5",X"10",X"37",
-		X"BA",X"98",X"9C",X"ED",X"DA",X"30",X"04",X"9B",X"A8",X"9B",X"DE",X"DA",X"50",X"03",X"8B",X"B9",
-		X"79",X"DF",X"FD",X"60",X"00",X"6B",X"C9",X"77",X"BF",X"FF",X"A6",X"00",X"19",X"CB",X"86",X"9D",
-		X"FF",X"D5",X"00",X"06",X"CC",X"96",X"7B",X"FF",X"FB",X"10",X"03",X"AC",X"B7",X"59",X"EF",X"FB",
-		X"60",X"01",X"9C",X"C8",X"68",X"EF",X"FC",X"50",X"01",X"9E",X"C8",X"58",X"DF",X"FD",X"30",X"02",
-		X"9D",X"A5",X"49",X"FF",X"FB",X"40",X"04",X"CC",X"62",X"6F",X"FF",X"F4",X"00",X"2C",X"C5",X"05",
-		X"EF",X"FF",X"C0",X"04",X"D9",X"00",X"BF",X"FF",X"F0",X"01",X"DB",X"00",X"DF",X"FF",X"F0",X"01",
-		X"F9",X"00",X"FF",X"CF",X"F0",X"0F",X"F0",X"0C",X"F6",X"EF",X"B0",X"0F",X"71",X"1F",X"8D",X"FF",
-		X"00",X"F4",X"06",X"F5",X"EF",X"F0",X"2F",X"10",X"9B",X"7F",X"F0",X"0F",X"F0",X"0F",X"6F",X"F6",
-		X"0D",X"F0",X"0F",X"7F",X"F0",X"0F",X"C0",X"5F",X"9F",X"F0",X"0F",X"00",X"FC",X"FF",X"00",X"F9",
-		X"06",X"FF",X"F0",X"0F",X"60",X"BF",X"FF",X"00",X"FC",X"07",X"FF",X"F0",X"0F",X"B0",X"6F",X"FF",
-		X"00",X"F1",X"0A",X"FF",X"F0",X"6F",X"00",X"FF",X"F6",X"0B",X"F0",X"0C",X"FF",X"60",X"8F",X"00",
-		X"CF",X"F7",X"01",X"F0",X"0F",X"FF",X"60",X"0F",X"00",X"FF",X"F7",X"00",X"71",X"0F",X"FF",X"81",
-		X"03",X"43",X"FF",X"FF",X"00",X"05",X"7F",X"FF",X"F0",X"00",X"39",X"EF",X"FF",X"93",X"01",X"69",
-		X"BC",X"FD",X"D9",X"87",X"98",X"6B",X"BB",X"9A",X"9B",X"88",X"87",X"46",X"78",X"76",X"89",X"96",
-		X"88",X"86",X"78",X"87",X"67",X"A6",X"79",X"69",X"99",X"89",X"99",X"88",X"98",X"9B",X"A7",X"77",
-		X"8A",X"9A",X"98",X"86",X"66",X"87",X"8C",X"98",X"56",X"87",X"77",X"99",X"68",X"89",X"79",X"9A",
-		X"96",X"89",X"88",X"A9",X"97",X"79",X"A9",X"88",X"A9",X"78",X"57",X"AA",X"8B",X"74",X"89",X"77",
-		X"7A",X"77",X"76",X"86",X"97",X"68",X"99",X"99",X"87",X"8B",X"84",X"7A",X"98",X"A9",X"89",X"87",
-		X"98",X"9A",X"7B",X"96",X"58",X"B8",X"6C",X"7B",X"68",X"8B",X"8A",X"7A",X"9B",X"75",X"97",X"B8",
-		X"89",X"96",X"86",X"9A",X"98",X"79",X"96",X"97",X"A6",X"77",X"97",X"A7",X"78",X"77",X"9A",X"97",
-		X"B6",X"4B",X"A9",X"87",X"96",X"87",X"79",X"AA",X"75",X"65",X"89",X"87",X"88",X"79",X"79",X"78",
-		X"99",X"C9",X"98",X"BB",X"88",X"66",X"78",X"75",X"74",X"88",X"77",X"58",X"ED",X"AB",X"8B",X"98",
-		X"64",X"87",X"A8",X"74",X"95",X"78",X"43",X"23",X"9C",X"FF",X"EF",X"B1",X"00",X"00",X"BF",X"FF",
-		X"FF",X"B0",X"00",X"00",X"0B",X"FF",X"FF",X"FA",X"00",X"11",X"21",X"4F",X"FF",X"FB",X"C9",X"01",
-		X"82",X"77",X"0F",X"FD",X"F7",X"6B",X"20",X"B4",X"2E",X"62",X"FD",X"8D",X"99",X"D0",X"0C",X"05",
-		X"C2",X"96",X"8C",X"99",X"65",X"E0",X"07",X"0F",X"03",X"B0",X"D7",X"76",X"4B",X"C0",X"54",X"0F",
-		X"0F",X"87",X"E6",X"C5",X"98",X"CD",X"06",X"04",X"63",X"E1",X"F3",X"F6",X"B7",X"8A",X"9F",X"FE",
-		X"6F",X"0F",X"0D",X"3C",X"59",X"7B",X"69",X"A6",X"C8",X"88",X"89",X"79",X"68",X"88",X"8A",X"8A",
-		X"8A",X"69",X"69",X"89",X"89",X"89",X"79",X"79",X"79",X"8A",X"7A",X"59",X"69",X"78",X"70",X"70",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"75",X"A8",X"B8",X"88",X"88",X"78",X"77",X"98",X"97",X"87",
-		X"8C",X"0B",X"3C",X"87",X"B7",X"B7",X"67",X"9B",X"88",X"88",X"97",X"99",X"BB",X"B7",X"00",X"68",
-		X"62",X"4A",X"DF",X"FF",X"FF",X"00",X"1D",X"60",X"2B",X"C2",X"4C",X"DD",X"FF",X"FF",X"00",X"5E",
-		X"00",X"9C",X"40",X"B9",X"9E",X"FF",X"FF",X"00",X"78",X"05",X"B3",X"39",X"73",X"BB",X"FF",X"FF",
-		X"30",X"D8",X"03",X"C5",X"0D",X"45",X"8C",X"FF",X"FF",X"F0",X"0A",X"00",X"D4",X"36",X"92",X"99",
-		X"FF",X"FF",X"FF",X"0F",X"10",X"0F",X"07",X"76",X"59",X"CF",X"FF",X"FF",X"40",X"F0",X"06",X"B0",
-		X"75",X"39",X"9F",X"FF",X"FF",X"F0",X"F2",X"00",X"F0",X"85",X"66",X"C9",X"FF",X"FF",X"F0",X"09",
-		X"00",X"D3",X"26",X"66",X"B8",X"FF",X"FF",X"F0",X"0A",X"00",X"B6",X"18",X"56",X"C9",X"FF",X"FF",
-		X"F0",X"67",X"00",X"A5",X"29",X"47",X"CA",X"FF",X"FF",X"F0",X"B4",X"00",X"96",X"1A",X"48",X"BD",
-		X"FF",X"FF",X"60",X"F0",X"00",X"B4",X"08",X"7A",X"BF",X"FF",X"FF",X"00",X"F0",X"00",X"A6",X"27",
-		X"CD",X"CF",X"FF",X"FF",X"00",X"50",X"00",X"68",X"A9",X"99",X"9A",X"BD",X"EF",X"BA",X"41",X"00",
-		X"24",X"66",X"79",X"CD",X"EF",X"FC",X"B9",X"10",X"00",X"25",X"78",X"8B",X"EF",X"FF",X"FC",X"B4",
-		X"00",X"00",X"34",X"8A",X"AD",X"FF",X"FF",X"BB",X"60",X"00",X"00",X"45",X"9C",X"CE",X"FF",X"FD",
-		X"A6",X"00",X"00",X"03",X"67",X"AE",X"FF",X"FF",X"FB",X"91",X"00",X"00",X"24",X"89",X"CF",X"FF",
-		X"FF",X"CB",X"40",X"00",X"01",X"47",X"9C",X"FF",X"FF",X"FC",X"B5",X"00",X"00",X"03",X"69",X"BE",
-		X"FF",X"FF",X"EC",X"71",X"00",X"00",X"25",X"8B",X"DF",X"FF",X"FF",X"CB",X"20",X"00",X"02",X"47",
-		X"AD",X"FF",X"FF",X"FC",X"B4",X"00",X"00",X"14",X"69",X"CE",X"FF",X"FF",X"FC",X"71",X"00",X"01",
-		X"25",X"7B",X"DE",X"FF",X"FF",X"CA",X"31",X"00",X"12",X"47",X"9C",X"DF",X"FF",X"FE",X"B7",X"11",
-		X"00",X"23",X"57",X"AC",X"DF",X"FF",X"FC",X"94",X"11",X"02",X"35",X"68",X"BC",X"EE",X"EF",X"EB",
-		X"72",X"10",X"13",X"36",X"7A",X"BC",X"EE",X"FF",X"CA",X"62",X"10",X"23",X"57",X"9B",X"CE",X"EE",
-		X"ED",X"B9",X"42",X"11",X"23",X"68",X"AB",X"DE",X"DD",X"CC",X"99",X"42",X"11",X"24",X"69",X"BC",
-		X"DD",X"CC",X"BB",X"98",X"64",X"23",X"35",X"69",X"BC",X"CB",X"AA",X"99",X"88",X"87",X"65",X"56",
-		X"78",X"99",X"A9",X"99",X"99",X"9A",X"BA",X"96",X"54",X"45",X"67",X"89",X"99",X"AA",X"AA",X"BB",
-		X"A8",X"75",X"43",X"45",X"79",X"9A",X"AA",X"64",X"3F",X"FF",X"00",X"0F",X"F0",X"06",X"F8",X"1B",
-		X"FF",X"FF",X"F0",X"09",X"B0",X"0C",X"90",X"0D",X"B9",X"FF",X"FF",X"00",X"F6",X"00",X"F3",X"08",
-		X"E4",X"AF",X"FF",X"FF",X"00",X"F1",X"00",X"F0",X"0F",X"17",X"9B",X"FF",X"FF",X"00",X"F1",X"03",
-		X"C0",X"4F",X"09",X"AA",X"FF",X"FF",X"00",X"F2",X"0B",X"90",X"6F",X"0B",X"97",X"FF",X"FF",X"81",
-		X"F1",X"05",X"A0",X"3F",X"09",X"97",X"FF",X"FF",X"F0",X"F4",X"00",X"F1",X"0F",X"08",X"B7",X"FF",
-		X"FF",X"F0",X"F8",X"01",X"F1",X"0F",X"04",X"D7",X"FF",X"FF",X"F0",X"DA",X"00",X"E4",X"0F",X"01",
-		X"D6",X"FF",X"FF",X"F0",X"4A",X"00",X"F7",X"0F",X"60",X"C7",X"BF",X"FF",X"F0",X"08",X"20",X"EB",
-		X"0B",X"B0",X"9A",X"8F",X"FF",X"F6",X"09",X"C0",X"5D",X"04",X"D4",X"1A",X"BD",X"FF",X"FF",X"06",
-		X"E0",X"0A",X"C0",X"7F",X"04",X"EA",X"FF",X"FF",X"00",X"6B",X"00",X"F4",X"0A",X"82",X"7D",X"FF",
-		X"FF",X"F0",X"0E",X"10",X"2F",X"81",X"88",X"69",X"CF",X"FF",X"F5",X"00",X"66",X"56",X"37",X"98",
-		X"76",X"77",X"DF",X"FF",X"E8",X"10",X"05",X"99",X"A9",X"75",X"69",X"CC",X"CD",X"EE",X"B6",X"00",
-		X"03",X"AC",X"C9",X"64",X"7B",X"DE",X"EC",X"DF",X"A3",X"00",X"16",X"AC",X"C8",X"55",X"7B",X"DC",
-		X"BE",X"FE",X"30",X"05",X"BA",X"43",X"6C",X"93",X"7E",X"FF",X"FF",X"F0",X"06",X"E5",X"00",X"8F",
-		X"60",X"4D",X"CC",X"FF",X"F0",X"00",X"F8",X"00",X"FA",X"06",X"B6",X"8E",X"FF",X"FF",X"00",X"89",
-		X"00",X"8F",X"40",X"C9",X"1A",X"FF",X"FF",X"F0",X"0F",X"A0",X"0F",X"B0",X"5F",X"40",X"CE",X"CF",
-		X"FF",X"00",X"E9",X"00",X"F9",X"07",X"F5",X"0B",X"FC",X"FF",X"F6",X"04",X"C0",X"08",X"D3",X"1D",
-		X"B0",X"6F",X"EE",X"FF",X"F0",X"0F",X"C0",X"0F",X"A0",X"6F",X"40",X"CF",X"CF",X"FF",X"81",X"2E",
-		X"40",X"4F",X"60",X"AF",X"20",X"EF",X"CF",X"FF",X"00",X"7D",X"00",X"9E",X"30",X"CF",X"00",X"EF",
-		X"AF",X"FF",X"20",X"7D",X"00",X"6D",X"71",X"8F",X"60",X"9F",X"CE",X"FF",X"81",X"2D",X"81",X"1E",
-		X"D0",X"3F",X"C0",X"4E",X"DC",X"FF",X"F0",X"09",X"F0",X"0B",X"F5",X"0A",X"F8",X"07",X"ED",X"DF",
-		X"FE",X"00",X"AE",X"10",X"9F",X"61",X"9F",X"90",X"5D",X"CB",X"FF",X"F0",X"08",X"D1",X"07",X"F7",
-		X"18",X"FB",X"13",X"BC",X"9C",X"FF",X"81",X"4C",X"91",X"2B",X"D6",X"4C",X"F7",X"36",X"B9",X"58",
-		X"CC",X"BC",X"C8",X"34",X"89",X"64",X"9B",X"75",X"8B",X"A7",X"79",X"97",X"67",X"98",X"78",X"9A",
-		X"9A",X"C9",X"54",X"79",X"75",X"6A",X"96",X"79",X"A8",X"79",X"A9",X"78",X"89",X"98",X"88",X"88",
-		X"99",X"87",X"88",X"88",X"99",X"87",X"79",X"99",X"87",X"89",X"98",X"87",X"88",X"88",X"70",X"70",
-		X"89",X"98",X"77",X"79",X"99",X"87",X"78",X"A9",X"87",X"78",X"A9",X"87",X"79",X"A9",X"77",X"79",
-		X"B8",X"77",X"79",X"A9",X"77",X"77",X"9A",X"87",X"77",X"79",X"B9",X"66",X"88",X"9B",X"B8",X"55",
-		X"78",X"99",X"BB",X"96",X"44",X"69",X"9A",X"CD",X"B8",X"43",X"46",X"89",X"9B",X"DE",X"B7",X"32",
-		X"35",X"89",X"99",X"AD",X"FF",X"DB",X"97",X"67",X"87",X"53",X"33",X"33",X"46",X"50",X"00",X"6D",
-		X"FC",X"7F",X"FF",X"F5",X"00",X"28",X"C9",X"9F",X"FF",X"71",X"01",X"AC",X"38",X"FF",X"F0",X"00",
-		X"AE",X"75",X"FF",X"E0",X"00",X"7D",X"76",X"FF",X"F2",X"00",X"7F",X"D6",X"FF",X"F4",X"00",X"6C",
-		X"99",X"FF",X"71",X"00",X"99",X"5E",X"FF",X"20",X"08",X"C5",X"8F",X"F8",X"00",X"4D",X"86",X"FF",
-		X"90",X"00",X"C7",X"6F",X"FC",X"00",X"0C",X"87",X"FF",X"60",X"05",X"C5",X"BF",X"F0",X"00",X"B9",
-		X"6F",X"FD",X"00",X"4F",X"78",X"FF",X"10",X"0C",X"9A",X"FF",X"40",X"09",X"B9",X"FF",X"B0",X"07",
-		X"C8",X"DF",X"F0",X"04",X"E9",X"EF",X"F0",X"03",X"E6",X"FF",X"F0",X"08",X"F5",X"FF",X"F0",X"0D",
-		X"E5",X"FF",X"F0",X"0F",X"95",X"FF",X"50",X"0F",X"30",X"FF",X"00",X"4F",X"03",X"FF",X"00",X"FF",
-		X"0D",X"FF",X"00",X"F6",X"0F",X"FF",X"04",X"F0",X"0F",X"FC",X"0F",X"F0",X"4F",X"FD",X"0D",X"81",
-		X"FF",X"FC",X"04",X"90",X"FF",X"EC",X"00",X"E0",X"CF",X"F4",X"00",X"20",X"FF",X"F3",X"00",X"02",
-		X"EF",X"F5",X"09",X"05",X"FF",X"F6",X"0C",X"00",X"FF",X"F6",X"0C",X"09",X"9F",X"FB",X"0C",X"00",
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-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_sound.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_sound.vhd
index 180470e5..024ca68e 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_sound.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_sound.vhd	
@@ -6,7 +6,8 @@ use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
 entity ckong_sound is
 port	(
-	cpu_clock    : in std_logic;
+	clock_12     : in std_logic;
+	cpu_clock_en : in std_logic;
 	cpu_addr     : in std_logic_vector(15 downto 0);
 	cpu_data     : in std_logic_vector( 7 downto 0);
 	cpu_iorq_n   : in std_logic;
@@ -23,6 +24,8 @@ architecture struct of ckong_sound is
 signal hdiv         : std_logic_vector(1 downto 0);
 signal clock_1_5mhz : std_logic; -- 1.50Mhz
 signal clock_750khz : std_logic; -- 0.75MHz
+signal clock_1_5mhz_en : std_logic; -- 1.50Mhz
+signal clock_750khz_en : std_logic; -- 0.75MHz
 
 signal ym_2149_audio : std_logic_vector(7 downto 0);
 
@@ -42,12 +45,15 @@ signal sample_data     : std_logic_vector(3 downto 0);
 
 begin
 
-clock_1_5mhz <= hdiv(0);
-clock_750khz <= hdiv(1);
+--clock_1_5mhz <= hdiv(0);
+--clock_750khz <= hdiv(1);
 
-process(cpu_clock)
+clock_1_5mhz_en <= cpu_clock_en and hdiv(0);
+clock_750khz_en <= '1' when cpu_clock_en = '1' and hdiv="01" else '0';
+
+process(clock_12, cpu_clock_en)
 begin
-	if falling_edge(cpu_clock) then
+	if rising_edge(clock_12) and cpu_clock_en = '1' then
 
 		if hdiv = "11" then
 			hdiv <= "00";
@@ -76,9 +82,9 @@ end process;
 
 -- Sample machine
 
-process(clock_750khz)
+process(clock_12, clock_750khz_en)
 begin
-	if rising_edge(clock_750khz) then
+	if rising_edge(clock_12) and clock_750khz_en = '1' then
 		if frequency_cnt = "11111111" then
 			frequency_cnt   <= frequency_div;
 			frequency_tick  <= '1';
@@ -114,7 +120,7 @@ sound_sample <= std_logic_vector(( "0000" & unsigned(ym_2149_audio) & "0000") +
 sample_rom : entity work.ckong_samples
 port map (
 	addr  => sample_rom_addr,
-	clk   => cpu_clock, 
+	clk   => clock_12, 
 	data  => sound_data
 );
 
@@ -142,9 +148,9 @@ port map (
 	O_IOB           => sample_start2, --: out std_logic_vector(7 downto 0);
 	O_IOB_OE_L      => open,          --: out std_logic;
 
-	ENA             => '1',           --: in  std_logic; -- clock enable for higher speed operation
+	ENA             => clock_1_5mhz_en,--: in  std_logic; -- clock enable for higher speed operation
 	RESET_L         => '1',           --: in  std_logic;
-	CLK             => clock_1_5mhz   --: in  std_logic  -- note 6 Mhz!
+	CLK             => clock_12       --: in  std_logic
 );
 
 end architecture;
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_big_sprite_palette.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_palette.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_big_sprite_palette.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit0.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_big_sprite_tile_bit0.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit0.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_big_sprite_tile_bit0.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit1.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_big_sprite_tile_bit1.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit1.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_big_sprite_tile_bit1.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_palette.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_palette.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_palette.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_program.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_program.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_program.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_program.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_samples.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_samples.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CannonBall_MiST/rtl/rom/rom/ckong_samples.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_samples.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_tile_bit0.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_tile_bit0.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_tile_bit0.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_tile_bit0.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_tile_bit1.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_tile_bit1.vhd
similarity index 100%
rename from Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_tile_bit1.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/rom/ckong_tile_bit1.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/video_gen.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/video_gen.vhd
index b6da7119..279e4842 100644
--- a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/video_gen.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/video_gen.vhd	
@@ -20,7 +20,8 @@ port(
 	x_pixel     : out std_logic_vector(2 downto 0);
 	y_pixel     : out std_logic_vector(2 downto 0);
 
-	cpu_clock   : out std_logic
+	cpu_clock   : out std_logic;
+	cpu_clock_en: out std_logic
 );
 end video_gen;
 
@@ -40,6 +41,7 @@ signal enable_clk : std_logic := '0';
 begin
 
 cpu_clock  <= not hcnt(0);
+cpu_clock_en <= ena_pixel and hcnt(0);
 is_sprite  <= not hcnt(8);
 sprite     <= std_logic_vector(hcnt(6 downto 4));
 x_tile     <= std_logic_vector(hcnt(7 downto 3));
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/RiverPatrol.qsf b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/RiverPatrol.qsf
index 313466b3..7a834b67 100644
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/RiverPatrol.qsf	
+++ b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/RiverPatrol.qsf	
@@ -40,7 +40,7 @@
 # Project-Wide Assignments
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
@@ -156,14 +156,9 @@ set_global_assignment -name VHDL_FILE rtl/rom/cclimber_palette.vhd
 set_global_assignment -name VHDL_FILE rtl/rom/cclimber_big_sprite_tile_bit1.vhd
 set_global_assignment -name VHDL_FILE rtl/rom/cclimber_big_sprite_tile_bit0.vhd
 set_global_assignment -name VHDL_FILE rtl/rom/cclimber_big_sprite_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
 set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
 set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
 set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
 set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/RiverPatrol.sdc b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/RiverPatrol.sdc
new file mode 100644
index 00000000..fc76f46c
--- /dev/null
+++ b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/RiverPatrol.sdc	
@@ -0,0 +1,134 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk   "pll|altpll_component|auto_generated|pll1|clk[0]"
+set vid_clk   "pll|altpll_component|auto_generated|pll1|clk[1]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $vid_clk]  1.000 [get_ports {VGA_*}]
+
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/RiverPatrol_mist.sv b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/RiverPatrol_mist.sv
index 1df3b1ee..fac33bc0 100644
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/RiverPatrol_mist.sv	
+++ b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/RiverPatrol_mist.sv	
@@ -20,16 +20,21 @@ module RiverPatrol_mist (
 
 localparam CONF_STR = {
 	"RiverPat.;;",
+	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.25.",`BUILD_DATE
+	"O5,Blend,Off,On;",
+	"T0,Reset;",
+	"V,v1.26.",`BUILD_DATE
 };
 
+wire       rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire       blend = status[5];
 
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-wire clock_24, clock_12, clock_6;
+wire clock_24, clock_12;
 pll pll(
 	.inclk0(CLOCK_27),
 	.c0(clock_24),
@@ -43,8 +48,10 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
 wire [15:0] audio;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
 wire hs, vs;
 wire hb, vb;
 wire blankn = ~(hb | vb);
@@ -53,7 +60,7 @@ wire [1:0] b;
 
 crazy_climber crazy_climber (
 	.clock_12(clock_12),
-	.reset(status[0] | status[6] | buttons[1]),
+	.reset(status[0] | buttons[1]),
 	.video_r(r),
 	.video_g(g),
 	.video_b(b),
@@ -62,18 +69,18 @@ crazy_climber crazy_climber (
 	.video_hs(hs),
 	.video_vs(vs),
 	.audio_out(audio),
-	.start2(btn_two_players),
-	.start1(btn_one_player),
-	.coin1(btn_coin),
-	.right1(m_right),
-	.left1(m_left),
-	.fire1(m_fire),
+	.start2(m_two_players),
+	.start1(m_one_player),
+	.coin1(m_coin1),
+	.right1(m_right2),
+	.left1(m_left2),
+	.fire1(m_fire2A),
 	.right2(m_right),
 	.left2(m_left),
-	.fire2(m_fire)
+	.fire2(m_fireA)
 );
 
-mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
+mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
 	.clk_sys(clock_24),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
@@ -88,8 +95,10 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.ce_divider(0),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
+	.ce_divider(1'b1),
+	.rotate({1'b1,rotate}),
+	.scanlines(scanlines),
+	.blend(blend),
 	.scandoubler_disable(scandoublerD),
 	.ypbpr(ypbpr)
 	);
@@ -97,7 +106,7 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
 user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
 user_io(
-	.clk_sys        (clock_24       ),
+	.clk_sys        (clock_12       ),
 	.conf_str       (CONF_STR       ),
 	.SPI_CLK        (SPI_SCK        ),
 	.SPI_SS_IO      (CONF_DATA0     ),
@@ -116,40 +125,32 @@ user_io(
 	);
 
 dac #(
-	.C_bits(8))
+	.C_bits(16))
 dac(
-	.clk_i(clock_24),
+	.clk_i(clock_12),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
-wire       key_pressed;
-wire [7:0] key_code;
-wire       key_strobe;
-
-always @(posedge clock_24) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h6B: btn_left      		<= key_pressed; // left
-			'h74: btn_right       	<= key_pressed; // right
-			'h76: btn_coin				<= key_pressed; // ESC
-			'h05: btn_one_player   	<= key_pressed; // F1
-			'h06: btn_two_players  	<= key_pressed; // F2
-			'h29: btn_fire1   		<= key_pressed; // Space
-		endcase
-	end
-end
-
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+ 
+arcade_inputs inputs (
+        .clk         ( clock_12    ),
+        .key_strobe  ( key_strobe  ),
+        .key_pressed ( key_pressed ),
+        .key_code    ( key_code    ),
+        .joystick_0  ( joystick_0  ),
+        .joystick_1  ( joystick_1  ),
+        .rotate      ( rotate      ),
+        .orientation ( 2'b10       ),
+        .joyswap     ( 1'b0        ),
+        .oneplayer   ( 1'b1        ),
+        .controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+        .player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+        .player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index 398fa0df..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1073 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed wait and halt
---
---	0211 : Fixed Refresh addition and IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---	0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---	0237 : Changed 8080 I/O address output, added IntE output
---
---	0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---	0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---	0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F			: std_logic_vector(7 downto 0);
-	signal Ap, Fp			: std_logic_vector(7 downto 0);
-	signal I				: std_logic_vector(7 downto 0);
-	signal R				: unsigned(7 downto 0);
-	signal SP, PC			: unsigned(15 downto 0);
-	signal RegDIH			: std_logic_vector(7 downto 0);
-	signal RegDIL			: std_logic_vector(7 downto 0);
-	signal RegBusA			: std_logic_vector(15 downto 0);
-	signal RegBusB			: std_logic_vector(15 downto 0);
-	signal RegBusC			: std_logic_vector(15 downto 0);
-	signal RegAddrA_r		: std_logic_vector(2 downto 0);
-	signal RegAddrA			: std_logic_vector(2 downto 0);
-	signal RegAddrB_r		: std_logic_vector(2 downto 0);
-	signal RegAddrB			: std_logic_vector(2 downto 0);
-	signal RegAddrC			: std_logic_vector(2 downto 0);
-	signal RegWEH			: std_logic;
-	signal RegWEL			: std_logic;
-	signal Alternate		: std_logic;
-
-	-- Help Registers
-	signal TmpAddr			: std_logic_vector(15 downto 0);	-- Temporary address register
-	signal IR				: std_logic_vector(7 downto 0);		-- Instruction register
-	signal ISet				: std_logic_vector(1 downto 0);		-- Instruction set selector
-	signal RegBusA_r		: std_logic_vector(15 downto 0);
-
-	signal ID16				: signed(15 downto 0);
-	signal Save_Mux			: std_logic_vector(7 downto 0);
-
-	signal TState			: unsigned(2 downto 0);
-	signal MCycle			: std_logic_vector(2 downto 0);
-	signal IntE_FF1			: std_logic;
-	signal IntE_FF2			: std_logic;
-	signal Halt_FF			: std_logic;
-	signal BusReq_s			: std_logic;
-	signal BusAck			: std_logic;
-	signal ClkEn			: std_logic;
-	signal NMI_s			: std_logic;
-	signal INT_s			: std_logic;
-	signal IStatus			: std_logic_vector(1 downto 0);
-
-	signal DI_Reg			: std_logic_vector(7 downto 0);
-	signal T_Res			: std_logic;
-	signal XY_State			: std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M		: std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch	: std_logic;
-	signal XY_Ind			: std_logic;
-	signal No_BTR			: std_logic;
-	signal BTR_r			: std_logic;
-	signal Auto_Wait		: std_logic;
-	signal Auto_Wait_t1		: std_logic;
-	signal Auto_Wait_t2		: std_logic;
-	signal IncDecZ			: std_logic;
-
-	-- ALU signals
-	signal BusB				: std_logic_vector(7 downto 0);
-	signal BusA				: std_logic_vector(7 downto 0);
-	signal ALU_Q			: std_logic_vector(7 downto 0);
-	signal F_Out			: std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r	: std_logic_vector(4 downto 0);
-	signal Arith16_r		: std_logic;
-	signal Z16_r			: std_logic;
-	signal ALU_Op_r			: std_logic_vector(3 downto 0);
-	signal Save_ALU_r		: std_logic;
-	signal PreserveC_r		: std_logic;
-	signal MCycles			: std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d		: std_logic_vector(2 downto 0);
-	signal TStates			: std_logic_vector(2 downto 0);
-	signal IntCycle			: std_logic;
-	signal NMICycle			: std_logic;
-	signal Inc_PC			: std_logic;
-	signal Inc_WZ			: std_logic;
-	signal IncDec_16		: std_logic_vector(3 downto 0);
-	signal Prefix			: std_logic_vector(1 downto 0);
-	signal Read_To_Acc		: std_logic;
-	signal Read_To_Reg		: std_logic;
-	signal Set_BusB_To		: std_logic_vector(3 downto 0);
-	signal Set_BusA_To		: std_logic_vector(3 downto 0);
-	signal ALU_Op			: std_logic_vector(3 downto 0);
-	signal Save_ALU			: std_logic;
-	signal PreserveC		: std_logic;
-	signal Arith16			: std_logic;
-	signal Set_Addr_To		: std_logic_vector(2 downto 0);
-	signal Jump				: std_logic;
-	signal JumpE			: std_logic;
-	signal JumpXY			: std_logic;
-	signal Call				: std_logic;
-	signal RstP				: std_logic;
-	signal LDZ				: std_logic;
-	signal LDW				: std_logic;
-	signal LDSPHL			: std_logic;
-	signal IORQ_i			: std_logic;
-	signal Special_LD		: std_logic_vector(2 downto 0);
-	signal ExchangeDH		: std_logic;
-	signal ExchangeRp		: std_logic;
-	signal ExchangeAF		: std_logic;
-	signal ExchangeRS		: std_logic;
-	signal I_DJNZ			: std_logic;
-	signal I_CPL			: std_logic;
-	signal I_CCF			: std_logic;
-	signal I_SCF			: std_logic;
-	signal I_RETN			: std_logic;
-	signal I_BT				: std_logic;
-	signal I_BC				: std_logic;
-	signal I_BTR			: std_logic;
-	signal I_RLD			: std_logic;
-	signal I_RRD			: std_logic;
-	signal I_INRC			: std_logic;
-	signal SetDI			: std_logic;
-	signal SetEI			: std_logic;
-	signal IMode			: std_logic_vector(1 downto 0);
-	signal Halt				: std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR => IR,
-			ISet => ISet,
-			MCycle => MCycle,
-			F => F,
-			NMICycle => NMICycle,
-			IntCycle => IntCycle,
-			MCycles => MCycles_d,
-			TStates => TStates,
-			Prefix => Prefix,
-			Inc_PC => Inc_PC,
-			Inc_WZ => Inc_WZ,
-			IncDec_16 => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op => ALU_Op,
-			Save_ALU => Save_ALU,
-			PreserveC => PreserveC,
-			Arith16 => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ => IORQ_i,
-			Jump => Jump,
-			JumpE => JumpE,
-			JumpXY => JumpXY,
-			Call => Call,
-			RstP => RstP,
-			LDZ => LDZ,
-			LDW => LDW,
-			LDSPHL => LDSPHL,
-			Special_LD => Special_LD,
-			ExchangeDH => ExchangeDH,
-			ExchangeRp => ExchangeRp,
-			ExchangeAF => ExchangeAF,
-			ExchangeRS => ExchangeRS,
-			I_DJNZ => I_DJNZ,
-			I_CPL => I_CPL,
-			I_CCF => I_CCF,
-			I_SCF => I_SCF,
-			I_RETN => I_RETN,
-			I_BT => I_BT,
-			I_BC => I_BC,
-			I_BTR => I_BTR,
-			I_RLD => I_RLD,
-			I_RRD => I_RRD,
-			I_INRC => I_INRC,
-			SetDI => SetDI,
-			SetEI => SetEI,
-			IMode => IMode,
-			Halt => Halt,
-			NoRead => NoRead,
-			Write => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16 => Z16_r,
-			ALU_Op => ALU_Op_r,
-			IR => IR(5 downto 0),
-			ISet => ISet,
-			BusA => BusA,
-			BusB => BusB,
-			F_In => F,
-			Q => ALU_Q,
-			F_Out => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 and Auto_Wait_t1 = '0' then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if T_Res = '1' then
-				Auto_Wait_t1 <= '0';
-			else
-				Auto_Wait_t1 <= Auto_Wait or IORQ_i;
-			end if;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
-						(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 86fddce7..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0238 : Fixed zero flag for 16 bit SBC and ADC
---
---	0240 : Added GB operations
---
---	0242 : Cleanup
---
---	0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A : std_logic_vector;
-					B : std_logic_vector;
-					Sub : std_logic;
-					Carry_In : std_logic;
-					signal Res : out std_logic_vector;
-					signal Carry : out std_logic) is
-		variable B_i		: unsigned(A'length - 1 downto 0);
-		variable Res_i		: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i := unsigned(B);
-		end if;
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal	UseCarry		: std_logic;
-	signal	Carry7_v		: std_logic;
-	signal	Overflow_v		: std_logic;
-	signal	HalfCarry_v		: std_logic;
-	signal	Carry_v			: std_logic;
-	signal	Q_v				: std_logic_vector(7 downto 0);
-
-	signal	BitMask			: std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-									"00000010" when "001",
-									"00000100" when "010",
-									"00001000" when "011",
-									"00010000" when "100",
-									"00100000" when "101",
-									"01000000" when "110",
-									"10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);	-- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 4cc30f35..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1934 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0235 : Added IM 2 fix by Mike Johnson
---
---	0238 : Added NoRead signal
---
---	0238b: Fixed instruction timing for POP and DJNZ
---
---	0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
---	0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
---	constant aNone	: std_logic_vector(2 downto 0) := "000";
---	constant aXY	: std_logic_vector(2 downto 0) := "001";
---	constant aIOA	: std_logic_vector(2 downto 0) := "010";
---	constant aSP	: std_logic_vector(2 downto 0) := "011";
---	constant aBC	: std_logic_vector(2 downto 0) := "100";
---	constant aDE	: std_logic_vector(2 downto 0) := "101";
---	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---	Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To	<= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To	<= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";	-- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n	-- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To	<= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---	CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-					Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others =>
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---	ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)	<= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index ac7d34da..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,208 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80s.vhd
deleted file mode 100644
index 5b612110..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/T80/T80s.vhd	
+++ /dev/null
@@ -1,190 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed read with wait
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0236 : Added T2Write generic
---
---	0237 : Fixed T2Write with wait state
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80s is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
-		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80s;
-
-architecture rtl of T80s is
-
-	signal CEN			: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => IOWait)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_n,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => RESET_n,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK_n,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			if MCycle = "001" then
-				if TState = "001" or (TState = "010" and Wait_n = '0') then
-					RD_n <= not IntCycle_n;
-					MREQ_n <= not IntCycle_n;
-					IORQ_n <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					MREQ_n <= '0';
-				end if;
-			else
-				if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
-					RD_n <= '0';
-					IORQ_n <= not IORQ;
-					MREQ_n <= IORQ;
-				end if;
-				if T2Write = 0 then
-					if TState = "010" and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				end if;
-			end if;
-			if TState = "010" and Wait_n = '1' then
-				DI_Reg <= DI;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/crazy_climber.vhd b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/crazy_climber.vhd
index 34efa910..479b5d70 100644
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/crazy_climber.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/crazy_climber.vhd	
@@ -116,6 +116,7 @@ signal video_mux              : std_logic_vector(7 downto 0);
 
 -- Z80 interface 
 signal cpu_clock  : std_logic;
+signal cpu_clock_en: std_logic;
 signal cpu_wr_n   : std_logic;
 signal cpu_addr   : std_logic_vector(15 downto 0);
 signal cpu_do     : std_logic_vector(7 downto 0);
@@ -226,7 +227,7 @@ video_vs    <= vsync;
 ------------------
 player1 <= right1 & left1 & "00000" & fire1;
 player2 <= right2 & left2 & "00000" & fire2;
-coins <=  ("0001" & start2 & start1 & '0' & coin1); -- upright cabinet
+coins <=  ("1111" & start2 & start1 & '0' & coin1); -- upright cabinet
 
 -----------------------
 -- cpu write addressing
@@ -246,13 +247,13 @@ reg6_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto
 ---------------------------
 -- enable/disable interrupt
 ---------------------------
-process (cpu_clock)
+process (clock_12)
 begin
-	if falling_edge(cpu_clock) then
-		if cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then
+	if rising_edge(clock_12) then
+		if cpu_clock_en = '1' and cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then
 			raz_int_n <= cpu_do(0);
 		end if;
-end if;
+	end if;
 end process;
 
 -------------------------------
@@ -658,7 +659,8 @@ port map (
   x_pixel    => x_pixel,
   y_pixel    => y_pixel,
 	
-  cpu_clock  => cpu_clock
+  cpu_clock  => cpu_clock,
+  cpu_clock_en=> cpu_clock_en
 );
 
 -- sprite palette rom
@@ -678,11 +680,12 @@ port map (
 );
 
 -- Z80
-Z80 : entity work.T80s
+Z80 : entity work.T80se
 generic map(Mode => 0, T2Write => 1, IOWait => 1)
 port map(
   RESET_n => reset_n,
-  CLK_n   => cpu_clock,
+  CLK_n   => clock_12,
+  CLKEN   => cpu_clock_en,
   WAIT_n  => '1',
   INT_n   => '1',
   NMI_n   => cpu_int_n,
@@ -802,7 +805,8 @@ port map (
 -- sound
 cclimber_sound : entity work.crazy_climber_sound
 port map(
-  cpu_clock    => cpu_clock,
+  clock_12     => clock_12,
+  cpu_clock_en => cpu_clock_en,
   cpu_addr     => cpu_addr,
   cpu_data     => cpu_do,
   cpu_iorq_n   => cpu_iorq_n,
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/crazy_climber_sound.vhd b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/crazy_climber_sound.vhd
index 5ce5478d..29458bf5 100644
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/crazy_climber_sound.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/crazy_climber_sound.vhd	
@@ -6,7 +6,8 @@ use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
 entity crazy_climber_sound is
 port	(
-	cpu_clock    : in std_logic;
+	clock_12     : in std_logic;
+	cpu_clock_en : in std_logic;
 	cpu_addr     : in std_logic_vector(15 downto 0);
 	cpu_data     : in std_logic_vector( 7 downto 0);
 	cpu_iorq_n   : in std_logic;
@@ -23,6 +24,8 @@ architecture struct of crazy_climber_sound is
 signal hdiv         : std_logic_vector(1 downto 0);
 signal clock_1_5mhz : std_logic; -- 1.50Mhz
 signal clock_750khz : std_logic; -- 0.75MHz
+signal clock_1_5mhz_en : std_logic; -- 1.50Mhz
+signal clock_750khz_en : std_logic; -- 0.75MHz
 
 signal ym_2149_audio : std_logic_vector(7 downto 0);
 
@@ -42,12 +45,15 @@ signal sample_data     : std_logic_vector(3 downto 0);
 
 begin
 
-clock_1_5mhz <= hdiv(0);
-clock_750khz <= hdiv(1);
+--clock_1_5mhz <= hdiv(0);
+--clock_750khz <= hdiv(1);
 
-process(cpu_clock)
+clock_1_5mhz_en <= cpu_clock_en and hdiv(0);
+clock_750khz_en <= '1' when cpu_clock_en = '1' and hdiv="01" else '0';
+
+process(clock_12, cpu_clock_en)
 begin
-	if falling_edge(cpu_clock) then
+	if rising_edge(clock_12) and cpu_clock_en = '1' then
 
 		if hdiv = "11" then
 			hdiv <= "00";
@@ -76,9 +82,9 @@ end process;
 
 -- Sample machine
 
-process(clock_750khz)
+process(clock_12, clock_750khz_en)
 begin
-	if rising_edge(clock_750khz) then
+	if rising_edge(clock_12) and clock_750khz_en = '1' then
 		if frequency_cnt = "11111111" then
 			frequency_cnt   <= frequency_div;
 			frequency_tick  <= '1';
@@ -104,9 +110,8 @@ begin
 	end if; 
 end process;
 
-
 sound_sample <= std_logic_vector( unsigned(ym_2149_audio) & unsigned(ym_2149_audio));
-
+------
 
 ym2149 : entity work.ym2149
 port map (
@@ -132,9 +137,9 @@ port map (
 	O_IOB           => sample_start2, --: out std_logic_vector(7 downto 0);
 	O_IOB_OE_L      => open,          --: out std_logic;
 
-	ENA             => '1',           --: in  std_logic; -- clock enable for higher speed operation
+	ENA             => clock_1_5mhz_en,--: in  std_logic; -- clock enable for higher speed operation
 	RESET_L         => '1',           --: in  std_logic;
-	CLK             => clock_1_5mhz   --: in  std_logic  -- note 6 Mhz!
+	CLK             => clock_12       --: in  std_logic
 );
 
 end architecture;
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/video_gen.vhd b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/video_gen.vhd
index 2abe45d1..94c0dcd0 100644
--- a/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/video_gen.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/River Patrol_MiST/rtl/video_gen.vhd	
@@ -11,8 +11,8 @@ port(
 	hsync       : out std_logic;
 	vsync       : out std_logic;
 	csync       : out std_logic;
-	hblank       : out std_logic;
-	vblank       : out std_logic;
+	hblank      : out std_logic;
+	vblank      : out std_logic;
 
 	is_sprite   : out std_logic;
 	sprite      : out std_logic_vector(2 downto 0);
@@ -21,7 +21,8 @@ port(
 	x_pixel     : out std_logic_vector(2 downto 0);
 	y_pixel     : out std_logic_vector(2 downto 0);
 
-	cpu_clock   : out std_logic
+	cpu_clock   : out std_logic;
+	cpu_clock_en: out std_logic
 );
 end video_gen;
 
@@ -39,6 +40,7 @@ signal enable_clk : std_logic := '0';
 begin
 
 cpu_clock  <= not hcnt(0);
+cpu_clock_en <= ena_pixel and hcnt(0);
 is_sprite  <= not hcnt(8);
 sprite     <= std_logic_vector(hcnt(6 downto 4));
 x_tile     <= std_logic_vector(hcnt(7 downto 3));
@@ -113,14 +115,14 @@ begin
 			end if;
 
 			if    vcnt = 511 then vsync <= '0';
-			elsif vcnt = 250 then vsync <= '1';--
+			elsif vcnt = 250 then vsync <= '1';
 			end if;    
 
-			if    hcnt = (127+8+1) then hblank <= '1'; -- +8 = retard du shift_register + 1 pixel--
-			elsif hcnt = (255+8+1) then hblank <= '0'; -- +8 = retard du shift_register + 1 pixel--
+			if    hcnt = (127+8+1) then hblank <= '1'; -- +8 = retard du shift_register + 1 pixel
+			elsif hcnt = (255+8+1) then hblank <= '0'; -- +8 = retard du shift_register + 1 pixel
 			end if;    
 
-			if    vcnt = (495+1+0) then vblank <= '1';
+			if    vcnt = (495+1+1) then vblank <= '1';
 			elsif vcnt = (271+1+1) then vblank <= '0';
 			end if;   
 
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.qsf b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.qsf
index fb176537..bf3f39d6 100644
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.qsf	
+++ b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.qsf	
@@ -40,7 +40,7 @@
 # Project-Wide Assignments
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
@@ -156,14 +156,9 @@ set_global_assignment -name VHDL_FILE rtl/rom/silverland_big_sprite_tile_bit1.vh
 set_global_assignment -name VHDL_FILE rtl/rom/silverland_big_sprite_tile_bit0.vhd
 set_global_assignment -name VHDL_FILE rtl/rom/silverland_big_sprite_palette.vhd
 set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
 set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
 set_global_assignment -name VHDL_FILE rtl/ym_2149_linmix.vhd
 set_global_assignment -name VERILOG_FILE rtl/pll.v
 set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.sdc b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.sdc
new file mode 100644
index 00000000..fc76f46c
--- /dev/null
+++ b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.sdc	
@@ -0,0 +1,134 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk   "pll|altpll_component|auto_generated|pll1|clk[0]"
+set vid_clk   "pll|altpll_component|auto_generated|pll1|clk[1]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $vid_clk]  1.000 [get_ports {VGA_*}]
+
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.srf b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.srf
deleted file mode 100644
index f55bfbb9..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/SilverLand.srf	
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "" "" "" "VHDL Process Statement warning at ym_2149_linmix.vhd(315): signal \"ioa_inreg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } {  } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred dual-clock RAM node \"video_mixer:video_mixer\|osd:osd\|osd_buffer_rtl_0\" from synchronous design logic.  The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." {  } {  } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" {  } {  } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "VHDL Process Statement warning at ym_2149_linmix.vhd(320): signal \"iob_inreg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } {  } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL information at scandoubler.sv(102): always construct contains both blocking and non-blocking assignments" {  } {  } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "VHDL Process Statement warning at ym_2149_linmix.vhd(469): signal \"reg\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } {  } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." {  } {  } 0 13004 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/SilverLand_mist.sv b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/SilverLand_mist.sv
index 5e1cd76c..66825b81 100644
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/SilverLand_mist.sv	
+++ b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/SilverLand_mist.sv	
@@ -16,16 +16,20 @@ module SilverLand_mist (
 	input         CLOCK_27
 );
 
-`include "rtl\build_id.sv" 
+`include "rtl\build_id.v" 
 
 localparam CONF_STR = {
-	"Silver Land;;",
+	"SilverL;;",
+	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"O5,Pause,Off,On;",
-	"T6,Reset;",
-	"V,v1.25.",`BUILD_DATE
+	"O5,Blend,Off,On;",
+	"T0,Reset;",
+	"V,v1.26.",`BUILD_DATE
 };
 
+wire       rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire       blend = status[5];
 
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
@@ -44,8 +48,10 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
-wire [7:0] audio;
+wire  [7:0] audio;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
 wire hs, vs;
 wire hb, vb;
 wire blankn = ~(hb | vb);
@@ -54,8 +60,7 @@ wire [1:0] b;
 
 crazy_climber crazy_climber (
 	.clock_12(clock_12),
-	.pause(status[5]),
-	.reset(status[0] | status[6] | buttons[1]),
+	.reset(status[0] | buttons[1]),
 	.video_r(r),
 	.video_g(g),
 	.video_b(b),
@@ -64,18 +69,18 @@ crazy_climber crazy_climber (
 	.video_hs(hs),
 	.video_vs(vs),
 	.audio_out(audio),
-	.start2(btn_two_players),
-	.start1(btn_one_player),
-	.coin1(btn_coin),
-	.right1(~m_right),
-	.left1(~m_left),
-	.fire1(m_fire),
+	.start2(m_two_players),
+	.start1(m_one_player),
+	.coin1(m_coin1),
+	.right1(m_right2),
+	.left1(m_left2),
+	.fire1(m_fire2A),
 	.right2(m_right),
 	.left2(m_left),
-	.fire2(m_fire)
+	.fire2(m_fireA)
 );
 
-mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
+mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
 	.clk_sys(clock_24),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
@@ -90,8 +95,10 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.ce_divider(0),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
+	.ce_divider(1'b1),
+	.rotate({1'b1,rotate}),
+	.scanlines(scanlines),
+	.blend(blend),
 	.scandoubler_disable(scandoublerD),
 	.ypbpr(ypbpr)
 	);
@@ -120,38 +127,30 @@ user_io(
 dac #(
 	.C_bits(8))
 dac(
-	.clk_i(clock_24),
+	.clk_i(clock_12),
 	.res_n_i(1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 
-wire m_left   = btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_fire1 = 0;
-reg btn_coin  = 0;
-wire       key_pressed;
-wire [7:0] key_code;
-wire       key_strobe;
-
-always @(posedge clock_24) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h6B: btn_left      		<= key_pressed; // left
-			'h74: btn_right       	<= key_pressed; // right
-			'h76: btn_coin				<= key_pressed; // ESC
-			'h05: btn_one_player   	<= key_pressed; // F1
-			'h06: btn_two_players  	<= key_pressed; // F2
-			'h29: btn_fire1   		<= key_pressed; // Space
-		endcase
-	end
-end
-
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+ 
+arcade_inputs inputs (
+        .clk         ( clock_12    ),
+        .key_strobe  ( key_strobe  ),
+        .key_pressed ( key_pressed ),
+        .key_code    ( key_code    ),
+        .joystick_0  ( joystick_0  ),
+        .joystick_1  ( joystick_1  ),
+        .rotate      ( rotate      ),
+        .orientation ( 2'b10       ),
+        .joyswap     ( 1'b0        ),
+        .oneplayer   ( 1'b1        ),
+        .controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+        .player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+        .player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
 
 endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80.vhd
deleted file mode 100644
index 398fa0df..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80.vhd	
+++ /dev/null
@@ -1,1073 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed wait and halt
---
---	0211 : Fixed Refresh addition and IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---	0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---	0237 : Changed 8080 I/O address output, added IntE output
---
---	0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---	0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---	0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F			: std_logic_vector(7 downto 0);
-	signal Ap, Fp			: std_logic_vector(7 downto 0);
-	signal I				: std_logic_vector(7 downto 0);
-	signal R				: unsigned(7 downto 0);
-	signal SP, PC			: unsigned(15 downto 0);
-	signal RegDIH			: std_logic_vector(7 downto 0);
-	signal RegDIL			: std_logic_vector(7 downto 0);
-	signal RegBusA			: std_logic_vector(15 downto 0);
-	signal RegBusB			: std_logic_vector(15 downto 0);
-	signal RegBusC			: std_logic_vector(15 downto 0);
-	signal RegAddrA_r		: std_logic_vector(2 downto 0);
-	signal RegAddrA			: std_logic_vector(2 downto 0);
-	signal RegAddrB_r		: std_logic_vector(2 downto 0);
-	signal RegAddrB			: std_logic_vector(2 downto 0);
-	signal RegAddrC			: std_logic_vector(2 downto 0);
-	signal RegWEH			: std_logic;
-	signal RegWEL			: std_logic;
-	signal Alternate		: std_logic;
-
-	-- Help Registers
-	signal TmpAddr			: std_logic_vector(15 downto 0);	-- Temporary address register
-	signal IR				: std_logic_vector(7 downto 0);		-- Instruction register
-	signal ISet				: std_logic_vector(1 downto 0);		-- Instruction set selector
-	signal RegBusA_r		: std_logic_vector(15 downto 0);
-
-	signal ID16				: signed(15 downto 0);
-	signal Save_Mux			: std_logic_vector(7 downto 0);
-
-	signal TState			: unsigned(2 downto 0);
-	signal MCycle			: std_logic_vector(2 downto 0);
-	signal IntE_FF1			: std_logic;
-	signal IntE_FF2			: std_logic;
-	signal Halt_FF			: std_logic;
-	signal BusReq_s			: std_logic;
-	signal BusAck			: std_logic;
-	signal ClkEn			: std_logic;
-	signal NMI_s			: std_logic;
-	signal INT_s			: std_logic;
-	signal IStatus			: std_logic_vector(1 downto 0);
-
-	signal DI_Reg			: std_logic_vector(7 downto 0);
-	signal T_Res			: std_logic;
-	signal XY_State			: std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M		: std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch	: std_logic;
-	signal XY_Ind			: std_logic;
-	signal No_BTR			: std_logic;
-	signal BTR_r			: std_logic;
-	signal Auto_Wait		: std_logic;
-	signal Auto_Wait_t1		: std_logic;
-	signal Auto_Wait_t2		: std_logic;
-	signal IncDecZ			: std_logic;
-
-	-- ALU signals
-	signal BusB				: std_logic_vector(7 downto 0);
-	signal BusA				: std_logic_vector(7 downto 0);
-	signal ALU_Q			: std_logic_vector(7 downto 0);
-	signal F_Out			: std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r	: std_logic_vector(4 downto 0);
-	signal Arith16_r		: std_logic;
-	signal Z16_r			: std_logic;
-	signal ALU_Op_r			: std_logic_vector(3 downto 0);
-	signal Save_ALU_r		: std_logic;
-	signal PreserveC_r		: std_logic;
-	signal MCycles			: std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d		: std_logic_vector(2 downto 0);
-	signal TStates			: std_logic_vector(2 downto 0);
-	signal IntCycle			: std_logic;
-	signal NMICycle			: std_logic;
-	signal Inc_PC			: std_logic;
-	signal Inc_WZ			: std_logic;
-	signal IncDec_16		: std_logic_vector(3 downto 0);
-	signal Prefix			: std_logic_vector(1 downto 0);
-	signal Read_To_Acc		: std_logic;
-	signal Read_To_Reg		: std_logic;
-	signal Set_BusB_To		: std_logic_vector(3 downto 0);
-	signal Set_BusA_To		: std_logic_vector(3 downto 0);
-	signal ALU_Op			: std_logic_vector(3 downto 0);
-	signal Save_ALU			: std_logic;
-	signal PreserveC		: std_logic;
-	signal Arith16			: std_logic;
-	signal Set_Addr_To		: std_logic_vector(2 downto 0);
-	signal Jump				: std_logic;
-	signal JumpE			: std_logic;
-	signal JumpXY			: std_logic;
-	signal Call				: std_logic;
-	signal RstP				: std_logic;
-	signal LDZ				: std_logic;
-	signal LDW				: std_logic;
-	signal LDSPHL			: std_logic;
-	signal IORQ_i			: std_logic;
-	signal Special_LD		: std_logic_vector(2 downto 0);
-	signal ExchangeDH		: std_logic;
-	signal ExchangeRp		: std_logic;
-	signal ExchangeAF		: std_logic;
-	signal ExchangeRS		: std_logic;
-	signal I_DJNZ			: std_logic;
-	signal I_CPL			: std_logic;
-	signal I_CCF			: std_logic;
-	signal I_SCF			: std_logic;
-	signal I_RETN			: std_logic;
-	signal I_BT				: std_logic;
-	signal I_BC				: std_logic;
-	signal I_BTR			: std_logic;
-	signal I_RLD			: std_logic;
-	signal I_RRD			: std_logic;
-	signal I_INRC			: std_logic;
-	signal SetDI			: std_logic;
-	signal SetEI			: std_logic;
-	signal IMode			: std_logic_vector(1 downto 0);
-	signal Halt				: std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR => IR,
-			ISet => ISet,
-			MCycle => MCycle,
-			F => F,
-			NMICycle => NMICycle,
-			IntCycle => IntCycle,
-			MCycles => MCycles_d,
-			TStates => TStates,
-			Prefix => Prefix,
-			Inc_PC => Inc_PC,
-			Inc_WZ => Inc_WZ,
-			IncDec_16 => IncDec_16,
-			Read_To_Acc => Read_To_Acc,
-			Read_To_Reg => Read_To_Reg,
-			Set_BusB_To => Set_BusB_To,
-			Set_BusA_To => Set_BusA_To,
-			ALU_Op => ALU_Op,
-			Save_ALU => Save_ALU,
-			PreserveC => PreserveC,
-			Arith16 => Arith16,
-			Set_Addr_To => Set_Addr_To,
-			IORQ => IORQ_i,
-			Jump => Jump,
-			JumpE => JumpE,
-			JumpXY => JumpXY,
-			Call => Call,
-			RstP => RstP,
-			LDZ => LDZ,
-			LDW => LDW,
-			LDSPHL => LDSPHL,
-			Special_LD => Special_LD,
-			ExchangeDH => ExchangeDH,
-			ExchangeRp => ExchangeRp,
-			ExchangeAF => ExchangeAF,
-			ExchangeRS => ExchangeRS,
-			I_DJNZ => I_DJNZ,
-			I_CPL => I_CPL,
-			I_CCF => I_CCF,
-			I_SCF => I_SCF,
-			I_RETN => I_RETN,
-			I_BT => I_BT,
-			I_BC => I_BC,
-			I_BTR => I_BTR,
-			I_RLD => I_RLD,
-			I_RRD => I_RRD,
-			I_INRC => I_INRC,
-			SetDI => SetDI,
-			SetEI => SetEI,
-			IMode => IMode,
-			Halt => Halt,
-			NoRead => NoRead,
-			Write => Write);
-
-	alu : T80_ALU
-		generic map(
-			Mode => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			Arith16 => Arith16_r,
-			Z16 => Z16_r,
-			ALU_Op => ALU_Op_r,
-			IR => IR(5 downto 0),
-			ISet => ISet,
-			BusA => BusA,
-			BusB => BusB,
-			F_In => F,
-			Q => ALU_Q,
-			F_Out => F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 and Auto_Wait_t1 = '0' then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk => CLK_n,
-			CEN => ClkEn,
-			WEH => RegWEH,
-			WEL => RegWEL,
-			AddrA => RegAddrA,
-			AddrB => RegAddrB,
-			AddrC => RegAddrC,
-			DIH => RegDIH,
-			DIL => RegDIL,
-			DOAH => RegBusA(15 downto 8),
-			DOAL => RegBusA(7 downto 0),
-			DOBH => RegBusB(15 downto 8),
-			DOBL => RegBusB(7 downto 0),
-			DOCH => RegBusC(15 downto 8),
-			DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if T_Res = '1' then
-				Auto_Wait_t1 <= '0';
-			else
-				Auto_Wait_t1 <= Auto_Wait or IORQ_i;
-			end if;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
-						(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_ALU.vhd
deleted file mode 100644
index 86fddce7..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_ALU.vhd	
+++ /dev/null
@@ -1,351 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0238 : Fixed zero flag for 16 bit SBC and ADC
---
---	0240 : Added GB operations
---
---	0242 : Cleanup
---
---	0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A : std_logic_vector;
-					B : std_logic_vector;
-					Sub : std_logic;
-					Carry_In : std_logic;
-					signal Res : out std_logic_vector;
-					signal Carry : out std_logic) is
-		variable B_i		: unsigned(A'length - 1 downto 0);
-		variable Res_i		: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i := unsigned(B);
-		end if;
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal	UseCarry		: std_logic;
-	signal	Carry7_v		: std_logic;
-	signal	Overflow_v		: std_logic;
-	signal	HalfCarry_v		: std_logic;
-	signal	Carry_v			: std_logic;
-	signal	Q_v				: std_logic_vector(7 downto 0);
-
-	signal	BitMask			: std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-									"00000010" when "001",
-									"00000100" when "010",
-									"00001000" when "011",
-									"00010000" when "100",
-									"00100000" when "101",
-									"01000000" when "110",
-									"10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-	OverFlow_v <= Carry_v xor Carry7_v;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);	-- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_MCode.vhd
deleted file mode 100644
index 4cc30f35..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_MCode.vhd	
+++ /dev/null
@@ -1,1934 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed IM 1
---
---	0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---	0235 : Added IM 2 fix by Mike Johnson
---
---	0238 : Added NoRead signal
---
---	0238b: Fixed instruction timing for POP and DJNZ
---
---	0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
---
---	0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
---	constant aNone	: std_logic_vector(2 downto 0) := "000";
---	constant aXY	: std_logic_vector(2 downto 0) := "001";
---	constant aIOA	: std_logic_vector(2 downto 0) := "010";
---	constant aSP	: std_logic_vector(2 downto 0) := "011";
---	constant aBC	: std_logic_vector(2 downto 0) := "100";
---	constant aDE	: std_logic_vector(2 downto 0) := "101";
---	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---	Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To	<= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To	<= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";	-- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n	-- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To	<= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---	CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if MCycle = "001" then
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if MCycle = "001" then
-					Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					ALU_Op <= "1001";
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others =>
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if MCycle = "001" then
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if MCycle = "001" then
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-				end if;
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---	ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)	<= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0010";
-					else
-						IncDec_16 <= "1010";
-					end if;
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---				TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_Pack.vhd
deleted file mode 100644
index ac7d34da..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_Pack.vhd	
+++ /dev/null
@@ -1,208 +0,0 @@
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait : integer := 0;	-- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		CEN			: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		IORQ		: out std_logic;
-		NoRead		: out std_logic;
-		Write		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DInst		: in std_logic_vector(7 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0);
-		MC			: out std_logic_vector(2 downto 0);
-		TS			: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE		: out std_logic;
-		Stop		: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle			: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		MCycles			: out std_logic_vector(2 downto 0);
-		TStates			: out std_logic_vector(2 downto 0);
-		Prefix			: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC			: out std_logic;
-		Inc_WZ			: out std_logic;
-		IncDec_16		: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg		: out std_logic;
-		Read_To_Acc		: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op			: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC		: out std_logic;
-		Arith16			: out std_logic;
-		Set_Addr_To		: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY			: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ				: out std_logic;
-		LDW				: out std_logic;
-		LDSPHL			: out std_logic;
-		Special_LD		: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH		: out std_logic;
-		ExchangeRp		: out std_logic;
-		ExchangeAF		: out std_logic;
-		ExchangeRS		: out std_logic;
-		I_DJNZ			: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN			: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC			: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead			: out std_logic;
-		Write			: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16		: in std_logic;
-		Z16			: in std_logic;
-		ALU_Op		: in std_logic_vector(3 downto 0);
-		IR			: in std_logic_vector(5 downto 0);
-		ISet		: in std_logic_vector(1 downto 0);
-		BusA		: in std_logic_vector(7 downto 0);
-		BusB		: in std_logic_vector(7 downto 0);
-		F_In		: in std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80s.vhd
deleted file mode 100644
index 5b612110..00000000
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/T80/T80s.vhd	
+++ /dev/null
@@ -1,190 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0210 : Fixed read with wait
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0236 : Added T2Write generic
---
---	0237 : Fixed T2Write with wait state
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80s is
-	generic(
-		Mode : integer := 0;	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		T2Write : integer := 0;	-- 0 => WR_n active in T3, /=0 => WR_n active in T2
-		IOWait : integer := 1	-- 0 => Single cycle I/O, 1 => Std I/O cycle
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80s;
-
-architecture rtl of T80s is
-
-	signal CEN			: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => IOWait)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_n,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => RESET_n,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n,
-			CLK_n => CLK_n,
-			A => A,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			if MCycle = "001" then
-				if TState = "001" or (TState = "010" and Wait_n = '0') then
-					RD_n <= not IntCycle_n;
-					MREQ_n <= not IntCycle_n;
-					IORQ_n <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					MREQ_n <= '0';
-				end if;
-			else
-				if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
-					RD_n <= '0';
-					IORQ_n <= not IORQ;
-					MREQ_n <= IORQ;
-				end if;
-				if T2Write = 0 then
-					if TState = "010" and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				else
-					if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
-						WR_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-				end if;
-			end if;
-			if TState = "010" and Wait_n = '1' then
-				DI_Reg <= DI;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.tcl b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.tcl
index be673dac..938515d8 100644
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.tcl	
+++ b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/build_id.tcl	
@@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
 	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
 
 	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.sv"
+	set outputFileName "rtl/build_id.v"
 	set outputFile [open $outputFileName "w"]
 
 	# Output the Verilog source
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/crazy_climber.vhd b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/crazy_climber.vhd
index e7002afb..aca26e50 100644
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/crazy_climber.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/crazy_climber.vhd	
@@ -9,7 +9,6 @@ use ieee.numeric_std.all;
 entity crazy_climber is
 port(
   clock_12  	: in std_logic;
-  pause  		: in std_logic;
   reset        : in std_logic;
   video_r      : out std_logic_vector(2 downto 0);
   video_g      : out std_logic_vector(2 downto 0);
@@ -118,7 +117,7 @@ signal video_mux              : std_logic_vector(7 downto 0);
 
 -- Z80 interface 
 signal cpu_clock  : std_logic;
-signal cpu_clk  : std_logic;
+signal cpu_clock_en  : std_logic;
 signal cpu_wr_n   : std_logic;
 signal cpu_addr   : std_logic_vector(15 downto 0);
 signal cpu_do     : std_logic_vector(7 downto 0);
@@ -200,7 +199,7 @@ video_vs    <= vsync;
 ------------------
 player1 		<= right1 & left1 & "00000" & fire1;
 player2 		<= right2 & left2 & "00000" & fire2;
-coins 		<=  ("0001" & start2 & start1 & '0' & coin1); -- upright cabinet
+coins 		<=  ("1111" & start2 & start1 & '0' & coin1); -- upright cabinet
 
 -----------------------
 -- cpu write addressing
@@ -219,10 +218,10 @@ reg6_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto
 ---------------------------
 -- enable/disable interrupt
 ---------------------------
-process (cpu_clock)
+process (clock_12)
 begin
-	if falling_edge(cpu_clock) then
-		if cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then
+	if rising_edge(clock_12) then
+		if cpu_clock_en = '1' and cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then
 			raz_int_n <= cpu_do(0);
 		end if;
 end if;
@@ -608,7 +607,8 @@ port map (
   y_tile     => y_tile,
   x_pixel    => x_pixel,
   y_pixel    => y_pixel,
-  cpu_clock  => cpu_clock
+  cpu_clock  => cpu_clock,
+  cpu_clock_en => cpu_clock_en
 );
 
 
@@ -628,13 +628,13 @@ port map (
 	data  => do_big_sprite_palette 
 );
 
-cpu_clk <= cpu_clock when pause = '0';
 -- Z80
-Z80 : entity work.T80s
+Z80 : entity work.T80se
 generic map(Mode => 0, T2Write => 1, IOWait => 1)
 port map(
   RESET_n => reset_n,
-  CLK_n   => cpu_clk,
+  CLK_n   => clock_12,
+  CLKEN   => cpu_clock_en,
   WAIT_n  => '1',
   INT_n   => '1',
   NMI_n   => cpu_int_n,
diff --git a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/video_gen.vhd b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/video_gen.vhd
index 2abe45d1..94c0dcd0 100644
--- a/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/video_gen.vhd	
+++ b/Arcade_MiST/Crazy Climber Hardware/Silver Land_MiST/rtl/video_gen.vhd	
@@ -11,8 +11,8 @@ port(
 	hsync       : out std_logic;
 	vsync       : out std_logic;
 	csync       : out std_logic;
-	hblank       : out std_logic;
-	vblank       : out std_logic;
+	hblank      : out std_logic;
+	vblank      : out std_logic;
 
 	is_sprite   : out std_logic;
 	sprite      : out std_logic_vector(2 downto 0);
@@ -21,7 +21,8 @@ port(
 	x_pixel     : out std_logic_vector(2 downto 0);
 	y_pixel     : out std_logic_vector(2 downto 0);
 
-	cpu_clock   : out std_logic
+	cpu_clock   : out std_logic;
+	cpu_clock_en: out std_logic
 );
 end video_gen;
 
@@ -39,6 +40,7 @@ signal enable_clk : std_logic := '0';
 begin
 
 cpu_clock  <= not hcnt(0);
+cpu_clock_en <= ena_pixel and hcnt(0);
 is_sprite  <= not hcnt(8);
 sprite     <= std_logic_vector(hcnt(6 downto 4));
 x_tile     <= std_logic_vector(hcnt(7 downto 3));
@@ -113,14 +115,14 @@ begin
 			end if;
 
 			if    vcnt = 511 then vsync <= '0';
-			elsif vcnt = 250 then vsync <= '1';--
+			elsif vcnt = 250 then vsync <= '1';
 			end if;    
 
-			if    hcnt = (127+8+1) then hblank <= '1'; -- +8 = retard du shift_register + 1 pixel--
-			elsif hcnt = (255+8+1) then hblank <= '0'; -- +8 = retard du shift_register + 1 pixel--
+			if    hcnt = (127+8+1) then hblank <= '1'; -- +8 = retard du shift_register + 1 pixel
+			elsif hcnt = (255+8+1) then hblank <= '0'; -- +8 = retard du shift_register + 1 pixel
 			end if;    
 
-			if    vcnt = (495+1+0) then vblank <= '1';
+			if    vcnt = (495+1+1) then vblank <= '1';
 			elsif vcnt = (271+1+1) then vblank <= '0';
 			end if;