From 0ad1fab5b5e71b9fb8595e1db16fb1f43063dbfd Mon Sep 17 00:00:00 2001 From: Gehstock Date: Fri, 9 Feb 2018 10:15:04 +0100 Subject: [PATCH] Add Soundboard Core --- 2048_Mist/README.md | 4 +- .../AS-2518-51_snd-master/AS-2518-51_snd.qpf | 30 + .../AS-2518-51_snd-master/AS-2518-51_snd.qsf | 161 + .../AS-2518-51_snd-master/README.txt | 6 + .../Release/AS-2518-51_snd.rbf | Bin 0 -> 236224 bytes .../AS-2518-51_snd-master/clean.bat | 37 + .../rtl/AS-2518-51_core.vhd | 165 + .../AS-2518-51_snd-master/rtl/Debouncer.vhd | 43 + .../AS-2518-51_snd-master/rtl/Keyboard.vhd | 61 + .../rtl/KeyboardMapper.vhd | 170 + .../AS-2518-51_snd-master/rtl/MPU_RAM.vhd | 181 + .../rtl/PS2Controller.vhd | 209 + .../rtl/ROM/NitroGroundshaker.hex | 129 + .../AS-2518-51_snd-master/rtl/U4_ROM.qip | 3 + .../AS-2518-51_snd-master/rtl/U4_ROM.vhd | 143 + .../rtl/ay-3-8910-core.Vhd | 375 ++ .../AS-2518-51_snd-master/rtl/ay-3-8910.Vhd | 262 ++ .../rtl/ay-3-8910_vectors.vhd | 1165 +++++ .../AS-2518-51_snd-master/rtl/cpu68.vhd | 3962 +++++++++++++++++ .../AS-2518-51_snd-master/rtl/dac.vhd | 71 + .../rtl/greybox_tmp/cbx_args.txt | 16 + .../AS-2518-51_snd-master/rtl/m6810.vhd | 65 + .../AS-2518-51_snd-master/rtl/minibd_top.vhd | 144 + .../AS-2518-51_snd-master/rtl/mist_io.sv | 491 ++ .../AS-2518-51_snd-master/rtl/pia6821.vhd | 534 +++ .../rtl/williams_snd_pll.qip | 4 + .../rtl/williams_snd_pll.vhd | 355 ++ 27 files changed, 8784 insertions(+), 2 deletions(-) create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/AS-2518-51_snd.qpf create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/AS-2518-51_snd.qsf create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/README.txt create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/Release/AS-2518-51_snd.rbf create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/clean.bat create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/AS-2518-51_core.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/Debouncer.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/Keyboard.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/KeyboardMapper.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/MPU_RAM.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/PS2Controller.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/ROM/NitroGroundshaker.hex create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.qip create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910-core.Vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910.Vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910_vectors.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/cpu68.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/dac.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/greybox_tmp/cbx_args.txt create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/m6810.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/minibd_top.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/mist_io.sv create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/pia6821.vhd create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.qip create mode 100644 Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.vhd diff --git a/2048_Mist/README.md b/2048_Mist/README.md index aad9d400..d7424ad4 100644 --- a/2048_Mist/README.md +++ b/2048_Mist/README.md @@ -1,5 +1,5 @@ -# 2048-DE1 -VHDL implementation of 2048 Game on Altera DE1 FPGA Board developed in the "Digital Systems M" course of the University of Bologna +# 2048-MIST +VHDL implementation of 2048 Game on MiST FPGA Board developed in the "Digital Systems M" course of the University of Bologna Controls diff --git a/Soundboards_MiST/AS-2518-51_snd-master/AS-2518-51_snd.qpf b/Soundboards_MiST/AS-2518-51_snd-master/AS-2518-51_snd.qpf new file mode 100644 index 00000000..9fdfc13a --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/AS-2518-51_snd.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 21:32:18 December 01, 2015 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "21:32:18 December 01, 2015" + +# Revisions + +PROJECT_REVISION = "AS-2518-51_snd" diff --git a/Soundboards_MiST/AS-2518-51_snd-master/AS-2518-51_snd.qsf b/Soundboards_MiST/AS-2518-51_snd-master/AS-2518-51_snd.qsf new file mode 100644 index 00000000..eb4d71a3 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/AS-2518-51_snd.qsf @@ -0,0 +1,161 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 21:32:18 December 01, 2015 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# AS-2518-51_snd_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name TOP_LEVEL_ENTITY minibd_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:32:18 DECEMBER 01, 2015" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity robotron_sound_top -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity robotron_sound_top -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -entity robotron_sound_top -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity robotron_sound_top -section_id Top +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp +set_global_assignment -name VHDL_FILE rtl/minibd_top.vhd +set_global_assignment -name VHDL_FILE "rtl/AS-2518-51_core.vhd" +set_global_assignment -name QIP_FILE rtl/williams_snd_pll.qip +set_global_assignment -name QIP_FILE rtl/U4_ROM.qip +set_global_assignment -name VHDL_FILE rtl/PS2Controller.vhd +set_global_assignment -name VHDL_FILE rtl/pia6821.vhd +set_global_assignment -name VHDL_FILE rtl/MPU_RAM.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv +set_global_assignment -name VHDL_FILE rtl/m6810.vhd +set_global_assignment -name VHDL_FILE rtl/KeyboardMapper.vhd +set_global_assignment -name VHDL_FILE rtl/Keyboard.vhd +set_global_assignment -name VHDL_FILE rtl/Debouncer.vhd +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name VHDL_FILE rtl/cpu68.vhd +set_global_assignment -name VHDL_FILE "rtl/ay-3-8910-core.Vhd" +set_global_assignment -name VHDL_FILE "rtl/ay-3-8910_vectors.vhd" +set_global_assignment -name VHDL_FILE "rtl/ay-3-8910.Vhd" +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Soundboards_MiST/AS-2518-51_snd-master/README.txt b/Soundboards_MiST/AS-2518-51_snd-master/README.txt new file mode 100644 index 00000000..c5cc0a35 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/README.txt @@ -0,0 +1,6 @@ +Bally AS-2518-51 sound board, the predecessor of the Squawk & Talk used in late 70's Bally pinballs + +https://github.com/FPGA-Code/AS-2518-51_snd + +No Video Output!!! +Keyboard Controls diff --git a/Soundboards_MiST/AS-2518-51_snd-master/Release/AS-2518-51_snd.rbf b/Soundboards_MiST/AS-2518-51_snd-master/Release/AS-2518-51_snd.rbf new file mode 100644 index 0000000000000000000000000000000000000000..7c5f278bf4f2f667b7fdfd0835061bbf387d6e6e GIT binary patch literal 236224 zcmeFa4V+{}b@zX#X~qFp>}i{^U3p;cczf9;AZmy)F+SYeRF5Mr?l2DPCZbEPJs3r^ zVALluFFU>Tz^W){Q1kaCfB`j$1T^Mj{O5&57B$fXf|&Rc0~lYDzlroFBta$a|NA@l zR`;FRnceBx%_k-gH8Xwd)~z~q&Z$$U&N)@L=fHtOr&s>FrGNSUzkL6D-`oH2!~gNf zBi}u6;F140@Vy^=|B>(h$0H9v{KzAZe2;YQ>kbX*fBe&cG*8N3m47s?jRVCjTC%C`|-s*}e@c_oz}D)~BA zd4>AEPM#mj!4$5)NYXQp({lBWW|?>)ygW?xtK{!>?Mq&NE~K?q{#2X%QxDJc$zOeW zo;MmBwUx|vNFGPs`+0G=Ya>f}91_yd3Tc$2M+;f<)zs!rk}nrN`__;=9)hRj>GrbW z?@L)yKT0Z>T&TV17oSAC=hxw`o_D^U@5f(#|DIl7?yo5posQ7DmgMQsbKh2F8t*#E zKVQvN^}U?<{&X$mlE=&Ap+}-cZTFIPlddPdiS!xLJtUPMD&0@=&+~X*L>kXh9v|gZ ztm}tKSCK-Ja8sMlk$kzH>HcrBq`XhQY`N?7lH}!J=~Xx=sUIah7jHy|c&Rb*N%u?B zwk+k#eVMLH(3oD@zwW<55}$=f{`q^eq;laPoHSMZ*j+*LQ|D78pI>^tH%q=;aPoMm z&oU{0T@DYGRY{kU1X6h1NYYiXRp$Fx&2@(K8j|qQxQotwzf1F;A1c3wBpNOxolH6@ zOS;#*K2-X-EcrU>e@8AoBTEw`Wp&M`-_4TBP9v%5H%Xokx+;0zq<05@YX0X-eIMe3 zpC7rYThJIOsZ7_mW=Z$QlQf4V2a*e)4kZ^Wjgk0~PkFqAo02cn^-r>-y!a)4e23)u zq^s_iCO?n;RnL81*E|l&YuwY`(@*uMHeW7w2?v$=bU2*!JdcC&T4Ti%pL~D*nrgJGuF}2q$ID3HB1z`1BEJ}x_{bX zlIM}XUPqEX@%N%ZGAI1})#Iw`)midoTAzHGuD6i{^C_fbvh<^*CoD-S^GT2LI;}zy zKfXx%^(@JD(>m;vp8344-_Fv~GL5y;&u2+^`Q-c0UxmMtFB2Y`2OdAkY<^ydM~6xZ zemqE$?E55qJPs>eZ^@GIP#vK!I4Tx?;(xy1)#BuFkZw}ad^nVj_4-q~_3b3BRa;48 zS<;%L`5 z{j96(>6Mb^R6c2)(!IySUp*d6uO2V){brJ$izixZ{(|%yq`xKkwMbW$9WHsf^7C)$ zRkY`E(R1Ak4<+&F10>=9N|MG?Hkhv8C0#;Necg+1vRjTL>0Zf~soW=(DJ|8j9yiTb zpZECWaZ+Bkv~bdV{2h{}r{?f)k#v<^?bExncu189 zAN8*!yp)vx5J}fJ=hAz!YA(sP zP}11@tMV%)zut-;8gq?{WM6BB))yt+A1-OlRPyx%N4m@>uQN4Qyx#KjM%PTG-J-ns zu68dcNmis2bX7W*l;&3V>DL+2=aVnXkC`viI;AyA^lmn~ffb^gA>7x4chYjWDt5@}qpT*<(joT)!2efOH z3#SzV8lC+I#{q+`r?>?5QT3b7vvJTZ>WNP!x)guPOtbObVi@U~x<1u-&v=o>yCWDD zB;kDF{=ayv9vzkRLoRAZg~lK_`g7n>#8%INM`djFyh>~4IcCaWPyqS*-4DD!e|u#4 zM`zNY{CkvRk8*4o4rq$+UZ#94Me)#?zww`GW3L6Ltj+%|(my_szjY{vR_^-a;X^$i z=owP>!;9HqKI)<99{r~`@pycw8kE91PDxak^?c6A=5$obI3c4Gm5o6>QQTAvp4Qph zF=zuf2yXk<`V_sKC$`X zE9&P?d=d(8jMAHrUS`bI*d2Mg?<2<_Igktjn&Rl`%DZntx{p#i+A3^Nw3r8J(u`e{ zx~G43(fulK1aRD7DLm7Mdi6II%o!*NKp&iPeQ;-g*oyw;ENj!>Z4_hyKs1 zp=1?7h*TxSndb8CcRljB{Ov089$Ln@MJ?{?u;vb$=9y0(v2t#r2Ep082DZjISK+Dj zFnjpi_lbeAE0?Q5wOZz9J{yk37=HZ1K`p=ecGzwYRRPRT8S7X84d-$X;duZ1UODih zLmYj5I7HAKOogmc4`MKS_3OmTBellMvg5aXeCiRU z+w-^M3oraj*WZ|Fn3|YQUt~}$yhp*i6%JBAu?Hk`eRzBm?nDa9IvF%gq zed%@LYi8{K=QjVs(q7a1-%r&0I}Q2ozSEHZ?z@EiJGO5U@_&sze>b= zxlC(F@U^V1!R*&V=sxFfd^U)CGo@Fwd`82+T#7$((s6s1dvK^S2}_W!&ed_{`_N1K zzxRTy>8f#)wo@_@HQ0T4!Sfd~aD!gVcv#Zt!Cx5E?j=M6M)n6RLoNsNwhs)h?6ky* zYy1LkoFzn7NtU{2+ObrByP7M87w<-mhi$ET0IF&(3S=MX=09Bxphb1SE^SXnsRt|w z4%|EVDwJyuFzEKF`%fSD*(1NM&D>9g4LWmDCtPm%tH%$Bl0**LjAc-4ME8Mi|F_2s zYAC6H02n|nVY|<`p!=r%1EQB!7eX0Q8C;cjC(lbCui+DD0+<`)?*6j}hhsDfhTfRB4#V^+9&FUPrLAUy+1CK038rwuQQx@Qg24|`J zjGyq?0j>rTT9>AU#|^pwL0qQz3_TeSW~uiP{C_^Rw3ox(bBtaD2DbP!b051*niN>Q_0r>W^}R$^kJ#wH_1dA$AClRZvbT)Qzy6ruF-Yclka!c*Y((wGXF^8FFmBzR0^Pb+jrB<0H1;=u1XfhG5h71bM@)j69e1)xH>6@ z2E(%b`^v2^T9d2et$tuGqWIhgJ*I> z6o{tic+LPBJ@qAvx>)s1y4o$N-faxLpp?tw*u26}YCp5l&CktXzvcT&IyvmE-~>{c zO8v30+sT24L*|08O99Rs_cGW(-1Wvm0Wt`H!*{TS4g{I(49I+nE+EhTN-ygS=T(37 z(dspM+GV}$V3}oLbinzrA&lu8XVlq_Ir*Q*b?mZ zByf45t8}0J+1|q=&g9s3#IV-1?`EXU_awBB#4Vp2+>6dy=h>AOZC^j|Nu+reOyOm? zX_*`EBiX%Y>zW4CVC4ZBc9rk^dWQHKFFDMD?)G0F6g8UnAV6p@FKjAzy?S6DYaRnW zRlo+#K5|2{ee(E0V@tALFy^u1&7PA&rYN)Rgy!g(JCEUVq(S`kAHkp>p%XJgvFk^} zuZ^|~*NXzphmo_;3eFico zs#%)@FIQ}99{wI=p0BDfMQqus-R7&+34N~3bx4r~boJo&yEZ6PwQRSmDO8=6P}}+C zWBxl@_Agv=Dv0})P6fRqJ5;ptxty7S=RnHMzG{ai2Tvgn_|lIIYTx>n{+fe**AoU_)y?vT?Om;{_0rcX52~?ZK~6Z*I^7Gd zU9s}Y4-Nv8R=xDRC9=3Ogk_&B0{a`EUbfDf3bB<3UP%?rv{Mpg3v}9e%7yL^>&|~! zlwd=p`^ey@rD)DLXoTTg%004u;6xE)oBc%vT2kSb(AaIpwNv&#c2FB%;Tr!d>mDH-SJ={zL-&f8k{ySZBR)+J z5A@rIb$VFbbZqXF&X(5=Y=}!?r)jCa?Y>|Qr&T=FORsCuK}%uy`%3p~f9mstUl|{z zKDE1kap2WBgJFO?`|Kv@p8M}<=4gDTQ&F9*&3-o=mTi8dhwA4Q{^OTxI8<3*K)&-w z{%`#)nQ_bZeE336;iNq6S6vjHKYQYF{~c}kHJt2U*@nMt(9L`kg=Ie~JD+siz{+$f zq~0Xxe(n{6n()A~$*AF8l16WP*};WN>MVbY1$r>N7kz&D%7-dF7)n~Zd+s|A)ol4^ z(%y>mYjqId`L-4dU-#@g1~%ip@oqqL4kwp({r$jJH^a!vg`I~Xq=kVcSZMmxJ@8DQ zUGke}T}+^FZC*8$e#IOAk#holk?BGtL%E;po2Ru3i&XB&T`!P z)V=4Xf!7{?h@3DqI&Xf+-z!Sr<7R39{^!$4-|k-98?o1qKL1I3J9g?ii=Y##R;2!h zrw8jF2*cu!oKM8H_nvL{ci-qKTkUn6usmUP@ky~;WwVl8y#AC&`Yc-|V1V_0760!2 z`u5$6e`VlPIKJ&c*GqqI;DyUm%2x;xsLv5?d`Nrf-hRqKT^**t13KFLG}*NeiF0=6 zak=!vI)60JApKBT{pGzKk872Q61R_G9&X~em>mQX@@KxUAVZQFe{f9y2n!#5opuec z)1r6v8xplcnzB19(`YGO`ow`}TH0`#Pwbq5wXbPdzYro_68bE4U-%-QUF|j3+N3ad z-@WJd)k5jl10jCXDOK|_SgNIVH*OYn)_R-$;ql2Db z1PIvKdvHQ(33lBV+dmcRcd&|_AbL3D35a<{V)t*qY84O`S22{*q8^6nZMQXWz>bC) zIyS2PaR9fMoV>W>Ro>$m8B{$>4})#ernTK?uagGb{uqJ0pH?@qaJaDPemrQqrC za~`s2d+^zV!jtn$GC)~g_i5_>*-!iIAlJT__35Vl_L~PqE=Z*}g|`S+5Iq0NK~VB_ zJrF?JO!MXU{rD-HVhXbR?B{vdtG%YU0S%Z-+Fbh4fpwFuG)M`s z1kM(rKG^$zdeAk85F_#-5m7{fO{g?0bhEVOu0d5^?(I+_dBtN)cWrs)&0Yt?d4aS z>A5^&;6W}=5bS)}z*1+6;!1}9-EY^XCH(nsX!!rAfsuhB;@k&F8P zi5`;O>oyGvFxA7Xg7Q&+_Dz8E;1(jJli#>qq>sARTUk#XfQ@!`- z?6(d28g#E|Dk&+^S>ettgPJEEDWlonWYF$=*5IBZ!%5ON(10Gc55E~SUAFwx@Ze!s zf5yL>!D1K6gRFGFtnrp(+F$>X4z58HRQe|A7%R(+gJF(JjD0S9cB?t1B zp~lRR4BLST4~^@uoRPa(eb%N!`hsWX+gjW1&JV60MplyvX80Z4@a`WB{N5FuLV{&& zlkA3Ue|&Eqc=<@%8a(?*XGx0dgC89kbhCK89Wu81v|}-FP+yZHRnwR3__D7KY)he+ zS=dd(&v{Y|n$23_cAk5}s{1m=3TP5z;{wE!`8p;7MBT)$CvlZnP6g zuqm0(9l8&KyOV*x8ep8^!~e>h6%eE#T|f-4O83S$T4sO`fiyh9&sIt^Ia0I*ru%bG z9RQlI>U}9wpa$7L*|~9GKR#V{(`6RGns<<%rS32Om2x~iqG-B>>e-_>IB$0XUqHE?p8FTfEa*Av{X^fB&+9@zGq81#4g=jQ!O8 zv;F-W%N_nD9y^0NZc}vLbf0aj^uTn(PxkVw&9De+0WmvI(_E{Tb&~<;{_6Wz3o2Jn zOOjV~eHN-h_e*oRdaKJ4=uHm;X`vmG4KLeFSo`+fYk$dSSAES;%<9hrx7W1$@;CSL ztIgz^t4WUP`+ijcl|hqvQ#}Ivt-q~xXQcp1P>qVt;ikeZZ(759feeRH zoWjk(3tHut9fO8}new?fK6*f~4Y~lb_y3avAEK7m$Z5#*BYPDhWc-JLsD4>GOkWB2}wK$^WOn>G8(K$br8LPaDbu}5*& z0D+@xe_ZHxeOJ#y?zGUYpU{iM1EuV{ALZ!Cto2_7xtN$>%g%xATI^!^O8}CDq<3hC zENCDccU~~CJez?m-z*fanjzY<=?`h8d&A8GkxylbMjPJ+P_Q?>OFuoN?w|iJpI!CU z^Z*!2n`X9*_>iXV&7se(_L^b@2>X^!Z_UZ3^JzTGWv(3Fi^CNmufG^qs>y!md z^!SDlC8Y0_?S0kGrGF>k5_i^sxP4ux^raM0Ic`tzc};yh_eDP6f6k-32Lp$H?7$G( zK4e9cjPa2x%0w>S|CN9A(s$(7!QVNXw>6T*gI^{t%ZBCy>yk&NwEyET@cDtS0xF^G zr|umCe?Jg<6f;CPN==_bZq5;jc1h4vnV~y^uF|uL}oV)O%KjVY(QFot=R- zwBg0%hFp@?+TMB_ocSNpP-{z`-d^ilYJW{ zqSy4G%+W-wa`)JpId;%c25b0+n}ewH1#6*FlQT=oF+cl4`_=RPqXDnkeCmUyefLej zIUp1n5c56k7B_z7z~(mXai!B zB$w~NtllFc6S3Sso+tN4X>-x3b`>Xcvw|4BlI{n7}|9(LDmt6XvVsEXVn^MF5 zmJbd7u9>OQOrIX))*krzfsM}3=a5@5oM5V~dhWDv^N6TjixSFvI!Q)u* zG~?paf$t8ib3sc0ywk3Dx`#$MlIc?p;vviU}U0G_eXfb|C>xODR&jTeP{0SpO^aSi?QwtG z-R69Dg{ueJdkp4=^+69PzWRX`$5!px+RHF88u?%gQpA%(dD>x`ObW1f`{|VPR#NqX zlbvu5{1jH%qI6KfnSZggimz`PNs$(r@yI5WF~b3GF=U39pd5WNxJeDs>D3FbAYLN8<*XyYvW=(WLlw z8gn1Q_O|^4PcxJ9jYIKjeTg4Qg7K%@Kj2;DOw1?gzvjJmZwK&i9!=rR59xdU3;toh z+0(D?_kPG6RFF&mc}(l>&R zFYa7TXm6*VY<932VVF~HC!qQ;uY30)=SZ(&>J#yq;%LiwdS@v6*E)Rt?&q)a*+X7a zp6L^2LaYfzdTW~;WaT#X({1H}cPewQK=%xm$M2L}n`To+nW&3Ymiz^qi-2>G<<;Nd)#fp8~5u#@? zA^C5_h^+l@uOzL_W&z>IYwAq+tlxC$JeYv1FFEc}SEBD39f>QUC2CyiH08B|C|QzD z?5FOV&h6hEX%2ULPacLAHVKA>{aAhVi%~w0m}|e5VomMrfgZ~k=xsA<%^43vb{l%Q z2i@kE^Bt@vFHX>nri>|5?NI|+NoC#lo@ROfA)FLZTn=Y3^kAI9(sPuIEkhnyaQDVl zMB+8&lu|I-LT3*s1*u`v3!u5Q{U;8il-jwrW=g;q13R^Z6Ax^!7s1kNUmU!jA~^J zAiynSL#k3s+v}?s8fvO_ddULKcDwZB(noqnP#{<&tSWi>tU->0SKoVZ)Zf?b1HODH zBQztkhamS$YIje4;o|QMS-R(DgwoElF5@JpZkR2o5gQ9`81x)<_djt(Hv}}tmt%t! zX6gteb3_Nh{cm4kjMa#mLP`jB0+zssF|s2^=;V>nRcfd?5)Daj`Zb4 zZH+w@SRPPD{E%x8jfYw=^oP)D@ypUh|LSw;l|IBuVI{=W$s32>n2cOg?X<^}sgbLO zt`a@`Qli5};5%<%L*@g(?Vb!-I?u!z*xen`{K_1sLT6#bgqN)8{Z5-)?`>!R>6BLA zeMxO~s*rx_cv^_hx$ice*FPiJgVp-R8%8_WwL*0?{3P!>&p*Ka1^)|nVWg^WLaJU3 z($tyW^XAdULHw8X6a%jp5KWRklKeLBKyM8|(dB1OM-d&GXs6{pBe}*(cRa z^6&XMnJ`$A{DvY@TNn=u_5smM(q! z;?R)wkU10rqdu=6g`Ik!Pi{~QdNjICJu3%eSgB;_OO(xrvYnCsB;$Uq8nWJJP`-~XpI$uu z@pkgNL~yvBD}Y1B?ETg1g6*zd-6jjytd@UDPhx}Zgr$Ro5ZDp19=CRW@HlB^IMLf= z!G*DEl6fA0wf?EzdfX=j?fTKZS6x4f;8~T0k-b@kb9fRkC14HzI++1FS=K32xmu2I zcsiB(FIQ-8c5l917lvdRXRD741GP6>I5c|k4I!wS8)yC+`hz}@S01RlO%d?CBX{YR zV-Mw1d3r(P?x{?zq#d^d94!=wIaue}z-^$ekNcYqoDb z=f$VLxqLFaJP#!sZC~V^_e4*vYIo=P?};`%oNo8L?DDsCc5eLG^O~2xWntIG4~&hm zWwbECmeI}n*Ul-F(;m3};kRaA>#A!Cgv=5k$zg%i&$ay~ysH#O{oH@va@%;uU6VPJ z3DfX!Q*zS#9UGyz^F}5}m{j)+b;h-X@|dfAq$2CB4~8mDmG3*BUE8$>iRRtw-Zh`c zHiHNXY0{{hy36jDT;^rX1;RK>rTss;!{_tYUZ2RCO@jQxUVdIWU)^c$rm6cgzwfhy zU%?A_xwPvu2b;pV#{*>t+guJ04ZHih-#K)JMNf|^FhNfEYxCFVyGqk^>q~mxh%Z|6 zbugagy6MSJuB^L#(D$D`nK>Z6?AddRm%QGCHDuOI=5l=<<#Pwib+NXxM-dy8Z%3bF zQf~*xKA9~&FCuYsOCir7HxqVj(^$80&58n+bMXUSr3 z+h5F72-3V2$Eyp;SzSIBSHJBmau_53aOvZI`AWGIwe0Dub6;N{V`(e-YkIe;&lJV( zDc7y4_KKAk!?*2FfFj7pD_zuJRAK5n`4F!AI8fF0Q)YSd-YAcDKU^*4)M^HpO) z>kLkBOv8BS?9JIYt{TpgilwrbPryF-#l`W7C3RPGD}uwg5DLj}*H_bGQ3pX0 zy|HZvbU*aDwIUZvhF|V2+nBcl1jz)7q8Xj z24uu|*SU}t+3AfTz3cU>IiFDM9TQj_@$*J8@T(>RzXnUgU`iinT!Bm!6!^IH3k3vu zQK-;2JZvD3c0MlGGrXsK;S{Xi{)6GwMC*JL(CNYH{llg_cJnE%aUrh4tNq`2`$fq= zS!l~nP)8en!46bs(Xqn^wvI}4?5G1-pC09oPJMrNru)?2v}j*)*)zUuC&Mo*Te$D% zI1|p%@PD32&xUg)Y`Dx3i1&ScjT$;iHM0MdZmnfMwnSC7{M}l`o)KS?u!N3CLu+P} zY(Apn_J8{0OFB4$+avS{@~A~Y@M?XlRl=WZmWokOs<=Xe>U0z)W}(VNP2wU2s;Em` zDcX$-N|tfKG!3Z{1rcj;qO2LVA<*u9!$=gthf=-Z!cx6lELDo}Y*ZT7id`#)*3u;| zp*wy`MY;k?uf%8wS4!PAsYXmg=tJT(MNR8oh@afr_wEt_)L^hSM8L z!_E`>tnq-Ypn$0-A`@plfnri}l?p5^r3jZmfGo^)JSk4sg#(O%HnCp~I>L*-;TO1d zfBClo4X@(iBrZ_DloYW!gM_RM3u6b=SBlPw6w#9youJLIX%u5gBkXgcIZ}RhqpB*Y zi)}m7JeWyj0q!5EB&{UOvRdhdhFM}Pd{%`Tmtfb;#P&utKIy%&SrD8{LGmEt&k(Sy zy3%tM@gyC7-6_Sz)JFK#yVOVnA(KjCqND*zbAkAq6=fZBm%=jq!Bzdh6;dev>4(H zJLaL1vrqp4h?HR&18Gy_nc1nsVpE(Mu87iI?{A|Z0@chBMTWRXP{2|NFk%hqj7KR2>Vr{{cSqeOUh(%_QleNMP8j%NqfkTr z2pt5>F1F=O$VFq%(%&BWI7##U{tzQegqZe~ZVc+S*4 z^$|+SQ(M0l#x5G#JX)M?Jhxui*qC+kYuv2c#Dej(&fX3q+jjfVk>$M=7o6CligU35 zAw>4iu1X_~b<-{^-|fz?hbfR~t{By+(b(!P?aWM^(TQg+4%>~{uZN{#`RuP2F|hI8 z?Jqr`_CG0eIbAS6UG>8((6&1sfSA?1Ey{Oqc<>nMQgFOhty)pLSAIEu1_J}_>V895V!*PVONFGV4%1)B zoZ!$etGL$ErN1C!-8L#ro@v%6;}fuFCmDGdE>wcb-6tL&g<)LAe=30m@3Bas$@68)8C9qgw*kd=}{rT6HAS;0tGFIDvzNbA_$c)7-{6T zPJ(iG*VoNK6rHg3V%XXW(MwTNAQEV6W%Oki6Cu##A?P#0h#5I*Dkq_16ktzCzgihn zqJc{eVqvBjF*6DE-MMpOd2&@eeD~Uouw{7Ky_%=4xVNLv>5c)el8s%Pn%C4dRC=hs zcxQ+wRm-~t@vd}l-2|Q*F@iG^v_g(~1kqU==`rcqM_9Dx zhtLmWn~>Tt1^}~#_DL()2S1bfQHLmO6nkGGi$RZq_@rWx%qOyaD;p_{ubqVTJYs}| zvsy89Y%D?M6b<%v$mo&QoQw8^j3a)tHknwNHWkV4y#jW{s5!Z*0!u5%H7_^`pr=Ur zqOB^F-a3PW9t1(A*ei;Vc6WV5cJoPvxZ=Xc{a2he`A>eO`2GI9WbecJ_mWS|POO}2 zZ#RE!!@);Z`ln6Kw6~k_XutFEwR*6ci?XFGE=bO9Dpy{TW{<`vzTqYbsLY*^^^}zr zzaVT%36ADVWy>{{0pA*V2Xf*ofUr`Hg zOn)(%OK2O`^RlaBIH;HpHR1y-RFEa%L{8CS+Nh1 zBX#Za8Ru_4zG@IZT)aCB3zL6#ZG6W>z1tbRs&GyHoT;~M+;lAUZY^8K_t(F;yLk1@ zkB?uGTzbR4b4&Z%<%vC$Z+en@dw8nrE{uM7ahrRSb=mzzW?dKu5BEBp#GV2ga1{Yxah`TPtH318Seh-Uv>)DOkUx@;l$$R>d49GY(9Q^ zx2Ru)tJMq7%aC<@ZXf-T@}S{v8)THWM3q04$sMC%sdz?Nv${#H#-cwQwnJ*uo;swvzRc^}nmDm5@_-iH zmg{=?=Zpz(*sKnu^o02ekT@m8nbG-ueeV(1nX16-WaxYFFLySaJjg-Sh5c^dAeZ zP*8e0TP%-WYTpteMDK>;J{a&k9P@8(>q**AczpE zXEcyUrAvwu8xTE&5J3l?fzUw5!{E^ZU=%YsnDtJMEU6Q8e=K_wxKT)wR%v!Z!$(Sx z=X6FJLOnWor02j&w2{hMYA8)l*g-ov?G;2&D;H?iVL;IR^t%Mml7t~6Ic0iEWGYSB zFr+ojgtoq%yQoPVvk3=Oo7qSWVTllZ==G_QpzdIRq7gwnNd?A?*l5a$9!Fhij6eeT zA_*##@aQ)QU1TzAmVv@0+InLkgYLWD8tsl?e<;AlGBr_4CE-K28oS;-1tph_B^<)< z(4(kPr*2jgG1WUSm0d4masdiHT5|>KfEgF)LW%_x>A`WQq)zCJ771dgj5H6#2#ZL! z>er@y5FB_{aW`=aZPw0iz&&OBnoSt&TBXSXG1#WUw3=b+0HN1VBLVb4r%A*BicQ>v zIDO4>-v8UrmI^{Nm@~6G zQ1Qqe%Y<`H1fxK>!HGj?QliS3a?F0zY7H{feO#wA=>*L}uq8mVK`I)Z8`Lg__*N@$ z&=xtuC+Pc`2_&&la>HR5GTYzx1s^lnfH$k~1_a8-M+50L(rx~?CDxJX&E$p)sv7Uq zHy=}kL|||p0TID3`t;G0iFm3wy5+0*uIt%ud1SzOlSK8L9ozSgR=ANlY3h|1$Q+L$bGZ7B;IgVZ@=86ipM2)d>)m3NqG>YZx zE`GcmVeMAWM7Wdqt8(yJf3{A-A`5M#JTmuE?j{mKC_I%6J0K50gt%M#z0g1 zpNgi0!I(huhgWN2&1{0N@Pv@vNU&?yi231^$mv&*L#{WyY@Lijix>#3v7k%p>&ma@ zH+8}_E3)6oV$5%Pi^$-^(+J=5`J*jDF?0vbj0d_Lfn$0^kWrf16Lc^6kKoje3^wsS z;+~A8<`2UY;4|CYRv^eGT6WDkk+o18BhSsK1M{+F(gdFdSM|X6w3h$a5aWdRa6x^$0C7`NEU&Y z7%8y7tjH)QoCXk<(~yuG+DBw42@U+8*S|p<*4kuuwRRd#h=;Xz9tQh(UWGEk1LQUl zbgJ`!=w8q`Nl27;pWkZ2urXpUlwAwTmBQYR1{4|1LKK$+d>+IpM~$++cbmT!9}f~$ zRJ7t0CHw_MDDAT2s7=VEL_h{wiAdCov}C#vjY-tTf+;#Gz)*rEp|Ew~-in(~B*aF* z6d?CrAzKuG%JHtTHu|S0=7(T+?ecw(XbsLbtC?EPhMp z%n5x5nw@3v+yDM6-TK@Ac{qm-o%CMR+5O>hncs&^uw5gEJiuK0GrJW2Q|6^Pg|hSK zR|WB~U8+K5=aY`x69i4BD*Fu66VAyysMLq$S+FeAzvgv@fwT)6RxXI+k`|MZfq-q- zl1`*i6h#OS2?Gy>8YH6!zQkMC7#3Q|@e~n8f-*H0va}vmZQ82|IV3boGTqV}%qpJlIW9bFpA*;LAc_C(68^;r?$IJm2dZ^UZ;=pthh*VEXZ7K*VJqiKX z6$Ky{)FFh?&zV2YECu~ENEA|ChBjjZy$lz8u^o0pQLS(;fF!*fW3Y$_u~G)G8>8(A zOPvEq$TZV%(}P%h=4&|`1wdf4p7Z=f^epxa$y~w+KrFoC5yPWmjSM!5a;&y^MUaN| z1ZCV%Qo@!eQcZ>hC$fShxcbJ&ny88GaDbM0!q!b`rp`Ua99XhD2_Wd8i$(!A5b}){ zXC6zWmd%8Rn}=M`W^{Eb0ec{xVz0~qHNleJ-LwCmeHYeMaZfG}W0KTnB@anhbM;E4 zJj`wiHVgLBbR9GS!fsu~c4nP}V$oo3UK6G`8QH*cnELpA30R1=bx<~sux|YB1ou5} zvsei)Db{)eZ`qE3<_ISWrZvC?1nUe?Bo?Y3ryT$tM&O|#3=kT;z4g!LmabG*m+B#KIBzLoD{Rb7A9QCbsaAcSp64-PJqen7P_99FA~= zTm(z$132^|&`6dLlarbeLtOw`u$(3o`_(|l#Zy}X7ulcI0-xCN zt-Ep&T57Ws6xL`F1BI^1IVJ-kYc-=AiU1)FTYSqVK$GAe#kg%Shduq7Z-_HgGXfRa zV<>Hg7?5F{JqbJYDTji}?2c){v&lk_l+Nye2T=moRLKj4jUu<=!j(TEJ*LVeDyMPB zmh=WNO>&(*QD6W8)2L97(eO~1&PA~`Wfh%DlSviAs+&JZr$86QB3Tb~&sB}WNW7I4 z3v5VyPM^Rlp#hkOj%lnd^bj#%(3H?I;4L^&(Bk%iZ#*`|$#}qrdIE-elmE*FGR1-r zBvXyzOco@;fPn{m)a2W`VOAzr!55SQPXPkyThE5=GYEiy;l^Sg*BL05$odQo>V-L6 zp$2X_dUCjigI&k>VwvUor>++~hDi z9AM}yhu@DTbB-l|$x063m12#93pnYz$5Y2W*H6$yXj?7}g%FbsjZ?!XXNtRzeg8OE zLD#)s4R`+6Jo63aaI zhU3&RpHIq#3!WL(+U$b9#uYi#aB+BPr_P~!QQP9%?n6Am-)w~G5WzdZ=d9jzB^qkLA|)adV`95~bg{<)oVn1r=F zKn{5(pGzKN!~zv%9y4-I%eYRlSkYi})EGx@x)tF|H7ZD&3!~ar7fj>AaCl-uZMzrT zfyhUpgqcOHQ4HvSuJFQeV`e5PVslr;@;E0bjF2c00FEB>)Z9{aWZHCQl8x_z>?PHv zR8Qy=Mx?GT{s&y=@BwJ?Y|9@Ut7$|VU?(Bn2XjR_X-L39Vh(bc$SN^J;OR4G-g`r zuz~R+ibS+LWH9t3&rzue*v9N6lCO@LmIZu#i7e<6=dj^{3shn(xpE5OSJ}h^Amc72 zGbhv|hE+vGOc-jJOX|63Iy6U<(S>Gh3?oI>F~iL~NhvmVF^B}7Dv}mPO=1LO*=e`l zcLF`wk}3A-$O+e20!%sa0L7~;zN1I#oS2MR$_WVel3 zG0pgDq$?}{$(KDDXBszD+?$=<7$fI*Pa4&GuOKKj8GL=tVgi`%jjgjA;m^I3D1Urr zK00tdNDm;qc4JT*mUD0JG?=ef*HvOZIxWyB;A!g+0sN1rXmtNuAKQ`stHvXyJSc1xX%_y#f!^3#Q(v5W#Pv&UZL@eIbwRIObdPhG z(4fb=>lMuC48UrLI5Dg=R zU@<0{wsB>q4lvlITbYNoVdr=nsdw}sUJ!r7`tmF~2=3Z2BL33?eCotpB1|vNbxJs7 zpThrGTOLx6gkS4g+dx$K0WYqL2hapy;1*#8-U<(}&cp?lsVdD}=tTc@7am7nNCJI< zD44`pXKa3I)3XJ64KwZ7l4j&%4Ok*;sG!Xkg%YruV;QdO0ct>tMDiI9$QedHBKFu| z6~}3zrB$j_3t~RJ?f&H_DM9;#c4@56VA1OYEaL?K4(T|WHCsCS%+8GrS4>3VfwU5U z5-`UwR2(q@#uuy|XcQQMF&jPTMqwxTe~e^fBmos_!;8d~9;$TIHJC^gVF4a~#GhtC zlxVqbqJa)gTgaa z0cO;qTA4rsGX}&ZeUdkct^6Fu4>Lh1(3)bnPCL8T*$5Zh_W2jwfgpCkV>y$8srdk4L28n0sd7LgOA(Kd6y!FR`v5-TO%qY z6Kv3pYXT%Rpq>of2s!HN-oh<4!1j&7G7^1%HK!%sr zE(Hz{a_CMDxHIUfoH1^iez?qVc(xAkv=%(EDFBO@DkNlpL{|K}?XqK1ZV7iN!cDBx za~PpKR4q&D99(Inc8SGI$ccD>h`UHHRMn}c6j|fs?%R%gN*V}{T9E`b2EPIwbA=Zc z$%Y-WzL5v@i*)f^kR3{m35z=&;?=Nz8QL(msG*`t+I+IMQULwaiX5I>LV=RtMFtwln zO?W!H0T6XuenNfa;#{3Y%~22Edq#$Xx<^F6U53(-`N6U~i3WCcVgw8tcLbVtFpZLC zix96~OwbCJG>Iu7qAmiVdZEcXB1sGFkSNHDb3^>1rZXim(->beatZrWkz?tbtv5rc zstsd77m-Dx67(>U5H!)uC|2%!`{Vc2;J1F`*^6=ehqVuug`2$sN_%)-TPtalIAMD3-Rl4$cm>#`^FswzndtlkC{**@-K|?dh)t$@u;|@h>JM;CNf? zkJ?rxGh%EQO-#fv>Up0*i(2?T{NgFJzyoh+b_ed0*g1yFj_ly@$ISE~Y08rS2u$W0CXbxps8(c;ok62G0)OlRIf;0PbPrUV zQthakn_I_Y#KlYC5zpy4buH!MvF%PJ{8I#K+H?*mLKoDWGB*;jO%J|d&|>5u4pA#J zy{I3TiCEx41JCpV)Z#V*f?otyWO0G;h*gG;1R6=EV{>GAwa4rj>P^5m)IO9?SGrIC zxgNjSS(o$9VuL@<`XpD?!3GqTIrY3PWN{1W53rKiVeF5Ybeua#i4{^f-JDFBZnZe% z03Rbz2vK(O#6gaOYOt(EH^J2xu9MejgAF?P;1D#CZs_x-1{v7R(2x_GNpM9M+;K)p zBOw%I=>R?+(|HS?0$;sZhv=lpWFm^-+xBlV0|X*s%%Il6Dh;f#fT4A9TOwklqH%%5 zNUOhWeBm;fgRu=P=A+tb0_Xj(5)<0rH9FS$adwKAMm`Mbr z>M*5MN1L-Yfsh{Ajy~@JAQJ@e5UY1hu%uk0*jW6@4jhbshGB1o)zWZKTPVPv;CaO$ z*vq5fMltjyx5UT8gZUwNUT^bSNrBe|cxCJEdKIl0>_hz*=0|0?*4{C}L=Ud1OEcl~ zgVq$0_4%X#J{zIq?z+^Fx@Eu{>w;EL#X5`Y3z{2jvx688e_dYz;9U31r(d)u0_!10 z2M?WLf}Bcm?-g?FJ2YrOD#lzJBFEN#R zsdCCY{TbO_*_t!<#y)!h2)3Lk`oXTixIR(S87-5Tp}{WB9E-F|aMR71VhV{G*-7N^ z9%Wr2M+l=VC5&PWKh&9gL#(6)=Zc+pxFeq^#PMxnsV1lFJC>;sqAW_2xE)w-0K}$7 zTgbdeM`Laz#2e(32&vFPCR{jVd=h<+@bpAm94A0qD+Z@N zD{F-=Fd%LeQ1l)IO(0?d0Uacq;swkg6bh=0#^B^cA{FJ)WpRL33|(M`?!wZ?)ECbGkVXGyNg4K?ppGb%*gISE2mg>VWKz)@6 zIgPo;faYu+3$l);hu313E5jnRXsG>EjdhgVo;Z-oY+ouvKb zm(x2Uj>#+St5ISY`Jhv*B)mfWwqYb2`9VwbYgP2&STzs;$&fF^{uhuW{oeRaut2vR z*C{=G)-$QY!-#1ygN(R@VNoj>4D-myZ4?9Lr71$dR#^z+%z0!wQcH5HkO3}geY2>+ zOB{jYNt35-?s@FGpZJ71ZlgooQ^JsjtZWmkxR~+64MypS>jd!-;x0Bt07xVzh;7P) z(g;~AqC|;FY!iv>uFo86Y_Jh_=0>sYmsDmEe2_$5BywO2rHqw^gp^?U1A=4_QzQ^f zxCl~ohNLm?I0oD91nsu)T-W_*J&JZSzW|4e!89^ZunHzgzA0q#GH@jBpdeD$fo4jU zB*ioZCr8Io(g`{axwO+D2m=P&eYc_HG=(D#C>VtXOpZS=QrOmUT!;i)1J%ITjkr&c zxnc{grkl9Xaw5+l;CEF(DMY#;0tmb^f-_8f z41Z8PQltjDq%EZ=GX~On`t0{9am>g2Nd7Tb>^>dnvz*TpTv$d%+Ls72}bM& zk?7LX`b-nl1hhZ|MXWCZq?9qso=7-Byv>+&cp$M!ZvFIQ(>WHy8<#}1(0tcQ8OFsH z^2CAx=>ROfpLg-7AFk+g4(+8o<(4mo-q5_1xmgsSMccajbZb#7< zQJS17F={Zf>~qa;8IeUXen`(@7+MOE~W_~t-sU^2= z*Lz0J>tGaH1fd@cfL-Sk&5)J7IEbLT-uZznbg=m1pUTu;{DgxUA6hu6Qs4HBUwG+N+cuujnf_d(*w*>*J1=zQE58Qv9mB)Y%iQ!?A$pFE-bGcHn`*0&`5l3Ll`svG$jd(#O19v zrGO1K(wrQkr<`u-0QVGx=@kWLx*SiK*h2dLz-%33SDrngFrDO}Sq)bdvnGO97dr4b zxv-$){ue^kY(2O=IB@5>=qV#~B)=BL05r_RISW&$fKZDBCSp`e!{E|DPskKxQHFY~ z9L;9YjvsQnr(A&$uonBNtZr12Ug1M)4guKa z;-7gdW>jJNRd=4Cc*OMQg8P1FU8G@!C|w9}L^V-dDjypo3HX+9u)$dB6$AL5Ahz_( zpo1vUGWq%qW*-+j#9zUXM35i@ha9@$AUcchjt~mKz44}X@f62wF8pmM5cS>de~l%` z-U`!Mc0r>In#t#ttB#@kxk7tNPl#0O_ z>MJ`;P>_R8&v@Ya>VfHcu(t!nL5En`M92XI&8lCUNTVuKM$VV(BhxqDR4(i@svG}+ z5nCVzg2~mGe21jznmQvmMh`3;9fY>LJ1GRy&tPM}Tu8$X!i)LZVHh}Qpn%1+zPh1S zvFCO0=1~~N+n9RA`5~5+HUqHN#Zyy7@cX(p5jk;s;5*s3Fi0Cxg^NXC4E%6>;RLHt z)uI3A^!|g+8;Cj>f~mt7Rut8S@=Y2puuXz}0opQq*@7{)m`(f{<6#rR&YnE>f8bX! z^!`P>|0;(5`vl8M-M`#(?E{~)QKd(Rj7-|ScfYfBiCnCpt|VuJ;I zHwI$+u}fC^N6Lfuq4xxBPzMqsKOMfwJfld>J znIKV^FDP?198m)fb2Dbfvh?Fkx# z*x~Iw7}GYyBtiu_fD-mK(7*%*vd{?i z^wuOl2SV6f0pFLjzymki(L@FsJcwNP4KI{U2+G72CMd)Ipi<#1Q3h!Rc6I2-4Ao)! zi-!rU&=PhMqNQQ6MMTGC??^C4J7|R{;6cL&)??R!gi^UW!apk$dEI;ez5+!B;hE@L z0t5>_LKImDiLqxY}ki8vQ9uPK^&T8ua*BCdc7Cawf1#PlbIfj7fs zqfxy+IXg8ywJ%(7Q)PU6dcv=&uXFc3hbl$Q0_IHw%QbNL97rwhh3&02C9cSIJOtZd zBqoD~m5PXnUMkU`Q0!WX{1+thb{v5qxB+Kp9gj+%sVUSaizq-8Xo=L&18mi~kVd%} zItFSCc2OmLYXVfFgt27_qat)^W+2zkER33vVwDC)$TZPOH0P7%!lfAmx0j~sKujXK zyX~9jX`q=?@PaXbW@nW4c8m4XD>9yWU7Q)FVnTp{Z9C!2lIEkOfpHd=mavZiVzBDPUMNH>j=W^a~E4 z$qXpes#7fRfSukA)zx}+wsXsK)*)BYc{Z-FR4g_+3wCCn^@2eHHlOOQX^%1E>o7~F z)NyUKrZ7bckS0dic$P@o>9eJkf-(nuCE;(Q z!UQkiACgUq`z*_=i9Mv?^J%AHy zXKDr%LTU?+f+Sg)P|;!!c9Q9Jt__>orTUaU3#|_S2X4p_BWi{^o1k+9{5X(I_;Nbd z$mtDIvWfzbX(s4wL{V|`x};=!0|6zJ^H^ne11~j&C{!*LpLZeR1VOX<++1rFi ztSf|05DLVC^As#s!Cbw7v{Q+I_y*7$CLqtr1bbT&>M#{Cl#0BfXRn#$csD5Ab?a~hm@Kma-lPQ2-s((Ko96`wLx z#Yy9wgMtY`^jv)>fgD|e4xjAcdg39w_4smjE&<+Z!iXu@uFeSi& zK(q|B4F*zzhEtTnDcYc?dI>=_fJ}c{2^kQ50fSxvNFzwjQ_X3CN!mM%OC6~IL;e^# z4fXUM0yU*=9bTUqDP8zEI9MrkT=$X-Z1mG0f}DSJs~E{hK(oe#S6f+8bSMN}hWc!> za={lJfRQjz4y)|^f?f~Na?Y^o8z1%ckdX~okqH*BUr!(p5+X$i{`V)??gLc~jg}LX zVkF|r6mebx+~Ao31q%W$v_zpWYnqCV@GS@|9R&o)v@PW0jzA=RA{*!@S2m$XvzB;2 zVWG?+yjIxmG>W&KvaX?TzndSz)@#$rHOxWt!tw4wc77<-D+toF_N|fSVWy{Sw+k8Y zWImbYwGoR=Y!ZL=c0iIpA{~fcJj0m_#IwWL$6w|M1T}7~mFv}QuKU0f;ukR56Z1o$ zJ*!s{_!K$2U^ML0HQlArIp=7jH-JZ3M~CX$zuG; zPSAoC(8w27vhKtS3|DnevE6a;XRZp`9iisBU;Sgf9FZP~(5a9_H0!_xOS7Ityz)`V zLJzOdp%4W_hV=w4G1PMeGD5Xs$=J&y>{$3_uX=Ebg3(qS187W?eWn_VS6}@4Ds+mN1=ct8K#l>c(@{=@u}gX?}%I~{9Ep|z6C!+1tmAG^L}6Gqw9rD)}9 z@kb7YPkmXVPhtV{#ag#e=L2JDuwcP`(&z?3TzS#HL`;M+;!JV2LF} zFv={uyhd7N{{t@&my@;_BB&4#r)SvOgHkj1HbzMRH*QquIm$2WtX9) zBgedf?y_tZJ6eW>;V;V+^!Ue7sYgvF~*?S6r099xz{*oGx9V{b!CJ4Z) z(DZcyuaED84I>K$xB&|)Bi(=7CN+vLl!Q?diaK~vqmfM9s8pT=H+zK@GAIKX1|+bP z1F)McirO(k#5Gb8pclyFPpoT$ism<|d*LsFFI5w|Bf-8ReL#6-2tNXIew4D94e2lm zgC_iCPtwT;4CV?Bi1O6;6WT`vmX-<{%Q~*^YxtZ8LV+w}J^*zw?-o*3;}{ zsSUkjcu&GjRG+FjUg53tJ^0+C^sxIX9OZyYjS&OP$@&QgagLrGty&O?p;(L%C7_24 zB!ZQ2mKM*pR^D9bn7ay54_)vFr5VBx3{cFff?c}p}ha``(>(7=M zF0POOLv-hGtw@*$EXO#k3*wU%&hBz3LW8KKTvChNu9F0|Sm29EXL^dLPp7R*QK&9F zbVpRGCvrlx|F0zBtRp@!y}iPG8=rWLu3OOfvtnfGtmT$2P8^z-$Lvx^n9xK@|8Hy%7Za z=oRR;Ubd~=#Uq!#loCb?R>4DuJ#f6$9>)*C3Ltc!~gVzspfgCu5ZKF8P;66b5)47)Vz^pqqh@Hocv<4tzduNWTVS2Nbg zTdebKVzVl6p(B(g=(58M|+&PK3wk`q^N54wMTqNIxg^&|ePp@ad@6j>=#La_-L zWGX#$KxH>WCM-JD|G4wuHf38_~ENI^3+bF9AEsw+i~b+-s_NM!7oOG@O7-^wh9yP2qTu%$}n4@l-o}Onp+Wv zZ_1UC5P0x`klsyoP7f1-sO;SM_{|)$ZZT2#og?&cv4($cE6Y^@zgmCx^$FU%<<^1} zi=qn~w9Rc#5F9GtDvlAis2A;K$yYB-PbGZsLK55rpr`gi5BL1hbgLr|>?wo`Cc@HX z8z$Q`96qQ|%(^N0QR#nqkeiwsLxEsui3ng*Dn;9xat3A?|tCpxT-tf zs+yYdV2r71RgVT6uxnH;j}49)TQYw(iR+ebj|NBJ?pBYi=NQb09zzJhf3OJ2X0clI z8105&n@3*WW_RPYBZy!2!`dP2OZII5o5+DA1UUrqoPTRz3CV7<>$V{qhiu~g{%&>m zjBH2gHpzSM^FAqQx~uEnI``c3@1Aq+t-6n}xT1YbiHW0Hl8`ok(YnkpeJ&2n6GG2}pD3 zDI&aHlgkg0&j+v8&w8dy<%ewe=sN?hXBnX=?4pTfhKn-3CD1}8XA~M|Xsse;4Fl4F zI=+i_QD=RIFgavgY`|i49NWq`O{;;|p-zoxmJXaCU|&}_SV!km;_M_m`G3u3I|u+l zvP6K;R6rdjO1set#wsO=02M+hs51ooChb7u2n8C7_PTmXIdGN3xFT}gy1i_4ZWgj^ z*y+#wA>}x(bhSfJNq3!B$32)ft^f@&M<%r9!6gNpy$jVX{Z^0Qk1(Lqd5iY=K|&Ae zC>KFlN2V2HN?q*b2J2;`gP-%RyPK1|P+meE3_*i_V+b+M%BEAb&ca-l2Dr5>%k>Z- z#OaFtp{t%?adr=GI|FLg_5Mjrm5cN>BLJ{QXHEUji9W;r#TRi}a+QvCYBY(r06EoF z?gQgi;aDfCa@|=$@whBRz$9c)nY4kPov6>zVI`SlAT_~~GNZ4R72uA990FwjoA+qK zsBrK2+r`Tby@>oBu-#03k0!LFf!6}+e(4S`FVv&O`N0m-e546r71FN@fuFNw1h7wl zHvmD5w+5QbyQ6?q%Pcnl+;K$?C;uWi!FP1jKwDbPGPgd!Q}kY&;gyLDzejvV#5))A z)*;=WTHZ$p;p;r`5fH%7c*%tt6Di8L4WW#J9t1z)Bl)zN&oow8fsq>TbL6K^@Tvxu z0ndkzePXr;-Kgb}C$XOPfpD*5bZZ@Sx31G;h~Sb5O2fLu0Ch>A=m8VYp{X0Njf1Tz zY$_x>9&bj>L$6mu=aQ%X#nk_w*D(y=i}>^{CFb0&h;KXHjuNBSBAz@6ML8sn&<)i> z{;*D-%}V1jupa}bK*cBv!d8Bjry6R)t$qWA$t9nE{!zaFZjMKP?#fT&+yP9Am|^hb zFyda}DYGomvL3A<>_Y!>4?xP`7a&(z)+j(3KW|QM6G{_eE}3{h)Gcm-NHE5ukGq7L+-gXf`Eal~;p8?;IUMn_g=ZEjaWbMgt7!jW@r#F$*ma4|uK zE>IU}shl59oimHyq{js4k`)IrX+X@un-Du>aM8{9xzw*$+{76*J=3563z%qPfMndu z$k(VifO!a=t*#RBc3gAZFJr6x1h+8F0~(;uB@Q*p<%}xAj+R(VfHAkT{T;u+9h-8Y ziseDw!9m;5Y4~gK%|OYe0eqg40y#@j&oyuR-6tq^rGSUm-jV9@qGYq0S0PQMoOR{k_403i>py_yV8=o(D?-qh zjzrv6XC*@%E*qp1D?p+Fq(mh|2dcUcSC2TJDf4gcyI!QGF}fhAs^CsIbHN*M03p^J zou)!wi8)~aRH2#iH#kbXr3*am`G@S0pmGjsx`W%Ci0U`D<-UM(u4)25?1m$RewW3A zpWOAb-*ZCJOG!0_qEedYySu=Ofn8{L$Gt(PqeTW`;k!ZtbxR_EW1eT}zQ=xBb( zb@UZIb=3QIZ@ue(^Z!QTPr#>Vulnd~o<|4%?smeK!}fq6>hHSL?}={n&@KPX_#Wu? z@WRJMw|$Oox#)I8bW2{6LO1W?LIUzYNw;tJ*4sZh^Y==(r%TCm{;dsyp4(xe)~QDx z_RssHQ!jlxzc4r37cQCmP`Z#U+v~Hv_Tr+rvA6Q7-e->OdsXj_`T6dT#=UOx(sXfq z{F8*BUbcMap@$cC5u}-m?E}4E{%kM$?ECXq&G*iKaQ=??()oC2 zch7I8hvpUs6;E6k?s=p*Yu~Hhzi+ntx!K-(&1~iU?0xm#c&+lP9jScUcPW!vGAcoWxY!-p<5FiII?vT(29!XkPQxAoWhKINJvb= zpQ$yg;MnWm{i0!o@xBQ!Mp?+g9fDLR?}lgZPIL<7Z~gFi5QnuK7`!IJWQY6kdY%B) z;^mN^p(QzA4}WxeSUT1>2>??UR)Riq+qhM2k}nV`1h_78-M8Jn)p#txWhHK-{~RLu z@F0gND&rUe-T6Q_{Fez|mIqX#At-K)a#O|Z|NhKJBV6Sla- z?*0KbxwyuE(k)8=0{7_Vc1dGlOplqS7S?6_G`I8VIDW%Mnr%x?SCK;N$lHfAgAXyN! z!67;TQ{qT>)an(#RnB}3Yy55BNE^gJ8AMP8T!TY)Ll;QHx;C|d!0Z1MuXdf}Kt7l{ z5D30cL443GJPe)v=)dQ&NdRLv;~u*QtTOKIc7tgD^q09RxIkg|KHnms2nl%tWzQ2(-IBESw;QCPS;Eg9TyX$IML z4FX(D?D~^|76<}w;l5SN$$mR3iO}LMNY_3!8DyjiBEUWnbY^IHyVHM6G^k4^9i>kG z+sTN{O%PgK)EbPfaxDs}NC^n8pZC3!5d@4GO(nc6@kCBGb;j9Lph6DZ6sI!%4Ndz@ zaHy}0UD8F=d=qWbCR|g-U*zEWpMPxvs8rRsBCMTxLO+Iwqc0S}?z!0n#({kw9u|)E z4gVx|GWX7M4sLQ(cE%67IHhzHx#B|;x*!^Gflbf1U;}mKOKBYDQ{8#V7q%3SajGFe zG(kV)hK%lT_EnS@sWGaa_g9}A6^?bHz(}NkC~$0e(2hn$nNo?nGXq}#t(OnW$NH8d zfc?Q4I}` zMVr9^KvBWrD_P->9{u{c!}2k|0U&i&zf0Wl;K2r?*jRXp#8SDrB@@L@G{UW^m6 zIA|lnZ(f80l$C>AzcZQhho~r1D?5vg-GnYlabsLL(m8qe`Zv{vNR9c87-FkR+&6F8 zg1U>Iu#tGJpWm!7&Y80rZdMYvX%lgI-Aqe5<$^4wN4#*)I1o4M;P%RwmQZjyx?Zx- zsg?jclk(^5qvCN+N-tiy%GjcZ6o zWCyPa4&)lymUue@HM|qZbOrRmoJM4_`afR`OUL>aWF!z14Fs?paZ<2p6wje_Du8{( zpG+3vVN0E}1If1-5Q&YPHX3jd8ZVu`ce1Dy9?BrQfCh$+`sq-0SH)lC((}IjOa7>M ztP?GS!Mv&S9Glb-71XGcdRZz+{h9+~fgDu=Wf4N6w{@&V_#}`LL%wCVo~lh2DJh`^ zelp6a<7Rsz0Y6JIkyL+qeZogRl#N9d!3=%eBnMIrH54|=-a3?DHDUTt9o8tI0e5he zcydW6z*Uv2UO$;N#esI#jc5yYZ9#dE>tY<2uFxYG_|GpMHa*@qqJeIgs&Xowkqa=^ zlNGW6fZjf#_s&i98l?Foe>K9#iNpY?(xODWzcZQhp>Y>p z42e~T#U+W@@IWC;N~pkMH(ongj4L+)tM9<0GFt%C2bA57UFyln+b84RK!gEax}GJ% zcnofU1tOQl)&A0FhJ6|Dd%!!%+o>LnvqOSO(^7Eya>FMlLmG3zZP+8}G0L{dLO0T~ zya@OMp}yp!o5UImbL@i%3j8f@hg>i569v&%|J9QP6bMF{qykqZZZ;8i)1i+yYW?pj|TX`@T9>_ctqP`V9LnncH#^a%+5rMtp$o?T05bpc+Iq z9BHg$+};#r8BkducuTQs^x>sov*mHlh^yS)sLGbfKWF*WraV3gBNEYnO-O_=6Ha{j;H1g| z!pJj-4P3DSMu3*-4omkyVu|suPUb2pc%Z)`iIau_Xt5Ee5rZZ79k~4y6V8XqiIbFI zEX7oWZA3?uTUTJCxXJaWI-7-~TBkWdwSO9fV;e7s-hp&Tc`HTPC!qj4RR%vanLUAy}D~ayXRSlytg(anz?#wbPwQssSk9 zZWC@vA4u#Lk~=QmcWlB@OViehP!PXS`#_YtM^ZvG#>Rg6pg$@c>jYfOe_Op=xalSu z1hbq|y#LQ89laf%rv`5fMx31H!+`o3bZ4HWA(oC8QJ3M*p!T z8hRi7iOI&nL8eHodOE(24uZ-s2)^fTp9EV{{9>Kcx>Eszu`&>D#!Tr(@BYtCrg$#Z zR~k>*^zuM{2Y?|n9-W$g>_1LM3!n*Q@B`Eku$&k-F3M84$djVG-ZPm;P^t+eb`zW< z(7<(}icG5WZvSe+guG0!v;!_7Sexo6Ym9+&@}|B(<^Ih(M(vJuGL$!sZSa3^xY$sX zmViTv{xAHx`B*a1@5)z255&=QM6%t5Z`XBvgV?o=jB&!SKWYo99<=h>J90%)+Cp5;T zuPJ|L)ABgX)eI*f4AZ>(etWXC3v6<^9K=A!s2fg8APbTQk-7Zn^%Lrw1`Rj-Y8LVo z*dQ!#!VRXVhS2W+`h@F62%wxE3-A_#pffTK>I|Px{pn=BL^%}$jZc~DVazW{T-uGh zHYVFkMHq6(J>H_jir+&=WH1#EJnxbRC&P9C*A4Gm?YsD;p;H6DqsDo^F_~rvFc|T| zLcp9Na1>}%LKRgm;9q`ZGO=)v<~UQZ)e5^o#3{Jf|I|;6gmA1ACrEAtKE0xNC!YC-0if10;*$9RCq`C$A0|V;^886wZ0| z`tN$z5Sj75A~0 z6%9n!L8`O=PY#a*YO~H3pc;-hz^$TGU=%j-8U*t}`1GazGJ0g3|C^G(r(1~fzJ z-VM|AjXC0mBIf;0~gbsTNg+7k}$|-g&l}vltZNrwv`TN;q~#p zg-R)}68$a6B3N>T5nO2mZQNR)EI);K0a&st6SI{L{6hH1Pcf*KsTK- zq#2mRwnr!RnlQMoucDyCY5*8c!7WF6nKZ9|<-Z*^Io`Koy->0MdYgC1kPEIZ1N2>A z+bkOAY@ld#)x~_HTS~CvB?FMU(Qp4Bqr$OHWW*i9$da=xgS)UiZhb_lFkb(`)v>^B zR+1=*>u$K&ybKXwrar~N{@1^6vuLa{av+#5c^f4u-A#gtBQ@}VuXy`pLhHtxf!FW+ z9E}UZ1KAt;{Sa8!`}h8F^i3DM$F@(pl+hWXtzzel9e4|2Nn`(e zCRDzWT7x%mAolP8Ly3zFJr{30Fq!v&>xl2@;Awat9z!DpXh-7n4o(PmF!ca#&Uy~v z;`NoTYS{pU_|&dZ*;pr11$9@7FhIP#PvRf}mOCM>?Elc~#sWC1BxZ{QTcubLrVNM% zRyTF!-MDAMxy3TOhhhsU@xDB8fSg@(!J_xyt{Gk*@4IBxDF##HyNiLGF;#^dF7d~M zHmC(pkS@SHZA?ZHxenF2E^(oHzjbgT&`=fXmPY#D_)CiRvHX3wc#mP@k zreu;y42wp&Eiln#P<0WVY;ynNUmOp=VJ(cUn--Kha11YFxnyW~@kW_e^gi>{sA#Mc zXTcbG2mZgLb$G}a&>2O{5;W#ee`G=>Q&5a)ar(c>G6z$_9P$Ut4*u4##WBB~!1EDq z4Xr>NkA=Jmb6Rd)UjJWYW5OF$(+~s8z}E$;V$?Q#^jz}xbimk0DF=G&;NJSzlPO#zcDY=@R>cthZao7s<^~YY`{ZP+ zw49iM)4=em%jE%G$_5pC4W7nM8!T}CrX;2R$Yg7BTyhH; zb3XRgm_SfrX=&8U4A{w!Ot!pTx)Hi~8H0qBNVNxti}a-(PJ1+P$bacy^ysj{c;Bd) z*rklzmLW+VD-dOeAeeyD?w|L@139SWv>4d>Cx>Trvka=5WLPhJ5_g4^0SKZULhowoc?M4-E${(gUvCXR!DB zpZMcp@p#{;o$L^V76G=51sW0MDZ7;!P=t*oZ9zmaYH%=ON@Do$80p>m#Rg)LIZ<*X z9$iu_jaH(Pa!$nCetohBk#OvsS15UK&ejk%zh&%%GoONd&wm@1jrR>z!H&Udit3P<{cmM~rAOVhHs5B1huqhGvB~m+=aB}kPfbW0HM8Hc^qoImMw%qAd z668x|SJ5SpPd3*m^Qi->AX=LSLrNjr%tcO|(SX=jPQ0F!z9X|z6qq$UG<<26R}?Ra zeecf=%f|b5W(bh7pf1@ox(&Qbn<^3F>Lst+O0ZG2)0{BUIgN16#YhR25SNGUj0QQP z|7Ak2z?n9Q8PwPkYSNYxp3W|ps(IgEoP8SPo>}DbZyH*4Y!#1EKgk~>q?;OX16lu1 zUUC{VpIPKAgphYC8EzTE>5Ll;!Cej+bRorY#bm>*!x%A!?x(D~lBvd~isll`fhBnA z+6iMMhn1vvE5)7jB+vxXt{KW7+n7vPWIaPSQacDxcz8HP)EF$)g7&YQ{Ho6GbdL%-ZZ}{wF-Xnr7yDC*jz6OUxLsZsJKKhUJh9%>Di#ZSgQUd;zTQr%%^`;xz#Y>4M~YJ#{o8+_%K%{1;%k$(kVS4eQ3l?m zD)cX#aP*ct$bIfn6@8V56cWXOHYJh!zqB$e8tYrjnA{>y`B$en9CRPDOQ9X9BoO`I zpKM{NERyqM#J_=14e=K5L?yR`sDJXUV_`e2gl(5RzQMdM*RtX1k6iY)k}gCP(aiPAz{lENCx9h2E*$)2cyIy%!c z08U4o`>RD%Q29SkoSo4#1MmkjJ5r9oDyu8T%3?VNzVc(E{)}}ZWYGvAyM+{TB%R+i zuyg5^V*wjgLKtL#>9dq%blJIisHPGH&SacBq54Uw(KDAI-QtMKYjR{@94{AUyzxgj z8y)YAE=xa7sqC&fpU(5{c*iM4j&5EY z_sk6t&%_X!QmWDG|Mq?3LK@U_HbB-yQn}?C(x8h7!*|%g^bH(!3dg5?{Mv^-+t|6v9E)}P|ql^CB@8D2Riy@@*QPMlYDCQ zIQ19|*!=?=r(PfP*VD%PGB?C3>|Y-9{w>wyE)o}Rx#HHx5)E*z{};ENQt)m4_-MMP}^8wQx$>E!*Ul4(V*X)W1};#HkGlDT~x3~Wo&Bj zHt4j09J5)Wnt|W+)XS^%JxH{JiZ*M^X+@<>KLWKp2rSsNNjuxPmR45C5*9rgVn3SB zCHMJRKD7qiY6VC>XV?c|!;z%H)~ivx-DfUh&c+pJlL9gdGZb~bLa52MtiVZ$m4jLc z3YBn;B6yKe&#)iQ!ME0Dt?95mDcgWqHsE`(QS=v|NU~`ELMKkMXb(I3WHCFMm}sWv zdp7gZxRKDT-=?e9ay=Hu6BA?vs6~4xTMwlQ&8&D1E_?^tt5NYfI~SQ$ZvUZZ<(#v$ ztICNiBK-uNzWJZOFSBtYWuw9UCXd4orX@%y@u~&e++}e!jI+3HmTGKjtnCn&o0Zgh ziEUgE)%}{Ew=&q7Wrm$g-JXYJO>#EoONxNK7umuSP0Pe&cCoklSzWd=@AklrZF|_x z($2S!pZAHg4iy5|=p)$-;tGRYytFI)pJ+Ir1f*uTHgPdg6KK4g2mp#jx)aAc{fye>) z23eNSy>&>N1ng{-Gzw_J4oY`AnTCJxko{`lDd%ch3PKewbL20sg!ya^Oo~nKu6OXB z|HMmVuaPqP6U3lSJ@yM_BOpJ{olLlUqi_weC!7>0n1{gfOSj1gxOUtw$-2bOw%*-v z`LBOJ^1)mL+Z7=T4iNm{Ds9fBP`1gYOXOmGe*3OiSl7a|hFpi-M@6&_2@~D;om=)+ z>uj)XPd8c-MH-8Zm8<4oU$JupO+HUeHYx@h!Eu@{e6+ztJ|q!Qg0(z=nGy-mcAc}M zMujD1gvBGXW_#+cY9hp;-IYDMHseLp*t!^|td;$t?^Q5`gs55^gHoD717ucvuZo)L zhjy8T5|G`?8W~-aoFkVC^^k*=WPSw#pSj^6Njq-6Zq_qdq(vW4dzoE{pj70uH)JKr z11qR*w>Ybr4`5YyeMGWuwiau@0z?=DOO$_6LA<=nZmg8bZWzy7wU7N8R+G2dB&dy)#s)g#);|{H9YfiOJ&(}aIg_JO^ zv68c=XP5^YNr8cnW_tbYF9#nsA4P7ot*nV5aVX4@1h@Z}XhOkgsMbP)Lff^huLoJjLiUYZ1c&0$Z2+#@B{fdpEY?(cco{R?N@RJ9dT z-8Sdvwz{0`Z6>vusMuzF*@O13Mj9Cz?x4>8%yG=Va3)?#ZPwVK-BqJ)QwSeh!Xhr1 zKX#Li<_;7!_H3&K#$=x9m|BbNJ=0pjK5Yk(A8S&Q5n0dJ4V;043-)fW*FD~$*PZ&6 zHdz10%^!>EtzB_eZCA=|p_5{D&epdjHYOpGp>n3yzBF#ewJEc9i>ZZc+5s)Hal)qN z1|DJzz$t~Uw3Q;eY!PihDNIv_uK*nCYz&SdrqsbLK_eTz2kl0X^){C0?Uk)8i>_o7 z-rCt;v+GYD{{FmuIfUTvfWCKn?ZZKyOy||*09x^V)nA#zuRBEC9~ZYo9JfSlhq$D zD4E`Ka7mSIMBTH^Oree@Zv%U6?B1_rxw({v-BkQmYZR=~8)yf@IYOJ%L zZC+{J`@R!L!iUbf@%;zyJ=XZ##(ag{EjL#7U0QkU8&mamz3SW5c&a|fzS1+Ai^}RS zhg@(a$idNPBhuY|W3}pMyZ6U=%O=_hwc1?u?CNwQu8}hi8fc7Om{W)1XlkV>LRg!l z&H%CN?CN^R>u^d{uaov3V!zQp^)?RPTMIYd_-hCPL&jZinKg|V5CRFZoyU{_vdiArsht7&t=7Wb0{4+H6*v4%CmT!Q9^`m$SSO|rBhW)FDQ7g{pT6m$G zv;gtdY8ba`WT*Ztr5 z!p3US$Zny9t1GVWvK)JijJBE-o2jo z2WGon?pR5lxH4{JyN$1%g0q?r@oH5cU~REJfb$lcDRSZwR(A<@)qq5W)*vmLztRC1 zE8Y(_@RfsCvYaiy#dA8uX3X@u=LFV9E3=J#Z1QEijWhfI{$S&4DFf5oQNKPnW!b_N zO0RfC9s3TJ9baLlo3 z|8&nYSe<;JrWAyJ7L;X6?N{wsGs?N9O*d3H@^YxuE-F8`mw~L%)9bmmd1+0$bni`QDdbvhbA$pZq{^` z_8wb2KIl+!4>g&eoh<3dV%kkWj0OM zgI;YuISXH{>qTc#sb<5QKJW%23#<+ya8yZRc00{ceRQ~!8B0`Ogh|cJqy#jyjIdS{ zKeGftvRd+9g)^;c;?`ZFCygRI-^V{CKA+3XIjE*)*A(65WEIRCR(9b$7Of@$5Zw9HsQDnKy~eZaB7(+hzPnXnIZjQ-$=DpGK*qFYMA$T4p3#8qvOuJF?1_?c0_ zpLUB@?UVbalF|(=a4axS7VZa89T$_xvy%A0iETAZ>5ZioB6PaOcxST?+$O%k|D*>R zF>-<+ib-zZTct$Aii@Z`>-AEMA2|k)In%rDiRaM~0$N9xJs|*%ksKL#o8te5)tRW$ zPSU8gLu4d8<_k}fXfdyln~_I=6oNK40pIOhuY1$znv4tH-KB_j)00bnl20et6@0x8 zCW|RnGwrRx2a(1kjh(bM=ik)8bM<$NjA^wuXy!rr%@~cx-d3ioZih=$#xJ4$9c18z-YY9 zPCah#tQHI>`GGZCwSE=9wUv<)Fd>4{Ug$u__94&Kl4M4E&gYfnz##+O2~jKTO75-W z+InkX0aqH(dcG)Dl9hcGCK3bh4fkeIWjTgY88RKv6(T&+RnUn$0?=1Rk3>L@bi-$^ zlX6ihRZ}QQeRKq`hw2n`DB|crQm=6o;@4(nwY~e_<5NzB3`W-DAWqTKAWqT*a{18= zfr8>A6v!Gcfz67=kZoJwpXVX5G7v>zG>%3iE(;gq+84TMPe1QA8Tbd?>I;q1KUs|E z2=Ux+=P|v^5h!r=YCcNKK+;%9kQazlGe|sABU%Z9fXRu#nq{0rX9Cg2PMy-TE>eri zCt)vt;=(_{^c7t0M2QsB)M6ANqhE+WcQeW&_(TR^@ht&R5u_3T(n1!<)xx**#Xt_>)6^&8uWTj< z+6^E~07*42P{Dl&Kbk{mz)5#DdL0qqv4TU_!{DLbnBk>={L&wAl3o^&#EG zH65yqC8NN29r|Sljd{m&$(Bp+c-P%LtjGLq_{<0}f525c zh?F$ep+kY7S6YSaf*N-<4RYA+fBl9i!~(@rk}gVf3`t>WNF$~cf|~~cIvoW(tPbG9 zdI0Z56MZ6V`tKQ3N9s#j3h~3FbHjW^Wa)q41IaFRWskpR;7gp4`&1(wIHL5}>*!2W zNV%2=ZeMf#)GslIv4BB@6X6jB@O73Jxo#=#@;;AyUvV@eLD7k$!USGI-UlJ7`4XfV z_zHh4*b$p^59XCN7?N}|-GNx@03$C~X+w=#tZ6Ra9GwcgaH=PCqWPfq_?-(3iWP=r z1j~04M=K44R>}Z3>F7+ILh8d9D{vg@p2v_zY)@W##j;tChO4cu)~mz*_xYG2jJ>5soi?esND69sd#BUuB_snOxHDN z#-y7WP2(#5laEEClW{#*kGBOWh-8+ufU?izARsPeOpypkWuSb$AS(_l7+#2y>A6rk zkXe#vBwuWb;2J9S7#9y=i|ECN;dIi%%w*XWfA;)iySMp`ORIk4a%DZM&C9$b_Nv?b zoXc|FDAC_e7l1Y~5;*vWWGxswl$W5=mV5mnyAlJg7@`+b^OEEEZ^9>=AMgtdF$S2rFAszKGa^=@%VpwV@ZdB`jqiVeB{{5gxOkbHI8CQ|vR>ojjDS$LvtA~gzzqy7#(kA}3b=AlN zled;BRrHpDvE{GcD!k5`r^q=9H!3Yl&a!a~Pvp$*L(9Qai)VFqZx3vBl>|}-6@jzI zs{+nWHS|z+>^J!3G}=yC92=) z;%TIcUj(Kbt%db)qjeEcd8S~wSXrq&@tTeNT}NrY>De{%8DO#;=0YTFEYUi@E%9q7 zMG8e9Fxkb~(4lo~V?OL{T(g{Cb5H7R zklj!7m6fS0K7U5Gdz!wJ4VtFysM*9$>$AFl8|sj^4te>3Z4lm&GYMUj2gCvEFo7rs z3i1FJ+}9zyOJA%bz=XwfK|VtoVh(CiO$1w?YaMIY{2J(R9D3$d3J96g>;CZz>cv!) z#D2YX83RYq*uC4Qu~i1f{o9mxsRv8gld6v?fB}vQSxt`U043!lBoxZ*h#ihka$Bh` zdyLHlfleI+yv8EaOt6EgKCeq6;^r@%(K$Sww@H9?NIA5<>Vahk$JCLA-J}x3{J?UO zBXSBPXrKo2gaL>Z!GDl}pM;`JaY1sIq!KCUBIP;RDfL!Fp!Rymmhv0d+>0#02_>mW zzK}!PS9#(GTaB+Fv~$z*%B)vGfP-*hl;bP$rSnI(EsIogB`&7~iRN;Tr7!V1Xop#_zsuK7bmH<6!fU z4c_xD4Ubuz&NF2dEMofa*yG{OT{|z1%`y^~Q0`3gX=MWl)iUw{);l35Y92dJzD1OJ zt(-5~_PpabBDI-$#=Q2Wi?HM2oieo#7xO_hgUbxY{Tu$^O~)9uj`+1Hr_`*YH9+l@l`d@YD*chcktFq0z z@G3lu{|y&7#3MNqsfIKDqY$_#?!PP-4w-6Y-84VAm>2W2HU9G1#zL3u)#K;BO@$mK ztnz&DdA_@`{BcCF&fj+QpM23eJ5F-#9>1Y#Hcgi_YU zNce_$u#DG=!a*WT8;9~0a+9@L{4%Z(Ctdf&vl@hgct@6dUASITRDmBt=NV#gZseh+ zc$MJIC;knCCg3c|85Rc+OFRD%t-|qv1Ok*}Fj>Eh@zUfN>Wf=%@PB$)_P+m~Yi82m zw8iZhpk9owF~1o35pzepgeA!u7bG|sHnoIJxN|g^Z1Yh-05OQOiU6>*VJM+d1ua-l z5gCcWn>{DY=aZH2ZdD3W@8sv7uV^x7Oi;Rn92p;hc*-?WGI8z$n$l(_$=gN0;S|as(jQ2vdL)HQ{B5z;tXMl3c7*Sbw2@_J8)Zqy@ql<3620f-o}6)1c-vBM{TG zWIEl|CIaci3@s=^!tPo6E4Dp%mw^sbHYj_1JB{<0RlWWL9K9eDCbP5(A1M~!OQ%P=D zY&yp(mr#l-XLEJ-{%>97D*;6lfraVN)}oK_C7SkfQ!sle(UZb)mpd?3 z6}Tl1=vp)f6%73(ei2o&4DEJtU@r=LJ?;jN_`a9EfYH+UFwGXGP{J_x-R(ZBWRj&6 zK+9GVYY|_Bf+IB<|BxJLmqAJ(sTyn|`lG3uFv=^lwONyO^Mfm?vLeA+x^%_d*^LyH z7hhNogywTjbeGURE+Wa-D)K>Nc{9Thc#&zM{<)MHYUMIcg!4?b(<52{e=%K6OKC7^ z5E{ctnA~2x;r(auoJ&Pa(tmY{14Tsr3um_b!nW zFowI-m?%i34w;!+j0=iz0}mKOm#UZ^(bDxy*f2=aM^YFWOv_vw;slhxyGN!k=xG@f zcg)`UkIwLF3>ReF=!4{~iL=SLSTy&b9W~(i;ezX$F)863Rgg$k zx7dY%PYa1xSZv0G3=8P)VmenFnw1x2;n5!8s0;0W#TxOcrlkIp1Rl9m= zCkkq&d8iti-N8+3yOZKTjm+jvX-xarPQ+@>uGM5_8E1*;Sye$8K<1xvQbcXUEDtcz zWEs$R>~Z7hS86L2UV(BEYiMd`_41(8d+_d!_R;UZD{7|An1Qt(C)0Kp69POcw?83E zZQ|;(pEvi^EAd{2fw-L{v1K{NwmJh=wavnfWUWzIH+D54_*^qA0I@YKM6~3&u}U16 zWe|i-`oY1H3q(c9Ua}z}8Sa3gIk^%ap?$pD%~vYz#S;(KF*y&`lI3sxz+dC^5iuwF z6NgxfQU3P`me=vD>M;Sc7GLPR@L92uwVP?<=9{!6qqFXk9hPXYv*u;%q~q5yMI>$y zDI8Wl!+Oeyj1nH$Jd^e|X7Cto{^GMCELYYmzxfGP4*Z#x53FuyMMm?Mv{8RckuKI( z_mlBx*I8$=_we+d`7i95t+!c}F>hb&*AE<4ZluZjhvwcx>Ei1C!|9Fn)zy`3ck}93 z^y2T@V3oogGr3<=IKQj%z#MT}`j$hrZj0-|UVFs0mc2bIUnt513DHEyr9P4Xc(pEz z9b1cgd-Y!X*h4Q3K67m2*z88@^U=Z1`b%5K9=c}vvd4e#<*feLUujs@7tq99VAGnv z+P*q%G*`pM)rbA4#e#tKZ9$#1Nd3UO=-+{NB?@L6w;T?$)%I%II82;Mg##UzcOX&> zGQ5S>^~6=nDONpLM-K>uHN&q`tx@1BuM`LOSz^qy8ppbr+|LuSU(afRWA&LEJ~?X? z>5~efDdy|z#O&2G8mp_*S^dB&iya{I^}EqZmMrXMl|}~oc%*4#cXf(deq-q{t44%u zC#7xIvrdVW0)8x7gc~fJ&{3jvmnSeFMLwa6E*|{TG&)E?+yW^=`}#Gu|Dx~AJM&(n zTJ^Cx%gnMLrYO#fR+Z2bA)pbg6o~<3)nz}RPovJ_ja61x?BAvuZh?r%fVIYS8mw>b ztY00oK;jX~xQHBAZGN8kJk1G4h;Na?mG$tvk38S5UcHSx6)0?nA$TN!pUx|*tAK$n zWFj0&1pQ(uM7w1-IMB(~a$XT?^w9N({6oXy9MZMcvd9xc3`UD(jq;*LXB~fS9WE|7 zj)WTrPY@zO5!N$w*28YMp4|Kk(<~Gt|HR4^;m&x(iXD1eU)}CC)R+p|qz87#z|tBF zQ9Oa2H!)}r@K9@XuoRc;F`13)l@S09N0DrOhCCYQqyjb$zSZk)1dYxgYK2mmAM7Nz zf0Z?!$br`MczNqmy7Nxdo-9|@C*7mr3eQ*s%o3WM^LJIl2ow=eR18|uRk%?nJED{k zDb4^u{D+m?o+8c03B;uqT=EA0M4SANIikV5ekY+-7@Z&um9P$i#e05zej11RD3&@fx3HFj z5%BHII9V;WfLPZS47f*pM6t5Sgh}wga$d}UF)l;O&=-aCxa)?TNt@rjuuIVQzaL{z z0ky{Qdhpaw&D^$9@x6GS!Inj0_}=73h|EEsD=RTe3XY7@CS|VX;@e_bQY5;a9Wgkt zE*qrOiCeqjxdko^<_%IUUa!mAl3Dcy8~fs!p4UJ8`Zt;X>Q-a8#7MUD-Sc0({Nv`G zm;PRvAbI6aZ(RZL)txMT_>7i543$rDXXHo*ODUc$NAko%nQ8f| zTS)bG?YEwrI}c_yaNY_i(Jzj z2_N_s)Zxh83GRaK;gF5MX_0Q~IQeTx^>aAPmU~u)=gAFknZ9dOh}Vgk^R8CB^=Gx7~`j(VUbVPmJlZd~i-7{4;p|F;a|CiBRAoqXpO(V1?I>xzM~W*HBZshqte8Q!!_eSRIebHj3m^7d;P~ z0}>2UF$?Z9;tA}b&%HLmR`}cqTDecSf6VJ!NS`XrzcWXry!q>e4O*-W9Q&nGV!6g{)@4POx++CrV|^ zOlX1ER>Msdhv% zfv_B-L_acl{h*yIQ18%DImu~S3ysLjfzz+gghxMq|4Y+|9dl_#Qme!Q%|ah>Kbq3Q z@LjQ}HWk<9Lnn3$>8zWgS}APYs*ui@sS!D48TL~Hd@Z0^%j6?5O>H?`bA2L-VeulA z=xBT->tb;`YCQk%|LRN7g$8{+%9AP2Ok1?a6=(>Ghz!A@VFZ=7(m*@ont(zzM^VIv zZ+Atx4k8V)ij1b}^zv{1-p|6W+)T6bgFDlx4ict~xbsQaP0Y7vZ1YaIi! zUO;9TkIGVRxvj`3FSt!NxqJ8>^wgjLbZ@w98i_!|fv89v3FXs33ShzJEXTz&2_^&R zCaC!cva(u^FjVD$H5skYcYSd8tcJdx3;kHD*zawJet_c{0md}x29+{IFGJQ++K?Q; z;z+YfqLr(`WgV`o-~@!h6&kGY0FEo|@`T*Wi$Ieuv7^i ziGGwYt>KxJs{GH&HqbVKbjA5>H`V=J9`u=2I{4q+pzu<~D1a*}KXYSf65Nof)1s(mi4FYa1E3)y7<-DkH?pq-N`Z;(h8ZF5fh`+8H*$N(bKw z@EU%lBfO~vh9w_ZJtIL8fsqwQWx_G;A3z__!(nm%O}qvRwznW>_2_R+DW-^X6CyUY`1}teOBSIv}BR%^_@r_FRStgYks4O@?~)dOeT-Uhjmp z^~V>V1oO3s2Z|he7>O)Lx1k!T6%{7ydfrwZ|(!~C-Op^R~IWGZn7{WoH z=+T;5>~@((o@I7j6YM%a*t7L_KYF&swI?bNT2eGa7K(-&mjXfY!juBE`dmTSxFc`1 z>EIHfWvykni-Pt7!GePzGlGrBswp_*RD&06WK;o@#=Ra7J_Jmt^1s_S%4}*9e(H~2 zShur`3OoGQno1Baq>I?Rg|=PM4D#N^2YPucO{u-x&z34jsKVlfBP||^AR!R1TbV-A(SoDxLP_Qd~pwGTm2q3*;RbzK17Sp+5X;#fDg9N zPV6q5tGVU^b(4#kYzoWJ8d@V0lic%dMzS?fAH`I4QoN-ieRsdqcdicyjGlVi+ql-o zx2`f7X7C5W3ZbAydRqZLBb`!8I7a{hhUU{7RZ`;+zk<|J-v~Ukajoe?C{r_Z;uY#j zS7POQNL0+CnDD$`0}*7o?g&qd_=Az3VSu-}_LvNH#8e*%*yN` zJgVxV>LaxFfI!2du>aQYgJZT zY-Yy2NR|_mv|Ei9H5XWMP29nCQr9~z8EZSb1$LriWn_#3_PV`%er2}&VugDzpMAr> z8CL%Gzuo&B(v-LySC9pNdBEhF8+%(Cf2;bLW_e-!4iBa8;mLGn{xba5q%vdD3?(eE zn+PulellhuMCS8wfLSz$n0DO{bL0EDnzHPE0c%aqG;A_Dl&(uEvj!1x^3W{z^r>;> zz?X>`9NY$s!4K2JO!V}_c>OCbXC{?Xi-+!fFLiw)*cS1}ZVg?S8b{P>b0hoQ%Tfzn1QnCZ3oXoLD(( z;H*(#oijSff(v`KB{xrAhuWzH-Ns^6AyKAsT72vmW@~=kZz}AInZ?u!6c=N+$jH^m zcn7(URpx05QIg4f&63idplj(ug$XIy8^#T?pTv)96?_?+y3}EKTj4u}F_~Q1^!6ua z5>vG;x=Pu;d32*AQWqt0t&7);D#*v1`P$SG@XcyACeRWW z`+vFP2*jkO#>KpVaG8enoSt)^5n7&Wl@_fq6MV!)l_+4MOf)MnL#k-4K53kz=dOJB zOU|DU0h3TG_IDw}^_YH8W`MS)mlyZ~#k*Nh17^6n6OjSCJfuB-N^x%nv=mrYJ;B#rjWl;Mm80%`opGWAv?+2w@+bcC5}?G$j$h{qQB`z_7>k-!10JVAOQaEWjrA6x zq|@-zI^Kel;O3#+xDqx$w;qpPONIi}=nW}QcMu5EMqv1kamT0s9!CW|jeik?8 zv^1@m-jbQRpE7S`eENh9skU3Um?pF8q8fx?SeFXl110a+B~w&bRj;+fBk6gv$80w!?vWxBU}mYfF(mt63=L~h^xj_u*_}b zhIIx&Pi|t?T$aM{!UmYoC~|Uj*0Snmrp8LHXbv#gOM?yPZ9ecR2Q3hAkF~+`iq?Jv z-KeNMx%XEdwkv)aW)o`HYs59gQ2HN*)sPs6saxjhEX%4nkB!&9DKA#*1o?IJi)m7& z81)pvdf=dR2(;^A%0wWKWAP*eTqbTJQgy}R#KvsYV)42QxfvU4vm3Lu%2&VQzpht( z9@EB`5h(l2XcBR=)Va9Xh8Nma$GfdKI?D?5_+Y2{B4YbkllG<(+?et7!S2J;H`=CM zX~gyL=n>wFa6LhH`vl7aF0U}PZ_`F?N2{`kfqI2KVkZ2Cs53s}bU-6&`m8 zTwv~PTokTs@Km=V?+vnx1jH*Xo;f(V^A)|SkKcvhuy)Sxz&(x0c@gBx{6u-%F_W5E zicD9pzB+H!O{%5mbbcpeH8ZndVG)IzQjd;6m=PB|5_5H2a4F*8D^zHomHu5M7yH** z=->67O!~tkLY9Pu4X6!p;5tJubM^~fXNj?#Nz`q$y?XV2-ao+f0Mf7NQ9ik;-s<41 z5U$qnRalu6fG1BTku1T0@s+A+mjIzjR<&c<^?*Swxc#EphI`2tE@Ww{M$NJs)gN?v zH~m~?{vYY6s$uuM1M~0@tB&lsbc+zi3S#bZ7O;1C9$-O@auAbaX4G3S4xW0+v|$!_ z8>_ZhtxpHf(4fM@h#1|F$4+ohSXgDGGy>mbrG3+aJW{ABYAk_u;%n)tw+47dnK~=3 z_%g1!?kHN;tVR0R_n+n3BYuq0yS%-FEGUD$pJ5DU0G5Z0B(OdQdO2cpj@Hp0s>Zii zo&g)gln^K{sHx4CaE$WcsULa1Yl*4e7TFUJs`3IXB@}k=uXwwM;knvkN<73evlf8I z1|g`9hNT^~CkxFt4P`KqCI_~07@c>O*2S} zbUlp8%LtfZ$Ul9XLEEOj#&VxHnP=?Fe_S+spn#qa^q?HAAy)GZ(qrvQnUSaTB?a`)-GHrj#27^ITxQVdU;VwwdFGMtW*+*3H@SK2Lmw=o^~-)d52F54;`O(cv*H6N1ja60|JcGa z-gGdS%pSez;1no>sDJSE0e6>E>%+P1&BqT$Q`y5{{aGGA_}IdhE^S%#?=ld@l{bHb zfTL}AK{(4S+liLNu_C!?a~_Rq%MEAHWIST>lEJafQn>(`f;9wj8m;A^S~-@k&YG&u z=-K}ar<6r#$+8CBj6ZG~1n%=1ReRl@ejo4O^C6XtbL0cfD(en^o$qhC_u=0-E1GWS z)4aN_#`E;GqPdU|Q6>3Q8mG+mEZ7v&RBhqZtX4?X;r!w)G!5(O@FbE3U1G)v-!K=mQu_IG9!i@oK?)pG-4x z6yt?fc#JsE2EzblWaj0;%GwtJ(M`c*JVpxFYe(6=Or3Q1%5XjTr4MQv-9}SO>SmU# zv-}u_ER)qwm1K)syU2GFC#2kFjPaIogEG@a+O;u0v1M??)o{$DY2dpVF}~=Jg2^-` z6N=4;2AN8EQfUV>`K+EcW)Ckm!`n8|wt%1!ca;jv%Uc2>W^Xf-MbMK+Az6-$54g_E z8-r)YGnj<3#Nk;6X7n4m$?&~!cIa}FEGta&YV#ztF)=P~RMPy`>jG-xALa#*XM&4d za2$B%yLrx)uw`4tFT*SvvtDYWc$=UL7_mdZFaUbM$Ml*Wcj^x)1$-7sEBJPK&?8fW zdGhW%_v|L`VrZt)1lCuE>p?BV!>iIJ$#gObXh~69UM+Ipvihp126%V$)tJCUam<3s z7XBUmU`89sYZX}rMZm_=)%GESw+@NvF9RyHt+f_29O!OuBVgqY0yCR={a^nQz|$z$ zP1Xkw5#O{(lI^}FKEpe=anVepZAGzMm?}7-X)MWPKBtOXiJu!-^@=4K8H^0Q-0-K> z*&iD?Its3wpilEjzX!V7hlOm29B6%NanPIdp_=t{Pvf-cb@~~fbFWV_9gO7&e~&G3+|hbK@ni@sEKO2c&V&T0(x@Dv}WN&GAJKZy<)T70w)1(iTd< zHB@`G&@~Iktx8iGz?p*4%$?^vCr?{9eC!2BxhjpsEW~N52Mf?=AMP**iIavPTclk8 zgnHd~r!*vbaj_=z?D|J%Sgul9Ai9K4g`lNW^iJNcm-%NpEf2`gFTt~I;9|kVjq-qZ zG8r7`1Pzk|5skJSKvu@6OT(|cfokxCXWxMi`W1Bqm!9{uGKzqtU!yN9%&CWpfRO<} z%8dse(Wi(mRT!`Uhnwq|+fllc(zL&O?oBJl@;b}33}Y)*99>;kCB7WM#P0+;-{o&q zm0Br35IQ0k`dU-GfYRjwxaMb)7!bSf?(wU8+&lg@gco0Rfje;Xy$;XgqSmmu7VJV* z99(D?HF*Y0@+*+_;X`YV3JiS(*Mn3lp3*kR*U&h5>s?w&lZ%t@5Xhr3d=0oFG7~l zC#(T7Va=~K7vkORn{C!+vYEHfkPc0aT=gdT6<)Q2nMR;#6z_!?p}kNKGR7%5gt;tc zI?M#n8u>4aRM&V@Ou^hd!W31`#P}BT2ajS~@e_*ToP$U6Z+wC+8VEXr+Mea9UG0>d z#TgmdhvrU};5QSV99ydGtu%MC+@F~!h7i=asx&X_`N4$s^kLGh`|526xl9TYIOKX* z+aypymNj+~Q>-&6GJYS>A|=d3QJHNlBA$8BOS7!kSlD2V)Z$_| z`?3v&Gp42&8uxmQdpX-6{%9Plk;=cPajdZr|K-~n_CthI2QFnoZezPa99y)a~5{P_ptmvq6c zYkFE_T{+V1@I=4`3#{F@-i;(7!a8{ak_#cASQ*eswQ?V%s)wjkXyNr@cwzhADEQ31 z4;Ql=%zm=&okT~CH!8k-#xl`5HvG_o%4lo7HOftB zDLSztn_U-oF_%;@2WIgQ@$Bv3(wl>vyKP@7*zoy@fFg=>2s%#R~+0dq)9O zH+in*0+|-l5Pic*UOE6LFJ}3X^WD?_y|=U8+@$0el=ND3`2`jNbkh6_YxC1A2*|I! z85+)uA;j-Spkwc0Gau4l9MI^f!NdU@w(?rSOxXn-r{Dx)e8iBg$aXC}@y#f#&?P7b%LnQ2rKZGdC)w>-wlEZ(7Jn+>mF0o32Y|F}*R5 zBjC~rD^TtMI^*2(ntK)Edr=jk2?#CZcY{#=c>BPOcYd)7%shk##;_feHr3cca}+ymu+2o zza`O7E}6gbiGTDhmIE}+u4;R(%D|$P0Yq4=Ge2BZ_f+fEW{d2g7vo?uj4N&6QVPhM zJ7OkAam=IynN|;Mtwe~e427{N&*bSYxSchQc6<53i}+h~%LP!um6gX=|9AlJ>0jJ3 z>2c%xnCKuj#9Rft38e}7^e*gLJF7PrcH!hKRg0L_N4pEl1Hnnn_-lG~vd%oMnGfp^0uZ%>jPqZImF>brDAj<^h`GQ|T_K;`^*#(l1}A`d zw|{Yp`YB#IPs%R`CPR@T5<+BH+LahvA|k|1brGd)V=)_h$aL@;HRT!Bn0Sy6p|K|C zf)rA-Tr!VP-NkWg+x?WE`V<>z%X|Wdv3Exf*^*!hpSr-8CPJhnqo+xo@KDp2db5M3 zP>iN1Ydql$9RuZ`c$*@gGvfdRv{2Jlz$Akn?S(GkQ;+I2q;aEh^t}C3HGmVy6nZU$ ztLXr71^=*ut&a?kL1JoabjlKffeb?xXi~%y3R{RW@|GDE=nt3WxThV(MZBTbo{-lo;1p9y#z00n@@6Bkh2Ckw@Q(8tb~b_sdmpw0_?56mhr0%M=gIBg zyNk#=%g8d|B2z0#Ez1sKz2?EjY0ku899Q;3aq?fVJiJN$WgJejU3icpvnBrGEM0@6 z8zJEtf|L=;@QQKX&S+l`ZbTx8EKl6^dL*4{v&Xx&gy;2bw{blB#mfm5kSm_*tGNdp zEU!Q(s{qBI8W@-sU1iY<0<7gE7-eZi89zg8uxa%e{t*6!6L{yCh7CD2WQ#}-+h8M^ zUDFvGL0BZk>z{ir^v~on`*f&+R1$;8Q!qXlNFJ%hk>)|Vs#T)I~L)>ux@^K_fxA=i9|t@6pZM;o^N*VSWpuj++fz3g)N&yzRPBT zNwNN<7hFR=&}Wneg6KZX0iW3iG|R(VWT$UYL?zZVDs_4jC3}@!XlHR&=aKxN=@fJ= z1sn?Q)+LE?w3^QhT2x;`VT0zO8X;ZCc{fJZ&3Z^a7rPs9xPRIInbqGsA17-y7)^J1`(qwr+pbx` zp}|V{=e_QX|H#=pWqc#l{bXooXN=+b7{QOO-GK|aus#~q!5=h5dC;SkSv%Elr-=nn!X)k&?`Y|#k1#W_vkvGI9 z*xNBoZX_UCgVnjPr(RviNsIQ8JeGgVoWcML8<=Bbz#;=ul1xqw6DNBjnkH>(Sg4)R z8Z(ZG=%oqUc~BS3Z1|Thh3FOw8%xm7GlXcAM(%b=)bMK+kv%W~#?i90>r5;ETO}4!IlR>aJ z#vp>k18K6TcOipQ20o|?Ta7WyIQUe>OTpG?XS|OfQ;=#b@FC)m7IGGcTuHkyC14-@ z>7%T^QA(Iinf2o#v_a6CBnkKMCJNjk*cRu(;Jb;aPuQi^EXF~Uh+2u0jUJW8HUDXs z$Vslt0H#d^u>e?vGl>HXv?&?5xXz;{CGa#UgNi`-jK&~=Q+1^wat&Tli8@%qHxV`g@ z>luA&J5xLYjOdN}{7jtUjDV`m5RC(hVH~iA0apP2>FHUyeRxTsSz$6S*%!B_r)J&$ z?T1_0bE0N;&tSQ_`O6pqFJoZ59&y-J!=|ug+{Me!85Hb709q*sI97SGpDqV~IBLb( zDw}hN(l|z{1kG1>;=|-)lMAYlqEfH|@w2C2}OfYr#Hw!7iu07F*#PcEpF;T^2HQ3*1Q@0wIUQ-gj-^$6^PP z?Q{kE!_Au80{20lV$yfnl5r}+wXy2}do6YjM0s|wvtyAp&F4z=H^)dKrmgmL=9 zqo4UB8T_(*+ua40z0V+D996^WMV#qfen}hTE5}5%TZl|Y3)#Es2mrE)qg%FV9^AxU z4cR;i=06Cf1G6q6Zx?r`!?*?pFLy7W$yg81U&+2TMiE(t#-<{Q8ztEb8Qm7+o z%l5`)MMgT-!c3#-!XV{N8$z_ErYcB1q!lrxeu&fP!^)@n+>}B zASk+$73dW^7LZ7l_8UbDs*_Ycb#CZ(&B3M^$qV3))D#&gm$%gsMO28IfSUFyq}?5F zpv!8;O&}iy7Pn$?Flc22kxqxr|> z^kAgNkzq?Xbjkpg#ZbU$qC;I+nv=@UhD2_mrtsMdl`%*&*6vV8^nO(vKOMz$!v?9= z9MY^-2}?Q%BnJUXE-OG@KkM2%g7zn9eox8oXA8y43<-|Ufdd*a1?%2hs3AdWe9)pQ ztmj0%ncN~tl}u7Uh$J^hY<&xMP{R;{iv`CXw+&kk0>C89*@8PuYx42UE#Qm-@93`o zvZYmLxrcc;_^nm;u!=!$R%5^ze}g$bEPmhFBG6=qH5FUg5R?~GpbV`bD}hd{+8&UU zr6FKI1T{q0_$6LUk?bzY+1GJVud(N#yohHcc;wD!6%2`SWL!u~j+9xetl^$O{=>^j-tK?ghmjJUKxN*FzLdr(L-I zBO-75noQ%W7EA=~f*LoL#t3b`PlJ$mJuJ{9%!E2Evq)%wv% zTM?lfzfHhLj-F#@J{n|$fLA~Ix!u?1csn%Mv&(!3@5c-SUD9dV3XA6R zn6{hrk+?+q>FgE>&GJ%KVsI9dW7nNY_L>M8Bc({;<)BlTA|wq=dX;R=MO5o%1@(J+ zf6*;&_r8zw=H>`2SZfjek@B4Sg#vuS)wucHTMji)?m0&#J$nyT*xt@M$rv^xo`NU} zYQ zv-!Cd-u(~Q3kz0e$v`$9Z+&#<)$BcAVW_H&Ezmn{=@o-@8cWEA3v7reur>BDL6_$@ zAyC~^>KeKx-v~T;h3P&jin4j>U_1&I0{I5oOBhV@DbPi;YtKF-+JpS#*p5`2LdjmI zvVg=|N6{Ti@KsF4O#LCRu|nKlRwZm5lh2-sL5HQtL@#!Ll>%C#CniDEs-)=b94(Vn zQmNtl=M+;U8FG$lW{;kK8_2P98yV;8DE*+P3o%KDe;GxiiKmsW_<`jC8Cp1-@hy^D zz8z5$-Pdx67LGgBnoDxFjZ~x5_%HuKRFk|CDP*QG4F^88F~=*F&_^a0+ZqITIb;^4 zICqTqEW1?(@(V5nin1Cwcqyxc#Ff&{3kON{w*NR5qXcWRK8D=XJSLMv%)+l*y6r64 zGZQpovNyWHo&=+TwI*&16@&#vh((<>LMu7nRw@Ie4FL^XybFMg%NK&f=n7#_#5eya z&W>@{X&-QG&VVH`=^}a!?gWR3o2+N8`dHkR{|scqreD7KNy;TsrPZzXhV2r_Y=Tzl5}w z#tb!!@?NGpT3%0DlN@R^6_WV4W`L&l29q#Yp+S`fo+lU}`n0p0+Om9K<}vM_RC^cx z1mhCZ*d}kp84vt)FtUQ;>1*TL)YJd_Z{L76< zj3=*PsuagwuoS=+pA-}~djHq=sMQoFD3C*W9L-`DD@Iv5ukN#_#cGE!qRf7D5p6;P zfEOGixRlO^!W{%h&$B}WTeg37GEuzuLl%p^O=0*X@sr@(VVXayhg-8Oq-2+D!ED=8 zXT^!oS-r@TkWR%|#S}qFgzYc#l+gr6rZCt0gYQ+nW!Z|kv?eZ!DM+=Gh)hzJ3d+9= z$|;L{X) zHO2Inu1GGuzyJh`ud&q6*3|`Av+RDW(}ArG$S(IC zp6D=*=mbU<;je#GNL?zj78YVAqfjmE9eUliIox;DZ6S)%cOs(n3R?;lBD&zqCYw7u zb>4aE;FL&Ni_+NJ*puvO@Fre|2l}U6(lMf$5?QK-Q=ub!9`?ZGiyR}St8~?G90Ebi z!G~=b=~xr+8w6y;TWPwZcf7Gd7Z}5%!O0Hu4GeesCqvsGNMkdPW75uNHVF+T;rC($ z{&VcMA3a+~Gjz`8Aj-zlJVWs=JBM@0{fMVOG_q6S9| zzHk2_j-M>3l>gM{yI0V>Y?G0yG-=)O65o88wNm41*Qi z0$A_+yTPTuau)mEq3gN5+AQ$^`zF3D*o)GISx5)k_d0wb`(|H;Q`Ah$w2SdeC&$L0 zZL-?$Y?@Rp4i0KL*t23~2?rq~?*L3ggs~3##xh&_Q@S$*<|@7SzcqQ+lD6ctO%>VP zq0ZKN^`HSELWS&o?LP_jY~2#SBHO|S zB!-JBOUpx}4F1HG0C~|bb>lB99Q{>JC+*0{Gf5x)h5wXXIjJQSV|&MfgO#mp!8bVv z${5axy@~)%(-g!`Crd0buLoPd%u3r=KzlY=kPqd~CY-4E8{StDgBK#i0|&G&xzMMFcsmQmopJg4Fy z#e-SM>`xfKbvo?QketwlIG;w`X}`hoAf2O)$c>M`0(?qltZ+H?XRkoEny=jlXh`Vlb?GlQ2%)Hx{QvA!8moIC4=litx;4xnSYbV$hp}%Qh|9FN^&y-GuM`zCQ z&V+dTx4d_u|DMHlFS9o!^tOl2ar~-QWoUnex_?LFC6gN*^ze?E{?U}>YaiFW+`npZ zUETXR{5}nRj6QvWSHTuRoX!!KYZg+JZ)|+^{(p8|?#|}$$kybZDZY5c5Jx;KDEQyv z(k|S>FpIlk)uVt;7ABn0*x6IVlMvuEwB-_-r_j8$dFkb;cjJuwNL_OL~ zr-2cezBbaKe!NRCx%aZ`wL6^K!dsu{SIi$c*H!IF7Dlif+6gKu-IP90pT=awHitz~ zotXQpM&JxHySX!KM?d$nWY3+{Ai;-$B@|}+y~@{ zdcWG^L49qYIb5as%yAeq=aa5)81X|$Iry*EQuGC7^6MU)3c-jeW2D!uF8Oa~{A zz9@n`WCXPYUoAKMnUO&GNKsHK;hXIfsR$?v=29@FCxs~jg2i1_hn;26p@Q^hzoE=A zwT?+eL3LjWxlu+10vec>r6%ECDEM$PQC|*7D3XSs;nVY6HBTv)>2>nWO;?L+uV*hb zkc%B9bg@ck3Gn2rQroj27`ia-(}r@$55Rba0m8;2w%N>u7#}==caCQf~)#L>= zMv*;C<2)QQbC%J-lA*i_ok5%g9%`hF;;gt>KsBYr3Y8H4c=?rq zz!9<9fFDHK^Fn~hF9Tl3J7v~BC`Rt{S=|9_I~bebm)ZUp;u%T8!U|`GNHCw8P>uA z+65e?Tc-gi&7OrUT?r#@r~z{gc~E0OK=q(dC@4HhmSajB{-`o*q8LC%{>fOF!Q4u$ ze}B=vR0aOQDuuvhUDR`^fCxdCkWSvu5ajp#^*AlwK7ey=MpbS?*|f%-OcW!pWSydM zkZp|Y@QffBT?E0%3AfS(^+a8CmP&OQlC7jgA=GLU#>efs-e>+MSfcYbD(vQN{G~6r zn`ul0EoIbZ@e%l@67X0RQ-S>W8(a5|LyAWMl?*Cq6&MZvbk#<2#kO&qAg+;*Od0U>nSjH>j!`U#5X!UxecAJ_1pw5G7*0t+TCOV@Q{;2Uw|N8np@qBj=z_$yV?+Vobrh;LP6ipXfRAfp8Jo`RBWV z0|)xx5c2q14j^-(%yPlIvZ7T|0oh5{M}d~6b~k@?;zs(Du0*XsCJ0QEbK~Jq2Q@Me zd_W&i0*YJ*Zf+T+26B1#4@?15!6?>IWD9YhJ7FbrI zg|1LZY=4fk5)v0g7B+-1L=}{nCXZe5{qYj+(iz4=t-fJCy~#Yjq*SxQ^2EwQ6xa40 zh#NTRQcb6`V4~J}C5i30WH``M(Agna5`O+C(#&jBL9QJ0hoQ5-;=~xaiB6~rb2{Dr*2H@D)+Bgly zNg_7f}+IIFr zh3%^lG7vyz@iV@uSzLdb9ESLH7BdS42@ATAeh~zc7y3x@AUUQvb=H@eGc>>lwnZYs z4i114t%=@G-3}xMf&|A&tdA*e+;z3zGVjX-ub_%l8qcc=OH4B9#(W%BFz~DvPErcZ zc7+>gE8+>WpUve=i>Z{&2Fi}5X`u)=T^gH-e_n9#P5@rTO0}`3Ej$29Ip9bds!~+O zG#W9F?vhaTDttMFsZvF7&)gXW673*}GnXC*X6?R}@hd1A<`IC0@CfXQf~_CU^nQrF zPM{H5=KfF5fV5*ElTpu-5$bTSpMGbO1ydN%mY#>+!|x?UTO}p#!!vkLYY)zZ?JNqg z`C=^3lG=85 zAmd5{Jk_RWMNYX_-|>d~7SW{+rVTbO%Vh}2MrVlw>ubU{`Gq@oUnA@BmJcV!}oSr z_sYcyr#TKdVxZiX;X>~%*zR9+SUvNgZ{=S)^Q2$iICjQ>-`#=dd;VZ-DF_xTENy0Q z#O)XoOz&f(ht2UOgRni$r;B^i=Bk~~JL@cyZS3hxcKknWtdrhQxh*OT>V@#D#A4X!7MqD&el%=9LVpCKiqiyX+zk18G(!r zF*kwkx+1k7CUDv`hd{CejzN#4MwF5w9}NVY?;ORrj6UuG*XD8gw(S56oe^QsvvbV!AL=At%Jl;gk3kk0yOmU0P-5`m$sXSe2nNo zvVlS>bOqVtVxD6RwHc(AB8@_M-cKfMg|4W`(rYS}r+G4sfsNdod*tdZrT`}hAh{Dz zFHO@6m~A#C8fPt;(-fWvf(2?4S)E{TUHWDUgD2qK67CXO9? z0@yNH#%z9wRe%?4jL|d`W`tLGogRAz2DR4V&cSJ<1bO(5_HYH|VR!LX5h5AASB0r+ zVl!hnI3Nf<_1_?zh)QvhV9Qnk3dki?DGOun`JqVR3v>YKQkuf<$kl-TltJ9k#7eq0F*XimEe2z!McR$$CeswyFdy4Z`>PB%1{gTN}3~?MWb~bt+J+Gv9m$VTd$fK5^cCMlp z)4z&rj!ObKYN?)Lp{hq&asiHME4wClY{^ zVujMV=Tu^FSWyzny-R+DAp?@iH)_@5&R+&F4!VLtyzd)joSZ14JXk17oq=bzV$BKF zFOn$?e)(^Ga*;z9fIPB*E-!l)wbxV-(7xuDh9^-Q`9f9j8(r~=XN!nn3)eISnNTi9 z1coA(5YvVtghaL-d{M>%1qL?Gr!d%BxG;Ne4r=j`zpnbiv(jjRL;WaGpLDU#h!1U5 zPYq{q-$IuqNi%pWnG@$7lZe9Wynj`pSm!7wB@O*(dP4SjmtgOf~KGT!t^(_QbtbCats|(x4{*P3dl-EY> zE8b8)g0+xitS>h(e>4$2m$q+8!ewu+ldE?0z3;~SJYO$lm)j2PeaDQpG^|%%>U650 zd&7?AN0zYq!aQ!0ZeNBW-VED|FU+v(qhOb%3T$$J3O~WVB`~XNbHsoxt#)9Ez1-cB z<*o3ghYm^-Qpf4Ao_}dN$baTv#qPs9jzFPz?5;9rf0I+1Bb_g5j+Y$uoBzd`yhtF^ zTKM_-a4b$Lj3C&#sAq2o@OfN$)6 z|9v=orqTDWbftR(N|E5on_w{nYwz|?KpriIkQq9|R6PGUT-7us0zhZ=H*JaB#5%^{ zH4MRsl>~aEo%qnG>It&rXsld*GS!md;7FAt2D!yXwfmd658AtrFm)~N>K(ZO^hE<9 z;q(vxYZW;w6Tpi3GK}qDLAs2|EXqX?#1d1;Atz=%ewfgJVHMvmw*)>MqT%I0fifdq zqxbhm7@FkPKtGE0Q6Hv*^Fz_iklx=9*YW{bw=(pJCIjqC4O{9Lh^`~Xr+O5VR`G!B zr(QD8)n(-p5p#)y|MVNYFKSd`u&|Gpt*U_4!YJ<(s0d2)#O)K-Y~;fdxT33#w7HER zIUSi+l^|yS!ux)k_SEt%L)X3lugj!a?7X?Ig4R{d(h9I-^4fwZr7Vb%1*IO0a~Hho z=vf8raBvLGJ!jM^jadpR_{UJyk$bCi%&VaT4b^}(@Il|GMMNS=AK3TY6>-%xr0CRH z1Yb$8!3n_1hC^ZZ*d0s}az4@<=(amSH)!8U?GL8VRWtduIp)(D7Rk7RUV0eueG7B# zd9qw5w7~K|9OOji%mgt8_5KjXnei2~w+zZz@{`n{OiE++y$GTV<-@|b2WsKH1^qHu zK}07<@BGMxVkxG|1gCo>`hoRx!&KUp!j1yPGWAS z{4cDU-AsNV_ZHgQnKKU~{dBgkv&*MC*?LaQd6w&)~s|nv{l;ih6?zkVaB3=~~Pv zBo&5d7&HR1XoRRo`kMObK!)Oq0;$7I($Mr=k%JWJ5OLfS;P76l;?VDK?=PEDtW5h= z9d#d;20E5G4{kx2OX=X!GD(xYx}_wp!n%KvAEtVej6tzNE|#m}UcmSb+#^52A$fMi z<*$B>JocrhwJ}zl0!afnyF~2O@ZPJg6wW7J!t>bG&)W|{*4bFSty|&uZoy?k3$PUA@=s*(6ASvC~dA3EWd0v2F0f z+LfX;69y&6wxav zC1)NXsQ;hLctrD)FG7dR;ukv=bp;sm z4B3|!LYBFIzUtJoc3nh0gLqc;40b-IdOq2#y*Hh+ISn$XnR}o7X(@LHi92=ODhTeS zem2%k2SvBW3nJ(iT#~7g@AY&mM7L?^mV9~g4(Rs4%-y2f zZll|i&D#5`w|raawmG~dC{JZs^Sqf$r*4gA;#qffyvtpZW!DySmlwZ#X!qsCEz{Ha zPfp_NJ3rd-yvgrciY9+`=GLA43_no3^^NfryC0f~!(E4po&V~l`-+{_59E`dold9c z{%msT9h0}eaJoME;_RPZA3b^?J!dBSs=M#T*+*B3O)unAGq+~jKYgI^Mcn_ryrgj2 zQf*KtlB^71Uj*n4zq2Kt{qTVYW-fCVh3O^k-r{%eD{A-Mlw3YtY&$%C%jC-aB((N1T-aFZgkLfofBD`6)ikZAu-V+MRWis)z%5q)MG4Ek_hPMS_iZ z>{JOhqS%OH11a!S)*lBVd^&+60eh-c8&PaTu|X6ViHkv085TC8*f8o0iW^aE5LJeS zjVLyZI)may6dOd9VPPYR4WrJWxDmw$QDs=zh+@O2GbnCEu|ZTB7B-^TFzO778&PZ! zRfdI)C^n2bgW^UM8$^|1VIztSqt2kX5yb{kWmwpVV#BC2C~ictK~xzQHlo-t>I{k- zQEU)ZhJ}qNHjFxh;zkr3M3rG-BZ>{9&Y-vv#RgGjSlEbS!>BVTZbY#`R2ddFqS!F% z42m03Y!Fq3g^egSj5>qjMid)Fm0@8ciVdUAptupm22o{L*ob1os52;TM6p3s85TC8 z*f8o0iW^aE5LJeSjVLyZI)may6dOd9VPPYR4WrJWxDmw$QDs=zh+@O2GbnCEu|ZTB z7B-^TFzO778&PZ!RfdI)C^n2bgW^UM8$^|1VIztSqt2kX5yb{kWmwpVV#BC2C~ict zK~xzQHlo-t>I{k-QEU)ZhJ}qNHjFxh;zkr3M3rG-BZ>{9&Y-vv#RgGjSlBa;V(Bny zJdwEG$L_FA<=K7GU$!qTVA*7tJ(m3@#K~%`rRgWJJ#2M?NO{?2$T<(m+&6yb+7TLbawR^N!)YVnCxEE7@D#-35G~70UzKk0w+>L2 zibo3J;;^WSVV4TAk`T5fu|@Nx<88n}I~J3W+&ad`jz%Hs?wiJRLMVGnC+tSeVU)2F zajq#R9MZ1Ku|L27 z$l$;cM214*vQYcn>#!U$Cmh|!4K>yl%K&Jo9v(Odic*{;qLMs?)G7tHVed!&Qelz4 z?1&Tn0zy|;`+8fuQ8ouK86}}6b@QbNgeQ1Ei=NpRpQC)(lJ`@;cZP@Szf&q=1!+fd zE^uW>YJW#1!QGnL2%%72hKUi*^$(N@g0EcvTpufHuclIM7I;#Sa;&{T-Rar+?|xKC ze5KDH{!wT&>m1EUIsiaej(6ZGjbf11*6T!Y-VU++_hInsE8zn;Y`|^`E=bJ30ej@0 zGq$mFu%Kyo>sZ{*kwRT-J)Idy;dPbC`Ducvvl#VD!|8_@g3DSY6G~E65=4R7`@U~- z!YWm-)w8U@5iXpvtBvA0l13-`>ZA_p$XVDFuWCUzCrVKql=0wb4g)Jx+%#t;!JIS+ z1*C;aQL5gXKO=0o<;<^G$rbABuQZPHw^g!YkX}0HM}19ETt;qX&}A7p49bqCR_a^+ zje-rRm{ku-WWWVLtbZKYOQ@Ex|E1LBmgPZk!B2&;D`WVLxOE)XAqG$N}#E3x^!BWVJ)I0okBsLJiq+`j>_Z6 zST^p5;0TNiuHppZ3WqX)CBnB>Z@{TK#)t!gUCOyfbS#n+P6vQUbU{@B;e`;R-XXux zyJ*ij>j5>6Whj=zBG>5!^fuvgfA{+j?9gc?shYJ*D|gA*KEM&99Beupx-Mtb=!gOO zNW@7>obRC1M?;Q;$Yy85E(C_r%NDZ31>nGxvr??SAVeSGsIS_U@B*jO83(wqH}lu` zE-mQP+?dmCrZ{tWA(?lzW5*LI#7A)atP&EPMjW}qfi+oZA%cAT2MVad_9-~2h4WqX z*&P%dV#FB=?G<}=!NWVB6)#RC^_j7Y$AZ1@+U_`p$OU!`kqd6D9BOx6&CU$&F2*`p zm^3p=!wE#LRdAwFE8JyA8gXC{#}$1+NAqxAQ5x3X8M_<_!lugX6wE<5O9!huqNn91 zIJKyrzlL*G_Qsrg1QB)iFc`i6P;m$pNy1@0+m60>7d4d>BJ*C z@xIvrGJqN%BzkB8i(%pqi;6jZhnn?IP3jUcKWin5t;OJ!Z_RET-RhsL(_$}TD(DgV z;a>`t)ZxU^CPmcq>5vV7a4<#CeJW@bpiB;M1C9ZuB&y}hQ$?*jzH}h~?Bdj+|M?OK zBC(?Ks7MO8ibfnRgp?sT))APZG3|ojA*8D#3CSa<$6a}$Qp)~Wc2pPKcJ){+!~kk! zQ(?OAhxrG3cV=zFS@b6W_N7p*<6)=4ZTq)?pCGJaueJbb66<^enm`*It~w8cqqPVcprh(uL_R$!Nz1GLGwo;O9yH zPBU(_<~glrT(L=obEAt?&2eQ$S3a0>id%zb;rog1CF95A&mghJx15 zWeF#d#wQ+fRMsO6ZkZ+Ry#-$hOj#zTb&k~<;tkyNzH!%E z&X{`e`|eJ^x^&(2gRi_hJ+Sot^ldwzf7vS^ntSZV?D>sXKD7U__aAukf}Ndv2S@t; z*l!)VqdxV}ciqj;`8Pds`Q7OWNAMn4x;cI9#-}Ba0Vnug@$qLbH7gNk0#*32<9qEK z-_*4aq^oE6W}HqJxh8{{B7Ncon4MfGh-Lm&7FPc)FNqj5bAP^&e(11v))4od3x1=t zhWe?W_%95#?t0t8!MO@!38Ne_HkPFl8G44tmxw3~4HMnALhrA2V${j{ z6d8f&vaGVu%Er@})Fwd?7gpQ~uuuyM24qu-0HR->jflPd&quO)Ewii@8ZJ3qJH!4l zh2t2tQ70-4rqCO8OWx8R0JO3eo|($<(juS)Pv@kX-*W?^)9hJ;$I-!p5(|543gIN|01qO-h4=Y} zVqzl|s@i+_d~?{9zB&C;5xqzLR6hdYFQudjVqc`dsoMQ7ffc?U9^u?js6D3ejE-AI zbqCvO@RjZvsgB_!QoOD6t!uL(wm+SiJn*IA=|QOwrJyau9lmB(#j<#XqhzB;hdIT_ zfl_cZA*b~|?{5XaowX1WVM$@Nffz{_eBmo2u)6pKvOb`pXYNQr-y;f2!1;~_D4eL- zs-}&V`@gUSj_)cl&8tIrYdY{cp%lYWaC|)k$nf_eR<^}?B-ARQw5ODwR?v<3ch|h) zET9roF%v{LN~Le#;?m)jQT36qLA)6%{V!j%Z$r3~GgTpyB02T%!ngXfza`+}eg^$2 zlm4N&k)Z@x{;W&M5!ZBtwBX;Er50ZCGiQlrU;+>!mq>WiUE*}X*Rljbqv}o_$rs4| zanRMd^23A`1WVZUmi`8`OmS3mAl(6tYhc~w;aU#eI-<*{uY23>EC)zZI*#0jZ$I=lZdC+paF^q5Lyy| z@)4NUYkg^`7?=QH>$2NYe_{R%SUPSBasBERgU@v+oHC=SSiStF1y{KyW(qS zwH)S$j8n8$*+8WciU}4+&WDcc^w<_!Xy5LnGO(Ccid&t-D?;=?qBS3gqM(-IIaya< zJRH$MzgOTDs)rvOcjUtB1hNhBld}I!0X5c&$x$R)Pduw}E|n zy=+);`uMJ*b!)af-Er3*nmbfIa-|)r%PFg^_~;it*miLMVQ6vDMnBYbF@%Zjd7(U6 z7=kN;qC_Sd1j?h|Lxxa&B(+%BK$J30qh~tKlWl}B0d{KprXw7)t+QRz-rs*#nJ^bP zJ(mw74^^qjm`wRJ86zRQieWf`quRjNrF)gV{<5^m{*^QVIH#PqIk<}EOz=|t?(1va z9YL4ok~@*gfxj85dRnl?qYx@kmcfq-@r}E_9N+vpBG(R=UGCf@xm9iSet4xO4#RYZ zf-w??Dj>LY@UT5nDbYlw$Qt%_uoCesh+v{0365RPC?bAB>*gPEa2OKNzzkFm7ti)7 zEtAhl?*0?wO?i2c_N_9GT?$gQ)kF&AK23WIyHyP%mJC%ji#PFQbC-2cE9gTGyZ9Z{ zB(x{>vZI7ok=IGQuJfZ3jcEW z+gG5Crwa#Dnj^!2rA0AOvrr}~+~yCvoutB@9b~yhmAtn|`EGISaOwmW+f^+1U>3sS zKt{~0h`Q4vm=0pg3y#4JY7fm#hnTI!VI9qU*JqMBusIP|rew^XHJjJHiKo>g*bb)1 zkbx(=wMh*ZVm?zQC$^=*3QW@b`sYR`;V$H#-1$Qnzv#~nKlW3DPr~iQ3}=g_WqRxe zum7NnAN9Z(9BcSzd?rRC5%<>r>C4iG3M<{&VX;nQG!kKjN^JdKiuxzDA|*(_2rPL*Sd;}3i&nGsc5mzNkO_*D=ksBf4tfS8i<$=nye z>2erc`uAgzY6E^=PecdM;1T02Qf6|Sb?)qeFQugf6`1=lD^A!ulpX2~#VIBSVp?!+ z_+!8H|HVvk3ac3F1?M`6q=KPQ3V?nL1pUY^|3C!Q$$7xA$bBNdDY?o7gubLdav^`d zaq-_6Ld^;_<%;dg5hpa&07TOU+!L=b-ExO$aJj0BtPo{#$%#I0wY3-KMR38fS7NY=4DyoRowNS3ybOQ%Lg0iEN&OwVBk>Ic^XdB&8 zEwy^@o99`*n)MLq%u?Xt28)Cvq9cgc6-J<4$7GQ?LV=Q@aE~XZ8irO$LK?VeRoyaB zT$SP7)pl14%7Vo3BvmSeTkEmCZx-W<#cCBe$+tr!e2iN}v`8sQYo+*mm0<-Hpu>$w z+MZMGc_he?40><-8Qnyb>45`ZS6r&f0&H}mbh{XlCC<4gB~3$a4rc~F_2CQal^<)S z!;gRV3>geU8#0qzlPIEyCy;M=)zzb7Sg8!Bq(=HSuqXrBq60`*6e-}UO>g<%!$IVX zpfnvpB=VQ~vuIp4Ls$lrf(S5U_8sb1L4!VB<%vSzAn`A_*JOWVzW&7P<2TF!v@31` zyhy0>7F-{muvmMk7De7Jpm!mx8QxTk+wGk}kWuJ@S|k0B{}y0CtDq^!E1oViJ5W4E zo6B&NSJaVwo2iw{5sikwiSxx;S3ZH0177|E$Jgo3dH z*ZYZICt)hEU=dMMS0Nn6(w8qqwRbIdJ-ipZJ{zpsZQ0i)aMn$-eD4yBgVimSSNjUpJza1_ZpRS<<^rt;s$)To8a)wF$65*|5kB6qEc z<++ZVeB_75HLKZ;>JN1HTphI+e+28ZweLW5t?Rfs%_Lr1)IVRe{VeK|&7vNZl{!N* z%z&8=W^9^n!$xhx+C|X9%zaHGs4d8f#X$Yt!d=ukMAB<-+J9(w^~juANz41c*oyZY z`qFtVaDHd(zI>>{-HQO$0oQ8}RS&hlctrEDZDprp z;osz^q*Ku98!p}sBUt=FYf@o@rvr{xunPK*RWmO|A=)k%o44nVOvswc0eZt#X9yzp zg}E#@GLGB?=Sxq7ddmSxXZXZAPoGFEtCy zAoCMYi?OTz$5}S%n)uo2n0ndNYb=L-Aj6lkJRvp^907sa&}EH^WgD%L8LP#t4HLJkEfHR{mH*II(1E)3RtO;y z67+{%%^DwjSOvLyQ+O##QQZ<4R! zflSsL@b37@fzC;r5{f44AwG)zV%h7r@ir@^`ljxiF_0$J+BdG~fQk&%`V&>XwN~rvGzBJGkV&LMC==dP3_gJ}~LR0?SiG zdmt0v6}zXy6^$Et(EIbLHyi>@3|zB;Wu%9|E-^be#t=lU*G@ejpE|(KCPe?!FrK&F zS1EBGtJ>#Rv*<*9f11D!+b6{@Ow#83dPPp2{YdP!64>TTp6?ws;A!aP)oux6# z$Gm74%N>hC1+(9kWP*`$dVkS)+~Jeoq>EDz<3kv1nff$5+@+f)S)E}jWB9JIaL=jh zI(6Xk;$FIq6s1)C9OlHfovSi@lXsetn?Vi9h0C`#he%O}L^*~XL-*xZ{l>FV#{i*A z12OsMS+M{lJpm8?waX%H%r?)jQu9#Y+RXrv2nd-#LXr8YRQI$5OI@g3?Jzgz}fH$K2QQtOXVOa>qhQBo`$c~zp6a2#Va5Lqd+=zZ?hTA*vo zUej25mP%rcrrfeIaE&BZw92r#CC86VnL6r~OcWvw1*;gVhS`IdziOLQtw(LDkH3-j zU|NUCz_=#yn?}STFa?}v88 zWTkl(hZ4aI@@itwyeg<)ikbo%I`nurR2UdC1%8t5I&^x9?7|2n!L+=}{ze(cp+*tZ zpRW~aR;YF<94b?YPi^`<3T^NV`8r?u^D3-wR&#~}pF9amDB)9wkP;YQF*Tm=s{r$t zA~n+TuL(C6N-}Vg941vQ(BcmVE2`_Re<>h!1T}bi64RBmc)%kqh~jTWaz|^BPESG^ z)D;SSECE4fB8BA-e^hCFa^oIlh!tYV^;BL;^n4d4?~K@xjRCza&9%;q7|MHd(;}0U45tdPtJ#&Ib`i zI3@9KHy(8#Y2jESPLLe^#y2I1)j>;6jLJLn9r>nF^8O{bSe%sSODL!^k`%32 zDSVi|=?wpH_h;i9QGZ#=g6?W4FEG+jX{1}ym{oT-d4=p^#N2f}$uKW@t#ao)f4daLn-so!@*-y_2Ei&N>)=cAVAB3~*XS z93#7Vo@WGyS}Kvs*bOpR4riL)fAoknJDfDmo2Z>P(Jl_d&~9$R74-7+)H8671}iHC zV-uX#nscsGIG5k^SC!Y?xPZAf>zB$hUAtI`TQYaAW{kzY?_yBxn<=Ly`_r~4wjt89 z|7h!GVJtpo^3qmEFrn^40=B9a!c<}V5K9`csF?Rz-hW>}0z^RG>a4U69ceU<&fG}R z6RgsW$1Y~pc2TpoU5u<q}LvauyEXfvu;R*|A{HcGefO*lTBq#TzX7 zRm0FV_0e0qvUo9l-ht(OQG=4-hZVbxvu1?f<|`;{%mo`Nv#{rMp};OV?>m zQ;}bE^_xHPY!}%CY6S%)uSJM`(WlO56dIu{uRMP-I zgB~@lk6c6|(9o)ux~QyPyK~Bb%t5mPVtd8gyfWfd!@}cGs7SJ6*e&lKyX*DOY01LH zQy?3Q1;q@s=I2DA(}!AkV*1MY3VJzBY1D%{P%k{O-kV}|C5T_-owBNI=yWx2P?=dwhAERmgpe(_pQ= zZnM$Y$W&y#!LB*mP}9++aj%M;I33I|l^or3;b;j5U>qm!m@UR+9?! zPaHSsPD~##*qY?gEJCr87n3*aewI`P!BzZ3?=3|SBZ6d*N&%Mr^Hm!KE0uwo?D z&^mC|BE4!jqHSu?k`dVZ<8#pfnqf?81UngkiM(OdN8AVmSKKebo~^D5mhobWET!k5X#kY`87l)+oX>3o^H@ z5oYPOMk8tzjY&6_Cf{iMli=2=#zJ<lKrqsN9n6tbQoEXiH=F zboIsQIp>C?`?Kt!rSO)?nRxcTTa&{xN_bP5@M0xA^ZfLpbHnBv)5(_UkIeHbM0HKViyPH*uA7-VG3CF}k%u|0feI|uFPb82P{+oLsroH=}ZQJ>(<7>j5iHI#5F}H*UpkzEC+gJC2?*%M%FNi zO7Bm`BlIEW&jf?cE6~cPFZCR&81&oS(CgUH3U!^Z-ub!St98=;sT0dK@g>LH(h6Ei zYSa=8o9a`IYrN=)7$(XJP}Q709Q#to7Zo45n^utTN)+HCw_T9{CXUrFR2s9!6R3<7 zIF-j`KOkxF+XYkPQeKxW^6{CmGJ|StD5w?7c3?VD4`>xs#@Ef#7~URtiAKAeXr?fl zG7R!pz4iOa8sV@?c%efu`G^l_%P8TR zaK%GrSDo!Mz)m)tvMvWlo3S=^C0~SQmxTXF`F$R!t2TY2hM1@!he76e~4{)yY z|AW5EtBYq#<){F%z(bYQCR8U>peU~F*32a3(Fb@Kg}~;)ZQGxVZf?{pktI=ViD4E7 zXnD+387Kw)Xc5Ix9|EjVtqj8Y#mF3SMG}HK9jlr=_V_OtuY(Gmk}^O%77FH901^@9 zcmK!u$FQVQNVJkDZ~{F^sd0|wLGa@X@e)r0X6l1(BA|I0$b(Un&?cRVAGn4<4_qLP z?0j=?x2l+)AVzZZ(SHMi1W2LqEvmf!g3A>}`^>BsW^5`vN@RUXXdvtX&y6*5FZ=jQ zZ$z1s*CFV}wajJa%V^4)sqxm?0t?8SG-;G{4j|UkZZhj;T?2=OSU=epcVT2b5-Fn( zMn!s>atJa=FI`Yo81l8u1Okd5Ex~#)q=me@%SZqEH+gkBr3~K5X6+JOOVdQKQGK?u zAgLxH3Tm?~mI7oKNlSO1kK@>S5l&=!2F370QO;TYge|!6M7Tcq#N-yk32!f;AYgy% zT@Q4p{p-T`IO2t%yEq=RDm!jYg{}D+r&oDp{w}h#xC;fg%hZou8nq8Bh&Z?`FpBk0 zBegUD@-eRnga8vl{YQ2nAMgCY7h+TX@_rO}Kf=kozBJz2x5T1@8Qz<2)+<}zu^q=o zjQb<&dq3u9E~?_Dsm;xQ0hC@@Ke(qGwWAAXnm9mO;k7QDi<|SaZ?N~PyUnTk{%-U9 zil6y!t$o3owdr_I(DnRWdS?aCtSt{{x3qpBY=0bQO6L$(^ZO4SWc500;pLAwQmtRI zf`HYG|Gt?>?=aicyTdE7h))7n0X#&gZsjzJZCy81pPxSdo{ZhNt3!;<-40{G$1pC|G3W2tPp^1lrudD4K|ewdZF5 z0J&q(5IR?zgNyRueJjaXYdKg_9tPo|-s78SI%EkruAgeKrt-bnk0zI?cgx!|Pj;Gy z34AzX4PSlEUq~I+N`M&8!&Df&O+u*uqBic6Aeu%@ zrJai^Af8?_8!Tqwy+z76n@muhgDEuX7iTYNGh@PHCw?QfXFDTV^{m1VC)hvFbFiNO{5TJmF69 z4iVM^xFWaJYK&)cmfUc;W)C;#YFu;9vvwm{nKYc`JB_*^h5lKg2K0Phs%33o8cY9o zF%#=TEOflL7e!6Fp*pu_8q^z6U!?X>nSd{KQKXul6v=SQV^I6npFF5KGoL|tM0SR6 z^e*nwq*4O~)t#&92XM3%)~b`(U>FF4uJu0z*@$W*y!g2)K~YF4B^=e`v0r;TiDIT* zN=YN*0$oYS*Haje1|%xu zl`u9LEJW;ThDH>Vl0L*YJvr@$g;%SYZ!4aQq64qQPE-+YA!1xbm}Eq~Q`%Tq8@{Ou zCci+S;i*lOfD7C}p&%9OE7P2!@*ueOTW6{%H6&92VX8cf&<&9;xmd&L?|tjh2I5Wt zLDkUUDw|5?F zNkdqB8!at8S?z&e@?G(saWzcnK^Yu)lN1qXDku7HC_&&;5CyRbC%111Lr3LMLth7y z6b3GT_;0qT>J*373Mt7)HxO{f6^H=4^N)LgCL$qF48k$yG4caT!IY?3m7II%LrgWe z?Y8G`leJ^^dKb8;JW4A!s=+ffEClpbyqckZ3AmM~DiP0*2Iicb;+m;5z&QqFB996r zLHVQW!x>&R>oM_P`Byz?L^8#b+v#^Wpl?zb+X=Nrj^aCE$WYh#D>ywz_w#6zLa3 zXjv7X6OIP?uf)%xjae#^st~)x-4b^YhZ!uh*qgXKv~dHiTTXtHaxKv*sK%A+?Fu!i;%2a?vG^Kdc0h#7?E3CM21r>4TQ|xWO z`K3kLoR9HJ;@~r1VwZe~1QcT|%P8ow!%L&mm8o0NEA$b+?YPB1^sUp1o@~ZnR9d2% z5XyxB2vO&le#wh8&uflXC_yGKYL9*JMGv_Bv7g(=mSNgo7VbRG#`#%x87ki_ z#g@1GW=N4n@gf^g*0Zp+Z@Wc13=QNBADalrkfK|bAr|hiG_*DV(<}g>6@5 zaeVK`-;D+Ki%ZO-zp%e)*uMG>O1)M#?P6G(w7jw1ZSq?8IIH4$W&3Iwz8GWII>+(= z;NPhI$GTD8n$^tx8jBVi@*Pa=gO3@#EPk*p!?Ys4-O`KQ7#Pdn0QZ{$j0zp&c_G!(@vxb1THrA2B)mrl|d5_?clmLsHC8KCIBM!=zdjZ*3$h zs9pN#{ z80~2&OV-kCKADVqzCLSi85Q7Un+eqH0C%^2mVHRs)PY>IZJAXfX-&cFs-m?0dU%oA zf1*59419bwGze)Ve%*76IM~2UJ#hk@Ry{a|Jk2X$&b+;5%fW301Xsh?n2#jy?VD;B zY7y-_=9 zmI^S@QN!A$RxMlfe%+7gt?n4a)*I&Fy;`?&%HNMUtD(MXG^(%hDuD8Z?g9u`-2NS- z1@9+W@cwLutz&O-YXyLo1E7@Zb#9DA|Hv``+ojCnv?jo>3+TV{tw)Oo7D~F@z^ix2 zg1*J8NSMX14X~HJSqXr;!XV$9{Y@HdbFSp*zy2`G;FqKxL=>kEXF88qS0jE#?aW~H zJ+@1+*eYogT?kZ#p#@-3al`njCyQYLLzq*wVA+-^OE%PgeaCaqO=6#mr1Vu?i4+kG z(U2c?4v8ODN+Ua=Oj!iuC?zNf0?c%O;>6D^Cs)yA`9}Pz07bl3>5|xLq8^D>*aZu# zNhD}aiS;F=Q4pI!h=q3heoVXb#8 z3~;N|pktB6W9!N!y)Uq=x4blA3=lnwN35)pZc6T~l}R9&rPZl$9>G`PIpio{4VXhn z_Z~b)(Ok#q>z_3b?p6xV-2{oMBr?*MDUQ#h0z8=7H{SCX>IEVMc(_K!YuXSD!@#Pl zFHadz;)ajU?BRl#8qhjrNilILp=x&GdcVIlfJ20nu?BYwmetc6=_HqwUEoa4lIm8v zVL+UU5YYbR^Imhqgkdi0##1Ds7&%v{zOfY;8M4L@BCN1iQZb6)S%{$e3iv>!dgN>b z161Kc?F$i8-0>eH6^YafzNG7`sOYVd7xkZCv2ipXwQ z2;&mev0i9kLdh&upq{`1FThamCcmOFtL<8_)dJR7^{XS4(ZBnsa(D9nKUU1Nr4>^g4kTWHvk4$ z@KMp$0UDW?PkJ2@e@BFJGkXpN#sb`ce>j_3uE9}6z6eFFu z)|d^u@F@JaAgZTP#Ks|5VZbFFlmAsoZ$;$68nfGG6lZ0cptM|KXO7>wUBf z+iQ|EmWhw$uX#--n88o;xGK{^R1(}ESc0#THOnbdoAIv*0R}%y1P^*NjxX;kzj;!{{AYPVYURPsGT4L9?!CwqSgX zNhv%*mx9WPUxP(~C1hY~o|ITmTQRNzcrLLjs}I!P*6$&=N|Ief$5~^fmeNYNo^Xj} zMKbFW{oB=4Na{y^!l3d6{(=k2_QRuP0znTzH6hx*bZ=v?XeS4n0u*F7J{F;J;7_Gg zp2W(^$Wy+{yf!JYEL0ZnAlu6Y*Zk!8oygOJV-enhywVM{lpKeNrb@9WThk0X2PeaT z8A=V(OkLV+Xv&1NhQnzpquJ0P^^=+!6Nvx^WLf`(ZZj!K)6%@q!-ux4SwOxz8S1^X zeH>YM9%v$TZ72ZV6w*&Dc!j6|Gs1*EzB1axdd;5P1K*RjO{_5wnf3I0Rrjq%9Hh)1 zVn(hSl8grYiRo?GC5)?419btT%Ky@)rS1&xYD9rI;0zn4ygBKONQK>hm5!_-elxCD z{rs7S=w)=Ve%}(*uD&ErH6x|LmPj*VHS`KAMmS}#JXSNp7>KDBgCZ;r0}F((?ETZ< zuv^qgkdOR*UvW|`_}7nDH-T98-hM*$Ws0yK&r&A!!XQ{7$IX8^fh1oA=+mbbASmij z^dFJYKX^C` zT-_QN4@>yKAJp8GjWS*N)7v+9e87oMnpx&ri&$BR1kAdt_rag+r!NwLWPH@ZhcF2flfd*BfkVN5uhe{Z+zV6MX4g&MHe3&-x|+ zO}k>bC=AT8d|+baD?|FkAXWdCti2z*ykF50lmYLCHJ9Do_NFs7KvQx7Y3hw52~`CkBp`qW z2;&`2)9x zZ1;aqeUIQxZ|)!C|JCd&8SxZ%Rjwf5L)RUtY0i#tY3K2Nsf6A$6QYwZLU-Er+B)(Hjy zIzJ|h=|Xl-SowGyyyWQK)^Pz(>VdOx4<&Ho@ zWVWwK^aO988nqmN>U_Nl&09yP}HAzWHNT?FKVxd&AFb^B-@-S0_CYXdTNE= zrd4uNYpECRHj86};Nf3A^U!A1v-ag*(Uu+Z#nmE?ZVKW|z7HL3##>g!N!)j*n&s$! z`>V}DeDm3Gvl{4`BT`_TC+&n9?49dvtv^kHH?Fwk*`wv+Em=3Mn!^-} zK`Q;wf=6DFq2w75IgI=Rk`E7hs;W<$s_}?on>C;Y*Z$h@N$=tGK0bETl*iNKdj1=^fDd^7(xq50HYDnslRxyM)1EWS18%UNRftyXSO;hR`y|4b> z5WG(@>KS7mog!T}PQICHunt4txTI5!c}in8@}ZA>=%>oiq~B!u^z>EHzpa>$)}@|o zUFvDD?gm*lTS_0?G}p)E*FU%c&ZiN)$sPAJFxVi=2(b+avtjUvVjGfXa75#QsgVnP zFljal9r4&kl-VeJGbyHd-HpmQ2%8U8<61{BT&ArTJF;q_((th zU#g!E=z*sfwCQs7^w1cPYqQ;(1By7kpb=uHO1EbW#kOshr8{z=pDK?9&ln~A}KQ}(|pl`Z6c(iD4Bkmm-4og3cb!hdUZ_m4)qctu^?l}2obpu)IbON8s zYX?uKJ_GZN2Hb&U84@_6*bw3jj2cmFAX$b4jwm*SI0K_b6dOpEA%UXUX1@x$@e8Nd z+^iE9Hs>0(^{LWvvndAOe4BLKlWf2?U^BH-(6ztaz(*_4PqqU6R2g@}^qbAm8y0k` z5hKJ#6dOc=&74Oc@z@{=4+|SnY#4P0#f>O7h$_RvHk)GjKu7O~?ioh$Q;U11NZ_Zh z@BG_}`Dk&=({pjlW{cHR6BEar04lLcAK6c~I=U?{9hvpu;F?)XFl@INI?EMGcypVrr`KldvOiexX zW50FWniBHdQ9r+U3IG{=6yruh_msm&TP&V3$u|2X@l!`&qa2$p(KjmRl*31eohr#T zkz&c%+n%C3Xa8?$IiJwdo7j}kjCJvwy48E_=)S|F^)0rPebY>+XU+>PPu~SDCqFLz z2^@nsa7|6)kq=ZxD_l;t!e!I;SbP$jc5yiC`m49Na&WU;f5B5^2bXOpR`aflHg&(> z^;A5`^N>y3d$%`ElKB*(N1DYc5X+K2RVnt2*>T}i8*JnBPt~T}RPA+BeGQwsJ-}w# zZX+GtvpFn1($P2W@q=O@*+@rEINIy@Q_V*@`tkn!!Cv&If{s3bsp08OeffSs5vLcl znKFM~c_{(HI zUQfHBu8*8}D>1MX!^%5O>eie%P^IG$p96TIf%R$tNtZ+kU&kvhQCP zQj6zk(eO%yO984X01qK+Vdyp6Xi+D$DoROK^egc^;%P$AXw8(k4=O`SdFFw*bGTtD zp{*%pCRVgDnMof6Ik||6OVS3UD%#!C8(?Ek!w#zr#|NlgM$ltreJ1gTNsQUW-}ewS zxgkX0tBM~DL=kM32|kJ4zw{+aC6*^aluz*p*$~wy-g`lz2C$-FpMk4yhDG cpu_clk, + rst => reset_h, + rw => cpu_rw, + vma => cpu_vma, + address => cpu_addr, + data_in => cpu_din, + data_out => cpu_dout, + hold => '0', + halt => '0', + irq => cpu_irq, + nmi => cpu_nmi +); + +U4: entity work.U4_ROM +port map( + address => cpu_addr(10 downto 0), + clock => cpu_clk, + q => rom_dout + ); + +U2: entity work.PIA6821 +port map( + clk => cpu_clk, + rst => reset_h, + cs => pia_cs, + rw => cpu_rw, + addr => cpu_addr(1 downto 0), + data_in => cpu_dout, + data_out => pia_dout, + irqa => pia_irq_a, + irqb => pia_irq_b, + pa_i => pia_pa_i, + pa_o => pia_pa_o, + ca1 => snd_int_i, + ca2_i => '1', + ca2_o => open, + pb_i => x"FF", + pb_o => pia_pb_o, + cb1 => pia_cb1, + cb2_i => '0', + cb2_o => open +); + +U10: entity work.m6810 +port map( + clk => cpu_clk, + rst => reset_h, + address => cpu_addr(6 downto 0), + cs => ram_cs, + rw => cpu_rw, + data_in => cpu_dout, + data_out => ram_dout + ); + +U1: entity work.AY_3_8910 +port map( + clk => cpu_clk, + reset => reset_h, + clk_en => e, + cpu_d_in => pia_pa_o, + cpu_d_out => pia_pa_i, + cpu_bdir => pia_pb_o(1), + cpu_bc1 => pia_pb_o(0), + cpu_bc2 => '1', + io_a_in => ay_pa_i, + io_b_in => x"FF", + io_a_out => open, + io_b_out => open, + snd_A => snd_a, + snd_B => snd_b, + snd_C => snd_c + ); + +ay_pa_i(5 downto 0) <= not addr_i; +ay_pa_i(7 downto 6) <= "00"; + +audio <= snd_a & '0' + snd_b & '0'+ snd_c & '0'; + +end rtl; + + + \ No newline at end of file diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/Debouncer.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/Debouncer.vhd new file mode 100644 index 00000000..2d7e90bd --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/Debouncer.vhd @@ -0,0 +1,43 @@ +-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360 + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity Debouncer is + generic (Delay : positive); + port ( + Clock : in STD_LOGIC; + Reset : in STD_LOGIC; + Input : in STD_LOGIC; + Output : out STD_LOGIC + ); +end Debouncer; + +architecture Behavioral of Debouncer is + + signal DelayCounter : natural range 0 to Delay; + signal Internal : STD_LOGIC; + +begin + + process(Clock, Reset) + begin + if Reset = '1' then + Output <= '0'; + Internal <= '0'; + DelayCounter <= 0; + elsif rising_edge(Clock) then + if Input /= Internal then + Internal <= Input; + DelayCounter <= 0; + elsif DelayCounter = Delay then + Output <= Internal; + else + DelayCounter <= DelayCounter + 1; + end if; + end if; + end process; + +end Behavioral; \ No newline at end of file diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/Keyboard.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/Keyboard.vhd new file mode 100644 index 00000000..49140020 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/Keyboard.vhd @@ -0,0 +1,61 @@ +-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity Keyboard is + GENERIC( + clk_freq : INTEGER := 32 );-- system clock frequency in MHz + port ( + Reset : in std_logic; + Clock : in std_logic; + PS2Clock : inout std_logic; + PS2Data : inout std_logic; + CodeReady : out std_logic; + ScanCode : out std_logic_vector(9 downto 0) + ); +end Keyboard; + +architecture Behavioral of Keyboard is + + signal Send : std_logic; + signal Command : std_logic_vector(7 downto 0); + signal PS2Busy : std_logic; + signal PS2Error : std_logic; + signal DataReady : std_logic; + signal DataByte : std_logic_vector(7 downto 0); + +begin + + PS2_Controller: entity work.PS2Controller + generic map (clk_freq => clk_freq) + port map ( + Reset => Reset, + Clock => Clock, + PS2Clock => PS2Clock, + PS2Data => PS2Data, + Send => Send, + Command => Command, + PS2Busy => PS2Busy, + PS2Error => PS2Error, + DataReady => DataReady, + DataByte => DataByte + ); + + Keyboard_Mapper: entity work.KeyboardMapper + port map ( + Clock => Clock, + Reset => Reset, + PS2Busy => PS2Busy, + PS2Error => PS2Error, + DataReady => DataReady, + DataByte => DataByte, + Send => Send, + Command => Command, + CodeReady => CodeReady, + ScanCode => ScanCode + ); + +end Behavioral; diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/KeyboardMapper.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/KeyboardMapper.vhd new file mode 100644 index 00000000..72ef7b77 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/KeyboardMapper.vhd @@ -0,0 +1,170 @@ +-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity KeyboardMapper is + port ( + Clock : in std_logic; + Reset : in std_logic; + PS2Busy : in std_logic; + PS2Error : in std_logic; + DataReady : in std_logic; + DataByte : in std_logic_vector(7 downto 0); + Send : out std_logic; + Command : out std_logic_vector(7 downto 0); + CodeReady : out std_logic; + ScanCode : out std_logic_vector(9 downto 0) + ); +end KeyboardMapper; + +-- ScanCode(9) = 1 -> Extended +-- = 0 -> Regular (Not Extended) +-- ScanCode(8) = 1 -> Break +-- = 0 -> Make +-- ScanCode(7 downto 0) -> Key Code + +architecture Behavioral of KeyboardMapper is + + type StateType is (ResetKbd, ResetAck, WaitForBAT, Start, Extended, ExtendedBreak, Break, LEDs, CheckAck); + signal State : StateType; + signal CapsLock : STD_LOGIC; + signal NumLock : STD_LOGIC; + signal ScrollLock : STD_LOGIC; +-- signal PauseON : STD_LOGIC; +-- signal i : natural range 0 to 7; + signal KbdFound : std_logic := '0'; +begin + + process(Reset, PS2Error, Clock) + begin + if Reset = '1' or PS2Error = '1' then + CapsLock <= '0'; + NumLock <= '0'; + ScrollLock <= '0'; +-- PauseON <= '0'; +-- i <= 0; + Send <= '0'; + Command <= (others => '0'); + CodeReady <= '0'; + ScanCode <= (others => '0'); + KbdFound <= '0'; + State <= Start; + elsif rising_edge(Clock) then + case State is + when ResetKbd => + if PS2Busy = '0' then + Send <= '1'; + Command <= x"FF"; + State <= ResetAck; + end if; + when ResetAck => + Send <= '0'; + if Dataready = '1' then + if DataByte = x"FA" then + State <= WaitForBAT; + else + State <= ResetKbd; + end if; + end if; + when WaitForBAT => + if DataReady = '1' then + if DataByte = x"AA" then -- BAT(self test) completed successfully + State <= Start; + KbdFound <= '1'; + else + State <= ResetKbd; + end if; + end if; + when Start => + CodeReady <= '0'; + if DataReady = '1' then + case DataByte is + when x"E0" => + State <= Extended; + when x"F0" => + State <= Break; + when x"FA" => --Acknowledge + null; + when x"AA" => + State <= Start; + when x"FC" => + State <= ResetKbd; + when x"58" => + Send <= '1'; + Command <= x"ED"; + CapsLock <= not CapsLock; + ScanCode <= "00" & DataByte; + CodeReady <= '1'; + State <= LEDs; + when x"77" => + Send <= '1'; + Command <= x"ED"; + NumLock <= not NumLock; + ScanCode <= "00" & DataByte; + CodeReady <= '1'; + State <= LEDs; + when x"7E" => + Send <= '1'; + Command <= x"ED"; + ScrollLock <= not ScrollLock; + ScanCode <= "00" & DataByte; + CodeReady <= '1'; + State <= LEDs; + when others => + ScanCode <= "00" & DataByte; + CodeReady <= '1'; + State <= Start; + end case; + end if; + when Extended => + if DataReady = '1' then + if DataByte = x"F0" then + State <= ExtendedBreak; + else + ScanCode <= "10" & DataByte; + CodeReady <= '1'; + State <= Start; + end if; + end if; + when ExtendedBreak => + if DataReady = '1' then + ScanCode <= "11" & DataByte; + CodeReady <= '1'; + State <= Start; + end if; + when Break => + if DataReady = '1' then + ScanCode <= "01" & DataByte; + CodeReady <= '1'; + State <= Start; + end if; + when LEDs => + Send <= '0'; + CodeReady <= '0'; + if Dataready = '1' then + if DataByte = x"FA" then + Send <= '1'; + Command <= "00000" & CapsLock & NumLock & ScrollLock; + State <= CheckAck; + elsif DataByte = x"FE" then + Send <= '1'; + end if; + end if; + when CheckAck => + Send <= '0'; + if Dataready = '1' then + if DataByte = x"FA" then + State <= Start; + elsif DataByte = x"FE" then + Send <= '1'; + end if; + end if; + when others => null; + end case; + end if; + end process; + +end Behavioral; \ No newline at end of file diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/MPU_RAM.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/MPU_RAM.vhd new file mode 100644 index 00000000..0d71661e --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/MPU_RAM.vhd @@ -0,0 +1,181 @@ +-- megafunction wizard: %RAM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: MPU_RAM.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY MPU_RAM IS + PORT + ( + address : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END MPU_RAM; + + +ARCHITECTURE SYN OF mpu_ram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + clock0 : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren_a : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + intended_device_family => "Cyclone II", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 128, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + widthad_a => 7, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + data_a => data, + wren_a => wren, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrData NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegData NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL MPU_RAM_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/PS2Controller.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/PS2Controller.vhd new file mode 100644 index 00000000..6e42eb6d --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/PS2Controller.vhd @@ -0,0 +1,209 @@ +-- (C) Rui T. Sousa from http://sweet.ua.pt/~a16360 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity PS2Controller is +GENERIC( + clk_freq : INTEGER := 50 );-- system clock frequency in MHz + port ( + Reset : in std_logic; + Clock : in std_logic; + PS2Clock : in std_logic; + PS2Data : in std_logic; + Send : in std_logic; + Command : in std_logic_vector(7 downto 0); + PS2Busy : out std_logic; + PS2Error : buffer std_logic; + DataReady : out std_logic; + DataByte : out std_logic_vector(7 downto 0) + ); +end PS2Controller; + +architecture Behavioral of PS2Controller is + + constant ClockFreq : natural := clk_freq; -- MHz + constant Time100us : natural := 100 * ClockFreq; + constant Time20us : natural := 20 * ClockFreq; + constant DebounceDelay : natural := 16; + + type StateType is (Idle, ReceiveData, InhibitComunication, RequestToSend, SendData, CheckAck, WaitRiseClock); + signal State : StateType; + signal BitsRead : natural range 0 to 10; + signal BitsSent : natural range 0 to 10; + signal Byte : std_logic_vector(7 downto 0); + signal CountOnes : std_logic; -- One bit only to know if even or odd number of ones + signal DReady : std_logic; + signal PS2ClockPrevious : std_logic; + signal PS2ClockOut : std_logic; + signal PS2Clock_Z : std_logic; + signal PS2Clock_D : std_logic; + signal PS2DataOut : std_logic; + signal PS2Data_Z : std_logic; + signal PS2Data_D : std_logic; + signal TimeCounter : natural range 0 to Time100us; + +begin + + DebounceClock: entity work.Debouncer + generic map (Delay => DebounceDelay) + port map ( + Clock => Clock, + Reset => Reset, + Input => PS2Clock, + Output => PS2Clock_D + ); + + DebounceData: entity work.Debouncer + generic map (Delay => DebounceDelay) + port map ( + Clock => Clock, + Reset => Reset, + Input => PS2Data, + Output => PS2Data_D + ); + + --PS2Clock <= PS2ClockOut when PS2Clock_Z <= '0' else 'Z'; + --PS2Data <= PS2DataOut when PS2Data_Z <= '0' else 'Z'; + + process(Reset, Clock) + begin + if Reset = '1' then + PS2Clock_Z <= '1'; + PS2ClockOut <= '1'; + PS2Data_Z <= '1'; + PS2DataOut <= '1'; + DataReady <= '0'; + DReady <= '0'; + DataByte <= (others => '0'); + PS2Busy <= '0'; + PS2Error <= '0'; + BitsRead <= 0; + BitsSent <= 0; + CountOnes <= '0'; + TimeCounter <= 0; + PS2ClockPrevious <= '1'; + Byte <= x"FF"; + State <= InhibitComunication; + elsif rising_edge(Clock) then + PS2ClockPrevious <= PS2Clock_D; + case State is + when Idle => + DataReady <= '0'; + DReady <= '0'; + BitsRead <= 0; + PS2Error <= '0'; + CountOnes <= '0'; + if PS2Data_D = '0' then -- Start bit + PS2Busy <= '1'; + State <= ReceiveData; + elsif Send = '1' then + Byte <= Command; + PS2Busy <= '1'; + TimeCounter <= 0; + State <= InhibitComunication; + else + State <= Idle; + end if; + when ReceiveData => + if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge + case BitsRead is + when 1 to 8 => -- 8 Data bits + Byte(BitsRead - 1) <= PS2Data_D; + if PS2Data_D = '1' then + CountOnes <= not CountOnes; + end if; + when 9 => -- Parity bit + case CountOnes is + when '0' => + if PS2Data_D = '0' then + PS2Error <= '1'; -- Error when CountOnes is even (0) + else -- and parity bit is unasserted + PS2Error <= '0'; + end if; + when others => + if PS2Data_D = '1' then + PS2Error <= '1'; -- Error when CountOnes is odd (1) + else -- and parity bit is asserted + PS2Error <= '0'; + end if; + end case; + when 10 => -- Stop bit + if PS2Error = '0' then + DataByte <= Byte; + DReady <= '1'; + else + DReady <= '0'; + end if; + State <= WaitRiseClock; + when others => null; + end case; + BitsRead <= BitsRead + 1; + end if; + when InhibitComunication => + PS2Clock_Z <= '0'; + PS2ClockOut <= '0'; + if TimeCounter = Time100us then + TimeCounter <= 0; + State <= RequestToSend; + else + TimeCounter <= TimeCounter + 1; + end if; + when RequestToSend => + PS2Clock_Z <= '1'; + PS2Data_Z <= '0'; + PS2DataOut <= '0'; -- Sets the start bit, valid when PS2Clock is high + if TimeCounter = Time20us then + TimeCounter <= 0; + PS2ClockOut <= '1'; + BitsSent <= 1; + State <= SendData; + else + TimeCounter <= TimeCounter + 1; + end if; + when SendData => + PS2Clock_Z <= '1'; + if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge + case BitsSent is + when 1 to 8 => -- 8 Data bits + if Byte(BitsSent - 1) = '0' then + PS2DataOut <= '0'; + else + CountOnes <= not CountOnes; + PS2DataOut <= '1'; + end if; + when 9 => -- Parity bit + if CountOnes = '0' then + PS2DataOut <= '1'; + else + PS2DataOut <= '0'; + end if; + when 10 => -- Stop bit + PS2DataOut <= '1'; + State <= CheckAck; + when others => null; + end case; + BitsSent <= BitsSent + 1; + end if; + when CheckAck => + PS2Data_Z <= '1'; + if PS2ClockPrevious = '1' and PS2Clock_D = '0' then + if PS2Data_D = '1' then -- no Acknowledge received + PS2Error <= '1'; + end if; + State <= WaitRiseClock; + end if; + when WaitRiseClock => + if PS2ClockPrevious = '0' and PS2Clock_D = '1' then + PS2Busy <= '0'; + DataReady <= DReady; + State <= Idle; + end if; + when others => null; + end case; + end if; + end process; + +end Behavioral; \ No newline at end of file diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/ROM/NitroGroundshaker.hex b/Soundboards_MiST/AS-2518-51_snd-master/rtl/ROM/NitroGroundshaker.hex new file mode 100644 index 00000000..991dd82c --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/ROM/NitroGroundshaker.hex @@ -0,0 +1,129 @@ +:100000008E007F4F97834397828634978386079726 +:10001000817F003F8632CE3D2D0926FD4A26F79688 +:10002000800E3E8E007FCE0033DF31BD10C3860EC2 +:10003000BD10D3BD10EB810327010E3648CE1075DD +:10004000BD10B532810422158607BD10D3863FBD91 +:1000500016448608BD10D3EE00AD002007EE00DF89 +:1000600021BD113B7D003F270BBD12B6CE1323DF10 +:10007000217E113B3E15A2157B17141713158E1404 +:10008000BD12AF14E4157A1507133E13511357131D +:100090005D12A61429157A1559157A140E157A13BE +:1000A00083157A157A14A7145313C8147E13A61354 +:1000B000FB13631429DF2C9B2D24037C002C972D2C +:1000C000DE2C394F36BD10D34FBD1632324C811065 +:1000D00026F239BD112A97809726C603D7825FD7AB +:1000E00082399626810E2603962E39BD111AC60135 +:1000F000D78296805FD782369626840FCE110A4D1E +:100100002704084A26FC32A40039FF0FFF0FFF0F17 +:100110001FFF1F1F1FFFFF0F1FFFD681C4FBD781CB +:10012000375FD78033CA04D78139D681C4FBD781E2 +:10013000375F53D78033CA04D78139DE21E601A661 +:1001400000840F36A60084F0CE12157F003D444493 +:1001500044BD10B532EE00AD0020E03932323937FF +:10016000BD10D332BD163220164D2702D647D725F3 +:100170009625270B7A0025CE007D0926FD20F1DE8D +:10018000210808DF2139DE2120F88DF3201C37BD3E +:1001900010D3BD10E28DE8334D271E200D37BD1062 +:1001A000D3BD10E28DD9334D260F5D2B0DC47FDBFF +:1001B00022D722C600D921D7213950C47F9622D711 +:1001C0002290229722D621C200D7213937DE21E69C +:1001D0000237BD117FBD1186DE319621A700962220 +:1001E000A7010808DF3132972232972139DE310921 +:1001F00009A6009721A6019722DF3139BD10D38DC2 +:1002000006BD16327E11869627489B2748489B27B5 +:100210008B01972739115F123812351242123F11A4 +:100220008A119D118E116911FC129611ED12721234 +:1002300084115B115C73003DBD1186C601200673FD +:10024000003DBD117F37BD10D3BD10E2337D003DB1 +:100250002B031B20011025037E1632BD1632962675 +:1002600085F9260481062605810B2701394CC60134 +:1002700020D37F002FD730BD10D3DE2FA600BD16B0 +:10028000327E117F7F002FD730BD10D3BD10E2DE4C +:100290002FA7007E117F4D270ABD1186EE00AD000D +:1002A0007E117F7E11CCA112AAF08606973F39A15C +:1002B00012B27F003F3ECE0040DF1DC608963F8150 +:1002C000012605CE131B202781022605CE131320FD +:1002D0001E81032605CE130B201581042605CE139F +:1002E00003200C81052605CE12FB2003CE12F3BDA0 +:1002F00016FF39FF0B870C0D0A0403FF09000D0DD3 +:100300000A0403FF07BE0A0E0B0403FF0600080ED3 +:100310000C0303FF055E050E0D0303FF04AF020F80 +:100320000E030307FCC242C343C844C945CF46C1BC +:1003300041C04081472070FB212F7FF550EF00C066 +:10034000023007FC080F090C80196901292878F888 +:10035000F00090022450EB0073021D50E500600293 +:100360001850DF07F708100C280D010F070E0716AD +:1003700080042E7EFA0E102680042E7EFA2F7FED4A +:100380000800F007F608100C280D0100100F070EEA +:1003900007101680042E7EFA0E102680042E7EFA98 +:1003A0002F7FEC0800F007FE08100C080D0100205C +:1003B000A013BB3020A013BB0800F00E20202E7E1F +:1003C000FC0E20102E7EFCB007FC081009100C104B +:1003D0000D01002802280F08A013EA3028A013EA14 +:1003E00040102F7FF308000900F00E082032102E75 +:1003F0007EFA0E081032102E7EFAB007F70C28088D +:10040000100D090F0C96807D2F7FFA0800F007FE73 +:1004100008300C000B600D0E0E028001400201003E +:1004200070F81C2E7EF40800F007FE0030080C0661 +:100430000C0F000E018008181F2E7EF9080A3003E9 +:100440001F8008181E2F7FF9080A30031E2676E544 +:100450000800F007FE008008000F000E0F8008184B +:1004600040061F2E7EF7080000802F6F10800818AE +:1004700040061E2F7FF7080000802E7EE0F0A114BA +:100480009B07FE01000C2808300D090F100E4000DC +:1004900070202E7EFC2F7FF507FFF0963F27078107 +:1004A0000127037A003F390F0307FE080F0E4000B3 +:1004B000308003102E7EFA07FF2F7FEDF007FE003D +:1004C0008008000F000E0F8008181F2E7EF908000C +:1004D00040032F6F0E8008181E2F7FF9080040037D +:1004E0002E7EE4F009300C0E020107FD0D0D128086 +:1004F0000A72FB800008300C18070706010D011670 +:10050000800A76FB80FFF0030F07FC080F090A0E34 +:1005100004010600008000207002212E7EF70830C2 +:100520000C05004001000D0D0F140E0A8004102E62 +:100530007EFA0E0A8001202E7EFA102F7FEC090031 +:1005400008300C2807F706010D0116800A76FB809B +:10055000FFA11555F07F003F3907F502300830093B +:10056000300C2006010D0E8050162276FA0E2080E7 +:1005700050122E7EFA08000900F0F0CE0001DF1DB7 +:10058000C606CE174EBD16FFC60FD71C204ACE009A +:1005900000DF1DC61CCE1754BD16FFC6AFD71C7E8C +:1005A0001650860F971C973ECE0001DF1DCE1770A8 +:1005B000C606BD16FF8D21CE0001DF1DCE1770C609 +:1005C00006BD16FF8D12963E4A81082706971C9796 +:1005D0003E20D54FBD164439961CD605D707D60206 +:1005E000D70843840FD6018D5B5A26FDC6035A26D1 +:1005F000FD43840FD6018D4C5A26FD7A000827173B +:100600007A000726DD43840FD6058D38D707D6013B +:100610009B062B1D01201408090143840FD6028D6F +:1006200023D708D601D003D1042706D701C005205F +:10063000B839D626C10E2603972E39C10726028463 +:10064000BFBD112A379780C602D7827F0082333917 +:10065000CE16F1DF1F8680D6032A09D627545454BC +:100660005C5A26FD7A0008274C7A0009274C7A004C +:100670000A274C7A000B26DFD60327DBC47FD70B73 +:10068000D62758DB27CB0BD7277A001B260ED60F91 +:10069000D71BDE1F098C16EA274EDF1FD6272B0635 +:1006A000D407C47F2005D407C47F50361B1632DE22 +:1006B0001FAD0020A2CE00002008CE00012003CEF6 +:1006C00000026D1827126A18260EE60CE718E600DD +:1006D000EB10E1142712E700E600E708AB04600422 +:1006E00016DE1FAD007E16573954545454545454DA +:1006F000548D073617BD1644323954545454393684 +:10070000A600DF1FDE1DA7007C001EDE1F085A2684 +:10071000EF32390FC611D71586FE9701CE01C009F9 +:100720002722D700860FBD16440927187A00002615 +:10073000F8092710D7004FBD16440927077A000093 +:1007400026F820DBD001C11022D296800E39FE049B +:100750000204FF00010A00003F3F0000010A000000 +:10076000050500000101000031FF00000505000043 +:100770004803010CFF000000000000000000000022 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:1007A0000000000000000000000000000000000049 +:1007B0000000000000000000000000000000000039 +:1007C0000000000000000000000000000000000029 +:1007D0000000000000000000000000000000000019 +:1007E0000000000000000000000000000000000009 +:1007F0000000000000000000102310001000100096 +:00000001FF diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.qip b/Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.qip new file mode 100644 index 00000000..230a8b5d --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "U4_ROM.vhd"] diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.vhd new file mode 100644 index 00000000..5399db6b --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/U4_ROM.vhd @@ -0,0 +1,143 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: U4_ROM.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY U4_ROM IS + PORT + ( + address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END U4_ROM; + + +ARCHITECTURE SYN OF u4_rom IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "./ROM/NitroGroundshaker.hex", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 2048, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + widthad_a => 11, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "./ROM/NitroGroundshaker.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROM/NitroGroundshaker.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL U4_ROM_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910-core.Vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910-core.Vhd new file mode 100644 index 00000000..2ac88ad0 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910-core.Vhd @@ -0,0 +1,375 @@ +library IEEE; +use IEEE.std_logic_1164.all; +Use IEEE.std_logic_arith.all; +Use IEEE.std_logic_unsigned.all; + +-- (async) 5 to 8-bit linear to log value convolver +entity lin5_to_log8 is +port +( + a : in std_logic_vector(4 downto 0); + o : out std_logic_vector(7 downto 0) +); +end lin5_to_log8; + +architecture rtl of lin5_to_log8 is +begin + o <= X"00" when a = "00000" else + X"01" when a = "00001" else + X"01" when a = "00010" else + X"02" when a = "00011" else + X"02" when a = "00100" else + X"02" when a = "00101" else + X"03" when a = "00110" else + X"04" when a = "00111" else + X"04" when a = "01000" else + X"05" when a = "01001" else + X"06" when a = "01010" else + X"08" when a = "01011" else + X"09" when a = "01100" else + X"0B" when a = "01101" else + X"0D" when a = "01110" else + X"10" when a = "01111" else + X"13" when a = "10000" else + X"16" when a = "10001" else + X"1B" when a = "10010" else + X"20" when a = "10011" else + X"26" when a = "10100" else + X"2D" when a = "10101" else + X"36" when a = "10110" else + X"40" when a = "10111" else + X"4C" when a = "11000" else + X"5A" when a = "11001" else + X"6B" when a = "11010" else + X"80" when a = "11011" else + X"98" when a = "11100" else + X"B5" when a = "11101" else + X"D7" when a = "11110" else + X"FF" when a = "11111"; +end rtl; + + + +library IEEE; +use IEEE.std_logic_1164.all; +Use IEEE.std_logic_arith.all; +Use IEEE.std_logic_unsigned.all; + +-- AY-3-8910 sound generator +-- Internals +entity ay_3_8910_core is +port +( + clk : in std_logic; + reset : in std_logic; + clk_en : in std_logic; -- Clock enable pulse - this should occur between 1 and 2.5MHz + + -- Registers + TPA : in std_logic_vector(11 downto 0); -- Tone generator period channel A + TPB : in std_logic_vector(11 downto 0); -- Tone generator period channel B + TPC : in std_logic_vector(11 downto 0); -- Tone generator period channel C + NGP : in std_logic_vector(4 downto 0); -- Noise generator period + MCIOEN : in std_logic_vector(7 downto 0); -- Mixer, control and I/O enable + ACA : in std_logic_vector(4 downto 0); -- Amplitude control channel A + ACB : in std_logic_vector(4 downto 0); -- Amplitude control channel B + ACC : in std_logic_vector(4 downto 0); -- Amplitude control channel C + EPC : in std_logic_vector(15 downto 0); -- Envelope period control + ESR : in std_logic_vector(3 downto 0); -- Envelope shape/cycle control + ESR_updated : in std_logic; -- ESR was written, reset envelope + + -- Sound output + snd_A : out std_logic_vector(7 downto 0); + snd_B : out std_logic_vector(7 downto 0); + snd_C : out std_logic_vector(7 downto 0); + + -- Test outputs + deb_clk16_en : out std_logic; + deb_clk1256_en : out std_logic; + deb_wave_A : out std_logic; + deb_wave_B : out std_logic; + deb_wave_C : out std_logic; + deb_noise_out : out std_logic; + deb_mixed_A : out std_logic; + deb_mixed_B : out std_logic; + deb_mixed_C : out std_logic; + deb_env_out : out std_logic_vector(3 downto 0); + deb_ampl_A : out std_logic_vector(3 downto 0); + deb_ampl_B : out std_logic_vector(3 downto 0); + deb_ampl_C : out std_logic_vector(3 downto 0); + deb_psnd_A : out std_logic_vector(4 downto 0); + deb_psnd_B : out std_logic_vector(4 downto 0); + deb_psnd_C : out std_logic_vector(4 downto 0); + deb_ef_cont : out std_logic; + deb_ef_attack : out std_logic; + deb_ef_alt : out std_logic; + deb_ef_hold : out std_logic; + + deb_div_cnt : out std_logic_vector(7 downto 0); + deb_tcnt_A : out std_logic_vector(11 downto 0); + deb_tcnt_B : out std_logic_vector(11 downto 0); + deb_tcnt_C : out std_logic_vector(11 downto 0); + deb_nse : out std_logic_vector(4 downto 0); + deb_ecnt : out std_logic_vector(15 downto 0); + deb_ephase : out std_logic_vector(3 downto 0); + deb_nse_lfsr : out std_logic_vector(17 downto 0); + deb_noise_in : out std_logic; + deb_env_holding : out std_logic; + deb_env_inv : out std_logic + +) ; +end ay_3_8910_core; + +architecture rtl of ay_3_8910_core is + + signal clk16_en : std_logic; -- High 1/16 of input clock + signal clk256_en : std_logic; -- High 1/256 of input clock + + signal wave_A : std_logic; -- Square wave A + signal wave_B : std_logic; -- Square wave B + signal wave_C : std_logic; -- Square wave C + + signal noise_out : std_logic; -- Noise wave + + signal mixed_A : std_logic; -- Mixed wave A + signal mixed_B : std_logic; -- Mixed wave B + signal mixed_C : std_logic; -- Mixed wave C + + signal env_out : std_logic_vector(3 downto 0); -- Envelope wave + + signal ampl_A : std_logic_vector(3 downto 0); -- Current amplitude, channel A + signal ampl_B : std_logic_vector(3 downto 0); -- Current amplitude, channel B + signal ampl_C : std_logic_vector(3 downto 0); -- Current amplitude, channel C + + signal psnd_A : std_logic_vector(4 downto 0); -- Sound out, channel A, pre lin-log + signal psnd_B : std_logic_vector(4 downto 0); -- Sound out, channel A, pre lin-log + signal psnd_C : std_logic_vector(4 downto 0); -- Sound out, channel A, pre lin-log + + signal ef_cont : std_logic; -- Envelope continue + signal ef_attack : std_logic; -- Envelope attack + signal ef_alt : std_logic; -- Envelope alternate + signal ef_hold : std_logic; -- Envelope hold + + use work.all; + +begin + + -- Magic helper signals + ef_cont <= ESR(3); + ef_attack <= ESR(2); + ef_alt <= ESR(1); + ef_hold <= ESR(0); + + -- Debug signals + deb_clk16_en <= clk16_en; + deb_clk1256_en <= clk256_en; + deb_wave_A <= wave_A; + deb_wave_B <= wave_B; + deb_wave_C <= wave_C; + deb_noise_out <= noise_out; + deb_mixed_A <= mixed_A; + deb_mixed_B <= mixed_B; + deb_mixed_C <= mixed_C; + deb_env_out <= env_out; + deb_ampl_A <= ampl_A; + deb_ampl_B <= ampl_B; + deb_ampl_C <= ampl_C; + deb_psnd_A <= psnd_A; + deb_psnd_B <= psnd_B; + deb_psnd_C <= psnd_C; + deb_ef_cont <= ef_cont; + deb_ef_attack <= ef_attack; + deb_ef_alt <= ef_alt; + deb_ef_hold <= ef_hold; + + -- Waveform mixer scale selection + ampl_A <= env_out when ACA(4) = '1' else ACA(3 downto 0); + ampl_B <= env_out when ACB(4) = '1' else ACB(3 downto 0); + ampl_C <= env_out when ACC(4) = '1' else ACC(3 downto 0); + + -- Waveform output + psnd_A(4 downto 1) <= ampl_A when mixed_A = '1' else X"0"; psnd_A(0) <= '1'; + psnd_B(4 downto 1) <= ampl_B when mixed_B = '1' else X"0"; psnd_B(0) <= '1'; + psnd_C(4 downto 1) <= ampl_C when mixed_C = '1' else X"0"; psnd_C(0) <= '1'; + + -- Instantiate linear to logarithmic output convolvers + sA_log: entity lin5_to_log8 port map(a => psnd_A, o => snd_A); + sB_log: entity lin5_to_log8 port map(a => psnd_B, o => snd_B); + sC_log: entity lin5_to_log8 port map(a => psnd_C, o => snd_C); + + -- Waveform mixers + mixed_A <= (wave_A or MCIOEN(0)) and (noise_out or MCIOEN(3)); + mixed_B <= (wave_B or MCIOEN(1)) and (noise_out or MCIOEN(4)); + mixed_C <= (wave_C or MCIOEN(2)) and (noise_out or MCIOEN(5)); + + -- Main process + process (clk, clk_en, reset) + + variable div_cnt : std_logic_vector(7 downto 0); -- Clock divider counter + + variable wave_A_v : std_logic; -- Square wave A + variable wave_B_v : std_logic; -- Square wave B + variable wave_C_v : std_logic; -- Square wave C + + variable tcnt_A : std_logic_vector(11 downto 0); -- Square wave A period counter + variable tcnt_B : std_logic_vector(11 downto 0); -- Square wave B period counter + variable tcnt_C : std_logic_vector(11 downto 0); -- Square wave C period counter + variable nse : std_logic_vector(4 downto 0); -- Noise period counter + + variable ecnt : std_logic_vector(15 downto 0); -- Envelope period counter + variable ephase : std_logic_vector(3 downto 0); -- Envelope waveform counter + + variable nse_lfsr : std_logic_vector(17 downto 0); -- Noise generator LFSR + variable noise_in : std_logic; + + variable env_holding: std_logic; -- Envelope in hold state + variable env_inv : std_logic; -- Envelope inverted + + begin + + -- Debug signals + deb_div_cnt <= div_cnt; -- 7 downto 0 + deb_tcnt_A <= tcnt_A; -- 11 downto 0 + deb_tcnt_B <= tcnt_B; -- 11 downto 0 + deb_tcnt_C <= tcnt_C; -- 11 downto 0 + deb_nse <= nse; -- 4 downto 0 + deb_ecnt <= ecnt; -- 15 downto 0 + deb_ephase <= ephase; -- 3 downto 0 + deb_nse_lfsr <= nse_lfsr; -- 17 downto 0 + deb_noise_in <= noise_in; + deb_env_holding <= env_holding; + deb_env_inv <= env_inv; + + wave_A <= wave_A_v; + wave_B <= wave_B_v; + wave_C <= wave_C_v; + + if div_cnt(3 downto 0) = "1111" then + clk16_en <= '1'; + else + clk16_en <= '0'; + end if; + +-- clk256_en <= (div_cnt = "11111111"); + + noise_out <= nse_lfsr(0); + + if reset = '1' then + wave_A_v := '0'; + wave_B_v := '0'; + wave_C_v := '0'; + + div_cnt := X"00"; + tcnt_A := X"000"; + tcnt_B := X"000"; + tcnt_C := X"000"; + nse_lfsr := "000000000000000000"; + + ecnt := X"0000"; + ephase := X"0"; + env_holding := '0'; + env_inv := '0'; + + elsif rising_edge(clk) then + + if clk_en = '1' then + -- Clock divider + div_cnt := div_cnt + 1; + + -- Envelope shape/cycle control updated, reset envelope state + if ESR_updated = '1' then + ecnt := X"0000"; + ephase := X"0"; + env_holding := '0'; + env_inv := '0'; + end if; + + -- Envelope waveform generation + -- Envelope holding + if env_holding = '1' then + if ef_cont = '1' then + env_out(3) <= (ef_attack xor ef_alt); + env_out(2) <= (ef_attack xor ef_alt); + env_out(1) <= (ef_attack xor ef_alt); + env_out(0) <= (ef_attack xor ef_alt); + else + env_out <= X"0"; + end if; + -- Otherwise envelope is a function of ephase + else + env_out(3) <= ((not ef_attack) xor env_inv) xor ephase(3); + env_out(2) <= ((not ef_attack) xor env_inv) xor ephase(2); + env_out(1) <= ((not ef_attack) xor env_inv) xor ephase(1); + env_out(0) <= ((not ef_attack) xor env_inv) xor ephase(0); + end if; + + -- Events with period clk/16 + if clk16_en = '1' then + -- Tone generator counters + -- Channel A + if unsigned(tcnt_A) >= unsigned(TPA) then + wave_A_v := not wave_A_v; + tcnt_A := X"000"; + else + tcnt_A := tcnt_A + 1; + end if; + + -- Channel B + if unsigned(tcnt_B) >= unsigned(TPB) then + wave_B_v := not wave_B_v; + tcnt_B := X"000"; + else + tcnt_B := tcnt_B + 1; + end if; + + -- Channel C + if unsigned(tcnt_C) >= unsigned(TPC) then + wave_C_v := not wave_C_v; + tcnt_C := X"000"; + else + tcnt_C := tcnt_C + 1; + end if; + + -- Noise period counter and LFSR + if nse >= NGP then + nse := "00000"; + noise_in := nse_lfsr(0) xnor nse_lfsr(3); -- Input = bit 0 xor bit 3 + nse_lfsr(16 downto 0) := nse_lfsr(17 downto 1); -- Shift right - bit 0 is output bit + nse_lfsr(17) := noise_in; -- Bit 16 is input bit + else + nse := nse + 1; + end if; + + -- Envelope counters + if ecnt >= EPC then + if ephase = "1111" then + -- If hold flag is set, latch hold value after one envelope cycle + if ef_hold = '1' or ef_cont = '0' then + env_holding := '1'; + end if; + + -- If alternate flag is set, toggle inverted flag + if ef_alt = '1' then + env_inv := not env_inv; + end if; + ephase := X"0"; + else + ephase := ephase + 1; + end if; + ecnt := X"0000"; + else + ecnt := ecnt + 1; + end if; + + end if; + + -- Events with period clk/256 +-- if clk256_en = '1' then +-- end if; + + end if; + end if; + end process; +end rtl; + + + diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910.Vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910.Vhd new file mode 100644 index 00000000..84ed6210 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910.Vhd @@ -0,0 +1,262 @@ +library IEEE; +use IEEE.std_logic_1164.all; +Use IEEE.std_logic_unsigned.all; + +-- AY-3-8910 sound generator +-- Chip-level module, registers and decoding +entity ay_3_8910 is +port +( + -- AY-3-8910 sound controller + clk : in std_logic; + reset : in std_logic; + clk_en : in std_logic; -- Clock enable pulse - this should occur between 1 and 2.5MHz + + -- CPU I/F + cpu_d_in : in std_logic_vector(7 downto 0); + cpu_d_out : out std_logic_vector(7 downto 0); + cpu_bdir : in std_logic; + cpu_bc1 : in std_logic; + cpu_bc2 : in std_logic; + + -- I/O I/F + io_a_in : in std_logic_vector(7 downto 0); + io_b_in : in std_logic_vector(7 downto 0); + io_a_out : out std_logic_vector(7 downto 0); + io_b_out : out std_logic_vector(7 downto 0); + + -- Sound output + snd_A : out std_logic_vector(7 downto 0); + snd_B : out std_logic_vector(7 downto 0); + snd_C : out std_logic_vector(7 downto 0) + + -- Debug + --deb_addr : out std_logic_vector(3 downto 0); + --deb_TPA : out std_logic_vector(11 downto 0); -- Tone generator period channel A + --deb_TPB : out std_logic_vector(11 downto 0); -- Tone generator period channel B + --deb_TPC : out std_logic_vector(11 downto 0); -- Tone generator period channel C + --deb_NGP : out std_logic_vector(4 downto 0); -- Noise generator period + --deb_MCIOEN : out std_logic_vector(7 downto 0); -- Mixer, control and I/O enable + --deb_ACA : out std_logic_vector(4 downto 0); -- Amplitude control channel A + --deb_ACB : out std_logic_vector(4 downto 0); -- Amplitude control channel B + --deb_ACC : out std_logic_vector(4 downto 0); -- Amplitude control channel C + --deb_EPC : out std_logic_vector(15 downto 0); -- Envelope period control + --deb_ESR : out std_logic_vector(3 downto 0); -- Envelope shape/cycle control + --deb_ESR_updated : out std_logic; -- ESR was written, reset envelope + + -- Test outputs + --deb_clk16_en : out std_logic; + --deb_clk1256_en : out std_logic; + --deb_wave_A : out std_logic; + --deb_wave_B : out std_logic; + --deb_wave_C : out std_logic; + --deb_noise_out : out std_logic; + --deb_mixed_A : out std_logic; + --deb_mixed_B : out std_logic; + --deb_mixed_C : out std_logic; + --deb_env_out : out std_logic_vector(3 downto 0); + --deb_ampl_A : out std_logic_vector(3 downto 0); + --deb_ampl_B : out std_logic_vector(3 downto 0); + --deb_ampl_C : out std_logic_vector(3 downto 0); + --deb_psnd_A : out std_logic_vector(4 downto 0); + --deb_psnd_B : out std_logic_vector(4 downto 0); + --deb_psnd_C : out std_logic_vector(4 downto 0); + --deb_ef_cont : out std_logic; + --deb_ef_attack : out std_logic; + --deb_ef_alt : out std_logic; + --deb_ef_hold : out std_logic; + + --deb_div_cnt : out std_logic_vector(7 downto 0); + --deb_tcnt_A : out std_logic_vector(11 downto 0); + --deb_tcnt_B : out std_logic_vector(11 downto 0); + --deb_tcnt_C : out std_logic_vector(11 downto 0); + --deb_nse : out std_logic_vector(4 downto 0); + --deb_ecnt : out std_logic_vector(15 downto 0); + --deb_ephase : out std_logic_vector(3 downto 0); + --deb_nse_lfsr : out std_logic_vector(17 downto 0); + --deb_noise_in : out std_logic; + --deb_env_holding : out std_logic; + --deb_env_inv : out std_logic + +) ; +end ay_3_8910; + +architecture rtl of ay_3_8910 is + signal TPA : std_logic_vector(11 downto 0); -- Tone generator period channel A + signal TPB : std_logic_vector(11 downto 0); -- Tone generator period channel B + signal TPC : std_logic_vector(11 downto 0); -- Tone generator period channel C + signal NGP : std_logic_vector(4 downto 0); -- Noise generator period + signal MCIOEN : std_logic_vector(7 downto 0); -- Mixer, control and I/O enable + signal ACA : std_logic_vector(4 downto 0); -- Amplitude control channel A + signal ACB : std_logic_vector(4 downto 0); -- Amplitude control channel B + signal ACC : std_logic_vector(4 downto 0); -- Amplitude control channel C + signal EPC : std_logic_vector(15 downto 0); -- Envelope period control + signal ESR : std_logic_vector(3 downto 0); -- Envelope shape/cycle control + signal PAO : std_logic_vector(7 downto 0); -- Port A out + signal PBO : std_logic_vector(7 downto 0); -- Port B out + signal ESR_updated : std_logic; -- ESR was written, reset envelope + + use work.all; + +begin + + -- Connect core sound processing module to input registers + ay_core: entity ay_3_8910_core port map(clk => clk, reset => reset, clk_en => clk_en, + TPA => TPA, TPB => TPB, TPC => TPC, NGP => NGP, MCIOEN => MCIOEN, ACA => ACA, ACB => ACB, + ACC => ACC, EPC => EPC, ESR => ESR, ESR_updated => ESR_updated, + snd_A => snd_A, snd_B => snd_B, snd_C => snd_C + --deb_clk16_en => deb_clk16_en, + --deb_clk1256_en => deb_clk1256_en, + --deb_wave_A => deb_wave_A, + --deb_wave_B => deb_wave_B, + --deb_wave_C => deb_wave_C, + --deb_noise_out => deb_noise_out, + --deb_mixed_A => deb_mixed_A, + --deb_mixed_B => deb_mixed_B, + --deb_mixed_C => deb_mixed_C, + --deb_env_out => deb_env_out, + --deb_ampl_A => deb_ampl_A, + --deb_ampl_B => deb_ampl_B, + --deb_ampl_C => deb_ampl_C, + --deb_psnd_A => deb_psnd_A, + --deb_psnd_B => deb_psnd_B, + --deb_psnd_C => deb_psnd_C, + --deb_ef_cont => deb_ef_cont, + --deb_ef_attack => deb_ef_attack, + --deb_ef_alt => deb_ef_alt, + --deb_ef_hold => deb_ef_hold, + --deb_div_cnt => deb_div_cnt, + --deb_tcnt_A => deb_tcnt_A, + --deb_tcnt_B => deb_tcnt_B, + --deb_tcnt_C => deb_tcnt_C, + --deb_nse => deb_nse, + --deb_ecnt => deb_ecnt, + --deb_ephase => deb_ephase, + --deb_nse_lfsr => deb_nse_lfsr, + --deb_noise_in => deb_noise_in, + --deb_env_holding => deb_env_holding, + --deb_env_inv => deb_env_inv + + ); + + -- I/O outputs + io_a_out <= PAO when MCIOEN(6) = '0' else X"FF"; + io_b_out <= PBO when MCIOEN(7) = '0' else X"FF"; + + -- Main process + process (clk, clk_en, reset) + variable addr : std_logic_vector(3 downto 0); -- Addressed register + + variable rTPA : std_logic_vector(11 downto 0); -- Tone generator period channel A + variable rTPB : std_logic_vector(11 downto 0); -- Tone generator period channel B + variable rTPC : std_logic_vector(11 downto 0); -- Tone generator period channel C + variable rNGP : std_logic_vector(4 downto 0); -- Noise generator period + variable rMCIOEN : std_logic_vector(7 downto 0); -- Mixer, control and I/O enable + variable rACA : std_logic_vector(4 downto 0); -- Amplitude control channel A + variable rACB : std_logic_vector(4 downto 0); -- Amplitude control channel B + variable rACC : std_logic_vector(4 downto 0); -- Amplitude control channel C + variable rEPC : std_logic_vector(15 downto 0); -- Envelope period control + variable rESR : std_logic_vector(3 downto 0); -- Envelope shape/cycle control + variable rPAO : std_logic_vector(7 downto 0); -- Port A out + variable rPBO : std_logic_vector(7 downto 0); -- Port B out + variable rESR_updated : std_logic; -- ESR was written, reset envelope + begin + TPA <= rTPA; TPB <= rTPB; + TPC <= rTPC; NGP <= rNGP; + MCIOEN <= rMCIOEN; ACA <= rACA; + ACB <= rACB; ACC <= rACC; + EPC <= rEPC; ESR <= rESR; + PAO <= rPAO; PBO <= rPBO; + ESR_updated <= rESR_updated; + + -- Debug + --deb_addr <= addr; + --deb_TPA <= TPA; + --deb_TPB <= TPB; + --deb_TPC <= TPC; + --deb_NGP <= NGP; + --deb_MCIOEN <= MCIOEN; + --deb_ACA <= ACA; + --deb_ACB <= ACB; + --deb_ACC <= ACC; + --deb_EPC <= EPC; + --deb_ESR <= ESR; + --deb_ESR_updated <= ESR_updated; + + if reset = '1' then + + rTPA := X"000"; + rTPB := X"000"; + rTPC := X"000"; + rNGP := "00000"; + rMCIOEN := X"00"; + rACA := "00000"; + rACB := "00000"; + rACC := "00000"; + rEPC := X"0000"; + rESR := X"0"; + rESR_updated := '0'; + + elsif rising_edge(clk) then + +-- if clk_en = '1' then + rESR_updated := '0'; + + -- Latch address + if (cpu_bdir = '0' and cpu_bc2 = '0' and cpu_bc1 = '1') or + (cpu_bdir = '1' and cpu_bc2 = '0' and cpu_bc1 = '0') or + (cpu_bdir = '1' and cpu_bc2 = '1' and cpu_bc1 = '1') then + + addr(3 downto 0) := cpu_d_in(3 downto 0); + + -- Data write + elsif (cpu_bdir = '1' and cpu_bc2 = '1' and cpu_bc1 = '0') then + case addr(3 downto 0) is + when X"0" => rTPA(7 downto 0) := cpu_d_in(7 downto 0); + when X"1" => rTPA(11 downto 8) := cpu_d_in(3 downto 0); + when X"2" => rTPB(7 downto 0) := cpu_d_in(7 downto 0); + when X"3" => rTPB(11 downto 8) := cpu_d_in(3 downto 0); + when X"4" => rTPC(7 downto 0) := cpu_d_in(7 downto 0); + when X"5" => rTPC(11 downto 8) := cpu_d_in(3 downto 0); + when X"6" => rNGP(4 downto 0) := cpu_d_in(4 downto 0); + when X"7" => rMCIOEN(7 downto 0) := cpu_d_in(7 downto 0); + when X"8" => rACA(4 downto 0) := cpu_d_in(4 downto 0); + when X"9" => rACB(4 downto 0) := cpu_d_in(4 downto 0); + when X"A" => rACC(4 downto 0) := cpu_d_in(4 downto 0); + when X"B" => rEPC(7 downto 0) := cpu_d_in(7 downto 0); + when X"C" => rEPC(15 downto 8) := cpu_d_in(7 downto 0); + when X"D" => rESR(3 downto 0) := cpu_d_in(3 downto 0); rESR_updated := '1'; + when X"E" => rPAO(7 downto 0) := cpu_d_in(7 downto 0); + when X"F" => rPBO(7 downto 0) := cpu_d_in(7 downto 0); + when others => + end case; + + -- Data read + elsif (cpu_bdir = '0' and cpu_bc2 = '1' and cpu_bc1 = '1') then + cpu_d_out <= X"00"; + case addr(3 downto 0) is + when X"0" => cpu_d_out <= rTPA(7 downto 0); + when X"1" => cpu_d_out(3 downto 0) <= rTPA(11 downto 8); + when X"2" => cpu_d_out <= rTPB(7 downto 0); + when X"3" => cpu_d_out(3 downto 0) <= rTPB(11 downto 8); + when X"4" => cpu_d_out <= rTPC(7 downto 0); + when X"5" => cpu_d_out(3 downto 0) <= rTPC(11 downto 8); + when X"6" => cpu_d_out(4 downto 0) <= rNGP(4 downto 0); + when X"7" => cpu_d_out <= rMCIOEN(7 downto 0); + when X"8" => cpu_d_out(4 downto 0) <= rACA(4 downto 0); + when X"9" => cpu_d_out(4 downto 0) <= rACB(4 downto 0); + when X"A" => cpu_d_out(4 downto 0) <= rACC(4 downto 0); + when X"B" => cpu_d_out <= rEPC(7 downto 0); + when X"C" => cpu_d_out <= rEPC(15 downto 8); + when X"D" => cpu_d_out(3 downto 0) <= rESR(3 downto 0); + when X"E" => cpu_d_out <= io_a_in(7 downto 0); + when X"F" => cpu_d_out <= io_b_in(7 downto 0); + when others => + end case; + end if; +-- end if; + + end if; + end process; +end rtl; + diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910_vectors.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910_vectors.vhd new file mode 100644 index 00000000..c8e4deb0 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/ay-3-8910_vectors.vhd @@ -0,0 +1,1165 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +entity rominfr is + port ( + clk : in std_logic; + en : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(47 downto 0) + ); +end rominfr; +architecture syn of rominfr is + type rom_type is array (1136 downto 0) of std_logic_vector (47 downto 0); + constant ROM : rom_type := +( + X"000000000000", -- len= 0 r=$00 v=$00 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000000200", -- len= 0 r=$02 v=$00 + X"000000000300", -- len= 0 r=$03 v=$00 + X"000000000400", -- len= 0 r=$04 v=$00 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000000600", -- len= 0 r=$06 v=$00 + X"000000000700", -- len= 0 r=$07 v=$00 + X"000000000800", -- len= 0 r=$08 v=$00 + X"000000000900", -- len= 0 r=$09 v=$00 + X"000000000A00", -- len= 0 r=$0A v=$00 + X"000000000B00", -- len= 0 r=$0B v=$00 + X"000000000C00", -- len= 0 r=$0C v=$00 + X"000000000D00", -- len= 0 r=$0D v=$00 + X"00000390073F", -- len= 912 r=$07 v=$3F + X"000000000800", -- len= 0 r=$08 v=$00 + X"000000000900", -- len= 0 r=$09 v=$00 + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00000000073F", -- len= 0 r=$07 v=$3F + X"00000000073F", -- len= 0 r=$07 v=$3F + X"000000000800", -- len= 0 r=$08 v=$00 + X"00000000073F", -- len= 0 r=$07 v=$3F + X"000000000900", -- len= 0 r=$09 v=$00 + X"00000000073F", -- len= 0 r=$07 v=$3F + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00011704073F", -- len= 71428 r=$07 v=$3F + X"000002D8073F", -- len= 728 r=$07 v=$3F + X"000000000800", -- len= 0 r=$08 v=$00 + X"000000000900", -- len= 0 r=$09 v=$00 + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00000000073F", -- len= 0 r=$07 v=$3F + X"00000000073F", -- len= 0 r=$07 v=$3F + X"000000000800", -- len= 0 r=$08 v=$00 + X"00000000073F", -- len= 0 r=$07 v=$3F + X"000000000900", -- len= 0 r=$09 v=$00 + X"00000000073F", -- len= 0 r=$07 v=$3F + X"000000000A00", -- len= 0 r=$0A v=$00 + X"000038D40020", -- len= 14548 r=$00 v=$20 + X"000000000100", -- len= 0 r=$01 v=$00 + X"00000004073E", -- len= 4 r=$07 v=$3E + X"000000030809", -- len= 3 r=$08 v=$09 + X"000007D70808", -- len= 2007 r=$08 v=$08 + X"000007E30807", -- len= 2019 r=$08 v=$07 + X"000007E30806", -- len= 2019 r=$08 v=$06 + X"000007E30805", -- len= 2019 r=$08 v=$05 + X"000007E10804", -- len= 2017 r=$08 v=$04 + X"000007E40803", -- len= 2020 r=$08 v=$03 + X"000007E30802", -- len= 2019 r=$08 v=$02 + X"000007E30801", -- len= 2019 r=$08 v=$01 + X"000007E20800", -- len= 2018 r=$08 v=$00 + X"0000002F0000", -- len= 47 r=$00 v=$00 + X"000000010103", -- len= 1 r=$01 v=$03 + X"000000020808", -- len= 2 r=$08 v=$08 + X"000000CB00F8", -- len= 203 r=$00 v=$F8 + X"000000010102", -- len= 1 r=$01 v=$02 + X"000000AF00F0", -- len= 175 r=$00 v=$F0 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000CB00E8", -- len= 203 r=$00 v=$E8 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000B000E0", -- len= 176 r=$00 v=$E0 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000CA00D8", -- len= 202 r=$00 v=$D8 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000B100D0", -- len= 177 r=$00 v=$D0 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000CA00C8", -- len= 202 r=$00 v=$C8 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000AF00C0", -- len= 175 r=$00 v=$C0 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000CC00B8", -- len= 204 r=$00 v=$B8 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000B000B0", -- len= 176 r=$00 v=$B0 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000C900A8", -- len= 201 r=$00 v=$A8 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000B000A0", -- len= 176 r=$00 v=$A0 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000CC0098", -- len= 204 r=$00 v=$98 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000B00090", -- len= 176 r=$00 v=$90 + X"000000000102", -- len= 0 r=$01 v=$02 + X"000000C90088", -- len= 201 r=$00 v=$88 + X"000000000102", -- len= 0 r=$01 v=$02 + X"0000003D073F", -- len= 61 r=$07 v=$3F + X"00000000073F", -- len= 0 r=$07 v=$3F + X"0000003F0800", -- len= 63 r=$08 v=$00 + X"00000000073F", -- len= 0 r=$07 v=$3F + X"000000000900", -- len= 0 r=$09 v=$00 + X"00000000073F", -- len= 0 r=$07 v=$3F + X"000000000A00", -- len= 0 r=$0A v=$00 + X"000002AD073E", -- len= 685 r=$07 v=$3E + X"0000007300F0", -- len= 115 r=$00 v=$F0 + X"000000010100", -- len= 1 r=$01 v=$00 + X"000000030807", -- len= 3 r=$08 v=$07 + X"00000263073C", -- len= 611 r=$07 v=$3C + X"00000040025D", -- len= 64 r=$02 v=$5D + X"000000010302", -- len= 1 r=$03 v=$02 + X"000000030907", -- len= 3 r=$09 v=$07 + X"0000024D0806", -- len= 589 r=$08 v=$06 + X"0000005E0738", -- len= 94 r=$07 v=$38 + X"000000000A00", -- len= 0 r=$0A v=$00 + X"000002210906", -- len= 545 r=$09 v=$06 + X"000002FD0A06", -- len= 765 r=$0A v=$06 + X"0000045E0805", -- len= 1118 r=$08 v=$05 + X"0000027F0905", -- len= 639 r=$09 v=$05 + X"000002FF0A05", -- len= 767 r=$0A v=$05 + X"0000045E0804", -- len= 1118 r=$08 v=$04 + X"0000027E0904", -- len= 638 r=$09 v=$04 + X"000002FF0A04", -- len= 767 r=$0A v=$04 + X"0000045E0803", -- len= 1118 r=$08 v=$03 + X"0000027F0903", -- len= 639 r=$09 v=$03 + X"00000277002E", -- len= 631 r=$00 v=$2E + X"000000010101", -- len= 1 r=$01 v=$01 + X"000000040807", -- len= 4 r=$08 v=$07 + X"000000810A03", -- len= 129 r=$0A v=$03 + X"000001FA02E0", -- len= 506 r=$02 v=$E0 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000002620806", -- len= 610 r=$08 v=$06 + X"00000096045D", -- len= 150 r=$04 v=$5D + X"000000010502", -- len= 1 r=$05 v=$02 + X"000000040A07", -- len= 4 r=$0A v=$07 + X"000001E40906", -- len= 484 r=$09 v=$06 + X"000002FD0A06", -- len= 765 r=$0A v=$06 + X"0000045E0805", -- len= 1118 r=$08 v=$05 + X"000002800905", -- len= 640 r=$09 v=$05 + X"000002FD0A05", -- len= 765 r=$0A v=$05 + X"0000045E0804", -- len= 1118 r=$08 v=$04 + X"0000027F0904", -- len= 639 r=$09 v=$04 + X"000002FF0A04", -- len= 767 r=$0A v=$04 + X"0000045E0803", -- len= 1118 r=$08 v=$03 + X"0000027E0903", -- len= 638 r=$09 v=$03 + X"00000000002E", -- len= 0 r=$00 v=$2E + X"000000000101", -- len= 0 r=$01 v=$01 + X"0000027D0807", -- len= 637 r=$08 v=$07 + X"000000810A03", -- len= 129 r=$0A v=$03 + X"000001FA0227", -- len= 506 r=$02 v=$27 + X"000000010303", -- len= 1 r=$03 v=$03 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000002610806", -- len= 609 r=$08 v=$06 + X"000000930A00", -- len= 147 r=$0A v=$00 + X"000001ED0906", -- len= 493 r=$09 v=$06 + X"000002FD0A02", -- len= 765 r=$0A v=$02 + X"0000045E0805", -- len= 1118 r=$08 v=$05 + X"0000027E0905", -- len= 638 r=$09 v=$05 + X"000002FF0A01", -- len= 767 r=$0A v=$01 + X"0000045E0804", -- len= 1118 r=$08 v=$04 + X"0000027E0904", -- len= 638 r=$09 v=$04 + X"000002FE0A00", -- len= 766 r=$0A v=$00 + X"0000045F0803", -- len= 1119 r=$08 v=$03 + X"0000027F0903", -- len= 639 r=$09 v=$03 + X"0000000D002E", -- len= 13 r=$00 v=$2E + X"000000000101", -- len= 0 r=$01 v=$01 + X"000002700807", -- len= 624 r=$08 v=$07 + X"0000027902E0", -- len= 633 r=$02 v=$E0 + X"000000020301", -- len= 2 r=$03 v=$01 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000002610806", -- len= 609 r=$08 v=$06 + X"00000000045D", -- len= 0 r=$04 v=$5D + X"000000000502", -- len= 0 r=$05 v=$02 + X"0000009D0A07", -- len= 157 r=$0A v=$07 + X"000001E30906", -- len= 483 r=$09 v=$06 + X"000002FC0A06", -- len= 764 r=$0A v=$06 + X"000004600805", -- len= 1120 r=$08 v=$05 + X"0000027F0905", -- len= 639 r=$09 v=$05 + X"000002FC0A05", -- len= 764 r=$0A v=$05 + X"0000045F0804", -- len= 1119 r=$08 v=$04 + X"000002800904", -- len= 640 r=$09 v=$04 + X"000002FD0A04", -- len= 765 r=$0A v=$04 + X"0000045E0803", -- len= 1118 r=$08 v=$03 + X"000002800903", -- len= 640 r=$09 v=$03 + X"0000027700F0", -- len= 631 r=$00 v=$F0 + X"000000010100", -- len= 1 r=$01 v=$00 + X"000000030807", -- len= 3 r=$08 v=$07 + X"000000820A03", -- len= 130 r=$0A v=$03 + X"000001F9025D", -- len= 505 r=$02 v=$5D + X"000000010302", -- len= 1 r=$03 v=$02 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000002610806", -- len= 609 r=$08 v=$06 + X"000000950A00", -- len= 149 r=$0A v=$00 + X"000001EB0906", -- len= 491 r=$09 v=$06 + X"000002FD0A02", -- len= 765 r=$0A v=$02 + X"0000045E0805", -- len= 1118 r=$08 v=$05 + X"000002810905", -- len= 641 r=$09 v=$05 + X"000002FC0A01", -- len= 764 r=$0A v=$01 + X"0000045F0804", -- len= 1119 r=$08 v=$04 + X"000002800904", -- len= 640 r=$09 v=$04 + X"000002FD0A00", -- len= 765 r=$0A v=$00 + X"0000045E0803", -- len= 1118 r=$08 v=$03 + X"000002800903", -- len= 640 r=$09 v=$03 + X"00000277002E", -- len= 631 r=$00 v=$2E + X"000000010101", -- len= 1 r=$01 v=$01 + X"000000030807", -- len= 3 r=$08 v=$07 + X"0000027C02E0", -- len= 636 r=$02 v=$E0 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000040907", -- len= 4 r=$09 v=$07 + X"000002610806", -- len= 609 r=$08 v=$06 + X"00000000045D", -- len= 0 r=$04 v=$5D + X"000000000502", -- len= 0 r=$05 v=$02 + X"0000009A0A07", -- len= 154 r=$0A v=$07 + X"000001E50906", -- len= 485 r=$09 v=$06 + X"000002FD0A06", -- len= 765 r=$0A v=$06 + X"0000045E0805", -- len= 1118 r=$08 v=$05 + X"0000027E0905", -- len= 638 r=$09 v=$05 + X"000002FF0A05", -- len= 767 r=$0A v=$05 + X"0000045E0804", -- len= 1118 r=$08 v=$04 + X"0000027F0904", -- len= 639 r=$09 v=$04 + X"000002FC0A04", -- len= 764 r=$0A v=$04 + X"000004610803", -- len= 1121 r=$08 v=$03 + X"0000027E0903", -- len= 638 r=$09 v=$03 + X"000001280738", -- len= 296 r=$07 v=$38 + X"000000DE04BE", -- len= 222 r=$04 v=$BE + X"000000010500", -- len= 1 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"00000000002E", -- len= 0 r=$00 v=$2E + X"000000000101", -- len= 0 r=$01 v=$01 + X"000000EE0807", -- len= 238 r=$08 v=$07 + X"000000560A08", -- len= 86 r=$0A v=$08 + X"000002250227", -- len= 549 r=$02 v=$27 + X"000000010303", -- len= 1 r=$03 v=$03 + X"000000040907", -- len= 4 r=$09 v=$07 + X"0000004D0A07", -- len= 77 r=$0A v=$07 + X"000001370497", -- len= 311 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000000D70806", -- len= 215 r=$08 v=$06 + X"000000620A08", -- len= 98 r=$0A v=$08 + X"0000021E0906", -- len= 542 r=$09 v=$06 + X"0000005A0A07", -- len= 90 r=$0A v=$07 + X"00000137047F", -- len= 311 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013C0A08", -- len= 316 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"00000136045F", -- len= 310 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000000D90805", -- len= 217 r=$08 v=$05 + X"000000620A08", -- len= 98 r=$0A v=$08 + X"0000021D0905", -- len= 541 r=$09 v=$05 + X"0000005A0A07", -- len= 90 r=$0A v=$07 + X"0000013A0471", -- len= 314 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001380A08", -- len= 312 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"000002150804", -- len= 533 r=$08 v=$04 + X"000000630A06", -- len= 99 r=$0A v=$06 + X"0000021C0904", -- len= 540 r=$09 v=$04 + X"0000005A0A05", -- len= 90 r=$0A v=$05 + X"000002770A04", -- len= 631 r=$0A v=$04 + X"000002760A03", -- len= 630 r=$0A v=$03 + X"000002140803", -- len= 532 r=$08 v=$03 + X"000000630A02", -- len= 99 r=$0A v=$02 + X"0000021D0903", -- len= 541 r=$09 v=$03 + X"0000005A0A01", -- len= 90 r=$0A v=$01 + X"000000AE002E", -- len= 174 r=$00 v=$2E + X"000000000101", -- len= 0 r=$01 v=$01 + X"000001730807", -- len= 371 r=$08 v=$07 + X"000000560A00", -- len= 86 r=$0A v=$00 + X"0000022502E0", -- len= 549 r=$02 v=$E0 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000040907", -- len= 4 r=$09 v=$07 + X"000002620806", -- len= 610 r=$08 v=$06 + X"000002320738", -- len= 562 r=$07 v=$38 + X"000000980906", -- len= 152 r=$09 v=$06 + X"0000004604BE", -- len= 70 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013D0A08", -- len= 317 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"000001390497", -- len= 313 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001390A08", -- len= 313 r=$0A v=$08 + X"000001180805", -- len= 280 r=$08 v=$05 + X"0000015E0A07", -- len= 350 r=$0A v=$07 + X"000001200905", -- len= 288 r=$09 v=$05 + X"0000001D047F", -- len= 29 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001360A08", -- len= 310 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"00000138045F", -- len= 312 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001390A08", -- len= 313 r=$0A v=$08 + X"000001180804", -- len= 280 r=$08 v=$04 + X"0000015F0A07", -- len= 351 r=$0A v=$07 + X"000001220904", -- len= 290 r=$09 v=$04 + X"0000001E0471", -- len= 30 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000001310A08", -- len= 305 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"000002760A06", -- len= 630 r=$0A v=$06 + X"000001170803", -- len= 279 r=$08 v=$03 + X"0000015F0A05", -- len= 351 r=$0A v=$05 + X"000001220903", -- len= 290 r=$09 v=$03 + X"000001560A04", -- len= 342 r=$0A v=$04 + X"0000012000E3", -- len= 288 r=$00 v=$E3 + X"000000010100", -- len= 1 r=$01 v=$00 + X"000000030807", -- len= 3 r=$08 v=$07 + X"000001530A03", -- len= 339 r=$0A v=$03 + X"00000128021B", -- len= 296 r=$02 v=$1B + X"000000020302", -- len= 2 r=$03 v=$02 + X"000000030907", -- len= 3 r=$09 v=$07 + X"0000014A0A02", -- len= 330 r=$0A v=$02 + X"000001170806", -- len= 279 r=$08 v=$06 + X"0000015E0A01", -- len= 350 r=$0A v=$01 + X"000001200906", -- len= 288 r=$09 v=$06 + X"000001580A00", -- len= 344 r=$0A v=$00 + X"000006050805", -- len= 1541 r=$08 v=$05 + X"000002800905", -- len= 640 r=$09 v=$05 + X"0000075C0804", -- len= 1884 r=$08 v=$04 + X"0000027E0904", -- len= 638 r=$09 v=$04 + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00000058073C", -- len= 88 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00000000073C", -- len= 0 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"000007040803", -- len= 1796 r=$08 v=$03 + X"000002810903", -- len= 641 r=$09 v=$03 + X"0000014600E3", -- len= 326 r=$00 v=$E3 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000001350807", -- len= 309 r=$08 v=$07 + X"0000027902C5", -- len= 633 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000040907", -- len= 4 r=$09 v=$07 + X"000002620806", -- len= 610 r=$08 v=$06 + X"0000027F0906", -- len= 639 r=$09 v=$06 + X"000000210738", -- len= 33 r=$07 v=$38 + X"0000006B04BE", -- len= 107 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001430A08", -- len= 323 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"000001360497", -- len= 310 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000000E50805", -- len= 229 r=$08 v=$05 + X"000001910A07", -- len= 401 r=$0A v=$07 + X"000000EE0905", -- len= 238 r=$09 v=$05 + X"00000048047F", -- len= 72 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"00000136045F", -- len= 310 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000000E50804", -- len= 229 r=$08 v=$04 + X"000001910A07", -- len= 401 r=$0A v=$07 + X"000000F00904", -- len= 240 r=$09 v=$04 + X"0000004B0471", -- len= 75 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001370A08", -- len= 311 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"000002760A06", -- len= 630 r=$0A v=$06 + X"000000E50803", -- len= 229 r=$08 v=$03 + X"000001910A05", -- len= 401 r=$0A v=$05 + X"000000F00903", -- len= 240 r=$09 v=$03 + X"000001880A04", -- len= 392 r=$0A v=$04 + X"000000EE00F0", -- len= 238 r=$00 v=$F0 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000050807", -- len= 5 r=$08 v=$07 + X"000001B60A03", -- len= 438 r=$0A v=$03 + X"000000F70227", -- len= 247 r=$02 v=$27 + X"000000010303", -- len= 1 r=$03 v=$03 + X"000000030907", -- len= 3 r=$09 v=$07 + X"0000017D0A02", -- len= 381 r=$0A v=$02 + X"000000E50806", -- len= 229 r=$08 v=$06 + X"000001910A01", -- len= 401 r=$0A v=$01 + X"000000EE0906", -- len= 238 r=$09 v=$06 + X"000001880A00", -- len= 392 r=$0A v=$00 + X"000005D30805", -- len= 1491 r=$08 v=$05 + X"000000FF0738", -- len= 255 r=$07 v=$38 + X"000000C404BE", -- len= 196 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001040905", -- len= 260 r=$09 v=$05 + X"000000410A08", -- len= 65 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"000001500497", -- len= 336 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000016E0A08", -- len= 366 r=$0A v=$08 + X"000002140804", -- len= 532 r=$08 v=$04 + X"000000620A07", -- len= 98 r=$0A v=$07 + X"00000136047F", -- len= 310 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000000E10904", -- len= 225 r=$09 v=$04 + X"0000005A0A08", -- len= 90 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"00000139045F", -- len= 313 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013A0A08", -- len= 314 r=$0A v=$08 + X"000002150803", -- len= 533 r=$08 v=$03 + X"000000620A07", -- len= 98 r=$0A v=$07 + X"000001390471", -- len= 313 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000000DE0903", -- len= 222 r=$09 v=$03 + X"0000005A0A08", -- len= 90 r=$0A v=$08 + X"000000AE00F0", -- len= 174 r=$00 v=$F0 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000001740807", -- len= 372 r=$08 v=$07 + X"000000550A07", -- len= 85 r=$0A v=$07 + X"0000022602C5", -- len= 550 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000040907", -- len= 4 r=$09 v=$07 + X"0000004B0A06", -- len= 75 r=$0A v=$06 + X"000002160806", -- len= 534 r=$08 v=$06 + X"000000630A05", -- len= 99 r=$0A v=$05 + X"0000021C0906", -- len= 540 r=$09 v=$06 + X"0000005A0A04", -- len= 90 r=$0A v=$04 + X"000002300738", -- len= 560 r=$07 v=$38 + X"000000AA04BE", -- len= 170 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001450A08", -- len= 325 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"000000B40805", -- len= 180 r=$08 v=$05 + X"0000009C0497", -- len= 156 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"0000016D0A08", -- len= 365 r=$0A v=$08 + X"000000A20905", -- len= 162 r=$09 v=$05 + X"000001D40A07", -- len= 468 r=$0A v=$07 + X"00000137047F", -- len= 311 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000002770A07", -- len= 631 r=$0A v=$07 + X"000000990804", -- len= 153 r=$08 v=$04 + X"0000009D045F", -- len= 157 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000000A30904", -- len= 163 r=$09 v=$04 + X"000001D50A07", -- len= 469 r=$0A v=$07 + X"000001390471", -- len= 313 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000001370A08", -- len= 311 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"0000009A0803", -- len= 154 r=$08 v=$03 + X"000001DC0A06", -- len= 476 r=$0A v=$06 + X"000000A20903", -- len= 162 r=$09 v=$03 + X"000001D60A05", -- len= 470 r=$0A v=$05 + X"000000A2000D", -- len= 162 r=$00 v=$0D + X"000000010101", -- len= 1 r=$01 v=$01 + X"000000030807", -- len= 3 r=$08 v=$07 + X"000001440738", -- len= 324 r=$07 v=$38 + X"000000BC04BE", -- len= 188 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000000C2021B", -- len= 194 r=$02 v=$1B + X"000000010302", -- len= 1 r=$03 v=$02 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000000B10A08", -- len= 177 r=$0A v=$08 + X"000001E10806", -- len= 481 r=$08 v=$06 + X"000000970A07", -- len= 151 r=$0A v=$07 + X"000001500497", -- len= 336 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000000E00906", -- len= 224 r=$09 v=$06 + X"0000008C0A08", -- len= 140 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"00000136047F", -- len= 310 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013C0A08", -- len= 316 r=$0A v=$08 + X"000001E20805", -- len= 482 r=$08 v=$05 + X"000000940A07", -- len= 148 r=$0A v=$07 + X"00000136045F", -- len= 310 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000000B00905", -- len= 176 r=$09 v=$05 + X"0000008C0A08", -- len= 140 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"0000013B0471", -- len= 315 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001380A08", -- len= 312 r=$0A v=$08 + X"000001E10804", -- len= 481 r=$08 v=$04 + X"000000940A07", -- len= 148 r=$0A v=$07 + X"000001EC0904", -- len= 492 r=$09 v=$04 + X"0000008C0A06", -- len= 140 r=$0A v=$06 + X"000002760A05", -- len= 630 r=$0A v=$05 + X"000002780A04", -- len= 632 r=$0A v=$04 + X"000001E10803", -- len= 481 r=$08 v=$03 + X"000000240738", -- len= 36 r=$07 v=$38 + X"000000A104BE", -- len= 161 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001460A08", -- len= 326 r=$0A v=$08 + X"000000A20903", -- len= 162 r=$09 v=$03 + X"000001D40A07", -- len= 468 r=$0A v=$07 + X"000001390497", -- len= 313 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001390A08", -- len= 313 r=$0A v=$08 + X"000000AB02C5", -- len= 171 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000001C80A07", -- len= 456 r=$0A v=$07 + X"0000009A0802", -- len= 154 r=$08 v=$02 + X"0000009C047F", -- len= 156 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000000A30906", -- len= 163 r=$09 v=$06 + X"000001D30A07", -- len= 467 r=$0A v=$07 + X"00000139045F", -- len= 313 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001390A08", -- len= 313 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"0000009A0801", -- len= 154 r=$08 v=$01 + X"0000009F0471", -- len= 159 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001380A08", -- len= 312 r=$0A v=$08 + X"000000A20905", -- len= 162 r=$09 v=$05 + X"000001D60A07", -- len= 470 r=$0A v=$07 + X"000002750A06", -- len= 629 r=$0A v=$06 + X"000002790A05", -- len= 633 r=$0A v=$05 + X"0000009A0800", -- len= 154 r=$08 v=$00 + X"000001DC0A04", -- len= 476 r=$0A v=$04 + X"000000A20904", -- len= 162 r=$09 v=$04 + X"000001D30A03", -- len= 467 r=$0A v=$03 + X"000002780A02", -- len= 632 r=$0A v=$02 + X"000002760A01", -- len= 630 r=$0A v=$01 + X"000002770A00", -- len= 631 r=$0A v=$00 + X"000000A20903", -- len= 162 r=$09 v=$03 + X"000000A90800", -- len= 169 r=$08 v=$00 + X"0000044E0227", -- len= 1102 r=$02 v=$27 + X"000000010303", -- len= 1 r=$03 v=$03 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000004E10906", -- len= 1249 r=$09 v=$06 + X"000007DB0A00", -- len= 2011 r=$0A v=$00 + X"00000060073C", -- len= 96 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00000000073C", -- len= 0 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"000001A00905", -- len= 416 r=$09 v=$05 + X"000003D90738", -- len= 985 r=$07 v=$38 + X"000000A304BE", -- len= 163 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001460A08", -- len= 326 r=$0A v=$08 + X"000002770A07", -- len= 631 r=$0A v=$07 + X"000001360497", -- len= 310 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000000DF0904", -- len= 223 r=$09 v=$04 + X"0000005A0A08", -- len= 90 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"00000136047F", -- len= 310 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013C0A08", -- len= 316 r=$0A v=$08 + X"000002770A07", -- len= 631 r=$0A v=$07 + X"00000136045F", -- len= 310 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000000DF0903", -- len= 223 r=$09 v=$03 + X"0000005A0A08", -- len= 90 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"000001390471", -- len= 313 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000000E702C5", -- len= 231 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000030907", -- len= 3 r=$09 v=$07 + X"0000004E0A08", -- len= 78 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"0000021C0906", -- len= 540 r=$09 v=$06 + X"0000005A0A06", -- len= 90 r=$0A v=$06 + X"000002780A05", -- len= 632 r=$0A v=$05 + X"000002760A04", -- len= 630 r=$0A v=$04 + X"000002770A03", -- len= 631 r=$0A v=$03 + X"000000000738", -- len= 0 r=$07 v=$38 + X"000000AF04BE", -- len= 175 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001450A08", -- len= 325 r=$0A v=$08 + X"000000710905", -- len= 113 r=$09 v=$05 + X"000002050A07", -- len= 517 r=$0A v=$07 + X"000001360497", -- len= 310 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"00000138047F", -- len= 312 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013C0A08", -- len= 316 r=$0A v=$08 + X"000000700904", -- len= 112 r=$09 v=$04 + X"000002050A07", -- len= 517 r=$0A v=$07 + X"00000137045F", -- len= 311 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013C0A08", -- len= 316 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"000001390471", -- len= 313 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000001390A08", -- len= 313 r=$0A v=$08 + X"0000006E0903", -- len= 110 r=$09 v=$03 + X"000002080A07", -- len= 520 r=$0A v=$07 + X"0000007000E3", -- len= 112 r=$00 v=$E3 + X"000000020100", -- len= 2 r=$01 v=$00 + X"000000030807", -- len= 3 r=$08 v=$07 + X"000002350A06", -- len= 565 r=$0A v=$06 + X"00000079021B", -- len= 121 r=$02 v=$1B + X"000000010302", -- len= 1 r=$03 v=$02 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000001F90A05", -- len= 505 r=$0A v=$05 + X"000000680806", -- len= 104 r=$08 v=$06 + X"0000020E0A04", -- len= 526 r=$0A v=$04 + X"000000700906", -- len= 112 r=$09 v=$06 + X"000002080A03", -- len= 520 r=$0A v=$03 + X"000002770A02", -- len= 631 r=$0A v=$02 + X"000002770A01", -- len= 631 r=$0A v=$01 + X"000000660805", -- len= 102 r=$08 v=$05 + X"000002100A00", -- len= 528 r=$0A v=$00 + X"000000700905", -- len= 112 r=$09 v=$05 + X"0000075C0804", -- len= 1884 r=$08 v=$04 + X"000002800904", -- len= 640 r=$09 v=$04 + X"0000075A0803", -- len= 1882 r=$08 v=$03 + X"000000700A00", -- len= 112 r=$0A v=$00 + X"000000A3073C", -- len= 163 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00000000073C", -- len= 0 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"0000016D0903", -- len= 365 r=$09 v=$03 + X"000000C700E3", -- len= 199 r=$00 v=$E3 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000001B50807", -- len= 437 r=$08 v=$07 + X"0000027C02C5", -- len= 636 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000002600806", -- len= 608 r=$08 v=$06 + X"0000027E0906", -- len= 638 r=$09 v=$06 + X"0000075E0805", -- len= 1886 r=$08 v=$05 + X"0000027F0905", -- len= 639 r=$09 v=$05 + X"0000075B0804", -- len= 1883 r=$08 v=$04 + X"0000027F0904", -- len= 639 r=$09 v=$04 + X"0000075D0803", -- len= 1885 r=$08 v=$03 + X"0000027F0903", -- len= 639 r=$09 v=$03 + X"0000027700F0", -- len= 631 r=$00 v=$F0 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000050807", -- len= 5 r=$08 v=$07 + X"0000027B0227", -- len= 635 r=$02 v=$27 + X"000000010303", -- len= 1 r=$03 v=$03 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000002600806", -- len= 608 r=$08 v=$06 + X"0000027F0906", -- len= 639 r=$09 v=$06 + X"000005C30738", -- len= 1475 r=$07 v=$38 + X"0000006704BE", -- len= 103 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001450A08", -- len= 325 r=$0A v=$08 + X"000000340805", -- len= 52 r=$08 v=$05 + X"000002420A07", -- len= 578 r=$0A v=$07 + X"0000003E0905", -- len= 62 r=$09 v=$05 + X"000001120497", -- len= 274 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000016E0A08", -- len= 366 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"00000138047F", -- len= 312 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000001390A08", -- len= 313 r=$0A v=$08 + X"0000001C0804", -- len= 28 r=$08 v=$04 + X"0000025C0A07", -- len= 604 r=$0A v=$07 + X"000000230904", -- len= 35 r=$09 v=$04 + X"00000114045F", -- len= 276 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013A0A08", -- len= 314 r=$0A v=$08 + X"000002770A07", -- len= 631 r=$0A v=$07 + X"000001390471", -- len= 313 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013A0A08", -- len= 314 r=$0A v=$08 + X"0000001A0803", -- len= 26 r=$08 v=$03 + X"0000025C0A07", -- len= 604 r=$0A v=$07 + X"000000250903", -- len= 37 r=$09 v=$03 + X"000002510A06", -- len= 593 r=$0A v=$06 + X"0000000000F0", -- len= 0 r=$00 v=$F0 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000290807", -- len= 41 r=$08 v=$07 + X"0000024D0A05", -- len= 589 r=$0A v=$05 + X"0000002E02C5", -- len= 46 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000040907", -- len= 4 r=$09 v=$07 + X"000002450A04", -- len= 581 r=$0A v=$04 + X"0000001C0806", -- len= 28 r=$08 v=$06 + X"0000025C0A03", -- len= 604 r=$0A v=$03 + X"000000230906", -- len= 35 r=$09 v=$06 + X"000002520A02", -- len= 594 r=$0A v=$02 + X"000002760A01", -- len= 630 r=$0A v=$01 + X"000002790A00", -- len= 633 r=$0A v=$00 + X"0000001C0805", -- len= 28 r=$08 v=$05 + X"0000027D0905", -- len= 637 r=$09 v=$05 + X"0000075C0804", -- len= 1884 r=$08 v=$04 + X"000002800904", -- len= 640 r=$09 v=$04 + X"000005900A00", -- len= 1424 r=$0A v=$00 + X"000000B2073C", -- len= 178 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00000000073C", -- len= 0 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"0000011A0803", -- len= 282 r=$08 v=$03 + X"0000027F0903", -- len= 639 r=$09 v=$03 + X"00000277000D", -- len= 631 r=$00 v=$0D + X"000000010101", -- len= 1 r=$01 v=$01 + X"000000030807", -- len= 3 r=$08 v=$07 + X"0000027C021B", -- len= 636 r=$02 v=$1B + X"000000010302", -- len= 1 r=$03 v=$02 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000002620806", -- len= 610 r=$08 v=$06 + X"0000027F0906", -- len= 639 r=$09 v=$06 + X"0000075B0805", -- len= 1883 r=$08 v=$05 + X"0000027F0905", -- len= 639 r=$09 v=$05 + X"0000075E0804", -- len= 1886 r=$08 v=$04 + X"0000027E0904", -- len= 638 r=$09 v=$04 + X"0000075C0803", -- len= 1884 r=$08 v=$03 + X"0000027E0903", -- len= 638 r=$09 v=$03 + X"000001C4000D", -- len= 452 r=$00 v=$0D + X"000000000101", -- len= 0 r=$01 v=$01 + X"000000B80807", -- len= 184 r=$08 v=$07 + X"0000027B02C5", -- len= 635 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000002620806", -- len= 610 r=$08 v=$06 + X"000002800906", -- len= 640 r=$09 v=$06 + X"0000075B0805", -- len= 1883 r=$08 v=$05 + X"0000027F0905", -- len= 639 r=$09 v=$05 + X"0000075D0804", -- len= 1885 r=$08 v=$04 + X"0000027F0904", -- len= 639 r=$09 v=$04 + X"0000075B0803", -- len= 1883 r=$08 v=$03 + X"0000027F0903", -- len= 639 r=$09 v=$03 + X"0000027900B4", -- len= 633 r=$00 v=$B4 + X"000000010100", -- len= 1 r=$01 v=$00 + X"000000030807", -- len= 3 r=$08 v=$07 + X"0000027A0227", -- len= 634 r=$02 v=$27 + X"000000010303", -- len= 1 r=$03 v=$03 + X"000000040907", -- len= 4 r=$09 v=$07 + X"000002610806", -- len= 609 r=$08 v=$06 + X"0000027F0906", -- len= 639 r=$09 v=$06 + X"0000075B0805", -- len= 1883 r=$08 v=$05 + X"000002810905", -- len= 641 r=$09 v=$05 + X"000005530738", -- len= 1363 r=$07 v=$38 + X"000000A304BE", -- len= 163 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001450A08", -- len= 325 r=$0A v=$08 + X"0000009A0804", -- len= 154 r=$08 v=$04 + X"000001DC0A07", -- len= 476 r=$0A v=$07 + X"000000A20904", -- len= 162 r=$09 v=$04 + X"000000940497", -- len= 148 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"00000137047F", -- len= 311 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013C0A08", -- len= 316 r=$0A v=$08 + X"000000990803", -- len= 153 r=$08 v=$03 + X"000001DC0A07", -- len= 476 r=$0A v=$07 + X"000000A30903", -- len= 163 r=$09 v=$03 + X"00000096045F", -- len= 150 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013A0A08", -- len= 314 r=$0A v=$08 + X"0000002D00B4", -- len= 45 r=$00 v=$B4 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000007A0807", -- len= 122 r=$08 v=$07 + X"000001D00A07", -- len= 464 r=$0A v=$07 + X"000000AB02C5", -- len= 171 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000030907", -- len= 3 r=$09 v=$07 + X"0000008A0471", -- len= 138 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000001370A08", -- len= 311 r=$0A v=$08 + X"0000009A0806", -- len= 154 r=$08 v=$06 + X"000001DE0A07", -- len= 478 r=$0A v=$07 + X"000000A20906", -- len= 162 r=$09 v=$06 + X"000001D40A06", -- len= 468 r=$0A v=$06 + X"000002780A05", -- len= 632 r=$0A v=$05 + X"000002750A04", -- len= 629 r=$0A v=$04 + X"0000009A0805", -- len= 154 r=$08 v=$05 + X"000001DD0A03", -- len= 477 r=$0A v=$03 + X"000000A20905", -- len= 162 r=$09 v=$05 + X"000001D60A02", -- len= 470 r=$0A v=$02 + X"000002750A01", -- len= 629 r=$0A v=$01 + X"000002780A00", -- len= 632 r=$0A v=$00 + X"0000009A0804", -- len= 154 r=$08 v=$04 + X"000002800904", -- len= 640 r=$09 v=$04 + X"0000075C0803", -- len= 1884 r=$08 v=$03 + X"0000027D0903", -- len= 637 r=$09 v=$03 + X"0000027700CA", -- len= 631 r=$00 v=$CA + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000050807", -- len= 5 r=$08 v=$07 + X"0000027C021B", -- len= 636 r=$02 v=$1B + X"000000010302", -- len= 1 r=$03 v=$02 + X"000000030907", -- len= 3 r=$09 v=$07 + X"0000003D0A00", -- len= 61 r=$0A v=$00 + X"0000008B073C", -- len= 139 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00000000073C", -- len= 0 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"000001990806", -- len= 409 r=$08 v=$06 + X"0000027F0906", -- len= 639 r=$09 v=$06 + X"0000075D0805", -- len= 1885 r=$08 v=$05 + X"0000027F0905", -- len= 639 r=$09 v=$05 + X"0000075B0804", -- len= 1883 r=$08 v=$04 + X"0000027F0904", -- len= 639 r=$09 v=$04 + X"0000075D0803", -- len= 1885 r=$08 v=$03 + X"000002800903", -- len= 640 r=$09 v=$03 + X"0000027600E3", -- len= 630 r=$00 v=$E3 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000040807", -- len= 4 r=$08 v=$07 + X"0000027C02C5", -- len= 636 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000030907", -- len= 3 r=$09 v=$07 + X"000002610806", -- len= 609 r=$08 v=$06 + X"0000027E0906", -- len= 638 r=$09 v=$06 + X"0000075D0805", -- len= 1885 r=$08 v=$05 + X"0000027F0905", -- len= 639 r=$09 v=$05 + X"0000075B0804", -- len= 1883 r=$08 v=$04 + X"000002800904", -- len= 640 r=$09 v=$04 + X"0000075D0803", -- len= 1885 r=$08 v=$03 + X"000000290738", -- len= 41 r=$07 v=$38 + X"0000006904BE", -- len= 105 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001450A08", -- len= 325 r=$0A v=$08 + X"000000EE0903", -- len= 238 r=$09 v=$03 + X"0000018A0A07", -- len= 394 r=$0A v=$07 + X"000000EE00F0", -- len= 238 r=$00 v=$F0 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000040807", -- len= 4 r=$08 v=$07 + X"0000008F0497", -- len= 143 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000016F0A08", -- len= 367 r=$0A v=$08 + X"000000F60227", -- len= 246 r=$02 v=$27 + X"000000010303", -- len= 1 r=$03 v=$03 + X"000000040907", -- len= 4 r=$09 v=$07 + X"000001AE0A07", -- len= 430 r=$0A v=$07 + X"000000E60806", -- len= 230 r=$08 v=$06 + X"0000006B047F", -- len= 107 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000016B0A08", -- len= 363 r=$0A v=$08 + X"000000EE0906", -- len= 238 r=$09 v=$06 + X"0000018A0A07", -- len= 394 r=$0A v=$07 + X"00000137045F", -- len= 311 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013A0A08", -- len= 314 r=$0A v=$08 + X"000002780A07", -- len= 632 r=$0A v=$07 + X"000000E50805", -- len= 229 r=$08 v=$05 + X"000000530471", -- len= 83 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000001390A08", -- len= 313 r=$0A v=$08 + X"000000ED0905", -- len= 237 r=$09 v=$05 + X"000001890A07", -- len= 393 r=$0A v=$07 + X"000002760A06", -- len= 630 r=$0A v=$06 + X"000000DD0738", -- len= 221 r=$07 v=$38 + X"000000D004BE", -- len= 208 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"000001430A08", -- len= 323 r=$0A v=$08 + X"000000E70804", -- len= 231 r=$08 v=$04 + X"000001910A07", -- len= 401 r=$0A v=$07 + X"000000EE0904", -- len= 238 r=$09 v=$04 + X"000000480497", -- len= 72 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000002750A07", -- len= 629 r=$0A v=$07 + X"00000137047F", -- len= 311 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013C0A08", -- len= 316 r=$0A v=$08 + X"000000E50803", -- len= 229 r=$08 v=$03 + X"000001910A07", -- len= 401 r=$0A v=$07 + X"000000EE0903", -- len= 238 r=$09 v=$03 + X"00000048045F", -- len= 72 r=$04 v=$5F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"0000013B0A08", -- len= 315 r=$0A v=$08 + X"000000EE000D", -- len= 238 r=$00 v=$0D + X"000000010101", -- len= 1 r=$01 v=$01 + X"000000030807", -- len= 3 r=$08 v=$07 + X"000001B70A07", -- len= 439 r=$0A v=$07 + X"000000F702C5", -- len= 247 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000040907", -- len= 4 r=$09 v=$07 + X"000000580471", -- len= 88 r=$04 v=$71 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000016A0A08", -- len= 362 r=$0A v=$08 + X"000000E50806", -- len= 229 r=$08 v=$06 + X"000001910A07", -- len= 401 r=$0A v=$07 + X"000000EF0906", -- len= 239 r=$09 v=$06 + X"000001890A06", -- len= 393 r=$0A v=$06 + X"000002760A05", -- len= 630 r=$0A v=$05 + X"000002780A04", -- len= 632 r=$0A v=$04 + X"000000E50805", -- len= 229 r=$08 v=$05 + X"000001900A03", -- len= 400 r=$0A v=$03 + X"000000EE0905", -- len= 238 r=$09 v=$05 + X"0000018B0A02", -- len= 395 r=$0A v=$02 + X"000002760A01", -- len= 630 r=$0A v=$01 + X"000002750A00", -- len= 629 r=$0A v=$00 + X"000000E80804", -- len= 232 r=$08 v=$04 + X"0000027D0904", -- len= 637 r=$09 v=$04 + X"0000075C0803", -- len= 1884 r=$08 v=$03 + X"000002800903", -- len= 640 r=$09 v=$03 + X"00000278002E", -- len= 632 r=$00 v=$2E + X"000000000101", -- len= 0 r=$01 v=$01 + X"000000040807", -- len= 4 r=$08 v=$07 + X"000002AD02E0", -- len= 685 r=$02 v=$E0 + X"000000000301", -- len= 0 r=$03 v=$01 + X"000000050907", -- len= 5 r=$09 v=$07 + X"000000000A00", -- len= 0 r=$0A v=$00 + X"0000007C073C", -- len= 124 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"00000000073C", -- len= 0 r=$07 v=$3C + X"000000000A00", -- len= 0 r=$0A v=$00 + X"000001E60806", -- len= 486 r=$08 v=$06 + X"0000027E0906", -- len= 638 r=$09 v=$06 + X"0000075B0805", -- len= 1883 r=$08 v=$05 + X"0000027F0905", -- len= 639 r=$09 v=$05 + X"0000075D0804", -- len= 1885 r=$08 v=$04 + X"000002800904", -- len= 640 r=$09 v=$04 + X"0000075B0803", -- len= 1883 r=$08 v=$03 + X"0000027F0903", -- len= 639 r=$09 v=$03 + X"0000075D0802", -- len= 1885 r=$08 v=$02 + X"0000027F0902", -- len= 639 r=$09 v=$02 + X"0000075B0801", -- len= 1883 r=$08 v=$01 + X"0000027F0901", -- len= 639 r=$09 v=$01 + X"0000075D0800", -- len= 1885 r=$08 v=$00 + X"0000027F0900", -- len= 639 r=$09 v=$00 + X"00000BFB0800", -- len= 3067 r=$08 v=$00 + X"000000000900", -- len= 0 r=$09 v=$00 + X"00000B940738", -- len= 2964 r=$07 v=$38 + X"000000A304BE", -- len= 163 r=$04 v=$BE + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000001430A08", -- len= 323 r=$0A v=$08 + X"000002770A07", -- len= 631 r=$0A v=$07 + X"000001390497", -- len= 313 r=$04 v=$97 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000050A09", -- len= 5 r=$0A v=$09 + X"0000013A0A08", -- len= 314 r=$0A v=$08 + X"000002760A07", -- len= 630 r=$0A v=$07 + X"00000136047F", -- len= 310 r=$04 v=$7F + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000060A09", -- len= 6 r=$0A v=$09 + X"000000B4073F", -- len= 180 r=$07 v=$3F + X"00000009073C", -- len= 9 r=$07 v=$3C + X"000000030A00", -- len= 3 r=$0A v=$00 + X"00000014073D", -- len= 20 r=$07 v=$3D + X"000000000800", -- len= 0 r=$08 v=$00 + X"00000013073F", -- len= 19 r=$07 v=$3F + X"000000000900", -- len= 0 r=$09 v=$00 + X"000002B0080D", -- len= 688 r=$08 v=$0D + X"000000030050", -- len= 3 r=$00 v=$50 + X"000000010100", -- len= 1 r=$01 v=$00 + X"00000004073E", -- len= 4 r=$07 v=$3E + X"00000031005A", -- len= 49 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004A0050", -- len= 74 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"00000033005A", -- len= 51 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004D0050", -- len= 77 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"00000031005A", -- len= 49 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004C0050", -- len= 76 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"00000031005A", -- len= 49 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004D0050", -- len= 77 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"00000033005A", -- len= 51 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000060800", -- len= 6 r=$08 v=$00 + X"000000CD073C", -- len= 205 r=$07 v=$3C + X"000000A50287", -- len= 165 r=$02 v=$87 + X"000000010300", -- len= 1 r=$03 v=$00 + X"000000030906", -- len= 3 r=$09 v=$06 + X"000002190738", -- len= 537 r=$07 v=$38 + X"0000005804A0", -- len= 88 r=$04 v=$A0 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000040A06", -- len= 4 r=$0A v=$06 + X"000001CE0905", -- len= 462 r=$09 v=$05 + X"000002320A05", -- len= 562 r=$0A v=$05 + X"000001B3080D", -- len= 435 r=$08 v=$0D + X"000000370050", -- len= 55 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004A005A", -- len= 74 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000330050", -- len= 51 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004C005A", -- len= 76 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000330050", -- len= 51 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004C005A", -- len= 76 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000330050", -- len= 51 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004B005A", -- len= 75 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000330050", -- len= 51 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000060800", -- len= 6 r=$08 v=$00 + X"000001C70904", -- len= 455 r=$09 v=$04 + X"000002320A04", -- len= 562 r=$0A v=$04 + X"00000266080D", -- len= 614 r=$08 v=$0D + X"000000000050", -- len= 0 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000000738", -- len= 0 r=$07 v=$38 + X"0000000E0800", -- len= 14 r=$08 v=$00 + X"00000040005A", -- len= 64 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000330050", -- len= 51 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004C005A", -- len= 76 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000330050", -- len= 51 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004A005A", -- len= 74 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000320050", -- len= 50 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004C005A", -- len= 76 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000330050", -- len= 51 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004C005A", -- len= 76 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000000800", -- len= 0 r=$08 v=$00 + X"000001030903", -- len= 259 r=$09 v=$03 + X"000002320A03", -- len= 562 r=$0A v=$03 + X"000005A7080D", -- len= 1447 r=$08 v=$0D + X"0000000F0902", -- len= 15 r=$09 v=$02 + X"000000260050", -- len= 38 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004C005A", -- len= 76 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000320050", -- len= 50 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004C005A", -- len= 76 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000330050", -- len= 51 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004C005A", -- len= 76 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000320050", -- len= 50 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"0000004A005A", -- len= 74 r=$00 v=$5A + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000330050", -- len= 51 r=$00 v=$50 + X"000000000100", -- len= 0 r=$01 v=$00 + X"000000060800", -- len= 6 r=$08 v=$00 + X"000000170A02", -- len= 23 r=$0A v=$02 + X"000001B50900", -- len= 437 r=$09 v=$00 + X"000002350A00", -- len= 565 r=$0A v=$00 + X"000001B80901", -- len= 440 r=$09 v=$01 + X"0000002F0800", -- len= 47 r=$08 v=$00 + X"0000007B0739", -- len= 123 r=$07 v=$39 + X"000000000800", -- len= 0 r=$08 v=$00 + X"000000000739", -- len= 0 r=$07 v=$39 + X"000000000800", -- len= 0 r=$08 v=$00 + X"000001840A01", -- len= 388 r=$0A v=$01 + X"000005AF0900", -- len= 1455 r=$09 v=$00 + X"000002340A00", -- len= 564 r=$0A v=$00 + X"000001C60278", -- len= 454 r=$02 v=$78 + X"000000000300", -- len= 0 r=$03 v=$00 + X"000000040906", -- len= 4 r=$09 v=$06 + X"0000023004AA", -- len= 560 r=$04 v=$AA + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000040A06", -- len= 4 r=$0A v=$06 + X"000001B10905", -- len= 433 r=$09 v=$05 + X"000002340A05", -- len= 564 r=$0A v=$05 + X"000005AE0904", -- len= 1454 r=$09 v=$04 + X"000002340A04", -- len= 564 r=$0A v=$04 + X"000001C80287", -- len= 456 r=$02 v=$87 + X"000000000300", -- len= 0 r=$03 v=$00 + X"000000040906", -- len= 4 r=$09 v=$06 + X"0000022F04A0", -- len= 559 r=$04 v=$A0 + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000040A06", -- len= 4 r=$0A v=$06 + X"000001B10905", -- len= 433 r=$09 v=$05 + X"000002310A05", -- len= 561 r=$0A v=$05 + X"000005B10904", -- len= 1457 r=$09 v=$04 + X"000002330A04", -- len= 563 r=$0A v=$04 + X"000005AF0903", -- len= 1455 r=$09 v=$03 + X"000002340A03", -- len= 564 r=$0A v=$03 + X"000005AF0902", -- len= 1455 r=$09 v=$02 + X"000002330A02", -- len= 563 r=$0A v=$02 + X"000005AF0901", -- len= 1455 r=$09 v=$01 + X"000002340A01", -- len= 564 r=$0A v=$01 + X"000005AE0900", -- len= 1454 r=$09 v=$00 + X"000002340A00", -- len= 564 r=$0A v=$00 + X"0000118C02C5", -- len= 4492 r=$02 v=$C5 + X"000000010301", -- len= 1 r=$03 v=$01 + X"000000030906", -- len= 3 r=$09 v=$06 + X"0000022F04CA", -- len= 559 r=$04 v=$CA + X"000000000500", -- len= 0 r=$05 v=$00 + X"000000040A06", -- len= 4 r=$0A v=$06 + X"000001B10905", -- len= 433 r=$09 v=$05 + X"000002340A05", -- len= 564 r=$0A v=$05 + X"000005AE0904", -- len= 1454 r=$09 v=$04 + X"000002340A04", -- len= 564 r=$0A v=$04 + X"000005AE0903", -- len= 1454 r=$09 v=$03 + X"000002340A03", -- len= 564 r=$0A v=$03 + X"000005AF0902", -- len= 1455 r=$09 v=$02 + X"000002330A02" -- len= 563 r=$0A v=$02 +); +signal raddr : std_logic_vector(10 downto 0); +begin + process (clk) + begin + if (clk'event and clk = '1') then + if (en = '1') then + raddr <= addr; + end if; + end if; + end process; + data <= ROM(conv_integer(raddr)); +end syn; diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/cpu68.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/cpu68.vhd new file mode 100644 index 00000000..03bdfc63 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/cpu68.vhd @@ -0,0 +1,3962 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E CPU68 C O R E +-- +-- www.OpenCores.Org - December 2002 +-- This core adheres to the GNU public license +-- +-- File name : cpu68.vhd +-- +-- Purpose : Implements a 6800 compatible CPU core with some +-- additional instructions found in the 6801 +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- +-- Author : John E. Kent +-- +--===========================================================================---- +-- +-- Revision History: +-- +-- Date: Revision Author +-- 22 Sep 2002 0.1 John Kent +-- +-- 30 Oct 2002 0.2 John Kent +-- made NMI edge triggered +-- +-- 30 Oct 2002 0.3 John Kent +-- more corrections to NMI +-- added wai_wait_state to prevent stack overflow on wai. +-- +-- 1 Nov 2002 0.4 John Kent +-- removed WAI states and integrated WAI with the interrupt service routine +-- replace Data out (do) and Data in (di) register with a single Memory Data (md) reg. +-- Added Multiply instruction states. +-- run ALU and CC out of CPU module for timing measurements. +-- +-- 3 Nov 2002 0.5 John Kent +-- Memory Data Register was not loaded on Store instructions +-- SEV and CLV were not defined in the ALU +-- Overflow Flag on NEG was incorrect +-- +-- 16th Feb 2003 0.6 John Kent +-- Rearranged the execution cycle for dual operand instructions +-- so that occurs during the following fetch cycle. +-- This allows the reduction of one clock cycle from dual operand +-- instruction. Note that this also necessitated re-arranging the +-- program counter so that it is no longer incremented in the ALU. +-- The effective address has also been re-arranged to include a +-- separate added. The STD (store accd) now sets the condition codes. +-- +-- 28th Jun 2003 0.7 John Kent +-- Added Hold and Halt signals. Hold is used to steal cycles from the +-- CPU or add wait states. Halt puts the CPU in the inactive state +-- and is only honoured in the fetch cycle. Both signals are active high. +-- +-- 9th Jan 2004 0.8 John Kent +-- Clear instruction did an alu_ld8 rather than an alu_clr, so +-- the carry bit was not cleared correctly. +-- This error was picked up by Michael Hassenfratz. +-- + +library ieee; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity cpu68 is + port ( + clk: in std_logic; + rst: in std_logic; + rw: out std_logic; + vma: out std_logic; + address: out std_logic_vector(15 downto 0); + data_in: in std_logic_vector(7 downto 0); + data_out: out std_logic_vector(7 downto 0); + hold: in std_logic; + halt: in std_logic; + irq: in std_logic; + nmi: in std_logic; + test_alu: out std_logic_vector(15 downto 0); + test_cc: out std_logic_vector(7 downto 0) + ); +end; + +architecture CPU_ARCH of cpu68 is + + constant SBIT : integer := 7; + constant XBIT : integer := 6; + constant HBIT : integer := 5; + constant IBIT : integer := 4; + constant NBIT : integer := 3; + constant ZBIT : integer := 2; + constant VBIT : integer := 1; + constant CBIT : integer := 0; + + type state_type is (reset_state, fetch_state, decode_state, + extended_state, indexed_state, read8_state, read16_state, immediate16_state, + write8_state, write16_state, + execute_state, halt_state, error_state, + mul_state, mulea_state, muld_state, + mul0_state, mul1_state, mul2_state, mul3_state, + mul4_state, mul5_state, mul6_state, mul7_state, + jmp_state, jsr_state, jsr1_state, + branch_state, bsr_state, bsr1_state, + rts_hi_state, rts_lo_state, + int_pcl_state, int_pch_state, + int_ixl_state, int_ixh_state, + int_cc_state, int_acca_state, int_accb_state, + int_wai_state, int_mask_state, + rti_state, rti_cc_state, rti_acca_state, rti_accb_state, + rti_ixl_state, rti_ixh_state, + rti_pcl_state, rti_pch_state, + pula_state, psha_state, pulb_state, pshb_state, + pulx_lo_state, pulx_hi_state, pshx_lo_state, pshx_hi_state, + vect_lo_state, vect_hi_state ); + type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad ); + type dout_type is (md_lo_dout, md_hi_dout, acca_dout, accb_dout, ix_lo_dout, ix_hi_dout, cc_dout, pc_lo_dout, pc_hi_dout ); + type op_type is (reset_op, fetch_op, latch_op ); + type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca ); + type accb_type is (reset_accb, load_accb, pull_accb, latch_accb ); + type cc_type is (reset_cc, load_cc, pull_cc, latch_cc ); + type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix ); + type sp_type is (reset_sp, latch_sp, load_sp ); + type pc_type is (reset_pc, latch_pc, load_ea_pc, add_ea_pc, pull_lo_pc, pull_hi_pc, inc_pc ); + type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md ); + type ea_type is (reset_ea, latch_ea, add_ix_ea, load_accb_ea, inc_ea, fetch_first_ea, fetch_next_ea ); + type iv_type is (reset_iv, latch_iv, swi_iv, nmi_iv, irq_iv ); + type nmi_type is (reset_nmi, set_nmi, latch_nmi ); + type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, sp_left ); + type right_type is (md_right, zero_right, plus_one_right, accb_right ); + type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc, + alu_and, alu_ora, alu_eor, + alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com, + alu_inx, alu_dex, alu_cpx, + alu_lsr16, alu_lsl16, + alu_ror8, alu_rol8, + alu_asr8, alu_asl8, alu_lsr8, + alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv, alu_tpa, alu_tap, + alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa ); + + signal op_code: std_logic_vector(7 downto 0); + signal acca: std_logic_vector(7 downto 0); + signal accb: std_logic_vector(7 downto 0); + signal cc: std_logic_vector(7 downto 0); + signal cc_out: std_logic_vector(7 downto 0); + signal xreg: std_logic_vector(15 downto 0); + signal sp: std_logic_vector(15 downto 0); + signal ea: std_logic_vector(15 downto 0); + signal pc: std_logic_vector(15 downto 0); + signal md: std_logic_vector(15 downto 0); + signal left: std_logic_vector(15 downto 0); + signal right: std_logic_vector(15 downto 0); + signal out_alu: std_logic_vector(15 downto 0); + signal iv: std_logic_vector(1 downto 0); + signal nmi_req: std_logic; + signal nmi_ack: std_logic; + + signal state: state_type; + signal next_state: state_type; + signal pc_ctrl: pc_type; + signal ea_ctrl: ea_type; + signal op_ctrl: op_type; + signal md_ctrl: md_type; + signal acca_ctrl: acca_type; + signal accb_ctrl: accb_type; + signal ix_ctrl: ix_type; + signal cc_ctrl: cc_type; + signal sp_ctrl: sp_type; + signal iv_ctrl: iv_type; + signal left_ctrl: left_type; + signal right_ctrl: right_type; + signal alu_ctrl: alu_type; + signal addr_ctrl: addr_type; + signal dout_ctrl: dout_type; + signal nmi_ctrl: nmi_type; + + +begin + +---------------------------------- +-- +-- Address bus multiplexer +-- +---------------------------------- + +addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv ) +begin + case addr_ctrl is + when idle_ad => + address <= "1111111111111111"; + vma <= '0'; + rw <= '1'; + when fetch_ad => + address <= pc; + vma <= '1'; + rw <= '1'; + when read_ad => + address <= ea; + vma <= '1'; + rw <= '1'; + when write_ad => + address <= ea; + vma <= '1'; + rw <= '0'; + when push_ad => + address <= sp; + vma <= '1'; + rw <= '0'; + when pull_ad => + address <= sp; + vma <= '1'; + rw <= '1'; + when int_hi_ad => + address <= "1111111111111" & iv & "0"; + vma <= '1'; + rw <= '1'; + when int_lo_ad => + address <= "1111111111111" & iv & "1"; + vma <= '1'; + rw <= '1'; + when others => + address <= "1111111111111111"; + vma <= '0'; + rw <= '1'; + end case; +end process; + +-------------------------------- +-- +-- Data Bus output +-- +-------------------------------- +dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, pc, cc ) +begin + case dout_ctrl is + when md_hi_dout => -- alu output + data_out <= md(15 downto 8); + when md_lo_dout => + data_out <= md(7 downto 0); + when acca_dout => -- accumulator a + data_out <= acca; + when accb_dout => -- accumulator b + data_out <= accb; + when ix_lo_dout => -- index reg + data_out <= xreg(7 downto 0); + when ix_hi_dout => -- index reg + data_out <= xreg(15 downto 8); + when cc_dout => -- condition codes + data_out <= cc; + when pc_lo_dout => -- low order pc + data_out <= pc(7 downto 0); + when pc_hi_dout => -- high order pc + data_out <= pc(15 downto 8); + when others => + data_out <= "00000000"; + end case; +end process; + + +---------------------------------- +-- +-- Program Counter Control +-- +---------------------------------- + +pc_mux: process( clk, pc_ctrl, pc, out_alu, data_in, ea, hold ) +variable tempof : std_logic_vector(15 downto 0); +variable temppc : std_logic_vector(15 downto 0); +begin + case pc_ctrl is + when add_ea_pc => + if ea(7) = '0' then + tempof := "00000000" & ea(7 downto 0); + else + tempof := "11111111" & ea(7 downto 0); + end if; + when inc_pc => + tempof := "0000000000000001"; + when others => + tempof := "0000000000000000"; + end case; + + case pc_ctrl is + when reset_pc => + temppc := "1111111111111110"; + when load_ea_pc => + temppc := ea; + when pull_lo_pc => + temppc(7 downto 0) := data_in; + temppc(15 downto 8) := pc(15 downto 8); + when pull_hi_pc => + temppc(7 downto 0) := pc(7 downto 0); + temppc(15 downto 8) := data_in; + when others => + temppc := pc; + end case; + + if clk'event and clk = '0' then + if hold = '1' then + pc <= pc; + else + pc <= temppc + tempof; + end if; + end if; +end process; + +---------------------------------- +-- +-- Effective Address Control +-- +---------------------------------- + +ea_mux: process( clk, ea_ctrl, ea, out_alu, data_in, accb, xreg, hold ) +variable tempind : std_logic_vector(15 downto 0); +variable tempea : std_logic_vector(15 downto 0); +begin + case ea_ctrl is + when add_ix_ea => + tempind := "00000000" & ea(7 downto 0); + when inc_ea => + tempind := "0000000000000001"; + when others => + tempind := "0000000000000000"; + end case; + + case ea_ctrl is + when reset_ea => + tempea := "0000000000000000"; + when load_accb_ea => + tempea := "00000000" & accb(7 downto 0); + when add_ix_ea => + tempea := xreg; + when fetch_first_ea => + tempea(7 downto 0) := data_in; + tempea(15 downto 8) := "00000000"; + when fetch_next_ea => + tempea(7 downto 0) := data_in; + tempea(15 downto 8) := ea(7 downto 0); + when others => + tempea := ea; + end case; + + if clk'event and clk = '0' then + if hold = '1' then + ea <= ea; + else + ea <= tempea + tempind; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator A +-- +-------------------------------- +acca_mux : process( clk, acca_ctrl, out_alu, acca, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + acca <= acca; + else + case acca_ctrl is + when reset_acca => + acca <= "00000000"; + when load_acca => + acca <= out_alu(7 downto 0); + when load_hi_acca => + acca <= out_alu(15 downto 8); + when pull_acca => + acca <= data_in; + when others => +-- when latch_acca => + acca <= acca; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Accumulator B +-- +-------------------------------- +accb_mux : process( clk, accb_ctrl, out_alu, accb, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + accb <= accb; + else + case accb_ctrl is + when reset_accb => + accb <= "00000000"; + when load_accb => + accb <= out_alu(7 downto 0); + when pull_accb => + accb <= data_in; + when others => +-- when latch_accb => + accb <= accb; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- X Index register +-- +-------------------------------- +ix_mux : process( clk, ix_ctrl, out_alu, xreg, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + xreg <= xreg; + else + case ix_ctrl is + when reset_ix => + xreg <= "0000000000000000"; + when load_ix => + xreg <= out_alu(15 downto 0); + when pull_hi_ix => + xreg(15 downto 8) <= data_in; + when pull_lo_ix => + xreg(7 downto 0) <= data_in; + when others => +-- when latch_ix => + xreg <= xreg; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- stack pointer +-- +-------------------------------- +sp_mux : process( clk, sp_ctrl, out_alu, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + sp <= sp; + else + case sp_ctrl is + when reset_sp => + sp <= "0000000000000000"; + when load_sp => + sp <= out_alu(15 downto 0); + when others => +-- when latch_sp => + sp <= sp; + end case; + end if; + end if; +end process; + +-------------------------------- +-- +-- Memory Data +-- +-------------------------------- +md_mux : process( clk, md_ctrl, out_alu, data_in, md, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + md <= md; + else + case md_ctrl is + when reset_md => + md <= "0000000000000000"; + when load_md => + md <= out_alu(15 downto 0); + when fetch_first_md => + md(15 downto 8) <= "00000000"; + md(7 downto 0) <= data_in; + when fetch_next_md => + md(15 downto 8) <= md(7 downto 0); + md(7 downto 0) <= data_in; + when shiftl_md => + md(15 downto 1) <= md(14 downto 0); + md(0) <= '0'; + when others => +-- when latch_md => + md <= md; + end case; + end if; + end if; +end process; + + +---------------------------------- +-- +-- Condition Codes +-- +---------------------------------- + +cc_mux: process( clk, cc_ctrl, cc_out, cc, data_in, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + cc <= cc; + else + case cc_ctrl is + when reset_cc => + cc <= "11000000"; + when load_cc => + cc <= cc_out; + when pull_cc => + cc <= data_in; + when others => +-- when latch_cc => + cc <= cc; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- interrupt vector +-- +---------------------------------- + +iv_mux: process( clk, iv_ctrl, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + iv <= iv; + else + case iv_ctrl is + when reset_iv => + iv <= "11"; + when nmi_iv => + iv <= "10"; + when swi_iv => + iv <= "01"; + when irq_iv => + iv <= "00"; + when others => + iv <= iv; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- op code fetch +-- +---------------------------------- + +op_fetch: process( clk, data_in, op_ctrl, op_code, hold ) +begin + if clk'event and clk = '0' then + if hold = '1' then + op_code <= op_code; + else + case op_ctrl is + when reset_op => + op_code <= "00000001"; -- nop + when fetch_op => + op_code <= data_in; + when others => +-- when latch_op => + op_code <= op_code; + end case; + end if; + end if; +end process; + +---------------------------------- +-- +-- Left Mux +-- +---------------------------------- + +left_mux: process( left_ctrl, acca, accb, xreg, sp, pc, ea, md ) +begin + case left_ctrl is + when acca_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= acca; + when accb_left => + left(15 downto 8) <= "00000000"; + left(7 downto 0) <= accb; + when accd_left => + left(15 downto 8) <= acca; + left(7 downto 0) <= accb; + when ix_left => + left <= xreg; + when sp_left => + left <= sp; + when others => +-- when md_left => + left <= md; + end case; +end process; +---------------------------------- +-- +-- Right Mux +-- +---------------------------------- + +right_mux: process( right_ctrl, data_in, md, accb, ea ) +begin + case right_ctrl is + when zero_right => + right <= "0000000000000000"; + when plus_one_right => + right <= "0000000000000001"; + when accb_right => + right <= "00000000" & accb; + when others => +-- when md_right => + right <= md; + end case; +end process; + +---------------------------------- +-- +-- Arithmetic Logic Unit +-- +---------------------------------- + +mux_alu: process( alu_ctrl, cc, left, right, out_alu, cc_out ) +variable valid_lo, valid_hi : boolean; +variable carry_in : std_logic; +variable daa_reg : std_logic_vector(7 downto 0); +begin + + case alu_ctrl is + when alu_adc | alu_sbc | + alu_rol8 | alu_ror8 => + carry_in := cc(CBIT); + when others => + carry_in := '0'; + end case; + + valid_lo := left(3 downto 0) <= 9; + valid_hi := left(7 downto 4) <= 9; + + if (cc(CBIT) = '0') then + if( cc(HBIT) = '1' ) then + if valid_hi then + daa_reg := "00000110"; + else + daa_reg := "01100110"; + end if; + else + if valid_lo then + if valid_hi then + daa_reg := "00000000"; + else + daa_reg := "01100000"; + end if; + else + if( left(7 downto 4) <= 8 ) then + daa_reg := "00000110"; + else + daa_reg := "01100110"; + end if; + end if; + end if; + else + if ( cc(HBIT) = '1' )then + daa_reg := "01100110"; + else + if valid_lo then + daa_reg := "01100000"; + else + daa_reg := "01100110"; + end if; + end if; + end if; + + case alu_ctrl is + when alu_add8 | alu_inc | + alu_add16 | alu_inx | + alu_adc => + out_alu <= left + right + ("000000000000000" & carry_in); + when alu_sub8 | alu_dec | + alu_sub16 | alu_dex | + alu_sbc | alu_cpx => + out_alu <= left - right - ("000000000000000" & carry_in); + when alu_and => + out_alu <= left and right; -- and/bit + when alu_ora => + out_alu <= left or right; -- or + when alu_eor => + out_alu <= left xor right; -- eor/xor + when alu_lsl16 | alu_asl8 | alu_rol8 => + out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16 + when alu_lsr16 | alu_lsr8 => + out_alu <= carry_in & left(15 downto 1); -- lsr + when alu_ror8 => + out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror + when alu_asr8 => + out_alu <= "00000000" & left(7) & left(7 downto 1); -- asr + when alu_neg => + out_alu <= right - left; -- neg (right=0) + when alu_com => + out_alu <= not left; + when alu_clr | alu_ld8 | alu_ld16 => + out_alu <= right; -- clr, ld + when alu_st8 | alu_st16 => + out_alu <= left; + when alu_daa => + out_alu <= left + ("00000000" & daa_reg); + when alu_tpa => + out_alu <= "00000000" & cc; + when others => + out_alu <= left; -- nop + end case; + + -- + -- carry bit + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(CBIT) <= (left(7) and right(7)) or + (left(7) and not out_alu(7)) or + (right(7) and not out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(CBIT) <= ((not left(7)) and right(7)) or + ((not left(7)) and out_alu(7)) or + (right(7) and out_alu(7)); + when alu_add16 => + cc_out(CBIT) <= (left(15) and right(15)) or + (left(15) and not out_alu(15)) or + (right(15) and not out_alu(15)); + when alu_sub16 => + cc_out(CBIT) <= ((not left(15)) and right(15)) or + ((not left(15)) and out_alu(15)) or + (right(15) and out_alu(15)); + when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 => + cc_out(CBIT) <= left(0); + when alu_rol8 | alu_asl8 => + cc_out(CBIT) <= left(7); + when alu_lsl16 => + cc_out(CBIT) <= left(15); + when alu_com => + cc_out(CBIT) <= '1'; + when alu_neg | alu_clr => + cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0); + when alu_daa => + if ( daa_reg(7 downto 4) = "0110" ) then + cc_out(CBIT) <= '1'; + else + cc_out(CBIT) <= '0'; + end if; + when alu_sec => + cc_out(CBIT) <= '1'; + when alu_clc => + cc_out(CBIT) <= '0'; + when alu_tap => + cc_out(CBIT) <= left(CBIT); + when others => -- carry is not affected by cpx + cc_out(CBIT) <= cc(CBIT); + end case; + -- + -- Zero flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_inc | alu_dec | + alu_neg | alu_com | alu_clr | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_ld8 | alu_st8 => + cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_add16 | alu_sub16 | + alu_lsl16 | alu_lsr16 | + alu_inx | alu_dex | + alu_ld16 | alu_st16 | alu_cpx => + cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or + out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or + out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or + out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) ); + when alu_tap => + cc_out(ZBIT) <= left(ZBIT); + when others => + cc_out(ZBIT) <= cc(ZBIT); + end case; + + -- + -- negative flag + -- + case alu_ctrl is + when alu_add8 | alu_sub8 | + alu_adc | alu_sbc | + alu_and | alu_ora | alu_eor | + alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 | + alu_inc | alu_dec | alu_neg | alu_com | alu_clr | + alu_ld8 | alu_st8 => + cc_out(NBIT) <= out_alu(7); + when alu_add16 | alu_sub16 | + alu_lsl16 | alu_lsr16 | + alu_ld16 | alu_st16 | alu_cpx => + cc_out(NBIT) <= out_alu(15); + when alu_tap => + cc_out(NBIT) <= left(NBIT); + when others => + cc_out(NBIT) <= cc(NBIT); + end case; + + -- + -- Interrupt mask flag + -- + case alu_ctrl is + when alu_sei => + cc_out(IBIT) <= '1'; -- set interrupt mask + when alu_cli => + cc_out(IBIT) <= '0'; -- clear interrupt mask + when alu_tap => + cc_out(IBIT) <= left(IBIT); + when others => + cc_out(IBIT) <= cc(IBIT); -- interrupt mask + end case; + + -- + -- Half Carry flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(HBIT) <= (left(3) and right(3)) or + (right(3) and not out_alu(3)) or + (left(3) and not out_alu(3)); + when alu_tap => + cc_out(HBIT) <= left(HBIT); + when others => + cc_out(HBIT) <= cc(HBIT); + end case; + + -- + -- Overflow flag + -- + case alu_ctrl is + when alu_add8 | alu_adc => + cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or + ((not left(7)) and (not right(7)) and out_alu(7)); + when alu_sub8 | alu_sbc => + cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or + ((not left(7)) and right(7) and out_alu(7)); + when alu_add16 => + cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or + ((not left(15)) and (not right(15)) and out_alu(15)); + when alu_sub16 | alu_cpx => + cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or + ((not left(15)) and right(15) and out_alu(15)); + when alu_inc => + cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and + left(3) and left(2) and left(1) and left(0)); + when alu_dec | alu_neg => + cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and + (not left(3)) and (not left(2)) and (not left(1)) and (not left(0))); + when alu_asr8 => + cc_out(VBIT) <= left(0) xor left(7); + when alu_lsr8 | alu_lsr16 => + cc_out(VBIT) <= left(0); + when alu_ror8 => + cc_out(VBIT) <= left(0) xor cc(CBIT); + when alu_lsl16 => + cc_out(VBIT) <= left(15) xor left(14); + when alu_rol8 | alu_asl8 => + cc_out(VBIT) <= left(7) xor left(6); + when alu_tap => + cc_out(VBIT) <= left(VBIT); + when alu_and | alu_ora | alu_eor | alu_com | + alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | + alu_clv => + cc_out(VBIT) <= '0'; + when alu_sev => + cc_out(VBIT) <= '1'; + when others => + cc_out(VBIT) <= cc(VBIT); + end case; + + case alu_ctrl is + when alu_tap => + cc_out(XBIT) <= cc(XBIT) and left(XBIT); + cc_out(SBIT) <= left(SBIT); + when others => + cc_out(XBIT) <= cc(XBIT) and left(XBIT); + cc_out(SBIT) <= cc(SBIT); + end case; + + test_alu <= out_alu; + test_cc <= cc_out; +end process; + +------------------------------------ +-- +-- Detect Edge of NMI interrupt +-- +------------------------------------ + +nmi_handler : process( clk, rst, nmi, nmi_ack ) +begin + if clk'event and clk='0' then + if hold = '1' then + nmi_req <= nmi_req; + else + if rst='1' then + nmi_req <= '0'; + else + if (nmi='1') and (nmi_ack='0') then + nmi_req <= '1'; + else + if (nmi='0') and (nmi_ack='1') then + nmi_req <= '0'; + else + nmi_req <= nmi_req; + end if; + end if; + end if; + end if; + end if; +end process; + +------------------------------------ +-- +-- Nmi mux +-- +------------------------------------ + +nmi_mux: process( clk, nmi_ctrl, nmi_ack, hold ) +begin + if clk'event and clk='0' then + if hold = '1' then + nmi_ack <= nmi_ack; + else + case nmi_ctrl is + when set_nmi => + nmi_ack <= '1'; + when reset_nmi => + nmi_ack <= '0'; + when others => +-- when latch_nmi => + nmi_ack <= nmi_ack; + end case; + end if; + end if; +end process; + +------------------------------------ +-- +-- state sequencer +-- +------------------------------------ +process( state, op_code, cc, ea, irq, nmi_req, nmi_ack, hold, halt ) + begin + case state is + when reset_state => -- released from reset + -- reset the registers + op_ctrl <= reset_op; + acca_ctrl <= reset_acca; + accb_ctrl <= reset_accb; + ix_ctrl <= reset_ix; + sp_ctrl <= reset_sp; + pc_ctrl <= reset_pc; + ea_ctrl <= reset_ea; + md_ctrl <= reset_md; + iv_ctrl <= reset_iv; + nmi_ctrl <= reset_nmi; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= reset_cc; + -- idle the bus + dout_ctrl <= md_lo_dout; + addr_ctrl <= idle_ad; + next_state <= vect_hi_state; + + -- + -- Jump via interrupt vector + -- iv holds interrupt type + -- fetch PC hi from vector location + -- + when vect_hi_state => + -- default the registers + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + ea_ctrl <= latch_ea; + iv_ctrl <= latch_iv; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- fetch pc low interrupt vector + pc_ctrl <= pull_hi_pc; + addr_ctrl <= int_hi_ad; + dout_ctrl <= pc_hi_dout; + next_state <= vect_lo_state; + -- + -- jump via interrupt vector + -- iv holds vector type + -- fetch PC lo from vector location + -- + when vect_lo_state => + -- default the registers + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + ea_ctrl <= latch_ea; + iv_ctrl <= latch_iv; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- fetch the vector low byte + pc_ctrl <= pull_lo_pc; + addr_ctrl <= int_lo_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + -- + -- Here to fetch an instruction + -- PC points to opcode + -- Should service interrupt requests at this point + -- either from the timer + -- or from the external input. + -- + when fetch_state => + case op_code(7 downto 4) is + when "0000" | + "0001" | + "0010" | -- branch conditional + "0011" | + "0100" | -- acca single op + "0101" | -- accb single op + "0110" | -- indexed single op + "0111" => -- extended single op + -- idle ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + + when "1000" | -- acca immediate + "1001" | -- acca direct + "1010" | -- acca indexed + "1011" => -- acca extended + case op_code(3 downto 0) is + when "0000" => -- suba + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0001" => -- cmpa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0010" => -- sbca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0011" => -- subd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0100" => -- anda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0101" => -- bita + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0110" => -- ldaa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1000" => -- eora + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1001" => -- adca + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1010" => -- oraa + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1011" => -- adda + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1100" => -- cpx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_cpx; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1101" => -- bsr / jsr + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1110" => -- lds + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when others => + left_ctrl <= acca_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + when "1100" | -- accb immediate + "1101" | -- accb direct + "1110" | -- accb indexed + "1111" => -- accb extended + case op_code(3 downto 0) is + when "0000" => -- subb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0001" => -- cmpb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0010" => -- sbcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_sbc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0011" => -- addd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0100" => -- andb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0101" => -- bitb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_and; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0110" => -- ldab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "0111" => -- stab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1000" => -- eorb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_eor; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1001" => -- adcb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_adc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1010" => -- orab + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ora; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1011" => -- addb + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1100" => -- ldd + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1101" => -- std + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when "1110" => -- ldx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_ld16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + when "1111" => -- stx + left_ctrl <= ix_left; + right_ctrl <= md_right; + alu_ctrl <= alu_st16; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + when others => + left_ctrl <= accb_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + when others => + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + end case; + md_ctrl <= latch_md; + -- fetch the op code + op_ctrl <= fetch_op; + ea_ctrl <= reset_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + iv_ctrl <= latch_iv; + if halt = '1' then + pc_ctrl <= latch_pc; + nmi_ctrl <= latch_nmi; + next_state <= halt_state; + -- service non maskable interrupts + elsif (nmi_req = '1') and (nmi_ack = '0') then + pc_ctrl <= latch_pc; + nmi_ctrl <= set_nmi; + next_state <= int_pcl_state; + -- service maskable interrupts + else + -- + -- nmi request is not cleared until nmi input goes low + -- + if(nmi_req = '0') and (nmi_ack='1') then + nmi_ctrl <= reset_nmi; + else + nmi_ctrl <= latch_nmi; + end if; + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + pc_ctrl <= latch_pc; + next_state <= int_pcl_state; + else + -- Advance the PC to fetch next instruction byte + pc_ctrl <= inc_pc; + next_state <= decode_state; + end if; + end if; + -- + -- Here to decode instruction + -- and fetch next byte of intruction + -- whether it be necessary or not + -- + when decode_state => + -- fetch first byte of address or immediate data + ea_ctrl <= fetch_first_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + iv_ctrl <= latch_iv; + case op_code(7 downto 4) is + when "0000" => + md_ctrl <= fetch_first_md; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + case op_code(3 downto 0) is + when "0001" => -- nop + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "0100" => -- lsrd + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + when "0101" => -- lsld + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_lsl16; + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + ix_ctrl <= latch_ix; + when "0110" => -- tap + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_tap; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "0111" => -- tpa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_tpa; + cc_ctrl <= latch_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1000" => -- inx + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inx; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + when "1001" => -- dex + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dex; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= load_ix; + when "1010" => -- clv + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_clv; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1011" => -- sev + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sev; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1100" => -- clc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_clc; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1101" => -- sec + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sec; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1110" => -- cli + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_cli; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when "1111" => -- sei + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sei; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + end case; + next_state <= fetch_state; + -- acca / accb inherent instructions + when "0001" => + md_ctrl <= fetch_first_md; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + left_ctrl <= acca_left; + right_ctrl <= accb_right; + case op_code(3 downto 0) is + when "0000" => -- sba + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "0001" => -- cba + alu_ctrl <= alu_sub8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + when "0110" => -- tab + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= load_accb; + when "0111" => -- tba + alu_ctrl <= alu_ld8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "1001" => -- daa + alu_ctrl <= alu_daa; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when "1011" => -- aba + alu_ctrl <= alu_add8; + cc_ctrl <= load_cc; + acca_ctrl <= load_acca; + accb_ctrl <= latch_accb; + when others => + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end case; + next_state <= fetch_state; + when "0010" => -- branch conditional + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0000" => -- bra + next_state <= branch_state; + when "0001" => -- brn + next_state <= fetch_state; + when "0010" => -- bhi + if (cc(CBIT) or cc(ZBIT)) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0011" => -- bls + if (cc(CBIT) or cc(ZBIT)) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0100" => -- bcc/bhs + if cc(CBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0101" => -- bcs/blo + if cc(CBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0110" => -- bne + if cc(ZBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "0111" => -- beq + if cc(ZBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1000" => -- bvc + if cc(VBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1001" => -- bvs + if cc(VBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1010" => -- bpl + if cc(NBIT) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1011" => -- bmi + if cc(NBIT) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1100" => -- bge + if (cc(NBIT) xor cc(VBIT)) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1101" => -- blt + if (cc(NBIT) xor cc(VBIT)) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1110" => -- bgt + if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when "1111" => -- ble + if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then + next_state <= branch_state; + else + next_state <= fetch_state; + end if; + when others => + next_state <= fetch_state; + end case; + -- + -- Single byte stack operators + -- Do not advance PC + -- + when "0011" => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + case op_code(3 downto 0) is + when "0000" => -- tsx + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + when "0001" => -- ins + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0010" => -- pula + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pula_state; + when "0011" => -- pulb + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pulb_state; + when "0100" => -- des + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0101" => -- txs + left_ctrl <= ix_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= fetch_state; + when "0110" => -- psha + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= psha_state; + when "0111" => -- pshb + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= pshb_state; + when "1000" => -- pulx + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= pulx_hi_state; + when "1001" => -- rts + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= rts_hi_state; + when "1010" => -- abx + left_ctrl <= ix_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= load_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + when "1011" => -- rti + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= load_sp; + next_state <= rti_cc_state; + when "1100" => -- pshx + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= pshx_lo_state; + when "1101" => -- mul + left_ctrl <= acca_left; + right_ctrl <= accb_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= mul_state; + when "1110" => -- wai + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= int_pcl_state; + when "1111" => -- swi + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= int_pcl_state; + when others => + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + next_state <= fetch_state; + end case; + -- + -- Accumulator A Single operand + -- source = Acc A dest = Acc A + -- Do not advance PC + -- + when "0100" => -- acca single op + md_ctrl <= fetch_first_md; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= acca_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + acca_ctrl <= latch_acca; + cc_ctrl <= load_cc; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + acca_ctrl <= load_acca; + cc_ctrl <= load_cc; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + acca_ctrl <= latch_acca; + cc_ctrl <= latch_cc; + end case; + next_state <= fetch_state; + -- + -- single operand acc b + -- Do not advance PC + -- + when "0101" => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + pc_ctrl <= latch_pc; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + left_ctrl <= accb_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + accb_ctrl <= latch_accb; + cc_ctrl <= load_cc; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + accb_ctrl <= load_accb; + cc_ctrl <= load_cc; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + accb_ctrl <= latch_accb; + cc_ctrl <= latch_cc; + end case; + next_state <= fetch_state; + -- + -- Single operand indexed + -- Two byte instruction so advance PC + -- EA should hold index offset + -- + when "0110" => -- indexed single op + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + -- + -- Single operand extended addressing + -- three byte instruction so advance the PC + -- Low order EA holds high order address + -- + when "0111" => -- extended single op + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when "1000" => -- acca immediate + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0011" | -- subdd # + "1100" | -- cpx # + "1110" => -- lds # + next_state <= immediate16_state; + when "1101" => -- bsr + next_state <= bsr_state; + when others => + next_state <= fetch_state; + end case; + + when "1001" => -- acca direct + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0111" => -- staa direct + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1111" => -- sts direct + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1101" => -- jsr direct + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= jsr_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= read8_state; + end case; + + when "1010" => -- acca indexed + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + + when "1011" => -- acca extended + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when "1100" => -- accb immediate + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0011" | -- addd # + "1100" | -- ldd # + "1110" => -- ldx # + next_state <= immediate16_state; + when others => + next_state <= fetch_state; + end case; + + when "1101" => -- accb direct + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + pc_ctrl <= inc_pc; + case op_code(3 downto 0) is + when "0111" => -- stab direct + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std direct + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx direct + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + next_state <= read8_state; + end case; + + when "1110" => -- accb indexed + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= indexed_state; + + when "1111" => -- accb extended + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- increment the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + next_state <= extended_state; + + when others => + md_ctrl <= fetch_first_md; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + -- idle the pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= latch_pc; + next_state <= fetch_state; + end case; + + when immediate16_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + op_ctrl <= latch_op; + iv_ctrl <= latch_iv; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment pc + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= inc_pc; + -- fetch next immediate byte + md_ctrl <= fetch_next_md; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + -- + -- ea holds 8 bit index offet + -- calculate the effective memory address + -- using the alu + -- + when indexed_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- calculate effective address from index reg + -- index offest is not sign extended + ea_ctrl <= add_ix_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + -- work out next state + case op_code(7 downto 4) is + when "0110" => -- single op indexed + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + case op_code(3 downto 0) is + when "1011" => -- undefined + next_state <= fetch_state; + when "1110" => -- jmp + next_state <= jmp_state; + when others => + next_state <= read8_state; + end case; + when "1010" => -- acca indexed + case op_code(3 downto 0) is + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- jsr + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= jsr_state; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when "1110" => -- accb indexed + case op_code(3 downto 0) is + when "0111" => -- stab direct + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std direct + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx direct + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when others => + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + next_state <= fetch_state; + end case; + -- + -- ea holds the low byte of the absolute address + -- Move ea low byte into ea high byte + -- load new ea low byte to for absolute 16 bit address + -- advance the program counter + -- + when extended_state => -- fetch ea low byte + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- increment pc + pc_ctrl <= inc_pc; + -- fetch next effective address bytes + ea_ctrl <= fetch_next_ea; + addr_ctrl <= fetch_ad; + dout_ctrl <= md_lo_dout; + -- work out the next state + case op_code(7 downto 4) is + when "0111" => -- single op extended + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + case op_code(3 downto 0) is + when "1011" => -- undefined + next_state <= fetch_state; + when "1110" => -- jmp + next_state <= jmp_state; + when others => + next_state <= read8_state; + end case; + when "1011" => -- acca extended + case op_code(3 downto 0) is + when "0111" => -- staa + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- jsr + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= jsr_state; + when "1111" => -- sts + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when "1111" => -- accb extended + case op_code(3 downto 0) is + when "0111" => -- stab + left_ctrl <= accb_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- std + left_ctrl <= accd_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when "1111" => -- stx + left_ctrl <= ix_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= read8_state; + end case; + when others => + md_ctrl <= latch_md; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + next_state <= fetch_state; + end case; + -- + -- here if ea holds low byte (direct page) + -- can enter here from extended addressing + -- read memory location + -- note that reads may be 8 or 16 bits + -- + when read8_state => -- read data + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + case op_code(7 downto 4) is + when "0110" | "0111" => -- single operand + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= execute_state; + + when "1001" | "1010" | "1011" => -- acca + case op_code(3 downto 0) is + when "0011" | -- subd + "1110" | -- lds + "1100" => -- cpx + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + -- increment the effective address in case of 16 bit load + ea_ctrl <= inc_ea; + next_state <= read16_state; +-- when "0111" => -- staa +-- left_ctrl <= acca_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st8; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write8_state; +-- when "1101" => -- jsr +-- left_ctrl <= acca_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_nop; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= latch_md; +-- ea_ctrl <= latch_ea; +-- next_state <= jsr_state; +-- when "1111" => -- sts +-- left_ctrl <= sp_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= fetch_state; + end case; + + when "1101" | "1110" | "1111" => -- accb + case op_code(3 downto 0) is + when "0011" | -- addd + "1100" | -- ldd + "1110" => -- ldx + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + -- increment the effective address in case of 16 bit load + ea_ctrl <= inc_ea; + next_state <= read16_state; +-- when "0111" => -- stab +-- left_ctrl <= accb_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st8; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write8_state; +-- when "1101" => -- std +-- left_ctrl <= accd_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; +-- when "1111" => -- stx +-- left_ctrl <= ix_left; +-- right_ctrl <= zero_right; +-- alu_ctrl <= alu_st16; +-- cc_ctrl <= latch_cc; +-- md_ctrl <= load_md; +-- ea_ctrl <= latch_ea; +-- next_state <= write16_state; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= execute_state; + end case; + when others => + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= fetch_first_md; + ea_ctrl <= latch_ea; + next_state <= fetch_state; + end case; + + when read16_state => -- read second data byte from ea + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle the effective address + ea_ctrl <= latch_ea; + -- read the low byte of the 16 bit data + md_ctrl <= fetch_next_md; + addr_ctrl <= read_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + -- + -- 16 bit Write state + -- write high byte of ALU output. + -- EA hold address of memory to write to + -- Advance the effective address in ALU + -- + when write16_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + -- increment the effective address + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + ea_ctrl <= inc_ea; + -- write the ALU hi byte to ea + addr_ctrl <= write_ad; + dout_ctrl <= md_hi_dout; + next_state <= write8_state; + -- + -- 8 bit write + -- Write low 8 bits of ALU output + -- + when write8_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- write ALU low byte output + addr_ctrl <= write_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when jmp_state => + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- load PC with effective address + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= load_ea_pc; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when jsr_state => -- JSR + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= jsr1_state; + + when jsr1_state => -- JSR + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= jmp_state; + + when branch_state => -- Bcc + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- calculate signed branch + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + pc_ctrl <= add_ea_pc; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when bsr_state => -- BSR + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= bsr1_state; + + when bsr1_state => -- BSR + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= branch_state; + + when rts_hi_state => -- RTS + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment the sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_hi_dout; + next_state <= rts_lo_state; + + when rts_lo_state => -- RTS1 + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle the ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- read pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + when mul_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- move acca to md + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_st16; + cc_ctrl <= latch_cc; + md_ctrl <= load_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mulea_state; + + when mulea_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + md_ctrl <= latch_md; + -- idle ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- move accb to ea + ea_ctrl <= load_accb_ea; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= muld_state; + + when muld_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + md_ctrl <= latch_md; + -- clear accd + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_ld8; + cc_ctrl <= latch_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul0_state; + + when mul0_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 0 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(0) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul1_state; + + when mul1_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 1 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(1) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul2_state; + + when mul2_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 2 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(2) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul3_state; + + when mul3_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 3 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(3) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul4_state; + + when mul4_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 4 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(4) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul5_state; + + when mul5_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 5 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(5) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul6_state; + + when mul6_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 6 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(6) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= mul7_state; + + when mul7_state => + -- default + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- if bit 7 of ea set, add accd to md + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_add16; + if ea(7) = '1' then + cc_ctrl <= load_cc; + acca_ctrl <= load_hi_acca; + accb_ctrl <= load_accb; + else + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + end if; + md_ctrl <= shiftl_md; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + + when execute_state => -- execute single operand instruction + -- default + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + case op_code(7 downto 4) is + when "0110" | -- indexed single op + "0111" => -- extended single op + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + iv_ctrl <= latch_iv; + ea_ctrl <= latch_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + left_ctrl <= md_left; + case op_code(3 downto 0) is + when "0000" => -- neg + right_ctrl <= zero_right; + alu_ctrl <= alu_neg; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0011" => -- com + right_ctrl <= zero_right; + alu_ctrl <= alu_com; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0100" => -- lsr + right_ctrl <= zero_right; + alu_ctrl <= alu_lsr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0110" => -- ror + right_ctrl <= zero_right; + alu_ctrl <= alu_ror8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "0111" => -- asr + right_ctrl <= zero_right; + alu_ctrl <= alu_asr8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1000" => -- asl + right_ctrl <= zero_right; + alu_ctrl <= alu_asl8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1001" => -- rol + right_ctrl <= zero_right; + alu_ctrl <= alu_rol8; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1010" => -- dec + right_ctrl <= plus_one_right; + alu_ctrl <= alu_dec; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1011" => -- undefined + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1100" => -- inc + right_ctrl <= plus_one_right; + alu_ctrl <= alu_inc; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when "1101" => -- tst + right_ctrl <= zero_right; + alu_ctrl <= alu_st8; + cc_ctrl <= load_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1110" => -- jmp + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + when "1111" => -- clr + right_ctrl <= zero_right; + alu_ctrl <= alu_clr; + cc_ctrl <= load_cc; + md_ctrl <= load_md; + next_state <= write8_state; + when others => + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + md_ctrl <= latch_md; + next_state <= fetch_state; + end case; + + when others => + left_ctrl <= accd_left; + right_ctrl <= md_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + ea_ctrl <= latch_ea; + -- idle the bus + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= fetch_state; + end case; + + when psha_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write acca + addr_ctrl <= push_ad; + dout_ctrl <= acca_dout; + next_state <= fetch_state; + + when pula_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pull_ad; + dout_ctrl <= acca_dout; + next_state <= fetch_state; + + when pshb_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= push_ad; + dout_ctrl <= accb_dout; + next_state <= fetch_state; + + when pulb_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pull_ad; + dout_ctrl <= accb_dout; + next_state <= fetch_state; + + when pshx_lo_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= push_ad; + dout_ctrl <= ix_lo_dout; + next_state <= pshx_hi_state; + + when pshx_hi_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= push_ad; + dout_ctrl <= ix_hi_dout; + next_state <= fetch_state; + + when pulx_hi_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- pull ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_hi_dout; + next_state <= pulx_lo_state; + + when pulx_lo_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_lo_dout; + next_state <= fetch_state; + + -- + -- return from interrupt + -- enter here from bogus interrupts + -- + when rti_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- idle address bus + cc_ctrl <= latch_cc; + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + next_state <= rti_cc_state; + + when rti_cc_state => + -- default registers + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + sp_ctrl <= load_sp; + -- read cc + cc_ctrl <= pull_cc; + addr_ctrl <= pull_ad; + dout_ctrl <= cc_dout; + next_state <= rti_accb_state; + + when rti_accb_state => + -- default registers + acca_ctrl <= latch_acca; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read accb + accb_ctrl <= pull_accb; + addr_ctrl <= pull_ad; + dout_ctrl <= accb_dout; + next_state <= rti_acca_state; + + when rti_acca_state => + -- default registers + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read acca + acca_ctrl <= pull_acca; + addr_ctrl <= pull_ad; + dout_ctrl <= acca_dout; + next_state <= rti_ixh_state; + + when rti_ixh_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read ix hi + ix_ctrl <= pull_hi_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_hi_dout; + next_state <= rti_ixl_state; + + when rti_ixl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- read ix low + ix_ctrl <= pull_lo_ix; + addr_ctrl <= pull_ad; + dout_ctrl <= ix_lo_dout; + next_state <= rti_pch_state; + + when rti_pch_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- increment sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_add16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- pull pc hi + pc_ctrl <= pull_hi_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_hi_dout; + next_state <= rti_pcl_state; + + when rti_pcl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- idle sp + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + sp_ctrl <= latch_sp; + -- pull pc low + pc_ctrl <= pull_lo_pc; + addr_ctrl <= pull_ad; + dout_ctrl <= pc_lo_dout; + next_state <= fetch_state; + + -- + -- here on interrupt + -- iv register hold interrupt type + -- + when int_pcl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc low + addr_ctrl <= push_ad; + dout_ctrl <= pc_lo_dout; + next_state <= int_pch_state; + + when int_pch_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write pc hi + addr_ctrl <= push_ad; + dout_ctrl <= pc_hi_dout; + next_state <= int_ixl_state; + + when int_ixl_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix low + addr_ctrl <= push_ad; + dout_ctrl <= ix_lo_dout; + next_state <= int_ixh_state; + + when int_ixh_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write ix hi + addr_ctrl <= push_ad; + dout_ctrl <= ix_hi_dout; + next_state <= int_acca_state; + + when int_acca_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write acca + addr_ctrl <= push_ad; + dout_ctrl <= acca_dout; + next_state <= int_accb_state; + + + when int_accb_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write accb + addr_ctrl <= push_ad; + dout_ctrl <= accb_dout; + next_state <= int_cc_state; + + when int_cc_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- decrement sp + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_sub16; + cc_ctrl <= latch_cc; + sp_ctrl <= load_sp; + -- write cc + addr_ctrl <= push_ad; + dout_ctrl <= cc_dout; + nmi_ctrl <= latch_nmi; + -- + -- nmi is edge triggered + -- nmi_req is cleared when nmi goes low. + -- + if nmi_req = '1' then + iv_ctrl <= nmi_iv; + next_state <= vect_hi_state; + else + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + iv_ctrl <= irq_iv; + next_state <= int_mask_state; + else + case op_code is + when "00111110" => -- WAI (wait for interrupt) + iv_ctrl <= latch_iv; + next_state <= int_wai_state; + when "00111111" => -- SWI (Software interrupt) + iv_ctrl <= swi_iv; + next_state <= vect_hi_state; + when others => -- bogus interrupt (return) + iv_ctrl <= latch_iv; + next_state <= rti_state; + end case; + end if; + end if; + + when int_wai_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + op_ctrl <= latch_op; + ea_ctrl <= latch_ea; + -- enable interrupts + left_ctrl <= sp_left; + right_ctrl <= plus_one_right; + alu_ctrl <= alu_cli; + cc_ctrl <= load_cc; + sp_ctrl <= latch_sp; + -- idle bus + addr_ctrl <= idle_ad; + dout_ctrl <= cc_dout; + if (nmi_req = '1') and (nmi_ack='0') then + iv_ctrl <= nmi_iv; + nmi_ctrl <= set_nmi; + next_state <= vect_hi_state; + else + -- + -- nmi request is not cleared until nmi input goes low + -- + if (nmi_req = '0') and (nmi_ack='1') then + nmi_ctrl <= reset_nmi; + else + nmi_ctrl <= latch_nmi; + end if; + -- + -- IRQ is level sensitive + -- + if (irq = '1') and (cc(IBIT) = '0') then + iv_ctrl <= irq_iv; + next_state <= int_mask_state; + else + iv_ctrl <= latch_iv; + next_state <= int_wai_state; + end if; + end if; + + when int_mask_state => + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- Mask IRQ + left_ctrl <= sp_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_sei; + cc_ctrl <= load_cc; + sp_ctrl <= latch_sp; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= vect_hi_state; + + when halt_state => -- halt CPU. + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- do nothing in ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + if halt = '1' then + next_state <= halt_state; + else + next_state <= fetch_state; + end if; + + when others => -- error state halt on undefine states + -- default + acca_ctrl <= latch_acca; + accb_ctrl <= latch_accb; + ix_ctrl <= latch_ix; + sp_ctrl <= latch_sp; + pc_ctrl <= latch_pc; + md_ctrl <= latch_md; + iv_ctrl <= latch_iv; + op_ctrl <= latch_op; + nmi_ctrl <= latch_nmi; + ea_ctrl <= latch_ea; + -- do nothing in ALU + left_ctrl <= acca_left; + right_ctrl <= zero_right; + alu_ctrl <= alu_nop; + cc_ctrl <= latch_cc; + -- idle bus cycle + addr_ctrl <= idle_ad; + dout_ctrl <= md_lo_dout; + next_state <= error_state; + end case; +end process; + +-------------------------------- +-- +-- state machine +-- +-------------------------------- + +change_state: process( clk, rst, state, hold ) +begin + if clk'event and clk = '0' then + if rst = '1' then + state <= reset_state; + elsif hold = '1' then + state <= state; + else + state <= next_state; + end if; + end if; +end process; + -- output + +end CPU_ARCH; diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/dac.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/dac.vhd new file mode 100644 index 00000000..c133f074 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/dac.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- $Id: dac.vhd,v 1.1 2006/05/10 20:57:06 arnim Exp $ +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity dac is + + generic ( + msbi_g : integer := 7 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(msbi_g downto 0); + dac_o : out std_logic + ); + +end dac; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of dac is + + signal DACout_q : std_logic; + signal DeltaAdder_s, + SigmaAdder_s, + SigmaLatch_q, + DeltaB_s : unsigned(msbi_g+2 downto 0); + +begin + + DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & + SigmaLatch_q(msbi_g+2); + DeltaB_s(msbi_g downto 0) <= (others => '0'); + + DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; + + SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; + + seq: process (clk_i, res_n_i) + begin + if res_n_i = '0' then + SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); + DACout_q <= '0'; + + elsif clk_i'event and clk_i = '1' then + SigmaLatch_q <= SigmaAdder_s; + DACout_q <= SigmaLatch_q(msbi_g+2); + end if; + end process seq; + + dac_o <= DACout_q; + +end rtl; diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/greybox_tmp/cbx_args.txt b/Soundboards_MiST/AS-2518-51_snd-master/rtl/greybox_tmp/cbx_args.txt new file mode 100644 index 00000000..eaf4ac94 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/greybox_tmp/cbx_args.txt @@ -0,0 +1,16 @@ +ADDRESS_ACLR_A=NONE +CLOCK_ENABLE_INPUT_A=BYPASS +CLOCK_ENABLE_OUTPUT_A=BYPASS +INIT_FILE=./ROM/NitroGroundshaker.hex +INTENDED_DEVICE_FAMILY="Cyclone III" +NUMWORDS_A=2048 +OPERATION_MODE=ROM +OUTDATA_ACLR_A=NONE +OUTDATA_REG_A=UNREGISTERED +WIDTHAD_A=11 +WIDTH_A=8 +WIDTH_BYTEENA_A=1 +DEVICE_FAMILY="Cyclone III" +address_a +clock0 +q_a diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/m6810.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/m6810.vhd new file mode 100644 index 00000000..0c114032 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/m6810.vhd @@ -0,0 +1,65 @@ +----------------------------------------------------------------------- +-- +-- Copyright 2009-2011 ShareBrained Technology, Inc. +-- +-- This file is part of robotron-fpga. +-- +-- robotron-fpga is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- robotron-fpga is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. +-- +-- You should have received a copy of the GNU General +-- Public License along with robotron-fpga. If not, see +-- . +-- +----------------------------------------------------------------------- + +library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + use IEEE.NUMERIC_STD.ALL; + +entity m6810 is + Port ( clk : in std_logic; + rst : in std_logic; + address : in std_logic_vector (6 downto 0); + cs : in std_logic; + rw : in std_logic; + data_in : in std_logic_vector (7 downto 0); + data_out : out std_logic_vector (7 downto 0)); +end m6810; + +architecture rtl of m6810 is + subtype word_t is std_logic_vector(7 downto 0); + type memory_t is array(127 downto 0) of word_t; + + signal ram : memory_t; + signal address_reg : std_logic_vector(6 downto 0); + + signal we : std_logic; +begin + + process(clk) + begin + if( rising_edge(clk) ) then + if( we = '1' and cs = '1' ) then + ram(to_integer(unsigned(address))) <= data_in; + end if; + + address_reg <= address; + end if; + end process; + + we <= not rw; + + data_out <= ram(to_integer(unsigned(address))); + +end architecture rtl; + diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/minibd_top.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/minibd_top.vhd new file mode 100644 index 00000000..71efaf81 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/minibd_top.vhd @@ -0,0 +1,144 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity minibd_top is +port( + CLOCK_27 : in std_logic; + SPI_SCK : in std_logic; + SPI_DO : out std_logic; + SPI_DI : in std_logic; + SPI_SS2 : in std_logic; + SPI_SS3 : in std_logic; + CONF_DATA0 : in std_logic; + LED : out std_logic; + AUDIO_L : out std_logic; + AUDIO_R : out std_logic + ); +end minibd_top; + +architecture rtl of minibd_top is +-- Sound board signals +signal reset_l : std_logic; +signal ps2_clk : std_logic; +signal ps2_dat : std_logic; +signal cpu_clk : std_logic; +signal snd_ctl : std_logic_vector(7 downto 0); +signal audio : std_logic_vector(10 downto 0); + +-- PS/2 interface signals +signal scanCode : std_logic_vector(9 downto 0); +signal send : std_logic; +signal Command : std_logic_vector(7 downto 0); +signal PS2Busy : std_logic; +signal PS2Error : std_logic; +signal dataByte : std_logic_vector(7 downto 0); +signal dataReady : std_logic; +signal buttons : std_logic_vector(1 downto 0); + +component mist_io generic(STRLEN : integer := 0 ); port +( + clk_sys : in std_logic; + SPI_SCK : in std_logic; + CONF_DATA0 : in std_logic; + SPI_SS2 : in std_logic; + SPI_DI : in std_logic; + SPI_DO : out std_logic; + buttons : out std_logic_vector(1 downto 0); + ps2_kbd_clk : out std_logic; + ps2_kbd_data : out std_logic + ); +end component mist_io; + +begin + +reset_l <= not buttons(1); +LED <= '1'; + +io: mist_io +port map( + clk_sys => CLOCK_27, + SPI_SCK => SPI_SCK, + CONF_DATA0 => CONF_DATA0, + SPI_SS2 => SPI_SS2, + SPI_DO => SPI_DO, + SPI_DI => SPI_DI, + buttons => buttons, + ps2_kbd_clk => ps2_clk, + ps2_kbd_data => ps2_dat + ); + +Core: entity work.AS_2518_51 +port map( + cpu_clk => cpu_clk, + reset_l => reset_l, + addr_i => snd_ctl(5 downto 0), + snd_int_i => not scancode(8), + test_sw_l => '1', + audio => audio + ); + +PLL: entity work.williams_snd_pll +port map( + areset => not reset_l, + inclk0 => CLOCK_27, + c0 => cpu_clk + ); + +keyboard: entity work.PS2Controller +port map( + Reset => not reset_l, + Clock => CLOCK_27, + PS2Clock => ps2_clk, + PS2Data => ps2_dat, + Send => send, + Command => command, + PS2Busy => ps2Busy, + PS2Error => ps2Error, + DataReady => dataReady, + DataByte => dataByte + ); + +decoder: entity work.KeyboardMapper +port map( + Clock => CLOCK_27, + Reset => not reset_l, + PS2Busy => ps2Busy, + PS2Error => ps2Error, + DataReady => dataReady, + DataByte => dataByte, + Send => send, + Command => command, + CodeReady => open, + ScanCode => scanCode + ); + +inputreg: process +begin + wait until rising_edge(CLOCK_27); + if scanCode(8) = '0' then + snd_ctl(5 downto 0) <= not scanCode(5 downto 0); + else + snd_ctl(5 downto 0) <= "111111"; + end if; +end process; + +snd_ctl(7 downto 6) <= "11"; + +Audio_DACl: entity work.dac +port map( + clk_i => CLOCK_27, + res_n_i => reset_l, + dac_i => audio(10 downto 3), + dac_o => AUDIO_L + ); + +Audio_DACr: entity work.dac +port map( + clk_i => CLOCK_27, + res_n_i => reset_l, + dac_i => audio(10 downto 3), + dac_o => AUDIO_R + ); + +end rtl; diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/mist_io.sv b/Soundboards_MiST/AS-2518-51_snd-master/rtl/mist_io.sv new file mode 100644 index 00000000..dcc7ecde --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/mist_io.sv @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [23:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [23:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [23:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/pia6821.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/pia6821.vhd new file mode 100644 index 00000000..6a403356 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/pia6821.vhd @@ -0,0 +1,534 @@ +--===========================================================================-- +-- +-- S Y N T H E Z I A B L E I/O Port C O R E +-- +-- www.OpenCores.Org - May 2004 +-- This core adheres to the GNU public license +-- +-- File name : pia6821.vhd +-- +-- Purpose : Implements 2 x 8 bit parallel I/O ports +-- with programmable data direction registers +-- +-- Dependencies : ieee.Std_Logic_1164 +-- ieee.std_logic_unsigned +-- +-- Author : John E. Kent +-- +--===========================================================================---- +-- +-- Revision History: +-- +-- Date: Revision Author +-- 1 May 2004 0.0 John Kent +-- Initial version developed from ioport.vhd +-- +--===========================================================================---- +-- +-- Memory Map +-- +-- IO + $00 - Port A Data & Direction register +-- IO + $01 - Port A Control register +-- IO + $02 - Port B Data & Direction Direction Register +-- IO + $03 - Port B Control Register +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity pia6821 is + port ( + clk : in std_logic; + rst : in std_logic; + cs : in std_logic; + rw : in std_logic; + addr : in std_logic_vector(1 downto 0); + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0); + irqa : out std_logic; + irqb : out std_logic; + pa_i : in std_logic_vector(7 downto 0); + pa_o : out std_logic_vector(7 downto 0); + ca1 : in std_logic; + ca2_i : in std_logic; + ca2_o : out std_logic; + pb_i : in std_logic_vector(7 downto 0); + pb_o : out std_logic_vector(7 downto 0); + cb1 : in std_logic; + cb2_i : in std_logic; + cb2_o : out std_logic + ); +end; + +architecture pia_arch of pia6821 is + +signal porta_ddr : std_logic_vector(7 downto 0); +signal porta_data : std_logic_vector(7 downto 0); +signal porta_ctrl : std_logic_vector(5 downto 0); +signal porta_read : std_logic; + +signal portb_ddr : std_logic_vector(7 downto 0); +signal portb_data : std_logic_vector(7 downto 0); +signal portb_ctrl : std_logic_vector(5 downto 0); +signal portb_read : std_logic; +signal portb_write : std_logic; + +signal ca1_del : std_logic; +signal ca1_rise : std_logic; +signal ca1_fall : std_logic; +signal ca1_edge : std_logic; +signal irqa1 : std_logic; + +signal ca2_del : std_logic; +signal ca2_rise : std_logic; +signal ca2_fall : std_logic; +signal ca2_edge : std_logic; +signal irqa2 : std_logic; +signal ca2_out : std_logic; + +signal cb1_del : std_logic; +signal cb1_rise : std_logic; +signal cb1_fall : std_logic; +signal cb1_edge : std_logic; +signal irqb1 : std_logic; + +signal cb2_del : std_logic; +signal cb2_rise : std_logic; +signal cb2_fall : std_logic; +signal cb2_edge : std_logic; +signal irqb2 : std_logic; +signal cb2_out : std_logic; + +begin + +-------------------------------- +-- +-- read I/O port +-- +-------------------------------- + +pia_read : process( addr, cs, + irqa1, irqa2, irqb1, irqb2, + porta_ddr, portb_ddr, + porta_data, portb_data, + porta_ctrl, portb_ctrl, + pa_i, pb_i ) +variable count : integer; +begin + case addr is + when "00" => + for count in 0 to 7 loop + if porta_ctrl(2) = '0' then + data_out(count) <= porta_ddr(count); + porta_read <= '0'; + else + if porta_ddr(count) = '1' then + data_out(count) <= porta_data(count); + else + data_out(count) <= pa_i(count); + end if; + porta_read <= cs; + end if; + end loop; + portb_read <= '0'; + + when "01" => + data_out <= irqa1 & irqa2 & porta_ctrl; + porta_read <= '0'; + portb_read <= '0'; + + when "10" => + for count in 0 to 7 loop + if portb_ctrl(2) = '0' then + data_out(count) <= portb_ddr(count); + portb_read <= '0'; + else + if portb_ddr(count) = '1' then + data_out(count) <= portb_data(count); + else + data_out(count) <= pb_i(count); + end if; + portb_read <= cs; + end if; + end loop; + porta_read <= '0'; + + when "11" => + data_out <= irqb1 & irqb2 & portb_ctrl; + porta_read <= '0'; + portb_read <= '0'; + + when others => + data_out <= "00000000"; + porta_read <= '0'; + portb_read <= '0'; + + end case; +end process; + +--------------------------------- +-- +-- Write I/O ports +-- +--------------------------------- + +pia_write : process( clk, rst, addr, cs, rw, data_in, + porta_ctrl, portb_ctrl, + porta_data, portb_data, + porta_ctrl, portb_ctrl, + porta_ddr, portb_ddr ) +begin + if rst = '1' then + porta_ddr <= "00000000"; + porta_data <= "00000000"; + porta_ctrl <= "000000"; + portb_ddr <= "00000000"; + portb_data <= "00000000"; + portb_ctrl <= "000000"; + portb_write <= '0'; + elsif clk'event and clk = '1' then + if cs = '1' and rw = '0' then + case addr is + when "00" => + if porta_ctrl(2) = '0' then + porta_ddr <= data_in; + porta_data <= porta_data; + else + porta_ddr <= porta_ddr; + porta_data <= data_in; + end if; + porta_ctrl <= porta_ctrl; + portb_ddr <= portb_ddr; + portb_data <= portb_data; + portb_ctrl <= portb_ctrl; + portb_write <= '0'; + when "01" => + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= data_in(5 downto 0); + portb_ddr <= portb_ddr; + portb_data <= portb_data; + portb_ctrl <= portb_ctrl; + portb_write <= '0'; + when "10" => + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= porta_ctrl; + if portb_ctrl(2) = '0' then + portb_ddr <= data_in; + portb_data <= portb_data; + portb_write <= '0'; + else + portb_ddr <= portb_ddr; + portb_data <= data_in; + portb_write <= '1'; + end if; + portb_ctrl <= portb_ctrl; + when "11" => + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= porta_ctrl; + portb_ddr <= portb_ddr; + portb_data <= portb_data; + portb_ctrl <= data_in(5 downto 0); + portb_write <= '0'; + when others => + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= porta_ctrl; + portb_ddr <= portb_ddr; + portb_data <= portb_data; + portb_ctrl <= portb_ctrl; + portb_write <= '0'; + end case; + else + porta_ddr <= porta_ddr; + porta_data <= porta_data; + porta_ctrl <= porta_ctrl; + portb_data <= portb_data; + portb_ddr <= portb_ddr; + portb_ctrl <= portb_ctrl; + portb_write <= '0'; + end if; + end if; +end process; + +--------------------------------- +-- +-- direction control port a +-- +--------------------------------- +porta_direction : process ( porta_data, porta_ddr ) +variable count : integer; +begin + for count in 0 to 7 loop + if porta_ddr(count) = '1' then + pa_o(count) <= porta_data(count); + else + pa_o(count) <= 'Z'; + end if; + end loop; +end process; + +--------------------------------- +-- +-- CA1 Edge detect +-- +--------------------------------- +ca1_input : process( clk, rst, ca1, ca1_del, + ca1_rise, ca1_fall, ca1_edge, + irqa1, porta_ctrl, porta_read ) +begin + if rst = '1' then + ca1_del <= '0'; + ca1_rise <= '0'; + ca1_fall <= '0'; + ca1_edge <= '0'; + irqa1 <= '0'; + elsif clk'event and clk = '0' then + ca1_del <= ca1; + ca1_rise <= (not ca1_del) and ca1; + ca1_fall <= ca1_del and (not ca1); + if ca1_edge = '1' then + irqa1 <= '1'; + elsif porta_read = '1' then + irqa1 <= '0'; + else + irqa1 <= irqa1; + end if; + end if; + + if porta_ctrl(1) = '0' then + ca1_edge <= ca1_fall; + else + ca1_edge <= ca1_rise; + end if; +end process; + +--------------------------------- +-- +-- CA2 Edge detect +-- +--------------------------------- +ca2_input : process( clk, rst, ca2_i, ca2_del, + ca2_rise, ca2_fall, ca2_edge, + irqa2, porta_ctrl, porta_read ) +begin + if rst = '1' then + ca2_del <= '0'; + ca2_rise <= '0'; + ca2_fall <= '0'; + ca2_edge <= '0'; + irqa2 <= '0'; + elsif clk'event and clk = '0' then + ca2_del <= ca2_i; + ca2_rise <= (not ca2_del) and ca2_i; + ca2_fall <= ca2_del and (not ca2_i); + if porta_ctrl(5) = '0' and ca2_edge = '1' then + irqa2 <= '1'; + elsif porta_read = '1' then + irqa2 <= '0'; + else + irqa2 <= irqa2; + end if; + end if; + + if porta_ctrl(4) = '0' then + ca2_edge <= ca2_fall; + else + ca2_edge <= ca2_rise; + end if; +end process; + +--------------------------------- +-- +-- CA2 output control +-- +--------------------------------- +ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out ) +begin + if rst='1' then + ca2_out <= '0'; + elsif clk'event and clk='0' then + case porta_ctrl(5 downto 3) is + when "100" => -- read PA clears, CA1 edge sets + if porta_read = '1' then + ca2_out <= '0'; + elsif ca1_edge = '1' then + ca2_out <= '1'; + else + ca2_out <= ca2_out; + end if; + when "101" => -- read PA clears, E sets + ca2_out <= not porta_read; + when "110" => -- set low + ca2_out <= '0'; + when "111" => -- set high + ca2_out <= '1'; + when others => -- no change + ca2_out <= ca2_out; + end case; + end if; +end process; + +--------------------------------- +-- +-- CA2 direction control +-- +--------------------------------- +ca2_direction : process( porta_ctrl, ca2_out ) +begin + if porta_ctrl(5) = '0' then + ca2_o <= 'Z'; + else + ca2_o <= ca2_out; + end if; +end process; + +--------------------------------- +-- +-- direction control port b +-- +--------------------------------- +portb_direction : process ( portb_data, portb_ddr ) +variable count : integer; +begin + for count in 0 to 7 loop + if portb_ddr(count) = '1' then + pb_o(count) <= portb_data(count); + else + pb_o(count) <= 'Z'; + end if; + end loop; +end process; + +--------------------------------- +-- +-- CB1 Edge detect +-- +--------------------------------- +cb1_input : process( clk, rst, cb1, cb1_del, + cb1_rise, cb1_fall, cb1_edge, + irqb1, portb_ctrl, portb_read ) +begin + if rst = '1' then + cb1_del <= '0'; + cb1_rise <= '0'; + cb1_fall <= '0'; + cb1_edge <= '0'; + irqb1 <= '0'; + elsif clk'event and clk = '0' then + cb1_del <= cb1; + cb1_rise <= (not cb1_del) and cb1; + cb1_fall <= cb1_del and (not cb1); + if cb1_edge = '1' then + irqb1 <= '1'; + elsif portb_read = '1' then + irqb1 <= '0'; + else + irqb1 <= irqb1; + end if; + end if; + + if portb_ctrl(1) = '0' then + cb1_edge <= cb1_fall; + else + cb1_edge <= cb1_rise; + end if; +end process; + +--------------------------------- +-- +-- CB2 Edge detect +-- +--------------------------------- +cb2_input : process( clk, rst, cb2_i, cb2_del, + cb2_rise, cb2_fall, cb2_edge, + irqb2, portb_ctrl, portb_read ) +begin + if rst = '1' then + cb2_del <= '0'; + cb2_rise <= '0'; + cb2_fall <= '0'; + cb2_edge <= '0'; + irqb2 <= '0'; + elsif clk'event and clk = '0' then + cb2_del <= cb2_i; + cb2_rise <= (not cb2_del) and cb2_i; + cb2_fall <= cb2_del and (not cb2_i); + if portb_ctrl(5) = '0' and cb2_edge = '1' then + irqb2 <= '1'; + elsif portb_read = '1' then + irqb2 <= '0'; + else + irqb2 <= irqb2; + end if; + end if; + + if portb_ctrl(4) = '0' then + cb2_edge <= cb2_fall; + else + cb2_edge <= cb2_rise; + end if; + +end process; + +--------------------------------- +-- +-- CB2 output control +-- +--------------------------------- +cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out ) +begin + if rst='1' then + cb2_out <= '0'; + elsif clk'event and clk='0' then + case portb_ctrl(5 downto 3) is + when "100" => -- write PB clears, CA1 edge sets + if portb_write = '1' then + cb2_out <= '0'; + elsif cb1_edge = '1' then + cb2_out <= '1'; + else + cb2_out <= cb2_out; + end if; + when "101" => -- write PB clears, E sets + cb2_out <= not portb_write; + when "110" => -- set low + cb2_out <= '0'; + when "111" => -- set high + cb2_out <= '1'; + when others => -- no change + cb2_out <= cb2_out; + end case; + end if; +end process; + +--------------------------------- +-- +-- CB2 direction control +-- +--------------------------------- +cb2_direction : process( portb_ctrl, cb2_out ) +begin + if portb_ctrl(5) = '0' then + cb2_o <= 'Z'; + else + cb2_o <= cb2_out; + end if; +end process; + +--------------------------------- +-- +-- IRQ control +-- +--------------------------------- +pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl ) +begin + irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3)); + irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3)); +end process; + +end pia_arch; + diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.qip b/Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.qip new file mode 100644 index 00000000..7c22c6f7 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "williams_snd_pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "williams_snd_pll.ppf"] diff --git a/Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.vhd b/Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.vhd new file mode 100644 index 00000000..3162a251 --- /dev/null +++ b/Soundboards_MiST/AS-2518-51_snd-master/rtl/williams_snd_pll.vhd @@ -0,0 +1,355 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: williams_snd_pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY williams_snd_pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); +END williams_snd_pll; + + +ARCHITECTURE SYN OF williams_snd_pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire4_bv(0 DOWNTO 0) <= "0"; + sub_wire4 <= To_stdlogicvector(sub_wire4_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + sub_wire2 <= inclk0; + sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1350, + clk0_duty_cycle => 50, + clk0_multiply_by => 179, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=williams_snd_pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire3, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1350" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "3.580000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "179" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "3.58000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "williams_snd_pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1350" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "179" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL williams_snd_pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON