From 0c9f2b4d7a58ffb829989a7a9e308ee3064b8a2b Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Thu, 22 Apr 2021 15:33:06 +0200 Subject: [PATCH] Merge Time Pilot and Power Surge --- .../Power_Surge_MiST/Power_Surge.qsf | 246 --- .../Power_Surge_MiST/README.txt | 216 --- .../Power_Surge_MiST/rtl/Power_Surge_MiST.sv | 257 --- .../rtl/rom/gen/make_power_surge_proms.bat | 19 - .../rtl/rom/gen/make_vhdl_prom.exe | Bin 119861 -> 0 bytes .../rtl/rom/power_surge_char_color_lut.vhd | 38 - .../rtl/rom/power_surge_char_grphx.vhd | 534 ------ .../rom/power_surge_palette_blue_green.vhd | 24 - .../rtl/rom/power_surge_palette_green_red.vhd | 24 - .../rtl/rom/power_surge_prog.vhd | 1558 ----------------- .../rtl/rom/power_surge_sound_prog.vhd | 534 ------ .../rtl/rom/power_surge_sprite_color_lut.vhd | 38 - .../rtl/rom/power_surge_sprite_grphx.vhd | 1046 ----------- .../{Time_Pilot_MiST => }/README.txt | 11 +- .../Konami Timepilot Hardware/ReadMe.txt | 4 - .../Power_Surge.qpf => TimePlt_MiST.qpf} | 2 +- .../time_pilot_mist.qsf => TimePlt_MiST.qsf} | 93 +- .../Power_Surge.sdc => TimePlt_MiST.sdc} | 0 .../Time_Pilot_MiST/clean.bat | 15 - .../Time_Pilot_MiST/rtl/build_id.tcl | 35 - .../Time_Pilot_MiST/rtl/gen_video.vhd | 70 - .../Time_Pilot_MiST/rtl/pll.v | 393 ----- .../rtl/rom/time_pilot_char_color_lut.vhd | 38 - .../rtl/rom/time_pilot_char_grphx.vhd | 534 ------ .../rtl/rom/time_pilot_palette_blue_green.vhd | 24 - .../rtl/rom/time_pilot_palette_green_red.vhd | 24 - .../rtl/rom/time_pilot_sound_prog.vhd | 236 --- .../rtl/rom/time_pilot_sprite_color_lut.vhd | 38 - .../rtl/rom/time_pilot_sprite_grphx.vhd | 1046 ----------- .../Time_Pilot_MiST/rtl/sdram.sv | 254 --- .../rtl/time_pilot_sound_board.vhd | 426 ----- .../Time_Pilot_MiST/time_pilot_mist.qpf | 31 - .../Time_Pilot_MiST/time_pilot_mist.sdc | 138 -- .../{Power_Surge_MiST => }/clean.bat | 0 .../meta/Power Surge.mra | 39 + .../meta/Time Pilot.mra | 36 + .../rtl/TimePilot_MiST.sv | 34 +- .../{Power_Surge_MiST => }/rtl/build_id.tcl | 0 .../rtl/gen_ram.vhd => rtl/dpram.vhd} | 65 +- .../{Power_Surge_MiST => }/rtl/gen_ram.vhd | 0 .../{Power_Surge_MiST => }/rtl/gen_video.vhd | 0 .../{Time_Pilot_MiST => }/rtl/pll.qip | 0 .../{Power_Surge_MiST => }/rtl/pll.v | 0 .../rtl/power_surge.vhd | 0 .../{Power_Surge_MiST => }/rtl/sdram.sv | 0 .../{Time_Pilot_MiST => }/rtl/time_pilot.vhd | 185 +- .../rtl/time_pilot_sound_board.vhd | 29 +- 47 files changed, 344 insertions(+), 7990 deletions(-) delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.qsf delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/README.txt delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/Power_Surge_MiST.sv delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_power_surge_proms.bat delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_vhdl_prom.exe delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_char_color_lut.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_char_grphx.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_palette_blue_green.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_palette_green_red.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_prog.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_sound_prog.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_sprite_color_lut.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/power_surge_sprite_grphx.vhd rename Arcade_MiST/Konami Timepilot Hardware/{Time_Pilot_MiST => }/README.txt (96%) delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/ReadMe.txt rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST/Power_Surge.qpf => TimePlt_MiST.qpf} (97%) rename Arcade_MiST/Konami Timepilot Hardware/{Time_Pilot_MiST/time_pilot_mist.qsf => TimePlt_MiST.qsf} (91%) rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST/Power_Surge.sdc => TimePlt_MiST.sdc} (100%) delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/clean.bat delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/build_id.tcl delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/gen_video.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/pll.v delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_char_color_lut.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_char_grphx.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_palette_blue_green.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_palette_green_red.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_sound_prog.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_color_lut.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/rom/time_pilot_sprite_grphx.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/sdram.sv delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.qpf delete mode 100644 Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.sdc rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST => }/clean.bat (100%) create mode 100644 Arcade_MiST/Konami Timepilot Hardware/meta/Power Surge.mra create mode 100644 Arcade_MiST/Konami Timepilot Hardware/meta/Time Pilot.mra rename Arcade_MiST/Konami Timepilot Hardware/{Time_Pilot_MiST => }/rtl/TimePilot_MiST.sv (92%) rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST => }/rtl/build_id.tcl (100%) rename Arcade_MiST/Konami Timepilot Hardware/{Time_Pilot_MiST/rtl/gen_ram.vhd => rtl/dpram.vhd} (53%) rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST => }/rtl/gen_ram.vhd (100%) rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST => }/rtl/gen_video.vhd (100%) rename Arcade_MiST/Konami Timepilot Hardware/{Time_Pilot_MiST => }/rtl/pll.qip (100%) rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST => }/rtl/pll.v (100%) rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST => }/rtl/power_surge.vhd (100%) rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST => }/rtl/sdram.sv (100%) rename Arcade_MiST/Konami Timepilot Hardware/{Time_Pilot_MiST => }/rtl/time_pilot.vhd (85%) rename Arcade_MiST/Konami Timepilot Hardware/{Power_Surge_MiST => }/rtl/time_pilot_sound_board.vhd (95%) diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.qsf b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.qsf deleted file mode 100644 index 67b15917..00000000 --- a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/Power_Surge.qsf +++ /dev/null @@ -1,246 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 18:23:45 September 22, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Power_Surge_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] - -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name TOP_LEVEL_ENTITY Power_Surge_MiST -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name ENABLE_NCE_PIN OFF - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# SignalTap II Assignments -# ======================== -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise - -# ------------------------------ -# start ENTITY(Power_Surge_MiST) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Power_Surge_MiST) -# ---------------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Power_Surge_MiST.sv -set_global_assignment -name VHDL_FILE rtl/power_surge.vhd -set_global_assignment -name VHDL_FILE rtl/gen_video.vhd -set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd -set_global_assignment -name VHDL_FILE rtl/time_pilot_sound_board.vhd -set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sprite_grphx.vhd -set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sprite_color_lut.vhd -set_global_assignment -name VHDL_FILE rtl/rom/power_surge_sound_prog.vhd -set_global_assignment -name VHDL_FILE rtl/rom/power_surge_palette_green_red.vhd -set_global_assignment -name VHDL_FILE rtl/rom/power_surge_palette_blue_green.vhd -set_global_assignment -name VHDL_FILE rtl/rom/power_surge_char_grphx.vhd -set_global_assignment -name VHDL_FILE rtl/rom/power_surge_char_color_lut.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/YM2149.vhd -set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/vol_table_array.vhd -set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip -set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/README.txt b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/README.txt deleted file mode 100644 index 5198b564..00000000 --- a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/README.txt +++ /dev/null @@ -1,216 +0,0 @@ -Arcade: Power Surge port to MiST by Gehstock - -PSURGE.ROM is required at the root of the SD-Card. - -Todo: Sound - - - ---------------------------------------------------------------------------------- --- Time pilot by Dar (darfpga@aol.fr) (29/10/2017) --- http://darfpga.blogspot.fr ---------------------------------------------------------------------------------- --- gen_ram.vhd & io_ps2_keyboard --------------------------------- --- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) --- http://www.syntiac.com/fpga64.html ---------------------------------------------------------------------------------- --- T80/T80se - Version : 0247 ------------------------------ --- Z80 compatible microprocessor core --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) ---------------------------------------------------------------------------------- --- YM2149 (AY-3-8910) --- Copyright (c) MikeJ - Jan 2005 ---------------------------------------------------------------------------------- --- Educational use only --- Do not redistribute synthetized file with roms --- Do not redistribute roms whatever the form --- Use at your own risk ---------------------------------------------------------------------------------- --- Features : --- TV 15KHz mode only (atm) --- Coctail mode ok --- Sound ok --- No external RAM/SDRAM required - --- Use with MAME roms from timeplt.zip --- --- Use make_time_pilot_proms.bat to build vhd file from binaries - --- Time Pilot Hardware caracteristics : --- --- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram, --- sprite data ram, I/O, sound board register and trigger. --- 24Kx8bits program rom --- --- One char tile map 32x28 --- 8Kx8bits graphics rom 2bits/pixel --- 4 colors/32sets among 16 colors --- --- 24 sprites with priorities and flip H/V --- 16Kx8bits graphics rom 2bits/pixel --- 3 colors/64sets among 16 colors (different of char colors). --- --- Char/sprites color palette 2x16 colors among 32768 colors --- 15bits 5red/5green/5blue --- --- Working ram : 4Kx8bits --- Sprites data ram : 256x16bits --- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x4bits - --- SOUND : 1xZ80@1.79MHz CPU accessing its program rom, working ram, 2x-AY3-8910 --- 8Kx8bits program rom --- --- 1xAY-3-8910 --- I/O noise input and command/trigger from video board. --- 3 sound channels --- --- 1xAY-3-8910 --- 3 sound channels --- --- 6 RC filters with 4 states : transparent or cut 600Hz, 700Hz, 3.4KHz --- ---------------------------------------------------------------------------------- --- --- Uses 1 pll for 12MHz and 14MHz generation from 50MHz --- --- Board key : --- 0 : reset game --- --- Keyboard players inputs : --- --- F3 : Add coin --- F2 : Start 2 players --- F1 : Start 1 player --- SPACE : Fire --- RIGHT arrow : rotate right --- LEFT arrow : rotate left --- UP arrow : rotate up --- DOWN arrow : rotate down --- --- Other details : see time_pilot.vhd - ---------------------------------------------------------------------------------- --- Use time_pilot_lite.sdc to compile (Timequest constraints) --- /!\ --- Don't forget to set device configuration mode with memory initialization --- (Assignments/Device/Pin options/Configuration mode) ---------------------------------------------------------------------------------- - -+----------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+---------------------------------------------+ -; Fitter Status ; Successful - Sun Nov 05 10:17:02 2017 ; -; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ; -; Revision Name ; time_pilot_de10_lite ; -; Top-level Entity Name ; time_pilot_de10_lite ; -; Family ; MAX 10 ; -; Device ; 10M50DAF484C6GES ; -; Timing Models ; Preliminary ; -; Total logic elements ; 6,231 / 49,760 ( 13 % ) ; -; Total combinational functions ; 6,005 / 49,760 ( 12 % ) ; -; Dedicated logic registers ; 1,579 / 49,760 ( 3 % ) ; -; Total registers ; 1579 ; -; Total pins ; 105 / 360 ( 29 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 475,648 / 1,677,312 ( 28 % ) ; -; Embedded Multiplier 9-bit elements ; 2 / 288 ( < 1 % ) ; -; Total PLLs ; 1 / 4 ( 25 % ) ; -; UFM blocks ; 0 / 1 ( 0 % ) ; -; ADC blocks ; 0 / 2 ( 0 % ) ; -+------------------------------------+---------------------------------------------+ - ---------------- -VHDL File list ---------------- - -de_10/max10_pll_12M_14M.vhd Pll 12MHz and 14 MHz from 50MHz altera mf - -rtl_dar/time_pilot_de10_lite.vhd Top level for de10_lite board -rtl_dar/time_pilot.vhd Main video board logic -rtl_dar/time_pilot_sound_board.vhd Main sound board logic - -rtl_mikej/YM2149_linmix_sep.vhd Copyright (c) MikeJ - Jan 2005 - -rtl_T80/T80se.vhdT80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) -rtl_T80/T80_Reg.vhd -rtl_T80/T80_Pack.vhd -rtl_T80/T80_MCode.vhd -rtl_T80/T80_ALU.vhd -rtl_T80/T80.vhd - -rtl_dar/kbd_joystick.vhd Keyboard key to player/coin input -rtl_dar/io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) -rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification) -rtl_dar/decodeur_7_seg.vhd 7 segments display decoder - -rtl_dar/time_pilot_prog.vhd Time pilot video board PROMs -rtl_dar/time_pilot_char_grphx.vhd -rtl_dar/time_pilot_char_color_lut.vhd -rtl_dar/time_pilot_sprite_grphx.vhd -rtl_dar/time_pilot_sprite_color_lut.vhd -rtl_dar/time_pilot_palette_green_red.vhd -rtl_dar/time_pilot_palette_blue_green.vhd - -rtl_dar/time_pilot_sound_prog.vhd Time pilot sound board PROM - ----------------------- -Quartus project files ----------------------- -de10_lite/time_pilot_de10_lite.sdc Timequest constraints file -de10_lite/time_pilot_de10_lite.qsf de10_lite settings (files,pins...) -de10_lite/time_pilot_de10_lite.qpf de10_lite project - ------------------------------ -Required ROMs (Not included) ------------------------------ -You need the following 11 ROMs binary files from timeplt.zip (MAME) - -tm1, tm2,tm3, tm4, tm5, tm6, tm7 -timeplt.b4 -timeplt.b5 -timeplt.e9 -timeplt.e12 - ------- -Tools ------- -You need to build vhdl files from the binary file : - - Unzip the roms file in the tools/time_pilot_unzip directory - - Double click (execute) the script tools/make_time_pilot_proms.bat to get the following files - -time_pilot_prog.vhd : tm1, tm2,tm3 -time_pilot_sprite_grphx.vhd : tm4, tm5 -time_pilot_char_grphx.vhd : tm6 -time_pilot_sound_prog.vhd : tm7 -time_pilot_palette_blue_green.vhd : timeplt.b4 -time_pilot_palette_green_red.vhd : timeplt.b5 -time_pilot_sprite_color_lut.vhd : timeplt.e9 -time_pilot_char_color_lut.vhd : timeplt.e12 - - -*DO NOT REDISTRIBUTE THESE FILES* - -VHDL files are needed to compile and include roms into the project - -The script make_time_pilot_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux. - -Source code of make_vhdl_prom.c is also delivered. - ---------------------------------- -Compiling for de10_lite ---------------------------------- -You can build the project with ROM image embeded in the sof file. -*DO NOT REDISTRIBUTE THESE FILES* - -3 steps - - - put the VHDL ROM files (.vhd) into the rtl_dar directory - - build time_pilot_de10_lite - - program time_pilot_de10_lite.sof - ------------------------- ------------------------- -End of file ------------------------- diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/Power_Surge_MiST.sv b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/Power_Surge_MiST.sv deleted file mode 100644 index 74b4e3a2..00000000 --- a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/Power_Surge_MiST.sv +++ /dev/null @@ -1,257 +0,0 @@ -//============================================================================ -// Arcade: Power Surge -// -// Port to MiST -// Copyright (C) 2017 Gehstock -// -// Time pilot by Dar (darfpga@aol.fr) (29/10/2017) -// http://darfpga.blogspot.fr -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -//============================================================================ - -module Power_Surge_MiST( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27, - output [12:0] SDRAM_A, - inout [15:0] SDRAM_DQ, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nWE, - output SDRAM_nCAS, - output SDRAM_nRAS, - output SDRAM_nCS, - output [1:0] SDRAM_BA, - output SDRAM_CLK, - output SDRAM_CKE - -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "PSURGE;;", - "O2,Rotate Controls,Off,On;", - "O34,Scanlines,Off,25%,50%,75%;", - "O5,Blend,Off,On;", - "O6,Initial Energy,4,6;", - "O78,Lives,3,4,5,6;", - "O9,Stop at Junctions,Off,On;", - "T0,Reset;", - "V,v1.15.",`BUILD_DATE -}; - -wire rotate = status[2]; -wire [1:0] scanlines = status[4:3]; -wire blend = status[5]; -wire energy = status[6]; -wire [1:0] lives = ~status[8:7]; -wire stpatjunct = ~status[9]; - -assign LED = 1; -assign AUDIO_R = AUDIO_L; -assign SDRAM_CLK = clock_48; - -wire clock_48, clock_12, clock_6, clock_14, pll_locked; -pll pll( - .inclk0(CLOCK_27), - .c0(clock_48),//24,57600000 - .c1(clock_12),//12.28800000 - .c2(clock_14),//14.31800000 - .c3(clock_6), - .locked(pll_locked) -); - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoublerD; -wire ypbpr; -wire no_csync; -wire key_strobe; -wire key_pressed; -wire [7:0] key_code; - -user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( - .clk_sys (clock_12 ), - .conf_str (CONF_STR ), - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), - .SPI_MOSI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoublerD ), - .ypbpr (ypbpr ), - .no_csync (no_csync ), - .key_strobe (key_strobe ), - .key_pressed (key_pressed ), - .key_code (key_code ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ) - ); - -wire [14:0] rom_addr; -wire [15:0] rom_do; -wire rom_rd; -wire ioctl_downl; -wire [7:0] ioctl_index; -wire ioctl_wr; -wire [24:0] ioctl_addr; -wire [7:0] ioctl_dout; - -data_io data_io( - .clk_sys ( clock_48 ), - .SPI_SCK ( SPI_SCK ), - .SPI_SS2 ( SPI_SS2 ), - .SPI_DI ( SPI_DI ), - .ioctl_download( ioctl_downl ), - .ioctl_index ( ioctl_index ), - .ioctl_wr ( ioctl_wr ), - .ioctl_addr ( ioctl_addr ), - .ioctl_dout ( ioctl_dout ) -); - -sdram rom( - .*, - .init ( ~pll_locked ), - .clk ( clock_48 ), - .wtbt ( 2'b00 ), - .dout ( rom_do ), - .din ( {ioctl_dout, ioctl_dout} ), - .addr ( ioctl_downl ? ioctl_addr : rom_addr ), - .we ( ioctl_downl & ioctl_wr ), - .rd ( !ioctl_downl & rom_rd), - .ready() -); - -reg reset = 1; -reg rom_loaded = 0; -always @(posedge clock_12) begin - reg ioctl_downlD; - ioctl_downlD <= ioctl_downl; - if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; - reset <= status[0] | buttons[1] | ~rom_loaded; -end - -reg [10:0] audio; -wire hb, vb; -wire blankn = ~(hb | vb); -wire ce_vid; -wire hs, vs; -wire [4:0] r,g,b; - -power_surge power_surge( - .clock_6(clock_6), - .clock_12(clock_12), - .clock_14(clock_14), - .reset(reset), - .video_r(r), - .video_g(g), - .video_b(b), - .video_hblank(hb), - .video_vblank(vb), - .video_hs(hs), - .video_vs(vs), - .audio_out(audio), - .roms_addr(rom_addr), - .roms_do(rom_do[7:0]), - .roms_rd(rom_rd), - .dip_switch_1({2'b11,lives,energy,3'b000}), // Cabinet Unknown Lives Lives Initial_Energy Unknown Unknown Unknown - .dip_switch_2({stpatjunct,7'b110_1111}), // Stop_at_Junctions, Unknown, Unknown, Cheat, Coin_B Coin_B Coin_A Coin_A - .start2(m_two_players), - .start1(m_one_player), - .coin1(m_coin1), - - .fire1(m_fireA), - .right1(m_right), - .left1(m_left), - .down1(m_down), - .up1(m_up), - .fire2(m_fire2A), - .right2(m_right2), - .left2(m_left2), - .down2(m_down2), - .up2(m_up2) - ); - -mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video( - .clk_sys ( clock_48 ), - .SPI_SCK ( SPI_SCK ), - .SPI_SS3 ( SPI_SS3 ), - .SPI_DI ( SPI_DI ), - .R ( r ), - .G ( g ), - .B ( b ), - .HSync ( hs ), - .VSync ( vs ), - .VGA_R ( VGA_R ), - .VGA_G ( VGA_G ), - .VGA_B ( VGA_B ), - .VGA_VS ( VGA_VS ), - .VGA_HS ( VGA_HS ), - .rotate ( { 1'b0, rotate } ), - .scandoubler_disable( scandoublerD ), - .scanlines ( scanlines ), - .blend ( blend ), - .ypbpr ( ypbpr ), - .no_csync ( no_csync ) - ); - -dac #(.C_bits(11))dac( - .clk_i(clock_14), - .res_n_i(1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -// Arcade inputs -wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; -wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; -wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; - -arcade_inputs inputs ( - .clk ( clock_12 ), - .key_strobe ( key_strobe ), - .key_pressed ( key_pressed ), - .key_code ( key_code ), - .joystick_0 ( joystick_0 ), - .joystick_1 ( joystick_1 ), - .rotate ( rotate ), - .orientation ( 2'b01 ), - .joyswap ( 1'b0 ), - .oneplayer ( 1'b1 ), - .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), - .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), - .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) -); - -endmodule \ No newline at end of file diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_power_surge_proms.bat b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_power_surge_proms.bat deleted file mode 100644 index 163a73cd..00000000 --- a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_power_surge_proms.bat +++ /dev/null @@ -1,19 +0,0 @@ - -copy /B p1 + p2 + p3 power_surge_prog.bin -make_vhdl_prom power_surge_prog.bin power_surge_prog.vhd -copy /B p6 + p7 power_surge_sound.bin -make_vhdl_prom power_surge_sound.bin power_surge_sound_prog.vhd -make_vhdl_prom p4 power_surge_char_grphx.vhd -copy /B p5 + tm5 power_surge_sprite_grphx.bin -make_vhdl_prom power_surge_sprite_grphx.bin power_surge_sprite_grphx.vhd - - - -make_vhdl_prom timeplt.b4 power_surge_palette_blue_green.vhd -make_vhdl_prom timeplt.b5 power_surge_palette_green_red.vhd -make_vhdl_prom timeplt.e9 power_surge_sprite_color_lut.vhd -make_vhdl_prom timeplt.e12 power_surge_char_color_lut.vhd - - - -pause \ No newline at end of file diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_vhdl_prom.exe b/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/rom/gen/make_vhdl_prom.exe deleted file mode 100644 index 1e5618bf9417eaeb90556e3021a78e9860a815e8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 119861 zcmeFa34D~*^*4T>XXcqD3p0TP!#R;I3im94{WDd))P*nEKjw;3-)UlQLkgOB&vHgLsaCW=mlXa{` zB=P6lm;e@v{KDCr72jJL2<`Y#zVq?1{Yk!c9UVkEOl{aj(9wTgqPA~#laeRfnks`n z77K^+LSEnO;;I^=ZlJFn_)xxu_}KmmMPc9UShLJGMD(5b5Z`h_l7EHBcMg}ipW^%Q zq578KWBWt9ET2=bSW@2Gj-Vf(ui+zwOS1eb6#nIN<`qcz!BGg>(Kwk1-;yNjOY+TM zAn_-%5cGm?G{Pemiv%R!f|Dier}o$hzBGg*sL_*usPFPQC+ADToEq}F!Xz}UXelia|q(bTM{vTLqWVGH!yJ9BqINk@a{c}cH89T z74$V;w(Qz>1_#T}-fO%84jNW_C9i^ZTeK$`imi_u7XwZhPvd)AUo7+xP1u2D$R)J* z(LwwTya^SP$oenDhfto)GWazG31j=^D2#vL8ovPcVhLk79{;vBm#iXp*FN^sSHO7J8l7z;{oQO)Wz z*Hnitd%G7gC5Z{IwNko=(t(9~YH|a?ZTmyBhZ4)&ml5@l7bM@-g-H6)0H*ffOQHB-nQAvuAx-BS z1@9+}?*r*RqWQK?24ljw9q6_`-_|g&y~eLwRF5T$D^0f1h}iaiX9|_zN@FvLN*F(! zB_+nvf(3mKgFzHLIoLn&5&8g)vL_XpXI;<*ByLPcB?s<+h8svffnu{ZE+hJ*gINbJ z1%R4(k)-aQXrTUqhrv>k$l8rk1h+jOYe7zTLQKJvp@cY;w)Oc~{?;dBflzm!=6k^3 z^Yoff`le&x8LUS_@yF5WgQ3KNClGnb=>_{6lk+E$_WHmN zz*N#xtCiQkRTh79;1-#tc_ik-qGw6%oxb&G&J;tB&pU4zryMz=v zpF#a zgeDCQkZo_EQy#)36a%l0qu3Z?WyGHmLG!66>!Ac>_oUx}VBlw9+H0H+CK?b2_kk%C z|K(to_Yz=p2?0j`*Vkmjdop<$-?6+iU#jLgs40V{~BG z$CyaHa(3gJ;;%zI{SA~;{4KWl)uH(B!BZJ8_lM%Evj@_^(0#Grff1AlW``2~P>$^<-^f{*4q9 z4<3Nf10v=|(gRN@2}Qf8LmsBuk+9Xo$b!!R91p%mXwfcWu(;+BSC0``Ld>fNO5?vQ z+BJe0sK-dm>tiH?&(1K<&hRs0uqy6Bo1P$fgAlflB)oPE32wWDFDZui7u(8!Ig%{H z*IGS#SU@Kq&s$Lo-1i2r7ZQ>;i|>XFM1V4Na3F^EiU!!uLRM zzwd#4XvmAW5?s)!;OP#2tRZ86r<+R@>Iv@0I5{lG36;%i6c^Y-@_|zY9gp_AeG#=1 z_rQ<>B}f7G7$fZ^rnRmm>jK4a#4ce-50ol~emlbu33-ZPkDXyiE4vj#pPhjo!d4mn z04;(-4#|QxKo-N}is2!%9>lb1p&Zhk2KbSRO2kX8}T(D>;-f~N`=p|On* zc~JC$pJzd0B7Gk*+(!(F^gV#pLUlU`Wj!Uid2)RfioZhSyn*XwnzGzLD875(3Yn-3 zJaOZ4lF|u+lnufbA~X|w{AIL!{yDoLWH9Sgszw|z6O+%Yft4f^!c{U0;^ejRUg%6FJd>2CE9-9*54wr?B5Pd zw*)%+U_U6TLOUhb!JiXB7V&mP_&x~ceBt$Z_uGMiGtdg?;Dpg$Pj%nlISRcQu$E7% zd{|K*#Ny|@`LviR1|xOlz!gvirSU%5`sHAG0vdEVBFo}^56RVh&w?K}&|Yim+j513 zRr;^7<`2a`D4p@z4+8)T1`nM~{fmS>;C#aQiMJ%4`(dIoExuYfD)A(BeiG{5tA%E~ z91nWptDT|l$Fb-g48$gc;{O=P!upn0`+cEpgPkYJavVGrjo15d0Oc#inC(gb;W}EP ze<#NJ;owBX$3HyuTiPI6^HJ)HMWI9n=3qjPKYH1l;0j#!kK*E$0pHfEAxsYCjVpN| z7NGvVEB{Dz8jP_^)j*tMwlC)Y803qx`L^cM;KqE!{_&jip%LVGmNVikxd1h1#E}f} z$)^VyMo9NOq-H|@E))hcjneb@et)?WtJV!5tMOsykn(B##}4|g#QacWKlYj&_r7g) zNMw%vZB~{~gHM)rIil6LACj#a{I|%#@7p#($&jO~$dd6LQ^qIe&>I{gqu~96ek7FT zljHrTJl>xJ|G~wGO3shIgK2hLK5^6}_$78;+uoNI_HF$mQp$O7Ax46n2fqfTu~+fS z`Tb4sOYVaYBZ~F4ikIcT%!=QRc-CQ1$7|7t@2NhFofwMOKx-y$$n8QM-}PnGGAhNg6`zY8&CsA17AY&q1*VxV;d3Z97J z@%49t5F3iWS{gq*@MoX{hw;@b%{$5VD_U)}@LFghndeJo@h3V*Q-7$|DLOB?UPz=b zslzaO(s%VgkSlsR2WYV1t>pZL?pge+Xl7ZW&>u_`ddjrNfcq}*276KW9u1q4?4rfb zbiRn0JuneZ6igm$pnY3^2nKABD|&JpN*{g8Q6B$&nPb-DwWN)L{-V7>M57L`Aw^A=KnmC<$75 zU^ylM3NZ=^6RV+r)2~Iuszgb^GccXzhmueG&7vAI@pQjkTauXiT9`KGZ^cqWJ&^-w z?xJ(g+r8I#3{@~iDH1rpm zu_uJ#6Tr&kN|0dR!7~8r(S6C+@SW<9;bP7kNWe~a!*GRP|jQhb>)>Dq%=;~deMEQ=Agfn~ar9*eaB6M&LRpa^2sc4cn0n7d@Nu-k9 zW7||@RFWum2Jv9omJK9P?ZIl+w+&}ZXw%(kvfi7h4||q<@ao`T=})OK!ALET7=^T+ zBHsgjA?-snLiZ6^TT)_cH%;z7;_+?mr)KX-_ajsA^oRBai6RE(z|hcr1kb_Cfnj8I zzFIotmt_ubS-czrcXfZ!F1bA23^p!8^tyvPQHB!VgIduCeWDACsVSwG?W2N}&gd`K z_LaqhoK&YAmLch(-7@M?Dij3A4s5DLsXD)>a*)GlG_ifHBq4=jJr{en+PL>i!bn16tAheO<9TD1Q)=?1%0`rD9K^LcVRJ#}4M>E997veV%NFTW3*E6{CfU zJ&8)szzm2)>pTqdzy!dy)h_A3#>*C$pB;1m4a?OMB&z^okOE#>n zH}skDMTmd2pbt${m$)fH7?F&66-t5zR(z?oe%J$_o_9jAU*pikm z?%(8bgrJ$8il#yX<&`bo*ZEdK-`{qtnHVU5RrR?6H<1Zo$M;~R%lBX?69aY$vhMy942b7?vN21q3-x??cithNn(ye>ywKv0 zV$)S$hvM&&-fKlhSbhCgZ4PM7XxiJTAhcm%njk%asr)nwR7VAR2BQN7LPqIlP)Xvi zhGsk^`47HHT1KvZ1GM(vit$0!c^ey>^r@7#7Yqf@BlW0Iy-`7_d$Q6H_#Uj$U2*Kz zurajd_t%$@=3FyPB`o9PWE$gTM1-_`s6KT-Vdl0cV{_5|eccDq{566aAr2MvSRU+u z?=PPofc19U{+KV+eF$^^F*L_xodX5Whh&Z@>X7v$m$#GhJ^=MX%&-VME9TayFT=8bT#(IUpaI&%nXBB zD>ujj;VH8iMe}V_3m#H~i%+C|Lzv>@#&|>?454^D>-Ya|$o5^@Cs4hg(54m^RMc<+ z>;?(rTSVx=S^`UmP(15KLeZ(elY?~l{sRk4!vU)x_WkkQv6&cbBhg8Jbz!*^e|a$T z33Ni|`zYBp)J(Fu55^9w^)yCK&w{<+Jmi-8C%(IOSQ~(fRJ7`xC|mYiX{= zT%@21@tj=)oRsRJtyCpz^;8&2OqfHZ+%@-(H)h>>5}>_!3WE_=k=?NqLLdAp6rV7G zIJ);(%TCx&u&@}+%20XHsY0OJzt**o3O%Fb5Bom!ZW5vu-2uw!YH%qrR>hQQ0~v*q8{x#JJ$=h}vuX?HnPzPSLm5_%k4C zY*gc2favF^u_q73gM9$|6}WFOYl>{6^h-e)%vu0sFzd<)7R4k)j@As&1`az&0+xz# z<9k$u9tkc7cyKeCQjSn_{-f#z=aQV0AqQ12143GC9#%BZNYa932znE#bcFW!;ENcX zBSPE$3|)uEUMPN$M)5g*G7Dg>Vw6&np7htL4m{uGhSt(I3F8jL73`1yA`~ZCsiszf zVt6IOvNER3?~NsmzwpLL@Qg8sp*y@)*L0igal$bj7|6#zuK94==4O!;#Xrc zV5Y;e4b^?J^Djv9{@IkI21%0QwvsrM@C<(_Ug;nB64o!^d`5Df2+l(9)6CX8A@FavaAN~gyF?=`-FZ~7a| z+E5RPk6}GvERp=N=~B{OV>(bd!szKo@nco|O#^?0IzMy`WaWV}m~{zBcxqrjQLkrh z*4ukVWoQ}Q&!HKb9UT+8?4ZQDy&^PALNa#KA44;6#^)7l&l;-!=m~3*I*n4^B zUi18E*cg}O9{!E-7P{v*fL{6i8wXzL`$n|j<=?*2_sW~EP52ce-Z;?pRxsxK%`30` z<2UE#9)8#72j}kJy!^^vZRkbM{^k|@OUBDG4^CZ(di3@VPCb>wH5`sW9}xW$#z!-5 z#;+L0e+A=DaCj4k&vCes!$uBYHS1 z%JQCId==x5FmB5IOP$K+bq+TU3%||yaK078_*OAKdRTZW<7+rP|2W|#On*-V(M^tFBc5u@A`_ucXX>z=X7RZ zFB{R!hou?+EI*q}{6FFU-4+OUL}KBl){S+|O%37pI^5fg#3Iq~hPu{<=15eC>MgCY zy3K(lfvFvV#-`>7cvaZe8A}n-bpp3Mr^fU%?Cgk0cy>puA>7=yzNtQ3P_S_R?7HUWnZz@@wX-D>1r_l`T$++1BCWBe*cQsU z36k5}qOm|;ityGqUl>4vP>_HnjIxk_-nxc{=gy|x6}8qLyrV_VvB@f9@O zh^>o8>$c?O2as`KYQqd-vr2x9ypWN%qiKC>T{8&?Qwf(yQA?Hu@}(PQC?KKYDO}eird*-7o`r*t1exMIQdtxF%oTTZrc=y*0rvWn8_>F1gln* zRh&6PRMtgfO=zg*wvGF8{Z zQOCvF+5#Od7>?9+bdfpIj!0A|(h$g7y{g14#p>1zTQRUy@npHfEp=$}Xf$tzoI0ra z)Q-HV>t_b0uAdPIR3}tB+yvb)QkbQM74JjItpDMnA#rLP}dP?Z3{HD)UA)q>cFsUYHJmNz?!CLth289 zjLrzABPB-J8_@@t4C}VUA{d>q0Cl&LqFP-bomr>$j!0)i8>-&iR$oUlX{g8A>f4$F z=$j5AOl_F0O7rRI)-_>{HC+_3^S6i&u~F2EsDR=S&>Q&opTGZ$Er7MGh7aB8_9I-2 zj}ve$!b>x7{TOf;!h5l)%mlm>;Vf69X*93ekkm zmjSmU?7-(MfV&W0h0j+3_aeLjpI*Q_5Ppkrz&jD1Jx+*Q0M{an;j;s97sBibLfj2F zfG`Jk@|}S55iSnkJP&Xo!b|aahWHVF6`vOX_abbbEX2!z+Yxr)GeA5D-^Ax_z=si@ zorCMyfNK#pOhY?-5&Q^m!zTcE2g1Ynp8}Y|4tz=g zcOm=^K4pM+BK#Pi8sdSbx*DHaz`Y31IuUsSu0>dn&t|~w2=Bt@%Yb(x^uzG56)=S} z@#zJekMIaSHvkqhh4=`cZxIZOYzsd318zt74nBJTA4d4q*=QfYy$GknuKgPE|L5<2 zd<$r(q2|owa4MPPOG%#<8lbsay?(GRWfB+s66yBbYWC!`Bs@sJjEqa<|a#~k&JaL zgUWaZrzgIsjgMs7dDGk??G8`AyVliiR66_ge#ED{x1~GMf8@>g)VkYUeX^`(dE8Fn zp6kfhYqfS+wz_Z z7%p=-Zsx)Ak=1ekPU%fXwci5$bRG2kwMkm$t$6?G`Xp|L%5G3t1BYMcu$RMcbNEvZ zpW*NThwpOeyiv)S$l+`bzrf)-4x=1?mBTwYe1OA#4&UNX#|0$%OW|-Lhch`0ada7{8puUJiF~_+1Vk=I|*FU*qsFhaYn2xmigb$>Deo^Ek}sa0!Pc9F}pohQsqY zY~-+=!_6FC&f!%YUdQ2f4)5UbUJmc)@DUF8ariukuW|SX4i9tqA%|vr{bwAgmiYhs zICx2vM4DkfD8?=hJFwBYjz2M=VI2N~{A3FK=t;Y>tGa{h~;S)kGuVyipP&N|fpt_KltGrLB!^ zMItUKTRLKqmKyA^iaJ(clSGiXlVWO`>MtyA!|qFn5A@Pj)D6axi;k*gsiQ1XxA7>l zsBo0E)isnUd&rr%V&#xqu}bV~+oCPBPnE)9Z281d6>CO0S9G?@&09^~y5@)&Bx-S8 zJ6Rcu+t84BPt@fEt*ou>!p?S+8BHABB1AgH@Ro0N>!zkwwA0s|)sfihR%O#^2yU*A zw9`HgwM4Iodz{tHkx09E&{-3SwluZY#Uf^Bh)0|?%^hfhHFeFM5%IM1xI)B1CufSZ zWDI$t3YpPZf%xs_AFR-UHP^SbZj|v@B?Bj8R$Y60n2aw%tWy-2p3u&6H;&#H;kx>k zhUQkW1yD-|Y$TMeNQiK~g8nGNjr5i>mgAZfjYew0E1R%d)n6zU>R~SF>w37eRnorg zs9Oi)l(^r4K@W-$KXKGY==GgP97<-Nqp=V`cJ%vrCyNtv zoyvA3#0qCeEZU6BL@7b7^)2n9k|6xYuFSd7ECQ)7S_k}J_?#ZBS`{ptH+MF=oU+YC zp8sy2mX3|}(U@66D&_zDKfk~5n3b$$de^XX0*jgH{bP=u-s1ZY@Nd}yMLSi$m2h}& zm%sg;nV%qkIxI|z z-_#>1pUVGKfyv*?`X%#I`4^sS^6zB+J)g?|O{@&LJmU%_r+fkA7->}br>-&i3j>OO zCT-x4@u&FzagNE~KDkhGIgY_gB*ouzp2^?E{BM1F`(I%4w@)jSk`Epy10{dbmrefK z6BYk)*tt9hEdF-p|EbL7=r1LI;^n6N{F9XYr$4oQ=EK6E+F#64{L}TLWfMiok8L;k z+vh0$3y;nIAL?gpffsYF`LC^9wK`B7m_K{r?72dlJ$sJzAG-o|2sI1qqB;DDY>wax z$DDPYP0bDJyJ1d}aqjH=*##WAdC|h~!ufQFHA^zgn>z>VR~s`V!h)?j_MJ=>QayCd zRllJwDs+z<`-Am3Cy!vOEp?t&1W>1Yp3`y)Cn)E9Zb56!IS1cb-q^pH0Q zZ@9Q(RZVbhjp%pkUvXW8^0_JtLT%U`>v5My<^;-IMY)P89#`c&MM*Hl@2Z@yC|_kt zwySc1qVzB&;Hq4xC|5Hj&&69_ZiZ`Is)6!d<(rE;Ffw|XFyB=jSznAAUhBG1HsK;7 zlz?y@6P6Gm2*UMDIE4r+K)8VkrxIZ$2sbjJkOnkI2>n(@D}l}x`gTUw0-Y!H+Ze3{x=`p}V{`-1lZF0uM%!Igb(@9$4MsP+s_KE> zE>TBLm*%Q!0KS9quK-^M{F{vT0`F)S`W=klLh-=wWPAt3Hwpb)jNc8s0r*{v?*zU` z=-*~^7tqB*{|=*lKnqaqyBXg{IO=^5EiMBNheIKXZ;dPZn z)^)D8BA(=kyS*+lA1%k-g8B_LZ8FQJIBussZUydP$k?Yjc9)8^rY|RchNJt2MO*2g zWrlrTk$Pt7s^t|GWx^RD4U@Y3teT*3ezA<;Gf7D}qol4h?xJDNWr_dX98iYFWjqmEp>oDq$4-oTRQ!66W4zWwUU;Ft$sy za!o~P35Ek{snp_7QI*htOzKby68cYkD2>yTi|LO-R70-*#3_V?idL1B1%>`LC3H|G z^bz_=8fEK{*(%CRshypkE08QrlSjqefKd-(PZ`pY2jghR3GUvvp@d&6tX%fr=0Yl7jTs$kK)xk#jUxE{gUMk+20!!z5W z4S2Jj6^L-b@)+yvP}EMQ>aLo)^@_C7MIEc>I9*k^XcFBRX~4AF#6-g-Eu9tZ_3~-4 znUlMi+z5ja9*J96HR0JncF}6sWNF3-{UYX1vt-W|`j?nE!c~HMMingM%Phk$sYwwR zGk2yX0<-!OCXP0h@}-iT`On|n==^d^)lIFc_|@S5$|{pe`exku+%C3a40!`$Psc=3h)aEF8nTOW*1`6(UCM(DWa< zPKO?GgaA{cY=VneUJ%Immr{} zb}<3^5d_rbAtpc}f&dNpFcY8wLBP}DznB2c2LhfCKV?F%BtS?1j0rm=0b2SIChU|1 z($ha@N}r;jtbI)BR}>WXQKlSF6qNQcrW{rj6n8gMx*Sv((%5^L0>5#xGe}L##@FBp zPuG7Sm2=jL=2&&zM$GG-F6s^77yyd$LrEF!@}dK!gs+M z`H0CdLO70ES?P zd{@+6wRulD6U@7b(?hj(aE)}4F40O8*V5}G({g+p;nMP=mBBDvfQCcC zB3zskg?g_4x9Mns2=2<^KB&;A`qk2nNcHQQ@%*306rCu*r!(#(Jlc#jc}#Ihj=JcE z2Gnc@6Fnf(iH0nAcbg{XC#nR*ga(?IQjE}F^s2*Q!&EXMu7>pMDIgg%=oBSE1> z${fZsC5O=S86OS2xv@?bvw&&YptWsmZ4>%jri=vzcki(Fm#v}aj3<^zOB0?N^O+}? zNm!|4>CePzDj{a>LjSvHM?EJG6lB;M!4vFcf4+QTogy-*QHeoLOH5PQ$Ril{3dd1B zqc8HWN1r(=j}@~3DV-jQH~Vx&X<5+h)J*+)|7agNwY&~@V_PwHZ{Xqz-i=f=^06SQ zd?Ux<`G?asOq>YDHx4QEoBV2-?{x8Kt!b;?(z33tSsjV#H*>rvDO5&7<}DnR=Bmaa zT}5MsJnO1!Hud_goTuMajBR0EJ*EOCUQ<1iZs(|xW}Db+rr+jYimIEHE-9)h3YU~( zKUY&xbrxK^KI^}T>dmKM)@JNEE)M21iX-%2m^Cx=7$!*X_vb^7nN5Y*igV)Q-9CD z8+=aB&Bq@xSkWKW-5ERarX1#^95WuJ0dj;IGhVq!(sOvsq%g{3CN+a+q8c-4jPjUC zXOzdx2u69#_!!Mpqr;z}7S-8mbYyTWkB*Uy^5_`Fh2+tZ$taJGEJk^BjAoQa#|ez` z=*VW2N5>e>h)2g*MtO9MW0Xh7ct&}2OkhzwIwms8qhk_RkVi*=(MmNsCNsKLjgBdd z)~eBw!x?Q*qa&BmW;HsdX3(V9bJ|UElPm-T5GPlD$-qeU_N6{EoEAvP~RkMXQl zkK<}^cr<-k#yPOGLs#ML1G;b^^i#Pc!bP_tOf7m^25EWPrVQ7wg>tOvIoVcGhUB3a zWo$wYSUI6AW?_>YLa&r1Fk@=Us>8)aWo65YiciNTGV{kW?L+t;q0u#DAFZ-{G(;r? zxxWT=j7AT?-%~uT=fv1h>8k3QqE*Gga9B8<{i#{Fbl=&EivbP7*)O-AIka~*xj-Bb z7N>_qI4Wx@D#K;LHNi65vIvg`tQm#dX;3j7WuMAq7*in52%`*DHLEL2SFNZh5*ysx zT}MWvvFq0f_iem460YWUbE_lVUvn)-J!sw6++GstxG>h%F5F*dq94SXrWkh1?r$(D z+tq+qcHOtLumI4rgnI|0xfCm(Lhf%eDUUc5=?*5%BrbU)g`STc!hI)4RLRG=))nzqe3?XDj8cRTR(TZSERaMbhVjQ8x3La1J z>gr%sNpMB!s$hwjKm=tanyA1tsm_xKW`lSx!PtgL*;5HwZDP|1qm@`qX?ale$);ak zRDnUpJ7L|*~7^$ejHbd;TMFmU370bVXb(+{?@g!-FOB%^Dxt@@e;uT`A0?Mjk z2-_!NymeF!D?UsSR*_q+=bB(q?C~CE+7+~ zp6lMhARULDfV|1%x!%%oc)w2Gd~2e;gy)7Az&7b5tVeLzQH<9uCWLXRiSApeJ8lh< zV&OOj!YEf4vP=eD1Sq}db_bF>!Wh1=6?%WfE+aC#_9)TNa6&2-}{(oo#if|n&D*u3Lb-TH{Nr|va0Y53fM6jPwGV|1TR zo~-m5k`~+ywTcutxiIM2HH9QaV1UMUPf>F4irGe-W5{Uq%eNtF8nF&7!BJV?$XWlL zvaZ49Icm=vRj%s(9x#$4riW=)yna&{IZ-We1&*!+hH(xQmUo{P<%dzA@CMjEVJOh< z)iiC%cr;#PX=O-g-_^bV1P|HoK^TEP0#H)oncmRZ-i*tiu}HYR9rw(TPlwRDA>oIJ zol;j%2#v-mbsGsJYEIq8W}$75LN_vEUKf z*A=?<#Ae#hYTwYvj;x(^V)8ky-L8>YS-&ccBCYG*`m%Hluccrp4D0Q_x68 zGFUgXH;MEpky2mRB?C|=IVlrK)(ZN z7Y>iik0a(a#NhAb84&za7T5=Z_Pbe=gjhhYlnsJqK^p)n)1q?#%%)dS@~;DQGU|nw z%kBes>c~QZMTkR9XlqHt?-ADpwnZ-j5Q}LVUcxNjG+9%$Ua&44PS2l-S@12H#r#Tu zQ%4n24&rtWwG*`kt)TA*%fjK2`CAb)27@@i7r+GsYzJ^PfCXCsyaZrjB}?k!F#j&Z zOoHWG{y9CX&_qi#EXvAp@zy?KZk8ivCy$h0a9Dzrs{-gbQrgaY>7q}ckSta zEYtUMI`eRUADFMU(*K0gXTmNlmZEh;N*UprwiK{%4NO+Z73dUC3&-Su=4oZ*eheee zMp7h5(@bn%A{7DTDvJ5$!2luC=<&8Rof6*hk)$|1+GM<(xAa>`qD|HD3_+4&B++K7 zJeToBU~P`dDPu35mM0_4sbX0;ytye{C$vQ~foqz=FA~~fg=f$rah=6lPpnJMv{>uI zU|p*4rSnlu?bK^zr2l3-xRx%}Kq>sDq&Ph!YUx}mWRW5*rOQWJF;~Btk_Tx^gW~s7 z%nC!+Z|S!PSxK8CO`D4c0(5UFCGt9)U4=-6X$>mWa0RuO*Wod#xNHq&QK_hYlL}th z-PKA)u1TjZmk~88B0Cu&AK&uny;{YMH{@3Pr9@v@>ZL<8=f$ zYH26cXzdDB*FO=mff8%lX>=VzJ5>%gU@xO?+G!^CV`{rX6N4obEy>u?15P{1HsG|m zO8nCQjR7}gtQ}*J89q~dmkr0Kp!Q^%HnpE4U z@;Yu|>X4o(;?+exEgXdwp=qO`7k4PRR&;y2VrZlh4h9c1Ed4xsRy=|#=%O5b@A)h@ zo5H+k{ygtCnU^HZ@F^WdGcyvJ`(YFn_0Q*F?ofA;u)(1kT>M#Uun8Bk>g%En|H>MS zLZS39cJQ2+&;mbGl_(rmiO2Bx(Z%;ZYbEe=ULBq7|B5Pf@D0&(sS5u`7tC~Z!R)_% zq3nP65}6@yO$f&cWQj23oe@XV5j3}+=XTD$ ziv+5a#$A-s;JX~g+l1M!ZW!w7hJL*38ZOU2kie}S(}-uBlz9S%zsoZL-yUrqzP;ZA zyZ2oBB1ojLagvOG))5Q#Yk9`3Obxx3Di@=C#8S~%Rkul=Mi{d*_aQmXPE&)e4M#`M z;b>2)6<6BY5ZNq@e2(!aV~TM+xEu$t9k?*VvDvBWMCt5Ew2katc#k)e3XK!iRI-)X z&ytLJ9F;5hd~JATjQN>V_hZEhW2LO8p?3J%gufw|H0-4twzP&ZF?i>2u2u=U_6@X1 z`d{&-olDNT)A6D*Kq^@Jeo2i29MLXcn$pfE?h)<%<(lv271IPW>K-9_4vvp3Hh9I4TsvfS;I-ADTNyb-_exnGyo@%uoFo1 z36v53veAsO=4fQSs_2c{5fIy1rl}gRQG5!88>8CnMrtArCa*tGII|cP)3mW46EcUa z96cA4$&fz+u9`8ja+59cyo9?YcFjmU0w{f6eemUjYdmUlu;%R9kCEbl~M%ew-V<(**D@=ma6YoAI;((+E2 z&GJqtTiyw@Ebj_2E$_*wq?LV-?6zuLl}OSam$adlcSK}#+K2Jr}%L?jS92TKu|9*-%DR#-g|sMHfdq@H95 z^+X}5CmBLLQAp~ELZzMvQtC<4EcHYft0&1K)e}LMdLqP9PlQ-~>PZqvJt+#QCxVoEBFIutgh=&7fK5FSYN{uKho~nauzFIUQcnb%>WN@W zJrR;rPlVaj6QQi02(;9bLQM6Pj7qAaJ+j+|t0z-l@?elCQawq4)f2(TP){Pd2%>WL7$dLrDWo@}V4o`_~wPcALofUBwvIDz4-p4upFAykz)BX8gt38hqq zA?qgI2D~#Rv{A%{r7lE7T8D}lBSq{OHmM=vDiR@6kKxoFrBf_N4BDhWD>c_{E~kD9 zTo?4hz-L-cZH{e@$sdsa9N#?{KzCC$>rgs~=;EK(B_WNBhTEKN*^ zrHKh4O)NP`6Dt6kSOL()k_DPr5uk}Bfi$tAkR~QbX<~vbO-zW?#01zhF`=d=CU}S@ zCIV|>1u9KUu&Id&wlpyzNli?cO%oH!nwUUK6D!2j#K|bTCN_DJw8v#v4qYe`m(;`( zU` zG1_Ep4XEbyJ)5U*C#)7f#OO^?wui~YGd&G9FO^I>{1sXbv9u@2@X;%@Tq1slh&YYG zYf?g+N~vE51p}O>gjd74Jh{8k7RfnP%bA+GV>-@84kt5TL}}=E6GhroKw36splNAi zC>W!VbXkkB(1#-^Gm$orBF9e$LBneTDF}VG#9qhUd}83UN%1;%GIdCDOnp+b^Kn@C znI03kav{%vot7StU)D<)Sv`e8k7)AgA!tCP(nz9N)FPX3V;Sx05qs% zfd*9sXi!NY4XP-lK?zbClpsrk5+XGy0X7XvsHs5-9-={sz#3G6N`n$?YEXhL4N6E- zgA!)bpoFppCD78K3NbZkGAgMp_sDJ=zLquRCD*b*Pw*kG^h==G$_&R8q_GFap?H^ate;Rn+D3zyJ>a;E|loPMd=;4(`a^w z!*myGBVOxK*I_86ODpLc5sRJlF4jSC*Lf^%y38W95qB!)K4$iM?g1esDI9*S=s=wA zy>-w9qtq8vf?VFmdp?4eOtNpRuWyD|FN-~m*#pcj9v?|M@Oz(C2i8Ypri-=$Qw=&g@P-TdS?JOpLeyt)+VC$nMmjz8MvI}5xyJP&727E-k8az2Zl0p# zm?1;Q^Tv8Dub3S(+)U4+99x9tm_fxjy*Htw;h2GP!IkZ#1nXU(gXmEI%bHXe4eCZhL5Dn~0mW;tx4INs2^0^p?ToGk zI*%MPsMuPd(lLWVHvpB685G*?VaE&#-Rxn<41|(n1`j)CQ21AXE5{59?**gTi+LmyQ_}x(ldu%%IRdpvp0W!uJu5df&s+`w2(I z?`8aD!cp`47(YNbUMBf2;{$|C#|%o|Vc^O!gTjw!X%FKlj~p|2j&{uOwu-`TO1^<^ z`Cr(_(sy`0!yPjyv3Gkt$8gM`;&$5OEXN8@v&da4)|$SSV+NJDZ&6U?*tYud^`(xPnFvfz@b1A;lEgua;`?TW_m9JcQ z7;{O3syuM;ZETmQ>63vJRJwAa@DmN$4{@{bDXVk zQd0?!>Hi={;&%TBVNgfLyj4HM|G_NKl}@nxKUk)y4l#nd zjCg!BK->zaSc&_@2x_--6F;{9gRet`e+T(LxEIsaW4___V~NreFX{ilR?2+xe?Ym* z(vdR&0sjYz02KuS+V(*vKr4ZOmfFPxs38!bXC7h#^bQEp|ACSLMFWELf1n6ZFd#_( z2a3=u3DW<8BJ7X^>Hk0xc1nWsf1oIRih{ECnI%ya6!uZGD2js8KE{;8ih|JGma!GBqPj3cI#*zHG zwtNLnzgE&vMD^Z#HD2Q(pIz*)AW!ef*bZBYXBE6@3H|DfnGj6#qr9mDjtH*Hpp0qZ zH~baw>!nydC(Wbo51IFs^cy$=D==lK$HR*6GU+#RT&69~`URd2EPOZ~Yc(@1UD?O4 zXyJA};&0~o@x0c=H7R@YTQZa$3s})ZQs2taQ#`{jHtE}0FfKN+e}G}_q~DgY3(e&8 zP{TVtdjMx?^xnw}fLzl+M9NQjrPAdz9s%d4zf$Qk3=%imvRHUhcH)K96R>?`iv@wo zVnGmDEMy3a1%+g>kRdD<6q3b)LS?ZaNLef-&9Yb!#uf|7A}tmKSr!XIEQzu}}n9EF^&}7K%a^3xbrzf}jw#*YdSILZrol0Gq{vP}5>T z@DPgy5!hm(KxMHY*tA#>Y*{P_Nm?ujvso+%Ws3!Ymc>FLro|!|Ww%(EJW1N)vMYz$ ze2Gh1EF{1d3xbbfu^_VD=BwD)VnK*yv5=gm#exvK#e#5~#lnVK77L=;Ef(qFaC;bj zxWbLNt0&xZ=(<=o#ss{5m7pnCRKS)w=0ZPim$7e{qSgkrmDI+nRgM?~AL{stJgJnl zaf+yok+0rXG%CeSyHZ@@8?PeuF)PT$pSf~?L|(^e6BL7EjCJMFS{Yk!N=>A#BUW5k z_}WUTP1=JAH5S+9l-asE7z#&dJ!P5|aLG`k&9rF|&7M#Q3{MFdjEgdGLyVNUb}ns) zx8vQ4@j;kd)-^YE;FU62TA`gs3)%M(H;xp&c0N7fs*vgUlBSOKx)|O8jPfQE*AH%)hAu|F6VD>Fo?<@%YO4a-ioy}RekXt0P%Dtd4{)(_ zCKiGjR(050o=byp!VhzTIgzZbyvQ9#<^&O~Sn=*e(|@Ng;p z{+jgLqb>X%TDAypbWkDIw|4T2b|`+b5&Q6J9Bwyq?xtPkDkLgJNye*J^C(3F`4!Uo zh}t#Uto375>pZ-@VKvKc5_c~ssvY)F*{{sTm(xR!*b%f=2t$T^L{1WuA}yWab|rgO z1?XN!AJ=mPjnb=zv2IqZvoDgYg_jpXvJiobsm*sCK_h6|WE+CF30RtV5arTE7|-(0 zWXzW@5q!?RMolNaW=LxX(~9-)W47YcBh7g#TF&Vy!MCBg3J}mqi~BpW)AwxY42){2H`_7#nhd~At4{oF8Ay-WVUihkZ(P&L>Bxmx9x=zNO84#;ZA7T9iZcyb9M+@7uYPSM^% z{0)Fo=?hev9`sg(TAxJgnmWj@oBEv>y+Jdz#ifBlu)|_D1~1k^k)@;TIL9GrXM>b3 z%dU-}vR_MhT>)aLX!|5Km$5^@MnpTBad_^N1-~}n!@DC|1{FiUwov%3qQDC$Zq8f3 zIiojfU0jB*a)@hFjZ~CIp-rSJju?y5WN69a|5(%v&eee1gpr0J@{*G#xYR<_Q43JnQz{NQ~AA0MUTS{k!wh>m|n#e0$JNcGt~LyX$6M z9!K!805z9hU3zvfTqBGdvvgoeoa-(U2UjJg%jBURl)d5dU^yHWhL;yrmln%?XjQrN z=_&GE=ZqK)9hO3S7SlfFI(Ni;5}qScipYDWbYdbmHLmkG#$$^yfAq_B{s?-54@y6U zHluB=au4eYkC-NfWv7t!KO$VU%oa$oQr0mkH>HMtyvwzY@jPK1x9G0=5obeiDz)-T zR3VL;2ftnFbX}7{ug#7aZuWEaW>EP?*v)>fYbDKci8jofmFMcoxC^Q?MVkFwS7)3I z!PG9&?B}{JgEGcLFJ+k7&vm^N3$tI!P_v)w29EHjSf)GE?B}|X<1%e=HoKkcCXUZe z#@h{duA4c2e2O|^9%}Y;-IDQ5**yU(dPwS9IeJRUaI>FlI}6UmJEF%lkGgKl*o|g# zd#K@kmR-)BaxShe__3tmRV;zZE=LgAgDNZI8i&9ci8 z#&$W$BJFYnS#~)>EV~>bmR*hzvdc*hvdbv|b~y#WE+<)Fms14THSU%Dctj^va!@Gy-&$L zy@Za5q+ev@SZ0cs1hAEx;y1E?X>HY~XRr~8D%^C?^d2T@w)UNSNPb&$1AIWK-)q$F zF*E6i)T=8}@cgt}steCZxa-&;wEIXALb;1flA?XL9zwFhVfnL!Vf+$d8-9UO`=_S8 z1NvyRa}*domPU6(VI%wJy9Cnj5o-S&fT9*BG_(zAVxi^081{9T8M0w3#Bag?r{vkP zzZhOe9Jztzdfn}zp@cVm;Xn&NC8G?ZcyU5AmrQR?E|iH1 z;g#k?$QzGennXN--vnvGM2tC<`r22(rC$r5jUItj-y~WyWwq2rFT`q5nmJ|L%AWz% zexzw-;Nf=t(OW20V4cwJr)PHno%0jwoB-TsJ@5r8@Z|eZ+QVFovvUeTf-fNC{W}Pm z@(d!Mf;XipF9VncuRBxd)$Pjx(eo52vVA7#F zyh3%L>b)wfhk;7tRA~EUXW)l9+apc$@UueZOqEjiLWHn* zJ&|m>%IC;q8s&f&p1T$6NiDGBq6~W^eePtul}@AhUY0~FH?3bA2_e%0SaRg$qbFB` zE3XK^x+wt80PuYR8Ufss1E3SYGXQdP0OX!PUtWC8(sEUv3pvc|0`(m*PHQL831CZd zWd+1k>MfIR2V%8Xv}ygsor8(@{G9;Y6kEZ7w8cmuu``d)%Gx7&Q z3KTLCdu3{VRQvmJ)C_M>cdL@QJ)|Ed;?-re3Ypu%@&naiwaoJ0%tJh!fe|iF#i77w z+Gn=ozC(TN^W4p}Pg8X}>qHg)1qTo2Hq*SisCQ}iqtX6-Y{1w6nLiWbh`fiQ8FDw` z_~I-KNJH*M9MLz3Zn^@=Muc@A$xyoy$HuEbb$Kc%k>wqP%*tp0`^H1JZ#)dTVkB2D z&VuJCi{wVcIhUGA<*7JseoD%w-+D2A@-anP-a{xK+l?f64^eGwZdHc;*o&J=S%e|( zAvU+QF1P=5fRXF}sRL_rGWd{BYh$XPE+5dc9Pan%rvr>>Owow~d^+P!!pSGUk;fF5 z|xRK-Z)X^}A z88`XqeK8zjCig}59}F;V=6Fw16#rm=aSKP8`?O&Wt&LkbCx7Z}%4s{J$NZ51<2HX5 zs$f8`$aa&2T6|=m_^iB+ z_6UC1aA!OPHI4?AbHtNj&XMxE3)-UC`CS-^nmecl=wxL4*82NR_YU&Az!6F znjxDR=BB`ng@$EGQ&iqq-hwAf zMkOZOr@G!Zre)BCG?m`bGZ74_Sk$>ZpTY($p7AHl*0f`L<~NpQ+yD`%uj!fJIF*Ym z0(Sc-+&n{E}mMVqsLsvK^fi zwxWz5AYr=GxF%x>RH&db#YZG?&np(3q*D1SZoXY^s`P_TB#@PTA7T-*NV32Cb${I zC7lg;;Yk>0a}1ubbR1}$!+09TXENJ!nd&zmb4O=voF{8wj;CWVoS%6P3g+@q@iMHR zZJ-}_aP(gZ+DQI!2S-1xnNfBuN39=saP;3I6VtC#8KLrulGSBF;rJz`8>NMzFq>dP zh$J5@TDDe*M%296!(^U{iLPZ|3_Q#3gM93JSQU-VrO0uA!idjm$L!-Nsg2J7MV#>&VS-^bTDO4r5w+d0&-Ws(_FVOkg- zHpG3Q~bo{wpZ|R>Y|MS5p4h5-Rf#QT_*kVw}Vw zBA48=p(uP_yfPBwcEC91r3Y@2$s+Y~QTB0|o+rfLWs$(q3$Z@~K^3QgiZfNVO@!LU zHRCwB$m@GTYu9K*_OoD-R|rgq8Aw%v%WX<#lw_*G)In7|ssV$W>CV~ZvaF_v4i?o3 zQGF1V6Ilgo*5!90`9YAB5jGyVtE^lB9Bq>9X*sWRujrfbn;CL~i`bJIHdB|N+f z+Cn!d`!pI}Vn!jp;FFreGmw5V3>V~$zK=TW!C7YBk5S&Lb9Pe`PE~T@>mOaRX9=bo z+=g>m9;dRb0?JGsSpP(0Rcnfb_5|tWFCxk|Bw>YC{`bvSH-&ak`vxTTaQH0QDIqGq5XxbI(`lnM`-U*wN3*9Taw$rd>u&} zJ6PcCh#;q~x~N9CekSV;c`$5jFUbEq?KkEx*Vms|NQD*&j1XNzHrN7_`QEDy=b$6? zC8(M%zWiA$u)e;Y-s1f{%iqrBo_Ufg|3O*)&;A4F$rEsWr`Cst_!qxDYZ;S1%~o{W z`)v4qUyMoITeMCD9Vz4Rv~c5ihED_uR40N2(TSi8aUw_|oe0VhCxR5xi6DjQM35kL zA}DFri6CKoA}Cqpi6BANi69}?i69}?i69|#A}BfNL{I@Z5mW$91SJbj1Qh`%f|5Wd zf{H>Xf&{4(L4vFkK|z2oix$1Qn=G1PL}z1PQiI1PMu=2oh#H z5hRpP1PQcG1QlYQ2qvTKCxRwVlJ>al%Aq&)iA$acN`OxU2|mV&Ad#sDRgnfKDK?AR+b>LBee(f;QAT5hR-ZM9@PnR>IPARcaS0POJ@ZBDKD`ZCzb+nEb=y z`H-oZ^Y$*Dzn##Ttr)>6IKLT9033H0sws{87c{nq3L+=>5ERgMvH(9TfJY(dF|en$ zq72}eG9HEK$Oi%HIfsyYfT$~Ow7}LDXl7DVhd{%nQ;u)rGeY?4NROwz2}IL;ZG@yN zB*k)*5P_qZx&MGzucND5mHPO}L=_$wx>x~C^_kTF`i?N1chlqc^HiYu+-@JuROOzE zE9j;H|KG=AZ_|X%w6yi6OG1dCT9K0-cGKaz3D9Yk^AV0}9;$R5~9}XuHAA2Nb&5VCMsblJfzBoewDd zE5McW0fqMhSI!3%ehbA*=K~7gLGjZ0fWq$vuAC1jd?#?}d_bYQfJ)~B3he``oDV2` zAK|F?J+fwwoPNSl@p~D6nQ+wnKE@9aE}ajk^aF%T=K~5q3|u)MQ1}teD-WCDe84!` z`M|mq*&=YNDNT7c=L0JB4zDrX`GAVJ+iM)d`GAVsX^*p<2RzLc*rj5v>1#P3P>K77 zMO*2g<@9hqkizGCbekcC&-Y${x=u0A_tFvZX)Cc5>$&gDzlRdqPwkQfSp1x~N>mCa zbh||DP6krg$-rMBCzW7@pQP<3f)uPMGc`(^=Ft~xXX8yz15N~>UvN8giKZrma9vFE zZ>csYr=gR0muXiF;XQRI?`alqdbq5pYGsg?H^G(o(M^xONc%aGj+l)vU#HLuWv;$6 zI_nx#wnbVhqEO}`>Gb6?N2kr@f#FuA6?&U%Jd%)-HC-N%2-p!tYI(ujMMXmYqU+b7 zc#iGz;Cc@P@fbT({?=WL6^bzE(qm_bqINP>H*78s_ys(JE#nQCGn-tBXc*FoK}CDL z^h2|mle?H~xjazK>`~;Tzk-XHKh2Vj`S&Fzjxfm9opgDiWcVdDDdJ-0&a^~e%3i|6 z(Wb_|)TL5qD}v?nKvBmVN4q?r7Q-XOz>D;iq=nZQ@~(y0*L=>+Cf_EF^W%Gzg^L{U)KN6n%r z3QGGJQw}Q%io2UBT@EUYa(Td|;m#l(EE``Fqp%tM!T)OSUEu4gs{HYD?@80srVY1G zQYdf>1tOO8QbH-vmZV8bQ__+)X-UiDCQWW0Hjis^(+5@>X;D#Vc(T5GSh z_S*aGbIv~blzC4IEO|iQz;R&71Hu&k2tV3=J;Gs@Q&4dgT6uk)6aB9G6l6h706{N^ z=H*@j;kV?->?II%@L|{#S^`01^TvgjK+ssU_L`h)AYlCCdbdGH>~X}`SvXWxE_4c( z*H_4*_ks*JnmH0Igzu@1~?NJTX@2!4-uwlvXV#tW&Bh~mv0lEn||wf43& zws+8nts|I#;|mG7pt$Qo$N4a3<7cVclohN`EAi*po;L!Th_bJ>Rfbh&B@SJ-S2iH9TdawC-SzgX3ES?q*IOA z@qA#6YD{9ep`Ai{7F|)B^v4<;8j-Upws3KGi?$un@L*Xe&Y|Xp7jyaYFT{nPNXOM^ z@kCtv;e8>#v^|xga`p$IMPwf75{b-yfOhBWgVO?MFagPhP79DgCB{03;8VO#iV4i) zx~jw%NjjTO>?NghzP6I=FP#R>{O_+!;?bA^YhfeHrn%jg7v^Q+B=a3wsOgw$4{w6 zcO^y{@8+5Dt-IiJ#83@M^S=6Pg83n|yjO|MxMX!zE#?K+)UDfyr9;0Mc@4v~Sj?nq%FVlzz8R6lg_Yn|!fx>xTiV!MrtslO`AD3KLSB*HTs;k1+>yvT^yK?!m z^;bBFyt`)3!(4m5deJ5C(=*G76$Dpc%}7iZ(PyXX@HHviEosIZhIxO@1W^#+!_3IA zasw~#?wQYn5&D6Ayhqc7Z`xL4k;>j`dNC{SGc$j$_{Q>8e$n@z^7hSKt+4TYl@;)u zdv_O~8st-RVUk9CwKs2w5yiPRQ{&{kdsw@9`L$_$OIW`kbuS}JVDns-aEkK|DAn`T zC7AlEY~Gh=(j5pg1l59-`pV3GN?$J@>8r1YKHAG?{+7>7%D-wG9xH0CYokw1J9!V! z`~ugT*wm&v8`Eug;MmFgDxWBVruax{Hy-kL^1e3nW7;0@GC9So$)ztQhskq!_sw)L zxi;QAGYZOFgihYqm2dO1eeaC>c0P(?fl~FlDiT3*OKJyRV~fnL1zx`H!FW8Of5sg^ zPXvt?Az<-iJ=IqlvgVQyvCVl1(Qk&3{B!Rf;}f>hn1H z)J3>^p5QZA@qX%0a3*gdahQ%iIJs?Msi{7m-S@R{BJa{KMRLL4@cvSi{VYVxPi!hkL!}`R_iM*SrZvzT-r)t|`d+?e9)_?`In&PDogHlR*jV0b% zQidaZFBm*%%{wi*j3f_T0!g^rv{j2*Muz$Y;SiS^RY9mLE=6&YtKUn;ci+%r`BPXs zFuK9*JeDC@`}-*IbCT7DXQ=eDEKXzxMe)YVfR&YGZy+Upq%nBCcq>iizK{HK-C~S7 z$U_I1aRPxHx%um0S=0b<7C8t{6DTKgPcen}kxxu>vQSJ;uQ&LyO3#STIty$tBKU9_ zamzZ*kJX=Y9{NUn>XT_ElW9*CTkAJQBj=EnCb(@(gZG{hzs@prUB@*X2)^}tKD~>2 zLg$*wTB8vKd0NSZAn`!i;cMOIg>x#DU}%;18cx>{$+B;G4s ziF~gD8`d!;9CbIVKM>ev}Q!kokSu|8V7Q8OXsNF zlt`p%8lk7o!SQ@>pEfO0;Pak-a^PTwQ4X1!q#{>>z}LQL8nj;wVY5h>=6i}?!2%L< zD)WGjr1I=MslGaUS}_>Ro{ZXb$73CK*Llb52R*@=4mRBr&cEoH@?7 zB6=R&{PyiWw*>OYaEAEo5+}?7&w^Z}>UORn)_jW#kY3+qu;k^kiBzrgjKnCa_3jca zv*6rGiUyG|kBb3SHBBR_;Q6OTE||71vOd4QU?YrQQUK6#=9fAb;ADb!Q5<6?U#X2M z)8T@^A*5YMJcuRnAf}}O1p4rc#xa|P1qjipsKdoUsZ?SSkvPsJ!GeUp)HiRI-uTkG zIN|b1C1p`#PoTR;>LxuNWNr|@j;JyrcH7Kgv1HiD!dcf zNZ(|4%l(K%s6GCk08!5TltptYMyLNDdG52>HPtVZ6~wN0q0u`2-1@ ziIk~E6U+w8>a3-a=j-Z>4>xiz+{p2av$6+xP@A8qJMV&U=RHX}@5w=z6-uvslJv^4 zV6QwS*eg#pQqg(qUYWXWzgM1N+%Pk2&y&TTMSew8|1pbMawmPtaPe?zI04NLhX=KH z>T9{vqSnsgLD6zX;4G{YH)nP5%n2giNvH(v7Y=z0tHhq;#h&l11qNDF*m5Qk!XkXwFi>y1HZt*P{_*o-wNQsH&Bz9u-60fXQU2>xVLix~i_+qzc5X zlf0u>IjyS_8LK!-4 z0-A~i5;C1VGY1znNH{A{40LmK<~!Tei%OppI0Wx=b<`o)q`tZn$QcyD6r`0OCIO8U zJ(P*Y>0wZQI5Uiw%-{tRSZGXS!hd489@!(JT&hl%_$;JrqtJ+mM$tK|9H@z;$2>pK z)CI;klj~@(LH$r5s8v$MurnOn7@+XbBv@0KMNr8Jt-%Z=&=!Jo6-cjS#gmL=v;(Q! z6lr`@g9Ddo!GVhmQdC2cxdmii%q;|C%NYCQfUyxnMS(+9Ie2-3v#01$->EwM=u#w< zZmf%uoOU-7^ic9RM&RTpbap|@jxyIHo|U*$4lub(nMpc8?w|@}KsreeASUZd7nP< zGE#~;AwDqr%IXcYMp~E|Y+f%rc6?J-H-ALp=&^oXH6JUpqOG@VZe`<17 zO|xP`bv{k1jyyZtoZ8&p*fl@XnV#R*+cQ7MG;MoVQ%7HO%JD@22ul%)6C`PVy0>`? zZc{Wl4)oV6ilds_+Pk_kC2cT*qi=U;80h9yi-u{*sZ4LPKIqLfL7!!z!uZ}b*_ z(|sY58FGJhqgUciIpX$a+{p*s-o@_Zmb|F@(!>_@7Z3Ce0RHlXRe+Cf-9P`DrI+G( z|AYY?Keu(&U*X_yCS-8%{jCSDb_+^gd1>gEz}=w=yt;MYqlY$nOWn^!>b)yBx-Z>0 zu<7sIL%TBW6Hdue+_;bCm*l$zHvx*ceXDMEC%%4V)rU6p^=;UyPPXK?yFYeXytAtM zUU>Sq-g&>=>wbDyCi%nE5--uycH5&5xm&zd?uyqNuluAsai4dlH{acS%$@oC{~dI{ zrMJeeQ(F#!U;{2`$0H=s3jfa@aBITu#Aze39%Var=-zD^9ULc1GK9 zzoH4RMB}~-F?vI3^ws0n=mbSPqOhYEFJfqQ-cfW1S_3X*qDNI1q`{xU&Yl zd7Ipi?b`32*0OhKlUrEtZa>oZ*zWW0aC;BJSMJG?s0-`=0wto(ckp|ho;X4EHZ6Vh zZce{HD_JObC7 zt3p(T0ja{YNMz}=k)_cH6d!xYZ_jMc1lkTg_!z}2t$!(N{6)GGJhX#HG1}<{G%6nK zAi@!3XMg$nw>u|NUw&xiro`Z*y&E?@wQ19ar5msA!`~*iZ@?`$_{xtPILeED0Wg5|m8qJu@Lt_m2$cv7PKx%!bsn`rIXpuHG zw4h;%Nm3YSsI+uy83B&_&-kd0JOB0T9<5r^>6R^a4?Fc2^tmUMxL@A2&-;P<4^BOx zgVD2Q52fRt9u7`Uw!RQce>j$OD26=V=|jEMSGF#_va0!VciSrN^WE5yO>WnIcS`+l z?{7Vi_>A^pnE@#Chi9Z@0i>2`cI#B*LjQGY2LButUoJ}1->(bFmxyu zqt2^<{>MZle~tweqsK$60V&5)S-cFDMl78asebI5{^r$fS8rUhW!ly$e|3+0YP~lz zdg%=JdavF+$&2@4nECtP_qhcFeIM;p`KcZSvDhPikJD<7`K|z2AN`c9kMB;4OjjLk znaUC8;Pi3wK0%|3|AHJ5e1u6SiLF?%s->5Gqxy3V4|_Qh%qn(Xm{Uf^bkL+C?&U3R zdA)nN7vJQ);_Y#dIo_(nXpNt8XO*~rz00fjezw=U3G$4)XIH&9_kC`kH`PnL;oaf>ljH4kCmwvvo#EZ&PC8ia&UxM4 zyszAyP~vX8>0-BVF;YsUd&-e7?si-1-T3oM+*ro_#;#-Ttmm)X>(0z9aVKQlt=`ln zmtV5_Hn+u_x^%A_TfD@blyNtBi?3{TPt7d3%{_?Ap`N}f_d}6`QM$IhOSS61*|=cgFl5*O&k9nX6lWf7PSsuipCT`|2yOC(_;{ z?&QU8Z@oL^VB045hE*%wg8KR1^{XHKnOD>aG0Xn_qfc+#wEKG$3)@N-{%-3JS3h_y zlJXMJ(gk3CCV$(N9dFNnQ6=>)#|XE;oA&e%v8nUVt6#TwpF4Hc-pl&-s@%N^kvg^u zxWIBFoIPYI5L_-!U!aD#iO~(H*>BB5ik`+w$2tgJxaHmIB|7`x}SHJhV-?wff zC+xsa^bq}QxUMhdZXI|-xdzwrCp|yyjeBCzDD0)5(0uSOXFDgfq5x_eNPEMkMrtnd zDv`S&a^HX6w#kj}bDNKR>H6Kf+cqRNyOZnP%)TXM6_K^SJ>ocXi8?5N5kEJaU!=o;|=w-ZTzIWeHGHi4?p03byv&Ht><0i##XsK z`+s`bk_+ZnKeMf;cXgYa+3&_~x_0vd_mov``?0^@y2&l@rnDY;9wsK| zT&XzHJ7dwZadc`@iXg@y->lQ^?Td$lyfBqc& z&u^W-1ix3dp2#`H5CrQXJdS%B^FN#ngCsx>yktBvO;8STs#G~>zGv{e?C zMJozDXP!QE8u!lDnl z<%RK^^U4d0_lzqqOzh6TqVO;#7^4#l6Tm%=lTU!^$@0S3Q_BjyXIJ9>h1x{V1JldY z@fjKoJrkRtreBYv!<-+^E_1=B2z8Q~vH6DYI@D`b!5ZQYdoZ2D(=F{x2SxW#y>`2> zSj)u1A|Ox;?}=pv-E{PLVXXWKG85C29waX<(>4M8aDJm#lVqlf?oiM+Tzv@t3g~58 zC{IyqdcqH}+#o)e+)|WFV1zC+8ed>OsNU`<1;@uHqGpBOAe^R}@5#_+T|?sl0st)#dWT#$9D$ z&DFyMT@{?w!TjVyuE>dM3;Mez+8A*76$RTuM;im~UtSPh6F5YpDGwbEZx@RDN6?1k zGLGiMX{#)3xIyem=lkPj3O`BxIu6-`@bbyIml!{SJ<`z)!x&^$!LWWKf7TN_pgilt*r+JhCUhyl~O(@s))G z5j5LHz@QNpBbCIFN{Wz5V$UL-d}mcb^gAP*#`1m?hoql;aw3oO7xepJv|@68&F=g? z<8IEo)m=65@$x6ipIr8AIkN0iq4u4tJ&`^7$H7kLlmWs+D(YAJo$#_~XAR@Ye}tFS zG-{deb4OT2MnVH_A#IED&)Pp&Me0^)HbpC`~zp42U~6lIB@EQPs9 zar4_(qM4i5ih>ooUGsU0KPo3HT+#|ww4pt3Ak220kXgUK40wr*{)1$%o5@~# zC|-7tL(`9TO)M-121YA_(PD@a@2M3qTrmt6hvAA~xLEm9+IZkK5C6npmTr97@K^P$ zVf&$}sBO6TC;TmVr^>&eVLrprlieNxy$tx(bECk)ZfR1E{7UC#F|r06(-yLu>WR2t zqU45+AB zY}vDcev;yfzE`8~kSVEG*JaJ?N4sszOq@kukE zT_f{Bmtut#vi((r&I&A@GRS|#U*1=|+wfO$g>0s}*_8#+72Me=50ZVToV*6MpEp!i$FIi}5~)w zR|Vvo2ebx;S&3gW<)t~)Hv-I(#QGf8@$o+q(5bGzs45+JbOY+PboW4zCREGn<@g9j z5)0*K+VOTU)auFfrIV=k7XR@8Hcw+Zom3y&O(ykizs>m4WtYPX?S;Nx5mo{puwpI5 z5csSWKIEJBZxpe5*`Lu6an(3Fxi=Yp4vLs8Y+*Dax~ztm;EZPKAuMpo~Mb7Q6DB-+e7<_fDq z-D%#oF4frE-Q_48RV`Refpw&FHFWTUE_YO@Rhh9mbDu+B8Ek9pYVJt&IN_yeBv`F> zknM$$-kx5*hTgm$iGt3CEZB<$G}M|CX<11li-1-~qP39FwD57k^qM+eBCG-ri!?Uj zIWN3!-i~+T)5=ej;+(9{zqT9Bw3e-YNt_g^3>?u48fwA1z*L|fF^<_UbYM&WU`ZHFB>sAnV*GU)Fb7;5G{(FpvS!6gKy z*?8KBPT+cMrqoVD4-fYLPPcUD#@*LiQzV0Jl$ zG-Wh2KUc|YqJAd2iT6}#fp;5ROyE5RS0wPw1{W8Y*4L&D{E7wsn877{I8W1&HzQFw z;5}K}WjN2^iUl5LaB+cYJrmkcwn$*l;9>&D49*ky3yf3BXg20oH2wz9p+ud;;9-U* z@%44YsS)rDM&Wy810OC^Y$h=KQ+OXZC8&FStrCMqw1z|h5gJtBUs;ievrfQcj2h=` zcP==0P!2^eP-g1`)H~7RA$H@peRtZr9^!M~@M+SXz$<)X)rtl^TsK}xxfml%|CCXRs2E=lvCw23(o zGa6xjrGmnoJe|#(aHfQY#3QtV6m4MrpA1g)1EfZbaE@kd$mebg z&Xty%DD&aj(P>nvln(1trM=?v@x5e*iTa!(3*i zZ>!UGiLY0UfRbS%&IVi923^ejO5G(gCmQVsvx^7M84eoS$cnV`-gVLuD;N&2d)4|n zC`XxH;P3kJzbzr~_YBVJLZ#dhra`p7JtzlKFo&~`GW~M_-U9#H;1UA=#^5X+q}(e^ zqjZo1DVReCF&-CFb`W?bpQMgP;JCqg0+$$ELSVVaLU!fT)^09ikXfyBj4&it*Dpm3 zi41e(jFVvK0^XA{0xvMQn7|7Su1H{-9HLDPsN~=}jU#In34Fc5#RP6JI8WeDFitU) zg8@TWB=BB?iwXQmgYyKwE69*xeuu*?TjQsf&a?jJb@nw7M6q08^V~ta?6gi;nUXcB*wtc0;YUat%$tGpt3nk zXGF12QX`;|zqcW~SS=%@(IEQ>C_V@~03`%(a%AjoCR+_STZ?t)Dw0Uo|d2bY6 zvX@w@WJJ`tU{K%{J}xmRun0zL5isMET`(x{4U7YsfZqv_2`oC(s8HaTA2JsV3M>^N zI)N(#bOIaa*9a&V;8ZbzKjarp3<|v0$6YWeutaLELF@Tk9jwf#Hq=zW3LmxhYYa+e z0F{8x8miwh=&}x=67VD+wN`4h(MQ#6Wl*L?P*CbKV5pe8zZ0LI!WgQaz~W~lNb#@8 zB{G3UFvtWP$yh_I%)Pv)%qH-C1{V|feuFC#__GEV7x;4qS1j-s3@#z?HyMYNbJUT8 zZv_Yie%#=S1%ATd;sQTua76;k)gk3SfsYzGPvHCb;!P>zJB0z!_%Xj=V(*sSfh#veAv)=0?*^lPbtIa{he594`X0Vddi^26(xT;>-hv6f&pB+^GPsz)Lk8yw+{unp3d%tjBS}GlyA3WOaN6LC1%9u=#RaCNW@rPy zB7yr1E+(*Cp@Gg5_(i5u3TigyS6u!%Mj=oH6ul8B0`6c|pt^xU;XXn*J>v6TE1=XB z!)^f$@3l5>$#=fuqW4F9-t_{C^U-|?C}JZ{y@28YPzh)>sJAt!^F=f8ChyPkZBip( zgOA!EjQ+-;9%4`~Q83&Q&=_+=wzwfii2l?Q{|n=O$@_?Nt;i7}xjO8ZS%H7yJq3%v z#|$neu#8jm;|Wk~j~e#wmj{)$mlQf`LLWj#?+z+zwZ_c|9bOkcvF4P*jd6(GBo;XXqq z;En*y%1rZN-iu(@xPFN>?`GY};4;J|5SSR-0 zXi#F?-3BFg6r&*pNu7VfIbI5@> zDo0Mt;n!+$h8Puotrl&hj)e17W1gzyK^+z~IRSB~;n_ z<16(J7$;c5#ly>%Q!@JsjkDFNV1$swoSx~oN4>;cFL8E{bLLq^gEH{A(U)UIi^!3i zhq;nxKNtT1?&D z49*jH7UPrv5l!Dope;vp711wh3UxKjpudZA@i_ro2z<7| z#RQgnJFsIyV3`*t+X`G`%KGfqcnSPhrd&+m2&X`@vkw~_y`--; z8PX8HZ2d*%AoGW<1eD@A4D%>czu=d$0``e45<6gj%M^d~nON2pIX`BST=`0_A*Y*~ zdjc;sxP-tL8=Pg0GCo%xpb>bP!Nmk#VQ@tPH!@D8AUW6^AQZUC;9>$d8=NQbhl32| z;3I~xNZ^keTuk6w4Q|-lu45YbUO>?Y$x74^jydwzR%T#sELh<%z$7vhP_fOpPx2nP zn85NN8*oJe-)`vQ0^ezH#RBK^SO^|C>d3)(MuK6nz@EXy1)gAVMFLMWxR}5(gYyKQ z#W*Ec4o)$I#RAKOHI#`9Ec2RFV}VaIWn%)LZg7@I#me`wRp3zprOs&01W55|iL ze379`2)xkXVgi>LoG0)v3@(vfn^k=75btwb>B&=)%YBk{0t)9GMi)Um+Ef9IYu4KvD=w%V&)PaW{}vTs_+#nTj~K_(DznUC5i93J*jH3Ay> za<#103;c2+)yNI331CwhR62o%UnH@9hEN~0UL)aemZ`{bEp+qRKBqw4h za61!`x#jO=k3<4@!T%BJn20qXG$9zUL0*b{D zjy9v3Y(}p!;@@~r5i0QS3@#?Hq$AKJ1eQ4{;6|K}k|_)-E3iyBP+5Ux8UZ*@;9EH_ zQQ6_@aI&BL)(I#q(V}INL^$PWuK9^~PV;}(u z>QbNMIsupZs2Tx{D(gg*4xegWwkkPB|#~h|7PQ_dn*n+y(wOKK7e&7K1;x{1EeNXF2lt z!i#*ICC(9g$^HFIccSRe;|98j_iK4Cci804T=rc#x#OL!?}_HOm-YE9@3ZedX3HN< z??0DbCU6dL{5{NjnZ3#8FI|M>aLGZ^75usM+2#MMk4swGJ5msG5&r-5w&S!${Es7r zM9Wo3#ECoZFtPm+l!)P9(KuL{B~2^{laGJbY3ylLvoc-~(}V*x!=h>E=nnkH@$Z-F zNoDlPafap|oNvItmIc6}d5YQiH#A?z5w$Nv^E5EDX&PFDh*%f-7&`Y4_@_5|sgw>< z8oqu*VW?zD2Ua|3-sU{*W2h93*XbQxT?#a6U6p_GX>=*a`GvvY8&s&4+Mpz?`Wu{+ z#~d}jq!~*fX;A5s%km|gd*yOU*DF%YCCsj5yJ0jAXgAV^--(6*P)XX*KoQWa#P8HF zO^>0WhT=xf2%VRMKLH>w)4v;`U#ekvqmgwSsF7&oer5sa+{lY_;fF929G%XrCn=h0 zZogr&c}zpG=tim`k|H3yUCcCO6*rQ=FQ=#g*$SqaqG-zaC_n(PjgyIL2P%sLL5Y#-*di7+FQN9lJ_O zBKd+mpnYKziOy?4t#$5f+>%OeZENmGrhB?ONpotI#7yfBa+ZkxHYu_rCU?jGejw^X(eFYnv_lGl)s5JXzov2Bk(0MrjoiJ zouK3B#CedkvNvjR)XsE^`xXeOhT)C8Oz%NxFOxOxjamW4zHS9!UlFy`o%$7BcUb_- zj@}bh_cF-R(K~$I?><}V{v@b#*ZuwPpzhN^Gg{s6_UrC{rwtghZHEnY-Q$QugAYO< zB0N%-?st;O?aj$Xtgs8D%Bxs#3YZ&oU#T%v`co*C_Dk6@b{}ZM8PaZF#4W6p^h7mW z+Kt2jg*RzC)bo*b-3ax*;Z52O%?#zPggym#SBeUWREZ%0{Ar z>4hyxa3jU|4aW!b*+lg+vZR#WGfnxTk!T=m?xszfDnX-Vh3!Y2N{FVsyu55A8ddko za^K6U?o`@rTA#{I4L}X2Gf`7}Z#+k0{wX+p0ii=1wf6`8n7`Xr8r0OoQol+bcO< zwY^afn*e&G9+vXPwJ5FI&YPgN#Zm7`eWva`m)e4Wq281FOx=490h1NaJnsD(&T#MP ze+UpLf4dhv`njd#YJ<{tG!50AYKKCBP1+9GhQ<_bBphEvDs86$Flm~ThWnjcabCBb z9DH~bw;eQe){W%ocU1gTRZygx*a+*4Qz|yjJzrwuKClb7L8779sDd)OFW5;aYa_om z06UuB>mWh<{a2v2^&y`=f`9E(iX^h8*`!bT9#A~GP^*BNFCuDMx`rEIpGIvlis&%# zLqg+^Ky)dx>U1NPA@On?$J)yliSOk!PL1Z}0nlhKlaIoiWXL^0YcCf83P(7Vpw|7& z1>(W|!+P*Z--Fwzn6;4yNuSX?SPnkggHM9mHZ6JZ75r-tt^^HfZ#MDZkAc!2418ab z$)v>{P~IV5nDPQ0k1zUBXgFUGKeFN0g<`|Qz>rtM8?}PPU^3c>C?7Q1K2>1`IFh>m z5wNa%;JcCm>Z6dQ>yEK;j=E#nN_>kFEe=CCz8dAL0AsNyz>j=jw&SrFMS`}NDKC)p z?{@-0cFH*h;2cHcpV6XsA#P6Uv1lvUoh)MfJz2iPxBL+w9|Wjx>I0J)kZxp7IB75; zMfhRBqeb{tz6X;ifxoP+0jOE1l4< zz6~j}g*Ry_=Yvk$C;YKZp{BWDZJ*pNh3NhOnmCj(vptjHnFnx2MYv)$8<@i(%sIf6 z;os1ZKNE0hxWyUo(0uDDiktjMi%S53!nyMpduIsem8{4Rk%l&Daip_uadSiG=|K96 zhXGTpxe=lX_vUitTLTF+d~+jkQ;v-y;hu7dgr_k zM)<&)JHDE_;l^;Z4b6$n^wzvkMHlpIXRj#(=5Q17ISy#788atB3%_dP-fioO+ zw7j_fkUWz~t1LsMK$hF5Jm2z8{9Xn}Xulgh1kxk?icMrcYS((6P0s2))0ETE$TU@( zNS{$?%Bd|5M?*3wHr|8FHl4BQp>CoMZxkCzgr4pz<#p#U4P}Y%!RhSN@JSqrFE)ct z`+`4innig9{Hc90dOKS=+-@3=@|Tx)=k-TwAS4KWpwKpMywyq)Q(B zhVManQX;64z8;)BOIr7Z5J}pHH)`E+{EybUi=d2-goU8SU)H9s3m`$a+##IJ-Ewb0 zQ5`MjYqP>C*_*>!$Zpw7-I%=QHzzH&Huff91LgAdYmu@in1QB8Grz5X(Dg+Hidn zzIDpJP&E6AW*SF=!aN0x?=L?Rv~-FDx_>%PQOeKQBEfEL(k~A|L;OM3iz33`%NXEQ zV05&U`sW0YXrcQqI$Gx9RCo+Pv=l8LyH29zIrx(94Td+0mjCdhr2@9GH_C}+NLEOj z(E0s#M*uuUR6qVliYU70Qigvx5qu5K*wxo>VWAFVVZ$C5W;+bN+Ca+QuhHf5W+kLOd9_xNBJ?Y>qWkxd*ovu z)B2o8==I{TvySI_Wuf4Y#52X2j_2(-eR`0@k+#zh0w@ceVcr}Y#eCy?B<8J`pG67&B`yxyiK1TcMw4|`mYFj0>~^}UYu7lwp{$J};br`f6baD~%woo&PiVPh~K0j3OR6lXsUwayfWe-Ev*dJw)^_e-gJnxZLKVUsxYrAM|? zsD(Beq0#7D$6-8lo(?1qp92k5Pv092`-12w4o|;H^3Mji&GswB;R?it&Oem(?2Y2^ zjfBMEPhq=oy{H7mVHwb)#o^hQ2hure21?lCC=TE6$Kgs_8DJ<5%iu2^hX;TmE0|5< zuoU{}IK<7;PR#w8j>z{Zt)E9)bpZ6m7Jy?(vyaTf8RnD6rIMOTPG1UB1W zTLNb_DETLi!_i`OG=EWB9s-l$+Op{Lvc!*LN%zMRzAUGtorWNDFW!&Fid5vdg1IOI ze}yom9nc_zSvVDkjN!Y$W0O8)NvEfDLb6K9A0f=b*U(r`g!Ef2>7|x*%C=$YLnlZ& zjUhvvFQO$dLYUI&mh|^n(q9>q-*2&`&$Fb{>vti277kd_UmKJ3J1yz-d~ZlrX{9Co z8B6+`W0L-+C4CZ7MObe%a?j4rjo2|Ngmh_@ANx$EcPBWOHnwDN`N&ll2 zb@4GtKVV7UX-Usm(q~(BFCLThXD#XUPExq;`z`6$ThbF_l1}5pkgSW|vZTLZN&kW+ zebJbtzhp^&&XWGDCH*E#dfAwyzhz0M&l-fRQ98+LaYroaE5{`LIZHaN4;z+#$f|qV zl3p_==|?T;hb-w2Thd!B>GflhKFP{;rIzLCJ&cew7QSXlZy1yGSFF0fYSsOiRrgO@ z(%Z%){Z&i)8d_Sxfp8mh|nG^zCDke#DZ#-;#d6C4GY>y?;#7 zU$&&bWJ!O{lKv4(`YmIUe!C^T(vnVdx)5i^{0k3SecZs9q(5Rwztxhy$C93~>VD^# zq(5v)-(yMNX-O}(qz{cr`W{RATub_FOZrWgV9BM(j6<) z&bBfwEvgxgx*u559~qPMyREv{S#__r>i&{t`NLz9K43{-Y)LP*r0=(+9~qPMm}U9J zmgQ+?J8bzsT9!XLCh3Q*y5DWp{dTMFm6r4u#w6Xd>ORk^JFR3AuKUj{=`W8-`V&^& z@3-oHw^jFQOZqEgl77sRe$0~ok|q6ZS1ZP*c z?$;n%hO4{Gs{J?Ct8}r%YStZ0svg(tqDqPI;b|_OF6|;h&s&B!t6s-7cTsOgo#-qY zmeP!}@{V8@My*`;W_&C&Cv}!|S`juRtMoZb`Y}vzGmXsK%o&UHxt8>umUNoA4(YS- zW$~AP578Tw^kPf;9!vU8OZw}U^w^lBS6b2!S<)Z2q~B^;zGzI+J1pswO#adH*rj=q zY|C%5qAorr>1~$uJWKjpR^3-x(u>C=J#IC-Lg*ILr+Ea?N52Fxl zU$vy4Zqw?2liwJ~fZ72E~me{MF zdW36OqqBeYXY9jur>9YetGit5{WsRDbP{Z*>jmd#ZBmQrGJYQ68a6Gl5usMqwb^~Jz4ZM|H&ddfUsgx6Rns;PwkOq;7Dw>h~=TWGUx5L z1w*5lJ?v#oa|Bj zSEj{r%HmWi&U}6j8W{uVQhx$QuHQB06l7wV`@);89ou?8&Gk!*CFML2IPwx0O-I#c-uV1`09?F42~2y-(q^mHe7EbDG6h4=w0 zV3JLGb&FU$SoZ^J7Qs)2zQwK21fC*cp4j9Q}s0CT9*>P5)l(twBk22G`l9j+1JJa3W=R(qV0#g*S z*oO(@^8w)eH89PgQu~1k>vIU0H$pUYAG-{twe-$ZXH$9y;zvEV6K7xi18C&QG#wki z0%i!M$dnpG&$%`O#0g+J8#@qX0OLWco&lONzZOY)p=foT@;mX+d@clyj8Zh_a$sc4 zrZF@Mrp-vd9vGSP)HFMQ3AbFj3n62EP4lP4~&d1G|fK&b1Y=BUjXwgPU@N} zJz%`JUoXPU049yS(Qqy>^}vuw&3Pd(_lNkb1*SMeLvPH>lY6>U2AJFZQjMGOG6qWM zy906N{2|a7S;-{cdrl@n6^zw8KoiF72j*6vGo5<|7#Xi>>HiE&1J2Nq#=NEYlm%Kr z0Um^G2wCGadNeX*=L>+@;iXn8pvjFu~@6gCo|WvvHhdx&!vFbz0w?A#BGjDK{g zTY;H`Ok(_X7ceF^@P?X7tm$}A`qx1tb7)bgwj-4yf68pL=KOuokUx!2Uj}9X7&;$y zT6$9{%CrsfAm?9!=B-df{SlbMp?Z0k7@ilRnaxwhrWOlB9k z&F7n-sRn3dy#&m);HP!&ZEx*rL>4~~D)n>FJmS|2#Ll09q0Q7QHVNyuglJ9&MrMSf z4wUI?>P$N?#Dn@Q0!?Me&Q}8SYDmM)!0ZfRwgD6N*9U=_9g4BrfXReP(VNP&nSSRn zU>*+9{0JC%-VZ0Ry#h>Li1Y7&xieJLLJYy;pw-rB=}9#<Nx zp4YP00CS5fr9JI9*8roRUlk9w1M`UQW$<)%1M{$N!4op#8A}ZO^+1(6Z^n=Fa-q%4x7>XwP$NPtP0r8EH&U1k2_v=nH7XtH0TsRY^ z5}0R0Ijn4hR)Q9xB6PQW9 zEEILV2+Yn9=22kkaK`ZY0WgO`H2(}tS%~KU0kb$n^A<3)k+tX_nHUilkBc>AWnjwT zT2{-p9;`lu2={4l$~hgS=J~COF!O++&3L)e!mI}-p+stIfFt7Tuw({WSh|d|l1EL36-N(?;IK0Q1#-4aYos)4?(wy4d*P3kXY3yoE^~zy; zS4+3Rjhi?3q_)aYM>}2>;zBJw^jrcT&?taGx+Gwb+2Xx%wN__)*Ve|4_U0Oh>r7=* zJu4f#nmbZG4%Qb)Hl@=^T5=0rcwqm7%xLaamDIlznNZ zt+6-R)RgJ&ajtIfS{*(oi}i0)OOFQ%$?93OiER%%|7&KGBGTLGo zsqg4gmxRrvvpH1NNA)^-QmyJ#=Z<7YQ+L-^ZG&WUstM^hneN6w7FI*&6*|^7=4L4- zuU)<}iS@0zdy;KzY&k>Hk}1J%gAK6|R;py-1*N46om6LEQom41kbccR+1k~YOl@yU zr8Di_T^7Hd#`fNntfvJpuJ29ttj6kE%X_GfS~;x4)CV-bcL#J&irzEV8sbo8y(BJA zyL)!PVcTo5{0e0CI>~gZ{lY~HlRbT1nfA^U$|1_Igl3OJic?ic@k=gok{c+(uuNuE zCjw?!BZd;m742QkHOrY-*5R@pYbc6E!7EZ3rd!e7Q{LQ+g)bnSwKpd#x}irFr{&vI zO->RtHOm9Ct9sXTcTu$(H+Q6}x+?m5dQx2(Md0&Ib@g>7+dGvdI@&k)H1_OB(lb9s za%(D+?CjlYRzh?_M_9Vy;!@N-+1#CM?daazi1`QDhRPcZHIQD1Ow|q(-H>X=SuAhU z2i6o70w+htqgZFUBh`s&fg?M#wYR0Qy`!%u+X%D^-$4t1n4FmWnAl-_+~K>10QHFX@rowy@L? zG&VQ;48jGuX=Ty(AOg3htRl&}>RP&r-Q0+&wcxT<=aW>-dqVEI^=s;?RxeN1)Gl9N zc~x@V^6IN9lGRnUbr@$R$;%WXoVluyXUiF@ukn-6e={`4@0L_gSE}Q}1<6L}sAH5I zqrW|(m?bOgu38u7%_BA~NKXN3cwMGrLp!o%W5@cgZDXaq+@8$bYyya`?`}Y-91gz9+4H&y{ehBAXWq+4Yl;xL&2)!Z)}3z@IiZ1uTrQN z0iNt`Ar+gpP=w-jR_%c9&B>O&E~!?sv8l7UqYJ#lC1}B$9z+27th4bwNT0oZn|oCS zl3Pr7Xj$zrqMvw_Y4oU;eX+JLg+wQ8+Oyas8#{Yj zk#W%}8WMfQqMf3zr;IO1S=G_P!_-G6JJJ=Ma2xt;In&+Ij1->E1kyLhB&VjjHoCB^ zLOV@m7**5L-Gn>{TwO;m&`7a;DW?v39D$ih@o9*_!-LsXNLD0!)2XKRmiDHA$Prq} z@->yPEW))K*{CnQ0=}XyV0l+YSxVg0mTF9g{Hhz42{^V8jf4Cakc%aI0+q<1v*CEe zI3tB!|AMgRi_%a=5VmKewsV-oKsBsbw@#S^{bO=7I!JBqipF#X`I>Vz z2+%jEejc4gYZqmA74UF)JK6=>pb9X=N^dus52XY2?9I-wIYpa>EW-nJh^Q*B<129O zBA%CiCrK0mg6>(OqmFu4_FWnyNp^tBmts{iAYWD`lNEO6Otz-fz!D2ZqVqv~HRsC3 z)GStaH}`d<^x&1!H-){Hf|CKqhIw$0-KcC&@uX(XlIZD`MYlFJbs%A&1JxGgsAyu& zx$3KpmfQK{5TyCkc8FsMDo6FHNXDh5M0QgkvUOTjpBZ8;Q6Vb{XtC(20z*@k+HzzB zj#^3)W;B(<`aC13S?4fus5d}vXZ2M6tV#8t)4&x%6QUR6G8!5yefZ)|AMm{j$%B$1 zyK39Iw;@UT!NZ|L_jQxu(5Jdo`NJoxxrOb~8VIJ53K3Jz@VcML(d^~&j;n?GKnr|< z4ad}ir0>b_z!jDF-Alz1lnL9Gfc zB|_H)O-RkB%P6RwuBt-)QU?Zxsh(s@M`NoVdSN`ar8lz$*DDa4m3q|tM|KlztLj1s zqxDj5t<~4`dSq-I;Ezhe14A;SVmIsnP4}g?+RC0hA)~9B6{n`Z!oai{ql1u*`DT(X zsi)#c8uX!2SpDnp7Ycd^#Jtr+dw9@Gx*OA&;g_@n2{r#xLb@LRLPCX!x@|?Z=4(K{ H%=`ZUgl. -// -// ------------------------------------------ -// -// v2.1 - Add universal 8/16 bit mode. -// - -module sdram -( - input init, // reset to initialize RAM - input clk, // clock ~100MHz - // - // SDRAM_* - signals to the MT48LC16M16 chip - inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus - output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus - output reg SDRAM_DQML, // two byte masks - output reg SDRAM_DQMH, // - output reg [1:0] SDRAM_BA, // two banks - output SDRAM_nCS, // a single chip select - output SDRAM_nWE, // write enable - output SDRAM_nRAS, // row address select - output SDRAM_nCAS, // columns address select - output SDRAM_CKE, // clock enable - // - input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte, - // 8bit mode: 2'b00 - use addr[0] to decide which byte to write - // Ignored while reading. - // - input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations. - output [15:0] dout, // data output to cpu - input [15:0] din, // data input from cpu - input we, // cpu requests write - input rd, // cpu requests read - output reg ready // dout is valid. Ready to accept new read/write. -); - -assign SDRAM_nCS = command[3]; -assign SDRAM_nRAS = command[2]; -assign SDRAM_nCAS = command[1]; -assign SDRAM_nWE = command[0]; -assign SDRAM_CKE = cke; - -// no burst configured -localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 -localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved -localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz -localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed -localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write -localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; - -localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz -localparam cycles_per_refresh = 14'd186; // (64000*24)/8192-1 Calc'd as (64ms @ 24MHz)/8192 rose -localparam startup_refresh_max = 14'b11111111111111; - -// SDRAM commands -localparam CMD_INHIBIT = 4'b1111; -localparam CMD_NOP = 4'b0111; -localparam CMD_ACTIVE = 4'b0011; -localparam CMD_READ = 4'b0101; -localparam CMD_WRITE = 4'b0100; -localparam CMD_BURST_TERMINATE = 4'b0110; -localparam CMD_PRECHARGE = 4'b0010; -localparam CMD_AUTO_REFRESH = 4'b0001; -localparam CMD_LOAD_MODE = 4'b0000; - -reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles; -reg [3:0] command = CMD_INHIBIT; -reg cke = 0; -reg [24:0] save_addr; -reg [15:0] data; - -assign dout = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]}; -typedef enum -{ - STATE_STARTUP, - STATE_OPEN_1, - STATE_WRITE, - STATE_READ, - STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3, - STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7 -} state_t; - -state_t state = STATE_STARTUP; - -always @(posedge clk) begin - reg old_we, old_rd; - reg [CAS_LATENCY:0] data_ready_delay; - - reg [15:0] new_data; - reg [1:0] new_wtbt; - reg new_we; - reg new_rd; - reg save_we = 1; - - - command <= CMD_NOP; - refresh_count <= refresh_count+1'b1; - - data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]}; - - if(data_ready_delay[0]) data <= SDRAM_DQ; - - case(state) - STATE_STARTUP: begin - //------------------------------------------------------------------------ - //-- This is the initial startup state, where we wait for at least 100us - //-- before starting the start sequence - //-- - //-- The initialisation is sequence is - //-- * de-assert SDRAM_CKE - //-- * 100us wait, - //-- * assert SDRAM_CKE - //-- * wait at least one cycle, - //-- * PRECHARGE - //-- * wait 2 cycles - //-- * REFRESH, - //-- * tREF wait - //-- * REFRESH, - //-- * tREF wait - //-- * LOAD_MODE_REG - //-- * 2 cycles wait - //------------------------------------------------------------------------ - cke <= 1; - SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; - SDRAM_DQML <= 1; - SDRAM_DQMH <= 1; - SDRAM_A <= 0; - SDRAM_BA <= 0; - - // All the commands during the startup are NOPS, except these - if(refresh_count == startup_refresh_max-31) begin - // ensure all rows are closed - command <= CMD_PRECHARGE; - SDRAM_A[10] <= 1; // all banks - SDRAM_BA <= 2'b00; - end else if (refresh_count == startup_refresh_max-23) begin - // these refreshes need to be at least tREF (66ns) apart - command <= CMD_AUTO_REFRESH; - end else if (refresh_count == startup_refresh_max-15) - command <= CMD_AUTO_REFRESH; - else if (refresh_count == startup_refresh_max-7) begin - // Now load the mode register - command <= CMD_LOAD_MODE; - SDRAM_A <= MODE; - end - - //------------------------------------------------------ - //-- if startup is complete then go into idle mode, - //-- get prepared to accept a new command, and schedule - //-- the first refresh cycle - //------------------------------------------------------ - if(!refresh_count) begin - state <= STATE_IDLE; - ready <= 1; - refresh_count <= 0; - end - end - - STATE_IDLE_7: state <= STATE_IDLE_6; - STATE_IDLE_6: state <= STATE_IDLE_5; - STATE_IDLE_5: state <= STATE_IDLE_4; - STATE_IDLE_4: state <= STATE_IDLE_3; - STATE_IDLE_3: state <= STATE_IDLE_2; - STATE_IDLE_2: state <= STATE_IDLE_1; - STATE_IDLE_1: begin - SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; - state <= STATE_IDLE; - // mask possible refresh to reduce colliding. - if(refresh_count > cycles_per_refresh) begin - //------------------------------------------------------------------------ - //-- Start the refresh cycle. - //-- This tasks tRFC (66ns), so 2 idle cycles are needed @ 24MHz - //------------------------------------------------------------------------ - state <= STATE_IDLE_2; - command <= CMD_AUTO_REFRESH; - refresh_count <= refresh_count - cycles_per_refresh + 1'd1; - end - end - - STATE_IDLE: begin - // Priority is to issue a refresh if one is outstanding - if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1; - else if(new_rd | new_we) begin - new_we <= 0; - new_rd <= 0; - save_addr<= addr; - save_we <= new_we; - state <= STATE_OPEN_1; - command <= CMD_ACTIVE; - SDRAM_A <= addr[13:1]; - SDRAM_BA <= addr[24:23]; - end - end - - // ACTIVE-to-READ or WRITE delay >20ns (1 cycle @ 24 MHz)(-75) - STATE_OPEN_1: begin - SDRAM_A <= {4'b0010, save_addr[22:14]}; - SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]); - SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]); - state <= save_we ? STATE_WRITE : STATE_READ; - end - - STATE_READ: begin - state <= STATE_IDLE_5; - command <= CMD_READ; - SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; - - // Schedule reading the data values off the bus - data_ready_delay[CAS_LATENCY] <= 1; - end - - STATE_WRITE: begin - state <= STATE_IDLE_5; - command <= CMD_WRITE; - SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]}; - ready <= 1; - end - endcase - - if(init) begin - state <= STATE_STARTUP; - refresh_count <= startup_refresh_max - sdram_startup_cycles; - end - - old_we <= we; - old_rd <= rd; - if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt}; - else - if((rd & ~old_rd) || (rd & old_rd & (save_addr != addr))) {ready, new_rd} <= {1'b0, 1'b1}; - -end - -endmodule diff --git a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd deleted file mode 100644 index 626d06d9..00000000 --- a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot_sound_board.vhd +++ /dev/null @@ -1,426 +0,0 @@ ---------------------------------------------------------------------------------- --- Time pilot sound board by Dar (darfpga@aol.fr) (29/10/2017) --- http://darfpga.blogspot.fr ---------------------------------------------------------------------------------- --- gen_ram.vhd --------------------------------- --- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) --- http://www.syntiac.com/fpga64.html ---------------------------------------------------------------------------------- --- T80/T80se - Version : 0247 ------------------------------ --- Z80 compatible microprocessor core --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) ---------------------------------------------------------------------------------- --- YM2149 (AY-3-8910) --- Copyright (c) MikeJ - Jan 2005 ---------------------------------------------------------------------------------- --- Educational use only --- Do not redistribute synthetized file with roms --- Do not redistribute roms whatever the form --- Use at your own risk ---------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -entity time_pilot_sound_board is -port( - clock_14 : in std_logic; - reset : in std_logic; - - sound_cmd : in std_logic_vector(7 downto 0); - sound_trig : in std_logic; - - audio_out : out std_logic_vector(10 downto 0); - - dbg_cpu_addr : out std_logic_vector(15 downto 0) - ); -end time_pilot_sound_board; - -architecture struct of time_pilot_sound_board is - - signal reset_n: std_logic; - signal clock_14n : std_logic; - - signal clock_div1 : std_logic_vector(11 downto 0) := (others => '0'); - signal biquinary_div : std_logic_vector(3 downto 0) := (others => '0'); - - signal cpu_clock_en : std_logic; - signal ayx_clock_en : std_logic; - - signal cpu_addr : std_logic_vector(15 downto 0); - signal cpu_di : std_logic_vector( 7 downto 0); - signal cpu_do : std_logic_vector( 7 downto 0); - signal cpu_wr_n : std_logic; - signal cpu_mreq_n : std_logic; - signal cpu_irq_n : std_logic; - signal cpu_iorq_n : std_logic; - signal cpu_m1_n : std_logic; - - signal cpu_rom_do : std_logic_vector( 7 downto 0); - signal wram_do : std_logic_vector( 7 downto 0); - signal wram_we : std_logic; - - signal clr_irq_n : std_logic; - signal sen1_n : std_logic; - signal sen2_n : std_logic; - signal sen3_n : std_logic; - signal sen4_n : std_logic; - - signal sound_trig_r : std_logic; - - signal ay1_do : std_logic_vector(7 downto 0); - signal ay1_cs_n : std_logic; - signal ay1_bdir : std_logic; - signal ay1_bc1 : std_logic; - signal ay1_audio_muxed : std_logic_vector(7 downto 0); - signal ay1_audio_chan : std_logic_vector(1 downto 0); - signal ay1_port_b_di : std_logic_vector(7 downto 0); - - signal ay2_do : std_logic_vector(7 downto 0); - signal ay2_cs_n : std_logic; - signal ay2_bdir : std_logic; - signal ay2_bc1 : std_logic; - signal ay2_audio_muxed : std_logic_vector(7 downto 0); - signal ay2_audio_chan : std_logic_vector(1 downto 0); - - signal ay1_chan_a : std_logic_vector(7 downto 0); - signal ay1_chan_b : std_logic_vector(7 downto 0); - signal ay1_chan_c : std_logic_vector(7 downto 0); - signal ay2_chan_a : std_logic_vector(7 downto 0); - signal ay2_chan_b : std_logic_vector(7 downto 0); - signal ay2_chan_c : std_logic_vector(7 downto 0); - - signal filter_cmd_we : std_logic; - signal filter_cmd : std_logic_vector(11 downto 0); - signal mult_cmd : std_logic_vector(1 downto 0); - signal mult_value : integer range 0 to 779; - - signal Vc_1a : integer range -256*1024 to 256*1024-1; - signal Vc_1b : integer range -256*1024 to 256*1024-1; - signal Vc_1c : integer range -256*1024 to 256*1024-1; - signal Vc_2a : integer range -256*1024 to 256*1024-1; - signal Vc_2b : integer range -256*1024 to 256*1024-1; - signal Vc_2c : integer range -256*1024 to 256*1024-1; - signal Vc : integer range -256*1024 to 256*1024-1; - signal Vin : integer range -256 to 255; - signal dV : integer range -512 to 511; - signal Vcn_a : integer range -1024*1024 to 1024*1024-1; - signal Vcn_b : integer range -1024*1024 to 1024*1024-1; - signal Vcn_c : integer range -256*1024 to 256*1024-1; - -begin - -clock_14n <= not clock_14; -reset_n <= not reset; - --- debug -process (reset, clock_14) -begin - if rising_edge(clock_14) and cpu_mreq_n ='0' then - dbg_cpu_addr <= cpu_addr; - end if; -end process; - --------------------------------------------------------- --- RC filters equation --- --- Vc : capacitor voltage = output voltage --- fs : sample frequency --- Vin : voltage at resistor input --- --- Vc(k+1) = Vc(k) + (Vin-Vc(k))/(fs.R.C) --- --- Vcn * 1024 <= Vcn * 1024 + (Vin-Vc) * 1024/(fs.R.C) --- With Vcn = 1024 * Vc --------------------------------------------------------- --- Filters will be run at 14.318MHz/512 = 27.96KHz --------------------------------------------------------- --- 6 filters have to be implemented --- RC equation is time multiplexed to save multiplier --- for small FPGA --------------------------------------------------------- - --- mux Vc -with clock_div1(3 downto 0) select -Vc <= Vc_1a when X"0", -- Vc_xy : [0..255*1024] - Vc_1b when X"1", -- => Vc : [-256*1024..255*1024] - Vc_1c when X"2", - Vc_2a when X"3", - Vc_2b when X"4", - Vc_2c when others; - --- mux Vin -with clock_div1(3 downto 0) select -Vin <= to_integer(unsigned(ay1_chan_a)) when X"0", -- ayx_chan_y : [0..255] - to_integer(unsigned(ay1_chan_b)) when X"1", -- => Vin : [-256:255] - to_integer(unsigned(ay1_chan_c)) when X"2", - to_integer(unsigned(ay2_chan_a)) when X"3", - to_integer(unsigned(ay2_chan_b)) when X"4", - to_integer(unsigned(ay2_chan_c)) when others; - --- compute dV -dV <= Vin-Vc/1024; -- Vc/1024 : [0..255], dv : [-255..511] => [-512..511] - --- mux filter cmd -with clock_div1(3 downto 0) select -mult_cmd <= filter_cmd( 7 downto 6) when X"0", - filter_cmd( 9 downto 8) when X"1", - filter_cmd(11 downto 10) when X"2", - filter_cmd( 1 downto 0) when X"3", - filter_cmd( 3 downto 2) when X"4", - filter_cmd( 5 downto 4) when others; - --- mux multiplier value -with mult_cmd select -mult_value <= 779 when "10", -- 0.047uF/1KOhm => (1024/fs.R.C = 779, cut fcy 3386Hz) - 166 when "01", -- 0.220uF/1KOhm => (1024/fs.R.C = 166, cut fcy 723Hz) - 137 when "11", -- 0.267uF/1KOhm => (1024/fs.R.C = 137, cut fcy 596Hz) - 779 when others; -- Not use - --- compute Vcn -Vcn_a <= Vin*1024 when mult_cmd = "00" else Vc + dv*mult_value; -- => Vcn_a : [-1024*1024..1023*1024] - --- limit to > 0 -Vcn_b <= 0 when Vcn_a < 0 else Vcn_a; - --- limit to < 255*1024 -Vcn_c <= 255*1024 when Vcn_b > 255*1024 else Vcn_b; - --- demux/store result and mix channels -process (clock_14) -begin - if rising_edge(clock_14) then -- 14.318MHz/512 => fs = 27.96KHz - - -- demux & down sample - if clock_div1(8 downto 0) = '0'&X"00" then Vc_1a <= Vcn_c; end if; - if clock_div1(8 downto 0) = '0'&X"01" then Vc_1b <= Vcn_c; end if; - if clock_div1(8 downto 0) = '0'&X"02" then Vc_1c <= Vcn_c; end if; - if clock_div1(8 downto 0) = '0'&X"03" then Vc_2a <= Vcn_c; end if; - if clock_div1(8 downto 0) = '0'&X"04" then Vc_2b <= Vcn_c; end if; - if clock_div1(8 downto 0) = '0'&X"05" then Vc_2c <= Vcn_c; end if; - - -- rescale and mix channels with down sample - if clock_div1(8 downto 0) = '0'&X"06" then - audio_out <= std_logic_vector(to_unsigned(Vc_1a/1024,11)) + - std_logic_vector(to_unsigned(Vc_1b/1024,11)) + - std_logic_vector(to_unsigned(Vc_1c/1024,11)) + - std_logic_vector(to_unsigned(Vc_2a/1024,11)) + - std_logic_vector(to_unsigned(Vc_2b/1024,11)) + - std_logic_vector(to_unsigned(Vc_2c/1024,11)); - end if; - end if; -end process; - - --- divide clocks --- random generator ? -process (clock_14) -begin - if reset='1' then - clock_div1 <= (others =>'0'); - biquinary_div <= (others =>'0'); - else - if rising_edge(clock_14) then - clock_div1 <= clock_div1 + '1'; - - if clock_div1 = X"800" then - if biquinary_div(3 downto 1) = "100" then - biquinary_div(3 downto 1) <= "000"; - biquinary_div(0) <= not biquinary_div(0); - else - biquinary_div(3 downto 1) <= biquinary_div(3 downto 1) + '1'; - end if; - end if; - - end if; - end if; -end process; - --- make clocks for cpu and sound generators -cpu_clock_en <= '1' when clock_div1(2 downto 0) = "011" else '0'; -ayx_clock_en <= '1' when clock_div1(2 downto 0) = "111" else '0'; - --- mux rom/ram/devices data ouput to cpu data input w.r.t cpu address -cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) = "0000" else -- 0000-0FFF - wram_do when cpu_addr(15 downto 12) = "0011" else -- 3000-3FFF - ay1_do when cpu_addr(15 downto 13) = "010" else -- 4000-5FFF - ay2_do when cpu_addr(15 downto 13) = "011" else -- 6000-7FFF - X"FF"; - --- write enable to working ram and filter command register -wram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = "0011" else '0'; -filter_cmd_we <= '1' when cpu_wr_n = '0' and cpu_addr(15) = '1' else '0'; - --- chip select with r/w direction to AY chips -sen1_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"4" else '1'; -sen2_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"5" else '1'; -sen3_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"6" else '1'; -sen4_n <= '0' when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"7" else '1'; - --- finalise AY r/w & address controls -ay1_bc1 <= not sen2_n or ( cpu_wr_n and not sen1_n); -ay1_bdir <= not sen2_n or (not cpu_wr_n and not sen1_n); -ay1_cs_n <= sen1_n and sen2_n; - -ay2_bc1 <= not sen4_n or ( cpu_wr_n and not sen3_n); -ay2_bdir <= not sen4_n or (not cpu_wr_n and not sen3_n); -ay2_cs_n <= sen3_n and sen4_n; - --- input random (?) to AY1 chip -ay1_port_b_di <= biquinary_div(0)&biquinary_div(3)&biquinary_div(2)&clock_div1(11)&"0000"; - --- clear irq when reset and irq acknowledge -clr_irq_n <= reset_n and (cpu_m1_n or cpu_iorq_n); - --- regsiter filters commands (11 bits data are cpu address) -process (clock_14, cpu_clock_en) -begin - if rising_edge(clock_14) and cpu_clock_en = '1' then - if filter_cmd_we = '1' then filter_cmd <= cpu_addr(11 downto 0); end if; - end if; -end process; - --- latch sound trigger rising edge to set cpu_irq, and manage clear -process (clock_14) -begin - if rising_edge(clock_14) then - - sound_trig_r <= sound_trig; - - if clr_irq_n = '0' then - cpu_irq_n <= '1'; - else - if sound_trig ='1' and sound_trig_r = '0' then - cpu_irq_n <= '0'; - end if; - end if; - - end if; -end process; - --- demux AY chips output -process (clock_14, ayx_clock_en) -begin - if rising_edge(clock_14) and ayx_clock_en = '1' then - if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if; - if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if; - if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if; - if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if; - if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if; - if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if; - end if; -end process; - --- microprocessor Z80 -cpu : entity work.T80se -generic map(Mode => 0, T2Write => 1, IOWait => 1) -port map( - RESET_n => reset_n, - CLK_n => clock_14, - CLKEN => cpu_clock_en, - WAIT_n => '1', - INT_n => cpu_irq_n, - NMI_n => '1', - BUSRQ_n => '1', - M1_n => cpu_m1_n, - MREQ_n => cpu_mreq_n, - IORQ_n => cpu_iorq_n, - RD_n => open, - WR_n => cpu_wr_n, - RFSH_n => open, - HALT_n => open, - BUSAK_n => open, - A => cpu_addr, - DI => cpu_di, - DO => cpu_do -); - --- cpu1 program ROM -rom_cpu1 : entity work.time_pilot_sound_prog -port map( - clk => clock_14n, - addr => cpu_addr(11 downto 0), - data => cpu_rom_do -); - --- working RAM -wram : entity work.gen_ram -generic map( dWidth => 8, aWidth => 10) -port map( - clk => clock_14n, - we => wram_we, - addr => cpu_addr(9 downto 0), - d => cpu_do, - q => wram_do -); - --- AY-3-8910 #1 -ay_3_8910_1 : entity work.YM2149 -port map( - -- data bus - I_DA => cpu_do, -- in std_logic_vector(7 downto 0); - O_DA => ay1_do, -- out std_logic_vector(7 downto 0); - O_DA_OE_L => open, -- out std_logic; - -- control - I_A9_L => ay1_cs_n, -- in std_logic; - I_A8 => '1', -- in std_logic; - I_BDIR => ay1_bdir, -- in std_logic; - I_BC2 => '1', -- in std_logic; - I_BC1 => ay1_bc1, -- in std_logic; - I_SEL_L => '1', -- in std_logic; - - O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0); - O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0); - - -- port a - I_IOA => sound_cmd, -- in std_logic_vector(7 downto 0); - O_IOA => open, -- out std_logic_vector(7 downto 0); - O_IOA_OE_L => open, -- out std_logic; - -- port b - I_IOB => ay1_port_b_di, -- in std_logic_vector(7 downto 0); - O_IOB => open, -- out std_logic_vector(7 downto 0); - O_IOB_OE_L => open, -- out std_logic; - - ENA => ayx_clock_en, -- in std_logic; -- clock enable for higher speed operation - RESET_L => reset_n, -- in std_logic; - CLK => clock_14 -- in std_logic -); - --- AY-3-8910 #2 -ay_3_8910_2 : entity work.YM2149 -port map( - -- data bus - I_DA => cpu_do, -- in std_logic_vector(7 downto 0); - O_DA => ay2_do, -- out std_logic_vector(7 downto 0); - O_DA_OE_L => open, -- out std_logic; - -- control - I_A9_L => ay2_cs_n, -- in std_logic; - I_A8 => '1', -- in std_logic; - I_BDIR => ay2_bdir, -- in std_logic; - I_BC2 => '1', -- in std_logic; - I_BC1 => ay2_bc1, -- in std_logic; - I_SEL_L => '1', -- in std_logic; - - O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0); - O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0); - - -- port a - I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); - O_IOA => open, -- out std_logic_vector(7 downto 0); - O_IOA_OE_L => open, -- out std_logic; - -- port b - I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); - O_IOB => open, -- out std_logic_vector(7 downto 0); - O_IOB_OE_L => open, -- out std_logic; - - ENA => ayx_clock_en, -- in std_logic; -- clock enable for higher speed operation - RESET_L => reset_n, -- in std_logic; - CLK => clock_14 -- in std_logic -); - - -end struct; \ No newline at end of file diff --git a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.qpf b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.qpf deleted file mode 100644 index 91b40ed1..00000000 --- a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2016 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Intel and sold by Intel or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition -# Date created = 11:17:10 October 25, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "16.1" -DATE = "11:17:10 October 25, 2017" - -# Revisions - -PROJECT_REVISION = "time_pilot_mist" diff --git a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.sdc b/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.sdc deleted file mode 100644 index ca3faf31..00000000 --- a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/time_pilot_mist.sdc +++ /dev/null @@ -1,138 +0,0 @@ -## Generated SDC file "vectrex_MiST.out.sdc" - -## Copyright (C) 1991-2013 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" - -## DATE "Sun Jun 24 12:53:00 2018" - -## -## DEVICE "EP3C25E144C8" -## - -# Clock constraints - -# Automatically constrain PLL and other generated clocks -derive_pll_clocks -create_base_clocks - -# Automatically calculate clock uncertainty to jitter and other effects. -derive_clock_uncertainty - -# tsu/th constraints - -# tco constraints - -# tpd constraints - -#************************************************************** -# Time Information -#************************************************************** - -set_time_format -unit ns -decimal_places 3 - - - -#************************************************************** -# Create Clock -#************************************************************** - -create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] - -set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]" -set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" -set snd_clk "pll|altpll_component|auto_generated|pll1|clk[2]" -set vid_clk "pll|altpll_component|auto_generated|pll1|clk[0]" -#************************************************************** -# Create Generated Clock -#************************************************************** - - -#************************************************************** -# Set Clock Latency -#************************************************************** - - - -#************************************************************** -# Set Clock Uncertainty -#************************************************************** - -#************************************************************** -# Set Input Delay -#************************************************************** - -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] - -set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]] -set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]] - -#************************************************************** -# Set Output Delay -#************************************************************** - -set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] -set_output_delay -add_delay -clock_fall -clock [get_clocks $snd_clk] 1.000 [get_ports {AUDIO_L}] -set_output_delay -add_delay -clock_fall -clock [get_clocks $snd_clk] 1.000 [get_ports {AUDIO_R}] -set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}] -set_output_delay -add_delay -clock_fall -clock [get_clocks $vid_clk] 1.000 [get_ports {VGA_*}] - -set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] -set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] - -#************************************************************** -# Set Clock Groups -#************************************************************** - -set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] -# audio-main cpu clocks are asynchronous -set_clock_groups -asynchronous -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[3]}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] - -#************************************************************** -# Set False Path -#************************************************************** - - - -#************************************************************** -# Set Multicycle Path -#************************************************************** - -set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 1 - -#************************************************************** -# Set Maximum Delay -#************************************************************** - - - -#************************************************************** -# Set Minimum Delay -#************************************************************** - - - -#************************************************************** -# Set Input Transition -#************************************************************** - diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/clean.bat b/Arcade_MiST/Konami Timepilot Hardware/clean.bat similarity index 100% rename from Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/clean.bat rename to Arcade_MiST/Konami Timepilot Hardware/clean.bat diff --git a/Arcade_MiST/Konami Timepilot Hardware/meta/Power Surge.mra b/Arcade_MiST/Konami Timepilot Hardware/meta/Power Surge.mra new file mode 100644 index 00000000..14c08a28 --- /dev/null +++ b/Arcade_MiST/Konami Timepilot Hardware/meta/Power Surge.mra @@ -0,0 +1,39 @@ + + Power Surge + 0220 + psurge + 20200427161917 + 1982 + Konami + timeplt + + + + + + + + + + + 01 + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/Konami Timepilot Hardware/meta/Time Pilot.mra b/Arcade_MiST/Konami Timepilot Hardware/meta/Time Pilot.mra new file mode 100644 index 00000000..19f484d2 --- /dev/null +++ b/Arcade_MiST/Konami Timepilot Hardware/meta/Time Pilot.mra @@ -0,0 +1,36 @@ + + Time Pilot + 0220 + timeplt + 20200427161917 + 1982 + Konami + Army / Dog-Fight + timeplt + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/TimePilot_MiST.sv b/Arcade_MiST/Konami Timepilot Hardware/rtl/TimePilot_MiST.sv similarity index 92% rename from Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/TimePilot_MiST.sv rename to Arcade_MiST/Konami Timepilot Hardware/rtl/TimePilot_MiST.sv index 81b36989..667eae59 100644 --- a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/TimePilot_MiST.sv +++ b/Arcade_MiST/Konami Timepilot Hardware/rtl/TimePilot_MiST.sv @@ -59,21 +59,18 @@ localparam CONF_STR = { "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", "O5,Blend,Off,On;", - "O67,Lives,3,4,5,Unl.;", - "O8,Bonus Life,10K 50k,20K 60K;", - "O9B,Difficulty,1,2,3,4,5,6,7,8;", - "OC,Demo Sounds,Off,On;", + "DIP;", "T0,Reset;", - "V,v1.15.",`BUILD_DATE + "V,",`BUILD_DATE }; wire rotate = status[2]; wire [1:0] scanlines = status[4:3]; wire blend = status[5]; -wire [1:0] lives = status[7:6]; -wire bonus = status[8]; -wire [2:0] difficulty = status[11:9]; -wire demosnd = status[12]; + +wire psurge = core_mod[0]; +wire [7:0] sw1 = status[15:8]; +wire [7:0] sw2 = status[23:16]; assign LED = 1; assign AUDIO_R = AUDIO_L; @@ -100,6 +97,7 @@ wire no_csync; wire key_strobe; wire key_pressed; wire [7:0] key_code; +wire [6:0] core_mod; user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( .clk_sys (clock_12 ), @@ -118,7 +116,8 @@ user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io( .key_code (key_code ), .joystick_0 (joystick_0 ), .joystick_1 (joystick_1 ), - .status (status ) + .status (status ), + .core_mod (core_mod ) ); wire [14:0] rom_addr; @@ -174,6 +173,7 @@ time_pilot time_pilot( .clock_12(clock_12), .clock_14(clock_14), .reset(reset), + .psurge(psurge), .video_r(r), .video_g(g), .video_b(b), @@ -183,8 +183,8 @@ time_pilot time_pilot( .roms_addr(rom_addr), .roms_do(rom_do[7:0]), .roms_rd(rom_rd), - .dip_switch_1(8'b11111111),// Coinage_B / Coinage_A - .dip_switch_2(~{demosnd, difficulty, bonus, 1'b1, lives}),// Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1) + .dip_switch_1(sw1), + .dip_switch_2(sw2), .start2(m_two_players), .start1(m_one_player), .coin1(m_coin1), @@ -197,7 +197,11 @@ time_pilot time_pilot( .right2(m_right2), .left2(m_left2), .down2(m_down2), - .up2(m_up2) + .up2(m_up2), + .dl_clk(clock_48), + .dl_addr(ioctl_addr[15:0]), + .dl_wr(ioctl_wr), + .dl_data(ioctl_dout) ); mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video( @@ -216,7 +220,7 @@ mist_video #(.COLOR_DEPTH(5), .SD_HCNT_WIDTH(10)) mist_video( .VGA_VS ( VGA_VS ), .VGA_HS ( VGA_HS ), .ce_divider ( 1'b0 ), - .rotate ( { 1'b1, rotate } ), + .rotate ( { ~psurge, rotate } ), .scandoubler_disable( scandoublerD ), .scanlines ( scanlines ), .blend ( blend ), @@ -244,7 +248,7 @@ arcade_inputs inputs ( .joystick_0 ( joystick_0 ), .joystick_1 ( joystick_1 ), .rotate ( rotate ), - .orientation ( 2'b11 ), + .orientation ( {~psurge, 1'b1} ), .joyswap ( 1'b0 ), .oneplayer ( 1'b1 ), .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/build_id.tcl b/Arcade_MiST/Konami Timepilot Hardware/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/build_id.tcl rename to Arcade_MiST/Konami Timepilot Hardware/rtl/build_id.tcl diff --git a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Konami Timepilot Hardware/rtl/dpram.vhd similarity index 53% rename from Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/gen_ram.vhd rename to Arcade_MiST/Konami Timepilot Hardware/rtl/dpram.vhd index f1a95608..284194c5 100644 --- a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/gen_ram.vhd +++ b/Arcade_MiST/Konami Timepilot Hardware/rtl/dpram.vhd @@ -12,7 +12,7 @@ -- -- ----------------------------------------------------------------------- -- --- gen_rwram.vhd +-- dpram.vhd -- -- ----------------------------------------------------------------------- -- @@ -26,59 +26,56 @@ use IEEE.numeric_std.ALL; -- ----------------------------------------------------------------------- -entity gen_ram is +entity dpram is generic ( dWidth : integer := 8; aWidth : integer := 10 ); port ( - clk : in std_logic; - we : in std_logic; - addr : in std_logic_vector((aWidth-1) downto 0); - d : in std_logic_vector((dWidth-1) downto 0); - q : out std_logic_vector((dWidth-1) downto 0) + clk_a : in std_logic; + we_a : in std_logic := '0'; + addr_a : in std_logic_vector((aWidth-1) downto 0); + d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_a : out std_logic_vector((dWidth-1) downto 0); + + clk_b : in std_logic; + we_b : in std_logic := '0'; + addr_b : in std_logic_vector((aWidth-1) downto 0); + d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_b : out std_logic_vector((dWidth-1) downto 0) ); end entity; -- ----------------------------------------------------------------------- -architecture rtl of gen_ram is +architecture rtl of dpram is subtype addressRange is integer range 0 to ((2**aWidth)-1); type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); signal ram: ramDef; - - signal rAddrReg : std_logic_vector((aWidth-1) downto 0); - signal qReg : std_logic_vector((dWidth-1) downto 0); + signal addr_a_reg: std_logic_vector((aWidth-1) downto 0); + signal addr_b_reg: std_logic_vector((aWidth-1) downto 0); begin --- ----------------------------------------------------------------------- --- Signals to entity interface --- ----------------------------------------------------------------------- --- q <= qReg; -- ----------------------------------------------------------------------- --- Memory write --- ----------------------------------------------------------------------- - process(clk) + process(clk_a) begin - if rising_edge(clk) then - if we = '1' then - ram(to_integer(unsigned(addr))) <= d; + if rising_edge(clk_a) then + if we_a = '1' then + ram(to_integer(unsigned(addr_a))) <= d_a; end if; + q_a <= ram(to_integer(unsigned(addr_a))); + end if; + end process; + + process(clk_b) + begin + if rising_edge(clk_b) then + if we_b = '1' then + ram(to_integer(unsigned(addr_b))) <= d_b; + end if; + q_b <= ram(to_integer(unsigned(addr_b))); end if; end process; --- ----------------------------------------------------------------------- --- Memory read --- ----------------------------------------------------------------------- -process(clk) - begin - if rising_edge(clk) then --- qReg <= ram(to_integer(unsigned(rAddrReg))); --- rAddrReg <= addr; ----- qReg <= ram(to_integer(unsigned(addr))); - q <= ram(to_integer(unsigned(addr))); - end if; - end process; ---q <= ram(to_integer(unsigned(addr))); end architecture; diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Konami Timepilot Hardware/rtl/gen_ram.vhd similarity index 100% rename from Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/gen_ram.vhd rename to Arcade_MiST/Konami Timepilot Hardware/rtl/gen_ram.vhd diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/gen_video.vhd b/Arcade_MiST/Konami Timepilot Hardware/rtl/gen_video.vhd similarity index 100% rename from Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/gen_video.vhd rename to Arcade_MiST/Konami Timepilot Hardware/rtl/gen_video.vhd diff --git a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/pll.qip b/Arcade_MiST/Konami Timepilot Hardware/rtl/pll.qip similarity index 100% rename from Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/pll.qip rename to Arcade_MiST/Konami Timepilot Hardware/rtl/pll.qip diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/pll.v b/Arcade_MiST/Konami Timepilot Hardware/rtl/pll.v similarity index 100% rename from Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/pll.v rename to Arcade_MiST/Konami Timepilot Hardware/rtl/pll.v diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/power_surge.vhd b/Arcade_MiST/Konami Timepilot Hardware/rtl/power_surge.vhd similarity index 100% rename from Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/power_surge.vhd rename to Arcade_MiST/Konami Timepilot Hardware/rtl/power_surge.vhd diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/sdram.sv b/Arcade_MiST/Konami Timepilot Hardware/rtl/sdram.sv similarity index 100% rename from Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/sdram.sv rename to Arcade_MiST/Konami Timepilot Hardware/rtl/sdram.sv diff --git a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot.vhd b/Arcade_MiST/Konami Timepilot Hardware/rtl/time_pilot.vhd similarity index 85% rename from Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot.vhd rename to Arcade_MiST/Konami Timepilot Hardware/rtl/time_pilot.vhd index 3574d728..848ce375 100644 --- a/Arcade_MiST/Konami Timepilot Hardware/Time_Pilot_MiST/rtl/time_pilot.vhd +++ b/Arcade_MiST/Konami Timepilot Hardware/rtl/time_pilot.vhd @@ -81,10 +81,11 @@ use ieee.numeric_std.all; entity time_pilot is port( - clock_6 : in std_logic; - clock_12 : in std_logic; - clock_14 : in std_logic; - reset : in std_logic; + clock_6 : in std_logic; + clock_12 : in std_logic; + clock_14 : in std_logic; + reset : in std_logic; + psurge : in std_logic; video_r : out std_logic_vector(4 downto 0); video_g : out std_logic_vector(4 downto 0); video_b : out std_logic_vector(4 downto 0); @@ -95,8 +96,8 @@ port( video_vs : out std_logic; audio_out : out std_logic_vector(10 downto 0); roms_addr : out std_logic_vector(14 downto 0); - roms_do : in std_logic_vector(7 downto 0); - roms_rd : out std_logic; + roms_do : in std_logic_vector(7 downto 0); + roms_rd : out std_logic; dip_switch_1 : in std_logic_vector(7 downto 0); -- Coinage_B / Coinage_A dip_switch_2 : in std_logic_vector(7 downto 0); -- Sound(8)/Difficulty(7-5)/Bonus(4)/Cocktail(3)/lives(2-1) @@ -116,6 +117,11 @@ port( down2 : in std_logic; up2 : in std_logic; + dl_clk : in std_logic; + dl_addr : in std_logic_vector(15 downto 0); + dl_wr : in std_logic; + dl_data : in std_logic_vector(7 downto 0); + dbg_cpu_addr : out std_logic_vector(15 downto 0) ); end time_pilot; @@ -214,6 +220,14 @@ architecture struct of time_pilot is signal input_1 : std_logic_vector(7 downto 0); signal input_2 : std_logic_vector(7 downto 0); + signal char_graphics_we : std_logic; + signal ch_palette_we : std_logic; + signal sp_graphics_we : std_logic; + signal sp_palette_we : std_logic; + signal rgb_palette_gb_we: std_logic; + signal rgb_palette_br_we: std_logic; + signal sound_rom_we : std_logic; + begin video_clk <= clock_6n; @@ -287,7 +301,8 @@ input_1 <= "111" & not fire1 & not down1 & not up1 & not right1 & not le input_2 <= "111" & not fire2 & not down2 & not up2 & not right2 & not left2; -- ?/2FL/2SR/2SL/2DW/2UP/2RI/2LE -- cpu input address decoding (mirror mostly from Mame) -cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) < X"6" else -- 0000-5FFF +cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) < X"6" else -- 0000-5FFF + X"80" when cpu_addr(15 downto 0) = X"6004" and psurge = '1' else -- 6004 Protection X"FF" when cpu_addr(15 downto 12) < X"A" else -- 6000-9FFF wram_do when cpu_addr(15 downto 12) = X"A" else -- A000-AFFF @@ -347,17 +362,21 @@ begin sound_cmd <= cpu_do; end if; - if C3xx_we = '1' then + if C3xx_we = '1' then if cpu_addr(3 downto 1) = "000" then itt_n <= cpu_do(0); end if; if cpu_addr(3 downto 1) = "001" then flip <= not cpu_do(0); end if; if cpu_addr(3 downto 1) = "010" then sound_trig <= cpu_do(0); end if; end if; - - if itt_n = '0' then - cpu_nmi_n <= '1'; - else -- lauch nmi and end of frame - if (vcnt = 493) and (hcnt = "000000") and (pxcnt = "000") then - cpu_nmi_n <= '0'; + + if psurge = '1' then + cpu_nmi_n <= vblank; + else + if itt_n = '0' then + cpu_nmi_n <= '1'; + else -- lauch nmi and end of frame + if (vcnt = 493) and (hcnt = "000000") and (pxcnt = "000") then + cpu_nmi_n <= '0'; + end if; end if; end if; end if; @@ -499,7 +518,7 @@ sp_buffer_ram2_we <= not clock_6 when sp_buffer_sel = '1' else sp_buffer_write_w -- latch current char data with respect to vcnt and hcnt in relation -- with wram ram addressing -process (clock_6) +process (clock_6, pxcnt) begin if rising_edge(clock_6) and pxcnt = "001" then ch_data1 <= wram_do ; @@ -585,7 +604,7 @@ video_vblank <= vblank; -- video syncs and blanks -- ---------------------------- -process(clock_6) +process(clock_6, pxcnt) constant hcnt_base : integer := 36; variable vsync_cnt : std_logic_vector(3 downto 0); begin @@ -605,9 +624,9 @@ begin if hcnt = hcnt_base-4 then hblank <= '1'; - if vcnt = 496 then + if vcnt = 495 then vblank <= '1'; -- 492 ok - elsif vcnt = 262 then + elsif vcnt = 263 then vblank <= '0'; -- 262 ok end if; elsif hcnt = 0 then @@ -635,7 +654,7 @@ port map( CLK_n => clock_6, CLKEN => cpu_ena, WAIT_n => '1', - INT_n => '1', --cpu_irq_n, + INT_n => '1', NMI_n => cpu_nmi_n, BUSRQ_n => '1', M1_n => open, @@ -720,54 +739,127 @@ port map( ); -- char graphics ROM -char_graphics : entity work.time_pilot_char_grphx +char_graphics_we <= '1' when dl_wr = '1' and dl_addr(15 downto 13) = "011" else '0'; + +char_graphics : entity work.dpram +generic map( + dWidth => 8, + aWidth => 13 +) port map( - clk => clock_6, - addr => ch_graphx_addr, - data => ch_graphx_do + clk_a => clock_6, + addr_a => ch_graphx_addr, + d_a => (others => '0'), + q_a => ch_graphx_do, + clk_b => dl_clk, + we_b => char_graphics_we, + addr_b => dl_addr(12 downto 0), + d_b => dl_data, + q_b => open ); -- char palette ROM -ch_palette : entity work.time_pilot_char_color_lut +ch_palette_we <= '1' when dl_wr = '1' and dl_addr(15 downto 8) = x"E1" else '0'; +ch_palette : entity work.dpram +generic map( + dWidth => 8, + aWidth => 8 +) port map( - clk => clock_6, - addr => ch_palette_addr, - data => ch_palette_do + clk_a => clock_6, + addr_a => ch_palette_addr, + d_a => (others => '0'), + q_a => ch_palette_do, + clk_b => dl_clk, + we_b => ch_palette_we, + addr_b => dl_addr(7 downto 0), + d_b => dl_data, + q_b => open ); -- sprite graphics ROM -sp_graphics : entity work.time_pilot_sprite_grphx +sp_graphics_we <= '1' when dl_wr = '1' and dl_addr(15 downto 14) = "10" else '0'; + +sp_graphics : entity work.dpram +generic map( + dWidth => 8, + aWidth => 14 +) port map( - clk => clock_6, - addr => sp_graphx_addr, - data => sp_graphx_do + clk_a => clock_6, + addr_a => sp_graphx_addr, + d_a => (others => '0'), + q_a => sp_graphx_do, + clk_b => dl_clk, + we_b => sp_graphics_we, + addr_b => dl_addr(13 downto 0), + d_b => dl_data, + q_b => open ); -- sprite palette ROM -sp_palette : entity work.time_pilot_sprite_color_lut +sp_palette_we <= '1' when dl_wr = '1' and dl_addr(15 downto 8) = x"E0" else '0'; + +sp_palette : entity work.dpram +generic map( + dWidth => 8, + aWidth => 8 +) port map( - clk => clock_6, - addr => sp_palette_addr, - data => sp_palette_do + clk_a => clock_6, + addr_a => sp_palette_addr, + d_a => (others => '0'), + q_a => sp_palette_do, + clk_b => dl_clk, + we_b => sp_palette_we, + addr_b => dl_addr(7 downto 0), + d_b => dl_data, + q_b => open ); -- rgb palette ROM 1 -rgb_palette_gb : entity work.time_pilot_palette_blue_green +rgb_palette_gb_we <= '1' when dl_wr = '1' and dl_addr(15 downto 5) = x"E2"&"000" else '0'; + +rgb_palette_gb : entity work.dpram +generic map( + dWidth => 8, + aWidth => 5 +) port map( - clk => clock_6, - addr => rgb_palette_addr, - data => rgb_palette_bg_do + clk_a => clock_6, + addr_a => rgb_palette_addr, + d_a => (others => '0'), + q_a => rgb_palette_bg_do, + clk_b => dl_clk, + we_b => rgb_palette_gb_we, + addr_b => dl_addr(4 downto 0), + d_b => dl_data, + q_b => open ); -- rgb palette ROM 2 -rgb_palette_br : entity work.time_pilot_palette_green_red +rgb_palette_br_we <= '1' when dl_wr = '1' and dl_addr(15 downto 5) = x"E2"&"001" else '0'; + +rgb_palette_br : entity work.dpram +generic map( + dWidth => 8, + aWidth => 5 +) port map( - clk => clock_6, - addr => rgb_palette_addr, - data => rgb_palette_gr_do + clk_a => clock_6, + addr_a => rgb_palette_addr, + d_a => (others => '0'), + q_a => rgb_palette_gr_do, + clk_b => dl_clk, + we_b => rgb_palette_br_we, + addr_b => dl_addr(4 downto 0), + d_b => dl_data, + q_b => open ); -- sound board +sound_rom_we <= '1' when dl_wr = '1' and dl_addr(15 downto 13) = "110" else '0'; + time_pilot_sound_board : entity work.time_pilot_sound_board port map( clock_14 => clock_14, @@ -777,7 +869,12 @@ port map( sound_cmd => sound_cmd, audio_out => audio_out, - + + ROMCL => dl_clk, + ROMAD => dl_addr(12 downto 0), + ROMDT => dl_data, + ROMEN => sound_rom_we, + dbg_cpu_addr => open ); diff --git a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd b/Arcade_MiST/Konami Timepilot Hardware/rtl/time_pilot_sound_board.vhd similarity index 95% rename from Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd rename to Arcade_MiST/Konami Timepilot Hardware/rtl/time_pilot_sound_board.vhd index c92f6e64..fdccde8b 100644 --- a/Arcade_MiST/Konami Timepilot Hardware/Power_Surge_MiST/rtl/time_pilot_sound_board.vhd +++ b/Arcade_MiST/Konami Timepilot Hardware/rtl/time_pilot_sound_board.vhd @@ -35,6 +35,11 @@ port( sound_trig : in std_logic; audio_out : out std_logic_vector(10 downto 0); + + ROMCL : in std_logic; + ROMAD : in std_logic_vector(12 downto 0); + ROMDT : in std_logic_vector(7 downto 0); + ROMEN : in std_logic; dbg_cpu_addr : out std_logic_vector(15 downto 0) ); @@ -218,7 +223,7 @@ end process; -- divide clocks -- random generator ? -process (clock_14) +process (clock_14, reset) begin if reset='1' then clock_div1 <= (others =>'0'); @@ -245,7 +250,7 @@ cpu_clock_en <= '1' when clock_div1(2 downto 0) = "011" else '0'; ayx_clock_en <= '1' when clock_div1(2 downto 0) = "111" else '0'; -- mux rom/ram/devices data ouput to cpu data input w.r.t cpu address -cpu_di <= cpu_rom_do when cpu_addr(15 downto 13) = "000" else -- 0000-1FFF +cpu_di <= cpu_rom_do when cpu_addr(15 downto 13) = "00000" else -- 0000-1FFF wram_do when cpu_addr(15 downto 12) = "0011" else -- 3000-3FFF ay1_do when cpu_addr(15 downto 13) = "010" else -- 4000-5FFF ay2_do when cpu_addr(15 downto 13) = "011" else -- 6000-7FFF @@ -340,11 +345,23 @@ port map( ); -- cpu1 program ROM -rom_cpu1 : entity work.power_surge_sound_prog +--rom_cpu1 : entity work.time_pilot_sound_prog +--port map( +-- clk => clock_14n, +-- addr => cpu_addr(11 downto 0), +-- data => cpu_rom_do +--); +rom_cpu1 : entity work.dpram +generic map( dWidth => 8, aWidth => 13) port map( - clk => clock_14n, - addr => cpu_addr(12 downto 0), - data => cpu_rom_do + clk_a => clock_14n, + addr_a => cpu_addr(12 downto 0), + we_a => '0', + q_a => cpu_rom_do, + clk_b => ROMCL, + addr_b => ROMAD, + we_b => ROMEN, + d_b => ROMDT ); -- working RAM