diff --git a/Arcade_MiST/Universal MrDo/MrDo.qsf b/Arcade_MiST/Universal MrDo/MrDo.qsf index afc21e15..4a010507 100644 --- a/Arcade_MiST/Universal MrDo/MrDo.qsf +++ b/Arcade_MiST/Universal MrDo/MrDo.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:07:52 FEBRUARY 01, 2013" -set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" @@ -222,6 +222,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE output_files/mrdo.stp set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrDo_mist.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrDo_top.sv +set_global_assignment -name VERILOG_FILE rtl/secret_pal.v set_global_assignment -name VERILOG_FILE rtl/video_timing.v set_global_assignment -name VERILOG_FILE rtl/ram_dp_1k.v set_global_assignment -name VERILOG_FILE rtl/cpu_ram.v diff --git a/Arcade_MiST/Universal MrDo/meta/Mr.Do.Fixed.mra b/Arcade_MiST/Universal MrDo/meta/Mr.Do.Fixed.mra index 6076be72..395ad154 100644 --- a/Arcade_MiST/Universal MrDo/meta/Mr.Do.Fixed.mra +++ b/Arcade_MiST/Universal MrDo/meta/Mr.Do.Fixed.mra @@ -37,6 +37,5 @@ - 00 \ No newline at end of file diff --git a/Arcade_MiST/Universal MrDo/meta/Mr.Do.mra b/Arcade_MiST/Universal MrDo/meta/Mr.Do.mra index f079226e..078433ed 100644 --- a/Arcade_MiST/Universal MrDo/meta/Mr.Do.mra +++ b/Arcade_MiST/Universal MrDo/meta/Mr.Do.mra @@ -37,6 +37,5 @@ - 00 diff --git a/Arcade_MiST/Universal MrDo/rtl/MrDo_top.sv b/Arcade_MiST/Universal MrDo/rtl/MrDo_top.sv index 7526d763..08e928db 100644 --- a/Arcade_MiST/Universal MrDo/rtl/MrDo_top.sv +++ b/Arcade_MiST/Universal MrDo/rtl/MrDo_top.sv @@ -678,13 +678,8 @@ reg [15:0] unhandled_addr ; always @ (posedge clk_20M ) begin if ( rd_n == 0 ) begin - // read program rom - if (cpu_addr == 16'h049a ) begin - // patch rom to bypass "secret" pal protection - // cpu tries to read val from 0x9803 which is state machine pal - // written to on all tile ram access. should try converting pal logic to verilog. - cpu_din <= 0; - end else if ( cpu_addr >= 16'h0000 && cpu_addr < 16'h8000 ) begin + // read program rom + if ( cpu_addr >= 16'h0000 && cpu_addr < 16'h8000 ) begin cpu_din <= rom_do; // 0x0000 end else if ( cpu_addr >= 16'h8000 && cpu_addr < 16'h8400 ) begin cpu_din <= bg_ram0_data; @@ -695,7 +690,7 @@ always @ (posedge clk_20M ) begin end else if ( cpu_addr >= 16'h8c00 && cpu_addr < 16'h9000 ) begin cpu_din <= fg_ram1_data; end else if ( cpu_addr == 16'h9803 ) begin - cpu_din <= 0; + cpu_din <= u001_dout; end else if ( cpu_addr == 16'ha000 ) begin cpu_din <= p1; end else if ( cpu_addr == 16'ha001 ) begin @@ -755,6 +750,24 @@ always @ (posedge clk_20M ) begin end end +// u001 "secret" pal protection +// cpu tries to read val from 0x9803 which is state machine pal +// written to on all tile ram access.. + +wire [7:0] u001_dout ; + +reg gfx_ram_wr_old; +always @(posedge clk_20M) gfx_ram_wr_old <= gfx_fg_ram0_wr | gfx_fg_ram1_wr; +wire secret_pal_clk_en = ~gfx_ram_wr_old & (gfx_fg_ram0_wr | gfx_fg_ram1_wr); + +secret_pal u001 +( + .clk( clk_20M ), + .clk_en( secret_pal_clk_en ), + .din( cpu_dout ), + .dout( u001_dout ) +); + // first 256 bytes are attribute data // bit 7 of attr == MSB of tile // bit 6 tile flip diff --git a/Arcade_MiST/Universal MrDo/rtl/secret_pal.v b/Arcade_MiST/Universal MrDo/rtl/secret_pal.v new file mode 100644 index 00000000..36c8355d --- /dev/null +++ b/Arcade_MiST/Universal MrDo/rtl/secret_pal.v @@ -0,0 +1,79 @@ + +// PAL16R6 (IC U001) + +// no feedback used so a 128 byte lookup table could work too. + +module secret_pal +( + input clk, + input clk_en, + input [7:0] din, + output [7:0] dout +); + +wire [9:2] i ; +reg [19:12] r ; + +// data bus d7 (msb) is pin 2 so reverse input bit order +assign i = {din[0],din[1],din[2],din[3],din[4],din[5],din[6],din[7]}; + +assign dout = r ; + +wire t1 = i[2] & ~i[3] & i[4] & ~i[5] & ~i[6] & ~i[8] & i[9] ; +wire t2 = ~i[2] & ~i[3] & i[4] & i[5] & ~i[6] & i[8] & ~i[9] ; +wire t3 = i[2] & i[3] & ~i[4] & ~i[5] & i[6] & ~i[8] & i[9] ; +wire t4 = ~i[2] & i[3] & i[4] & ~i[5] & i[6] & i[8] & i[9] ; + + +always @(posedge clk) begin + + if (clk_en) begin + // pal output is registered clocked by pin 1 connected to (TRAM WE) $8800-$8fff + // pal OE is enabled by reading address $9803 (SECRE) + + r[12] <= 0; + + // /rf13 := i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 + r[13] <= ~ ( t1 ); + + // /rf14 := /i2 & /i3 & i4 & i5 & /i6 & i8 & /i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 + r[14] <= ~ ( t2 | t1 ); + + // /rf15 := i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 + r[15] <= ~ ( t3 | t1 ); + + // /rf16 := i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 + r[16] <= ~ ( t1 ); + + // /rf17 := i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 + r[17] <= ~ ( t3 | t1 ); + + // /rf18 := /i2 & i3 & i4 & /i5 & i6 & i8 & i9 + i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 + r[18] <= ~ ( t4 | t3 ); + + r[19] <= 0; + end +end + +endmodule +/* + +/rf13 := i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 +rf13.oe = OE + +/rf14 := /i2 & /i3 & i4 & i5 & /i6 & i8 & /i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 +rf14.oe = OE + +/rf15 := i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 +rf15.oe = OE + +/rf16 := i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 +rf16.oe = OE + +/rf17 := i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 + i2 & /i3 & i4 & /i5 & /i6 & /i8 & i9 +rf17.oe = OE + +/rf18 := /i2 & i3 & i4 & /i5 & i6 & i8 & i9 + i2 & i3 & /i4 & /i5 & i6 & /i8 & i9 +rf18.oe = OE + +*/ \ No newline at end of file