diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qpf b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.qpf similarity index 97% rename from Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qpf rename to Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.qpf index bbd04726..81af7a3d 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qpf +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.qpf @@ -27,4 +27,4 @@ DATE = "14:59:16 November 16, 2017" # Revisions -PROJECT_REVISION = "Centipede" \ No newline at end of file +PROJECT_REVISION = "Centiped" \ No newline at end of file diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qsf b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.qsf similarity index 94% rename from Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qsf rename to Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.qsf index ed46cc58..41271f8d 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.qsf +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.qsf @@ -145,21 +145,17 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/cent.stp set_global_assignment -name SYSTEMVERILOG_FILE rtl/Centipede_MiST.sv set_global_assignment -name VERILOG_FILE rtl/centipede.v set_global_assignment -name VERILOG_FILE rtl/pf_ram.v -set_global_assignment -name VHDL_FILE rtl/roms/F7.vhd -set_global_assignment -name VHDL_FILE rtl/roms/HJ7.vhd -set_global_assignment -name VHDL_FILE rtl/roms/PROG.vhd -set_global_assignment -name VHDL_FILE rtl/roms/P4.vhd set_global_assignment -name VHDL_FILE rtl/spram.vhd set_global_assignment -name VHDL_FILE rtl/dpram.vhd set_global_assignment -name VHDL_FILE rtl/pll.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/POKEY.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/matoro.sv set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip -set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/Sound/Pokey/POKEY.sv -set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/Sound/Pokey/matoro.sv set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/cent.stp set_global_assignment -name SIGNALTAP_FILE output_files/cent.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.sdc b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.sdc similarity index 87% rename from Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.sdc rename to Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.sdc index 1d0f7c84..69dc312a 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centipede.sdc +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/Centiped.sdc @@ -72,12 +72,12 @@ create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_port # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] -set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] +set_input_delay -add_delay -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] #************************************************************** # Set Output Delay diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/README.txt b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/README.txt index 126df0b2..be27738e 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/README.txt +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/README.txt @@ -1,15 +1,28 @@ Arcade: Centipede port to MiST by Gehstock 24 November 2018 --- --- - Only controls and OSD are rotated on Video output. +Millipede added by Gyorgy Szombathelyi - Keyboard inputs : +April 2021 - ESC : Coin/Start Player --- - SPACE : Fire or Fire Button --- - ARROW KEYS : Movements \ No newline at end of file +-- +-- +-- Usage: +-- - Create ROM and ARC files from the MRA files using the MRA utility. +-- Example: mra -A -z /path/to/mame/roms Centipede.mra +-- - Copy the ROM files to the root of the SD Card +-- - Copy the RBF and ARC files to the same folder on the SD Card +-- +-- MRA utility: https://github.com/sebdel/mra-tools-c/ +-- + +-- Only controls and OSD are rotated on Video output. + +-- Keyboard inputs : + +-- ESC : Coin/Start Player +-- +-- CTRL : Fire or Fire Button +-- +-- ARROW KEYS : Movements \ No newline at end of file diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede (revision 4).mra b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede (revision 4).mra new file mode 100644 index 00000000..90f3d924 --- /dev/null +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede (revision 4).mra @@ -0,0 +1,38 @@ + + Centipede (revision 4) + 0220 + centiped + 20200430141713 + 1980 + Atari + Maze / Bugs + Maze / Centipede + Maze / Spiders + centiped + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede.mra b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede.mra new file mode 100644 index 00000000..9b7a0dcc --- /dev/null +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Centipede.mra @@ -0,0 +1,37 @@ + + Centipede (revision 3) + 0218 + centiped3 + 20200225084106 + 1980 + Atari + Maze / Bugs + Maze / Centipede + Maze / Spiders + centiped + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Millipede.mra b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Millipede.mra new file mode 100644 index 00000000..52decf04 --- /dev/null +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/meta/Millipede.mra @@ -0,0 +1,33 @@ + + Millipede + 0218 + milliped + 20200225084106 + 1980 + Atari + Maze / Bugs + Maze / Centipede + Maze / Spiders + centiped + + + + + + + 1 + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede_MiST.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede_MiST.sv index 8929dc6a..e4e2a64f 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede_MiST.sv +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/Centipede_MiST.sv @@ -40,16 +40,13 @@ module Centipede_MiST `include "rtl\build_id.v" localparam CONF_STR = { - "Centipede;;", + "CENTIPED;;", "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", "O5,Blend,Off,On;", "O7,Test,Off,On;", - "O89,Language,English,German,French,Spanish;", - "OAB,Lives,2,3,4,5;", - "OCD,Bonus Life,10000,12000,15000,20000;", - "OE,Difficulty,Hard,Easy;", - "OF,Credit minimum,1,2;", + "DIP;", + "R64,Save highscores;", "T0,Reset;", "V,v1.50.",`BUILD_DATE }; @@ -60,11 +57,13 @@ wire blend = status[5]; wire joyswap = status[6]; wire service = status[7]; +wire milliped = core_mod[0]; + wire [15:0] dipsw; assign dipsw[ 7:0] = status[15:8]; assign dipsw[15:8] = 8'h01; -assign LED = 1; +assign LED = ~(ioctl_downl | ioctl_upl); assign AUDIO_R = AUDIO_L; wire clk_24, clk_12, clk_100mhz; @@ -76,29 +75,55 @@ pll pll( .c2(clk_12), .c4(clk_100mhz) ); - + wire [31:0] status; wire [1:0] buttons; wire [1:0] switches; wire [7:0] joystick_0; wire [7:0] joystick_1; wire scandoublerD; +wire [7:0] core_mod; wire ypbpr; wire no_csync; wire key_pressed; wire [7:0] key_code; wire key_strobe; -wire [7:0] RGB; +wire [7:0] RGB; wire hs, vs, vb, hb; -reg blankn; +wire blankn = ~(hb | vb); wire [3:0] audio; -always @(posedge clk_12) blankn <= ~(hb | vb); +wire ioctl_downl; +wire ioctl_upl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; +wire [7:0] ioctl_din; + +data_io data_io( + .clk_sys ( clk_12 ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_DI ( SPI_DI ), + .SPI_DO ( SPI_DO ), + .ioctl_download( ioctl_downl ), + .ioctl_upload ( ioctl_upl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ), + .ioctl_din ( ioctl_din ) +); + +reg reset; +always @(posedge clk_12) reset <= status[0] | buttons[1] | ioctl_downl; centipede centipede( .clk_100mhz(clk_100mhz), .clk_12mhz(clk_12), - .reset(status[0] | buttons[1]), + .reset(reset), + .milli(milliped), .playerinput_i(~{ 1'b0, 1'b0, m_coin1, service, 1'b0, 1'b0, m_two_players, m_one_player, m_fireB, m_fireA }), .trakball_i(), .joystick_i(~{m_right , m_left, m_down, m_up, m_right , m_left, m_down, m_up}), @@ -109,17 +134,26 @@ centipede centipede( .vsync_o(vs), .hblank_o(hb), .vblank_o(vb), - .audio_o(audio) + .audio_o(audio), + // ROM download + .dl_addr(ioctl_addr[14:0]), + .dl_data(ioctl_dout), + .dl_we(ioctl_wr && ioctl_index == 0), + // High score table save-load + .hsram_addr(ioctl_addr[5:0]), + .hsram_dout(ioctl_din), + .hsram_din(ioctl_dout), + .hsram_we(ioctl_wr && ioctl_index == 8'hff) ); - + mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( .clk_sys ( clk_24 ), .SPI_SCK ( SPI_SCK ), .SPI_SS3 ( SPI_SS3 ), .SPI_DI ( SPI_DI ), - .R (blankn ? RGB[2:0] : 0), - .G (blankn ? RGB[5:3] : 0), - .B (blankn ? RGB[7:6] : 0), + .R (blankn ? RGB[2:0] : 0), + .G (blankn ? RGB[5:3] : 0), + .B (blankn ? RGB[7:6] : 0), .HSync ( hs ), .VSync ( vs ), .VGA_R ( VGA_R ), @@ -127,14 +161,15 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( .VGA_B ( VGA_B ), .VGA_VS ( VGA_VS ), .VGA_HS ( VGA_HS ), + .scanlines ( scanlines ), .rotate ( { 1'b0, rotate } ), .ce_divider ( 1'b1 ), .blend ( blend ), .scandoubler_disable(scandoublerD ), .no_csync ( no_csync ), .ypbpr ( ypbpr ) - ); - + ); + user_io #( .STRLEN(($size(CONF_STR)>>3))) user_io( @@ -146,17 +181,18 @@ user_io( .SPI_MOSI (SPI_DI ), .buttons (buttons ), .switches (switches ), - .scandoubler_disable (scandoublerD ), + .scandoubler_disable (scandoublerD ), .ypbpr (ypbpr ), .no_csync (no_csync ), + .core_mod (core_mod ), .key_strobe (key_strobe ), .key_pressed (key_pressed ), .key_code (key_code ), .joystick_0 (joystick_0 ), .joystick_1 (joystick_1 ), .status (status ) - ); - + ); + dac #( .C_bits(15)) dac ( @@ -165,7 +201,7 @@ dac ( .dac_i({2{audio,audio}}), .dac_o(AUDIO_L) ); - + wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF; wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F; wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players; @@ -178,12 +214,12 @@ arcade_inputs inputs ( .joystick_0 ( joystick_0 ), .joystick_1 ( joystick_1 ), .rotate ( rotate ), - .orientation ( 2'b01 ), + .orientation ( 2'b01 ), .joyswap ( joyswap ), - .oneplayer ( 1'b1 ), + .oneplayer ( 1'b1 ), .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ), .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ), .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ) -); +); endmodule diff --git a/common/Sound/Pokey/POKEY.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/POKEY.sv similarity index 100% rename from common/Sound/Pokey/POKEY.sv rename to Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/POKEY.sv diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/centipede.v b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/centipede.v index 541a2069..67f79219 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/centipede.v +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/centipede.v @@ -14,11 +14,17 @@ // The game code also relies on the pokey's random number generation working correctly and caused me to // do some debugging of the pokey code I was using. // Edit: Changed 2018 Gehstock +// +// György Szombathelyi 04/2021 +// - Made it synchronous (still left some combinatorial async resets for an exercise to the reader) +// - Fixed the high score RAM +// - Added Millipede module centipede( input clk_100mhz, input clk_12mhz, input reset, + input milli, input [9:0] playerinput_i, input [7:0] trakball_i, input [7:0] joystick_i, @@ -31,7 +37,16 @@ module centipede( output vsync_o, output hblank_o, output vblank_o, - output [3:0] audio_o + output [3:0] audio_o, + + input [14:0] dl_addr, + input [7:0] dl_data, + input dl_we, + + input [5:0] hsram_addr, + output [7:0] hsram_dout, + input [7:0] hsram_din, + input hsram_we ); // @@ -44,16 +59,16 @@ module centipede( reg phi0a; // - wire rom_n; - wire ram0_n; - wire steerclr_n, watchdog_n, out0_n, irqres_n; - wire pokey_n, pokey2_n, swrd_n, pf_n; - wire coloram_n, ea_read_n, ea_ctrl_n, ea_addr_n; - wire in0_n, in1_n; + reg rom_n; + reg ram0_n; + reg steerclr_n, watchdog_n, out0_n, irqres_n; + reg pokey_n, pokey2_n, swrd_n, pf_n; + reg coloram_n, ea_read_n, ea_ctrl_n, ea_addr_n; + reg in0_n, in1_n; - wire pframrd_n; - wire pfwr3_n, pfwr2_n, pfwr1_n, pfwr0_n; - wire pfrd3_n, pfrd2_n, pfrd1_n, pfrd0_n; + reg pframrd_n; + reg pfwr3_n, pfwr2_n, pfwr1_n, pfwr0_n; + reg pfrd3_n, pfrd2_n, pfrd1_n, pfrd0_n; wire [9:0] adecode; wire pac_n; @@ -92,13 +107,13 @@ module centipede( wire s_4h_n_en; wire s_256hd_n; wire s_256h2d_n; - wire vblankd_n; + wire vblankd_n; wire s_6_12; - - reg s_256h2d; - reg s_256hd; - reg vblankd; - + + reg s_256h2d; + reg s_256hd; + reg vblankd; + wire pload_n; wire write_n; wire brw_n; @@ -125,15 +140,15 @@ module centipede( wire pf_addr_stamp; wire [31:0] pfd; - reg [29:16] pfd_hold; - reg [29:16] pfd_hold2; + reg [31:16] pfd_hold; + reg [31:16] pfd_hold2; reg [1:0] gry; wire [1:0] y; reg [1:0] mr; wire [7:0] line_ram_addr; - reg [1:0] line_ram[0:255]; + reg [3:0] line_ram[0:255]; reg [7:0] line_ram_ctr; wire line_ram_ctr_load; wire line_ram_ctr_clr; @@ -147,7 +162,7 @@ module centipede( wire [7:0] pf_rom1_out, pf_rom0_out; wire [7:0] pf_rom1_out_rev, pf_rom0_out_rev; - reg [7:0] pic; + reg [7:0] pic, picD; // @@ -160,22 +175,14 @@ module centipede( reg hs; wire hs_set; - wire hs_addr_clk; - wire hs_ctrl_clk; - // wire comp_sync; - reg [3:0] rgbi; - wire [3:0] coloram_out; - wire [3:0] coloram_rgbi; + reg [7:0] rgbi; + wire [7:0] coloram_out; + wire [7:0] coloram_rgbi; wire coloram_w_n; reg coloren; - wire [1:0] rama_sel; - wire [1:0] rama_hi; - wire [1:0] rama_lo; - wire [3:0] rama; - wire [3:0] audio; // wire mob_n; @@ -189,17 +196,19 @@ module centipede( wire [7:0] switch_out; wire flip; + wire cntrlsel; wire coin_ctr_r_drive, coin_ctr_c_drive, coin_ctr_l_drive; wire [7:0] playerin_out; wire [7:0] pokey_out; + wire [7:0] pokey2_out; reg [11:0] h_counter; reg [7:0] v_counter; wire v_counter_reset; initial h_counter = 0; - always @(posedge s_12mhz or posedge reset) + always @(posedge s_12mhz) if (reset) h_counter <= 0; else @@ -239,7 +248,7 @@ module centipede( assign v_counter_reset = reset | ~vreset == 0; - always @(posedge s_12mhz or posedge reset) + always @(posedge s_12mhz) if (reset) v_counter <= 0; else if (s_256h_n_en) @@ -254,77 +263,127 @@ module centipede( assign s_4v = v_counter[2]; assign s_8v = v_counter[3]; assign s_16v = v_counter[4]; - assign s_16v_en = s_256h_n_en & v_counter[4:0] == 5'b01111; + assign s_16v_en = s_256h_n_en & v_counter[4:0] == 5'b01111; assign s_32v = v_counter[5]; assign s_64v = v_counter[6]; assign s_128v = v_counter[7]; + assign mob_n = ~((s_256h_n & s_256hd) | (s_256h2d_n & s_256hd)) | milli; + + assign blank_clk = ~s_12mhz & (h_counter[3:0] == 4'b1111); + + always @(posedge s_12mhz) + if (reset) + begin + s_256h2d <= 1'b0; + s_256hd <= 1'b0; + vblankd <= 1'b0; + end + else if (h_counter[3:0] == 4'b1111) + begin + s_256h2d <= s_256hd; + s_256hd <= s_256h; + vblankd <= vblank; + end + + assign s_256h2d_n = ~s_256h2d; + assign s_256hd_n = ~s_256hd; + assign vblankd_n = ~vblankd; assign vprom_addr = {vblank, s_128v, s_64v, s_32v, s_8v, s_4v, s_2v, s_1v}; -P4 P4( - .clk(s_12mhz), - .addr(vprom_addr), - .data(vprom_out) - ); + dpram #( + .addr_width_g(8), + .data_width_g(4)) + P4( + .clk_a_i(s_12mhz), + .clk_b_i(s_12mhz), + .we_i(1'b0), + .addr_a_i(vprom_addr), + .data_a_o(vprom_out), + .data_a_i(), + .addr_b_i(dl_addr[7:0]), + .data_b_o(), + .data_b_i(dl_data[3:0]), + .we_b_i(dl_we && dl_addr[14:8] == 7'b1010000) + ); -always @(posedge s_12mhz or posedge reset) + always @(posedge s_12mhz) if (reset) vprom_reg <= 0; - else if (s_256h_n_en) - vprom_reg <= vprom_out; + else if (s_256h_n_en) + vprom_reg <= vprom_out; -assign vsync = vprom_reg[0]; -assign vreset = vprom_reg[2]; -assign hs_set = reset | ~s_256h_n; + assign vsync = vprom_reg[0]; + assign vreset = vprom_reg[2]; + assign hs_set = reset | ~s_256h_n; -always @(posedge s_12mhz or posedge hs_set) - if (hs_set) - hs <= 1; - else if (s_32h_en) - hs <= s_64h; + always @(posedge s_12mhz or posedge hs_set) + if (hs_set) + hs <= 1; + else if (s_32h_en) + hs <= s_64h; -assign hsync_reset = reset | hs; + assign hsync_reset = reset | hs; -always @(posedge s_12mhz or posedge hsync_reset) - if (hsync_reset) - hsync <= 0; - else if (s_8h_en) - hsync <= s_32h; + always @(posedge s_12mhz or posedge hsync_reset) + if (hsync_reset) + hsync <= 0; + else if (s_8h_en) + hsync <= s_32h; -always @(posedge s_12mhz) - if (reset) + always @(posedge s_12mhz) + if (reset) coloren <= 0; else if (s_6mhz_en) coloren <= s_256hd; -assign s_6_12 = ~(s_6mhz & s_12mhz); -reg xxx1; + assign s_6_12 = ~(s_6mhz & s_12mhz); + reg xxx1; -always @(posedge s_12mhz)//s_6_12) - if (reset) - xxx1 <= 0; - else if (s_6mhz_en) - xxx1 <= coloren; + always @(posedge s_12mhz)//s_6_12) + if (reset) + xxx1 <= 0; + else if (s_6mhz_en) + xxx1 <= coloren; -assign vblank = vprom_reg[3]; -assign hblank = ~(xxx1 | coloren); + reg hblank1_n; + always @(posedge s_12mhz) + if (reset) + hblank1_n <= 0; + else if (s_6mhz_n_en) + hblank1_n <= s_256hd; -PROG PROG ( - .clk(s_12mhz), - .addr(ab[12:0]), - .data(rom_out[7:0]) - ); - -spram #( - .addr_width_g(10), - .data_width_g(8)) -ram( - .address(ab[9:0]), - .clock(s_12mhz), - .wren(~write_n & ~ram0_n), - .data(db_out[7:0]), - .q(ram_out[7:0]) - ); + + assign vblank = vprom_reg[3]; + //assign hblank = ~(xxx1 | coloren); + assign hblank = ~hblank1_n; + + dpram #( + .addr_width_g(14), + .data_width_g(8)) + PROG( + .clk_a_i(s_12mhz), + .clk_b_i(s_12mhz), + .we_i(1'b0), + .addr_a_i(ab[13:0]), + .data_a_o(rom_out[7:0]), + .data_a_i(), + .addr_b_i(dl_addr[13:0]), + .data_b_o(), + .data_b_i(dl_data), + .we_b_i(dl_we && !dl_addr[14]) + ); + + spram #( + .addr_width_g(10), + .data_width_g(8)) + ram( + .address(ab[9:0]), + .clock(s_12mhz), + .wren(~write_n & ~ram0_n), + .data(db_out[7:0]), + .q(ram_out[7:0]) + ); wire irq_n; @@ -339,7 +398,7 @@ ram( assign irq_n = irq; - always @(posedge s_12mhz or posedge reset) + always @(posedge s_12mhz) if (reset) phi0a <= 1'b0; else if (s_1h_en) @@ -366,33 +425,30 @@ ram( end assign mpu_clk = s_6mhz; - assign mpu_reset_n = ~mpu_reset; - -assign phi2 = ~phi0; -T65 T65( - .Mode("00"), - .Res_n(mpu_reset_n), - .Enable(phi0_en), - .Clk(s_12mhz), - .Rdy(1'b1), - .Abort_n(1'b1), - .IRQ_n(irq_n), - .NMI_n(1'b1), - .SO_n(1'b1), - .R_W_n(rw_n), - .A(ab), - .DI(db_in[7:0]), - .DO(db_out[7:0]) - ); + assign mpu_reset_n = ~mpu_reset; + assign phi2 = ~phi0; + T65 T65( + .Mode("00"), + .Res_n(mpu_reset_n), + .Enable(phi0_en), + .Clk(s_12mhz), + .Rdy(1'b1), + .Abort_n(1'b1), + .IRQ_n(irq_n), + .NMI_n(1'b1), + .SO_n(1'b1), + .R_W_n(rw_n), + .A(ab), + .DI(db_in[7:0]), + .DO(db_out[7:0]) + ); // Address Decoder assign write_n = ~(phi2 & ~rw_n); assign brw_n = ~rw_n; - assign rom_n = brw_n | ~ab[13]; - assign adecode = (ab[13:10] == 4'b0000) ? 10'b1111111110 : (ab[13:10] == 4'b0001) ? 10'b1111111101 : @@ -406,74 +462,283 @@ T65 T65( (ab[13:10] == 4'b1001) ? 10'b0111111111 : 10'b1111111111; -// assign write2_n = ~(s_6mhz & ~write_n); - reg write2_n; - always @(posedge s_12mhz) - if (reset) - write2_n <= 0; - else if (s_6mhz_en) - write2_n <= write_n; - - assign steerclr_n = adecode[9] | write2_n; - assign watchdog_n = adecode[8] | write2_n; - assign out0_n = adecode[7] | write2_n; - assign irqres_n = (adecode[6] | write2_n) & mpu_reset_n; + wire write2_n = ~(s_6mhz & ~write_n); - assign coloram_n = (adecode[5] | ab[9])/* | pac_n*/; + // For millipede + wire mos_n = ab[14:12] != 3'b000; + wire io_n = ab[14:12] != 3'b010; + wire inputs_n = {io_n, ab[11:10]} != 3'b000; + wire outputs_n = {io_n, ab[11:10]} != 3'b001; - assign pokey_n = adecode[4]; - assign pokey2_n = adecode[3]; + always @(*) begin + if (milli) begin + rom_n = brw_n | ~ab[14]; - assign in0_n = adecode[3] | ab[1]; - assign in1_n = adecode[3] | ~ab[1]; + steerclr_n = 1;//adecode[9] | write2_n; + + in0_n = {inputs_n, ab[5:4]} != 3'b000; + in1_n = {inputs_n, ab[5:4]} != 3'b001; + ea_read_n = {inputs_n, ab[5:4]} != 3'b011; - assign swrd_n = adecode[2]; - assign pf_n = adecode[1]; - assign ram0_n = adecode[0]; + swrd_n = 1;//adecode[2]; + pf_n = ab[14:12] != 3'b001; // _scram + ram0_n = {mos_n, ab[11:10]} != 3'b000; + pokey_n = {mos_n, ab[11:10]} != 3'b001; + pokey2_n = {mos_n, ab[11:10]} != 3'b010; + + coloram_n = {outputs_n | write_n, ab[9:7]} != 4'b0001; + out0_n = {outputs_n | write_n, ab[9:7]} != 4'b0010; + irqres_n = {outputs_n | write_n, ab[9:7]} != 4'b0100 & mpu_reset_n; + watchdog_n = {outputs_n | write_n, ab[9:7]} != 4'b0101; + ea_ctrl_n = {outputs_n | write_n, ab[9:7]} != 4'b0110; + ea_addr_n = {outputs_n | write_n, ab[9:7]} != 4'b0111; - assign {ea_read_n, ea_ctrl_n, ea_addr_n} = - ({~ab[9]|adecode[5], ab[8:7]} == 3'b000) ? 3'b110 : - ({~ab[9]|adecode[5], ab[8:7]} == 3'b001) ? 3'b101 : - ({~ab[9]|adecode[5], ab[8:7]} == 3'b010) ? 3'b011 : - 3'b111; - assign pframrd_n = pf_n | brw_n; + pframrd_n = pf_n | brw_n; - assign {pfwr3_n, pfwr2_n, pfwr1_n, pfwr0_n} = + {pfwr3_n, pfwr2_n, pfwr1_n, pfwr0_n} = ({pf_n, write_n, ab[5:4]} == 4'b0000) ? 4'b1110 : ({pf_n, write_n, ab[5:4]} == 4'b0001) ? 4'b1101 : ({pf_n, write_n, ab[5:4]} == 4'b0010) ? 4'b1011 : ({pf_n, write_n, ab[5:4]} == 4'b0011) ? 4'b0111 : 4'b1111; - assign {pfrd3_n, pfrd2_n, pfrd1_n, pfrd0_n} = + {pfrd3_n, pfrd2_n, pfrd1_n, pfrd0_n} = (ab[5:4] == 2'b00) ? 4'b1110 : (ab[5:4] == 2'b01) ? 4'b1101 : (ab[5:4] == 2'b10) ? 4'b1011 : (ab[5:4] == 2'b11) ? 4'b0111 : 4'b1111; + end else begin + rom_n = brw_n | ~ab[13]; + + steerclr_n = adecode[9] | write2_n; + watchdog_n = adecode[8] | write2_n; + out0_n = adecode[7] | write2_n; + irqres_n = (adecode[6] | write2_n) & mpu_reset_n; + + coloram_n = (adecode[5] | ab[9])/* | pac_n*/; + + pokey_n = adecode[4]; + pokey2_n = 1;// adecode[3]; + + in0_n = adecode[3] | ab[1]; + in1_n = adecode[3] | ~ab[1]; + + swrd_n = adecode[2]; + pf_n = adecode[1]; + ram0_n = adecode[0]; + + {ea_read_n, ea_ctrl_n, ea_addr_n} = + ({~ab[9]|adecode[5], ab[8:7]} == 3'b000) ? 3'b110 : + ({~ab[9]|adecode[5], ab[8:7]} == 3'b001) ? 3'b101 : + ({~ab[9]|adecode[5], ab[8:7]} == 3'b010) ? 3'b011 : + 3'b111; + pframrd_n = pf_n | brw_n; + + {pfwr3_n, pfwr2_n, pfwr1_n, pfwr0_n} = + ({pf_n, write_n, ab[5:4]} == 4'b0000) ? 4'b1110 : + ({pf_n, write_n, ab[5:4]} == 4'b0001) ? 4'b1101 : + ({pf_n, write_n, ab[5:4]} == 4'b0010) ? 4'b1011 : + ({pf_n, write_n, ab[5:4]} == 4'b0011) ? 4'b0111 : + 4'b1111; + + {pfrd3_n, pfrd2_n, pfrd1_n, pfrd0_n} = + (ab[5:4] == 2'b00) ? 4'b1110 : + (ab[5:4] == 2'b01) ? 4'b1101 : + (ab[5:4] == 2'b10) ? 4'b1011 : + (ab[5:4] == 2'b11) ? 4'b0111 : + 4'b1111; + end + end // - assign mob_n = ~((s_256h_n & s_256hd) | (s_256h2d_n & s_256hd)); + assign db_in = + ~rom_n ? rom_out : + ~ram0_n ? ram_out : + ~coloram_n ? coloram_out : + ~pframrd_n ? pf_out[7:0] : + ~ea_read_n ? hs_out : + ~in0_n ? playerin_out : + ~in1_n ? joystick_out : + ~swrd_n ? switch_out : + ~pokey_n ? pokey_out : + ~pokey2_n ? pokey2_out : + 8'b0; + // + // High Score Memory Circuitry - assign blank_clk = ~s_12mhz & (h_counter[3:0] == 4'b1111); + wire hs_addr_en = ~ea_addr_n & ~write2_n; + wire hs_ctrl_en = ~ea_ctrl_n & ~write2_n; - always @(posedge blank_clk or posedge reset) + always @(posedge s_12mhz) begin + if (hs_addr_en) begin + hs_addr <= ab[5:0]; + hs_data <= db_out[7:0]; + end + if (hs_ctrl_en) hs_ctrl <= db_out[3:0]; + end + + dpram #( + .addr_width_g(6), + .data_width_g(8)) + hs_ram( + .clk_a_i(s_12mhz), + .clk_b_i(s_12mhz), + .we_i(hs_ctrl[1] & ~hs_ctrl[2]), + .addr_a_i(hs_addr), + .data_a_o(hs_out), + .data_a_i(hs_data), + .addr_b_i(hsram_addr), + .data_b_o(hsram_dout), + .data_b_i(hsram_din), + .we_b_i(hsram_we) + ); + + // Joystick Circuitry + wire js1_right, js1_left, js1_down, js1_up; + wire js2_right, js2_left, js2_down, js2_up; + + assign js1_right = joystick_i[7]; + assign js1_left = joystick_i[6]; + assign js1_down = joystick_i[5]; + assign js1_up = joystick_i[4]; + assign js2_right = joystick_i[3]; + assign js2_left = joystick_i[2]; + assign js2_down = joystick_i[1]; + assign js2_up = joystick_i[0]; + + wire [7:0] joystick_out_centi = ab[0] ? + { js1_right, js1_left, js1_down, js1_up, js2_right, js2_left, js2_down, js2_up } : + { dir2, 3'b0, trb }; + + wire [7:0] joystick_out_milli = { + ab[0] ? { self_test, 1'b0, cocktail, 1'b1 } : { coin_r, coin_l, coin_c, slam }, + cntrlsel ? { js2_down, js2_up, js2_right, js2_left } : { js1_up, js1_down, js1_left, js1_right } }; + + assign joystick_out = milli ? joystick_out_milli : joystick_out_centi; + + // Option Input Circuitry + + assign switch_out = ab[0] ? + sw2_i : + sw1_i; + + // Player Input Circuitry + wire coin_r, coin_c, coin_l, self_test; + wire cocktail, slam, start1, start2, fire2, fire1; + + assign coin_r = coin_ctr_r_drive ? coin_ctr_r_drive : playerinput_i[9]; + assign coin_c = coin_ctr_c_drive ? coin_ctr_c_drive : playerinput_i[8]; + assign coin_l = coin_ctr_l_drive ? coin_ctr_l_drive : playerinput_i[7]; + assign self_test = playerinput_i[6]; + assign cocktail = playerinput_i[5]; + assign slam = playerinput_i[4]; + assign start2 = playerinput_i[3]; + assign start1 = playerinput_i[2]; + assign fire2 = playerinput_i[1]; + assign fire1 = playerinput_i[0]; + + wire [7:0] playerin_out0; + wire [7:0] playerin_out1; + + assign playerin_out1 = milli ? + { dir2, 1'b0, start2, fire2, sw1_i[7:4] } : + { coin_r, coin_c, coin_l, slam, fire2, fire1, start2, start1 }; + + assign playerin_out0 = milli ? + { dir1, vblank, start1, fire1, sw1_i[3:0] } : + { dir1, vblank, self_test, cocktail, tra }; + + assign playerin_out = ab[0] ? playerin_out1 : playerin_out0; + + // Coin Counter Output + reg [7:0] cc_latch; + + always @(posedge s_12mhz) if (reset) - begin - s_256h2d <= 1'b0; - s_256hd <= 1'b0; - vblankd <= 1'b0; - end - else - begin - s_256h2d <= s_256hd; - s_256hd <= s_256h; - vblankd <= vblank; - end + cc_latch <= 0; + else if (s_6mhz_en) + if (~out0_n) + cc_latch[ ab[2:0] ] <= db_out[7]; - assign s_256h2d_n = ~s_256h2d; - assign s_256hd_n = ~s_256hd; - assign vblankd_n = ~vblankd; + assign flip = milli ? cc_latch[6] : cc_latch[7]; + assign cntrlsel = milli ? cc_latch[6] : 1'b0; + assign led_o[4] = milli ? 1'b0 : cc_latch[6]; + assign led_o[3] = milli ? 1'b0 : cc_latch[5]; + assign led_o[2] = cc_latch[4]; + assign led_o[1] = cc_latch[3]; + assign coin_ctr_r_drive = cc_latch[2]; + assign coin_ctr_c_drive = cc_latch[1]; + assign coin_ctr_l_drive = cc_latch[1]; + + // Mini-Trak Ball inputs + wire [3:0] tb_mux; + wire s_1_horiz_dir, s_1_horiz_ck, s_1_vert_dir, s_1_vert_ck; + wire s_2_horiz_dir, s_2_horiz_ck, s_2_vert_dir, s_2_vert_ck; + wire tb_h_dir, tb_h_ck, tb_v_dir, tb_v_ck; + reg tb_h_reg, tb_v_reg; + reg [3:0] tb_h_ctr, tb_v_ctr; + wire tb_h_ctr_clr, tb_v_ctr_clr; + + assign s_1_horiz_dir = trakball_i[7]; + assign s_2_horiz_dir = trakball_i[6]; + assign s_1_horiz_ck = trakball_i[5]; + assign s_2_horiz_ck = trakball_i[4]; + assign s_1_vert_dir = trakball_i[3]; + assign s_2_vert_dir = trakball_i[2]; + assign s_1_vert_ck = trakball_i[1]; + assign s_2_vert_ck = trakball_i[0]; + + assign tb_mux = flip ? + { s_1_horiz_dir, s_1_horiz_ck, s_1_vert_dir, s_1_vert_ck } : + { s_2_horiz_dir, s_2_horiz_ck, s_2_vert_dir, s_2_vert_ck }; + + assign tb_h_dir = tb_mux[3]; + assign tb_h_ck = tb_mux[2]; + assign tb_v_dir = tb_mux[1]; + assign tb_v_ck = tb_mux[0]; +/* + // H + always @(posedge tb_h_ck or posedge reset) + if (reset) + tb_h_reg <= 0; + else + tb_h_reg <= tb_h_dir; + + assign tb_h_ctr_clr = reset | ~steerclr_n; + + always @(posedge tb_h_ck or posedge tb_h_ctr_clr) + if (tb_h_ctr_clr) + tb_h_ctr <= 0; + else + if (tb_h_reg) + tb_h_ctr <= tb_h_ctr + 4'd1; + else + tb_h_ctr <= tb_h_ctr - 4'd1; + + // V + always @(posedge tb_v_ck or posedge reset) + if (reset) + tb_v_reg <= 0; + else + tb_v_reg <= tb_v_dir; + + assign tb_v_ctr_clr = reset | ~steerclr_n; + + always @(posedge tb_v_ck or posedge tb_v_ctr_clr) + if (tb_v_ctr_clr) + tb_v_ctr <= 0; + else + if (tb_v_reg) + tb_v_ctr <= tb_v_ctr + 4'd1; + else + tb_v_ctr <= tb_v_ctr - 4'd1; +*/ + assign tra = tb_h_ctr; + assign trb = tb_v_ctr; + assign dir1 = tb_h_reg; + assign dir2 = tb_v_reg; + // motion objects (vertical) @@ -520,12 +785,15 @@ T65 T65( // for debug only assign match_true = (~match_n & s_256h_n) && pfd != 0; + wire pic7 = milli ? !s_256h & pic[7] : pic[7]; - assign mga = { match_mux[3] ^ (pic[7] & s_256h_n), - match_mux[2] ^ pic[7], - match_mux[1] ^ pic[7], - match_mux[0] ^ pic[7] }; - + assign mga = { match_mux[3] ^ (pic7 & s_256h_n), + match_mux[2] ^ pic7, + match_mux[1] ^ pic7, + match_mux[0] ^ pic7 }; + + wire horrot = milli ? (!s_256h & pic[6]) : pic[6]; + wire mga10 = s_256h ? pic[6] : pic[0]; //--- // motion objects (horizontal) @@ -548,7 +816,7 @@ T65 T65( else /* posedge s_4h */ if (s_4h_en) - pfd_hold <= pfd[29:16]; + pfd_hold <= pfd[31:16]; // always @(posedge s_4h_n) // if (reset) @@ -562,7 +830,9 @@ T65 T65( /* posedge s_4h_n */ if (s_4h_n_en) pfd_hold2 <= pfd_hold; - + + reg [1:0] y_reg; + assign y[1] = // C7 (area == 2'b00) ? (s_256hd ? 1'b0 : gry[1]) : (area == 2'b01) ? (s_256hd ? 1'b0 : pfd_hold2[25]) : @@ -577,13 +847,16 @@ T65 T65( (area == 2'b11) ? (s_256hd ? 1'b0 : pfd_hold2[28]) : 1'b0; + assign mocbx[0] = (area == 2'b00) ? (s_256hd ? 1'b0 : mocb[0]) : pfd_hold2[30]; + assign mocbx[1] = (area == 2'b00) ? (s_256hd ? 1'b0 : mocb[1]) : pfd_hold2[31]; + assign line_ram_ctr_load = ~(pload_n | s_256h); assign line_ram_ctr_clr = ~(pload_n | ~(s_256h & s_256hd_n)); - always @(posedge s_6mhz) // A5-B5 + always @(posedge s_12mhz) // A5-B5 if (reset) line_ram_ctr <= 0; - else /*if (s_6mhz_en)*/ begin + else if (s_6mhz_en) begin if (line_ram_ctr_clr) line_ram_ctr <= 0; else if (line_ram_ctr_load) @@ -595,25 +868,26 @@ T65 T65( assign line_ram_addr = line_ram_ctr; always @(posedge s_12mhz) - if (~s_6mhz) line_ram[line_ram_addr] <= y; + if (~s_6mhz) line_ram[line_ram_addr] <= {mocbx, y}; - always @(posedge s_12mhz) - if (reset) + always @(negedge s_12mhz) + if (reset) begin mr <= 0; - else - mr <= line_ram[line_ram_addr]; + mocb_o <= 0; + end else + {mocb_o, mr} <= line_ram[line_ram_addr]; + reg [1:0] mocb, mocb_o; + wire [1:0] mocbx; - always @(posedge s_6mhz_n) - if (reset) - gry <= 0; - else - if (~mob_n) + always @(posedge s_12mhz, negedge mob_n) + if (~mob_n) gry <= 2'b00; - else/* if (s_6mhz_n_en)*/ + else if (s_6mhz_n_en) begin gry <= mr; - + mocb <= mocb_o; + end // playfield multiplexer // The playfield multiplexer receives playfield data from the pf memory @@ -634,26 +908,48 @@ T65 T65( // else // pic <= pf[7:0]; always @(posedge s_12mhz) - if (reset) - pic <= 0; - else if (s_4h_en) - pic <= pf[7:0]; - -F7 F7( - .clk(s_12mhz), - .addr(pf_rom0_addr), - .data(pf_rom0_out) - ); - -HJ7 HJ7( - .clk(s_12mhz), - .addr(pf_rom1_addr), - .data(pf_rom1_out) - ); + if (reset) + pic <= 0; + else if (s_4h_en) + pic <= pf[7:0]; + else if (s_4h_n_en) + picD <= pic; + + dpram #( + .addr_width_g(11), + .data_width_g(8)) + F7( + .clk_a_i(s_12mhz), + .clk_b_i(s_12mhz), + .we_i(1'b0), + .addr_a_i(pf_rom0_addr), + .data_a_o(pf_rom0_out), + .data_a_i(), + .addr_b_i(dl_addr[10:0]), + .data_b_o(), + .data_b_i(dl_data), + .we_b_i(dl_we && dl_addr[14:11] == 4'b1000) + ); + + dpram #( + .addr_width_g(11), + .data_width_g(8)) + HJ7( + .clk_a_i(s_12mhz), + .clk_b_i(s_12mhz), + .we_i(1'b0), + .addr_a_i(pf_rom1_addr), + .data_a_o(pf_rom1_out), + .data_a_i(), + .addr_b_i(dl_addr[10:0]), + .data_b_o(), + .data_b_i(dl_data), + .we_b_i(dl_we && dl_addr[14:11] == 4'b1001) + ); // a guess, based on millipede schematics wire pf_romx_haddr; - assign pf_romx_haddr = s_256h_n & pic[0]; + assign pf_romx_haddr = milli ? mga10 : s_256h_n & pic[0]; assign pf_rom1_addr = { pf_romx_haddr, s_256h, pic[5:1], mga }; assign pf_rom0_addr = { pf_romx_haddr, s_256h, pic[5:1], mga }; assign pf_rom0_out_rev = { pf_rom0_out[0], pf_rom0_out[1], pf_rom0_out[2], pf_rom0_out[3], @@ -662,8 +958,8 @@ HJ7 HJ7( assign pf_rom1_out_rev = { pf_rom1_out[0], pf_rom1_out[1], pf_rom1_out[2], pf_rom1_out[3], pf_rom1_out[4], pf_rom1_out[5], pf_rom1_out[6], pf_rom1_out[7] }; - assign pf_mux0 = match_n ? 8'b0 : (pic[6] ? pf_rom0_out_rev : pf_rom0_out); - assign pf_mux1 = match_n ? 8'b0 : (pic[6] ? pf_rom1_out_rev : pf_rom1_out); + assign pf_mux0 = match_n ? 8'b0 : (horrot ? pf_rom0_out_rev : pf_rom0_out); + assign pf_mux1 = match_n ? 8'b0 : (horrot ? pf_rom1_out_rev : pf_rom1_out); always @(posedge s_12mhz) if (reset) @@ -689,19 +985,6 @@ HJ7 HJ7( else if (s_6mhz_n_en) area <= { pf_shift1[7], pf_shift0[7] }; - // - assign db_in = - ~rom_n ? rom_out : - ~ram0_n ? ram_out : - ~coloram_n ? { 4'b0, coloram_out } : - ~pframrd_n ? pf_out[7:0] : - ~ea_read_n ? hs_out : - ~in0_n ? playerin_out : - ~in1_n ? joystick_out : - ~swrd_n ? switch_out : - ~pokey_n ? pokey_out : - 8'b0; - // we ignore the cpu, as pf ram is now dp and cpu has it's own port // assign pf_sel = mob_n ? { s_8v, s_128h } : 2'b00; @@ -732,209 +1015,27 @@ HJ7 HJ7( assign pfa = { pfa7654, pfa3210 }; wire pf_ce; - reg pf_ce_d; wire [3:0] pf_ce4_n; assign pf_ce = ~(s_1h & s_2h & s_4h & s_6mhz); - always @(posedge s_12mhz) - if (reset) - pf_ce_d <= 0; - else - pf_ce_d <= pf_ce; - -// assign pf_ce4_n = { pf_ce_d, pf_ce_d, pf_ce_d, pf_ce_d }; assign pf_ce4_n = 4'b0; - + pf_ram pf_ram( - .clk_a(s_12mhz), - .clk_b(s_12mhz), - .reset(reset), - // - .addr_a({ab[9:6], ab[3:0]}), - .din_a(db_out[7:0]), - .dout_a(pf_out), - .ce_a({pfrd3_n, pfrd2_n, pfrd1_n, pfrd0_n}), - .we_a({pfwr3_n, pfwr2_n, pfwr1_n, pfwr0_n}), - // - .addr_b(pfa), - .dout_b(pfd), - .ce_b(pf_ce4_n) - ); - - // High Score Memory Circuitry + .clk_a(s_12mhz), + .clk_b(s_12mhz), + .reset(reset), + // + .addr_a({ab[9:6], ab[3:0]}), + .din_a(db_out[7:0]), + .dout_a(pf_out), + .ce_a({pfrd3_n, pfrd2_n, pfrd1_n, pfrd0_n}), + .we_a({pfwr3_n, pfwr2_n, pfwr1_n, pfwr0_n}), + // + .addr_b(pfa), + .dout_b(pfd), + .ce_b(pf_ce4_n) + ); - assign hs_addr_clk = ~(~ea_addr_n & ~write2_n); - assign hs_ctrl_clk = ~(~ea_ctrl_n & ~write2_n); - always @(posedge hs_addr_clk) - hs_addr <= ab[5:0]; - - always @(posedge hs_ctrl_clk) - hs_ctrl <= db_out[3:0]; -/* -spram #( - .addr_width_g(6), - .data_width_g(8)) -hs_ram( - .address(hs_addr), - .clock(hs_ctrl[0] & ~hs_ctrl[3]), - .wren(~hs_ctrl[1] & hs_ctrl[2]), - .data(hs_data), - .q(hs_out) - ); */ -assign hs_out = 8'b0; - always @(posedge hs_addr_clk) - hs_data <= db_out[7:0]; - - // Joystick Circuitry - wire js1_right, js1_left, js1_down, js1_up; - wire js2_right, js2_left, js2_down, js2_up; - - assign js1_right = joystick_i[7]; - assign js1_left = joystick_i[6]; - assign js1_down = joystick_i[5]; - assign js1_up = joystick_i[4]; - assign js2_right = joystick_i[3]; - assign js2_left = joystick_i[2]; - assign js2_down = joystick_i[1]; - assign js2_up = joystick_i[0]; - - assign joystick_out = ab[0] ? - { js1_right, js1_left, js1_down, js1_up, js2_right, js2_left, js2_down, js2_up } : - { dir2, 3'b0, trb }; - - // Option Input Circuitry - - assign switch_out = ab[0] ? - sw2_i : - sw1_i; - - // Player Input Circuitry - wire coin_r, coin_c, coin_l, self_test; - wire cocktail, slam, start1, start2, fire2, fire1; - - assign coin_r = coin_ctr_r_drive ? coin_ctr_r_drive : playerinput_i[9]; - assign coin_c = coin_ctr_c_drive ? coin_ctr_c_drive : playerinput_i[8]; - assign coin_l = coin_ctr_l_drive ? coin_ctr_l_drive : playerinput_i[7]; - assign self_test = playerinput_i[6]; - assign cocktail = playerinput_i[5]; - assign slam = playerinput_i[4]; - assign start1 = playerinput_i[3]; - assign start2 = playerinput_i[2]; - assign fire2 = playerinput_i[1]; - assign fire1 = playerinput_i[0]; - - wire [7:0] playerin_out0; - wire [7:0] playerin_out1; - - assign playerin_out1 = { coin_r, coin_c, coin_l, slam, fire2, fire1, start1, start2 }; - assign playerin_out0 = { dir1, vblank, self_test, cocktail, tra }; - - assign playerin_out = ab[0] ? playerin_out1 : playerin_out0; - - // Coin Counter Output - reg [7:0] cc_latch; - - always @(posedge s_12mhz or posedge reset) - if (reset) - cc_latch <= 0; - else if (s_6mhz_en) - if (~out0_n) - cc_latch[ ab[2:0] ] <= db_out[7]; - - assign flip = cc_latch[7]; - assign led_o[4] = cc_latch[6]; - assign led_o[3] = cc_latch[5]; - assign led_o[2] = cc_latch[4]; - assign led_o[1] = cc_latch[3]; - assign coin_ctr_r_drive = cc_latch[2]; - assign coin_ctr_c_drive = cc_latch[1]; - assign coin_ctr_l_drive = cc_latch[1]; - - // Mini-Trak Ball inputs - wire [3:0] tb_mux; - wire s_1_horiz_dir, s_1_horiz_ck, s_1_vert_dir, s_1_vert_ck; - wire s_2_horiz_dir, s_2_horiz_ck, s_2_vert_dir, s_2_vert_ck; - wire tb_h_dir, tb_h_ck, tb_v_dir, tb_v_ck; - reg tb_h_reg, tb_v_reg; - reg [3:0] tb_h_ctr, tb_v_ctr; - wire tb_h_ctr_clr, tb_v_ctr_clr; - - assign s_1_horiz_dir = trakball_i[7]; - assign s_2_horiz_dir = trakball_i[6]; - assign s_1_horiz_ck = trakball_i[5]; - assign s_2_horiz_ck = trakball_i[4]; - assign s_1_vert_dir = trakball_i[3]; - assign s_2_vert_dir = trakball_i[2]; - assign s_1_vert_ck = trakball_i[1]; - assign s_2_vert_ck = trakball_i[0]; - - assign tb_mux = flip ? - { s_1_horiz_dir, s_1_horiz_ck, s_1_vert_dir, s_1_vert_ck } : - { s_2_horiz_dir, s_2_horiz_ck, s_2_vert_dir, s_2_vert_ck }; - - assign tb_h_dir = tb_mux[3]; - assign tb_h_ck = tb_mux[2]; - assign tb_v_dir = tb_mux[1]; - assign tb_v_ck = tb_mux[0]; - - // H - always @(posedge tb_h_ck or posedge reset) - if (reset) - tb_h_reg <= 0; - else - tb_h_reg <= tb_h_dir; - - assign tb_h_ctr_clr = reset | ~steerclr_n; - - always @(posedge tb_h_ck or posedge tb_h_ctr_clr) - if (tb_h_ctr_clr) - tb_h_ctr <= 0; - else - if (tb_h_reg) - tb_h_ctr <= tb_h_ctr + 4'd1; - else - tb_h_ctr <= tb_h_ctr - 4'd1; - - // V - always @(posedge tb_v_ck or posedge reset) - if (reset) - tb_v_reg <= 0; - else - tb_v_reg <= tb_v_dir; - - assign tb_v_ctr_clr = reset | ~steerclr_n; - - always @(posedge tb_v_ck or posedge tb_v_ctr_clr) - if (tb_v_ctr_clr) - tb_v_ctr <= 0; - else - if (tb_v_reg) - tb_v_ctr <= tb_v_ctr + 4'd1; - else - tb_v_ctr <= tb_v_ctr - 4'd1; - - assign tra = tb_h_ctr; - assign trb = tb_v_ctr; - assign dir1 = tb_h_reg; - assign dir2 = tb_v_reg; - - - // Audio output circuitry - - -POKEY POKEY( - .Din(db_out[7:0]), - .Dout(pokey_out), - .A(ab[3:0]), - .P(8'b0), - .phi2(phi2), - .readHighWriteLow(rw_n), - .cs0Bar(pokey_n), - .audio(audio), - .clk(clk_100mhz) - ); - - // Video output circuitry // The video output circuit receives motion object, playfield, address and data inputs @@ -955,7 +1056,7 @@ POKEY POKEY( wire gry0_or_1; assign gry0_or_1 = gry[1] | gry[0]; - assign rama_sel = { coloram_n, gry0_or_1 }; + //assign rama_sel = { coloram_n, gry0_or_1 }; // assign rama = // (rama_sel == 2'b00) ? { ab[3:0] } : @@ -964,42 +1065,50 @@ POKEY POKEY( // (rama_sel == 2'b11) ? { {gry0_or_1, 1'b1}, gry[1:0] } : // 4'b0; - assign rama = gry0_or_1 ? - { {gry0_or_1, 1'b1}, gry[1:0] } : - { {gry0_or_1, 1'b1}, area[1:0] }; + wire [3:0] rama_centi = gry0_or_1 ? + { {gry0_or_1, 1'b1}, gry[1:0] } : + { {gry0_or_1, 1'b1}, area[1:0] }; - -dpram #( - .addr_width_g(4), - .data_width_g(4)) -color_ram( - .clk_a_i(s_12mhz), - .clk_b_i(s_12mhz), - .we_i(~coloram_w_n), - .addr_a_i(ab[3:0]), - .data_a_o(coloram_out), - .data_a_i(db_out[3:0]), - .addr_b_i(rama), - .data_b_o(coloram_rgbi) - ); + wire rama_hi_sel = (gry0_or_1 & s_256h & s_256h2d); + wire [4:0] rama_milli = {rama_hi_sel, rama_hi_sel ? {mocb, gry} : {picD[7:6], area}}; - assign rgb_o = - rgbi == 4'b0000 ? 9'b111_111_111 : - rgbi == 4'b0001 ? 9'b111_111_011 : - rgbi == 4'b0010 ? 9'b111_011_111 : - rgbi == 4'b0011 ? 9'b111_011_011 : - rgbi == 4'b0100 ? 9'b011_111_111 : - rgbi == 4'b0101 ? 9'b011_111_011 : - rgbi == 4'b0110 ? 9'b011_011_111 : - rgbi == 4'b0111 ? 9'b011_011_011 : - rgbi == 4'b1000 ? 9'b111_111_111 : - rgbi == 4'b1001 ? 9'b111_111_000 : - rgbi == 4'b1010 ? 9'b111_000_111 : - rgbi == 4'b1011 ? 9'b111_000_000 : - rgbi == 4'b1100 ? 9'b000_111_111 : - rgbi == 4'b1101 ? 9'b000_111_000 : - rgbi == 4'b1110 ? 9'b000_000_111 : - rgbi == 4'b1111 ? 9'b000_000_000 : + wire [4:0] rama = milli ? rama_milli : {1'b0, rama_centi}; + wire [4:0] cram_a = milli ? ab[4:0] : {1'b0, ab[3:0]}; + + dpram #( + .addr_width_g(5), + .data_width_g(8)) + color_ram( + .clk_a_i(s_12mhz), + .clk_b_i(s_12mhz), + .we_i(~coloram_w_n), + .addr_a_i(cram_a), + .data_a_o(coloram_out), + .data_a_i(milli ? db_out : {db_out[3:0], db_out[3:0]}), + .addr_b_i(rama), + .data_b_o(coloram_rgbi) + ); + + assign rgb_o = milli ? rgb_o_milli : rgb_o_centi; + + wire [8:0] rgb_o_milli = ~{ rgbi[2:0], rgbi[4:3], 1'b1, rgbi[7:5] }; + wire [8:0] rgb_o_centi = + rgbi[3:0] == 4'b0000 ? 9'b111_111_111 : + rgbi[3:0] == 4'b0001 ? 9'b111_111_011 : + rgbi[3:0] == 4'b0010 ? 9'b111_011_111 : + rgbi[3:0] == 4'b0011 ? 9'b111_011_011 : + rgbi[3:0] == 4'b0100 ? 9'b011_111_111 : + rgbi[3:0] == 4'b0101 ? 9'b011_111_011 : + rgbi[3:0] == 4'b0110 ? 9'b011_011_111 : + rgbi[3:0] == 4'b0111 ? 9'b011_011_011 : + rgbi[3:0] == 4'b1000 ? 9'b111_111_111 : + rgbi[3:0] == 4'b1001 ? 9'b111_111_000 : + rgbi[3:0] == 4'b1010 ? 9'b111_000_111 : + rgbi[3:0] == 4'b1011 ? 9'b111_000_000 : + rgbi[3:0] == 4'b1100 ? 9'b000_111_111 : + rgbi[3:0] == 4'b1101 ? 9'b000_111_000 : + rgbi[3:0] == 4'b1110 ? 9'b000_000_111 : + rgbi[3:0] == 4'b1111 ? 9'b000_000_000 : 9'd0; @@ -1008,6 +1117,38 @@ color_ram( assign vsync_o = vsync; assign audio_o = audio; assign hblank_o = hblank; - assign vblank_o = vblank; + assign vblank_o = vblankd; + + // Audio output circuitry + + wire [3:0] pokey_audio; + POKEY POKEY( + .Din(db_out[7:0]), + .Dout(pokey_out), + .A(ab[3:0]), + .P(8'b0), + .phi2(phi2), + .readHighWriteLow(rw_n), + .cs0Bar(pokey_n), + .audio(pokey_audio), + .clk(clk_100mhz) + ); + + POKEY POKEY2( + .Din(db_out[7:0]), + .Dout(pokey2_out), + .A(ab[3:0]), + .P(8'b0), + .phi2(phi2), + .readHighWriteLow(rw_n), + .cs0Bar(pokey2_n), + .audio(pokey2_audio), + .clk(clk_100mhz) + ); + wire [3:0] pokey2_audio; + wire [4:0] pokey_mux = pokey_audio + pokey2_audio; + + assign audio = milli ? (pokey_mux[4] ? 4'hf : pokey_mux[3:0]) : pokey_audio; + endmodule diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/dpram.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/dpram.vhd index d867b5d2..e42e9194 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/dpram.vhd +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/dpram.vhd @@ -18,7 +18,9 @@ entity dpram is data_a_i : in std_logic_vector(data_width_g-1 downto 0); data_a_o : out std_logic_vector(data_width_g-1 downto 0); clk_b_i : in std_logic; + we_b_i : in std_logic := '0'; addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); + data_b_i : in std_logic_vector(data_width_g-1 downto 0); data_b_o : out std_logic_vector(data_width_g-1 downto 0) ); end entity; @@ -52,6 +54,9 @@ begin begin if rising_edge(clk_b_i) then read_addr_v := unsigned(addr_b_i); + if we_b_i = '1' then + ram_q(to_integer(read_addr_v)) <= data_b_i; + end if; data_b_o <= ram_q(to_integer(read_addr_v)); end if; end process mem_b; diff --git a/common/Sound/Pokey/matoro.sv b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/matoro.sv similarity index 100% rename from common/Sound/Pokey/matoro.sv rename to Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/matoro.sv diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/pf_ram.v b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/pf_ram.v index aac899ac..c774f7bb 100644 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/pf_ram.v +++ b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/pf_ram.v @@ -27,12 +27,12 @@ dpram #( .addr_width_g(8), .data_width_g(8)) ram0( - .clk_a_i(clk_a & ~ce_a[0]), + .clk_a_i(clk_a), .we_i(~we_a[0]), .addr_a_i(addr_a), .data_a_i(din_a), .data_a_o(d_a0), - .clk_b_i(clk_b & ~ce_b[0]), + .clk_b_i(clk_b), .addr_b_i(addr_b), .data_b_o(d_b0) ); @@ -41,12 +41,12 @@ dpram #( .addr_width_g(8), .data_width_g(8)) ram1( - .clk_a_i(clk_a & ~ce_a[1]), + .clk_a_i(clk_a), .we_i(~we_a[1]), .addr_a_i(addr_a), .data_a_i(din_a), .data_a_o(d_a1), - .clk_b_i(clk_b & ~ce_b[1]), + .clk_b_i(clk_b), .addr_b_i(addr_b), .data_b_o(d_b1) ); @@ -55,12 +55,12 @@ dpram #( .addr_width_g(8), .data_width_g(8)) ram2( - .clk_a_i(clk_a & ~ce_a[2]), + .clk_a_i(clk_a), .we_i(~we_a[2]), .addr_a_i(addr_a), .data_a_i(din_a), .data_a_o(d_a2), - .clk_b_i(clk_b & ~ce_b[2]), + .clk_b_i(clk_b), .addr_b_i(addr_b), .data_b_o(d_b2) ); @@ -69,12 +69,12 @@ dpram #( .addr_width_g(8), .data_width_g(8)) ram3( - .clk_a_i(clk_a & ~ce_a[3]), + .clk_a_i(clk_a), .we_i(~we_a[3]), .addr_a_i(addr_a), .data_a_i(din_a), .data_a_o(d_a3), - .clk_b_i(clk_b & ~ce_b[3]), + .clk_b_i(clk_b), .addr_b_i(addr_b), .data_b_o(d_b3) ); diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/F7.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/F7.vhd deleted file mode 100644 index 0af1e96f..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/F7.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity F7 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of F7 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"00",X"00",X"00",X"3C",X"18",X"18",X"FF",X"7E",X"3C",X"18",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"3C",X"18",X"18",X"7E",X"7E",X"BD",X"18",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"3C",X"18",X"18",X"FF",X"7E",X"3C",X"18",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"3C",X"99",X"18",X"7E",X"7E",X"3C",X"18",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"0A",X"4C",X"3E",X"3E",X"FE",X"7C",X"B8",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"0A",X"4C",X"3E",X"3E",X"FE",X"7C",X"B8",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"10",X"18",X"9C",X"FE",X"FE",X"9C",X"18",X"10",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"10",X"18",X"9C",X"FE",X"FE",X"9C",X"18",X"10",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"18",X"30",X"F2",X"FF",X"F2",X"30",X"18",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"44",X"22",X"11",X"22",X"44",X"68",X"A0",X"3C",X"A0",X"68",X"44",X"22",X"11",X"22",X"44",X"00", - X"90",X"48",X"24",X"24",X"44",X"68",X"E0",X"3C",X"A0",X"68",X"44",X"24",X"24",X"48",X"90",X"00", - X"90",X"48",X"24",X"24",X"44",X"68",X"A0",X"3C",X"A0",X"68",X"44",X"24",X"24",X"48",X"90",X"00", - X"10",X"88",X"44",X"33",X"44",X"68",X"E0",X"3C",X"A0",X"68",X"44",X"33",X"44",X"88",X"10",X"00", - X"00",X"00",X"00",X"18",X"18",X"98",X"7F",X"8F",X"7F",X"1E",X"7C",X"B8",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"18",X"18",X"18",X"6F",X"9F",X"2F",X"5E",X"BC",X"78",X"00",X"00",X"00",X"00", - X"22",X"55",X"BE",X"74",X"02",X"61",X"C2",X"74",X"36",X"43",X"E0",X"40",X"36",X"7D",X"AE",X"44", - X"14",X"94",X"42",X"F1",X"42",X"94",X"34",X"3C",X"3C",X"34",X"94",X"42",X"F1",X"42",X"94",X"14", - X"00",X"24",X"4A",X"34",X"34",X"0C",X"3E",X"75",X"6D",X"2A",X"1C",X"34",X"34",X"4A",X"24",X"00", - X"00",X"00",X"00",X"00",X"10",X"00",X"3C",X"1C",X"1C",X"1E",X"00",X"04",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"80",X"98",X"50",X"34",X"3C",X"3C",X"3C",X"3F",X"3E",X"3C",X"7C",X"BC",X"3C",X"7C",X"B8",X"98", - X"00",X"86",X"FC",X"05",X"0F",X"0F",X"0F",X"7F",X"8F",X"8F",X"0F",X"1F",X"EF",X"8F",X"0E",X"06", - X"01",X"06",X"0D",X"08",X"08",X"7C",X"FF",X"FC",X"F8",X"C8",X"CD",X"C6",X"C1",X"CC",X"E4",X"7C", - X"01",X"06",X"0D",X"08",X"7C",X"FF",X"FC",X"C8",X"CD",X"C6",X"E1",X"60",X"30",X"18",X"44",X"3C", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"F8",X"88",X"F8",X"00",X"F8",X"88",X"F8",X"00",X"F8",X"A8",X"A8",X"00",X"00", - X"00",X"00",X"00",X"F8",X"88",X"F8",X"00",X"F8",X"88",X"F8",X"00",X"E8",X"A8",X"F8",X"00",X"00", - X"00",X"00",X"00",X"00",X"08",X"B1",X"42",X"81",X"02",X"00",X"29",X"50",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"59",X"96",X"01",X"83",X"82",X"84",X"EA",X"31",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"7C",X"FE",X"7F",X"3E",X"7F",X"FE",X"7C",X"7E",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3C",X"42",X"81",X"81",X"81",X"81",X"42",X"3C", - X"3C",X"42",X"81",X"81",X"81",X"81",X"42",X"3C",X"00",X"00",X"00",X"00",X"08",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"30",X"F2",X"FF",X"F2",X"30",X"18",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"0C",X"06",X"0F",X"03",X"0F",X"07",X"0E",X"0C",X"1C",X"0E",X"3F",X"0F",X"1F",X"0F",X"1E",X"0C", - X"1C",X"0E",X"3F",X"7F",X"3F",X"3F",X"1E",X"1C",X"1C",X"1E",X"FF",X"FF",X"FF",X"FF",X"1E",X"1C", - X"00",X"04",X"0E",X"02",X"0E",X"06",X"0C",X"00",X"00",X"0C",X"0E",X"0E",X"0E",X"0E",X"0C",X"00", - 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if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/HJ7.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/HJ7.vhd deleted file mode 100644 index 3223a70a..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/HJ7.vhd +++ /dev/null @@ -1,150 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity HJ7 is -port ( - clk : in std_logic; - addr : in std_logic_vector(10 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of HJ7 is - type rom is array(0 to 2047) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"00",X"00",X"00",X"00",X"3C",X"7E",X"7E",X"7E",X"7E",X"3C",X"18",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"3C",X"7E",X"7E",X"7E",X"7E",X"3C",X"18",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"3C",X"7E",X"7E",X"7E",X"7E",X"3C",X"18",X"00",X"00",X"00",X"00",X"00", - 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", - X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/P4.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/P4.vhd deleted file mode 100644 index 06353288..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/P4.vhd +++ /dev/null @@ -1,38 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity P4 is -port ( - clk : in std_logic; - addr : in std_logic_vector(7 downto 0); - data : out std_logic_vector(3 downto 0) -); -end entity; - -architecture prom of P4 is - type rom is array(0 to 255) of std_logic_vector(3 downto 0); - signal rom_data: rom := ( - "0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000", - "0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000", - "0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000", - "0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000", - "0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000", - "0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000","0000", - "0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0010","0010","0010","0010","0010","0010", - "0010","0010","0010","0010","0010","0010","0010","0010","0010","0010","0010","0010","0010","0010","0010","1010", - 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end if; -end process; -end architecture; diff --git a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/PROG.vhd b/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/PROG.vhd deleted file mode 100644 index 902078c2..00000000 --- a/Arcade_MiST/Atari Centipede Hardware/Centipede_MiST/rtl/roms/PROG.vhd +++ /dev/null @@ -1,534 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity PROG is -port ( - clk : in std_logic; - addr : in std_logic_vector(12 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of PROG is - type rom is array(0 to 8191) of std_logic_vector(7 downto 0); - signal rom_data: rom := ( - X"4C",X"4B",X"3B",X"1B",X"31",X"39",X"38",X"30",X"20",X"41",X"54",X"41",X"52",X"C9",X"20",X"76", - X"28",X"58",X"20",X"60",X"2D",X"46",X"8A",X"90",X"FC",X"8D",X"00",X"20",X"AD",X"00",X"0C",X"29", - X"20",X"F0",X"FE",X"20",X"66",X"25",X"20",X"79",X"30",X"20",X"45",X"27",X"10",X"E7",X"20",X"07", - X"3B",X"20",X"19",X"21",X"20",X"27",X"33",X"20",X"55",X"29",X"20",X"01",X"27",X"20",X"D2",X"2A", - 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X"4C",X"41",X"59",X"D3",X"20",X"47",X"41",X"4D",X"45",X"20",X"54",X"49",X"4D",X"C5",X"48",X"41", - X"52",X"C4",X"45",X"41",X"53",X"D9",X"4C",X"F6",X"3F",X"13",X"F6",X"3F",X"4B",X"3B",X"C0",X"38"); -begin -process(clk) -begin - if rising_edge(clk) then - data <= rom_data(to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Arcade_MiST/Atari Tetris/Tetris.qsf b/Arcade_MiST/Atari Tetris/Tetris.qsf index 3c7abb8a..a40b2bf0 100644 --- a/Arcade_MiST/Atari Tetris/Tetris.qsf +++ b/Arcade_MiST/Atari Tetris/Tetris.qsf @@ -218,23 +218,12 @@ set_global_assignment -name USE_SIGNALTAP_FILE output_files/tet.stp set_global_assignment -name SYSTEMVERILOG_FILE rtl/Tetris_MiST.sv set_global_assignment -name VERILOG_FILE rtl/FPGA_ATetris.v set_global_assignment -name VERILOG_FILE rtl/ATARI_SLAPSTIK1.v -set_global_assignment -name VHDL_FILE rtl/Pokey/syncreset_enable_divider.vhd -set_global_assignment -name VHDL_FILE rtl/Pokey/synchronizer.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_poly_17_9.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_poly_5.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_poly_4.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_noise_filter.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_keyboard_scanner.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/pokey_countdown_timer.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/pokey.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/latch_delay_line.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/delay_line.vhdl -set_global_assignment -name VHDL_FILE rtl/Pokey/complete_address_decoder.vhdl set_global_assignment -name VHDL_FILE rtl/dpram.vhd set_global_assignment -name VERILOG_FILE rtl/hvgen.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name QIP_FILE ../../common/Sound/Pokey/Pokey.qip set_global_assignment -name QIP_FILE ../../common/CPU/T65/T65.qip set_global_assignment -name QIP_FILE ../../common/mist/mist.qip set_global_assignment -name SIGNALTAP_FILE output_files/tet.stp diff --git a/Arcade_MiST/Atari Tetris/rtl/FPGA_ATetris.v b/Arcade_MiST/Atari Tetris/rtl/FPGA_ATetris.v index 16afec24..b7759450 100644 --- a/Arcade_MiST/Atari Tetris/rtl/FPGA_ATetris.v +++ b/Arcade_MiST/Atari Tetris/rtl/FPGA_ATetris.v @@ -24,7 +24,13 @@ module FPGA_ATetris input [7:0] PRDT, output [15:0] CRAD, - input [15:0] CRDT + input [15:0] CRDT, + + input NVRAM_CLK, + input [8:0] NVRAM_A, + input [7:0] NVRAM_D, + input NVRAM_WE, + output [7:0] NVRAM_Q ); // INP = {`SELFT,`COIN2,`COIN1,`P2LF,`P2RG,`P2DW,`P2RO,`P1LF,`P1RG,`P1DW,`P1RO}; @@ -66,7 +72,7 @@ ATETRIS_ROMAXS romaxs(RST,MCLK,CPUCE,CPUAD,PRAD,PRDV); // RAMs wire [7:0] RMDT; wire RMDV; -ATETRIS_RAMS rams(MCLK,CPUAD,CPUWR,CPUDO,RMDT,RMDV); +ATETRIS_RAMS rams(MCLK,CPUAD,CPUWR,CPUDO,RMDT,RMDV,NVRAM_CLK,NVRAM_A,NVRAM_D,NVRAM_WE,NVRAM_Q); // Video @@ -164,7 +170,13 @@ module ATETRIS_RAMS input CPUWR, input [7:0] CPUDO, output [7:0] RMDT, - output RMDV + output RMDV, + + input NVRAM_CLK, + input [8:0] NVRAM_A, + input [7:0] NVRAM_D, + input NVRAM_WE, + output [7:0] NVRAM_Q ); // WorkRAM @@ -188,16 +200,24 @@ wire NVDV = (CPUAD[15:10]==6'b0010_01); // $24xx-$27xx wire [7:0] NVDT; //RAM_B #(9,255) nvram(DEVCL,CPUAD,NVDV,CPUWR,CPUDO,NVDT); -spram#( - .init_file("nvinit.hex"), - .widthad_a(9), - .width_a(8)) +dpram#( + .init_file("rtl/nvinit.mif"), + .data_width_g(8), + .addr_width_g(9)) nvram( - .address(CPUAD), - .clock(MCLK), - .data(CPUDO), - .wren(CPUWR & NVDV), - .q(NVDT) + // CPU side + .clk_a_i(MCLK), + .en_a_i(1'b1), + .addr_a_i(CPUAD), + .data_a_i(CPUDO), + .we_i(CPUWR & NVDV), + .data_a_o(NVDT), + // IO Controller side + .clk_b_i(NVRAM_CLK), + .addr_b_i(NVRAM_A), + .data_b_o(NVRAM_Q), + .data_b_i(NVRAM_D), + .we_b_i(NVRAM_WE) ); DSEL4x8 dsel(RMDV,RMDT, @@ -253,7 +273,7 @@ reg [8:0] pVPT; always @(posedge MCLK) begin if (tWDTR) WDT <= 0; else if (pVPT!=VP) begin - if (VP==0) WDT <= (WDT==8) ? 14 : (WDT+1); + if (VP==0) WDT <= (WDT==8) ? 4'd14 : (WDT+1); pVPT <= VP; end end diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/syncreset_enable_divider.vhd b/Arcade_MiST/Atari Tetris/rtl/Pokey/syncreset_enable_divider.vhd deleted file mode 100644 index 998e8958..00000000 --- a/Arcade_MiST/Atari Tetris/rtl/Pokey/syncreset_enable_divider.vhd +++ /dev/null @@ -1,81 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY syncreset_enable_divider IS -generic(COUNT : natural := 1; RESETCOUNT : natural := 0); -PORT -( - CLK : IN STD_LOGIC; - SYNCRESET : in std_logic; - RESET_N : IN STD_LOGIC; - ENABLE_IN : IN STD_LOGIC; - - ENABLE_OUT : OUT STD_LOGIC -); -END syncreset_enable_divider; - -ARCHITECTURE vhdl OF syncreset_enable_divider IS - function log2c(n : integer) return integer is - variable m,p : integer; - begin - m := 0; - p := 1; - while p'0'); - enabled_out_reg <= '0'; - elsif (clk'event and clk='1') then - count_reg <= count_next; - enabled_out_reg <= enabled_out_next; - end if; - end process; - - -- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28 - process(count_reg,enable_in,enabled_out_reg,syncreset) - begin - count_next <= count_reg; - enabled_out_next <= enabled_out_reg; - - if (enable_in = '1') then - count_next <= std_logic_vector(unsigned(count_reg) + 1); - enabled_out_next <= '0'; - - if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then - count_next <= std_logic_vector(to_unsigned(0,WIDTH)); - enabled_out_next <= '1'; - end if; - end if; - - if (syncreset='1') then - count_next <= std_logic_vector(to_unsigned(resetcount,width)); - end if; - end process; - - -- output - enable_out <= enabled_out_reg and enable_in; - -END vhdl; diff --git a/Arcade_MiST/Atari Tetris/rtl/Tetris_MiST.sv b/Arcade_MiST/Atari Tetris/rtl/Tetris_MiST.sv index 0c359596..e16c40ca 100644 --- a/Arcade_MiST/Atari Tetris/rtl/Tetris_MiST.sv +++ b/Arcade_MiST/Atari Tetris/rtl/Tetris_MiST.sv @@ -32,11 +32,12 @@ module Tetris_MiST( `include "rtl/build_id.v" localparam CONF_STR = { - "TETRIS;ROM;", + "TETRIS;;", "O2,Service,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", "O5,Blend,Off,On;", "O6,Joystick Swap,Off,On;", + "R512,Save NVRAM;", "T0,Reset;", "V,v1.0.",`BUILD_DATE }; @@ -46,7 +47,7 @@ wire joyswap = status[6]; wire rotate = 0; wire blend = status[5]; -assign LED = ~ioctl_downl; +assign LED = ~(ioctl_downl | ioctl_upl); assign SDRAM_CLK = clk_sd; assign SDRAM_CKE = 1; assign AUDIO_R = AUDIO_L; @@ -100,21 +101,26 @@ wire [15:0] rom_do; wire [15:0] gfx_addr; wire [15:0] gfx_do; wire ioctl_downl; +wire ioctl_upl; wire [7:0] ioctl_index; wire ioctl_wr; wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; +wire [7:0] ioctl_din; data_io data_io( - .clk_sys ( clk_sd ), + .clk_sys ( clk_sd ), .SPI_SCK ( SPI_SCK ), .SPI_SS2 ( SPI_SS2 ), .SPI_DI ( SPI_DI ), + .SPI_DO ( SPI_DO ), .ioctl_download( ioctl_downl ), + .ioctl_upload ( ioctl_upl ), .ioctl_index ( ioctl_index ), .ioctl_wr ( ioctl_wr ), .ioctl_addr ( ioctl_addr ), - .ioctl_dout ( ioctl_dout ) + .ioctl_dout ( ioctl_dout ), + .ioctl_din ( ioctl_din ) ); reg port1_req, port2_req; @@ -154,7 +160,7 @@ always @(posedge clk_sd) begin ioctl_wr_last <= ioctl_wr; if (ioctl_downl) begin - if (~ioctl_wr_last && ioctl_wr) begin + if (~ioctl_wr_last && ioctl_wr && ioctl_index == 0) begin port1_req <= ~port1_req; port2_req <= ~port2_req; end @@ -196,7 +202,13 @@ FPGA_ATetris FPGA_ATetris( .PRDT(rom_addr[0] ? rom_do[15:8] : rom_do[7:0]), .CRAD(gfx_addr), - .CRDT(gfx_do) + .CRDT(gfx_do), + + .NVRAM_CLK(clk_sd), + .NVRAM_A(ioctl_addr[8:0]), + .NVRAM_D(ioctl_dout), + .NVRAM_Q(ioctl_din), + .NVRAM_WE(ioctl_wr && ioctl_index == 8'hff) ); wire PCLK; diff --git a/Arcade_MiST/Atari Tetris/rtl/dpram.vhd b/Arcade_MiST/Atari Tetris/rtl/dpram.vhd index 9ab46487..a20c5c79 100644 --- a/Arcade_MiST/Atari Tetris/rtl/dpram.vhd +++ b/Arcade_MiST/Atari Tetris/rtl/dpram.vhd @@ -8,8 +8,9 @@ use ieee.std_logic_1164.all; entity dpram is generic ( - addr_width_g : integer := 8; - data_width_g : integer := 8 + addr_width_g : integer := 8; + data_width_g : integer := 8; + init_file : string := "" ); port ( clk_a_i : in std_logic; @@ -20,7 +21,9 @@ port ( data_a_o : out std_logic_vector(data_width_g-1 downto 0); clk_b_i : in std_logic; addr_b_i : in std_logic_vector(addr_width_g-1 downto 0); - data_b_o : out std_logic_vector(data_width_g-1 downto 0) + data_b_o : out std_logic_vector(data_width_g-1 downto 0); + we_b_i : in std_logic := '0'; + data_b_i : in std_logic_vector(data_width_g-1 downto 0) := (others => '0') ); end dpram; @@ -33,6 +36,8 @@ architecture rtl of dpram is type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); signal ram_q : ram_t; + attribute ram_init_file : string; + attribute ram_init_file of ram_q : signal is init_file; begin @@ -51,7 +56,10 @@ begin mem_b: process (clk_b_i) begin if rising_edge(clk_b_i) then - data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); + if we_b_i = '1' then + ram_q(to_integer(unsigned(addr_b_i))) <= data_b_i; + end if; + data_b_o <= ram_q(to_integer(unsigned(addr_b_i))); end if; end process mem_b; diff --git a/Arcade_MiST/Atari Tetris/rtl/nvinit.mif b/Arcade_MiST/Atari Tetris/rtl/nvinit.mif new file mode 100644 index 00000000..a5508835 --- /dev/null +++ b/Arcade_MiST/Atari Tetris/rtl/nvinit.mif @@ -0,0 +1,32 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 512; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0018: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0030: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0048: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0060: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0078: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0090: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +00A8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +00C0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +00D8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +00F0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0108: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0120: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0138: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0150: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0168: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0180: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +0198: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +01B0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +01C8: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +01E0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF; +01F8: FF FF FF FF FF FF FF FF; +END; diff --git a/common/Sound/Pokey MrX/complete_address_decoder.vhdl b/common/Sound/Pokey MrX/complete_address_decoder.vhdl deleted file mode 100644 index e7a18b31..00000000 --- a/common/Sound/Pokey MrX/complete_address_decoder.vhdl +++ /dev/null @@ -1,52 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY complete_address_decoder IS -generic (width : natural := 1); -PORT -( - addr_in : in std_logic_vector(width-1 downto 0); - - addr_decoded : out std_logic_vector((2**width)-1 downto 0) -); -END complete_address_decoder; - ---ARCHITECTURE vhdl OF complete_address_decoder IS ---BEGIN --- comp_gen: --- for i in 0 to ((2**width)-1) generate --- addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0'; --- end generate; ---end vhdl; - -architecture tree of complete_address_decoder is - constant STAGE : natural:=width; - type std_logic_2d is array (natural range <>,natural range <>) of std_logic; - signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0); - signal a: std_logic_vector(width-1 downto 0) ; -begin - a<=addr_in; - process(a,p) - begin - p(stage,0) <= '1'; - - for s in stage downto 1 loop - for r in 0 to (2**(stage-s)-1) loop - p(s-1,2*r) <= (not a(s-1)) and p(s,r); - p(s-1,2*r+1) <= a(s-1) and p(s,r); - end loop; - end loop; - - for i in 0 to (2**stage-1) loop - addr_decoded(i) <= p(0,i); - end loop; - end process; -end tree; \ No newline at end of file diff --git a/common/Sound/Pokey MrX/delay_line.vhdl b/common/Sound/Pokey MrX/delay_line.vhdl deleted file mode 100644 index c67ada0d..00000000 --- a/common/Sound/Pokey MrX/delay_line.vhdl +++ /dev/null @@ -1,57 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY delay_line IS -generic(COUNT : natural := 1); -PORT -( - CLK : IN STD_LOGIC; - SYNC_RESET : IN STD_LOGIC; - DATA_IN : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; -- i.e. shift on this clock - RESET_N : IN STD_LOGIC; - - DATA_OUT : OUT STD_LOGIC -); -END delay_line; - -ARCHITECTURE vhdl OF delay_line IS - signal shift_reg : std_logic_vector(COUNT-1 downto 0); - signal shift_next : std_logic_vector(COUNT-1 downto 0); -BEGIN - -- register - process(clk,reset_n) - begin - if (reset_N = '0') then - shift_reg <= (others=>'0'); - elsif (clk'event and clk='1') then - shift_reg <= shift_next; - end if; - end process; - - -- shift on enable - process(shift_reg,enable,data_in,sync_reset) - begin - shift_next <= shift_reg; - - if (enable = '1') then - shift_next <= data_in&shift_reg(COUNT-1 downto 1); - end if; - - if (sync_reset = '1') then - shift_next <= (others=>'0'); - end if; - end process; - - -- output - data_out <= shift_reg(0) and enable; - -END vhdl; diff --git a/common/Sound/Pokey MrX/latch_delay_line.vhdl b/common/Sound/Pokey MrX/latch_delay_line.vhdl deleted file mode 100644 index 296a6c4a..00000000 --- a/common/Sound/Pokey MrX/latch_delay_line.vhdl +++ /dev/null @@ -1,66 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY latch_delay_line IS -generic(COUNT : natural := 1); -PORT -( - CLK : IN STD_LOGIC; - SYNC_RESET : IN STD_LOGIC; - DATA_IN : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; -- i.e. shift on this clock - RESET_N : IN STD_LOGIC; - - DATA_OUT : OUT STD_LOGIC -); -END latch_delay_line; - -ARCHITECTURE vhdl OF latch_delay_line IS - signal shift_reg : std_logic_vector(COUNT-1 downto 0); - signal shift_next : std_logic_vector(COUNT-1 downto 0); - - signal data_in_reg : std_logic; - signal data_in_next : std_logic; -BEGIN - -- register - process(clk,reset_n) - begin - if (reset_N = '0') then - shift_reg <= (others=>'0'); - data_in_reg <= '0'; - elsif (clk'event and clk='1') then - shift_reg <= shift_next; - data_in_reg <= data_in_next; - end if; - end process; - - -- shift on enable - process(shift_reg,enable,data_in,data_in_reg,sync_reset) - begin - shift_next <= shift_reg; - - data_in_next <= data_in or data_in_reg; - - if (enable = '1') then - shift_next <= (data_in or data_in_reg)&shift_reg(COUNT-1 downto 1); - data_in_next <= '0'; - end if; - - if (sync_reset = '1') then - shift_next <= (others=>'0'); - data_in_next <= '0'; - end if; - end process; - - -- output - data_out <= shift_reg(0) and enable; - -END vhdl; diff --git a/common/Sound/Pokey MrX/pokey.vhdl b/common/Sound/Pokey MrX/pokey.vhdl deleted file mode 100644 index 6628311d..00000000 --- a/common/Sound/Pokey MrX/pokey.vhdl +++ /dev/null @@ -1,1307 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - --- Problem - UART on the DE1 does not have all pins connected. Need to use... - -ENTITY pokey IS -GENERIC -( - CUSTOM_KEYBOARD_SCAN : integer := 0 -- drive from hsync-like if 0, otherwise custom increment signal -); -PORT -( - CLK : IN STD_LOGIC; - ENABLE_179 :in std_logic; - ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - WR_EN : IN STD_LOGIC; - - RESET_N : IN STD_LOGIC; - - -- keyboard interface - keyboard_scan_enable : in std_logic := '0'; - keyboard_scan : out std_logic_vector(5 downto 0); - keyboard_response : in std_logic_vector(1 downto 0); - - -- pots - go high as capacitor charges - POT_IN : in std_logic_vector(7 downto 0); - - -- sio interface - SIO_IN1 : IN std_logic; - SIO_IN2 : IN std_logic; - SIO_IN3 : IN std_logic; - - DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - - CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0); - CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0); - CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0); - CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0); - - IRQ_N_OUT : OUT std_logic; - - SIO_OUT1 : OUT std_logic; - SIO_OUT2 : OUT std_logic; - SIO_OUT3 : OUT std_logic; - - SIO_CLOCKIN_IN : IN std_logic := '1'; - SIO_CLOCKIN_OUT : OUT std_logic; - SIO_CLOCKIN_OE : OUT std_logic; - SIO_CLOCKOUT : OUT std_logic; - - POT_RESET : out std_logic -); -END pokey; - -ARCHITECTURE vhdl OF pokey IS - component synchronizer IS - PORT - ( - CLK : IN STD_LOGIC; - RAW : IN STD_LOGIC; - SYNC : OUT STD_LOGIC - ); - END component; - - component syncreset_enable_divider IS - generic(COUNT : natural := 1; RESETCOUNT : natural := 0); - PORT - ( - CLK : IN STD_LOGIC; - syncreset : in std_logic; - reset_n : in std_logic; - ENABLE_IN : IN STD_LOGIC; - - ENABLE_OUT : OUT STD_LOGIC - ); - END component; - - component pokey_poly_17_9 IS - PORT - ( - CLK : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low - INIT : IN STD_LOGIC; - - BIT_OUT : OUT STD_LOGIC; - - RAND_OUT : OUT std_logic_vector(7 downto 0) - ); - END component; - - component pokey_poly_5 IS - PORT - ( - CLK : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - INIT : IN STD_LOGIC; - - BIT_OUT : OUT STD_LOGIC - ); - END component; - - component pokey_poly_4 IS - PORT - ( - CLK : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - INIT : IN STD_LOGIC; - - BIT_OUT : OUT STD_LOGIC - ); - END component; - - component pokey_countdown_timer IS - generic(UNDERFLOW_DELAY : natural := 3); - PORT - ( - CLK : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - ENABLE_UNDERFLOW : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - - WR_EN : IN STD_LOGIC; - DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0); - - DATA_OUT : OUT STD_LOGIC - ); - END component; - - component pokey_noise_filter IS - PORT - ( - CLK : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - - NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0); - - PULSE_IN : IN STD_LOGIC; - - NOISE_4 : IN STD_LOGIC; - NOISE_5 : IN STD_LOGIC; - NOISE_LARGE : IN STD_LOGIC; - - SYNC_RESET : IN STD_LOGIC; - - PULSE_OUT : OUT STD_LOGIC - ); - END component; - - COMPONENT complete_address_decoder IS - generic (width : natural := 1); - PORT - ( - addr_in : in std_logic_vector(width-1 downto 0); - addr_decoded : out std_logic_vector((2**width)-1 downto 0) - ); - END component; - - component delay_line IS - generic(COUNT : natural := 1); - PORT - ( - CLK : IN STD_LOGIC; - SYNC_RESET : IN STD_LOGIC; - DATA_IN : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - - DATA_OUT : OUT STD_LOGIC - ); - END component; - - component latch_delay_line IS - generic(COUNT : natural := 1); - PORT - ( - CLK : IN STD_LOGIC; - SYNC_RESET : IN STD_LOGIC; - DATA_IN : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - - DATA_OUT : OUT STD_LOGIC - ); - END component; - - component pokey_keyboard_scanner is - port - ( - clk : in std_logic; - reset_n : in std_logic; - - enable : in std_logic; -- typically hsync or equiv timing - keyboard_response : in std_logic_vector(1 downto 0); - debounce_disable : in std_logic; - scan_enable : in std_logic; - - keyboard_scan : out std_logic_vector(5 downto 0); - - key_held : out std_logic; - shift_held : out std_logic; - keycode : out std_logic_vector(7 downto 0); - other_key_irq : out std_logic; - break_irq : out std_logic - ); - end component; - - --signal enable_179 : std_logic; - signal enable_64 : std_logic; - signal enable_15 : std_logic; - - signal audf0_reg : std_logic_vector(7 downto 0); - signal audc0_reg : std_logic_vector(7 downto 0); - signal audf1_reg : std_logic_vector(7 downto 0); - signal audc1_reg : std_logic_vector(7 downto 0); - signal audf2_reg : std_logic_vector(7 downto 0); - signal audc2_reg : std_logic_vector(7 downto 0); - signal audf3_reg : std_logic_vector(7 downto 0); - signal audc3_reg : std_logic_vector(7 downto 0); - signal audctl_reg : std_logic_vector(7 downto 0); - signal audf0_next : std_logic_vector(7 downto 0); - signal audc0_next : std_logic_vector(7 downto 0); - signal audf1_next : std_logic_vector(7 downto 0); - signal audc1_next : std_logic_vector(7 downto 0); - signal audf2_next : std_logic_vector(7 downto 0); - signal audc2_next : std_logic_vector(7 downto 0); - signal audf3_next : std_logic_vector(7 downto 0); - signal audc3_next : std_logic_vector(7 downto 0); - signal audctl_next : std_logic_vector(7 downto 0); - - signal audf0_pulse : std_logic; - signal audf1_pulse : std_logic; - signal audf2_pulse : std_logic; - signal audf3_pulse : std_logic; - - signal audf0_reload : std_logic; - signal audf1_reload : std_logic; - signal audf2_reload : std_logic; - signal audf3_reload : std_logic; - - signal stimer_write : std_logic; - signal stimer_write_delayed : std_logic; - - signal audf0_pulse_noise : std_logic; - signal audf1_pulse_noise : std_logic; - signal audf2_pulse_noise : std_logic; - signal audf3_pulse_noise : std_logic; - - signal audf0_enable : std_logic; - signal audf1_enable : std_logic; - signal audf2_enable : std_logic; - signal audf3_enable : std_logic; - - signal chan0_output_next : std_logic; - signal chan1_output_next : std_logic; - signal chan2_output_next : std_logic; - signal chan3_output_next : std_logic; - signal chan0_output_reg : std_logic; - signal chan1_output_reg : std_logic; - signal chan2_output_reg : std_logic; - signal chan3_output_reg : std_logic; - - signal chan0_output_del_next : std_logic; - signal chan1_output_del_next : std_logic; - signal chan0_output_del_reg : std_logic; - signal chan1_output_del_reg : std_logic; - - signal highpass0_next : std_logic; - signal highpass1_next : std_logic; - signal highpass0_reg : std_logic; - signal highpass1_reg : std_logic; - - signal volume_channel_0_next : std_logic_vector(3 downto 0); - signal volume_channel_1_next : std_logic_vector(3 downto 0); - signal volume_channel_2_next : std_logic_vector(3 downto 0); - signal volume_channel_3_next : std_logic_vector(3 downto 0); - signal volume_channel_0_reg : std_logic_vector(3 downto 0); - signal volume_channel_1_reg : std_logic_vector(3 downto 0); - signal volume_channel_2_reg : std_logic_vector(3 downto 0); - signal volume_channel_3_reg : std_logic_vector(3 downto 0); - - signal addr_decoded : std_logic_vector(15 downto 0); - - signal noise_4 : std_logic; - signal noise_5 : std_logic; - signal noise_large : std_logic; - signal noise_4_next : std_logic_vector(2 downto 0); - signal noise_4_reg : std_logic_vector(2 downto 0); - signal noise_5_next : std_logic_vector(2 downto 0); - signal noise_5_reg : std_logic_vector(2 downto 0); - signal noise_large_next : std_logic_vector(2 downto 0); - signal noise_large_reg : std_logic_vector(2 downto 0); - - signal rand_out : std_logic_vector(7 downto 0); -- snoop part of the shift reg - - signal initmode : std_logic; - - signal irqen_next : std_logic_vector(7 downto 0); - signal irqen_reg : std_logic_vector(7 downto 0); - - signal irqst_next : std_logic_vector(7 downto 0); - signal irqst_reg : std_logic_vector(7 downto 0); - - signal irq_n_next : std_logic; - signal irq_n_reg : std_logic; -- for output - - -- serial ports! - signal serial_ip_ready_interrupt : std_logic; - signal serial_ip_framing_next : std_logic; - signal serial_ip_framing_reg : std_logic; - signal serial_ip_overrun_next : std_logic; - signal serial_ip_overrun_reg : std_logic; - signal serial_op_needed_interrupt : std_logic; - - signal skctl_next : std_logic_vector(7 downto 0); - signal skctl_reg : std_logic_vector(7 downto 0); - - signal serin_shift_next : std_logic_vector(9 downto 0); - signal serin_shift_reg : std_logic_vector(9 downto 0); - signal serin_next : std_logic_vector(7 downto 0); - signal serin_reg : std_logic_vector(7 downto 0); - signal serin_bitcount_next : std_logic_vector(3 downto 0); - signal serin_bitcount_reg : std_logic_vector(3 downto 0); - - signal sio_in1_reg : std_logic; - signal sio_in2_reg : std_logic; - signal sio_in3_reg : std_logic; - signal sio_in_next : std_logic; - signal sio_in_reg : std_logic; - - signal sio_out_next : std_logic; - signal sio_out_reg : std_logic; - signal serial_out_next : std_logic; - signal serial_out_reg : std_logic; - - signal serout_shift_next : std_logic_vector(9 downto 0); - signal serout_shift_reg : std_logic_vector(9 downto 0); - - signal serout_holding_full_next : std_logic; - signal serout_holding_full_reg : std_logic; - signal serout_holding_next : std_logic_vector(7 downto 0); - signal serout_holding_reg : std_logic_vector(7 downto 0); - signal serout_holding_load : std_logic; - - signal serout_bitcount_next : std_logic_vector(3 downto 0); - signal serout_bitcount_reg : std_logic_vector(3 downto 0); - - signal serout_active_next : std_logic; - signal serout_active_reg : std_logic; - - signal serial_reset : std_logic; - signal serout_sync_reset : std_logic; - signal skrest_write : std_logic; - - signal serout_enable : std_logic; - signal serout_enable_delayed : std_logic; - signal serin_enable : std_logic; - - signal async_serial_reset : std_logic; - signal waiting_for_start_bit : std_logic; - - signal serin_clock_next : std_logic; - signal serin_clock_reg : std_logic; - signal serin_clock_last_next : std_logic; - signal serin_clock_last_reg : std_logic; - - signal serout_clock_next : std_logic; - signal serout_clock_reg : std_logic; - signal serout_clock_last_next : std_logic; - signal serout_clock_last_reg : std_logic; - - signal twotone_reset : std_logic; - signal twotone_reset_delayed : std_logic; - signal twotone_next : std_logic; - signal twotone_reg : std_logic; - - signal clock_next : std_logic; - signal clock_reg : std_logic; - signal clock_sync_next : std_logic; - signal clock_sync_reg : std_logic; - signal clock_input : std_logic; - - -- keyboard - signal keyboard_overrun_next : std_logic; - signal keyboard_overrun_reg : std_logic; - - signal shift_held : std_logic; - signal break_irq : std_logic; - signal key_held : std_logic; - signal other_key_irq : std_logic; - - signal kbcode : std_logic_vector(7 downto 0); - - -- pots - signal pot0_next : std_logic_vector(7 downto 0); - signal pot0_reg : std_logic_vector(7 downto 0); - signal pot1_next : std_logic_vector(7 downto 0); - signal pot1_reg : std_logic_vector(7 downto 0); - signal pot2_next : std_logic_vector(7 downto 0); - signal pot2_reg : std_logic_vector(7 downto 0); - signal pot3_next : std_logic_vector(7 downto 0); - signal pot3_reg : std_logic_vector(7 downto 0); - signal pot4_next : std_logic_vector(7 downto 0); - signal pot4_reg : std_logic_vector(7 downto 0); - signal pot5_next : std_logic_vector(7 downto 0); - signal pot5_reg : std_logic_vector(7 downto 0); - signal pot6_next : std_logic_vector(7 downto 0); - signal pot6_reg : std_logic_vector(7 downto 0); - signal pot7_next : std_logic_vector(7 downto 0); - signal pot7_reg : std_logic_vector(7 downto 0); - - signal allpot_next : std_logic_vector(7 downto 0); - signal allpot_reg : std_logic_vector(7 downto 0); - - signal pot_counter_next : std_logic_vector(7 downto 0); - signal pot_counter_reg : std_logic_vector(7 downto 0); - - signal potgo_write : std_logic; - - signal pot_reset_next : std_logic; - signal pot_reset_reg : std_logic; -BEGIN - -- register - process(clk,reset_n) - begin - if (reset_n = '0') then - -- FIXME - Pokey does not have RESET - instead this is caused by 'init' sequence - audf0_reg <= X"00"; - audc0_reg <= X"00"; - audf1_reg <= X"00"; - audc1_reg <= X"00"; - audf2_reg <= X"00"; - audc2_reg <= X"00"; - audf3_reg <= X"00"; - audc3_reg <= X"00"; - audctl_reg <= X"00"; - - irqen_reg <= X"00"; - irqst_reg <= X"FF"; - irq_n_reg <= '1'; - - skctl_reg <= X"00"; - - highpass0_reg <= '0'; - highpass1_reg <= '0'; - - chan0_output_reg <= '0'; - chan1_output_reg <= '0'; - chan2_output_reg <= '0'; - chan3_output_reg <= '0'; - - chan0_output_del_reg <= '0'; - chan1_output_del_reg <= '0'; - - volume_channel_0_reg <= (others=>'0'); - volume_channel_1_reg <= (others=>'0'); - volume_channel_2_reg <= (others=>'0'); - volume_channel_3_reg <= (others=>'0'); - - serin_reg <= (others=>'0'); - serin_shift_reg <= (others=>'0'); - serin_bitcount_reg <= (others=>'0'); - serout_shift_reg <= (others=>'0'); - serout_holding_reg <= (others=>'0'); - serout_holding_full_reg <= '0'; - serout_active_reg <= '0'; - sio_out_reg <= '1'; - serial_out_reg <= '1'; - - serial_ip_framing_reg <= '0'; - serial_ip_overrun_reg <= '0'; - - clock_reg <= '0'; - clock_sync_reg <= '0'; - - keyboard_overrun_reg <= '0'; - - serin_clock_reg <= '0'; - serin_clock_last_reg <= '0'; - serout_clock_reg <= '0'; - serout_clock_last_reg <= '0'; - - twotone_reg <= '0'; - - sio_in_reg <= '0'; - - pot0_reg <= (others=>'0'); - pot1_reg <= (others=>'0'); - pot2_reg <= (others=>'0'); - pot3_reg <= (others=>'0'); - pot4_reg <= (others=>'0'); - pot5_reg <= (others=>'0'); - pot6_reg <= (others=>'0'); - pot7_reg <= (others=>'0'); - - allpot_reg <= (others=>'1'); - - pot_counter_reg <= (others=>'0'); - - pot_reset_reg <= '1'; - - noise_4_reg <= (others=>'0'); - noise_5_reg <= (others=>'0'); - noise_large_reg <= (others=>'0'); - - elsif (clk'event and clk='1') then - audf0_reg <= audf0_next; - audc0_reg <= audc0_next; - audf1_reg <= audf1_next; - audc1_reg <= audc1_next; - audf2_reg <= audf2_next; - audc2_reg <= audc2_next; - audf3_reg <= audf3_next; - audc3_reg <= audc3_next; - audctl_reg <= audctl_next; - - irqen_reg <= irqen_next; - irqst_reg <= irqst_next; - irq_n_reg <= irq_n_next; - - skctl_reg <= skctl_next; - - highpass0_reg <= highpass0_next; - highpass1_reg <= highpass1_next; - - chan0_output_reg <= chan0_output_next; - chan1_output_reg <= chan1_output_next; - chan2_output_reg <= chan2_output_next; - chan3_output_reg <= chan3_output_next; - - chan0_output_del_reg <= chan0_output_del_next; - chan1_output_del_reg <= chan1_output_del_next; - - volume_channel_0_reg<= volume_channel_0_next; - volume_channel_1_reg<= volume_channel_1_next; - volume_channel_2_reg<= volume_channel_2_next; - volume_channel_3_reg<= volume_channel_3_next; - - serin_reg <= serin_next; - serin_shift_reg <= serin_shift_next; - serin_bitcount_reg <= serin_bitcount_next; - serout_shift_reg <= serout_shift_next; - serout_bitcount_reg <= serout_bitcount_next; - - serout_holding_reg<=serout_holding_next; - serout_holding_full_reg<=serout_holding_full_next; - serout_active_reg <= serout_active_next; - - sio_out_reg <= sio_out_next; - serial_out_reg <= serial_out_next; - - serial_ip_framing_reg <= serial_ip_framing_next; - serial_ip_overrun_reg <= serial_ip_overrun_next; - - clock_reg <= clock_next; - clock_sync_reg <= clock_sync_next; - - keyboard_overrun_reg <= keyboard_overrun_next; - - serin_clock_reg <= serin_clock_next; - serin_clock_last_reg <= serin_clock_last_next; - serout_clock_reg <= serout_clock_next; - serout_clock_last_reg <= serout_clock_last_next; - - twotone_reg <= twotone_next; - - sio_in_reg <= sio_in_next; - - pot0_reg <= pot0_next; - pot1_reg <= pot1_next; - pot2_reg <= pot2_next; - pot3_reg <= pot3_next; - pot4_reg <= pot4_next; - pot5_reg <= pot5_next; - pot6_reg <= pot6_next; - pot7_reg <= pot7_next; - - allpot_reg <= allpot_next; - - pot_counter_reg <= pot_counter_next; - - pot_reset_reg <= pot_reset_next; - - noise_4_reg <= noise_4_next; - noise_5_reg <= noise_5_next; - noise_large_reg <= noise_large_next; - end if; - end process; - - -- decode address - decode_addr1 : complete_address_decoder - generic map(width=>4) - port map (addr_in=>addr, addr_decoded=>addr_decoded); - - -- clock selection - process(enable_64,enable_15,enable_179,audctl_reg,audf0_pulse,audf2_pulse) - begin - audf0_enable <= enable_64; - audf1_enable <= enable_64; - audf2_enable <= enable_64; - audf3_enable <= enable_64; - - if (audctl_reg(0) = '1') then - audf0_enable <= enable_15; - audf1_enable <= enable_15; - audf2_enable <= enable_15; - audf3_enable <= enable_15; - end if; - - if (audctl_reg(6) = '1') then - audf0_enable <= enable_179; - end if; - - if (audctl_reg(5) = '1') then - audf2_enable <= enable_179; - end if; - - if(audctl_reg(4) = '1') then - audf1_enable <= audf0_pulse; - end if; - - if(audctl_reg(3) = '1') then - audf3_enable <= audf2_pulse; - end if; - end process; - - -- Instantiate timers - timer0 : pokey_countdown_timer - generic map (UNDERFLOW_DELAY=>3) - port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse); - timer1 : pokey_countdown_timer - generic map (UNDERFLOW_DELAY=>3) - port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse); - timer2 : pokey_countdown_timer - generic map (UNDERFLOW_DELAY=>3) - port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse); - timer3 : pokey_countdown_timer - generic map (UNDERFLOW_DELAY=>3) - port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse); - - -- Timer reloading - process (audctl_reg, audf0_pulse, audf1_pulse, audf2_pulse, audf3_pulse, stimer_write_delayed, async_serial_reset, twotone_reset_delayed) - begin - audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse)) or (audctl_reg(4) and audf1_pulse) or stimer_write_delayed or twotone_reset_delayed; - audf1_reload <= audf1_pulse or stimer_write_delayed or twotone_reset_delayed; - audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse)) or (audctl_reg(3) and audf3_pulse) or stimer_write_delayed or async_serial_reset; - audf3_reload <= audf3_pulse or stimer_write_delayed or async_serial_reset; - end process; - - twotone_del : latch_delay_line - generic map (count=>2) - port map (clk=>clk, sync_reset=>'0',data_in=>twotone_reset, enable=>enable_179, reset_n=>reset_n, data_out=>twotone_reset_delayed); --- twotone_reset_delayed <= twotone_reset; - - -- Writes to registers - process(data_in,wr_en,addr_decoded,audf0_reg,audc0_reg,audf1_reg,audc1_reg,audf2_reg,audc2_reg,audf3_reg,audc3_reg,audf0_enable,audf1_enable,audf2_enable,audf3_enable,audctl_reg, irqen_reg, skctl_reg, serout_holding_reg) - begin - audf0_next <= audf0_reg; - audc0_next <= audc0_reg; - audf1_next <= audf1_reg; - audc1_next <= audc1_reg; - audf2_next <= audf2_reg; - audc2_next <= audc2_reg; - audf3_next <= audf3_reg; - audc3_next <= audc3_reg; - audctl_next <= audctl_reg; - - irqen_next <= irqen_reg; - skctl_next <= skctl_reg; - - stimer_write <= '0'; - - serout_holding_load <= '0'; - serout_holding_next <= serout_holding_reg; - - serial_reset <= '0'; - skrest_write <= '0'; - potgo_write <= '0'; - - if (wr_en = '1') then - if(addr_decoded(0) = '1') then - audf0_next <= data_in; - end if; - - if(addr_decoded(1) = '1') then - audc0_next <= data_in; - end if; - - if(addr_decoded(2) = '1') then - audf1_next <= data_in; - end if; - - if(addr_decoded(3) = '1') then - audc1_next <= data_in; - end if; - - if(addr_decoded(4) = '1') then - audf2_next <= data_in; - end if; - - if(addr_decoded(5) = '1') then - audc2_next <= data_in; - end if; - - if(addr_decoded(6) = '1') then - audf3_next <= data_in; - end if; - - if(addr_decoded(7) = '1') then - audc3_next <= data_in; - end if; - - if(addr_decoded(8) = '1') then - audctl_next <= data_in; - end if; - - if (addr_decoded(9) = '1') then --STIMER - stimer_write <= '1'; - end if; - - if (addr_decoded(10) = '1') then -- skrest - resets the serial input problems - overflow etc - skrest_write <= '1'; - end if; - - if (addr_decoded(11) = '1') then -- POTGO - start POT scan - potgo_write <= '1'; - end if; - - if (addr_decoded(13) = '1') then --SEROUT - serout_holding_next <= data_in; - serout_holding_load <= '1'; - end if; - - if (addr_decoded(14) = '1') then --IRQEN - irqen_next <= data_in; - end if; - - if (addr_decoded(15) = '1') then --SKCTL - skctl_next <= data_in; - - if (data_in(6 downto 4)="000") then - serial_reset <= '1'; - end if; - end if; - - end if; - end process; - - -- Read from registers - process(addr_decoded,kbcode,RAND_OUT,IRQST_REG,key_held,shift_held,sio_in_reg,serin_reg,keyboard_overrun_reg, serial_ip_framing_reg, serial_ip_overrun_reg, waiting_for_start_bit, pot_in, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg, allpot_reg) - begin - data_out <= X"FF"; - - if(addr_decoded(0) = '1') then --POT0 - data_out <= pot0_reg; - end if; - - if(addr_decoded(1) = '1') then --POT1 - data_out <= pot1_reg; - end if; - - if(addr_decoded(2) = '1') then --POT2 - data_out <= pot2_reg; - end if; - - if(addr_decoded(3) = '1') then --POT3 - data_out <= pot3_reg; - end if; - - if(addr_decoded(4) = '1') then --POT4 - data_out <= pot4_reg; - end if; - - if(addr_decoded(5) = '1') then --POT5 - data_out <= pot5_reg; - end if; - - if(addr_decoded(6) = '1') then --POT6 - data_out <= pot6_reg; - end if; - - if(addr_decoded(7) = '1') then --POT7 - data_out <= pot7_reg; - end if; - - if(addr_decoded(8) = '1') then --ALLPOT - data_out <= allpot_reg; - end if; - - if(addr_decoded(9) = '1') then --KBCODE - data_out <= kbcode; - end if; - - if(addr_decoded(10) = '1') then -- RANDOM - data_out <= RAND_OUT; - end if; - - if (addr_decoded(13) = '1') then --SERIN - data_out <= serin_reg; - end if; - - if (addr_decoded(14) = '1') then --IRQST - bits set to low when irq - data_out <= IRQST_REG; - --break_irq_n & other_key_irq_n & serial_ip_irq_n & serial_op_irq_n & serial_trans_irq_n & timer3_irq_n & timer_1_irq_n & timer_0_irq_n - end if; - - if (addr_decoded(15) = '1') then --SKSTAT - data_out <= not(serial_ip_framing_reg)¬(keyboard_overrun_reg)¬(serial_ip_overrun_reg)&sio_in_reg¬(shift_held)¬(key_held)&waiting_for_start_bit&"1"; - end if; - - end process; - - -- Fire interrupts - process (irqen_reg, irqst_reg, audf0_pulse, audf1_pulse, audf3_pulse, other_key_irq, serial_ip_ready_interrupt, serout_active_reg, serial_op_needed_interrupt, break_irq) - begin - -- clear interrupts - irqst_next <= irqst_reg or not(irqen_reg); - - irq_n_next <= '0'; - - if ((irqst_reg or "0000"¬(irqen_reg(3))&"000") = X"FF") then - irq_n_next <= '1'; - end if; - - -- set interrupts - if (audf0_pulse = '1') then - irqst_next(0) <= not(irqen_reg(0)); - end if; - - if (audf1_pulse = '1') then - irqst_next(1) <= not(irqen_reg(1)); - end if; - - if (audf3_pulse = '1') then - irqst_next(2) <= not(irqen_reg(2)); - end if; - - if (other_key_irq = '1') then - irqst_next(6) <= not(irqen_reg(6)); - end if; - - if (break_irq = '1') then - irqst_next(7) <= not(irqen_reg(7)); - end if; - - if (serial_ip_ready_interrupt = '1') then - irqst_next(5) <= not(irqen_reg(5)); - end if; - - irqst_next(3) <= serout_active_reg; - - if (serial_op_needed_interrupt = '1') then - irqst_next(4) <= not(irqen_reg(4)); - end if; - - end process; - - -- Instantiate delay for stimer reload_request - stimer_delay : latch_delay_line - generic map (count=>3) - port map (clk=>clk, sync_reset=>'0',data_in=>stimer_write, enable=>enable_179, reset_n=>reset_n, data_out=>stimer_write_delayed); - - --stimer_write_delayed <= stimer_write; - - -- Instantiate audio noise filters - pokey_noise_filter0 : pokey_noise_filter - port map(clk=>clk,reset_n=>reset_n,noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large, sync_reset=>stimer_write_delayed); - pokey_noise_filter1 : pokey_noise_filter - port map(clk=>clk,reset_n=>reset_n,noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4_reg(0),noise_5=>noise_5_reg(0),noise_large=>noise_large_reg(0), sync_reset=>stimer_write_delayed); - pokey_noise_filter2 : pokey_noise_filter - port map(clk=>clk,reset_n=>reset_n,noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4_reg(1),noise_5=>noise_5_reg(1),noise_large=>noise_large_reg(1), sync_reset=>stimer_write_delayed); - pokey_noise_filter3 : pokey_noise_filter - port map(clk=>clk,reset_n=>reset_n,noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4_reg(2),noise_5=>noise_5_reg(2),noise_large=>noise_large_reg(2), sync_reset=>stimer_write_delayed); - - -- Audio output stage - -- (toggling now handled in the noise filter - the subtlety on when to toggle and when to sample is important) - chan0_output_next <= audf0_pulse_noise; - chan1_output_next <= audf1_pulse_noise; - chan2_output_next <= audf2_pulse_noise; - chan3_output_next <= audf3_pulse_noise; - - -- High pass filters - process(audctl_reg,audf2_pulse,audf3_pulse,chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, highpass0_reg, highpass1_reg) - begin - highpass0_next <= highpass0_reg; - highpass1_next <= highpass1_reg; - - if (audctl_reg(2) = '1') then - if (audf2_pulse = '1') then - highpass0_next <= chan0_output_reg; - end if; - else - highpass0_next <= '1'; - end if; - - if (audctl_reg(1) = '1') then - if (audf3_pulse = '1') then - highpass1_next <= chan1_output_reg; - end if; - else - highpass1_next <= '1'; - end if; - - end process; - - process(chan0_output_reg,chan1_output_reg,chan0_output_del_reg,chan1_output_del_reg,enable_179) - begin - chan0_output_del_next <= chan0_output_del_reg; - chan1_output_del_next <= chan1_output_del_reg; - - if (enable_179 = '1') then - chan0_output_del_next <= chan0_output_reg; - chan1_output_del_next <= chan1_output_reg; - end if; - end process; - - -- Instantiate key pokey clocks - -- ~1.79MHz - from 25MHz/14 - -- ~64KHz - from 1.79MHz/28 - -- ~15KHz - from 1.79MHz/114 - --enable_179_div : enable_divider - -- generic map (COUNT=>14) - -- port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179); - - -- resetcount 6/33 - enable_64_div : syncreset_enable_divider - generic map (COUNT=>28,RESETCOUNT=>6) -- 28-22 - port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_64); - - enable_15_div : syncreset_enable_divider - generic map (COUNT=>114,RESETCOUNT=>33) -- 114-81 - port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_15); - - -- Instantiate pokey noise circuits (lfsr) - initmode <= skctl_next(1) nor skctl_next(0); - poly_17_19_lfsr : pokey_poly_17_9 - port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,select_9_17=>audctl_reg(7),bit_out=>noise_large,rand_out=>rand_out); - - poly_5_lfsr : pokey_poly_5 - port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_5); - - poly_4_lfsr : pokey_poly_4 - port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4); - - -- Delay between feeding noise between channels - process(noise_large_reg, noise_5_reg, noise_4_reg, noise_large, noise_5, noise_4, enable_179) - begin - noise_large_next <= noise_large_reg; - noise_5_next <= noise_5_reg; - noise_4_next <= noise_4_reg; - - if (enable_179='1') then - noise_large_next <= noise_large_reg(1 downto 0)&noise_large; - noise_5_next <= noise_5_reg(1 downto 0)&noise_5; - noise_4_next <= noise_4_reg(1 downto 0)&noise_4; - end if; - end process; - - --AUDIO_LEFT <= "000"&count_reg(15 downto 3); - process(chan0_output_del_reg, chan1_output_del_reg, chan2_output_reg, chan3_output_reg, audc0_reg, audc1_reg, audc2_reg, audc3_reg, highpass0_reg, highpass1_reg) - begin - volume_channel_0_next <= "0000"; - volume_channel_1_next <= "0000"; - volume_channel_2_next <= "0000"; - volume_channel_3_next <= "0000"; - - if (((chan0_output_del_reg xor highpass0_reg) or audc0_reg(4)) = '1') then - volume_channel_0_next <= audc0_reg(3 downto 0); - end if; - - if (((chan1_output_del_reg xor highpass1_reg) or audc1_reg(4)) = '1') then - volume_channel_1_next <= audc1_reg(3 downto 0); - end if; - - if ((chan2_output_reg or audc2_reg(4)) = '1') then - volume_channel_2_next <= audc2_reg(3 downto 0); - end if; - - if ((chan3_output_reg or audc3_reg(4)) = '1') then - volume_channel_3_next <= audc3_reg(3 downto 0); - end if; - - end process; - - -- serial port output - -- urghhh (TODO: If timers are cleared with stimer_write, some clocks are still triggering. This workaround fixes the acid test. Investigate the proper fix) - serout_sync_reset <= serial_reset or stimer_write_delayed; - serout_clock_delay : delay_line - generic map (count=>2) - port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed); - - - process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset) - begin - serout_clock_next <= serout_clock_reg; - serout_clock_last_next <= serout_clock_reg; - - serout_shift_next <= serout_shift_reg; - serout_bitcount_next <= serout_bitcount_reg; - serout_holding_full_next <= serout_holding_full_reg; - serout_active_next <= serout_active_reg; - - serial_out_next <= serial_out_reg; -- output from shift reg (if unchanged) - sio_out_next <= serial_out_reg; - - -- two tone output - twotone_next <= twotone_reg; - twotone_reset <= '0'; - - if ((audf1_pulse or (audf0_pulse and serial_out_reg)) = '1') then - twotone_next <= not(twotone_reg); - twotone_reset <= skctl_reg(3); - end if; - - if (skctl_reg(3) = '1') then - sio_out_next <= twotone_reg; - end if; - - serial_op_needed_interrupt <= '0'; - - -- generate clock from enable signals - if (serout_enable_delayed = '1') then - serout_clock_next <= not(serout_clock_reg); - end if; - - -- output bits over sio - if (serout_clock_last_reg = '0' and serout_clock_reg = '1') then - serout_shift_next <= '0'&serout_shift_reg(9 downto 1); -- next - serial_out_next <= serout_shift_reg(1) or not(serout_active_reg); -- i.e. next serout_shift_reg(0) - - -- reload - if (serout_bitcount_reg = X"0") then - if (serout_holding_full_reg='1') then -- unless, more to send in holding reg? - serout_bitcount_next <= X"9"; -- 10 bits to send, 9 more after this - serout_shift_next <= '1'&serout_holding_reg&'0'; - serial_out_next <= '0'; -- start bit (serout_shift_reg(0) after this cycle) - serout_holding_full_next <= '0'; - serial_op_needed_interrupt <= '1'; -- more data please! - serout_active_next <= '1'; - else - serout_active_next <= '0'; - serial_out_next <= '1'; -- remove blip! - end if; - else - serout_bitcount_next <= std_logic_vector(unsigned(serout_bitcount_reg)-1); - end if; - end if; - - -- force break - if (skctl_reg(7) = '1') then - serial_out_next <= '0'; - end if; - - -- register to load has been written too, update our state to reflect that it is full - if (serout_holding_load = '1') then - serout_holding_full_next <= '1'; - end if; - - if (serial_reset = '1') then - twotone_next <= '0'; - serout_bitcount_next <= (others=>'0'); - serout_shift_next <= (others=>'0'); - serout_holding_full_next <= '0'; - serout_clock_next <= '0'; - serout_clock_last_next <= '0'; - serout_active_next <= '0'; - end if; - end process; - - -- serial port input - sio_in1_synchronizer : synchronizer - port map (clk=>clk, raw=>sio_in1, sync=>sio_in1_reg); - sio_in2_synchronizer : synchronizer - port map (clk=>clk, raw=>sio_in2, sync=>sio_in2_reg); - sio_in3_synchronizer : synchronizer - port map (clk=>clk, raw=>sio_in3, sync=>sio_in3_reg); - sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg; - - waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0'; - process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset) - begin - serin_clock_next <= serin_clock_reg; - serin_clock_last_next <= serin_clock_reg; - - serin_shift_next <= serin_shift_reg; - serin_bitcount_next <= serin_bitcount_reg; - serin_next <= serin_reg; - - serial_ip_overrun_next <= serial_ip_overrun_reg; - serial_ip_framing_next <= serial_ip_framing_reg; - serial_ip_ready_interrupt <= '0'; - - async_serial_reset <= '0'; - - -- generate clock from enable signals - if (serin_enable = '1') then - serin_clock_next <= not(serin_clock_reg); - end if; - - -- resync clock on receipt of start bit - if ((skctl_reg(4) and sio_in_reg and waiting_for_start_bit)= '1') then - async_serial_reset <= '1'; - serin_clock_next <= '1'; - end if; - - -- receive bits into shift reg - if (serin_clock_last_reg='1' and serin_clock_reg='0') then -- failing edge - if (((waiting_for_start_bit and not(sio_in_reg)) or not(waiting_for_start_bit))='1') then - serin_shift_next <= sio_in_reg&serin_shift_reg(9 downto 1); - - if (serin_bitcount_reg = X"0") then -- full byte - serin_next <= serin_shift_reg(9 downto 2); -- not shifted yet - - serin_bitcount_next <= X"9"; -- next... no disable for serial input, always happening. - - -- irq to alert new data avilable - serial_ip_ready_interrupt <= '1'; - - -- flag up overrun - if (irqst_reg(5) = '0') then -- if interrupt bit not cleared yet... - serial_ip_overrun_next <= '1'; - end if; - - -- flag up framing problem (stop bit is 1 - pull from sio since reg not yet shifted) - if (sio_in_reg='0') then - serial_ip_framing_next <= '1'; - end if; - else - serin_bitcount_next <= std_logic_vector(unsigned(serin_bitcount_reg)-1); - end if; - end if; - end if; - - if (skrest_write = '1') then - serial_ip_overrun_next <= '0'; - serial_ip_framing_next <= '0'; - end if; - - if (serial_reset = '1') then - serin_clock_next <= '0'; - serin_bitcount_next <= X"9"; -- i.e. waiting for start bit - serin_shift_next <= (others=>'0'); - end if; - end process; - - -- serial clocks - process(sio_clockin_in,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse) - begin - clock_next <= sio_clockin_in; - clock_sync_next <= clock_reg; - - serout_enable <= '0'; - serin_enable <= '0'; - clock_input <= '1'; -- when output, outputs channel 4 - - case skctl_reg(6 downto 4) is - when "000" => - serin_enable <= not(clock_sync_reg) and clock_reg; - serout_enable <= not(clock_sync_reg) and clock_reg; - when "001" => - serin_enable <= audf3_pulse; - serout_enable <= not(clock_sync_reg) and clock_reg; - when "010" => - serin_enable <= audf3_pulse; - serout_enable <= audf3_pulse; - clock_input <= '0'; - when "011" => - serin_enable <= audf3_pulse; - serout_enable <= audf3_pulse; - when "100" => - serin_enable <= not(clock_sync_reg) and clock_reg; - serout_enable <= audf3_pulse; - when "101" => - serin_enable <= audf3_pulse; - serout_enable <= audf3_pulse; - when "110" => - serin_enable <= audf3_pulse; - serout_enable <= audf1_pulse; - clock_input <= '0'; - when "111" => - serin_enable <= audf3_pulse; - serout_enable <= audf1_pulse; - when others => - -- nop - end case; - end process; - - -- keyboard overrun (i.e. second key pressed before interrupt cleared) - process(other_key_irq,keyboard_overrun_reg,skrest_write,irqst_reg) - begin - keyboard_overrun_next <= keyboard_overrun_reg; - - if (other_key_irq='1' and irqst_reg(6)='0') then - keyboard_overrun_next <= '1'; - end if; - - if (skrest_write = '1') then - keyboard_overrun_next <= '0'; - end if; - end process; - - -- keyboard scan -gen_custom_scan : if custom_keyboard_scan=1 generate - pokey_keyboard_scanner1 : pokey_keyboard_scanner - port map (clk=>clk, reset_n=>reset_n, enable=>keyboard_scan_enable, keyboard_response=>keyboard_response, debounce_disable=>not(skctl_reg(0)), scan_enable=>skctl_reg(1), keyboard_scan=>keyboard_scan, key_held=>key_held, shift_held=>shift_held, keycode=>kbcode, other_key_irq=>other_key_irq, break_irq=>break_irq); -end generate; - -gen_normal_scan : if custom_keyboard_scan=0 generate - pokey_keyboard_scanner1 : pokey_keyboard_scanner - port map (clk=>clk, reset_n=>reset_n, enable=>enable_15, keyboard_response=>keyboard_response, debounce_disable=>not(skctl_reg(0)), scan_enable=>skctl_reg(1), keyboard_scan=>keyboard_scan, key_held=>key_held, shift_held=>shift_held, keycode=>kbcode, other_key_irq=>other_key_irq, break_irq=>break_irq); -end generate; - - -- POT scan - process(potgo_write, pot_reset_reg, pot_counter_reg, pot_in, enable_15, enable_179, skctl_reg, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg, allpot_reg) - begin - pot0_next <= pot0_reg; - pot1_next <= pot1_reg; - pot2_next <= pot2_reg; - pot3_next <= pot3_reg; - pot4_next <= pot4_reg; - pot5_next <= pot5_reg; - pot6_next <= pot6_reg; - pot7_next <= pot7_reg; - - allpot_next <= allpot_reg; - - pot_reset_next <= pot_reset_reg; - - pot_counter_next <= pot_counter_reg; - - if (((enable_15 and not(skctl_reg(2))) or (enable_179 and skctl_reg(2))) = '1') then - pot_counter_next <= std_logic_vector(unsigned(pot_counter_reg) + 1); - if (pot_counter_reg = X"E4") then - pot_reset_next <= '1'; -- turn on pot dump transistors - allpot_next <= (others=>'0'); - end if; - - if (pot_reset_reg = '0') then - if (pot_in(0) = '0') then -- pot now high, latch - pot0_next <= pot_counter_reg; - end if; - if (pot_in(1) = '0') then -- pot now high, latch - pot1_next <= pot_counter_reg; - end if; - if (pot_in(2) = '0') then -- pot now high, latch - pot2_next <= pot_counter_reg; - end if; - if (pot_in(3) = '0') then -- pot now high, latch - pot3_next <= pot_counter_reg; - end if; - if (pot_in(4) = '0') then -- pot now high, latch - pot4_next <= pot_counter_reg; - end if; - if (pot_in(5) = '0') then -- pot now high, latch - pot5_next <= pot_counter_reg; - end if; - if (pot_in(6) = '0') then -- pot now high, latch - pot6_next <= pot_counter_reg; - end if; - if (pot_in(7) = '0') then -- pot now high, latch - pot7_next <= pot_counter_reg; - end if; - - allpot_next <= allpot_reg and not(pot_in); - end if; - end if; - - if (potgo_write = '1') then - pot_counter_next <= (others=>'0'); - pot_reset_next <= '0'; -- turn off pot dump transistors, so they start to get charged - allpot_next <= (others=>'1'); - end if; - end process; - - -- Outputs - irq_n_out <= irq_n_reg; - - CHANNEL_0_OUT <= volume_channel_0_reg; - CHANNEL_1_OUT <= volume_channel_1_reg; - CHANNEL_2_OUT <= volume_channel_2_reg; - CHANNEL_3_OUT <= volume_channel_3_reg; - - sio_out1 <= sio_out_reg; - sio_out2 <= sio_out_reg; - sio_out3 <= sio_out_reg; - - sio_clockout <= serout_clock_reg; - sio_clockin_oe <= not(clock_input); - sio_clockin_out <= serin_clock_reg; - - pot_reset <= pot_reset_reg; - -END vhdl; - - diff --git a/common/Sound/Pokey MrX/pokey_countdown_timer.vhdl b/common/Sound/Pokey MrX/pokey_countdown_timer.vhdl deleted file mode 100644 index fd7c1dc3..00000000 --- a/common/Sound/Pokey MrX/pokey_countdown_timer.vhdl +++ /dev/null @@ -1,102 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY pokey_countdown_timer IS -generic(UNDERFLOW_DELAY : natural := 3); -PORT -( - CLK : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - ENABLE_UNDERFLOW : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - - WR_EN : IN STD_LOGIC; - DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0); - - DATA_OUT : OUT STD_LOGIC -); -END pokey_countdown_timer; - -ARCHITECTURE vhdl OF pokey_countdown_timer IS - component delay_line IS - generic(COUNT : natural := 1); - PORT - ( - CLK : IN STD_LOGIC; - SYNC_RESET : IN STD_LOGIC; - DATA_IN : IN STD_LOGIC; - - ENABLE : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - - DATA_OUT : OUT STD_LOGIC - ); - END component; - - function To_Std_Logic(L: BOOLEAN) return std_ulogic is - begin - if L then - return('1'); - else - return('0'); - end if; - end function To_Std_Logic; - - signal count_reg : std_logic_vector(7 downto 0); - signal count_next: std_logic_vector(7 downto 0); - - signal underflow : std_logic; - - signal count_command : std_logic_vector(1 downto 0); - signal underflow_command: std_logic_vector(1 downto 0); -BEGIN - -- Instantiate delay (provides output) - underflow0_delay : delay_line - generic map (COUNT=>UNDERFLOW_DELAY) - port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out); - - -- register - process(clk,reset_n) - begin - if (reset_N = '0') then - count_reg <= (others=>'0'); - elsif (clk'event and clk='1') then - count_reg <= count_next; - end if; - end process; - - -- count down on enable - process(count_reg,enable,wr_en,count_command,data_in) - begin - count_command <= enable&wr_en; - case count_command is - when "10" => - count_next <= std_logic_vector(unsigned(count_reg) -1); - when "01"|"11" => - count_next <= data_in; - when others => - count_next <= count_reg; - end case; - end process; - - -- underflow - process(count_reg,enable,underflow_command) - begin - underflow_command <= enable & To_Std_Logic(count_reg = X"00"); - case underflow_command is - when "11" => - underflow <= '1'; - when others => - underflow <= '0'; - end case; - end process; - -END vhdl; diff --git a/common/Sound/Pokey MrX/pokey_keyboard_scanner.vhdl b/common/Sound/Pokey MrX/pokey_keyboard_scanner.vhdl deleted file mode 100644 index 5ce97b13..00000000 --- a/common/Sound/Pokey MrX/pokey_keyboard_scanner.vhdl +++ /dev/null @@ -1,202 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity pokey_keyboard_scanner is -port -( - clk : in std_logic; - reset_n : in std_logic; - - enable : in std_logic; -- typically hsync or equiv timing - keyboard_response : in std_logic_vector(1 downto 0); - debounce_disable : in std_logic; - scan_enable : in std_logic; - - keyboard_scan : out std_logic_vector(5 downto 0); - - key_held : out std_logic; - shift_held : out std_logic; - keycode : out std_logic_vector(7 downto 0); - other_key_irq : out std_logic; - break_irq : out std_logic -); -end pokey_keyboard_scanner; - -architecture vhdl of pokey_keyboard_scanner is - signal bincnt_next : std_logic_vector(5 downto 0); - signal bincnt_reg : std_logic_vector(5 downto 0); - - signal break_pressed_next : std_logic; - signal break_pressed_reg : std_logic; - - signal shift_pressed_next : std_logic; - signal shift_pressed_reg : std_logic; - - signal control_pressed_next : std_logic; - signal control_pressed_reg : std_logic; - - signal compare_latch_next : std_logic_vector(5 downto 0); - signal compare_latch_reg : std_logic_vector(5 downto 0); - - signal keycode_latch_next : std_logic_vector(7 downto 0); - signal keycode_latch_reg : std_logic_vector(7 downto 0); - - signal irq_next : std_logic; - signal irq_reg : std_logic; - - signal break_irq_next : std_logic; - signal break_irq_reg : std_logic; - - signal key_held_next : std_logic; - signal key_held_reg : std_logic; - - signal my_key : std_logic; - - signal state_next : std_logic_vector(1 downto 0); - signal state_reg : std_logic_vector(1 downto 0); - constant state_wait_key : std_logic_vector(1 downto 0) := "00"; - constant state_key_bounce : std_logic_vector(1 downto 0) := "01"; - constant state_valid_key : std_logic_vector(1 downto 0) := "10"; - constant state_key_debounce : std_logic_vector(1 downto 0) := "11"; -begin - - -- register - process(clk,reset_n) - begin - if (reset_n = '0') then - bincnt_reg <= (others=>'0'); - break_pressed_reg <= '0'; - shift_pressed_reg <= '0'; - control_pressed_reg <= '0'; - compare_latch_reg <= (others=>'0'); - keycode_latch_reg <= (others=>'1'); - key_held_reg <= '0'; - state_reg <= state_wait_key; - irq_reg <= '0'; - break_irq_reg <= '0'; - elsif (clk'event and clk = '1') then - bincnt_reg <= bincnt_next; - state_reg <= state_next; - break_pressed_reg <= break_pressed_next; - shift_pressed_reg <= shift_pressed_next; - control_pressed_reg <= control_pressed_next; - compare_latch_reg <= compare_latch_next; - keycode_latch_reg <= keycode_latch_next; - key_held_reg <= key_held_next; - state_reg <= state_next; - irq_reg <= irq_next; - break_irq_reg <= break_irq_next; - end if; - end process; - - process (enable, keyboard_response, scan_enable, key_held_reg, my_key, state_reg,bincnt_reg, compare_latch_reg, break_pressed_next, break_pressed_reg, shift_pressed_reg, break_irq_reg, control_pressed_reg, keycode_latch_reg, debounce_disable) - begin - bincnt_next <= bincnt_reg; - state_next <= state_reg; - compare_latch_next <= compare_latch_reg; - irq_next <= '0'; - break_irq_next <= '0'; - break_pressed_next <= break_pressed_reg; - shift_pressed_next <= shift_pressed_reg; - control_pressed_next <= control_pressed_reg; - keycode_latch_next <= keycode_latch_reg; - key_held_next <= key_held_reg; - - my_key <= '0'; - if (bincnt_reg = compare_latch_reg or debounce_disable='1') then - my_key <= '1'; - end if; - - if (enable = '1' and scan_enable='1') then - bincnt_next <= std_logic_vector(unsigned(bincnt_reg) + 1); -- check another key - - key_held_next<= '0'; - - case state_reg is - when state_wait_key => - if (keyboard_response(0) = '0') then -- detected key press - if (debounce_disable = '1') then - keycode_latch_next <= control_pressed_reg&shift_pressed_reg&bincnt_reg; - irq_next <= '1'; - key_held_next<= '1'; - else - state_next <= state_key_bounce; - compare_latch_next <= bincnt_reg; - end if; - end if; - - when state_key_bounce => - if (keyboard_response(0) = '0') then -- detected key press - if (my_key = '1') then -- same key - keycode_latch_next <= control_pressed_reg&shift_pressed_reg&compare_latch_reg; - irq_next <= '1'; - key_held_next<= '1'; - state_next <= state_valid_key; - else -- different key (multiple keys pressed) - state_next <= state_wait_key; - end if; - else -- key not pressed - if (my_key = '1') then -- same key, no longer pressed - state_next <= state_wait_key; - end if; - end if; - - when state_valid_key => - key_held_next<= '1'; - if (my_key = '1') then -- only response to my key - if (keyboard_response(0) = '1') then -- no longer pressed - state_next <= state_key_debounce; - end if; - end if; - - when state_key_debounce => - key_held_next<= '1'; - if (my_key = '1') then - if (keyboard_response(0) = '1') then -- no longer pressed - key_held_next<= '0'; - state_next <= state_wait_key; - else - state_next <= state_valid_key; - end if; - end if; - - when others=> - state_next <= state_wait_key; - end case; - - if (bincnt_reg(3 downto 0) = "0000") then - case bincnt_reg(5 downto 4) is - when "11" => - break_pressed_next <= not(keyboard_response(1)); --0x30 - when "01" => - shift_pressed_next <= not(keyboard_response(1)); --0x10 - when "00" => - control_pressed_next <= not(keyboard_response(1)); -- 0x00 - when others => - -- - end case; - end if; - end if; - - if (break_pressed_next='1' and break_pressed_reg='0') then - break_irq_next <= '1'; - end if; - end process; - - -- outputs - keyboard_scan <= not(bincnt_reg); - - key_held <= key_held_reg; - shift_held <= shift_pressed_reg; - keycode <= keycode_latch_reg; - other_key_irq <= irq_reg; - break_irq <= break_irq_reg; -end vhdl; diff --git a/common/Sound/Pokey MrX/pokey_noise_filter.vhdl b/common/Sound/Pokey MrX/pokey_noise_filter.vhdl deleted file mode 100644 index 9c00918c..00000000 --- a/common/Sound/Pokey MrX/pokey_noise_filter.vhdl +++ /dev/null @@ -1,79 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY pokey_noise_filter IS -PORT -( - CLK : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - - NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0); - - PULSE_IN : IN STD_LOGIC; - - NOISE_4 : IN STD_LOGIC; - NOISE_5 : IN STD_LOGIC; - NOISE_LARGE : IN STD_LOGIC; - - SYNC_RESET : IN STD_LOGIC; - - PULSE_OUT : OUT STD_LOGIC -); -END pokey_noise_filter; - -ARCHITECTURE vhdl OF pokey_noise_filter IS --- signal pulse_noise_a : std_logic; --- signal pulse_noise_b : std_logic; - - signal audclk : std_logic; - signal out_next : std_logic; - signal out_reg : std_logic; -BEGIN - process(clk,reset_n) - begin - if (reset_n='0') then - out_reg <= '0'; - elsif (clk'event and clk='1') then - out_reg <= out_next; - end if; - end process; - - pulse_out <= out_reg; - - process(pulse_in, noise_4, noise_5, noise_large, noise_select, audclk, out_reg, sync_reset) - begin - audclk <= pulse_in; - out_next <= out_reg; - - if (NOISE_SELECT(2) = '0') then - audclk <= pulse_in and noise_5; - end if; - - if (audclk = '1') then - if (NOISE_SELECT(0) = '1') then - -- toggle - out_next <= not(out_reg); - else - -- sample - if (NOISE_SELECT(1) = '1') then - out_next <= noise_4; - else - out_next <= noise_large; - end if; - end if; - end if; - - if (sync_reset = '1') then - out_next <= '0'; - end if; - - end process; -end vhdl; diff --git a/common/Sound/Pokey MrX/pokey_poly_17_9.vhdl b/common/Sound/Pokey MrX/pokey_poly_17_9.vhdl deleted file mode 100644 index 964168ff..00000000 --- a/common/Sound/Pokey MrX/pokey_poly_17_9.vhdl +++ /dev/null @@ -1,77 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY pokey_poly_17_9 IS -PORT -( - CLK : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low - INIT : IN STD_LOGIC; - - BIT_OUT : OUT STD_LOGIC; - - RAND_OUT : OUT std_logic_vector(7 downto 0) -); -END pokey_poly_17_9; - -ARCHITECTURE vhdl OF pokey_poly_17_9 IS - signal shift_reg: std_logic_vector(16 downto 0); - signal shift_next: std_logic_vector(16 downto 0); - - signal cycle_delay_reg : std_logic; - signal cycle_delay_next : std_logic; - - signal select_9_17_del_reg : std_logic; - signal select_9_17_del_next : std_logic; - - signal feedback : std_logic; -BEGIN - -- register - process(clk,reset_n) - begin - if (reset_n = '0') then - shift_reg <= "01010101010101010"; - cycle_delay_reg <= '0'; - select_9_17_del_reg <= '0'; - elsif (clk'event and clk='1') then - shift_reg <= shift_next; - cycle_delay_reg <= cycle_delay_next; - select_9_17_del_reg <= select_9_17_del_next; - end if; - end process; - - -- next state (as pokey decap) - feedback <= shift_reg(13) xnor shift_reg(8); - process(enable,shift_reg,feedback,select_9_17,select_9_17_del_reg,init,cycle_delay_reg) - begin - shift_next <= shift_reg; - cycle_delay_next <= cycle_delay_reg; - select_9_17_del_next <= select_9_17_del_reg; - - if (enable = '1') then - select_9_17_del_next <= select_9_17; - shift_next(15 downto 8) <= shift_reg(16 downto 9); - shift_next(7) <= feedback; - shift_next(6 downto 0) <= shift_reg(7 downto 1); - - shift_next(16) <= ((feedback and select_9_17_del_reg) or (shift_reg(0) and not(select_9_17))) and not(init); - - cycle_delay_next <= shift_reg(9); - end if; - end process; - - -- output - bit_out <= cycle_delay_reg; -- from pokey schematics - RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8)); - -END vhdl; diff --git a/common/Sound/Pokey MrX/pokey_poly_4.vhdl b/common/Sound/Pokey MrX/pokey_poly_4.vhdl deleted file mode 100644 index 76ff2b19..00000000 --- a/common/Sound/Pokey MrX/pokey_poly_4.vhdl +++ /dev/null @@ -1,50 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY pokey_poly_4 IS -PORT -( - CLK : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - INIT : IN STD_LOGIC; - - BIT_OUT : OUT STD_LOGIC -); -END pokey_poly_4; - -ARCHITECTURE vhdl OF pokey_poly_4 IS - signal shift_reg: std_logic_vector(3 downto 0); - signal shift_next: std_logic_vector(3 downto 0); -BEGIN - -- register - process(clk, reset_n) - begin - if (reset_n = '0') then - shift_reg <= "1010"; - elsif (clk'event and clk='1') then - shift_reg <= shift_next; - end if; - end process; - - -- next state - process(shift_reg,enable,init) - begin - shift_next <= shift_reg; - if (enable = '1') then - shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1); - end if; - end process; - - -- output - bit_out <= shift_reg(0); - -END vhdl; diff --git a/common/Sound/Pokey MrX/pokey_poly_5.vhdl b/common/Sound/Pokey MrX/pokey_poly_5.vhdl deleted file mode 100644 index e64b9324..00000000 --- a/common/Sound/Pokey MrX/pokey_poly_5.vhdl +++ /dev/null @@ -1,50 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY pokey_poly_5 IS -PORT -( - CLK : IN STD_LOGIC; - RESET_N : IN STD_LOGIC; - ENABLE : IN STD_LOGIC; - INIT : IN STD_LOGIC; - - BIT_OUT : OUT STD_LOGIC -); -END pokey_poly_5; - -ARCHITECTURE vhdl OF pokey_poly_5 IS - signal shift_reg: std_logic_vector(4 downto 0); - signal shift_next: std_logic_vector(4 downto 0); -BEGIN - -- register - process(clk,reset_n) - begin - if (reset_n = '0') then - shift_reg <= "01010"; - elsif (clk'event and clk='1') then - shift_reg <= shift_next; - end if; - end process; - - -- next state - process(shift_reg,enable,init) - begin - shift_next <= shift_reg; - if (enable = '1') then - shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1); - end if; - end process; - - -- output - bit_out <= shift_reg(0); - -END vhdl; diff --git a/common/Sound/Pokey MrX/synchronizer.vhdl b/common/Sound/Pokey MrX/synchronizer.vhdl deleted file mode 100644 index e84b5360..00000000 --- a/common/Sound/Pokey MrX/synchronizer.vhdl +++ /dev/null @@ -1,39 +0,0 @@ ---------------------------------------------------------------------------- --- (c) 2013 mark watson --- I am happy for anyone to use this for non-commercial use. --- If my vhdl files are used commercially or otherwise sold, --- please contact me for explicit permission at scrameta (gmail). --- This applies for source and binary form and derived works. ---------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -ENTITY synchronizer IS -PORT -( - CLK : IN STD_LOGIC; - RAW : IN STD_LOGIC; - SYNC : OUT STD_LOGIC -); -END synchronizer; - -ARCHITECTURE vhdl OF synchronizer IS - signal ff_next : std_logic_vector(2 downto 0); - signal ff_reg : std_logic_vector(2 downto 0); -begin - -- register - process(clk) - begin - if (clk'event and clk='1') then - ff_reg <= ff_next; - end if; - end process; - - ff_next <= RAW&ff_reg(2 downto 1); - - SYNC <= ff_reg(0); - -end vhdl; - - diff --git a/common/Sound/Pokey MrX/Pokey.qip b/common/Sound/Pokey/Pokey.qip similarity index 100% rename from common/Sound/Pokey MrX/Pokey.qip rename to common/Sound/Pokey/Pokey.qip diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/complete_address_decoder.vhdl b/common/Sound/Pokey/complete_address_decoder.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/complete_address_decoder.vhdl rename to common/Sound/Pokey/complete_address_decoder.vhdl diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/delay_line.vhdl b/common/Sound/Pokey/delay_line.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/delay_line.vhdl rename to common/Sound/Pokey/delay_line.vhdl diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/latch_delay_line.vhdl b/common/Sound/Pokey/latch_delay_line.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/latch_delay_line.vhdl rename to common/Sound/Pokey/latch_delay_line.vhdl diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/pokey.vhdl b/common/Sound/Pokey/pokey.vhdl similarity index 98% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/pokey.vhdl rename to common/Sound/Pokey/pokey.vhdl index 6628311d..fdbabfc6 100644 --- a/Arcade_MiST/Atari Tetris/rtl/Pokey/pokey.vhdl +++ b/common/Sound/Pokey/pokey.vhdl @@ -367,6 +367,7 @@ ARCHITECTURE vhdl OF pokey IS signal serout_enable : std_logic; signal serout_enable_delayed : std_logic; signal serin_enable : std_logic; + signal serin_enable_delayed : std_logic; signal async_serial_reset : std_logic; signal waiting_for_start_bit : std_logic; @@ -1000,6 +1001,10 @@ BEGIN serout_clock_delay : delay_line generic map (count=>2) port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed); + + serin_clock_delay : delay_line + generic map (count=>5) + port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serin_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serin_enable_delayed); process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset) @@ -1089,7 +1094,7 @@ BEGIN sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg; waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0'; - process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset) + process(serin_enable_delayed,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset) begin serin_clock_next <= serin_clock_reg; serin_clock_last_next <= serin_clock_reg; @@ -1105,7 +1110,7 @@ BEGIN async_serial_reset <= '0'; -- generate clock from enable signals - if (serin_enable = '1') then + if (serin_enable_delayed = '1') then serin_clock_next <= not(serin_clock_reg); end if; diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_countdown_timer.vhdl b/common/Sound/Pokey/pokey_countdown_timer.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_countdown_timer.vhdl rename to common/Sound/Pokey/pokey_countdown_timer.vhdl diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_keyboard_scanner.vhdl b/common/Sound/Pokey/pokey_keyboard_scanner.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_keyboard_scanner.vhdl rename to common/Sound/Pokey/pokey_keyboard_scanner.vhdl diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_noise_filter.vhdl b/common/Sound/Pokey/pokey_noise_filter.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_noise_filter.vhdl rename to common/Sound/Pokey/pokey_noise_filter.vhdl diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_poly_17_9.vhdl b/common/Sound/Pokey/pokey_poly_17_9.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_poly_17_9.vhdl rename to common/Sound/Pokey/pokey_poly_17_9.vhdl diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_poly_4.vhdl b/common/Sound/Pokey/pokey_poly_4.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_poly_4.vhdl rename to common/Sound/Pokey/pokey_poly_4.vhdl diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_poly_5.vhdl b/common/Sound/Pokey/pokey_poly_5.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/pokey_poly_5.vhdl rename to common/Sound/Pokey/pokey_poly_5.vhdl diff --git a/Arcade_MiST/Atari Tetris/rtl/Pokey/synchronizer.vhdl b/common/Sound/Pokey/synchronizer.vhdl similarity index 100% rename from Arcade_MiST/Atari Tetris/rtl/Pokey/synchronizer.vhdl rename to common/Sound/Pokey/synchronizer.vhdl diff --git a/common/Sound/Pokey MrX/syncreset_enable_divider.vhdl b/common/Sound/Pokey/syncreset_enable_divider.vhdl similarity index 100% rename from common/Sound/Pokey MrX/syncreset_enable_divider.vhdl rename to common/Sound/Pokey/syncreset_enable_divider.vhdl diff --git a/common/mist/arcade_inputs.v b/common/mist/arcade_inputs.v index 9c28c93f..8d0fdebf 100644 --- a/common/mist/arcade_inputs.v +++ b/common/mist/arcade_inputs.v @@ -112,10 +112,10 @@ always @(posedge clk) begin 'h06: btn_two_players <= key_pressed; // F2 'h04: btn_three_players <= key_pressed; // F3 'h0C: btn_four_players <= key_pressed; // F4 - 'h12: btn_fireD <= key_pressed; // l-shift - 'h14: btn_fireC <= key_pressed; // ctrl + 'h14: btn_fireA <= key_pressed; // ctrl 'h11: btn_fireB <= key_pressed; // alt - 'h29: btn_fireA <= key_pressed; // Space + 'h29: btn_fireC <= key_pressed; // Space + 'h12: btn_fireD <= key_pressed; // l-shift 'h1A: btn_fireE <= key_pressed; // Z 'h22: btn_fireF <= key_pressed; // X 'h21: btn_fireG <= key_pressed; // C