diff --git a/Arcade_MiST/Kiwako MrJong/MrJong.qsf b/Arcade_MiST/Kiwako MrJong/MrJong.qsf index 5e836a8d..16377111 100644 --- a/Arcade_MiST/Kiwako MrJong/MrJong.qsf +++ b/Arcade_MiST/Kiwako MrJong/MrJong.qsf @@ -43,25 +43,6 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrJong.sv -set_global_assignment -name VERILOG_FILE rtl/core.v -set_global_assignment -name VERILOG_FILE rtl/mcpu.v -set_global_assignment -name VERILOG_FILE rtl/clk_en.v -set_global_assignment -name VERILOG_FILE rtl/cpu_rom.v -set_global_assignment -name VERILOG_FILE rtl/cpu_ram.v -set_global_assignment -name VERILOG_FILE rtl/jg_decode.v -set_global_assignment -name VERILOG_FILE rtl/video.v -set_global_assignment -name VERILOG_FILE rtl/vdata.v -set_global_assignment -name VERILOG_FILE rtl/hvgen.v -set_global_assignment -name VERILOG_FILE rtl/audio.v -set_global_assignment -name VHDL_FILE rtl/sn76489_audio.vhd -set_global_assignment -name VERILOG_FILE rtl/rising_edge.v -set_global_assignment -name VERILOG_FILE rtl/falling_edge.v -set_global_assignment -name VERILOG_FILE rtl/ram.v -set_global_assignment -name VERILOG_FILE rtl/dpram.v -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/CPU/T80/T80.qip" -set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip" # Pin & Location Assignments # ========================== @@ -173,7 +154,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF # SignalTap II Assignments # ======================== set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/cpu.stp # Power Estimation Assignments # ============================ @@ -235,10 +216,29 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(MrJong) -# ------------------ \ No newline at end of file +# ------------------ +set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrJong.sv +set_global_assignment -name VERILOG_FILE rtl/core.v +set_global_assignment -name VERILOG_FILE rtl/mcpu.v +set_global_assignment -name VERILOG_FILE rtl/clk_en.v +set_global_assignment -name VERILOG_FILE rtl/cpu_rom.v +set_global_assignment -name VERILOG_FILE rtl/cpu_ram.v +set_global_assignment -name VERILOG_FILE rtl/jg_decode.v +set_global_assignment -name VERILOG_FILE rtl/video.v +set_global_assignment -name VERILOG_FILE rtl/vdata.v +set_global_assignment -name VERILOG_FILE rtl/hvgen.v +set_global_assignment -name VERILOG_FILE rtl/audio.v +set_global_assignment -name VHDL_FILE rtl/sn76489_audio.vhd +set_global_assignment -name VERILOG_FILE rtl/rising_edge.v +set_global_assignment -name VERILOG_FILE rtl/falling_edge.v +set_global_assignment -name VERILOG_FILE rtl/ram.v +set_global_assignment -name VERILOG_FILE rtl/dpram.v +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Kiwako MrJong/MrJong.sdc b/Arcade_MiST/Kiwako MrJong/MrJong.sdc new file mode 100644 index 00000000..5127b1f3 --- /dev/null +++ b/Arcade_MiST/Kiwako MrJong/MrJong.sdc @@ -0,0 +1,135 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +set aud_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]] +#set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_L}] +set_output_delay -clock [get_clocks $aud_clk] 1.000 [get_ports {AUDIO_R}] +set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}] +set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}] + +#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +#set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/Kiwako MrJong/Readme.md b/Arcade_MiST/Kiwako MrJong/Readme.md index 7b59b862..027ef17a 100644 --- a/Arcade_MiST/Kiwako MrJong/Readme.md +++ b/Arcade_MiST/Kiwako MrJong/Readme.md @@ -1,1716 +1,6 @@ +# Mr.Jong/CrazyBlocks/BlockBuster by Kiwako Co., Ltd. +## General description +Mr.Jong/CrazyBlocks/BlockBuster by Pierco (Pierre Cornier). - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Arcade-MrJong_MiSTer/Readme.md at master · pcornier/Arcade-MrJong_MiSTer · GitHub - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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- Mr.Jong/CrazyBlocks/BlockBuster by Kiwako Co., Ltd. - General description - Patreon Contributors!! -
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Mr.Jong/CrazyBlocks/BlockBuster by Kiwako Co., Ltd.

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General description

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Mr.Jong/CrazyBlocks/BlockBuster ported to MiSTerFPGA by Pierco (Pierre Cornier).

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Patreon Contributors!!

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- - - +Original core: https://github.com/pcornier/Arcade-MrJong_MiSTer diff --git a/Arcade_MiST/Kiwako MrJong/meta/BlockBuster.mra b/Arcade_MiST/Kiwako MrJong/meta/BlockBuster.mra index 08dd48fa..27265a8b 100644 --- a/Arcade_MiST/Kiwako MrJong/meta/BlockBuster.mra +++ b/Arcade_MiST/Kiwako MrJong/meta/BlockBuster.mra @@ -18,16 +18,16 @@ - - - - + + + + - - + + - - + + diff --git a/Arcade_MiST/Kiwako MrJong/meta/MrJong.mra b/Arcade_MiST/Kiwako MrJong/meta/MrJong.mra index e41efaf5..6f871245 100644 --- a/Arcade_MiST/Kiwako MrJong/meta/MrJong.mra +++ b/Arcade_MiST/Kiwako MrJong/meta/MrJong.mra @@ -18,16 +18,16 @@ - - - - + + + + - - + + - - + + diff --git a/Arcade_MiST/Kiwako MrJong/rtl/MrJong.sv b/Arcade_MiST/Kiwako MrJong/rtl/MrJong.sv index f4beda04..ccfa1b84 100644 --- a/Arcade_MiST/Kiwako MrJong/rtl/MrJong.sv +++ b/Arcade_MiST/Kiwako MrJong/rtl/MrJong.sv @@ -25,24 +25,27 @@ localparam CONF_STR = { "O34,Scanlines,Off,25%,50%,75%;", "O5,Blend,Off,On;", "O6,Joystick Swap,Off,On;", - "O7,Cabinet,Cocktail,Upright;", - "O8,Bonus Life,50k,30k;", - "O9,Difficulty,Normal,Hard;", - "OAB,Lives,6,4,5,3;", - "OCD,Coin,1c/1c,1c/2c,1c/3c,2c/1c;", + "O8,Cabinet,Cocktail,Upright;", + "O9,Flip,Off,On;", + "OA,Bonus Life,50k,30k;", + "OB,Difficulty,Normal,Hard;", + "OCD,Lives,6,4,5,3;", + "OEF,Coin,1c/1c,1c/2c,1c/3c,2c/1c;", "T0,Reset;", "V,v1.0.",`BUILD_DATE }; -wire [1:0] orientation = 2'b01; +wire flipped; +wire [1:0] orientation = {flipped, 1'b1}; wire rotate = status[2]; wire [1:0] scanlines = status[4:3]; wire blend = status[5]; wire joyswap = status[6]; -wire cabinet = status[7]; -wire bonus = status[8]; -wire difficulty = status[9]; -wire [1:0] lives = status[11:10]; -wire [1:0] coins = status[13:12]; +wire cabinet = status[8]; +wire flip = status[9]; +wire bonus = status[10]; +wire difficulty = status[11]; +wire [1:0] lives = status[13:12]; +wire [1:0] coins = status[15:14]; assign LED = ~ioctl_downl; assign AUDIO_R = AUDIO_L; @@ -98,15 +101,15 @@ always @(posedge clk_sys) begin reset <= status[0] | buttons[1] | ~rom_loaded; end -wire [7:0] dsw = {coins, lives, difficulty, bonus, 1'b0, cabinet}; -wire [7:0] p1 = { m_fireB, 1'b0, m_coin1, m_fireA, m_down, m_right, m_left, m_up }; -wire [7:0] p2 = { m_fire2B, m_two_players, m_one_player, m_fire2A, m_down2, m_right2, m_left2, m_up2 }; +wire [7:0] dsw = {coins, lives, difficulty, bonus, flip, cabinet}; +wire [7:0] p1 = { 1'b0, m_coin2, m_coin1, m_fireA, m_down, m_right, m_left, m_up }; +wire [7:0] p2 = { 1'b1, m_two_players, m_one_player, m_fire2A, m_down2, m_right2, m_left2, m_up2 }; core core( .reset(reset), .clk_sys(clk_sys), - .p1(p1), - .p2(p2), + .p1(p1), + .p2(p2), .dsw(dsw), .ioctl_index(ioctl_index), .ioctl_download(ioctl_downl), @@ -120,6 +123,7 @@ core core( .hb(hb), .vs(vs), .hs(hs), + .flipped(flipped), .sound_mix(audio) ); diff --git a/Arcade_MiST/Kiwako MrJong/rtl/core.v b/Arcade_MiST/Kiwako MrJong/rtl/core.v index 585a903d..ab4c95ef 100644 --- a/Arcade_MiST/Kiwako MrJong/rtl/core.v +++ b/Arcade_MiST/Kiwako MrJong/rtl/core.v @@ -22,6 +22,7 @@ module core( output vs, output hs, output ce_pix, + output flipped, output [15:0] sound_mix @@ -70,6 +71,8 @@ reg hflip; always @(posedge clk_sys) if (flip_wr) hflip <= cpu_dout[2]; +assign flipped = hflip; + wire [7:0] cpu_din = p1_cs ? p1 : p2_cs ? p2 : @@ -161,7 +164,7 @@ video u_video( .blue ( blue ), .vram_cs ( vram_cs ), .cram_cs ( cram_cs ), - .flip ( dsw[1] ^ hflip ) + .flip ( flipped ) ); vdata u_vdata( diff --git a/Arcade_MiST/Kiwako MrJong/rtl/cpu_ram.v b/Arcade_MiST/Kiwako MrJong/rtl/cpu_ram.v index 7d66c5ce..7c2182d1 100644 --- a/Arcade_MiST/Kiwako MrJong/rtl/cpu_ram.v +++ b/Arcade_MiST/Kiwako MrJong/rtl/cpu_ram.v @@ -13,19 +13,15 @@ module cpu_ram( ); wire [7:0] ram_din = cpu_dout; -wire ram1_ce_n = ~ram1_cs; -wire ram2_ce_n = ~ram2_cs; -wire ram1_wr_n = (ram1_ce_n | ~cpu_wr); -wire ram2_wr_n = (ram2_ce_n | ~cpu_wr); +wire ram1_wr_n = ~(ram1_cs & cpu_wr); +wire ram2_wr_n = ~(ram2_cs & cpu_wr); ram #(11,8) ram1( .clk ( clk_sys ), .addr ( cpu_ab[10:0] ), .din ( ram_din ), .q ( ram1_data ), - .rd_n ( ~cpu_rd ), - .wr_n ( ram1_wr_n ), - .ce_n ( ~ram1_cs ) + .wr_n ( ram1_wr_n ) ); ram #(11,8) ram2( @@ -33,9 +29,7 @@ ram #(11,8) ram2( .addr ( cpu_ab[10:0] ), .din ( ram_din ), .q ( ram2_data ), - .rd_n ( ~cpu_rd ), - .wr_n ( ram2_wr_n ), - .ce_n ( ~ram2_cs ) + .wr_n ( ram2_wr_n ) ); endmodule diff --git a/Arcade_MiST/Kiwako MrJong/rtl/cpu_rom.v b/Arcade_MiST/Kiwako MrJong/rtl/cpu_rom.v index 23e5b315..1c2b9b17 100644 --- a/Arcade_MiST/Kiwako MrJong/rtl/cpu_rom.v +++ b/Arcade_MiST/Kiwako MrJong/rtl/cpu_rom.v @@ -19,9 +19,7 @@ ram #(15,8) rom( .addr ( rom_addr ), .din ( ioctl_dout ), .q ( rom_data ), - .rd_n ( 1'b0 ), - .wr_n ( ~rom_wr ), - .ce_n ( 1'b0 ) + .wr_n ( ~rom_wr ) ); diff --git a/Arcade_MiST/Kiwako MrJong/rtl/hvgen.v b/Arcade_MiST/Kiwako MrJong/rtl/hvgen.v index 0778b302..6150467e 100644 --- a/Arcade_MiST/Kiwako MrJong/rtl/hvgen.v +++ b/Arcade_MiST/Kiwako MrJong/rtl/hvgen.v @@ -3,21 +3,20 @@ module hvgen( input clk_sys, output reg hb, vb, hs, vs, output reg [8:0] hcount, vcount, - output reg ce_pix + output ce_pix ); wire cen_6; clk_en #(7) hclk_en(clk_sys, cen_6); +assign ce_pix = cen_6; // 240x224 always @(posedge clk_sys) begin - ce_pix <= 1'b0; - if (cen_6) begin - ce_pix <= 1'b1; + if (ce_pix) begin hcount <= hcount + 9'd1; case (hcount) - 4: hb <= 1'b0; - 244: hb <= 1'b1; + 18: hb <= 1'b0; + 258: hb <= 1'b1; 308: hs <= 1'b0; 340: hs <= 1'b1; 383: begin diff --git a/Arcade_MiST/Kiwako MrJong/rtl/mcpu.v b/Arcade_MiST/Kiwako MrJong/rtl/mcpu.v index ee7b75d5..9fdc016b 100644 --- a/Arcade_MiST/Kiwako MrJong/rtl/mcpu.v +++ b/Arcade_MiST/Kiwako MrJong/rtl/mcpu.v @@ -31,15 +31,13 @@ clk_en #(17) cpu_clk_en(clk_sys, cen_26); reg old_vb; reg [7:0] hold_nmi; -reg [7:0] data_latch; always @(posedge clk_sys) begin old_vb <= vb; if (~old_vb & vb) hold_nmi <= 8'hff; if (hold_nmi != 8'd0) hold_nmi <= hold_nmi - 8'd1; - if (~cpu_rd_n) data_latch <= cpu_din; end -T80se ( +T80se cpu ( .RESET_n ( ~reset ), .CLK_n ( clk_sys ), .CLKEN ( cen_26 ), @@ -56,7 +54,7 @@ T80se ( .HALT_n ( ), .BUSAK_n ( ), .A ( cpu_ab ), - .DI ( data_latch ), + .DI ( cpu_din ), .DO ( cpu_dout ) ); diff --git a/Arcade_MiST/Kiwako MrJong/rtl/ram.v b/Arcade_MiST/Kiwako MrJong/rtl/ram.v index 75cc848f..f608b12b 100644 --- a/Arcade_MiST/Kiwako MrJong/rtl/ram.v +++ b/Arcade_MiST/Kiwako MrJong/rtl/ram.v @@ -9,19 +9,17 @@ module ram input [addr_width-1:0] addr, input [data_width-1:0] din, output [data_width-1:0] q, - input rd_n, - input wr_n, - input ce_n + input wr_n ); reg [data_width-1:0] data; reg [data_width-1:0] mem[(1<