From 18ab8d24dd18446c8660b5d460b89048a88604a2 Mon Sep 17 00:00:00 2001
From: Marcel <marceljenke@gmail.com>
Date: Sat, 19 Jun 2021 03:37:55 +0200
Subject: [PATCH] Add Sprint 4 Project Files WIP

---
 .../Sprint4_MiST/README.txt                   |   7 +
 .../Sprint4_MiST/clean.bat                    |  16 +
 .../Sprint4_MiST/rtl/EngineSound.vhd          | 165 ++++++
 .../Sprint4_MiST/rtl/Sprint4_MiST.sv          | 307 ++++++++++
 .../Sprint4_MiST/rtl/build_id.sv              |   2 +
 .../Sprint4_MiST/rtl/collision.vhd            |  73 +++
 .../Sprint4_MiST/rtl/colormix.vhd             |  53 ++
 .../Sprint4_MiST/rtl/cpu_mem.vhd              | 560 ++++++++++++++++++
 .../Sprint4_MiST/rtl/gearshift.vhd            |  89 +++
 .../Sprint4_MiST/rtl/inputs.vhd               | 191 ++++++
 .../Sprint4_MiST/rtl/joy2quad.sv              | 100 ++++
 .../Sprint4_MiST/rtl/motion.vhd               | 299 ++++++++++
 .../Sprint4_MiST/rtl/playfield.vhd            | 235 ++++++++
 .../Sprint4_MiST/rtl/pll.v                    | 365 ++++++++++++
 .../Sprint4_MiST/rtl/ram1k.vhd                | 184 ++++++
 .../Sprint4_MiST/rtl/rom/PROM_SYNC.vhd        |  54 ++
 .../Sprint4_MiST/rtl/rom/ROM_C1.vhd           | 150 +++++
 .../Sprint4_MiST/rtl/rom/ROM_E1.vhd           | 150 +++++
 .../Sprint4_MiST/rtl/rom/ROM_H5.vhd           | 150 +++++
 .../Sprint4_MiST/rtl/rom/ROM_K1_High.vhd      | 150 +++++
 .../Sprint4_MiST/rtl/rom/ROM_L6.vhd           |  86 +++
 .../Sprint4_MiST/rtl/rom/ROM_M6.vhd           |  86 +++
 .../Sprint4_MiST/rtl/rom/ROM_N1_Low.vhd       | 150 +++++
 .../Sprint4_MiST/rtl/rom/ROM_N6.vhd           |  86 +++
 .../Sprint4_MiST/rtl/screech.vhd              |  73 +++
 .../Sprint4_MiST/rtl/sound.vhd                | 332 +++++++++++
 .../Sprint4_MiST/rtl/sprint4.vhd              | 340 +++++++++++
 .../Sprint4_MiST/rtl/sync.vhd                 | 193 ++++++
 .../Sprint4_MiST/rtl/videomix.vhd             |   0
 .../Sprint4_MiST/sprint4.qpf                  |  30 +
 .../Sprint4_MiST/sprint4.qsf                  | 184 ++++++
 31 files changed, 4860 insertions(+)
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/README.txt
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/clean.bat
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/EngineSound.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/Sprint4_MiST.sv
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/build_id.sv
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/collision.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/colormix.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/cpu_mem.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/gearshift.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/inputs.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/joy2quad.sv
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/motion.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/playfield.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/pll.v
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/ram1k.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/PROM_SYNC.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_C1.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_E1.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_H5.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_K1_High.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_L6.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_M6.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_N1_Low.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_N6.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/screech.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sound.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sprint4.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sync.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/videomix.vhd
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/sprint4.qpf
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/sprint4.qsf

diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/README.txt b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/README.txt
new file mode 100644
index 00000000..8a53b75e
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/README.txt	
@@ -0,0 +1,7 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Sprint 4 from james10952001
+-- Port to MiST by Gehstock
+-- 19 June 2021
+-- 
+
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/clean.bat b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/clean.bat
new file mode 100644
index 00000000..ac9bf0a8
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/clean.bat	
@@ -0,0 +1,16 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s build_id.v
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/EngineSound.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/EngineSound.vhd
new file mode 100644
index 00000000..d02ecde3
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/EngineSound.vhd	
@@ -0,0 +1,165 @@
+-- Motor sound generator for Atari Sprint 4
+-- This was originally created for Sprint 2 - Identical circuit 
+-- Similar circuits are used in a number of other games
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 555 configured as an astable oscillator with the frequency controlled by
+-- a four bit binary value. The output of this oscillator drives a counter configured to produce an
+-- irregular thumping simulating the sound of an engine.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity EngineSound is 
+generic(
+			constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the overall engine sound frequency
+			);
+port(		
+			Clk_6			: in  std_logic; 
+			Reset			: in  std_logic;
+			Ena_3k		: in  std_logic;
+			EngineData	: in	std_logic_vector(3 downto 0);
+			Motor			: out std_logic_vector(5 downto 0)
+			);
+end EngineSound;
+
+architecture rtl of EngineSound is
+
+signal RPM_val 				: integer range 1 to 350;
+signal Ramp_term_unfilt		: integer range 1 to 80000;
+signal Ramp_Count 			: integer range 0 to 80000;
+signal Ramp_term				: integer range 1 to 80000;
+signal Freq_mod				: integer range 0 to 400;
+signal Motor_Clk				: std_logic;
+
+signal Counter_A				: std_logic;
+signal Counter_B 				: unsigned(2 downto 0);
+signal Counter_A_clk			: std_logic;
+
+signal Motor_prefilter 		: unsigned(1 downto 0);
+signal Motor_filter_t1 		: unsigned(3 downto 0);
+signal Motor_filter_t2 		: unsigned(3 downto 0);
+signal Motor_filter_t3 		: unsigned(3 downto 0);
+signal Motor_filtered		: unsigned(5 downto 0);
+
+
+begin
+
+-- The frequency of the oscillator is set by a 4 bit binary value controlled by the game CPU
+-- in the real hardware this is a 555 coupled to a 4 bit resistor DAC used to pull the frequency.
+-- The output of this DAC has a capacitor to smooth out the frequency variation.
+-- The constants assigned to RPM_val can be tweaked to adjust the frequency curve
+
+Speed_select: process(Clk_6)
+begin
+	if rising_edge(Clk_6) then
+		case EngineData is
+			when "0000" => RPM_val <= 280;
+			when "0001" => RPM_val <= 245;
+			when "0010" => RPM_val <= 230;
+			when "0011" => RPM_val <= 205;
+			when "0100" => RPM_val <= 190;
+			when "0101" => RPM_val <= 175;
+			when "0110" => RPM_val <= 160;
+			when "0111" => RPM_val <= 145;
+		   when "1000" => RPM_val <= 130;
+			when "1001" => RPM_val <= 115;
+			when "1010" => RPM_val <= 100;
+			when "1011" => RPM_val <= 85;
+			when "1100" => RPM_val <= 70;
+			when "1101" => RPM_val <= 55;
+			when "1110" => RPM_val <= 40;
+			when "1111" => RPM_val <= 25; 
+		end case;
+	end if;
+end process;
+
+
+-- There is a RC filter between the frequency control DAC and the 555 to smooth out the transitions between the
+-- 16 possible states. We can simulate a reasonable approximation of that behavior using a linear slope which is
+-- not truly accurate but should be close enough.
+RC_filt: process(clk_6, ena_3k, ramp_term_unfilt)
+begin
+	if rising_edge(clk_6) then
+		if ena_3k = '1' then
+			if ramp_term_unfilt > ramp_term then
+				ramp_term <= ramp_term + 10;
+			elsif ramp_term_unfilt = ramp_term then
+				ramp_term <= ramp_term;
+			else
+				ramp_term <= ramp_term - 8;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower
+-- the frequency. RPM_val is multiplied by a constant which can be adjusted by changing the value of freq_tune
+-- to simulate the function of the frequency adjustment pot in the original hardware.
+ramp_term_unfilt <= ((200 - freq_tune) * RPM_val);
+
+-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator
+Ramp_osc: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		motor_clk <= '1';
+		ramp_count <= ramp_count + 1;
+		if ramp_count > ramp_term then
+			ramp_count <= 0;
+			motor_clk <= '0';
+		end if;
+	end if;
+end process;
+		
+
+-- 7492 counter with XOR on two of the outputs creates lumpy engine sound from smooth pulse train
+-- 7492 has two sections, one div-by-2 and one div-by-6.
+Engine_counter: process(motor_clk, counter_A_clk, counter_B, reset)
+begin
+	if reset = '1' then
+		Counter_B <= (others => '0');
+	elsif rising_edge(motor_clk) then
+		Counter_B <= Counter_B + '1';
+	end if;
+	Counter_A_clk <= Counter_B(0) xor Counter_B(2);
+	if reset = '1' then		
+		Counter_A <= '0';
+	elsif rising_edge(counter_A_clk) then 
+		Counter_A <= (not Counter_A);
+	end if;
+end process;
+motor_prefilter <= ('0' & Counter_B(2)) + ('0' & Counter_B(1)) + ('0' & Counter_A);
+
+-- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Engine_filter: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		if (ena_3k = '1') then
+			motor_filter_t1 <= ("00" & motor_prefilter) + ("00" & motor_prefilter);
+			motor_filter_t2 <= motor_filter_t1;
+			motor_filter_t3 <= motor_filter_t2;
+		end if;
+		motor_filtered <= ("00" & motor_filter_t1) +
+								('0'  & motor_filter_t2 & '0') +
+								("00" & motor_filter_t3);
+	end if;
+end process;	
+
+motor <= std_logic_vector(motor_filtered);
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/Sprint4_MiST.sv b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/Sprint4_MiST.sv
new file mode 100644
index 00000000..9c064e9b
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/Sprint4_MiST.sv	
@@ -0,0 +1,307 @@
+//FPGA implementation of Sprint 4 arcade game released by Kee Games in 1978
+//james10952001
+module Sprint4_MiST(
+	output        LED,
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.sv" 
+
+localparam CONF_STR = {
+	"Sprint4;;",
+	"O1,Test Mode,Off,On;",
+	"T2,Next Track;",
+	"O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
+	"T0,Reset;",
+	"V,v1.00.",`BUILD_DATE
+};
+
+assign LED = 1'b1;
+wire clk_24, clk_12, locked;
+pll pll(
+	.inclk0(CLOCK_27),
+	.c0(clk_24),//24.192
+	.c1(clk_12),//12.096
+	.locked(locked)
+	);
+
+//	PORT_START("DIP")
+//	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Language ) ) PORT_DIPLOCATION("DIP:8,7")
+//	PORT_DIPSETTING(    0x00, DEF_STR( German ) )
+//	PORT_DIPSETTING(    0x01, DEF_STR( French ) )
+//	PORT_DIPSETTING(    0x02, DEF_STR( Spanish ) )
+//	PORT_DIPSETTING(    0x03, DEF_STR( English ) )
+//	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Coinage ) ) PORT_DIPLOCATION("DIP:6")
+//	PORT_DIPSETTING(    0x00, DEF_STR( 2C_1C ) )
+//	PORT_DIPSETTING(    0x04, DEF_STR( 1C_1C ) )
+//	PORT_DIPNAME( 0x08, 0x08, "Allow Late Entry" ) PORT_DIPLOCATION("DIP:5")
+//	PORT_DIPSETTING(    0x08, DEF_STR( No ) )
+//	PORT_DIPSETTING(    0x00, DEF_STR( Yes ) )
+//	PORT_DIPNAME( 0xf0, 0xb0, "Play Time" ) PORT_DIPLOCATION("DIP:4,3,2,1")
+//	PORT_DIPSETTING(    0x70, "60 seconds" )
+//	PORT_DIPSETTING(    0xb0, "90 seconds" )
+//	PORT_DIPSETTING(    0xd0, "120 seconds" )
+//	PORT_DIPSETTING(    0xe0, "150 seconds" )								
+//wire  [7:0] DIP_Sw = 8'b10000000;		
+		
+wire [63:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire [11:0] kbjoy;
+wire [31:0] joystick_0, joystick_1, joystick_2, joystick_3;
+wire        scandoublerD;
+wire        ypbpr;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [6:0]	audio_l, audio_r;
+wire	 		r, g, b;
+
+wire hs, vs, cs, hb, vb;
+wire blankn = ~(hb | vb);
+wire compositesync;//todo
+wire Steer_1A, Steer_1B, Steer_2A, Steer_2B, Steer_3A, Steer_3B, Steer_4A, Steer_4B;
+wire Gear1_1, Gear2_1, Gear3_1, Gear1_2, Gear2_2, Gear3_2, Gear1_3, Gear2_3, Gear3_3, Gear1_4, Gear2_4, Gear3_4;
+wire reset = (status[0] | buttons[1]);
+sprint4 sprint4(		
+	.Clk_50_I(),
+	.Clk_12(clk_12),
+	.Reset_I(~reset),
+	.Video1_O(),
+	.Video2_O(),
+	.Vsync(vs),
+	.Hsync(hs),
+	.Hblank(hb),
+	.Vblank(vb),
+	.VideoR_O(r),
+	.VideoG_O(g),
+	.VideoB_O(b),
+	.P1_2audio(audio_l),
+	.P3_4audio(audio_r),
+	.Coin1_I(~m_coin1),
+	.Coin2_I(~m_coin2),
+	.Coin3_I(~m_coin3),
+	.Coin4_I(~m_coin4),
+	.Start1_I(~m_one_player),
+	.Start2_I(~m_two_players),
+	.Start3_I(~m_three_players),
+	.Start4_I(~m_four_players),
+	.Gas1_I(~m_fireA),
+	.Gas2_I(~m_fire2A),
+	.Gas3_I(~m_fire3A),
+	.Gas4_I(~m_fire4A),
+	.Gear1_1_I(Gear1_1),
+	.Gear2_1_I(Gear2_1),
+	.Gear3_1_I(Gear3_1),	
+	.Gear1_2_I(Gear1_2),
+	.Gear2_2_I(Gear2_2),
+	.Gear3_2_I(Gear3_2),	
+	.Gear1_3_I(Gear1_3),
+	.Gear2_3_I(Gear2_3),
+	.Gear3_3_I(Gear3_3),
+	.Gear1_4_I(Gear1_4),
+	.Gear2_4_I(Gear2_4),
+	.Gear3_4_I(Gear3_4),
+	.Steer_1A_I(Steer_1A),
+	.Steer_1B_I(Steer_1B),
+	.Steer_2A_I(Steer_2A),	
+	.Steer_2B_I(Steer_2B),
+	.Steer_3A_I(Steer_3A),	
+	.Steer_3B_I(Steer_3B),
+	.Steer_4A_I(Steer_4A),	
+	.Steer_4B_I(Steer_4B),
+	.TrackSel_I(~status[2]),
+	.Test_I(~status[1]),
+	.StartLamp_O()
+	);
+	
+joy2quad steer1(
+	.CLK(clk_12),
+	.clkdiv(45000),	
+	.c_right(m_right),
+	.c_left(m_left),
+	.steerA(Steer_1A),
+	.steerB(Steer_1B)
+);	
+
+joy2quad steer2(
+	.CLK(clk_12),
+	.clkdiv(45000),	
+	.c_right(m_right2),
+	.c_left(m_left2),
+	.steerA(Steer_2A),
+	.steerB(Steer_2B)
+);	
+
+joy2quad steer3(
+	.CLK(clk_12),
+	.clkdiv(45000),	
+	.c_right(m_right3),
+	.c_left(m_left3),
+	.steerA(Steer_3A),
+	.steerB(Steer_3B)
+);	
+
+joy2quad steer4(
+	.CLK(clk_12),
+	.clkdiv(45000),	
+	.c_right(m_right4),
+	.c_left(m_left4),
+	.steerA(Steer_4A),
+	.steerB(Steer_4B)
+);	
+
+gearshift gear1(   
+	.Clk(clk_12),
+	.reset(reset),
+	.gearup(m_fireB),
+	.geardown(m_fireC),
+	.gearout(),
+	.gear1(Gear1_1),
+	.gear2(Gear2_1),
+	.gear3(Gear3_1)
+);
+
+gearshift gear2(   
+	.Clk(clk_12),
+	.reset(reset),
+	.gearup(m_fire2B),
+	.geardown(m_fire2C),
+	.gearout(),
+	.gear1(Gear1_2),
+	.gear2(Gear2_2),
+	.gear3(Gear3_2)
+);
+
+gearshift gear3(   
+	.Clk(clk_12),
+	.reset(reset),
+	.gearup(m_fire3B),
+	.geardown(m_fire3C),
+	.gearout(),
+	.gear1(Gear1_3),
+	.gear2(Gear2_3),
+	.gear3(Gear3_3)
+);
+
+gearshift gear4(   
+	.Clk(clk_12),
+	.reset(reset),
+	.gearup(m_fire4B),
+	.geardown(m_fire4C),
+	.gearout(),
+	.gear1(Gear1_4),
+	.gear2(Gear2_4),
+	.gear3(Gear3_4)
+);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        ( clk_24         	),
+	.conf_str       ( CONF_STR       	),
+	.SPI_CLK        ( SPI_SCK        	),
+	.SPI_SS_IO      ( CONF_DATA0     	),
+	.SPI_MISO       ( SPI_DO         	),
+	.SPI_MOSI       ( SPI_DI         	),
+	.buttons        ( buttons        	),
+	.switches       ( switches       	),
+	.scandoubler_disable (scandoublerD	),
+	.ypbpr          ( ypbpr          	),
+	.no_csync       ( no_csync       	),
+	.key_strobe     ( key_strobe     	),
+	.key_pressed    ( key_pressed    	),
+	.key_code       ( key_code       	),
+	.joystick_0     ( joystick_0     	),
+	.joystick_1     ( joystick_1     	),
+	.joystick_2     ( joystick_2     	),
+	.joystick_3     ( joystick_3     	),	
+	.status         ( status         	)
+	);
+	
+mist_video #(
+	.COLOR_DEPTH(1), 
+	.SD_HCNT_WIDTH(9)) 
+mist_video(
+	.clk_sys        ( clk_24           	),
+	.SPI_SCK        ( SPI_SCK          	),
+	.SPI_SS3        ( SPI_SS3          	),
+	.SPI_DI         ( SPI_DI           	),
+	.R					 ( blankn ? r : 0	),
+	.G					 ( blankn ? g : 0	),
+	.B					 ( blankn ? b : 0	),
+	.HSync          ( hs               	),
+	.VSync          ( vs               	),
+	.VGA_R          ( VGA_R           	),
+	.VGA_G          ( VGA_G            	),
+	.VGA_B          ( VGA_B            	),
+	.VGA_VS         ( VGA_VS           	),
+	.VGA_HS         ( VGA_HS           	),
+	.scanlines      ( status[4:3]      	),
+//	.rotate         ( { 1'b1, rotate } 	),
+//	.ce_divider     ( 1'b1             	),
+//	.blend          ( status[6]        	),
+	.scandoubler_disable(scandoublerD  	),
+	.no_csync       ( no_csync         	),
+	.ypbpr          ( ypbpr            	)
+	);
+
+dac #(
+	.C_bits(7))
+dac_l(
+	.clk_i(clk_24),
+	.res_n_i(1),
+	.dac_i(audio_l),
+	.dac_o(AUDIO_L)
+	);
+	
+dac #(
+	.C_bits(7))
+dac_r(
+	.clk_i(clk_24),
+	.res_n_i(1),
+	.dac_i(audio_r),
+	.dac_o(AUDIO_R)
+	);
+
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_up3, m_down3, m_left3, m_right3, m_fire3A, m_fire3B, m_fire3C, m_fire3D, m_fire3E, m_fire3F;
+wire m_up4, m_down4, m_left4, m_right4, m_fire4A, m_fire4B, m_fire4C, m_fire4D, m_fire4E, m_fire4F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+	.clk         ( clk_24      ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.joystick_2  ( joystick_2  ),
+	.joystick_3  ( joystick_3  ),	
+//	.rotate      ( rotate      ),
+//	.orientation ( 2'b11       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b0        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ),
+	.player3     ( {m_fire3F, m_fire3E, m_fire3D, m_fire3C, m_fire3B, m_fire3A, m_up3, m_down3, m_left3, m_right3} ),
+	.player4     ( {m_fire4F, m_fire4E, m_fire4D, m_fire4C, m_fire4B, m_fire4A, m_up4, m_down4, m_left4, m_right4} )
+);
+
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/build_id.sv b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/build_id.sv
new file mode 100644
index 00000000..1d53a3f2
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/build_id.sv	
@@ -0,0 +1,2 @@
+`define BUILD_DATE "171221"
+`define BUILD_TIME "172231"
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/collision.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/collision.vhd
new file mode 100644
index 00000000..5d911d00
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/collision.vhd	
@@ -0,0 +1,73 @@
+-- Collision detection logic for for Atari Sprint 4
+-- This works by comparing the video signals representing cars and playfield objects generating 
+-- collision signals when multiple objects appear at the same time (location) in the video.  
+--
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity collision_detect is 
+port(		
+			Clk6						: in	std_logic;
+			Car_n						: in  std_logic_vector(4 downto 1);
+			Playfield_n				: in  std_logic;
+			CollisionReset_n		: in  std_logic_vector(4 downto 1);
+			Collision_n				: buffer std_logic_vector(4 downto 1)
+			);
+end collision_detect;
+
+architecture rtl of collision_detect is
+
+begin
+	
+-- 74LS279 quad SR latch at L11, all inputs are active low
+H6: process(Clk6, Car_n, Playfield_n, CollisionReset_n, Collision_n)
+begin
+	if rising_edge(Clk6) then
+-- Units 1 and 3 each have an extra Set element but these are not used in this game
+-- Ordered from top to bottom as drawn in the schematic
+		if CollisionReset_n(1) = '0' then
+			Collision_n(1) <= '0';
+		elsif (Car_n(1) or Playfield_n) = '0' then 
+			Collision_n(1) <= '1';
+		else
+			Collision_n(1) <= Collision_n(1);
+		end if;
+		if CollisionReset_n(2) = '0' then
+			Collision_n(2) <= '0';
+		elsif (Car_n(2) or Playfield_n) = '0' then 
+			Collision_n(2) <= '1';
+		else
+			Collision_n(2) <= Collision_n(2);
+		end if;
+		if CollisionReset_n(4) = '0' then
+			Collision_n(4) <= '0';
+		elsif (Car_n(4) or Playfield_n) = '0' then 
+			Collision_n(4) <= '1';
+		else
+			Collision_n(4) <= Collision_n(4);
+		end if;
+		if CollisionReset_n(3) = '0' then
+			Collision_n(3) <= '0';
+		elsif (Car_n(3) or Playfield_n) = '0' then 
+			Collision_n(3) <= '1';
+		else
+			Collision_n(3) <= Collision_n(3);
+		end if;
+	end if;
+end process;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/colormix.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/colormix.vhd
new file mode 100644
index 00000000..766c34a1
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/colormix.vhd	
@@ -0,0 +1,53 @@
+-- Video color mixer for Atari Sprint 4 - Original monitor
+-- had 8 separate color inputs which we can mix to drive
+-- a more conventional RGB monitor.
+-- (c) 2018 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity colormix is 
+port(		
+			Clk6				: in  std_logic;
+			CompBlank		: in  std_logic;
+			WhiteVid			: in  std_logic;
+			PeachVid			: in  std_logic;
+			VioletVid		: in  std_logic;
+			GreenVid			: in  std_logic;
+			BlueVid			: in  std_logic;
+			video_r			: out std_logic;
+			video_g			: out std_logic;
+			video_b			: out std_logic
+			);
+end colormix;
+
+architecture rtl of colormix is
+
+
+begin
+
+
+-- Todo: Utilize blanking signal
+
+-- Todo: Consider synchronous process
+
+
+video_r <= (WhiteVid or PeachVid or VioletVid);
+video_g <= (WhiteVid or GreenVid);
+video_b <= (WhiteVid or VioletVid or BlueVid);
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/cpu_mem.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/cpu_mem.vhd
new file mode 100644
index 00000000..675c907d
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/cpu_mem.vhd	
@@ -0,0 +1,560 @@
+-- CPU, RAM, ROM and address decoder for Atari Sprint 4
+-- (c) 2018 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity CPU_mem is 
+port(		
+			CLK12					: in  std_logic;
+			CLK6					: in  std_logic; -- 6MHz on schematic
+			Reset_I				: in  std_logic;
+			Reset_n				: buffer	std_logic;
+			VCount				: in 	std_logic_vector(7 downto 0);
+			HCount				: in  std_logic_vector(8 downto 0);
+			Vblank_n_s			: in  std_logic; -- Vblank* on schematic
+			Test_n				: in  std_logic;
+			DB_in					: in 	std_logic_vector(7 downto 0); -- CPU data bus
+			DBus					: buffer std_logic_vector(7 downto 0);
+			DBuS_n				: buffer std_logic_vector(7 downto 0);
+			PRAM  				: buffer std_logic_vector(7 downto 0);
+			ABus					: out std_logic_vector(15 downto 0);
+			Attract				: buffer std_logic;
+			Attract_n			: out std_logic;
+			CollReset_n			: out std_logic_vector(4 downto 1);
+			Trac_Sel_Read_n	: buffer std_logic;		
+			AD_Read_n			: buffer std_logic;
+			Gas_Read_n			: buffer std_logic;
+			Coin_Read_n			: buffer std_logic;
+			Options_Read_n		: buffer std_logic;
+			Wr_DA_Latch_n		: out std_logic;
+			Wr_CrashWord_n		: out std_logic;
+			StartLamp			: out std_logic_vector(4 downto 1);
+			Skid					: out std_logic_vector(4 downto 1);
+			PHI1_O				: out std_logic;
+			PHI2_O				: out std_logic;
+			DMA					: buffer std_logic_vector(7 downto 0);
+			DMA_n				   : out	std_logic_vector(7 downto 0);
+			ADR : buffer std_logic_vector(15 downto 0)
+			);
+end CPU_mem;
+
+architecture rtl of CPU_mem is
+-- Clock signals
+signal cpu_clk				: std_logic;
+signal PHI1					: std_logic;
+signal PHI2					: std_logic;
+signal ena_count        : std_logic_vector(10 downto 0) := (others => '0');
+signal ena_750k			: std_logic;
+signal ena_3k				: std_logic;
+
+-- Watchdog timer signals
+signal WDog_Clear			: std_logic;
+signal WDog_count			: std_logic_vector(3 downto 0);
+
+-- Video scan signals
+signal H256					: std_logic;
+signal H256_n				: std_logic;
+signal H128					: std_logic;
+signal H64					: std_logic;
+signal H32					: std_logic;
+signal H16					: std_logic;
+signal H8					: std_logic;
+signal H4					: std_logic;
+signal H2					: std_logic;
+signal H1					: std_logic;
+signal V128					: std_logic;
+signal V64					: std_logic;
+signal V32					: std_logic;
+signal V16					: std_logic;
+signal V8					: std_logic;
+
+-- CPU signals
+signal NMI_n				: std_logic := '1';
+signal RW_n					: std_logic;
+signal RnW 					: std_logic;
+signal A						: std_logic_vector(15 downto 0);
+--signal ADR					: std_logic_vector(15 downto 0);
+signal cpuDin				: std_logic_vector(7 downto 0);
+signal cpuDout				: std_logic_vector(7 downto 0);
+
+-- Address decoder signals
+signal N10_in				: std_logic_vector(3 downto 0); -- := (others => '0');
+signal N10_out				: std_logic_vector(9 downto 0); -- := (others => '1');
+signal M10_out_A			: std_logic_vector(3 downto 0); -- := (others => '1');
+signal M10_out_B			: std_logic_vector(3 downto 0); -- := (others => '1');
+signal B2_in				: std_logic_vector(3 downto 0); -- := (others => '0');
+signal B2_out				: std_logic_vector(9 downto 0); -- := (others => '1');
+signal R10_Q				: std_logic := '0';
+signal D4_8					: std_logic := '1';
+
+-- Buses and chip enables
+signal cpuRAM_dout		: std_logic_vector(7 downto 0) := (others => '0');
+signal Vram_dout			: std_logic_vector(7 downto 0) := (others => '0');
+signal RAM_din				: std_logic_vector(7 downto 0) := (others => '0');
+signal RAM_addr			: std_logic_vector(9 downto 0) := (others => '0');
+signal Vram_addr			: std_logic_vector(9 downto 0) := (others => '0');
+signal RAM_dout			: std_logic_vector(7 downto 0) := (others => '0');
+signal RAM_we				: std_logic;
+signal RAM_n				: std_logic := '1'; 
+signal WRAM					: std_logic;
+signal WRITE_n				: std_logic := '1';
+signal ROM_mux_in			: std_logic_vector(2 downto 0) := (others => '0');
+signal ROM2_dout			: std_logic_vector(7 downto 0) := (others => '0');
+signal ROM3_dout			: std_logic_vector(7 downto 0) := (others => '0');
+signal ROM4_dout			: std_logic_vector(7 downto 0) := (others => '0');
+signal ROM_dout			: std_logic_vector(7 downto 0) := (others => '0');
+signal ROM1_n 				: std_logic;
+signal ROM2_n				: std_logic;
+signal ROM3_n				: std_logic;
+signal ROM4_n				: std_logic;
+signal ROMCE_n				: std_logic;
+signal Display_n			: std_logic;
+signal VBlank_Read_n		: std_logic;
+signal Timer_Reset_n		: std_logic;
+signal Inputs_n			: std_logic;
+signal Test					: std_logic;
+
+
+begin
+
+Test <= (not Test_n);
+
+H1 <= HCount(0);
+H2 <= HCount(1);
+H4 <= HCount(2);
+H8 <= HCount(3);
+H16 <= HCount(4);
+H32 <= HCount(5);
+H64 <= HCount(6);
+H128 <= HCount(7);
+H256 <= HCount(8);
+H256_n <= (not HCount(8));
+
+V8 <= VCount(3);
+V16 <= VCount(4);
+V32 <= VCount(5);
+V64 <= VCount(6);
+V128 <= VCount(7);
+
+
+-- In the original hardware the CPU is clocked directly by the 4H signal from the horizontal
+-- line counter. This attemps to do thins in a manner that is more proper for a synchronous
+-- FPGA design using the main 6MHz clock in conjunction with a 750kHz clock enable for the CPU.
+-- This also creates a 3kHz clock enable used by filters in the sound module.
+Clock_ena: process(Clk6) 
+begin
+	if rising_edge(Clk6) then
+		ena_count <= ena_count + "1";
+		ena_750k <= '0';
+		if (ena_count(2 downto 0) = "000") then
+			ena_750k <= '1'; -- 750 kHz
+		end if;
+		ena_3k <= '0';
+		if (ena_count(10 downto 0) = "00000000000") then
+			ena_3k <= '1';
+		end if;
+	end if;
+end process;
+
+
+-- Watchdog timer, counts pulses from V128 and resets CPU if not cleared by Timer_Reset_n
+Watchdog: process(V128, WDog_Clear, Reset_I)
+begin
+	if Reset_I = '0' then
+		WDog_count <= "1111";
+	elsif Wdog_Clear = '1' then
+		WDog_count <= "0000";
+	elsif rising_edge(V128) then
+		WDog_count <= WDog_count + 1;
+	end if;
+end process;
+WDog_Clear <= '1'; -- temporarily disable (Test_n nand Timer_Reset_n);
+Reset_n <= (not WDog_count(3));
+
+
+CPU: entity work.T65
+port map(
+		Enable => ena_750k,
+		Mode => "00",
+		Res_n => reset_n,
+		Clk => clk6,
+		Rdy => '1',
+		Abort_n => '1',
+		IRQ_n => '1',
+		NMI_n => NMI_n,
+		SO_n => '1',
+		R_W_n => RW_n,
+		A(15 downto 0) => A,
+		DI => cpuDin,
+		DO => cpuDout
+		);
+	
+DBus_n <= (not cpuDout); -- Data bus to video RAM is inverted
+DBus <= cpuDout;
+ABus <= ADR;
+ADR(15 downto 10) <= A(15 downto 10);
+ADR(9 downto 8) <= (A(9) or WRAM) & (A(8) or WRAM);
+ADR(7 downto 0) <= A(7 downto 0);
+RnW <= (not RW_n);
+
+NMI_n <= ((not V32) or Test);
+
+--Write_n <= (Phi2 and H2) nand RnW;
+
+-- DFF and logic used to generate the Write_n signal
+R10: process(H1, H2)
+begin
+	if rising_edge(H1) then
+		R10_Q <= (not H2);
+	end if;
+end process;
+Write_n <= (phi2 and R10_Q) nand RnW;
+
+
+-- CPU clock and phase 2 clock output
+Phi2 <= H4;
+Phi1 <= (not Phi2);
+Phi1_O <= Phi1;
+Phi2_O <= Phi2;
+
+	
+-- Program ROMs
+--C1: entity work.prog_rom2
+--port map(
+--		clock => clk6,
+--		address => ADR(10 downto 0),
+--		q => rom2_dout
+--		);
+
+C1: entity work.ROM_C1
+port map(
+	clk => clk6,
+	addr => ADR(10 downto 0),
+	data => rom2_dout
+);	
+
+--N1: entity work.prog_rom3l
+--port map(
+--		clock => clk6,
+--		address => ADR(10 downto 0),
+--		q => rom3_dout(3 downto 0)
+--		);
+
+N1: entity work.ROM_N1_Low
+port map(
+	clk => clk6,
+	addr => ADR(10 downto 0),
+	data => rom3_dout(3 downto 0)
+);	
+	
+--K1: entity work.prog_rom3h	
+--port map(
+--		clock => clk6,
+--		address => ADR(10 downto 0),
+--		q => rom3_dout(7 downto 4)
+--		);
+
+K1: entity work.ROM_K1_High
+port map(
+	clk => clk6,
+	addr => ADR(10 downto 0),
+	data => rom3_dout(7 downto 4)
+);	
+
+--E1: entity work.prog_rom4
+--port map(
+--		clock => clk6,
+--		address => ADR(10 downto 0),
+--		q => rom4_dout
+--		);
+
+E1: entity work.ROM_E1
+port map(
+	clk => clk6,
+	addr => ADR(10 downto 0),
+	data => rom4_dout
+); 
+-- ROM data mux
+ROM_mux_in <= (ROM4_n & ROM3_n & ROM2_n);
+ROM_mux: process(ROM_mux_in, rom2_dout, rom3_dout, rom4_dout)
+	begin
+	ROM_dout <= (others => '0');
+ case ROM_mux_in is
+	when "110" => rom_dout <= rom2_dout;
+	when "101" => rom_dout <= rom3_dout;
+	when "011" => rom_dout <= rom4_dout;
+	when others => null;
+ end case;
+end process;
+ROMCE_n <= (ROM2_n and ROM3_n and ROM4_n);
+
+
+	
+-- Video RAM 
+RAM: entity work.ram1k
+port map(
+	clock => clk6,
+	address => RAM_addr,
+	wren => RAM_we,
+	data => DBus_n,
+	q => RAM_dout
+	);
+
+	
+-- Altera block RAM has active high WE, original RAM had active low WE
+ram_we <= (not Write_n) and (not Display_n);
+
+Vram_addr <= (V128 or H256_n) & (V64 or H256_n) & (V32 or H256_n) & (V16 and H256) & (V8 and H256) & H128 & H64 & H32 & H16 & H8;
+
+
+VRAM_mux: process(clk6)
+begin	
+	if rising_edge(clk6) then
+		if phi2 = '0' then
+			RAM_addr <= Vram_addr; 
+		else
+			RAM_addr <= Adr(9 downto 0);
+		end if;
+	end if;
+end process;
+
+
+PRAM <= (not RAM_dout);
+
+
+-- Rising edge of phi2 clock latches inverted and non-inverted output of VRAM data bus into DMA and DMA_n complementary buses
+F5: process(phi2, PRAM)
+begin
+	if rising_edge(phi2) then
+			DMA <= PRAM;
+			DMA_n <= (not PRAM);
+	end if;
+end process;
+
+
+
+-- Address decoder
+B2_in <= '0' & Adr(13 downto 11); -- AND gate C4 is involved with Adr(15), used for test interface
+B2: process(B2_in)
+begin
+	case B2_in is
+      when "0000" =>
+         B2_out <= "1111111110";
+      when "0001" =>
+         B2_out <= "1111111101";
+      when "0010" =>
+         B2_out <= "1111111011";
+      when "0011" =>
+         B2_out <= "1111110111";
+      when "0100" =>
+         B2_out <= "1111101111";
+      when "0101" =>
+         B2_out <= "1111011111";
+      when "0110" =>
+         B2_out <= "1110111111";
+      when "0111" =>
+         B2_out <= "1101111111";
+      when "1000" =>
+         B2_out <= "1011111111";
+      when others =>
+         B2_out <= "1111111111";
+      end case;
+end process;
+VBlank_Read_n <= B2_out(2);
+Trac_Sel_Read_n <= B2_out(3);
+ROM1_n <= B2_out(4);
+ROM2_n <= B2_out(5);
+ROM3_n <= B2_out(6);
+ROM4_n <= B2_out(7);
+WRAM <= not ((not Adr(7)) or B2_out(0));
+Display_n <= (not WRAM) and B2_out(1);
+RAM_n <= (Display_n or RnW);
+
+
+D4_8 <= not ( (not B2_out(4)) and (not Adr(7)) and (Write_n nand (Phi2 nand RW_n)));
+
+N10_in <= D4_8 & RnW & Adr(6 downto 5);
+N10: process(N10_in)
+begin
+	case N10_in is
+		when "0000" =>
+         N10_out <= "1111111110";
+		when "0001" =>
+         N10_out <= "1111111101";
+      when "0010" =>
+         N10_out <= "1111111011";
+      when "0011" =>
+         N10_out <= "1111110111";
+      when "0100" =>
+         N10_out <= "1111101111";
+		when "0101" =>
+         N10_out <= "1111011111";
+		when "0110" =>
+         N10_out <= "1110111111";
+		when "0111" =>
+         N10_out <= "1101111111";
+      when "1000" =>
+         N10_out <= "1011111111";
+      when "1001" =>
+         N10_out <= "0111111111";
+      when others =>
+         N10_out <= "1111111111";
+      end case;
+end process;	
+AD_Read_n <= N10_out(0);
+Coin_Read_n <= N10_out(1);
+Gas_Read_n <= N10_out(2);
+Options_Read_n <= N10_out(3);
+
+-- Used for CPU data-in mux, asserts to read inputs 
+--Inputs_n <= B2_out(2) and B2_out(3) and N10_out(0) and N10_out(1) and N10_out(2) and N10_out(3);
+--Inputs_n <= B2_out(3) and N10_out(0) and N10_out(1) and N10_out(2) and N10_out(3) and B2_out(3);
+
+Inputs_n <= (AD_Read_n and Coin_Read_n and Gas_Read_n and options_Read_n and Trac_Sel_Read_n);
+
+-- DFF that creates the Attract and Attract_n signals
+R_10: process(N10_out, DBus_n, Attract)
+begin
+	if rising_edge(N10_out(4)) then 
+		Attract <= DBus_n(0);                  
+	end if;
+end process;
+Attract_n <= (not Attract);
+
+
+-- 9321 dual decoder at M10 creates collision reset, watchdog reset, explosion sound and input DA latch signals
+--M10: process(N10_out, Adr)
+--begin
+--	if N10_out(5) = '1' then
+--		M10_out_A <= "1111";
+--	else
+--		case Adr(2 downto 1) is
+--			when "00" => M10_out_A <= "1110";
+--			when "01" => M10_out_A <= "1101";
+--			when "10" => M10_out_A <= "1011";
+--			when "11" => M10_out_A <= "0111";
+--			when others => M10_out_A <= "1111";
+--		end case;
+--	end if;
+--	if N10_out(6) = '1' then
+--		M10_out_B <= "1111";
+--	else
+--		case Adr(2 downto 1) is
+--			when "00" => M10_out_B <= "1110";
+--			when "01" => M10_out_B <= "1101";
+--			when "10" => M10_out_B <= "1011";
+--			when "11" => M10_out_B <= "0111";
+--			when others => M10_out_B <= "1111";
+--		end case;
+--	end if;			
+--end process;
+--CollReset_n <= M10_out_A;
+--Timer_Reset_n <= M10_out_B(2);
+--Wr_CrashWord_n <= M10_out_B(1);
+--Wr_DA_Latch_n <= M10_out_B(0);
+
+
+-- 9321 dual decoder at M10 creates collision reset, watchdog reset, explosion sound and input DA latch signals
+M10: process(Clk6, Reset_n)
+begin
+--	if (Reset_n = '1') then	
+		if rising_edge(clk6) then
+			if (RW_n = '0' and ADR(13 downto 11) = "100" and ADR(7 downto 5) = "001") then
+			 	case Adr(2 downto 1) is
+					when "00" => CollReset_n <= "1110"; 
+					when "01" => CollReset_n <= "1101";
+					when "10" => CollReset_n <= "1011";
+					when "11" => CollReset_n <= "0111";
+					when others => CollReset_n <= "1111";
+				end case;
+			else
+				CollReset_n <= "1111";
+			end if;
+			if (Write_n = '0' and ADR(13 downto 11) = "100" and ADR(7 downto 5) = "010") then
+			 	case Adr(2 downto 1) is
+					when "00" => Wr_DA_Latch_n <= '0'; 
+					when "01" => Wr_CrashWord_n <= '0';
+					when "10" => Timer_Reset_n <= '0';
+					when others => null;
+				end case;
+			else
+				Timer_Reset_n <= '1';
+				Wr_CrashWord_n <= '1';
+				Wr_DA_Latch_n <= '1';
+			end if;
+		end if;
+--	end if;
+end process;
+
+-- E11 9334 addressable latch drives skid sound triggers and player start button LEDs
+--E11: process(clk6, N10_out, Adr)
+--begin
+--if rising_edge(clk6) then
+--	if (N10_out(7) = '0') then
+--	  case Adr(3 downto 1) is
+--		 when "000" => Skid(4) <= Adr(0);
+--		 when "001" => Skid(3) <= Adr(0);
+--		 when "010" => Skid(2) <= Adr(0);
+--		 when "011" => Skid(1) <= Adr(0);
+--		 when "100" => StartLamp(4) <= Adr(0);
+--		 when "101" => StartLamp(3) <= Adr(0);
+--		 when "110" => StartLamp(2) <= Adr(0);
+--		 when "111" => StartLamp(1) <= Adr(0);
+--		 when others => null;
+--	  end case;
+--	end if;
+-- end if;
+--end process;	
+
+
+-- E11 9334 addressable latch drives skid sound triggers and player start button LEDs
+E11: process(clk6, Reset_n)
+begin
+	if (Reset_n = '0') then
+		Skid <= "0000";
+		StartLamp <= "0000";
+	elsif rising_edge(clk6) then
+		-- Lazy way of implementing the address decoder is just look at the memory map 
+		if (Write_n = '0' and ADR(13 downto 11) = "100" and ADR(7 downto 5) = "011") then 
+			case A(3 downto 1) is
+				when "000" => Skid(4) <= Adr(0);
+				when "001" => Skid(3) <= Adr(0);
+				when "010" => Skid(2) <= Adr(0);
+				when "011" => Skid(1) <= Adr(0);
+				when "100" => StartLamp(4) <= Adr(0);
+				when "101" => StartLamp(3) <= Adr(0);
+				when "110" => StartLamp(2) <= Adr(0);
+				when "111" => StartLamp(1) <= Adr(0);
+				when others => null;
+			end case;
+		end if;
+ end if;
+end process;	
+
+
+-- CPU Din mux, no tristate logic in modern FPGAs so this mux is used to select the source to the CPU data-in bus
+cpuDin <=  	
+				PRAM when (RAM_n = '0') and (Display_n = '0') else 				-- Video RAM
+				ROM_dout when ROMCE_n = '0' else 										-- Program ROM
+				VBlank_n_s & Test_n & "111111" when Vblank_Read_n = '0' else 	-- VBlank and Self Test switch
+				DB_in when Inputs_n = '0' else 											-- Inputs
+				x"FF";
+end rtl;
+
+
+
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/gearshift.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/gearshift.vhd
new file mode 100644
index 00000000..9cbf72f3
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/gearshift.vhd	
@@ -0,0 +1,89 @@
+-- Gear Shift
+-- (c) 2019 alanswx
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity gearshift is 
+port(   
+			Clk				: in	std_logic;
+			reset				: in	std_logic;
+			gearup			: in	std_logic;
+			geardown			: in	std_logic;
+			gearout			: out std_logic_vector(2 downto 0);
+			gear1				: out std_logic;
+			gear2				: out std_logic;
+			gear3				: out std_logic
+			
+			);
+end gearshift;
+
+architecture rtl of gearshift is
+
+signal gear : std_logic_vector(2 downto 0):= (others =>'0');
+signal old_gear_up : std_logic:='0';
+signal old_gear_down : std_logic:='0';
+
+
+begin
+
+gearout<=gear;
+
+process (clk, gear)
+begin
+
+  if rising_edge(clk) then
+
+
+  if (reset='1') then
+		gear<="000";
+  elsif (gearup='1') then
+   if (old_gear_up='0') then
+		old_gear_up<='1';
+		if (gear < 3) then
+			gear<= gear +1;
+		end if;
+	end if;
+  elsif (geardown='1') then
+   if (old_gear_down='0') then
+	   old_gear_down<='1';
+		if (gear>0) then
+			gear<=gear-1;
+		end if;
+	end if;
+  else
+    old_gear_up<='0';
+	 old_gear_down<='0';
+  end if;
+
+  end if;
+
+   case gear is
+        when "000" => gear1 <=  '0' ;
+        when "001" => gear1 <=  '1' ;
+        when "010" => gear1 <=  '1' ;
+        when "011" => gear1 <=  '1' ;
+        when others => gear1 <= '1' ;
+    end case;
+   case gear is
+        when "000" => gear2 <=  '1' ;
+        when "001" => gear2 <=  '0' ;
+        when "010" => gear2 <=  '1' ;
+        when "011" => gear2 <=  '1' ;
+        when others => gear2 <= '1' ;
+    end case;
+   case gear is
+        when "000" => gear3 <=  '1' ;
+        when "001" => gear3 <=  '1' ;
+        when "010" => gear3 <=  '0' ;
+        when "011" => gear3 <=  '1' ;
+        when others => gear3 <= '1' ;
+    end case;
+	
+end process;
+
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/inputs.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/inputs.vhd
new file mode 100644
index 00000000..b3d22831
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/inputs.vhd	
@@ -0,0 +1,191 @@
+-- Input module for Kee Games Ultra Tank
+-- 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity control_inputs is 
+port(		
+			Clk6					: in	std_logic;
+			DipSw					: in  std_logic_vector(7 downto 0);
+			Trac_Sel_n			: in  std_logic;
+			Coin1					: in 	std_logic;
+			Coin2					: in	std_logic;
+			Coin3					: in 	std_logic;
+			Coin4					: in	std_logic;			
+			Start1_n				: in	std_logic;
+			Start2_n				: in	std_logic;
+			Start3_n				: in	std_logic;
+			Start4_n				: in	std_logic;	
+			Gas1_n				: in  std_logic; -- Gas pedals, these are simple on/off switches
+			Gas2_n				: in  std_logic;		
+			Gas3_n				: in  std_logic;	
+			Gas4_n				: in  std_logic;				
+			Gear1_1_n			: in  std_logic; -- Gear select levers
+			Gear2_1_n			: in  std_logic;	
+			Gear3_1_n			: in  std_logic;			
+			Gear1_2_n			: in  std_logic;
+			Gear2_2_n			: in  std_logic;
+			Gear3_2_n			: in  std_logic;
+			Gear1_3_n			: in  std_logic;
+			Gear2_3_n			: in  std_logic;
+			Gear3_3_n			: in  std_logic;
+			Gear1_4_n			: in  std_logic;
+			Gear2_4_n			: in  std_logic;
+			Gear3_4_n			: in  std_logic;
+			Steering1A_n		: in  std_logic; -- Steering wheel signals
+			Steering1B_n		: in  std_logic;
+			Steering2A_n		: in  std_logic;
+			Steering2B_n		: in  std_logic;
+			Steering3A_n		: in  std_logic;
+			Steering3B_n		: in  std_logic;
+			Steering4A_n		: in  std_logic;
+			Steering4B_n		: in  std_logic;
+			Collision_n			: in	std_logic_vector(4 downto 1); -- Collision detection signals
+			Gas_Read_n			: in	std_logic;
+			AD_Read_n			: in  std_logic;
+			Coin_Read_n			: in	std_logic;
+			Options_Read_n		: in	std_logic;
+			Trac_Sel_Read_n	: in  std_logic;
+			Wr_DA_Latch_n		: in  std_logic;
+			
+			da_latch				: out std_logic_vector(3 downto 0);
+			
+			
+			Adr					: in  std_logic_vector(2 downto 0);
+			DBus					: in  std_logic_vector(3 downto 0);
+			Dout					: out std_logic_vector(7 downto 0)
+			);
+end control_inputs;
+
+architecture rtl of control_inputs is
+
+
+signal Coin					: std_logic := '1';
+
+signal Options				: std_logic_vector(1 downto 0) := "11";
+signal AD_Sel				: std_logic := '1';
+--signal DA_latch			: std_logic_vector(3 downto 0) := (others => '0');
+signal Gas_Collis_n		: std_logic;
+signal Steer1				: std_logic;
+signal Steer2				: std_logic;
+signal Steer3				: std_logic;
+signal Steer4				: std_logic;
+signal Shift1				: std_logic;
+signal Shift2				: std_logic;
+signal Shift3				: std_logic;
+signal Shift4				: std_logic;
+
+begin
+
+-- Steering and gear shifts use a clever analog multiplexing in the real hardware in order to reduce the pins required
+-- in the wiring harness to the board. For an FPGA this would require additional hardware and complexity 
+-- so this has been re-worked to provide individual active-low inputs
+
+--- E6 is a quad synchronous latch driving a 4 bit resistor DAC
+E6: process(Clk6, Wr_DA_Latch_n, DBus)
+begin	
+	if falling_edge(Wr_DA_Latch_n) then
+		DA_latch <= (not DBus);
+	end if;
+end process;
+
+-- Each steering and gear shift input goes to a comparator that compares it with a reference voltage coming 
+-- from the DAC Here we dispense with the DAC and use separate inputs for each of the two outputs from each 
+-- steering wheel and three from each gear shifter
+
+--Steer1 <= JoyW_Fw and (JoyW_Bk or DA_latch(0));
+--Shift1 <= JoyW_Fw and (JoyW_Bk or DA_latch(0));
+--Steer2 <= JoyY_Fw and (JoyY_Bk or DA_latch(0));
+--Shift2 <= JoyW_Fw and (JoyW_Bk or DA_latch(0));
+--Steer3 <= JoyX_Fw and (JoyX_Bk or DA_latch(1));
+--Shift3 <= JoyW_Fw and (JoyW_Bk or DA_latch(0));
+--Steer4 <= JoyZ_Fw and (JoyZ_Bk or DA_latch(1));
+--Shift4 <= JoyZ_Fw and (JoyZ_Bk or DA_latch(1));
+
+-- 9312 Data Selector/Multiplexer at K11
+-- Reads steering and gear shift inputs
+K11: process(Adr, Steer1, Steer2, Steer3, Steer4, Shift1, Shift2, Shift3, Shift4)
+begin
+	case Adr(2 downto 0) is
+		when "000" => AD_Sel <= Steer1;
+		when "001" => AD_Sel <= Shift1;
+		when "010" => AD_Sel <= Steer2;
+		when "011" => AD_Sel <= Shift2;
+		when "100" => AD_Sel <= Steer3;
+		when "101" => AD_Sel <= Shift3;
+		when "110" => AD_Sel <= Steer4;
+		when "111" => AD_Sel <= Shift4;
+		when others => AD_Sel <= '0';
+	end case;
+end process;
+
+-- 9312 Data Selector/Multiplexer at F10
+-- Reads coin switches and player start buttons
+F10: process(Adr, Coin1, Coin2, Coin3, Coin4, Start1_n, Start2_n, Start3_n, Start4_n)
+begin
+	case Adr(2 downto 0) is
+		when "000" => Coin <= (not Coin1);
+		when "001" => Coin <= Start1_n;
+		when "010" => Coin <= (not Coin2);
+		when "011" => Coin <= Start2_n;
+		when "100" => Coin <= (not Coin3);
+		when "101" => Coin <= Start3_n;
+		when "110" => Coin <= (not Coin4);
+		when "111" => Coin <= Start4_n;
+		when others => Coin <= '0';
+	end case;
+end process;
+
+
+-- Configuration DIP switches
+N9: process(Adr(1 downto 0), DipSw)
+begin
+	case Adr(1 downto 0) is
+		when "00" => Options <= DipSw(0) & DipSw(1);
+		when "01" => Options <= DipSw(2) & DipSw(3);
+		when "10" => Options <= DipSw(4) & DipSw(5);
+		when "11" => Options <= DipSw(6) & DipSw(7);
+		when others => Options <= "11";
+		end case;
+end process;
+
+
+-- 9312 Data Selector/Multiplexer at L12
+-- Reads collision detection signals and gas pedals
+L12: process(Adr, Gas1_n, Gas2_n, Gas3_n, Gas4_n, Collision_n)
+begin
+	case Adr(2 downto 0) is
+		when "000" => Gas_Collis_n <= Gas1_n;
+		when "001" => Gas_Collis_n <= Collision_n(1);
+		when "010" => Gas_Collis_n <= Gas2_n;
+		when "011" => Gas_Collis_n <= Collision_n(2);
+		when "100" => Gas_Collis_n <= Gas3_n;
+		when "101" => Gas_Collis_n <= Collision_n(3);
+		when "110" => Gas_Collis_n <= Gas4_n;
+		when "111" => Gas_Collis_n <= Collision_n(4);
+		when others => Gas_Collis_n <= '1';
+	end case;
+end process;	
+
+-- Inputs data mux
+Dout <=  	AD_Sel & "1111111" when AD_Read_n = '0' else
+				Coin & "1111111" when Coin_Read_n = '0' else 
+				Trac_Sel_n & "1111111" when Trac_Sel_Read_n = '0' else
+				"111111" & Options when Options_Read_n = '0' else
+				Gas_Collis_n & "1111111" when Gas_Read_n = '0' else
+				x"FF";
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/joy2quad.sv b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/joy2quad.sv
new file mode 100644
index 00000000..d2eaeabb
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/joy2quad.sv	
@@ -0,0 +1,100 @@
+//============================================================================
+//  joy2quad
+//
+//  Take in digital joystick buttons, and try to estimate a quadrature encoder
+//
+// 
+//  This makes an offset wave pattern for each keyboard stroke.  It might
+//  be a good extension to change the size of the wave based on how long the joystick
+//  is held down. 
+//
+//  Copyright (c) 2019 Alan Steremberg - alanswx
+//
+//   
+//============================================================================
+// digital joystick button to quadrature encoder
+
+module joy2quad
+(
+	input CLK,
+	input [31:0] clkdiv,
+	
+	input c_right,
+	input c_left,
+	output reg steerA,
+	output reg steerB
+);
+
+
+reg [3:0] state = 0;
+
+always @(posedge CLK) begin
+ reg [31:0] count = 0;
+ if (count >0)
+  begin 
+	count=count-1;
+ end
+ else
+ begin
+ count=clkdiv;
+ casex(state)
+	4'b0000: 
+	  begin
+	    {steerB,steerA} =2'b00;
+		 if (c_left==1)
+		 begin
+			state=4'b0001;
+		 end
+		 if (c_right==1)
+		 begin
+			state=4'b0101;
+		 end
+
+		 end
+	4'b0001: 
+	  begin
+	    {steerB,steerA}=2'b00;
+		 state=4'b0010;
+	  end
+	4'b0010: 
+	  begin
+	    {steerB,steerA}=2'b01;
+		 state=3'b0011;
+	  end
+	4'b0011: 
+	  begin
+	    {steerB,steerA}=2'b11;
+		 state=4'b0100;
+	  end
+	4'b0100: 
+	  begin
+	    {steerB,steerA}=2'b10;
+		 state=4'b000;
+	  end
+	4'b0101: 
+	  begin
+	    {steerB,steerA}=2'b00;
+		 state=4'b0110;
+	  end
+	4'b0110: 
+	  begin
+	    {steerB,steerA}=2'b10;
+		 state=4'b0111;
+	  end
+	4'b0111: 
+	  begin
+	    {steerB,steerA}=2'b11;
+		 state=4'b1000;
+	  end
+	4'b1000: 
+	  begin
+	    {steerB,steerA}=2'b01;
+		 state=4'b0000;
+		 
+	  end
+
+ endcase
+ end
+end
+
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/motion.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/motion.vhd
new file mode 100644
index 00000000..8f9f385b
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/motion.vhd	
@@ -0,0 +1,299 @@
+-- Motion Car generation circuitry for Atari Sprint 4
+-- This generates the four cars, the only motion objects in the game
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity motion is 
+port(		
+			CLK6			: in  std_logic; -- 6MHz* on schematic
+			PHI2			: in  std_logic;
+			DMA_n			: in  std_logic_vector(7 downto 0);
+			PRAM			: in  std_logic_vector(7 downto 0);
+			H256_s		: in  std_logic; -- 256H* on schematic
+			VCount		: in  std_logic_vector(7 downto 0);
+			HCount		: in  std_logic_vector(8 downto 0);
+			Load_n		: buffer std_logic_vector(8 downto 1);
+			Car			: out std_logic_vector(4 downto 1);
+			Car_n			: out std_logic_vector(4 downto 1)
+			);
+end motion;
+
+architecture rtl of motion is
+
+signal phi1			: std_logic;
+
+signal H256_n			: std_logic;
+signal H64 				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+
+signal P6_R5sum		: std_logic_vector(7 downto 0);
+signal Match_n			: std_logic := '1';
+signal R6_8				: std_logic := '1';
+
+signal P7_in			: std_logic_vector(3 downto 0) := (others => '0');
+signal P7_out			: std_logic_vector(9 downto 0) := (others => '1');
+signal R4_in			: std_logic_vector(3 downto 0) := (others => '0');
+signal R4_out			: std_logic_vector(9 downto 0) := (others => '1');
+
+signal Car1_Hpos	: std_logic_vector(7 downto 0) := (others => '0');
+signal Car2_Hpos	: std_logic_vector(7 downto 0) := (others => '0');
+signal Car3_Hpos	: std_logic_vector(7 downto 0) := (others => '0');
+signal Car4_Hpos	: std_logic_vector(7 downto 0) := (others => '0');
+
+signal Car1_reg	: std_logic_vector(15 downto 0) := (others => '0');
+signal Car2_reg	: std_logic_vector(15 downto 0) := (others => '0');
+signal Car3_reg 	: std_logic_vector(15 downto 0) := (others => '0');
+signal Car4_reg 	: std_logic_vector(15 downto 0) := (others => '0');
+
+signal Car1_Inh	: std_logic := '1';
+signal Car2_Inh	: std_logic := '1';
+signal Car3_Inh	: std_logic := '1';
+signal Car4_Inh	: std_logic := '1';
+
+signal Vid			: std_logic_vector(12 downto 1) := (others => '0');
+
+
+begin
+phi1 <= (not phi2);
+
+H8 <= Hcount(3);
+H16 <= Hcount(4);
+H32 <= Hcount(5);
+H64 <= Hcount(6);
+H256_n <= not(Hcount(8));
+
+-- Vertical line comparator
+P6_R5sum <= DMA_n + VCount; 
+
+-- Motion Object PROMs
+--N6: entity work.n6_prom
+--port map(
+--	clock => clk6,
+--	address => H16 & PRAM(7 downto 3) & P6_R5sum(3 downto 0),
+--	q => Vid(4 downto 1)
+--	);
+	
+N6: entity work.ROM_N6
+port map(
+	clk => clk6,
+	addr => H16 & PRAM(7 downto 3) & P6_R5sum(3 downto 0),
+	data => Vid(4 downto 1)
+);	
+
+--M6: entity work.m6_prom
+--port map(
+--	clock => clk6,
+--   address => H16 & PRAM(7 downto 3) & P6_R5sum(3 downto 0),
+--	q => Vid(8 downto 5)
+--	);
+	
+M6: entity work.ROM_M6
+port map(
+	clk => clk6,
+	addr => H16 & PRAM(7 downto 3) & P6_R5sum(3 downto 0),
+	data => Vid(8 downto 5)
+);		
+
+--L6: entity work.l6_prom
+--port map(
+--	clock => clk6,
+--	address => H16 & PRAM(7 downto 3) & P6_R5sum(3 downto 0),
+--	q => Vid(12 downto 9)
+--	);
+
+L6: entity work.ROM_L6
+port map(
+	clk => clk6,
+	addr => H16 & PRAM(7 downto 3) & P6_R5sum(3 downto 0),
+	data => Vid(12 downto 9)
+);		
+	
+-- Some glue logic
+Match_n <= not(P6_R5sum(7) and P6_R5sum(6) and P6_R5sum(5) and P6_R5sum(4));
+R6_8 <= not(H256_n and H8 and Phi1 and (H64 nand Match_n));
+
+
+R4_in <= R6_8 & H64 & H32 & H16;
+R4: process(clk6, R4_in)
+begin
+	case R4_in is
+		when "0000" =>
+			R4_out <= "1111111110";
+		when "0001" =>
+			R4_out <= "1111111101"; 
+		when "0010" =>
+			R4_out <= "1111111011"; 
+		when "0011" =>
+			R4_out <= "1111110111";
+		when "0100" =>
+			R4_out <= "1111101111"; 
+		when "0101" =>
+			R4_out <= "1111011111";
+		when "0110" =>
+			R4_out <= "1110111111"; 
+		when "0111" =>
+			R4_out <= "1101111111";
+		when others =>
+			R4_out <= "1111111111";
+		end case;
+end process;
+Load_n(8) <= R4_out(7);
+Load_n(7) <= R4_out(6);
+Load_n(6) <= R4_out(5);
+Load_n(5) <= R4_out(4);
+Load_n(4) <= R4_out(3);
+Load_n(3) <= R4_out(2);
+Load_n(2) <= R4_out(1);
+Load_n(1) <= R4_out(0);
+
+
+-- Car 1 Horizontal position counter
+-- This combines two 74163s at locations P5 and P6 on the PCB 
+P5_4: process(clk6, H256_s, Load_n, DMA_n)
+begin
+	if rising_edge(clk6) then
+		if Load_n(1) = '0' then -- preload the counter
+			Car1_Hpos <= DMA_n;
+		elsif H256_s = '1' then -- increment the counter
+			Car1_Hpos <= Car1_Hpos + '1';		
+		end if;
+		if Car1_Hpos(7 downto 4) = "1111" then
+			Car1_Inh <= '0';
+		else
+			Car1_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 1 video shift register
+-- This combines two 74165s at locations N7 and N8 on the PCB
+N7_8: process(clk6, Car1_Inh, Load_n, Vid)
+begin
+	if Load_n(5) = '0' then
+			Car1_reg <= "000" & Vid & '0'; -- Preload the register
+	elsif rising_edge(clk6) then
+		if Car1_Inh = '0' then
+			Car1_reg <= '0' & Car1_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car(1) <= Car1_reg(0);
+Car_n(1) <= (not Car1_reg(0));
+
+
+-- Car 2 Horizontal position counter
+-- This combines two 74LS163s at locations P5 and P6 on the PCB 
+P5_6: process(clk6, H256_s, Load_n, DMA_n)
+begin
+	if rising_edge(clk6) then
+		if Load_n(2) = '0' then -- preload the counter
+			Car2_Hpos <= DMA_n;
+		elsif H256_s = '1' then -- increment the counter
+			Car2_Hpos <= Car2_Hpos + '1';
+		end if;
+		if Car2_Hpos(7 downto 4) = "1111" then
+			Car2_Inh <= '0';
+		else
+			Car2_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 2 video shift register
+M7_8: process(clk6, Load_n, Vid)
+begin
+	if Load_n(6) = '0' then
+			Car2_reg <= "000" & Vid & '0'; -- Preload the register
+	elsif rising_edge(clk6) then
+		if Car2_Inh = '0' then
+			Car2_reg <= '0' & Car2_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car(2) <= Car2_reg(0);
+Car_n(2) <= (not Car2_reg(0));
+
+
+-- Car 3 Horizontal position counter
+-- This combines two 74LS163s at locations M5 and M4 on the PCB 
+M5_4: process(clk6, H256_s, Load_n, DMA_n)
+begin
+	if rising_edge(clk6) then
+		if Load_n(3) = '0' then -- preload the counter
+			Car3_Hpos <= DMA_n;
+		elsif H256_s = '1' then -- increment the counter
+			Car3_Hpos <= Car3_Hpos + '1';
+		end if;
+		if Car3_Hpos(7 downto 4) = "1111" then
+			Car3_Inh <= '0';
+		else
+			Car3_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 3 video shift register
+L7_8: process(clk6, Car3_Inh, Load_n, Vid)
+begin
+	if Load_n(7) = '0' then
+			Car3_reg <= "000" & Vid & '0'; -- Preload the register
+	elsif rising_edge(clk6) then
+		if Car3_Inh = '0' then
+			Car3_reg <= '0' & Car3_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car(3) <= Car3_reg(0);
+Car_n(3) <= (not Car3_reg(0));
+
+
+-- Car 4 Horizontal position counter
+-- This combines two 74LS163s at locations L5 and L4on the PCB 
+L5_4: process(clk6, H256_s, Load_n, DMA_n)
+begin
+	if rising_edge(clk6) then
+		if Load_n(4) = '0' then -- preload the counter
+			Car4_Hpos <= DMA_n;
+		elsif H256_s = '1' then -- increment the counter
+			Car4_Hpos <= Car4_Hpos + '1';
+		end if;
+		if Car4_Hpos(7 downto 4) = "1111" then
+			Car4_Inh <= '0';
+		else
+			Car4_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 4 video shift register
+K7_8: process(clk6, Car4_Inh, Load_n, Vid)
+begin
+	if Load_n(8) = '0' then
+			Car4_reg <= "000" & Vid & '0'; -- Preload the register
+	elsif rising_edge(clk6) then
+		if Car4_Inh = '0' then
+			Car4_reg <= '0' & Car4_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car(4) <= Car4_reg(0);
+Car_n(4) <= (not Car4_reg(0));
+
+end rtl;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/playfield.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/playfield.vhd
new file mode 100644
index 00000000..2db5d97f
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/playfield.vhd	
@@ -0,0 +1,235 @@
+-- Playfield generation and video mixing circuitry for Atari Sprint 4
+-- (c) 2018 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity playfield is 
+port(		
+			Clk6				: in	std_logic;
+			DMA				: in	std_logic_vector(7 downto 0);
+			PRAM				: in  std_logic_vector(7 downto 0);
+			Load_n			: in  std_logic_vector(8 downto 1);
+			Car				: in  std_logic_vector(4 downto 1);
+			HCount			: in  std_logic_vector(8 downto 0);
+			VCount			: in  std_logic_vector(7 downto 0);
+			HBlank			: in  std_logic;
+			VBlank			: in  std_logic;
+			VBlank_n_s		: in  std_logic; -- VBLANK* on the schematic	
+			HSync				: in	std_logic;
+			VSync				: in	std_logic;
+			H256_s			: out std_logic;
+			CompBlank		: buffer std_logic;
+			CompSync_n		: out std_logic;
+			Playfield_n		: out std_logic;
+			WhiteVid			: buffer std_logic;
+			PeachVid			: buffer std_logic;
+			VioletVid		: buffer std_logic;
+			GreenVid			: buffer std_logic;
+			BlueVid			: buffer std_logic;
+			Video1			: out std_logic;
+			Video2			: out std_logic
+			);
+end playfield;
+
+architecture rtl of playfield is
+
+signal H1				: std_logic;
+signal H2				: std_logic;
+signal H4				: std_logic;
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+
+signal V1				: std_logic;
+signal V2				: std_logic;
+signal V4				: std_logic;
+
+signal char_addr		: std_logic_vector(10 downto 0) := (others => '0');
+signal char_data		: std_logic_vector(7 downto 0) := (others => '0');
+signal shift_data		: std_logic_vector(7 downto 0) := (others => '0');
+signal QH				: std_logic := '0';
+signal H8_reg			: std_logic_vector(3 downto 0) := (others => '0');
+signal H9_in			: std_logic_vector(3 downto 0) := (others => '0');
+signal H9_out			: std_logic_vector(9 downto 0) := (others => '0');
+signal H10_Q 			: std_logic_vector(7 downto 0) := (others => '0');
+signal Numeral_n		: std_logic;
+signal Color0			: std_logic;
+signal Color1			: std_logic;
+signal J10_D			: std_logic_vector(4 downto 0) := (others => '0');
+signal J10_Q			: std_logic_vector(4 downto 0) := (others => '0');
+signal CarLoad_n		: std_logic_vector(4 downto 1) := (others => '0');
+signal CarLoad			: std_logic_vector(4 downto 1) := (others => '1');
+signal CharLoad_n		: std_logic := '1';
+signal K9 				: std_logic_vector(4 downto 1) := (others => '0');
+signal DMA6_s			: std_logic := '0'; -- DMA6* on schematic
+signal PRAM6_s			: std_logic := '0'; -- PRAM6* on schematic
+
+-- These signals are based off the schematic and are formatted as Designator_PinNumber
+-- they really ought to have more descriptive names
+signal R3_8				: std_logic;
+signal P2_13			: std_logic;
+signal P3_6				: std_logic;
+signal A6_6				: std_logic;
+signal A6_3				: std_logic;
+signal L10				: std_logic;
+
+
+begin
+
+-- Video synchronization signals
+H1 <= Hcount(0);
+H2 <= Hcount(1);
+H4 <= Hcount(2);
+H256 <= Hcount(8);
+H256_n <= not(Hcount(8));
+
+V1 <= Vcount(0);
+V2 <= Vcount(1);
+V4 <= Vcount(2);
+
+-- Some glue logic, may be re-written later to be cleaner and easier to follow without referring to schematic
+CharLoad_n <= not(H1 and H2 and H4);
+R3_8 <= (H256_n or CharLoad_n);
+PRAM6_s <= PRAM(6) and (PRAM(5) nand PRAM(4));
+DMA6_s <= DMA(6) and (DMA(5) nand DMA(4));
+Char_Addr <= DMA(7) & DMA6_s & DMA(5 downto 0) & V4 & V2 & V1;
+
+
+-- Background character ROM
+--H5: entity work.Char_ROM
+--port map(
+--	clock => clk6,
+--	Address => char_addr,
+--	q => char_data
+--	);
+
+H5: entity work.ROM_H5
+port map(
+	clk => clk6,
+	addr => char_addr,
+	data => char_data
+);
+	
+	
+-- 74LS166 video shift register	
+R3: process(clk6, R3_8, VBlank_n_s, char_data, shift_data)
+begin
+	if VBlank_n_s = '0' then -- Connected Clear input
+		shift_data <= (others => '0');
+	elsif rising_edge(clk6) then 
+		if R3_8 = '0' then -- Parallel load
+			shift_data <= char_data;
+		else
+			shift_data <= shift_data(6 downto 0) & '0';
+		end if;
+	end if;
+	QH <= shift_data(7);
+end process;
+
+
+-- 9316 counter at H8
+-- CEP and CET tied to ground, counter is used only as a synchronous latch
+H8: process(clk6, CharLoad_n, DMA, H256)
+begin
+	if rising_edge(clk6) then
+		if CharLoad_n = '0' then
+			H8_reg <= ((not DMA(7)) or (DMA(5) nand DMA(4))) & ((not DMA(6)) or (DMA(5) nand DMA(4))) & (DMA(5) nand DMA(4)) & H256; -- A bit hard to follow, see schematic
+		end if;
+	end if;
+end process;
+
+Color0 <= H8_reg(3);
+Color1 <= H8_reg(2);
+Numeral_n <= H8_reg(1);
+H256_s <= H8_reg(0);
+
+Playfield_n <= (not QH);
+
+H9_in <= (not QH) & Numeral_n & Color1 & Color0;
+
+H9: process(H9_in)
+begin
+	case H9_in is
+      when "0000" =>
+         H9_out <= "1111111110";
+      when "0001" =>
+         H9_out <= "1111111101";
+      when "0010" =>
+         H9_out <= "1111111011";
+      when "0011" =>
+         H9_out <= "1111110111";
+      when "0111" =>
+         H9_out <= "1101111111";
+      when others =>
+         H9_out <= "1111111111";
+      end case;
+end process;
+
+
+LK9_10: process(Load_n, PRAM)
+begin
+	if rising_edge(Load_n(1)) then
+		CarLoad_n(1) <= (not PRAM(7));
+		CarLoad(1) <= PRAM(7);
+	end if;
+	
+	if rising_edge(Load_n(2)) then
+		CarLoad_n(2) <= (not PRAM(7));
+		CarLoad(2) <= PRAM(7);
+	end if;
+	
+	if rising_edge(Load_n(3)) then
+		CarLoad_n(3) <= (not PRAM(7));
+		CarLoad(3) <= PRAM(7);
+	end if;
+	
+	if rising_edge(Load_n(4)) then
+		CarLoad_n(4) <= (not PRAM(7));
+		CarLoad(4) <= PRAM(7);
+	end if;
+end process;
+
+K9(4) <= CarLoad_n(4) nand Car(4);
+K9(3) <= CarLoad_n(3) nand Car(3);
+K9(2) <= CarLoad_n(2) nand Car(2);
+K9(1) <= CarLoad_n(1) nand Car(1);
+
+L10 <=  ((CarLoad(4) nand Car(4)) and (CarLoad(3) nand Car(3)) and (CarLoad(2) nand Car(2)) and (CarLoad(1) nand Car(1)));
+
+J10_D <= (L10 nand H9_out(7)) & (K9(1) nand H9_out(0)) & (K9(2) nand H9_out(1)) & (K9(3) nand H9_out(2)) & (K9(4) nand H9_out(3));
+
+-- 74LS174 hex D flip-flop at J10
+J10: process(clk6, J10_D)
+begin	
+	if rising_edge(clk6) then
+		J10_Q <= J10_D;
+	end if;
+end process;
+
+WhiteVid <= J10_Q(4);
+PeachVid <= J10_Q(3);
+VioletVid <= J10_Q(2);
+GreenVid <= J10_Q(1);
+BlueVid <= J10_Q(0);
+
+CompBlank <= HBlank nor VBlank;
+CompSync_n <= HSync nor VSync;
+
+Video1 <= (WhiteVid or VioletVid or GreenVid); -- should be inverted?
+Video2 <= (PeachVid or BlueVid or WhiteVid);
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/pll.v b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/pll.v
new file mode 100644
index 00000000..aec82b25
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/pll.v	
@@ -0,0 +1,365 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	inclk0,
+	c0,
+	c1,
+	c2,
+	locked);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  c2;
+	output	  locked;
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire7 = 1'h0;
+	wire [2:2] sub_wire4 = sub_wire0[2:2];
+	wire [0:0] sub_wire3 = sub_wire0[0:0];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  c0 = sub_wire3;
+	wire  c2 = sub_wire4;
+	wire  sub_wire5 = inclk0;
+	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+	altpll	altpll_component (
+				.inclk (sub_wire6),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 125,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 112,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 125,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 56,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk2_divide_by = 125,
+		altpll_component.clk2_duty_cycle = 50,
+		altpll_component.clk2_multiply_by = 28,
+		altpll_component.clk2_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_USED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.191999"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.048000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "112"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "28"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.19200000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.04800000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "28"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/ram1k.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/ram1k.vhd
new file mode 100644
index 00000000..74d70d0c
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/ram1k.vhd	
@@ -0,0 +1,184 @@
+-- megafunction wizard: %RAM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: ram1k.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ram1k IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END ram1k;
+
+
+ARCHITECTURE SYN OF ram1k IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_a	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 1024,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 10,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		data_a => data,
+		wren_a => wren,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegData NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING ""
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/PROM_SYNC.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/PROM_SYNC.vhd
new file mode 100644
index 00000000..91ceed4b
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/PROM_SYNC.vhd	
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity PROM_SYNC is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(8 downto 0);
+	data : out std_logic_vector(3 downto 0)
+);
+end entity;
+
+architecture prom of PROM_SYNC is
+	type rom is array(0 to  511) of std_logic_vector(3 downto 0);
+	signal rom_data: rom := (
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"8",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"B",X"B",X"A",X"A",X"A",X"A",X"A",X"A",
+		X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"6",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"A",X"A",X"A",X"A",X"A",X"A",X"A",X"A",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"8",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"A",X"A",X"A",X"6",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"8",X"A",X"A",X"B",X"B",X"A",X"A",X"A",X"A");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_C1.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_C1.vhd
new file mode 100644
index 00000000..476dd023
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_C1.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_C1 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_C1 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"EC",X"28",X"F2",X"FE",X"1F",X"08",X"72",X"2A",X"F2",X"FE",X"1F",X"08",X"80",X"2B",X"F2",
+		X"FE",X"1F",X"08",X"8E",X"2C",X"F2",X"FE",X"1F",X"08",X"9C",X"2D",X"F2",X"FE",X"1F",X"08",X"AA",
+		X"2E",X"F2",X"FE",X"1F",X"08",X"B8",X"2F",X"F2",X"FE",X"1F",X"08",X"C6",X"30",X"F2",X"FE",X"1F",
+		X"08",X"D4",X"31",X"F2",X"FE",X"1F",X"08",X"E2",X"32",X"F2",X"FE",X"1F",X"08",X"FA",X"29",X"88",
+		X"FF",X"5F",X"0A",X"84",X"74",X"64",X"64",X"34",X"24",X"14",X"04",X"3C",X"2C",X"1C",X"0C",X"6C",
+		X"7C",X"8C",X"9C",X"70",X"71",X"72",X"73",X"33",X"34",X"35",X"36",X"57",X"58",X"59",X"5A",X"3C",
+		X"3D",X"3E",X"3F",X"71",X"72",X"73",X"74",X"3B",X"4B",X"5B",X"6B",X"25",X"15",X"05",X"05",X"8C",
+		X"8D",X"8E",X"8F",X"70",X"71",X"72",X"73",X"0A",X"1A",X"2A",X"3A",X"37",X"47",X"57",X"67",X"8C",
+		X"8D",X"8E",X"8F",X"70",X"71",X"72",X"73",X"34",X"35",X"36",X"37",X"48",X"49",X"4A",X"4B",X"7C",
+		X"7D",X"7E",X"7F",X"53",X"54",X"55",X"56",X"46",X"47",X"48",X"49",X"39",X"3A",X"3B",X"3C",X"7C",
+		X"7D",X"7E",X"7F",X"80",X"81",X"82",X"83",X"36",X"46",X"56",X"66",X"39",X"3A",X"3B",X"3C",X"7C",
+		X"7D",X"7E",X"7F",X"70",X"71",X"72",X"73",X"28",X"38",X"48",X"58",X"0B",X"1B",X"2B",X"3B",X"6C",
+		X"6D",X"6E",X"6F",X"60",X"61",X"62",X"63",X"98",X"88",X"78",X"68",X"49",X"4A",X"4B",X"4C",X"6C",
+		X"6D",X"6E",X"6F",X"90",X"91",X"92",X"93",X"04",X"14",X"24",X"34",X"49",X"4A",X"4B",X"4C",X"7C",
+		X"7D",X"7E",X"7F",X"96",X"A6",X"B6",X"C6",X"D6",X"00",X"00",X"00",X"00",X"3F",X"CC",X"CC",X"CC",
+		X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"95",X"FB",X"33",X"33",X"33",X"33",
+		X"22",X"22",X"22",X"22",X"22",X"22",X"33",X"34",X"44",X"D9",X"A2",X"33",X"33",X"32",X"22",X"22",
+		X"22",X"22",X"22",X"22",X"22",X"23",X"34",X"44",X"5E",X"A2",X"22",X"22",X"22",X"22",X"22",X"22",
+		X"22",X"22",X"22",X"22",X"22",X"33",X"44",X"5E",X"A2",X"22",X"21",X"12",X"22",X"22",X"22",X"22",
+		X"22",X"22",X"22",X"22",X"33",X"55",X"5E",X"A2",X"11",X"1F",X"88",X"88",X"88",X"88",X"88",X"88",
+		X"88",X"88",X"88",X"44",X"55",X"5E",X"A1",X"10",X"16",X"65",X"55",X"55",X"55",X"D9",X"11",X"1F",
+		X"B4",X"55",X"55",X"55",X"5E",X"A1",X"00",X"07",X"66",X"66",X"55",X"56",X"6D",X"91",X"FB",X"44",
+		X"55",X"55",X"55",X"6E",X"A1",X"00",X"07",X"77",X"66",X"66",X"66",X"66",X"EF",X"B4",X"44",X"55",
+		X"66",X"66",X"6E",X"D9",X"10",X"07",X"77",X"76",X"66",X"66",X"66",X"EB",X"34",X"45",X"56",X"66",
+		X"66",X"6E",X"1D",X"90",X"07",X"77",X"77",X"77",X"77",X"7F",X"B3",X"34",X"45",X"67",X"77",X"77",
+		X"6E",X"3F",X"CC",X"CC",X"CC",X"10",X"77",X"77",X"FB",X"33",X"33",X"44",X"88",X"88",X"88",X"8B",
+		X"FB",X"22",X"22",X"22",X"10",X"00",X"7F",X"B2",X"22",X"22",X"22",X"33",X"34",X"44",X"D9",X"A2",
+		X"22",X"22",X"22",X"11",X"10",X"FA",X"22",X"22",X"22",X"22",X"23",X"33",X"44",X"5E",X"A2",X"22",
+		X"22",X"21",X"11",X"0F",X"BA",X"22",X"22",X"22",X"22",X"22",X"33",X"44",X"5E",X"A2",X"21",X"11",
+		X"11",X"00",X"FB",X"5D",X"92",X"22",X"22",X"22",X"22",X"23",X"44",X"5E",X"A1",X"10",X"00",X"10",
+		X"0F",X"B5",X"55",X"D9",X"11",X"11",X"11",X"11",X"24",X"44",X"5E",X"A1",X"11",X"10",X"DC",X"CC",
+		X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"B5",X"54",X"4E",X"A1",X"00",X"07",X"65",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"54",X"4E",X"A1",X"00",X"07",X"65",X"56",X"65",X"66",
+		X"66",X"66",X"66",X"66",X"66",X"65",X"55",X"5E",X"A1",X"00",X"76",X"66",X"66",X"66",X"66",X"66",
+		X"66",X"66",X"66",X"66",X"66",X"55",X"5E",X"A1",X"00",X"77",X"66",X"66",X"66",X"66",X"66",X"66",
+		X"66",X"66",X"66",X"66",X"65",X"5E",X"A1",X"00",X"77",X"76",X"66",X"66",X"66",X"66",X"66",X"66",
+		X"66",X"66",X"66",X"65",X"5E",X"A1",X"00",X"77",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",
+		X"66",X"66",X"66",X"6E",X"D9",X"00",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",X"77",
+		X"77",X"77",X"FB",X"1D",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
+		X"88",X"B7",X"3F",X"CC",X"CC",X"CC",X"CC",X"95",X"3F",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",
+		X"95",X"FB",X"33",X"34",X"44",X"45",X"D9",X"FB",X"22",X"22",X"22",X"23",X"33",X"34",X"45",X"D9",
+		X"A2",X"23",X"33",X"44",X"44",X"5E",X"B2",X"22",X"22",X"22",X"22",X"33",X"34",X"45",X"5E",X"A2",
+		X"22",X"33",X"44",X"44",X"5E",X"22",X"22",X"22",X"22",X"22",X"23",X"34",X"55",X"5E",X"A2",X"22",
+		X"23",X"34",X"44",X"5E",X"22",X"22",X"22",X"12",X"22",X"12",X"34",X"55",X"5E",X"A2",X"11",X"12",
+		X"34",X"44",X"4E",X"11",X"11",X"11",X"F8",X"88",X"88",X"45",X"55",X"5E",X"A1",X"11",X"0E",X"34",
+		X"44",X"5E",X"11",X"11",X"17",X"A1",X"FB",X"44",X"55",X"55",X"5E",X"A1",X"11",X"7E",X"34",X"44",
+		X"5E",X"11",X"11",X"07",X"D8",X"B4",X"44",X"55",X"55",X"6E",X"A1",X"10",X"7E",X"34",X"44",X"5E",
+		X"11",X"10",X"07",X"7A",X"34",X"44",X"55",X"56",X"6E",X"A1",X"00",X"0E",X"33",X"44",X"5E",X"91",
+		X"00",X"00",X"7A",X"33",X"44",X"55",X"66",X"FB",X"A0",X"00",X"0E",X"33",X"33",X"4E",X"D9",X"00",
+		X"77",X"7A",X"33",X"34",X"56",X"6F",X"B7",X"A0",X"00",X"0E",X"33",X"33",X"3D",X"8B",X"10",X"77",
+		X"7A",X"33",X"34",X"4C",X"CC",X"95",X"A0",X"00",X"0E",X"33",X"33",X"33",X"21",X"00",X"07",X"7A",
+		X"23",X"33",X"34",X"44",X"D9",X"A1",X"00",X"7E",X"22",X"22",X"22",X"21",X"00",X"00",X"7A",X"22",
+		X"33",X"34",X"44",X"5E",X"A1",X"00",X"7E",X"22",X"22",X"22",X"11",X"00",X"00",X"7A",X"22",X"23",
+		X"34",X"44",X"4E",X"A1",X"00",X"7D",X"91",X"22",X"21",X"11",X"00",X"00",X"FC",X"92",X"22",X"34",
+		X"44",X"4E",X"A1",X"00",X"07",X"D9",X"11",X"11",X"11",X"00",X"0F",X"B5",X"D9",X"22",X"34",X"44",
+		X"4E",X"A1",X"00",X"07",X"7D",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"44",X"44",X"4E",
+		X"3F",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"95",X"FB",
+		X"44",X"45",X"55",X"56",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"D9",X"A4",X"44",
+		X"45",X"55",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"6E",X"A3",X"44",X"45",
+		X"55",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"66",X"6E",X"A3",X"44",X"44",X"5F",
+		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"97",X"77",X"7E",X"A3",X"33",X"44",X"4D",X"9F",
+		X"B3",X"33",X"33",X"33",X"33",X"3D",X"9F",X"B0",X"07",X"7E",X"D9",X"33",X"34",X"44",X"DB",X"22",
+		X"22",X"22",X"33",X"33",X"33",X"DB",X"10",X"07",X"7E",X"0D",X"93",X"33",X"44",X"42",X"22",X"22",
+		X"22",X"22",X"33",X"32",X"21",X"10",X"00",X"7E",X"01",X"D9",X"33",X"34",X"12",X"22",X"22",X"22",
+		X"22",X"22",X"22",X"11",X"10",X"00",X"0E",X"00",X"1D",X"93",X"33",X"11",X"11",X"1F",X"88",X"89",
+		X"22",X"21",X"11",X"10",X"00",X"7E",X"00",X"01",X"E1",X"13",X"11",X"11",X"4A",X"11",X"1D",X"92",
+		X"11",X"11",X"10",X"07",X"FB",X"00",X"0F",X"B1",X"13",X"33",X"33",X"3D",X"93",X"33",X"D8",X"88",
+		X"88",X"88",X"88",X"B7",X"00",X"FB",X"11",X"10",X"33",X"33",X"33",X"DC",X"CC",X"CC",X"CC",X"CC",
+		X"CC",X"CC",X"95",X"0F",X"B1",X"11",X"07",X"22",X"23",X"22",X"22",X"22",X"22",X"22",X"33",X"34",
+		X"44",X"D9",X"FB",X"11",X"10",X"07",X"F9",X"22",X"22",X"22",X"22",X"22",X"22",X"23",X"34",X"44",
+		X"5E",X"A1",X"11",X"00",X"0F",X"BD",X"92",X"22",X"22",X"22",X"22",X"22",X"22",X"34",X"44",X"5E",
+		X"A1",X"10",X"00",X"FB",X"55",X"D9",X"11",X"11",X"11",X"11",X"11",X"22",X"24",X"44",X"5E",X"A1",
+		X"00",X"00",X"6C",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"B4",X"44",X"4E",X"3F",X"CC",
+		X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"9F",X"CC",X"CC",X"CC",X"95",X"FB",X"22",X"22",
+		X"22",X"22",X"22",X"22",X"22",X"33",X"34",X"DB",X"23",X"33",X"34",X"D9",X"A2",X"22",X"22",X"22",
+		X"22",X"22",X"22",X"22",X"23",X"33",X"32",X"22",X"33",X"34",X"4E",X"A2",X"22",X"22",X"22",X"22",
+		X"22",X"22",X"22",X"22",X"23",X"22",X"22",X"23",X"34",X"5E",X"A2",X"22",X"12",X"22",X"22",X"22",
+		X"22",X"22",X"22",X"22",X"22",X"11",X"12",X"45",X"5E",X"A1",X"11",X"11",X"FC",X"CC",X"CC",X"CC",
+		X"CC",X"C9",X"33",X"33",X"33",X"F4",X"55",X"5E",X"A1",X"11",X"1F",X"B4",X"44",X"45",X"55",X"56",
+		X"6D",X"88",X"88",X"88",X"B5",X"55",X"5E",X"A1",X"11",X"0E",X"34",X"44",X"45",X"55",X"56",X"66",
+		X"66",X"66",X"66",X"56",X"66",X"6E",X"A1",X"10",X"0E",X"34",X"44",X"45",X"56",X"66",X"66",X"66",
+		X"66",X"66",X"66",X"66",X"6E",X"A1",X"00",X"0E",X"33",X"44",X"45",X"66",X"66",X"66",X"66",X"66",
+		X"66",X"66",X"66",X"6E",X"A0",X"00",X"0E",X"33",X"34",X"45",X"89",X"77",X"77",X"66",X"66",X"66",
+		X"66",X"66",X"FB",X"A0",X"00",X"0E",X"33",X"33",X"4E",X"4D",X"97",X"77",X"77",X"77",X"77",X"77",
+		X"7F",X"B7",X"A0",X"00",X"0E",X"22",X"23",X"33",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",
+		X"95",X"A0",X"00",X"0E",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"23",X"33",X"44",X"44",X"D9",
+		X"A0",X"00",X"0E",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"33",X"34",X"44",X"5E",X"A0",
+		X"00",X"0D",X"92",X"22",X"22",X"22",X"22",X"22",X"22",X"22",X"23",X"34",X"45",X"5E",X"A0",X"00",
+		X"76",X"D9",X"11",X"11",X"11",X"11",X"11",X"11",X"22",X"22",X"34",X"55",X"5E",X"A0",X"00",X"07",
+		X"6D",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"45",X"55",X"5E",X"3F",X"CC",X"CC",X"CC",
+		X"CC",X"CC",X"95",X"43",X"FC",X"CC",X"CC",X"CC",X"CC",X"CC",X"95",X"FB",X"22",X"23",X"33",X"34",
+		X"45",X"D9",X"3F",X"B2",X"23",X"33",X"33",X"44",X"44",X"D9",X"A2",X"22",X"22",X"33",X"34",X"44",
+		X"5D",X"8B",X"22",X"22",X"33",X"33",X"44",X"44",X"5E",X"A2",X"22",X"22",X"23",X"34",X"44",X"55",
+		X"E2",X"22",X"22",X"23",X"33",X"44",X"44",X"5E",X"A1",X"11",X"11",X"12",X"34",X"44",X"55",X"E2",
+		X"22",X"22",X"22",X"33",X"44",X"44",X"5E",X"A1",X"11",X"11",X"FC",X"94",X"44",X"45",X"E1",X"11",
+		X"11",X"1F",X"93",X"44",X"44",X"5E",X"A1",X"11",X"17",X"D9",X"A4",X"44",X"45",X"E1",X"11",X"11",
+		X"1A",X"D9",X"34",X"44",X"5E",X"A1",X"11",X"07",X"7D",X"A3",X"44",X"45",X"E1",X"11",X"10",X"7D",
+		X"9A",X"44",X"44",X"5E",X"D9",X"00",X"07",X"76",X"A3",X"34",X"45",X"E9",X"11",X"00",X"77",X"DA",
+		X"44",X"44",X"5E",X"2A",X"00",X"00",X"76",X"A3",X"33",X"45",X"AD",X"90",X"00",X"07",X"6A",X"44",
+		X"44",X"5E",X"FB",X"10",X"00",X"7E",X"23",X"33",X"35",X"A4",X"E0",X"00",X"07",X"7A",X"44",X"44",
+		X"5E",X"A1",X"10",X"00",X"7E",X"23",X"33",X"33",X"D8",X"B1",X"10",X"07",X"7A",X"44",X"44",X"5E",
+		X"A1",X"10",X"00",X"7A",X"23",X"33",X"33",X"32",X"11",X"00",X"07",X"7A",X"44",X"44",X"5E",X"A1",
+		X"10",X"00",X"7A",X"22",X"22",X"22",X"22",X"11",X"00",X"07",X"7A",X"44",X"45",X"5E",X"A1",X"00",
+		X"00",X"7A",X"22",X"22",X"22",X"21",X"11",X"00",X"07",X"7A",X"44",X"55",X"5E",X"A1",X"00",X"00",
+		X"7D",X"92",X"22",X"22",X"11",X"10",X"00",X"07",X"FB",X"45",X"55",X"5E",X"A1",X"00",X"00",X"76",
+		X"D9",X"11",X"11",X"11",X"10",X"00",X"0F",X"B4",X"55",X"55",X"5E",X"A1",X"00",X"00",X"77",X"6D",
+		X"CC",X"CC",X"CC",X"CC",X"CC",X"CB",X"55",X"55",X"55",X"5E",X"23",X"FC",X"CC",X"CC",X"CC",X"CC",
+		X"CC",X"95",X"44",X"3F",X"CC",X"CC",X"CC",X"CC",X"95",X"3F",X"B2",X"22",X"23",X"33",X"44",X"44",
+		X"D9",X"53",X"FB",X"33",X"33",X"34",X"45",X"D9",X"2A",X"22",X"22",X"22",X"33",X"34",X"44",X"4D",
+		X"9F",X"B3",X"23",X"33",X"34",X"44",X"5E",X"2A",X"22",X"22",X"22",X"23",X"33",X"34",X"44",X"DA",
+		X"22",X"22",X"33",X"34",X"44",X"5E",X"2A",X"22",X"11",X"11",X"22",X"33",X"34",X"44",X"4A",X"22",
+		X"22",X"23",X"34",X"44",X"5E",X"2A",X"11",X"11",X"10",X"EA",X"23",X"34",X"44",X"4A",X"22",X"22",
+		X"22",X"34",X"44",X"5E",X"2A",X"11",X"11",X"07",X"7D",X"92",X"34",X"44",X"4A",X"11",X"11",X"1E",
+		X"44",X"44",X"4E",X"1D",X"91",X"10",X"07",X"77",X"D9",X"33",X"44",X"4A",X"11",X"11",X"0E",X"44",
+		X"44",X"4E",X"11",X"D9",X"00",X"07",X"77",X"7E",X"33",X"44",X"4A",X"11",X"10",X"0E",X"44",X"44",
+		X"4E",X"11",X"1D",X"90",X"07",X"77",X"7E",X"33",X"34",X"4A",X"11",X"00",X"0E",X"44",X"44",X"4E",
+		X"13",X"41",X"D9",X"07",X"77",X"7E",X"33",X"34",X"4A",X"10",X"00",X"0E",X"44",X"44",X"4E",X"3F",
+		X"CC",X"CB",X"10",X"77",X"7E",X"33",X"33",X"4B",X"10",X"00",X"0E",X"44",X"44",X"4E",X"FB",X"22",
+		X"22",X"10",X"01",X"1E",X"22",X"22",X"32",X"10",X"00",X"0E",X"44",X"44",X"4E",X"A2",X"22",X"21",
+		X"10",X"00",X"7E",X"22",X"22",X"21",X"10",X"00",X"0E",X"44",X"44",X"4E",X"A2",X"21",X"11",X"00",
+		X"00",X"0E",X"22",X"22",X"11",X"00",X"00",X"0E",X"44",X"54",X"4E",X"A2",X"11",X"11",X"00",X"00",
+		X"FC",X"92",X"21",X"11",X"00",X"00",X"FB",X"55",X"44",X"4E",X"A1",X"11",X"11",X"00",X"0F",X"B1",
+		X"D9",X"11",X"11",X"00",X"0F",X"B5",X"55",X"44",X"4E",X"A0",X"00",X"0D",X"CC",X"CC",X"CC",X"CC",
+		X"CC",X"CC",X"CC",X"CB",X"55",X"55",X"44",X"4E",X"3F",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",X"CC",
+		X"93",X"FC",X"CC",X"CC",X"CC",X"CC",X"95",X"FB",X"22",X"22",X"22",X"23",X"33",X"34",X"44",X"D8",
+		X"B2",X"23",X"33",X"34",X"44",X"D9",X"A2",X"22",X"22",X"22",X"22",X"33",X"34",X"44",X"5E",X"22",
+		X"22",X"33",X"34",X"44",X"4E",X"A2",X"22",X"22",X"22",X"22",X"23",X"34",X"45",X"5E",X"22",X"22",
+		X"23",X"34",X"44",X"4E",X"A2",X"22",X"11",X"11",X"11",X"22",X"34",X"55",X"5E",X"22",X"22",X"22");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_E1.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_E1.vhd
new file mode 100644
index 00000000..48eede2a
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_E1.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_E1 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_E1 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"C6",X"C6",X"20",X"53",X"3D",X"A5",X"C6",X"D0",X"03",X"4C",X"AE",X"3B",X"20",X"8C",X"3B",X"90",
+		X"0A",X"20",X"38",X"3D",X"24",X"BB",X"10",X"03",X"20",X"53",X"3D",X"20",X"72",X"3D",X"4C",X"B7",
+		X"37",X"20",X"D3",X"3A",X"A9",X"01",X"85",X"00",X"20",X"2E",X"3D",X"E6",X"B8",X"20",X"08",X"36",
+		X"A2",X"06",X"20",X"C0",X"39",X"95",X"68",X"B5",X"41",X"30",X"1A",X"B5",X"A1",X"F0",X"05",X"D6",
+		X"A1",X"4C",X"73",X"38",X"B5",X"41",X"30",X"0D",X"A9",X"00",X"95",X"A1",X"A9",X"F7",X"35",X"A0",
+		X"95",X"A0",X"4C",X"73",X"38",X"95",X"20",X"A0",X"00",X"94",X"C7",X"B5",X"A0",X"29",X"08",X"D0",
+		X"0E",X"A9",X"01",X"95",X"80",X"A9",X"08",X"15",X"A0",X"95",X"A0",X"A9",X"0F",X"85",X"CF",X"A9",
+		X"10",X"95",X"A1",X"A4",X"CF",X"F0",X"0B",X"8A",X"D0",X"0A",X"A5",X"B8",X"29",X"03",X"D0",X"04",
+		X"C6",X"CF",X"84",X"42",X"B5",X"C7",X"F0",X"1A",X"95",X"69",X"D6",X"C7",X"A0",X"02",X"B5",X"A0",
+		X"30",X"04",X"A0",X"02",X"D0",X"06",X"29",X"10",X"D0",X"02",X"A0",X"FE",X"98",X"18",X"75",X"99",
+		X"95",X"99",X"B5",X"A0",X"10",X"28",X"A5",X"B8",X"29",X"03",X"D0",X"22",X"20",X"03",X"3B",X"C9",
+		X"F9",X"10",X"02",X"95",X"69",X"C9",X"00",X"18",X"30",X"0C",X"75",X"80",X"D0",X"0E",X"B5",X"80",
+		X"F0",X"0A",X"A9",X"FF",X"D0",X"06",X"75",X"80",X"D0",X"02",X"A9",X"01",X"95",X"80",X"B5",X"80",
+		X"4A",X"4A",X"4A",X"85",X"BC",X"B5",X"B1",X"B4",X"A0",X"30",X"0C",X"B5",X"99",X"4A",X"4A",X"4A",
+		X"4A",X"4A",X"09",X"88",X"4C",X"07",X"39",X"A8",X"0A",X"85",X"BE",X"B9",X"C4",X"3D",X"A8",X"A9",
+		X"00",X"18",X"65",X"BC",X"88",X"D0",X"FA",X"4A",X"4A",X"4A",X"38",X"E5",X"BE",X"10",X"02",X"A9",
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+		X"20",X"47",X"55",X"54",X"53",X"43",X"48",X"52",X"49",X"46",X"54",X"00",X"43",X"52",X"45",X"44",
+		X"49",X"54",X"20",X"50",X"4F",X"55",X"52",X"20",X"20",X"20",X"4A",X"4F",X"55",X"45",X"55",X"52",
+		X"53",X"00",X"20",X"20",X"4A",X"55",X"47",X"41",X"44",X"4F",X"52",X"45",X"53",X"20",X"41",X"56",
+		X"45",X"4E",X"54",X"41",X"4A",X"41",X"4E",X"00",X"82",X"00",X"0A",X"35",X"27",X"35",X"27",X"35");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_H5.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_H5.vhd
new file mode 100644
index 00000000..968d2e0a
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_H5.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_H5 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_H5 is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"6C",X"C6",X"C6",X"FE",X"C6",X"C6",
+		X"00",X"FC",X"C6",X"C6",X"FC",X"C6",X"C6",X"FC",X"00",X"3C",X"66",X"C0",X"C0",X"C0",X"66",X"3C",
+		X"00",X"F8",X"CC",X"C6",X"C6",X"C6",X"CC",X"F8",X"00",X"FC",X"C0",X"C0",X"F8",X"C0",X"C0",X"FE",
+		X"00",X"FE",X"C0",X"C0",X"FC",X"C0",X"C0",X"C0",X"00",X"3E",X"60",X"C0",X"CE",X"C6",X"66",X"3E",
+		X"00",X"C6",X"C6",X"C6",X"FE",X"C6",X"C6",X"C6",X"00",X"FC",X"30",X"30",X"30",X"30",X"30",X"FC",
+		X"00",X"06",X"06",X"06",X"06",X"06",X"C6",X"7C",X"00",X"C6",X"CC",X"D8",X"F0",X"F8",X"DC",X"CE",
+		X"00",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"FE",X"00",X"C6",X"EE",X"FE",X"FE",X"D6",X"C6",X"C6",
+		X"00",X"C6",X"E6",X"F6",X"FE",X"DE",X"CE",X"C6",X"00",X"7C",X"C6",X"C6",X"C6",X"C6",X"C6",X"7C",
+		X"00",X"FC",X"C6",X"C6",X"C6",X"FC",X"C0",X"C0",X"00",X"7C",X"C6",X"C6",X"C6",X"CE",X"CC",X"7A",
+		X"00",X"FC",X"C6",X"C6",X"CE",X"F8",X"DC",X"CE",X"00",X"78",X"CC",X"C0",X"7C",X"06",X"C6",X"7C",
+		X"00",X"FC",X"30",X"30",X"30",X"30",X"30",X"30",X"00",X"C6",X"C6",X"C6",X"C6",X"C6",X"C6",X"7C",
+		X"00",X"C6",X"C6",X"C6",X"EE",X"7C",X"38",X"10",X"00",X"C6",X"C6",X"D6",X"FE",X"FE",X"EE",X"C6",
+		X"00",X"C6",X"EE",X"7C",X"38",X"7C",X"EE",X"C6",X"00",X"CC",X"CC",X"CC",X"78",X"30",X"30",X"30",
+		X"00",X"FE",X"0E",X"1C",X"38",X"70",X"E0",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"EE",X"4A",X"4E",X"4C",X"4A",X"00",X"00",X"00",X"4D",X"E9",X"AD",X"E9",X"A9",X"00",X"00",
+		X"00",X"D7",X"14",X"94",X"14",X"17",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"66",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"60",X"00",
+		X"00",X"10",X"38",X"54",X"10",X"10",X"00",X"00",X"00",X"00",X"1C",X"0C",X"14",X"20",X"00",X"00",
+		X"08",X"1C",X"36",X"77",X"77",X"77",X"36",X"1C",X"08",X"1C",X"22",X"7B",X"63",X"6F",X"22",X"1C",
+		X"08",X"1C",X"22",X"7B",X"63",X"7B",X"22",X"1C",X"08",X"1C",X"2A",X"6B",X"63",X"7B",X"3A",X"1C",
+		X"08",X"1C",X"22",X"6F",X"63",X"7B",X"22",X"1C",X"08",X"1C",X"2E",X"6F",X"63",X"6B",X"22",X"1C",
+		X"08",X"1C",X"22",X"7B",X"7B",X"7B",X"3A",X"1C",X"08",X"1C",X"22",X"6B",X"63",X"6B",X"22",X"1C",
+		X"08",X"1C",X"22",X"6B",X"63",X"7B",X"3A",X"1C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"38",X"4C",X"C6",X"C6",X"C6",X"64",X"38",X"00",X"30",X"70",X"30",X"30",X"30",X"30",X"FC",
+		X"00",X"7C",X"C6",X"0E",X"3C",X"78",X"E0",X"FE",X"00",X"7E",X"0C",X"18",X"3C",X"06",X"C6",X"7C",
+		X"00",X"1C",X"3C",X"6C",X"CC",X"FE",X"0C",X"0C",X"00",X"FC",X"C0",X"FC",X"06",X"06",X"C6",X"7C",
+		X"00",X"3C",X"60",X"C0",X"FC",X"C6",X"C6",X"7C",X"00",X"FE",X"C6",X"0C",X"18",X"30",X"30",X"30",
+		X"00",X"78",X"C4",X"E4",X"78",X"9E",X"86",X"7C",X"00",X"7C",X"C6",X"C6",X"7E",X"06",X"0C",X"78",
+		X"00",X"10",X"38",X"AA",X"AA",X"28",X"AA",X"BA",X"00",X"10",X"38",X"BA",X"BA",X"38",X"BA",X"BA",
+		X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"FC",X"26",X"22",X"26",X"FC",X"F8",X"00",
+		X"FE",X"FE",X"92",X"92",X"92",X"FE",X"6C",X"00",X"38",X"7C",X"C6",X"82",X"82",X"C6",X"44",X"00",
+		X"FE",X"FE",X"82",X"82",X"C6",X"7C",X"38",X"00",X"FE",X"FE",X"92",X"92",X"92",X"82",X"80",X"00",
+		X"FE",X"FE",X"12",X"12",X"12",X"12",X"02",X"00",X"38",X"7C",X"C6",X"82",X"92",X"F2",X"F2",X"00",
+		X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"00",
+		X"40",X"C0",X"80",X"80",X"80",X"FE",X"7E",X"00",X"FE",X"FE",X"30",X"78",X"EC",X"C6",X"82",X"00",
+		X"FE",X"FE",X"80",X"80",X"80",X"80",X"80",X"00",X"FE",X"FE",X"1C",X"38",X"1C",X"FE",X"FE",X"00",
+		X"FE",X"FE",X"1C",X"38",X"70",X"FE",X"FE",X"00",X"7C",X"FE",X"82",X"82",X"82",X"FE",X"7C",X"00",
+		X"FE",X"FE",X"22",X"22",X"22",X"3E",X"1C",X"00",X"7C",X"FE",X"82",X"A2",X"E2",X"7E",X"BC",X"00",
+		X"FE",X"FE",X"22",X"62",X"F2",X"DE",X"9C",X"00",X"4C",X"DE",X"92",X"92",X"96",X"F4",X"60",X"00",
+		X"02",X"02",X"FE",X"FE",X"02",X"02",X"00",X"00",X"7E",X"FE",X"80",X"80",X"80",X"FE",X"7E",X"00",
+		X"1E",X"3E",X"70",X"E0",X"70",X"3E",X"1E",X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00",
+		X"C6",X"EE",X"7C",X"38",X"7C",X"EE",X"C6",X"00",X"0E",X"1E",X"F0",X"F0",X"1E",X"0E",X"00",X"00",
+		X"C2",X"E2",X"F2",X"B2",X"9E",X"8E",X"86",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"02",X"3E",X"02",X"00",X"3E",X"1A",X"2E",X"00",X"3C",X"16",X"3C",X"00",X"3E",X"0A",X"00",X"3E",
+		X"0A",X"02",X"00",X"3E",X"00",X"3E",X"22",X"22",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"60",X"60",X"00",X"00",X"60",X"60",X"00",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"08",X"04",X"3E",X"04",X"08",X"00",X"00",X"00",X"00",X"20",X"14",X"0C",X"1C",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"80",X"84",X"FE",X"FE",X"80",X"80",X"00",X"00",
+		X"C4",X"E6",X"F2",X"B2",X"BA",X"9E",X"8C",X"00",X"40",X"C2",X"92",X"9A",X"9E",X"F6",X"62",X"00",
+		X"30",X"38",X"2C",X"26",X"FE",X"FE",X"20",X"00",X"4E",X"CE",X"8A",X"8A",X"8A",X"FA",X"70",X"00",
+		X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00",X"06",X"06",X"E2",X"F2",X"1A",X"0E",X"06",X"00",
+		X"6C",X"9E",X"9A",X"B2",X"B2",X"EC",X"60",X"00",X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",
+		X"D8",X"00",X"FC",X"86",X"FC",X"00",X"D8",X"00",X"D8",X"00",X"FC",X"FE",X"FC",X"00",X"D8",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"63",X"63",X"7F",X"63",X"63",X"36",X"1C",X"0C",
+		X"3F",X"63",X"63",X"3F",X"63",X"63",X"3F",X"00",X"3C",X"66",X"03",X"03",X"03",X"66",X"3C",X"00",
+		X"1F",X"33",X"63",X"63",X"63",X"33",X"1F",X"00",X"7F",X"03",X"03",X"1F",X"03",X"03",X"3F",X"00",
+		X"03",X"03",X"03",X"3F",X"03",X"03",X"7F",X"00",X"7C",X"66",X"63",X"73",X"03",X"06",X"7C",X"00",
+		X"63",X"63",X"63",X"7F",X"63",X"63",X"63",X"00",X"3F",X"0C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00",
+		X"3E",X"63",X"60",X"60",X"60",X"60",X"60",X"00",X"73",X"3B",X"1F",X"0F",X"1B",X"33",X"63",X"00",
+		X"7F",X"03",X"03",X"03",X"03",X"03",X"03",X"00",X"63",X"63",X"6B",X"7F",X"7F",X"77",X"63",X"00",
+		X"63",X"73",X"7B",X"7F",X"6F",X"67",X"63",X"00",X"3E",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",
+		X"03",X"03",X"3F",X"63",X"63",X"63",X"3F",X"00",X"5E",X"33",X"7B",X"63",X"63",X"63",X"3E",X"00",
+		X"73",X"3B",X"1F",X"73",X"63",X"63",X"3F",X"00",X"3E",X"63",X"60",X"3E",X"03",X"33",X"1E",X"00",
+		X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00",X"3E",X"63",X"63",X"63",X"63",X"63",X"63",X"00",
+		X"08",X"1C",X"3E",X"77",X"63",X"63",X"63",X"00",X"63",X"77",X"7F",X"7F",X"6B",X"63",X"63",X"00",
+		X"63",X"77",X"3E",X"1C",X"3E",X"77",X"63",X"00",X"0C",X"0C",X"0C",X"1E",X"33",X"33",X"33",X"00",
+		X"7F",X"07",X"0E",X"1C",X"38",X"70",X"7F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"52",X"32",X"72",X"52",X"77",X"00",X"00",X"00",X"95",X"97",X"B5",X"97",X"B2",X"00",
+		X"00",X"00",X"E8",X"28",X"29",X"28",X"EB",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"66",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"08",X"08",X"2A",X"1C",X"08",X"00",X"00",X"00",X"04",X"28",X"30",X"38",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"1C",X"26",X"63",X"63",X"63",X"32",X"1C",X"00",X"3F",X"0C",X"0C",X"0C",X"0C",X"0E",X"0C",X"00",
+		X"7F",X"07",X"1E",X"3C",X"70",X"63",X"3E",X"00",X"3E",X"63",X"60",X"3C",X"18",X"30",X"7E",X"00",
+		X"30",X"30",X"7F",X"33",X"36",X"3C",X"38",X"00",X"3E",X"63",X"60",X"60",X"3F",X"03",X"3F",X"00",
+		X"3E",X"63",X"63",X"3F",X"03",X"06",X"3C",X"00",X"0C",X"0C",X"0C",X"18",X"30",X"63",X"6F",X"00",
+		X"3E",X"61",X"79",X"1E",X"27",X"23",X"1E",X"00",X"1E",X"30",X"60",X"7E",X"63",X"63",X"3E",X"00",
+		X"5D",X"55",X"14",X"55",X"55",X"1C",X"08",X"00",X"5D",X"5D",X"1C",X"5D",X"5D",X"1C",X"08",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"3F",X"64",X"44",X"64",X"3F",X"1F",
+		X"00",X"36",X"7F",X"49",X"49",X"49",X"7F",X"7F",X"00",X"22",X"63",X"41",X"41",X"63",X"3E",X"1C",
+		X"00",X"1C",X"3E",X"63",X"41",X"41",X"7F",X"7F",X"00",X"01",X"41",X"49",X"49",X"49",X"7F",X"7F",
+		X"00",X"40",X"48",X"48",X"48",X"48",X"7F",X"7F",X"00",X"4F",X"4F",X"49",X"41",X"63",X"3E",X"1C",
+		X"00",X"7F",X"7F",X"08",X"08",X"08",X"7F",X"7F",X"00",X"00",X"41",X"41",X"7F",X"7F",X"41",X"41",
+		X"00",X"7E",X"7F",X"01",X"01",X"01",X"03",X"02",X"00",X"41",X"63",X"37",X"1E",X"0C",X"7F",X"7F",
+		X"00",X"01",X"01",X"01",X"01",X"01",X"7F",X"7F",X"00",X"7F",X"7F",X"38",X"1C",X"38",X"7F",X"7F",
+		X"00",X"7F",X"7F",X"0E",X"1C",X"38",X"7F",X"7F",X"00",X"3E",X"7F",X"41",X"41",X"41",X"7F",X"3E",
+		X"00",X"38",X"7C",X"44",X"44",X"44",X"7F",X"7F",X"00",X"3D",X"7E",X"47",X"45",X"41",X"7F",X"3E",
+		X"00",X"39",X"7B",X"4F",X"46",X"44",X"7F",X"7F",X"00",X"06",X"2F",X"69",X"49",X"49",X"7B",X"32",
+		X"00",X"00",X"40",X"40",X"7F",X"7F",X"40",X"40",X"00",X"7E",X"7F",X"01",X"01",X"01",X"7F",X"7E",
+		X"00",X"78",X"7C",X"0E",X"07",X"0E",X"7C",X"78",X"00",X"7F",X"7F",X"0E",X"1C",X"0E",X"7F",X"7F",
+		X"00",X"63",X"77",X"3E",X"1C",X"3E",X"77",X"63",X"00",X"00",X"70",X"78",X"0F",X"0F",X"78",X"70",
+		X"00",X"61",X"71",X"79",X"5D",X"4F",X"47",X"43",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"74",X"58",X"7C",X"00",X"40",X"7C",X"40",X"7C",X"00",X"50",X"7C",X"00",X"3C",X"68",X"3C",
+		X"44",X"44",X"7C",X"00",X"7C",X"00",X"40",X"50",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"06",X"06",X"00",X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"06",X"00",
+		X"00",X"00",X"10",X"20",X"7C",X"20",X"10",X"00",X"00",X"00",X"38",X"30",X"28",X"04",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"1C",X"3E",X"61",X"41",X"43",X"3E",X"1C",X"00",X"00",X"01",X"01",X"7F",X"7F",X"21",X"01",
+		X"00",X"31",X"79",X"5D",X"4D",X"4F",X"67",X"23",X"00",X"46",X"6F",X"79",X"59",X"49",X"43",X"02",
+		X"00",X"04",X"7F",X"7F",X"64",X"34",X"1C",X"0C",X"00",X"0E",X"5F",X"51",X"51",X"51",X"73",X"72",
+		X"00",X"06",X"4F",X"49",X"49",X"69",X"3F",X"1E",X"00",X"60",X"70",X"58",X"4F",X"47",X"60",X"60",
+		X"00",X"06",X"37",X"4D",X"4D",X"59",X"79",X"36",X"00",X"3C",X"7E",X"4B",X"49",X"49",X"79",X"30",
+		X"00",X"1B",X"00",X"3F",X"61",X"3F",X"00",X"1B",X"00",X"1B",X"00",X"3F",X"7F",X"3F",X"00",X"1B",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_K1_High.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_K1_High.vhd
new file mode 100644
index 00000000..7ab68e4a
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_K1_High.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_K1_High is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(3 downto 0)
+);
+end entity;
+
+architecture prom of ROM_K1_High is
+	type rom is array(0 to  2047) of std_logic_vector(3 downto 0);
+	signal rom_data: rom := (
+		X"3",X"4",X"4",X"A",X"1",X"1",X"F",X"C",X"C",X"5",X"5",X"5",X"1",X"1",X"0",X"3",
+		X"4",X"4",X"A",X"1",X"1",X"B",X"4",X"5",X"5",X"6",X"6",X"1",X"1",X"0",X"4",X"4",
+		X"4",X"A",X"1",X"0",X"4",X"4",X"5",X"5",X"6",X"6",X"1",X"1",X"0",X"4",X"4",X"4",
+		X"A",X"1",X"0",X"3",X"4",X"5",X"5",X"6",X"6",X"1",X"0",X"0",X"4",X"4",X"4",X"A",
+		X"0",X"0",X"3",X"4",X"5",X"6",X"6",X"F",X"9",X"0",X"0",X"4",X"4",X"4",X"A",X"0",
+		X"0",X"3",X"3",X"5",X"6",X"6",X"B",X"A",X"0",X"0",X"4",X"4",X"4",X"A",X"0",X"0",
+		X"3",X"3",X"4",X"C",X"C",X"C",X"2",X"0",X"0",X"4",X"4",X"4",X"A",X"0",X"0",X"2",
+		X"2",X"3",X"2",X"2",X"2",X"1",X"0",X"0",X"4",X"4",X"4",X"A",X"0",X"0",X"2",X"2",
+		X"2",X"2",X"2",X"2",X"1",X"0",X"0",X"4",X"4",X"4",X"A",X"0",X"0",X"2",X"2",X"2",
+		X"2",X"2",X"1",X"1",X"0",X"0",X"4",X"4",X"4",X"A",X"0",X"0",X"2",X"2",X"2",X"2",
+		X"1",X"1",X"1",X"0",X"F",X"5",X"4",X"4",X"A",X"0",X"7",X"9",X"2",X"2",X"2",X"1",
+		X"1",X"1",X"0",X"B",X"5",X"4",X"4",X"A",X"0",X"7",X"D",X"C",X"C",X"C",X"C",X"C",
+		X"C",X"C",X"5",X"5",X"4",X"4",X"3",X"3",X"4",X"C",X"C",X"8",X"4",X"4",X"4",X"4",
+		X"8",X"8",X"4",X"4",X"4",X"3",X"3",X"C",X"3",X"3",X"3",X"9",X"4",X"4",X"F",X"3",
+		X"3",X"C",X"9",X"5",X"2",X"F",X"2",X"3",X"3",X"3",X"D",X"4",X"4",X"B",X"2",X"3",
+		X"3",X"D",X"5",X"2",X"A",X"2",X"3",X"3",X"3",X"3",X"8",X"8",X"2",X"2",X"3",X"3",
+		X"4",X"9",X"2",X"2",X"2",X"2",X"3",X"3",X"3",X"3",X"2",X"2",X"2",X"3",X"3",X"4",
+		X"E",X"2",X"2",X"1",X"2",X"2",X"2",X"2",X"2",X"2",X"1",X"1",X"3",X"3",X"4",X"E",
+		X"2",X"1",X"1",X"2",X"2",X"3",X"2",X"2",X"1",X"1",X"C",X"9",X"3",X"4",X"5",X"E",
+		X"1",X"1",X"1",X"9",X"2",X"2",X"2",X"1",X"F",X"7",X"E",X"3",X"4",X"5",X"E",X"1",
+		X"1",X"F",X"D",X"2",X"2",X"1",X"1",X"B",X"0",X"2",X"4",X"4",X"5",X"A",X"1",X"1",
+		X"B",X"1",X"9",X"1",X"1",X"F",X"7",X"0",X"2",X"4",X"4",X"5",X"A",X"1",X"0",X"6",
+		X"6",X"D",X"1",X"1",X"B",X"7",X"0",X"2",X"4",X"4",X"5",X"A",X"0",X"0",X"6",X"6",
+		X"1",X"8",X"C",X"0",X"7",X"0",X"2",X"4",X"4",X"5",X"A",X"0",X"0",X"6",X"6",X"0",
+		X"0",X"0",X"0",X"4",X"4",X"E",X"5",X"5",X"5",X"A",X"0",X"0",X"A",X"5",X"0",X"0",
+		X"0",X"0",X"4",X"4",X"B",X"5",X"5",X"5",X"A",X"0",X"7",X"E",X"4",X"4",X"4",X"4",
+		X"4",X"4",X"8",X"5",X"5",X"5",X"5",X"A",X"0",X"7",X"7",X"4",X"4",X"4",X"4",X"3",
+		X"8",X"4",X"5",X"5",X"5",X"5",X"A",X"0",X"7",X"7",X"9",X"4",X"4",X"4",X"8",X"5",
+		X"5",X"5",X"5",X"5",X"5",X"A",X"0",X"7",X"7",X"D",X"8",X"8",X"C",X"5",X"5",X"5",
+		X"5",X"5",X"5",X"5",X"4",X"2",X"3",X"C",X"C",X"C",X"C",X"9",X"3",X"3",X"C",X"C",
+		X"C",X"C",X"5",X"4",X"3",X"C",X"4",X"4",X"4",X"4",X"D",X"5",X"F",X"3",X"3",X"4",
+		X"4",X"9",X"4",X"F",X"3",X"2",X"2",X"3",X"4",X"5",X"9",X"B",X"1",X"2",X"3",X"3",
+		X"D",X"4",X"B",X"2",X"2",X"2",X"3",X"3",X"5",X"E",X"2",X"1",X"2",X"3",X"4",X"5",
+		X"3",X"2",X"1",X"2",X"2",X"2",X"3",X"5",X"E",X"1",X"1",X"2",X"3",X"4",X"5",X"E",
+		X"2",X"1",X"2",X"2",X"2",X"4",X"4",X"E",X"1",X"0",X"1",X"3",X"4",X"4",X"A",X"1",
+		X"1",X"4",X"6",X"8",X"4",X"4",X"E",X"0",X"0",X"0",X"3",X"4",X"5",X"A",X"1",X"2",
+		X"4",X"E",X"0",X"4",X"5",X"E",X"0",X"1",X"0",X"3",X"4",X"4",X"A",X"1",X"2",X"3",
+		X"D",X"F",X"5",X"5",X"E",X"0",X"1",X"7",X"3",X"4",X"4",X"A",X"0",X"0",X"3",X"4",
+		X"B",X"5",X"5",X"E",X"1",X"7",X"7",X"3",X"4",X"4",X"A",X"0",X"0",X"2",X"3",X"4",
+		X"4",X"6",X"B",X"1",X"0",X"7",X"3",X"4",X"4",X"A",X"0",X"0",X"2",X"3",X"4",X"4",
+		X"F",X"1",X"0",X"0",X"7",X"3",X"4",X"4",X"A",X"0",X"0",X"2",X"3",X"3",X"3",X"B",
+		X"1",X"0",X"0",X"7",X"4",X"4",X"4",X"A",X"0",X"0",X"9",X"2",X"3",X"2",X"1",X"2",
+		X"1",X"1",X"7",X"4",X"4",X"4",X"A",X"0",X"7",X"D",X"1",X"2",X"2",X"1",X"2",X"1",
+		X"1",X"E",X"5",X"5",X"4",X"A",X"0",X"7",X"7",X"9",X"1",X"1",X"1",X"1",X"1",X"7",
+		X"B",X"5",X"6",X"4",X"A",X"0",X"7",X"7",X"D",X"0",X"0",X"0",X"0",X"0",X"F",X"5",
+		X"5",X"5",X"4",X"A",X"0",X"7",X"7",X"7",X"C",X"C",X"C",X"C",X"C",X"B",X"5",X"5",
+		X"5",X"5",X"3",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"9",X"3",X"C",X"C",X"C",X"C",
+		X"9",X"F",X"3",X"3",X"3",X"3",X"3",X"3",X"4",X"D",X"F",X"3",X"3",X"3",X"4",X"D",
+		X"A",X"2",X"2",X"2",X"2",X"3",X"3",X"4",X"5",X"A",X"2",X"3",X"3",X"4",X"5",X"A",
+		X"2",X"2",X"2",X"2",X"3",X"3",X"4",X"4",X"A",X"2",X"2",X"3",X"4",X"5",X"A",X"2",
+		X"2",X"2",X"2",X"2",X"3",X"4",X"4",X"A",X"2",X"2",X"3",X"4",X"6",X"A",X"1",X"1",
+		X"8",X"8",X"8",X"3",X"4",X"4",X"A",X"1",X"1",X"3",X"4",X"4",X"A",X"1",X"0",X"6",
+		X"D",X"0",X"3",X"4",X"4",X"A",X"1",X"1",X"A",X"4",X"5",X"A",X"1",X"7",X"7",X"6",
+		X"8",X"4",X"4",X"5",X"A",X"1",X"0",X"A",X"4",X"5",X"A",X"0",X"0",X"7",X"6",X"E",
+		X"3",X"4",X"5",X"A",X"1",X"0",X"A",X"4",X"5",X"D",X"0",X"7",X"7",X"7",X"E",X"3",
+		X"4",X"6",X"A",X"0",X"0",X"A",X"4",X"5",X"1",X"9",X"0",X"7",X"7",X"E",X"3",X"3",
+		X"F",X"A",X"0",X"0",X"A",X"4",X"5",X"3",X"C",X"C",X"7",X"7",X"E",X"3",X"3",X"D",
+		X"B",X"0",X"0",X"A",X"4",X"5",X"F",X"3",X"2",X"0",X"7",X"E",X"3",X"3",X"3",X"1",
+		X"0",X"0",X"A",X"4",X"5",X"A",X"3",X"1",X"0",X"7",X"E",X"2",X"2",X"2",X"1",X"0",
+		X"0",X"A",X"4",X"5",X"A",X"2",X"1",X"0",X"0",X"E",X"2",X"2",X"1",X"1",X"0",X"0",
+		X"A",X"4",X"5",X"A",X"1",X"1",X"0",X"0",X"C",X"2",X"2",X"1",X"1",X"0",X"7",X"B",
+		X"5",X"5",X"A",X"1",X"1",X"0",X"F",X"7",X"9",X"1",X"1",X"0",X"0",X"F",X"5",X"5",
+		X"5",X"A",X"1",X"0",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"B",X"5",X"5",X"5",
+		X"8",X"0",X"A",X"0",X"A",X"0",X"9",X"9",X"0",X"0",X"C",X"9",X"9",X"0",X"0",X"C",
+		X"9",X"9",X"0",X"0",X"C",X"9",X"9",X"0",X"0",X"8",X"8",X"E",X"D",X"E",X"9",X"5",
+		X"0",X"0",X"9",X"0",X"0",X"D",X"2",X"C",X"9",X"5",X"0",X"0",X"9",X"0",X"0",X"D",
+		X"1",X"C",X"9",X"5",X"0",X"0",X"9",X"0",X"0",X"D",X"1",X"C",X"9",X"5",X"0",X"0",
+		X"9",X"0",X"0",X"D",X"0",X"8",X"8",X"E",X"D",X"D",X"C",X"D",X"B",X"F",X"3",X"A",
+		X"0",X"8",X"0",X"0",X"A",X"0",X"A",X"0",X"C",X"0",X"F",X"2",X"1",X"2",X"9",X"0",
+		X"8",X"4",X"8",X"6",X"8",X"D",X"F",X"C",X"D",X"F",X"F",X"0",X"8",X"4",X"8",X"6",
+		X"8",X"D",X"F",X"C",X"D",X"F",X"8",X"4",X"8",X"6",X"8",X"D",X"F",X"C",X"D",X"F",
+		X"F",X"D",X"8",X"0",X"F",X"F",X"A",X"0",X"A",X"0",X"A",X"0",X"2",X"3",X"3",X"A",
+		X"0",X"8",X"C",X"8",X"C",X"8",X"B",X"A",X"2",X"8",X"B",X"A",X"0",X"B",X"B",X"1",
+		X"6",X"C",X"8",X"C",X"C",X"D",X"F",X"E",X"B",X"C",X"D",X"F",X"A",X"C",X"D",X"0",
+		X"E",X"C",X"A",X"C",X"C",X"0",X"9",X"E",X"4",X"B",X"3",X"A",X"C",X"1",X"6",X"7",
+		X"8",X"B",X"0",X"A",X"2",X"8",X"B",X"0",X"2",X"D",X"3",X"8",X"B",X"A",X"0",X"9",
+		X"6",X"9",X"6",X"C",X"C",X"1",X"F",X"2",X"D",X"3",X"4",X"B",X"F",X"E",X"A",X"0",
+		X"9",X"6",X"9",X"6",X"C",X"C",X"1",X"F",X"3",X"E",X"A",X"0",X"1",X"A",X"0",X"4",
+		X"2",X"F",X"3",X"B",X"B",X"1",X"6",X"3",X"1",X"5",X"3",X"B",X"4",X"3",X"8",X"C",
+		X"B",X"4",X"3",X"8",X"C",X"A",X"0",X"9",X"C",X"6",X"5",X"4",X"5",X"2",X"9",X"6",
+		X"5",X"2",X"C",X"C",X"1",X"D",X"2",X"8",X"6",X"0",X"4",X"8",X"4",X"9",X"4",X"D",
+		X"A",X"D",X"C",X"5",X"D",X"1",X"A",X"E",X"C",X"A",X"D",X"0",X"B",X"B",X"0",X"0",
+		X"C",X"4",X"9",X"3",X"4",X"E",X"3",X"7",X"D",X"A",X"F",X"9",X"A",X"0",X"9",X"0",
+		X"C",X"3",X"F",X"A",X"5",X"8",X"D",X"A",X"A",X"8",X"E",X"A",X"0",X"A",X"C",X"9",
+		X"A",X"9",X"9",X"B",X"C",X"3",X"9",X"A",X"C",X"C",X"1",X"F",X"A",X"0",X"4",X"C",
+		X"A",X"D",X"0",X"2",X"0",X"4",X"4",X"8",X"3",X"A",X"0",X"B",X"A",X"1",X"6",X"8",
+		X"B",X"A",X"0",X"8",X"4",X"B",X"0",X"1",X"0",X"A",X"1",X"2",X"B",X"D",X"0",X"0",
+		X"2",X"B",X"D",X"2",X"A",X"6",X"D",X"1",X"A",X"0",X"8",X"4",X"B",X"0",X"1",X"0",
+		X"B",X"A",X"2",X"6",X"0",X"1",X"D",X"0",X"A",X"1",X"2",X"B",X"D",X"0",X"0",X"2",
+		X"B",X"F",X"0",X"A",X"4",X"8",X"B",X"A",X"8",X"3",X"A",X"0",X"B",X"9",X"A",X"2",
+		X"0",X"1",X"3",X"1",X"A",X"C",X"D",X"1",X"B",X"A",X"0",X"1",X"1",X"A",X"0",X"0",
+		X"3",X"0",X"A",X"F",X"9",X"1",X"7",X"9",X"9",X"9",X"A",X"B",X"3",X"A",X"9",X"A",
+		X"2",X"9",X"3",X"B",X"2",X"4",X"8",X"2",X"3",X"C",X"B",X"C",X"C",X"F",X"D",X"0",
+		X"F",X"E",X"A",X"6",X"4",X"9",X"0",X"F",X"E",X"B",X"E",X"4",X"F",X"0",X"A",X"B",
+		X"0",X"4",X"8",X"B",X"2",X"D",X"3",X"C",X"C",X"3",X"0",X"4",X"5",X"3",X"6",X"A",
+		X"6",X"A",X"6",X"4",X"A",X"0",X"B",X"0",X"3",X"8",X"4",X"B",X"0",X"3",X"0",X"8",
+		X"D",X"F",X"9",X"B",X"6",X"0",X"0",X"0",X"A",X"0",X"B",X"A",X"2",X"F",X"9",X"A",
+		X"C",X"C",X"1",X"F",X"A",X"0",X"8",X"A",X"8",X"8",X"B",X"A",X"3",X"F",X"A",X"0",
+		X"1",X"0",X"C",X"F",X"B",X"0",X"9",X"3",X"C",X"0",X"B",X"2",X"B",X"A",X"3",X"F",
+		X"A",X"0",X"1",X"0",X"C",X"F",X"9",X"2",X"B",X"0",X"C",X"0",X"B",X"1",X"B",X"A",
+		X"3",X"0",X"B",X"A",X"0",X"1",X"1",X"B",X"C",X"D",X"0",X"A",X"2",X"9",X"C",X"B",
+		X"C",X"0",X"D",X"0",X"A",X"2",X"9",X"C",X"0",X"8",X"8",X"1",X"B",X"C",X"C",X"D",
+		X"B",X"6",X"B",X"A",X"3",X"0",X"A",X"8",X"9",X"9",X"A",X"0",X"9",X"A",X"9",X"8",
+		X"9",X"D",X"9",X"D",X"9",X"2",X"A",X"C",X"9",X"A",X"9",X"9",X"9",X"8",X"B",X"C",
+		X"3",X"9",X"A",X"2",X"1",X"3",X"6",X"A",X"0",X"2",X"6",X"3",X"2",X"9",X"3",X"C",
+		X"C",X"1",X"F",X"6",X"A",X"B",X"1",X"0",X"A",X"C",X"D",X"0",X"A",X"6",X"2",X"0",
+		X"D",X"2",X"B",X"E",X"4",X"F",X"2",X"B",X"A",X"3",X"2",X"9",X"6",X"B",X"2",X"3",
+		X"1",X"D",X"E",X"D",X"E",X"B",X"A",X"0",X"8",X"9",X"A",X"A",X"B",X"0",X"8",X"8",
+		X"B",X"2",X"6",X"3",X"9",X"6",X"4",X"D",X"3",X"A",X"B",X"2",X"1",X"D",X"F",X"B",
+		X"A",X"3",X"0",X"9",X"6",X"6",X"E",X"0",X"D",X"0",X"A",X"0",X"8",X"D",X"B",X"E",
+		X"C",X"0",X"9",X"1",X"B",X"A",X"3",X"0",X"E",X"D",X"E",X"D",X"C",X"1",X"9",X"0",
+		X"A",X"1",X"9",X"E",X"4",X"F",X"3",X"0",X"C",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"2",X"9",X"3",X"2",X"2",X"3",X"4",X"8",
+		X"3",X"A",X"0",X"8",X"B",X"8",X"0",X"8",X"D",X"A",X"0",X"8",X"C",X"2",X"0",X"1",
+		X"5",X"1",X"2",X"A",X"3",X"2",X"D",X"3",X"2",X"3",X"3",X"E",X"B",X"A",X"B",X"D",
+		X"0",X"2",X"A",X"3",X"4",X"A",X"3",X"2",X"0",X"1",X"7",X"0",X"4",X"F",X"3",X"A",
+		X"0",X"A",X"F",X"3",X"9",X"9",X"9",X"9",X"6",X"2",X"9",X"3",X"C",X"C",X"1",X"F",
+		X"A",X"0",X"8",X"C",X"8",X"0",X"8",X"4",X"2",X"0",X"1",X"1",X"F",X"2",X"0",X"1",
+		X"3",X"F",X"8",X"4",X"2",X"2",X"3",X"E",X"B",X"2",X"B",X"3",X"0",X"7",X"1",X"5",
+		X"B",X"A",X"B",X"2",X"3",X"D",X"1",X"A",X"C",X"C",X"0",X"D",X"0",X"2",X"8",X"3");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_L6.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_L6.vhd
new file mode 100644
index 00000000..e9c22c83
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_L6.vhd	
@@ -0,0 +1,86 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_L6 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(9 downto 0);
+	data : out std_logic_vector(3 downto 0)
+);
+end entity;
+
+architecture prom of ROM_L6 is
+	type rom is array(0 to  1023) of std_logic_vector(3 downto 0);
+	signal rom_data: rom := (
+		X"0",X"0",X"0",X"0",X"0",X"1",X"1",X"D",X"D",X"D",X"1",X"1",X"D",X"D",X"D",X"1",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"1",X"D",X"D",X"D",X"1",X"1",X"6",X"6",X"6",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"3",X"3",X"3",X"F",X"D",X"5",X"1",X"1",X"6",X"6",X"6",
+		X"0",X"0",X"0",X"0",X"3",X"7",X"6",X"6",X"2",X"F",X"D",X"4",X"0",X"1",X"3",X"1",
+		X"0",X"0",X"0",X"0",X"6",X"F",X"C",X"4",X"6",X"3",X"D",X"E",X"4",X"0",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"7",X"F",X"C",X"6",X"3",X"D",X"E",X"4",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"7",X"F",X"C",X"6",X"3",X"0",X"7",X"3",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"1",X"0",X"7",X"F",X"C",X"E",X"7",X"0",X"3",X"3",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"1",X"0",X"7",X"C",X"8",X"C",X"7",X"0",X"1",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"3",X"3",X"0",X"7",X"E",X"C",X"F",X"7",X"0",X"1",X"1",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"3",X"7",X"0",X"3",X"6",X"C",X"F",X"7",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"4",X"E",X"D",X"3",X"6",X"C",X"F",X"7",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"0",X"4",X"E",X"D",X"3",X"6",X"4",X"C",X"F",X"6",
+		X"0",X"0",X"0",X"0",X"1",X"3",X"1",X"0",X"4",X"D",X"F",X"2",X"6",X"6",X"7",X"3",
+		X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"1",X"1",X"5",X"D",X"F",X"3",X"3",X"3",X"1",
+		X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"1",X"1",X"D",X"D",X"D",X"1",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"D",X"D",X"D",X"1",X"1",X"D",X"D",X"D",X"1",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"D",X"D",X"D",X"1",X"0",X"6",X"6",X"6",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"1",X"D",X"F",X"6",X"0",X"0",X"3",X"3",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"3",X"6",X"3",X"D",X"F",X"4",X"0",X"0",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"1",X"3",X"6",X"3",X"D",X"E",X"4",X"0",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"3",X"6",X"C",X"E",X"7",X"D",X"E",X"4",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"1",X"0",X"7",X"5",X"C",X"8",X"F",X"1",X"E",X"E",X"0",
+		X"0",X"0",X"0",X"0",X"3",X"3",X"0",X"7",X"D",X"9",X"9",X"F",X"0",X"7",X"7",X"0",
+		X"0",X"0",X"0",X"0",X"7",X"7",X"0",X"F",X"9",X"9",X"9",X"F",X"0",X"7",X"7",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"7",X"7",X"0",X"F",X"9",X"9",X"D",X"7",X"0",X"3",X"3",
+		X"0",X"0",X"0",X"0",X"0",X"E",X"E",X"1",X"F",X"8",X"C",X"5",X"7",X"0",X"1",X"1",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"4",X"E",X"D",X"7",X"E",X"C",X"6",X"3",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"0",X"4",X"E",X"D",X"3",X"6",X"3",X"1",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"0",X"0",X"4",X"F",X"D",X"3",X"6",X"3",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"3",X"3",X"0",X"0",X"6",X"F",X"D",X"1",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"0",X"1",X"D",X"D",X"D",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"1",X"D",X"D",X"D",X"1",X"1",X"D",X"D",X"D",X"1",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"1",X"D",X"D",X"D",X"1",X"1",X"6",X"6",X"6",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"3",X"3",X"3",X"F",X"D",X"5",X"1",X"1",X"6",X"6",X"6",
+		X"0",X"0",X"0",X"0",X"3",X"7",X"7",X"7",X"3",X"F",X"D",X"4",X"0",X"1",X"3",X"1",
+		X"0",X"0",X"0",X"0",X"6",X"F",X"F",X"7",X"7",X"3",X"D",X"E",X"4",X"0",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"7",X"F",X"F",X"7",X"3",X"D",X"E",X"4",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"7",X"F",X"F",X"7",X"3",X"0",X"7",X"3",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"1",X"0",X"7",X"F",X"F",X"F",X"7",X"0",X"3",X"3",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"1",X"0",X"7",X"F",X"F",X"F",X"7",X"0",X"1",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"3",X"3",X"0",X"7",X"F",X"F",X"F",X"7",X"0",X"1",X"1",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"3",X"7",X"0",X"3",X"7",X"F",X"F",X"7",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"4",X"E",X"D",X"3",X"7",X"F",X"F",X"7",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"0",X"4",X"E",X"D",X"3",X"7",X"7",X"F",X"F",X"6",
+		X"0",X"0",X"0",X"0",X"1",X"3",X"1",X"0",X"4",X"D",X"F",X"3",X"7",X"7",X"7",X"3",
+		X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"1",X"1",X"5",X"D",X"F",X"3",X"3",X"3",X"1",
+		X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"1",X"1",X"D",X"D",X"D",X"1",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"D",X"D",X"D",X"1",X"1",X"D",X"D",X"D",X"1",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"D",X"D",X"D",X"1",X"0",X"6",X"6",X"6",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"1",X"D",X"F",X"6",X"0",X"0",X"3",X"3",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"3",X"7",X"3",X"D",X"F",X"4",X"0",X"0",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"1",X"3",X"7",X"3",X"D",X"E",X"4",X"0",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"3",X"7",X"F",X"F",X"7",X"D",X"E",X"4",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"1",X"0",X"7",X"7",X"F",X"F",X"F",X"1",X"E",X"E",X"0",
+		X"0",X"0",X"0",X"0",X"3",X"3",X"0",X"7",X"F",X"F",X"F",X"F",X"0",X"7",X"7",X"0",
+		X"0",X"0",X"0",X"0",X"7",X"7",X"0",X"F",X"F",X"F",X"F",X"F",X"0",X"7",X"7",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"7",X"7",X"0",X"F",X"F",X"F",X"F",X"7",X"0",X"3",X"3",
+		X"0",X"0",X"0",X"0",X"0",X"E",X"E",X"1",X"F",X"F",X"F",X"7",X"7",X"0",X"1",X"1",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"4",X"E",X"D",X"7",X"F",X"F",X"7",X"3",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"0",X"4",X"E",X"D",X"3",X"7",X"3",X"1",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"0",X"0",X"4",X"F",X"D",X"3",X"7",X"3",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"1",X"3",X"3",X"0",X"0",X"6",X"F",X"D",X"1",X"1",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"0",X"1",X"D",X"D",X"D",X"1",X"0");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_M6.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_M6.vhd
new file mode 100644
index 00000000..d71b4fb8
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_M6.vhd	
@@ -0,0 +1,86 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_M6 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(9 downto 0);
+	data : out std_logic_vector(3 downto 0)
+);
+end entity;
+
+architecture prom of ROM_M6 is
+	type rom is array(0 to  1023) of std_logic_vector(3 downto 0);
+	signal rom_data: rom := (
+		X"0",X"0",X"0",X"0",X"E",X"F",X"B",X"1",X"1",X"1",X"5",X"F",X"F",X"1",X"1",X"F",
+		X"0",X"0",X"0",X"0",X"E",X"F",X"B",X"9",X"1",X"1",X"5",X"F",X"F",X"8",X"9",X"F",
+		X"0",X"0",X"0",X"0",X"8",X"C",X"6",X"2",X"3",X"1",X"7",X"F",X"9",X"8",X"B",X"F",
+		X"0",X"0",X"0",X"0",X"3",X"B",X"D",X"6",X"3",X"1",X"B",X"E",X"C",X"6",X"F",X"B",
+		X"0",X"0",X"0",X"0",X"3",X"B",X"D",X"6",X"3",X"7",X"E",X"C",X"6",X"B",X"D",X"C",
+		X"0",X"0",X"0",X"0",X"6",X"7",X"C",X"6",X"3",X"1",X"B",X"E",X"7",X"5",X"E",X"6",
+		X"0",X"0",X"0",X"0",X"C",X"E",X"8",X"F",X"1",X"3",X"B",X"F",X"1",X"3",X"3",X"1",
+		X"0",X"0",X"0",X"0",X"C",X"C",X"0",X"F",X"1",X"3",X"1",X"F",X"3",X"8",X"9",X"1",
+		X"0",X"0",X"0",X"0",X"C",X"C",X"0",X"F",X"3",X"7",X"3",X"F",X"0",X"C",X"C",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"9",X"8",X"3",X"F",X"1",X"3",X"1",X"F",X"0",X"C",X"C",
+		X"0",X"0",X"0",X"0",X"1",X"3",X"3",X"1",X"F",X"B",X"3",X"1",X"F",X"8",X"E",X"C",
+		X"0",X"0",X"0",X"0",X"6",X"E",X"5",X"7",X"E",X"B",X"1",X"3",X"6",X"C",X"7",X"6",
+		X"0",X"0",X"0",X"0",X"C",X"D",X"B",X"6",X"C",X"E",X"7",X"3",X"6",X"D",X"B",X"3",
+		X"0",X"0",X"0",X"0",X"B",X"F",X"6",X"C",X"E",X"B",X"1",X"3",X"6",X"D",X"B",X"3",
+		X"0",X"0",X"0",X"0",X"E",X"B",X"8",X"9",X"F",X"7",X"1",X"3",X"2",X"6",X"C",X"8",
+		X"0",X"0",X"0",X"0",X"F",X"9",X"8",X"F",X"F",X"5",X"1",X"1",X"9",X"B",X"F",X"E",
+		X"0",X"0",X"0",X"0",X"F",X"1",X"1",X"F",X"F",X"5",X"1",X"1",X"1",X"B",X"F",X"E",
+		X"0",X"0",X"0",X"0",X"F",X"9",X"1",X"F",X"F",X"A",X"8",X"8",X"9",X"D",X"F",X"7",
+		X"0",X"0",X"0",X"0",X"7",X"D",X"1",X"9",X"F",X"E",X"8",X"C",X"4",X"6",X"3",X"1",
+		X"0",X"0",X"0",X"0",X"D",X"F",X"6",X"3",X"7",X"D",X"8",X"C",X"6",X"B",X"D",X"C",
+		X"0",X"0",X"0",X"0",X"3",X"B",X"D",X"6",X"3",X"7",X"E",X"C",X"6",X"B",X"D",X"C",
+		X"0",X"0",X"0",X"0",X"6",X"7",X"A",X"E",X"7",X"D",X"8",X"C",X"6",X"3",X"E",X"6",
+		X"0",X"0",X"0",X"0",X"8",X"C",X"C",X"8",X"F",X"D",X"C",X"8",X"F",X"1",X"7",X"3",
+		X"0",X"0",X"0",X"0",X"8",X"9",X"1",X"C",X"F",X"8",X"C",X"8",X"F",X"0",X"3",X"3",
+		X"0",X"0",X"0",X"0",X"3",X"3",X"0",X"F",X"C",X"E",X"C",X"F",X"0",X"3",X"3",X"0",
+		X"0",X"0",X"0",X"0",X"3",X"3",X"0",X"F",X"8",X"C",X"8",X"F",X"C",X"1",X"9",X"8",
+		X"0",X"0",X"0",X"0",X"3",X"7",X"1",X"F",X"8",X"C",X"D",X"F",X"8",X"C",X"C",X"8",
+		X"0",X"0",X"0",X"0",X"6",X"E",X"3",X"6",X"C",X"8",X"D",X"7",X"E",X"A",X"7",X"6",
+		X"0",X"0",X"0",X"0",X"C",X"D",X"B",X"6",X"C",X"E",X"7",X"3",X"6",X"D",X"B",X"3",
+		X"0",X"0",X"0",X"0",X"C",X"D",X"B",X"6",X"C",X"8",X"D",X"7",X"3",X"6",X"F",X"D",
+		X"0",X"0",X"0",X"0",X"1",X"3",X"6",X"4",X"C",X"8",X"E",X"F",X"9",X"1",X"D",X"F",
+		X"0",X"0",X"0",X"0",X"7",X"F",X"D",X"9",X"8",X"8",X"A",X"F",X"F",X"1",X"9",X"F",
+		X"0",X"0",X"0",X"0",X"E",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",
+		X"0",X"0",X"0",X"0",X"E",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",
+		X"0",X"0",X"0",X"0",X"8",X"C",X"E",X"E",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",
+		X"0",X"0",X"0",X"0",X"3",X"B",X"D",X"E",X"F",X"F",X"F",X"F",X"F",X"7",X"F",X"B",
+		X"0",X"0",X"0",X"0",X"3",X"B",X"D",X"E",X"F",X"F",X"F",X"F",X"7",X"B",X"D",X"C",
+		X"0",X"0",X"0",X"0",X"6",X"7",X"C",X"E",X"F",X"F",X"F",X"F",X"7",X"5",X"E",X"6",
+		X"0",X"0",X"0",X"0",X"C",X"E",X"8",X"F",X"F",X"F",X"F",X"F",X"1",X"3",X"3",X"1",
+		X"0",X"0",X"0",X"0",X"C",X"C",X"0",X"F",X"F",X"F",X"F",X"F",X"3",X"8",X"9",X"1",
+		X"0",X"0",X"0",X"0",X"C",X"C",X"0",X"F",X"F",X"F",X"F",X"F",X"0",X"C",X"C",X"0",
+		X"0",X"0",X"0",X"0",X"1",X"9",X"8",X"3",X"F",X"F",X"F",X"F",X"F",X"0",X"C",X"C",
+		X"0",X"0",X"0",X"0",X"1",X"3",X"3",X"1",X"F",X"F",X"F",X"F",X"F",X"8",X"E",X"C",
+		X"0",X"0",X"0",X"0",X"6",X"E",X"5",X"7",X"F",X"F",X"F",X"F",X"E",X"C",X"7",X"6",
+		X"0",X"0",X"0",X"0",X"C",X"D",X"B",X"7",X"F",X"F",X"F",X"F",X"E",X"D",X"B",X"3",
+		X"0",X"0",X"0",X"0",X"B",X"F",X"7",X"F",X"F",X"F",X"F",X"F",X"E",X"D",X"B",X"3",
+		X"0",X"0",X"0",X"0",X"E",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"E",X"E",X"C",X"8",
+		X"0",X"0",X"0",X"0",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"E",
+		X"0",X"0",X"0",X"0",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"E",
+		X"0",X"0",X"0",X"0",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"7",
+		X"0",X"0",X"0",X"0",X"7",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"7",X"7",X"3",X"1",
+		X"0",X"0",X"0",X"0",X"D",X"F",X"E",X"F",X"F",X"F",X"F",X"F",X"7",X"B",X"D",X"C",
+		X"0",X"0",X"0",X"0",X"3",X"B",X"D",X"E",X"F",X"F",X"F",X"F",X"7",X"B",X"D",X"C",
+		X"0",X"0",X"0",X"0",X"6",X"7",X"A",X"E",X"F",X"F",X"F",X"F",X"7",X"3",X"E",X"6",
+		X"0",X"0",X"0",X"0",X"8",X"C",X"C",X"8",X"F",X"F",X"F",X"F",X"F",X"1",X"7",X"3",
+		X"0",X"0",X"0",X"0",X"8",X"9",X"1",X"C",X"F",X"F",X"F",X"F",X"F",X"0",X"3",X"3",
+		X"0",X"0",X"0",X"0",X"3",X"3",X"0",X"F",X"F",X"F",X"F",X"F",X"0",X"3",X"3",X"0",
+		X"0",X"0",X"0",X"0",X"3",X"3",X"0",X"F",X"F",X"F",X"F",X"F",X"C",X"1",X"9",X"8",
+		X"0",X"0",X"0",X"0",X"3",X"7",X"1",X"F",X"F",X"F",X"F",X"F",X"8",X"C",X"C",X"8",
+		X"0",X"0",X"0",X"0",X"6",X"E",X"3",X"7",X"F",X"F",X"F",X"F",X"E",X"A",X"7",X"6",
+		X"0",X"0",X"0",X"0",X"C",X"D",X"B",X"7",X"F",X"F",X"F",X"F",X"E",X"D",X"B",X"3",
+		X"0",X"0",X"0",X"0",X"C",X"D",X"B",X"7",X"F",X"F",X"F",X"F",X"F",X"E",X"F",X"D",
+		X"0",X"0",X"0",X"0",X"1",X"3",X"7",X"7",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",
+		X"0",X"0",X"0",X"0",X"7",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F",X"F");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_N1_Low.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_N1_Low.vhd
new file mode 100644
index 00000000..23cccbc9
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_N1_Low.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_N1_Low is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(3 downto 0)
+);
+end entity;
+
+architecture prom of ROM_N1_Low is
+	type rom is array(0 to  2047) of std_logic_vector(3 downto 0);
+	signal rom_data: rom := (
+		X"4",X"4",X"E",X"1",X"1",X"1",X"C",X"C",X"C",X"5",X"5",X"E",X"1",X"1",X"F",X"4",
+		X"4",X"E",X"1",X"1",X"F",X"4",X"4",X"5",X"6",X"6",X"E",X"1",X"0",X"E",X"4",X"4",
+		X"E",X"1",X"1",X"A",X"4",X"4",X"5",X"6",X"6",X"E",X"1",X"0",X"E",X"4",X"4",X"E",
+		X"1",X"0",X"A",X"4",X"4",X"5",X"6",X"6",X"E",X"1",X"0",X"E",X"4",X"4",X"E",X"1",
+		X"0",X"A",X"3",X"4",X"5",X"6",X"6",X"C",X"0",X"0",X"E",X"4",X"4",X"E",X"0",X"0",
+		X"A",X"3",X"4",X"6",X"6",X"F",X"3",X"0",X"0",X"E",X"4",X"4",X"E",X"0",X"0",X"A",
+		X"3",X"3",X"C",X"C",X"C",X"C",X"0",X"0",X"E",X"4",X"4",X"E",X"0",X"0",X"A",X"2",
+		X"2",X"2",X"2",X"2",X"2",X"0",X"0",X"E",X"4",X"4",X"E",X"0",X"0",X"A",X"2",X"2",
+		X"2",X"2",X"2",X"1",X"0",X"0",X"E",X"4",X"4",X"E",X"0",X"0",X"A",X"2",X"2",X"2",
+		X"2",X"2",X"1",X"0",X"0",X"E",X"4",X"4",X"E",X"0",X"0",X"A",X"2",X"2",X"2",X"2",
+		X"1",X"1",X"0",X"0",X"B",X"5",X"4",X"E",X"0",X"0",X"D",X"2",X"2",X"2",X"1",X"1",
+		X"1",X"0",X"F",X"5",X"5",X"4",X"E",X"0",X"0",X"7",X"C",X"C",X"C",X"C",X"C",X"C",
+		X"C",X"B",X"5",X"5",X"4",X"E",X"3",X"3",X"8",X"C",X"C",X"4",X"4",X"4",X"4",X"4",
+		X"8",X"8",X"4",X"4",X"5",X"3",X"F",X"3",X"3",X"3",X"C",X"4",X"4",X"4",X"C",X"3",
+		X"3",X"C",X"5",X"5",X"3",X"B",X"3",X"3",X"3",X"3",X"9",X"4",X"F",X"2",X"2",X"3",
+		X"4",X"9",X"5",X"2",X"2",X"2",X"3",X"3",X"3",X"D",X"4",X"B",X"2",X"2",X"3",X"3",
+		X"D",X"5",X"E",X"2",X"2",X"3",X"3",X"3",X"3",X"C",X"2",X"2",X"2",X"3",X"4",X"4",
+		X"6",X"A",X"1",X"1",X"2",X"3",X"2",X"2",X"2",X"2",X"1",X"2",X"3",X"4",X"4",X"6",
+		X"A",X"1",X"1",X"2",X"2",X"2",X"2",X"2",X"1",X"F",X"C",X"3",X"4",X"4",X"A",X"1",
+		X"1",X"1",X"F",X"2",X"2",X"2",X"1",X"1",X"B",X"1",X"2",X"4",X"4",X"A",X"1",X"1",
+		X"1",X"B",X"9",X"2",X"1",X"1",X"F",X"7",X"2",X"A",X"4",X"4",X"A",X"1",X"1",X"F",
+		X"7",X"D",X"2",X"1",X"1",X"B",X"7",X"2",X"E",X"4",X"4",X"E",X"1",X"0",X"E",X"6",
+		X"1",X"9",X"1",X"8",X"7",X"7",X"2",X"E",X"4",X"4",X"E",X"1",X"0",X"E",X"6",X"0",
+		X"D",X"8",X"0",X"7",X"7",X"2",X"A",X"5",X"4",X"E",X"0",X"0",X"E",X"6",X"0",X"1",
+		X"0",X"0",X"0",X"4",X"4",X"4",X"5",X"5",X"E",X"0",X"0",X"7",X"5",X"0",X"0",X"0",
+		X"0",X"0",X"4",X"F",X"5",X"5",X"5",X"E",X"0",X"0",X"7",X"5",X"4",X"4",X"4",X"4",
+		X"4",X"4",X"B",X"5",X"5",X"5",X"E",X"0",X"0",X"7",X"A",X"4",X"4",X"4",X"4",X"4",
+		X"C",X"5",X"5",X"5",X"5",X"E",X"0",X"0",X"7",X"D",X"4",X"4",X"4",X"4",X"C",X"5",
+		X"5",X"5",X"5",X"5",X"E",X"0",X"7",X"7",X"7",X"8",X"8",X"8",X"C",X"5",X"5",X"5",
+		X"5",X"5",X"5",X"E",X"3",X"2",X"8",X"C",X"C",X"C",X"C",X"5",X"5",X"F",X"C",X"C",
+		X"C",X"9",X"4",X"2",X"F",X"3",X"4",X"4",X"4",X"5",X"9",X"3",X"B",X"3",X"3",X"4",
+		X"D",X"5",X"3",X"B",X"2",X"2",X"2",X"3",X"5",X"D",X"F",X"3",X"2",X"2",X"3",X"5",
+		X"9",X"F",X"3",X"1",X"2",X"2",X"3",X"4",X"5",X"B",X"1",X"2",X"2",X"4",X"5",X"E",
+		X"A",X"2",X"1",X"2",X"2",X"3",X"4",X"5",X"2",X"1",X"2",X"2",X"4",X"4",X"E",X"2",
+		X"1",X"1",X"2",X"2",X"3",X"4",X"5",X"2",X"1",X"1",X"1",X"4",X"4",X"E",X"2",X"1",
+		X"4",X"4",X"8",X"2",X"4",X"5",X"2",X"0",X"1",X"E",X"4",X"4",X"E",X"1",X"1",X"4",
+		X"5",X"0",X"A",X"5",X"5",X"2",X"0",X"0",X"E",X"4",X"5",X"E",X"1",X"0",X"2",X"4",
+		X"9",X"B",X"5",X"6",X"1",X"1",X"7",X"E",X"4",X"4",X"E",X"0",X"0",X"F",X"3",X"D",
+		X"5",X"5",X"6",X"2",X"1",X"7",X"E",X"4",X"4",X"E",X"0",X"0",X"E",X"3",X"4",X"4",
+		X"5",X"F",X"1",X"0",X"7",X"E",X"4",X"4",X"E",X"0",X"0",X"E",X"3",X"3",X"4",X"5",
+		X"B",X"1",X"0",X"0",X"E",X"4",X"5",X"E",X"0",X"0",X"E",X"2",X"3",X"3",X"4",X"1",
+		X"0",X"1",X"0",X"E",X"4",X"4",X"E",X"1",X"0",X"D",X"1",X"3",X"2",X"2",X"1",X"2",
+		X"1",X"0",X"A",X"4",X"4",X"E",X"0",X"0",X"7",X"9",X"2",X"2",X"1",X"2",X"2",X"1",
+		X"7",X"4",X"5",X"4",X"E",X"0",X"0",X"7",X"D",X"1",X"1",X"1",X"1",X"1",X"1",X"F",
+		X"5",X"5",X"4",X"E",X"0",X"0",X"7",X"7",X"9",X"0",X"0",X"0",X"0",X"7",X"B",X"5",
+		X"6",X"4",X"E",X"0",X"0",X"7",X"7",X"D",X"C",X"C",X"C",X"C",X"C",X"5",X"5",X"5",
+		X"4",X"E",X"F",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"5",X"F",X"C",X"C",X"C",X"C",
+		X"5",X"B",X"3",X"3",X"3",X"3",X"3",X"4",X"5",X"9",X"B",X"3",X"3",X"4",X"5",X"9",
+		X"3",X"2",X"2",X"2",X"3",X"3",X"3",X"5",X"D",X"3",X"2",X"3",X"4",X"4",X"E",X"2",
+		X"2",X"2",X"2",X"2",X"3",X"4",X"4",X"5",X"2",X"2",X"3",X"4",X"4",X"E",X"2",X"2",
+		X"2",X"2",X"2",X"3",X"4",X"4",X"5",X"2",X"2",X"2",X"4",X"4",X"E",X"1",X"1",X"1",
+		X"8",X"8",X"9",X"4",X"4",X"5",X"1",X"1",X"1",X"4",X"4",X"E",X"1",X"1",X"7",X"5",
+		X"9",X"E",X"4",X"4",X"5",X"1",X"1",X"7",X"4",X"4",X"E",X"1",X"0",X"7",X"6",X"D",
+		X"B",X"4",X"4",X"5",X"1",X"1",X"7",X"4",X"4",X"E",X"1",X"0",X"7",X"7",X"5",X"3",
+		X"4",X"5",X"6",X"1",X"0",X"0",X"3",X"4",X"E",X"9",X"0",X"7",X"7",X"6",X"3",X"3",
+		X"5",X"F",X"1",X"0",X"7",X"3",X"4",X"E",X"D",X"0",X"7",X"7",X"7",X"3",X"3",X"4",
+		X"B",X"1",X"0",X"0",X"4",X"4",X"E",X"F",X"C",X"0",X"7",X"7",X"3",X"3",X"3",X"8",
+		X"1",X"0",X"0",X"4",X"4",X"E",X"B",X"3",X"1",X"7",X"7",X"2",X"3",X"3",X"3",X"0",
+		X"0",X"0",X"4",X"4",X"E",X"3",X"2",X"1",X"0",X"7",X"2",X"2",X"2",X"1",X"0",X"0",
+		X"0",X"4",X"4",X"E",X"2",X"1",X"1",X"0",X"7",X"2",X"2",X"2",X"1",X"0",X"0",X"7",
+		X"4",X"4",X"E",X"2",X"1",X"1",X"0",X"F",X"9",X"2",X"1",X"1",X"0",X"0",X"F",X"5",
+		X"5",X"E",X"1",X"1",X"0",X"0",X"B",X"D",X"0",X"1",X"1",X"0",X"0",X"B",X"5",X"5",
+		X"E",X"1",X"0",X"7",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"C",X"5",X"5",X"5",X"E",
+		X"5",X"0",X"0",X"0",X"2",X"0",X"8",X"D",X"0",X"8",X"8",X"8",X"D",X"0",X"9",X"8",
+		X"8",X"D",X"0",X"A",X"8",X"8",X"D",X"0",X"B",X"8",X"8",X"8",X"0",X"8",X"8",X"D",
+		X"0",X"8",X"D",X"0",X"8",X"0",X"8",X"8",X"8",X"D",X"0",X"9",X"D",X"0",X"9",X"0",
+		X"E",X"8",X"8",X"D",X"0",X"A",X"D",X"0",X"A",X"0",X"4",X"8",X"8",X"D",X"0",X"B",
+		X"D",X"0",X"B",X"0",X"A",X"8",X"8",X"8",X"0",X"4",X"8",X"0",X"7",X"0",X"7",X"2",
+		X"1",X"E",X"0",X"0",X"2",X"0",X"0",X"0",X"9",X"0",X"0",X"6",X"8",X"A",X"0",X"C",
+		X"6",X"2",X"5",X"8",X"8",X"0",X"9",X"A",X"0",X"6",X"0",X"A",X"6",X"2",X"5",X"9",
+		X"8",X"0",X"D",X"A",X"0",X"A",X"4",X"2",X"5",X"8",X"8",X"0",X"B",X"A",X"0",X"8",
+		X"0",X"2",X"5",X"0",X"0",X"E",X"0",X"1",X"2",X"6",X"9",X"0",X"0",X"6",X"B",X"0",
+		X"0",X"4",X"2",X"4",X"3",X"4",X"C",X"9",X"8",X"5",X"D",X"2",X"8",X"1",X"C",X"8",
+		X"5",X"2",X"5",X"2",X"8",X"0",X"6",X"6",X"D",X"A",X"0",X"1",X"5",X"2",X"0",X"B",
+		X"6",X"3",X"5",X"3",X"9",X"3",X"0",X"3",X"C",X"8",X"4",X"5",X"3",X"8",X"9",X"1",
+		X"D",X"5",X"9",X"9",X"0",X"D",X"4",X"9",X"0",X"A",X"4",X"5",X"C",X"2",X"6",X"5",
+		X"8",X"5",X"0",X"A",X"A",X"0",X"8",X"0",X"A",X"4",X"5",X"C",X"0",X"F",X"2",X"6",
+		X"5",X"1",X"5",X"9",X"A",X"A",X"0",X"8",X"0",X"D",X"D",X"0",X"8",X"2",X"6",X"8",
+		X"0",X"4",X"5",X"5",X"1",X"8",X"9",X"1",X"D",X"0",X"E",X"C",X"8",X"E",X"4",X"0",
+		X"C",X"9",X"E",X"4",X"1",X"0",X"0",X"1",X"0",X"8",X"5",X"0",X"5",X"0",X"5",X"0",
+		X"5",X"1",X"A",X"A",X"0",X"9",X"9",X"0",X"0",X"0",X"8",X"A",X"8",X"8",X"8",X"8",
+		X"5",X"F",X"9",X"5",X"0",X"1",X"5",X"7",X"9",X"A",X"0",X"B",X"A",X"D",X"6",X"1",
+		X"9",X"0",X"0",X"5",X"C",X"E",X"5",X"8",X"8",X"2",X"F",X"A",X"9",X"0",X"5",X"0",
+		X"A",X"0",X"B",X"9",X"5",X"5",X"F",X"9",X"A",X"5",X"7",X"2",X"6",X"9",X"0",X"5",
+		X"8",X"5",X"9",X"D",X"D",X"D",X"5",X"9",X"A",X"A",X"0",X"1",X"D",X"0",X"0",X"9",
+		X"A",X"0",X"3",X"0",X"0",X"0",X"C",X"8",X"7",X"2",X"6",X"5",X"0",X"0",X"1",X"5",
+		X"A",X"9",X"B",X"5",X"0",X"5",X"0",X"0",X"F",X"9",X"0",X"4",X"A",X"0",X"5",X"A",
+		X"4",X"A",X"0",X"B",X"9",X"0",X"0",X"D",X"9",X"4",X"5",X"0",X"5",X"0",X"0",X"8",
+		X"5",X"0",X"9",X"0",X"9",X"0",X"0",X"D",X"9",X"0",X"4",X"A",X"0",X"5",X"A",X"4",
+		X"A",X"0",X"C",X"9",X"0",X"5",X"A",X"9",X"F",X"5",X"0",X"5",X"A",X"5",X"0",X"C",
+		X"0",X"0",X"0",X"C",X"5",X"6",X"0",X"8",X"5",X"0",X"A",X"0",X"3",X"0",X"5",X"A",
+		X"0",X"2",X"0",X"B",X"8",X"8",X"5",X"9",X"5",X"9",X"9",X"F",X"5",X"0",X"5",X"0",
+		X"0",X"4",X"6",X"5",X"0",X"9",X"0",X"A",X"6",X"8",X"5",X"8",X"9",X"0",X"0",X"9",
+		X"6",X"0",X"5",X"1",X"A",X"0",X"2",X"6",X"0",X"5",X"0",X"A",X"0",X"6",X"5",X"B",
+		X"9",X"0",X"5",X"B",X"0",X"6",X"6",X"A",X"A",X"0",X"3",X"C",X"B",X"5",X"8",X"8",
+		X"8",X"A",X"8",X"0",X"0",X"3",X"9",X"4",X"6",X"5",X"0",X"5",X"1",X"0",X"3",X"8",
+		X"0",X"4",X"4",X"1",X"0",X"4",X"8",X"C",X"2",X"6",X"5",X"0",X"9",X"B",X"5",X"0",
+		X"A",X"A",X"0",X"6",X"2",X"6",X"A",X"8",X"8",X"8",X"5",X"8",X"8",X"9",X"8",X"0",
+		X"0",X"6",X"9",X"8",X"0",X"6",X"0",X"1",X"9",X"9",X"0",X"D",X"5",X"9",X"8",X"9",
+		X"9",X"0",X"0",X"6",X"9",X"8",X"0",X"1",X"0",X"4",X"9",X"9",X"0",X"B",X"5",X"0",
+		X"0",X"5",X"9",X"0",X"0",X"0",X"2",X"5",X"7",X"0",X"4",X"9",X"0",X"5",X"7",X"9",
+		X"7",X"0",X"0",X"5",X"9",X"0",X"9",X"7",X"0",X"8",X"8",X"0",X"D",X"A",X"A",X"0",
+		X"5",X"0",X"4",X"0",X"0",X"4",X"9",X"0",X"5",X"1",X"9",X"0",X"5",X"1",X"5",X"0",
+		X"5",X"5",X"5",X"6",X"5",X"0",X"9",X"0",X"5",X"8",X"5",X"9",X"5",X"1",X"D",X"D",
+		X"D",X"5",X"9",X"0",X"B",X"D",X"0",X"2",X"6",X"0",X"2",X"6",X"0",X"F",X"C",X"A",
+		X"A",X"0",X"6",X"0",X"5",X"B",X"0",X"A",X"5",X"6",X"0",X"6",X"5",X"1",X"9",X"2",
+		X"0",X"D",X"5",X"0",X"A",X"0",X"8",X"5",X"0",X"0",X"A",X"5",X"0",X"5",X"1",X"0",
+		X"8",X"6",X"0",X"6",X"0",X"5",X"0",X"9",X"0",X"5",X"0",X"5",X"B",X"9",X"0",X"5",
+		X"B",X"0",X"2",X"6",X"5",X"1",X"C",X"5",X"6",X"5",X"8",X"9",X"0",X"0",X"5",X"5",
+		X"0",X"0",X"2",X"5",X"0",X"0",X"0",X"6",X"0",X"4",X"9",X"0",X"5",X"D",X"5",X"0",
+		X"9",X"2",X"0",X"0",X"4",X"0",X"0",X"4",X"6",X"D",X"6",X"D",X"9",X"1",X"0",X"4",
+		X"9",X"0",X"5",X"0",X"C",X"4",X"5",X"0",X"4",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"1",X"7",X"0",X"1",X"8",X"C",X"8",
+		X"7",X"9",X"0",X"5",X"8",X"5",X"0",X"5",X"E",X"9",X"8",X"5",X"6",X"C",X"0",X"0",
+		X"0",X"A",X"0",X"E",X"B",X"0",X"3",X"A",X"0",X"8",X"D",X"6",X"8",X"5",X"8",X"0",
+		X"6",X"0",X"3",X"B",X"C",X"5",X"7",X"C",X"0",X"0",X"0",X"3",X"C",X"2",X"3",X"2",
+		X"6",X"9",X"0",X"5",X"1",X"5",X"1",X"5",X"8",X"0",X"F",X"C",X"A",X"A",X"0",X"1",
+		X"9",X"0",X"5",X"F",X"5",X"0",X"5",X"2",X"C",X"0",X"0",X"0",X"B",X"C",X"0",X"0",
+		X"0",X"B",X"5",X"4",X"0",X"E",X"D",X"6",X"8",X"4",X"B",X"0",X"4",X"0",X"D",X"0",
+		X"C",X"5",X"8",X"9",X"F",X"0",X"5",X"5",X"6",X"9",X"8",X"0",X"3",X"0",X"7",X"6");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_N6.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_N6.vhd
new file mode 100644
index 00000000..3c30ecad
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/rom/ROM_N6.vhd	
@@ -0,0 +1,86 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_N6 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(9 downto 0);
+	data : out std_logic_vector(3 downto 0)
+);
+end entity;
+
+architecture prom of ROM_N6 is
+	type rom is array(0 to  1023) of std_logic_vector(3 downto 0);
+	signal rom_data: rom := (
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"0",X"0",X"6",X"6",X"6",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"0",X"8",X"B",X"B",X"B",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"C",X"C",X"0",X"0",X"6",X"F",X"B",X"8",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"0",X"0",X"2",X"F",X"B",X"C",X"6",X"C",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"0",X"2",X"7",X"B",X"C",X"6",X"C",X"8",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"2",X"7",X"B",X"E",X"7",X"3",X"6",X"C",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"7",X"7",X"8",X"F",X"1",X"3",X"A",X"E",X"0",X"8",X"8",
+		X"0",X"0",X"0",X"0",X"0",X"E",X"E",X"0",X"F",X"9",X"9",X"B",X"E",X"0",X"E",X"E",
+		X"0",X"0",X"0",X"0",X"E",X"E",X"0",X"F",X"9",X"9",X"9",X"F",X"0",X"E",X"E",X"0",
+		X"0",X"0",X"0",X"0",X"C",X"C",X"0",X"E",X"B",X"9",X"9",X"F",X"0",X"E",X"E",X"0",
+		X"0",X"0",X"0",X"0",X"8",X"8",X"0",X"E",X"A",X"3",X"1",X"F",X"8",X"7",X"7",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"C",X"6",X"3",X"7",X"E",X"B",X"7",X"2",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"8",X"C",X"6",X"C",X"B",X"7",X"2",X"0",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"C",X"6",X"C",X"B",X"F",X"2",X"0",X"0",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"8",X"B",X"F",X"6",X"0",X"0",X"C",X"C",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"B",X"B",X"B",X"8",X"0",X"6",X"6",X"6",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"0",X"0",X"6",X"6",X"6",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"8",X"8",X"B",X"B",X"B",X"8",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"8",X"8",X"A",X"B",X"F",X"C",X"C",X"C",X"8",
+		X"0",X"0",X"0",X"0",X"8",X"C",X"8",X"0",X"2",X"B",X"F",X"4",X"6",X"6",X"E",X"C",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"0",X"2",X"7",X"B",X"C",X"6",X"2",X"3",X"F",X"6",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"2",X"7",X"B",X"C",X"6",X"3",X"F",X"E",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"C",X"E",X"0",X"C",X"6",X"3",X"F",X"E",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"C",X"C",X"0",X"E",X"7",X"3",X"F",X"E",X"0",X"8",X"8",
+		X"0",X"0",X"0",X"0",X"8",X"8",X"0",X"E",X"3",X"1",X"3",X"E",X"0",X"8",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"8",X"8",X"0",X"E",X"F",X"3",X"7",X"E",X"0",X"C",X"C",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"E",X"F",X"3",X"6",X"C",X"0",X"E",X"C",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"E",X"F",X"3",X"6",X"C",X"B",X"7",X"2",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"6",X"F",X"3",X"2",X"6",X"C",X"B",X"7",X"2",X"0",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"C",X"E",X"6",X"6",X"4",X"F",X"B",X"2",X"0",X"8",X"C",X"8",
+		X"0",X"0",X"0",X"0",X"8",X"C",X"C",X"C",X"F",X"B",X"A",X"8",X"8",X"6",X"6",X"6",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"8",X"B",X"B",X"B",X"8",X"8",X"6",X"6",X"6",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"0",X"0",X"6",X"6",X"6",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"0",X"8",X"B",X"B",X"B",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"C",X"C",X"0",X"0",X"6",X"F",X"B",X"8",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"0",X"0",X"2",X"F",X"B",X"C",X"E",X"C",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"0",X"2",X"7",X"B",X"C",X"E",X"C",X"8",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"2",X"7",X"B",X"E",X"F",X"F",X"E",X"C",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"7",X"7",X"8",X"F",X"F",X"F",X"E",X"E",X"0",X"8",X"8",
+		X"0",X"0",X"0",X"0",X"0",X"E",X"E",X"0",X"F",X"F",X"F",X"F",X"E",X"0",X"C",X"C",
+		X"0",X"0",X"0",X"0",X"E",X"E",X"0",X"F",X"F",X"F",X"F",X"F",X"0",X"E",X"E",X"0",
+		X"0",X"0",X"0",X"0",X"C",X"C",X"0",X"E",X"F",X"F",X"F",X"F",X"0",X"E",X"E",X"0",
+		X"0",X"0",X"0",X"0",X"8",X"8",X"0",X"E",X"E",X"F",X"F",X"F",X"8",X"7",X"7",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"C",X"E",X"F",X"F",X"E",X"B",X"7",X"2",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"8",X"C",X"E",X"C",X"B",X"7",X"2",X"0",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"C",X"E",X"C",X"B",X"F",X"2",X"0",X"0",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"8",X"B",X"F",X"6",X"0",X"0",X"C",X"C",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"B",X"B",X"B",X"8",X"0",X"6",X"6",X"6",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"0",X"0",X"6",X"6",X"6",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"8",X"8",X"B",X"B",X"B",X"8",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"6",X"6",X"6",X"8",X"8",X"A",X"B",X"F",X"C",X"C",X"C",X"8",
+		X"0",X"0",X"0",X"0",X"8",X"C",X"8",X"0",X"2",X"B",X"F",X"C",X"E",X"E",X"E",X"C",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"0",X"2",X"7",X"B",X"C",X"E",X"E",X"F",X"F",X"6",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"2",X"7",X"B",X"C",X"E",X"F",X"F",X"E",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"C",X"E",X"0",X"C",X"E",X"F",X"F",X"E",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"C",X"C",X"0",X"E",X"F",X"F",X"F",X"E",X"0",X"8",X"8",
+		X"0",X"0",X"0",X"0",X"8",X"8",X"0",X"E",X"F",X"F",X"F",X"E",X"0",X"8",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"8",X"8",X"0",X"E",X"F",X"F",X"F",X"E",X"0",X"C",X"C",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"0",X"E",X"F",X"F",X"E",X"C",X"0",X"E",X"C",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"0",X"E",X"F",X"F",X"E",X"C",X"B",X"7",X"2",X"0",X"0",X"0",
+		X"0",X"0",X"0",X"0",X"6",X"F",X"F",X"E",X"E",X"C",X"B",X"7",X"2",X"0",X"8",X"0",
+		X"0",X"0",X"0",X"0",X"C",X"E",X"E",X"E",X"C",X"F",X"B",X"2",X"0",X"8",X"C",X"8",
+		X"0",X"0",X"0",X"0",X"8",X"C",X"C",X"C",X"F",X"B",X"A",X"8",X"8",X"6",X"6",X"6",
+		X"0",X"0",X"0",X"0",X"0",X"8",X"8",X"B",X"B",X"B",X"8",X"8",X"6",X"6",X"6",X"0");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/screech.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/screech.vhd
new file mode 100644
index 00000000..0ca3b4ea
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/screech.vhd	
@@ -0,0 +1,73 @@
+-- Tire screech sound generator for Atari Sprint 4 
+-- This was originally created as tire screech sound for Sprint 2 - Identical circuit 
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 7414 Schmitt trigger oscillator operating at approximately
+-- 1.2kHz producing a sawtooth with the frequency modulated slightly by the pseudo-random 
+-- noise generator. This is an extension of work initially done in Verilog by Jonas Elofsson.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity screech is 
+generic(
+			constant Inc1 : integer := 24; -- These constants can be adjusted to tune the frequency and modulation
+			constant Inc2 : integer := 34;
+			constant Dec1 : integer := 23;
+			constant Dec2 : integer := 12
+			);
+port(		
+			Clk			: in  std_logic;  -- 750kHz from the horizontal line counter chain works well here
+			Noise			: in	std_logic;  -- Output from LFSR pseudo-random noise generator
+			Screech_out	: out std_logic	-- Screech output - single bit
+			);
+end screech;
+
+architecture rtl of screech is
+
+signal Screech_count	: integer range 1000 to 11000;
+signal Screech_state	: std_logic;
+
+begin
+
+Screech: process(Clk, Screech_state)
+begin
+	if rising_edge(Clk) then
+		if screech_state = '1' then -- screech_state is 1, counter is rising
+			if noise = '1' then 	-- Noise signal from LFSR, when high increases the slope of the rising ramp
+				screech_count <= screech_count + inc2;
+			else 						-- When Noise is low, decreas the slope of the ramp
+				screech_count <= screech_count + inc1; 
+			end if;
+			if screech_count > 10000 then -- Reverse the ramp direction when boundary value of 10,000 is reached
+				screech_state <= '0';
+			end if;
+		elsif screech_state = '0' then -- screech_state is now low, decrement the counter (ramp down)
+			if noise = '1' then 
+				screech_count <= screech_count - dec2; -- Slope is influenced by the Noise signal
+			else
+				screech_count <= screech_count - dec1;
+			end if;
+			if screech_count < 1000 then -- Reverse the ramp direction again when the lower boundary of 1,000 is crossed
+				screech_state <= '1';
+			end if;
+		end if;
+	end if;
+screech_out <= screech_state;
+end process;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sound.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sound.vhd
new file mode 100644
index 00000000..1215acd4
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sound.vhd	
@@ -0,0 +1,332 @@
+-- Audio for Atari Sprint 4
+-- The real hardware used analog circuitry to generate some of the sounds, may be room for improvement as
+-- I do not have a real board to compare.
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity audio is 
+port(		
+			Clk_50				: in	std_logic;
+			Clk_6					: in  std_logic;
+			Reset_n				: in	std_logic;
+			Load_n				: in	std_logic_vector(8 downto 1);
+			Skid					: in	std_logic_vector(4 downto 1);
+			Wr_CrashWord_n		: in  std_logic;
+			Attract				: in  std_logic;
+			Attract_n			: in  std_logic;
+			PRAM					: in	std_logic_vector(7 downto 0);
+			DBus_n				: in  std_logic_vector(7 downto 0);
+			HCount				: in  std_logic_vector(8 downto 0);
+			VCount				: in  std_logic_vector(7 downto 0);
+			P1_2audio			: out std_logic_vector(6 downto 0);
+			P3_4audio			: out std_logic_vector(6 downto 0)
+);
+end audio;
+
+architecture rtl of audio is
+
+signal reset						: std_logic;
+
+signal H4							: std_logic;
+signal V2							: std_logic;
+
+signal Noise						: std_logic;
+signal Noise_Shift				: std_logic_vector(15 downto 0);
+signal Shift_in  					: std_logic;
+
+signal Crash						: std_logic_vector(3 downto 0);
+signal Bang							: std_logic_vector(3 downto 0);
+
+signal Mtr1_Freq					: std_logic_vector(3 downto 0);
+signal Mtr2_Freq					: std_logic_vector(3 downto 0);
+signal Mtr3_Freq					: std_logic_vector(3 downto 0);
+signal Mtr4_Freq					: std_logic_vector(3 downto 0);
+signal Motor1_speed				: std_logic_vector(3 downto 0);
+signal Motor2_speed				: std_logic_vector(3 downto 0);
+signal Motor3_speed				: std_logic_vector(3 downto 0);
+signal Motor4_speed				: std_logic_vector(3 downto 0);
+signal Motor1_snd					: std_logic_vector(5 downto 0);
+signal Motor2_snd					: std_logic_vector(5 downto 0);
+signal Motor3_snd					: std_logic_vector(5 downto 0);
+signal Motor4_snd					: std_logic_vector(5 downto 0);
+
+
+signal Screech_snd1				: std_logic := '0';
+signal Screech_snd2				: std_logic := '0';
+signal Screech_snd3				: std_logic := '0';
+signal Screech_snd4	   		: std_logic := '0';
+signal Screech1					: std_logic_vector(3 downto 0);
+signal Screech2					: std_logic_vector(3 downto 0);
+signal Screech3					: std_logic_vector(3 downto 0);
+signal Screech4	   			: std_logic_vector(3 downto 0);
+
+signal ena_count					: std_logic_vector(10 downto 0) := (others => '0');
+signal ena_3k						: std_logic := '0';
+
+signal crash_prefilter    		: std_logic_vector(3 downto 0);
+signal crash_filter_t1    		: std_logic_vector(3 downto 0);
+signal crash_filter_t2    		: std_logic_vector(3 downto 0);
+signal crash_filter_t3    		: std_logic_vector(3 downto 0);
+signal crash_filtered     		: std_logic_vector(5 downto 0);
+
+
+begin
+
+-- HCount
+-- (0) 1H 	3 MHz
+-- (1) 2H   1.5MHz
+-- (2) 4H	750 kHz
+-- (3) 8H	375 kHz
+-- (4) 16H	187 kHz
+-- (5) 32H	93 kHz
+-- (6) 64H	46 kHz
+-- (7) 128H 23 kHz
+-- (8) 256H 12 kHz
+
+reset <= (not reset_n);
+
+H4 <= HCount(2);
+V2 <= VCount(1);
+
+-- Generate the 3kHz clock enable used by the filter
+Enable: process(clk_6)
+begin
+	if rising_edge(CLK_6) then
+		ena_count <= ena_count + "1";
+		ena_3k <= '0';
+		if (ena_count(10 downto 0) = "00000000000") then
+			ena_3k <= '1';
+		end if;
+	end if;
+end process;
+
+
+-- LFSR that generates pseudo-random noise
+Noise_gen: process(Attract_n, V2)
+begin
+	if (attract_n = '0') then
+		noise_shift <= (others => '0');
+		noise <= '0';
+	elsif rising_edge(V2) then
+		shift_in <= not(noise_shift(6) xor noise_shift(8));
+		noise_shift <= shift_in & noise_shift(15 downto 1);
+		noise <= noise_shift(0); 
+	end if;
+end process;
+
+
+-- Tire screech sound, these can be tuned slightly differently to model variations in analog sound hardware.
+Screech_gen1: entity work.screech
+generic map( -- These values can be tweaked to tune the screech sound
+		Inc1 => 24, -- Ramp increase rate when noise = 0
+		Inc2 => 33, -- Ramp increase rate when noise = 1
+		Dec1 => 29, -- Ramp decrease rate when noise = 0
+		Dec2 => 16  -- Ramp decrease rate when noise = 1
+		)
+port map(
+		Clk => H4,
+		Noise => noise,
+		Screech_out => screech_snd1
+		);
+			
+Screech_gen2: entity work.screech
+generic map( -- These values can be tweaked to tune the screech sound
+		Inc1 => 24, -- Ramp increase rate when noise = 0
+		Inc2 => 34, -- Ramp increase rate when noise = 1
+		Dec1 => 23, -- Ramp decrease rate when noise = 0
+		Dec2 => 12  -- Ramp decrease rate when noise = 1
+		)
+port map(
+		Clk => H4,
+		Noise => noise,
+		Screech_out => screech_snd2
+		);
+		
+Screech_gen3: entity work.screech
+generic map( -- These values can be tweaked to tune the screech sound
+		Inc1 => 25, -- Ramp increase rate when noise = 0
+		Inc2 => 33, -- Ramp increase rate when noise = 1
+		Dec1 => 29, -- Ramp decrease rate when noise = 0
+		Dec2 => 17  -- Ramp decrease rate when noise = 1
+		)
+port map(
+		Clk => H4,
+		Noise => noise,
+		Screech_out => screech_snd3
+		);
+		
+Screech_gen4: entity work.screech
+generic map( -- These values can be tweaked to tune the screech sound
+		Inc1 => 24, -- Ramp increase rate when noise = 0
+		Inc2 => 35, -- Ramp increase rate when noise = 1
+		Dec1 => 26, -- Ramp decrease rate when noise = 0
+		Dec2 => 14  -- Ramp decrease rate when noise = 1
+		)
+port map(
+		Clk => H4,
+		Noise => noise,
+		Screech_out => screech_snd4
+		);
+
+		
+-- Convert screech from 1 bit to 4 bits wide and enable via skid1 and skid2 signals
+Screech_ctrl: process(screech_snd1, screech_snd2, screech_snd3, screech_snd4, skid)
+begin
+	if (skid(1) and screech_snd1) = '1' then
+		screech1 <= "1111";
+	else
+		screech1 <= "0000";
+	end if;
+	
+	if (skid(2) and screech_snd2) = '1' then
+		screech2 <= "1111";
+	else
+		screech2 <= "0000";
+	end if;
+	
+	if (skid(3) and screech_snd3) = '1' then
+		screech3 <= "1111";
+	else
+		screech3 <= "0000";
+	end if;
+	
+	if (skid(4) and screech_snd4) = '1' then
+		screech4 <= "1111";
+	else
+		screech4 <= "0000";
+	end if;
+end process;
+		
+	
+Crash_sound: process(Clk_6, DBus_n, Wr_crashword_n, crash, noise)		
+begin
+	if rising_edge(clk_6) then
+		if Wr_crashword_n = '0' then
+			crash <= not DBus_n(3 downto 0);
+		end if;
+		if noise = '1' then
+			crash_prefilter <= crash;
+		else
+			crash_prefilter <= "0000";
+		end if;
+	end if;
+end process;
+
+---- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Crash_filter: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		if (ena_3k = '1') then
+			crash_filter_t1 <= crash_prefilter;
+			crash_filter_t2 <= crash_filter_t1;
+			crash_filter_t3 <= crash_filter_t2;
+		end if;
+		crash_filtered <=  ("00" & crash_filter_t1) +
+								     ('0'  & crash_filter_t2 & '0') +
+								     ("00" & crash_filter_t3);
+	end if;
+end process;	
+
+
+Motor1_latch: process(Load_n, PRAM)
+begin
+	if Load_n(1) = '0' then
+		Motor1_speed <= PRAM(3 downto 0);
+	end if;
+end process;
+
+Motor1: entity work.EngineSound 
+generic map( 
+		Freq_tune => 46 -- Tuning pot for engine sound frequency
+		)
+port map(		
+		Clk_6 => clk_6,
+	   Reset => Attract,	
+		Ena_3k => ena_3k,
+		EngineData => motor1_speed,
+		Motor => motor1_snd
+		);
+	
+
+Motor2_latch: process(Load_n, PRAM)
+begin
+	if Load_n(2) = '0' then
+		Motor2_speed <= PRAM(3 downto 0);
+	end if;
+end process;
+	
+Motor2: entity work.EngineSound 
+generic map( 
+		Freq_tune => 51 -- Tuning pot for engine sound frequency
+		)
+port map(		
+		Clk_6 => clk_6, 
+		Reset => Attract,
+		Ena_3k => ena_3k,
+		EngineData => motor2_speed,
+		Motor => motor2_snd
+		);		
+		
+Motor3_latch: process(Load_n, PRAM)
+begin
+	if Load_n(3) = '0' then
+		Motor3_speed <= PRAM(3 downto 0);
+	end if;
+end process;
+
+Motor3: entity work.EngineSound 
+generic map( 
+		Freq_tune => 50 -- Tuning pot for engine sound frequency
+		)
+port map(		
+		Clk_6 => clk_6,
+	   Reset => Attract,	
+		Ena_3k => ena_3k,
+		EngineData => motor3_speed,
+		Motor => motor3_snd
+		);
+	
+
+Motor4_latch: process(Load_n, PRAM)
+begin
+	if Load_n(4) = '0' then
+		Motor4_speed <= PRAM(3 downto 0);
+	end if;
+end process;
+	
+Motor4: entity work.EngineSound 
+generic map( 
+		Freq_tune => 47 -- Tuning pot for engine sound frequency
+		)
+port map(		
+		Clk_6 => clk_6, 
+		Reset => Attract,
+		Ena_3k => ena_3k,
+		EngineData => motor4_speed,
+		Motor => motor4_snd
+		);		
+	
+	
+-- Audio mixer
+P1_2Audio <= ('0' & motor1_snd) + ('0' & motor2_snd) + ("00" & screech1) + ("00" & screech2)+ ('0' & crash_filtered); 
+				
+P3_4Audio <= ('0' & motor3_snd) + ('0' & motor4_snd) + ("00" & screech3) + ("00" & screech4)+ ('0' & crash_filtered); 
+
+	
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sprint4.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sprint4.vhd
new file mode 100644
index 00000000..f89eded1
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sprint4.vhd	
@@ -0,0 +1,340 @@
+-- Top level file for Atari Sprint 4
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple
+-- See Ultra Tank manual for video output details. Resistor values listed here have been scaled 
+-- for 3.3V logic. 
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+
+entity sprint4 is 
+port(		
+			Clk_50_I		: in	std_logic;	-- 50MHz input clock
+			Clk_12		: in std_logic;
+			Reset_I		: in	std_logic;	-- Reset button (Active low)
+			Video1_O		: out std_logic;  -- White video output (680 Ohm)
+			Video2_O		: out std_logic;	-- Black video output (1.2k)
+			Vsync			: out std_logic;
+			Hsync			: out std_logic;
+			Hblank		: out std_logic;
+			Vblank		: out std_logic;
+			Sync_O		: out std_logic;  -- Composite sync output (1.2k)
+			Blank_O		: out std_logic;  -- Composite blank output
+			VideoR_O		: out std_logic;  -- Color monitor signals, the Electrohome G02 had digital color inputs
+			VideoG_O		: out std_logic;
+			VideoB_O		: out std_logic;
+			P1_2audio			: out std_logic_vector(6 downto 0);
+			P3_4audio			: out std_logic_vector(6 downto 0);
+			Coin1_I		: in  std_logic;  -- Coin switches (Active low)
+			Coin2_I		: in  std_logic;
+			Coin3_I		: in  std_logic;
+			Coin4_I		: in  std_logic;
+			Start1_I		: in  std_logic;  -- Start buttons
+			Start2_I		: in  std_logic;
+			Start3_I		: in  std_logic;
+			Start4_I		: in  std_logic;
+			Gas1_I		: in  std_logic;
+			Gas2_I		: in  std_logic;
+			Gas3_I		: in  std_logic;
+			Gas4_I		: in  std_logic;
+			Gear1_1_I	: in  std_logic;  -- Gear shifters, 4th gear = no other gear selected
+			Gear2_1_I	: in  std_logic;
+			Gear3_1_I	: in  std_logic;
+			Gear1_2_I	: in  std_logic;
+			Gear2_2_I	: in  std_logic;
+			Gear3_2_I	: in  std_logic;
+			Gear1_3_I	: in  std_logic;
+			Gear2_3_I	: in  std_logic;
+			Gear3_3_I	: in  std_logic;
+			Gear1_4_I	: in  std_logic;
+			Gear2_4_I	: in  std_logic;
+			Gear3_4_I	: in  std_logic;
+			Steer_1A_I	: in  std_logic;	-- Steering wheel inputs, these are quadrature encoders
+			Steer_1B_I	: in	std_logic;
+			Steer_2A_I	: in  std_logic;	
+			Steer_2B_I	: in	std_logic;
+			Steer_3A_I	: in  std_logic;	
+			Steer_3B_I	: in	std_logic;
+			Steer_4A_I	: in  std_logic;	
+			Steer_4B_I	: in	std_logic;
+			TrackSel_I	: in  std_logic;
+			Test_I		: in  std_logic;  -- Self-test switch
+			StartLamp_O	: out std_logic_vector(4 downto 1)	-- Player start button LEDs
+			);
+end sprint4;
+
+architecture rtl of sprint4 is
+
+
+signal Clk_6				: std_logic;
+signal Phi1 				: std_logic;
+signal Phi2					: std_logic;
+signal Reset_n				: std_logic;
+
+signal Hcount		   	: std_logic_vector(8 downto 0);
+signal Vcount  			: std_logic_vector(7 downto 0) := (others => '0');
+signal H256_s				: std_logic;
+signal Vblank_s			: std_logic;
+signal Vblank_n_s			: std_logic;
+signal HBlank_s			: std_logic;
+signal VSync_s				: std_logic;
+signal HSync_s				: std_logic;
+signal CompBlank			: std_logic;
+signal CompBlank_s		: std_logic;
+signal CompSync_n_s		: std_logic;
+signal WhiteVid 			: std_logic;
+signal PeachVid 			: std_logic;
+signal VioletVid 			: std_logic;
+signal GreenVid 			: std_logic;
+signal BlueVid 			: std_logic;
+
+signal DMA					: std_logic_vector(7 downto 0);
+signal DMA_n				: std_logic_vector(7 downto 0);
+signal PRAM					: std_logic_vector(7 downto 0);
+signal Load_n				: std_logic_vector(8 downto 1);
+signal Car					: std_logic_vector(4 downto 1);
+signal Car_n				: std_logic_vector(4 downto 1);
+signal Playfield_n		: std_logic;
+
+signal CPU_Din				: std_logic_vector(7 downto 0);
+signal CPU_Dout			: std_logic_vector(7 downto 0);
+signal DBus_n				: std_logic_vector(7 downto 0);
+signal BA					: std_logic_vector(15 downto 0);
+
+signal Trac_Sel_Read_n	: std_logic;
+signal Gas_Read_n			: std_logic;
+signal Coin_Read_n		: std_logic;
+signal Collision_Read_n	: std_logic;
+signal Collision_n		: std_logic_vector(4 downto 1);
+signal CollisionReset_n	: std_logic_vector(4 downto 1);
+signal Options_Read_n	: std_logic;
+signal AD_Read_n			: std_logic;
+signal Wr_DA_Latch_n 	: std_logic;
+signal Wr_CrashWord_n	: std_logic;
+signal Skid					: std_logic_vector(4 downto 1);
+signal Attract				: std_logic;
+signal Attract_n			: std_logic;	
+
+
+signal SW1					: std_logic_vector(7 downto 0);
+
+
+begin
+-- Configuration DIP switches, these can be brought out to external switches if desired
+-- See Sprint 4 manual page 6 for complete information. Active low (0 = On, 1 = Off)
+--    1 	2	3	4							Game Length		(0111 - 60sec, 1011 - 90sec, 1101 - 120sec, 1110 - 150sec, 1111 - 150sec)
+--   					5						Late Entry		(0 - Permitted, 1 - Not Permitted)
+--							6					Game Cost		(0 - 2 Coins/Player, 1 - 1 Coin/Player) 
+--								7	8			Language			(11 - English, 01 - French, 10 - Spanish, 00 - German)
+SW1 <= "00000000"; -- Config dip switches
+
+
+
+		
+		
+Vid_sync: entity work.synchronizer
+port map(
+		Clk_12 => Clk_12,
+		Clk_6 => Clk_6,
+		HCount => HCount,
+		VCount => VCount,
+		HSync => Hsync_s,
+		HBlank => HBlank_s,
+		VBlank_n_s => VBlank_n_s,
+		VBlank => VBlank_s,
+		VSync => VSync_s
+		);
+		
+Color_mixer: entity work.colormix
+port map(
+		Clk6 => Clk_6,
+		CompBlank => CompBlank,
+		WhiteVid => WhiteVid,
+		PeachVid => PeachVid,
+		VioletVid => VioletVid,
+		GreenVid => GreenVid,
+		BlueVid => BlueVid,
+		video_r => VideoR_O,
+		video_g => VideoG_O,
+		video_b => VideoB_O
+		);
+
+Background: entity work.playfield
+port map( 
+		Clk6 => Clk_6,
+		DMA => DMA,
+		PRAM => PRAM,
+		Load_n => Load_n,
+		Car => Car,
+		HCount => HCount,
+		VCount => VCount,
+		HBlank => HBlank_s,
+		VBlank => VBlank_s,
+		VBlank_n_s => VBlank_n_s,
+		HSync => Hsync_s,
+		VSync => VSync_s,
+		H256_s => H256_s,
+		Playfield_n => Playfield_n,
+		WhiteVid => WhiteVid,
+		PeachVid => PeachVid,
+		VioletVid => VioletVid,
+		GreenVid => GreenVid,
+		BlueVid => BlueVid,
+		Video1 => Video1_O,
+		Video2 => Video2_O
+		);
+			
+		
+Cars: entity work.motion
+port map(
+		CLK6 => Clk_6,
+		PHI2 => Phi2,
+		DMA_n => DMA_n,
+      PRAM => PRAM,
+		H256_s => H256_s,
+		VCount => VCount,
+		HCount => HCount,
+		Load_n => Load_n,
+		Car => Car,
+		Car_n => Car_n
+		);
+
+	
+	
+CPU: entity work.cpu_mem
+port map(
+		Clk12 => clk_12,
+		Clk6 => clk_6,
+		Reset_I => Reset_I,
+		Reset_n => reset_n,
+		VCount => VCount,
+		HCount => HCount,
+		Vblank_n_s => Vblank_n_s,
+		Test_n => Test_I,
+		DB_in => CPU_Din,
+		DBus => CPU_Dout,
+		DBus_n => DBus_n,
+		PRAM => PRAM,
+		ABus => BA,
+		Attract => Attract,
+		Attract_n => Attract_n,
+		CollReset_n => CollisionReset_n,
+		Trac_Sel_Read_n => Trac_Sel_Read_n,
+		AD_Read_n => AD_Read_n,
+		Gas_Read_n => Gas_Read_n,
+		Coin_Read_n => Coin_Read_n,
+		Options_Read_n => Options_Read_n,
+		Wr_DA_Latch_n => Wr_DA_Latch_n,
+		Wr_CrashWord_n => Wr_CrashWord_n,
+		StartLamp => StartLamp_O,
+		Skid => Skid,
+		Phi1_o => Phi1,
+		Phi2_o => Phi2,
+		DMA => DMA,
+		DMA_n => DMA_n,
+		ADR => open
+		);
+		
+		
+Input: entity work.Control_Inputs
+port map(
+		Clk6 => Clk_6,
+		DipSw => SW1, -- DIP switches
+		Trac_Sel_n => TrackSel_I,
+		Coin1 => not Coin1_I, -- Coin switches are active-high in real hardware, active-low is easier here
+		Coin2 => not Coin2_I,
+		Coin3 => not Coin3_I,
+		Coin4 => not Coin4_I,
+		Start1_n => Start1_I,
+		Start2_n => Start2_I,
+		Start3_n => Start3_I,
+		Start4_n => Start4_I,
+		Gas1_n => Gas1_I,
+		Gas2_n => Gas2_I,
+		Gas3_n => Gas3_I,
+		Gas4_n => Gas4_I,		
+		Gear1_1_n => Gear1_1_I,
+		Gear2_1_n => Gear2_1_I,
+		Gear3_1_n => Gear3_1_I,		
+		Gear1_2_n => Gear1_2_I,
+		Gear2_2_n => Gear2_2_I,
+		Gear3_2_n => Gear3_2_I,
+		Gear1_3_n => Gear1_3_I,
+		Gear2_3_n => Gear2_3_I,
+		Gear3_3_n => Gear3_3_I,
+		Gear1_4_n => Gear1_4_I,
+		Gear2_4_n => Gear2_4_I,
+		Gear3_4_n => Gear3_4_I,
+		Steering1A_n => Steer_1A_I,
+		Steering1B_n => Steer_1B_I,
+		Steering2A_n => Steer_2A_I,
+		Steering2B_n => Steer_2B_I,
+		Steering3A_n => Steer_3A_I,
+		Steering3B_n => Steer_3B_I,
+		Steering4A_n => Steer_4A_I,
+		Steering4B_n => Steer_4B_I,
+		Collision_n => Collision_n,	
+	   Gas_Read_n => Gas_Read_n,
+		AD_Read_n => AD_Read_n,
+		Coin_Read_n => Coin_Read_n,
+		Options_Read_n => Options_Read_n,
+		Trac_Sel_Read_n => Trac_Sel_Read_n,
+		Wr_DA_Latch_n => Wr_DA_Latch_n,
+		Adr => BA(2 downto 0),
+		DBus => CPU_Dout(3 downto 0),
+		Dout => CPU_Din
+	);	
+		
+		
+--PF_Comparator: entity work.collision_detect
+--port map(	
+--		Clk6 => Clk_6,
+--		Car_n	=> Car_n,
+--		Playfield_n => Playfield_n,
+--		CollisionReset_n => CollisionReset_n,
+--		Collision_n	=> Collision_n
+--		);
+
+	
+Sound: entity work.audio
+port map( 
+		Clk_50 => Clk_50_I,
+		Clk_6 => Clk_6,
+		Reset_n => Reset_n,
+		Load_n => Load_n,
+		Skid => Skid,
+		Wr_CrashWord_n => Wr_CrashWord_n,
+		Attract => Attract,
+		Attract_n => Attract_n,
+		PRAM => PRAM,
+		DBus_n => DBus_n,
+		HCount => HCount,
+		VCount => VCount,
+		P1_2audio => P1_2audio,
+		P3_4audio => P3_4audio
+		);
+
+Sync_O <= Hsync_s nor VSync_s;
+Hsync <= Hsync_s;
+VSync <= VSync_s;
+Blank_O <= HBlank_s nor VBlank_s;
+HBlank <= HBlank_s;
+VBlank <= VBlank_s;
+
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sync.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sync.vhd
new file mode 100644
index 00000000..0355c1dc
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/sync.vhd	
@@ -0,0 +1,193 @@
+-- Video synchronizer circuit for Atari Sprint 4
+-- Similar circuit used in many other Atari and Kee Games arcade games
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity synchronizer is 
+port(		
+			clk_12		: in	std_logic;
+			clk_6			: buffer	std_logic;
+			hcount		: out	std_logic_vector(8 downto 0);
+			vcount		: out	std_logic_vector(7 downto 0);
+		   hsync			: out	std_logic;
+			hblank		: out std_logic;
+			vblank_s		: out std_logic;
+			vblank_n_s	: out std_logic;
+			vblank		: out	std_logic;
+			vsync			: out std_logic;
+			vreset		: out	std_logic);
+end synchronizer;
+
+architecture rtl of synchronizer is
+
+signal h_counter		: std_logic_vector(8 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+signal v_counter		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+signal sync_bus		: std_logic_vector(3 downto 0) := (others => '0');
+signal sync_reg		: std_logic_vector(3 downto 0) := (others => '0');
+signal vblank_int		: std_logic := '0';
+signal vreset_n		: std_logic := '0';
+
+signal hblank_int		: std_logic := '0';
+signal hsync_int		: std_logic := '0';
+signal hsync_n			: std_logic := '1';
+signal hsync_reset 	: std_logic := '0';
+
+
+begin
+
+Divider: process(clk_12)
+begin
+	if rising_edge(clk_12) then
+		Clk_6 <= (not Clk_6);
+	end if;
+end process;
+		
+
+-- Horizontal counter is 8 bits long plus additional flip flop. The last 4 bit IC in the chain resets to 0010 so total count resets to 128 
+-- using only the last three count states
+H_count: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		if h_counter = "111111111" then
+			h_counter <= "010000000";
+		else
+			h_counter <= h_counter + 1;
+		end if;
+	end if;
+end process;
+
+-- Vertical counter is 8 bits, clocked by the rising edge of HSync at the end of each horizontal line
+V_count: process(hsync_int)
+begin
+	if rising_edge(Hsync_int) then
+		if vreset_n = '0' then
+			v_counter <= (others => '0');
+		else
+			v_counter <= v_counter + '1';
+		end if;
+	end if;
+end process;
+
+-- Many Atari raster games use a prom to decode vertical sync signals
+-- This could be replaced by combinatorial logic
+--P8: entity work.sync_prom
+--port map(
+--		clock => clk_12, 
+--		address => '1' & sync_reg(3) & V128 & V64 & V32 & V16 & V8 & V4 & V2,
+--		q => sync_bus
+--		);
+
+P8: entity work.PROM_SYNC
+port map(
+	clk => clk_12, 
+	addr => '1' & sync_reg(3) & V128 & V64 & V32 & V16 & V8 & V4 & V2,
+	data => sync_bus
+);
+
+-- Register fed by the sync PROM, in the original hardware this also creates the complements of these signals
+sync_register: process(hsync_n)
+begin
+	if rising_edge(hsync_n) then
+		sync_reg <= sync_bus;
+	end if;
+end process;
+
+-- Outputs of sync PROM
+vblank_s <= sync_reg(3);
+vblank_n_s <= not sync_reg(3);
+vreset <= sync_reg(2);
+vreset_n <= not sync_reg(2);
+vblank <= sync_reg(1);
+vsync <= sync_reg(0);
+
+-- A pair of D type flip-flops that generate the HBlank and HSync signals
+HBlank_gen: process(H256_n, H32)
+begin	
+	if H256_n = '0' then	
+		hblank_int <= '0';
+	else
+		if rising_edge(H32) then
+			hblank_int <= not H64;
+		end if;
+	end if;
+end process;
+
+HSync_gen: process(hblank_int, H8) 
+begin
+	if hblank_int = '0' then
+		hsync_int <= '0';
+		hsync_n <= '1';
+	else
+		if rising_edge(H8) then
+			hsync_int <= H32;
+			hsync_n <= (not H32);
+		end if;
+	end if;
+end process;
+
+-- Assign various signals
+H1 <= h_counter(0);
+H2 <= h_counter(1);
+H4 <= h_counter(2);
+H8 <= h_counter(3);
+H16 <=  h_counter(4);
+H32 <= h_counter(5);
+H64 <= h_counter(6);
+H128 <= h_counter(7);
+H256 <= h_counter(8);
+H4_n <= not H4;
+H8_n <= not H8;
+H256_n <= not H256;
+
+V1 <= v_counter(0);
+V2 <= v_counter(1);
+V4 <= v_counter(2);
+V8 <= v_counter(3);
+V16 <= v_counter(4);
+V32 <= v_counter(5);
+V64 <= v_counter(6);
+V128 <= v_counter(7);
+
+hcount <= h_counter;
+vcount <= v_counter;
+hsync <= hsync_int;
+hblank <= hblank_int;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/videomix.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/rtl/videomix.vhd
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/sprint4.qpf b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/sprint4.qpf
new file mode 100644
index 00000000..a2c3f3e7
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/sprint4.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 19:51:47  November 12, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "19:51:47  November 12, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "sprint4"
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/sprint4.qsf b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/sprint4.qsf
new file mode 100644
index 00000000..ecb6ddcc
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint4_MiST/sprint4.qsf	
@@ -0,0 +1,184 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
+# Date created = 03:11:21  June 19, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		sprint4_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16  OCTOBER 10, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Sprint4_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/sprint4.vhd
+set_global_assignment -name VHDL_FILE rtl/videomix.vhd
+set_global_assignment -name VHDL_FILE rtl/sync.vhd
+set_global_assignment -name VHDL_FILE rtl/sound.vhd
+set_global_assignment -name VHDL_FILE rtl/screech.vhd
+set_global_assignment -name VHDL_FILE rtl/playfield.vhd
+set_global_assignment -name VHDL_FILE rtl/motion.vhd
+set_global_assignment -name VHDL_FILE rtl/inputs.vhd
+set_global_assignment -name VHDL_FILE rtl/EngineSound.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd
+set_global_assignment -name VHDL_FILE rtl/colormix.vhd
+set_global_assignment -name VHDL_FILE rtl/collision.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VHDL_FILE rtl/ram1k.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/joy2quad.sv
+set_global_assignment -name VHDL_FILE rtl/gearshift.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/PROM_SYNC.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_H5.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_N6.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_M6.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_L6.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_N1_Low.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_K1_High.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_E1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/ROM_C1.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY Sprint4_MiST
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# --------------------------
+# start ENTITY(Sprint4_MiST)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(Sprint4_MiST)
+# ------------------------
+
+# --------------------------
+# start ENTITY(sprint1_mist)
+
+# end ENTITY(sprint1_mist)
+# ------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file