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Journey: change to common CTC, inputs

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This commit is contained in:
Gyorgy Szombathelyi 2020-01-14 13:09:40 +01:00
parent 63d1419eea
commit 1a9080b2b3
6 changed files with 52 additions and 573 deletions
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6
Arcade_MiST/Midway MCR 2/Journey_MiST/Journey.qsf
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@ -41,7 +41,7 @@
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
@ -184,17 +184,15 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/jo.stp
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Journey_MiST.sv
set_global_assignment -name VHDL_FILE rtl/journey.vhd
set_global_assignment -name VHDL_FILE rtl/z80ctc_top.vhd
set_global_assignment -name VHDL_FILE rtl/satans_hollow_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
set_global_assignment -name VHDL_FILE rtl/ctc_counter.vhd
set_global_assignment -name VHDL_FILE rtl/ctc_controler.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd
set_global_assignment -name VHDL_FILE rtl/rom/midssio_82s123.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name QIP_FILE ../../../common/IO/Z80CTC/z80ctc.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

107
Arcade_MiST/Midway MCR 2/Journey_MiST/rtl/Journey_MiST.sv
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@ -56,6 +56,18 @@ localparam CONF_STR = {
"V,v1.0.",`BUILD_DATE
};
wire rotate = status[2];
wire blend = status[5];
wire service = status[6];
wire [1:0] orientation = 2'b11;
wire [7:0] input_0 = ~{ service, 1'b0, m_tilt, m_fireA, m_two_players, m_one_player, m_coin2, m_coin1 };
wire [7:0] input_1 = ~{ 4'b0000, m_down, m_up, m_right, m_left };
wire [7:0] input_2 = ~{ 3'b000, m_fire2A, m_down2, m_up2, m_right2, m_left2 };
wire [7:0] input_3 = ~{ 8'b00000010 };
wire [7:0] input_4 = 8'hFF;
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_mem;
assign SDRAM_CKE = 1;
@ -81,6 +93,10 @@ wire [15:0] audio_l, audio_r;
wire hs, vs, cs;
wire blankn;
wire [2:0] g, r, b;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
wire [15:0] rom_addr;
wire [15:0] rom_do;
wire [13:0] snd_addr;
@ -188,29 +204,16 @@ journey journey(
.video_hs(hs),
.video_vs(vs),
.video_csync(cs),
.separate_audio(1'b0),
.separate_audio(1'b1),
.audio_out_l(audio_l),
.audio_out_r(audio_r),
.coin1(btn_coin),
.coin2(1'b0),
.start2(btn_two_players),
.start1(btn_one_player),
.left1(m_left1),
.right1(m_right1),
.up1(m_up1),
.down1(m_down1),
.fire1(m_fire1),
.left2(m_left2),
.right2(m_right2),
.up2(m_up2),
.down2(m_down2),
.fire2(m_fire2),
.cocktail(0),
.coin_meters(1),
.service(status[6]),
.input_0 ( input_0 ),
.input_1 ( input_1 ),
.input_2 ( input_2 ),
.input_3 ( input_3 ),
.input_4 ( input_4 ),
.cpu_rom_addr ( rom_addr ),
.cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
.snd_rom_addr ( snd_addr ),
@ -242,9 +245,9 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.VGA_B ( VGA_B ),
.VGA_VS ( vs_out ),
.VGA_HS ( hs_out ),
.rotate ( {1'b1,status[2]} ),
.rotate ( { orientation[1], rotate } ),
.ce_divider ( 1'b1 ),
.blend ( status[5] ),
.blend ( blend ),
.scandoubler_disable(1),//scandoublerD ),
.no_csync ( 1'b1 ),
.scanlines ( ),
@ -290,48 +293,24 @@ dac_r(
.dac_o(AUDIO_R)
);
// Rotated Normal
wire m_up1 = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_1[3] | joystick_1[3];
wire m_down1 = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_1[2] | joystick_1[2];
wire m_left1 = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_1[1] | joystick_1[1];
wire m_right1 = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_1[0] | joystick_1[0];
wire m_fire1 = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
wire m_up2 = m_up1;
wire m_down2 = m_down1;
wire m_left2 = m_left1;
wire m_right2 = m_right1;
wire m_fire2 = m_fire1;
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
//reg btn_fire2 = 0;
//reg btn_fire3 = 0;
reg btn_coin = 0;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
always @(posedge clk_sys) begin
if(key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
// 'h14: btn_fire3 <= key_pressed; // ctrl
// 'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( orientation ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

120
Arcade_MiST/Midway MCR 2/Journey_MiST/rtl/ctc_controler.vhd
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@ -1,120 +0,0 @@
---------------------------------------------------------------------------------
-- Z80-CTC controler by Dar (darfpga@aol.fr) (19/10/2019)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ctc_controler is
port(
clock : in std_logic;
clock_ena : in std_logic;
reset : in std_logic;
d_in : in std_logic_vector( 7 downto 0);
load_data : in std_logic;
int_ack : in std_logic;
int_end : in std_logic; -- RETI detected
int_pulse_0 : in std_logic;
int_pulse_1 : in std_logic;
int_pulse_2 : in std_logic;
int_pulse_3 : in std_logic;
d_out : out std_logic_vector( 7 downto 0);
int_n : out std_logic
);
end ctc_controler;
architecture struct of ctc_controler is
signal int_vector : std_logic_vector(4 downto 0);
signal wait_for_time_constant : std_logic;
signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
signal int_reg_0 : std_logic;
signal int_reg_1 : std_logic;
signal int_reg_2 : std_logic;
signal int_reg_3 : std_logic;
signal int_in_service : std_logic_vector(3 downto 0);
signal int_ack_r : std_logic;
signal int_end_r : std_logic;
begin
int_n <= '0' when (int_reg_0 or int_reg_1 or int_reg_2 or int_reg_3) = '1' else '1';
d_out <= int_vector & "000" when int_reg_0 = '1' else
int_vector & "010" when int_reg_1 = '1' else
int_vector & "100" when int_reg_2 = '1' else
int_vector & "110" when int_reg_3 = '1' else (others => '0');
process (reset, clock)
begin
if reset = '1' then -- hardware and software reset
wait_for_time_constant <= '0';
int_reg_0 <= '0';
int_reg_1 <= '0';
int_reg_2 <= '0';
int_reg_3 <= '0';
int_in_service <= (others => '0');
load_data_r <= '0';
int_vector <= (others => '0');
else
if rising_edge(clock) then
if clock_ena = '1' then
load_data_r <= load_data;
int_ack_r <= int_ack;
int_end_r <= int_end;
if load_data = '1' and load_data_r = '0' then
if wait_for_time_constant = '1' then
wait_for_time_constant <= '0';
else
if d_in(0) = '1' then -- check if its a control world
wait_for_time_constant <= d_in(2);
-- if d_in(1) = '1' then -- software reset
-- wait_for_time_constant <= '0';
-- end if;
else -- its an interrupt vector
int_vector <= d_in(7 downto 3);
end if;
end if;
end if;
if int_pulse_0 = '1' and int_in_service(0) = '0' then int_reg_0 <= '1'; end if;
if int_pulse_1 = '1' and int_in_service(1 downto 0) = "00" then int_reg_1 <= '1'; end if;
if int_pulse_2 = '1' and int_in_service(2 downto 0) = "000" then int_reg_2 <= '1'; end if;
if int_pulse_3 = '1' and int_in_service(3 downto 0) = "0000" then int_reg_3 <= '1'; end if;
if int_ack_r = '0' and int_ack = '1' then
if int_reg_0 = '1' then int_reg_0 <= '0'; int_in_service(0) <= '1';
elsif int_reg_1 = '1' then int_reg_1 <= '0'; int_in_service(1) <= '1';
elsif int_reg_2 = '1' then int_reg_2 <= '0'; int_in_service(2) <= '1';
elsif int_reg_3 = '1' then int_reg_3 <= '0'; int_in_service(3) <= '1';
end if;
end if;
if int_end_r = '0' and int_end = '1' then
if int_in_service(0) = '1' then int_in_service(0) <= '0';
elsif int_in_service(1) = '1' then int_in_service(1) <= '0';
elsif int_in_service(2) = '1' then int_in_service(2) <= '0';
elsif int_in_service(3) = '1' then int_in_service(3) <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
end struct;

151
Arcade_MiST/Midway MCR 2/Journey_MiST/rtl/ctc_counter.vhd
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@ -1,151 +0,0 @@
---------------------------------------------------------------------------------
-- Z80-CTC counter by Dar (darfpga@aol.fr) (19/10/2019)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ctc_counter is
port(
clock : in std_logic;
clock_ena : in std_logic;
reset : in std_logic;
d_in : in std_logic_vector( 7 downto 0);
load_data : in std_logic;
clk_trg : in std_logic;
d_out : out std_logic_vector(7 downto 0);
zc_to : out std_logic;
int_pulse : out std_logic
);
end ctc_counter;
architecture struct of ctc_counter is
signal control_word : std_logic_vector(7 downto 0);
signal wait_for_time_constant : std_logic;
signal time_constant_loaded : std_logic;
signal restart_on_next_clock : std_logic;
signal restart_on_next_trigger : std_logic;
signal prescale_max : std_logic_vector(7 downto 0);
signal prescale_in : std_logic_vector(7 downto 0) := (others => '0');
signal count_max : std_logic_vector(7 downto 0);
signal count_in : std_logic_vector(7 downto 0) := (others => '0');
signal zc_to_in : std_logic;
signal clk_trg_in : std_logic;
signal clk_trg_r : std_logic;
signal trigger : std_logic;
signal count_ena : std_logic;
signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
begin
prescale_max <=
(others => '0') when control_word(6) = '1' else -- counter mode (prescale max = 0)
X"0F" when control_word(6 downto 5) = "00" else -- timer mode prescale 16
X"FF"; -- timer mode prescale 256
clk_trg_in <= clk_trg xor control_word(4);
trigger <= '1' when clk_trg_in = '0' and clk_trg_r = '1' else '0';
d_out <= count_in(7 downto 0);
zc_to <= zc_to_in;
int_pulse <= zc_to_in when control_word(7) = '1' else '0';
process (reset, clock)
begin
if reset = '1' then -- hardware reset
count_ena <= '0';
wait_for_time_constant <= '0';
time_constant_loaded <= '0';
restart_on_next_clock <= '0';
restart_on_next_trigger <= '0';
count_in <= (others=> '0');
zc_to_in <= '0';
clk_trg_r <= '0';
else
if rising_edge(clock) then
if clock_ena = '1' then
clk_trg_r <= clk_trg_in;
load_data_r <= load_data;
if (restart_on_next_trigger = '1' and trigger = '1') or (restart_on_next_clock = '1') then
restart_on_next_clock <= '0';
restart_on_next_trigger <= '0';
count_ena <= '1';
count_in <= count_max;
prescale_in <= prescale_max;
end if;
if load_data = '1' and load_data_r = '0' then
if wait_for_time_constant = '1' then
wait_for_time_constant <= '0';
time_constant_loaded <= '1';
count_max <= d_in;
if control_word(6) = '0' and count_ena = '0' then -- in timer mode, if count was stooped
if control_word(3) = '0' then -- auto start when time_constant loaded
restart_on_next_clock <= '1';
else -- wait for trigger to start
restart_on_next_trigger <= '1';
end if;
end if;
if control_word(6) = '1' then -- in trigger mode reload the counter immediately,
-- otherwise the first period will undefined
prescale_in <= (others => '0');
count_in <= d_in;
end if;
else -- not waiting for time constant
if d_in(0) = '1' then -- check if its a control world
control_word <= d_in;
wait_for_time_constant <= d_in(2);
restart_on_next_clock <= '0';
restart_on_next_trigger <= '0';
if d_in(1) = '1' then -- software reset
count_ena <= '0';
time_constant_loaded <= '0';
zc_to_in <= '0';
-- zc_to_in_r <= '0';
clk_trg_r <= clk_trg;
end if;
end if;
end if;
end if; -- end load data
-- counter
zc_to_in <= '0';
if ((control_word(6) = '1' and trigger = '1' ) or
(control_word(6) = '0' and count_ena = '1') ) and time_constant_loaded = '1' then
if prescale_in = 0 then
prescale_in <= prescale_max;
if count_in = 1 then
zc_to_in <= '1';
count_in <= count_max;
else
count_in <= count_in - '1';
end if;
else
prescale_in <= prescale_in - '1';
end if;
end if;
end if;
end if;
end if;
end process;
end struct;

56
Arcade_MiST/Midway MCR 2/Journey_MiST/rtl/journey.vhd
View File

@ -134,6 +134,7 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- 91475 CPU board + 91464 video board
entity journey is
port(
clock_40 : in std_logic;
@ -152,27 +153,11 @@ port(
audio_out_l : out std_logic_vector(15 downto 0);
audio_out_r : out std_logic_vector(15 downto 0);
coin1 : in std_logic;
coin2 : in std_logic;
start1 : in std_logic;
start2 : in std_logic;
left1 : in std_logic;
right1 : in std_logic;
up1 : in std_logic;
down1 : in std_logic;
fire1 : in std_logic;
left2 : in std_logic;
right2 : in std_logic;
up2 : in std_logic;
down2 : in std_logic;
fire2 : in std_logic;
cocktail : in std_logic;
coin_meters : in std_logic;
service : in std_logic;
input_0 : in std_logic_vector( 7 downto 0);
input_1 : in std_logic_vector( 7 downto 0);
input_2 : in std_logic_vector( 7 downto 0);
input_3 : in std_logic_vector( 7 downto 0);
input_4 : in std_logic_vector( 7 downto 0);
cpu_rom_addr : out std_logic_vector(15 downto 0);
cpu_rom_do : in std_logic_vector(7 downto 0);
@ -182,14 +167,11 @@ port(
snd_rom_do : in std_logic_vector(7 downto 0);
sp_addr : out std_logic_vector(14 downto 0);
-- sp_graphx_do : in std_logic_vector(7 downto 0);
sp_graphx32_do : in std_logic_vector(31 downto 0);
dl_addr : in std_logic_vector(16 downto 0);
dl_data : in std_logic_vector( 7 downto 0);
dl_wr : in std_logic;
dbg_cpu_addr : out std_logic_vector(15 downto 0)
dl_wr : in std_logic
);
end journey;
@ -320,12 +302,6 @@ architecture struct of journey is
signal ssio_iowe : std_logic;
signal ssio_do : std_logic_vector(7 downto 0);
signal input_0 : std_logic_vector(7 downto 0);
signal input_1 : std_logic_vector(7 downto 0);
signal input_2 : std_logic_vector(7 downto 0);
signal input_3 : std_logic_vector(7 downto 0);
signal input_4 : std_logic_vector(7 downto 0);
signal bg_graphics_1_we : std_logic;
signal bg_graphics_2_we : std_logic;
begin
@ -334,14 +310,6 @@ clock_vid <= clock_40;
clock_vidn <= not clock_40;
reset_n <= not reset;
-- debug
process (reset, clock_vid)
begin
if rising_edge(clock_vid) and cpu_ena ='1' and cpu_mreq_n ='0' then
dbg_cpu_addr<= "000000000000000"&service; --cpu_addr;
end if;
end process;
-- make enables clock from clock_vid
process (clock_vid, reset)
begin
@ -470,16 +438,6 @@ begin
end if;
end process;
--------------------
-- players inputs --
--------------------
-- "111" for test & tilt & unused
input_0 <= not service & "11" & not fire1 & not start2 & not start1 & not coin2 & not coin1;
input_1 <= "1111" & not down1 & not up1 & not right1 & not left1;
input_2 <= "111" & not fire2 & not down2 & not up2 & not right2 & not left2;
input_3 <= "111111" & cocktail & coin_meters;
input_4 <= x"FF";
------------------------------------------
-- cpu data input with address decoding --
------------------------------------------

185
Arcade_MiST/Midway MCR 2/Journey_MiST/rtl/z80ctc_top.vhd
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@ -1,185 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- Z80-CTC (MK3882) top-level
entity z80ctc_top is
port(
clock : in std_logic;
clock_ena : in std_logic;
reset : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
cpu_din : in std_logic_vector(7 downto 0); -- mirror the input to the cpu, for RETI detection
ce_n : in std_logic;
cs : in std_logic_vector(1 downto 0);
m1_n : in std_logic;
iorq_n : in std_logic;
rd_n : in std_logic;
int_n : out std_logic;
trg0 : in std_logic;
to0 : out std_logic;
trg1 : in std_logic;
to1 : out std_logic;
trg2 : in std_logic;
to2 : out std_logic;
trg3 : in std_logic
);
end z80ctc_top;
architecture struct of z80ctc_top is
signal cpu_int_ack_n : std_logic;
signal ctc_controler_we : std_logic;
signal ctc_controler_do : std_logic_vector(7 downto 0);
signal ctc_int_ack : std_logic;
signal ctc_int_ack_phase : std_logic_vector(1 downto 0);
signal ctc_counter_0_we : std_logic;
signal ctc_counter_0_do : std_logic_vector(7 downto 0);
signal ctc_counter_0_int : std_logic;
signal ctc_counter_1_we : std_logic;
signal ctc_counter_1_do : std_logic_vector(7 downto 0);
signal ctc_counter_1_int : std_logic;
signal ctc_counter_2_we : std_logic;
signal ctc_counter_2_do : std_logic_vector(7 downto 0);
signal ctc_counter_2_int : std_logic;
signal ctc_counter_3_we : std_logic;
signal ctc_counter_3_do : std_logic_vector(7 downto 0);
signal ctc_counter_3_int : std_logic;
begin
process (clock, reset)
begin
if reset = '1' then
ctc_int_ack_phase <= "00";
elsif rising_edge(clock) then
-- decode ED4D (reti)
if clock_ena = '1' and rd_n = '0' and m1_n = '0' then
case ctc_int_ack_phase is
when "00" => if cpu_din = x"ED" then ctc_int_ack_phase <= "01"; end if;
when "01" => if cpu_din = x"4D" then ctc_int_ack_phase <= "11"; elsif cpu_din /= x"ED" then ctc_int_ack_phase <= "00"; end if;
when "11" => if cpu_din = x"ED" then ctc_int_ack_phase <= "01"; elsif cpu_din /= x"4D" then ctc_int_ack_phase <= "00"; end if;
when others => ctc_int_ack_phase <= "00";
end case;
end if;
end if;
end process;
ctc_int_ack <= '1' when ctc_int_ack_phase = "11" else '0';
cpu_int_ack_n <= iorq_n or m1_n;
ctc_controler_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "00" else '0';
ctc_counter_0_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "00" else '0';
ctc_counter_1_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "01" else '0';
ctc_counter_2_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "10" else '0';
ctc_counter_3_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "11" else '0';
dout <= ctc_controler_do when cpu_int_ack_n = '0' else
ctc_counter_0_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "00" else
ctc_counter_1_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "01" else
ctc_counter_2_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "10" else
ctc_counter_3_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "11" else
x"FF";
-- CTC interrupt controler Z80-CTC (MK3882)
ctc_controler : entity work.ctc_controler
port map(
clock => clock,
clock_ena => clock_ena,
reset => reset,
d_in => din,
load_data => ctc_controler_we,
int_ack => cpu_int_ack_n,
int_end => ctc_int_ack,
int_pulse_0 => ctc_counter_0_int,
int_pulse_1 => ctc_counter_1_int,
int_pulse_2 => ctc_counter_2_int,
int_pulse_3 => ctc_counter_3_int,
d_out => ctc_controler_do,
int_n => int_n
);
ctc_counter_0 : entity work.ctc_counter
port map(
clock => clock,
clock_ena => clock_ena,
reset => reset,
d_in => din,
load_data => ctc_counter_0_we,
clk_trg => trg0,
d_out => ctc_counter_0_do,
zc_to => to0,
int_pulse => ctc_counter_0_int
);
ctc_counter_1 : entity work.ctc_counter
port map(
clock => clock,
clock_ena => clock_ena,
reset => reset,
d_in => din,
load_data => ctc_counter_1_we,
clk_trg => trg1,
d_out => ctc_counter_1_do,
zc_to => to1,
int_pulse => ctc_counter_1_int
);
ctc_counter_2 : entity work.ctc_counter
port map(
clock => clock,
clock_ena => clock_ena,
reset => reset,
d_in => din,
load_data => ctc_counter_2_we,
clk_trg => trg2,
d_out => ctc_counter_2_do,
zc_to => to2,
int_pulse => ctc_counter_2_int
);
ctc_counter_3 : entity work.ctc_counter
port map(
clock => clock,
clock_ena => clock_ena,
reset => reset,
d_in => din,
load_data => ctc_counter_3_we,
clk_trg => trg3,
d_out => ctc_counter_3_do,
zc_to => open,
int_pulse => ctc_counter_3_int
);
end struct;