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Bombjack first working version without Backgrounds

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Gehstock
2019-10-28 20:03:04 +01:00
parent 7ff9dcbb17
commit 1b2e10823a
526 changed files with 670 additions and 2011 deletions
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28
Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.qsf
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@@ -150,6 +150,13 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
#set_location_assignment PLL_1 -to #"pll:pll|altpll:altpll_component"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/b2m_mist.sv
set_global_assignment -name VERILOG_FILE rtl/b2m_top.v
set_global_assignment -name VERILOG_FILE rtl/k580wi53.v
set_global_assignment -name VERILOG_FILE rtl/k580wm80a.v
@@ -157,23 +164,10 @@ set_global_assignment -name VERILOG_FILE rtl/k580wn59.v
set_global_assignment -name VERILOG_FILE rtl/k580ww55.v
set_global_assignment -name VERILOG_FILE rtl/b2m_video.v
set_global_assignment -name VERILOG_FILE rtl/b2m_kbd.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name VERILOG_FILE rtl/build_id.v
set_global_assignment -name VERILOG_FILE rtl/SDRAM_Controller.v
set_global_assignment -name QIP_FILE rtl/bios.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/b2m_mist.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
set_global_assignment -name VERILOG_FILE rtl/sd_card.v
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
#set_location_assignment PLL_1 -to #"pll:pll|altpll:altpll_component"
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name QIP_FILE rtl/clk20mhz.qip
set_global_assignment -name VERILOG_FILE rtl/clk20mhz.v
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name VHDL_FILE rtl/bios.vhd
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

7
Computer_MiST/Bashkiria2M_MiST/Bashkiria2m_Mist.srf
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@@ -1,7 +1,2 @@
{ "" "" "" "*" { } { } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13012 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 14320 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 14284 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}

257
Computer_MiST/Bashkiria2M_MiST/rtl/BIOS4.HEX
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@@ -1,257 +0,0 @@
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14
Computer_MiST/Bashkiria2M_MiST/rtl/SDRAM_Controller.v
View File

@@ -7,7 +7,7 @@ module SDRAM_Controller(
input clk100, // Clock 100MHz
input reset, // System reset
inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits
output reg[11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits
output reg[12:0] DRAM_ADDR, // SDRAM Address bus 12 Bits
output reg DRAM_LDQM, // SDRAM Low-byte Data Mask
output reg DRAM_UDQM, // SDRAM High-byte Data Mask
output reg DRAM_WE_N, // SDRAM Write Enable
@@ -17,7 +17,7 @@ module SDRAM_Controller(
output DRAM_BA_0, // SDRAM Bank Address 0
output DRAM_BA_1, // SDRAM Bank Address 0
input [21:0] iaddr,
input [7:0] idata,
input [15:0] idata,
input rd,
input we_n,
output reg [15:0] odata,
@@ -50,17 +50,17 @@ reg[15:0] data;
reg exrd,exwen;
reg ubn,lbn,rdvid;
assign DRAM_DQ[7:0] = (state==ST_WRITE0) ? data : 8'bZZZZZZZZ;
assign DRAM_DQ[15:8] = (state == ST_WRITE0) ? data : 8'bZZZZZZZZ;
assign DRAM_DQ[7:0] = (state==ST_WRITE0) ? data[7:0] : 8'bZZZZZZZZ;
assign DRAM_DQ[15:8] = (state == ST_WRITE0) ? data[7:0] : 8'bZZZZZZZZ;
assign DRAM_CS_N = 1'b0;
assign DRAM_BA_0 = addr[20];
assign DRAM_BA_1 = addr[21];
always @(*) begin
case (state)
ST_RESET0: DRAM_ADDR = 12'b100000;
ST_RAS0: DRAM_ADDR = addr[19:8];
default: DRAM_ADDR = {4'b0100,addr[7:0]};
ST_RESET0: DRAM_ADDR = 13'b100000;
ST_RAS0: DRAM_ADDR = addr[20:8];
default: DRAM_ADDR = {5'b00100,addr[7:0]};
endcase
case (state)
ST_RESET0: {DRAM_RAS_N,DRAM_CAS_N,DRAM_WE_N} = 3'b000;

231
Computer_MiST/Bashkiria2M_MiST/rtl/b2m_mist.sv
View File

@@ -1,6 +1,5 @@
module b2m_mist
(
input CLOCK_27,
module b2m_mist(
input CLOCK_27,
output LED,
output SPI_DO,
input SPI_DI,
@@ -9,17 +8,17 @@ module b2m_mist
input SPI_SS3,
input SPI_SS4,
input CONF_DATA0,
inout [15:0] SDRAM_DQ, // SDRAM Data bus 16 Bits
output [12:0] SDRAM_A, // SDRAM Address bus 13 Bits
output SDRAM_DQML, // SDRAM Low-byte Data Mask
output SDRAM_DQMH, // SDRAM High-byte Data Mask
output SDRAM_nWE, // SDRAM Write Enable
output SDRAM_nCAS, // SDRAM Column Address Strobe
output SDRAM_nRAS, // SDRAM Row Address Strobe
output SDRAM_nCS, // SDRAM Chip Select
output [1:0] SDRAM_BA, // SDRAM Bank Address
output SDRAM_CLK, // SDRAM Clock
output SDRAM_CKE, // SDRAM Clock Enable
inout [15:0] SDRAM_DQ,
output [12:0] SDRAM_A,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE,
output AUDIO_L,
output AUDIO_R,
output VGA_HS,
@@ -33,34 +32,28 @@ module b2m_mist
`include "rtl\build_id.v"
localparam CONF_STR = {
"B2M;;",
"Bashkiria 2M;;",
"O2,Turbo ,ON,OFF;",
"O3,Color Mode ,COLOR,B/W;",
"O4,Video Mode ,PAL,NTSC;",
"O56,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"O56,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
"T7,Reset;",
"V,v1.00.",`BUILD_DATE
};
assign LED = 1'b1;
assign AUDIO_R = AUDIO_L;
wire clk_sys;
wire clk12p5;
wire clk100;
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] kbjoy;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoubler_disable;
wire scandoublerD;
wire ypbpr;
wire ps2_kbd_clk, ps2_kbd_data;
wire ps2_kbd_clk;
wire ps2_kbd_data;
wire [15:0] audio;
//assign LED = 1;
wire hblank, vblank;
wire ce_vid;
wire hs, vs;
wire [3:0] r,g,b;
@@ -68,102 +61,11 @@ wire [3:0] r,g,b;
pll pll(
.inclk0(CLOCK_27),
.c0(clk_sys),//50
.c1(clk12p5)
);
video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(0)) video_mixer(
.clk_sys(clk_sys),
.ce_pix(clk12p5),
.ce_pix_actual(clk12p5),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R({r,r[1:0]}),
.G({g,g[1:0]}),
.B({b,b[1:0]}),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.scandoubler_disable(1),//scandoubler_disable),
.scanlines(scandoubler_disable ? 2'b00 : {status[6:5] == 3, status[6:5] == 2}),
.hq2x(status[6:5]==1),
.ypbpr_full(1),
.line_start(0),
.mono(0)
);
mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable(scandoubler_disable),
.ypbpr (ypbpr ),
.ps2_kbd_clk (ps2_kbd_clk ),
.ps2_kbd_data (ps2_kbd_data ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status ),
.sd_lba (sd_lba ),
.sd_rd (sd_rd ),
.sd_wr (sd_wr ),
.sd_ack (sd_ack ),
.sd_conf (sd_conf ),
.sd_sdhc (sd_sdhc ),
.sd_buff_dout (sd_data_out ),
.sd_buff_din (sd_data_in ),
.sd_dout_strobe (sd_data_in_strobe),
.sd_din_strobe (sd_data_out_strobe)
);
wire [31:0] sd_lba;
wire sd_rd;
wire sd_wr;
wire sd_ack;
wire sd_conf;
wire sd_sdhc;
wire allow_sdhc;
wire [7:0] sd_data_in;
wire sd_data_in_strobe;
wire [7:0] sd_data_out;
wire sd_data_out_strobe;
wire sd_cs;
wire sd_sck;
wire sd_sdi;
wire sd_sdo;
sd_card sd_card(
.io_lba (sd_lba),
.io_rd (sd_rd),
.io_wr (sd_wr),
.io_ack (sd_ack),
.io_conf (sd_conf),
.io_sdhc (sd_sdhc),
.io_din (sd_data_out),
.io_din_strobe (sd_data_in_strobe),
.io_dout (sd_data_in),
.io_dout_strobe(sd_data_out_strobe),
.allow_sdhc (allow_sdhc),
.sd_cs (sd_cs),
.sd_sck (sd_sck),
.sd_sdi (sd_sdi),
.sd_sdo (sd_sdo)
);
b2m_top b2m_top(
.clk50mhz(clk_sys),
.res(~(status[0] || status[7] || buttons[1])),
.res(~(status[0] | status[7] | buttons[1])),
.color_mode(~status[3] ),
.video_mode(status[4] ),
.turbo(~status[2] ),
@@ -192,14 +94,95 @@ b2m_top b2m_top(
.SD_CMD(sd_sdi),
.SD_CLK(sd_sck)
);
dac dac(
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(9)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( r),
.G ( g),
.B ( b),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.scandoubler_disable( 1'b1),//scandoublerD ),
.scanlines ( status[6:5] ),
.ce_divider (1),
.ypbpr ( ypbpr )
);
user_io #(.STRLEN(($size(CONF_STR)>>3))) user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.ps2_kbd_clk (ps2_kbd_clk ),
.ps2_kbd_data (ps2_kbd_data ),
.status (status ),
.sd_lba (sd_lba ),
.sd_rd (sd_rd ),
.sd_wr (sd_wr ),
.sd_ack (sd_ack ),
.sd_conf (sd_conf ),
.sd_sdhc (sd_sdhc ),
.sd_dout (sd_data_out ),
.sd_din (sd_data_in ),
.sd_dout_strobe (sd_data_in_strobe),
.sd_din_strobe (sd_data_out_strobe)
);
dac #(
.C_bits(16))
dac(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
assign AUDIO_R = AUDIO_L;
);
wire [31:0] sd_lba;
wire sd_rd;
wire sd_wr;
wire sd_ack;
wire sd_conf;
wire sd_sdhc;
wire allow_sdhc;
wire [7:0] sd_data_in;
wire sd_data_in_strobe;
wire [7:0] sd_data_out;
wire sd_data_out_strobe;
wire sd_cs;
wire sd_sck;
wire sd_sdi;
wire sd_sdo;
sd_card sd_card(
.io_lba (sd_lba),
.io_rd (sd_rd),
.io_wr (sd_wr),
.io_ack (sd_ack),
.io_conf (sd_conf),
.io_sdhc (sd_sdhc),
.io_din (sd_data_out),
.io_din_strobe (sd_data_in_strobe),
.io_dout (sd_data_in),
.io_dout_strobe(sd_data_out_strobe),
.allow_sdhc (allow_sdhc),
.sd_cs (sd_cs),
.sd_sck (sd_sck),
.sd_sdi (sd_sdi),
.sd_sdo (sd_sdo)
);
endmodule

11
Computer_MiST/Bashkiria2M_MiST/rtl/b2m_top.v
View File

@@ -107,11 +107,10 @@ reg[7:0] mem_o;
always @(negedge memvidbusy) vid_data <= dramout;
always @(negedge memcpubusy) mem_o <= dramout[7:0];
bios rom(
.address(addrbus[12:0]),
.clock(clk50mhz),
.q(rom_o)
.addr(addrbus[12:0]),
.clk(clk50mhz),
.data(rom_o)
);
//////////////////// CPU ////////////////////
@@ -161,7 +160,7 @@ wire cpu_ce = cpu_ce2;
always @(posedge clk50mhz) begin
vidce2<=vidce;
cpu_cnt <= cpu_cnt + 1;
cpu_cnt <= cpu_cnt + 1'b1;
if (cpu_sync) sysctl <= cpu_o;
if (addrbus[0]&~sio_we_n) sound_on <= ~cpu_o[5];
if(turbo==1 && {vidce2,vidce}==2'b01 && cpu_cnt>3){cpu_cnt,cpu_ce2}<={10'b0,~memcpubusy&~memvidbusy};
@@ -333,7 +332,7 @@ always @(posedge clk50mhz) begin
if (line6bit > 32) tapein <= 1'b1;
end*/
//I2C_AV_Config sndcfg(.iCLK(clk50mhz), .iRST_N(reset_n), .I2C_SCLK(I2C_SCLK), .I2C_SDAT(I2C_SDAT));
//////////////////// SD CARD ////////////////////
reg sdcs;

3
Computer_MiST/Bashkiria2M_MiST/rtl/bios.qip
View File

@@ -1,3 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "bios.v"]

159
Computer_MiST/Bashkiria2M_MiST/rtl/bios.v
View File

@@ -1,159 +0,0 @@
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bios.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bios (
address,
clock,
q);
input [12:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./rtl/BIOS4.HEX",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./rtl/BIOS4.HEX"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/BIOS4.HEX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf

534
Computer_MiST/Bashkiria2M_MiST/rtl/bios.vhd Normal file
View File

@@ -0,0 +1,534 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity bios is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of bios is
type rom is array(0 to 8191) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"C3",X"13",X"E0",X"C3",X"55",X"E8",X"C3",X"CB",X"F1",X"C3",X"72",X"E2",X"C3",X"CC",X"E2",X"C3",
X"F5",X"F1",X"32",X"F3",X"3E",X"AA",X"D3",X"10",X"D3",X"11",X"D3",X"12",X"D3",X"13",X"3E",X"80",
X"D3",X"6B",X"3E",X"30",X"D3",X"63",X"3E",X"76",X"D3",X"63",X"3E",X"94",X"D3",X"63",X"3E",X"0D",
X"D3",X"62",X"3E",X"90",X"D3",X"47",X"3E",X"F0",X"D3",X"46",X"3E",X"15",X"D3",X"79",X"3E",X"40",
X"D3",X"79",X"3E",X"FE",X"D3",X"79",X"3E",X"16",X"D3",X"74",X"3E",X"DF",X"D3",X"75",X"3E",X"FF",
X"D3",X"75",X"AF",X"D3",X"6A",X"32",X"FE",X"DF",X"32",X"FF",X"DF",X"3E",X"C3",X"32",X"04",X"DF",
X"21",X"13",X"E0",X"22",X"05",X"DF",X"FB",X"01",X"00",X"60",X"3E",X"E9",X"D3",X"61",X"3E",X"07",
X"D3",X"61",X"3E",X"15",X"D3",X"79",X"0B",X"79",X"B0",X"C2",X"76",X"E0",X"3E",X"25",X"D3",X"79",
X"01",X"FF",X"FF",X"0B",X"79",X"B0",X"C2",X"83",X"E0",X"31",X"00",X"DF",X"CD",X"66",X"EE",X"01",
X"20",X"DF",X"21",X"26",X"DF",X"CD",X"55",X"F0",X"7A",X"FE",X"DC",X"CC",X"3C",X"F8",X"3A",X"FF",
X"DF",X"B7",X"C2",X"9E",X"E0",X"31",X"00",X"DF",X"CD",X"10",X"FF",X"3E",X"25",X"D3",X"79",X"3E",
X"FF",X"D3",X"75",X"3E",X"20",X"D3",X"74",X"CD",X"04",X"E9",X"21",X"19",X"E1",X"CD",X"C2",X"E3",
X"21",X"25",X"E1",X"CD",X"C2",X"E3",X"31",X"00",X"DF",X"21",X"8C",X"E1",X"CD",X"C2",X"E3",X"CD",
X"72",X"E2",X"21",X"C6",X"E0",X"E5",X"FE",X"3F",X"CA",X"AB",X"E0",X"FE",X"0D",X"C8",X"FE",X"53",
X"CA",X"05",X"E2",X"FE",X"52",X"CA",X"53",X"E2",X"FE",X"57",X"CA",X"5A",X"E2",X"FE",X"4C",X"CA",
X"6A",X"E3",X"FE",X"47",X"CA",X"41",X"E2",X"FE",X"59",X"CA",X"53",X"E3",X"FE",X"55",X"CA",X"60",
X"E3",X"CD",X"07",X"E1",X"C3",X"C6",X"E0",X"21",X"0D",X"E1",X"C3",X"C2",X"E3",X"0D",X"0A",X"2D",
X"DE",X"E8",X"D8",X"D1",X"DA",X"D0",X"2D",X"0D",X"00",X"1B",X"42",X"B7",X"B0",X"B3",X"C0",X"C3",
X"B7",X"C7",X"B8",X"BA",X"00",X"C4",X"E3",X"DD",X"DA",X"E6",X"D8",X"D8",X"3A",X"0D",X"0A",X"53",
X"2D",X"E3",X"E1",X"E2",X"D0",X"DD",X"DE",X"D2",X"DA",X"D0",X"20",X"EF",X"E7",X"D5",X"D9",X"DA",
X"D8",X"0D",X"0A",X"4C",X"2D",X"D7",X"D0",X"D3",X"E0",X"E3",X"D7",X"DA",X"D0",X"20",X"D8",X"D7",
X"20",X"BF",X"B7",X"C3",X"0D",X"0A",X"52",X"2D",X"E7",X"E2",X"D5",X"DD",X"D8",X"D5",X"20",X"E1",
X"20",X"BC",X"BB",X"0D",X"0A",X"57",X"2D",X"D7",X"D0",X"DF",X"D8",X"E1",X"EC",X"20",X"DD",X"D0",
X"20",X"BC",X"BB",X"0D",X"0A",X"47",X"2D",X"D2",X"EB",X"DF",X"DE",X"DB",X"DD",X"D8",X"E2",X"EC",
X"20",X"DF",X"E0",X"DE",X"D3",X"E0",X"D0",X"DC",X"DC",X"E3",X"0D",X"00",X"0A",X"3E",X"00",X"0D",
X"0A",X"BF",X"DE",X"D4",X"D3",X"DE",X"E2",X"DE",X"D2",X"EC",X"E2",X"D5",X"20",X"DC",X"D0",X"D3",
X"DD",X"D8",X"E2",X"DE",X"E4",X"DE",X"DD",X"20",X"D4",X"DB",X"EF",X"20",X"00",X"B7",X"B0",X"BF",
X"B8",X"C1",X"B8",X"00",X"C7",X"C2",X"B5",X"BD",X"B8",X"CF",X"00",X"0D",X"0A",X"D8",X"20",X"DD",
X"D0",X"D6",X"DC",X"D8",X"E2",X"D5",X"20",X"3C",X"B2",X"BA",X"3E",X"00",X"0A",X"2A",X"B7",X"B0",
X"BF",X"B8",X"C1",X"CC",X"2A",X"0D",X"00",X"0A",X"2A",X"C7",X"C2",X"B5",X"BD",X"B8",X"B5",X"2A",
X"0D",X"00",X"0A",X"2A",X"DE",X"E8",X"D8",X"D1",X"DA",X"D0",X"20",X"BA",X"C1",X"2A",X"0D",X"00",
X"0A",X"D2",X"EB",X"DA",X"DB",X"EE",X"E7",X"D8",X"20",X"DC",X"D0",X"D3",X"DD",X"D8",X"E2",X"DE",
X"E4",X"DE",X"DD",X"0D",X"00",X"CD",X"CC",X"E2",X"3D",X"C2",X"01",X"E1",X"2A",X"1A",X"DF",X"CD",
X"41",X"E3",X"E5",X"CD",X"46",X"E3",X"CD",X"4E",X"E3",X"E1",X"7E",X"E5",X"CD",X"D5",X"E3",X"CD",
X"4E",X"E3",X"CD",X"72",X"E2",X"E1",X"FE",X"0D",X"CA",X"3D",X"E2",X"FE",X"2E",X"C8",X"E5",X"CD",
X"CF",X"E2",X"2A",X"1A",X"DF",X"7C",X"B7",X"C2",X"01",X"E1",X"7D",X"E1",X"77",X"23",X"C3",X"0F",
X"E2",X"CD",X"CC",X"E2",X"3D",X"C2",X"01",X"E1",X"31",X"00",X"DF",X"21",X"C6",X"E0",X"E5",X"2A",
X"1A",X"DF",X"E9",X"CD",X"61",X"E2",X"CD",X"E2",X"EF",X"C9",X"CD",X"61",X"E2",X"CD",X"A8",X"EF",
X"C9",X"CD",X"CC",X"E2",X"FE",X"02",X"C2",X"01",X"E1",X"2A",X"1A",X"DF",X"44",X"4D",X"2A",X"1C",
X"DF",X"C9",X"11",X"DA",X"DF",X"06",X"00",X"CD",X"6F",X"E4",X"FE",X"0D",X"CA",X"89",X"E2",X"FE",
X"7F",X"CA",X"9D",X"E2",X"FE",X"20",X"DA",X"77",X"E2",X"CD",X"CE",X"E3",X"12",X"13",X"FE",X"0D",
X"CA",X"AC",X"E2",X"04",X"78",X"FE",X"20",X"CA",X"AC",X"E2",X"C3",X"77",X"E2",X"AF",X"B0",X"CA",
X"77",X"E2",X"05",X"1B",X"3E",X"7F",X"CD",X"CE",X"E3",X"C3",X"77",X"E2",X"21",X"DA",X"DF",X"22",
X"17",X"DF",X"78",X"32",X"16",X"DF",X"E5",X"21",X"16",X"DF",X"7E",X"B7",X"3E",X"0D",X"CA",X"CA",
X"E2",X"35",X"2A",X"17",X"DF",X"7E",X"23",X"22",X"17",X"DF",X"E1",X"C9",X"CD",X"B6",X"E2",X"21",
X"19",X"DF",X"36",X"00",X"23",X"FE",X"0D",X"CA",X"01",X"E3",X"CD",X"08",X"E3",X"CD",X"20",X"E3",
X"FE",X"0D",X"CA",X"01",X"E3",X"CD",X"B6",X"E2",X"CD",X"08",X"E3",X"CD",X"20",X"E3",X"FE",X"0D",
X"CA",X"01",X"E3",X"CD",X"B6",X"E2",X"CD",X"08",X"E3",X"CD",X"20",X"E3",X"FE",X"0D",X"C2",X"01",
X"E1",X"11",X"19",X"DF",X"1A",X"13",X"B7",X"C9",X"EB",X"21",X"00",X"00",X"CD",X"2B",X"E3",X"29",
X"29",X"29",X"29",X"B5",X"6F",X"CD",X"B6",X"E2",X"CD",X"38",X"E3",X"C2",X"0C",X"E3",X"EB",X"C9",
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X"42",X"FE",X"11",X"80",X"80",X"21",X"20",X"4E",X"CD",X"5A",X"FE",X"4F",X"92",X"BB",X"79",X"D0",
X"2B",X"7C",X"B5",X"C2",X"98",X"FE",X"D6",X"01",X"C9",X"C5",X"D5",X"E5",X"11",X"FF",X"00",X"CD",
X"95",X"FE",X"E1",X"D1",X"C1",X"C9",X"CD",X"3D",X"FE",X"06",X"10",X"CD",X"40",X"FE",X"05",X"C2",
X"BB",X"FE",X"CD",X"3C",X"FE",X"3E",X"40",X"CD",X"6F",X"FE",X"FE",X"01",X"C0",X"3E",X"77",X"CD",
X"6F",X"FE",X"E6",X"FE",X"C0",X"3E",X"69",X"CD",X"6F",X"FE",X"FE",X"01",X"CA",X"CD",X"FE",X"B7",
X"C9",X"CD",X"A9",X"FE",X"D8",X"E5",X"EB",X"29",X"5C",X"65",X"AF",X"57",X"6F",X"3E",X"51",X"CD",
X"75",X"FE",X"E1",X"D8",X"06",X"00",X"E5",X"11",X"01",X"FF",X"CD",X"95",X"FE",X"E1",X"FE",X"FE",
X"C0",X"CD",X"5A",X"FE",X"77",X"23",X"CD",X"5A",X"FE",X"77",X"23",X"05",X"C2",X"01",X"FF",X"C9",
X"3E",X"02",X"D3",X"6A",X"3A",X"80",X"28",X"E6",X"04",X"C0",X"AF",X"D3",X"6A",X"CD",X"24",X"FF",
X"DA",X"3D",X"FE",X"E9",X"CD",X"B6",X"FE",X"37",X"C0",X"11",X"00",X"00",X"21",X"00",X"C0",X"CD",
X"E1",X"FE",X"D8",X"CD",X"42",X"FF",X"D0",X"2A",X"C6",X"C1",X"EB",X"21",X"00",X"C0",X"CD",X"E1",
X"FE",X"D8",X"CD",X"BA",X"FF",X"37",X"C0",X"2A",X"16",X"C0",X"EB",X"2A",X"0E",X"C0",X"3A",X"10",
X"C0",X"19",X"3D",X"C2",X"51",X"FF",X"EB",X"2A",X"1C",X"C0",X"19",X"22",X"F0",X"C1",X"EB",X"2A",
X"11",X"C0",X"4D",X"44",X"29",X"29",X"29",X"29",X"E5",X"79",X"E6",X"0F",X"C5",X"CC",X"9E",X"FF",
X"D5",X"E5",X"06",X"0B",X"11",X"CB",X"FF",X"1A",X"BE",X"C2",X"AA",X"FF",X"13",X"23",X"05",X"C2",
X"77",X"FF",X"C1",X"C1",X"C1",X"11",X"0F",X"00",X"19",X"5E",X"23",X"56",X"1B",X"1B",X"2A",X"F0",
X"C1",X"3A",X"0D",X"C0",X"19",X"3D",X"C2",X"94",X"FF",X"D1",X"5A",X"57",X"19",X"EB",X"D5",X"21",
X"00",X"C2",X"E5",X"CD",X"E1",X"FE",X"E1",X"D1",X"13",X"C9",X"E1",X"11",X"20",X"00",X"19",X"D1",
X"C1",X"0B",X"78",X"B1",X"C2",X"69",X"FF",X"C1",X"37",X"C9",X"21",X"36",X"C0",X"7E",X"23",X"FE",
X"46",X"C0",X"7E",X"23",X"FE",X"41",X"C0",X"7E",X"FE",X"54",X"C9",X"42",X"4F",X"4F",X"54",X"20",
X"20",X"20",X"20",X"52",X"4F",X"4D",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",X"59",X"2C",X"2C",X"2D",X"DE",X"E8",X"D8",
X"D1",X"DA",X"D0",X"20",X"D7",X"D0",X"D3",X"E0",X"E3",X"D7",X"DA",X"D8",X"2D",X"00",X"FF",X"F6");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

4
Computer_MiST/Bashkiria2M_MiST/rtl/clk20mhz.qip
View File

@@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk20mhz.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk20mhz.ppf"]

48
Computer_MiST/Bashkiria2M_MiST/rtl/dac.vhd
View File

@@ -1,48 +0,0 @@
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac is
generic (
C_bits : integer := 16
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(C_bits-1 downto 0);
dac_o : out std_logic
);
end dac;
architecture rtl of dac is
signal sig_in: unsigned(C_bits downto 0);
begin
seq: process(clk_i, res_n_i)
begin
if res_n_i = '0' then
sig_in <= to_unsigned(2**C_bits, sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
dac_o <= sig_in(C_bits);
end if;
end process seq;
end rtl;

511
Computer_MiST/Bashkiria2M_MiST/rtl/mist_io.v
View File

@@ -1,511 +0,0 @@
//
// mist_io.v
//
// mist_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output reg sd_buff_wr,
output reg sd_dout_strobe,
output reg sd_din_strobe,
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
input ps2_caps_led,
// ARM -> FPGA download
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output ioctl_wr,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
reg [7:0] b_data;
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
wire [7:0] spi_dout = { sbuf, SPI_DI};
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
// drive MISO only when transmitting core id
always@(negedge SPI_SCK) begin
if(!CONF_DATA0) begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
spi_do <= core_type[~bit_cnt];
end else begin
case(cmd)
// reading config string
8'h14: begin
// returning a byte from string
if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else spi_do <= 0;
end
// reading sd card status
8'h16: begin
if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else spi_do <= 0;
end
// reading sd card write data
8'h18:
spi_do <= b_data[~bit_cnt];
// reading keyboard LED status
8'h1f:
spi_do <= kbd_led[~bit_cnt];
default:
spi_do <= 0;
endcase
end
end
end
reg b_wr2,b_wr3;
always @(negedge clk_sys) begin
b_wr3 <= b_wr2;
sd_buff_wr <= b_wr3;
end
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
if(CONF_DATA0) begin
b_wr2 <= 0;
bit_cnt <= 0;
byte_cnt <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
sd_dout_strobe <= 0;
sd_din_strobe <= 0;
end else begin
b_wr2 <= 0;
sd_dout_strobe <= 0;
sd_din_strobe <= 0;
sbuf <= spi_dout[6:0];
bit_cnt <= bit_cnt + 1'd1;
if(bit_cnt == 5) begin
if (byte_cnt == 0) sd_buff_addr <= 0;
if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
end
// finished reading command byte
if(bit_cnt == 7) begin
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
if(byte_cnt == 0) begin
cmd <= spi_dout;
if(spi_dout == 8'h19) begin
sd_ack_conf <= 1;
sd_buff_addr <= 0;
end
if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
sd_ack <= 1;
sd_buff_addr <= 0;
end
if(spi_dout == 8'h18) begin
b_data <= sd_buff_din;
sd_din_strobe <= 1'b1;
mount_strobe <= 0;
end
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_dout;
8'h02: joystick_0 <= spi_dout;
8'h03: joystick_1 <= spi_dout;
// store incoming ps2 mouse bytes
8'h04: begin
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_dout;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19: begin
// flag that download begins
sd_buff_dout <= spi_dout;
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
sd_dout_strobe <= 1;
end
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_dout;
sd_dout_strobe <= 1;
b_wr2 <= 1;
end
8'h18: begin
b_data <= sd_buff_din;
sd_din_strobe <= 1;
end
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
end
end
// notify image selection
8'h1c: mount_strobe <= 1;
// send image info
8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
// status, 32bit version
8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
default: ;
endcase
end
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
// keyboard
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_kbd_r_inc <= 0;
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1;
// reset parity
ps2_kbd_parity <= 1;
// start transmitter
ps2_kbd_tx_state <= 1;
// put start bit on data line
ps2_kbd_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
else ps2_kbd_tx_state <= 0;
end
end
end
// mouse
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_mouse_r_inc <= 0;
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1;
// reset parity
ps2_mouse_parity <= 1;
// start transmitter
ps2_mouse_tx_state <= 1;
// put start bit on data line
ps2_mouse_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
else ps2_mouse_tx_state <= 0;
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [24:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [24:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
rclk <= 0;
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// increase target address after write
if(rclk) addr <= addr + 1'd1;
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 0;
ioctl_download <= 1;
end else begin
addr_w <= addr;
ioctl_download <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
rclk <= 1;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
assign ioctl_wr = |ioctl_wrd;
reg [1:0] ioctl_wrd;
always@(negedge clk_sys) begin
reg rclkD, rclkD2;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wrd<= {ioctl_wrd[0],1'b0};
if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wrd <= 2'b11;
end
end
endmodule

179
Computer_MiST/Bashkiria2M_MiST/rtl/osd.v
View File

@@ -1,179 +0,0 @@
// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input clk_sys,
// SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS3) begin
reg [4:0] cnt;
reg [10:0] bcnt;
reg [7:0] sbuf;
reg [7:0] cmd;
if(SPI_SS3) begin
cnt <= 0;
bcnt <= 0;
end else begin
sbuf <= {sbuf[6:0], SPI_DI};
// 0:7 is command, rest payload
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
bcnt <= bcnt + 1'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
// vertical counter
reg [9:0] v_cnt;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg hs;
cnt <= cnt + 1;
hs <= HSync;
pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(hs && ~HSync) begin
cnt <= 0;
pixsz <= (cnt >> 9) - 1;
pixcnt <= 0;
ce_pix <= 1;
end
end
always @(posedge clk_sys) begin
reg hsD, hsD2;
reg vsD, vsD2;
if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end
vsD <= VSync;
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
end
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [7:0] osd_byte;
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
endmodule

195
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//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input ce_pix,
input ce_pix_actual,
input hq2x,
// shifter video interface
input hs_in,
input vs_in,
input line_start,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
input [DWIDTH:0] b_in,
input mono,
// output interface
output reg hs_out,
output vs_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
assign vs_out = vs_in;
reg [2:0] phase;
reg [2:0] ce_div;
reg [7:0] pix_len = 0;
wire [7:0] pl = pix_len + 1'b1;
reg ce_x1, ce_x4;
reg req_line_reset;
wire ls_in = hs_in | line_start;
always @(negedge clk_sys) begin
reg old_ce;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
ce_x4 <= 0;
ce_x1 <= 0;
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
phase <= phase + 1'd1;
ce_x4 <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x4 <= 1;
pix_len <= 0;
phase <= phase + 1'd1;
ce_cnt <= ce_cnt + 1'd1;
if(ce_pix_actual) begin
phase <= 0;
ce_div <= ce_cnt + 1'd1;
ce_cnt <= 0;
req_line_reset <= 0;
end
if(ls_in) req_line_reset <= 1;
end
end
reg ce_sd;
always @(*) begin
case(ce_div)
2: ce_sd = !phase[0];
4: ce_sd = !phase[1:0];
default: ce_sd <= 1;
endcase
end
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4 & ce_sd),
.inputpixel({b_in,g_in,r_in}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.read_x(sd_h_actual),
.outpixel({b_out,g_out,r_out})
);
reg [10:0] sd_h_actual;
always @(*) begin
case(ce_div)
2: sd_h_actual = sd_h[10:1];
4: sd_h_actual = sd_h[10:2];
default: sd_h_actual = sd_h;
endcase
end
reg [10:0] sd_h;
reg [1:0] sd_line;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise,hs_ls;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg hs, hs2, vs, ls;
if(ce_x1) begin
hs <= hs_in;
ls <= ls_in;
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_max <= {hcnt,1'b1};
hcnt <= 0;
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
sd_h <= sd_h + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
if(sd_hcnt == hs_ls) sd_h <= 0;
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
end
end
endmodule

141
Computer_MiST/Bashkiria2M_MiST/rtl/unused/I2C_AV_Config.v
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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module I2C_AV_Config ( // Host Side
iCLK,
iRST_N,
// I2C Side
I2C_SCLK,
I2C_SDAT );
// Host Side
input iCLK;
input iRST_N;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [3:0] LUT_INDEX;
reg [1:0] mSetup_ST;
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 11;
// Audio Data Index
parameter Dummy_DATA = 0;
parameter SET_LIN_L = 1;
parameter SET_LIN_R = 2;
parameter SET_HEAD_L = 3;
parameter SET_HEAD_R = 4;
parameter A_PATH_CTRL = 5;
parameter D_PATH_CTRL = 6;
parameter POWER_ON = 7;
parameter SET_FORMAT = 8;
parameter SAMPLE_CTRL = 9;
parameter SET_ACTIVE = 10;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+16'b1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N) );
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
mI2C_DATA <= {8'h34,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+4'b1;
mSetup_ST <= 0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Audio Config Data
Dummy_DATA : LUT_DATA <= 16'h0000;
SET_LIN_L : LUT_DATA <= 16'h0017;
SET_LIN_R : LUT_DATA <= 16'h0217;
SET_HEAD_L : LUT_DATA <= 16'h0479;
SET_HEAD_R : LUT_DATA <= 16'h0679;
A_PATH_CTRL : LUT_DATA <= 16'h08F2;
D_PATH_CTRL : LUT_DATA <= 16'h0A06;
POWER_ON : LUT_DATA <= 16'h0C00;
SET_FORMAT : LUT_DATA <= 16'h0E01;
SAMPLE_CTRL : LUT_DATA <= 16'h1002;
SET_ACTIVE : LUT_DATA <= 16'h1201;
default : LUT_DATA <= 16'h0000;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule

108
Computer_MiST/Bashkiria2M_MiST/rtl/unused/I2C_Controller.v
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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module I2C_Controller (
CLOCK,
I2C_SCLK,//I2C CLOCK
I2C_SDAT,//I2C DATA
I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
GO, //GO transfor
END, //END transfor
ACK, //ACK
RESET
);
input CLOCK;
input [23:0]I2C_DATA;
input GO;
input RESET;
inout I2C_SDAT;
output I2C_SCLK;
output END;
output ACK;
reg SDO;
reg SCLK;
reg END;
reg [23:0]SD;
reg [5:0]SD_COUNTER;
wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=30))? ~CLOCK :1'b0 );
wire I2C_SDAT=SDO?1'bz:1'b0;
reg ACK1,ACK2,ACK3;
wire ACK=ACK1 | ACK2 |ACK3;
//--I2C COUNTER
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) SD_COUNTER=6'b111111;
else begin
if (GO==0)
SD_COUNTER=0;
else
if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER+6'b1;
end
end
//----
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end
else
case (SD_COUNTER)
6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end
//start
6'd1 : begin SD=I2C_DATA;SDO=0;end
6'd2 : SCLK=0;
//SLAVE ADDR
6'd3 : SDO=SD[23];
6'd4 : SDO=SD[22];
6'd5 : SDO=SD[21];
6'd6 : SDO=SD[20];
6'd7 : SDO=SD[19];
6'd8 : SDO=SD[18];
6'd9 : SDO=SD[17];
6'd10 : SDO=SD[16];
6'd11 : SDO=1'b1;//ACK
//SUB ADDR
6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end
6'd13 : SDO=SD[14];
6'd14 : SDO=SD[13];
6'd15 : SDO=SD[12];
6'd16 : SDO=SD[11];
6'd17 : SDO=SD[10];
6'd18 : SDO=SD[9];
6'd19 : SDO=SD[8];
6'd20 : SDO=1'b1;//ACK
//DATA
6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end
6'd22 : SDO=SD[6];
6'd23 : SDO=SD[5];
6'd24 : SDO=SD[4];
6'd25 : SDO=SD[3];
6'd26 : SDO=SD[2];
6'd27 : SDO=SD[1];
6'd28 : SDO=SD[0];
6'd29 : SDO=1'b1;//ACK
//stop
6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end
6'd31 : SCLK=1'b1;
6'd32 : begin SDO=1'b1; END=1; end
endcase
end
endmodule

242
Computer_MiST/Bashkiria2M_MiST/rtl/video_mixer.sv
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@@ -1,242 +0,0 @@
//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 3 bits per component
// For half depth 6 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0,
parameter OSD_COLOR = 3'd4,
parameter OSD_X_OFFSET = 10'd0,
parameter OSD_Y_OFFSET = 10'd0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
// Some systems have multiple resolutions.
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
input ce_pix_actual,
// OSD SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// 0 = HVSync 31KHz, 1 = CSync 15KHz
input scandoubler_disable,
// High quality 2x scaling
input hq2x,
// YPbPr always uses composite sync
input ypbpr,
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
input ypbpr_full,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
// interlace sync. Positive pulses.
input HSync,
input VSync,
// Falling of this signal means start of informative part of line.
// It can be horizontal blank signal.
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
// before first informative pixel.
input line_start,
// MiST video output signals
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_VS,
output VGA_HS
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.r_in(R),
.g_in(G),
.b_in(B),
.hs_out(hs_sd),
.vs_out(vs_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd);
wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd);
wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd);
generate
if(HALF_DEPTH) begin
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [5:0] r = rt;
wire [5:0] g = gt;
wire [5:0] b = bt;
end
endgenerate
wire hs = (scandoubler_disable ? HSync : hs_sd);
wire vs = (scandoubler_disable ? VSync : vs_sd);
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire [5:0] r_out, g_out, b_out;
always @(*) begin
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
end
2: begin // reduce 50% = 1/2
r_out = {1'b0, r[5:1]};
g_out = {1'b0, g[5:1]};
b_out = {1'b0, b[5:1]};
end
3: begin // reduce 75% = 1/4
r_out = {2'b00, r[5:2]};
g_out = {2'b00, g[5:2]};
b_out = {2'b00, b[5:2]};
end
default: begin
r_out = r;
g_out = g;
b_out = b;
end
endcase
end
wire [5:0] red, green, blue;
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
(
.*,
.R_in(r_out),
.G_in(g_out),
.B_in(b_out),
.HSync(hs),
.VSync(vs),
.R_out(red),
.G_out(green),
.B_out(blue)
);
wire [5:0] yuv_full[225] = '{
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
6'd63
};
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
endmodule