diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/README.txt b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/README.txt new file mode 100644 index 00000000..6e73d02f --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/README.txt @@ -0,0 +1,19 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Canyon Bomber from james10952001 +-- Port to MiST by Gehstock +-- 23 November 2018 +-- + +-- +-- Keyboard inputs : +-- ESC : Coin +-- F1 or F2 : Start +-- Joy 1 and Joy 2 : Fire +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- + +todo: GFX Glitch \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/Release/canyon_bomber.rbf b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/Release/canyon_bomber.rbf new file mode 100644 index 00000000..f7ed341c Binary files /dev/null and b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/Release/canyon_bomber.rbf differ diff --git a/Console_MiST/Sega - SG1000/sg1000.qpf b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/canyon_bomber.qpf similarity index 85% rename from Console_MiST/Sega - SG1000/sg1000.qpf rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/canyon_bomber.qpf index c0a2f737..391eeadb 100644 --- a/Console_MiST/Sega - SG1000/sg1000.qpf +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/canyon_bomber.qpf @@ -17,14 +17,14 @@ # -------------------------------------------------------------------------- # # # Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 20:36:09 September 21, 2018 +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 19:51:47 November 12, 2017 # # -------------------------------------------------------------------------- # QUARTUS_VERSION = "13.0" -DATE = "20:36:09 September 21, 2018" +DATE = "19:51:47 November 12, 2017" # Revisions -PROJECT_REVISION = "sg1000" +PROJECT_REVISION = "canyon_bomber" diff --git a/Console_MiST/Sega - SG1000/sg1000.qsf b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/canyon_bomber.qsf similarity index 68% rename from Console_MiST/Sega - SG1000/sg1000.qsf rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/canyon_bomber.qsf index 2577ae9d..d06bdb83 100644 --- a/Console_MiST/Sega - SG1000/sg1000.qsf +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/canyon_bomber.qsf @@ -18,14 +18,14 @@ # # Quartus II 64-Bit # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 20:12:16 September 22, 2018 +# Date created = 21:02:30 September 12, 2018 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: -# sg1000_assignment_defaults.qdf +# dominos_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # @@ -40,53 +40,16 @@ # Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:36:09 SEPTEMBER 21, 2018" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16 OCTOBER 10, 2017" set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -# Classic Timing Assignments +# Pin & Location Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY SG1000_MiST -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# ------------------------- -# start ENTITY(SG1000_MiST) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(SG1000_MiST) -# ----------------------- - -# ------------------------ -# start ENTITY(sg1000_top) set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 set_location_assignment PIN_144 -to VGA_R[5] set_location_assignment PIN_143 -to VGA_R[4] set_location_assignment PIN_142 -to VGA_R[3] @@ -114,16 +77,27 @@ set_location_assignment PIN_88 -to SPI_DI set_location_assignment PIN_126 -to SPI_SCK set_location_assignment PIN_127 -to SPI_SS2 set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_90 -to SPI_SS4 set_location_assignment PIN_13 -to CONF_DATA0 -# end ENTITY(sg1000_top) -# ---------------------- +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name TOP_LEVEL_ENTITY canyon_bomber_mist + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_location_assignment PIN_54 -to CLOCK_27 set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" @@ -131,44 +105,82 @@ set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27 + +# Assembler Assignments +# ===================== +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON + +# SignalTap II Assignments +# ======================== +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sg1000_top.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/SG1000_MiST.sv -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name VHDL_FILE rtl/vga_video.vhd + +# -------------------------- +# start ENTITY(dominos_mist) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(dominos_mist) +# ------------------------ +set_global_assignment -name SYSTEMVERILOG_FILE rtl/canyon_bomber_mist.sv +set_global_assignment -name VHDL_FILE rtl/canyon_bomber.vhd +set_global_assignment -name VHDL_FILE rtl/Char_ROM.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd +set_global_assignment -name VHDL_FILE rtl/whistle.vhd set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name VHDL_FILE rtl/sync_prom.vhd +set_global_assignment -name VHDL_FILE rtl/sync.vhd set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/vdp/vdp_sprites.vhd -set_global_assignment -name VHDL_FILE rtl/vdp/vdp_sprite_shifter.vhd -set_global_assignment -name VHDL_FILE rtl/vdp/vdp_main.vhd -set_global_assignment -name VHDL_FILE rtl/vdp/vdp_cram.vhd -set_global_assignment -name VHDL_FILE rtl/vdp/vdp_background.vhd -set_global_assignment -name VHDL_FILE rtl/vdp/vdp.vhd -set_global_assignment -name VHDL_FILE rtl/psg/psg_tone.vhd -set_global_assignment -name VHDL_FILE rtl/psg/psg_noise.vhd -set_global_assignment -name VHDL_FILE rtl/psg/psg.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80se.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80.vhd -set_global_assignment -name VERILOG_FILE rtl/TTL74_257.v +set_global_assignment -name VHDL_FILE rtl/sound.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv +set_global_assignment -name VHDL_FILE rtl/ram256.vhd +set_global_assignment -name VHDL_FILE rtl/ram1k.vhd +set_global_assignment -name VHDL_FILE rtl/ProgROM4.vhd +set_global_assignment -name VHDL_FILE rtl/prog_rom3L.vhd +set_global_assignment -name VHDL_FILE rtl/prog_rom3H.vhd +set_global_assignment -name VERILOG_FILE rtl/pll.v +set_global_assignment -name VHDL_FILE rtl/playfield.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv +set_global_assignment -name VHDL_FILE rtl/N5_rom.vhd +set_global_assignment -name VHDL_FILE rtl/motor.vhd +set_global_assignment -name VHDL_FILE rtl/motion.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv +set_global_assignment -name VHDL_FILE rtl/M5_rom.vhd set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cart.sv -set_global_assignment -name VHDL_FILE rtl/tv_video.vhd -set_global_assignment -name VHDL_FILE rtl/color_encoder.vhd -set_global_assignment -name VHDL_FILE rtl/yuv_table.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv +set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/canyon_bomber.srf b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/canyon_bomber.srf new file mode 100644 index 00000000..b287316a --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/canyon_bomber.srf @@ -0,0 +1,11 @@ +{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." { } { } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13004 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 113007 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 113015 "" 0 0 "Quartus II" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Console_MiST/Bally - Astrocade_MiST/clean.bat b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/clean.bat similarity index 92% rename from Console_MiST/Bally - Astrocade_MiST/clean.bat rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/clean.bat index 9a939cda..51db334e 100644 --- a/Console_MiST/Bally - Astrocade_MiST/clean.bat +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/clean.bat @@ -3,7 +3,6 @@ del /s *.bak del /s *.orig del /s *.rej del /s *~ -del /s PLLJ_PLLSPE_INFO.txt rmdir /s /q db rmdir /s /q incremental_db rmdir /s /q output_files @@ -19,8 +18,8 @@ for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" cd .. for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt +del /s c5_pin_model_dump.txt +del /s PLLJ_PLLSPE_INFO.txt del /s *.qws del /s *.ppf del /s *.ddb diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ROM256X1.qip b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/Char_ROM.qip similarity index 61% rename from Computer_MiST/Oric Atmos_MiST/rtl/ROM256X1.qip rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/Char_ROM.qip index 4af713a0..eaa8821c 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ROM256X1.qip +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/Char_ROM.qip @@ -1,3 +1,3 @@ set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ROM256X1.vhd"] +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Char_ROM.vhd"] diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/Char_ROM.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/Char_ROM.vhd new file mode 100644 index 00000000..17c5ad01 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/Char_ROM.vhd @@ -0,0 +1,169 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: Char_ROM.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY Char_ROM IS + PORT + ( + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END Char_ROM; + + +ARCHITECTURE SYN OF char_rom IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_aclr_a : STRING; + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock0 : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(3 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "./roms/9492-01.n8.hex", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 1024, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + widthad_a => 10, + width_a => 4, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/9492-01.n8.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +-- Retrieval info: PRIVATE: WidthData NUMERIC "4" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/9492-01.n8.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_ROM.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_ROM.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_ROM.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_ROM.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_ROM_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/rrom.qip b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/M5_rom.qip similarity index 62% rename from Computer_MiST/Oric Atmos_MiST/rtl/rrom.qip rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/M5_rom.qip index 27645f1c..2057957e 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/rrom.qip +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/M5_rom.qip @@ -1,3 +1,3 @@ set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rrom.vhd"] +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "M5_rom.vhd"] diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/BALLY_CHECK.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/M5_rom.vhd similarity index 59% rename from Console_MiST/Bally - Astrocade_MiST/rtl/BALLY_CHECK.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/M5_rom.vhd index dd2f2419..bb02fee1 100644 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/BALLY_CHECK.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/M5_rom.vhd @@ -4,7 +4,7 @@ -- MODULE: altsyncram -- ============================================================ --- File Name: BALLY_CHECK.vhd +-- File Name: M5_rom.vhd -- Megafunction Name(s): -- altsyncram -- @@ -14,7 +14,7 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version -- ************************************************************ @@ -37,47 +37,71 @@ LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; +USE altera_mf.all; -ENTITY BALLY_CHECK IS +ENTITY M5_rom IS PORT ( - address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); - clken : IN STD_LOGIC := '1'; + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock : IN STD_LOGIC := '1'; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); -END BALLY_CHECK; +END M5_rom; -ARCHITECTURE SYN OF bally_check IS +ARCHITECTURE SYN OF m5_rom IS - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_aclr_a : STRING; + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock0 : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; BEGIN - q <= sub_wire0(7 DOWNTO 0); + q <= sub_wire0(3 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_a => "NONE", - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "NORMAL", - init_file => "../roms/balcheck.hex", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "./roms/9506-01.m5.hex", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", - numwords_a => 2048, + numwords_a => 1024, operation_mode => "ROM", outdata_aclr_a => "NONE", - outdata_reg_a => "CLOCK0", - widthad_a => 11, - width_a => 8, + outdata_reg_a => "UNREGISTERED", + widthad_a => 10, + width_a => 4, width_byteena_a => 1 ) PORT MAP ( address_a => address, clock0 => clock, - clocken0 => clken, q_a => sub_wire0 ); @@ -95,9 +119,9 @@ END SYN; -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" --- Retrieval info: PRIVATE: Clken NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" @@ -105,43 +129,41 @@ END SYN; -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "../roms/balcheck.hex" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/9506-01.m5.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" --- Retrieval info: PRIVATE: RegOutput NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "11" --- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +-- Retrieval info: PRIVATE: WidthData NUMERIC "4" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL" --- Retrieval info: CONSTANT: INIT_FILE STRING "../roms/balcheck.hex" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/9506-01.m5.hex" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" --- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" +-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" --- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" --- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 +-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 --- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL BALLY_CHECK.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL BALLY_CHECK.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL BALLY_CHECK.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL BALLY_CHECK.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL BALLY_CHECK_inst.vhd FALSE +-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL M5_rom.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL M5_rom.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL M5_rom.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL M5_rom.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL M5_rom_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/N5_rom.qip b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/N5_rom.qip new file mode 100644 index 00000000..02ab0bf6 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/N5_rom.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "N5_rom.vhd"] diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/N5_rom.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/N5_rom.vhd new file mode 100644 index 00000000..8ae20a51 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/N5_rom.vhd @@ -0,0 +1,169 @@ +-- megafunction wizard: %ROM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: N5_rom.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY N5_rom IS + PORT + ( + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END N5_rom; + + +ARCHITECTURE SYN OF n5_rom IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_aclr_a : STRING; + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock0 : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(3 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "./roms/9505-01.n5.hex", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 1024, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + widthad_a => 10, + width_a => 4, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/9505-01.n5.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +-- Retrieval info: PRIVATE: WidthData NUMERIC "4" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/9505-01.n5.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL N5_rom.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL N5_rom.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL N5_rom.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL N5_rom.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL N5_rom_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ProgROM4.qip b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ProgROM4.qip new file mode 100644 index 00000000..85eca294 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ProgROM4.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ProgROM4.vhd"] diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/cvBios.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ProgROM4.vhd similarity index 82% rename from Console_MiST/Coleco - Vision_MiST/rtl/cvBios.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ProgROM4.vhd index 959f502e..4038c091 100644 --- a/Console_MiST/Coleco - Vision_MiST/rtl/cvBios.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ProgROM4.vhd @@ -4,7 +4,7 @@ -- MODULE: altsyncram -- ============================================================ --- File Name: cvBios.vhd +-- File Name: ProgROM4.vhd -- Megafunction Name(s): -- altsyncram -- @@ -39,17 +39,17 @@ USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; -ENTITY cvBios IS +ENTITY ProgROM4 IS PORT ( - address : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + address : IN STD_LOGIC_VECTOR (10 DOWNTO 0); clock : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); -END cvBios; +END ProgROM4; -ARCHITECTURE SYN OF cvbios IS +ARCHITECTURE SYN OF progrom4 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); @@ -73,7 +73,7 @@ ARCHITECTURE SYN OF cvbios IS width_byteena_a : NATURAL ); PORT ( - address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0); clock0 : IN STD_LOGIC ; q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); @@ -87,15 +87,15 @@ BEGIN address_aclr_a => "NONE", clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", - init_file => "./roms/CVbios.hex", + init_file => "./roms/9496-01.d1.hex", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", - numwords_a => 8192, + numwords_a => 2048, operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", - widthad_a => 13, + widthad_a => 11, width_a => 8, width_byteena_a => 1 ) @@ -129,41 +129,41 @@ END SYN; -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "./roms/CVbios.hex" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/9496-01.d1.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "13" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/CVbios.hex" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/9496-01.d1.hex" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" +-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" --- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 +-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL cvBios.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL cvBios.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL cvBios.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL cvBios.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL cvBios_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ProgROM4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ProgROM4.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ProgROM4.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ProgROM4.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ProgROM4_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/t65.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65.vhd similarity index 93% rename from Computer_MiST/Oric Atmos_MiST/rtl/t65.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65.vhd index b0a11b50..09253fe0 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/t65.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65.vhd @@ -64,8 +64,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library work; - use work.pack_t65.all; + use work.T65_Pack.all; -- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use -- the ready signal to limit the CPU. @@ -183,7 +182,7 @@ begin XF <= XF_i; ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1'; VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1'; - VDA <= '1' when Set_Addr_To_r /= "000" else '0'; -- Incorrect !!!!!!!!!!!! + VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!! VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!! mcode : T65_MCode @@ -334,7 +333,6 @@ begin if (really_rdy = '1') then if MCycle = "000" then if LDA = '1' then - -- assert false report "Chargement A" severity warning; ABC(7 downto 0) <= ALU_Q; end if; if LDX = '1' then @@ -372,13 +370,26 @@ begin when others => end case; end if; - if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then - P(Flag_B) <= '1'; - end if; - if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then - P(Flag_I) <= '1'; - P(Flag_B) <= B_o; + + --if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then + -- P(Flag_B) <= '1'; + --end if; + --if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + -- P(Flag_I) <= '1'; + -- P(Flag_B) <= B_o; + --end if; + + -- B=1 always on the 6502 + P(Flag_B) <= '1'; + if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then + if MCycle = "011" then + -- B=0 in *copy* of P pushed onto the stack + P(Flag_B) <= '0'; + elsif MCycle = "100" then + P(Flag_I) <= '1'; + end if; end if; + if SO_n_o = '1' and SO_n = '0' then P(Flag_V) <= '1'; end if; @@ -484,13 +495,13 @@ begin with Set_BusA_To select - BusA <= DI when "000", - ABC(7 downto 0) when "001", - X(7 downto 0) when "010", - Y(7 downto 0) when "011", - std_logic_vector(S(7 downto 0)) when "100", - P when "101", - (others => '-') when others; + BusA <= DI when "000", + ABC(7 downto 0) when "001", + X(7 downto 0) when "010", + Y(7 downto 0) when "011", + std_logic_vector(S(7 downto 0)) when "100", + P when "101", + (others => '-') when others; with Set_Addr_To_r select A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01", diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/t65_alu.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65_ALU.vhd similarity index 99% rename from Computer_MiST/Oric Atmos_MiST/rtl/t65_alu.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65_ALU.vhd index 38b84a06..b1f6d632 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/t65_alu.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65_ALU.vhd @@ -59,8 +59,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library work; -use work.pack_t65.all; +use work.T65_Pack.all; entity T65_ALU is port( diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/t65_MCode.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65_MCode.vhd similarity index 96% rename from Computer_MiST/Oric Atmos_MiST/rtl/t65_MCode.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65_MCode.vhd index 68f9323e..6c6c864a 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/t65_MCode.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65_MCode.vhd @@ -2,6 +2,7 @@ -- T65(b) core. In an effort to merge and maintain bug fixes .... -- -- +-- Ver 302 minor timing fixes -- Ver 301 Jump timing fixed -- Ver 300 Bugfixes by ehenciak added -- MikeJ March 2005 @@ -64,8 +65,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library work; -use work.pack_t65.all; +use work.T65_Pack.all; entity T65_MCode is port( @@ -109,13 +109,13 @@ begin with IR(7 downto 5) select Branch <= not P(Flag_N) when "000", - P(Flag_N) when "001", - not P(Flag_V) when "010", - P(Flag_V) when "011", - not P(Flag_C) when "100", - P(Flag_C) when "101", - not P(Flag_Z) when "110", - P(Flag_Z) when others; + P(Flag_N) when "001", + not P(Flag_V) when "010", + P(Flag_V) when "011", + not P(Flag_C) when "100", + P(Flag_C) when "101", + not P(Flag_Z) when "110", + P(Flag_Z) when others; process (IR, MCycle, P, Branch, Mode) begin @@ -144,18 +144,18 @@ begin Write <= '0'; AddY <= '0'; - case IR(7 downto 5) is + case IR(7 downto 5) is when "100" => --{{{ case IR(1 downto 0) is when "00" => Set_BusA_To <= "011"; -- Y - Write_Data <= "011"; -- Y + Write_Data <= "011"; -- Y when "10" => Set_BusA_To <= "010"; -- X - Write_Data <= "010"; -- X + Write_Data <= "010"; -- X when others => - Write_Data <= "001"; -- A + Write_Data <= "001"; -- A end case; --}}} when "101" => @@ -197,13 +197,13 @@ begin end case; --}}} when others => - end case; + end case; - if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then + if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then Set_BusA_To <= "000"; -- DI - end if; + end if; - case IR(4 downto 0) is + case IR(4 downto 0) is when "00000" | "01000" | "01010" | "11000" | "11010" => --{{{ -- Implied @@ -309,11 +309,15 @@ begin case to_integer(unsigned(MCycle)) is when 1 => case IR(7 downto 4) is - when "0000" => Write_Data <= "101"; -- P - when "0100" => Write_Data <= "001"; -- A - when "0101" => Write_Data <= "011"; -- Y - when "1101" => Write_Data <= "010"; -- X - when others => + when "0000" => + Write_Data <= "101"; -- P + when "0100" => + Write_Data <= "001"; -- A + when "0101" => + Write_Data <= "011"; -- Y + when "1101" => + Write_Data <= "010"; -- X + when others => end case; Write <= '1'; Set_Addr_To <= "01"; -- S @@ -591,13 +595,14 @@ begin when others => end case; else - LCycle <= "101"; + --LCycle <= "101"; + LCycle <= "100"; -- mikej case to_integer(unsigned(MCycle)) is - when 2 => + when 1 => Jump <= "01"; LDDI <= '1'; LDBAL <= '1'; - when 3 => + when 2 => LDBAH <= '1'; if Mode /= "00" then Jump <= "10"; -- DIDL @@ -605,7 +610,7 @@ begin if Mode = "00" then Set_Addr_To <= "11"; -- BA end if; - when 4 => + when 3 => LDDI <= '1'; if Mode = "00" then Set_Addr_To <= "11"; -- BA @@ -613,7 +618,7 @@ begin else Jump <= "01"; end if; - when 5 => + when 4 => Jump <= "10"; -- DIDL when others => end case; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/pack_t65.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65_Pack.vhd similarity index 99% rename from Computer_MiST/Oric Atmos_MiST/rtl/pack_t65.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65_Pack.vhd index fbe4afe1..e025e1bf 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/pack_t65.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/T65/T65_Pack.vhd @@ -57,7 +57,7 @@ library IEEE; use IEEE.std_logic_1164.all; -package pack_t65 is +package T65_Pack is constant Flag_C : integer := 0; constant Flag_Z : integer := 1; @@ -114,4 +114,4 @@ package pack_t65 is ); end component; -end; \ No newline at end of file +end; diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/build_id.sv b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/build_id.sv new file mode 100644 index 00000000..e8c4ed1b --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/build_id.sv @@ -0,0 +1,2 @@ +`define BUILD_DATE "181123" +`define BUILD_TIME "010645" diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/build_id.tcl b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/build_id.tcl similarity index 100% rename from Console_MiST/Nintendo - Gameboy_MiST/rtl/build_id.tcl rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/build_id.tcl diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/canyon_bomber.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/canyon_bomber.vhd new file mode 100644 index 00000000..4f3810a9 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/canyon_bomber.vhd @@ -0,0 +1,240 @@ +-- Top level file for Atari Canyon Bomber +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple +-- See Canyon Bomber manual for video output details. Resistor values listed here have been scaled +-- for 3.3V logic. +-- R44 1.2k Ohm +-- R43 1.2k Ohm +-- R51 1.2k Ohm +-- R42 330R + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +entity canyon_bomber is +port( + clk_12 : in std_logic; -- 50MHz input clock + Reset_I : in std_logic; -- Reset button (Active low) + Video : out std_logic_vector(1 downto 0); + Vblank_O : out std_logic; + HBlank_O : out std_logic; + HSync_O : out std_logic; + VSync_O : out std_logic; + Sync_O : out std_logic; -- Composite sync output (1.2k) + Audio1_O : out std_logic_vector(6 downto 0); -- Player 1 audio + Audio2_O : out std_logic_vector(6 downto 0); -- Player 2 audio + Coin1_I : in std_logic; -- Coin switches (All inputs are active-low) + Coin2_I : in std_logic; + Start1_I : in std_logic; -- Player 1 and 2 Start buttons + Start2_I : in std_logic; + Fire1_I : in std_logic; -- Fire buttons + Fire2_I : in std_logic; + Slam_I : in std_logic; -- Slam switch + Test_I : in std_logic; -- Self-test switch + Lamp1_O : out std_logic; -- Player 1 and 2 start button LEDs + Lamp2_O : out std_logic + ); +end canyon_bomber; + +architecture rtl of canyon_bomber is + +signal clk_6 : std_logic; +signal Ena_3k : std_logic; +signal phi1 : std_logic; +signal phi2 : std_logic; +signal reset_n : std_logic; + +signal Hcount : std_logic_vector(8 downto 0) := (others => '0'); +signal H256_s : std_logic; +signal Vcount : std_logic_vector(7 downto 0) := (others => '0'); +signal Vreset : std_logic; +signal HBlank : std_logic; +signal VBlank : std_logic; +signal HSync : std_logic; +signal VSync : std_logic; +signal Vblank_s : std_logic; +signal Vblank_n_s : std_logic; + +signal CompBlank_n_s : std_logic; + +signal CompSync_n_s : std_logic; + +signal WhitePF_n : std_logic; +signal BlackPF_n : std_logic; + +signal Adr : std_logic_vector(9 downto 0); +signal DBus : std_logic_vector(7 downto 0); +signal Display : std_logic_vector(7 downto 0); + +signal RnW : std_logic; +signal Write_n : std_logic; +signal NMI_n : std_logic; + +signal RAM_n : std_logic; +signal Sync_n : std_logic; +signal Switch_n : std_logic; +signal Display_n : std_logic; +signal TimerReset_n : std_logic; + +signal Attract1 : std_logic; +signal Attract2 : std_logic; +signal Skid1 : std_logic; +signal Skid2 : std_logic; +signal Lamp1 : std_logic; +signal Lamp2 : std_logic; + +signal Motor1_n : std_logic; +signal Motor2_n : std_logic; +signal Whistle1 : std_logic; +signal Whistle2 : std_logic; +signal Explode_n : std_logic; +signal Ship1_n : std_logic; +signal Ship2_n : std_logic; +signal Shell1_n : std_logic; +signal Shell2_n : std_logic; + +signal DIP_Sw : std_logic_vector(8 downto 1); + + +begin +-- Configuration DIP switches, these can be brought out to external switches if desired +-- See Canyon Bomber manual for complete information. Active low (0 = On, 1 = Off) +-- 8 7 Game Cost (10-1 Coin per player, 11-Two coins per player, 01-Two players per coin, 00-Free Play) +-- 6 5 Misses Per Play (00-Three, 01-Four, 10-Five, 11-Six) +-- 4 3 Not Used +-- 2 1 Language (00-English, 10-French, 01-Spanish, 11-German) +-- +DIP_Sw <= "10100000"; -- Config dip switches + + +Vid_sync: entity work.synchronizer +port map( + clk_12 => clk_12, + clk_6 => clk_6, + hcount => hcount, + vcount => vcount, + hsync => HSync, + hblank => HBlank, + vblank_s => vblank_s, + vblank_n_s => vblank_n_s, + vblank => VBlank, + vsync => VSync, + vreset => vreset + ); + + +Background: entity work.playfield +port map( + clk6 => clk_6, + display => display, + HCount => HCount, + VCount => VCount, + HBlank => HBlank, + H256_s => H256_s, + VBlank => VBlank, + VBlank_n_s => Vblank_n_s, + HSync => Hsync, + VSync => VSync, + CompSync_n_s => CompSync_n_s, + CompBlank_n_s => CompBlank_n_s, + WhitePF_n => WhitePF_n, + BlackPF_n => BlackPF_n + ); + + +Motion_Objects: entity work.motion +port map( + CLK6 => clk_6, + CLK12 => clk_12, + PHI2 => phi2, + DISPLAY => Display, + H256_s => H256_s, + HSync => HSync, + VCount => VCount, + HCount => HCount, + Shell1_n => Shell1_n, + Shell2_n => Shell2_n, + Ship1_n => Ship1_n, + Ship2_n => Ship2_n + ); + + +CPU: entity work.cpu_mem +port map( + Clk12 => clk_12, + Clk6 => clk_6, + Ena_3k => Ena_3k, + Reset_I => Reset_I, + Reset_n => reset_n, + VBlank => VBlank, + VCount => VCount, + HCount => HCount, + Test_n => Test_I, + Coin1_n => Coin1_I, + Coin2_n => Coin2_I, + Start1_n => Start1_I, + Start2_n => Start2_I, + Fire1_n => Fire1_I, + Fire2_n => Fire2_I, + Slam_n => Slam_I, + DIP_Sw => DIP_Sw, + Motor1_n => Motor1_n, + Motor2_n => Motor2_n, + Explode_n => Explode_n, + Whistle1 => Whistle1, + Whistle2 => Whistle2, + Player1Lamp => Lamp1_O, + Player2Lamp => Lamp2_O, + Attract1 => Attract1, + Attract2 => Attract2, + Phi1_o => Phi1, + Phi2_o => Phi2, + DBus => DBus, + Display => Display + ); + + +Sound: entity work.audio +port map( + Clk_6 => Clk_6, + Ena_3k => Ena_3k, + Reset_n => Reset_n, + Motor1_n => Motor1_n, + Motor2_n => Motor2_n, + Whistle1 => Whistle1, + Whistle2 => Whistle2, + Explode_n => Explode_n, + Attract1 => Attract1, + Attract2 => Attract2, + DBus => DBus, + VCount => VCount, + P1_audio => Audio1_O, + P2_audio => Audio2_O + ); + + +-- Video mixing +Video(0) <= ( BlackPF_n and Ship1_n and Shell1_n and CompBlank_n_s); +Video(1) <= not(WhitePF_n and Ship2_n and Shell2_n); +Sync_O <= CompSync_n_s; +HBlank_O <= HBlank; +VBlank_O <= VBlank; +HSync_O <= HSync; +VSync_O <= VSync; +end rtl; diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/canyon_bomber_mist.sv b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/canyon_bomber_mist.sv new file mode 100644 index 00000000..1f15e63d --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/canyon_bomber_mist.sv @@ -0,0 +1,150 @@ +//Canyon Bomber from james10952001 Port to Mist by Gehstock + +module canyon_bomber_mist( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.sv" + +localparam CONF_STR = { + "Dominos;;", + "O1,Self_Test,Off,On;", + "O2,Slam,Off,On;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [11:0] kbjoy; +wire [7:0] joy0; +wire [7:0] joy1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [6:0] audio1, audio2; +wire [1:0] video; + +wire clk_24, clk_12, clk_6; +wire locked; +pll pll +( + .inclk0(CLOCK_27), + .c0(clk_24),//24.192 + .c1(clk_12),//12.096 + .c2(clk_6),//6.048 + .locked(locked) +); + +assign LED = 1'b0; + +canyon_bomber canyon_bomber ( + .clk_12(clk_12), + .Reset_I(~(status[0] | status[6] | buttons[1])), + .Video(video), + .Sync_O(), + .HSync_O(hs), + .VSync_O(vs), + .Audio1_O(audio1), + .Audio2_O(audio2), + .Coin1_I(~kbjoy[7]), + .Coin2_I(~kbjoy[7]), + .Start1_I(~(kbjoy[5])), + .Start2_I(~(kbjoy[6])), + .Fire1_I(~joy0[4]), + .Fire2_I(~joy1[4]), + .Slam_I(~status[2]), + .Test_I(~status[1]), + .Lamp1_O(), + .Lamp2_O() + ); + +dac dacl ( + .CLK(clk_24), + .RESET(1'b0), + .DACin(audio1), + .DACout(AUDIO_L) + ); + +dac dacr ( + .CLK(clk_24), + .RESET(1'b0), + .DACin(audio2), + .DACout(AUDIO_R) + ); + +wire hs, vs; +wire hb, vb; +wire blankn = ~(hb | vb); +video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer +( + .clk_sys(clk_24), + .ce_pix(clk_6), + .ce_pix_actual(clk_6), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({video,video,video}), + .G({video,video,video}), + .B({video,video,video}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_24 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joy0 ), + .joystick_1 (joy1 ), + .status (status ) +); + +keyboard keyboard( + .clk(clk_24), + .reset(), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + .joystick(kbjoy) + ); + + +endmodule diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/cpu_mem.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/cpu_mem.vhd new file mode 100644 index 00000000..e3013876 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/cpu_mem.vhd @@ -0,0 +1,409 @@ +-- CPU, RAM, ROM and address decoder for Atari Canyon Bomber +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity CPU_mem is +port( + CLK12 : in std_logic; + CLK6 : in std_logic; -- 6MHz on schematic + Ena_3k : buffer std_logic; -- 3kHz clock enable, used by sound circuit + Reset_I : in std_logic; + Reset_n : buffer std_logic; + VBlank : in std_logic; + VCount : in std_logic_vector(7 downto 0); + HCount : in std_logic_vector(8 downto 0); + Test_n : in std_logic; + Coin1_n : in std_logic; + Coin2_n : in std_logic; + Start1_n : in std_logic; + Start2_n : in std_logic; + Fire1_n : in std_logic; + Fire2_n : in std_logic; + Slam_n : in std_logic; + DIP_Sw : in std_logic_vector(8 downto 1); + Motor1_n : out std_logic; + Motor2_n : out std_logic; + Explode_n : out std_logic; + Whistle1 : out std_logic; + Whistle2 : out std_logic; + Player1Lamp : out std_logic; + Player2Lamp : out std_logic; + Attract1 : out std_logic; + Attract2 : out std_logic; + PHI1_O : out std_logic; + PHI2_O : out std_logic; + DBus : buffer std_logic_vector(7 downto 0); + DISPLAY : out std_logic_vector(7 downto 0) + ); +end CPU_mem; + +architecture rtl of CPU_mem is + +signal PHI1 : std_logic; +signal PHI2 : std_logic; +signal Q5 : std_logic; +signal Q6 : std_logic; +signal A7_2 : std_logic; +signal A7_5 : std_logic; +signal A7_7 : std_logic; + +signal A8_6 : std_logic; + +signal H256 : std_logic; +signal H256_n : std_logic; +signal H128 : std_logic; +signal H64 : std_logic; +signal H32 : std_logic; +signal H16 : std_logic; +signal H8 : std_logic; +signal H4 : std_logic; + +signal V128 : std_logic; +signal V64 : std_logic; +signal V32 : std_logic; +signal V16 : std_logic; +signal V8 : std_logic; + +signal IRQ_n : std_logic; +signal NMI_n : std_logic; +signal RW_n : std_logic; +signal RnW : std_logic; +signal ADR : std_logic_vector(15 downto 0); +signal cpuDin : std_logic_vector(7 downto 0); +signal cpuDout : std_logic_vector(7 downto 0); + +signal ROM1_dout : std_logic_vector(7 downto 0); +signal ROM2_dout : std_logic_vector(7 downto 0); +signal ROM3_dout : std_logic_vector(7 downto 0); +signal ROM4_dout : std_logic_vector(7 downto 0); +signal ROM_dout : std_logic_vector(7 downto 0); + +signal ROM1 : std_logic; +signal ROM2 : std_logic; +signal ROM3 : std_logic; +signal ROM4 : std_logic; +signal ROM_ce : std_logic; + +signal cpuRAM_dout : std_logic_vector(7 downto 0); +signal Vram_dout : std_logic_vector(7 downto 0); +signal RAM_addr : std_logic_vector(9 downto 0) := (others => '0'); +signal VraM_Din : std_logic_vector(7 downto 0); +signal Vram_addr : std_logic_vector(9 downto 0) := (others => '0'); +signal RAM_dout : std_logic_vector(7 downto 0); +signal addRAM_dout : std_logic_vector(7 downto 0); +signal RAM_we : std_logic := '0'; +signal RAM_RW_n : std_logic := '1'; +signal RAM_ce_n : std_logic := '1'; +signal RAM_n : std_logic := '1'; +signal WRAM : std_logic := '0'; +signal WRAM_n : std_logic := '0'; +signal WRITE_n : std_logic := '1'; + +signal Display_n : std_logic := '1'; + +signal Timer_Reset_n : std_logic := '1'; +signal Options_n : std_logic; +signal Switch_n : std_logic := '1'; + +signal WDog_Clear : std_logic := '0'; +signal WDog_count : std_logic_vector(3 downto 0) := "0000"; + +signal Inputs : std_logic_vector(2 downto 0) := "111"; +signal Switchmux1_n : std_logic := '1'; +signal K8_y : std_logic_vector(1 downto 0); + +signal H7_y : std_logic_vector(1 downto 0); + +signal ena_count : std_logic_vector(10 downto 0) := (others => '0'); +signal ena_750k : std_logic; + + +begin + +H8 <= HCount(3); +H16 <= HCount(4); +H32 <= HCount(5); +H64 <= HCount(6); +H128 <= HCount(7); +H256 <= HCount(8); +H256_n <= (not HCount(8)); + +V8 <= VCount(3); +V16 <= VCount(4); +V32 <= VCount(5); +V64 <= VCount(6); +V128 <= VCount(7); + + +-- In the original hardware the CPU is clocked by a signal derived from 4H from the horizontal +-- line counter. This attemps to do things in a manner that is more proper for a synchronous +-- FPGA design using the main 6MHz clock in conjunction with a 750kHz clock enable for the CPU. +-- This also creates a 3kHz clock enable used by the sound module. +Clock_ena: process(Clk6) +begin + if rising_edge(Clk6) then + ena_count <= ena_count + "1"; + ena_750k <= '0'; + if (ena_count(2 downto 0) = "000") then --100 + ena_750k <= '1'; -- 750 kHz + end if; + ena_3k <= '0'; + if (ena_count(10 downto 0) = "00000000000") then + ena_3k <= '1'; + end if; + end if; +end process; + + +-- Watchdog timer, counts pulses from V128 and resets CPU if not cleared by Timer_Reset_n +Watchdog: process(V128, WDog_Clear, Reset_I) +begin + if Reset_I = '0' then + WDog_count <= "1111"; + elsif Wdog_Clear = '1' then + WDog_count <= "0000"; + elsif rising_edge(V128) then + WDog_count <= WDog_count + 1; + end if; +end process; +WDog_Clear <= (Test_n nand Timer_Reset_n); +Reset_n <= (not WDog_count(3)); + + +CPU: entity work.T65 +port map( + Enable => ena_750k, + Mode => "00", + Res_n => reset_n, + Clk => Clk6, + Rdy => '1', + Abort_n => '1', + IRQ_n => '1', + NMI_n => NMI_n, + SO_n => '1', + R_W_n => RW_n, + A(15 downto 0) => Adr, + DI => cpuDin, + DO => cpuDout + ); + + + +DBUS <= cpuDout; + +RnW <= (not RW_n); + +NMI_n <= not (Vblank and Test_n); + + +-- CPU clock -- Using 750kHz enable now, should probably derive Phi2 signal from that +H4 <= Hcount(2); +CPU_clock: process(clk12, H4, Q5, Q6) +begin + if rising_edge(clk12) then + Q5 <= H4; + Q6 <= Q5; + end if; + phi1 <= not (Q5 or Q6); --? +end process; + +PHI2 <= (not PHI1); +PHI1_O <= PHI1; +PHI2_O <= PHI2; + + +A8_6 <= not(RnW and PHI2 and H4 and WRITE_n); +A7: process(clk12, A8_6) -- Shift register chain of 4 DFF's clocked by clk12, creates a delayed WRITE_n +begin + if rising_edge(clk12) then + A7_2 <= A8_6; + A7_5 <= A7_2; + A7_7 <= A7_5; + WRITE_n <= A7_7; + end if; +end process; + + +-- Program ROMs +J1: entity work.prog_rom3L +port map( + clock => clk6, + address => Adr(9 downto 0), + q => rom3_dout(3 downto 0) + ); + +P1: entity work.prog_rom3H +port map( + clock => clk6, + address => Adr(9 downto 0), + q => rom3_dout(7 downto 4) + ); + +D1: entity work.progROM4 +port map( + clock => clk6, + address => Adr(10 downto 0), + q => rom4_dout + ); + +-- ROM data mux +ROM_dout <= ROM3_dout when ROM3 = '1' and Adr(10) = '1' else + ROM4_dout when ROM4 = '1' else + x"FF"; + + +-- CPU RAM +-- 256x4 RAM chips at E7 and D7 form zero-page memory +ED7: entity work.ram256 +port map( + clock => Clk6, + address => Adr(7 downto 0), + wren => (not write_n) and (not WRAM_n), + data => CPUDout, + q => addRAM_dout + ); + + +-- Video RAM +-- Access is multiplexed between the CPU and video hardware depending on the state of Phi2 +Video_RAM: entity work.ram1k +port map( + clock => Clk12, + address => Vram_addr, + wren => ram_we, + data => CPUDout, + q => VRAM_Dout + ); + +--Video RAM is addressed by video circuitry when Phi2 is low and by CPU when Phi2 is high +Vram_addr <= (V128 or H256_n) & (V64 or H256_n) & (V32 or H256_n) & (V16 or H256_n) & (V8 and H256) & H128 & H64 & H32 & H16 & H8 + when phi2 = '0' else Adr(9 downto 0); + + +-- Original RAM has both WE and CE which are selected by K2 according to the state of the phase 2 clock +-- Altera block RAM has active high WE, original RAM had active low WE +ram_we <= (not Write_n) and (not Display_n) and Phi2; + + +-- Rising edge of phi2 clock latches output of VRAM data bus +F5: process(phi2, VRam_Dout) +begin + if rising_edge(phi2) then + display <= Vram_dout; + end if; +end process; + + +-- Address decoder +-- 9301 decoder at F6 +Display_n <= '0' when Adr(13 downto 11) = "001" else '1'; +Switch_n <= '0' when Adr(13 downto 11) = "010" else '1'; +Options_n <= '0' when Adr(13 downto 11) = "011" else '1'; +ROM3 <= '1' when Adr(13 downto 11) = "110" else '0'; +ROM4 <= '1' when Adr(13 downto 11) = "111" else '0'; +RAM_n <= '0' when Adr(13 downto 11) = "001" and RnW = '0' else '1'; +ROM_ce <= (ROM3 or ROM4); + +-- 9321 Decoder at E6 +WRAM_n <= '0' when Adr(13 downto 9) = "00000" else '1'; +Motor1_n <= '0' when Write_n = '0' and Adr(13 downto 9) = "00010" and Adr(8) = '0' and Adr(0) = '0' else '1'; +Motor2_n <= '0' when Write_n = '0' and Adr(13 downto 9) = "00010" and Adr(8) = '0' and Adr(0) = '1' else '1'; +Explode_n <= '0' when Write_n = '0' and Adr(13 downto 9) = "00010" and Adr(8) = '1' and Adr(0) = '0' else '1'; +Timer_Reset_n <= '0' when Write_n = '0' and Adr(13 downto 9) = "00010" and Adr(8) = '1' and Adr(0) = '1' else '1'; + +-- 9334 addressable latch at C7, this drives outputs +C7: process(clk6, Reset_n, Adr) +begin + if (Reset_n = '0') then + Whistle1 <= '0'; -- Shell whistle sound 1 + Whistle2 <= '0'; -- Shell whistle sound 2 + Player1Lamp <= '0'; -- Player 1 Start LED + Player2Lamp <= '0'; -- Player 2 Start LED + Attract1 <= '0'; -- Attract1 signal + Attract2 <= '0'; -- Attract2 signal + elsif rising_edge(clk6) then + -- This next line models part of the address decoder that enables this latch + if (Write_n = '0' and ADR(13 downto 9) = "00011") then + case Adr(8 downto 7) & Adr(0) is + when "000" => Whistle1 <= Adr(1); + when "001" => Whistle2 <= Adr(1); + when "010" => Player1Lamp <= Adr(1); + when "011" => Player2Lamp <= Adr(1); + when "100" => Attract1 <= Adr(1); + when "101" => Attract2 <= Adr(1); + when others => null; + end case; + end if; + end if; +end process; + + +-- Input switches +J8: process(Adr, Coin1_n, Coin2_n, Start1_n, Start2_n, Test_n, VBlank, Slam_n) +begin + case Adr(2 downto 0) is -- Uses inverted output of mux + when "000" => Switchmux1_n <= (not Coin1_n); + when "001" => Switchmux1_n <= (not Coin2_n); + when "010" => Switchmux1_n <= (not Start1_n); + when "011" => Switchmux1_n <= (not Start2_n); + when "100" => Switchmux1_n <= (not Test_n); + when "101" => Switchmux1_n <= (not VBlank); + when "110" => Switchmux1_n <= '0'; + when "111" => Switchmux1_n <= (not Slam_n); + when others => Switchmux1_n <= '1'; + end case; +end process; + +-- 74LS153 dual selector/multiplexer at H7 reads configuration DIP switches +H7: process(Adr, DIP_Sw) +begin + case Adr(1 downto 0) is + when "00" => H7_y <= DIP_Sw(8) & DIP_Sw(7); + when "01" => H7_y <= DIP_Sw(6) & DIP_Sw(5); + when "10" => H7_y <= DIP_Sw(4) & DIP_Sw(3); + when "11" => H7_y <= DIP_Sw(2) & DIP_Sw(1); + when others => H7_y <= "11"; + end case; +end process; + +-- 74LS153 dual selector/multiplexer at K8 reads Fire buttons +K8: process(Adr, Fire1_n, Fire2_n) +begin + case Adr(1 downto 0) is + when "00" => K8_y <= '1' & '1'; + when "01" => K8_y <= '1' & '1'; + when "10" => K8_y <= '1' & Fire1_n; + when "11" => K8_y <= '1' & Fire2_n; + when others => K8_y <= "11"; + end case; +end process; +-- Steer and Thrust inputs are shown on schematic connected to this selector but +-- not used by Canyon Bomber. Listing here for completeness +-- Steer1A_n, Steer1B_n, Steer2A_n, Steer2B_n, Thrust1_n, Thrust2_n + + +-- CPU Din mux +cpuDin <= ROM_dout when rom_ce = '1' else + Vram_dout when RAM_n = '0' and Display_n = '0' else + addRAM_dout when WRAM_n = '0' else + Switchmux1_n & "11111" & K8_y(1 downto 0) when Switch_n = '0' else + "111111" & H7_y when Options_n = '0' else + x"FF"; + +end rtl; diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/dac.sv b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/dac.sv similarity index 94% rename from Console_MiST/Nintendo - Gameboy_MiST/rtl/dac.sv rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/dac.sv index 5dea333e..22ae8f07 100644 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/dac.sv +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/dac.sv @@ -3,7 +3,7 @@ // // MSBI is the highest bit number. NOT amount of bits! // -module dac #(parameter MSBI=15, parameter INV=1'b1) +module dac #(parameter MSBI=6, parameter INV=1'b1) ( output reg DACout, //Average Output feeding analog lowpass input [MSBI:0] DACin, //DAC input (excess 2**MSBI) diff --git a/Console_MiST/Sega - SG1000/rtl/dpram.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/dpram.vhd similarity index 100% rename from Console_MiST/Sega - SG1000/rtl/dpram.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/dpram.vhd diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/greybox_tmp/cbx_args.txt b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/greybox_tmp/cbx_args.txt new file mode 100644 index 00000000..a5666710 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/greybox_tmp/cbx_args.txt @@ -0,0 +1,16 @@ +ADDRESS_ACLR_A=NONE +CLOCK_ENABLE_INPUT_A=BYPASS +CLOCK_ENABLE_OUTPUT_A=BYPASS +INIT_FILE=./roms/9496-01.d1.hex +INTENDED_DEVICE_FAMILY="Cyclone III" +NUMWORDS_A=2048 +OPERATION_MODE=ROM +OUTDATA_ACLR_A=NONE +OUTDATA_REG_A=CLOCK0 +WIDTHAD_A=11 +WIDTH_A=8 +WIDTH_BYTEENA_A=1 +DEVICE_FAMILY="Cyclone III" +address_a +clock0 +q_a diff --git a/Computer_MiST/Galaksija_MiST/rtl/hq2x.sv b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/hq2x.sv similarity index 100% rename from Computer_MiST/Galaksija_MiST/rtl/hq2x.sv rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/hq2x.sv diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/keyboard.sv b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/keyboard.sv similarity index 83% rename from Console_MiST/Nintendo - Gameboy_MiST/rtl/keyboard.sv rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/keyboard.sv index a6d2ba94..b1d63764 100644 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/keyboard.sv +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/keyboard.sv @@ -7,7 +7,7 @@ module keyboard input ps2_kbd_clk, input ps2_kbd_data, - output reg[7:0] joystick + output reg[11:0] joystick ); reg [11:0] shift_reg = 12'hFFF; @@ -33,10 +33,15 @@ always @(negedge clk) begin 'h72: joystick[2] <= ~release_btn; // arrow down 'h6B: joystick[1] <= ~release_btn; // arrow left 'h74: joystick[0] <= ~release_btn; // arrow right - + //player2 + 'h1D: joystick[11] <= ~release_btn; // W + 'h1B: joystick[10] <= ~release_btn; // S + 'h1C: joystick[9] <= ~release_btn; // A + 'h23: joystick[8] <= ~release_btn; // D + 'h29: joystick[4] <= ~release_btn; // Space - 'h11: joystick[5] <= ~release_btn; // Left Alt - 'h0D: joystick[6] <= ~release_btn; // Tab + 'h05: joystick[5] <= ~release_btn; // F1 + 'h06: joystick[6] <= ~release_btn; // F2 'h76: joystick[7] <= ~release_btn; // Escape endcase end diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/mist_io.sv b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/mist_io.sv similarity index 100% rename from Console_MiST/Nintendo - Gameboy_MiST/rtl/mist_io.sv rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/mist_io.sv diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/motion.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/motion.vhd new file mode 100644 index 00000000..4a2a5603 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/motion.vhd @@ -0,0 +1,388 @@ +-- Motion object generation circuitry for Atari Canyon Bomber +-- This generates the two player ships (blimps or planes) and +-- the bomb shells dropped by the ships. +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity motion is +port( + CLK6 : in std_logic; + CLK12 : in std_logic; + PHI2 : in std_logic; + DISPLAY : in std_logic_vector(7 downto 0); + H256_s : in std_logic; -- 256H* on schematic + HSync : in std_logic; + VCount : in std_logic_vector(7 downto 0); + HCount : in std_logic_vector(8 downto 0); + Shell1_n : out std_logic; + Shell2_n : out std_logic; + Ship1_n : out std_logic; + Ship2_n : out std_logic + ); +end motion; + +architecture rtl of motion is + +signal phi0 : std_logic; + +signal LDH1_n : std_logic; +signal LDH2_n : std_logic; +signal LDH3_n : std_logic; +signal LDH4_n : std_logic; + +signal LDV1A_n : std_logic; +signal LDV1B_n : std_logic; +signal LDV1C_n : std_logic; +signal LDV1D_n : std_logic; + +signal LDV2A_n : std_logic; +signal LDV2B_n : std_logic; +signal LDV2C_n : std_logic; +signal LDV2D_n : std_logic; + +signal VSL2_n : std_logic; +signal VSL1_n : std_logic; +signal VSP1_n : std_logic; +signal VSP2_n : std_logic; + +signal KH5_sum : std_logic_vector(7 downto 0) := x"00"; +signal K4_8 : std_logic; + +signal HSync_n : std_logic; + +signal H256_n : std_logic; +signal H256 : std_logic; +signal H64 : std_logic; +signal H32 : std_logic; +signal H16 : std_logic; +signal H8 : std_logic; +signal H4 : std_logic; +signal H2 : std_logic; +signal H1 : std_logic; + +signal L5_reg : std_logic_vector(4 downto 0); + +signal J8_3 : std_logic; +signal J8_6 : std_logic; + +signal M9_in : std_logic_vector(3 downto 0); +signal M9_out : std_logic_vector(9 downto 0); + +signal VidROMAdr : std_logic_vector(9 downto 0); +signal VidROMdout : std_logic_vector(7 downto 0); +signal Vid : std_logic_vector(7 downto 0); + +signal HShell1Win_n : std_logic; +signal HShell2Win_n : std_logic; +signal ShipWin1_n : std_logic; +signal ShipWin2_n : std_logic; +signal Ship1_Hpos : std_logic_vector(7 downto 0) := x"00"; +signal Ship2_Hpos : std_logic_vector(7 downto 0) := x"00"; +signal Shell1_Hpos : std_logic_vector(7 downto 0) := x"00"; +signal Shell2_Hpos : std_logic_vector(7 downto 0) := x"00"; +signal Ship1_reg : std_logic_vector(31 downto 0) := (others => '0'); +signal Ship2_reg : std_logic_vector(31 downto 0) := (others => '0'); + +signal J4_8 : std_logic; +signal R9_Qa : std_logic; +signal R9_Qb : std_logic; + +signal LDV1_dec : std_logic_vector(3 downto 0); +signal LDV2_dec : std_logic_vector(3 downto 0); + + + +begin +phi0 <= phi2; + +H1 <= HCount(0); +H2 <= HCount(1); +H4 <= Hcount(2); +H8 <= Hcount(3); +H16 <= Hcount(4); +H32 <= Hcount(5); +H64 <= Hcount(6); +H256 <= Hcount(8); + +HSync_n <= (not Hsync); + +-- Vertical line comparator +KH5_sum <= Display + VCount; +K4_8 <= not(KH5_sum(7) and KH5_sum(6) and KH5_sum(5) and KH5_sum(4) and (not H256) and H8); + + +-- D type flip-flops in L3 and H4 latch data from vertical line comparator +L5: process(phi2, K4_8, KH5_sum(3 downto 0)) +begin + if rising_edge(phi2) then + L5_reg <= K4_8 & KH5_sum(3 downto 0); + end if; +end process; + +J4_8 <= not ((not L5_reg(3)) and L5_reg(2) and L5_reg(1)); + + +-- The shells are single pixels created by a pair of flip-flops +-- rather than sprites stored in ROM. +-- Black shell +R9a: process(VSL1_n) +begin + if rising_edge(VSL1_n) then + R9_Qa <= J4_8; + end if; +end process; + +-- White shell +R9b: process(Hsync_n, VSL2_n) +begin + if Hsync_n = '0' then + R9_Qb <= '1'; + elsif rising_edge(VSL2_n) then + R9_Qb <= J4_8; + end if; +end process; + +Shell1_n <= R9_Qa or HShell1Win_n; +Shell2_n <= R9_Qb or HShell2Win_n; + + + +M9_in <= (L5_reg(4) or H4) & H64 & H32 & H16; +M9: process(clk6, M9_in) +begin + if falling_edge(clk6) then + case M9_in is + when "0000" => + M9_out <= "1111111110"; + when "0001" => + M9_out <= "1111111101"; + when "0010" => + M9_out <= "1111111011"; + when "0011" => + M9_out <= "1111110111"; + when "0100" => + M9_out <= "1111101111"; + when "0101" => + M9_out <= "1111011111"; + when "0110" => + M9_out <= "1110111111"; + when "0111" => + M9_out <= "1101111111"; + when "1000" => + M9_out <= "1011111111"; + when "1001" => + M9_out <= "0111111111"; + when others => + M9_out <= "1111111111"; + end case; +end if; +end process; +VSL2_n <= M9_out(0); +LDH1_n <= M9_out(1); +LDH2_n <= M9_out(2); +LDH3_n <= M9_out(3); +LDH4_n <= M9_out(4); +VSP1_n <= M9_out(5); +VSP2_n <= M9_out(6); +VSL1_n <= M9_out(7); + + +VidROMAdr <= Display(0) + & Display(5 downto 3) + & (Display(7) xor H1) + & (Display(6) xor L5_reg(3)) + & (Display(6) xor L5_reg(2)) + & (Display(6) xor L5_reg(1)) + & (Display(6) xor L5_reg(0)) + & (Display(7) xor H2); + + +--Motion object ROMs +M5: entity work.M5_rom +port map( + clock => clk6, + address => VidROMAdr, + q => VidROMdout(7 downto 4) + ); + +N5: entity work.N5_rom +port map( + clock => clk6, + address => VidROMAdr, + q => VidROMdout(3 downto 0) + ); + + +--Flip bit order of motion object ROMs with state of Display(7) to horizontally mirror ships +Vid <= VidROMDout(4) & VidROMDout(5) & VidROMDout(6) & VidROMDout(7) & VidROMDout(0) & VidROMDout(1) & VidROMDout(2) & VidROMDout(3) + when Display(7) = '0' else + VidROMDout(3) & VidROMDout(2) & VidROMDout(1) & VidROMDout(0) & VidROMDout(7) & VidROMDout(6) & VidROMDout(5) & VidROMDout(4); + + + +-- Decoders P8 and F8 generate the LDVxx signals +LDV_Decoder: process(clk6, clk12, VSP1_n, VSP2_n, HCount) +begin + if rising_edge(clk12) then + if VSP1_n = '0' and clk6 = '0' then + case HCount(1 downto 0) is + when "00" => LDV1_dec <= "1110"; + when "10" => LDV1_dec <= "1101"; + when "01" => LDV1_dec <= "1011"; + when "11" => LDV1_dec <= "0111"; + when others => + null; + end case; + else + LDV1_dec <= "1111"; + end if; + + if VSP2_n = '0' and clk6 = '0' then + case HCount(1 downto 0) is + when "00" => LDV2_dec <= "1110"; + when "10" => LDV2_dec <= "1101"; + when "01" => LDV2_dec <= "1011"; + when "11" => LDV2_dec <= "0111"; + when others => + null; + end case; + else + LDV2_dec <= "1111"; + end if; + end if; +end process; +LDV1A_n <= LDV1_dec(0); +LDV1B_n <= LDV1_dec(1); +LDV1C_n <= LDV1_dec(2); +LDV1D_n <= LDV1_dec(3); +LDV2A_n <= LDV2_dec(0); +LDV2B_n <= LDV2_dec(1); +LDV2C_n <= LDV2_dec(2); +LDV2D_n <= LDV2_dec(3); + + +-- Ship 1 Horizontal position counter +-- This combines two 74163s at locations P3 and N3 on the PCB +Ship1Count: process(clk6, H256_s, LDH1_n, Display) +begin + if rising_edge(clk6) then + if LDH1_n = '0' then -- preload the counter + Ship1_Hpos <= Display; + elsif H256_s = '1' then -- increment the counter + Ship1_Hpos <= Ship1_Hpos + '1'; + end if; + end if; +end process; +ShipWin1_n <= '0' when Ship1_Hpos(7 downto 5) = "111" else '1'; + +-- Ship 2 Horizontal position counter +-- This combines two 74163s at locations R3 and M3 on the PCB +Ship2Count: process(clk6, H256_s, LDH2_n, Display) +begin + if rising_edge(clk6) then + if LDH2_n = '0' then -- preload the counter + Ship2_Hpos <= Display; + elsif H256_s = '1' then -- increment the counter + Ship2_Hpos <= Ship2_Hpos + '1'; + end if; + end if; +end process; +ShipWin2_n <= '0' when Ship2_Hpos(7 downto 5) = "111" else '1'; + +-- Shell 1 Horizontal position counter +-- This combines two 74163s at locations R4 and M4 on the PCB +Shell1Count: process(clk6, H256_s, LDH3_n, Display) +begin + if rising_edge(clk6) then + if LDH3_n = '0' then -- preload the counter + Shell1_Hpos <= Display; + elsif H256_s = '1' then -- increment the counter + Shell1_Hpos <= Shell1_Hpos + '1'; + end if; + if Shell1_Hpos(7 downto 1) = "1111111" then + HShell1Win_n <= '0'; + else + HShell1Win_n <= '1'; + end if; + end if; +end process; + + +-- Shell 2 Horizontal position counter +-- This combines two 74163s at locations P4 and N4 on the PCB +Shell2Count: process(clk6, H256_s, LDH4_n, Display) +begin + if rising_edge(clk6) then + if LDH4_n = '0' then -- preload the counter + Shell2_Hpos <= Display; + elsif H256_s = '1' then -- increment the counter + Shell2_Hpos <= Shell2_Hpos + '1'; + end if; + if Shell2_Hpos(7 downto 1) = "1111111" then + HShell2Win_n <= '0'; + else + HShell2Win_n <= '1'; + end if; + end if; +end process; + + + +-- Ship 1 video shift register +-- This combines four 74165s at locations R7, P7, N7 and M7 on the PCB +Ship1Shift: process(clk6, ShipWin1_n, LDV1A_n, LDV1B_n, LDV1C_n, LDV1D_n, Vid) +begin + if LDV1A_n = '0' then + Ship1_reg(31 downto 24) <= Vid(7 downto 0); -- Load the register with data from the video ROMs + elsif LDV1B_n = '0' then + Ship1_reg(23 downto 16) <= Vid(7 downto 0); + elsif LDV1C_n = '0' then + Ship1_reg(15 downto 8) <= Vid(7 downto 0); + elsif LDV1D_n = '0' then + Ship1_reg(7 downto 0) <= Vid(7 downto 0); + elsif rising_edge(clk6) then + if ShipWin1_n = '0' then + Ship1_reg <= '0' & Ship1_reg(31 downto 1); + end if; + end if; +end process; +Ship1_n <= (not Ship1_reg(0)) or ShipWin1_n; + + +-- Ship 2 video shift register +-- This combines four 74165s at locations R6, P6, N6 and M6 on the PCB +Ship2Shift: process(Clk6, ShipWin2_n, LDV2A_n, LDV2B_n, LDV2C_n, LDV2D_n, Vid) +begin + if LDV2A_n = '0' then + Ship2_reg(31 downto 24) <= Vid(7 downto 0); -- Load the register with data from the video ROMs + elsif LDV2B_n = '0' then + Ship2_reg(23 downto 16) <= Vid(7 downto 0); + elsif LDV2C_n = '0' then + Ship2_reg(15 downto 8) <= Vid(7 downto 0); + elsif LDV2D_n = '0' then + Ship2_reg(7 downto 0) <= Vid(7 downto 0); + elsif rising_edge(clk6) then + if ShipWin2_n = '0' then + Ship2_reg <= '0' & Ship2_reg(31 downto 1); + end if; + end if; +end process; +Ship2_n <= (not Ship2_reg(0)) or ShipWin2_n; + +end rtl; diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/motor.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/motor.vhd new file mode 100644 index 00000000..59b950f2 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/motor.vhd @@ -0,0 +1,138 @@ +-- Motor sound generator for Atari Canyon Bomber +-- Similar circuits are used in a number of other games +-- (c) 2018 James Sweet +-- +-- Original circuit used a 555 configured as an astable oscillator with the frequency controlled by +-- a four bit binary value. The output of this oscillator drives a counter configured to produce an +-- irregular thumping simulating the sound of a piston engine. +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity EngineSound is +generic( + constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the overall engine sound frequency + ); +port( + Clk_6 : in std_logic; + Ena_3k : in std_logic; + EngineData : in std_logic_vector(3 downto 0); + Motor : out std_logic_vector(5 downto 0) + ); +end EngineSound; + +architecture rtl of EngineSound is + +signal RPM_val : integer range 1 to 350; +signal Ramp_Count : integer range 0 to 80000; +signal Ramp_term : integer range 1 to 80000; +signal Freq_mod : integer range 0 to 400; +signal Motor_Clk : std_logic; + +signal Counter_A : std_logic; +signal Counter_B : unsigned(2 downto 0); +signal Counter_A_clk : std_logic; + +signal Motor_prefilter : unsigned(1 downto 0); +signal Motor_filter_t1 : unsigned(3 downto 0); +signal Motor_filter_t2 : unsigned(3 downto 0); +signal Motor_filter_t3 : unsigned(3 downto 0); +signal Motor_filtered : unsigned(5 downto 0); + + +begin + +-- The frequency of the oscillator is set by a 4 bit binary value controlled by the game CPU +-- in the real hardware this is a 555 coupled to a 4 bit resistor DAC used to pull the frequency. +-- The output of this DAC has a capacitor to smooth out the frequency variation. +-- The constants assigned to RPM_val can be tweaked to adjust the frequency curve + +Speed_select: process(Clk_6) +begin + if rising_edge(Clk_6) then + case EngineData is + when "0000" => RPM_val <= 280; + when "0001" => RPM_val <= 245; + when "0010" => RPM_val <= 230; + when "0011" => RPM_val <= 205; + when "0100" => RPM_val <= 190; + when "0101" => RPM_val <= 175; + when "0110" => RPM_val <= 160; + when "0111" => RPM_val <= 145; + when "1000" => RPM_val <= 130; + when "1001" => RPM_val <= 115; + when "1010" => RPM_val <= 100; + when "1011" => RPM_val <= 85; + when "1100" => RPM_val <= 70; + when "1101" => RPM_val <= 55; + when "1110" => RPM_val <= 40; + when "1111" => RPM_val <= 25; + end case; + end if; +end process; + +-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower +-- the frequency. RPM_val is multiplied by a constant which can be adjusted by changing the value of freq_tune +-- to simulate the function of the frequency adjustment pot in the original hardware. +ramp_term <= ((200 - freq_tune) * RPM_val); + +-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator +Ramp_osc: process(clk_6) +begin + if rising_edge(clk_6) then + motor_clk <= '1'; + ramp_count <= ramp_count + 1; + if ramp_count > ramp_term then + ramp_count <= 0; + motor_clk <= '0'; + end if; + end if; +end process; + + +-- 7492 counter with XOR on two of the outputs creates lumpy engine sound from smooth pulse train +-- 7492 has two sections, one div-by-2 and one div-by-6. +Engine_counter: process(motor_clk, counter_A_clk, counter_B) +begin + if rising_edge(motor_clk) then + Counter_B <= Counter_B + '1'; + end if; + Counter_A_clk <= Counter_B(0) xor Counter_B(2); + if rising_edge(counter_A_clk) then + Counter_A <= (not Counter_A); + end if; +end process; +motor_prefilter <= ('0' & Counter_B(2)) + ('0' & Counter_B(1)) + ('0' & Counter_A); + +-- Very simple low pass filter, borrowed from MikeJ's Asteroids code +Engine_filter: process(clk_6) +begin + if rising_edge(clk_6) then + if (ena_3k = '1') then + motor_filter_t1 <= ("00" & motor_prefilter) + ("00" & motor_prefilter); + motor_filter_t2 <= motor_filter_t1; + motor_filter_t3 <= motor_filter_t2; + end if; + motor_filtered <= ("00" & motor_filter_t1) + + ('0' & motor_filter_t2 & '0') + + ("00" & motor_filter_t3); + end if; +end process; + +motor <= std_logic_vector(motor_filtered); + +end rtl; diff --git a/Console_MiST/Atari - 7800_TeST/rtl/osd.sv b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/osd.sv similarity index 100% rename from Console_MiST/Atari - 7800_TeST/rtl/osd.sv rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/osd.sv diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/playfield.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/playfield.vhd new file mode 100644 index 00000000..99c00c74 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/playfield.vhd @@ -0,0 +1,141 @@ +-- Playfield generation circuitry for Atari Canyon Bomber +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity playfield is +port( + clk6 : in std_logic; + display : in std_logic_vector(7 downto 0); + HCount : in std_logic_vector(8 downto 0); + VCount : in std_logic_vector(7 downto 0); + H256_s : buffer std_logic; + HBlank : in std_logic; + VBlank : in std_logic; + VBlank_n_s : in std_logic; -- VBLANK* on the schematic + HSync : in std_logic; + VSync : in std_logic; + CompSync_n_s : out std_logic; -- COMP SYNC* on schematic + CompBlank_n_s : buffer std_logic; -- COMP BLANK* on schematic + WhitePF_n : out std_logic; + BlackPF_n : out std_logic + ); +end playfield; + +architecture rtl of playfield is + +signal H1 : std_logic; +signal H2 : std_logic; +signal H4 : std_logic; +signal H256 : std_logic; +signal H256_n : std_logic; + +signal V1 : std_logic; +signal V2 : std_logic; +signal V4 : std_logic; +signal V128 : std_logic; + +signal char_addr : std_logic_vector(9 downto 0) := (others => '0'); +signal char_data : std_logic_vector(3 downto 0) := (others => '0'); + +signal shift_data : std_logic_vector(3 downto 0) := (others => '0'); +signal QH : std_logic; + +signal R2_reg : std_logic_vector(3 downto 0) := (others => '0'); + +signal H1H2 : std_logic; +signal SL : std_logic; +signal CompSync_n : std_logic; +signal CompBlank_n : std_logic; + + +signal Display7_s : std_logic; + +begin + +-- Video synchronization signals +H1 <= Hcount(0); +H2 <= Hcount(1); +H4 <= Hcount(2); +H256 <= Hcount(8); +H256_n <= not(Hcount(8)); + +V1 <= Vcount(0); +V2 <= Vcount(1); +V4 <= Vcount(2); +V128 <= Vcount(7); + +H1H2 <= (H1 nand H2); +SL <= (not H256_s) or H1H2; + + +CompSync_n <= (HSync nor VSync); + +CompBlank_n <= VBlank nor (HBlank);-- or H256_s and V128)); + + + +char_addr <= display(5 downto 0) & V4 & V2 & V1 & (not H4); + +-- Background character ROM +N8: entity work.Char_ROM +port map( + clock => clk6, + Address => char_addr, + q => char_data + ); + + +-- 74LS195 video shift register +R3: process(clk6, SL, VBlank_n_s, char_data, shift_data) +begin + if VBlank_n_s = '0' then -- Connected Clear input + shift_data <= (others => '0'); + elsif rising_edge(clk6) then + if SL = '0' then -- Parallel load + shift_data <= char_data; + else + shift_data <= shift_data(2 downto 0) & '0'; + end if; + end if; + QH <= shift_data(3); +end process; + + +-- 9316 counter at R2 +-- CEP and CET tied to ground, counter is used only as a synchronous latch +R2: process(clk6, H1H2, display, H256, CompSync_n, CompBlank_n) +begin + if rising_edge(clk6) then + if H1H2 = '0' then + R2_reg <= (H256 & display(7) & CompBlank_n & CompSync_n); + end if; + end if; +end process; + + +H256_s <= R2_reg(3); +Display7_s <= R2_reg(2); +CompBlank_n_s <= R2_reg(1); +CompSync_n_s <= R2_reg(0); + + +WhitePF_n <= (QH nand Display7_s); +BlackPF_n <= (not QH) or Display7_s; + +end rtl; \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/pll.v b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/pll.v similarity index 88% rename from Console_MiST/Atari - 7800_TeST/rtl/pll.v rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/pll.v index e38a7e4c..95460fd9 100644 --- a/Console_MiST/Atari - 7800_TeST/rtl/pll.v +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/pll.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version // ************************************************************ -//Copyright (C) 1991-2014 Altera Corporation +//Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing @@ -37,26 +37,17 @@ `timescale 1 ps / 1 ps // synopsys translate_on module pll ( - areset, inclk0, c0, c1, c2, locked); - input areset; input inclk0; output c0; output c1; output c2; output locked; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri0 areset; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif wire [4:0] sub_wire0; wire sub_wire2; @@ -72,11 +63,11 @@ module pll ( wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; altpll altpll_component ( - .areset (areset), .inclk (sub_wire6), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), + .areset (1'b0), .clkbad (), .clkena ({6{1'b1}}), .clkloss (), @@ -111,17 +102,17 @@ module pll ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 27, + altpll_component.clk0_divide_by = 125, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 25, + altpll_component.clk0_multiply_by = 112, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 189, + altpll_component.clk1_divide_by = 125, altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 50, + altpll_component.clk1_multiply_by = 56, altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 108, + altpll_component.clk2_divide_by = 125, altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 25, + altpll_component.clk2_multiply_by = 28, altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, @@ -131,7 +122,7 @@ module pll ( altpll_component.operation_mode = "NORMAL", altpll_component.pll_type = "AUTO", altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_USED", + altpll_component.port_areset = "PORT_UNUSED", altpll_component.port_clkbad0 = "PORT_UNUSED", altpll_component.port_clkbad1 = "PORT_UNUSED", altpll_component.port_clkloss = "PORT_UNUSED", @@ -196,15 +187,15 @@ endmodule // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "189" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "108" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "7.142857" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.250000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.191999" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.048000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -225,19 +216,19 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "25" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "50" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "112" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "28" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "7.14300000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.25000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.19200000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.04800000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" @@ -252,9 +243,9 @@ endmodule // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" @@ -290,17 +281,17 @@ endmodule // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "189" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "108" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "28" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" @@ -309,7 +300,7 @@ endmodule // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" @@ -352,13 +343,11 @@ endmodule // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3H.qip b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3H.qip new file mode 100644 index 00000000..1e521ed3 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3H.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom3H.vhd"] diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ROM256X1.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3H.vhd similarity index 67% rename from Computer_MiST/Oric Atmos_MiST/rtl/ROM256X1.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3H.vhd index 83b01f59..22804600 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ROM256X1.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3H.vhd @@ -4,7 +4,7 @@ -- MODULE: altsyncram -- ============================================================ --- File Name: ROM256X1.vhd +-- File Name: prog_rom3H.vhd -- Megafunction Name(s): -- altsyncram -- @@ -14,7 +14,7 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version -- ************************************************************ @@ -37,43 +37,66 @@ LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; +USE altera_mf.all; -ENTITY ROM256X1 IS - generic ( - init_file : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - ) +ENTITY prog_rom3H IS PORT ( - address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock : IN STD_LOGIC := '1'; - q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) + q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); -END ROM256X1; +END prog_rom3H; -ARCHITECTURE SYN OF rom256x1 IS +ARCHITECTURE SYN OF prog_rom3h IS - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_aclr_a : STRING; + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock0 : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; BEGIN - q <= sub_wire0(0 DOWNTO 0); + q <= sub_wire0(3 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_a => "NONE", clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", - init_file => init_file, + init_file => "./roms/9503-01.p1.hex", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", - numwords_a => 256, + numwords_a => 1024, operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", - widthad_a => 8, - width_a => 1, + widthad_a => 10, + width_a => 4, width_byteena_a => 1 ) PORT MAP ( @@ -106,41 +129,41 @@ END SYN; -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "./roms/key1.hex" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" +-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/9503-01.p1.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" --- Retrieval info: PRIVATE: WidthData NUMERIC "1" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +-- Retrieval info: PRIVATE: WidthData NUMERIC "4" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/key1.hex" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/9503-01.p1.hex" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" +-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" --- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]" --- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 +-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ROM256X1_inst.vhd FALSE +-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3H.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3H.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3H.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3H.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3H_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3L.qip b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3L.qip new file mode 100644 index 00000000..9d9bf5b1 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3L.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom3L.vhd"] diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/rrom.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3L.vhd similarity index 66% rename from Computer_MiST/Oric Atmos_MiST/rtl/rrom.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3L.vhd index db0397df..2f15c390 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/rrom.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/prog_rom3L.vhd @@ -4,7 +4,7 @@ -- MODULE: altsyncram -- ============================================================ --- File Name: rrom.vhd +-- File Name: prog_rom3L.vhd -- Megafunction Name(s): -- altsyncram -- @@ -14,7 +14,7 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version -- ************************************************************ @@ -37,40 +37,64 @@ LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; +USE altera_mf.all; -ENTITY rrom IS +ENTITY prog_rom3L IS PORT ( - address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock : IN STD_LOGIC := '1'; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); -END rrom; +END prog_rom3L; -ARCHITECTURE SYN OF rrom IS +ARCHITECTURE SYN OF prog_rom3l IS - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock0 : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; BEGIN - q <= sub_wire0(7 DOWNTO 0); + q <= sub_wire0(3 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( - address_aclr_a => "NONE", clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", - init_file => "./roms/basic11b.hex", - intended_device_family => "Cyclone III", + init_file => "./roms/9499-01.j1.hex", + intended_device_family => "Cyclone II", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", - numwords_a => 16384, + numwords_a => 1024, operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", - widthad_a => 14, - width_a => 8, + widthad_a => 10, + width_a => 4, width_byteena_a => 1 ) PORT MAP ( @@ -99,45 +123,44 @@ END SYN; -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "./roms/basic11b.hex" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: PRIVATE: MIFfilename STRING "./roms/9499-01.j1.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "14" --- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +-- Retrieval info: PRIVATE: WidthData NUMERIC "4" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/basic11b.hex" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./roms/9499-01.j1.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]" +-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" --- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" --- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 +-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]" +-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL rrom.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL rrom.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL rrom.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL rrom.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL rrom_inst.vhd FALSE +-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3L.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3L.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3L.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3L.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3L_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ram32k.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ram1k.vhd similarity index 68% rename from Computer_MiST/Oric Atmos_MiST/rtl/ram32k.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ram1k.vhd index 10eece41..2597babf 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ram32k.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ram1k.vhd @@ -4,7 +4,7 @@ -- MODULE: altsyncram -- ============================================================ --- File Name: ram32k.vhd +-- File Name: ram1k.vhd -- Megafunction Name(s): -- altsyncram -- @@ -14,7 +14,7 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -- ************************************************************ @@ -37,42 +37,69 @@ LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; +USE altera_mf.all; -ENTITY ram32k IS +ENTITY ram1k IS PORT ( - address : IN STD_LOGIC_VECTOR (14 DOWNTO 0); - clken : IN STD_LOGIC := '1'; + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); -END ram32k; +END ram1k; -ARCHITECTURE SYN OF ram32k IS +ARCHITECTURE SYN OF ram1k IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + clock0 : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren_a : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + BEGIN q <= sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( - clock_enable_input_a => "NORMAL", - clock_enable_output_a => "NORMAL", - intended_device_family => "Cyclone III", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "../roms/cb_testfill.hex", + intended_device_family => "Cyclone II", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", - numwords_a => 32768, + numwords_a => 1024, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => 15, + widthad_a => 10, width_a => 8, width_byteena_a => 1 ) @@ -81,7 +108,6 @@ BEGIN clock0 => clock, data_a => data, wren_a => wren, - clocken0 => clken, q_a => sub_wire0 ); @@ -99,20 +125,20 @@ END SYN; -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" --- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" --- Retrieval info: PRIVATE: Clken NUMERIC "1" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768" +-- Retrieval info: PRIVATE: MIFfilename STRING "../roms/cb_testfill.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" @@ -122,39 +148,37 @@ END SYN; -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "15" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "../roms/cb_testfill.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" --- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" --- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" +-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" --- Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 +-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram32k_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ram16k.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ram256.vhd similarity index 76% rename from Computer_MiST/Oric Atmos_MiST/rtl/ram16k.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ram256.vhd index f99e4f93..4819522d 100644 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ram16k.vhd +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/ram256.vhd @@ -4,7 +4,7 @@ -- MODULE: altsyncram -- ============================================================ --- File Name: ram16k.vhd +-- File Name: ram256.vhd -- Megafunction Name(s): -- altsyncram -- @@ -14,7 +14,7 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -- ************************************************************ @@ -37,25 +37,51 @@ LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; +USE altera_mf.all; -ENTITY ram16k IS +ENTITY ram256 IS PORT ( - address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - rden : IN STD_LOGIC := '1'; wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); -END ram16k; +END ram256; -ARCHITECTURE SYN OF ram16k IS +ARCHITECTURE SYN OF ram256 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + clock0 : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren_a : IN STD_LOGIC ; + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + BEGIN q <= sub_wire0(7 DOWNTO 0); @@ -63,16 +89,15 @@ BEGIN GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", - intended_device_family => "Cyclone III", + intended_device_family => "Cyclone II", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", - numwords_a => 16384, + numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "CLOCK0", power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => 14, + widthad_a => 8, width_a => 8, width_byteena_a => 1 ) @@ -81,7 +106,6 @@ BEGIN clock0 => clock, data_a => data, wren_a => wren, - rden_a => rden, q_a => sub_wire0 ); @@ -107,12 +131,12 @@ END SYN; -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" --- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" @@ -122,39 +146,36 @@ END SYN; -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" --- Retrieval info: PRIVATE: WidthAddr NUMERIC "14" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "8" --- Retrieval info: PRIVATE: rden NUMERIC "1" +-- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" --- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]" +-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" --- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" --- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 +-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 --- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL ram16k_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram256.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram256.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram256.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram256.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram256_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/roms/9491-01.j6.hex b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/roms/9491-01.j6.hex new file mode 100644 index 00000000..9dbfacea --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/roms/9491-01.j6.hex @@ -0,0 +1,17 @@ +:1000000000000000000000000000000000000000F0 +:1000100000000000000000000000000000000000E0 +:1000200000000000000000000000000000000000D0 +:1000300000000000000000000000000000000000C0 +:1000400000000000000000000000000000000000B0 +:1000500000000000000000000000000000000000A0 +:100060000000000000000000000000000000000090 +:100070000000000000000000000000000000000878 +:100080000A0A0A0A0A0E0000000000000000000030 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000808080808080808080808080808080A8E +:1000F0000A0A0B0B0B0A0A0A0A0A0A0A0A0A0A0A5D +:00000001FF diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/roms/9492-01.n8.hex b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/roms/9492-01.n8.hex new file mode 100644 index 00000000..508df105 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/roms/9492-01.n8.hex @@ -0,0 +1,65 @@ +:1000000000000308040C0C060C060C06060403088A +:100010000000010803080108010801080108070E93 +:100020000000070C0C06000E030C07080E000F0E54 +:1000300000000F0E000C0108030C00060C06070C54 +:100040000000000E010E030606060F0E0006000655 +:1000500000000F0C0C000F0C000600060C06070C2D +:100060000000030C06000C000F0C0C060C06070C1D +:1000700000000F0E0C06000C010803000300030033 +:10008000000007080C040E040708090E0806070CF8 +:100090000000070C0C060C06070E0006000C0708F3 +:1000A00000000308060C0C060C060F0E0C060C06CE +:1000B00000000F0C0C060C060F0C0C060C060F0CA7 +:1000C0000000030C06060C000C000C000606030CD6 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+:1000F0000F000C00070000000000000000000000DE +:00000001FF diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/scandoubler.sv b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/scandoubler.sv similarity index 100% rename from Console_MiST/Nintendo - Gameboy_MiST/rtl/scandoubler.sv rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/scandoubler.sv diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sound.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sound.vhd new file mode 100644 index 00000000..62f43e3e --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sound.vhd @@ -0,0 +1,190 @@ +-- Audio for Atari Canyon Bomber +-- There may be some room for improvement as I do not have a real board to compare. +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity audio is +port( + Clk_6 : in std_logic; + Ena_3k : in std_logic; + Reset_n : in std_logic; + Motor1_n : in std_logic; + Motor2_n : in std_logic; + Whistle1 : in std_logic; + Whistle2 : in std_logic; + Explode_n : in std_logic; + Attract1 : in std_logic; + Attract2 : in std_logic; + DBus : in std_logic_vector(7 downto 0); + VCount : in std_logic_vector(7 downto 0); + P1_audio : out std_logic_vector(6 downto 0); + P2_audio : out std_logic_vector(6 downto 0) + ); +end audio; + +architecture rtl of audio is + +signal Reset : std_logic; + +signal V2 : std_logic; + +signal Noise : std_logic; +signal Noise_Shift : std_logic_vector(15 downto 0); +signal Shift_in : std_logic; + +signal Mtr1_Freq : std_logic_vector(3 downto 0) := "0000"; +signal Motor1_speed : std_logic_vector(3 downto 0) := "0000"; +signal Motor1_snd : std_logic_vector(5 downto 0); +signal Mtr2_Freq : std_logic_vector(3 downto 0) := "0000"; +signal Motor2_speed : std_logic_vector(3 downto 0) := "0000"; +signal Motor2_snd : std_logic_vector(5 downto 0); + +signal Explosion : std_logic_vector(3 downto 0); +signal Explosion_prefilter : std_logic_vector(3 downto 0); +signal Explosion_filter_t1 : std_logic_vector(3 downto 0); +signal Explosion_filter_t2 : std_logic_vector(3 downto 0); +signal Explosion_filter_t3 : std_logic_vector(3 downto 0); +signal Explosion_filtered : std_logic_vector(5 downto 0); + +signal Whistle_snd1 : std_logic_vector(3 downto 0); +signal Whistle_snd2 : std_logic_vector(3 downto 0); + + + + +begin + +reset <= (not reset_n); + +V2 <= VCount(1); + +-- Explosion -- +-- LFSR that generates pseudo-random noise used by the explosion sound +Noise_gen: process(Attract1, Attract2, V2) +begin + if ((Attract1 nand Attract2) = '0') then + noise_shift <= (others => '0'); + noise <= '0'; + elsif rising_edge(V2) then + shift_in <= not(noise_shift(6) xor noise_shift(8)); + noise_shift <= shift_in & noise_shift(15 downto 1); + noise <= noise_shift(0); + end if; +end process; + +-- Explosion envelope is latched on rising edge of Explode_n (not sure why this is shown active low) +Explosion_sound: process(Explode_n, DBus, noise) +begin + if rising_edge(Explode_n) then + explosion <= DBus(7 downto 4); + end if; +end process; +explosion_prefilter <= explosion when noise = '1' else "0000"; + +-- Very simple low pass filter, borrowed from MikeJ's Asteroids code, should probably be lower cutoff +explode_filter: process(clk_6) +begin + if rising_edge(clk_6) then + if (ena_3k = '1') then + explosion_filter_t1 <= explosion_prefilter; + explosion_filter_t2 <= explosion_filter_t1; + explosion_filter_t3 <= explosion_filter_t2; + end if; + explosion_filtered <= ("00" & explosion_filter_t1) + + ('0' & explosion_filter_t2 & '0') + + ("00" & explosion_filter_t3); + end if; +end process; +----------------------- + + +-- Engine Sounds -- +Motor1_Freq: process(Motor1_n, DBus) +begin + if rising_edge(Motor1_n) then + Motor1_speed <= DBus(3 downto 0); + end if; +end process; + +Player1_Motor: entity work.EngineSound +generic map( + Freq_tune => 45 -- Tuning pot for engine sound frequency (Range 1-100) + ) +port map( + Clk_6 => clk_6, + Ena_3k => ena_3k, + EngineData => motor1_speed, + Motor => motor1_snd + ); + +Motor2_Freq: process(Motor2_n, DBus) +begin + if rising_edge(Motor2_n) then + Motor2_speed <= DBus(3 downto 0); + end if; +end process; + +Player2_Motor: entity work.EngineSound +generic map( + Freq_tune => 47 -- Tuning pot for engine sound frequency (Range 1-100) + ) +port map( + Clk_6 => clk_6, + Ena_3k => ena_3k, + EngineData => motor2_speed, + Motor => motor2_snd + ); +----------------------- + + +-- Bomb Drop Whistles -- +-- Player 1 whistle +Player1_Whistle: entity work.Whistle +generic map( + Freq_tune => 40 -- Tuning pot for whistle sound frequency (Range 1-100) + ) +port map( + Clk_6 => clk_6, + Ena_3k => ena_3k, + Whistle_trig => whistle1, + Whistle_out => whistle_snd1 + ); + +Player2_Whistle: entity work.Whistle +generic map( + Freq_tune => 44 -- Tuning pot for whistle sound frequency (Range 1-100) + ) +port map( + Clk_6 => clk_6, + Ena_3k => ena_3k, + Whistle_trig => whistle2, + Whistle_out => whistle_snd2 + ); +----------------------- + + +-- Audio mixer, also mutes sound in attract mode +P1_Audio <= ("000" & whistle_snd1) + ('0' & motor1_snd) + ('0' & whistle_snd1) + ('0' & explosion_filtered) when attract1 = '0' + else "0000000"; + +P2_Audio <= ("000" & whistle_snd2) + ('0' & motor2_snd) + ('0' & whistle_snd2) + ('0' & explosion_filtered) when attract2 = '0' + else "0000000"; +----------------------- + + +end rtl; \ No newline at end of file diff --git a/Computer_MiST/Galaksija_MiST/rtl/sprom.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sprom.vhd similarity index 100% rename from Computer_MiST/Galaksija_MiST/rtl/sprom.vhd rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sprom.vhd diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sync.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sync.vhd new file mode 100644 index 00000000..c95a54ba --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sync.vhd @@ -0,0 +1,172 @@ +-- Video synchronizer circuit for Atari Canyon Bomber +-- Similar circuit used in many other Atari and Kee Games arcade games +-- (c) 2018 James Sweet +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity synchronizer is +port( + clk_12 : in std_logic; + clk_6 : out std_logic; + hcount : out std_logic_vector(8 downto 0); + vcount : out std_logic_vector(7 downto 0); + hsync : buffer std_logic; + hblank : buffer std_logic; + vblank_s : out std_logic; + vblank_n_s : out std_logic; + vblank : out std_logic; + vsync : out std_logic; + vreset : out std_logic + ); +end synchronizer; + +architecture rtl of synchronizer is + +signal h_counter : std_logic_vector(9 downto 0) := (others => '0'); +signal H256 : std_logic; +signal H256_n : std_logic; +signal H128 : std_logic; +signal H64 : std_logic; +signal H32 : std_logic; +signal H16 : std_logic; +signal H8 : std_logic; +signal H8_n : std_logic; +signal H4 : std_logic; +signal H4_n : std_logic; +signal H2 : std_logic; +signal H1 : std_logic; + +signal v_counter : std_logic_vector(7 downto 0) := (others => '0'); +signal V128 : std_logic; +signal V64 : std_logic; +signal V32 : std_logic; +signal V16 : std_logic; +signal V8 : std_logic; +signal V4 : std_logic; +signal V2 : std_logic; +signal V1 : std_logic; + +signal sync_bus : std_logic_vector(3 downto 0) := (others => '0'); +signal sync_reg : std_logic_vector(3 downto 0) := (others => '0'); +signal vreset_n : std_logic := '0'; + +signal hsync_reset : std_logic := '0'; + + +begin + +-- Horizontal counter is 9 bits long plus additional flip flop. The last 4 bit IC in the chain resets to 0010 so total count resets to 128 +-- using only the last three count states +H_count: process(clk_12) +begin + if rising_edge(clk_12) then + if h_counter = "1111111111" then + h_counter <= "0100000000"; + else + h_counter <= h_counter + 1; + end if; + end if; +end process; + +-- Vertical counter is 8 bits, clocked by the rising edge of H256 at the end of each horizontal line +V_count: process(hsync) +begin + if rising_edge(Hsync) then + if vreset_n = '0' then + v_counter <= (others => '0'); + else + v_counter <= v_counter + '1'; + end if; + end if; +end process; + +-- Original circuit used a bipolar PROM to decode sync signals +-- This has been replaced here by combinatorial logic +M2: entity work.prom +port map( + address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1, + data => sync_bus + ); + +-- Register fed by the sync PROM, in the original hardware this also creates the complements of these signals +sync_register: process(hsync) +begin + if rising_edge(hsync) then + sync_reg <= sync_bus; + end if; +end process; + +-- Outputs of sync PROM +vblank_s <= sync_reg(3); +vblank_n_s <= not sync_reg(3); +vreset <= sync_reg(2); +vreset_n <= not sync_reg(2); +vblank <= sync_reg(1); +vsync <= sync_reg(0); + +-- A pair of D type flip-flops that generate the Hsync signal +Hsync_1: process(H256_n, H32) +begin + if H256_n = '0' then + hblank <= '0'; + else + if rising_edge(H32) then + hblank <= not H64; + end if; + end if; +end process; + +Hsync_2: process(hblank, H8) +begin + if hblank = '0' then + hsync <= '0'; + else + if rising_edge(H8) then + hsync <= H32; + end if; + end if; +end process; + +-- Assign various signals +clk_6 <= h_counter(0); +H1 <= h_counter(1); +H2 <= h_counter(2); +H4 <= h_counter(3); +H8 <= h_counter(4); +H16 <= h_counter(5); +H32 <= h_counter(6); +H64 <= h_counter(7); +H128 <= h_counter(8); +H256 <= h_counter(9); +H4_n <= not H4; +H8_n <= not H8; +H256_n <= not H256; + +V1 <= v_counter(0); +V2 <= v_counter(1); +V4 <= v_counter(2); +V8 <= v_counter(3); +V16 <= v_counter(4); +V32 <= v_counter(5); +V64 <= v_counter(6); +V128 <= v_counter(7); + +hcount <= h_counter(9 downto 1); +vcount <= v_counter; + +end rtl; \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sync_prom.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sync_prom.vhd new file mode 100644 index 00000000..9778f088 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/sync_prom.vhd @@ -0,0 +1,108 @@ +-- Asynchronous implementation of the bipolar PROM used to decode some of the sync signals +-- This PROM data is used in several Kee and Atari games. Combinatorial logic uses no block +-- RAM and is vendor agnostic + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + + +entity prom is +port( + address : in std_logic_vector(7 downto 0); + data : out std_logic_vector(3 downto 0) + ); +end prom; + +architecture rtl of prom is + + +begin + + +process(address) +begin + case address is + when "01111111" => + data <= "1000"; + when "10000000" => + data <= "1010"; + when "10000001" => + data <= "1010"; + when "10000010" => + data <= "1010"; + when "10000011" => + data <= "1010"; + when "10000100" => + data <= "1010"; + when "10000101" => + data <= "1110"; + when "11100000" => + data <= "1000"; + when "11100001" => + data <= "1000"; + when "11100010" => + data <= "1000"; + when "11100011" => + data <= "1000"; + when "11100100" => + data <= "1000"; + when "11100101" => + data <= "1000"; + when "11100110" => + data <= "1000"; + when "11100111" => + data <= "1000"; + when "11101000" => + data <= "1000"; + when "11101001" => + data <= "1000"; + when "11101010" => + data <= "1000"; + when "11101011" => + data <= "1000"; + when "11101100" => + data <= "1000"; + when "11101101" => + data <= "1000"; + when "11101110" => + data <= "1000"; + when "11101111" => + data <= "1010"; + when "11110000" => + data <= "1010"; + when "11110001" => + data <= "1010"; + when "11110010" => + data <= "1011"; + when "11110011" => + data <= "1011"; + when "11110100" => + data <= "1011"; + when "11110101" => + data <= "1010"; + when "11110110" => + data <= "1010"; + when "11110111" => + data <= "1010"; + when "11111000" => + data <= "1010"; + when "11111001" => + data <= "1010"; + when "11111010" => + data <= "1010"; + when "11111011" => + data <= "1010"; + when "11111100" => + data <= "1010"; + when "11111101" => + data <= "1010"; + when "11111110" => + data <= "1010"; + when "11111111" => + data <= "1010"; + when others => + data <= "0000"; + end case; +end process; + +end rtl; \ No newline at end of file diff --git a/Computer_MiST/Galaksija_MiST/rtl/video_mixer.sv b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/video_mixer.sv similarity index 100% rename from Computer_MiST/Galaksija_MiST/rtl/video_mixer.sv rename to Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/video_mixer.sv diff --git a/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/whistle.vhd b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/whistle.vhd new file mode 100644 index 00000000..5d79cef7 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Canyon_Bomber_MiST/rtl/whistle.vhd @@ -0,0 +1,81 @@ +-- Whistle sound generator for Atari Canyon Bomber +-- Produces a descending slide whistle sound for the falling bomb shells +-- (c) 2018 James Sweet + +-- +-- This is free software: you can redistribute +-- it and/or modify it under the terms of the GNU General +-- Public License as published by the Free Software +-- Foundation, either version 3 of the License, or (at your +-- option) any later version. +-- +-- This is distributed in the hope that it will +-- be useful, but WITHOUT ANY WARRANTY; without even the +-- implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + +entity whistle is +generic( + constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the overall whistle sound frequency + ); +port( + clk_6 : in std_logic; + Ena_3k : in std_logic; -- Saves some logic since this signal is already used elsewhere + Whistle_trig : in std_logic; -- Active-high trigger for whistle sound + Whistle_out : out std_logic_vector(3 downto 0) -- Whistle output + ); +end whistle; + +architecture rtl of whistle is + +signal Ramp_Count : integer range 0 to 80000; +signal Ramp_term : integer range 1 to 80000; +signal Pitch_bend : integer range 0 to 30000; +signal Whistle_bit : std_logic; + +begin +-- The real hardware used a R-C circuit to pull the control voltage of a 555, bending the pitch +-- downward as a capacitor discharges through a resistor. This simulates that functionality by +-- incrementing a value on each cycle of ena_3k, this value is then used to alter the frequency +-- of the whistle. +RC_pitchbend: process(clk_6, ena_3k, Whistle_trig) +begin + if Whistle_trig = '0' then + Pitch_bend <= 0; + elsif rising_edge(clk_6) then + if ena_3k = '1' then + if Pitch_bend < 30000 then + Pitch_bend <= pitch_bend + 1; + end if; + end if; + end if; +end process; + + +-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower +-- the frequency. This is a constant which can be adjusted by changing the value of freq_tune, here a setting of +-- 0 to 100 results in a ramp_term value ranging from 1000 to 3000 to simulate the function of the frequency +-- adjustment pot in the original hardware. +Ramp_term <= 2800 - (20 * Freq_tune); + +-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator +Ramp_osc: process(clk_6, pitch_bend) +begin + if rising_edge(clk_6) then + Ramp_count <= Ramp_count + 1; + if Ramp_count > Ramp_term + Pitch_bend / 2 then + Ramp_count <= 0; + Whistle_bit <= (not Whistle_bit); + end if; + end if; +end process; +-- Whistle_out is 4 bits wide, the active value can be adjusted to tune the volume level +Whistle_out <= "0011" when Whistle_bit = '1' and Whistle_trig = '1' else "0000"; + +end rtl; \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/Dominos_MiST/README.txt b/Arcade_MiST/Atari-Hardware/Dominos_MiST/README.txt new file mode 100644 index 00000000..64dc7abf --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Dominos_MiST/README.txt @@ -0,0 +1,17 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Dominos from james10952001 +-- Port to MiST by Gehstock +-- 23 November 2018 +-- + +-- +-- Keyboard inputs : +-- ESC : Coin +-- F1 or F2 : Start +-- Joy 1 and Joy 2 : Fire +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- diff --git a/Arcade_MiST/Atari-Hardware/Dominos_MiST/release/dominos.rbf b/Arcade_MiST/Atari-Hardware/Dominos_MiST/release/dominos.rbf index 5bfede41..a7e5ac6a 100644 Binary files a/Arcade_MiST/Atari-Hardware/Dominos_MiST/release/dominos.rbf and b/Arcade_MiST/Atari-Hardware/Dominos_MiST/release/dominos.rbf differ diff --git a/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/build_id.sv b/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/build_id.sv index ae2d18c1..82585804 100644 --- a/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/build_id.sv +++ b/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/build_id.sv @@ -1,2 +1,2 @@ -`define BUILD_DATE "181022" -`define BUILD_TIME "124340" +`define BUILD_DATE "181123" +`define BUILD_TIME "011223" diff --git a/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/dominos.vhd b/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/dominos.vhd index eca24d04..b62a3dc2 100644 --- a/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/dominos.vhd +++ b/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/dominos.vhd @@ -35,7 +35,7 @@ port( Vs : out std_logic; Vb : out std_logic; Hb : out std_logic; - Video : out std_logic; + Video : out std_logic_vector(1 downto 0); Audio : out std_logic_vector(6 downto 0); -- Ideally this should have a simple low pass filter Coin1_I : in std_logic; -- Coin switches (Active low) Coin2_I : in std_logic; @@ -238,6 +238,7 @@ Vb <= VBLANK; Hb <= HBLANK; Hs <= Hsync; Vs <= Vsync; -Video <= (not (BlackPF_n and WhitePF_n)) nor CompBlank_s; +Video(0) <= (not BlackPF_n) nor CompBlank_s; +Video(1) <= (not WhitePF_n); end rtl; diff --git a/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/dominos_mist.sv b/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/dominos_mist.sv index 73b36499..e4bb0d87 100644 --- a/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/dominos_mist.sv +++ b/Arcade_MiST/Atari-Hardware/Dominos_MiST/rtl/dominos_mist.sv @@ -38,7 +38,7 @@ wire scandoubler_disable; wire ypbpr; wire ps2_kbd_clk, ps2_kbd_data; wire [6:0] audio; -wire video; +wire [1:0] video; wire clk_24, clk_12, clk_6; wire locked; @@ -96,7 +96,7 @@ assign AUDIO_R = AUDIO_L; wire hs, vs; wire hb, vb; wire blankn = ~(hb | vb); -video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer +video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer ( .clk_sys(clk_24), .ce_pix(clk_6), @@ -104,9 +104,12 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), .SPI_DI(SPI_DI), - .R(blankn ? {video,video,video} : "000"), - .G(blankn ? {video,video,video} : "000"), - .B(blankn ? {video,video,video} : "000"), + .R({video,video,video}), + .G({video,video,video}), + .B({video,video,video}), +// .R(blankn ? {video,video,video} : "000000"), +// .G(blankn ? {video,video,video} : "000000"), +// .B(blankn ? {video,video,video} : "000000"), .HSync(hs), .VSync(vs), .VGA_R(VGA_R), diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/README.txt b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/README.txt new file mode 100644 index 00000000..79fe7910 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/README.txt @@ -0,0 +1,18 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Sprint 2 from james10952001 +-- Port to MiST by Gehstock +-- 23 November 2018 +-- + +-- +-- Keyboard inputs : +-- ESC : Coin +-- F1 or F2 : Start +-- +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- +todo: Fix Controls \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dac.sv b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dac.sv index 25899384..22ae8f07 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dac.sv +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/dac.sv @@ -3,7 +3,7 @@ // // MSBI is the highest bit number. NOT amount of bits! // -module dac #(parameter MSBI=7, parameter INV=1'b1) +module dac #(parameter MSBI=6, parameter INV=1'b1) ( output reg DACout, //Average Output feeding analog lowpass input [MSBI:0] DACin, //DAC input (excess 2**MSBI) diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/pll.qip b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/pll.qip similarity index 100% rename from Console_MiST/Coleco - Vision_MiST/rtl/pll.qip rename to Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/pll.qip diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/pll.v b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/pll.v index 6a352243..95460fd9 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/pll.v +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/pll.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version // ************************************************************ -//Copyright (C) 1991-2014 Altera Corporation +//Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing @@ -40,26 +40,30 @@ module pll ( inclk0, c0, c1, + c2, locked); input inclk0; output c0; output c1; + output c2; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; wire locked = sub_wire2; wire c0 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; altpll altpll_component ( - .inclk (sub_wire5), + .inclk (sub_wire6), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -100,12 +104,16 @@ module pll ( altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 125, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 224, + altpll_component.clk0_multiply_by = 112, altpll_component.clk0_phase_shift = "0", altpll_component.clk1_divide_by = 125, altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 56, altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 125, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 28, + altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -140,7 +148,7 @@ module pll ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_USED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -181,10 +189,13 @@ endmodule // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.383999" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.191999" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.048000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -206,25 +217,33 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "224" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "112" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "28" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.38400000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.19200000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.04800000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -248,25 +267,32 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "224" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "28" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -300,7 +326,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -319,12 +345,14 @@ endmodule // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2.vhd b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2.vhd index d147f567..74f6bb76 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2.vhd +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2.vhd @@ -31,8 +31,7 @@ entity sprint2 is port( clk_12 : in std_logic; -- 12MHz input clock Reset_n : in std_logic; -- Reset button (Active low) - VideoW_O : out std_logic; -- White video output (680 Ohm) - VideoB_O : out std_logic; -- Black video output (1.2k) + Video : out std_logic_vector(1 downto 0); Sync_O : out std_logic; -- Composite sync output (1.2k) Audio1_O : out std_logic_vector(6 downto 0); -- Ideally this should have a simple low pass filter Audio2_O : out std_logic_vector(6 downto 0); @@ -41,7 +40,6 @@ port( Vs : out std_logic; Vb : out std_logic; Hb : out std_logic; - Video : out std_logic; Coin1_I : in std_logic; -- Coin switches (Active low) Coin2_I : in std_logic; @@ -324,8 +322,8 @@ port map( ); -- Video mixing -VideoB_O <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s; -VideoW_O <= not(WhitePF_n and Car1_n and Car3_4_n); +--VideoB_O <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s; +--VideoW_O <= not(WhitePF_n and Car1_n and Car3_4_n); Sync_O <= CompSync_n_s; @@ -333,6 +331,7 @@ Vb <= VBLANK; Hb <= HBLANK; Hs <= Hsync; Vs <= Vsync; -Video <= (WhitePF_n and blackpf_n and car1_n and Car2_n and Car3_4_n) nor CompBlank_s; +Video(0) <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s; +Video(1) <= not(WhitePF_n and Car1_n and Car3_4_n); end rtl; \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_mist.sv b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_mist.sv index 2406115a..1dd37a39 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_mist.sv +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/rtl/sprint2_mist.sv @@ -21,7 +21,7 @@ module sprint2_mist( localparam CONF_STR = { "Sprint2;;", "O1,Test Mode,Off,On;", - "T2,Next Track;", +// "T2,Next Track;", "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", "T6,Reset;", "V,v1.00.",`BUILD_DATE @@ -37,15 +37,16 @@ wire scandoubler_disable; wire ypbpr; wire ps2_kbd_clk, ps2_kbd_data; wire [6:0] audio1, audio2; -wire video; +wire [1:0] video; -wire clk_48, clk_12; +wire clk_24, clk_12, clk_6; wire locked; pll pll ( .inclk0(CLOCK_27), - .c0(clk_48), + .c0(clk_24), .c1(clk_12), + .c2(clk_6), .locked(locked) ); @@ -69,7 +70,7 @@ sprint2 sprint2 ( .Coin2_I(~kbjoy[7]), .Start1_I(~kbjoy[5]), .Start2_I(~kbjoy[6]), - .Trak_Sel_I(~status[2]), + .Trak_Sel_I(),//~status[2]), .Gas1_I(~kbjoy[4]), .Gas2_I(), // .Gear1_1_I(),// Gear shifters, 4th gear = no other gear selected @@ -88,33 +89,36 @@ sprint2 sprint2 ( ); dac dac1 ( - .CLK(clk_48), + .CLK(clk_24), .RESET(1'b0), .DACin(audio1), .DACout(AUDIO_L) ); -dac dac2 ( - .CLK(clk_48), +dac dacr ( + .CLK(clk_24), .RESET(1'b0), .DACin(audio2), .DACout(AUDIO_R) - ); + ); wire hs, vs; wire hb, vb; wire blankn = ~(hb | vb); video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer ( - .clk_sys(clk_48), - .ce_pix(clk_12), - .ce_pix_actual(clk_12), + .clk_sys(clk_24), + .ce_pix(clk_6), + .ce_pix_actual(clk_6), .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), .SPI_DI(SPI_DI), - .R(blankn ? {video,video,video} : "000"), - .G(blankn ? {video,video,video} : "000"), - .B(blankn ? {video,video,video} : "000"), + .R({video,video,video}), + .G({video,video,video}), + .B({video,video,video}), +// .R(blankn ? {video,video,video} : "000"), +// .G(blankn ? {video,video,video} : "000"), +// .B(blankn ? {video,video,video} : "000"), .HSync(hs), .VSync(vs), .VGA_R(VGA_R), @@ -132,7 +136,7 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ( - .clk_sys (clk_48 ), + .clk_sys (clk_24 ), .conf_str (CONF_STR ), .SPI_SCK (SPI_SCK ), .CONF_DATA0 (CONF_DATA0 ), @@ -151,7 +155,7 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ); keyboard keyboard( - .clk(clk_48), + .clk(clk_24), .reset(), .ps2_kbd_clk(ps2_kbd_clk), .ps2_kbd_data(ps2_kbd_data), diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/snapshot/sprint2.rbf b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/snapshot/sprint2.rbf index 1d603b9e..0ede2756 100644 Binary files a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/snapshot/sprint2.rbf and b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/snapshot/sprint2.rbf differ diff --git a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/sprint2.qsf b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/sprint2.qsf index 06dfc92c..c34032c8 100644 --- a/Arcade_MiST/Atari-Hardware/Sprint2_MiST/sprint2.qsf +++ b/Arcade_MiST/Atari-Hardware/Sprint2_MiST/sprint2.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16 OCTOBER 10, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files # Analysis & Synthesis Assignments @@ -57,9 +57,6 @@ set_global_assignment -name TOP_LEVEL_ENTITY sprint2_mist # ================== set_global_assignment -name DEVICE EP3C25E144C8 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON @@ -138,11 +135,23 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end ENTITY(sprint1_mist) # ------------------------ +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27 +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprint2_mist.sv +set_global_assignment -name VHDL_FILE rtl/sprint2.vhd set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd -set_global_assignment -name VHDL_FILE rtl/sprint2.vhd set_global_assignment -name VHDL_FILE rtl/sync.vhd set_global_assignment -name VHDL_FILE rtl/playfield.vhd set_global_assignment -name VHDL_FILE rtl/motion.vhd @@ -153,17 +162,12 @@ set_global_assignment -name VHDL_FILE rtl/sprint2_sound.vhd set_global_assignment -name VHDL_FILE rtl/screech.vhd set_global_assignment -name VHDL_FILE rtl/EngineSound.vhd set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprint2_mist.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name QIP_FILE rtl/roms/addec_prom.qip set_global_assignment -name QIP_FILE rtl/roms/Char_LSB.qip set_global_assignment -name QIP_FILE rtl/roms/Char_MSB.qip @@ -175,12 +179,5 @@ set_global_assignment -name QIP_FILE rtl/roms/prog_rom3.qip set_global_assignment -name QIP_FILE rtl/roms/prog_rom4.qip set_global_assignment -name QIP_FILE rtl/roms/sync_prom.qip set_global_assignment -name VERILOG_FILE rtl/pll.v -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27 set_global_assignment -name VHDL_FILE rtl/dpram.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/README.txt b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/README.txt new file mode 100644 index 00000000..d7d623d5 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/README.txt @@ -0,0 +1,18 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Sprint One from james10952001 +-- Port to MiST by Gehstock +-- 23 November 2018 +-- + +-- +-- Keyboard inputs : +-- ESC : Coin +-- F1 or F2 : Start +-- +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- +todo: Fix Controls \ No newline at end of file diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/pll.qip b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/pll.qip similarity index 80% rename from Console_MiST/Nintendo - Gameboy_MiST/rtl/pll.qip rename to Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/pll.qip index afd958be..aaef684a 100644 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/pll.qip +++ b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/pll.qip @@ -1,4 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name IP_TOOL_VERSION "13.0" set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/pll.v b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/pll.v index 6a352243..aec82b25 100644 --- a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/pll.v +++ b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/pll.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version // ************************************************************ -//Copyright (C) 1991-2014 Altera Corporation +//Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing @@ -40,26 +40,30 @@ module pll ( inclk0, c0, c1, + c2, locked); input inclk0; output c0; output c1; + output c2; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; wire locked = sub_wire2; wire c0 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; altpll altpll_component ( - .inclk (sub_wire5), + .inclk (sub_wire6), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -100,12 +104,16 @@ module pll ( altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 125, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 224, + altpll_component.clk0_multiply_by = 112, altpll_component.clk0_phase_shift = "0", altpll_component.clk1_divide_by = 125, altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 56, altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 125, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 28, + altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -140,7 +148,7 @@ module pll ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_USED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -181,10 +189,13 @@ endmodule // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.383999" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.191999" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.048000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -206,25 +217,33 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "224" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "112" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "28" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.38400000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.19200000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.04800000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -248,25 +267,32 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "224" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "28" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -300,7 +326,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -319,12 +345,14 @@ endmodule // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE diff --git a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/sprint1.vhd b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/sprint1.vhd index 7811fbef..d4245fcb 100644 --- a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/sprint1.vhd +++ b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/sprint1.vhd @@ -31,18 +31,12 @@ entity sprint1 is port( clk_12 : in std_logic; -- 12MHz input clock Reset_n : in std_logic; -- Reset button (Active low) - - - VideoW_O : out std_logic; -- White video output (680 Ohm) - VideoB_O : out std_logic; -- Black video output (1.2k) - Sync_O : out std_logic; -- Composite sync output (1.2k) - - + Sync_O : out std_logic; -- Composite sync output (1.2k) Hs : out std_logic; Vs : out std_logic; Vb : out std_logic; Hb : out std_logic; - Video : out std_logic; + Video : out std_logic_vector(1 downto 0); Audio : out std_logic_vector(6 downto 0); Coin1_I : in std_logic; -- Coin switches (Active low) Coin2_I : in std_logic; @@ -297,14 +291,14 @@ port map( ); -- Video mixing -VideoB_O <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s; -VideoW_O <= not(WhitePF_n and Car1_n); +Video(0) <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s; +Video(1) <= not(WhitePF_n and Car1_n); Sync_O <= CompSync_n_s; Vb <= VBLANK; Hb <= HBLANK; Hs <= Hsync; Vs <= Vsync; -Video <= (WhitePF_n and blackpf_n and car1_n and Car2_n and Car3_4_n) nor CompBlank_s; + end rtl; \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/sprint1_mist.sv b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/sprint1_mist.sv index f367af5e..8f9c27b3 100644 --- a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/sprint1_mist.sv +++ b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/rtl/sprint1_mist.sv @@ -36,15 +36,16 @@ wire scandoubler_disable; wire ypbpr; wire ps2_kbd_clk, ps2_kbd_data; wire [6:0] audio; -wire video; +wire [1:0] video; -wire clk_48, clk_12; +wire clk_48, clk_12, clk_6; wire locked; pll pll ( .inclk0(CLOCK_27), - .c0(clk_48),//48.384 + .c0(clk_24),//24.192 .c1(clk_12),//12.096 + .c2(clk_6),//6.048 .locked(locked) ); @@ -75,7 +76,7 @@ sprint1 sprint1 ( ); dac dac ( - .CLK(clk_48), + .CLK(clk_24), .RESET(1'b0), .DACin(audio), .DACout(AUDIO_L) @@ -86,17 +87,20 @@ assign AUDIO_R = AUDIO_L; wire hs, vs; wire hb, vb; wire blankn = ~(hb | vb); -video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer +video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer ( - .clk_sys(clk_48), - .ce_pix(clk_12), - .ce_pix_actual(clk_12), + .clk_sys(clk_24), + .ce_pix(clk_6), + .ce_pix_actual(clk_6), .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), .SPI_DI(SPI_DI), - .R(blankn ? {video,video,video} : "000"), - .G(blankn ? {video,video,video} : "000"), - .B(blankn ? {video,video,video} : "000"), + .R({video,video,video}), + .G({video,video,video}), + .B({video,video,video}), +// .R(blankn ? {video,video,video} : "000000"), +// .G(blankn ? {video,video,video} : "000000"), +// .B(blankn ? {video,video,video} : "000000"), .HSync(hs), .VSync(vs), .VGA_R(VGA_R), @@ -114,7 +118,7 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ( - .clk_sys (clk_48 ), + .clk_sys (clk_24 ), .conf_str (CONF_STR ), .SPI_SCK (SPI_SCK ), .CONF_DATA0 (CONF_DATA0 ), @@ -133,7 +137,7 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ); keyboard keyboard( - .clk(clk_48), + .clk(clk_24), .reset(), .ps2_kbd_clk(ps2_kbd_clk), .ps2_kbd_data(ps2_kbd_data), diff --git a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/snapshot/sprint1.rbf b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/snapshot/sprint1.rbf index 2fdbb624..3be3f765 100644 Binary files a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/snapshot/sprint1.rbf and b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/snapshot/sprint1.rbf differ diff --git a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/sprint1.qsf b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/sprint1.qsf index e1165832..e6723c1f 100644 --- a/Arcade_MiST/Atari-Hardware/SprintOne_MiST/sprint1.qsf +++ b/Arcade_MiST/Atari-Hardware/SprintOne_MiST/sprint1.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16 OCTOBER 10, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files # Analysis & Synthesis Assignments @@ -57,9 +57,6 @@ set_global_assignment -name TOP_LEVEL_ENTITY sprint1_mist # ================== set_global_assignment -name DEVICE EP3C25E144C8 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON diff --git a/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/README.txt b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/README.txt new file mode 100644 index 00000000..ae7b00c9 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/README.txt @@ -0,0 +1,18 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Super Breakout from james10952001 +-- Port to MiST by Gehstock +-- 23 November 2018 +-- + +-- +-- Keyboard inputs : +-- ESC : Coin +-- F1 or F2 : Start +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- + +todo: Fix Controls \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/SuperBreakout.qsf b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/SuperBreakout.qsf index 6bd41995..fa50ffe4 100644 --- a/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/SuperBreakout.qsf +++ b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/SuperBreakout.qsf @@ -41,23 +41,8 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16 OCTOBER 10, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd -set_global_assignment -name VHDL_FILE rtl/sync.vhd -set_global_assignment -name VHDL_FILE rtl/playfield.vhd -set_global_assignment -name VHDL_FILE rtl/motion.vhd -set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv # Analysis & Synthesis Assignments # ================================ @@ -72,9 +57,6 @@ set_global_assignment -name TOP_LEVEL_ENTITY super_breakout_mist # ================== set_global_assignment -name DEVICE EP3C25E144C8 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON @@ -153,16 +135,35 @@ set_location_assignment PIN_13 -to CONF_DATA0 # end ENTITY(sprint1_mist) # ------------------------ -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name VHDL_FILE rtl/super_breakout.vhd +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name SYSTEMVERILOG_FILE rtl/super_breakout_mist.sv +set_global_assignment -name VHDL_FILE rtl/super_breakout.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd +set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd +set_global_assignment -name VHDL_FILE rtl/sync.vhd +set_global_assignment -name VHDL_FILE rtl/playfield.vhd +set_global_assignment -name VHDL_FILE rtl/motion.vhd +set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv +set_global_assignment -name VERILOG_FILE rtl/pll.v set_global_assignment -name VHDL_FILE rtl/audio.vhd set_global_assignment -name VHDL_FILE rtl/paddle.vhd set_global_assignment -name VHDL_FILE rtl/IO.vhd set_global_assignment -name VHDL_FILE rtl/quadrature_decoder.vhd -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name VHDL_FILE rtl/sprom.vhd set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rom.mem b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/pll.qip similarity index 100% rename from Computer_MiST/Oric Atmos_MiST/storage/rom.mem rename to Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/pll.qip diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/pll.qip b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/pll.qip similarity index 68% rename from Console_MiST/Bally - Astrocade_MiST/rtl/pll.qip rename to Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/pll.qip index 68624e41..aaef684a 100644 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/pll.qip +++ b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/pll.qip @@ -1,4 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_VERSION "13.0" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/pll.v b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/pll.v index 6a352243..aec82b25 100644 --- a/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/pll.v +++ b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/pll.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version // ************************************************************ -//Copyright (C) 1991-2014 Altera Corporation +//Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing @@ -40,26 +40,30 @@ module pll ( inclk0, c0, c1, + c2, locked); input inclk0; output c0; output c1; + output c2; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; wire locked = sub_wire2; wire c0 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; altpll altpll_component ( - .inclk (sub_wire5), + .inclk (sub_wire6), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -100,12 +104,16 @@ module pll ( altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 125, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 224, + altpll_component.clk0_multiply_by = 112, altpll_component.clk0_phase_shift = "0", altpll_component.clk1_divide_by = 125, altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 56, altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 125, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 28, + altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -140,7 +148,7 @@ module pll ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_USED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -181,10 +189,13 @@ endmodule // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.383999" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.191999" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.048000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -206,25 +217,33 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "224" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "112" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "28" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.38400000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.19200000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.04800000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -248,25 +267,32 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "224" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "28" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -300,7 +326,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -319,12 +345,14 @@ endmodule // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE diff --git a/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv index 20f01e14..024bcd50 100644 --- a/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv +++ b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv @@ -38,13 +38,14 @@ wire ps2_kbd_clk, ps2_kbd_data; wire [7:0] audio; wire video; -wire clk_48, clk_12; +wire clk_24, clk_12, clk_6; wire locked; pll pll ( .inclk0(CLOCK_27), - .c0(clk_48),//48.384 + .c0(clk_24),//24.192 .c1(clk_12),//12.096 + .c2(clk_6),//6.048 .locked(locked) ); @@ -71,7 +72,7 @@ super_breakout super_breakout ( .Slam_I(), .Serve_I(~kbjoy[4]), .Test_I(~status[1]), - .Lamp1_O(~LED), + .Lamp1_O(), .Lamp2_O(), .Serve_LED_O(), .Counter_O() @@ -91,15 +92,18 @@ wire hb, vb; wire blankn = ~(hb | vb); video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer ( - .clk_sys(clk_48), - .ce_pix(clk_12), - .ce_pix_actual(clk_12), + .clk_sys(clk_24), + .ce_pix(clk_6), + .ce_pix_actual(clk_6), .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), .SPI_DI(SPI_DI), - .R(blankn ? {video,video,video} : "000"), - .G(blankn ? {video,video,video} : "000"), - .B(blankn ? {video,video,video} : "000"), + .R({video,video,video}), + .G({video,video,video}), + .B({video,video,video}), +// .R(blankn ? {video,video,video} : "000"), +// .G(blankn ? {video,video,video} : "000"), +// .B(blankn ? {video,video,video} : "000"), .HSync(hs), .VSync(vs), .VGA_R(VGA_R), @@ -117,7 +121,7 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ( - .clk_sys (clk_48 ), + .clk_sys (clk_24 ), .conf_str (CONF_STR ), .SPI_SCK (SPI_SCK ), .CONF_DATA0 (CONF_DATA0 ), @@ -136,7 +140,7 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ); keyboard keyboard( - .clk(clk_48), + .clk(clk_24), .reset(), .ps2_kbd_clk(ps2_kbd_clk), .ps2_kbd_data(ps2_kbd_data), diff --git a/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/snapshot/SuperBreakout.rbf b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/snapshot/SuperBreakout.rbf index 111dab4a..75c45c5f 100644 Binary files a/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/snapshot/SuperBreakout.rbf and b/Arcade_MiST/Atari-Hardware/SuperBreakout_MiST/snapshot/SuperBreakout.rbf differ diff --git a/Arcade_MiST/Atari-Hardware/UltraTank_MiST/README.txt b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/README.txt new file mode 100644 index 00000000..e2a67238 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/README.txt @@ -0,0 +1,18 @@ +--------------------------------------------------------------------------------- +-- +-- Arcade: Ultra Tank from james10952001 +-- Port to MiST by Gehstock +-- 23 November 2018 +-- + +-- +-- Keyboard inputs : +-- ESC : Coin +-- F1 or F2 : Start +-- +-- Joystick support. +-- +-- +--------------------------------------------------------------------------------- + +todo: Fix Video and Controls \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/pll.v b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/pll.v index 6a352243..aec82b25 100644 --- a/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/pll.v +++ b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/pll.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version // ************************************************************ -//Copyright (C) 1991-2014 Altera Corporation +//Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing @@ -40,26 +40,30 @@ module pll ( inclk0, c0, c1, + c2, locked); input inclk0; output c0; output c1; + output c2; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; wire locked = sub_wire2; wire c0 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; altpll altpll_component ( - .inclk (sub_wire5), + .inclk (sub_wire6), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -100,12 +104,16 @@ module pll ( altpll_component.bandwidth_type = "AUTO", altpll_component.clk0_divide_by = 125, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 224, + altpll_component.clk0_multiply_by = 112, altpll_component.clk0_phase_shift = "0", altpll_component.clk1_divide_by = 125, altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 56, altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 125, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 28, + altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -140,7 +148,7 @@ module pll ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_USED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -181,10 +189,13 @@ endmodule // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.383999" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.191999" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.048000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -206,25 +217,33 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "224" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "112" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "28" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.38400000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.19200000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.04800000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -248,25 +267,32 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "224" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "28" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -300,7 +326,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -319,12 +345,14 @@ endmodule // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE diff --git a/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/ultra_tank.vhd b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/ultra_tank.vhd index 11a82e92..4d5f1938 100644 --- a/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/ultra_tank.vhd +++ b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/ultra_tank.vhd @@ -26,8 +26,7 @@ entity ultra_tank is port( clk_12 : in std_logic; -- 50MHz input clock Reset_n : in std_logic; -- Reset button (Active low) - Video1_O : out std_logic; -- White video output (680 Ohm) - Video2_O : out std_logic; -- Black video output (1.2k) + Video : out std_logic_vector(1 downto 0); Sync_O : out std_logic; -- Composite sync output (1.2k) Blank_O : out std_logic; -- Composite blank output HS : out std_logic; @@ -159,8 +158,8 @@ port map( CC1 => CC1_O, CC0 => CC0_O, White => White_O, - PF_Vid1 => Video1_O, - PF_Vid2 => Video2_O + PF_Vid1 => Video(0), + PF_Vid2 => Video(1) ); diff --git a/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/ultratank_mist.sv b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/ultratank_mist.sv index 1b8a482d..77f2b1e4 100644 --- a/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/ultratank_mist.sv +++ b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/rtl/ultratank_mist.sv @@ -36,23 +36,23 @@ wire scandoubler_disable; wire ypbpr; wire ps2_kbd_clk, ps2_kbd_data; wire [6:0] audio1, audio2; -wire video1, video2; +wire [1:0] video; wire clk_48, clk_12; wire locked; pll pll ( .inclk0(CLOCK_27), - .c0(clk_48),//48.384 + .c0(clk_24),//24.192 .c1(clk_12),//12.096 + .c2(clk_6),//6.048 .locked(locked) ); ultra_tank ultra_tank ( .clk_12(clk_12), .Reset_n(~(status[0] | status[6] | buttons[1])), - .Video1_O(video1),// White video output (680 Ohm) - .Video2_O(video2),// Black video output (1.2k) + .Video(video), .Sync_O(), .Blank_O(), .HS(hs), @@ -91,14 +91,14 @@ ultra_tank ultra_tank ( ); dac dac1 ( - .CLK(clk_48), + .CLK(clk_24), .RESET(1'b0), .DACin(audio1), .DACout(AUDIO_L) ); dac dac2 ( - .CLK(clk_48), + .CLK(clk_24), .RESET(1'b0), .DACin(audio2), .DACout(AUDIO_R) @@ -107,17 +107,17 @@ dac dac2 ( wire hs, vs; wire hb, vb; wire blankn = ~(hb | vb); -video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer +video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer ( - .clk_sys(clk_48), - .ce_pix(clk_12), - .ce_pix_actual(clk_12), + .clk_sys(clk_24), + .ce_pix(clk_6), + .ce_pix_actual(clk_6), .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), .SPI_DI(SPI_DI), - .R(blankn ? {video1&video2,video1&video2,video1&video2} : "000"), - .G(blankn ? {video1&video2,video1&video2,video1&video2} : "000"), - .B(blankn ? {video1&video2,video1&video2,video1&video2} : "000"), + .R({video&video,video}), + .G({video&video,video}), + .B({video&video,video}), .HSync(hs), .VSync(vs), .VGA_R(VGA_R), @@ -135,7 +135,7 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ( - .clk_sys (clk_48 ), + .clk_sys (clk_24 ), .conf_str (CONF_STR ), .SPI_SCK (SPI_SCK ), .CONF_DATA0 (CONF_DATA0 ), @@ -154,7 +154,7 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ); keyboard keyboard( - .clk(clk_48), + .clk(clk_24), .reset(), .ps2_kbd_clk(ps2_kbd_clk), .ps2_kbd_data(ps2_kbd_data), diff --git a/Arcade_MiST/Atari-Hardware/UltraTank_MiST/ultratank.qsf b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/ultratank.qsf index f175df88..7c664a21 100644 --- a/Arcade_MiST/Atari-Hardware/UltraTank_MiST/ultratank.qsf +++ b/Arcade_MiST/Atari-Hardware/UltraTank_MiST/ultratank.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16 OCTOBER 10, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files # Analysis & Synthesis Assignments @@ -57,9 +57,6 @@ set_global_assignment -name TOP_LEVEL_ENTITY ultratank_mist # ================== set_global_assignment -name DEVICE EP3C25E144C8 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON diff --git a/Computer_MiST/Acorn - Electron_MiST/rtl/ElectronFpga_MiST - Kopie.vhd b/Computer_MiST/Acorn - Electron_MiST/rtl/ElectronFpga_MiST - Kopie.vhd deleted file mode 100644 index 56c13fec..00000000 --- a/Computer_MiST/Acorn - Electron_MiST/rtl/ElectronFpga_MiST - Kopie.vhd +++ /dev/null @@ -1,113 +0,0 @@ --------------------------------------------------------------------------------- --- Copyright (c) 2015 David Banks --------------------------------------------------------------------------------- --- ____ ____ --- / /\/ / --- /___/ \ / --- \ \ \/ --- \ \ --- / / Filename : ElectronFpga.vhf --- /___/ /\ Timestamp : 28/07/2015 --- \ \ / \ --- \___\/\___\ --- ---Design Name: ElectronFpga ---Device: Spartan6 LX9 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -entity ElectronFpga_MiST is - port ( - CLOCK_27 : in std_logic; - - VGA_R : out std_logic_vector (2 downto 0); - VGA_G : out std_logic_vector (2 downto 0); - VGA_B : out std_logic_vector (2 downto 0); - VGA_VS : out std_logic; - VGA_HS : out std_logic; - AUDIO_L : out std_logic; - AUDIO_R : out std_logic; - casIn : in std_logic; - casOut : out std_logic; - LED : out std_logic; - SDMISO : in std_logic; - SDSS : out std_logic; - SDCLK : out std_logic; - SDMOSI : out std_logic - ); -end; - -architecture behavioral of ElectronFpga_MiST is - - signal clk_16M00 : std_logic; - signal clk_33M33 : std_logic; - signal clk_40M00 : std_logic; - signal ERSTn : std_logic; - signal ps2_clk : std_logic; - signal ps2_data : std_logic; - signal pwrup_RSTn : std_logic; - signal reset_ctr : std_logic_vector (7 downto 0) := (others => '0'); - - component pll27 - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC - ); -end component; - - -begin - -pll27_inst : pll27 PORT MAP ( - inclk0 => CLOCK_27, - c0 => clk_40M00, - c1 => clk_16M00, - c2 => clk_33M33 - ); - - - inst_ElectronFpga_core : entity work.ElectronFpga_core - port map ( - clk_16M00 => clk_16M00, - clk_33M33 => clk_33M33, - clk_40M00 => clk_40M00, - ps2_clk => ps2_clk, - ps2_data => ps2_data, - ERSTn => ERSTn, - red => VGA_R, - green => VGA_G, - blue => VGA_B, - vsync => VGA_VS, - hsync => VGA_HS, - audiol => AUDIO_L, - audioR => AUDIO_R, - casIn => casIn, - casOut => casOut, - LED1 => LED, - SDMISO => SDMISO, - SDSS => SDSS, - SDCLK => SDCLK, - SDMOSI => SDMOSI - ); - - ERSTn <= pwrup_RSTn; - - -- This internal counter forces power up reset to happen - -- This is needed by the GODIL to initialize some of the registers - ResetProcess : process (clk_16M00) - begin - if rising_edge(clk_16M00) then - if (pwrup_RSTn = '0') then - reset_ctr <= reset_ctr + 1; - end if; - end if; - end process; - pwrup_RSTn <= reset_ctr(7); - -end behavioral; diff --git a/Computer_MiST/Galaksija_MiST/Galaksija3 (1).png b/Computer_MiST/Galaksija_MiST/Galaksija3 (1).png deleted file mode 100644 index 3151add6..00000000 Binary files a/Computer_MiST/Galaksija_MiST/Galaksija3 (1).png and /dev/null differ diff --git a/Computer_MiST/Galaksija_MiST/Galaksija3.png b/Computer_MiST/Galaksija_MiST/Galaksija3.png deleted file mode 100644 index 705979fc..00000000 Binary files a/Computer_MiST/Galaksija_MiST/Galaksija3.png and /dev/null differ diff --git a/Computer_MiST/Galaksija_MiST/GalaksijaPlus2.png b/Computer_MiST/Galaksija_MiST/GalaksijaPlus2.png deleted file mode 100644 index 6cc05554..00000000 Binary files a/Computer_MiST/Galaksija_MiST/GalaksijaPlus2.png and /dev/null differ diff --git a/Computer_MiST/Galaksija_MiST/GalaksijaPlus3.png b/Computer_MiST/Galaksija_MiST/GalaksijaPlus3.png deleted file mode 100644 index cfd394a7..00000000 Binary files a/Computer_MiST/Galaksija_MiST/GalaksijaPlus3.png and /dev/null differ diff --git a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qpf b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qpf deleted file mode 100644 index e6a13e46..00000000 --- a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 14:32:28 October 06, 2018 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.0" -DATE = "14:32:28 October 06, 2018" - -# Revisions - -PROJECT_REVISION = "Galaksija_Mist" -PROJECT_REVISION = "AtomElectron_Mist" diff --git a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf deleted file mode 100644 index 924d9325..00000000 --- a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf +++ /dev/null @@ -1,222 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 23:16:13 October 05, 2018 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# AtomElectron_Mist_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53 MARCH 09, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PIN_31 -to UART_RXD -set_location_assignment PIN_46 -to UART_TXD -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY Galaksija_MiST -set_global_assignment -name SEARCH_PATH roms/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/MC6522/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/RAM/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/T6502/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/ps2kybrd/ -tag from_archive - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ------------------------------- -# start ENTITY(AtomElectron_Mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(AtomElectron_Mist) -# ----------------------------- -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaksija_MiST.sv -set_global_assignment -name VERILOG_FILE rtl/galaksija_top.v -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/dpram.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name VERILOG_FILE rtl/video.v -set_global_assignment -name VERILOG_FILE rtl/TV80/tv80n.v -set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_reg.v -set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_mcode.v -set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_core.v -set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_alu.v -set_global_assignment -name VHDL_FILE rtl/galaksija_keyboard_v2.vhd -set_global_assignment -name VHDL_FILE rtl/keyboard.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/ay8910.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Computer_MiST/Galaksija_MiST/README.txt b/Computer_MiST/Galaksija_MiST/README.txt deleted file mode 100644 index 7f32ef26..00000000 --- a/Computer_MiST/Galaksija_MiST/README.txt +++ /dev/null @@ -1,7 +0,0 @@ -WIP - -VGA Only, No Keyboard - -32k Ram -Rom 1+2 -AY8910 diff --git a/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf b/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf deleted file mode 100644 index a641d5f9..00000000 Binary files a/Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf and /dev/null differ diff --git a/Computer_MiST/Galaksija_MiST/The+package+Truth+Tables+and+Boolean+Algebra+set+out+the+basic+principles+of+logic..jpg b/Computer_MiST/Galaksija_MiST/The+package+Truth+Tables+and+Boolean+Algebra+set+out+the+basic+principles+of+logic..jpg deleted file mode 100644 index bae3333d..00000000 Binary files a/Computer_MiST/Galaksija_MiST/The+package+Truth+Tables+and+Boolean+Algebra+set+out+the+basic+principles+of+logic..jpg and /dev/null differ diff --git a/Computer_MiST/Galaksija_MiST/galaxy.cpp b/Computer_MiST/Galaksija_MiST/galaxy.cpp deleted file mode 100644 index 2fe5eb55..00000000 --- a/Computer_MiST/Galaksija_MiST/galaxy.cpp +++ /dev/null @@ -1,278 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Krzysztof Strzecha, Miodrag Milanovic -/*************************************************************************** -Galaksija driver by Krzysztof Strzecha and Miodrag Milanovic - -22/05/2008 Tape support added (Miodrag Milanovic) -21/05/2008 Galaksija plus initial support (Miodrag Milanovic) -20/05/2008 Added real video implementation (Miodrag Milanovic) -18/04/2005 Possibilty to disable ROM 2. 2k, 22k, 38k and 54k memory - configurations added. -13/03/2005 Memory mapping improved. Palette corrected. Supprort for newer - version of snapshots added. Lot of cleanups. Keyboard mapping - corrected. -19/09/2002 malloc() replaced by image_malloc(). -15/09/2002 Snapshot loading fixed. Code cleanup. -31/01/2001 Snapshot loading corrected. -09/01/2001 Fast mode implemented (many thanks to Kevin Thacker). -07/01/2001 Keyboard corrected (still some keys unknown). - Horizontal screen positioning in video subsystem added. -05/01/2001 Keyboard implemented (some keys unknown). -03/01/2001 Snapshot loading added. -01/01/2001 Preliminary driver. - -***************************************************************************/ - -#include "emu.h" -#include "includes/galaxy.h" - -#include "cpu/z80/z80.h" -#include "formats/gtp_cas.h" -#include "imagedev/cassette.h" -#include "imagedev/snapquik.h" -#include "machine/ram.h" -#include "sound/ay8910.h" -#include "sound/wave.h" -#include "emupal.h" -#include "screen.h" -#include "softlist.h" -#include "speaker.h" - - -void galaxy_state::galaxyp_io(address_map &map) -{ - map.global_mask(0x01); - map.unmap_value_high(); - map(0x00, 0x00).w("ay8910", FUNC(ay8910_device::address_w)); - map(0x01, 0x01).w("ay8910", FUNC(ay8910_device::data_w)); -} - - -void galaxy_state::galaxy_mem(address_map &map) -{ - map(0x0000, 0x0fff).rom(); - map(0x2000, 0x2037).mirror(0x07c0).r(FUNC(galaxy_state::galaxy_keyboard_r)); - map(0x2038, 0x203f).mirror(0x07c0).w(FUNC(galaxy_state::galaxy_latch_w)); -} - -void galaxy_state::galaxyp_mem(address_map &map) -{ - map(0x0000, 0x0fff).rom(); // ROM A - map(0x1000, 0x1fff).rom(); // ROM B - map(0x2000, 0x2037).mirror(0x07c0).r(FUNC(galaxy_state::galaxy_keyboard_r)); - map(0x2038, 0x203f).mirror(0x07c0).w(FUNC(galaxy_state::galaxy_latch_w)); - map(0xe000, 0xefff).rom(); // ROM C - map(0xf000, 0xffff).rom(); // ROM D -} - -/* 2008-05 FP: -Small note about natural keyboard support. Currently: -- "List" is mapped to 'ESC' -- "Break" is mapped to 'F1' -- "Repeat" is mapped to 'F2' */ - -static INPUT_PORTS_START (galaxy_common) - PORT_START("LINE0") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('A') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('B') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('C') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('D') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('E') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('F') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('G') - - PORT_START("LINE1") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('H') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('I') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('J') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('K') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('L') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('M') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('N') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('O') - - PORT_START("LINE2") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('P') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('Q') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('R') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('S') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('T') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('U') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('V') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('W') - - PORT_START("LINE3") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('X') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('Y') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('Z') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP)) - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN)) - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT)) - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT)) - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ') - - PORT_START("LINE4") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('_') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'') - - PORT_START("LINE5") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(') - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')') - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+') - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*') - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<') - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('-') - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>') - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') - - PORT_START("LINE6") - PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13) - PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Break") PORT_CODE(KEYCODE_PAUSE) PORT_CHAR(UCHAR_MAMEKEY(F1)) - PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Repeat") PORT_CODE(KEYCODE_LALT) PORT_CHAR(UCHAR_MAMEKEY(F2)) - PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Delete") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) - PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("List") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC)) - PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1) - PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_UNUSED) - PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_UNUSED) -INPUT_PORTS_END - -static INPUT_PORTS_START( galaxy ) - PORT_INCLUDE( galaxy_common ) - PORT_START("ROM2") - PORT_CONFNAME(0x01, 0x01, "ROM 2") - PORT_CONFSETTING(0x01, "Installed") - PORT_CONFSETTING(0x00, "Not installed") -INPUT_PORTS_END - -static INPUT_PORTS_START( galaxyp ) - PORT_INCLUDE( galaxy_common ) -INPUT_PORTS_END - -#define XTAL 6144000 - -/* F4 Character Displayer */ -static const gfx_layout galaxy_charlayout = -{ - 8, 16, /* 8 x 16 characters */ - 128, /* 128 characters */ - 1, /* 1 bits per pixel */ - { 0 }, /* no bitplanes */ - /* x offsets */ - { 7, 6, 5, 4, 3, 2, 1, 0 }, - /* y offsets */ - { 0, 1*128*8, 2*128*8, 3*128*8, 4*128*8, 5*128*8, 6*128*8, 7*128*8, 8*128*8, 9*128*8, 10*128*8, 11*128*8, 12*128*8, 13*128*8, 14*128*8, 15*128*8 }, - 8 /* every char takes 1 x 16 bytes */ -}; - -static GFXDECODE_START( gfx_galaxy ) - GFXDECODE_ENTRY( "gfx1", 0x0000, galaxy_charlayout, 0, 1 ) -GFXDECODE_END - - -MACHINE_CONFIG_START(galaxy_state::galaxy) - /* basic machine hardware */ - MCFG_DEVICE_ADD("maincpu", Z80, XTAL / 2) - MCFG_DEVICE_PROGRAM_MAP(galaxy_mem) - MCFG_DEVICE_VBLANK_INT_DRIVER("screen", galaxy_state, galaxy_interrupt) - MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(galaxy_state,galaxy_irq_callback) - - MCFG_SCREEN_ADD("screen", RASTER) - MCFG_SCREEN_REFRESH_RATE(50) - MCFG_SCREEN_PALETTE("palette") - - MCFG_MACHINE_RESET_OVERRIDE(galaxy_state, galaxy ) - - /* video hardware */ - MCFG_SCREEN_SIZE(384, 212) - MCFG_SCREEN_VISIBLE_AREA(0, 384-1, 0, 208-1) - MCFG_SCREEN_UPDATE_DRIVER(galaxy_state, screen_update_galaxy) - - MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_galaxy) - MCFG_PALETTE_ADD_MONOCHROME("palette") - - - /* snapshot */ - MCFG_SNAPSHOT_ADD("snapshot", galaxy_state, galaxy, "gal", 0) - - SPEAKER(config, "mono").front_center(); - WAVE(config, "wave", "cassette").add_route(ALL_OUTPUTS, "mono", 0.25); - - MCFG_CASSETTE_ADD( "cassette" ) - MCFG_CASSETTE_FORMATS(gtp_cassette_formats) - MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_SPEAKER_ENABLED | CASSETTE_MOTOR_ENABLED) - MCFG_CASSETTE_INTERFACE("galaxy_cass") - - MCFG_SOFTWARE_LIST_ADD("cass_list","galaxy") - - /* internal ram */ - RAM(config, RAM_TAG).set_default_size("6K").set_extra_options("2K,22K,38K,54K"); -MACHINE_CONFIG_END - -MACHINE_CONFIG_START(galaxy_state::galaxyp) - /* basic machine hardware */ - MCFG_DEVICE_ADD("maincpu", Z80, XTAL / 2) - MCFG_DEVICE_PROGRAM_MAP(galaxyp_mem) - MCFG_DEVICE_IO_MAP(galaxyp_io) - MCFG_DEVICE_VBLANK_INT_DRIVER("screen", galaxy_state, galaxy_interrupt) - MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(galaxy_state,galaxy_irq_callback) - - MCFG_SCREEN_ADD("screen", RASTER) - MCFG_SCREEN_REFRESH_RATE(50) - MCFG_SCREEN_PALETTE("palette") - - MCFG_MACHINE_RESET_OVERRIDE(galaxy_state, galaxyp ) - - /* video hardware */ - MCFG_SCREEN_SIZE(384, 208) - MCFG_SCREEN_VISIBLE_AREA(0, 384-1, 0, 208-1) - MCFG_SCREEN_UPDATE_DRIVER(galaxy_state, screen_update_galaxy) - - MCFG_PALETTE_ADD_MONOCHROME("palette") - - - /* snapshot */ - MCFG_SNAPSHOT_ADD("snapshot", galaxy_state, galaxy, "gal", 0) - - /* sound hardware */ - SPEAKER(config, "mono").front_center(); - MCFG_DEVICE_ADD("ay8910", AY8910, XTAL/4) // FIXME: really no output routes for this AY? - WAVE(config, "wave", "cassette").add_route(ALL_OUTPUTS, "mono", 0.25); - - MCFG_CASSETTE_ADD( "cassette" ) - MCFG_CASSETTE_FORMATS(gtp_cassette_formats) - MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_SPEAKER_ENABLED | CASSETTE_MOTOR_ENABLED) - MCFG_CASSETTE_INTERFACE("galaxy_cass") - - MCFG_SOFTWARE_LIST_ADD("cass_list","galaxy") - - /* internal ram */ - RAM(config, RAM_TAG).set_default_size("38K"); -MACHINE_CONFIG_END - -ROM_START (galaxy) - ROM_REGION (0x10000, "maincpu", ROMREGION_ERASEFF) - ROM_LOAD ("galrom1.bin", 0x0000, 0x1000, CRC(dc970a32) SHA1(dfc92163654a756b70f5a446daf49d7534f4c739)) - ROM_LOAD_OPTIONAL ("galrom2.bin", 0x1000, 0x1000, CRC(5dc5a100) SHA1(5d5ab4313a2d0effe7572bb129193b64cab002c1)) - ROM_REGION(0x0800, "gfx1",0) - ROM_LOAD ("galchr.bin", 0x0000, 0x0800, CRC(5c3b5bb5) SHA1(19429a61dc5e55ddec3242a8f695e06dd7961f88)) -ROM_END - -ROM_START (galaxyp) - ROM_REGION (0x10000, "maincpu", ROMREGION_ERASEFF) - ROM_LOAD ("galrom1.bin", 0x0000, 0x1000, CRC(dc970a32) SHA1(dfc92163654a756b70f5a446daf49d7534f4c739)) - ROM_LOAD ("galrom2.bin", 0x1000, 0x1000, CRC(5dc5a100) SHA1(5d5ab4313a2d0effe7572bb129193b64cab002c1)) - ROM_LOAD ("galplus.bin", 0xe000, 0x1000, CRC(d4cfab14) SHA1(b507b9026844eeb757547679907394aa42055eee)) - ROM_REGION(0x0800, "gfx1",0) - ROM_LOAD ("galchr.bin", 0x0000, 0x0800, CRC(5c3b5bb5) SHA1(19429a61dc5e55ddec3242a8f695e06dd7961f88)) -ROM_END - -/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */ -COMP( 1983, galaxy, 0, 0, galaxy, galaxy, galaxy_state, init_galaxy, "Voja Antonic / Elektronika inzenjering", "Galaksija", 0) -COMP( 1985, galaxyp, galaxy, 0, galaxyp, galaxyp, galaxy_state, init_galaxyp, "Nenad Dunjic", "Galaksija plus", 0) diff --git a/Computer_MiST/Galaksija_MiST/galaxy.h b/Computer_MiST/Galaksija_MiST/galaxy.h deleted file mode 100644 index 0c132797..00000000 --- a/Computer_MiST/Galaksija_MiST/galaxy.h +++ /dev/null @@ -1,69 +0,0 @@ -// license:BSD-3-Clause -// copyright-holders:Krzysztof Strzecha, Miodrag Milanovic -/***************************************************************************** - * - * includes/galaxy.h - * - ****************************************************************************/ - -#ifndef MAME_INCLUDES_GALAXY_H -#define MAME_INCLUDES_GALAXY_H - -#include "imagedev/snapquik.h" -#include "imagedev/cassette.h" -#include "machine/ram.h" -#include "screen.h" - -class galaxy_state : public driver_device -{ -public: - galaxy_state(const machine_config &mconfig, device_type type, const char *tag) - : driver_device(mconfig, type, tag) - , m_maincpu(*this, "maincpu") - , m_screen(*this, "screen") - , m_cassette(*this, "cassette") - , m_ram(*this, RAM_TAG) - , m_region_gfx1(*this, "gfx1") {} - - void galaxy(machine_config &config); - void galaxyp(machine_config &config); - - void init_galaxy(); - void init_galaxyp(); - -private: - DECLARE_READ8_MEMBER(galaxy_keyboard_r); - DECLARE_WRITE8_MEMBER(galaxy_latch_w); - virtual void video_start() override; - DECLARE_MACHINE_RESET(galaxy); - DECLARE_MACHINE_RESET(galaxyp); - uint32_t screen_update_galaxy(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); - INTERRUPT_GEN_MEMBER(galaxy_interrupt); - TIMER_CALLBACK_MEMBER(gal_video); - IRQ_CALLBACK_MEMBER(galaxy_irq_callback); - void galaxy_set_timer(); - void galaxy_setup_snapshot (const uint8_t * data, uint32_t size); - DECLARE_SNAPSHOT_LOAD_MEMBER( galaxy ); - void galaxy_mem(address_map &map); - void galaxyp_io(address_map &map); - void galaxyp_mem(address_map &map); - - required_device m_maincpu; - required_device m_screen; - required_device m_cassette; - required_device m_ram; - required_memory_region m_region_gfx1; - ioport_port *m_io_ports[8]; - - int m_interrupts_enabled; - uint8_t m_latch_value; - uint32_t m_gal_cnt; - uint8_t m_code; - uint8_t m_first; - uint32_t m_start_addr; - emu_timer *m_gal_video_timer; - bitmap_ind16 m_bitmap; -}; - - -#endif // MAME_INCLUDES_GALAXY_H diff --git a/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv b/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv deleted file mode 100644 index ca8df81c..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv +++ /dev/null @@ -1,136 +0,0 @@ -module Galaksija_MiST( - input CLOCK_27, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output LED, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0/*, - output [12:0] SDRAM_A, - inout [15:0] SDRAM_DQ, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nWE, - output SDRAM_nCAS, - output SDRAM_nRAS, - output SDRAM_nCS, - output [1:0] SDRAM_BA, - output SDRAM_CLK, - output SDRAM_CKE*/ - ); - -`include "build_id.v" -localparam CONF_STR = { - "Galaksija;;", -// "F,GAL,Load Program;", - "O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", - "T9,Reset;", - "V,v1.00.",`BUILD_DATE -}; -wire clk_1p7, clk_25, clk_6p25; -wire ps2_kbd_clk, ps2_kbd_data; -wire [2:0] r, g; -wire [1:0] b; -wire hs, vs; -wire [1:0] buttons, switches; -wire ypbpr; -wire forced_scandoubler; -wire [31:0] status; -wire [7:0] audio; - - -pll pll ( - .inclk0 ( CLOCK_27 ), - .c0 ( clk_1p7 ), - .c1 ( clk_25 ), - .c2 ( clk_6p25 ) - ); - - -mist_io #( - .STRLEN($size(CONF_STR)>>3)) -user_io ( - .clk_sys(clk_25), - .CONF_DATA0(CONF_DATA0), - .SPI_SCK(SPI_SCK), - .SPI_DI(SPI_DI), - .SPI_DO(SPI_DO), - .SPI_SS2(SPI_SS2), - .conf_str(CONF_STR), - .ypbpr(ypbpr), - .status(status), - .scandoubler_disable(forced_scandoubler), - .buttons(buttons), - .switches(switches), - .ps2_kbd_clk(ps2_kbd_clk), - .ps2_kbd_data(ps2_kbd_data)/*, - .joystick_0(joystick_0), - .joystick_1(joystick_1), - .ioctl_wr(ioctl_wr), - .ioctl_index(ioctl_index), - .ioctl_download(ioctl_download), - .ioctl_addr(ioctl_addr), - .ioctl_dout(ioctl_dout)*/ - ); - -video_mixer #( - .LINE_LENGTH(320), - .HALF_DEPTH(0)) -video_mixer ( - .clk_sys ( clk_25 ), - .ce_pix ( clk_6p25 ), - .ce_pix_actual ( clk_6p25 ), - .SPI_SCK ( SPI_SCK ), - .SPI_SS3 ( SPI_SS3 ), - .SPI_DI ( SPI_DI ), - .R ( {r,r}), - .G ( {g,g}), - .B ( {2'b0,b,b}), - .HSync ( hs ), - .VSync ( vs ), - .VGA_R ( VGA_R ), - .VGA_G ( VGA_G ), - .VGA_B ( VGA_B ), - .VGA_VS ( VGA_VS ), - .VGA_HS ( VGA_HS ), - .scanlines (forced_scandoubler ? 2'b00 : {status[3:2] == 3, status[3:2] == 2}), - .scandoubler_disable(1'b1),//forced_scandoubler), - .hq2x (status[3:2]==1), - .ypbpr ( ypbpr ), - .ypbpr_full ( 1 ), - .line_start ( 0 ), - .mono ( 0 ) - ); - -galaksija_top galaksija_top ( - .clk(clk_25), - .a_en(clk_1p7), - .pixclk(clk_25), - .reset_n(~(status[0] | status[9] | buttons[1])), - .PS2_DATA(ps2_kbd_data), - .PS2_CLK(ps2_kbd_clk), - .audio(audio), - .LCD_DAT({b,g,r}),//todo - .LCD_HS(hs), - .LCD_VS(vs) -); - -dac #( - .msbi_g(7)) -dac ( - .clk_i(clk_25), - .res_n_i(1'b1), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -assign AUDIO_R = AUDIO_L; -endmodule diff --git a/Computer_MiST/Galaksija_MiST/rtl/ay8910.sv b/Computer_MiST/Galaksija_MiST/rtl/ay8910.sv deleted file mode 100644 index 31d79c50..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/ay8910.sv +++ /dev/null @@ -1,308 +0,0 @@ -// ports are not identical to the actual AY chip - no need for that. -// Also the parallel ports are not very useful, so they are not connected - - - - -module ay8910(rst_n,clk,clk_en,asel,wr_n,cs_n,din,dout,A,B,C,audio); - input rst_n; - input clk; // 28 MHz clock from the system - input clk_en; // 1.7 (?) clock to run the sound timing - input asel; - input wr_n; - input cs_n; - input [7:0] din; - output [7:0] dout; - output [7:0] A; - output [7:0] B; - output [7:0] C; - output [7:0] audio; - - - - -///////////////////////////////////////////////////////////////////////////// -// Write Register -///////////////////////////////////////////////////////////////////////////// - - -reg [3:0] addr; - - -// registers -reg [11:0] period_a,period_b,period_c; -reg [4:0] period_n; -reg [7:0] reg_en; -reg [4:0] vol_a,vol_b,vol_c; -reg [15:0] period_e; -reg [3:0] shape_e; -reg [7:0] pa_r,pb_r; - - -wire pb_od = reg_en[7]; -wire pa_od = reg_en[6]; -wire na = reg_en[5]; -wire nb = reg_en[4]; -wire nc = reg_en[3]; -wire ena = reg_en[2]; -wire enb = reg_en[1]; -wire enc = reg_en[0]; - - -always @(posedge clk) -if(~rst_n) begin - vol_a <= 0; - vol_b <= 0; - vol_c <= 0; -end else - - -if(~wr_n && ~cs_n) begin - if(asel) - begin - // address write - addr <= din[3:0]; - end else begin - // register write - case(addr) - 0:period_a[ 7:0] <= din; - 1:period_a[11:8] <= din[3:0]; - 2:period_b[ 7:0] <= din; - 3:period_b[11:8] <= din[3:0]; - 4:period_c[ 7:0] <= din; - 5:period_c[11:8] <= din[3:0]; - 6:period_n[ 4:0] <= din[4:0]; - 7:reg_en <= din; - 8:vol_a <= din[4:0]; - 9:vol_b <= din[4:0]; - 10:vol_c <= din[4:0]; - 11:period_e[7:0] <= din; - 12:period_e[15:8] <= din; - 13:shape_e <= din[3:0]; - 14:pa_r <= din; - 15:pb_r <= din; - endcase - end -end - - -///////////////////////////////////////////////////////////////////////////// -// Read Register -///////////////////////////////////////////////////////////////////////////// -assign dout = addr==4'h0 ? period_a[7:0] : - addr==4'h1 ? {4'h0,period_a[11:0]} : - addr==4'h2 ? period_b[7:0] : - addr==4'h3 ? {4'h0,period_b[11:0]} : - addr==4'h4 ? period_c[7:0] : - addr==4'h5 ? {4'h0,period_c[11:0]} : - addr==4'h6 ? {3'h0,period_n} : - addr==4'h7 ? reg_en : - addr==4'h8 ? {3'h0,vol_a} : - addr==4'h9 ? {3'h0,vol_b} : - addr==4'ha ? {3'h0,vol_c} : - addr==4'hb ? period_e[7:0] : - addr==4'hc ? period_e[15:8] : - addr==4'hd ? {4'h0,shape_e} : 8'hff; - - - -///////////////////////////////////////////////////////////////////////////// -// PSG -///////////////////////////////////////////////////////////////////////////// - - -// -// toneA 12bit | 12bit -// toneB 12bit | 12bit -// toneC 12bit | 12bit -// env 15bit | 15bit -// -reg [2:0] pris; -reg [11:0] cnt_a,cnt_b,cnt_c; - - -reg out_a,out_b,out_c; - - -always @(posedge clk) -if(clk_en) begin - pris <= pris + 1; - if(pris==0) - begin - // tone generator - cnt_a <= cnt_a + 1; - if(cnt_a==period_a) - begin - out_a <= ~out_a; - cnt_a <= 0; - end - cnt_b <= cnt_b + 1; - if(cnt_b==period_b) - begin - out_b <= ~out_b; - cnt_b <= 0; - end - cnt_c <= cnt_c + 1; - if(cnt_c==period_c) - begin - out_c <= ~out_c; - cnt_c <= 0; - end - end -end - - -///////////////////////////////////////////////////////////////////////////// -// envelope generator -///////////////////////////////////////////////////////////////////////////// -reg [15:0] env_cnt; -reg [3:0] env_phase; -reg env_start; -reg env_en; -reg env_inv; - - -// write eshape -wire env_clr = (addr==13) & ~cs_n & ~wr_n; - - -// bit3 = turn reset , 0=on , 1=off -// bit2 = start , 0=up , 1=down(inv) -// bit1 = turn invert, 0=tggle , 1=fix -// bit0 = turn repeat, 0=off, 1=on - - -wire next_no_reset = shape_e[3]; -wire start_no_inv = shape_e[2]; -wire next_toggle = shape_e[1]; -wire next_repeat = shape_e[0]; - - -// envelope volume output -wire [3:0] vol_e = env_phase ^ {4{env_inv}}; - - -// -always @(posedge clk or posedge env_clr) -begin - if(env_clr) env_start <= 1'b1; - else if(clk_en) env_start <= 1'b0; -end - - -always @(posedge clk or negedge rst_n) -begin - if(~rst_n) - begin - env_en <= 1'b0; - end else - if(clk_en)begin - - - // start trigger - if(env_start) - begin - env_cnt <= 0; - env_phase <= 0; - env_inv <= ~start_no_inv; - env_en <= 1'b1; - end - - - // count - if(pris==0 && env_en) - begin - // phase up - env_cnt <= env_cnt + 1; - if(env_cnt==period_e) - begin - env_cnt <= 0; - env_phase <= env_phase+1; - // turn over - if(env_phase==15) - begin - if(~next_no_reset) - begin - env_inv <= (env_inv ^ next_toggle) & next_no_reset; - env_en <= next_repeat & next_no_reset; - end - end - end - end - end -end - - -///////////////////////////////////////////////////////////////////////////// -// noise generator -///////////////////////////////////////////////////////////////////////////// -reg [16:0] shift_n; -reg [4:0] cnt_n; - - -always @(posedge clk or negedge rst_n) -begin - if(~rst_n) - begin - shift_n <= 17'b00000000000000001; - end else if((pris==0) &&(clk_en)) - begin - cnt_n <= cnt_n +1; - if(cnt_n == period_n) - begin - cnt_n <= 0; - shift_n <= {shift_n[0]^shift_n[3],shift_n[16:1]}; - end - end -end - - -wire out_n = shift_n[0]; - - -///////////////////////////////////////////////////////////////////////////// -// volume table 3db / step -///////////////////////////////////////////////////////////////////////////// -function [7:0] vol_tbl; -input [4:0] vol; -input [3:0] vole; -input out; -begin - if(~out) - vol_tbl = 0; - else case(vol[4]?vole:vol[3:0]) - 15:vol_tbl = 255; - 14:vol_tbl = 180; - 13:vol_tbl = 127; - 12:vol_tbl = 90; - 11:vol_tbl = 64; - 10:vol_tbl = 45; - 9:vol_tbl = 32; - 8:vol_tbl = 22; - 7:vol_tbl = 16; - 6:vol_tbl = 11; - 5:vol_tbl = 8; - 4:vol_tbl = 5; - 3:vol_tbl = 4; - 2:vol_tbl = 3; - 1:vol_tbl = 2; - 0:vol_tbl = 0; //1; - endcase -end -endfunction - - -///////////////////////////////////////////////////////////////////////////// -// output -///////////////////////////////////////////////////////////////////////////// -assign A = vol_tbl(vol_a,vol_e,(out_a | ena) & (out_n | na) ); -assign B = vol_tbl(vol_b,vol_e,(out_b | enb) & (out_n | nb) ); -assign C = vol_tbl(vol_c,vol_e,(out_c | enc) & (out_n | nc) ); -assign audio = {"00",A} + {"00",B} + {"00",C};//todo gehstock - - - - - - -endmodule \ No newline at end of file diff --git a/Computer_MiST/Galaksija_MiST/rtl/build_id.tcl b/Computer_MiST/Galaksija_MiST/rtl/build_id.tcl deleted file mode 100644 index 481e9ebf..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "sys/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Computer_MiST/Galaksija_MiST/rtl/build_id.v b/Computer_MiST/Galaksija_MiST/rtl/build_id.v deleted file mode 100644 index 6efa26c3..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/build_id.v +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "180816" -`define BUILD_TIME "200421" diff --git a/Computer_MiST/Galaksija_MiST/rtl/dac.vhd b/Computer_MiST/Galaksija_MiST/rtl/dac.vhd deleted file mode 100644 index c21b306b..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 7 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Computer_MiST/Galaksija_MiST/rtl/dpram.vhd b/Computer_MiST/Galaksija_MiST/rtl/dpram.vhd deleted file mode 100644 index 672d33d3..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,131 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY dpram IS - GENERIC - ( - init_file : string := ""; - --numwords_a : natural; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED"; - outdata_reg_b : string := "UNREGISTERED" - ); - PORT - ( - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock_a : IN STD_LOGIC ; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - wren_a : IN STD_LOGIC := '1'; - wren_b : IN STD_LOGIC := '1'; - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END dpram; - - -ARCHITECTURE SYN OF dpram IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_reg_b : STRING; - clock_enable_input_a : STRING; - clock_enable_input_b : STRING; - clock_enable_output_a : STRING; - clock_enable_output_b : STRING; - indata_reg_b : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - numwords_b : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_aclr_b : STRING; - outdata_reg_a : STRING; - outdata_reg_b : STRING; - power_up_uninitialized : STRING; - read_during_write_mode_port_a : STRING; - read_during_write_mode_port_b : STRING; - widthad_a : NATURAL; - widthad_b : NATURAL; - width_a : NATURAL; - width_b : NATURAL; - width_byteena_a : NATURAL; - width_byteena_b : NATURAL; - wrcontrol_wraddress_reg_b : STRING - ); - PORT ( - wren_a : IN STD_LOGIC ; - clock0 : IN STD_LOGIC ; - wren_b : IN STD_LOGIC ; - clock1 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q_a <= sub_wire0(width_a-1 DOWNTO 0); - q_b <= sub_wire1(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "BYPASS", - clock_enable_input_b => "BYPASS", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - numwords_b => 2**widthad_a, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => outdata_reg_a, - outdata_reg_b => outdata_reg_a, - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => widthad_a, - widthad_b => widthad_a, - width_a => width_a, - width_b => width_a, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - wren_a => wren_a, - clock0 => clock_a, - wren_b => wren_b, - clock1 => clock_b, - address_a => address_a, - address_b => address_b, - data_a => data_a, - data_b => data_b, - q_a => sub_wire0, - q_b => sub_wire1 - ); - - - -END SYN; diff --git a/Computer_MiST/Galaksija_MiST/rtl/font_rom.v b/Computer_MiST/Galaksija_MiST/rtl/font_rom.v deleted file mode 100644 index eb2a8f54..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/font_rom.v +++ /dev/null @@ -1,16 +0,0 @@ -module font_rom( - input clk, - input [10:0] addr, - output reg [7:0] data_out -); - - reg [7:0] store[0:2047] /* verilator public_flat */; - - initial - begin - $readmemh("galchr.mem", store); - end - - always @(posedge clk) - data_out <= store[addr]; -endmodule diff --git a/Computer_MiST/Galaksija_MiST/rtl/mist_io.v b/Computer_MiST/Galaksija_MiST/rtl/mist_io.v deleted file mode 100644 index 1cfcb753..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/mist_io.v +++ /dev/null @@ -1,496 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoubler_disable, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - input ioctl_wait, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [13:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; - - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [13:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin -// addr <= ioctl_index ? 14'd9 : 14'd0; //.p files loaded at $4009, ROM is at 0 - addr <= 14'd0; - ioctl_download <= 1; - end else begin - ioctl_addr <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - ioctl_addr <= addr; - ioctl_dout <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - ioctl_wr <= 1; - end else - ioctl_wr <= 0; - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -endmodule diff --git a/Computer_MiST/Galaksija_MiST/rtl/osd.v b/Computer_MiST/Galaksija_MiST/rtl/osd.v deleted file mode 100644 index c62c10af..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/osd.v +++ /dev/null @@ -1,179 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [7:0] osd_byte; -always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; - -wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Computer_MiST/Galaksija_MiST/rtl/pll.v b/Computer_MiST/Galaksija_MiST/rtl/pll.v deleted file mode 100644 index cff0ef05..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/pll.v +++ /dev/null @@ -1,357 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: pll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version -// ************************************************************ - - -//Copyright (C) 1991-2013 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module pll ( - inclk0, - c0, - c1, - c2); - - input inclk0; - output c0; - output c1; - output c2; - - wire [4:0] sub_wire0; - wire [0:0] sub_wire6 = 1'h0; - wire [2:2] sub_wire3 = sub_wire0[2:2]; - wire [0:0] sub_wire2 = sub_wire0[0:0]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; - wire c0 = sub_wire2; - wire c2 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; - - altpll altpll_component ( - .inclk (sub_wire5), - .clk (sub_wire0), - .activeclock (), - .areset (1'b0), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b0), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbmimicbidir (), - .fbout (), - .fref (), - .icdrclk (), - .locked (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 1000, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 63, - altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 27, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 25, - altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 108, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 25, - altpll_component.clk2_phase_shift = "0", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 37037, - altpll_component.intended_device_family = "Cyclone III", - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_UNUSED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_UNUSED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", - altpll_component.port_clk3 = "PORT_UNUSED", - altpll_component.port_clk4 = "PORT_UNUSED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena2 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED", - altpll_component.width_clock = 5; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1000" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "108" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.701000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.250000" -// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" -// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "63" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.70000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.25000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" -// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1000" -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "108" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf -// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Computer_MiST/Galaksija_MiST/rtl/scandoubler.v b/Computer_MiST/Galaksija_MiST/rtl/scandoubler.v deleted file mode 100644 index e85cba43..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,183 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Computer_MiST/Galaksija_MiST/rtl/spram.vhd b/Computer_MiST/Galaksija_MiST/rtl/spram.vhd deleted file mode 100644 index d4e8dd90..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/spram.vhd +++ /dev/null @@ -1,90 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY spram IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - power_up_uninitialized : STRING; - read_during_write_mode_port_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - wren_a : IN STD_LOGIC ; - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - wren_a => wren, - clock0 => clock, - address_a => address, - data_a => data, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Computer_MiST/Galaksija_MiST/rtl/vga_controller_640_60.vhd b/Computer_MiST/Galaksija_MiST/rtl/vga_controller_640_60.vhd deleted file mode 100644 index f3e2510b..00000000 --- a/Computer_MiST/Galaksija_MiST/rtl/vga_controller_640_60.vhd +++ /dev/null @@ -1,200 +0,0 @@ ------------------------------------------------------------------------- --- vga_controller_640_60.vhd ------------------------------------------------------------------------- --- Author : Ulrich Zolt --- Copyright 2006 Digilent, Inc. ------------------------------------------------------------------------- --- Software version : Xilinx ISE 7.1.04i --- WebPack --- Device : 3s200ft256-4 ------------------------------------------------------------------------- --- This file contains the logic to generate the synchronization signals, --- horizontal and vertical pixel counter and video disable signal --- for the 640x480@60Hz resolution. ------------------------------------------------------------------------- --- Behavioral description ------------------------------------------------------------------------- --- Please read the following article on the web regarding the --- vga video timings: --- http://www.epanorama.net/documents/pc/vga_timing.html - --- This module generates the video synch pulses for the monitor to --- enter 640x480@60Hz resolution state. It also provides horizontal --- and vertical counters for the currently displayed pixel and a blank --- signal that is active when the pixel is not inside the visible screen --- and the color outputs should be reset to 0. - --- timing diagram for the horizontal synch signal (HS) --- 0 648 744 800 (pixels) --- -------------------------|______|----------------- --- timing diagram for the vertical synch signal (VS) --- 0 482 484 525 (lines) --- -----------------------------------|______|------- - --- The blank signal is delayed one pixel clock period (40ns) from where --- the pixel leaves the visible screen, according to the counters, to --- account for the pixel pipeline delay. This delay happens because --- it takes time from when the counters indicate current pixel should --- be displayed to when the color data actually arrives at the monitor --- pins (memory read delays, synchronization delays). ------------------------------------------------------------------------- --- Port definitions ------------------------------------------------------------------------- --- rst - global reset signal --- pixel_clk - input pin, from dcm_25MHz --- - the clock signal generated by a DCM that has --- - a frequency of 25MHz. --- HS - output pin, to monitor --- - horizontal synch pulse --- VS - output pin, to monitor --- - vertical synch pulse --- hcount - output pin, 11 bits, to clients --- - horizontal count of the currently displayed --- - pixel (even if not in visible area) --- vcount - output pin, 11 bits, to clients --- - vertical count of the currently active video --- - line (even if not in visible area) --- blank - output pin, to clients --- - active when pixel is not in visible area. ------------------------------------------------------------------------- --- Revision History: --- 09/18/2006(UlrichZ): created ------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- the vga_controller_640_60 entity declaration --- read above for behavioral description and port definitions. -entity vga_controller_640_60 is -port( - rst : in std_logic; - pixel_clk : in std_logic; - - HS : out std_logic; - VS : out std_logic; - hcount : out std_logic_vector(10 downto 0); - vcount : out std_logic_vector(10 downto 0); - blank : out std_logic -); -end vga_controller_640_60; - -architecture Behavioral of vga_controller_640_60 is - ------------------------------------------------------------------------- --- CONSTANTS ------------------------------------------------------------------------- - --- maximum value for the horizontal pixel counter -constant HMAX : std_logic_vector(10 downto 0) := "01100100000"; -- 800 --- maximum value for the vertical pixel counter -constant VMAX : std_logic_vector(10 downto 0) := "01000001101"; -- 525 --- total number of visible columns -constant HLINES: std_logic_vector(10 downto 0) := "01010000000"; -- 640 --- value for the horizontal counter where front porch ends -constant HFP : std_logic_vector(10 downto 0) := "01010001000"; -- 648 --- value for the horizontal counter where the synch pulse ends -constant HSP : std_logic_vector(10 downto 0) := "01011101000"; -- 744 --- total number of visible lines -constant VLINES: std_logic_vector(10 downto 0) := "00111100000"; -- 480 --- value for the vertical counter where the front porch ends -constant VFP : std_logic_vector(10 downto 0) := "00111100010"; -- 482 --- value for the vertical counter where the synch pulse ends -constant VSP : std_logic_vector(10 downto 0) := "00111100100"; -- 484 --- polarity of the horizontal and vertical synch pulse --- only one polarity used, because for this resolution they coincide. -constant SPP : std_logic := '0'; - ------------------------------------------------------------------------- --- SIGNALS ------------------------------------------------------------------------- - --- horizontal and vertical counters -signal hcounter : std_logic_vector(10 downto 0) := (others => '0'); -signal vcounter : std_logic_vector(10 downto 0) := (others => '0'); - --- active when inside visible screen area. -signal video_enable: std_logic; - -begin - - -- output horizontal and vertical counters - hcount <= hcounter; - vcount <= vcounter; - - -- blank is active when outside screen visible area - -- color output should be blacked (put on 0) when blank in active - -- blank is delayed one pixel clock period from the video_enable - -- signal to account for the pixel pipeline delay. - blank <= not video_enable when rising_edge(pixel_clk); - - -- increment horizontal counter at pixel_clk rate - -- until HMAX is reached, then reset and keep counting - h_count: process(pixel_clk) - begin - if(rising_edge(pixel_clk)) then - if(rst = '1') then - hcounter <= (others => '0'); - elsif(hcounter = HMAX) then - hcounter <= (others => '0'); - else - hcounter <= hcounter + 1; - end if; - end if; - end process h_count; - - -- increment vertical counter when one line is finished - -- (horizontal counter reached HMAX) - -- until VMAX is reached, then reset and keep counting - v_count: process(pixel_clk) - begin - if(rising_edge(pixel_clk)) then - if(rst = '1') then - vcounter <= (others => '0'); - elsif(hcounter = HMAX) then - if(vcounter = VMAX) then - vcounter <= (others => '0'); - else - vcounter <= vcounter + 1; - end if; - end if; - end if; - end process v_count; - - -- generate horizontal synch pulse - -- when horizontal counter is between where the - -- front porch ends and the synch pulse ends. - -- The HS is active (with polarity SPP) for a total of 96 pixels. - do_hs: process(pixel_clk) - begin - if(rising_edge(pixel_clk)) then - if(hcounter >= HFP and hcounter < HSP) then - HS <= SPP; - else - HS <= not SPP; - end if; - end if; - end process do_hs; - - -- generate vertical synch pulse - -- when vertical counter is between where the - -- front porch ends and the synch pulse ends. - -- The VS is active (with polarity SPP) for a total of 2 video lines - -- = 2*HMAX = 1600 pixels. - do_vs: process(pixel_clk) - begin - if(rising_edge(pixel_clk)) then - if(vcounter >= VFP and vcounter < VSP) then - VS <= SPP; - else - VS <= not SPP; - end if; - end if; - end process do_vs; - - -- enable video output when pixel is in visible area - video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0'; - -end Behavioral; \ No newline at end of file diff --git a/Computer_MiST/HT1080z_MiST/ReadMe.txt b/Computer_MiST/HT1080z_MiST/ReadMe.txt deleted file mode 100644 index 68b127f9..00000000 --- a/Computer_MiST/HT1080z_MiST/ReadMe.txt +++ /dev/null @@ -1,5 +0,0 @@ -HT 1080Z (TSR-80 clone) - - -Copyright (c) 2016-2017 Jozsef Laszlo (rbendr@gmail.com) - diff --git a/Computer_MiST/HT1080z_MiST/clean.bat b/Computer_MiST/HT1080z_MiST/clean.bat deleted file mode 100644 index 748b4d5b..00000000 --- a/Computer_MiST/HT1080z_MiST/clean.bat +++ /dev/null @@ -1,38 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del *.cdf -del *.rpt -del /s new_rtl_netlist -del /s old_rtl_netlist -pause diff --git a/Computer_MiST/HT1080z_MiST/ht1080z.qpf b/Computer_MiST/HT1080z_MiST/ht1080z.qpf deleted file mode 100644 index fa8eb5cc..00000000 --- a/Computer_MiST/HT1080z_MiST/ht1080z.qpf +++ /dev/null @@ -1,31 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 00:15:27 November 10, 2018 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.0" -DATE = "00:15:27 November 10, 2018" - -# Revisions - -PROJECT_REVISION = "ht1080z" -PROJECT_REVISION = "ht1080z_mist" diff --git a/Computer_MiST/HT1080z_MiST/ht1080z.qsf b/Computer_MiST/HT1080z_MiST/ht1080z.qsf deleted file mode 100644 index 2b4f6edd..00000000 --- a/Computer_MiST/HT1080z_MiST/ht1080z.qsf +++ /dev/null @@ -1,222 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 18:00:14 October 22, 2018 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Galaksija_Mist_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53 MARCH 09, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PIN_31 -to UART_RXD -set_location_assignment PIN_46 -to UART_TXD -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY ht1080z -set_global_assignment -name SEARCH_PATH roms/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/MC6522/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/RAM/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/T6502/ -tag from_archive -set_global_assignment -name SEARCH_PATH src/ps2kybrd/ -tag from_archive -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ---------------------------- -# start ENTITY(Galaksija_MiST) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(Galaksija_MiST) -# -------------------------- -set_global_assignment -name VHDL_FILE rtl/ht1080z.vhd -set_global_assignment -name VHDL_FILE rtl/YM2149_linmix.vhd -set_global_assignment -name VHDL_FILE rtl/videoctrl.vhd -set_global_assignment -name VERILOG_FILE rtl/user_io.v -set_global_assignment -name VERILOG_FILE rtl/sdram.v -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name VHDL_FILE rtl/rom16k.vhd -set_global_assignment -name VHDL_FILE rtl/ram16k.vhd -set_global_assignment -name VHDL_FILE rtl/ps2reader.vhd -set_global_assignment -name VHDL_FILE rtl/ps2kbd.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/data_io.v -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Computer_MiST/HT1080z_MiST/rtl/T80/T80.vhd b/Computer_MiST/HT1080z_MiST/rtl/T80/T80.vhd deleted file mode 100644 index 0912e3d3..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1094 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Computer_MiST/HT1080z_MiST/rtl/T80/T80_ALU.vhd b/Computer_MiST/HT1080z_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index 95c98dab..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Computer_MiST/HT1080z_MiST/rtl/T80/T80_MCode.vhd b/Computer_MiST/HT1080z_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 4c15b9ba..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,2028 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Computer_MiST/HT1080z_MiST/rtl/T80/T80_Pack.vhd b/Computer_MiST/HT1080z_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 6904b66b..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,220 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Computer_MiST/HT1080z_MiST/rtl/T80/T80_Reg.vhd b/Computer_MiST/HT1080z_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Computer_MiST/HT1080z_MiST/rtl/T80/T80se.vhd b/Computer_MiST/HT1080z_MiST/rtl/T80/T80se.vhd deleted file mode 100644 index 1b0cb9b5..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/T80/T80se.vhd +++ /dev/null @@ -1,192 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original z80 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0240 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0235 : First release --- --- 0236 : Added T2Write generic --- --- 0237 : Fixed T2Write with wait state --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80se is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CLKEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T80se; - -architecture rtl of T80se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - -begin - - u0 : T80 - generic map( - Mode => Mode, - IOWait => IOWait) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Computer_MiST/HT1080z_MiST/rtl/YM2149_linmix.vhd b/Computer_MiST/HT1080z_MiST/rtl/YM2149_linmix.vhd deleted file mode 100644 index 41a82c33..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/YM2149_linmix.vhd +++ /dev/null @@ -1,623 +0,0 @@ --- --- A simulation model of YM2149 (AY-3-8910 with bells on) - --- Copyright (c) MikeJ - Jan 2005 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 001 initial release --- --- Clues from MAME sound driver and Kazuhiro TSUJIKAWA --- --- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) --- vol 15 .. 0 --- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 --- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order --- to produced all the required values. --- (The first part of the curve is a bit steeper and the last bit is more linear than expected) --- --- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only --- accurate for designs where the outputs are buffered and not simply wired together. --- The ouput level is more complex in that case and requires a larger table. - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity YM2149 is - port ( - -- data bus - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - O_DA_OE_L : out std_logic; - -- control - I_A9_L : in std_logic; - I_A8 : in std_logic; - I_BDIR : in std_logic; - I_BC2 : in std_logic; - I_BC1 : in std_logic; - I_SEL_L : in std_logic; - - O_AUDIO : out std_logic_vector(7 downto 0); - -- port a - I_IOA : in std_logic_vector(7 downto 0); - O_IOA : out std_logic_vector(7 downto 0); - O_IOA_OE_L : out std_logic; - -- port b - I_IOB : in std_logic_vector(7 downto 0); - O_IOB : out std_logic_vector(7 downto 0); - O_IOB_OE_L : out std_logic; - - ENA : in std_logic; -- clock enable for higher speed operation - RESET_L : in std_logic; - CLK : in std_logic -- note 6 Mhz - ); -end; - -architecture RTL of YM2149 is - type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0); - type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); - - signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); - signal noise_div : std_logic := '0'; - signal ena_div : std_logic; - signal ena_div_noise : std_logic; - signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); - - -- registers - signal addr : std_logic_vector(7 downto 0); - signal busctrl_addr : std_logic; - signal busctrl_we : std_logic; - signal busctrl_re : std_logic; - - signal reg : array_16x8; - signal env_reset : std_logic; - signal ioa_inreg : std_logic_vector(7 downto 0); - signal iob_inreg : std_logic_vector(7 downto 0); - - signal noise_gen_cnt : std_logic_vector(4 downto 0); - signal noise_gen_op : std_logic; - signal tone_gen_cnt : array_3x12 := (others => (others => '0')); - signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; - - signal env_gen_cnt : std_logic_vector(15 downto 0); - signal env_ena : std_logic; - signal env_hold : std_logic; - signal env_inc : std_logic; - signal env_vol : std_logic_vector(4 downto 0); - - signal tone_ena_l : std_logic; - signal tone_src : std_logic; - signal noise_ena_l : std_logic; - signal chan_vol : std_logic_vector(4 downto 0); - - signal dac_amp : std_logic_vector(7 downto 0); - signal audio_mix : std_logic_vector(9 downto 0); - signal audio_final : std_logic_vector(9 downto 0); -begin - -- cpu i/f - p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) - variable cs : std_logic; - variable sel : std_logic_vector(2 downto 0); - begin - -- BDIR BC2 BC1 MODE - -- 0 0 0 inactive - -- 0 0 1 address - -- 0 1 0 inactive - -- 0 1 1 read - -- 1 0 0 address - -- 1 0 1 inactive - -- 1 1 0 write - -- 1 1 1 read - busctrl_addr <= '0'; - busctrl_we <= '0'; - busctrl_re <= '0'; - - cs := '0'; - if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then - cs := '1'; - end if; - - sel := (I_BDIR & I_BC2 & I_BC1); - case sel is - when "000" => null; - when "001" => busctrl_addr <= '1'; - when "010" => null; - when "011" => busctrl_re <= cs; - when "100" => busctrl_addr <= '1'; - when "101" => null; - when "110" => busctrl_we <= cs; - when "111" => busctrl_addr <= '1'; - when others => null; - end case; - end process; - - p_oe : process(busctrl_re) - begin - -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns - O_DA_OE_L <= not (busctrl_re); - end process; - - -- - -- CLOCKED - -- - --p_waddr : process - --begin - ---- looks like registers are latches in real chip, but the address is caught at the end of the address state. - --wait until rising_edge(CLK); - - --if (RESET_L = '0') then - --addr <= (others => '0'); - --else - --if (busctrl_addr = '1') then - --addr <= I_DA; - --end if; - --end if; - --end process; - - --p_wdata : process - --begin - ---- looks like registers are latches in real chip, but the address is caught at the end of the address state. - --wait until rising_edge(CLK); - --env_reset <= '0'; - - --if (RESET_L = '0') then - --reg <= (others => (others => '0')); - --env_reset <= '1'; - --else - --env_reset <= '0'; - --if (busctrl_we = '1') then - --case addr(3 downto 0) is - --when x"0" => reg(0) <= I_DA; - --when x"1" => reg(1) <= I_DA; - --when x"2" => reg(2) <= I_DA; - --when x"3" => reg(3) <= I_DA; - --when x"4" => reg(4) <= I_DA; - --when x"5" => reg(5) <= I_DA; - --when x"6" => reg(6) <= I_DA; - --when x"7" => reg(7) <= I_DA; - --when x"8" => reg(8) <= I_DA; - --when x"9" => reg(9) <= I_DA; - --when x"A" => reg(10) <= I_DA; - --when x"B" => reg(11) <= I_DA; - --when x"C" => reg(12) <= I_DA; - --when x"D" => reg(13) <= I_DA; env_reset <= '1'; - --when x"E" => reg(14) <= I_DA; - --when x"F" => reg(15) <= I_DA; - --when others => null; - --end case; - --end if; - --end if; - --end process; - - -- - -- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock. - -- - p_waddr : process(reset_l, busctrl_addr) - begin - -- looks like registers are latches in real chip, but the address is caught at the end of the address state. - if (RESET_L = '0') then - addr <= (others => '0'); - elsif falling_edge(busctrl_addr) then -- yuk - addr <= I_DA; - end if; - end process; - - p_wdata : process(reset_l, busctrl_we, addr) - begin - if (RESET_L = '0') then - reg <= (others => (others => '0')); - elsif falling_edge(busctrl_we) then - case addr(3 downto 0) is - when x"0" => reg(0) <= I_DA; - when x"1" => reg(1) <= I_DA; - when x"2" => reg(2) <= I_DA; - when x"3" => reg(3) <= I_DA; - when x"4" => reg(4) <= I_DA; - when x"5" => reg(5) <= I_DA; - when x"6" => reg(6) <= I_DA; - when x"7" => reg(7) <= I_DA; - when x"8" => reg(8) <= I_DA; - when x"9" => reg(9) <= I_DA; - when x"A" => reg(10) <= I_DA; - when x"B" => reg(11) <= I_DA; - when x"C" => reg(12) <= I_DA; - when x"D" => reg(13) <= I_DA; - when x"E" => reg(14) <= I_DA; - when x"F" => reg(15) <= I_DA; - when others => null; - end case; - end if; - - env_reset <= '0'; - if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then - env_reset <= '1'; - end if; - end process; - - p_rdata : process(busctrl_re, addr, reg) - begin - O_DA <= (others => '0'); -- 'X' - if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator - case addr(3 downto 0) is - when x"0" => O_DA <= reg(0) ; - when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; - when x"2" => O_DA <= reg(2) ; - when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; - when x"4" => O_DA <= reg(4) ; - when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; - when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; - when x"7" => O_DA <= reg(7) ; - when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; - when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; - when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; - when x"B" => O_DA <= reg(11); - when x"C" => O_DA <= reg(12); - when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); - when x"E" => if (reg(7)(6) = '0') then -- input - O_DA <= ioa_inreg; - else - O_DA <= reg(14); -- read output reg - end if; - when x"F" => if (Reg(7)(7) = '0') then - O_DA <= iob_inreg; - else - O_DA <= reg(15); - end if; - when others => null; - end case; - end if; - end process; - -- - p_divider : process - begin - wait until rising_edge(CLK); - -- / 8 when SEL is high and /16 when SEL is low - if (ENA = '1') then - ena_div <= '0'; - ena_div_noise <= '0'; - if (cnt_div = "0000") then - cnt_div <= (not I_SEL_L) & "111"; - ena_div <= '1'; - - noise_div <= not noise_div; - if (noise_div = '1') then - ena_div_noise <= '1'; - end if; - else - cnt_div <= cnt_div - "1"; - end if; - end if; - end process; - - p_noise_gen : process - variable noise_gen_comp : std_logic_vector(4 downto 0); - variable poly17_zero : std_logic; - begin - wait until rising_edge(CLK); - - if (reg(6)(4 downto 0) = "00000") then - noise_gen_comp := "00000"; - else - noise_gen_comp := (reg(6)(4 downto 0) - "1"); - end if; - - poly17_zero := '0'; - if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; - - if (ENA = '1') then - - if (ena_div_noise = '1') then -- divider ena - - if (noise_gen_cnt >= noise_gen_comp) then - noise_gen_cnt <= "00000"; - poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); - else - noise_gen_cnt <= (noise_gen_cnt + "1"); - end if; - end if; - end if; - end process; - noise_gen_op <= poly17(0); - - p_tone_gens : process - variable tone_gen_freq : array_3x12; - variable tone_gen_comp : array_3x12; - begin - wait until rising_edge(CLK); - - -- looks like real chips count up - we need to get the Exact behaviour .. - tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); - tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); - tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); - -- period 0 = period 1 - for i in 1 to 3 loop - if (tone_gen_freq(i) = x"000") then - tone_gen_comp(i) := x"000"; - else - tone_gen_comp(i) := (tone_gen_freq(i) - "1"); - end if; - end loop; - - if (ENA = '1') then - for i in 1 to 3 loop - if (ena_div = '1') then -- divider ena - - if (tone_gen_cnt(i) >= tone_gen_comp(i)) then - tone_gen_cnt(i) <= x"000"; - tone_gen_op(i) <= not tone_gen_op(i); - else - tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); - end if; - end if; - end loop; - end if; - end process; - - p_envelope_freq : process - variable env_gen_freq : std_logic_vector(15 downto 0); - variable env_gen_comp : std_logic_vector(15 downto 0); - begin - wait until rising_edge(CLK); - env_gen_freq := reg(12) & reg(11); - -- envelope freqs 1 and 0 are the same. - if (env_gen_freq = x"0000") then - env_gen_comp := x"0000"; - else - env_gen_comp := (env_gen_freq - "1"); - end if; - - if (ENA = '1') then - env_ena <= '0'; - if (ena_div = '1') then -- divider ena - if (env_gen_cnt >= env_gen_comp) then - env_gen_cnt <= x"0000"; - env_ena <= '1'; - else - env_gen_cnt <= (env_gen_cnt + "1"); - end if; - end if; - end if; - end process; - - p_envelope_shape : process(env_reset, CLK) - variable is_bot : boolean; - variable is_bot_p1 : boolean; - variable is_top_m1 : boolean; - variable is_top : boolean; - begin - -- envelope shapes - -- C AtAlH - -- 0 0 x x \___ - -- - -- 0 1 x x /___ - -- - -- 1 0 0 0 \\\\ - -- - -- 1 0 0 1 \___ - -- - -- 1 0 1 0 \/\/ - -- ___ - -- 1 0 1 1 \ - -- - -- 1 1 0 0 //// - -- ___ - -- 1 1 0 1 / - -- - -- 1 1 1 0 /\/\ - -- - -- 1 1 1 1 /___ - if (env_reset = '1') then - -- load initial state - if (reg(13)(2) = '0') then -- attack - env_vol <= "11111"; - env_inc <= '0'; -- -1 - else - env_vol <= "00000"; - env_inc <= '1'; -- +1 - end if; - env_hold <= '0'; - - elsif rising_edge(CLK) then - is_bot := (env_vol = "00000"); - is_bot_p1 := (env_vol = "00001"); - is_top_m1 := (env_vol = "11110"); - is_top := (env_vol = "11111"); - - if (ENA = '1') then - if (env_ena = '1') then - if (env_hold = '0') then - if (env_inc = '1') then - env_vol <= (env_vol + "00001"); - else - env_vol <= (env_vol + "11111"); - end if; - end if; - - -- envelope shape control. - if (reg(13)(3) = '0') then - if (env_inc = '0') then -- down - if is_bot_p1 then env_hold <= '1'; end if; - else - if is_top then env_hold <= '1'; end if; - end if; - else - if (reg(13)(0) = '1') then -- hold = 1 - if (env_inc = '0') then -- down - if (reg(13)(1) = '1') then -- alt - if is_bot then env_hold <= '1'; end if; - else - if is_bot_p1 then env_hold <= '1'; end if; - end if; - else - if (reg(13)(1) = '1') then -- alt - if is_top then env_hold <= '1'; end if; - else - if is_top_m1 then env_hold <= '1'; end if; - end if; - end if; - - elsif (reg(13)(1) = '1') then -- alternate - if (env_inc = '0') then -- down - if is_bot_p1 then env_hold <= '1'; end if; - if is_bot then env_hold <= '0'; env_inc <= '1'; end if; - else - if is_top_m1 then env_hold <= '1'; end if; - if is_top then env_hold <= '0'; env_inc <= '0'; end if; - end if; - end if; - - end if; - end if; - end if; - end if; - end process; - - p_chan_mixer : process(cnt_div, reg, tone_gen_op) - begin - tone_ena_l <= '1'; tone_src <= '1'; - noise_ena_l <= '1'; chan_vol <= "00000"; - case cnt_div(1 downto 0) is - when "00" => - tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); - noise_ena_l <= reg(7)(3); - when "01" => - tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); - noise_ena_l <= reg(7)(4); - when "10" => - tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); - noise_ena_l <= reg(7)(5); - when "11" => null; -- tone gen outputs become valid on this clock - when others => null; - end case; - end process; - - p_op_mixer : process - variable chan_mixed : std_logic; - variable chan_amp : std_logic_vector(4 downto 0); - begin - wait until rising_edge(CLK); - if (ENA = '1') then - - chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); - - chan_amp := (others => '0'); - if (chan_mixed = '1') then - if (chan_vol(4) = '0') then - if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet - chan_amp := "00000"; - else - chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) - end if; - else - chan_amp := env_vol(4 downto 0); - end if; - end if; - - dac_amp <= x"00"; - case chan_amp is - when "11111" => dac_amp <= x"FF"; - when "11110" => dac_amp <= x"D9"; - when "11101" => dac_amp <= x"BA"; - when "11100" => dac_amp <= x"9F"; - when "11011" => dac_amp <= x"88"; - when "11010" => dac_amp <= x"74"; - when "11001" => dac_amp <= x"63"; - when "11000" => dac_amp <= x"54"; - when "10111" => dac_amp <= x"48"; - when "10110" => dac_amp <= x"3D"; - when "10101" => dac_amp <= x"34"; - when "10100" => dac_amp <= x"2C"; - when "10011" => dac_amp <= x"25"; - when "10010" => dac_amp <= x"1F"; - when "10001" => dac_amp <= x"1A"; - when "10000" => dac_amp <= x"16"; - when "01111" => dac_amp <= x"13"; - when "01110" => dac_amp <= x"10"; - when "01101" => dac_amp <= x"0D"; - when "01100" => dac_amp <= x"0B"; - when "01011" => dac_amp <= x"09"; - when "01010" => dac_amp <= x"08"; - when "01001" => dac_amp <= x"07"; - when "01000" => dac_amp <= x"06"; - when "00111" => dac_amp <= x"05"; - when "00110" => dac_amp <= x"04"; - when "00101" => dac_amp <= x"03"; - when "00100" => dac_amp <= x"03"; - when "00011" => dac_amp <= x"02"; - when "00010" => dac_amp <= x"02"; - when "00001" => dac_amp <= x"01"; - when "00000" => dac_amp <= x"00"; - when others => null; - end case; - - if (cnt_div(1 downto 0) = "10") then - audio_mix <= (others => '0'); - audio_final <= audio_mix; - else - audio_mix <= audio_mix + ("00" & dac_amp); - end if; - - if (RESET_L = '0') then - O_AUDIO(7 downto 0) <= "00000000"; - else - if (audio_final(9) = '0') then - O_AUDIO(7 downto 0) <= audio_final(8 downto 1); - else -- clip - O_AUDIO(7 downto 0) <= x"FF"; - end if; - end if; - end if; - end process; - - p_io_ports : process(reg) - begin - O_IOA <= reg(14); - - O_IOA_OE_L <= not reg(7)(6); - O_IOB <= reg(15); - O_IOB_OE_L <= not reg(7)(7); - end process; - - p_io_ports_inreg : process - begin - wait until rising_edge(CLK); - ioa_inreg <= I_IOA; - iob_inreg <= I_IOB; - end process; -end architecture RTL; diff --git a/Computer_MiST/HT1080z_MiST/rtl/build_id.tcl b/Computer_MiST/HT1080z_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Computer_MiST/HT1080z_MiST/rtl/build_id.v b/Computer_MiST/HT1080z_MiST/rtl/build_id.v deleted file mode 100644 index bd10db98..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/build_id.v +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "181110" -`define BUILD_TIME "002457" diff --git a/Computer_MiST/HT1080z_MiST/rtl/dac.vhd b/Computer_MiST/HT1080z_MiST/rtl/dac.vhd deleted file mode 100644 index c133f074..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2006/05/10 20:57:06 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 7 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Computer_MiST/HT1080z_MiST/rtl/data_io.v b/Computer_MiST/HT1080z_MiST/rtl/data_io.v deleted file mode 100644 index 5c5698b6..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/data_io.v +++ /dev/null @@ -1,121 +0,0 @@ -// -// data_io.v -// -// io controller writable ram for the MiST board -// http://code.google.com/p/mist-board/ -// -// ZX Spectrum adapted version -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module data_io ( - // io controller spi interface - input sck, - input ss, - input sdi, - - output downloading, // signal indicating an active download - output reg [4:0] index, // menu index used to upload the file - - // external ram interface - input clk, - output reg wr, - output reg [24:0] addr, - output reg [7:0] data -); - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg [6:0] sbuf; -reg [7:0] cmd; -reg [4:0] cnt; -reg rclk; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -assign downloading = downloading_reg; -reg downloading_reg = 1'b0; - -// data_io has its own SPI interface to the io controller -always@(posedge sck, posedge ss) begin - if(ss == 1'b1) - cnt <= 5'd0; - else begin - rclk <= 1'b0; - - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) - sbuf <= { sbuf[5:0], sdi}; - - // increase target address after write - if(rclk) - addr <= addr + 1; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 4'd1; - else cnt <= 4'd8; - - // finished command byte - if(cnt == 7) - cmd <= {sbuf, sdi}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(sdi) begin - //addr <= 25'd0; - // pppppppp - // xxxx....xxxx.... - if (index==5'b00000) addr <= 25'b0000000000000000000000000; - else addr <= 25'b0000000010000000000000000; - //addr <= 25'b0000000001100000000000000; - downloading_reg <= 1'b1; - end else - downloading_reg <= 1'b0; - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - data <= {sbuf, sdi}; - rclk <= 1'b1; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) - index <= {sbuf[3:0], sdi}; - end -end - -reg rclkD, rclkD2; -always@(posedge clk) begin - // bring rclk from spi clock domain into c64 clock domain - rclkD <= rclk; - rclkD2 <= rclkD; - wr <= 1'b0; - - if(rclkD && !rclkD2) - wr <= 1'b1; -end - -endmodule diff --git a/Computer_MiST/HT1080z_MiST/rtl/ht1080z.vhd b/Computer_MiST/HT1080z_MiST/rtl/ht1080z.vhd deleted file mode 100644 index 2e574c87..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/ht1080z.vhd +++ /dev/null @@ -1,611 +0,0 @@ --- --- HT 1080Z (TSR-80 clone) top level --- --- --- Copyright (c) 2016-2017 Jozsef Laszlo (rbendr@gmail.com) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity ht1080z is - Port ( - CLOCK_27 : in STD_LOGIC; - SDRAM_nCS : out std_logic; -- Chip Select - SDRAM_DQ : inout std_logic_vector(15 downto 0); -- SDRAM Data bus 16 Bits - SDRAM_A : out std_logic_vector(12 downto 0); -- SDRAM Address bus 13 Bits - SDRAM_DQMH : out std_logic; -- SDRAM High Data Mask - SDRAM_DQML : out std_logic; -- SDRAM Low-byte Data Mask - SDRAM_nWE : out std_logic; -- SDRAM Write Enable - SDRAM_nCAS : out std_logic; -- SDRAM Column Address Strobe - SDRAM_nRAS : out std_logic; -- SDRAM Row Address Strobe - SDRAM_BA : out std_logic_vector(1 downto 0); -- SDRAM Bank Address - SDRAM_CLK : out std_logic; -- SDRAM Clock - SDRAM_CKE : out std_logic; -- SDRAM Clock Enable - SPI_DO : out std_logic; - SPI_DI : in std_logic; - SPI_SCK : in std_logic; - SPI_SS2 : in std_logic; - SPI_SS3 : in std_logic; - SPI_SS4 : in std_logic; - CONF_DATA0 : in std_logic; - VGA_R : out STD_LOGIC_VECTOR (5 downto 0); - VGA_G : out STD_LOGIC_VECTOR (5 downto 0); - VGA_B : out STD_LOGIC_VECTOR (5 downto 0); - VGA_HS : out STD_LOGIC; - VGA_VS : out STD_LOGIC; - LED : out STD_LOGIC; - AUDIO_L : out STD_LOGIC; - AUDIO_R : out STD_LOGIC - ); -end ht1080z; - -architecture Behavioral of ht1080z is - -component data_io - port ( sck, ss, sdi : in std_logic; - - -- download info - downloading : out std_logic; - --size : out std_logic_vector(24 downto 0); - index : out std_logic_vector(4 downto 0); - - -- external ram interface - clk : in std_logic; - wr : out std_logic; - addr : out std_logic_vector(24 downto 0); - data : out std_logic_vector(7 downto 0) -); -end component data_io; - -component sdram is - port( sd_data : inout std_logic_vector(15 downto 0); - sd_addr : out std_logic_vector(12 downto 0); - sd_dqm : out std_logic_vector(1 downto 0); - sd_ba : out std_logic_vector(1 downto 0); - sd_cs : out std_logic; - sd_we : out std_logic; - sd_ras : out std_logic; - sd_cas : out std_logic; - init : in std_logic; - clk : in std_logic; - clkref : in std_logic; - din : in std_logic_vector(7 downto 0); - dout : out std_logic_vector(7 downto 0); - addr : in std_logic_vector(24 downto 0); - oe : in std_logic; - we : in std_logic - ); -end component; - -component osd - generic ( OSD_COLOR : integer ); - port ( pclk : in std_logic; - sck, sdi, ss : in std_logic; - - -- VGA signals coming from core - red_in : in std_logic_vector(5 downto 0); - green_in : in std_logic_vector(5 downto 0); - blue_in : in std_logic_vector(5 downto 0); - hs_in : in std_logic; - vs_in : in std_logic; - - -- VGA signals going to video connector - red_out : out std_logic_vector(5 downto 0); - green_out : out std_logic_vector(5 downto 0); - blue_out : out std_logic_vector(5 downto 0); - hs_out : out std_logic; - vs_out : out std_logic - ); -end component osd; - -component user_io - generic ( STRLEN : integer := 0 ); - port ( - -- ps2 interface - SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic; - SPI_MISO : out std_logic; - conf_str : in std_logic_vector(8*STRLEN-1 downto 0); - joystick_0 : out std_logic_vector(7 downto 0); - joystick_1 : out std_logic_vector(7 downto 0); - status: out std_logic_vector(7 downto 0); - ps2_clk : in std_LOGIC; - ps2_kbd_clk : out std_logic; - ps2_kbd_data : out std_logic; - ps2_mouse_clk : out std_logic; - ps2_mouse_data : out std_logic; - scandoubler_disable : out std_logic - ); -end component user_io; - -constant CONF_STR : string := "HT1080Z;CAS;O1,Scanlines,Off,On;T2,Reset"; - --"SMS;SMS;O1,Video,NTSC,PAL;O2,Scanlines,Off,On;O3,Joysticks,Normal,Swapped;T4,Pause;T5,Reset"; - - function to_slv(s: string) return std_logic_vector is - constant ss: string(1 to s'length) := s; - variable rval: std_logic_vector(1 to 8 * s'length); - variable p: integer; - variable c: integer; - - begin - for i in ss'range loop - p := 8 * i; - c := character'pos(ss(i)); - rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); - end loop; - return rval; - - end function; - - -signal sdram_dqm : std_logic_vector(1 downto 0); -signal ram_addr : std_logic_vector(24 downto 0); -signal ram_din : STD_LOGIC_VECTOR(7 downto 0); -signal ram_dout : STD_LOGIC_VECTOR(7 downto 0); -signal ram_we: std_logic; -signal ram_oe: std_logic; - -signal dn_go : std_logic; -signal dn_wr : std_logic; -signal dn_addr : std_logic_vector(24 downto 0); -signal dn_data : std_logic_vector(7 downto 0); -signal dn_idx : std_logic_vector(4 downto 0); - -signal dn_wr_r : std_logic; -signal dn_addr_r : std_logic_vector(24 downto 0); -signal dn_data_r : std_logic_vector(7 downto 0); - -signal res_cnt : std_logic_vector(5 downto 0) := "111111"; -signal autores : std_logic; - - -signal pvsel : std_logic; -signal ps2clkout : std_logic; - -signal PS2CLK : std_logic; -signal PS2DAT : std_logic; - -signal MPS2CLK : std_logic; -signal MPS2DAT : std_logic; - -signal joy0 : std_logic_vector(7 downto 0); -signal joy1 : std_logic_vector(7 downto 0); - -signal status: std_logic_vector(7 downto 0); - -signal clk56m : std_logic; -signal clk42m,clk21m,clk7m : std_logic; -signal pllLocked : std_logic; - -signal cpua : std_logic_vector(15 downto 0); -signal cpudo : std_logic_vector(7 downto 0); -signal cpudi : std_logic_vector(7 downto 0); -signal cpuwr,cpurd,cpumreq,cpuiorq,cpunmi,cpuint,cpum1,cpuclk,cpuClkEn : std_logic; - -signal rgbi : std_logic_vector(3 downto 0); -signal hs,vs : std_logic; -signal romdo,vramdo,ramdo,ramHdo,kbdout : std_logic_vector(7 downto 0); -signal vramcs : std_logic; - -signal page,vcut,swres : std_logic; - -signal romrd,ramrd,ramwr,vramsel,kbdsel : std_logic; -signal ior,iow,memr,memw : std_logic; -signal vdata : std_logic_vector(7 downto 0); - -signal clk_download : std_logic; - --- 0 1 2 3 4 --- 28 14 7 3.5 1.75 -signal clk56div : std_logic_vector(11 downto 0); - -signal dacout : std_logic; -signal sndBC1,sndBDIR,sndCLK : std_logic; -signal oaudio,snddo : std_logic_vector(7 downto 0); - -signal ht_rgb : std_logic_vector(17 downto 0); -signal out_rgb : std_logic_vector(17 downto 0); -signal p_hs,p_vs,vgahs,vgavs : std_logic; -signal pclk : std_logic; - -signal io_ram_addr : std_logic_vector(23 downto 0); -signal iorrd,iorrd_r : std_logic; - -signal audiomix : std_logic_vector(8 downto 0); -signal tapebits : std_logic_vector(2 downto 0); -signal speaker : std_logic_vector(7 downto 0); -signal vga : std_logic := '0'; -signal scanlines : std_logic; -signal oddline : std_logic; - -signal inkpulse, paperpulse, borderpulse : std_logic; - -begin - - led <= not scanlines; --not dn_go;--swres; - - -- generate system clocks - clkmgr : entity work.pll - port map ( - inclk0 => CLOCK_27, - c0 => clk56M, - c1 => SDRAM_CLK, - c2 => clk42m, - locked => pllLocked - ); - - process(clk56m) - begin - if rising_edge(clk56m) then - clk56div <= clk56div - 1; - end if; - end process; - clk7m <= clk56div(2); - ps2clkout <= clk56div(11); - - ior <= cpurd or cpuiorq or (not cpum1); - iow <= cpuwr or cpuiorq; - memr <= cpurd or cpumreq; - memw <= cpuwr or cpumreq; - - romrd <= '1' when memr='0' and cpua autores, --swres, - CLK_n => cpuClk, -- 1.75 MHz - CLKEN => cpuClkEn, - WAIT_n => '1', - INT_n => '1', - NMI_n => '1', - BUSRQ_n => '1', - M1_n => cpum1, - MREQ_n => cpumreq, - IORQ_n => cpuiorq, - RD_n => cpurd, - WR_n => cpuwr, - RFSH_n => open, - HALT_n => open, - BUSAK_n => open, - A => cpua, - DI => cpudi, - DO => cpudo - ); - - cpudi <= --romdo when romrd='1' else - --ramdo when ramrd='1' else - --ram_dout when romrd='1' else - --ram_dout when ramrd='1' else - vramdo when vramsel='1' else - kbdout when kbdsel='1' else - x"30" when ior='0' and cpua(7 downto 0)=x"fd" else -- printer io read - --ram_dout when iorrd='1' else - --x"ff"; - ram_dout; - - - vga <= not pvsel; - vdata <= cpudo when cpudo>x"1f" else cpudo or x"40"; - -- video ram at 0x3C00 - video : entity work.videoctrl - port map ( - reset => autores, --swres and pllLocked, - clk42 => clk42m, - -- clk7 => clk7m, - a => cpua(13 downto 0), - din => vdata,--cpudo, - dout => vramdo, - mreq => cpumreq, - iorq => cpuiorq, - wr => cpuwr, - cs => not vramsel, - vcut => vcut, - vvga => vga, - page => page, - rgbi => rgbi, - pclk => pclk, - inkp => inkpulse, - paperp => paperpulse, - borderp => borderpulse, - oddline => oddline, - hsync => hs, - vsync => vs - ); - - VGA_HS <= hs when vga='1' else hs xor (not vs); - VGA_VS <= vs when vga='1' else '1'; - - kbd : entity work.ps2kbd - port map ( - RESET => not pllLocked, - KBCLK => ps2clk, - KBDAT => ps2dat, - SWRES => swres, - CLK => clk7m, - A => cpua(7 downto 0), - DOUT => kbdout, - PAGE => page, - VCUT => vcut, - INKP => inkpulse, - PAPERP => paperpulse, - BORDERP => borderpulse - ); - - -- PSG - -- out 1e = data port - -- out 1f = register index - - soundchip : entity work.YM2149 - port map ( - -- data bus - I_DA => cpudo, - O_DA => open, - O_DA_OE_L => open, - -- control - I_A9_L => '0', - I_A8 => '1', - I_BDIR => sndBDIR, - I_BC2 => '1', - I_BC1 => sndBC1, - I_SEL_L => '1', - - O_AUDIO => oaudio, - -- port a - I_IOA => "ZZZZZZZZ", - O_IOA => open, - O_IOA_OE_L => open, - -- port b - I_IOB => "ZZZZZZZZ", - O_IOB => open, - O_IOB_OE_L => open, - -- - ENA => '1', - RESET_L => autores,--swres and pllLocked, - CLK => cpuClk - ); - sndBDIR <= '1' when cpua(7 downto 1)="0001111" and iow='0' else '0'; - sndBC1 <= cpua(0); - - -- Delta-Sigma DAC for audio (one channel, mono in this implementation) - audiodac : entity work.dac - port map ( - clk_i => clk7m, - res_n_i => swres and pllLocked, - dac_i => audiomix(8 downto 1), --oaudio, - dac_o => dacout - ); - - with tapebits select speaker <= - "00100000" when "001", - "00010000" when "000"|"011", - "00000000" when others; - - audiomix <= ('0' & oaudio) + ('0' & speaker); - - AUDIO_L <= dacout; - AUDIO_R <= dacout; - - -- fix palette for now - --with rgbi select rgb <= - with rgbi select ht_rgb <= - "000000000000000000" when "0000", - "000000000000100000" when "0001", - "000000100000000000" when "0010", - "000000100000100000" when "0011", - "100000000000000000" when "0100", - "100000000000100000" when "0101", - "110000011000000000" when "0110", - "100000100000100000" when "0111", - "110000110000110000" when "1000", - "000000000000111100" when "1001", - "000000111100000000" when "1010", - "000000111100111100" when "1011", - "111110000000000000" when "1100", - "111100000000111100" when "1101", - "111110111110000000" when "1110", - "111110111110111110" when others; - - scanlines <= status(1) and vga and oddline; - - userio: user_io - generic map (STRLEN => CONF_STR'length) - port map ( - - conf_str => to_slv(CONF_STR), - - SPI_CLK => SPI_SCK , - SPI_SS_IO => CONF_DATA0 , - SPI_MISO => SPI_DO , - SPI_MOSI => SPI_DI , - - status => status , - - -- ps2 interface - ps2_clk => ps2clkout, - ps2_kbd_clk => ps2CLK, - ps2_kbd_data => ps2DAT, - ps2_mouse_clk => mps2CLK, - ps2_mouse_data => mps2DAT, - - joystick_0 => joy0, - joystick_1 => joy1, - - scandoubler_disable => pvsel - ); - -osd_d : osd - generic map (OSD_COLOR => 6) - port map ( - pclk => pclk, - sck => SPI_SCK, - ss => SPI_SS3, - sdi => SPI_DI, - - red_in => ht_rgb(5 downto 0), - green_in => ht_rgb(11 downto 6), - blue_in => ht_rgb(17 downto 12), - hs_in => hs, - vs_in => vs, - - red_out => out_RGB(17 downto 12), - green_out => out_RGB(11 downto 6), - blue_out => out_RGB(5 downto 0), - hs_out => open, --HSYNC, - vs_out => open --VSYNC -); - - VGA_R <= out_RGB(17 downto 12) when scanlines='0' else "0" & out_RGB(17 downto 13); - VGA_G <= out_RGB(11 downto 6) when scanlines='0' else "0" & out_RGB(11 downto 7); - VGA_B <= out_RGB( 5 downto 0) when scanlines='0' else "0" & out_RGB( 5 downto 1); - - sdram_inst : sdram - port map( sd_data => SDRAM_DQ, - sd_addr => SDRAM_A, - sd_dqm => sdram_dqm, - sd_cs => SDRAM_nCS, - sd_ba => SDRAM_BA, - sd_we => SDRAM_nWE, - sd_ras => SDRAM_nRAS, - sd_cas => SDRAM_nCAS, - clk => clk56m, - clkref => clk_download, --cpuClk, - init => not pllLocked, - din => ram_din, - addr => ram_addr, - we => ram_we, - oe => ram_oe, - dout => ram_dout - ); - --ram_addr <= "000000000" & cpua when dn_go='0' else dn_addr_r; - ram_din <= cpudo when dn_go='0' else dn_data_r; - ram_we <= ((not memw) and (cpua(15) or cpua(14))) when dn_go='0' else dn_wr_r; - --ram_oe <= not memr when dn_go='0' else '0'; - - ram_addr <= "0" & io_ram_addr when iorrd='1' else "000000000" & cpua when dn_go='0' else dn_addr_r; - ram_oe <= '1' when iorrd='1' else not memr when dn_go='0' else '0'; - - -- sdram interface - SDRAM_CKE <= '1'; - SDRAM_DQMH <= sdram_dqm(1); - SDRAM_DQML <= sdram_dqm(0); - - - dataio : data_io - port map ( - sck => SPI_SCK, - ss => SPI_SS2, - sdi => SPI_DI, - - downloading => dn_go, - --size => ioctl_size, - index => dn_idx, - - -- ram interface - clk => clk_download, -- ??? - wr => dn_wr, - addr => dn_addr, - data => dn_data - ); - - process(clk_download) - begin - if rising_edge(clk_download) then - if dn_wr='1' then - dn_wr_r <= '1'; - dn_data_r <= dn_data; - dn_addr_r <= dn_addr; - else - dn_wr_r <= '0'; - end if; - end if; - end process; - - process (cpuClk) - begin - if rising_edge(cpuClk) then - if pllLocked='0' or status(0)='1' or status(2)='1' then - res_cnt <= "000000"; - else - if (res_cnt/="111111") then - res_cnt <= res_cnt+1; - end if; - end if; - end if; - end process; - - cpuClkEn <= not dn_go; - autores <= '1' when res_cnt="111111" else '0'; - - - process (cpuClk,dn_go,autores) - begin - if dn_go='1' or autores='0' then - io_ram_addr <= x"010000"; -- above 64k - iorrd_r<='0'; - else - if rising_edge(cpuClk) then - if iow='0' and cpua(7 downto 0)=x"ff" then - tapebits <= cpudo(2 downto 0); - end if; - if iow='0' and cpua(7 downto 2)="000001" then -- out 4 5 6 - case cpua(1 downto 0) is - when "00"=> io_ram_addr(7 downto 0) <= cpudo; - when "01"=> io_ram_addr(15 downto 8) <= cpudo; - when "10"=> io_ram_addr(23 downto 16) <= cpudo; - when others => null; - end case; - end if; - iorrd_r<=iorrd; - if iorrd='0' and iorrd_r='1' then - io_ram_addr <= io_ram_addr + 1; - end if; - end if; - end if; - end process; - - -end Behavioral; diff --git a/Computer_MiST/HT1080z_MiST/rtl/osd.v b/Computer_MiST/HT1080z_MiST/rtl/osd.v deleted file mode 100644 index a654b401..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/osd.v +++ /dev/null @@ -1,182 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input pclk, - - // SPI interface - input sck, - input ss, - input sdi, - - // VGA signals coming from core - input [5:0] red_in, - input [5:0] green_in, - input [5:0] blue_in, - input hs_in, - input vs_in, - - // VGA signals going to video connector - output [5:0] red_out, - output [5:0] green_out, - output [5:0] blue_out, - output hs_out, - output vs_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg [7:0] sbuf; -reg [7:0] cmd; -reg [4:0] cnt; -reg [10:0] bcnt; -reg osd_enable; - -reg [7:0] osd_buffer [2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge sck, posedge ss) begin - if(ss == 1'b1) begin - cnt <= 5'd0; - bcnt <= 11'd0; - end else begin - sbuf <= { sbuf[6:0], sdi}; - - // 0:7 is command, rest payload - if(cnt < 15) - cnt <= cnt + 4'd1; - else - cnt <= 4'd8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], sdi}; - - // lower three command bits are line address - bcnt <= { sbuf[1:0], sdi, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) - osd_enable <= sdi; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], sdi}; - bcnt <= bcnt + 11'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg hsD, hsD2; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high; -wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] }; - -always @(posedge pclk) begin - // bring hsync into local clock domain - hsD <= hs_in; - hsD2 <= hsD; - - // falling edge of hs_in - if(!hsD && hsD2) begin - h_cnt <= 10'd0; - hs_high <= h_cnt; - end - - // rising edge of hs_in - else if(hsD && !hsD2) begin - h_cnt <= 10'd0; - hs_low <= h_cnt; - end - - else - h_cnt <= h_cnt + 10'd1; -end - -// vertical counter -reg [9:0] v_cnt; -reg vsD, vsD2; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high; -wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] }; - -always @(posedge hs_in) begin - // bring vsync into local clock domain - vsD <= vs_in; - vsD2 <= vsD; - - // falling edge of vs_in - if(!vsD && vsD2) begin - v_cnt <= 10'd0; - vs_high <= v_cnt; - end - - // rising edge of vs_in - else if(vsD && !vsD2) begin - v_cnt <= 10'd0; - vs_low <= v_cnt; - end - - else - v_cnt <= v_cnt + 10'd1; -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1); -wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1; -wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1); -wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1; - -reg h_osd_active, v_osd_active; -always @(posedge pclk) begin - if(hs_in != hs_pol) begin - if(h_cnt == h_osd_start) h_osd_active <= 1'b1; - if(h_cnt == h_osd_end) h_osd_active <= 1'b0; - end - if(vs_in != vs_pol) begin - if(v_cnt == v_osd_start) v_osd_active <= 1'b1; - if(v_cnt == v_osd_end) v_osd_active <= 1'b0; - end -end - -wire osd_de = osd_enable && h_osd_active && v_osd_active; - -wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register -wire [6:0] osd_vcnt = v_cnt - v_osd_start; - -wire osd_pixel = osd_byte[osd_vcnt[3:1]]; - -reg [7:0] osd_byte; -always @(posedge pclk) - osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}]; - -wire [2:0] osd_color = OSD_COLOR; -assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] }; -assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]}; -assign blue_out = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] }; - -assign hs_out = hs_in; -assign vs_out = vs_in; - -endmodule \ No newline at end of file diff --git a/Computer_MiST/HT1080z_MiST/rtl/pll.vhd b/Computer_MiST/HT1080z_MiST/rtl/pll.vhd deleted file mode 100644 index 81efccba..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/pll.vhd +++ /dev/null @@ -1,424 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - locked <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 27, - clk0_duty_cycle => 50, - clk0_multiply_by => 56, - clk0_phase_shift => "0", - clk1_divide_by => 27, - clk1_duty_cycle => 50, - clk1_multiply_by => 56, - clk1_phase_shift => "-2000", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 14, - clk2_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "OFF", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire6, - clk => sub_wire0, - locked => sub_wire2 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "56.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "56.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "42.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "56.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "56.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "42.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "56" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2000" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "14" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Computer_MiST/HT1080z_MiST/rtl/ps2kbd.vhd b/Computer_MiST/HT1080z_MiST/rtl/ps2kbd.vhd deleted file mode 100644 index 2a1553fb..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/ps2kbd.vhd +++ /dev/null @@ -1,312 +0,0 @@ --- --- HT 1080Z (TSR-80 clone) ps2 keyboard --- --- --- Copyright (c) 2016-2017 Jozsef Laszlo (rbendr@gmail.com) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- - - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity ps2kbd is - Port ( - RESET : in STD_LOGIC; - KBCLK : in STD_LOGIC; - KBDAT : in STD_LOGIC; - SWRES : out STD_LOGIC; - CLK : in STD_LOGIC; - A : in STD_LOGIC_VECTOR(7 downto 0); - DOUT : out STD_LOGIC_VECTOR(7 downto 0); - PAGE : out STD_LOGIC; - VCUT : out STD_LOGIC; - INKP : out STD_LOGIC; - PAPERP : out STD_LOGIC; - BORDERP : out STD_LOGIC - ); - -end ps2kbd; - -architecture Behavioral of ps2kbd is - -type keys is array(0 to 7) of std_logic_vector(7 downto 0); - -signal keypress : std_logic:='0'; -signal extkey : std_logic:='0'; - -signal hasRead : std_logic; - -signal keybits : keys; -signal keysout : keys; -signal lastkc : std_logic; - -signal kbdsign : std_logic; -signal kbddata : std_logic_vector(7 downto 0); -signal swreset : std_logic := '1'; - -signal pageReg : std_logic := '0'; -signal vcutReg : std_logic := '0'; - -signal inkpulse, paperpulse, borderpulse : std_logic; - - -begin - - ps2rd : entity work.ps2reader - port map ( - mclk => CLK, - PS2C => KBCLK, - PS2D => KBDAT, - rst => RESET, - Ps2Dout => kbddata, - fRd => kbdsign - ); - - process(RESET,kbdsign,kbddata) - variable kk : std_logic_vector(6 downto 0); - variable ix : integer; - begin - if RESET='1' then - keypress <= '0'; - keybits(0) <= "00000000"; - keybits(1) <= "00000000"; - keybits(2) <= "00000000"; - keybits(3) <= "00000000"; - keybits(4) <= "00000000"; - keybits(5) <= "00000000"; - keybits(6) <= "00000000"; - keybits(7) <= "00000000"; - - swreset <= '1'; - pageReg <= '0'; - vcutReg <= '0'; - else - if rising_edge(kbdsign) then - if kbddata=x"F0" then - keypress <= '0'; -- released - --if shifrpress='1' then - -- keybits(7)(0)<='0'; - -- shifrpress<='0'; - --end if; - elsif kbddata=x"E0" then - extkey<='1'; - else - keypress <= '1'; -- pressed - - -- this is for ps2 read. we convert 0x83 to 0x02 (keyboard F2) - kk:= kbddata(6 downto 0); - if kbddata=x"83" then - kk:="0000010"; -- keyboard F7 code 0x83 converted to 0x02 - end if; - - - - case '0' & kk is - - when x"03" => inkpulse <= keypress; -- F1 - when x"0b" => paperpulse <= keypress; -- F2 - when x"02" => borderpulse <= keypress; -- F3 - - when x"78"=> swreset <= not keypress; -- F11 - - when x"01"=> --F9 - if keypress='1' then - vcutReg <= not vcutReg; - end if; - - when x"09"=> --F10 - if keypress='1' then - pageReg <= not pageReg; - end if; - - -- \| - when x"5d"=> keybits(0)(0)<=keypress; - -- A - when x"1c"=> keybits(0)(1)<=keypress; - -- B - when x"32"=> keybits(0)(2)<=keypress; - -- C - when x"21"=> keybits(0)(3)<=keypress; - -- D - when x"23"=> keybits(0)(4)<=keypress; - -- E - when x"24"=> keybits(0)(5)<=keypress; - -- F - when x"2b"=> keybits(0)(6)<=keypress; - -- G - when x"34"=> keybits(0)(7)<=keypress; - - -- H - when x"33"=> keybits(1)(0)<=keypress; - -- I - when x"43"=> keybits(1)(1)<=keypress; - -- J - when x"3B"=> keybits(1)(2)<=keypress; - -- K - when x"42"=> keybits(1)(3)<=keypress; - -- L - when x"4B"=> keybits(1)(4)<=keypress; - -- M - when x"3A"=> keybits(1)(5)<=keypress; - -- N - when x"31"=> keybits(1)(6)<=keypress; - -- O - when x"44"=> keybits(1)(7)<=keypress; - - -- P - when x"4D"=> keybits(2)(0)<=keypress; - -- Q - when x"15"=> keybits(2)(1)<=keypress; - -- R - when x"2D"=> keybits(2)(2)<=keypress; - -- S - when x"1B"=> keybits(2)(3)<=keypress; - -- T - when x"2C"=> keybits(2)(4)<=keypress; - -- U - when x"3C"=> keybits(2)(5)<=keypress; - -- V - when x"2A"=> keybits(2)(6)<=keypress; - -- W - when x"1D"=> keybits(2)(7)<=keypress; - - -- X - when x"22"=> keybits(3)(0)<=keypress; - -- Y - when x"35"=> keybits(3)(1)<=keypress; - -- Z - when x"1A"=> keybits(3)(2)<=keypress; - -- F2 - when x"06"=> keybits(3)(4)<=keypress; - -- F3 - when x"04"=> keybits(3)(5)<=keypress; - -- F4 - when x"0C"=> keybits(3)(6)<=keypress; - -- F1 - when x"05"=> keybits(3)(7)<=keypress; - - -- 0 - when x"45"=> keybits(4)(0)<=keypress; - -- 1 - when x"16"=> keybits(4)(1)<=keypress; - -- 2 - when x"1E"=> keybits(4)(2)<=keypress; - -- 3 - when x"26"=> keybits(4)(3)<=keypress; - -- 4 - when x"25"=> keybits(4)(4)<=keypress; - -- 5 - when x"2E"=> keybits(4)(5)<=keypress; - -- 6 - when x"36"=> keybits(4)(6)<=keypress; - -- 7 - when x"3D"=> keybits(4)(7)<=keypress; - - -- 8 - when x"3E"=> keybits(5)(0)<=keypress; - -- 9 - when x"46"=> keybits(5)(1)<=keypress; - -- *: - when x"0E"|x"4e" => keybits(5)(2)<=keypress; - -- +; - when x"4C"=> keybits(5)(3)<=keypress; - -- <, - when x"41"=> keybits(5)(4)<=keypress; - -- =- - when x"55"|x"7b"=> keybits(5)(5)<=keypress; - -- >. - when x"49"=> keybits(5)(6)<=keypress; - -- ?/ - when x"4A"=> keybits(5)(7)<=keypress; - - -- NL - when x"5A"=> keybits(6)(0)<=keypress; - -- CLR - when x"6C"=> keybits(6)(1)<=keypress; - -- BRK - when x"76"=> keybits(6)(2)<=keypress; - -- up-arrow - when x"75"=> keybits(6)(3)<=keypress; - -- dn-arrow - when x"72"=> keybits(6)(4)<=keypress; - -- lf-arrow and backspace - when x"6B"|x"66"=> keybits(6)(5)<=keypress; - -- rg-arrow - when x"74"=> keybits(6)(6)<=keypress; - -- SPA - when x"29"=> keybits(6)(7)<=keypress; - - -- L-SHIFT R-SHIFT - when x"12"|x"59"=> keybits(7)(0)<=keypress; - - -- numpad * - when x"7c"=> keybits(5)(2)<=keypress; - keybits(7)(0)<=keypress; - -- numpad + - when x"79"=> keybits(5)(3)<=keypress; - keybits(7)(0)<=keypress; - - when others => - null; - end case; - extkey<='0'; - end if; - end if; - end if; - end process; - - SWRES <= swreset; - VCUT <= vcutReg; - PAGE <= pageReg; - - keysout(0) <= keybits(0) when A(0)='1' else x"00"; - keysout(1) <= keybits(1) when A(1)='1' else x"00"; - keysout(2) <= keybits(2) when A(2)='1' else x"00"; - keysout(3) <= keybits(3) when A(3)='1' else x"00"; - keysout(4) <= keybits(4) when A(4)='1' else x"00"; - keysout(5) <= keybits(5) when A(5)='1' else x"00"; - keysout(6) <= keybits(6) when A(6)='1' else x"00"; - keysout(7) <= keybits(7) when A(7)='1' else x"00"; - DOUT <= keysout(0) or keysout(1) or keysout(2) or keysout(3) or keysout(4) or keysout(5) or keysout(6) or keysout(7); - - INKP <= inkpulse; - PAPERP <= paperpulse; - BORDERP <= borderpulse; - -end Behavioral; diff --git a/Computer_MiST/HT1080z_MiST/rtl/ps2reader.vhd b/Computer_MiST/HT1080z_MiST/rtl/ps2reader.vhd deleted file mode 100644 index e61c57a6..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/ps2reader.vhd +++ /dev/null @@ -1,198 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: Digilent Inc. --- Engineer: Claudia Goga --- --- Create Date: 22:33:35 11/25/06 --- Module Name: PS2_Reader - Behavioral --- Target Devices: CoolRunner2 CPLD --- Tool versions: Xilinx ISE v7.1i --- Description: --- This module reads scan codes from the PS2 Port. Every time a --- new scan code is entirely received it enables the fRd signal for one --- main clock period. --- --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - - -entity ps2reader is - Port ( mclk : in std_logic; -- System Clock - PS2C : in std_logic; -- PS2 Clock - PS2D : in std_logic; -- PS2 data - rst: in std_logic; -- Reset BTN0 - Ps2Dout : out std_logic_vector(7 downto 0); -- out data - fRd : out std_logic); -- data valid flag -end ps2reader; - -architecture Behavioral of ps2reader is - ------------------------------------------------------------------------- --- SIGNAL and CONSTANT DECLARATIONS ------------------------------------------------------------------------- ---The constants below define state codes for the PS2 Keyboard ---reader using ONE HOT encoding. - -constant idle: std_logic_vector (5 downto 0):="000000"; -constant shift_data: std_logic_vector (5 downto 0):="000001"; -constant check_parity: std_logic_vector (5 downto 0):="000010"; -constant check_stopbit:std_logic_vector (5 downto 0):="000100"; -constant frame_error: std_logic_vector (5 downto 0):="001000"; -constant parity_error: std_logic_vector (5 downto 0):="010000"; -constant end_char: std_logic_vector (5 downto 0):="100000"; - ---state register and next state register for the FSM -signal state, next_state: std_logic_vector (5 downto 0):=idle; - -signal D_PS2C: std_logic:='0'; -- debounced PS2C -signal Q1, Q2: std_logic:='0'; - ---shift register; stores the received bits -signal REG: std_logic_vector(7 downto 0):=X"00"; - -signal ptysum: std_logic:='0'; -- parity sum -signal ptycheck: std_logic:='0'; -- parity check bit - -signal cnt: integer range 0 to 7:=0; -- counter - ---The attributes below prevent the ISE compiler from ---optimizing the state machines. The states will be implemented as ---described in the constant declarations above. - -attribute fsm_extract : string; -attribute fsm_extract of state: signal is "no"; -attribute fsm_extract of next_state: signal is "no"; - -attribute fsm_encoding : string; -attribute fsm_encoding of state: signal is "user"; -attribute fsm_encoding of next_state: signal is "user"; - -attribute signal_encoding : string; -attribute signal_encoding of state: signal is "user"; -attribute signal_encoding of next_state: signal is "user"; - -begin - ----------------------------------------------------------------------- --- MODULE IMPLEMENTATION ----------------------------------------------------------------------- - ------------------ Sample Keyboard Inputs ----------------------------- - -debounce: process (mclk, PS2C, Q1, Q2) -begin - if mclk'event and mclk='1' then - Q1<=PS2C; - Q2<=Q1; - end if; -end process debounce; - -D_PS2C<= (NOT Q1) and Q2; - ------------------ Synchronization Process ---------------------------- - -regstate: process (mclk, next_state, rst) -begin - if rst='1' then - state<=idle; -- state machine reset - elsif mclk'EVENT and mclk='1' then - state<=next_state; - end if; -end process regstate; - --------------------- State Transitions ------------------------------- - -transition: process (state, D_PS2C, PS2D, cnt, ptycheck) -begin -case state is - when idle=>-- idle - if D_PS2C='1' and PS2D='0' then -- check start bit - next_state<=shift_data; - else - next_state<=idle; - end if; - - when shift_data=> -- shift in data - if D_PS2C='1' and cnt=7 then - next_state<=check_parity; -- go and check parity - else - next_state<=shift_data; - end if; - - when check_parity=> -- check parity - if D_PS2C='1' and PS2D=ptycheck then - next_state<=check_stopbit; -- valid parity bit - -- go and check stopbit - elsif D_PS2C='1' then - next_state<=parity_error; -- parity error - else - next_state<=check_parity; - end if; - - when check_stopbit=> -- check stopbit; - if D_PS2C='1' and PS2D='1' then - next_state<=end_char; -- valid stopbit, end Char - elsif D_PS2C='1' then - next_state<=frame_error; -- Frame Error - else - next_state<=check_stopbit; - end if; - - when frame_error=> -- Frame Error - next_state<=idle; - - when parity_error=> -- Parity Error - next_state<=idle; - - when end_char=> -- end Char - next_state<=idle; - - when others => next_state<=idle; -end case; -end process transition; - - -------Counting bits and registering when state=shift_data--------------- - -regin: process (mclk, D_PS2C, PS2D, cnt, ptysum, state) -begin -if state/=shift_data then - cnt<=0; - ptysum<='0'; -elsif mclk'EVENT and mclk='1' then - if D_PS2C='1' then - ptysum<=ptysum XOR PS2D; -- calculating the parity sum - REG(7 downto 0)<=PS2D®(7 downto 1); -- shifting data into register - - if cnt=7 then - cnt<=0; - else - cnt<=cnt+1; - end if; - end if; -end if; -end process regin; - -------------------PARITIY SUM------------------------------------------- - -parity_sum: process (mclk, D_PS2C, PS2D, cnt, state, ptysum) -begin -if mclk'EVENT and mclk='1' then - if state=shift_data and D_PS2C='1' and cnt=7 then - ptycheck<=(NOT ptysum) XOR PS2D; --parity check bit - end if; -end if; -end process parity_sum; - -----------------OUTPUT ASSIGNEMENT-------------------------------------- - -Ps2Dout<=REG; -fRd<='1' when state=end_char else '0'; - -end Behavioral; \ No newline at end of file diff --git a/Computer_MiST/HT1080z_MiST/rtl/ram16k.vhd b/Computer_MiST/HT1080z_MiST/rtl/ram16k.vhd deleted file mode 100644 index 66600697..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/ram16k.vhd +++ /dev/null @@ -1,34 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity ram16k is - Port ( clk : in STD_LOGIC; - a : in STD_LOGIC_VECTOR (13 downto 0); - din : in STD_LOGIC_VECTOR (7 downto 0); - dout : out STD_LOGIC_VECTOR (7 downto 0); - wr : in STD_LOGIC); -end ram16k; - -architecture Behavioral of ram16k is - -type - ramarray is array(0 to 16383) of std_logic_vector(7 downto 0); - -signal - mem : ramarray; -begin - -process(clk) -begin - if rising_edge(clk) then - dout <= mem(conv_integer(a)); - if wr='0' then - mem(conv_integer(a)) <= din; - end if; - end if; -end process; - -end Behavioral; - diff --git a/Computer_MiST/HT1080z_MiST/rtl/rom16k.vhd b/Computer_MiST/HT1080z_MiST/rtl/rom16k.vhd deleted file mode 100644 index d7ce2735..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/rom16k.vhd +++ /dev/null @@ -1,1081 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity rom16k is - Port ( CLK : in STD_LOGIC; - A : in STD_LOGIC_VECTOR (13 downto 0); - DOUT : out STD_LOGIC_VECTOR (7 downto 0) - ); - -end rom16k; - -architecture Behavioral of rom16k is - -type - -- 14K ROM 0000..37FF - romarray is array(0 to 16383) of std_logic_vector(7 downto 0); - -constant - myROM : romarray := ( - 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b/Computer_MiST/HT1080z_MiST/rtl/scandoubler.v deleted file mode 100644 index e1b0da48..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,147 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -module scandoubler ( - // system interface - input clk_in, - input clk_out, - - input scanlines, - - // shifter video interface - input hs_in, - input vs_in, - input [5:0] r_in, - input [5:0] g_in, - input [5:0] b_in, - - // output interface - output reg [5:0] r_out, - output reg [5:0] g_out, - output reg [5:0] b_out, - output reg vs_out, - output reg hs_out -); - -// scan doubler output register -reg [17:0] sd_out; - -// --------------------- create output signals ----------------- -// latch everything once more to make it glitch free and apply scanline effect -reg scanline; - -always @(posedge clk_out) begin - vs_out <= vs_in; - hs_out <= hs_sd; - - // reset scanlines at every new screen - if(vs_out != vs_in) - scanline <= 1'b0; - - // toggle scanlines at begin of every hsync - if(hs_out && !hs_sd) - scanline <= !scanline; - - // if no scanlines or not a scanline - if(!scanlines || !scanline) begin - r_out <= { sd_out[17:12] }; - g_out <= { sd_out[11:6] }; - b_out <= { sd_out[5:0] }; - end else begin - r_out <= { 1'b0, sd_out[17:13] }; - g_out <= { 1'b0, sd_out[11:7] }; - b_out <= { 1'b0, sd_out[5:1] }; - end -end - - - -// ================================================================== -// ======================== the line buffers ======================== -// ================================================================== - -// 2 lines of 1024 pixels 3*6 bit RGB -reg [17:0] sd_buffer [2047:0]; - -// use alternating sd_buffers when storing/reading data -reg vsD; -reg line_toggle; -always @(negedge clk_in) begin - vsD <= vs_in; - - if(vsD != vs_in) - line_toggle <= 1'b0; - - // begin of incoming hsync - if(hsD && !hs_in) - line_toggle <= !line_toggle; -end - -always @(negedge clk_in) begin - sd_buffer[{line_toggle, hcnt}] <= { r_in, g_in, b_in }; -end - -// ================================================================== -// =================== horizontal timing analysis =================== -// ================================================================== - -// total hsync time (in 16MHz cycles), hs_total reaches 1024 -reg [9:0] hs_max; -reg [9:0] hs_rise; -reg [9:0] hcnt; -reg hsD; - -always @(negedge clk_in) begin - hsD <= hs_in; - - // falling edge of hsync indicates start of line - if(hsD && !hs_in) begin - hs_max <= hcnt; - hcnt <= 10'd0; - end else - hcnt <= hcnt + 10'd1; - - // save position of rising edge - if(!hsD && hs_in) - hs_rise <= hcnt; -end - -// ================================================================== -// ==================== output timing generation ==================== -// ================================================================== - -reg [9:0] sd_hcnt; -reg hs_sd; - -// timing generation runs 32 MHz (twice the input signal analysis speed) -always @(posedge clk_out) begin - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 10'd1; - if(hsD && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 10'd0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_sd <= 1'b0; - if(sd_hcnt == hs_rise) hs_sd <= 1'b1; - - // read data from line sd_buffer - sd_out <= sd_buffer[{~line_toggle, sd_hcnt}]; -end - -endmodule diff --git a/Computer_MiST/HT1080z_MiST/rtl/sdram.v b/Computer_MiST/HT1080z_MiST/rtl/sdram.v deleted file mode 100644 index 9db47ec8..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/sdram.v +++ /dev/null @@ -1,147 +0,0 @@ -// -// sdram.v -// -// sdram controller implementation for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2013 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module sdram ( - - // interface to the MT48LC16M16 chip - inout [15:0] sd_data, // 16 bit bidirectional data bus - output [12:0] sd_addr, // 13 bit multiplexed address bus - output [1:0] sd_dqm, // two byte masks - output [1:0] sd_ba, // two banks - output sd_cs, // a single chip select - output sd_we, // write enable - output sd_ras, // row address select - output sd_cas, // columns address select - - // cpu/chipset interface - input init, // init signal after FPGA config to initialize RAM - input clk, // sdram is accessed at up to 128MHz - input clkref, // reference clock to sync to - - input [7:0] din, // data input from chipset/cpu - output [7:0] dout, // data output to chipset/cpu - input [24:0] addr, // 25 bit byte address - input oe, // cpu/chipset requests read - input we // cpu/chipset requests write -); - -// no burst configured -localparam RASCAS_DELAY = 3'd3; // tRCD>=20ns -> 2 cycles@64MHz -localparam BURST_LENGTH = 3'b000; // 000=none, 001=2, 010=4, 011=8 -localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved -localparam CAS_LATENCY = 3'd2; // 2/3 allowed -localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed -localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write - -localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; - -// --------------------------------------------------------------------- -// ------------------------ cycle state machine ------------------------ -// --------------------------------------------------------------------- - -localparam STATE_IDLE = 3'd0; // first state in cycle -localparam STATE_CMD_START = 3'd1; // state in which a new command can be started -localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY - 3'd1; // 4 command can be continued -localparam STATE_LAST = 3'd7; // last state in cycle - -reg [2:0] q /* synthesis noprune */; -always @(posedge clk) begin - // 32Mhz counter synchronous to 4 Mhz clock - // force counter to pass state 5->6 exactly after the rising edge of clkref - // since clkref is two clocks early - if(((q == 6) && ( clkref == 0)) || - ((q == 7) && ( clkref == 1)) || - ((q != 6) && (q != 7))) - q <= q + 3'd1; -end - -// --------------------------------------------------------------------- -// --------------------------- startup/reset --------------------------- -// --------------------------------------------------------------------- - -// wait 1ms (32 clkref cycles) after FPGA config is done before going -// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) -reg [4:0] reset; -always @(posedge clk) begin - if(init) reset <= 5'h1f; - else if((q == STATE_LAST) && (reset != 0)) - reset <= reset - 5'd1; -end - -// --------------------------------------------------------------------- -// ------------------ generate ram control signals --------------------- -// --------------------------------------------------------------------- - -// all possible commands -localparam CMD_INHIBIT = 4'b1111; -localparam CMD_NOP = 4'b0111; -localparam CMD_ACTIVE = 4'b0011; -localparam CMD_READ = 4'b0101; -localparam CMD_WRITE = 4'b0100; -localparam CMD_BURST_TERMINATE = 4'b0110; -localparam CMD_PRECHARGE = 4'b0010; -localparam CMD_AUTO_REFRESH = 4'b0001; -localparam CMD_LOAD_MODE = 4'b0000; - -reg [3:0] sd_cmd; // current command sent to sd ram - -// drive control signals according to current command -assign sd_cs = sd_cmd[3]; -assign sd_ras = sd_cmd[2]; -assign sd_cas = sd_cmd[1]; -assign sd_we = sd_cmd[0]; - -assign sd_data = we?{din, din}:16'bZZZZZZZZZZZZZZZZ; - -assign dout = sd_data[7:0]; - -always @(posedge clk) begin - sd_cmd <= CMD_INHIBIT; - - if(reset != 0) begin - if(q == STATE_IDLE) begin - if(reset == 13) sd_cmd <= CMD_PRECHARGE; - if(reset == 2) sd_cmd <= CMD_LOAD_MODE; - end - end else begin - if(q == STATE_IDLE) begin - if(we || oe) sd_cmd <= CMD_ACTIVE; - else sd_cmd <= CMD_AUTO_REFRESH; - end else if(q == STATE_CMD_CONT) begin - if(we) sd_cmd <= CMD_WRITE; - else if(oe) sd_cmd <= CMD_READ; - end - end -end - -wire [12:0] reset_addr = (reset == 13)?13'b0010000000000:MODE; - -wire [12:0] run_addr = - (q == STATE_CMD_START)?addr[20:8]:{ 4'b0010, addr[23], addr[7:0]}; - -assign sd_addr = (reset != 0)?reset_addr:run_addr; - -assign sd_ba = addr[22:21]; - -assign sd_dqm = 2'b00; - -endmodule diff --git a/Computer_MiST/HT1080z_MiST/rtl/user_io.v b/Computer_MiST/HT1080z_MiST/rtl/user_io.v deleted file mode 100644 index 0bf354da..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/user_io.v +++ /dev/null @@ -1,416 +0,0 @@ -// -// user_io.v -// -// user_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// parameter STRLEN and the actual length of conf_str have to match - -module user_io #(parameter STRLEN=0) ( - input [(8*STRLEN)-1:0] conf_str, - - input SPI_CLK, - input SPI_SS_IO, - output reg SPI_MISO, - input SPI_MOSI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - - output reg [7:0] status, - - // connection to sd card emulation - input [31:0] sd_lba, - input sd_rd, - input sd_wr, - output reg sd_ack, - input sd_conf, - input sd_sdhc, - output [7:0] sd_dout, // valid on rising edge of sd_dout_strobe - output reg sd_dout_strobe, - input [7:0] sd_din, - output reg sd_din_strobe, - - - // ps2 keyboard emulation - input ps2_clk, // 12-16khz provided by core - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // pal/vga switch - output scandoubler_disable, - - // serial com port - input [7:0] serial_data, - input serial_strobe -); - -reg [6:0] sbuf; -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [7:0] byte_cnt; // counts bytes -reg [5:0] joystick0; -reg [5:0] joystick1; -reg [4:0] but_sw; -reg [2:0] stick_idx; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; -assign sd_dout = { sbuf, SPI_MOSI}; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; - -// filter spi clock. the 8 bit gate delay is ~2.5ns in total -wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */; -wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff); - -// drive MISO only when transmitting core id -always@(negedge spi_sck or posedge SPI_SS_IO) begin - if(SPI_SS_IO == 1) begin - SPI_MISO <= 1'bZ; - end else begin - - // first byte returned is always core type, further bytes are - // command dependent - if(byte_cnt == 0) begin - SPI_MISO <= core_type[~bit_cnt]; - - end else begin - // reading serial fifo - if(cmd == 8'h1b) begin - // send alternating flag byte and data - if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt]; - else SPI_MISO <= serial_out_byte[~bit_cnt]; - end - - // reading config string - else if(cmd == 8'h14) begin - // returning a byte from string - if(byte_cnt < STRLEN + 1) - SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; - else - SPI_MISO <= 1'b0; - end - - // reading sd card status - else if(cmd == 8'h16) begin - if(byte_cnt == 1) - SPI_MISO <= sd_cmd[~bit_cnt]; - else if((byte_cnt >= 2) && (byte_cnt < 6)) - SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}]; - else - SPI_MISO <= 1'b0; - end - - // reading sd card write data - else if(cmd == 8'h18) - SPI_MISO <= sd_din[~bit_cnt]; - - else - SPI_MISO <= 1'b0; - end - end -end - -// ---------------- PS2 --------------------- - -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -// keyboard -reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0]; -reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr; -reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr; - -// ps2 transmitter state machine -reg [3:0] ps2_kbd_tx_state; -reg [7:0] ps2_kbd_tx_byte; -reg ps2_kbd_parity; - -assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0); - -// ps2 transmitter -// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. -reg ps2_kbd_r_inc; -always@(posedge ps2_clk) begin - ps2_kbd_r_inc <= 1'b0; - - if(ps2_kbd_r_inc) - ps2_kbd_rptr <= ps2_kbd_rptr + 1; - - // transmitter is idle? - if(ps2_kbd_tx_state == 0) begin - // data in fifo present? - if(ps2_kbd_wptr != ps2_kbd_rptr) begin - // load tx register from fifo - ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr]; - ps2_kbd_r_inc <= 1'b1; - - // reset parity - ps2_kbd_parity <= 1'b1; - - // start transmitter - ps2_kbd_tx_state <= 4'd1; - - // put start bit on data line - ps2_kbd_data <= 1'b0; // start bit is 0 - end - end else begin - - // transmission of 8 data bits - if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) - ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) - ps2_kbd_data <= 1'b1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) - ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1; - else - ps2_kbd_tx_state <= 4'd0; - - end -end - -// mouse -reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0]; -reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr; -reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr; - -// ps2 transmitter state machine -reg [3:0] ps2_mouse_tx_state; -reg [7:0] ps2_mouse_tx_byte; -reg ps2_mouse_parity; - -assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0); - -// ps2 transmitter -// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. -reg ps2_mouse_r_inc; -always@(posedge ps2_clk) begin - ps2_mouse_r_inc <= 1'b0; - - if(ps2_mouse_r_inc) - ps2_mouse_rptr <= ps2_mouse_rptr + 1; - - // transmitter is idle? - if(ps2_mouse_tx_state == 0) begin - // data in fifo present? - if(ps2_mouse_wptr != ps2_mouse_rptr) begin - // load tx register from fifo - ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr]; - ps2_mouse_r_inc <= 1'b1; - - // reset parity - ps2_mouse_parity <= 1'b1; - - // start transmitter - ps2_mouse_tx_state <= 4'd1; - - // put start bit on data line - ps2_mouse_data <= 1'b0; // start bit is 0 - end - end else begin - - // transmission of 8 data bits - if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) - ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) - ps2_mouse_data <= 1'b1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) - ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1; - else - ps2_mouse_tx_state <= 4'd0; - - end -end - -// fifo to receive serial data from core to be forwarded to io controller - -// 16 byte fifo to store serial bytes -localparam SERIAL_OUT_FIFO_BITS = 6; -reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0]; -reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr; -reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr; - -wire serial_out_data_available = serial_out_wptr != serial_out_rptr; -wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */; -wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available}; - -// status[0] is reset signal from io controller and is thus used to flush -// the fifo -always @(posedge serial_strobe or posedge status[0]) begin - if(status[0] == 1) begin - serial_out_wptr <= 0; - end else begin - serial_out_fifo[serial_out_wptr] <= serial_data; - serial_out_wptr <= serial_out_wptr + 1; - end -end - -always@(negedge spi_sck or posedge status[0]) begin - if(status[0] == 1) begin - serial_out_rptr <= 0; - end else begin - if((byte_cnt != 0) && (cmd == 8'h1b)) begin - // read last bit -> advance read pointer - if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available) - serial_out_rptr <= serial_out_rptr + 1; - end - end -end - -// SPI receiver -always@(posedge spi_sck or posedge SPI_SS_IO) begin - - if(SPI_SS_IO == 1) begin - bit_cnt <= 3'd0; - byte_cnt <= 8'd0; - sd_ack <= 1'b0; - sd_dout_strobe <= 1'b0; - sd_din_strobe <= 1'b0; - end else begin - sd_dout_strobe <= 1'b0; - sd_din_strobe <= 1'b0; - - if(bit_cnt != 7) - sbuf[6:0] <= { sbuf[5:0], SPI_MOSI }; - - bit_cnt <= bit_cnt + 3'd1; - if((bit_cnt == 7)&&(byte_cnt != 8'd255)) - byte_cnt <= byte_cnt + 8'd1; - - // finished reading command byte - if(bit_cnt == 7) begin - if(byte_cnt == 0) begin - cmd <= { sbuf, SPI_MOSI}; - - // fetch first byte when sectore FPGA->IO command has been seen - if({ sbuf, SPI_MOSI} == 8'h18) - sd_din_strobe <= 1'b1; - - if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18)) - sd_ack <= 1'b1; - - end else begin - - // buttons and switches - if(cmd == 8'h01) - but_sw <= { sbuf[3:0], SPI_MOSI }; - - if(cmd == 8'h02) - joystick_0 <= { sbuf, SPI_MOSI }; - - if(cmd == 8'h03) - joystick_1 <= { sbuf, SPI_MOSI }; - - if(cmd == 8'h04) begin - // store incoming ps2 mouse bytes - ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI }; - ps2_mouse_wptr <= ps2_mouse_wptr + 1; - end - - if(cmd == 8'h05) begin - // store incoming ps2 keyboard bytes - ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI }; - ps2_kbd_wptr <= ps2_kbd_wptr + 1; - end - - if(cmd == 8'h15) - status <= { sbuf[6:0], SPI_MOSI }; - - // send sector IO -> FPGA - if(cmd == 8'h17) begin - // flag that download begins -// sd_dout <= { sbuf, SPI_MOSI}; - sd_dout_strobe <= 1'b1; - end - - // send sector FPGA -> IO - if(cmd == 8'h18) - sd_din_strobe <= 1'b1; - - // send SD config IO -> FPGA - if(cmd == 8'h19) begin - // flag that download begins -// sd_dout <= { sbuf, SPI_MOSI}; - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - sd_dout_strobe <= 1'b1; - end - - // joystick analog - if(cmd == 8'h1a) begin - // first byte is joystick indes - if(byte_cnt == 1) - stick_idx <= { sbuf[1:0], SPI_MOSI }; - else if(byte_cnt == 2) begin - // second byte is x axis - if(stick_idx == 0) - joystick_analog_0[15:8] <= { sbuf, SPI_MOSI }; - else if(stick_idx == 1) - joystick_analog_1[15:8] <= { sbuf, SPI_MOSI }; - end else if(byte_cnt == 3) begin - // third byte is y axis - if(stick_idx == 0) - joystick_analog_0[7:0] <= { sbuf, SPI_MOSI }; - else if(stick_idx == 1) - joystick_analog_1[7:0] <= { sbuf, SPI_MOSI }; - end - end - - end - end - end -end - -endmodule diff --git a/Computer_MiST/HT1080z_MiST/rtl/videoctrl.vhd b/Computer_MiST/HT1080z_MiST/rtl/videoctrl.vhd deleted file mode 100644 index fe2bc9ff..00000000 --- a/Computer_MiST/HT1080z_MiST/rtl/videoctrl.vhd +++ /dev/null @@ -1,629 +0,0 @@ --- --- HT 1080Z (TSR-80 clone) video controller PAL/VGA capable --- --- --- Copyright (c) 2016-2017 Jozsef Laszlo (rbendr@gmail.com) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity videoctrl is - Generic ( - H_START : integer := 42+84+81-16; - V_START : integer := 2+28+((266-192)/2)+4 - ); - Port ( - reset : in STD_LOGIC; - clk42 : in STD_LOGIC; - --clk7 : in STD_LOGIC; - a : in STD_LOGIC_VECTOR (13 downto 0); - din : in STD_LOGIC_VECTOR (7 downto 0); - dout : out STD_LOGIC_VECTOR (7 downto 0); - mreq : in STD_LOGIC; - iorq : in STD_LOGIC; - wr : in STD_LOGIC; - cs : in STD_LOGIC; - vcut : in STD_LOGIC; - vvga : in STD_LOGIC; - page : in STD_LOGIC; - inkp : in STD_LOGIC; - paperp : in STD_LOGIC; - borderp : in STD_LOGIC; - oddline : out STD_LOGIC; - rgbi : out STD_LOGIC_VECTOR (3 downto 0); - pclk : out STD_LOGIC; - hsync : out STD_LOGIC; - vsync : out STD_LOGIC); -end videoctrl; - -architecture Behavioral of videoctrl is - -type videomem is array(0 to 1023) of std_logic_vector(7 downto 0); - -type charmem is array(0 to 4095) of std_logic_vector(7 downto 0); - -signal vidmem : videomem:=( -others => x"00" -); - -signal chrmem : charmem:=( - --[PATCH_START] -x"0e",x"11",x"15",x"17",x"16",x"10",x"0f",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", 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downto 0); -signal vstart : std_logic_vector(8 downto 0); -signal vend : std_logic_vector(8 downto 0); - -signal pxclk : std_logic; -signal xpxclk : std_logic; - -signal hact,vact : std_logic; - - -signal border : std_logic_vector(3 downto 0) := "0010"; -signal paper : std_logic_vector(3 downto 0) := "0000"; -signal ink : std_logic_vector(3 downto 0) := "1000"; -signal pixel : std_logic_vector(3 downto 0); - -signal screen : std_logic; -signal hblank,vblank,blank : std_logic; - -signal vaVert : std_logic_vector(3 downto 0); -- vertical line -signal vaHoriz : std_logic_vector(5 downto 0); -- horizontal columnt pos - -signal chraddr : std_logic_vector(11 downto 0); -- character bitmap data address in the charmem -signal chrCode : std_logic_vector(7 downto 0); -signal chrGrap : std_logic_vector(7 downto 0); -signal shiftReg : std_logic_vector(7 downto 0); - -signal xpxsel : std_logic_vector(1 downto 0); -signal v1 : std_logic; - -signal rinkp,rpaperp,rborderp : std_logic; - -begin - ---pxclk <= clk10_5; ---xpxclk <= clk10_5 when vcut='0' else clk5_25; ---hstart <= conv_std_logic_vector(H_START,10); ---vstart <= conv_std_logic_vector(V_START,9); ---vend <= conv_std_logic_vector(311,9); - -pxclk <= clk10_5 when vvga='0' else clk21; -xpxsel <= vvga & vcut; -with xpxsel select xpxclk <= - clk10_5 when "00", - clk5_25 when "01", - clk21 when "10", - clk10_5 when others; - -hstart <= conv_std_logic_vector(H_START,10) when vvga='0' else conv_std_logic_vector(H_START,10); -vstart <= conv_std_logic_vector(V_START,9) when vvga='0' else conv_std_logic_vector(V_START-30,9); -vend <= conv_std_logic_vector(311,9) when vvga='0' else conv_std_logic_vector(262,9); - -process(clk42) -begin - if rising_edge(clk42) then - clkdiv <= clkdiv + 1; - end if; -end process; - -process(RESET,clk10_5) -begin - if RESET='0' then - ink <= "1000"; - paper <= "0000"; - border <= "0000"; - else - if rising_edge(clk10_5) then - - rinkp <= INKP; - rpaperp <= PAPERP; - rborderp <= BORDERP; - if rinkp='0' and INKP='1' then - ink <= ink+1; - end if; - if rpaperp='0' and PAPERP='1' then - paper <= paper+1; - end if; - if rborderp='0' and BORDERP='1' then - border <= border+1; - end if; - - if iorq='0' and wr='0' and a(7 downto 2)="000000" then - case a(1 downto 0) is - when "00"=> ink<=din(3 downto 0); - when "01"=> paper<=din(3 downto 0); - when "10"=> border<=din(3 downto 0); - when others=>null; - end case; - end if; - end if; - end if; -end process; - - -process(clk10_5) -begin - if rising_edge(clk10_5) then - chrCode <= vidmem(conv_integer( vaVert & vaHoriz )); - chrGrap <= chrmem(conv_integer( chrCode & vpos )); - dout <= vidmem(conv_integer( a(9 downto 0) )); - if cs='0' and wr='0' then - vidmem(conv_integer( a(9 downto 0) )) <= din; - end if; - end if; -end process; - --- h and v counters --- 10.5 MHz pixelclock => 672 pixels per scan line --- 312 scanlines --- 64*6 pixels active screen = 384 pixels --- visible area: 52*10.5 = 546 --- Horizontal: |42T-hsync|84T-porch|81T-border|384T-screen|81T-border| -process(pxclk) -begin - if rising_edge(pxclk) then - if hctr=671 then - hctr<="0000000000"; - v1 <= not v1; - if vctr>=vend then - vctr<="000000000"; - v1 <= '0'; - else - --vctr<=vctr+1; - if v1='1' or vvga='0' then - vctr<=vctr+1; - end if; - end if; - else - hctr<=hctr+1; - end if; - end if; -end process; - ---process(pxclk) ---begin --- if falling_edge(pxclk) then --- --- -- 12*10.5 --- if hctr<126 or hctr>654 then --- hblank <= '0'; --- else --- hblank <= '1'; --- end if; --- --- if hctr<42 then -- 4*10.5 --- hsync <= '0'; --- else --- hsync <= '1'; --- end if; --- --- if vctr<6 or vctr>309 then --- vblank <= '0'; --- else --- vblank <= '1'; --- end if; --- --- if vctr<2 then --- vsync <= '0'; --- else --- vsync <= '1'; --- end if; --- --- end if; ---end process; - -process(pxclk) -begin - if falling_edge(pxclk) then - - if vvga='0' then - -- 12*10.5 - if hctr<126 or hctr>654 then - hblank <= '0'; - else - hblank <= '1'; - end if; - else - -- VGA 6us - -- - --if hctr<64 or hctr>662 then - if hctr<120 or hctr>654 then - hblank <= '0'; - else - hblank <= '1'; - end if; - end if; - - if vvga='0' then - if hctr<42 then -- 4*10.5 - hsync <= '0'; - else - hsync <= '1'; - end if; - - if vctr<6 or vctr>309 then - vblank <= '0'; - else - vblank <= '1'; - end if; - - else - if hctr<79 then -- 4*21 - hsync <= '0'; - else - hsync <= '1'; - end if; - - if vctr<16 or vctr>257 then - vblank <= '0'; - else - vblank <= '1'; - end if; - - end if; - - - if vctr<2 then - vsync <= '0'; - else - vsync <= '1'; - end if; - - end if; -end process; - -hact <= '1' when hctr>=hstart and hctr=vstart and vctr, NATURAL RANGE <>) of STD_LOGIC; - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC_2D (7 DOWNTO 0, 0 DOWNTO 0); - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC ; - SIGNAL sub_wire7 : STD_LOGIC ; - SIGNAL sub_wire8 : STD_LOGIC ; - SIGNAL sub_wire9 : STD_LOGIC ; - SIGNAL sub_wire10 : STD_LOGIC ; - -BEGIN - sub_wire10 <= data0; - sub_wire9 <= data1; - sub_wire8 <= data2; - sub_wire7 <= data3; - sub_wire6 <= data4; - sub_wire5 <= data5; - sub_wire4 <= data6; - sub_wire1 <= sub_wire0(0); - result <= sub_wire1; - sub_wire2 <= data7; - sub_wire3(7, 0) <= sub_wire2; - sub_wire3(6, 0) <= sub_wire4; - sub_wire3(5, 0) <= sub_wire5; - sub_wire3(4, 0) <= sub_wire6; - sub_wire3(3, 0) <= sub_wire7; - sub_wire3(2, 0) <= sub_wire8; - sub_wire3(1, 0) <= sub_wire9; - sub_wire3(0, 0) <= sub_wire10; - - LPM_MUX_component : LPM_MUX - GENERIC MAP ( - lpm_size => 8, - lpm_type => "LPM_MUX", - lpm_width => 1, - lpm_widths => 3 - ) - PORT MAP ( - data => sub_wire3, - sel => sel, - result => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" --- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" --- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0" --- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1" --- Retrieval info: USED_PORT: data2 0 0 0 0 INPUT NODEFVAL "data2" --- Retrieval info: USED_PORT: data3 0 0 0 0 INPUT NODEFVAL "data3" --- Retrieval info: USED_PORT: data4 0 0 0 0 INPUT NODEFVAL "data4" --- Retrieval info: USED_PORT: data5 0 0 0 0 INPUT NODEFVAL "data5" --- Retrieval info: USED_PORT: data6 0 0 0 0 INPUT NODEFVAL "data6" --- Retrieval info: USED_PORT: data7 0 0 0 0 INPUT NODEFVAL "data7" --- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result" --- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]" --- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0 --- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0 --- Retrieval info: CONNECT: @data 1 2 1 0 data2 0 0 0 0 --- Retrieval info: CONNECT: @data 1 3 1 0 data3 0 0 0 0 --- Retrieval info: CONNECT: @data 1 4 1 0 data4 0 0 0 0 --- Retrieval info: CONNECT: @data 1 5 1 0 data5 0 0 0 0 --- Retrieval info: CONNECT: @data 1 6 1 0 data6 0 0 0 0 --- Retrieval info: CONNECT: @data 1 7 1 0 data7 0 0 0 0 --- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 --- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL HC4051_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/I_PN_GEN.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/I_PN_GEN.vhd deleted file mode 100644 index 927558be..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/I_PN_GEN.vhd +++ /dev/null @@ -1,100 +0,0 @@ --- --- fg.vhd --- --- Generate a random noise. --- --- Copyright (C)2001 SEILEBOST --- All rights reserved. --- --- $Id: fg.vhd, v0.3 2001/11/14 00:00:00 SEILEBOST $ --- --- from XAPP211.pdf & XAPP211.ZIP (XILINX APPLICATION) --- ---The following is example code that implements one LFSR which can be used as part of pn generators. ---The number of taps, tap points, and LFSR width are parameratizable. When targetting Xilinx (Virtex) ---all the latest synthesis vendors (Leonardo, Synplicity, and FPGA Express) will infer the shift ---register LUTS (SRL16) resulting in a very efficient implementation. --- ---Control signals have been provided to allow external circuitry to control such things as filling, ---puncturing, stalling (augmentation), etc. --- ---Mike Gulotta ---11/4/99 ---Revised 3/17/00: Fixed "commented" block diagram to match polynomial. --- --- ---################################################################################################### --- I Polinomials: # --- I(x) = X**17 + X**2 + 1 # --- # --- LFSR implementation format examples: # ---################################################################################################### --- # --- I(x) = X**17 + X**2 + 1 # --- ________ # --- | |<<......................... # --- | Parity | | # --- .................| |<<... | # --- | |________| | | # --- | | | # --- | __________________ | ___ ___ | # --- |...|\ | | | | | | | | | pn_out_i # --- ||-->>| 16 | - - - -| 2 |-----| 1 | 0 | >>---------->> # ---DataIn_i.|/ |____|________|____| |___|___| # --- | srl_i # --- FillSel..| # --- ---> shifting -->> # - -library ieee ; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity i_pn_gen is - generic(NumOfTaps_i : integer := 2; -- # of taps for I channel LFSR, including output tap. - Width : integer := 17); -- LFSR length (ie, total # of storage elements) - port(clk, ShiftEn, FillSel, DataIn_i, RESET : in std_logic; - pn_out_i : out std_logic); -end i_pn_gen ; - - -architecture rtl of i_pn_gen is - - type TapPointArray_i is array (NumOfTaps_i-1 downto 0) of integer; - constant Tap_i : TapPointArray_i := (2, 0); - signal srl_i : std_logic_vector(Width-1 downto 0); -- shift register. - signal par_fdbk_i : std_logic_vector(NumOfTaps_i downto 0); -- Parity feedback. - signal lfsr_in_i : std_logic; -- mux output. - - -begin - ---------------------------------------------------------------------- ------------------- I Channel ---------------------------------------- ---------------------------------------------------------------------- - - Shift_i : process (clk, reset) - begin - if (RESET = '1') then - SRL_I <= "00000000000000000"; - elsif clk'event and clk = '1' then - if (ShiftEn = '1') then - srl_i <= lfsr_in_i & srl_i(srl_i'high downto 1); - end if; - end if; - end process; - - par_fdbk_i(0) <= '0'; - - fdbk_i : for X in 0 to Tap_i'high generate -- parity generator - par_fdbk_i(X+1) <= par_fdbk_i(X) xor srl_i(Tap_i(X)); - end generate fdbk_i; - - lfsr_in_i <= DataIn_i when FillSel = '1' else par_fdbk_i(par_fdbk_i'high); - - pn_out_i <= srl_i(srl_i'low); -- PN I channel output. - - -end rtl; - - - diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/MIXER.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/MIXER.vhd deleted file mode 100644 index 1e90676f..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/MIXER.vhd +++ /dev/null @@ -1,79 +0,0 @@ --- --- MIXER.vhd --- --- Mix tone generator and noise generator. --- --- Copyright (C)2001 SEILEBOST --- All rights reserved. --- --- $Id: MIXER.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $ --- --- A lot of work !! - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; - -entity MIXER is - Port ( CLK : in std_logic; - CS : in std_logic; - RST : in std_logic; - WR : in std_logic; - IN_A : in std_logic; - IN_B : in std_logic; - IN_C : in std_logic; - IN_NOISE : in std_logic; - DATA : in std_logic_vector(5 downto 0); - OUT_A : out std_logic; - OUT_B : out std_logic; - OUT_C : out std_logic ); -end MIXER; - -architecture Behavioral of MIXER is - - -begin - PROCESS(CLK, RST, CS, WR, DATA, IN_A, IN_B, IN_C, IN_NOISE) - BEGIN - if (RST = '1') then - OUT_A <= '0'; - OUT_B <= '0'; - OUT_C <= '0'; - elsif ( CLK'event and CLK = '1') then - if not (CS = '1' and WR = '1') then --- TONE A - if (DATA(0) = '0') then - if (DATA(3) = '0') then - OUT_A <= IN_A xor IN_NOISE; - else - OUT_A <= IN_A; - end if; - else - OUT_A <= '1'; - end if; - --- TONE B - if (DATA(1) = '0') then - if (DATA(4) = '0') then - OUT_B <= IN_B xor IN_NOISE; - else - OUT_B <= IN_B; - end if; - else - OUT_B <= '1'; - end if; - --- TONE C - if (DATA(2) = '0') then - if (DATA(5) = '0') then - OUT_C <= IN_C xor IN_NOISE; - else - OUT_C <= IN_C; - end if; - else - OUT_C <= '1'; - end if; - end if; - end if; - end process; -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/RAM8X1D.qip b/Computer_MiST/Oric Atmos_MiST/rtl/RAM8X1D.qip deleted file mode 100644 index 3684018b..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/RAM8X1D.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "RAM8X1D.vhd"] diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/RAM8X1D.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/RAM8X1D.vhd deleted file mode 100644 index 207c6dc0..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/RAM8X1D.vhd +++ /dev/null @@ -1,206 +0,0 @@ --- megafunction wizard: %RAM: 2-PORT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altsyncram - --- ============================================================ --- File Name: RAM8X1D.vhd --- Megafunction Name(s): --- altsyncram --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY RAM8X1D IS - PORT - ( - clock : IN STD_LOGIC := '1'; - data : IN STD_LOGIC_VECTOR (0 DOWNTO 0); - enable : IN STD_LOGIC := '1'; - rdaddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0); - rden : IN STD_LOGIC := '1'; - wraddress : IN STD_LOGIC_VECTOR (2 DOWNTO 0); - wren : IN STD_LOGIC := '0'; - q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) - ); -END RAM8X1D; - - -ARCHITECTURE SYN OF ram8x1d IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); - -BEGIN - q <= sub_wire0(0 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_b => "NONE", - address_reg_b => "CLOCK0", - clock_enable_input_a => "NORMAL", - clock_enable_input_b => "NORMAL", - clock_enable_output_b => "NORMAL", - intended_device_family => "Cyclone III", - lpm_type => "altsyncram", - numwords_a => 8, - numwords_b => 8, - operation_mode => "DUAL_PORT", - outdata_aclr_b => "NONE", - outdata_reg_b => "CLOCK0", - power_up_uninitialized => "FALSE", - rdcontrol_reg_b => "CLOCK0", - read_during_write_mode_mixed_ports => "DONT_CARE", - widthad_a => 3, - widthad_b => 3, - width_a => 1, - width_b => 1, - width_byteena_a => 1 - ) - PORT MAP ( - address_a => wraddress, - clock0 => clock, - data_a => data, - rden_b => rden, - wren_a => wren, - address_b => rdaddress, - clocken0 => enable, - q_b => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" --- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" --- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" --- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" --- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1" --- Retrieval info: PRIVATE: CLRdata NUMERIC "0" --- Retrieval info: PRIVATE: CLRq NUMERIC "0" --- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" --- Retrieval info: PRIVATE: CLRrren NUMERIC "0" --- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" --- Retrieval info: PRIVATE: CLRwren NUMERIC "0" --- Retrieval info: PRIVATE: Clock NUMERIC "0" --- Retrieval info: PRIVATE: Clock_A NUMERIC "0" --- Retrieval info: PRIVATE: Clock_B NUMERIC "0" --- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" --- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" --- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" --- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8" --- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "" --- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" --- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" --- Retrieval info: PRIVATE: REGdata NUMERIC "1" --- Retrieval info: PRIVATE: REGq NUMERIC "1" --- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" --- Retrieval info: PRIVATE: REGrren NUMERIC "1" --- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" --- Retrieval info: PRIVATE: REGwren NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" --- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" --- Retrieval info: PRIVATE: VarWidth NUMERIC "0" --- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "1" --- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1" --- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "1" --- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1" --- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" --- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: enable NUMERIC "1" --- Retrieval info: PRIVATE: rden NUMERIC "1" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" --- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8" --- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" --- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0" --- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" --- Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0" --- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3" --- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "3" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1" --- Retrieval info: CONSTANT: WIDTH_B NUMERIC "1" --- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" --- Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]" --- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC "enable" --- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]" --- Retrieval info: USED_PORT: rdaddress 0 0 3 0 INPUT NODEFVAL "rdaddress[2..0]" --- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" --- Retrieval info: USED_PORT: wraddress 0 0 3 0 INPUT NODEFVAL "wraddress[2..0]" --- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" --- Retrieval info: CONNECT: @address_a 0 0 3 0 wraddress 0 0 3 0 --- Retrieval info: CONNECT: @address_b 0 0 3 0 rdaddress 0 0 3 0 --- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0 --- Retrieval info: CONNECT: @data_a 0 0 1 0 data 0 0 1 0 --- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0 --- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 --- Retrieval info: CONNECT: q 0 0 1 0 @q_b 0 0 1 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL RAM8X1D_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/RAMB16_S18_S18.qip b/Computer_MiST/Oric Atmos_MiST/rtl/RAMB16_S18_S18.qip deleted file mode 100644 index da32ea00..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/RAMB16_S18_S18.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "RAMB16_S18_S18.vhd"] diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/RAMB16_S18_S18.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/RAMB16_S18_S18.vhd deleted file mode 100644 index 0b98af60..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/RAMB16_S18_S18.vhd +++ /dev/null @@ -1,234 +0,0 @@ --- megafunction wizard: %RAM: 2-PORT% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altsyncram - --- ============================================================ --- File Name: RAMB16_S18_S18.vhd --- Megafunction Name(s): --- altsyncram --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.altera_mf_components.all; - -ENTITY RAMB16_S18_S18 IS - PORT - ( - address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0); - clock_a : IN STD_LOGIC := '1'; - clock_b : IN STD_LOGIC ; - data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - rden_a : IN STD_LOGIC := '1'; - rden_b : IN STD_LOGIC := '1'; - wren_a : IN STD_LOGIC := '0'; - wren_b : IN STD_LOGIC := '0'; - q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) - ); -END RAMB16_S18_S18; - - -ARCHITECTURE SYN OF ramb16_s18_s18 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); - -BEGIN - q_a <= sub_wire0(15 DOWNTO 0); - q_b <= sub_wire1(15 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_reg_b => "CLOCK1", - clock_enable_input_a => "BYPASS", - clock_enable_input_b => "BYPASS", - clock_enable_output_a => "BYPASS", - clock_enable_output_b => "BYPASS", - indata_reg_b => "CLOCK1", - intended_device_family => "Cyclone III", - lpm_type => "altsyncram", - numwords_a => 1024, - numwords_b => 1024, - operation_mode => "BIDIR_DUAL_PORT", - outdata_aclr_a => "NONE", - outdata_aclr_b => "NONE", - outdata_reg_a => "CLOCK0", - outdata_reg_b => "CLOCK1", - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", - widthad_a => 10, - widthad_b => 10, - width_a => 16, - width_b => 16, - width_byteena_a => 1, - width_byteena_b => 1, - wrcontrol_wraddress_reg_b => "CLOCK1" - ) - PORT MAP ( - clock0 => clock_a, - wren_a => wren_a, - address_b => address_b, - clock1 => clock_b, - data_b => data_b, - rden_a => rden_a, - wren_b => wren_b, - address_a => address_a, - data_a => data_a, - rden_b => rden_b, - q_a => sub_wire0, - q_b => sub_wire1 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" --- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" --- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" --- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" --- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" --- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" --- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" --- Retrieval info: PRIVATE: CLRdata NUMERIC "0" --- Retrieval info: PRIVATE: CLRq NUMERIC "0" --- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" --- Retrieval info: PRIVATE: CLRrren NUMERIC "0" --- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" --- Retrieval info: PRIVATE: CLRwren NUMERIC "0" --- Retrieval info: PRIVATE: Clock NUMERIC "5" --- Retrieval info: PRIVATE: Clock_A NUMERIC "0" --- Retrieval info: PRIVATE: Clock_B NUMERIC "0" --- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" --- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" --- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" --- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" --- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" --- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" --- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384" --- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" --- Retrieval info: PRIVATE: MIFfilename STRING "" --- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" --- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" --- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" --- Retrieval info: PRIVATE: REGdata NUMERIC "1" --- Retrieval info: PRIVATE: REGq NUMERIC "1" --- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" --- Retrieval info: PRIVATE: REGrren NUMERIC "1" --- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" --- Retrieval info: PRIVATE: REGwren NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" --- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" --- Retrieval info: PRIVATE: VarWidth NUMERIC "0" --- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" --- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" --- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" --- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" --- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" --- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" --- Retrieval info: PRIVATE: enable NUMERIC "0" --- Retrieval info: PRIVATE: rden NUMERIC "1" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" --- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" --- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" --- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" --- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" --- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" --- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" --- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" --- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" --- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" --- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" --- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" --- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10" --- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" --- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" --- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" --- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" --- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" --- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]" --- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]" --- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" --- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" --- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]" --- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]" --- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]" --- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]" --- Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a" --- Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b" --- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" --- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" --- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0 --- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0 --- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 --- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 --- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0 --- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0 --- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0 --- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0 --- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 --- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 --- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0 --- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S18_S18_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/REG_ADDR.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/REG_ADDR.vhd deleted file mode 100644 index c334658d..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/REG_ADDR.vhd +++ /dev/null @@ -1,27 +0,0 @@ --- --- REG_ADDR.vhd --- --- DECODER of Registre. --- --- Copyright (C)2001 SEILEBOST --- All rights reserved. --- --- $Id: REG_ADDR.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $ --- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; - -entity REG_ADRESSE is - Port ( REG_ADDR : in std_logic_vector(3 downto 0); - RST : in std_logic, - SEL_REG : out std_logic_vector(15 downto 0) ); -end REG_ADRESSE; - -architecture Behavioral of REG_ADRESSE is - --- DECODER 4 -> 16 -begin - -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/STOP_WATCH.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/STOP_WATCH.vhd deleted file mode 100644 index 3442b987..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/STOP_WATCH.vhd +++ /dev/null @@ -1,78 +0,0 @@ ---=================================== --- Listing 4.17 ---=================================== -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -entity stop_watch is - port( - clk: in std_logic; - go, clr: in std_logic; - d2, d1, d0: out std_logic_vector(3 downto 0) - ); -end stop_watch; - ---=================================== --- Listing 4.18 ---=================================== -architecture if_arch of stop_watch is - constant DVSR: integer:=5000000; - signal ms_reg, ms_next: unsigned(22 downto 0); - signal d2_reg, d1_reg, d0_reg: unsigned(3 downto 0); - signal d2_next, d1_next, d0_next: unsigned(3 downto 0); - signal ms_tick: std_logic; -begin - -- register - process(clk) - begin - if (clk'event and clk='1') then - ms_reg <= ms_next; - d2_reg <= d2_next; - d1_reg <= d1_next; - d0_reg <= d0_next; - end if; - end process; - - -- next-state logic - -- 0.1 sec tick generator: mod-5000000 - ms_next <= - (others=>'0') when clr='1' or - (ms_reg=DVSR and go='1') else - ms_reg + 1 when go='1' else - ms_reg; - ms_tick <= '1' when ms_reg=DVSR else '0'; - -- 0.1 sec counter - process(d0_reg,d1_reg,d2_reg,ms_tick,clr) - begin - -- defult - d0_next <= d0_reg; - d1_next <= d1_reg; - d2_next <= d2_reg; - if clr='1' then - d0_next <= "0000"; - d1_next <= "0000"; - d2_next <= "0000"; - elsif ms_tick='1' then - if (d0_reg/=9) then - d0_next <= d0_reg + 1; - else -- reach XX9 - d0_next <= "0000"; - if (d1_reg/=9) then - d1_next <= d1_reg + 1; - else -- reach X99 - d1_next <= "0000"; - if (d2_reg/=9) then - d2_next <= d2_reg + 1; - else -- reach 999 - d2_next <= "0000"; - end if; - end if; - end if; - end if; - end process; - -- output logic - d0 <= std_logic_vector(d0_reg); - d1 <= std_logic_vector(d1_reg); - d2 <= std_logic_vector(d2_reg); -end if_arch; - diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/TST_ay3819x.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/TST_ay3819x.vhd deleted file mode 100644 index dbab8af7..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/TST_ay3819x.vhd +++ /dev/null @@ -1,174 +0,0 @@ - --- VHDL Test Bench Created from source file ay3819x.vhd -- 15:33:03 12/26/2001 --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY testbench IS -END testbench; - -ARCHITECTURE behavior OF testbench IS - -constant CLK_PERIOD : time := 60 nS; -- system clock period - - COMPONENT ay3819x - PORT( - RESET : IN std_logic; - CLOCK : IN std_logic; - BDIR : IN std_logic; - BC1 : IN std_logic; - BC2 : IN std_logic; - D : INOUT std_logic_vector(7 downto 0); - IOA : INOUT std_logic_vector(7 downto 0); - IOB : INOUT std_logic_vector(7 downto 0); - AnalogA : OUT std_logic; - AnalogB : OUT std_logic; - AnalogC : OUT std_logic ); - END COMPONENT; - - SIGNAL D : std_logic_vector(7 downto 0); - SIGNAL RESET : std_logic; - SIGNAL CLOCK : std_logic; - SIGNAL BDIR : std_logic; - SIGNAL BC1 : std_logic; - SIGNAL BC2 : std_logic; - SIGNAL IOA : std_logic_vector(7 downto 0); - SIGNAL IOB : std_logic_vector(7 downto 0); - SIGNAL AnalogA : std_logic; - SIGNAL AnalogB : std_logic; - SIGNAL AnalogC : std_logic; - -BEGIN - -uut: ay3819x PORT MAP( - D => D, - RESET => RESET, - CLOCK => CLOCK, - BDIR => BDIR, - BC1 => BC1, - BC2 => BC2, - IOA => IOA, - IOB => IOB, - AnalogA => AnalogA, - AnalogB => AnalogB, - AnalogC => AnalogC ); - - --- *** Test Bench - User Defined Section *** - -CREATE_CLK: process - begin - CLOCK <= '0'; - wait for CLK_PERIOD/2; - CLOCK <= '1'; - wait for CLK_PERIOD/2; -end process; - -SIMUL_RESET: process -begin - RESET <= '1'; - wait until CLOCK'event and CLOCK = '1'; - wait until CLOCK'event and CLOCK = '1'; - wait for 15 ns; - RESET <= '0'; - wait; -end process; - -SIMUL_WR_TO_R0: process -begin - BDIR <= '0'; - BC1 <= '0'; - BC2 <= '0'; - wait for 150 ns; - BDIR <= '1'; -- Latch - BC1 <= '1'; - BC2 <= '1'; - wait for 15 ns; - BDIR <= '0'; -- HIGH IMPEDANCE - BC1 <= '0'; - BC2 <= '0'; - wait for 45 ns; - BDIR <= '1'; -- write to register - BC1 <= '0'; - BC2 <= '1'; - wait for 15 ns; - BDIR <= '0'; -- HIGH IMPEDANCE - BC1 <= '0'; - BC2 <= '0'; - wait for 45 ns; - BDIR <= '1'; -- latch - BC1 <= '1'; - BC2 <= '1'; - wait for 15 ns; - BDIR <= '0'; -- High impedance - BC1 <= '0'; - BC2 <= '0'; - wait for 45 ns; - BDIR <= '1'; -- write to register - BC1 <= '0'; - BC2 <= '1'; - wait for 15 ns; - BDIR <= '0'; -- High impedance - BC1 <= '0'; - BC2 <= '0'; - wait for 45 ns; - BDIR <= '1'; -- Latch - BC1 <= '1'; - BC2 <= '1'; - wait for 15 ns; - BDIR <= '0'; -- High impedance - BC1 <= '0'; - BC2 <= '0'; - wait for 45 ns; - BDIR <= '0'; -- Read - BC1 <= '1'; - BC2 <= '1'; - wait for 15 ns; - BDIR <= '0'; -- High impedance - BC1 <= '0'; - BC2 <= '0'; - wait; - -end process; - -BUS_D : process -begin - D <= ( others => 'Z'); - wait for 150 ns; - D <= "00001110"; - wait for 30 ns; - D <= ( others => 'Z'); - wait for 30 ns; -- 195 ns - D <= "00010101"; - wait for 30 ns; -- 225 ns - D <= ( others => 'Z'); - wait for 30 ns; -- 255 ns - D <= "00000001"; - wait for 30 ns; -- 285 ns - D <= ( others => 'Z'); - wait for 30 ns; -- 315 ns - D <= "10010001"; - wait for 30 ns; -- 345 ns - D <= ( others => 'Z'); - wait for 30 ns; -- 375 ns - D <= "00001110"; - wait for 30 ns; -- 405 ns - D <= ( others => 'Z'); - wait; -end process; - -tb : PROCESS - BEGIN - wait for 1000 ns; -- will wait forever - END PROCESS; --- *** End Test Bench - User Defined Section *** - -END; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/YM2149_linmix.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/YM2149_linmix.vhd deleted file mode 100644 index a530887d..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/YM2149_linmix.vhd +++ /dev/null @@ -1,597 +0,0 @@ --- --- A simulation model of YM2149 (AY-3-8910 with bells on) - --- Copyright (c) MikeJ - Jan 2005 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 001 initial release --- --- Clues from MAME sound driver and Kazuhiro TSUJIKAWA --- --- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) --- vol 15 .. 0 --- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 --- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order --- to produced all the required values. --- (The first part of the curve is a bit steeper and the last bit is more linear than expected) --- --- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only --- accurate for designs where the outputs are buffered and not simply wired together. --- The ouput level is more complex in that case and requires a larger table. - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity YM2149 is - port ( - -- data bus - I_DA : in std_logic_vector(7 downto 0); - O_DA : out std_logic_vector(7 downto 0); - O_DA_OE_L : out std_logic; - -- control - I_A9_L : in std_logic; - I_A8 : in std_logic; - I_BDIR : in std_logic; - I_BC2 : in std_logic; - I_BC1 : in std_logic; - I_SEL_L : in std_logic; - - O_AUDIO : out std_logic_vector(7 downto 0) := (others => '0'); - -- port a --- I_IOA : in std_logic_vector(7 downto 0); --- O_IOA : out std_logic_vector(7 downto 0); --- O_IOA_OE_L : out std_logic; - -- port b --- I_IOB : in std_logic_vector(7 downto 0); --- O_IOB : out std_logic_vector(7 downto 0); --- O_IOB_OE_L : out std_logic; - - ENA : in std_logic; -- clock enable for higher speed operation - RESET_L : in std_logic; - CLK : in std_logic -- note 6 Mhz - ); -end; - -architecture RTL of YM2149 is - type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0); - type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); - - signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); - - signal noise_div : std_logic := '0'; - signal ena_div : std_logic := '0'; - signal ena_div_noise : std_logic := '0'; - signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); - - -- registers - signal addr : std_logic_vector(7 downto 0); - signal busctrl_addr : std_logic; - signal busctrl_we : std_logic; - signal busctrl_re : std_logic; - - signal reg : array_16x8 := (others => (others => '0')); - signal env_reset : std_logic := '1'; --- signal ioa_inreg : std_logic_vector(7 downto 0) := (others => '0'); --- signal iob_inreg : std_logic_vector(7 downto 0) := (others => '0'); - - signal noise_gen_cnt : std_logic_vector(4 downto 0) := (others => '0'); - signal noise_gen_op : std_logic; - signal tone_gen_cnt : array_3x12 := (others => (others => '0')); - signal tone_gen_op : std_logic_vector(3 downto 1) := (others => '0'); - - signal env_gen_cnt : std_logic_vector(15 downto 0) := (others => '0'); - signal env_ena : std_logic := '0'; - signal env_hold : std_logic := '0'; - signal env_inc : std_logic := '0'; - signal env_vol : std_logic_vector(4 downto 0) := (others => '0'); - - signal tone_ena_l : std_logic; - signal tone_src : std_logic; - signal noise_ena_l : std_logic; - signal chan_vol : std_logic_vector(4 downto 0); - - signal dac_amp : std_logic_vector(7 downto 0) := (others => '0'); - signal audio_mix : std_logic_vector(9 downto 0) := (others => '0'); - signal audio_final : std_logic_vector(9 downto 0) := (others => '0'); - -begin - -- cpu i/f - p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) - variable cs : std_logic; - variable sel : std_logic_vector(2 downto 0); - begin - -- BDIR BC2 BC1 MODE - -- 0 0 0 inactive - -- 0 0 1 address - -- 0 1 0 inactive - -- 0 1 1 read - -- 1 0 0 address - -- 1 0 1 inactive - -- 1 1 0 write - -- 1 1 1 read - busctrl_addr <= '0'; - busctrl_we <= '0'; - busctrl_re <= '0'; - - cs := '0'; - if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then - cs := '1'; - end if; - - sel := (I_BDIR & I_BC2 & I_BC1); - case sel is - when "000" => null; - when "001" => busctrl_addr <= '1'; - when "010" => null; - when "011" => busctrl_re <= cs; - when "100" => busctrl_addr <= '1'; - when "101" => null; - when "110" => busctrl_we <= cs; - when "111" => busctrl_addr <= '1'; - when others => null; - end case; - end process; - - p_oe : process(busctrl_re) - begin - -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns - O_DA_OE_L <= not (busctrl_re); - end process; - - -- - -- CLOCKED - -- - p_waddr : process(RESET_L, CLK) - begin - -- looks like registers are latches in real chip, but the address is caught at the end of the address state. - if (RESET_L = '0') then - addr <= (others => '0'); - elsif rising_edge(CLK) then - if (ENA = '1') then - if (busctrl_addr = '1') then - addr <= I_DA; - end if; - end if; - end if; - end process; - - p_wdata : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - reg <= (others => (others => '0')); - env_reset <= '1'; - elsif rising_edge(CLK) then - if (ENA = '1') then - env_reset <= '0'; - if (busctrl_we = '1') then - case addr(3 downto 0) is - when x"0" => reg(0) <= I_DA; - when x"1" => reg(1) <= I_DA; - when x"2" => reg(2) <= I_DA; - when x"3" => reg(3) <= I_DA; - when x"4" => reg(4) <= I_DA; - when x"5" => reg(5) <= I_DA; - when x"6" => reg(6) <= I_DA; - when x"7" => reg(7) <= I_DA; - when x"8" => reg(8) <= I_DA; - when x"9" => reg(9) <= I_DA; - when x"A" => reg(10) <= I_DA; - when x"B" => reg(11) <= I_DA; - when x"C" => reg(12) <= I_DA; - when x"D" => reg(13) <= I_DA; env_reset <= '1'; - when x"E" => reg(14) <= I_DA; - when x"F" => reg(15) <= I_DA; - when others => null; - end case; - end if; - end if; - end if; - end process; - - p_rdata : process(busctrl_re, addr, reg) --, ioa_inreg, iob_inreg) - begin - O_DA <= (others => '0'); -- 'X' - if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator - case addr(3 downto 0) is - when x"0" => O_DA <= reg(0) ; - when x"1" => O_DA <= reg(1); - when x"2" => O_DA <= reg(2); - when x"3" => O_DA <= reg(3); - when x"4" => O_DA <= reg(4); - when x"5" => O_DA <= reg(5); - when x"6" => O_DA <= reg(6); - when x"7" => O_DA <= reg(7); - when x"8" => O_DA <= reg(8); - when x"9" => O_DA <= reg(9); - when x"A" => O_DA <= reg(10); - when x"B" => O_DA <= reg(11); - when x"C" => O_DA <= reg(12); - when x"D" => O_DA <= reg(13); - when x"E" => - if (reg(7)(6) = '0') then -- input - O_DA <= x"00"; --ioa_inreg; - else - O_DA <= reg(14); -- read output reg - end if; - when x"F" => - if (Reg(7)(7) = '0') then - O_DA <= x"00"; --iob_inreg; - else - O_DA <= reg(15); - end if; - when others => null; - end case; - end if; - end process; - -- - p_divider : process - begin - wait until rising_edge(CLK); - -- / 8 when SEL is high and /16 when SEL is low - if (ENA = '1') then - ena_div <= '0'; - ena_div_noise <= '0'; - if (cnt_div = "0000") then - cnt_div <= (not I_SEL_L) & "111"; - ena_div <= '1'; - - noise_div <= not noise_div; - if (noise_div = '1') then - ena_div_noise <= '1'; - end if; - else - cnt_div <= cnt_div - "1"; - end if; - end if; - end process; - - p_noise_gen : process - variable noise_gen_comp : std_logic_vector(4 downto 0); - variable poly17_zero : std_logic; - begin - wait until rising_edge(CLK); - - if (reg(6)(4 downto 0) = "00000") then - noise_gen_comp := (others => '0'); - else - noise_gen_comp := (reg(6)(4 downto 0) - "1"); - end if; - - poly17_zero := '0'; - if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; - - if (ENA = '1') then - - if (ena_div_noise = '1') then -- divider ena - - if (noise_gen_cnt >= noise_gen_comp) then - noise_gen_cnt <= (others => '0'); - poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); - else - noise_gen_cnt <= (noise_gen_cnt + "1"); - end if; - end if; - end if; - end process; - noise_gen_op <= poly17(0); - - p_tone_gens : process - variable tone_gen_freq : array_3x12; - variable tone_gen_comp : array_3x12; - begin - wait until rising_edge(CLK); - - -- looks like real chips count up - we need to get the Exact behaviour .. - tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); - tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); - tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); - -- period 0 = period 1 - for i in 1 to 3 loop - if (tone_gen_freq(i) = x"000") then - tone_gen_comp(i) := (others => '0'); - else - tone_gen_comp(i) := (tone_gen_freq(i) - "1"); - end if; - end loop; - - if (ENA = '1') then - for i in 1 to 3 loop - if (ena_div = '1') then -- divider ena - - if (tone_gen_cnt(i) >= tone_gen_comp(i)) then - tone_gen_cnt(i) <= (others => '0'); - tone_gen_op(i) <= not tone_gen_op(i); - else - tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); - end if; - end if; - end loop; - end if; - end process; - - p_envelope_freq : process - variable env_gen_freq : std_logic_vector(15 downto 0); - variable env_gen_comp : std_logic_vector(15 downto 0); - begin - wait until rising_edge(CLK); - env_gen_freq := reg(12) & reg(11); - -- envelope freqs 1 and 0 are the same. - if (env_gen_freq = x"0000") then - env_gen_comp := (others => '0'); - else - env_gen_comp := (env_gen_freq - "1"); - end if; - - if (ENA = '1') then - env_ena <= '0'; - if (ena_div = '1') then -- divider ena - if (env_gen_cnt >= env_gen_comp) then - env_gen_cnt <= (others => '0'); - env_ena <= '1'; - else - env_gen_cnt <= (env_gen_cnt + "1"); - end if; - end if; - end if; - end process; - - p_envelope_shape : process - variable is_bot : boolean; - variable is_bot_p1 : boolean; - variable is_top_m1 : boolean; - variable is_top : boolean; - begin - wait until rising_edge(CLK); - - -- envelope shapes - -- C AtAlH - -- 0 0 x x \___ - -- - -- 0 1 x x /___ - -- - -- 1 0 0 0 \\\\ - -- - -- 1 0 0 1 \___ - -- - -- 1 0 1 0 \/\/ - -- ___ - -- 1 0 1 1 \ - -- - -- 1 1 0 0 //// - -- ___ - -- 1 1 0 1 / - -- - -- 1 1 1 0 /\/\ - -- - -- 1 1 1 1 /___ - - -- synchronous reset to avoid latch warning - if (env_reset = '1') then - -- load initial state - if (reg(13)(2) = '0') then -- attack - env_vol <= (others => '1'); - env_inc <= '0'; -- -1 - else - env_vol <= (others => '0'); - env_inc <= '1'; -- +1 - end if; - - env_hold <= '0'; - - else - - is_bot := (env_vol = "00000"); - is_bot_p1 := (env_vol = "00001"); - is_top_m1 := (env_vol = "11110"); - is_top := (env_vol = "11111"); - - if (ENA = '1') then - if (env_ena = '1') then - if (env_hold = '0') then - if (env_inc = '1') then - env_vol <= (env_vol + "00001"); - else - env_vol <= (env_vol + "11111"); - end if; - end if; - - -- envelope shape control. - if (reg(13)(3) = '0') then - if (env_inc = '0') then -- down - if is_bot_p1 then env_hold <= '1'; end if; - else - if is_top then env_hold <= '1'; end if; - end if; - else - if (reg(13)(0) = '1') then -- hold = 1 - if (env_inc = '0') then -- down - if (reg(13)(1) = '1') then -- alt - if is_bot then env_hold <= '1'; end if; - else - if is_bot_p1 then env_hold <= '1'; end if; - end if; - else - if (reg(13)(1) = '1') then -- alt - if is_top then env_hold <= '1'; end if; - else - if is_top_m1 then env_hold <= '1'; end if; - end if; - end if; - - elsif (reg(13)(1) = '1') then -- alternate - if (env_inc = '0') then -- down - if is_bot_p1 then env_hold <= '1'; end if; - if is_bot then env_hold <= '0'; env_inc <= '1'; end if; - else - if is_top_m1 then env_hold <= '1'; end if; - if is_top then env_hold <= '0'; env_inc <= '0'; end if; - end if; - end if; - - end if; - end if; - end if; - end if; - end process; - - p_chan_mixer : process(cnt_div, reg, tone_gen_op) - begin - tone_ena_l <= '1'; - tone_src <= '1'; - noise_ena_l <= '1'; - chan_vol <= "00000"; - case cnt_div(1 downto 0) is - when "00" => - tone_ena_l <= reg(7)(0); - tone_src <= tone_gen_op(1); - chan_vol <= reg(8)(4 downto 0); - noise_ena_l <= reg(7)(3); - when "01" => - tone_ena_l <= reg(7)(1); - tone_src <= tone_gen_op(2); - chan_vol <= reg(9)(4 downto 0); - noise_ena_l <= reg(7)(4); - when "10" => - tone_ena_l <= reg(7)(2); - tone_src <= tone_gen_op(3); - chan_vol <= reg(10)(4 downto 0); - noise_ena_l <= reg(7)(5); - when "11" => null; -- tone gen outputs become valid on this clock - when others => null; - end case; - end process; - - p_op_mixer : process - variable chan_mixed : std_logic; - variable chan_amp : std_logic_vector(4 downto 0); - begin - wait until rising_edge(CLK); - if (ENA = '1') then - - chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); - - chan_amp := (others => '0'); - if (chan_mixed = '1') then - if (chan_vol(4) = '0') then - if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet - chan_amp := (others => '0'); - else - chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) - end if; - else - chan_amp := env_vol(4 downto 0); - end if; - end if; - - dac_amp <= (others => '0'); - case chan_amp is - when "11111" => dac_amp <= x"FF"; - when "11110" => dac_amp <= x"D9"; - when "11101" => dac_amp <= x"BA"; - when "11100" => dac_amp <= x"9F"; - when "11011" => dac_amp <= x"88"; - when "11010" => dac_amp <= x"74"; - when "11001" => dac_amp <= x"63"; - when "11000" => dac_amp <= x"54"; - when "10111" => dac_amp <= x"48"; - when "10110" => dac_amp <= x"3D"; - when "10101" => dac_amp <= x"34"; - when "10100" => dac_amp <= x"2C"; - when "10011" => dac_amp <= x"25"; - when "10010" => dac_amp <= x"1F"; - when "10001" => dac_amp <= x"1A"; - when "10000" => dac_amp <= x"16"; - when "01111" => dac_amp <= x"13"; - when "01110" => dac_amp <= x"10"; - when "01101" => dac_amp <= x"0D"; - when "01100" => dac_amp <= x"0B"; - when "01011" => dac_amp <= x"09"; - when "01010" => dac_amp <= x"08"; - when "01001" => dac_amp <= x"07"; - when "01000" => dac_amp <= x"06"; - when "00111" => dac_amp <= x"05"; - when "00110" => dac_amp <= x"04"; - when "00101" => dac_amp <= x"03"; - when "00100" => dac_amp <= x"03"; - when "00011" => dac_amp <= x"02"; - when "00010" => dac_amp <= x"02"; - when "00001" => dac_amp <= x"01"; - when "00000" => dac_amp <= x"00"; - when others => null; - end case; - - if (cnt_div(1 downto 0) = "10") then - audio_mix <= (others => '0'); - audio_final <= audio_mix; - else - audio_mix <= audio_mix + ("00" & dac_amp); - end if; - end if; - end process; - - p_audio_output : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - O_AUDIO <= (others => '0'); - elsif rising_edge(CLK) then - if (ENA = '1') then - O_AUDIO <= audio_final(9 downto 2); - end if; - end if; - end process; - --- p_io_ports : process(reg) --- begin --- O_IOA <= reg(14); - --- O_IOA_OE_L <= not reg(7)(6); --- O_IOB <= reg(15); --- O_IOB_OE_L <= not reg(7)(7); --- end process; - --- p_io_ports_inreg : process --- begin --- wait until rising_edge(CLK); --- if (ENA = '1') then -- resync --- ioa_inreg <= I_IOA; --- iob_inreg <= I_IOB; --- end if; --- end process; -end architecture RTL; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/addmemux.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/addmemux.vhd deleted file mode 100644 index ea6acb53..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/addmemux.vhd +++ /dev/null @@ -1,87 +0,0 @@ --- --- addmenux.vhd --- --- Manage bus address multiplexer --- --- Copyright (C)2001 - 2005 SEILEBOST --- All rights reserved. --- --- $Id: addmenux.vhd, v0.10 2009/06/25 00:00:00 SEILEBOST $ --- MODIFICATION : --- v0.01 : 200X/??/?? --- v0.10 : 2009/06/25 : Intégration de la partie multiplexage de l'accès ram --- TODO : --- --- TODO : --- Remark : - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_STD.all; ---use IEEE.std_logic_unsigned.all; - -entity addmemux is -port ( RESETn : in std_logic; - VAP1 : in std_logic_vector(15 downto 0);-- Video address phase 1 - VAP2 : in std_logic_vector(15 downto 0);-- Video address phase 2 - BAP : in std_logic_vector(15 downto 0);-- Bus address processor (A15-A0) - VA1L : in std_logic; -- Video address phase 1 LATCH - VA1R : in std_logic; -- Video address phase 1 ROW - VA1C : in std_logic; -- Video address phase 1 COLUMN - VA2L : in std_logic; -- Video address phase 2 LATCH - VA2R : in std_logic; -- Video address phase 2 ROW - VA2C : in std_logic; -- Video address phase 2 COLUMN - BAC : in std_logic; -- Bus address COLUMN - BAL : in std_logic; -- Bus address LATCH - AD_DYN : out std_logic_vector(15 downto 0) -- Address Bus dynamic - ); -end entity addmemux; - -architecture addmemux_arch of addmemux is - -signal lVAP1 : std_logic_vector(15 downto 0); -signal lVAP2 : std_logic_vector(15 downto 0); -signal lBAP : std_logic_vector(15 downto 0); - -begin - --- Latch VAP1 -u_VAP1 : PROCESS ( VAP1, VA1L,resetn ) -begin - if (resetn = '0') then - lVAP1 <= (OTHERS => '0'); - elsif rising_edge(VA1L) then - lVAP1 <= VAP1; - end if; -end process; - --- Latch VAP2 -u_VAP2 : PROCESS ( VAP2, VA2L, resetn ) -begin - if (resetn = '0') then - lVAP2 <= (OTHERS => '0'); - elsif rising_edge(VA2L) then - lVAP2 <= VAP2; - end if; -end process; - --- Latch BAP -u_BAP: PROCESS ( BAP, BAL, resetn ) -begin - if (resetn = '0') then - lBAP<= (OTHERS => '0'); - elsif rising_edge(BAL) then - lBAP<= BAP; - end if; -end process; - --- Assignation - - AD_DYN <= lVAP1(15 downto 0) when VA1R = '1' else - -- lVAP1(7 downto 0) when VA1C = '1' else - lVAP2(15 downto 0) when VA2R = '1' else - -- lVAP2(7 downto 0) when VA2C = '1' else - -- lBAP when BAL = '1' else - -- (OTHERS => 'Z'); - lBAP; -end architecture addmemux_arch; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ay3819x.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/ay3819x.vhd deleted file mode 100644 index c6baa5f8..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ay3819x.vhd +++ /dev/null @@ -1,435 +0,0 @@ --- --- A simulation model of PSG hardware --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: passionoric.free.fr --- --- Email seilebost@free.fr --- --- --- Revision list --- --- v0.42 2002/01/03 : It seems ok --- v0.43 2009/01/21 : bus bidirectionnel => bus unidirectionnel --- v0.44 2009/10/11 : Reset asynchrone pour le process U_TRAIT --- v0.45 2010/01/03 : Ajout d'une horloge pour le DAC --- v0.46 2010/01/06 : Modification du générateur de fréquence --- pour ajouter la division par 16 et par 256 --- v0.50 2010/01/19 : Reorganisation du code --- --- AY3819X.vhd --- --- Top entity of AY3819X. --- --- Copyright (C)2001-2010 SEILEBOST --- All rights reserved. --- --- $Id: AY3819.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $ --- --- TODO : --- Many verification !! --- Remark : - -library IEEE; -library UNISIM; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_STD.all; -use IEEE.STD_LOGIC_UNSIGNED.ALL; ---use UNISIM.Vcomponents.ALL; -- for IOBUF and OBUF - -entity AY3819X is - Port ( DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - O_DATA_OE_L : out std_logic; - RESET : in std_logic; - CLOCK : in std_logic; - CLOCK_DAC : in std_logic; -- 24 MHz pour le DAC - BDIR : in std_logic; - BC1 : in std_logic; - BC2 : in std_logic; - IOA : inout std_logic_vector(7 downto 0); - IOB : inout std_logic_vector(7 downto 0); - AnalogA : out std_logic; - AnalogB : out std_logic; - AnalogC : out std_logic ); -end AY3819X; - - -architecture Behavioral of AY3819X is - - SIGNAL BUS_CS : std_logic_vector(15 downto 0); -- Select the different module when Read / Write Register - - -- Create register - SIGNAL R0 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel A - SIGNAL R1 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel A - SIGNAL R2 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel B - SIGNAL R3 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel B - SIGNAL R4 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel C - SIGNAL R5 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel B - SIGNAL R6 : std_logic_vector(7 downto 0); -- Noise generator frequency - SIGNAL R7 : std_logic_vector(7 downto 0); -- Mixer Control I/O Enable - SIGNAL R8 : std_logic_vector(7 downto 0); -- Amplitude control channel A - SIGNAL R9 : std_logic_vector(7 downto 0); -- Amplitude control channel B - SIGNAL R10 : std_logic_vector(7 downto 0); -- Amplitude control channel C - SIGNAL R11 : std_logic_vector(7 downto 0); -- Envelope period control fine tune - SIGNAL R12 : std_logic_vector(7 downto 0); -- Envelope period control coarse tune - SIGNAL R13 : std_logic_vector(7 downto 0); -- Envelope shape/cycle control - - SIGNAL REG_ADDR : std_logic_vector(3 downto 0); -- Keep the number of register addressed - - SIGNAL WR : std_logic; -- WRITE (FLAG) - - SIGNAL CLK_A : std_logic; -- CLOCK TONE VOICE A - SIGNAL CLK_B : std_logic; -- CLOCK TONE VOICE B - SIGNAL CLK_C : std_logic; -- CLOCK TONE VOICE C - SIGNAL CLK_TONE_A : std_logic; -- CLOCK TONE VOICE A +/- CLOCK NOISE - SIGNAL CLK_TONE_B : std_logic; -- CLOCK TONE VOICE B +/- CLOCK NOISE - SIGNAL CLK_TONE_C : std_logic; -- CLOCK TONE VOICE C +/- CLOCK NOISE - SIGNAL CLK_E : std_logic; -- CLOCK Envelope Generator - SIGNAL CLK_N : std_logic; -- CLOCK FROM NOISE GENERATOR - SIGNAL CLK_16 : std_logic; -- CLOCK (=1 MHz) / 16 pour le "tone" - SIGNAL CLK_256 : std_logic; -- CLOCK (=1 MHz) / 256 pour l'enveloppe - - SIGNAL OUT_AMPL_E : std_logic_vector(3 downto 0); -- Amplitude of signal from Envelope generator - - SIGNAL IAnalogA : std_logic; -- FOR IOPAD, exit from DAC VOICE A - SIGNAL IAnalogB : std_logic; -- FOR IOPAD, exit from DAC VOICE B - SIGNAL IAnalogC : std_logic; -- FOR IOPAD, exit from DAC VOICE C - - SIGNAL RST_ENV : std_logic; -- FOR RESET THE VALUE OF ENVELOPPE - - COMPONENT TONE_GENERATOR PORT ( CLK : in std_logic; - --CLK_TONE : in std_logic; - RST : in std_logic; - WR : in std_logic; - --CS_COARSE : in std_logic; - --CS_FINE : in std_logic; - DATA_COARSE : in std_logic_vector(7 downto 0); - DATA_FINE : in std_logic_vector(7 downto 0); - OUT_TONE : inout std_logic ); - END COMPONENT; - - COMPONENT NOISE_GENERATOR PORT ( CLK : in std_logic; - RST : in std_logic; - --WR : in std_logic; - --CS : in std_logic; - DATA : in std_logic_vector(4 downto 0); - CLK_N : out std_logic ); - END COMPONENT; - - COMPONENT GEN_CLK PORT ( CLK : in std_logic; - RST : in std_logic; - CLK_16 : out std_logic; - CLK_256 : out std_logic); - END COMPONENT; - --- COMPONENT MIXER PORT ( CLK : in std_logic; - -- CS : in std_logic; - -- RST : in std_logic; - -- WR : in std_logic; - -- IN_A : in std_logic; - -- IN_B : in std_logic; - -- IN_C : in std_logic; - -- IN_NOISE : in std_logic; - -- DATA : in std_logic_vector(5 downto 0); - -- OUT_A : out std_logic; - -- OUT_B : out std_logic; - -- OUT_C : out std_logic ); - --END COMPONENT; - - COMPONENT GEN_ENV PORT ( CLK_ENV : in std_logic; - DATA : in std_logic_vector(3 downto 0); - RST_ENV : in std_logic; - WR : in std_logic; - --CS : in std_logic; - OUT_DATA : inout std_logic_vector(3 downto 0)); - END COMPONENT; - - COMPONENT MANAGE_AMPLITUDE PORT ( CLK : in std_logic; - CLK_DAC : in std_logic; - CLK_TONE : in std_logic; - CLK_NOISE : in std_logic; - RST : in std_logic; - CLK_TONE_ENA : in std_logic; - CLK_NOISE_ENA : in std_logic; - AMPLITUDE : in std_logic_vector(4 downto 0); - AMPLITUDE_E : in std_logic_vector(3 downto 0); - OUT_DAC : out std_logic ); - END COMPONENT; - - --COMPONENT IOBUF_F_12 port ( O : out std_logic; - -- IO : inout std_logic; - -- I : in std_logic; - -- T : in std_logic ); - --END COMPONENT; - - --COMPONENT OBUF_F_12 port ( O : out std_logic; - -- IO : inout std_logic; - -- I : in std_logic; - -- T : in std_logic ); - --END COMPONENT; - - --component OBUF_F_24 - --port ( - -- I : in std_logic; - -- O : out std_logic ); - --end component; - -BEGIN - -U_TRAIT : PROCESS(CLOCK, RESET, BC1, BC2, BDIR, REG_ADDR, DATA_IN) -BEGIN - - if (RESET = '1') then - WR <= '0'; - R0 <= "00000000"; - R1 <= "00000000"; - R2 <= "00000000"; - R3 <= "00000000"; - R4 <= "00000000"; - R5 <= "00000000"; - R6 <= "00000000"; - R7 <= "00000000"; - R8 <= "00000000"; - R9 <= "00000000"; - R10 <= "00000000"; - R11 <= "00000000"; - R12 <= "00000000"; - R13 <= "00000000"; - IOA <= "00000000"; - IOB <= "00000000"; - DATA_OUT <= "00000000"; - RST_ENV <= '1'; - else - if rising_edge(CLOCK) then -- edge clock - -- READ FROM REGISTER - RST_ENV <= '0'; - if ((BDIR = '0') and (BC2 = '1') and (BC1 = '1')) then - CASE REG_ADDR is - WHEN "0000" => DATA_OUT <= R0; - WHEN "0001" => DATA_OUT <= R1; - WHEN "0010" => DATA_OUT <= R2; - WHEN "0011" => DATA_OUT <= R3; - WHEN "0100" => DATA_OUT <= R4; - WHEN "0101" => DATA_OUT <= R5; - WHEN "0110" => DATA_OUT <= R6; - WHEN "0111" => DATA_OUT <= R7; - WHEN "1000" => DATA_OUT <= R8; - WHEN "1001" => DATA_OUT <= R9; - WHEN "1010" => DATA_OUT <= R10; - WHEN "1011" => DATA_OUT <= R11; - WHEN "1100" => DATA_OUT <= R12; - WHEN "1101" => DATA_OUT <= R13; - WHEN "1110" => DATA_OUT <= IOA; - WHEN "1111" => DATA_OUT <= IOB; - WHEN OTHERS => NULL; - END CASE; - WR <= '0'; - else - DATA_OUT <= "00000000"; - WR <= '0'; - end if; - end if; - end if; - - -- LATCH WHAT REGISTER - if ((BDIR = '1') and (BC2 = '1') and (BC1 = '1')) then - REG_ADDR <= DATA_IN(3 downto 0); - WR <= '0'; - end if; - - -- WRITE TO REGISTER OR IOA/IOB - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0')) then WR <= '1'; end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0000") ) then R0 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0001") ) then R1 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0010") ) then R2 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0011") ) then R3 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0100") ) then R4 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0101") ) then R5 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0110") ) then R6 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0111") ) then R7 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1000") ) then R8 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1001") ) then R9 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1010") ) then R10 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1011") ) then R11 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1100") ) then R12 <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1101") ) then R13 <= DATA_IN; RST_ENV <= '1'; end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1110") ) then IOA <= DATA_IN;end if; - if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1111") ) then IOB <= DATA_IN;end if; - -end PROCESS; - -URA: PROCESS(REG_ADDR, RESET) -BEGIN - if (RESET = '1') then - BUS_CS <= "0000000000000000"; - else - case REG_ADDR is - when "0000" => BUS_CS <= "0000000000000001"; - when "0001" => BUS_CS <= "0000000000000010"; - when "0010" => BUS_CS <= "0000000000000100"; - when "0011" => BUS_CS <= "0000000000001000"; - when "0100" => BUS_CS <= "0000000000010000"; - when "0101" => BUS_CS <= "0000000000100000"; - when "0110" => BUS_CS <= "0000000001000000"; - when "0111" => BUS_CS <= "0000000010000000"; - when "1000" => BUS_CS <= "0000000100000000"; - when "1001" => BUS_CS <= "0000001000000000"; - when "1010" => BUS_CS <= "0000010000000000"; - when "1011" => BUS_CS <= "0000100000000000"; - when "1100" => BUS_CS <= "0001000000000000"; - when "1101" => BUS_CS <= "0010000000000000"; - when "1110" => BUS_CS <= "0100000000000000"; - when "1111" => BUS_CS <= "1000000000000000"; - when others => NULL; - end case; - end if; -END PROCESS; - - --- Instantiation of sub_level modules -UCLK : GEN_CLK PORT MAP( CLK => CLOCK, - RST => RESET, - CLK_16 => CLK_16, - CLK_256 => CLK_256 - ); - -UTONE_A : TONE_GENERATOR PORT MAP( CLK => CLOCK, - --CLK_TONE => CLK_16, - RST => RESET, - WR => WR, - --CS_COARSE => BUS_CS(1), - --CS_FINE => BUS_CS(0), - DATA_COARSE => R1, - DATA_FINE => R0, - OUT_TONE => CLK_A); - -UTONE_B : TONE_GENERATOR PORT MAP( CLK => CLOCK, - --CLK_TONE => CLK_16, - RST => RESET, - WR => WR, - --CS_COARSE => BUS_CS(3), - --CS_FINE => BUS_CS(2), - DATA_COARSE => R3, - DATA_FINE => R2, - OUT_TONE => CLK_B); - -UTONE_C : TONE_GENERATOR PORT MAP( CLK => CLOCK, - --CLK_TONE => CLK_16, - RST => RESET, - WR => WR, - --CS_COARSE => BUS_CS(5), - --CS_FINE => BUS_CS(4), - DATA_COARSE => R5, - DATA_FINE => R4, - OUT_TONE => CLK_C); - -UTONE_NOISE : NOISE_GENERATOR PORT MAP( CLK => CLK_16, - RST => RESET, - --WR => WR, - --CS => BUS_CS(6), - DATA => R6(4 downto 0), - CLK_N => CLK_N); - -UTONE_ENV : TONE_GENERATOR PORT MAP( CLK => CLK_16, - --CLK => CLOCK, - --CLK_TONE => CLK_256, - RST => RESET, - WR => WR, - --CS_COARSE => BUS_CS(12), - --CS_FINE => BUS_CS(11), - DATA_COARSE => R12, - DATA_FINE => R11, - OUT_TONE => CLK_E); - ---UMIXER : MIXER PORT MAP ( CLK => CLOCK, --- CS => BUS_CS(7), --- RST => RESET, --- WR => WR, --- IN_A => CLK_A, --- IN_B => CLK_B, --- IN_C => CLK_C, --- IN_NOISE => CLK_N, --- DATA => R7(5 downto 0), --- OUT_A => CLK_TONE_A, --- OUT_B => CLK_TONE_B, --- OUT_C => CLK_TONE_C); - -UGenEnv : GEN_ENV PORT MAP( CLK_ENV => CLK_E, - --CS => BUS_CS(13), - DATA => R13(3 downto 0), - RST_ENV => RST_ENV, - WR => WR, - OUT_DATA => OUT_AMPL_E); - -UManAmpA : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK, - CLK_DAC => CLOCK_DAC, - CLK_TONE => CLK_A, --CLK_TONE_A, - CLK_NOISE => CLK_N, - RST => RESET, - CLK_TONE_ENA => R7(0), - CLK_NOISE_ENA => R7(3), - AMPLITUDE => R8(4 downto 0), - AMPLITUDE_E => OUT_AMPL_E(3 downto 0), - OUT_DAC => IAnalogA ); - -UManAmpB : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK, - CLK_DAC => CLOCK_DAC, - CLK_TONE => CLK_B, --CLK_TONE_B, - CLK_NOISE => CLK_N, - RST => RESET, - CLK_TONE_ENA => R7(1), - CLK_NOISE_ENA => R7(4), - AMPLITUDE => R9(4 downto 0), - AMPLITUDE_E => OUT_AMPL_E(3 downto 0), - OUT_DAC => IAnalogB ); - -UManAmpC : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK, - CLK_DAC => CLOCK_DAC, - CLK_TONE => CLK_C, --CLK_TONE_C, - CLK_NOISE => CLK_N, - RST => RESET, - CLK_TONE_ENA => R7(2), - CLK_NOISE_ENA => R7(5), - AMPLITUDE => R10(4 downto 0), - AMPLITUDE_E => OUT_AMPL_E(3 downto 0), - OUT_DAC => IAnalogC ); - - ---PAD_ANALOGA : OBUF_F_24 port map( I => IAnalogA, O => AnalogA); ---PAD_ANALOGB : OBUF_F_24 port map( I => IAnalogB, O => AnalogB); ---PAD_ANALOGC : OBUF_F_24 port map( I => IAnalogC, O => AnalogC); -AnalogA <= IAnalogA; -AnalogB <= IAnalogB; -AnalogC <= IAnalogC; - -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/build_id.tcl b/Computer_MiST/Oric Atmos_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/build_id.v b/Computer_MiST/Oric Atmos_MiST/rtl/build_id.v deleted file mode 100644 index 23bf7247..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/build_id.v +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "180624" -`define BUILD_TIME "130024" diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ctrlseq.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/ctrlseq.vhd deleted file mode 100644 index 91ececfc..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ctrlseq.vhd +++ /dev/null @@ -1,321 +0,0 @@ --- --- ctrlseq.vhd --- --- Manage internal register --- --- Copyright (C)2001 - 2005 SEILEBOST --- All rights reserved. --- --- $Id: ctrlseq.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $ --- --- TODO : --- Remark : - - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; ---use IEEE.std_logic_arith.all; ---use IEEE.numeric_std.all; - -entity ctrlseq is -port ( RESETn : in std_logic; -- RESET - CLK_24 : in std_logic; -- 2 x CLOCK SYSTEM - TXTHIR_DEC : in std_logic; -- TeXT HIRes DECode signal - isAttrib : in std_logic; -- Is a attribute byte - iRW : in std_logic; -- Read/Write signal from CPU - CSRAMn : in std_logic; -- SELECT RAM (Active low) - -- OUTPUTS - CLK_1_CPU : out std_logic; -- CLK for CPU - CLK_4 : out std_logic; -- CLK internal for VIA - CLK_6 : out std_logic; -- CLK internal for video generation - VA1L : out std_logic; -- VIDEO ADDRESS PHASE1 LATCH - VA1R : out std_logic; -- VIDEO ADDRESS PHASE1 ROW - VA1C : out std_logic; -- VIDEO ADDRESS PHASE1 COLUMN - VA2L : out std_logic; -- VIDEO ADDRESS PHASE2 LATCH - VA2R : out std_logic; -- VIDEO ADDRESS PHASE2 ROW - VA2C : out std_logic; -- VIDEO ADDRESS PHASE2 COLUMN - BAC : out std_logic; -- BUS ADDRESS COLUMN - BAL : out std_logic; -- BUS ADDRESS LATCH - RAS : out std_logic; -- RAS FOR DYNAMIC RAM - CAS : out std_logic; -- CAS FOR DYNAMIC RAM - MUX : out std_logic; -- MUX - oRW : out std_logic; -- Output Read/Write - ATTRIB_DEC : out std_logic; -- Decode attribute - LD_REG_0 : out std_logic; -- Initialization of video register - LD_REG : out std_logic; -- Load data into video register - LDFROMBUS : out std_logic; -- Load data from data bus - DATABUS_EN : out std_logic; -- Enable data bus --- ajout du 09/02/09 - BAOE : out std_logic; -- Output enable for ram/rom --- ajout du 03/04/09 - SRAM_CE : out std_logic; -- Chip select enable for SRAM - SRAM_OE : out std_logic; -- Ouput enable for SRAM - SRAM_WE : out std_logic; -- Write enable for SRAM =1 for a read cycle - LATCH_SRAM : out std_logic; -- Latch data from SRAM for cpu --- FOR DEBUG/TESTBENCH - c0_out : out std_logic; - c1_out : out std_logic; - c2_out : out std_logic; - c3_out : out std_logic; - c4_out : out std_logic; - c5_out : out std_logic; - c6_out : out std_logic; - c7_out : out std_logic; - CLK_12 : out std_logic; - TB_CPT : out std_logic_vector(4 downto 0) - ); -end entity ctrlseq; - -architecture ctrlseq_arch of ctrlseq is - -signal lCPT_GEN : std_logic_vector(4 downto 0); -- counter -signal lstate : std_logic_vector(23 downto 0); -- states -signal lreload : std_logic; -- to reload null value to lCPT_GEN -signal lld_reg_p : std_logic; -- to load value into register for VIDEO - -signal c_ras : std_logic; -- RAS -signal c_cas : std_logic; -- CAS -signal c_mux : std_logic; -- MUX -signal c_clk_cpu : std_logic; -- CLK_CPU - --- Phase P0 -signal c_0 : std_logic; -- state number 0 -signal c_1 : std_logic; -- state number 1 -signal c_2 : std_logic; -- state number 2 -signal c_3 : std_logic; -- state number 3 -signal c_4 : std_logic; -- state number 4 -signal c_5 : std_logic; -- state number 5 -signal c_6 : std_logic; -- state number 6 -signal c_7 : std_logic; -- state number 7 --- Phase P1 -signal c_8 : std_logic; -- state number 8 -signal c_9 : std_logic; -- state number 9 -signal c_10 : std_logic; -- state number 10 -signal c_11 : std_logic; -- state number 11 -signal c_12 : std_logic; -- state number 12 -signal c_13 : std_logic; -- state number 13 -signal c_14 : std_logic; -- state number 14 -signal c_15 : std_logic; -- state number 15 --- Phase P2 -signal c_16 : std_logic; -- state number 16 -signal c_17 : std_logic; -- state number 17 -signal c_18 : std_logic; -- state number 18 -signal c_19 : std_logic; -- state number 19 -signal c_20 : std_logic; -- state number 20 -signal c_21 : std_logic; -- state number 21 -signal c_22 : std_logic; -- state number 22 -signal c_23 : std_logic; -- state number 23 - -signal p_0 : std_logic; -- phase number 0 -signal p_1 : std_logic; -- phase number 1 -signal p_2 : std_logic; -- phase number 2 - --- Constants for states --- Phase P0 -constant cd_step_0 : integer :=0; -constant cd_step_1 : integer :=1; -constant cd_step_2 : integer :=2; -constant cd_step_3 : integer :=3; -constant cd_step_4 : integer :=4; -constant cd_step_5 : integer :=5; -constant cd_step_6 : integer :=6; -constant cd_step_7 : integer :=7; --- Phase P1 -constant cd_step_8 : integer :=8; -constant cd_step_9 : integer :=9; -constant cd_step_10: integer :=10; -constant cd_step_11: integer :=11; -constant cd_step_12: integer :=12; -constant cd_step_13: integer :=13; -constant cd_step_14: integer :=14; -constant cd_step_15: integer :=15; --- Phase P2 -constant cd_step_16: integer :=16; -constant cd_step_17: integer :=17; -constant cd_step_18: integer :=18; -constant cd_step_19: integer :=19; -constant cd_step_20: integer :=20; -constant cd_step_21: integer :=21; -constant cd_step_22: integer :=22; -constant cd_step_23: integer :=23; - -begin - --- Increment counter -U_TB_CPT: PROCESS (RESETn, CLK_24) -BEGIN - if (RESETn = '0') then - lCPT_GEN <= "00000"; - elsif falling_edge(clk_24) then - if (lreload = '1') then - lCPT_GEN <= "00000"; - else - lCPT_GEN <= lCPT_GEN + "00001"; - end if; - end if; -END PROCESS; -lreload <= '1' when lCPT_GEN = "10111" else '0'; - --- Manage states -U_SM_GEST: PROCESS(lCPT_GEN) -BEGIN - lstate <= "000000000000000000000000"; - case lCPT_GEN(4 downto 0) is - -- Phase P0 - when "00000" => lstate(cd_step_0) <= '1'; - when "00001" => lstate(cd_step_1) <= '1'; - when "00010" => lstate(cd_step_2) <= '1'; - when "00011" => lstate(cd_step_3) <= '1'; - when "00100" => lstate(cd_step_4) <= '1'; - when "00101" => lstate(cd_step_5) <= '1'; - when "00110" => lstate(cd_step_6) <= '1'; - when "00111" => lstate(cd_step_7) <= '1'; - -- Phase P1 - when "01000" => lstate(cd_step_8) <= '1'; - when "01001" => lstate(cd_step_9) <= '1'; - when "01010" => lstate(cd_step_10) <= '1'; - when "01011" => lstate(cd_step_11) <= '1'; - when "01100" => lstate(cd_step_12) <= '1'; - when "01101" => lstate(cd_step_13) <= '1'; - when "01110" => lstate(cd_step_14) <= '1'; - when "01111" => lstate(cd_step_15) <= '1'; - -- Phase P2 - when "10000" => lstate(cd_step_16) <= '1'; - when "10001" => lstate(cd_step_17) <= '1'; - when "10010" => lstate(cd_step_18) <= '1'; - when "10011" => lstate(cd_step_19) <= '1'; - when "10100" => lstate(cd_step_20) <= '1'; - when "10101" => lstate(cd_step_21) <= '1'; - when "10110" => lstate(cd_step_22) <= '1'; - when "10111" => lstate(cd_step_23) <= '1'; - when others => null; - end case; -END PROCESS; - --- Assign states --- Phase P0 -c_0 <= lstate(cd_step_0); -c_1 <= lstate(cd_step_1); -c_2 <= lstate(cd_step_2); -c_3 <= lstate(cd_step_3); -c_4 <= lstate(cd_step_4); -c_5 <= lstate(cd_step_5); -c_6 <= lstate(cd_step_6); -c_7 <= lstate(cd_step_7); --- Phase P1 -c_8 <= lstate(cd_step_8); -c_9 <= lstate(cd_step_9); -c_10 <= lstate(cd_step_10); -c_11 <= lstate(cd_step_11); -c_12 <= lstate(cd_step_12); -c_13 <= lstate(cd_step_13); -c_14 <= lstate(cd_step_14); -c_15 <= lstate(cd_step_15); --- Phase P2 -c_16 <= lstate(cd_step_16); -c_17 <= lstate(cd_step_17); -c_18 <= lstate(cd_step_18); -c_19 <= lstate(cd_step_19); -c_20 <= lstate(cd_step_20); -c_21 <= lstate(cd_step_21); -c_22 <= lstate(cd_step_22); -c_23 <= lstate(cd_step_23); - --- Three phases -p_0 <= NOT lCPT_GEN(4) and NOT lCPT_GEN(3); -- 00 -p_1 <= NOT lCPT_GEN(4) and lCPT_GEN(3); -- 01 -p_2 <= lCPT_GEN(4) and NOT lCPT_GEN(3); -- 10 - --------------------------------- --- GENERATION DE LA CLOCK CPU -- --------------------------------- -CLK_1_CPU <= p_2; - ---------------------------------- --- GESTION DE LA RAM DYNAMIQUE -- ---------------------------------- -ras <= c_2 or c_3 or c_4 or c_5 or c_10 or c_11 or c_12 or c_13 or c_18 or c_19 or c_20 or c_20; -cas <= not (c_2 or c_3) and not (c_10 or c_11) and not (c_18 or c_19); --- Mux permet de slectionner soit l'adresse haute d'une adresse cpu --- soit l'adresse haute d'une adresse ula -mux <= '1' when ((c_1 = '1' or c_2 = '1') and p_2 = '1') else '0'; -oRW <= iRW and p_2; - ---------------------------------- --- GESTION DE LA RAM STATIQUE -- ---------------------------------- -SRAM_OE <= not (c_2 or c_3) and not (c_10 or c_11) and not iRW ; -SRAM_CE <= not (c_1 or c_2 or c_3 or c_4) and not (c_9 or c_10 or c_11 or c_12) AND (CSRAMn or not (c_19 or c_20)); -SRAM_WE <= CSRAMn or not (c_19 or c_20) or irW; -LATCH_SRAM <= not c_4 and not c_12 and not c_20; -- le 19/12/2011 : Ajout not c_4 and c_12 à not c_20 - ---------------------- --- GESTION INTERNE -- ---------------------- - ---Generation pour la gestion de l'adresse video 1 -VA1L <= '1' when (c_1='1') ELSE '0'; ---VA1R <= '1' when (c_1='1' or c_2='1') ELSE '0'; -VA1R <= '1' when (p_0='1') ELSE '0'; -VA1C <= '1' when (c_3='1' or c_4='1' or c_5='1') ELSE '0'; - ---Generation pour la gestion de l'adresse video 2 -VA2L <= '1' when (c_8='1') ELSE '0'; ---VA2R <= '1' when (c_8='1' or c_9='1') ELSE '0'; -VA2R <= '1' when (p_1='1') ELSE '0'; -VA2C <= '1' when (c_10='1' or c_11='1' or c_12='1') ELSE '0'; - ---Generation pour la gestion de l'adresse CPU -BAL <= '1' when (c_17='1' or c_18='1' or c_19='1' or c_20='1' or c_21='1' or c_22='1' or c_23='1') ELSE '0'; ---Modif. du 22/02/09 BAC <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_2='1' and CSRAMn='0') ELSE '0'; -BAC <= '1' when (c_19='1' or c_20='1' or c_21='1') ELSE '0'; --- Ajout du 09/02/09 : output enable pour la rom/ram lors de l'adressage par le CPU -BAOE <= '1' when (c_18='1') ELSE '0'; - ---Pour la partie video --- 27/07/09 lld_reg_p <= NOT isAttrib and c_7 and NOT TXTHIR_DEC; --- 27/07/09 c_7 aurait du tre c_15 en ram dynamique --- 27/07/09 en ram statique : --- 11/11/09 Modif c_10 en c_11 -lld_reg_p <= not isAttrib and c_11 and NOT TXTHIR_DEC; -- Partie texte - --- 04/12/09 ATTRIB_DEC <= '1' when (isAttrib='1' and c_10='1') ELSE '0'; ---ATTRIB_DEC <= '1' when (c_4='1') ELSE '0'; --- 04/12/09 LD_REG_0 <= '1' when (isAttrib='1' and c_15='1') ELSE '0'; ---LD_REG_0 <= '1' when (isAttrib='1' and c_11='1' and TXTHIR_DEC = '0') ELSE '0'; --- 05/12/09 LD_REG <= '1' when (lld_reg_p='1' or c_4='1') ELSE '0'; ---LD_REG <= '1' when (lld_reg_p='1' or (c_4='1' and TXTHIR_DEC = '0')) ELSE '0'; ---DATABUS_EN <= '1' when (lld_reg_p='1' or c_3='1') ELSE '0'; ---LDFROMBUS <= '1' when (c_16='1') ELSE '0'; - --- 15/12/2009 : -ATTRIB_DEC <= '1' when (c_4='1') ELSE '0'; -DATABUS_EN <= '1' when (c_11='1' or c_3='1') ELSE '0'; -LD_REG_0 <= '1' when (isAttrib='1' and c_5='1') ELSE '0'; -LDFROMBUS <= '1' when ( (isAttrib='0' and c_12='1' and TXTHIR_DEC='0') - or (isAttrib='0' and c_5 ='1' and TXTHIR_DEC='1') - ) ELSE '0'; -LD_REG <= '1' when (c_15='1') ELSE '0'; - --- for TEST BENCH -c0_OUT <= lstate(cd_step_0); -c1_OUT <= lstate(cd_step_1); -c2_OUT <= lstate(cd_step_2); -c3_OUT <= lstate(cd_step_3); -c4_OUT <= lstate(cd_step_4); -c5_OUT <= lstate(cd_step_5); -c6_OUT <= lstate(cd_step_6); -c7_OUT <= lstate(cd_step_7); -TB_CPT <= lCPT_GEN; -CLK_12 <= lCPT_GEN(0); - --- for VIA 6522 -CLK_4 <= c_0 or c_1 or c_2 - or c_6 or c_7 or c_8 - or c_12 or c_13 or c_14 - or c_18 or c_19 or c_20; - --- for Video Generation -CLK_6 <= c_0 or c_1 or c_4 or c_5 or c_8 or c_9 or c_12 or c_13 or c_16 or c_17 or c_20 or c_21; -end architecture ctrlseq_arch; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ctrlseq_orig.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/ctrlseq_orig.vhd deleted file mode 100644 index add6b8c3..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ctrlseq_orig.vhd +++ /dev/null @@ -1,207 +0,0 @@ --- --- ctrlseq.vhd --- --- Manage internal register --- --- Copyright (C)2001 - 2005 SEILEBOST --- All rights reserved. --- --- $Id: ctrlseq.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $ --- --- TODO : --- Remark : - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; ---use IEEE.std_logic_arith.all; ---use IEEE.numeric_std.all; - -entity ctrlseq is -port ( RESETn : in std_logic; -- RESET - CLK_24 : in std_logic; -- 2 x CLOCK SYSTEM - TXTHIR_DEC : in std_logic; -- TeXT HIRes DECode signal - isAttrib : in std_logic; -- Is a attribute byte - iRW : in std_logic; -- Read/Write signal from CPU - CSRAMn : in std_logic; -- SELECT RAM (Active low) - -- OUTPUTS - CLK_1_CPU : out std_logic; -- CLK for CPU - CLK_4 : out std_logic; -- CLK interne for ram statique - VA1L : out std_logic; -- VIDEO ADDRESS PHASE1 LATCH - VA1R : out std_logic; -- VIDEO ADDRESS PHASE1 ROW - VA1C : out std_logic; -- VIDEO ADDRESS PHASE1 COLUMN - VA2L : out std_logic; -- VIDEO ADDRESS PHASE2 LATCH - VA2R : out std_logic; -- VIDEO ADDRESS PHASE2 ROW - VA2C : out std_logic; -- VIDEO ADDRESS PHASE2 COLUMN - BAC : out std_logic; -- BUS ADDRESS COLUMN - BAL : out std_logic; -- BUS ADDRESS LATCH - RAS : out std_logic; -- RAS FOR DYNAMIC RAM - CAS : out std_logic; -- CAS FOR DYNAMIC RAM - MUX : out std_logic; -- MUX - oRW : out std_logic; -- Output Read/Write - ATTRIB_DEC : out std_logic; -- Decode attribute - LD_REG_0 : out std_logic; -- Initialization of video register - LD_REG : out std_logic; -- Load data into video register - LDFROMBUS : out std_logic; -- Load data from data bus - DATABUS_EN : out std_logic; -- Enable data bus - -- ajout du 09/02/09 - BAOE : out std_logic; -- Output enable for ram/rom --- FOR DEBUG/TESTBENCH - c0_out : out std_logic; - c1_out : out std_logic; - c2_out : out std_logic; - c3_out : out std_logic; - c4_out : out std_logic; - c5_out : out std_logic; - c6_out : out std_logic; - c7_out : out std_logic; - CLK_12 : out std_logic; - TB_CPT : out std_logic_vector(4 downto 0) - ); -end entity ctrlseq; - -architecture ctrlseq_arch of ctrlseq is - -signal lCPT_GEN : std_logic_vector(4 downto 0); -- counter -signal lstate : std_logic_vector(7 downto 0); -- states -signal lreload : std_logic; -- to reload null value to lCPT_GEN -signal lld_reg_p : std_logic; -- to load value into register for VIDEO - -signal c_ras : std_logic; -- RAS -signal c_cas : std_logic; -- CAS -signal c_mux : std_logic; -- MUX -signal c_clk_cpu : std_logic; -- CLK_CPU - -signal c_0 : std_logic; -- state number 0 -signal c_1 : std_logic; -- state number 1 -signal c_2 : std_logic; -- state number 2 -signal c_3 : std_logic; -- state number 3 -signal c_4 : std_logic; -- state number 4 -signal c_5 : std_logic; -- state number 5 -signal c_6 : std_logic; -- state number 6 -signal c_7 : std_logic; -- state number 7 - -signal p_0 : std_logic; -- phase number 0 -signal p_1 : std_logic; -- phase number 1 -signal p_2 : std_logic; -- phase number 2 - --- Constants for states -constant cd_step_0 : integer :=0; -constant cd_step_1 : integer :=1; -constant cd_step_2 : integer :=2; -constant cd_step_3 : integer :=3; -constant cd_step_4 : integer :=4; -constant cd_step_5 : integer :=5; -constant cd_step_6 : integer :=6; -constant cd_step_7 : integer :=7; - -begin - --- Increment counter -U_TB_CPT: PROCESS (RESETn, CLK_24) -BEGIN - if (RESETn = '0') then - lCPT_GEN <= "00000"; - elsif falling_edge(clk_24) then - if (lreload = '1') then - lCPT_GEN <= "00000"; - else - lCPT_GEN <= lCPT_GEN + "00001"; - end if; - end if; -END PROCESS; -lreload <= '1' when lCPT_GEN = "10111" else '0'; - --- Manage states -U_SM_GEST: PROCESS(lCPT_GEN) -BEGIN - lstate <= "00000000"; - case lCPT_GEN(2 downto 0) is - when "000" => lstate(cd_step_0) <= '1'; - when "001" => lstate(cd_step_1) <= '1'; - when "010" => lstate(cd_step_2) <= '1'; - when "011" => lstate(cd_step_3) <= '1'; - when "100" => lstate(cd_step_4) <= '1'; - when "101" => lstate(cd_step_5) <= '1'; - when "110" => lstate(cd_step_6) <= '1'; - when "111" => lstate(cd_step_7) <= '1'; - when others => null; - end case; -END PROCESS; - --- Assign states -c_0 <= lstate(cd_step_0); -c_1 <= lstate(cd_step_1); -c_2 <= lstate(cd_step_2); -c_3 <= lstate(cd_step_3); -c_4 <= lstate(cd_step_4); -c_5 <= lstate(cd_step_5); -c_6 <= lstate(cd_step_6); -c_7 <= lstate(cd_step_7); - --- Three phases -p_0 <= NOT lCPT_GEN(4) and NOT lCPT_GEN(3); -- 00 -p_1 <= NOT lCPT_GEN(4) and lCPT_GEN(3); -- 01 -p_2 <= lCPT_GEN(4) and NOT lCPT_GEN(3); -- 10 - --------------------------------- --- GENERATION DE LA CLOCK CPU -- --------------------------------- -CLK_1_CPU <= p_2; - ---------------------------------- --- GESTION DE LA RAM DYNAMIQUE -- ---------------------------------- -ras <= c_2 or c_3 or c_4 or c_5; -cas <= not (c_2 or c_3) and (not p_2 or CSRAMn); --- Mux permet de sélectionner soit l'adresse haute d'une adresse cpu --- soit l'adresse haute d'une adresse ula -mux <= '1' when ((c_1 = '1' or c_2 = '1') and p_2 = '1') else '0'; -oRW <= iRW and p_2; - ---------------------- --- GESTION INTERNE -- ---------------------- - ---Generation pour la gestion de l'adresse video 1 -VA1L <= '1' when (c_1='1' and p_0='1') ELSE '0'; -VA1R <= '1' when ((c_1='1' or c_2='1') and p_0='1') ELSE '0'; -VA1C <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_0='1') ELSE '0'; - ---Generation pour la gestion de l'adresse video 2 -VA2L <= '1' when (c_1='1' and p_1='1') ELSE '0'; -VA2R <= '1' when ((c_1='1' or c_2='1') and p_1='1') ELSE '0'; -VA2C <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_1='1') ELSE '0'; - ---Generation pour la gestion de l'adresse CPU -BAL <= '1' when (c_1='1' and p_2='1') ELSE '0'; ---Modif. du 22/02/09 BAC <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_2='1' and CSRAMn='0') ELSE '0'; -BAC <= '1' when ((c_3='1' or c_4='1' or c_5='1') and p_2='1') ELSE '0'; --- Ajout du 09/02/09 : output enable pour la rom/ram lors de l'adressage par le CPU -BAOE <= '1' when (not(c_0='1' or c_1 ='1') and p_2='1') ELSE '0'; - ---Pour la partie video -lld_reg_p <= NOT isAttrib and (c_7 and p_1) and NOT TXTHIR_DEC; - -ATTRIB_DEC <= '1' when (isAttrib='1' and c_2='1' and p_1='1') ELSE '0'; -LD_REG_0 <= '1' when (isAttrib='1' and c_7='1' and p_1='1') ELSE '0'; -LD_REG <= '1' when (lld_reg_p='1' or (c_7='1' and p_0='1')) ELSE '0'; -DATABUS_EN <= '1' when (lld_reg_p='1' or (c_7='1' and p_0='1')) ELSE '0'; -LDFROMBUS <= '1' when (c_0='1' and p_2='1') ELSE '0'; - --- for TEST BENCH -c0_OUT <= lstate(cd_step_0); -c1_OUT <= lstate(cd_step_1); -c2_OUT <= lstate(cd_step_2); -c3_OUT <= lstate(cd_step_3); -c4_OUT <= lstate(cd_step_4); -c5_OUT <= lstate(cd_step_5); -c6_OUT <= lstate(cd_step_6); -c7_OUT <= lstate(cd_step_7); -TB_CPT <= lCPT_GEN; -CLK_12 <= lCPT_GEN(0); - --- for ram statique -CLK_4 <= c_6 or c_7; - -end architecture ctrlseq_arch; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/dac.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/dac.vhd deleted file mode 100644 index 1af6b8c1..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/dac.vhd +++ /dev/null @@ -1,65 +0,0 @@ --- --- DAC.vhd --- --- Digital to analog convertor. --- --- Copyright (C)2001 SEILEBOST --- All rights reserved. --- --- $Id: DAC.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $ --- --- from XAPP154.pdf & XAPP154.ZIP (XILINX APPLICATION) --- --- DAC 8 Bits ( method : sigma delta) --- 2^N clock to convert with N = width of input --- Ex : Bus 8 bits => 256 CLOCK master to convert an value. --- Theorem Shannon : 2 x Fmax x 256 =< 16 MHz => Fmax = 31250 Hz --- band of sound : 0 -> 20000 Hz : Ok !! - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity DAC is - Port ( CLK_DAC : in std_logic; - RST : in std_logic; - IN_DAC : in std_logic_vector(7 downto 0); - OUT_DAC : out std_logic ); -end DAC; - -architecture Behavioral of DAC is - -signal DeltaAdder : std_logic_vector(9 downto 0); -signal SigmaAdder : std_logic_vector(9 downto 0); -signal SigmaLatch : std_logic_vector(9 downto 0); -signal DeltaB : std_logic_vector(9 downto 0); - -begin - PROCESS(SigmaLatch, DeltaB) - BEGIN - DeltaB <= TRANSPORT ( SigmaLatch(9) & SigmaLatch(9) & "00000000"); - END PROCESS; - - PROCESS(IN_DAC, DeltaB, DeltaAdder) - BEGIN - DeltaAdder <= IN_DAC + DeltaB; - END PROCESS; - - PROCESS(DeltaAdder, SigmaLatch) - BEGIN - SigmaAdder <= DeltaAdder + SigmaLatch; - END PROCESS; - - PROCESS(CLK_DAC, RST) - BEGIN - if (RST = '1') then - SigmaLatch <= "0100000000"; - OUT_DAC <= '1'; - elsif (CLK_DAC'event and CLK_DAC = '1') then - SigmaLatch <= SigmaAdder; - OUT_DAC <= SigmaLatch(9); - end if; - END PROCESS; - -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/gen_clk.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/gen_clk.vhd deleted file mode 100644 index 5def2c8d..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/gen_clk.vhd +++ /dev/null @@ -1,44 +0,0 @@ --- --- GEN_CLK.vhd --- --- GENERATOR of CLOCK. --- --- Copyright (C)2001 SEILEBOST --- All rights reserved. --- --- $Id: GEN_CLK.vhd, v0.42 2002/01/03 00:00:00 SEILEBOST $ --- --- Generate secondary CLK from CLK_MASTER --- CLK : Clock Master, 16 MHz --- CLK_16 : for the tone generator, --- CLK_256 : for the envelope generator - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity GEN_CLK is - Port ( CLK : in std_logic; - RST : in std_logic; - CLK_16 : out std_logic; - CLK_256 : out std_logic - ); -end GEN_CLK; - -architecture Behavioral of GEN_CLK is - -SIGNAL COUNT : std_logic_vector(7 downto 0); -begin - - PROCESS(CLK, RST) - BEGIN - if (RST = '1') then - COUNT <= (OTHERS => '0'); - elsif (CLK'event and CLK = '1') then - COUNT <= COUNT + 1; - CLK_16 <= COUNT(3); - CLK_256 <= COUNT(7); - end if; - END PROCESS; -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/gen_env.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/gen_env.vhd deleted file mode 100644 index 8fba2848..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/gen_env.vhd +++ /dev/null @@ -1,111 +0,0 @@ --- --- GEN_ENV.vhd --- --- GENERATOR of ENVELOPE. --- --- Copyright (C)2001-2010 SEILEBOST --- All rights reserved. --- --- $Id: GEN_ENV.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $ --- --- NO BUGS --- NEARLY TESTED --- --- Revision list --- --- v0.4 2001/11/21 : Modification --- v0.46 2010/01/06 : Modification du générateur d'enveloppe --- et de fréquence - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity gen_env is - Port ( CLK_ENV : in std_logic; - DATA : in std_logic_vector(3 downto 0); - RST_ENV : in std_logic; - WR : in std_logic; - --CS : in std_logic; - OUT_DATA : inout std_logic_vector(3 downto 0) ); -end gen_env; - -architecture Behavioral of gen_env is - -SIGNAL DIR : std_logic; -- direction -SIGNAL HOLD : std_logic; -- continue the sound - -begin - - PROCESS(CLK_ENV, RST_ENV, DATA, WR) - variable isMin : boolean; - variable isNearlyMin : boolean; - variable isNearlyMax : boolean; - variable isMax : boolean; - BEGIN - if (RST_ENV = '1') then -- Reset : to load the good value to generate enveloppe - if (DATA(2) = '0') then -- front initial : 0 = descendant et 1 = montant - OUT_DATA <= "1111"; - DIR <= '0'; - else - OUT_DATA <= "0000"; - DIR <= '1'; - end if; - HOLD <= '0'; - elsif (CLK_ENV'event and CLK_ENV = '1') then -- edge clock - -- To simply the written code ! - isMin := (OUT_DATA = "00000"); - isNearlyMin := (OUT_DATA = "00001"); - isNearlyMax := (OUT_DATA = "11110"); - isMax := (OUT_DATA = "11111"); - - -- To manage the next value - if (HOLD = '0') then - if (DIR = '0') then - OUT_DATA <= OUT_DATA - 1; - else - OUT_DATA <= OUT_DATA + 1; - end if; - end if; - - -- To generate the shape of envelope - if (DATA(3) = '0') then - if (DIR = '0') then - if (isNearlyMin) then - HOLD <= '1'; - end if; - else - if (isMax) then - HOLD <= '1'; -- Astuce : il faut que OUT_DATE = "0000" au prochain tick donc comparaison de la sortie sur "1111" car incrementation automatique - end if; - end if; - else - if (DATA(0) = '1') then -- hold = 1 - if (DIR = '0') then -- down - if (DATA(1) = '1') then -- alt - if isMin then HOLD <= '1'; end if; - else - if isNearlyMin then HOLD <= '1'; end if; - end if; - else - if (DATA(1) = '1') then -- alt - if isMax then HOLD <= '1'; end if; - else - if isNearlyMax then HOLD <= '1'; end if; - end if; - end if; - elsif (DATA(1) = '1') then -- alternate - if (DIR = '0') then -- down - if isNearlyMin then HOLD <= '1'; end if; - if isMin then HOLD <= '0'; DIR <= '1'; end if; - else - if isNearlyMax then HOLD <= '1'; end if; - if isMax then HOLD <= '0'; DIR <= '0'; end if; - end if; - end if; - end if; - end if; -- fin elsif - END PROCESS; - -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/greybox_tmp/cbx_args.txt b/Computer_MiST/Oric Atmos_MiST/rtl/greybox_tmp/cbx_args.txt deleted file mode 100644 index 1af637e5..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/greybox_tmp/cbx_args.txt +++ /dev/null @@ -1,29 +0,0 @@ -ADDRESS_ACLR_B=NONE -ADDRESS_REG_B=CLOCK0 -CLOCK_ENABLE_INPUT_A=NORMAL -CLOCK_ENABLE_INPUT_B=NORMAL -CLOCK_ENABLE_OUTPUT_B=NORMAL -INTENDED_DEVICE_FAMILY="Cyclone III" -LPM_TYPE=altsyncram -NUMWORDS_A=8 -NUMWORDS_B=8 -OPERATION_MODE=DUAL_PORT -OUTDATA_ACLR_B=NONE -OUTDATA_REG_B=CLOCK0 -POWER_UP_UNINITIALIZED=FALSE -RDCONTROL_REG_B=CLOCK0 -READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE -WIDTHAD_A=3 -WIDTHAD_B=3 -WIDTH_A=1 -WIDTH_B=1 -WIDTH_BYTEENA_A=1 -DEVICE_FAMILY="Cyclone III" -address_a -address_b -clock0 -clocken0 -data_a -rden_b -wren_a -q_b diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/hq2x.sv b/Computer_MiST/Oric Atmos_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/iodecode.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/iodecode.vhd deleted file mode 100644 index 9972721f..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/iodecode.vhd +++ /dev/null @@ -1,112 +0,0 @@ --- --- iodecode.vhd --- --- Manage access for I/O, Ram and Rom --- --- Copyright (C)2001 - 2005 SEILEBOST --- All rights reserved. --- --- $Id: iodecode.vhd, v0.10 2009/06/25 00:00:00 SEILEBOST $ --- --- TODO : --- Remark : --- 08/03/09 : Retour en arrière -Library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_STD.all; ---use IEEE.std_logic_unsigned.all; - -entity iodecode is -port ( RESETn : in std_logic; - CLK_1 : in std_logic; - ADDR : in std_logic_vector(15 downto 0); - ADDR_LE : in std_logic; - MAPn : in std_logic; - CSROMn : out std_logic; - CSRAMn : out std_logic; - CSIOn : out std_logic - ); -end entity iodecode; - -architecture iodecode_arch of iodecode is - -signal lCSROMn : std_logic; -signal lCSRAMn : std_logic; -signal lCSIOn : std_logic; -signal lADDR : std_logic_vector(15 downto 0); - -begin - --- Latch BAP -u_laddr: PROCESS ( ADDR_LE, resetn ) -begin - if (resetn = '0') then - lADDR<= (OTHERS => '0'); - elsif rising_edge(ADDR_LE) then - lAddr<= Addr; - end if; -end process; - - --- PAGE I/O : 0x300-0x3FF --- lCSIOn <= '0' WHEN (lADDR(7 downto 0) = "00000011") AND (CLK_1 = '1') ELSE '1'; -lCSIOn <= '0' WHEN (ADDR(15 downto 8) = "00000011") AND (ADDR_LE = '1') ELSE '1'; ---p_CSION : process(CLK_1) ---begin --- lCSIOn <= '1'; --- if (rising_edge(CLK_1)) then --- if (lADDR(7 downto 0) = "00000011") then --- lCSION <= '0'; --- end if; --- end if; ---end process; - --- PAGE ROM : 0xC000-0xFFFF --- lCSROMn <= '0' WHEN (lADDR(7 downto 6) = "11" AND MAPn = '1' AND CLK_1 = '1') ELSE '1'; p_CSION : process(CLK_1) -lCSROMn <= '0' WHEN (ADDR(15 downto 14) = "11" AND MAPn = '1' AND ADDR_LE = '1') ELSE '1'; ---p_CSROMN : process(CLK_1) ---begin --- lCSROMn <= '1'; --- if (rising_edge(CLK_1)) then --- if (lADDR(7 downto 6) = "11" AND MAPn = '1') then --- lCSROMn <= '0'; --- end if; --- end if; --- end process; - --- PAGR RAM : le reste ... --- lCSRAMn <= '0' WHEN -- Partie Ram shadow --- (lADDR(7 downto 6) = "11" AND MAPn = '0' AND CLK_1 = '1') --- OR --- -- Partie Ram normale --- ( (lADDR(7 downto 0) /= "00000011" and lADDR(7 downto 6) /= "11") --- AND MAPn = '1' AND CLK_1 = '1') --- ELSE '1'; -lCSRAMn <= '0' WHEN -- Partie Ram shadow - (ADDR(15 downto 14) = "11" AND MAPn = '0' AND ADDR_LE = '1') - OR - -- Partie Ram normale - (((ADDR(15 downto 8) /= "00000011") AND (ADDR(15 downto 14) /= "11")) AND MAPn = '1' AND ADDR_LE = '1') - ELSE '1'; - ---p_CSRAMN : process(CLK_1) ---begin --- lCSRAMn <= '1'; --- if (rising_edge(CLK_1)) then --- if ((lADDR(7 downto 6) = "11" AND MAPn = '0') --- OR ((lADDR(7 downto 0) /= "00000011" and lADDR(7 downto 6) /= "11") --- AND MAPn = '1')) then --- lCSRAMn <= '0'; --- end if; --- end if; ---end process; - --- Assign output signal -CSROMn <= lCSROMn; -CSRAMn <= lCSRAMn; -CSIOn <= lCSIOn; - -end architecture iodecode_arch; - - - diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/keyboard.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/keyboard.vhd deleted file mode 100644 index f313f1d7..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/keyboard.vhd +++ /dev/null @@ -1,109 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity keyboard is - port( - CLK : in std_logic; - RESET : in std_logic; - - PS2CLK : in std_logic; - PS2DATA : in std_logic; - - COL : in std_logic_vector(2 downto 0); - ROWbit : out std_logic_vector(7 downto 0) - ); -end keyboard; - -architecture arch of keyboard is - --- Gestion du protocole sur PS/2 -component ps2key is - generic ( - FREQ : integer := 24 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - - PS2CLK : in std_logic; - PS2DATA : in std_logic; - - BREAK : out std_logic; - EXTENDED : out std_logic; - CODE : out std_logic_vector(6 downto 0); - LATCH : out std_logic - ); -end component; - - --- La matrice du clavier -component keymatrix is - port( - CLK : in std_logic; - wROW : in std_logic_vector(2 downto 0); - wCOL : in std_logic_vector(2 downto 0); - wVAL : in std_logic; - wEN : in std_logic; - WE : in std_logic; - - rCOL : in std_logic_vector(2 downto 0); - rROWbit : out std_logic_vector(7 downto 0) - ); -end component; - -signal MAT_wROW : std_logic_vector(2 downto 0); -signal MAT_wCOL : std_logic_vector(2 downto 0); -signal MAT_wVAL : std_logic; -signal MAT_WE : std_logic; -signal MAT_wEN : std_logic; - -signal ROM_A : std_logic_vector(7 downto 0); - -signal DISPLAY : std_logic_vector(15 downto 0); - - -begin - -PS2 : ps2key port map( - CLK => CLK, - RESET => RESET, - - PS2CLK => PS2CLK, - PS2DATA => PS2DATA, - - BREAK => MAT_wVAL, - EXTENDED => ROM_A(7), - CODE(0) => ROM_A(0), - CODE(1) => ROM_A(1), - CODE(2) => ROM_A(2), - CODE(3) => ROM_A(3), - CODE(4) => ROM_A(4), - CODE(5) => ROM_A(5), - CODE(6) => ROM_A(6), - - LATCH => MAT_WE -); - -ROM : entity work.keymap port map( - A => ROM_A, - ROW => MAT_wROW, - COL => MAT_wCOL, - clk_sys => CLK, - EN => MAT_wEN -); - -MAT : keymatrix port map( - CLK => CLK, - wROW => MAT_wROW, - wCOL => MAT_wCOL, - wVAL => MAT_wVAL, - wEN => MAT_wEN, - WE => MAT_WE, - - rCOL => COL, - rROWbit => ROWbit -); - -end arch; \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/keyboardX.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/keyboardX.vhd deleted file mode 100644 index 014df377..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/keyboardX.vhd +++ /dev/null @@ -1,30 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity keyboardX is -port ( - CLK : in std_logic; - RESET : in std_logic; - PS2CLK : in std_logic; - PS2DATA : in std_logic_vector( 7 downto 0); - COL : in std_logic_vector(2 downto 0); - ROWbit : out std_logic_vector( 7 downto 0) -); -end; - -architecture RTL of keyboardX is - -begin - - CLKp: PROCESS ( CLK ) -begin - if (RESET = '0') then - COL<= (OTHERS => '0'); - ROWbit<= (OTHERS => '0'); - elsif rising_edge(CLK) then - --- - end if; -end process; -end RTL; \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/keymap.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/keymap.vhd deleted file mode 100644 index 743eac40..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/keymap.vhd +++ /dev/null @@ -1,180 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity keymap is - port( - A : in std_logic_vector(7 downto 0); - clk_sys: in std_logic; - ROW : out std_logic_vector(2 downto 0); - COL : out std_logic_vector(2 downto 0); - EN : out std_logic - ); -end keymap; - -architecture arch of keymap is -begin - -ROM256X1_ROW2 : entity work.sprom - generic map - ( - init_file => "roms/key1.hex", - widthad_a => 8, - width_a => 1 - ) - port map - ( - clock => clk_sys, - address => A, - q(0) => ROW(2) - ); - --- ROWS - --- ROM256X1_ROW2 : ROM256X1 - -- generic map ( --- INIT => X"00140800000000000000000000000000004000402E3400000000004E7C760000") - -- port map ( - -- q => ROW(2), -- ROM output --- address => A --- ); - -ROM256X1_ROW1 : entity work.sprom - generic map - ( - init_file => "roms/key2.hex", - widthad_a => 8, - width_a => 1 - ) - port map - ( - clock => clk_sys, - address => A, - q(0) => ROW(1) - ); - --- ROM256X1_ROW1 : ROM256X1 --- generic map ( --- INIT => X"00340000000000000000000000000000000000002834763000146C7E68200000") --- port map ( --- q => ROW(1), -- ROM output --- address => A --- ); - -ROM256X1_ROW0 : entity work.sprom - generic map - ( - init_file => "roms/key3.hex", - widthad_a => 8, - width_a => 1 - ) - port map - ( - clock => clk_sys, - address => A, - q(0) => ROW(0) - ); - --- ROM256X1_ROW0 : ROM256X1 --- generic map ( --- INIT => X"003008000000000000000000000000000040004004346C4A004A1C7A34400000") --- port map ( --- q => ROW(0), -- ROM output --- address => A -- ROM address --- ); - --- COLUMNS - -ROM256X1_COL2 : entity work.sprom - generic map - ( - init_file => "roms/key4.hex", - widthad_a => 8, - width_a => 1 - ) - port map - ( - clock => clk_sys, - address => A, - q(0) => COL(2) - ); - --- ROM256X1_COL2 : ROM256X1 --- generic map ( --- INIT => X"00340800000000000000000000000000000000400E302E3A5038021038060000") --- port map ( --- q => COL(2), -- ROM output --- address => A -- ROM address[7] --- ); - -ROM256X1_COL1 : entity work.sprom - generic map - ( - init_file => "roms/key5.hex", - widthad_a => 8, - width_a => 1 - ) - port map - ( - clock => clk_sys, - address => A, - q(0) => COL(1) - ); - --- ROM256X1_COL1 : ROM256X1 --- generic map ( --- INIT => X"000000000000000000000000000000000000000026245C64447C00327C100000") --- port map ( --- q => COL(1), -- ROM output --- address => A -- ROM address[7] --- ); - -ROM256X1_COL0 : entity work.sprom - generic map - ( - init_file => "roms/key6.hex", - widthad_a => 8, - width_a => 1 - ) - port map - ( - clock => clk_sys, - address => A, - q(0) => COL(0) - ); - --- ROM256X1_COL0 : ROM256X1 - -- generic map ( --- INIT => X"00000000000000000000000000000000004000402E347C7C5800380800220000") --- port map ( --- q => COL(0), -- ROM output --- address => A -- ROM address[7] - -- ); - --- ENABLE - -ROM256X1_EN : entity work.sprom - generic map - ( - init_file => "roms/key7.hex", - widthad_a => 8, - width_a => 1 - ) - port map - ( - clock => clk_sys, - address => A, - q(0) => EN - ); - --- ROM256X1_EN : ROM256X1 --- generic map ( --- INIT => X"00340800000000000000000000000000004000402E347E7E7C7E7E7E7C760000") --- port map ( --- q => EN, -- ROM output --- address => A -- ROM address[7] --- ); - -end arch; - diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/keymatrix.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/keymatrix.vhd deleted file mode 100644 index b9b2cef3..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/keymatrix.vhd +++ /dev/null @@ -1,102 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity keymatrix is - port( - CLK : in std_logic; - wROW : in std_logic_vector(2 downto 0); - wCOL : in std_logic_vector(2 downto 0); - wVAL : in std_logic; - wEN : in std_logic; - WE : in std_logic; - - rCOL : in std_logic_vector(2 downto 0); - rROWbit : out std_logic_vector(7 downto 0) - ); -end keymatrix; - -architecture arch of keymatrix is -signal WEi : std_logic_vector(7 downto 0); - --- inutilise -signal SPOi : std_logic_vector(7 downto 0); - -begin - -WEi(0) <= WE when wEN = '1' and wROW = "000" else '0'; -WEi(1) <= WE when wEN = '1' and wROW = "001" else '0'; -WEi(2) <= WE when wEN = '1' and wROW = "010" else '0'; -WEi(3) <= WE when wEN = '1' and wROW = "011" else '0'; -WEi(4) <= WE when wEN = '1' and wROW = "100" else '0'; -WEi(5) <= WE when wEN = '1' and wROW = "101" else '0'; -WEi(6) <= WE when wEN = '1' and wROW = "110" else '0'; -WEi(7) <= WE when wEN = '1' and wROW = "111" else '0'; - - ---ROWBit : for i in 0 to 7 generate --- RAM16X1D_ROWBit : RAM16X1D --- generic map ( --- INIT => X"FFFF") --- port map ( - --- D => wVAL, -- Write 1-bit data input---------------------------data - --- SPO => SPOi(i), -- R/W 1-bit data output for A0-A3 - --- A0 => wCOL(0), -- R/W address[0] input bit--------------------------waddress --- A1 => wCOL(1), -- R/W address[1] input bit --- A2 => wCOL(2), -- R/W address[2] input bit --- A3 => '0', -- R/W ddress[3] input bit - - --- DPO => rROWBit(i), -- Read-only 1-bit data output for DPRA--------------q - - --- DPRA0 => rCOL(0), -- Read-only address[0] input bit--------------------------raddress --- DPRA1 => rCOL(1), -- Read-only address[1] input bit --- DPRA2 => rCOL(2), -- Read-only address[2] input bit --- DPRA3 => '0', -- Read-only address[3] input bit - - - --- WCLK => CLK, -- Write clock input-----------------------------------clock - -- WE => WEi(i) -- Write enable input----------------------------------wren - -- ); ---end generate; - -ROWBit : for i in 0 to 7 generate - RAM16X1D_ROWBit : entity work.RAM8X1D --- generic map ( --- INIT => X"FFFF") - port map ( - - data(0) => wVAL, -- Write 1-bit data input---------------------------data - - enable => SPOi(i), -- R/W 1-bit data output for A0-A3 - wraddress => wCOL, --- A0 => wCOL(0), -- R/W address[0] input bit--------------------------waddress --- A1 => wCOL(1), -- R/W address[1] input bit --- A2 => wCOL(2), -- R/W address[2] input bit --- A3 => '0', -- R/W ddress[3] input bit - - --- rden => rROWBit(i), -- Read-only 1-bit data output for DPRA--------------q - - rdaddress => rCOL, --- DPRA0 => rCOL(0), -- Read-only address[0] input bit--------------------------raddress --- DPRA1 => rCOL(1), -- Read-only address[1] input bit --- DPRA2 => rCOL(2), -- Read-only address[2] input bit --- DPRA3 => '0', -- Read-only address[3] input bit - - - clock => CLK, --- WCLK => CLK, -- Write clock input-----------------------------------clock - wren => WEi(i) -- Write enable input----------------------------------wren - ); -end generate; - - -end arch; - diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/m6522.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/m6522.vhd deleted file mode 100644 index e6d74237..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/m6522.vhd +++ /dev/null @@ -1,886 +0,0 @@ --- --- A simulation model of VIC20 hardware --- Copyright (c) MikeJ - March 2003 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email vic20@fpgaarcade.com --- --- --- Revision list --- --- version 002 fix from Mark McDougall, untested --- version 001 initial release --- not very sure about the shift register, documentation is a bit light. - -library ieee ; - use ieee.std_logic_1164.all ; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity M6522 is - port ( - - I_RS : in std_logic_vector(3 downto 0); - I_DATA : in std_logic_vector(7 downto 0); - O_DATA : out std_logic_vector(7 downto 0); - O_DATA_OE_L : out std_logic; - - I_RW_L : in std_logic; - I_CS1 : in std_logic; - I_CS2_L : in std_logic; - - O_IRQ_L : out std_logic; -- note, not open drain - -- port a - I_CA1 : in std_logic; - I_CA2 : in std_logic; - O_CA2 : out std_logic; - O_CA2_OE_L : out std_logic; - - I_PA : in std_logic_vector(7 downto 0); - O_PA : out std_logic_vector(7 downto 0); - O_PA_OE_L : out std_logic_vector(7 downto 0); - - -- port b - I_CB1 : in std_logic; - O_CB1 : out std_logic; - O_CB1_OE_L : out std_logic; - - I_CB2 : in std_logic; - O_CB2 : out std_logic; - O_CB2_OE_L : out std_logic; - - I_PB : in std_logic_vector(7 downto 0); - O_PB : out std_logic_vector(7 downto 0); - O_PB_OE_L : out std_logic_vector(7 downto 0); - - I_P2_H : in std_logic; -- high for phase 2 clock ____----__ - RESET_L : in std_logic; - ENA_4 : in std_logic; -- clk enable - CLK : in std_logic - ); -end; - -architecture RTL of M6522 is - - signal phase : std_logic_vector(1 downto 0); - signal p2_h_t1 : std_logic; - signal cs : std_logic; - - -- registers - signal r_ddra : std_logic_vector(7 downto 0); - signal r_ora : std_logic_vector(7 downto 0); - signal r_ira : std_logic_vector(7 downto 0); - - signal r_ddrb : std_logic_vector(7 downto 0); - signal r_orb : std_logic_vector(7 downto 0); - signal r_irb : std_logic_vector(7 downto 0); - - signal r_t1l_l : std_logic_vector(7 downto 0); - signal r_t1l_h : std_logic_vector(7 downto 0); - signal r_t2l_l : std_logic_vector(7 downto 0); - signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip - signal r_sr : std_logic_vector(7 downto 0); - signal r_acr : std_logic_vector(7 downto 0); - signal r_pcr : std_logic_vector(7 downto 0); - signal r_ifr : std_logic_vector(7 downto 0); - signal r_ier : std_logic_vector(6 downto 0); - - signal sr_write_ena : boolean; - signal sr_read_ena : boolean; - signal ifr_write_ena : boolean; - signal ier_write_ena : boolean; - signal clear_irq : std_logic_vector(7 downto 0); - signal load_data : std_logic_vector(7 downto 0); - - -- timer 1 - signal t1c : std_logic_vector(15 downto 0); - signal t1c_active : boolean; - signal t1c_done : boolean; - signal t1_w_reset_int : boolean; - signal t1_r_reset_int : boolean; - signal t1_load_counter : boolean; - signal t1_reload_counter : boolean; - signal t1_toggle : std_logic; - signal t1_irq : std_logic := '0'; - - -- timer 2 - signal t2c : std_logic_vector(15 downto 0); - signal t2c_active : boolean; - signal t2c_done : boolean; - signal t2_pb6 : std_logic; - signal t2_pb6_t1 : std_logic; - signal t2_w_reset_int : boolean; - signal t2_r_reset_int : boolean; - signal t2_load_counter : boolean; - signal t2_reload_counter : boolean; - signal t2_irq : std_logic := '0'; - signal t2_sr_ena : boolean; - - -- shift reg - signal sr_cnt : std_logic_vector(3 downto 0); - signal sr_cb1_oe_l : std_logic; - signal sr_cb1_out : std_logic; - signal sr_drive_cb2 : std_logic; - signal sr_strobe : std_logic; - signal sr_strobe_t1 : std_logic; - signal sr_strobe_falling : boolean; - signal sr_strobe_rising : boolean; - signal sr_irq : std_logic; - signal sr_out : std_logic; - signal sr_off_delay : std_logic; - - -- io - signal w_orb_hs : std_logic; - signal w_ora_hs : std_logic; - signal r_irb_hs : std_logic; - signal r_ira_hs : std_logic; - - signal ca_hs_sr : std_logic; - signal ca_hs_pulse : std_logic; - signal cb_hs_sr : std_logic; - signal cb_hs_pulse : std_logic; - - signal cb1_in_mux : std_logic; - signal ca1_ip_reg : std_logic; - signal cb1_ip_reg : std_logic; - signal ca1_int : boolean; - signal cb1_int : boolean; - signal ca1_irq : std_logic; - signal cb1_irq : std_logic; - - signal ca2_ip_reg : std_logic; - signal cb2_ip_reg : std_logic; - signal ca2_int : boolean; - signal cb2_int : boolean; - signal ca2_irq : std_logic; - signal cb2_irq : std_logic; - - signal final_irq : std_logic; -begin - - p_phase : process - begin - -- internal clock phase - wait until rising_edge(CLK); - if (ENA_4 = '1') then - p2_h_t1 <= I_P2_H; - if (p2_h_t1 = '0') and (I_P2_H = '1') then - phase <= "11"; - else - phase <= phase + "1"; - end if; - end if; - end process; - - p_cs : process(I_CS1, I_CS2_L, I_P2_H) - begin - cs <= '0'; - if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then - cs <= '1'; - end if; - end process; - - -- peripheral control reg (pcr) - -- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge) - -- 3..1 ca2 operation - -- 000 input -ve edge - -- 001 independend interrupt input -ve edge - -- 010 input +ve edge - -- 011 independend interrupt input +ve edge - -- 100 handshake output - -- 101 pulse output - -- 110 low output - -- 111 high output - -- 7..4 as 3..0 for cb1,cb2 - - -- auxiliary control reg (acr) - -- 0 input latch PA (0 disable, 1 enable) - -- 1 input latch PB (0 disable, 1 enable) - -- 4..2 shift reg control - -- 000 disable - -- 001 shift in using t2 - -- 010 shift in using o2 - -- 011 shift in using ext clk - -- 100 shift out free running t2 rate - -- 101 shift out using t2 - -- 101 shift out using o2 - -- 101 shift out using ext clk - -- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6) - -- 7..6 t1 timer control - -- 00 timed interrupt each time t1 is loaded pb7 disable - -- 01 continuous interrupts pb7 disable - -- 00 timed interrupt each time t1 is loaded pb7 one shot output - -- 01 continuous interrupts pb7 square wave output - -- - - p_write_reg_reset : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - r_ora <= x"00"; r_orb <= x"00"; - r_ddra <= x"00"; r_ddrb <= x"00"; - r_acr <= x"00"; r_pcr <= x"00"; - - w_orb_hs <= '0'; - w_ora_hs <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - w_orb_hs <= '0'; - w_ora_hs <= '0'; - if (cs = '1') and (I_RW_L = '0') then - case I_RS is - when x"0" => r_orb <= I_DATA; w_orb_hs <= '1'; - when x"1" => r_ora <= I_DATA; w_ora_hs <= '1'; - when x"2" => r_ddrb <= I_DATA; - when x"3" => r_ddra <= I_DATA; - - when x"B" => r_acr <= I_DATA; - when x"C" => r_pcr <= I_DATA; - when x"F" => r_ora <= I_DATA; - - when others => null; - end case; - end if; - - if (r_acr(7) = '1') and (t1_toggle = '1') then - r_orb(7) <= not r_orb(7); -- toggle - end if; - end if; - end if; - end process; - - p_write_reg : process - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - t1_w_reset_int <= false; - t1_load_counter <= false; - - t2_w_reset_int <= false; - t2_load_counter <= false; - - load_data <= x"00"; - sr_write_ena <= false; - ifr_write_ena <= false; - ier_write_ena <= false; - - if (cs = '1') and (I_RW_L = '0') then - load_data <= I_DATA; - case I_RS is - when x"4" => r_t1l_l <= I_DATA; - when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; - t1_load_counter <= true; - - when x"6" => r_t1l_l <= I_DATA; - when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; - - when x"8" => r_t2l_l <= I_DATA; - when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true; - t2_load_counter <= true; - - when x"A" => sr_write_ena <= true; - when x"D" => ifr_write_ena <= true; - when x"E" => ier_write_ena <= true; - - when others => null; - end case; - end if; - end if; - end process; - - p_oe : process(cs, I_RW_L) - begin - O_DATA_OE_L <= '1'; - if (cs = '1') and (I_RW_L = '1') then - O_DATA_OE_L <= '0'; - end if; - end process; - - p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l, - r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb) - begin - t1_r_reset_int <= false; - t2_r_reset_int <= false; - sr_read_ena <= false; - r_irb_hs <= '0'; - r_ira_hs <= '0'; - O_DATA <= x"00"; -- default - if (cs = '1') and (I_RW_L = '1') then - case I_RS is - --when x"0" => O_DATA <= r_irb; r_irb_hs <= '1'; - -- fix from Mark McDougall, untested - when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1'; - when x"1" => O_DATA <= r_ira; r_ira_hs <= '1'; - when x"2" => O_DATA <= r_ddrb; - when x"3" => O_DATA <= r_ddra; - when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true; - when x"5" => O_DATA <= t1c(15 downto 8); - when x"6" => O_DATA <= r_t1l_l; - when x"7" => O_DATA <= r_t1l_h; - when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true; - when x"9" => O_DATA <= t2c(15 downto 8); - when x"A" => O_DATA <= r_sr; sr_read_ena <= true; - when x"B" => O_DATA <= r_acr; - when x"C" => O_DATA <= r_pcr; - when x"D" => O_DATA <= r_ifr; - when x"E" => O_DATA <= ('0' & r_ier); - when x"F" => O_DATA <= r_ira; - when others => null; - end case; - end if; - - end process; - -- - -- IO - -- - p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1) - begin - -- if the shift register is enabled, cb1 may be an output - -- in this case, we should listen to the CB1_OUT for the interrupt - if (sr_cb1_oe_l = '1') then - cb1_in_mux <= I_CB1; - else - cb1_in_mux <= sr_cb1_out; - end if; - end process; - - p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux) - begin - if (r_pcr(0) = '0') then -- ca1 control - -- negative edge - ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0'); - else - -- positive edge - ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1'); - end if; - - if (r_pcr(4) = '0') then -- cb1 control - -- negative edge - cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0'); - else - -- positive edge - cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1'); - end if; - end process; - - p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2) - begin - ca2_int <= false; - if (r_pcr(3) = '0') then -- ca2 input - if (r_pcr(2) = '0') then -- ca2 edge - -- negative edge - ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0'); - else - -- positive edge - ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1'); - end if; - end if; - - cb2_int <= false; - if (r_pcr(7) = '0') then -- cb2 input - if (r_pcr(6) = '0') then -- cb2 edge - -- negative edge - cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0'); - else - -- positive edge - cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1'); - end if; - end if; - end process; - - p_ca2_cb2 : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - O_CA2 <= '0'; - O_CA2_OE_L <= '1'; - O_CB2 <= '0'; - O_CB2_OE_L <= '1'; - - ca_hs_sr <= '0'; - ca_hs_pulse <= '0'; - cb_hs_sr <= '0'; - cb_hs_pulse <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - -- ca - if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then - ca_hs_sr <= '1'; - elsif ca1_int then - ca_hs_sr <= '0'; - end if; - - if (phase = "00") then - ca_hs_pulse <= w_ora_hs or r_ira_hs; - end if; - - O_CA2_OE_L <= not r_pcr(3); -- ca2 output - case r_pcr(3 downto 1) is - when "000" => O_CA2 <= '0'; -- input - when "001" => O_CA2 <= '0'; -- input - when "010" => O_CA2 <= '0'; -- input - when "011" => O_CA2 <= '0'; -- input - when "100" => O_CA2 <= not (ca_hs_sr); -- handshake - when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse - when "110" => O_CA2 <= '0'; -- low - when "111" => O_CA2 <= '1'; -- high - when others => null; - end case; - - -- cb - if (phase = "00") and (w_orb_hs = '1') then - cb_hs_sr <= '1'; - elsif cb1_int then - cb_hs_sr <= '0'; - end if; - - if (phase = "00") then - cb_hs_pulse <= w_orb_hs; - end if; - - O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial - if (sr_drive_cb2 = '1') then -- serial output - O_CB2 <= sr_out; - else - case r_pcr(7 downto 5) is - when "000" => O_CB2 <= '0'; -- input - when "001" => O_CB2 <= '0'; -- input - when "010" => O_CB2 <= '0'; -- input - when "011" => O_CB2 <= '0'; -- input - when "100" => O_CB2 <= not (cb_hs_sr); -- handshake - when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse - when "110" => O_CB2 <= '0'; -- low - when "111" => O_CB2 <= '1'; -- high - when others => null; - end case; - end if; - end if; - end if; - end process; - O_CB1 <= sr_cb1_out; - O_CB1_OE_L <= sr_cb1_oe_l; - - p_ca_cb_irq : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - ca1_irq <= '0'; - ca2_irq <= '0'; - cb1_irq <= '0'; - cb2_irq <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - -- not pretty - if ca1_int then - ca1_irq <= '1'; - elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then - ca1_irq <= '0'; - end if; - - if ca2_int then - ca2_irq <= '1'; - else - if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or - (clear_irq(0) = '1') then - ca2_irq <= '0'; - end if; - end if; - - if cb1_int then - cb1_irq <= '1'; - elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then - cb1_irq <= '0'; - end if; - - if cb2_int then - cb2_irq <= '1'; - else - if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or - (clear_irq(3) = '1') then - cb2_irq <= '0'; - end if; - end if; - end if; - end if; - end process; - - p_input_reg : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - ca1_ip_reg <= '0'; - cb1_ip_reg <= '0'; - - ca2_ip_reg <= '0'; - cb2_ip_reg <= '0'; - - r_ira <= x"00"; - r_irb <= x"00"; - - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - -- we have a fast clock, so we can have input registers - ca1_ip_reg <= I_CA1; - cb1_ip_reg <= cb1_in_mux; - - ca2_ip_reg <= I_CA2; - cb2_ip_reg <= I_CB2; - - if (r_acr(0) = '0') then - r_ira <= I_PA; - else -- enable latching - if ca1_int then - r_ira <= I_PA; - end if; - end if; - - if (r_acr(1) = '0') then - r_irb <= I_PB; - else -- enable latching - if cb1_int then - r_irb <= I_PB; - end if; - end if; - end if; - end if; - end process; - - - p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb) - begin - -- data direction reg (ddr) 0 = input, 1 = output - O_PA <= r_ora; - O_PA_OE_L <= not r_ddra; - - if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well - O_PB_OE_L(7) <= '0'; -- an output if under t1 control - else - O_PB_OE_L(7) <= not (r_ddrb(7)); - end if; - - O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0); - O_PB <= r_orb; - - end process; - -- - -- Timer 1 - -- - p_timer1_done : process - variable done : boolean; - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - done := (t1c = x"0000"); - t1c_done <= done and (phase = "11"); - if (phase = "11") then - t1_reload_counter <= done and (r_acr(6) = '1'); - end if; - end if; - end process; - - p_timer1 : process - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - if t1_load_counter or (t1_reload_counter and phase = "11") then - t1c( 7 downto 0) <= r_t1l_l; - t1c(15 downto 8) <= r_t1l_h; - elsif (phase="11") then - t1c <= t1c - "1"; - end if; - - if t1_load_counter or t1_reload_counter then - t1c_active <= true; - elsif t1c_done then - t1c_active <= false; - end if; - - t1_toggle <= '0'; - if t1c_active and t1c_done then - t1_toggle <= '1'; - t1_irq <= '1'; - elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then - t1_irq <= '0'; - end if; - end if; - end process; - -- - -- Timer2 - -- - p_timer2_pb6_input : process - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - if (phase = "01") then -- leading edge p2_h - t2_pb6 <= I_PB(6); - t2_pb6_t1 <= t2_pb6; - end if; - end if; - end process; - - p_timer2_done : process - variable done : boolean; - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - done := (t2c = x"0000"); - t2c_done <= done and (phase = "11"); - if (phase = "11") then - t2_reload_counter <= done; - end if; - end if; - end process; - - p_timer2 : process - variable ena : boolean; - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - if (r_acr(5) = '0') then - ena := true; - else - ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge - end if; - - if t2_load_counter or (t2_reload_counter and phase = "11") then - -- not sure if t2c_reload should be here. Does timer2 just continue to - -- count down, or is it reloaded ? Reloaded makes more sense if using - -- it to generate a clock for the shift register. - t2c( 7 downto 0) <= r_t2l_l; - t2c(15 downto 8) <= r_t2l_h; - else - if (phase="11") and ena then -- or count mode - t2c <= t2c - "1"; - end if; - end if; - - t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11"); - - if t2_load_counter then - t2c_active <= true; - elsif t2c_done then - t2c_active <= false; - end if; - - - if t2c_active and t2c_done then - t2_irq <= '1'; - elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then - t2_irq <= '0'; - end if; - end if; - end process; - -- - -- Shift Register - -- - p_sr : process(RESET_L, CLK) - variable dir_out : std_logic; - variable ena : std_logic; - variable cb1_op : std_logic; - variable cb1_ip : std_logic; - variable use_t2 : std_logic; - variable free_run : std_logic; - variable sr_count_ena : boolean; - begin - if (RESET_L = '0') then - r_sr <= x"00"; - sr_drive_cb2 <= '0'; - sr_cb1_oe_l <= '1'; - sr_cb1_out <= '0'; - sr_strobe <= '1'; - sr_cnt <= "0000"; - sr_irq <= '0'; - sr_out <= '1'; - sr_off_delay <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - -- decode mode - dir_out := r_acr(4); -- output on cb2 - cb1_op := '0'; - cb1_ip := '0'; - use_t2 := '0'; - free_run := '0'; - - case r_acr(4 downto 2) is - when "000" => ena := '0'; - when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1'; - when "010" => ena := '1'; cb1_op := '1'; - when "011" => ena := '1'; cb1_ip := '1'; - when "100" => ena := '1'; use_t2 := '1'; free_run := '1'; - when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1'; - when "110" => ena := '1'; - when "111" => ena := '1'; cb1_ip := '1'; - when others => null; - end case; - - -- clock select - if (ena = '0') then - sr_strobe <= '1'; - else - if (cb1_ip = '1') then - sr_strobe <= I_CB1; - else - if (sr_cnt(3) = '0') and (free_run = '0') then - sr_strobe <= '1'; - else - if ((use_t2 = '1') and t2_sr_ena) or - ((use_t2 = '0') and (phase = "00")) then - sr_strobe <= not sr_strobe; - end if; - end if; - end if; - end if; - - -- latch on rising edge, shift on falling edge - if sr_write_ena then - r_sr <= load_data; - elsif (ena = '1') then -- use shift reg - - if (dir_out = '0') then - -- input - if (sr_cnt(3) = '1') or (cb1_ip = '1') then - if sr_strobe_rising then - r_sr(0) <= I_CB2; - elsif sr_strobe_falling then - r_sr(7 downto 1) <= r_sr(6 downto 0); - end if; - end if; - sr_out <= '1'; - else - -- output - if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then - if sr_strobe_falling then - r_sr(7 downto 1) <= r_sr(6 downto 0); - r_sr(0) <= r_sr(7); - sr_out <= r_sr(7); - end if; - else - sr_out <= '1'; - end if; - end if; - end if; - - sr_count_ena := sr_strobe_rising; - - if sr_write_ena or sr_read_ena then - -- some documentation says sr bit in IFR must be set as well ? - sr_cnt <= "1000"; - elsif sr_count_ena and (sr_cnt(3) = '1') then - sr_cnt <= sr_cnt + "1"; - end if; - - if (phase = "00") then - sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out - end if; - - if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then - sr_irq <= '1'; - elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then - sr_irq <= '0'; - end if; - - -- assign ops - sr_drive_cb2 <= dir_out; - sr_cb1_oe_l <= not cb1_op; - sr_cb1_out <= sr_strobe; - end if; - end if; - end process; - - p_sr_strobe_rise_fall : process - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - sr_strobe_t1 <= sr_strobe; - sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1'); - sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0'); - end if; - end process; - -- - -- Interrupts - -- - p_ier : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - r_ier <= "0000000"; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - if ier_write_ena then - if (load_data(7) = '1') then - -- set - r_ier <= r_ier or load_data(6 downto 0); - else - -- clear - r_ier <= r_ier and not load_data(6 downto 0); - end if; - end if; - end if; - end if; - end process; - - p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq, - cb1_irq, cb2_irq) - begin - r_ifr(7) <= final_irq; - r_ifr(6) <= t1_irq; - r_ifr(5) <= t2_irq; - r_ifr(4) <= cb1_irq; - r_ifr(3) <= cb2_irq; - r_ifr(2) <= sr_irq; - r_ifr(1) <= ca1_irq; - r_ifr(0) <= ca2_irq; - - O_IRQ_L <= not final_irq; - end process; - - p_irq : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - final_irq <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then - final_irq <= '0'; -- no interrupts - else - final_irq <= '1'; - end if; - end if; - end if; - end process; - - p_clear_irq : process(ifr_write_ena, load_data) - begin - clear_irq <= x"00"; - if ifr_write_ena then - clear_irq <= load_data; - end if; - end process; - -end architecture RTL; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/manage_amplitude.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/manage_amplitude.vhd deleted file mode 100644 index fd8766d6..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/manage_amplitude.vhd +++ /dev/null @@ -1,95 +0,0 @@ --- --- MANAGE_AMPLITUDE.vhd --- --- Manage the amplitude for each tone. --- --- Copyright (C)2001-2010 SEILEBOST --- All rights reserved. --- --- $Id: MANAGE_AMPLITUDE.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $ --- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity MANAGE_AMPLITUDE is - Port ( CLK : in std_logic; -- the system clock - CLK_DAC : in std_logic; -- the clok of DAC - CLK_TONE : in std_logic; -- the frequency of sound - CLK_NOISE : in std_logic; -- the noise - RST : in std_logic; -- reset - CLK_TONE_ENA : in std_logic; -- enable tone - CLK_NOISE_ENA : in std_logic; -- enable noise - AMPLITUDE : in std_logic_vector(4 downto 0); -- value from register - AMPLITUDE_E : in std_logic_vector(3 downto 0); -- value from envelope - OUT_DAC : out std_logic ); -end MANAGE_AMPLITUDE; - -architecture Behavioral of MANAGE_AMPLITUDE is - - signal AMPLITUDE_TMP : std_logic_vector(3 downto 0); - signal IN_DATA : std_logic_vector(7 downto 0); - - COMPONENT DAC is Port ( CLK_DAC : in std_logic; - RST : in std_logic; - IN_DAC : in std_logic_vector(7 downto 0); - OUT_DAC : out std_logic ); - END COMPONENT; - - -begin - --- Convertisseur numérique analogique : méthode sigma delta -U_DAC : DAC PORT MAP ( CLK_DAC => CLK_DAC, - RST => RST, - IN_DAC => IN_DATA, - OUT_DAC => OUT_DAC); - --- Calcule de l'amplitude à générer par le DAC - PROCESS(CLK, RST, AMPLITUDE_TMP, AMPLITUDE_E) - variable mix_tone_noise : std_logic; - BEGIN - if (RST = '1') then -- reset - AMPLITUDE_TMP <= "0000"; - IN_DATA <= "00000000"; - elsif (CLK'event and CLK = '1') then -- edge clock - -- Note that this means that if both tone and noise are disabled, the output */ - -- is 1, not 0, and can be modulated changing the volume. */ - mix_tone_noise := (CLK_TONE or CLK_TONE_ENA) AND (CLK_NOISE or CLK_NOISE_ENA); - if (mix_tone_noise = '1') then - if (AMPLITUDE(4) = '0') then -- Utilisation de la valeur du registre - AMPLITUDE_TMP <= AMPLITUDE(3 downto 0); - else -- Utilisation de la valeur de l'enveloppe - AMPLITUDE_TMP <= AMPLITUDE_E; - end if; - else - AMPLITUDE_TMP <= "0000"; - end if; - - -- Each amplitude has an 1.5 db step from previous amplitude - CASE AMPLITUDE_TMP IS - when "0000" => IN_DATA <= "00000000"; -- 0 - when "0001" => IN_DATA <= "00010110"; -- 22 - when "0010" => IN_DATA <= "00011010"; -- 26 - when "0011" => IN_DATA <= "00011111"; -- 31 - when "0100" => IN_DATA <= "00100101"; -- 37 - when "0101" => IN_DATA <= "00101100"; -- 44 - when "0110" => IN_DATA <= "00110100"; -- 52 - when "0111" => IN_DATA <= "00111110"; -- 62 - when "1000" => IN_DATA <= "01001010"; -- 74 - when "1001" => IN_DATA <= "01011000"; -- 88 - when "1010" => IN_DATA <= "01101001"; -- 105 - when "1011" => IN_DATA <= "01110101"; -- 125 - when "1100" => IN_DATA <= "10011001"; -- 149 - when "1101" => IN_DATA <= "10110001"; -- 177 - when "1110" => IN_DATA <= "11010010"; -- 210 - when "1111" => IN_DATA <= "11111111"; -- 255 - when OTHERS => NULL; - END CASE; - end if; - - END PROCESS; - -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/memmap.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/memmap.vhd deleted file mode 100644 index 416a6a47..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/memmap.vhd +++ /dev/null @@ -1,78 +0,0 @@ --- --- memmap.vhd --- --- Manage offset for read ula --- --- Copyright (C)2001 - 2005 SEILEBOST --- All rights reserved. --- --- $Id: memmap.vhd, v0.02 2005/01/01 00:00:00 SEILEBOST $ --- --- TODO : --- Remark : - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; ---use IEEE.std_logic_arith.all; ---use IEEE.numeric_std.all; - -entity memmap is -port ( TXTHIR_SEL : in std_logic; - DBLHGT_SEL : in std_logic; - FORCETXT : in std_logic; - CPT_H : in std_logic_vector(6 downto 0); - CPT_V : in std_logic_vector(8 downto 0); - VAP1 : out std_logic_vector(15 downto 0); - CHROWCNT : out std_logic_vector(2 downto 0); - TXTHIR_DEC : out std_logic - ); -end entity memmap; - -architecture memmap_arch of memmap is - -signal lDBLHGT_EN : std_logic; -- ENABLE DOUBLE HEIGT -signal lTXTHIR_DEC : std_logic; -- MODE TEXT / HIRES -signal lCPT_V_TMP : std_logic_vector(8 downto 0); -- VERTICAL COUNTER -signal lCPT_V_8_TMP : std_logic_vector(8 downto 0); -- VERTICAL COUNTER DIVIDE OR NOT BY 8 -signal lVAP1 : std_logic_vector(12 downto 0); -- VIDEO ADDRESS PHASE 1 -signal lOFFSCR : std_logic_vector(15 downto 0); -- OFFSET SCREEN -signal ltmpBy10 : std_logic_vector(12 downto 0); -- Using to mult by 10 - - -begin - -- local signal - lTXTHIR_DEC <= (TXTHIR_SEL and FORCETXT); - lDBLHGT_EN <= (DBLHGT_SEL and lTXTHIR_DEC); - - -- Compute video adress phase 1 - lCPT_V_TMP <= '0'&CPT_V(8 downto 1) when lDBLHGT_EN = '1' else CPT_V(8 downto 0); - - -- divide by 8 if necessary : erreur sur la manière de diviser par 8? 03/02/2010 - --lCPT_V_8_TMP <= lCPT_V_TMP when lTXTHIR_DEC = '1' else lCPT_V_TMP(8 downto 3) & "000"; - - lCPT_V_8_TMP <= lCPT_V_TMP when lTXTHIR_DEC = '1' else "000" & lCPT_V_TMP(8 downto 3) ; - - -- 03/02/2010 : Le bonne blague : après la phase de synthese, le 'bench' ne - -- fonctionnait plus. Le synthetiseur de XILINX avait utilisé un multiplieur 18x18 - -- pour générer la multiplication par 10 et la simulation a repris cela. Or le - -- multiplier a une latence de 1 µs (latence de l'horloge PHI2) d'où les problèmes - -- durant les simulations (génération de 2 fois de suite de l'adresse vidéo) - -- On revient à la bonne vieille méthode Bx10 = Bx8 + Bx2 !! - --lVAP1 <= ("0000000" & CPT_H) + (lCPT_V_8_TMP * "1010"); - ltmpBy10 <= ("0" & lCPT_V_8_TMP & "000") + ("000" & lCPT_V_8_TMP & "0"); - -- le décalage en Y : il faut multiplier par 40 donc 4 * ltmpBy10 - lVAP1 <= ("00000" & CPT_H) + (ltmpBy10(10 downto 0) & "00"); - lOFFSCR <= X"A000" when lTXTHIR_DEC = '1' else X"BB80"; - VAP1 <= ("000" & lVAP1) + lOFFSCR; - - -- Compute character row counter - CHROWCNT <= CPT_V(2 downto 0) when lDBLHGT_EN = '1' else CPT_V(3 downto 1); - - -- Output signal for texte/hires mode decode - TXTHIR_DEC <= lTXTHIR_DEC; - -end architecture memmap_arch; - - - diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/mist_io.v b/Computer_MiST/Oric Atmos_MiST/rtl/mist_io.v deleted file mode 100644 index ad233a3b..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/mist_io.v +++ /dev/null @@ -1,491 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoubler_disable, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input sd_rd, - input sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - input ps2_caps_led, - - // ARM -> FPGA download - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output ioctl_wr, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] b_data; -reg [6:0] sbuf; -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; -assign ypbpr = but_sw[5]; - -wire [7:0] spi_dout = { sbuf, SPI_DI}; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; - -// drive MISO only when transmitting core id -always@(negedge SPI_SCK) begin - if(!CONF_DATA0) begin - // first byte returned is always core type, further bytes are - // command dependent - if(byte_cnt == 0) begin - spi_do <= core_type[~bit_cnt]; - - end else begin - case(cmd) - // reading config string - 8'h14: begin - // returning a byte from string - if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; - else spi_do <= 0; - end - - // reading sd card status - 8'h16: begin - if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; - else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; - else spi_do <= 0; - end - - // reading sd card write data - 8'h18: - spi_do <= b_data[~bit_cnt]; - - // reading keyboard LED status - 8'h1f: - spi_do <= kbd_led[~bit_cnt]; - - default: - spi_do <= 0; - endcase - end - end -end - -reg b_wr2,b_wr3; -always @(negedge clk_sys) begin - b_wr3 <= b_wr2; - sd_buff_wr <= b_wr3; -end - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - - if(CONF_DATA0) begin - b_wr2 <= 0; - bit_cnt <= 0; - byte_cnt <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - end else begin - b_wr2 <= 0; - - sbuf <= spi_dout[6:0]; - bit_cnt <= bit_cnt + 1'd1; - if(bit_cnt == 5) begin - if (byte_cnt == 0) sd_buff_addr <= 0; - if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; - if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; - end - - // finished reading command byte - if(bit_cnt == 7) begin - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - if(byte_cnt == 0) begin - cmd <= spi_dout; - - if(spi_dout == 8'h19) begin - sd_ack_conf <= 1; - sd_buff_addr <= 0; - end - if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin - sd_ack <= 1; - sd_buff_addr <= 0; - end - if(spi_dout == 8'h18) b_data <= sd_buff_din; - - mount_strobe <= 0; - - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_dout; - 8'h02: joystick_0 <= spi_dout; - 8'h03: joystick_1 <= spi_dout; - - // store incoming ps2 mouse bytes - 8'h04: begin - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_dout; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_dout; - b_wr2 <= 1; - end - - 8'h18: b_data <= sd_buff_din; - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; - else if(byte_cnt == 2) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; - end else if(byte_cnt == 3) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; - end - end - - // notify image selection - 8'h1c: mount_strobe <= 1; - - // send image info - 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; - - // status, 32bit version - 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; - default: ; - endcase - end - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - rclk <= 0; - - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // increase target address after write - if(rclk) addr <= addr + 1'd1; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - addr <= 0; - ioctl_download <= 1; - end else begin - addr_w <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - rclk <= 1; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -assign ioctl_wr = |ioctl_wrd; -reg [1:0] ioctl_wrd; - -always@(negedge clk_sys) begin - reg rclkD, rclkD2; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wrd<= {ioctl_wrd[0],1'b0}; - - if(rclkD & ~rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wrd <= 2'b11; - end -end - -endmodule diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/noise_generator.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/noise_generator.vhd deleted file mode 100644 index 83f80459..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/noise_generator.vhd +++ /dev/null @@ -1,80 +0,0 @@ --- --- NOISE_GENERATOR.vhd --- --- Generator a noise tone. --- --- Copyright (C)2001 SEILEBOST --- All rights reserved. --- --- $Id: NOISE_GENERATOR.vhd, v0.41 2002/01/03 00:00:00 SEILEBOST $ --- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity noise_generator is - Port ( CLK : in std_logic; - RST : in std_logic; - --WR : in std_logic; - --CS : in std_logic; - DATA : in std_logic_vector(4 downto 0); - CLK_N : out std_logic -- pseudo clock - ); -end noise_generator; - -architecture Behavioral of noise_generator is - -SIGNAL COUNT : std_logic_vector(4 downto 0); -signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); ---SIGNAL ShiftEn : std_logic; ---SIGNAL FillSel : std_logic; ---SIGNAL DataIn : std_logic; ---SIGNAL lData : std_logic_vector(4 downto 0); - ---COMPONENT i_pn_gen port (clk, ShiftEn, FillSel, DataIn_i, RESET : in std_logic; --- pn_out_i : out std_logic); ---END COMPONENT; - -begin - ---U_IPNG : I_PN_GEN PORT MAP ( CLK => CLK, --- ShiftEn => ShiftEn, --- FillSel => FillSel, --- RESET => RST, --- DataIn_i => DataIn, --- pn_out_i => CLK_N); - - -- The noise generator - PROCESS(CLK,RST) - variable COUNT_MAX : std_logic_vector(4 downto 0); - variable poly17_zero : std_logic; - BEGIN - if (RST = '1') then - poly17 <= (others => '0'); - elsif ( CLK'event and CLK = '1') then - if (DATA = "00000") then - COUNT_MAX := "00000"; - else - COUNT_MAX := (DATA - "1"); - end if; - - -- Manage the polynome = 0 to regenerate another sequence - poly17_zero := '0'; - if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; - - if (COUNT >= COUNT_MAX) then - COUNT <= "00000"; - poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) - & poly17(16 downto 1); - else - COUNT <= (COUNT + "1"); - end if; - end if; - - END PROCESS; - - CLK_N <= poly17(0); - -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/oricatmos.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/oricatmos.vhd deleted file mode 100644 index 997f15e7..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/oricatmos.vhd +++ /dev/null @@ -1,398 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.ALL; - use ieee.numeric_std.all; - -entity oricatmos is -port ( - CLOCK_27 : in std_logic; - LED : out std_logic; - VGA_R : out std_logic_vector(5 downto 0); - VGA_G : out std_logic_vector(5 downto 0); - VGA_B : out std_logic_vector(5 downto 0); - VGA_HS : out std_logic; - VGA_VS : out std_logic; - SPI_SCK : in std_logic; - SPI_DI : in std_logic; - SPI_DO : out std_logic; - SPI_SS3 : in std_logic; - CONF_DATA0 : in std_logic; - AUDIO_L : out std_logic; - AUDIO_R : out std_logic -); -end; - -architecture RTL of oricatmos is - signal VGA_R_O : std_logic_vector(3 downto 0); - signal VGA_G_O : std_logic_vector(3 downto 0); - signal VGA_B_O : std_logic_vector(3 downto 0); - signal hsync : std_logic; - signal vsync : std_logic; - signal hq2x : std_logic; - signal buttons : std_logic_vector(1 downto 0); - signal switches : std_logic_vector(1 downto 0); - signal status : std_logic_vector(31 downto 0); - signal scandoubler_disable : std_logic; - signal scanlines : std_logic_vector(1 downto 0); - signal ypbpr : std_logic; - signal ps2Clk : std_logic; - signal ps2Data : std_logic; - signal loc_reset_n : std_logic; --active low - signal reset : std_logic := '1'; - signal clk24 : std_logic := '0'; - signal clk12 : std_logic := '0'; - signal clk6 : std_logic := '0'; - signal pll_locked : std_logic := '0'; - signal CPU_ADDR : std_logic_vector(23 downto 0); - signal CPU_DI : std_logic_vector( 7 downto 0); - signal CPU_DO : std_logic_vector( 7 downto 0); - signal cpu_rw : std_logic; - signal cpu_irq : std_logic; - signal ad : std_logic_vector(15 downto 0); - signal via_pa_out_oe : std_logic_vector( 7 downto 0); - signal via_pa_in : std_logic_vector( 7 downto 0); - signal via_pa_out : std_logic_vector( 7 downto 0); - signal via_cb1_out : std_logic; - signal via_cb1_oe_l : std_logic; - signal via_cb2_out : std_logic; - signal via_cb2_oe_l : std_logic; - signal via_in : std_logic_vector( 7 downto 0); - signal via_out : std_logic_vector( 7 downto 0); - signal via_oe_l : std_logic_vector( 7 downto 0); - signal VIA_DO : std_logic_vector( 7 downto 0); - signal KEY_ROW : std_logic_vector( 7 downto 0); - signal psg_bdir : std_logic; - signal PSG_OUT : std_logic_vector( 7 downto 0); - signal ula_phi2 : std_logic; - signal ula_CSIOn : std_logic; - signal ula_CSIO : std_logic; - signal ula_CSROMn : std_logic; - signal SRAM_DO : std_logic_vector( 7 downto 0); - signal ula_AD_SRAM : std_logic_vector(15 downto 0); - signal ula_CE_SRAM : std_logic; - signal ula_OE_SRAM : std_logic; - signal ula_WE_SRAM : std_logic; - signal ula_LE_SRAM : std_logic; - signal ula_CLK_4 : std_logic; - signal ula_IOCONTROL : std_logic; - signal ula_VIDEO_R : std_logic; - signal ula_VIDEO_G : std_logic; - signal ula_VIDEO_B : std_logic; - signal ula_SYNC : std_logic; - signal ROM_DO : std_logic_vector( 7 downto 0); - signal hs_int : std_logic; - signal vs_int : std_logic; - signal dummy : std_logic_vector( 3 downto 0) := (others => '0'); - signal s_cmpblk_n_out : std_logic; - - - constant CONF_STR : string := - "ORIC;;O89,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T6,Reset;"; - - function to_slv(s: string) return std_logic_vector is - constant ss: string(1 to s'length) := s; - variable rval: std_logic_vector(1 to 8 * s'length); - variable p: integer; - variable c: integer; - begin - for i in ss'range loop - p := 8 * i; - c := character'pos(ss(i)); - rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); - end loop; - return rval; - end function; - - component mist_io - generic ( STRLEN : integer := 0 ); - port ( - clk_sys :in std_logic; - SPI_SCK, CONF_DATA0, SPI_DI :in std_logic; - SPI_DO : out std_logic; - conf_str : in std_logic_vector(8*STRLEN-1 downto 0); - buttons : out std_logic_vector(1 downto 0); - switches : out std_logic_vector(1 downto 0); - joystick_0 : out std_logic_vector(7 downto 0); - joystick_1 : out std_logic_vector(7 downto 0); - status : out std_logic_vector(31 downto 0); - scandoubler_disable, ypbpr : out std_logic; - ps2_kbd_clk : out std_logic; - ps2_kbd_data : out std_logic - ); - end component mist_io; - - component video_mixer - generic ( LINE_LENGTH : integer := 384; HALF_DEPTH : integer := 1 ); - port ( - clk_sys, ce_pix, ce_pix_actual : in std_logic; - SPI_SCK, SPI_SS3, SPI_DI : in std_logic; - - scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic; - scanlines : in std_logic_vector(1 downto 0); - R, G, B : in std_logic_vector(2 downto 0); - HSync, VSync, line_start, mono : in std_logic; - - VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); - VGA_VS, VGA_HS : out std_logic - ); - end component video_mixer; - -begin - inst_pll : entity work.pll - port map ( - areset => open, - inclk0 => CLOCK_27, - c0 => clk24, - c1 => clk12, - c2 => clk6, - locked => pll_locked - ); - -loc_reset_n <= pll_locked; ---reset <= not status(0) or status(6) or buttons(1); - inst_cpu : entity work.T65 - port map ( - Mode => "00", - Res_n => loc_reset_n, - Enable => '1', - Clk => ula_phi2, - Rdy => '1', - Abort_n => '1', - IRQ_n => cpu_irq, - NMI_n => '1', - SO_n => '1', - R_W_n => cpu_rw, - Sync => open, - EF => open, - MF => open, - XF => open, - ML_n => open, - VP_n => open, - VDA => open, - VPA => open, - A => CPU_ADDR, - DI => CPU_DI, - DO => CPU_DO - ); --- place Rom in LE and we can use 48kb Memory --- inst_rom : entity work.rom --- port map ( --- clk => clk24, --- ADDR => CPU_ADDR(13 downto 0), --- DATA => ROM_DO --- ); --- place in BRAM and reduce Memory to 16kb see file ram48k - inst_rom : entity work.rrom - port map ( - clock => clk24, - address => CPU_ADDR(13 downto 0), - q => ROM_DO - ); - -ad(15 downto 0) <= ula_AD_SRAM when ula_phi2 = '0' else CPU_ADDR(15 downto 0); - - inst_ram : entity work.ram48k - port map( - clk => clk24, - cs => ula_CE_SRAM, - oe => ula_OE_SRAM, - we => ula_WE_SRAM, - addr => ad, - di => CPU_DO, - do => SRAM_DO - ); - - inst_ula : entity work.ULA - port map ( - RESETn => loc_reset_n, - CLK => clk24, - CLK_4 => ula_CLK_4, - RW => cpu_rw, - ADDR => CPU_ADDR(15 downto 0), - MAPn => '1', - DB => SRAM_DO, - CSROMn => ula_CSROMn, - CSIOn => ula_CSIOn, - SRAM_AD => ula_AD_SRAM, - SRAM_OE => ula_OE_SRAM, - SRAM_CE => ula_CE_SRAM, - SRAM_WE => ula_WE_SRAM, - LATCH_SRAM => ula_LE_SRAM, - PHI2 => ula_PHI2, - R => ULA_VIDEO_R, - G => ULA_VIDEO_G, - B => ULA_VIDEO_B, - SYNC => ULA_SYNC, - HSYNC => hs_int, - VSYNC => vs_int - ); - - vmixer : video_mixer - generic map( - HALF_DEPTH => 1, - LINE_LENGTH => 480 - ) - - port map ( - clk_sys => clk24, - ce_pix => clk6, - ce_pix_actual => clk6, - SPI_SCK => SPI_SCK, - SPI_SS3 => SPI_SS3, - SPI_DI => SPI_DI, - hq2x => hq2x, - ypbpr => ypbpr, - ypbpr_full => '1', - scanlines => scanlines, - scandoubler_disable => scandoubler_disable, - R => ULA_VIDEO_R & ULA_VIDEO_R & ULA_VIDEO_R, - G => ULA_VIDEO_G & ULA_VIDEO_G & ULA_VIDEO_G, - B => ULA_VIDEO_B & ULA_VIDEO_B & ULA_VIDEO_B, - HSync => hs_int, - VSync => vs_int, - line_start => '0', - mono => '0', - VGA_R => VGA_R, - VGA_G => VGA_G, - VGA_B => VGA_B, - VGA_VS => VGA_VS, - VGA_HS => VGA_HS -); - -scanlines(1) <= '1' when status(9 downto 8) = "11" and scandoubler_disable = '0' else '0'; -scanlines(0) <= '1' when status(9 downto 8) = "10" and scandoubler_disable = '0' else '0'; -hq2x <= '1' when status(9 downto 8) = "01" else '0'; - -mist_io_inst : mist_io - generic map (STRLEN => CONF_STR'length) - port map ( - clk_sys => clk24, - SPI_SCK => SPI_SCK, - CONF_DATA0 => CONF_DATA0, - SPI_DI => SPI_DI, - SPI_DO => SPI_DO, - conf_str => to_slv(CONF_STR), - buttons => buttons, - switches => switches, - scandoubler_disable => scandoubler_disable, - ypbpr => ypbpr, - status => status, - ps2_kbd_clk => ps2Clk, - ps2_kbd_data => ps2Data -); - -ula_CSIO <= not ula_CSIOn; - - inst_via : entity work.M6522 - port map ( - I_RS => CPU_ADDR(3 downto 0), - I_DATA => CPU_DO(7 downto 0), - O_DATA => VIA_DO, - O_DATA_OE_L => open, - I_RW_L => cpu_rw, - I_CS1 => ula_CSIO, - I_CS2_L => ula_IOCONTROL, - O_IRQ_L => cpu_irq, -- note, not open drain - I_CA1 => '1', -- PRT_ACK - I_CA2 => '1', -- psg_bdir - O_CA2 => psg_bdir, -- via_ca2_out - O_CA2_OE_L => open, - I_PA => via_pa_in, - O_PA => via_pa_out, - O_PA_OE_L => via_pa_out_oe, --- I_CB1 => K7_TAPEIN, - I_CB1 => '0', - O_CB1 => via_cb1_out, - O_CB1_OE_L => via_cb1_oe_l, - I_CB2 => '1', - O_CB2 => via_cb2_out, - O_CB2_OE_L => via_cb2_oe_l, - I_PB => via_in, - O_PB => via_out, - O_PB_OE_L => via_oe_l, - RESET_L => loc_reset_n, - I_P2_H => ula_phi2, - ENA_4 => '1', - CLK => ula_CLK_4 - ); - - inst_key : entity work.keyboard - port map( - CLK => clk24, - RESET => '0', -- active high reset - PS2CLK => ps2Clk, - PS2DATA => ps2Data, - COL => via_out(2 downto 0), - ROWbit => KEY_ROW - ); - -via_in <= x"F7" when (KEY_ROW or VIA_PA_OUT) = x"FF" else x"FF"; - - inst_psg : entity work.YM2149 - port map ( - I_DA => via_pa_out, - O_DA => via_pa_in, - O_DA_OE_L => open, - I_A9_L => '0', - I_A8 => '1', - I_BDIR => via_cb2_out, - I_BC2 => '1', - I_BC1 => psg_bdir, - I_SEL_L => '1', - O_AUDIO => PSG_OUT, - RESET_L => loc_reset_n, - ENA => '1', - CLK => ula_PHI2 - ); - - inst_dacl : entity work.DAC - port map ( - CLK_DAC => clk24, - RST => loc_reset_n, - IN_DAC => PSG_OUT, - OUT_DAC => AUDIO_L - ); - - inst_dacr : entity work.DAC - port map ( - CLK_DAC => clk24, - RST => loc_reset_n, - IN_DAC => PSG_OUT, - OUT_DAC => AUDIO_R - ); - -ula_IOCONTROL <= '0'; - - process - begin - wait until rising_edge(clk24); - -- expansion port - if cpu_rw = '1' and ula_IOCONTROL = '1' and ula_CSIOn = '0' then - CPU_DI <= SRAM_DO; - -- Via - elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_CSIOn = '0' and ula_LE_SRAM = '0' then - CPU_DI <= VIA_DO; - -- ROM - elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_CSROMn = '0' then - CPU_DI <= ROM_DO; - -- Read data - elsif cpu_rw = '1' and ula_IOCONTROL = '0' and ula_phi2 = '1' and ula_LE_SRAM = '0' then - cpu_di <= SRAM_DO; - end if; - end process; - - ------------------------------------------------------------ - -- K7 PORT - ------------------------------------------------------------ --- K7_TAPEOUT <= via_out(7); --- K7_REMOTE <= via_out(6); --- K7_AUDIOOUT <= AUDIO_OUT; - - ------------------------------------------------------------ - -- PRINTER PORT - ------------------------------------------------------------ --- PRT_DATA <= via_pa_out; --- PRT_STR <= via_out(4); - LED <= '1'; -end RTL; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/osd.v b/Computer_MiST/Oric Atmos_MiST/rtl/osd.v deleted file mode 100644 index c62c10af..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/osd.v +++ /dev/null @@ -1,179 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [7:0] osd_byte; -always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; - -wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/pack_oricatmos.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/pack_oricatmos.vhd deleted file mode 100644 index e8b8e797..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/pack_oricatmos.vhd +++ /dev/null @@ -1,270 +0,0 @@ --- --- A simulation model of ORIC hardware --- Copyright (c) seilebost - January 2009 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email seilebost@free.fr --- --- --- Revision list --- --- version 001 initial release - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -package pkg_oric is - component T65 - port( - Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816 - Res_n : in std_logic; - Enable : in std_logic; - Clk : in std_logic; - Rdy : in std_logic; - Abort_n : in std_logic; - IRQ_n : in std_logic; - NMI_n : in std_logic; - SO_n : in std_logic; - R_W_n : out std_logic; - Sync : out std_logic; - EF : out std_logic; - MF : out std_logic; - XF : out std_logic; - ML_n : out std_logic; - VP_n : out std_logic; - VDA : out std_logic; - VPA : out std_logic; - A : out std_logic_vector(23 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); - end component; - - component ULA - port ( - CLK : in std_logic; - PHI2 : out std_logic; - CLK_4 : out std_logic; - RW : in std_logic; - RESETn : in std_logic; - MAPn : in std_logic; - DB : in std_logic_vector(7 downto 0); - AD : in std_logic_vector(15 downto 0); - AD_RAM : out std_logic_vector(7 downto 0); - AD_SRAM : out std_logic_vector(15 downto 0); - OE_SRAM : out std_logic; - CE_SRAM : out std_logic; - WE_SRAM : out std_logic; - LATCH_SRAM : out std_logic; - RASn : out std_logic; - CASn : out std_logic; - MUX : out std_logic; - RW_RAM : out std_logic; - CSIOn : out std_logic; - CSROMn : out std_logic; - CSRAMn : out std_logic; - R : out std_logic; - G : out std_logic; - B : out std_logic; - SYNC : out std_logic - ); - end component; - - component M6522 is - port ( - RS : in std_logic_vector(3 downto 0); - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_OUT_OE_L : out std_logic; - - RW_L : in std_logic; - CS1 : in std_logic; - CS2_L : in std_logic; - - IRQ_L : out std_logic; -- note, not open drain - - CA1_IN : in std_logic; - CA2_IN : in std_logic; - CA2_OUT : out std_logic; - CA2_OUT_OE_L : out std_logic; - - PA_IN : in std_logic_vector(7 downto 0); - PA_OUT : out std_logic_vector(7 downto 0); - PA_OUT_OE_L : out std_logic_vector(7 downto 0); - - -- port b - CB1_IN : in std_logic; - CB1_OUT : out std_logic; - CB1_OUT_OE_L : out std_logic; - - CB2_IN : in std_logic; - CB2_OUT : out std_logic; - CB2_OUT_OE_L : out std_logic; - - PB_IN : in std_logic_vector(7 downto 0); - PB_OUT : out std_logic_vector(7 downto 0); - PB_OUT_OE_L : out std_logic_vector(7 downto 0); - - RESET_L : in std_logic; - P2_H : in std_logic; -- high for phase 2 clock ____----__ - CLK_4 : in std_logic -- 4x system clock (4HZ) _-_-_-_-_- - ); - end component; - - component AY3819X - port ( - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - O_DATA_OE_L : out std_logic; - RESET : in std_logic; - CLOCK : in std_logic; - CLOCK_DAC : in std_logic; - BDIR : in std_logic; - BC1 : in std_logic; - BC2 : in std_logic; - IOA : inout std_logic_vector(7 downto 0); - IOB : inout std_logic_vector(7 downto 0); - AnalogA : out std_logic; - AnalogB : out std_logic; - AnalogC : out std_logic - ); - end component; - - component ORIC_PS2_IF - port ( - PS2_CLK : in std_logic; - PS2_DATA : in std_logic; - - COL_IN : in std_logic_vector(7 downto 0); - ROW_IN : in std_logic_vector(7 downto 0); - RESTORE : out std_logic; - - RESET_L : in std_logic; - ENA_1MHZ : in std_logic; - P2_H : in std_logic; -- high for phase 2 clock ____----__ - CLK_4 : in std_logic -- 4x system clock (4HZ) _-_-_-_-_- - ); - end component; - - component ORIC_CHAR_ROM - port ( - CLK : in std_logic; - ADDR : in std_logic_vector(11 downto 0); - DATA : out std_logic_vector(7 downto 0) - ); - end component; - - component ORIC_BASIC_ROM - port ( - CLK : in std_logic; - ADDR : in std_logic_vector(12 downto 0); - DATA : out std_logic_vector(7 downto 0) - ); - end component; - - component ORIC_KERNAL_ROM - port ( - CLK : in std_logic; - ADDR : in std_logic_vector(12 downto 0); - DATA : out std_logic_vector(7 downto 0) - ); - end component; - - component ORIC_RAMS - port ( - V_ADDR : in std_logic_vector(9 downto 0); - DIN : in std_logic_vector(7 downto 0); - DOUT : out std_logic_vector(7 downto 0); - V_RW_L : in std_logic; - CS_L : in std_logic; -- used for write enable gate only - CLK : in std_logic - ); - end component; - - component keyboard - port ( - CLK : in std_logic; - RESET : in std_logic; - PS2CLK : in std_logic; - PS2DATA : in std_logic; - COL : in std_logic_vector(2 downto 0); - ROWbit : out std_logic_vector(7 downto 0) - ); - end component; - - component file_log - generic ( - log_file: string := "res.log" - ); - port( - CLK : in std_logic; - RST : in std_logic; - x1 : in std_logic_vector(7 downto 0); - x2 : in std_logic_vector(7 downto 0); - x3 : in std_logic_vector(15 downto 0); - x4 : in std_logic_vector(2 downto 0); - x5 : in std_logic - ); - end component; - - component psg_log - generic ( - log_psg: string := "psg.log" - ); - port( - CLK : in std_logic; - RST : in std_logic; - x1 : in std_logic - ); - end component; - - component ula_log - generic ( - log_ula: string := "ula.log" - ); - port( - CLK : in std_logic; - RST : in std_logic; - x1 : in std_logic_vector(7 downto 0); - x2 : in std_logic_vector(15 downto 0); - x3 : in std_logic - ); - end component; -end pkg_oric; - -package body pkg_ORIC is - -end pkg_oric; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/pack_ula.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/pack_ula.vhd deleted file mode 100644 index 74b26f39..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/pack_ula.vhd +++ /dev/null @@ -1,135 +0,0 @@ --- --- ula_pkg.vhd --- --- Package of ULA --- --- Copyright (C)2001 - 2005 SEILEBOST --- All rights reserved. --- --- $Id: ula_pkg.vhd, v0.02 2005/01/01 00:00:00 SEILEBOST $ --- --- TODO : --- Remark : -library ieee; -use ieee.std_logic_1164.all; - -package pack_ula is - - component video port ( - RESETn : in std_logic; - CLK_PIXEL : in std_logic; - CLK_FLASH : in std_logic; - -- delete 17/11/2009 FLASH_SEL : in std_logic; - BLANKINGn : in std_logic; - RELOAD_SEL : in std_logic; - DATABUS : in std_logic_vector(7 downto 0); - ATTRIB_DEC : in std_logic; - DATABUS_EN : in std_logic; - LDFROMBUS : in std_logic; - LD_REG_0 : in std_logic; - RELD_REG : in std_logic; - CHROWCNT : in std_logic_vector(2 downto 0); - RGB : out std_logic_vector(2 downto 0); - FREQ_SEL : out std_logic; - TXTHIR_SEL : out std_logic; - isAttrib : out std_logic; - DBLSTD_SEL : out std_logic; - VAP2 : out std_logic_vector(15 downto 0) ); - end component; - - component iodecode port ( - RESETn : in std_logic; - CLK_1 : in std_logic; - ADDR : in std_logic_vector(15 downto 0); - ADDR_LE : in std_logic; - MAPn : in std_logic; - CSROMn : out std_logic; - CSRAMn : out std_logic; - CSIOn : out std_logic); - end component; - - component memmap port ( - TXTHIR_SEL : in std_logic; - DBLHGT_SEL : in std_logic; - FORCETXT : in std_logic; - CPT_H : in std_logic_vector(6 downto 0); - CPT_V : in std_logic_vector(8 downto 0); - VAP1 : out std_logic_vector(15 downto 0); - CHROWCNT : out std_logic_vector(2 downto 0); - TXTHIR_DEC : out std_logic ); - end component; - - component vag port ( - CLK_1 : in std_logic; - RESETn : in std_logic; - FREQ_SEL : in std_logic; - CPT_H : out std_logic_vector(6 downto 0); - CPT_V : out std_logic_vector(8 downto 0); - RELOAD_SEL : out std_logic; - FORCETXT : out std_logic; - CLK_FLASH : out std_logic; - COMPSYNC : out std_logic; - BLANKINGn : out std_logic); - end component; - - component ctrlseq port ( - RESETn : in std_logic; - CLK_24 : in std_logic; - TXTHIR_DEC : in std_logic; - isAttrib : in std_logic; - iRW : in std_logic; - CSRAMn : in std_logic; - CLK_1_CPU : out std_logic; - CLK_4 : out std_logic; - CLK_6 : out std_logic; - VA1L : out std_logic; - VA1R : out std_logic; - VA1C : out std_logic; - VA2L : out std_logic; - VA2R : out std_logic; - VA2C : out std_logic; - BAC : out std_logic; - BAL : out std_logic; - RAS : out std_logic; - CAS : out std_logic; - MUX : out std_logic; - oRW : out std_logic; - ATTRIB_DEC : out std_logic; - LD_REG_0 : out std_logic; - LD_REG : out std_logic; - LDFROMBUS : out std_logic; - DATABUS_EN : out std_logic; --- ajout du 09/02/09 - BAOE : out std_logic; --- ajout du 03/04/09 - SRAM_CE : out std_logic; - SRAM_OE : out std_logic; - SRAM_WE : out std_logic; - LATCH_SRAM : out std_logic - ); - end component; - - component addmemux port ( - RESETn : in std_logic; - VAP1 : in std_logic_vector(15 downto 0); - VAP2 : in std_logic_vector(15 downto 0); - BAP : in std_logic_vector(15 downto 0); - VA1L : in std_logic; - VA1R : in std_logic; - VA1C : in std_logic; - VA2L : in std_logic; - VA2R : in std_logic; - VA2C : in std_logic; - BAC : in std_logic; - BAL : in std_logic; - AD_DYN : out std_logic_vector(15 downto 0) ); - end component; - - component gen_clock port ( - RESETn : in std_logic; - CLK_12 : in std_logic; - CLK_24 : out std_logic; - CLK_12_INT : out std_logic; - CLK_PIXEL_INT : out std_logic ); - end component; -end pack_ula; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/pll.qip b/Computer_MiST/Oric Atmos_MiST/rtl/pll.qip deleted file mode 100644 index d54ed791..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/pll.qip +++ /dev/null @@ -1,5 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/pll.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/pll.vhd deleted file mode 100644 index 5572c5ef..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/pll.vhd +++ /dev/null @@ -1,429 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.1.0 Build 162 10/23/2013 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - locked <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 9, - clk0_duty_cycle => 50, - clk0_multiply_by => 8, - clk0_phase_shift => "0", - clk1_divide_by => 9, - clk1_duty_cycle => 50, - clk1_multiply_by => 4, - clk1_phase_shift => "0", - clk2_divide_by => 9, - clk2_duty_cycle => 50, - clk2_multiply_by => 2, - clk2_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "OFF", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0, - locked => sub_wire2 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ps2key.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/ps2key.vhd deleted file mode 100644 index 74d5441d..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ps2key.vhd +++ /dev/null @@ -1,120 +0,0 @@ --- base sur les infos des pages suivantes : --- http://www.computer-engineering.org/ps2protocol/ --- http://www.computer-engineering.org/ps2keyboard/ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity ps2key is - generic ( - FREQ : integer := 24 - ); - port( - CLK : in std_logic; - RESET : in std_logic; - - PS2CLK : in std_logic; - PS2DATA : in std_logic; - - BREAK : out std_logic; - EXTENDED : out std_logic; - CODE : out std_logic_vector(6 downto 0); - LATCH : out std_logic - ); -end ps2key; - -architecture rtl of ps2key is -constant CLKCNT_SAMPLE : integer := FREQ * 20; -- 20us apres transition de l'horloge - --- Sampling -signal clkcnt : std_logic_vector(15 downto 0); -signal shift : std_logic; -signal idlcnt : std_logic_vector(15 downto 0); - --- Shifting -signal bitcnt : std_logic_vector(3 downto 0); -signal cready : std_logic; -signal char : std_logic_vector(10 downto 0); - --- Decodage -signal brkcode : std_logic; -signal extcode : std_logic; - --- Signal de controle -signal kready : std_logic; - -begin - -process(RESET, CLK, PS2CLK, PS2DATA) -begin - if RESET = '1' then - clkcnt <= (others => '0'); - shift <= '0'; - - bitcnt <= x"0"; - cready <= '0'; - char <= (others => '0'); - - brkcode <= '0'; - extcode <= '0'; - kready <= '0'; - - elsif rising_edge(CLK) then - - -- Sampling des bits - if PS2CLK = '1' then - shift <= '0'; - clkcnt <= (others => '0'); - else - clkcnt <= clkcnt + 1; - if clkcnt = CLKCNT_SAMPLE then - shift <= '1'; - else - shift <= '0'; - end if; - end if; - - -- Bit-shifting - if shift = '1' then - char <= PS2DATA & char(10 downto 1); - - if bitcnt = x"A" then - bitcnt <= x"0"; - cready <= '1'; - else - bitcnt <= bitcnt + 1; - end if; - end if; - - -- Decodage sequence - if cready = '1' then - cready <= '0'; - if char(8 downto 1) = x"E0" then - extcode <= '1'; - kready <= '0'; - elsif char(8 downto 1) = x"F0" then - brkcode <= '1'; - kready <= '0'; - elsif char(8) = '1' then -- les codes > 0x7F sont reserves apparemment - kready <= '0'; - else - kready <= '1'; - end if; - else - if kready = '1' then - brkcode <= '0'; - extcode <= '0'; - kready <= '0'; - end if; - end if; - - end if; -end process; - -BREAK <= brkcode; -EXTENDED <= extcode; -CODE <= char(7 downto 1); -LATCH <= kready; - -end rtl; \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ram16k.qip b/Computer_MiST/Oric Atmos_MiST/rtl/ram16k.qip deleted file mode 100644 index 3d87ecde..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ram16k.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram16k.vhd"] diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ram32k.qip b/Computer_MiST/Oric Atmos_MiST/rtl/ram32k.qip deleted file mode 100644 index 7c70dd31..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ram32k.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram32k.vhd"] diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ram48k.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/ram48k.vhd deleted file mode 100644 index 64b89518..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ram48k.vhd +++ /dev/null @@ -1,87 +0,0 @@ --- --- 48K RAM comprised of three smaller 16K RAMs --- --- (c) 2012 d18c7db(a)hotmail --- --- This program is free software; you can redistribute it and/or modify it under --- the terms of the GNU General Public License version 3 or, at your option, --- any later version as published by the Free Software Foundation. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. --- --- For full details, see the GNU General Public License at www.gnu.org/licenses - --- Changed for Mist FPGA Gehstock(2018) -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity ram48k is -port ( - clk : in std_logic; - cs : in std_logic; - oe : in std_logic; - we : in std_logic; - addr : in std_logic_vector(15 downto 0); - di : in std_logic_vector( 7 downto 0); - do : out std_logic_vector( 7 downto 0) -); -end; - -architecture RTL of ram48k is - signal ro0, ro1, ro2, ro3 : std_logic_vector(7 downto 0); - signal cs0, cs1, cs2, cs3 : std_logic := '0'; -begin - cs0 <= '1'; --- cs0 <= '1' when cs='1' and addr(15 downto 14)="00" else '0'; --- cs1 <= '1' when cs='1' and addr(15 downto 14)="01" else '0'; --- cs2 <= '1' when cs='1' and addr(15 downto 14)="10" else '0'; --- cs3 <= '1' when cs='1' and addr(15 downto 14)="11" else '0'; - do <= ro0; - -- ro0 when oe='1' and cs0='1' else - -- ro1 when oe='1' and cs1='1' else - -- ro2 when oe='1' and cs2='1' else - -- ro3 when oe='1' and cs3='1' else - -- (others=>'0'); - ---16kb - RAM_0000_3FFF : entity work.spram - port map ( - clk_i => clk, - we_i => cs0 and we, - addr_i => addr(13 downto 0), - data_i => di, - data_o => ro0 - ); ---32kb --- RAM_4000_7FFF : entity work.spram --- port map ( --- clk_i => clk, --- we_i => cs1 and we, --- addr_i => addr(13 downto 0), --- data_i => di, --- data_o => ro1 --- ); ---48kb --- RAM_8000_BFFF : entity work.spram --- port map ( --- clk_i => clk, --- we_i => cs2 and we, --- addr_i => addr(13 downto 0), --- data_i => di, --- data_o => ro2 --- ); ---64kb --- RAM_C000_FFFF : entity work.spram --- port map ( --- clk_i => clk, --- we_i => cs3 and we, --- addr_i => addr(13 downto 0), --- data_i => di, --- data_o => ro3 --- ); - -end RTL; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/rom.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/rom.vhd deleted file mode 100644 index babb546c..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/rom.vhd +++ /dev/null @@ -1,2077 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity rom is - port ( - CLK : in std_logic; - ADDR : in std_logic_vector(13 downto 0); - DATA : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of rom is - - - type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"4C",x"CC",x"EC",x"4C",x"71",x"C4",x"72",x"C9", -- 0x0000 - x"91",x"C6",x"86",x"E9",x"D0",x"E9",x"15",x"CD", -- 0x0008 - x"18",x"CD",x"11",x"CA",x"50",x"DA",x"A0",x"DA", -- 0x0010 - x"DD",x"D9",x"66",x"D9",x"84",x"DA",x"A0",x"DA", -- 0x0018 - x"54",x"C8",x"FC",x"C7",x"08",x"C8",x"97",x"CE", -- 0x0020 - x"3B",x"CA",x"54",x"CD",x"7D",x"D1",x"CD",x"CC", -- 0x0028 - x"88",x"CD",x"1B",x"CB",x"E4",x"C9",x"BC",x"C9", -- 0x0030 - x"6F",x"CA",x"51",x"C9",x"C7",x"C9",x"11",x"CA", -- 0x0038 - x"98",x"CA",x"CD",x"EB",x"E6",x"EB",x"0B",x"EC", -- 0x0040 - x"20",x"EC",x"32",x"EC",x"B4",x"FA",x"CA",x"FA", -- 0x0048 - x"E0",x"FA",x"9E",x"FA",x"FB",x"EA",x"FB",x"EA", -- 0x0050 - x"FB",x"EA",x"EF",x"EA",x"EF",x"EA",x"EF",x"EA", -- 0x0058 - x"EF",x"EA",x"EF",x"EA",x"EF",x"EA",x"EF",x"EA", -- 0x0060 - x"FB",x"EA",x"FB",x"EA",x"70",x"C9",x"C1",x"CA", -- 0x0068 - x"57",x"D9",x"5A",x"E8",x"08",x"E9",x"B9",x"D4", -- 0x0070 - x"4E",x"D9",x"AA",x"CB",x"9F",x"C9",x"47",x"C7", -- 0x0078 - x"0C",x"C7",x"45",x"CD",x"45",x"E9",x"12",x"CD", -- 0x0080 - x"ED",x"C6",x"21",x"DF",x"BD",x"DF",x"49",x"DF", -- 0x0088 - x"21",x"00",x"7E",x"D4",x"A6",x"D4",x"B5",x"D9", -- 0x0090 - x"FB",x"02",x"2E",x"E2",x"4F",x"E3",x"AF",x"DC", -- 0x0098 - x"AA",x"E2",x"8B",x"E3",x"92",x"E3",x"DB",x"E3", -- 0x00A0 - x"3F",x"E4",x"38",x"D9",x"83",x"D9",x"D4",x"DD", -- 0x00A8 - x"A6",x"D8",x"93",x"D5",x"D7",x"D8",x"B5",x"D8", -- 0x00B0 - x"16",x"D8",x"77",x"DE",x"0F",x"DF",x"0B",x"DF", -- 0x00B8 - x"DA",x"DA",x"3F",x"DA",x"45",x"EC",x"2A",x"D8", -- 0x00C0 - x"56",x"D8",x"61",x"D8",x"79",x"24",x"DB",x"79", -- 0x00C8 - x"0D",x"DB",x"7B",x"EF",x"DC",x"7B",x"E6",x"DD", -- 0x00D0 - x"7F",x"37",x"E2",x"50",x"E5",x"D0",x"46",x"E2", -- 0x00D8 - x"D0",x"7D",x"70",x"E2",x"5A",x"3B",x"D0",x"64", -- 0x00E0 - x"12",x"D1",x"45",x"4E",x"C4",x"45",x"44",x"49", -- 0x00E8 - x"D4",x"53",x"54",x"4F",x"52",x"C5",x"52",x"45", -- 0x00F0 - x"43",x"41",x"4C",x"CC",x"54",x"52",x"4F",x"CE", -- 0x00F8 - x"54",x"52",x"4F",x"46",x"C6",x"50",x"4F",x"D0", -- 0x0100 - x"50",x"4C",x"4F",x"D4",x"50",x"55",x"4C",x"CC", -- 0x0108 - x"4C",x"4F",x"52",x"45",x"D3",x"44",x"4F",x"4B", -- 0x0110 - x"C5",x"52",x"45",x"50",x"45",x"41",x"D4",x"55", -- 0x0118 - x"4E",x"54",x"49",x"CC",x"46",x"4F",x"D2",x"4C", -- 0x0120 - x"4C",x"49",x"53",x"D4",x"4C",x"50",x"52",x"49", -- 0x0128 - x"4E",x"D4",x"4E",x"45",x"58",x"D4",x"44",x"41", -- 0x0130 - x"54",x"C1",x"49",x"4E",x"50",x"55",x"D4",x"44", -- 0x0138 - x"49",x"CD",x"43",x"4C",x"D3",x"52",x"45",x"41", -- 0x0140 - x"C4",x"4C",x"45",x"D4",x"47",x"4F",x"54",x"CF", -- 0x0148 - x"52",x"55",x"CE",x"49",x"C6",x"52",x"45",x"53", -- 0x0150 - x"54",x"4F",x"52",x"C5",x"47",x"4F",x"53",x"55", -- 0x0158 - x"C2",x"52",x"45",x"54",x"55",x"52",x"CE",x"52", -- 0x0160 - x"45",x"CD",x"48",x"49",x"4D",x"45",x"CD",x"47", -- 0x0168 - x"52",x"41",x"C2",x"52",x"45",x"4C",x"45",x"41", -- 0x0170 - x"53",x"C5",x"54",x"45",x"58",x"D4",x"48",x"49", -- 0x0178 - x"52",x"45",x"D3",x"53",x"48",x"4F",x"4F",x"D4", -- 0x0180 - x"45",x"58",x"50",x"4C",x"4F",x"44",x"C5",x"5A", -- 0x0188 - x"41",x"D0",x"50",x"49",x"4E",x"C7",x"53",x"4F", -- 0x0190 - x"55",x"4E",x"C4",x"4D",x"55",x"53",x"49",x"C3", -- 0x0198 - x"50",x"4C",x"41",x"D9",x"43",x"55",x"52",x"53", -- 0x01A0 - x"45",x"D4",x"43",x"55",x"52",x"4D",x"4F",x"D6", -- 0x01A8 - x"44",x"52",x"41",x"D7",x"43",x"49",x"52",x"43", -- 0x01B0 - x"4C",x"C5",x"50",x"41",x"54",x"54",x"45",x"52", -- 0x01B8 - x"CE",x"46",x"49",x"4C",x"CC",x"43",x"48",x"41", -- 0x01C0 - x"D2",x"50",x"41",x"50",x"45",x"D2",x"49",x"4E", -- 0x01C8 - x"CB",x"53",x"54",x"4F",x"D0",x"4F",x"CE",x"57", -- 0x01D0 - x"41",x"49",x"D4",x"43",x"4C",x"4F",x"41",x"C4", -- 0x01D8 - x"43",x"53",x"41",x"56",x"C5",x"44",x"45",x"C6", -- 0x01E0 - x"50",x"4F",x"4B",x"C5",x"50",x"52",x"49",x"4E", -- 0x01E8 - x"D4",x"43",x"4F",x"4E",x"D4",x"4C",x"49",x"53", -- 0x01F0 - x"D4",x"43",x"4C",x"45",x"41",x"D2",x"47",x"45", -- 0x01F8 - x"D4",x"43",x"41",x"4C",x"CC",x"A1",x"4E",x"45", -- 0x0200 - x"D7",x"54",x"41",x"42",x"A8",x"54",x"CF",x"46", -- 0x0208 - x"CE",x"53",x"50",x"43",x"A8",x"C0",x"41",x"55", -- 0x0210 - x"54",x"CF",x"45",x"4C",x"53",x"C5",x"54",x"48", -- 0x0218 - x"45",x"CE",x"4E",x"4F",x"D4",x"53",x"54",x"45", -- 0x0220 - x"D0",x"AB",x"AD",x"AA",x"AF",x"DE",x"41",x"4E", -- 0x0228 - x"C4",x"4F",x"D2",x"BE",x"BD",x"BC",x"53",x"47", -- 0x0230 - x"CE",x"49",x"4E",x"D4",x"41",x"42",x"D3",x"55", -- 0x0238 - x"53",x"D2",x"46",x"52",x"C5",x"50",x"4F",x"D3", -- 0x0240 - x"48",x"45",x"58",x"A4",x"A6",x"53",x"51",x"D2", -- 0x0248 - x"52",x"4E",x"C4",x"4C",x"CE",x"45",x"58",x"D0", -- 0x0250 - x"43",x"4F",x"D3",x"53",x"49",x"CE",x"54",x"41", -- 0x0258 - x"CE",x"41",x"54",x"CE",x"50",x"45",x"45",x"CB", -- 0x0260 - x"44",x"45",x"45",x"CB",x"4C",x"4F",x"C7",x"4C", -- 0x0268 - x"45",x"CE",x"53",x"54",x"52",x"A4",x"56",x"41", -- 0x0270 - x"CC",x"41",x"53",x"C3",x"43",x"48",x"52",x"A4", -- 0x0278 - x"50",x"C9",x"54",x"52",x"55",x"C5",x"46",x"41", -- 0x0280 - x"4C",x"53",x"C5",x"4B",x"45",x"59",x"A4",x"53", -- 0x0288 - x"43",x"52",x"CE",x"50",x"4F",x"49",x"4E",x"D4", -- 0x0290 - x"4C",x"45",x"46",x"54",x"A4",x"52",x"49",x"47", -- 0x0298 - x"48",x"54",x"A4",x"4D",x"49",x"44",x"A4",x"00", -- 0x02A0 - x"4E",x"45",x"58",x"54",x"20",x"57",x"49",x"54", -- 0x02A8 - x"48",x"4F",x"55",x"54",x"20",x"46",x"4F",x"D2", -- 0x02B0 - x"53",x"59",x"4E",x"54",x"41",x"D8",x"52",x"45", -- 0x02B8 - x"54",x"55",x"52",x"4E",x"20",x"57",x"49",x"54", -- 0x02C0 - x"48",x"4F",x"55",x"54",x"20",x"47",x"4F",x"53", -- 0x02C8 - x"55",x"C2",x"4F",x"55",x"54",x"20",x"4F",x"46", -- 0x02D0 - x"20",x"44",x"41",x"54",x"C1",x"49",x"4C",x"4C", -- 0x02D8 - x"45",x"47",x"41",x"4C",x"20",x"51",x"55",x"41", -- 0x02E0 - x"4E",x"54",x"49",x"54",x"D9",x"4F",x"56",x"45", -- 0x02E8 - x"52",x"46",x"4C",x"4F",x"D7",x"4F",x"55",x"54", -- 0x02F0 - x"20",x"4F",x"46",x"20",x"4D",x"45",x"4D",x"4F", -- 0x02F8 - x"52",x"D9",x"55",x"4E",x"44",x"45",x"46",x"27", -- 0x0300 - x"44",x"20",x"53",x"54",x"41",x"54",x"45",x"4D", -- 0x0308 - x"45",x"4E",x"D4",x"42",x"41",x"44",x"20",x"53", -- 0x0310 - x"55",x"42",x"53",x"43",x"52",x"49",x"50",x"D4", -- 0x0318 - x"52",x"45",x"44",x"49",x"4D",x"27",x"44",x"20", -- 0x0320 - x"41",x"52",x"52",x"41",x"D9",x"44",x"49",x"56", -- 0x0328 - x"49",x"53",x"49",x"4F",x"4E",x"20",x"42",x"59", -- 0x0330 - x"20",x"5A",x"45",x"52",x"CF",x"49",x"4C",x"4C", -- 0x0338 - x"45",x"47",x"41",x"4C",x"20",x"44",x"49",x"52", -- 0x0340 - x"45",x"43",x"D4",x"44",x"49",x"53",x"50",x"20", -- 0x0348 - x"54",x"59",x"50",x"45",x"20",x"4D",x"49",x"53", -- 0x0350 - x"4D",x"41",x"54",x"43",x"C8",x"53",x"54",x"52", -- 0x0358 - x"49",x"4E",x"47",x"20",x"54",x"4F",x"4F",x"20", -- 0x0360 - x"4C",x"4F",x"4E",x"C7",x"46",x"4F",x"52",x"4D", -- 0x0368 - x"55",x"4C",x"41",x"20",x"54",x"4F",x"4F",x"20", -- 0x0370 - x"43",x"4F",x"4D",x"50",x"4C",x"45",x"D8",x"43", -- 0x0378 - x"41",x"4E",x"27",x"54",x"20",x"43",x"4F",x"4E", -- 0x0380 - x"54",x"49",x"4E",x"55",x"C5",x"55",x"4E",x"44", -- 0x0388 - x"45",x"46",x"27",x"44",x"20",x"46",x"55",x"4E", -- 0x0390 - x"43",x"54",x"49",x"4F",x"CE",x"42",x"41",x"44", -- 0x0398 - x"20",x"55",x"4E",x"54",x"49",x"CC",x"20",x"45", -- 0x03A0 - x"52",x"52",x"4F",x"52",x"00",x"20",x"49",x"4E", -- 0x03A8 - x"20",x"00",x"0D",x"0A",x"52",x"65",x"61",x"64", -- 0x03B0 - x"79",x"20",x"0D",x"0A",x"00",x"0D",x"0A",x"20", -- 0x03B8 - x"42",x"52",x"45",x"41",x"4B",x"00",x"BA",x"E8", -- 0x03C0 - x"E8",x"E8",x"E8",x"BD",x"01",x"01",x"C9",x"8D", -- 0x03C8 - x"D0",x"21",x"A5",x"B9",x"D0",x"0A",x"BD",x"02", -- 0x03D0 - x"01",x"85",x"B8",x"BD",x"03",x"01",x"85",x"B9", -- 0x03D8 - x"DD",x"03",x"01",x"D0",x"07",x"A5",x"B8",x"DD", -- 0x03E0 - x"02",x"01",x"F0",x"07",x"8A",x"18",x"69",x"12", -- 0x03E8 - x"AA",x"D0",x"D8",x"60",x"20",x"44",x"C4",x"85", -- 0x03F0 - x"A0",x"84",x"A1",x"38",x"A5",x"C9",x"E5",x"CE", -- 0x03F8 - x"85",x"91",x"A8",x"A5",x"CA",x"E5",x"CF",x"AA", -- 0x0400 - x"E8",x"98",x"F0",x"23",x"A5",x"C9",x"38",x"E5", -- 0x0408 - x"91",x"85",x"C9",x"B0",x"03",x"C6",x"CA",x"38", -- 0x0410 - x"A5",x"C7",x"E5",x"91",x"85",x"C7",x"B0",x"08", -- 0x0418 - x"C6",x"C8",x"90",x"04",x"B1",x"C9",x"91",x"C7", -- 0x0420 - x"88",x"D0",x"F9",x"B1",x"C9",x"91",x"C7",x"C6", -- 0x0428 - x"CA",x"C6",x"C8",x"CA",x"D0",x"F2",x"60",x"0A", -- 0x0430 - x"69",x"3E",x"B0",x"40",x"85",x"91",x"BA",x"E4", -- 0x0438 - x"91",x"90",x"39",x"60",x"C4",x"A3",x"90",x"28", -- 0x0440 - x"D0",x"04",x"C5",x"A2",x"90",x"22",x"48",x"A2", -- 0x0448 - x"09",x"98",x"48",x"B5",x"C6",x"CA",x"10",x"FA", -- 0x0450 - x"20",x"50",x"D6",x"A2",x"F7",x"68",x"95",x"D0", -- 0x0458 - x"E8",x"30",x"FA",x"68",x"A8",x"68",x"C4",x"A3", -- 0x0460 - x"90",x"06",x"D0",x"10",x"C5",x"A2",x"B0",x"0C", -- 0x0468 - x"60",x"AD",x"C0",x"02",x"29",x"FE",x"8D",x"C0", -- 0x0470 - x"02",x"4C",x"A8",x"C4",x"A2",x"4D",x"20",x"2F", -- 0x0478 - x"C8",x"46",x"2E",x"20",x"F0",x"CB",x"20",x"D7", -- 0x0480 - x"CC",x"BD",x"A8",x"C2",x"48",x"29",x"7F",x"20", -- 0x0488 - x"D9",x"CC",x"E8",x"68",x"10",x"F3",x"20",x"26", -- 0x0490 - x"C7",x"A9",x"A6",x"A0",x"C3",x"20",x"B0",x"CC", -- 0x0498 - x"A4",x"A9",x"C8",x"F0",x"03",x"20",x"BA",x"E0", -- 0x04A0 - x"4E",x"52",x"02",x"46",x"2E",x"4E",x"F2",x"02", -- 0x04A8 - x"A9",x"B2",x"A0",x"C3",x"20",x"1A",x"00",x"20", -- 0x04B0 - x"2F",x"C8",x"20",x"92",x"C5",x"86",x"E9",x"84", -- 0x04B8 - x"EA",x"20",x"E2",x"00",x"AA",x"F0",x"F0",x"A2", -- 0x04C0 - x"FF",x"86",x"A9",x"90",x"06",x"20",x"FA",x"C5", -- 0x04C8 - x"4C",x"0C",x"C9",x"20",x"E2",x"CA",x"20",x"FA", -- 0x04D0 - x"C5",x"84",x"26",x"20",x"B3",x"C6",x"90",x"44", -- 0x04D8 - x"A0",x"01",x"B1",x"CE",x"85",x"92",x"A5",x"9C", -- 0x04E0 - x"85",x"91",x"A5",x"CF",x"85",x"94",x"A5",x"CE", -- 0x04E8 - x"88",x"F1",x"CE",x"18",x"65",x"9C",x"85",x"9C", -- 0x04F0 - x"85",x"93",x"A5",x"9D",x"69",x"FF",x"85",x"9D", -- 0x04F8 - x"E5",x"CF",x"AA",x"38",x"A5",x"CE",x"E5",x"9C", -- 0x0500 - x"A8",x"B0",x"03",x"E8",x"C6",x"94",x"18",x"65", -- 0x0508 - x"91",x"90",x"03",x"C6",x"92",x"18",x"B1",x"91", -- 0x0510 - x"91",x"93",x"C8",x"D0",x"F9",x"E6",x"92",x"E6", -- 0x0518 - x"94",x"CA",x"D0",x"F2",x"20",x"08",x"C7",x"20", -- 0x0520 - x"5F",x"C5",x"A5",x"35",x"F0",x"89",x"18",x"A5", -- 0x0528 - x"9C",x"85",x"C9",x"65",x"26",x"85",x"C7",x"A4", -- 0x0530 - x"9D",x"84",x"CA",x"90",x"01",x"C8",x"84",x"C8", -- 0x0538 - x"20",x"F4",x"C3",x"A5",x"A0",x"A4",x"A1",x"85", -- 0x0540 - x"9C",x"84",x"9D",x"A4",x"26",x"88",x"B9",x"31", -- 0x0548 - x"00",x"91",x"CE",x"88",x"10",x"F8",x"20",x"08", -- 0x0550 - x"C7",x"20",x"5F",x"C5",x"4C",x"B7",x"C4",x"A5", -- 0x0558 - x"9A",x"A4",x"9B",x"85",x"91",x"84",x"92",x"18", -- 0x0560 - x"A0",x"01",x"B1",x"91",x"F0",x"1D",x"A0",x"04", -- 0x0568 - x"C8",x"B1",x"91",x"D0",x"FB",x"C8",x"98",x"65", -- 0x0570 - x"91",x"AA",x"A0",x"00",x"91",x"91",x"A5",x"92", -- 0x0578 - x"69",x"00",x"C8",x"91",x"91",x"86",x"91",x"85", -- 0x0580 - x"92",x"90",x"DD",x"60",x"CA",x"10",x"05",x"20", -- 0x0588 - x"F0",x"CB",x"A2",x"00",x"20",x"E8",x"C5",x"C9", -- 0x0590 - x"01",x"D0",x"0D",x"AC",x"69",x"02",x"B1",x"12", -- 0x0598 - x"29",x"7F",x"C9",x"20",x"B0",x"02",x"A9",x"09", -- 0x05A0 - x"48",x"20",x"D9",x"CC",x"68",x"C9",x"7F",x"F0", -- 0x05A8 - x"DB",x"C9",x"0D",x"F0",x"30",x"C9",x"03",x"F0", -- 0x05B0 - x"28",x"C9",x"18",x"F0",x"0B",x"C9",x"20",x"90", -- 0x05B8 - x"D3",x"95",x"35",x"E8",x"E0",x"4F",x"90",x"07", -- 0x05C0 - x"A9",x"5C",x"20",x"D9",x"CC",x"D0",x"C0",x"E0", -- 0x05C8 - x"4C",x"90",x"C1",x"8A",x"48",x"98",x"48",x"20", -- 0x05D0 - x"9F",x"FA",x"68",x"A8",x"68",x"AA",x"4C",x"94", -- 0x05D8 - x"C5",x"E6",x"17",x"A2",x"00",x"4C",x"EA",x"CB", -- 0x05E0 - x"20",x"3B",x"02",x"10",x"FB",x"C9",x"0F",x"D0", -- 0x05E8 - x"08",x"48",x"A5",x"2E",x"49",x"FF",x"85",x"2E", -- 0x05F0 - x"68",x"60",x"A6",x"E9",x"A0",x"04",x"84",x"2A", -- 0x05F8 - x"B5",x"00",x"C9",x"20",x"F0",x"41",x"85",x"25", -- 0x0600 - x"C9",x"22",x"F0",x"5F",x"24",x"2A",x"70",x"37", -- 0x0608 - x"C9",x"3F",x"D0",x"04",x"A9",x"BA",x"D0",x"2F", -- 0x0610 - x"C9",x"30",x"90",x"04",x"C9",x"3C",x"90",x"27", -- 0x0618 - x"84",x"E0",x"A0",x"00",x"84",x"26",x"A9",x"E9", -- 0x0620 - x"85",x"18",x"A9",x"C0",x"85",x"19",x"86",x"E9", -- 0x0628 - x"CA",x"E8",x"E6",x"18",x"D0",x"02",x"E6",x"19", -- 0x0630 - x"B5",x"00",x"38",x"F1",x"18",x"F0",x"F2",x"C9", -- 0x0638 - x"80",x"D0",x"2F",x"05",x"26",x"A4",x"E0",x"E8", -- 0x0640 - x"C8",x"99",x"30",x"00",x"B9",x"30",x"00",x"F0", -- 0x0648 - x"39",x"38",x"E9",x"3A",x"F0",x"04",x"C9",x"57", -- 0x0650 - x"D0",x"02",x"85",x"2A",x"38",x"E9",x"63",x"D0", -- 0x0658 - x"9F",x"85",x"25",x"B5",x"00",x"F0",x"E0",x"C5", -- 0x0660 - x"25",x"F0",x"DC",x"C8",x"99",x"30",x"00",x"E8", -- 0x0668 - x"D0",x"F1",x"A6",x"E9",x"E6",x"26",x"B1",x"18", -- 0x0670 - x"08",x"E6",x"18",x"D0",x"02",x"E6",x"19",x"28", -- 0x0678 - x"10",x"F4",x"B1",x"18",x"D0",x"B2",x"B5",x"00", -- 0x0680 - x"10",x"BB",x"99",x"32",x"00",x"A9",x"34",x"85", -- 0x0688 - x"E9",x"60",x"20",x"E2",x"CA",x"20",x"B3",x"C6", -- 0x0690 - x"90",x"16",x"6E",x"F2",x"02",x"20",x"6C",x"C7", -- 0x0698 - x"4E",x"F2",x"02",x"20",x"F0",x"CB",x"A9",x"0B", -- 0x06A0 - x"20",x"D9",x"CC",x"68",x"68",x"4C",x"B7",x"C4", -- 0x06A8 - x"4C",x"23",x"CA",x"A9",x"00",x"85",x"1D",x"85", -- 0x06B0 - x"1E",x"A5",x"9A",x"A6",x"9B",x"A0",x"01",x"85", -- 0x06B8 - x"CE",x"86",x"CF",x"B1",x"CE",x"F0",x"25",x"C8", -- 0x06C0 - x"C8",x"E6",x"1D",x"D0",x"02",x"E6",x"1E",x"A5", -- 0x06C8 - x"34",x"D1",x"CE",x"90",x"18",x"F0",x"03",x"88", -- 0x06D0 - x"D0",x"09",x"A5",x"33",x"88",x"D1",x"CE",x"90", -- 0x06D8 - x"0C",x"F0",x"0A",x"88",x"B1",x"CE",x"AA",x"88", -- 0x06E0 - x"B1",x"CE",x"B0",x"D1",x"18",x"60",x"D0",x"FD", -- 0x06E8 - x"A9",x"00",x"4E",x"F4",x"02",x"A8",x"91",x"9A", -- 0x06F0 - x"C8",x"91",x"9A",x"A5",x"9A",x"18",x"69",x"02", -- 0x06F8 - x"85",x"9C",x"A5",x"9B",x"69",x"00",x"85",x"9D", -- 0x0700 - x"20",x"3A",x"C7",x"A9",x"00",x"D0",x"2A",x"A5", -- 0x0708 - x"A6",x"A4",x"A7",x"85",x"A2",x"84",x"A3",x"A5", -- 0x0710 - x"9C",x"A4",x"9D",x"85",x"9E",x"84",x"9F",x"85", -- 0x0718 - x"A0",x"84",x"A1",x"20",x"52",x"C9",x"A2",x"88", -- 0x0720 - x"86",x"85",x"68",x"A8",x"68",x"A2",x"FE",x"9A", -- 0x0728 - x"48",x"98",x"48",x"A9",x"00",x"85",x"AD",x"85", -- 0x0730 - x"2B",x"60",x"18",x"A5",x"9A",x"69",x"FF",x"85", -- 0x0738 - x"E9",x"A5",x"9B",x"69",x"FF",x"85",x"EA",x"60", -- 0x0740 - x"08",x"20",x"E2",x"CA",x"20",x"B3",x"C6",x"28", -- 0x0748 - x"F0",x"14",x"20",x"E8",x"00",x"F0",x"15",x"C9", -- 0x0750 - x"CD",x"D0",x"92",x"20",x"E2",x"00",x"F0",x"06", -- 0x0758 - x"20",x"E2",x"CA",x"F0",x"07",x"60",x"A9",x"FF", -- 0x0760 - x"85",x"33",x"85",x"34",x"A0",x"01",x"B1",x"CE", -- 0x0768 - x"F0",x"4D",x"20",x"62",x"C9",x"C9",x"20",x"D0", -- 0x0770 - x"0E",x"4E",x"DF",x"02",x"AD",x"DF",x"02",x"10", -- 0x0778 - x"FB",x"20",x"62",x"C9",x"4E",x"DF",x"02",x"C8", -- 0x0780 - x"B1",x"CE",x"AA",x"C8",x"B1",x"CE",x"C5",x"34", -- 0x0788 - x"D0",x"04",x"E4",x"33",x"F0",x"02",x"B0",x"27", -- 0x0790 - x"84",x"B8",x"48",x"20",x"F0",x"CB",x"68",x"20", -- 0x0798 - x"C5",x"E0",x"A9",x"20",x"A4",x"B8",x"29",x"7F", -- 0x07A0 - x"20",x"D9",x"CC",x"C8",x"F0",x"11",x"B1",x"CE", -- 0x07A8 - x"D0",x"1E",x"A8",x"B1",x"CE",x"AA",x"C8",x"B1", -- 0x07B0 - x"CE",x"86",x"CE",x"85",x"CF",x"D0",x"AD",x"2C", -- 0x07B8 - x"F2",x"02",x"10",x"01",x"60",x"20",x"F0",x"CB", -- 0x07C0 - x"20",x"2F",x"C8",x"68",x"68",x"4C",x"A8",x"C4", -- 0x07C8 - x"10",x"D6",x"38",x"E9",x"7F",x"AA",x"84",x"B8", -- 0x07D0 - x"A0",x"00",x"A9",x"E9",x"85",x"18",x"A9",x"C0", -- 0x07D8 - x"85",x"19",x"CA",x"F0",x"0D",x"E6",x"18",x"D0", -- 0x07E0 - x"02",x"E6",x"19",x"B1",x"18",x"10",x"F6",x"4C", -- 0x07E8 - x"E2",x"C7",x"C8",x"B1",x"18",x"30",x"AD",x"20", -- 0x07F0 - x"D9",x"CC",x"4C",x"F2",x"C7",x"20",x"16",x"C8", -- 0x07F8 - x"4E",x"F2",x"02",x"20",x"E8",x"00",x"4C",x"48", -- 0x0800 - x"C7",x"20",x"16",x"C8",x"20",x"E8",x"00",x"20", -- 0x0808 - x"AB",x"CB",x"20",x"2F",x"C8",x"60",x"2C",x"F1", -- 0x0810 - x"02",x"30",x"39",x"A5",x"30",x"8D",x"59",x"02", -- 0x0818 - x"AD",x"58",x"02",x"85",x"30",x"38",x"6E",x"F1", -- 0x0820 - x"02",x"AD",x"56",x"02",x"4C",x"44",x"C8",x"2C", -- 0x0828 - x"F1",x"02",x"10",x"20",x"A5",x"30",x"8D",x"58", -- 0x0830 - x"02",x"AD",x"59",x"02",x"85",x"30",x"4E",x"F1", -- 0x0838 - x"02",x"AD",x"57",x"02",x"85",x"31",x"38",x"E9", -- 0x0840 - x"08",x"B0",x"FB",x"49",x"FF",x"E9",x"06",x"18", -- 0x0848 - x"65",x"31",x"85",x"32",x"60",x"A9",x"80",x"85", -- 0x0850 - x"2B",x"20",x"1C",x"CB",x"20",x"C6",x"C3",x"D0", -- 0x0858 - x"05",x"8A",x"69",x"0F",x"AA",x"9A",x"68",x"68", -- 0x0860 - x"A9",x"09",x"20",x"37",x"C4",x"20",x"4E",x"CA", -- 0x0868 - x"18",x"98",x"65",x"E9",x"48",x"A5",x"EA",x"69", -- 0x0870 - x"00",x"48",x"A5",x"A9",x"48",x"A5",x"A8",x"48", -- 0x0878 - x"A9",x"C3",x"20",x"67",x"D0",x"20",x"06",x"CF", -- 0x0880 - x"20",x"03",x"CF",x"A5",x"D5",x"09",x"7F",x"25", -- 0x0888 - x"D1",x"85",x"D1",x"A9",x"9E",x"A0",x"C8",x"85", -- 0x0890 - x"91",x"84",x"92",x"4C",x"C0",x"CF",x"A9",x"81", -- 0x0898 - x"A0",x"DC",x"20",x"7B",x"DE",x"20",x"E8",x"00", -- 0x08A0 - x"C9",x"CB",x"D0",x"06",x"20",x"E2",x"00",x"20", -- 0x08A8 - x"03",x"CF",x"20",x"13",x"DF",x"20",x"B1",x"CF", -- 0x08B0 - x"A5",x"B9",x"48",x"A5",x"B8",x"48",x"A9",x"8D", -- 0x08B8 - x"48",x"20",x"62",x"C9",x"A5",x"E9",x"A4",x"EA", -- 0x08C0 - x"F0",x"06",x"85",x"AC",x"84",x"AD",x"A0",x"00", -- 0x08C8 - x"B1",x"E9",x"D0",x"5B",x"4E",x"52",x"02",x"A0", -- 0x08D0 - x"02",x"B1",x"E9",x"18",x"D0",x"03",x"4C",x"8A", -- 0x08D8 - x"C9",x"C8",x"B1",x"E9",x"85",x"A8",x"C8",x"B1", -- 0x08E0 - x"E9",x"85",x"A9",x"98",x"65",x"E9",x"85",x"E9", -- 0x08E8 - x"90",x"02",x"E6",x"EA",x"2C",x"F4",x"02",x"10", -- 0x08F0 - x"13",x"48",x"A9",x"5B",x"20",x"FB",x"CC",x"A5", -- 0x08F8 - x"A9",x"A6",x"A8",x"20",x"C5",x"E0",x"A9",x"5D", -- 0x0900 - x"20",x"FB",x"CC",x"68",x"20",x"E2",x"00",x"20", -- 0x0908 - x"15",x"C9",x"4C",x"C1",x"C8",x"F0",x"49",x"E9", -- 0x0910 - x"80",x"90",x"11",x"C9",x"42",x"B0",x"30",x"0A", -- 0x0918 - x"A8",x"B9",x"07",x"C0",x"48",x"B9",x"06",x"C0", -- 0x0920 - x"48",x"4C",x"E2",x"00",x"4C",x"1C",x"CB",x"C9", -- 0x0928 - x"3A",x"F0",x"C1",x"C9",x"C8",x"D0",x"0E",x"2C", -- 0x0930 - x"52",x"02",x"10",x"13",x"20",x"B1",x"CA",x"4E", -- 0x0938 - x"52",x"02",x"4C",x"C1",x"C8",x"C9",x"27",x"D0", -- 0x0940 - x"06",x"20",x"99",x"CA",x"4C",x"C1",x"C8",x"4C", -- 0x0948 - x"70",x"D0",x"38",x"A5",x"9A",x"E9",x"01",x"A4", -- 0x0950 - x"9B",x"B0",x"01",x"88",x"85",x"B0",x"84",x"B1", -- 0x0958 - x"60",x"60",x"AD",x"DF",x"02",x"10",x"F9",x"29", -- 0x0960 - x"7F",x"A2",x"08",x"C9",x"03",x"D0",x"F2",x"C9", -- 0x0968 - x"03",x"B0",x"01",x"18",x"D0",x"43",x"A5",x"E9", -- 0x0970 - x"A4",x"EA",x"F0",x"0C",x"85",x"AC",x"84",x"AD", -- 0x0978 - x"A5",x"A8",x"A4",x"A9",x"85",x"AA",x"84",x"AB", -- 0x0980 - x"68",x"68",x"A9",x"BD",x"A0",x"C3",x"A2",x"00", -- 0x0988 - x"8E",x"F1",x"02",x"8E",x"DF",x"02",x"86",x"2E", -- 0x0990 - x"90",x"03",x"4C",x"9D",x"C4",x"4C",x"A8",x"C4", -- 0x0998 - x"D0",x"17",x"A2",x"D7",x"A4",x"AD",x"D0",x"03", -- 0x09A0 - x"4C",x"7E",x"C4",x"A5",x"AC",x"85",x"E9",x"84", -- 0x09A8 - x"EA",x"A5",x"AA",x"A4",x"AB",x"85",x"A8",x"84", -- 0x09B0 - x"A9",x"60",x"4C",x"36",x"D3",x"D0",x"03",x"4C", -- 0x09B8 - x"08",x"C7",x"20",x"0F",x"C7",x"4C",x"DC",x"C9", -- 0x09C0 - x"A9",x"03",x"20",x"37",x"C4",x"A5",x"EA",x"48", -- 0x09C8 - x"A5",x"E9",x"48",x"A5",x"A9",x"48",x"A5",x"A8", -- 0x09D0 - x"48",x"A9",x"9B",x"48",x"20",x"E8",x"00",x"20", -- 0x09D8 - x"E5",x"C9",x"4C",x"C1",x"C8",x"20",x"53",x"E8", -- 0x09E0 - x"20",x"51",x"CA",x"A5",x"A9",x"C5",x"34",x"B0", -- 0x09E8 - x"0B",x"98",x"38",x"65",x"E9",x"A6",x"EA",x"90", -- 0x09F0 - x"07",x"E8",x"B0",x"04",x"A5",x"9A",x"A6",x"9B", -- 0x09F8 - x"20",x"BD",x"C6",x"90",x"1E",x"A5",x"CE",x"E9", -- 0x0A00 - x"01",x"85",x"E9",x"A5",x"CF",x"E9",x"00",x"85", -- 0x0A08 - x"EA",x"60",x"D0",x"FD",x"A9",x"FF",x"85",x"B9", -- 0x0A10 - x"20",x"C6",x"C3",x"9A",x"C9",x"9B",x"F0",x"0B", -- 0x0A18 - x"A2",x"16",x"2C",x"A2",x"5A",x"4C",x"7E",x"C4", -- 0x0A20 - x"4C",x"70",x"D0",x"68",x"68",x"C0",x"0C",x"F0", -- 0x0A28 - x"19",x"85",x"A8",x"68",x"85",x"A9",x"68",x"85", -- 0x0A30 - x"E9",x"68",x"85",x"EA",x"20",x"4E",x"CA",x"98", -- 0x0A38 - x"18",x"65",x"E9",x"85",x"E9",x"90",x"02",x"E6", -- 0x0A40 - x"EA",x"60",x"68",x"68",x"68",x"60",x"A2",x"3A", -- 0x0A48 - x"2C",x"A2",x"00",x"86",x"24",x"A0",x"00",x"84", -- 0x0A50 - x"25",x"A5",x"25",x"A6",x"24",x"85",x"24",x"86", -- 0x0A58 - x"25",x"B1",x"E9",x"F0",x"E4",x"C5",x"25",x"F0", -- 0x0A60 - x"E0",x"C8",x"C9",x"22",x"D0",x"F3",x"F0",x"E9", -- 0x0A68 - x"20",x"17",x"CF",x"20",x"E8",x"00",x"C9",x"97", -- 0x0A70 - x"F0",x"05",x"A9",x"C9",x"20",x"67",x"D0",x"A5", -- 0x0A78 - x"D0",x"D0",x"05",x"20",x"9E",x"CA",x"F0",x"B7", -- 0x0A80 - x"20",x"E8",x"00",x"B0",x"03",x"4C",x"E5",x"C9", -- 0x0A88 - x"08",x"38",x"6E",x"52",x"02",x"28",x"4C",x"15", -- 0x0A90 - x"C9",x"20",x"51",x"CA",x"F0",x"A1",x"A0",x"00", -- 0x0A98 - x"B1",x"E9",x"F0",x"0C",x"C8",x"C9",x"C9",x"F0", -- 0x0AA0 - x"F0",x"C9",x"C8",x"D0",x"F3",x"4C",x"3F",x"CA", -- 0x0AA8 - x"60",x"A0",x"FF",x"C8",x"B1",x"E9",x"F0",x"04", -- 0x0AB0 - x"C9",x"3A",x"D0",x"F7",x"4C",x"3F",x"CA",x"4C", -- 0x0AB8 - x"70",x"D0",x"20",x"C8",x"D8",x"48",x"C9",x"9B", -- 0x0AC0 - x"F0",x"04",x"C9",x"97",x"D0",x"F1",x"C6",x"D4", -- 0x0AC8 - x"D0",x"04",x"68",x"4C",x"17",x"C9",x"20",x"E2", -- 0x0AD0 - x"00",x"20",x"E2",x"CA",x"C9",x"2C",x"F0",x"EE", -- 0x0AD8 - x"68",x"60",x"A2",x"00",x"86",x"33",x"86",x"34", -- 0x0AE0 - x"B0",x"F7",x"E9",x"2F",x"85",x"24",x"A5",x"34", -- 0x0AE8 - x"85",x"91",x"C9",x"19",x"B0",x"D4",x"A5",x"33", -- 0x0AF0 - x"0A",x"26",x"91",x"0A",x"26",x"91",x"65",x"33", -- 0x0AF8 - x"85",x"33",x"A5",x"91",x"65",x"34",x"85",x"34", -- 0x0B00 - x"06",x"33",x"26",x"34",x"A5",x"33",x"65",x"24", -- 0x0B08 - x"85",x"33",x"90",x"02",x"E6",x"34",x"20",x"E2", -- 0x0B10 - x"00",x"4C",x"E8",x"CA",x"20",x"88",x"D1",x"85", -- 0x0B18 - x"B8",x"84",x"B9",x"A9",x"D4",x"20",x"67",x"D0", -- 0x0B20 - x"A5",x"29",x"48",x"A5",x"28",x"48",x"20",x"17", -- 0x0B28 - x"CF",x"68",x"2A",x"20",x"09",x"CF",x"D0",x"18", -- 0x0B30 - x"68",x"10",x"12",x"20",x"F4",x"DE",x"20",x"A9", -- 0x0B38 - x"D2",x"A0",x"00",x"A5",x"D3",x"91",x"B8",x"C8", -- 0x0B40 - x"A5",x"D4",x"91",x"B8",x"60",x"4C",x"A9",x"DE", -- 0x0B48 - x"68",x"A0",x"02",x"B1",x"D3",x"C5",x"A3",x"90", -- 0x0B50 - x"17",x"D0",x"07",x"88",x"B1",x"D3",x"C5",x"A2", -- 0x0B58 - x"90",x"0E",x"A4",x"D4",x"C4",x"9D",x"90",x"08", -- 0x0B60 - x"D0",x"0D",x"A5",x"D3",x"C5",x"9C",x"B0",x"07", -- 0x0B68 - x"A5",x"D3",x"A4",x"D4",x"4C",x"8D",x"CB",x"A0", -- 0x0B70 - x"00",x"B1",x"D3",x"20",x"A3",x"D5",x"A5",x"BF", -- 0x0B78 - x"A4",x"C0",x"85",x"DE",x"84",x"DF",x"20",x"A4", -- 0x0B80 - x"D7",x"A9",x"D0",x"A0",x"00",x"85",x"BF",x"84", -- 0x0B88 - x"C0",x"20",x"05",x"D8",x"A0",x"00",x"B1",x"BF", -- 0x0B90 - x"91",x"B8",x"C8",x"B1",x"BF",x"91",x"B8",x"C8", -- 0x0B98 - x"B1",x"BF",x"91",x"B8",x"60",x"20",x"B3",x"CC", -- 0x0BA0 - x"20",x"E8",x"00",x"F0",x"43",x"F0",x"5C",x"C9", -- 0x0BA8 - x"C2",x"F0",x"7B",x"C9",x"C5",x"18",x"F0",x"76", -- 0x0BB0 - x"C9",x"2C",x"F0",x"50",x"C9",x"3B",x"F0",x"6B", -- 0x0BB8 - x"C9",x"C6",x"D0",x"03",x"4C",x"59",x"CC",x"20", -- 0x0BC0 - x"17",x"CF",x"24",x"28",x"30",x"D7",x"20",x"D5", -- 0x0BC8 - x"E0",x"20",x"B5",x"D5",x"A0",x"00",x"B1",x"D3", -- 0x0BD0 - x"18",x"65",x"30",x"C5",x"31",x"90",x"03",x"20", -- 0x0BD8 - x"F0",x"CB",x"20",x"B3",x"CC",x"20",x"D4",x"CC", -- 0x0BE0 - x"D0",x"BE",x"A0",x"00",x"94",x"35",x"A2",x"34", -- 0x0BE8 - x"A5",x"30",x"48",x"A9",x"0D",x"20",x"D9",x"CC", -- 0x0BF0 - x"68",x"2C",x"F1",x"02",x"30",x"04",x"C5",x"31", -- 0x0BF8 - x"F0",x"09",x"A9",x"00",x"85",x"30",x"A9",x"0A", -- 0x0C00 - x"20",x"D9",x"CC",x"60",x"A5",x"30",x"2C",x"F1", -- 0x0C08 - x"02",x"30",x"04",x"38",x"ED",x"53",x"02",x"38", -- 0x0C10 - x"E9",x"08",x"B0",x"FC",x"49",x"FF",x"69",x"01", -- 0x0C18 - x"AA",x"18",x"65",x"30",x"C5",x"31",x"90",x"1F", -- 0x0C20 - x"20",x"F0",x"CB",x"4C",x"4B",x"CC",x"08",x"20", -- 0x0C28 - x"C5",x"D8",x"C9",x"29",x"D0",x"20",x"28",x"90", -- 0x0C30 - x"0E",x"8A",x"C5",x"31",x"90",x"03",x"4C",x"36", -- 0x0C38 - x"D3",x"38",x"E5",x"30",x"90",x"05",x"AA",x"E8", -- 0x0C40 - x"CA",x"D0",x"06",x"20",x"E2",x"00",x"4C",x"AD", -- 0x0C48 - x"CB",x"20",x"D4",x"CC",x"D0",x"F2",x"4C",x"70", -- 0x0C50 - x"D0",x"2C",x"F1",x"02",x"30",x"F8",x"AE",x"1F", -- 0x0C58 - x"02",x"F0",x"03",x"4C",x"F7",x"EA",x"20",x"C5", -- 0x0C60 - x"D8",x"E0",x"28",x"B0",x"40",x"86",x"0C",x"20", -- 0x0C68 - x"65",x"D0",x"20",x"C8",x"D8",x"E8",x"E0",x"1C", -- 0x0C70 - x"B0",x"33",x"AD",x"6A",x"02",x"48",x"29",x"FE", -- 0x0C78 - x"8D",x"6A",x"02",x"A9",x"00",x"20",x"01",x"F8", -- 0x0C80 - x"A5",x"0C",x"8D",x"69",x"02",x"8A",x"8D",x"68", -- 0x0C88 - x"02",x"20",x"0C",x"DA",x"A5",x"1F",x"A4",x"20", -- 0x0C90 - x"85",x"12",x"84",x"13",x"68",x"8D",x"6A",x"02", -- 0x0C98 - x"A9",x"01",x"20",x"01",x"F8",x"A9",x"3B",x"20", -- 0x0CA0 - x"67",x"D0",x"4C",x"AD",x"CB",x"4C",x"C2",x"D8", -- 0x0CA8 - x"20",x"B5",x"D5",x"20",x"D0",x"D7",x"AA",x"A0", -- 0x0CB0 - x"00",x"E8",x"CA",x"F0",x"10",x"B1",x"91",x"20", -- 0x0CB8 - x"D9",x"CC",x"C8",x"C9",x"0D",x"D0",x"F3",x"20", -- 0x0CC0 - x"0B",x"CC",x"4C",x"BA",x"CC",x"60",x"A9",x"0C", -- 0x0CC8 - x"2C",x"A9",x"11",x"2C",x"A9",x"20",x"2C",x"A9", -- 0x0CD0 - x"3F",x"24",x"2E",x"30",x"33",x"48",x"C9",x"20", -- 0x0CD8 - x"90",x"0B",x"A5",x"30",x"C5",x"31",x"D0",x"03", -- 0x0CE0 - x"20",x"F0",x"CB",x"E6",x"30",x"68",x"2C",x"F1", -- 0x0CE8 - x"02",x"10",x"08",x"48",x"20",x"3E",x"02",x"68", -- 0x0CF0 - x"29",x"FF",x"60",x"86",x"27",x"AA",x"20",x"7C", -- 0x0CF8 - x"F7",x"C9",x"20",x"90",x"04",x"C9",x"7F",x"D0", -- 0x0D00 - x"05",x"AE",x"69",x"02",x"86",x"30",x"A6",x"27", -- 0x0D08 - x"29",x"FF",x"60",x"6C",x"F5",x"02",x"A9",x"80", -- 0x0D10 - x"2C",x"A9",x"00",x"8D",x"F4",x"02",x"60",x"A5", -- 0x0D18 - x"2C",x"F0",x"13",x"30",x"04",x"A0",x"FF",x"D0", -- 0x0D20 - x"04",x"A5",x"AE",x"A4",x"AF",x"85",x"A8",x"84", -- 0x0D28 - x"A9",x"A2",x"A8",x"4C",x"7E",x"C4",x"A9",x"85", -- 0x0D30 - x"A0",x"CE",x"20",x"B0",x"CC",x"A5",x"AC",x"A4", -- 0x0D38 - x"AD",x"85",x"E9",x"84",x"EA",x"60",x"20",x"D2", -- 0x0D40 - x"D4",x"A2",x"36",x"A0",x"00",x"84",x"36",x"A9", -- 0x0D48 - x"40",x"20",x"8F",x"CD",x"60",x"46",x"2E",x"C9", -- 0x0D50 - x"22",x"D0",x"0B",x"20",x"25",x"D0",x"A9",x"3B", -- 0x0D58 - x"20",x"67",x"D0",x"20",x"B3",x"CC",x"20",x"D2", -- 0x0D60 - x"D4",x"A9",x"2C",x"85",x"34",x"A9",x"00",x"85", -- 0x0D68 - x"17",x"20",x"80",x"CD",x"A5",x"35",x"D0",x"16", -- 0x0D70 - x"A5",x"17",x"F0",x"F1",x"18",x"4C",x"80",x"C9", -- 0x0D78 - x"20",x"D7",x"CC",x"20",x"D4",x"CC",x"4C",x"92", -- 0x0D80 - x"C5",x"A6",x"B0",x"A4",x"B1",x"A9",x"98",x"85", -- 0x0D88 - x"2C",x"86",x"B2",x"84",x"B3",x"20",x"88",x"D1", -- 0x0D90 - x"85",x"B8",x"84",x"B9",x"A5",x"E9",x"A4",x"EA", -- 0x0D98 - x"85",x"BA",x"84",x"BB",x"A6",x"B2",x"A4",x"B3", -- 0x0DA0 - x"86",x"E9",x"84",x"EA",x"20",x"E8",x"00",x"D0", -- 0x0DA8 - x"1D",x"24",x"2C",x"50",x"0D",x"20",x"78",x"EB", -- 0x0DB0 - x"10",x"FB",x"85",x"35",x"A2",x"34",x"A0",x"00", -- 0x0DB8 - x"F0",x"08",x"30",x"71",x"20",x"D7",x"CC",x"20", -- 0x0DC0 - x"80",x"CD",x"86",x"E9",x"84",x"EA",x"20",x"E2", -- 0x0DC8 - x"00",x"24",x"28",x"10",x"31",x"24",x"2C",x"50", -- 0x0DD0 - x"09",x"E8",x"86",x"E9",x"A9",x"00",x"85",x"24", -- 0x0DD8 - x"F0",x"0C",x"85",x"24",x"C9",x"22",x"F0",x"07", -- 0x0DE0 - x"A9",x"3A",x"85",x"24",x"A9",x"2C",x"18",x"85", -- 0x0DE8 - x"25",x"A5",x"E9",x"A4",x"EA",x"69",x"00",x"90", -- 0x0DF0 - x"01",x"C8",x"20",x"BB",x"D5",x"20",x"0D",x"D9", -- 0x0DF8 - x"20",x"51",x"CB",x"4C",x"0E",x"CE",x"20",x"E7", -- 0x0E00 - x"DF",x"A5",x"29",x"20",x"39",x"CB",x"20",x"E8", -- 0x0E08 - x"00",x"F0",x"07",x"C9",x"2C",x"F0",x"03",x"4C", -- 0x0E10 - x"1F",x"CD",x"A5",x"E9",x"A4",x"EA",x"85",x"B2", -- 0x0E18 - x"84",x"B3",x"A5",x"BA",x"A4",x"BB",x"85",x"E9", -- 0x0E20 - x"84",x"EA",x"20",x"E8",x"00",x"F0",x"2C",x"20", -- 0x0E28 - x"65",x"D0",x"4C",x"95",x"CD",x"20",x"4E",x"CA", -- 0x0E30 - x"C8",x"AA",x"D0",x"12",x"A2",x"2A",x"C8",x"B1", -- 0x0E38 - x"E9",x"F0",x"69",x"C8",x"B1",x"E9",x"85",x"AE", -- 0x0E40 - x"C8",x"B1",x"E9",x"C8",x"85",x"AF",x"B1",x"E9", -- 0x0E48 - x"AA",x"20",x"3F",x"CA",x"E0",x"91",x"D0",x"DD", -- 0x0E50 - x"4C",x"CE",x"CD",x"A5",x"B2",x"A4",x"B3",x"A6", -- 0x0E58 - x"2C",x"10",x"03",x"4C",x"5C",x"C9",x"A0",x"00", -- 0x0E60 - x"B1",x"B2",x"F0",x"07",x"A9",x"74",x"A0",x"CE", -- 0x0E68 - x"4C",x"B0",x"CC",x"60",x"3F",x"45",x"58",x"54", -- 0x0E70 - x"52",x"41",x"20",x"49",x"47",x"4E",x"4F",x"52", -- 0x0E78 - x"45",x"44",x"0D",x"0A",x"00",x"3F",x"52",x"45", -- 0x0E80 - x"44",x"4F",x"20",x"46",x"52",x"4F",x"4D",x"20", -- 0x0E88 - x"53",x"54",x"41",x"52",x"54",x"0D",x"0A",x"00", -- 0x0E90 - x"D0",x"04",x"A0",x"00",x"F0",x"03",x"20",x"88", -- 0x0E98 - x"D1",x"85",x"B8",x"84",x"B9",x"20",x"C6",x"C3", -- 0x0EA0 - x"F0",x"04",x"A2",x"00",x"F0",x"66",x"9A",x"8A", -- 0x0EA8 - x"18",x"69",x"04",x"48",x"69",x"06",x"85",x"93", -- 0x0EB0 - x"68",x"A0",x"01",x"20",x"7B",x"DE",x"BA",x"BD", -- 0x0EB8 - x"09",x"01",x"85",x"D5",x"A5",x"B8",x"A4",x"B9", -- 0x0EC0 - x"20",x"22",x"DB",x"20",x"A9",x"DE",x"A0",x"01", -- 0x0EC8 - x"20",x"4E",x"DF",x"BA",x"38",x"FD",x"09",x"01", -- 0x0ED0 - x"F0",x"17",x"BD",x"0F",x"01",x"85",x"A8",x"BD", -- 0x0ED8 - x"10",x"01",x"85",x"A9",x"BD",x"12",x"01",x"85", -- 0x0EE0 - x"E9",x"BD",x"11",x"01",x"85",x"EA",x"4C",x"C1", -- 0x0EE8 - x"C8",x"8A",x"69",x"11",x"AA",x"9A",x"20",x"E8", -- 0x0EF0 - x"00",x"C9",x"2C",x"D0",x"F1",x"20",x"E2",x"00", -- 0x0EF8 - x"20",x"9E",x"CE",x"20",x"17",x"CF",x"18",x"24", -- 0x0F00 - x"38",x"24",x"28",x"30",x"03",x"B0",x"03",x"60", -- 0x0F08 - x"B0",x"FD",x"A2",x"A8",x"4C",x"7E",x"C4",x"A6", -- 0x0F10 - x"E9",x"D0",x"02",x"C6",x"EA",x"C6",x"E9",x"A2", -- 0x0F18 - x"00",x"24",x"48",x"8A",x"48",x"A9",x"01",x"20", -- 0x0F20 - x"37",x"C4",x"20",x"00",x"D0",x"A9",x"00",x"85", -- 0x0F28 - x"BC",x"20",x"E8",x"00",x"38",x"E9",x"D3",x"90", -- 0x0F30 - x"17",x"C9",x"03",x"B0",x"13",x"C9",x"01",x"2A", -- 0x0F38 - x"49",x"01",x"45",x"BC",x"C5",x"BC",x"90",x"61", -- 0x0F40 - x"85",x"BC",x"20",x"E2",x"00",x"4C",x"34",x"CF", -- 0x0F48 - x"A6",x"BC",x"D0",x"2C",x"B0",x"7F",x"69",x"07", -- 0x0F50 - x"90",x"7B",x"65",x"28",x"D0",x"03",x"4C",x"67", -- 0x0F58 - x"D7",x"69",x"FF",x"85",x"91",x"0A",x"65",x"91", -- 0x0F60 - x"A8",x"68",x"D9",x"CC",x"C0",x"B0",x"6B",x"20", -- 0x0F68 - x"06",x"CF",x"48",x"20",x"99",x"CF",x"68",x"A4", -- 0x0F70 - x"BA",x"10",x"17",x"AA",x"F0",x"5A",x"D0",x"63", -- 0x0F78 - x"46",x"28",x"8A",x"2A",x"A6",x"E9",x"D0",x"02", -- 0x0F80 - x"C6",x"EA",x"C6",x"E9",x"A0",x"1B",x"85",x"BC", -- 0x0F88 - x"D0",x"D7",x"D9",x"CC",x"C0",x"B0",x"4C",x"90", -- 0x0F90 - x"D9",x"B9",x"CE",x"C0",x"48",x"B9",x"CD",x"C0", -- 0x0F98 - x"48",x"20",x"AC",x"CF",x"A5",x"BC",x"4C",x"22", -- 0x0FA0 - x"CF",x"4C",x"70",x"D0",x"A5",x"D5",x"BE",x"CC", -- 0x0FA8 - x"C0",x"A8",x"68",x"85",x"91",x"68",x"85",x"92", -- 0x0FB0 - x"E6",x"91",x"D0",x"02",x"E6",x"92",x"98",x"48", -- 0x0FB8 - x"20",x"F4",x"DE",x"A5",x"D4",x"48",x"A5",x"D3", -- 0x0FC0 - x"48",x"A5",x"D2",x"48",x"A5",x"D1",x"48",x"A5", -- 0x0FC8 - x"D0",x"48",x"6C",x"91",x"00",x"A0",x"FF",x"68", -- 0x0FD0 - x"F0",x"23",x"C9",x"64",x"F0",x"03",x"20",x"06", -- 0x0FD8 - x"CF",x"84",x"BA",x"68",x"4A",x"85",x"2D",x"68", -- 0x0FE0 - x"85",x"D8",x"68",x"85",x"D9",x"68",x"85",x"DA", -- 0x0FE8 - x"68",x"85",x"DB",x"68",x"85",x"DC",x"68",x"85", -- 0x0FF0 - x"DD",x"45",x"D5",x"85",x"DE",x"A5",x"D0",x"60", -- 0x0FF8 - x"A9",x"00",x"85",x"28",x"20",x"E2",x"00",x"B0", -- 0x1000 - x"03",x"4C",x"E7",x"DF",x"20",x"16",x"D2",x"B0", -- 0x1008 - x"6B",x"C9",x"2E",x"F0",x"F4",x"C9",x"23",x"F0", -- 0x1010 - x"F0",x"C9",x"CD",x"F0",x"58",x"C9",x"CC",x"F0", -- 0x1018 - x"E3",x"C9",x"22",x"D0",x"0F",x"A5",x"E9",x"A4", -- 0x1020 - x"EA",x"69",x"00",x"90",x"01",x"C8",x"20",x"B5", -- 0x1028 - x"D5",x"4C",x"0D",x"D9",x"C9",x"CA",x"D0",x"13", -- 0x1030 - x"A0",x"18",x"D0",x"3B",x"20",x"A9",x"D2",x"A5", -- 0x1038 - x"D4",x"49",x"FF",x"A8",x"A5",x"D3",x"49",x"FF", -- 0x1040 - x"4C",x"99",x"D4",x"C9",x"C4",x"D0",x"03",x"4C", -- 0x1048 - x"22",x"D5",x"C9",x"D6",x"90",x"03",x"4C",x"A0", -- 0x1050 - x"D0",x"20",x"62",x"D0",x"20",x"17",x"CF",x"A9", -- 0x1058 - x"29",x"2C",x"A9",x"28",x"2C",x"A9",x"2C",x"A0", -- 0x1060 - x"00",x"D1",x"E9",x"D0",x"03",x"4C",x"E2",x"00", -- 0x1068 - x"A2",x"10",x"4C",x"7E",x"C4",x"A0",x"15",x"68", -- 0x1070 - x"68",x"4C",x"73",x"CF",x"20",x"88",x"D1",x"85", -- 0x1078 - x"D3",x"84",x"D4",x"A6",x"28",x"F0",x"05",x"A2", -- 0x1080 - x"00",x"86",x"DF",x"60",x"A6",x"29",x"10",x"0D", -- 0x1088 - x"A0",x"00",x"B1",x"D3",x"AA",x"C8",x"B1",x"D3", -- 0x1090 - x"A8",x"8A",x"4C",x"99",x"D4",x"4C",x"7B",x"DE", -- 0x1098 - x"0A",x"48",x"AA",x"20",x"E2",x"00",x"E0",x"DB", -- 0x10A0 - x"90",x"24",x"E0",x"E7",x"90",x"23",x"20",x"62", -- 0x10A8 - x"D0",x"20",x"17",x"CF",x"20",x"65",x"D0",x"20", -- 0x10B0 - x"08",x"CF",x"68",x"AA",x"A5",x"D4",x"48",x"A5", -- 0x10B8 - x"D3",x"48",x"8A",x"48",x"20",x"C8",x"D8",x"68", -- 0x10C0 - x"A8",x"8A",x"48",x"4C",x"D3",x"D0",x"20",x"59", -- 0x10C8 - x"D0",x"68",x"A8",x"B9",x"DE",x"BF",x"85",x"C4", -- 0x10D0 - x"B9",x"DF",x"BF",x"85",x"C5",x"20",x"C3",x"00", -- 0x10D8 - x"4C",x"06",x"CF",x"A0",x"FF",x"2C",x"A0",x"00", -- 0x10E0 - x"84",x"26",x"20",x"A9",x"D2",x"A5",x"D3",x"45", -- 0x10E8 - x"26",x"85",x"24",x"A5",x"D4",x"45",x"26",x"85", -- 0x10F0 - x"25",x"20",x"D5",x"DE",x"20",x"A9",x"D2",x"A5", -- 0x10F8 - x"D4",x"45",x"26",x"25",x"25",x"45",x"26",x"A8", -- 0x1100 - x"A5",x"D3",x"45",x"26",x"25",x"24",x"45",x"26", -- 0x1108 - x"4C",x"99",x"D4",x"20",x"09",x"CF",x"B0",x"13", -- 0x1110 - x"A5",x"DD",x"09",x"7F",x"25",x"D9",x"85",x"D9", -- 0x1118 - x"A9",x"D8",x"A0",x"00",x"20",x"4C",x"DF",x"AA", -- 0x1120 - x"4C",x"5E",x"D1",x"A9",x"00",x"85",x"28",x"C6", -- 0x1128 - x"BC",x"20",x"D0",x"D7",x"85",x"D0",x"86",x"D1", -- 0x1130 - x"84",x"D2",x"A5",x"DB",x"A4",x"DC",x"20",x"D4", -- 0x1138 - x"D7",x"86",x"DB",x"84",x"DC",x"AA",x"38",x"E5", -- 0x1140 - x"D0",x"F0",x"08",x"A9",x"01",x"90",x"04",x"A6", -- 0x1148 - x"D0",x"A9",x"FF",x"85",x"D5",x"A0",x"FF",x"E8", -- 0x1150 - x"C8",x"CA",x"D0",x"07",x"A6",x"D5",x"30",x"0F", -- 0x1158 - x"18",x"90",x"0C",x"B1",x"DB",x"D1",x"D1",x"F0", -- 0x1160 - x"EF",x"A2",x"FF",x"B0",x"02",x"A2",x"01",x"E8", -- 0x1168 - x"8A",x"2A",x"25",x"2D",x"F0",x"02",x"A9",x"FF", -- 0x1170 - x"4C",x"24",x"DF",x"20",x"65",x"D0",x"AA",x"20", -- 0x1178 - x"8D",x"D1",x"20",x"E8",x"00",x"D0",x"F4",x"60", -- 0x1180 - x"A2",x"00",x"20",x"E8",x"00",x"86",x"27",x"85", -- 0x1188 - x"B4",x"20",x"E8",x"00",x"20",x"16",x"D2",x"B0", -- 0x1190 - x"03",x"4C",x"70",x"D0",x"A2",x"00",x"86",x"28", -- 0x1198 - x"86",x"29",x"20",x"E2",x"00",x"90",x"05",x"20", -- 0x11A0 - x"16",x"D2",x"90",x"0B",x"AA",x"20",x"E2",x"00", -- 0x11A8 - x"90",x"FB",x"20",x"16",x"D2",x"B0",x"F6",x"C9", -- 0x11B0 - x"24",x"D0",x"06",x"A9",x"FF",x"85",x"28",x"D0", -- 0x11B8 - x"10",x"C9",x"25",x"D0",x"13",x"A5",x"2B",x"30", -- 0x11C0 - x"D0",x"A9",x"80",x"85",x"29",x"05",x"B4",x"85", -- 0x11C8 - x"B4",x"8A",x"09",x"80",x"AA",x"20",x"E2",x"00", -- 0x11D0 - x"86",x"B5",x"38",x"05",x"2B",x"E9",x"28",x"D0", -- 0x11D8 - x"03",x"4C",x"BB",x"D2",x"24",x"2B",x"70",x"F9", -- 0x11E0 - x"A9",x"00",x"85",x"2B",x"A5",x"9C",x"A6",x"9D", -- 0x11E8 - x"A0",x"00",x"86",x"CF",x"85",x"CE",x"E4",x"9F", -- 0x11F0 - x"D0",x"04",x"C5",x"9E",x"F0",x"24",x"A5",x"B4", -- 0x11F8 - x"D1",x"CE",x"D0",x"08",x"A5",x"B5",x"C8",x"D1", -- 0x1200 - x"CE",x"F0",x"6C",x"88",x"18",x"A5",x"CE",x"69", -- 0x1208 - x"07",x"90",x"E1",x"E8",x"D0",x"DC",x"C9",x"41", -- 0x1210 - x"90",x"07",x"E9",x"5B",x"38",x"E9",x"A5",x"B0", -- 0x1218 - x"00",x"60",x"68",x"48",x"C9",x"7E",x"D0",x"0D", -- 0x1220 - x"BA",x"BD",x"02",x"01",x"C9",x"D0",x"D0",x"05", -- 0x1228 - x"A9",x"07",x"A0",x"E2",x"60",x"A5",x"9E",x"A4", -- 0x1230 - x"9F",x"85",x"CE",x"84",x"CF",x"A5",x"A0",x"A4", -- 0x1238 - x"A1",x"85",x"C9",x"84",x"CA",x"18",x"69",x"07", -- 0x1240 - x"90",x"01",x"C8",x"85",x"C7",x"84",x"C8",x"20", -- 0x1248 - x"F4",x"C3",x"A5",x"C7",x"A4",x"C8",x"C8",x"85", -- 0x1250 - x"9E",x"84",x"9F",x"A0",x"00",x"A5",x"B4",x"91", -- 0x1258 - x"CE",x"C8",x"A5",x"B5",x"91",x"CE",x"A9",x"00", -- 0x1260 - x"C8",x"91",x"CE",x"C8",x"91",x"CE",x"C8",x"91", -- 0x1268 - x"CE",x"C8",x"91",x"CE",x"C8",x"91",x"CE",x"A5", -- 0x1270 - x"CE",x"18",x"69",x"02",x"A4",x"CF",x"90",x"01", -- 0x1278 - x"C8",x"85",x"B6",x"84",x"B7",x"60",x"A5",x"26", -- 0x1280 - x"0A",x"69",x"05",x"65",x"CE",x"A4",x"CF",x"90", -- 0x1288 - x"01",x"C8",x"85",x"C7",x"84",x"C8",x"60",x"90", -- 0x1290 - x"80",x"00",x"00",x"00",x"20",x"E2",x"00",x"20", -- 0x1298 - x"17",x"CF",x"20",x"06",x"CF",x"A5",x"D5",x"30", -- 0x12A0 - x"0D",x"A5",x"D0",x"C9",x"90",x"90",x"09",x"A9", -- 0x12A8 - x"97",x"A0",x"D2",x"20",x"4C",x"DF",x"D0",x"7E", -- 0x12B0 - x"4C",x"8C",x"DF",x"A5",x"2B",x"D0",x"47",x"A5", -- 0x12B8 - x"27",x"05",x"29",x"48",x"A5",x"28",x"48",x"A0", -- 0x12C0 - x"00",x"98",x"48",x"A5",x"B5",x"48",x"A5",x"B4", -- 0x12C8 - x"48",x"20",x"9C",x"D2",x"68",x"85",x"B4",x"68", -- 0x12D0 - x"85",x"B5",x"68",x"A8",x"BA",x"BD",x"02",x"01", -- 0x12D8 - x"48",x"BD",x"01",x"01",x"48",x"A5",x"D3",x"9D", -- 0x12E0 - x"02",x"01",x"A5",x"D4",x"9D",x"01",x"01",x"C8", -- 0x12E8 - x"20",x"E8",x"00",x"C9",x"2C",x"F0",x"D2",x"84", -- 0x12F0 - x"26",x"20",x"5F",x"D0",x"68",x"85",x"28",x"68", -- 0x12F8 - x"85",x"29",x"29",x"7F",x"85",x"27",x"A6",x"9E", -- 0x1300 - x"A5",x"9F",x"86",x"CE",x"85",x"CF",x"C5",x"A1", -- 0x1308 - x"D0",x"04",x"E4",x"A0",x"F0",x"3F",x"A0",x"00", -- 0x1310 - x"B1",x"CE",x"C8",x"C5",x"B4",x"D0",x"06",x"A5", -- 0x1318 - x"B5",x"D1",x"CE",x"F0",x"16",x"C8",x"B1",x"CE", -- 0x1320 - x"18",x"65",x"CE",x"AA",x"C8",x"B1",x"CE",x"65", -- 0x1328 - x"CF",x"90",x"D7",x"A2",x"6B",x"2C",x"A2",x"35", -- 0x1330 - x"4C",x"7E",x"C4",x"A2",x"78",x"A5",x"27",x"D0", -- 0x1338 - x"F7",x"A5",x"2B",x"F0",x"02",x"38",x"60",x"20", -- 0x1340 - x"86",x"D2",x"A5",x"26",x"A0",x"04",x"D1",x"CE", -- 0x1348 - x"D0",x"E1",x"4C",x"EB",x"D3",x"A5",x"2B",x"F0", -- 0x1350 - x"08",x"20",x"3D",x"E9",x"A2",x"2A",x"4C",x"7E", -- 0x1358 - x"C4",x"20",x"86",x"D2",x"20",x"44",x"C4",x"A9", -- 0x1360 - x"00",x"A8",x"85",x"E1",x"A2",x"05",x"A5",x"B4", -- 0x1368 - x"91",x"CE",x"10",x"01",x"CA",x"C8",x"A5",x"B5", -- 0x1370 - x"91",x"CE",x"10",x"02",x"CA",x"CA",x"86",x"E0", -- 0x1378 - x"A5",x"26",x"C8",x"C8",x"C8",x"91",x"CE",x"A2", -- 0x1380 - x"0B",x"A9",x"00",x"24",x"27",x"50",x"08",x"68", -- 0x1388 - x"18",x"69",x"01",x"AA",x"68",x"69",x"00",x"C8", -- 0x1390 - x"91",x"CE",x"C8",x"8A",x"91",x"CE",x"20",x"4D", -- 0x1398 - x"D4",x"86",x"E0",x"85",x"E1",x"A4",x"91",x"C6", -- 0x13A0 - x"26",x"D0",x"DC",x"65",x"C8",x"B0",x"5D",x"85", -- 0x13A8 - x"C8",x"A8",x"8A",x"65",x"C7",x"90",x"03",x"C8", -- 0x13B0 - x"F0",x"52",x"20",x"44",x"C4",x"85",x"A0",x"84", -- 0x13B8 - x"A1",x"A9",x"00",x"E6",x"E1",x"A4",x"E0",x"F0", -- 0x13C0 - x"05",x"88",x"91",x"C7",x"D0",x"FB",x"C6",x"C8", -- 0x13C8 - x"C6",x"E1",x"D0",x"F5",x"E6",x"C8",x"38",x"A5", -- 0x13D0 - x"A0",x"E5",x"CE",x"A0",x"02",x"91",x"CE",x"A5", -- 0x13D8 - x"A1",x"C8",x"E5",x"CF",x"91",x"CE",x"A5",x"27", -- 0x13E0 - x"D0",x"62",x"C8",x"B1",x"CE",x"85",x"26",x"A9", -- 0x13E8 - x"00",x"85",x"E0",x"85",x"E1",x"C8",x"68",x"AA", -- 0x13F0 - x"85",x"D3",x"68",x"85",x"D4",x"D1",x"CE",x"90", -- 0x13F8 - x"0E",x"D0",x"06",x"C8",x"8A",x"D1",x"CE",x"90", -- 0x1400 - x"07",x"4C",x"33",x"D3",x"4C",x"7C",x"C4",x"C8", -- 0x1408 - x"A5",x"E1",x"05",x"E0",x"18",x"F0",x"0A",x"20", -- 0x1410 - x"4D",x"D4",x"8A",x"65",x"D3",x"AA",x"98",x"A4", -- 0x1418 - x"91",x"65",x"D4",x"86",x"E0",x"C6",x"26",x"D0", -- 0x1420 - x"CA",x"85",x"E1",x"A2",x"05",x"A5",x"B4",x"10", -- 0x1428 - x"01",x"CA",x"A5",x"B5",x"10",x"02",x"CA",x"CA", -- 0x1430 - x"86",x"97",x"A9",x"00",x"20",x"56",x"D4",x"8A", -- 0x1438 - x"65",x"C7",x"85",x"B6",x"98",x"65",x"C8",x"85", -- 0x1440 - x"B7",x"A8",x"A5",x"B6",x"60",x"84",x"91",x"B1", -- 0x1448 - x"CE",x"85",x"97",x"88",x"B1",x"CE",x"85",x"98", -- 0x1450 - x"A9",x"10",x"85",x"CC",x"A2",x"00",x"A0",x"00", -- 0x1458 - x"8A",x"0A",x"AA",x"98",x"2A",x"A8",x"B0",x"A4", -- 0x1460 - x"06",x"E0",x"26",x"E1",x"90",x"0B",x"18",x"8A", -- 0x1468 - x"65",x"97",x"AA",x"98",x"65",x"98",x"A8",x"B0", -- 0x1470 - x"93",x"C6",x"CC",x"D0",x"E3",x"60",x"A5",x"28", -- 0x1478 - x"F0",x"03",x"20",x"D0",x"D7",x"20",x"50",x"D6", -- 0x1480 - x"38",x"A5",x"A2",x"E5",x"A0",x"A8",x"A5",x"A3", -- 0x1488 - x"E5",x"A1",x"A2",x"00",x"86",x"28",x"4C",x"40", -- 0x1490 - x"DF",x"A2",x"00",x"86",x"28",x"85",x"D1",x"84", -- 0x1498 - x"D2",x"A2",x"90",x"4C",x"2C",x"DF",x"20",x"CB", -- 0x14A0 - x"D8",x"8A",x"F0",x"08",x"AC",x"58",x"02",x"2C", -- 0x14A8 - x"F1",x"02",x"10",x"02",x"A4",x"30",x"A9",x"00", -- 0x14B0 - x"F0",x"DF",x"C9",x"D9",x"D0",x"21",x"20",x"E2", -- 0x14B8 - x"00",x"A9",x"D4",x"20",x"67",x"D0",x"20",x"53", -- 0x14C0 - x"E8",x"A5",x"33",x"A4",x"34",x"85",x"22",x"84", -- 0x14C8 - x"23",x"60",x"A6",x"A9",x"E8",x"D0",x"FA",x"A2", -- 0x14D0 - x"95",x"2C",x"A2",x"E5",x"4C",x"7E",x"C4",x"20", -- 0x14D8 - x"0D",x"D5",x"20",x"D2",x"D4",x"20",x"62",x"D0", -- 0x14E0 - x"A9",x"80",x"85",x"2B",x"20",x"88",x"D1",x"20", -- 0x14E8 - x"06",x"CF",x"20",x"5F",x"D0",x"A9",x"D4",x"20", -- 0x14F0 - x"67",x"D0",x"48",x"A5",x"B7",x"48",x"A5",x"B6", -- 0x14F8 - x"48",x"A5",x"EA",x"48",x"A5",x"E9",x"48",x"20", -- 0x1500 - x"3C",x"CA",x"4C",x"7D",x"D5",x"A9",x"C4",x"20", -- 0x1508 - x"67",x"D0",x"09",x"80",x"A2",x"80",x"86",x"2B", -- 0x1510 - x"20",x"8F",x"D1",x"85",x"BD",x"84",x"BE",x"4C", -- 0x1518 - x"06",x"CF",x"20",x"0D",x"D5",x"A5",x"BE",x"48", -- 0x1520 - x"A5",x"BD",x"48",x"20",x"59",x"D0",x"20",x"06", -- 0x1528 - x"CF",x"68",x"85",x"BD",x"68",x"85",x"BE",x"A0", -- 0x1530 - x"02",x"B1",x"BD",x"85",x"B6",x"AA",x"C8",x"B1", -- 0x1538 - x"BD",x"F0",x"97",x"85",x"B7",x"C8",x"B1",x"B6", -- 0x1540 - x"48",x"88",x"10",x"FA",x"A4",x"B7",x"20",x"AD", -- 0x1548 - x"DE",x"A5",x"EA",x"48",x"A5",x"E9",x"48",x"B1", -- 0x1550 - x"BD",x"85",x"E9",x"C8",x"B1",x"BD",x"85",x"EA", -- 0x1558 - x"A5",x"B7",x"48",x"A5",x"B6",x"48",x"20",x"03", -- 0x1560 - x"CF",x"68",x"85",x"BD",x"68",x"85",x"BE",x"20", -- 0x1568 - x"E8",x"00",x"F0",x"03",x"4C",x"70",x"D0",x"68", -- 0x1570 - x"85",x"E9",x"68",x"85",x"EA",x"A0",x"00",x"68", -- 0x1578 - x"91",x"BD",x"68",x"C8",x"91",x"BD",x"68",x"C8", -- 0x1580 - x"91",x"BD",x"68",x"C8",x"91",x"BD",x"68",x"C8", -- 0x1588 - x"91",x"BD",x"60",x"20",x"06",x"CF",x"A0",x"00", -- 0x1590 - x"20",x"D7",x"E0",x"68",x"68",x"A9",x"FF",x"A0", -- 0x1598 - x"00",x"F0",x"12",x"A6",x"D3",x"A4",x"D4",x"86", -- 0x15A0 - x"BF",x"84",x"C0",x"20",x"1E",x"D6",x"86",x"D1", -- 0x15A8 - x"84",x"D2",x"85",x"D0",x"60",x"A2",x"22",x"86", -- 0x15B0 - x"24",x"86",x"25",x"85",x"DE",x"84",x"DF",x"85", -- 0x15B8 - x"D1",x"84",x"D2",x"A0",x"FF",x"C8",x"B1",x"DE", -- 0x15C0 - x"F0",x"0C",x"C5",x"24",x"F0",x"04",x"C5",x"25", -- 0x15C8 - x"D0",x"F3",x"C9",x"22",x"F0",x"01",x"18",x"84", -- 0x15D0 - x"D0",x"98",x"65",x"DE",x"85",x"E0",x"A6",x"DF", -- 0x15D8 - x"90",x"01",x"E8",x"86",x"E1",x"A5",x"DF",x"D0", -- 0x15E0 - x"0B",x"98",x"20",x"A3",x"D5",x"A6",x"DE",x"A4", -- 0x15E8 - x"DF",x"20",x"B2",x"D7",x"A6",x"85",x"E0",x"91", -- 0x15F0 - x"D0",x"05",x"A2",x"C4",x"4C",x"7E",x"C4",x"A5", -- 0x15F8 - x"D0",x"95",x"00",x"A5",x"D1",x"95",x"01",x"A5", -- 0x1600 - x"D2",x"95",x"02",x"A0",x"00",x"86",x"D3",x"84", -- 0x1608 - x"D4",x"84",x"DF",x"88",x"84",x"28",x"86",x"86", -- 0x1610 - x"E8",x"E8",x"E8",x"86",x"85",x"60",x"46",x"2A", -- 0x1618 - x"48",x"49",x"FF",x"38",x"65",x"A2",x"A4",x"A3", -- 0x1620 - x"B0",x"01",x"88",x"C4",x"A1",x"90",x"11",x"D0", -- 0x1628 - x"04",x"C5",x"A0",x"90",x"0B",x"85",x"A2",x"84", -- 0x1630 - x"A3",x"85",x"A4",x"84",x"A5",x"AA",x"68",x"60", -- 0x1638 - x"A2",x"4D",x"A5",x"2A",x"30",x"B6",x"20",x"50", -- 0x1640 - x"D6",x"A9",x"80",x"85",x"2A",x"68",x"D0",x"D0", -- 0x1648 - x"A6",x"A6",x"A5",x"A7",x"86",x"A2",x"85",x"A3", -- 0x1650 - x"A0",x"00",x"84",x"BE",x"84",x"BD",x"A5",x"A0", -- 0x1658 - x"A6",x"A1",x"85",x"CE",x"86",x"CF",x"A9",x"88", -- 0x1660 - x"A2",x"00",x"85",x"91",x"86",x"92",x"C5",x"85", -- 0x1668 - x"F0",x"05",x"20",x"F1",x"D6",x"F0",x"F7",x"A9", -- 0x1670 - x"07",x"85",x"C2",x"A5",x"9C",x"A6",x"9D",x"85", -- 0x1678 - x"91",x"86",x"92",x"E4",x"9F",x"D0",x"04",x"C5", -- 0x1680 - x"9E",x"F0",x"05",x"20",x"E7",x"D6",x"F0",x"F3", -- 0x1688 - x"85",x"C7",x"86",x"C8",x"A9",x"03",x"85",x"C2", -- 0x1690 - x"A5",x"C7",x"A6",x"C8",x"E4",x"A1",x"D0",x"07", -- 0x1698 - x"C5",x"A0",x"D0",x"03",x"4C",x"30",x"D7",x"85", -- 0x16A0 - x"91",x"86",x"92",x"A0",x"00",x"B1",x"91",x"AA", -- 0x16A8 - x"C8",x"B1",x"91",x"08",x"C8",x"B1",x"91",x"65", -- 0x16B0 - x"C7",x"85",x"C7",x"C8",x"B1",x"91",x"65",x"C8", -- 0x16B8 - x"85",x"C8",x"28",x"10",x"D3",x"8A",x"30",x"D0", -- 0x16C0 - x"C8",x"B1",x"91",x"A0",x"00",x"0A",x"69",x"05", -- 0x16C8 - x"65",x"91",x"85",x"91",x"90",x"02",x"E6",x"92", -- 0x16D0 - x"A6",x"92",x"E4",x"C8",x"D0",x"04",x"C5",x"C7", -- 0x16D8 - x"F0",x"BA",x"20",x"F1",x"D6",x"F0",x"F3",x"B1", -- 0x16E0 - x"91",x"30",x"35",x"C8",x"B1",x"91",x"10",x"30", -- 0x16E8 - x"C8",x"B1",x"91",x"F0",x"2B",x"C8",x"B1",x"91", -- 0x16F0 - x"AA",x"C8",x"B1",x"91",x"C5",x"A3",x"90",x"06", -- 0x16F8 - x"D0",x"1E",x"E4",x"A2",x"B0",x"1A",x"C5",x"CF", -- 0x1700 - x"90",x"16",x"D0",x"04",x"E4",x"CE",x"90",x"10", -- 0x1708 - x"86",x"CE",x"85",x"CF",x"A5",x"91",x"A6",x"92", -- 0x1710 - x"85",x"BD",x"86",x"BE",x"A5",x"C2",x"85",x"C4", -- 0x1718 - x"A5",x"C2",x"18",x"65",x"91",x"85",x"91",x"90", -- 0x1720 - x"02",x"E6",x"92",x"A6",x"92",x"A0",x"00",x"60", -- 0x1728 - x"A5",x"BE",x"05",x"BD",x"F0",x"F5",x"A5",x"C4", -- 0x1730 - x"29",x"04",x"4A",x"A8",x"85",x"C4",x"B1",x"BD", -- 0x1738 - x"65",x"CE",x"85",x"C9",x"A5",x"CF",x"69",x"00", -- 0x1740 - x"85",x"CA",x"A5",x"A2",x"A6",x"A3",x"85",x"C7", -- 0x1748 - x"86",x"C8",x"20",x"FB",x"C3",x"A4",x"C4",x"C8", -- 0x1750 - x"A5",x"C7",x"91",x"BD",x"AA",x"E6",x"C8",x"A5", -- 0x1758 - x"C8",x"C8",x"91",x"BD",x"4C",x"54",x"D6",x"A5", -- 0x1760 - x"D4",x"48",x"A5",x"D3",x"48",x"20",x"00",x"D0", -- 0x1768 - x"20",x"08",x"CF",x"68",x"85",x"DE",x"68",x"85", -- 0x1770 - x"DF",x"A0",x"00",x"B1",x"DE",x"18",x"71",x"D3", -- 0x1778 - x"90",x"05",x"A2",x"B5",x"4C",x"7E",x"C4",x"20", -- 0x1780 - x"A3",x"D5",x"20",x"A4",x"D7",x"A5",x"BF",x"A4", -- 0x1788 - x"C0",x"20",x"D4",x"D7",x"20",x"B6",x"D7",x"A5", -- 0x1790 - x"DE",x"A4",x"DF",x"20",x"D4",x"D7",x"20",x"F4", -- 0x1798 - x"D5",x"4C",x"31",x"CF",x"A0",x"00",x"B1",x"DE", -- 0x17A0 - x"48",x"C8",x"B1",x"DE",x"AA",x"C8",x"B1",x"DE", -- 0x17A8 - x"A8",x"68",x"86",x"91",x"84",x"92",x"A8",x"F0", -- 0x17B0 - x"0A",x"48",x"88",x"B1",x"91",x"91",x"A4",x"98", -- 0x17B8 - x"D0",x"F8",x"68",x"18",x"65",x"A4",x"85",x"A4", -- 0x17C0 - x"90",x"02",x"E6",x"A5",x"60",x"20",x"08",x"CF", -- 0x17C8 - x"A5",x"D3",x"A4",x"D4",x"85",x"91",x"84",x"92", -- 0x17D0 - x"20",x"05",x"D8",x"08",x"A0",x"00",x"B1",x"91", -- 0x17D8 - x"48",x"C8",x"B1",x"91",x"AA",x"C8",x"B1",x"91", -- 0x17E0 - x"A8",x"68",x"28",x"D0",x"13",x"C4",x"A3",x"D0", -- 0x17E8 - x"0F",x"E4",x"A2",x"D0",x"0B",x"48",x"18",x"65", -- 0x17F0 - x"A2",x"85",x"A2",x"90",x"02",x"E6",x"A3",x"68", -- 0x17F8 - x"86",x"91",x"84",x"92",x"60",x"C4",x"87",x"D0", -- 0x1800 - x"0C",x"C5",x"86",x"D0",x"08",x"85",x"85",x"E9", -- 0x1808 - x"03",x"85",x"86",x"A0",x"00",x"60",x"20",x"CB", -- 0x1810 - x"D8",x"8A",x"48",x"A9",x"01",x"20",x"AB",x"D5", -- 0x1818 - x"68",x"A0",x"00",x"91",x"D1",x"68",x"68",x"4C", -- 0x1820 - x"F4",x"D5",x"20",x"8B",x"D8",x"D1",x"BF",x"98", -- 0x1828 - x"90",x"04",x"B1",x"BF",x"AA",x"98",x"48",x"8A", -- 0x1830 - x"48",x"20",x"AB",x"D5",x"A5",x"BF",x"A4",x"C0", -- 0x1838 - x"20",x"D4",x"D7",x"68",x"A8",x"68",x"18",x"65", -- 0x1840 - x"91",x"85",x"91",x"90",x"02",x"E6",x"92",x"98", -- 0x1848 - x"20",x"B6",x"D7",x"4C",x"F4",x"D5",x"20",x"8B", -- 0x1850 - x"D8",x"18",x"F1",x"BF",x"49",x"FF",x"4C",x"30", -- 0x1858 - x"D8",x"A9",x"FF",x"85",x"D4",x"20",x"E8",x"00", -- 0x1860 - x"C9",x"29",x"F0",x"06",x"20",x"65",x"D0",x"20", -- 0x1868 - x"C8",x"D8",x"20",x"8B",x"D8",x"F0",x"4B",x"CA", -- 0x1870 - x"8A",x"48",x"18",x"A2",x"00",x"F1",x"BF",x"B0", -- 0x1878 - x"B6",x"49",x"FF",x"C5",x"D4",x"90",x"B1",x"A5", -- 0x1880 - x"D4",x"B0",x"AD",x"20",x"5F",x"D0",x"68",x"A8", -- 0x1888 - x"68",x"85",x"C4",x"68",x"68",x"68",x"AA",x"68", -- 0x1890 - x"85",x"BF",x"68",x"85",x"C0",x"A5",x"C4",x"48", -- 0x1898 - x"98",x"48",x"A0",x"00",x"8A",x"60",x"20",x"AC", -- 0x18A0 - x"D8",x"4C",x"B6",x"D4",x"20",x"CD",x"D7",x"A2", -- 0x18A8 - x"00",x"86",x"28",x"A8",x"60",x"20",x"AC",x"D8", -- 0x18B0 - x"F0",x"08",x"A0",x"00",x"B1",x"91",x"A8",x"4C", -- 0x18B8 - x"B6",x"D4",x"4C",x"36",x"D3",x"20",x"E2",x"00", -- 0x18C0 - x"20",x"03",x"CF",x"20",x"A2",x"D2",x"A6",x"D3", -- 0x18C8 - x"D0",x"F0",x"A6",x"D4",x"4C",x"E8",x"00",x"20", -- 0x18D0 - x"AC",x"D8",x"D0",x"03",x"4C",x"B2",x"DB",x"A6", -- 0x18D8 - x"E9",x"A4",x"EA",x"86",x"E0",x"84",x"E1",x"A6", -- 0x18E0 - x"91",x"86",x"E9",x"18",x"65",x"91",x"85",x"93", -- 0x18E8 - x"A6",x"92",x"86",x"EA",x"90",x"01",x"E8",x"86", -- 0x18F0 - x"94",x"A0",x"00",x"B1",x"93",x"48",x"A9",x"00", -- 0x18F8 - x"91",x"93",x"20",x"E8",x"00",x"20",x"E7",x"DF", -- 0x1900 - x"68",x"A0",x"00",x"91",x"93",x"A6",x"E0",x"A4", -- 0x1908 - x"E1",x"86",x"E9",x"84",x"EA",x"60",x"20",x"03", -- 0x1910 - x"CF",x"20",x"22",x"D9",x"20",x"65",x"D0",x"4C", -- 0x1918 - x"C8",x"D8",x"A5",x"D5",x"30",x"9C",x"A5",x"D0", -- 0x1920 - x"C9",x"91",x"B0",x"96",x"20",x"8C",x"DF",x"A5", -- 0x1928 - x"D3",x"A4",x"D4",x"84",x"33",x"85",x"34",x"60", -- 0x1930 - x"A5",x"34",x"48",x"A5",x"33",x"48",x"20",x"22", -- 0x1938 - x"D9",x"A0",x"00",x"B1",x"33",x"A8",x"68",x"85", -- 0x1940 - x"33",x"68",x"85",x"34",x"4C",x"B6",x"D4",x"20", -- 0x1948 - x"16",x"D9",x"8A",x"A0",x"00",x"91",x"33",x"60", -- 0x1950 - x"20",x"03",x"CF",x"20",x"22",x"D9",x"A4",x"33", -- 0x1958 - x"A6",x"34",x"A9",x"02",x"4C",x"C9",x"EE",x"20", -- 0x1960 - x"53",x"E8",x"A5",x"33",x"A4",x"34",x"85",x"1D", -- 0x1968 - x"84",x"1E",x"20",x"65",x"D0",x"20",x"53",x"E8", -- 0x1970 - x"A0",x"01",x"B9",x"33",x"00",x"91",x"1D",x"88", -- 0x1978 - x"10",x"F8",x"60",x"20",x"22",x"D9",x"A0",x"01", -- 0x1980 - x"B1",x"33",x"48",x"88",x"B1",x"33",x"A8",x"68", -- 0x1988 - x"4C",x"40",x"DF",x"48",x"4A",x"4A",x"4A",x"4A", -- 0x1990 - x"20",x"9C",x"D9",x"68",x"29",x"0F",x"09",x"30", -- 0x1998 - x"C9",x"3A",x"90",x"02",x"69",x"06",x"C9",x"30", -- 0x19A0 - x"D0",x"04",x"A4",x"2F",x"F0",x"06",x"85",x"2F", -- 0x19A8 - x"9D",x"00",x"01",x"E8",x"60",x"20",x"22",x"D9", -- 0x19B0 - x"A2",x"00",x"86",x"2F",x"A9",x"23",x"85",x"FF", -- 0x19B8 - x"A5",x"34",x"20",x"93",x"D9",x"A5",x"33",x"20", -- 0x19C0 - x"93",x"D9",x"8A",x"D0",x"06",x"A9",x"30",x"9D", -- 0x19C8 - x"00",x"01",x"E8",x"A9",x"00",x"9D",x"00",x"01", -- 0x19D0 - x"4C",x"9B",x"D5",x"4C",x"70",x"D0",x"20",x"21", -- 0x19D8 - x"EC",x"20",x"C8",x"D8",x"8A",x"F0",x"06",x"CA", -- 0x19E0 - x"D0",x"F1",x"A9",x"09",x"2C",x"A9",x"08",x"A2", -- 0x19E8 - x"10",x"8E",x"F8",x"02",x"A2",x"1B",x"48",x"8A", -- 0x19F0 - x"20",x"0C",x"DA",x"AD",x"F8",x"02",x"A0",x"27", -- 0x19F8 - x"91",x"1F",x"88",x"D0",x"FB",x"68",x"91",x"1F", -- 0x1A00 - x"CA",x"D0",x"EB",x"60",x"20",x"31",x"F7",x"84", -- 0x1A08 - x"20",x"18",x"69",x"80",x"48",x"85",x"1F",x"A9", -- 0x1A10 - x"BB",x"65",x"20",x"85",x"20",x"68",x"60",x"4C", -- 0x1A18 - x"C2",x"D8",x"20",x"F6",x"DA",x"20",x"C8",x"D8", -- 0x1A20 - x"E0",x"28",x"B0",x"F3",x"8E",x"F8",x"02",x"20", -- 0x1A28 - x"65",x"D0",x"20",x"C8",x"D8",x"E0",x"1B",x"B0", -- 0x1A30 - x"E6",x"E8",x"8A",x"20",x"0C",x"DA",x"60",x"20", -- 0x1A38 - x"62",x"D0",x"20",x"22",x"DA",x"20",x"5F",x"D0", -- 0x1A40 - x"AC",x"F8",x"02",x"B1",x"1F",x"A8",x"4C",x"B6", -- 0x1A48 - x"D4",x"20",x"22",x"DA",x"20",x"65",x"D0",x"20", -- 0x1A50 - x"17",x"CF",x"24",x"28",x"10",x"1D",x"20",x"D0", -- 0x1A58 - x"D7",x"AA",x"18",x"AD",x"F8",x"02",x"65",x"1F", -- 0x1A60 - x"90",x"02",x"E6",x"20",x"85",x"1F",x"A0",x"00", -- 0x1A68 - x"E8",x"CA",x"F0",x"10",x"B1",x"91",x"91",x"1F", -- 0x1A70 - x"C8",x"D0",x"F6",x"20",x"CB",x"D8",x"8A",x"AC", -- 0x1A78 - x"F8",x"02",x"91",x"1F",x"60",x"D0",x"17",x"A9", -- 0x1A80 - x"03",x"20",x"37",x"C4",x"A5",x"EA",x"48",x"A5", -- 0x1A88 - x"E9",x"48",x"A5",x"A9",x"48",x"A5",x"A8",x"48", -- 0x1A90 - x"A9",x"8B",x"48",x"4C",x"C1",x"C8",x"4C",x"70", -- 0x1A98 - x"D0",x"A9",x"FF",x"85",x"B9",x"20",x"C6",x"C3", -- 0x1AA0 - x"9A",x"C9",x"8B",x"F0",x"05",x"A2",x"F5",x"4C", -- 0x1AA8 - x"7E",x"C4",x"C0",x"10",x"D0",x"05",x"84",x"D0", -- 0x1AB0 - x"98",x"D0",x"06",x"20",x"E8",x"00",x"20",x"17", -- 0x1AB8 - x"CF",x"68",x"A5",x"D0",x"F0",x"05",x"68",x"68", -- 0x1AC0 - x"68",x"68",x"60",x"68",x"85",x"A8",x"68",x"85", -- 0x1AC8 - x"A9",x"68",x"85",x"E9",x"68",x"85",x"EA",x"4C", -- 0x1AD0 - x"8C",x"DA",x"20",x"78",x"EB",x"08",x"48",x"10", -- 0x1AD8 - x"03",x"A9",x"01",x"2C",x"A9",x"00",x"20",x"AB", -- 0x1AE0 - x"D5",x"68",x"28",x"10",x"04",x"A0",x"00",x"91", -- 0x1AE8 - x"D1",x"68",x"68",x"4C",x"F4",x"D5",x"AD",x"C0", -- 0x1AF0 - x"02",x"29",x"01",x"F0",x"05",x"A2",x"A3",x"4C", -- 0x1AF8 - x"7E",x"C4",x"60",x"60",x"A9",x"05",x"A0",x"E2", -- 0x1B00 - x"4C",x"22",x"DB",x"20",x"51",x"DD",x"A5",x"D5", -- 0x1B08 - x"49",x"FF",x"85",x"D5",x"45",x"DD",x"85",x"DE", -- 0x1B10 - x"A5",x"D0",x"4C",x"25",x"DB",x"20",x"54",x"DC", -- 0x1B18 - x"90",x"3C",x"20",x"51",x"DD",x"D0",x"03",x"4C", -- 0x1B20 - x"D5",x"DE",x"A6",x"DF",x"86",x"C5",x"A2",x"D8", -- 0x1B28 - x"A5",x"D8",x"A8",x"F0",x"CE",x"38",x"E5",x"D0", -- 0x1B30 - x"F0",x"24",x"90",x"12",x"84",x"D0",x"A4",x"DD", -- 0x1B38 - x"84",x"D5",x"49",x"FF",x"69",x"00",x"A0",x"00", -- 0x1B40 - x"84",x"C5",x"A2",x"D0",x"D0",x"04",x"A0",x"00", -- 0x1B48 - x"84",x"DF",x"C9",x"F9",x"30",x"C7",x"A8",x"A5", -- 0x1B50 - x"DF",x"56",x"01",x"20",x"6B",x"DC",x"24",x"DE", -- 0x1B58 - x"10",x"57",x"A0",x"D0",x"E0",x"D8",x"F0",x"02", -- 0x1B60 - x"A0",x"D8",x"38",x"49",x"FF",x"65",x"C5",x"85", -- 0x1B68 - x"DF",x"B9",x"04",x"00",x"F5",x"04",x"85",x"D4", -- 0x1B70 - x"B9",x"03",x"00",x"F5",x"03",x"85",x"D3",x"B9", -- 0x1B78 - x"02",x"00",x"F5",x"02",x"85",x"D2",x"B9",x"01", -- 0x1B80 - x"00",x"F5",x"01",x"85",x"D1",x"B0",x"03",x"20", -- 0x1B88 - x"02",x"DC",x"A0",x"00",x"98",x"18",x"A6",x"D1", -- 0x1B90 - x"D0",x"4A",x"A6",x"D2",x"86",x"D1",x"A6",x"D3", -- 0x1B98 - x"86",x"D2",x"A6",x"D4",x"86",x"D3",x"A6",x"DF", -- 0x1BA0 - x"86",x"D4",x"84",x"DF",x"69",x"08",x"C9",x"28", -- 0x1BA8 - x"D0",x"E4",x"A9",x"00",x"85",x"D0",x"85",x"D5", -- 0x1BB0 - x"60",x"65",x"C5",x"85",x"DF",x"A5",x"D4",x"65", -- 0x1BB8 - x"DC",x"85",x"D4",x"A5",x"D3",x"65",x"DB",x"85", -- 0x1BC0 - x"D3",x"A5",x"D2",x"65",x"DA",x"85",x"D2",x"A5", -- 0x1BC8 - x"D1",x"65",x"D9",x"85",x"D1",x"4C",x"F1",x"DB", -- 0x1BD0 - x"69",x"01",x"06",x"DF",x"26",x"D4",x"26",x"D3", -- 0x1BD8 - x"26",x"D2",x"26",x"D1",x"10",x"F2",x"38",x"E5", -- 0x1BE0 - x"D0",x"B0",x"C7",x"49",x"FF",x"69",x"01",x"85", -- 0x1BE8 - x"D0",x"90",x"0E",x"E6",x"D0",x"F0",x"42",x"66", -- 0x1BF0 - x"D1",x"66",x"D2",x"66",x"D3",x"66",x"D4",x"66", -- 0x1BF8 - x"DF",x"60",x"A5",x"D5",x"49",x"FF",x"85",x"D5", -- 0x1C00 - x"A5",x"D1",x"49",x"FF",x"85",x"D1",x"A5",x"D2", -- 0x1C08 - x"49",x"FF",x"85",x"D2",x"A5",x"D3",x"49",x"FF", -- 0x1C10 - x"85",x"D3",x"A5",x"D4",x"49",x"FF",x"85",x"D4", -- 0x1C18 - x"A5",x"DF",x"49",x"FF",x"85",x"DF",x"E6",x"DF", -- 0x1C20 - x"D0",x"0E",x"E6",x"D4",x"D0",x"0A",x"E6",x"D3", -- 0x1C28 - x"D0",x"06",x"E6",x"D2",x"D0",x"02",x"E6",x"D1", -- 0x1C30 - x"60",x"A2",x"45",x"4C",x"7E",x"C4",x"A2",x"94", -- 0x1C38 - x"B4",x"04",x"84",x"DF",x"B4",x"03",x"94",x"04", -- 0x1C40 - x"B4",x"02",x"94",x"03",x"B4",x"01",x"94",x"02", -- 0x1C48 - x"A4",x"D7",x"94",x"01",x"69",x"08",x"30",x"E8", -- 0x1C50 - x"F0",x"E6",x"E9",x"08",x"A8",x"A5",x"DF",x"B0", -- 0x1C58 - x"14",x"16",x"01",x"90",x"02",x"F6",x"01",x"76", -- 0x1C60 - x"01",x"76",x"01",x"76",x"02",x"76",x"03",x"76", -- 0x1C68 - x"04",x"6A",x"C8",x"D0",x"EC",x"18",x"60",x"82", -- 0x1C70 - x"13",x"5D",x"8D",x"DE",x"82",x"49",x"0F",x"DA", -- 0x1C78 - x"9E",x"81",x"00",x"00",x"00",x"00",x"03",x"7F", -- 0x1C80 - x"5E",x"56",x"CB",x"79",x"80",x"13",x"9B",x"0B", -- 0x1C88 - x"64",x"80",x"76",x"38",x"93",x"16",x"82",x"38", -- 0x1C90 - x"AA",x"3B",x"20",x"80",x"35",x"04",x"F3",x"34", -- 0x1C98 - x"81",x"35",x"04",x"F3",x"34",x"80",x"80",x"00", -- 0x1CA0 - x"00",x"00",x"80",x"31",x"72",x"17",x"F8",x"20", -- 0x1CA8 - x"13",x"DF",x"F0",x"02",x"10",x"03",x"4C",x"36", -- 0x1CB0 - x"D3",x"A5",x"D0",x"E9",x"7F",x"48",x"A9",x"80", -- 0x1CB8 - x"85",x"D0",x"A9",x"9B",x"A0",x"DC",x"20",x"22", -- 0x1CC0 - x"DB",x"A9",x"A0",x"A0",x"DC",x"20",x"E4",x"DD", -- 0x1CC8 - x"A9",x"81",x"A0",x"DC",x"20",x"0B",x"DB",x"A9", -- 0x1CD0 - x"86",x"A0",x"DC",x"20",x"FD",x"E2",x"A9",x"A5", -- 0x1CD8 - x"A0",x"DC",x"20",x"22",x"DB",x"68",x"20",x"76", -- 0x1CE0 - x"E0",x"A9",x"AA",x"A0",x"DC",x"20",x"51",x"DD", -- 0x1CE8 - x"D0",x"03",x"4C",x"50",x"DD",x"20",x"7C",x"DD", -- 0x1CF0 - x"A9",x"00",x"85",x"95",x"85",x"96",x"85",x"97", -- 0x1CF8 - x"85",x"98",x"A5",x"DF",x"20",x"1E",x"DD",x"A5", -- 0x1D00 - x"D4",x"20",x"1E",x"DD",x"A5",x"D3",x"20",x"1E", -- 0x1D08 - x"DD",x"A5",x"D2",x"20",x"1E",x"DD",x"A5",x"D1", -- 0x1D10 - x"20",x"23",x"DD",x"4C",x"64",x"DE",x"D0",x"03", -- 0x1D18 - x"4C",x"3E",x"DC",x"4A",x"09",x"80",x"A8",x"90", -- 0x1D20 - x"19",x"18",x"A5",x"98",x"65",x"DC",x"85",x"98", -- 0x1D28 - x"A5",x"97",x"65",x"DB",x"85",x"97",x"A5",x"96", -- 0x1D30 - x"65",x"DA",x"85",x"96",x"A5",x"95",x"65",x"D9", -- 0x1D38 - x"85",x"95",x"66",x"95",x"66",x"96",x"66",x"97", -- 0x1D40 - x"66",x"98",x"66",x"DF",x"98",x"4A",x"D0",x"D6", -- 0x1D48 - x"60",x"85",x"91",x"84",x"92",x"A0",x"04",x"B1", -- 0x1D50 - x"91",x"85",x"DC",x"88",x"B1",x"91",x"85",x"DB", -- 0x1D58 - x"88",x"B1",x"91",x"85",x"DA",x"88",x"B1",x"91", -- 0x1D60 - x"85",x"DD",x"45",x"D5",x"85",x"DE",x"A5",x"DD", -- 0x1D68 - x"09",x"80",x"85",x"D9",x"88",x"B1",x"91",x"85", -- 0x1D70 - x"D8",x"A5",x"D0",x"60",x"A5",x"D8",x"F0",x"1F", -- 0x1D78 - x"18",x"65",x"D0",x"90",x"04",x"30",x"1D",x"18", -- 0x1D80 - x"2C",x"10",x"14",x"69",x"80",x"85",x"D0",x"D0", -- 0x1D88 - x"03",x"4C",x"B6",x"DB",x"A5",x"DE",x"85",x"D5", -- 0x1D90 - x"60",x"A5",x"D5",x"49",x"FF",x"30",x"05",x"68", -- 0x1D98 - x"68",x"4C",x"B2",x"DB",x"4C",x"39",x"DC",x"20", -- 0x1DA0 - x"E5",x"DE",x"AA",x"F0",x"10",x"18",x"69",x"02", -- 0x1DA8 - x"B0",x"F2",x"A2",x"00",x"86",x"DE",x"20",x"32", -- 0x1DB0 - x"DB",x"E6",x"D0",x"F0",x"E7",x"60",x"84",x"20", -- 0x1DB8 - x"00",x"00",x"00",x"20",x"E5",x"DE",x"A9",x"BE", -- 0x1DC0 - x"A0",x"DD",x"A2",x"00",x"86",x"DE",x"20",x"7B", -- 0x1DC8 - x"DE",x"4C",x"E7",x"DD",x"20",x"AF",x"DC",x"20", -- 0x1DD0 - x"E5",x"DE",x"A9",x"77",x"A0",x"DC",x"20",x"7B", -- 0x1DD8 - x"DE",x"4C",x"E7",x"DD",x"20",x"51",x"DD",x"F0", -- 0x1DE0 - x"76",x"20",x"F4",x"DE",x"A9",x"00",x"38",x"E5", -- 0x1DE8 - x"D0",x"85",x"D0",x"20",x"7C",x"DD",x"E6",x"D0", -- 0x1DF0 - x"F0",x"AA",x"A2",x"FC",x"A9",x"01",x"A4",x"D9", -- 0x1DF8 - x"C4",x"D1",x"D0",x"10",x"A4",x"DA",x"C4",x"D2", -- 0x1E00 - x"D0",x"0A",x"A4",x"DB",x"C4",x"D3",x"D0",x"04", -- 0x1E08 - x"A4",x"DC",x"C4",x"D4",x"08",x"2A",x"90",x"09", -- 0x1E10 - x"E8",x"95",x"98",x"F0",x"32",x"10",x"34",x"A9", -- 0x1E18 - x"01",x"28",x"B0",x"0E",x"06",x"DC",x"26",x"DB", -- 0x1E20 - x"26",x"DA",x"26",x"D9",x"B0",x"E6",x"30",x"CE", -- 0x1E28 - x"10",x"E2",x"A8",x"A5",x"DC",x"E5",x"D4",x"85", -- 0x1E30 - x"DC",x"A5",x"DB",x"E5",x"D3",x"85",x"DB",x"A5", -- 0x1E38 - x"DA",x"E5",x"D2",x"85",x"DA",x"A5",x"D9",x"E5", -- 0x1E40 - x"D1",x"85",x"D9",x"98",x"4C",x"24",x"DE",x"A9", -- 0x1E48 - x"40",x"D0",x"CE",x"0A",x"0A",x"0A",x"0A",x"0A", -- 0x1E50 - x"0A",x"85",x"DF",x"28",x"4C",x"64",x"DE",x"A2", -- 0x1E58 - x"85",x"4C",x"7E",x"C4",x"A5",x"95",x"85",x"D1", -- 0x1E60 - x"A5",x"96",x"85",x"D2",x"A5",x"97",x"85",x"D3", -- 0x1E68 - x"A5",x"98",x"85",x"D4",x"4C",x"92",x"DB",x"A9", -- 0x1E70 - x"7C",x"A0",x"DC",x"85",x"91",x"84",x"92",x"A0", -- 0x1E78 - x"04",x"B1",x"91",x"85",x"D4",x"88",x"B1",x"91", -- 0x1E80 - x"85",x"D3",x"88",x"B1",x"91",x"85",x"D2",x"88", -- 0x1E88 - x"B1",x"91",x"85",x"D5",x"09",x"80",x"85",x"D1", -- 0x1E90 - x"88",x"B1",x"91",x"85",x"D0",x"84",x"DF",x"60", -- 0x1E98 - x"A2",x"CB",x"2C",x"A2",x"C6",x"A0",x"00",x"F0", -- 0x1EA0 - x"04",x"A6",x"B8",x"A4",x"B9",x"20",x"F4",x"DE", -- 0x1EA8 - x"86",x"91",x"84",x"92",x"A0",x"04",x"A5",x"D4", -- 0x1EB0 - x"91",x"91",x"88",x"A5",x"D3",x"91",x"91",x"88", -- 0x1EB8 - x"A5",x"D2",x"91",x"91",x"88",x"A5",x"D5",x"09", -- 0x1EC0 - x"7F",x"25",x"D1",x"91",x"91",x"88",x"A5",x"D0", -- 0x1EC8 - x"91",x"91",x"84",x"DF",x"60",x"A5",x"DD",x"85", -- 0x1ED0 - x"D5",x"A2",x"05",x"B5",x"D7",x"95",x"CF",x"CA", -- 0x1ED8 - x"D0",x"F9",x"86",x"DF",x"60",x"20",x"F4",x"DE", -- 0x1EE0 - x"A2",x"06",x"B5",x"CF",x"95",x"D7",x"CA",x"D0", -- 0x1EE8 - x"F9",x"86",x"DF",x"60",x"A5",x"D0",x"F0",x"FB", -- 0x1EF0 - x"06",x"DF",x"90",x"F7",x"20",x"2A",x"DC",x"D0", -- 0x1EF8 - x"F2",x"4C",x"F3",x"DB",x"20",x"A9",x"D2",x"46", -- 0x1F00 - x"D4",x"B0",x"04",x"A9",x"00",x"F0",x"15",x"A9", -- 0x1F08 - x"FF",x"30",x"11",x"A5",x"D0",x"F0",x"09",x"A5", -- 0x1F10 - x"D5",x"2A",x"A9",x"FF",x"B0",x"02",x"A9",x"01", -- 0x1F18 - x"60",x"20",x"13",x"DF",x"85",x"D1",x"A9",x"00", -- 0x1F20 - x"85",x"D2",x"A2",x"88",x"A5",x"D1",x"49",x"FF", -- 0x1F28 - x"2A",x"A9",x"00",x"85",x"D4",x"85",x"D3",x"86", -- 0x1F30 - x"D0",x"85",x"DF",x"85",x"D5",x"4C",x"8D",x"DB", -- 0x1F38 - x"85",x"D1",x"84",x"D2",x"A2",x"90",x"38",x"B0", -- 0x1F40 - x"E8",x"46",x"D5",x"60",x"85",x"93",x"84",x"94", -- 0x1F48 - x"A0",x"00",x"B1",x"93",x"C8",x"AA",x"F0",x"BB", -- 0x1F50 - x"B1",x"93",x"45",x"D5",x"30",x"B9",x"E4",x"D0", -- 0x1F58 - x"D0",x"21",x"B1",x"93",x"09",x"80",x"C5",x"D1", -- 0x1F60 - x"D0",x"19",x"C8",x"B1",x"93",x"C5",x"D2",x"D0", -- 0x1F68 - x"12",x"C8",x"B1",x"93",x"C5",x"D3",x"D0",x"0B", -- 0x1F70 - x"C8",x"A9",x"7F",x"C5",x"DF",x"B1",x"93",x"E5", -- 0x1F78 - x"D4",x"F0",x"28",x"A5",x"D5",x"90",x"02",x"49", -- 0x1F80 - x"FF",x"4C",x"19",x"DF",x"A5",x"D0",x"F0",x"4A", -- 0x1F88 - x"38",x"E9",x"A0",x"24",x"D5",x"10",x"09",x"AA", -- 0x1F90 - x"A9",x"FF",x"85",x"D7",x"20",x"08",x"DC",x"8A", -- 0x1F98 - x"A2",x"D0",x"C9",x"F9",x"10",x"06",x"20",x"54", -- 0x1FA0 - x"DC",x"84",x"D7",x"60",x"A8",x"A5",x"D5",x"29", -- 0x1FA8 - x"80",x"46",x"D1",x"05",x"D1",x"85",x"D1",x"20", -- 0x1FB0 - x"6B",x"DC",x"84",x"D7",x"60",x"A5",x"D0",x"C9", -- 0x1FB8 - x"A0",x"B0",x"20",x"20",x"8C",x"DF",x"84",x"DF", -- 0x1FC0 - x"A5",x"D5",x"84",x"D5",x"49",x"80",x"2A",x"A9", -- 0x1FC8 - x"A0",x"85",x"D0",x"A5",x"D4",x"85",x"24",x"4C", -- 0x1FD0 - x"8D",x"DB",x"85",x"D1",x"85",x"D2",x"85",x"D3", -- 0x1FD8 - x"85",x"D4",x"A8",x"60",x"4C",x"81",x"E9",x"A0", -- 0x1FE0 - x"00",x"A2",x"0A",x"94",x"CC",x"CA",x"10",x"FB", -- 0x1FE8 - x"90",x"13",x"C9",x"23",x"F0",x"EE",x"C9",x"2D", -- 0x1FF0 - x"D0",x"04",x"86",x"D6",x"F0",x"04",x"C9",x"2B", -- 0x1FF8 - x"D0",x"05",x"20",x"E2",x"00",x"90",x"5B",x"C9", -- 0x2000 - x"2E",x"F0",x"2E",x"C9",x"45",x"D0",x"30",x"20", -- 0x2008 - x"E2",x"00",x"90",x"17",x"C9",x"CD",x"F0",x"0E", -- 0x2010 - x"C9",x"2D",x"F0",x"0A",x"C9",x"CC",x"F0",x"08", -- 0x2018 - x"C9",x"2B",x"F0",x"04",x"D0",x"07",x"66",x"CF", -- 0x2020 - x"20",x"E2",x"00",x"90",x"5C",x"24",x"CF",x"10", -- 0x2028 - x"0E",x"A9",x"00",x"38",x"E5",x"CD",x"4C",x"41", -- 0x2030 - x"E0",x"66",x"CE",x"24",x"CE",x"50",x"C3",x"A5", -- 0x2038 - x"CD",x"38",x"E5",x"CC",x"85",x"CD",x"F0",x"12", -- 0x2040 - x"10",x"09",x"20",x"C3",x"DD",x"E6",x"CD",x"D0", -- 0x2048 - x"F9",x"F0",x"07",x"20",x"A7",x"DD",x"C6",x"CD", -- 0x2050 - x"D0",x"F9",x"A5",x"D6",x"30",x"01",x"60",x"4C", -- 0x2058 - x"71",x"E2",x"48",x"24",x"CE",x"10",x"02",x"E6", -- 0x2060 - x"CC",x"20",x"A7",x"DD",x"68",x"38",x"E9",x"30", -- 0x2068 - x"20",x"76",x"E0",x"4C",x"02",x"E0",x"48",x"20", -- 0x2070 - x"E5",x"DE",x"68",x"20",x"24",x"DF",x"A5",x"DD", -- 0x2078 - x"45",x"D5",x"85",x"DE",x"A6",x"D0",x"4C",x"25", -- 0x2080 - x"DB",x"A5",x"CD",x"C9",x"0A",x"90",x"09",x"A9", -- 0x2088 - x"64",x"24",x"CF",x"30",x"11",x"4C",x"39",x"DC", -- 0x2090 - x"0A",x"0A",x"18",x"65",x"CD",x"0A",x"18",x"A0", -- 0x2098 - x"00",x"71",x"E9",x"38",x"E9",x"30",x"85",x"CD", -- 0x20A0 - x"4C",x"28",x"E0",x"9B",x"3E",x"BC",x"1F",x"FD", -- 0x20A8 - x"9E",x"6E",x"6B",x"27",x"FD",x"9E",x"6E",x"6B", -- 0x20B0 - x"28",x"00",x"A9",x"AD",x"A0",x"C3",x"20",x"D2", -- 0x20B8 - x"E0",x"A5",x"A9",x"A6",x"A8",x"85",x"D1",x"86", -- 0x20C0 - x"D2",x"A2",x"90",x"38",x"20",x"31",x"DF",x"20", -- 0x20C8 - x"D5",x"E0",x"4C",x"B0",x"CC",x"A0",x"01",x"A9", -- 0x20D0 - x"20",x"24",x"D5",x"10",x"02",x"A9",x"2D",x"99", -- 0x20D8 - x"FF",x"00",x"85",x"D5",x"84",x"E0",x"C8",x"A9", -- 0x20E0 - x"30",x"A6",x"D0",x"D0",x"03",x"4C",x"F8",x"E1", -- 0x20E8 - x"A9",x"00",x"E0",x"80",x"F0",x"02",x"B0",x"09", -- 0x20F0 - x"A9",x"B5",x"A0",x"E0",x"20",x"ED",x"DC",x"A9", -- 0x20F8 - x"F7",x"85",x"CC",x"A9",x"B0",x"A0",x"E0",x"20", -- 0x2100 - x"4C",x"DF",x"F0",x"1E",x"10",x"12",x"A9",x"AB", -- 0x2108 - x"A0",x"E0",x"20",x"4C",x"DF",x"F0",x"02",x"10", -- 0x2110 - x"0E",x"20",x"A7",x"DD",x"C6",x"CC",x"D0",x"EE", -- 0x2118 - x"20",x"C3",x"DD",x"E6",x"CC",x"D0",x"DC",x"20", -- 0x2120 - x"04",x"DB",x"20",x"8C",x"DF",x"A2",x"01",x"A5", -- 0x2128 - x"CC",x"18",x"69",x"0A",x"30",x"09",x"C9",x"0B", -- 0x2130 - x"B0",x"06",x"69",x"FF",x"AA",x"A9",x"02",x"38", -- 0x2138 - x"E9",x"02",x"85",x"CD",x"86",x"CC",x"8A",x"F0", -- 0x2140 - x"02",x"10",x"13",x"A4",x"E0",x"A9",x"2E",x"C8", -- 0x2148 - x"99",x"FF",x"00",x"8A",x"F0",x"06",x"A9",x"30", -- 0x2150 - x"C8",x"99",x"FF",x"00",x"84",x"E0",x"A0",x"00", -- 0x2158 - x"A2",x"80",x"A5",x"D4",x"18",x"79",x"0D",x"E2", -- 0x2160 - x"85",x"D4",x"A5",x"D3",x"79",x"0C",x"E2",x"85", -- 0x2168 - x"D3",x"A5",x"D2",x"79",x"0B",x"E2",x"85",x"D2", -- 0x2170 - x"A5",x"D1",x"79",x"0A",x"E2",x"85",x"D1",x"E8", -- 0x2178 - x"B0",x"04",x"10",x"DE",x"30",x"02",x"30",x"DA", -- 0x2180 - x"8A",x"90",x"04",x"49",x"FF",x"69",x"0A",x"69", -- 0x2188 - x"2F",x"C8",x"C8",x"C8",x"C8",x"84",x"B6",x"A4", -- 0x2190 - x"E0",x"C8",x"AA",x"29",x"7F",x"99",x"FF",x"00", -- 0x2198 - x"C6",x"CC",x"D0",x"06",x"A9",x"2E",x"C8",x"99", -- 0x21A0 - x"FF",x"00",x"84",x"E0",x"A4",x"B6",x"8A",x"49", -- 0x21A8 - x"FF",x"29",x"80",x"AA",x"C0",x"24",x"D0",x"AA", -- 0x21B0 - x"A4",x"E0",x"B9",x"FF",x"00",x"88",x"C9",x"30", -- 0x21B8 - x"F0",x"F8",x"C9",x"2E",x"F0",x"01",x"C8",x"A9", -- 0x21C0 - x"2B",x"A6",x"CD",x"F0",x"2E",x"10",x"08",x"A9", -- 0x21C8 - x"00",x"38",x"E5",x"CD",x"AA",x"A9",x"2D",x"99", -- 0x21D0 - x"01",x"01",x"A9",x"45",x"99",x"00",x"01",x"8A", -- 0x21D8 - x"A2",x"2F",x"38",x"E8",x"E9",x"0A",x"B0",x"FB", -- 0x21E0 - x"69",x"3A",x"99",x"03",x"01",x"8A",x"99",x"02", -- 0x21E8 - x"01",x"A9",x"00",x"99",x"04",x"01",x"F0",x"08", -- 0x21F0 - x"99",x"FF",x"00",x"A9",x"00",x"99",x"00",x"01", -- 0x21F8 - x"A9",x"00",x"A0",x"01",x"60",x"80",x"00",x"00", -- 0x2200 - x"00",x"00",x"FA",x"0A",x"1F",x"00",x"00",x"98", -- 0x2208 - x"96",x"80",x"FF",x"F0",x"BD",x"C0",x"00",x"01", -- 0x2210 - x"86",x"A0",x"FF",x"FF",x"D8",x"F0",x"00",x"00", -- 0x2218 - x"03",x"E8",x"FF",x"FF",x"FF",x"9C",x"00",x"00", -- 0x2220 - x"00",x"0A",x"FF",x"FF",x"FF",x"FF",x"20",x"E5", -- 0x2228 - x"DE",x"A9",x"05",x"A0",x"E2",x"20",x"7B",x"DE", -- 0x2230 - x"F0",x"70",x"A5",x"D8",x"D0",x"03",x"4C",x"B4", -- 0x2238 - x"DB",x"A2",x"BD",x"A0",x"00",x"20",x"AD",x"DE", -- 0x2240 - x"A5",x"DD",x"10",x"0F",x"20",x"BD",x"DF",x"A9", -- 0x2248 - x"BD",x"A0",x"00",x"20",x"4C",x"DF",x"D0",x"03", -- 0x2250 - x"98",x"A4",x"24",x"20",x"D7",x"DE",x"98",x"48", -- 0x2258 - x"20",x"AF",x"DC",x"A9",x"BD",x"A0",x"00",x"20", -- 0x2260 - x"ED",x"DC",x"20",x"AA",x"E2",x"68",x"4A",x"90", -- 0x2268 - x"0A",x"A5",x"D0",x"F0",x"06",x"A5",x"D5",x"49", -- 0x2270 - x"FF",x"85",x"D5",x"60",x"81",x"38",x"AA",x"3B", -- 0x2278 - x"29",x"07",x"71",x"34",x"58",x"3E",x"56",x"74", -- 0x2280 - x"16",x"7E",x"B3",x"1B",x"77",x"2F",x"EE",x"E3", -- 0x2288 - x"85",x"7A",x"1D",x"84",x"1C",x"2A",x"7C",x"63", -- 0x2290 - x"59",x"58",x"0A",x"7E",x"75",x"FD",x"E7",x"C6", -- 0x2298 - x"80",x"31",x"72",x"18",x"10",x"81",x"00",x"00", -- 0x22A0 - x"00",x"00",x"A9",x"7C",x"A0",x"E2",x"20",x"ED", -- 0x22A8 - x"DC",x"A5",x"DF",x"69",x"50",x"90",x"03",x"20", -- 0x22B0 - x"FC",x"DE",x"85",x"C5",x"20",x"E8",x"DE",x"A5", -- 0x22B8 - x"D0",x"C9",x"88",x"90",x"03",x"20",x"99",x"DD", -- 0x22C0 - x"20",x"BD",x"DF",x"A5",x"24",x"18",x"69",x"81", -- 0x22C8 - x"F0",x"F3",x"38",x"E9",x"01",x"48",x"A2",x"05", -- 0x22D0 - x"B5",x"D8",x"B4",x"D0",x"95",x"D0",x"94",x"D8", -- 0x22D8 - x"CA",x"10",x"F5",x"A5",x"C5",x"85",x"DF",x"20", -- 0x22E0 - x"0E",x"DB",x"20",x"71",x"E2",x"A9",x"81",x"A0", -- 0x22E8 - x"E2",x"20",x"13",x"E3",x"A9",x"00",x"85",x"DE", -- 0x22F0 - x"68",x"20",x"7E",x"DD",x"60",x"85",x"E0",x"84", -- 0x22F8 - x"E1",x"20",x"A3",x"DE",x"A9",x"C6",x"20",x"ED", -- 0x2300 - x"DC",x"20",x"17",x"E3",x"A9",x"C6",x"A0",x"00", -- 0x2308 - x"4C",x"ED",x"DC",x"85",x"E0",x"84",x"E1",x"20", -- 0x2310 - x"A0",x"DE",x"B1",x"E0",x"85",x"D6",x"A4",x"E0", -- 0x2318 - x"C8",x"98",x"D0",x"02",x"E6",x"E1",x"85",x"E0", -- 0x2320 - x"A4",x"E1",x"20",x"ED",x"DC",x"A5",x"E0",x"A4", -- 0x2328 - x"E1",x"18",x"69",x"05",x"90",x"01",x"C8",x"85", -- 0x2330 - x"E0",x"84",x"E1",x"20",x"22",x"DB",x"A9",x"CB", -- 0x2338 - x"A0",x"00",x"C6",x"D6",x"D0",x"E4",x"60",x"98", -- 0x2340 - x"35",x"44",x"7A",x"68",x"28",x"B1",x"46",x"20", -- 0x2348 - x"13",x"DF",x"AA",x"30",x"18",x"A9",x"FA",x"A0", -- 0x2350 - x"00",x"20",x"7B",x"DE",x"8A",x"F0",x"E7",x"A9", -- 0x2358 - x"47",x"A0",x"E3",x"20",x"ED",x"DC",x"A9",x"4B", -- 0x2360 - x"A0",x"E3",x"20",x"22",x"DB",x"A6",x"D4",x"A5", -- 0x2368 - x"D1",x"85",x"D4",x"86",x"D1",x"A9",x"00",x"85", -- 0x2370 - x"D5",x"A5",x"D0",x"85",x"DF",x"A9",x"80",x"85", -- 0x2378 - x"D0",x"20",x"92",x"DB",x"A2",x"FA",x"A0",x"00", -- 0x2380 - x"4C",x"AD",x"DE",x"A9",x"07",x"A0",x"E4",x"20", -- 0x2388 - x"22",x"DB",x"20",x"E5",x"DE",x"A9",x"0C",x"A0", -- 0x2390 - x"E4",x"A6",x"DD",x"20",x"CC",x"DD",x"20",x"E5", -- 0x2398 - x"DE",x"20",x"BD",x"DF",x"A9",x"00",x"85",x"DE", -- 0x23A0 - x"20",x"0E",x"DB",x"A9",x"11",x"A0",x"E4",x"20", -- 0x23A8 - x"0B",x"DB",x"A5",x"D5",x"48",x"10",x"0D",x"20", -- 0x23B0 - x"04",x"DB",x"A5",x"D5",x"30",x"09",x"A5",x"2D", -- 0x23B8 - x"49",x"FF",x"85",x"2D",x"20",x"71",x"E2",x"A9", -- 0x23C0 - x"11",x"A0",x"E4",x"20",x"22",x"DB",x"68",x"10", -- 0x23C8 - x"03",x"20",x"71",x"E2",x"A9",x"16",x"A0",x"E4", -- 0x23D0 - x"4C",x"FD",x"E2",x"20",x"A3",x"DE",x"A9",x"00", -- 0x23D8 - x"85",x"2D",x"20",x"92",x"E3",x"A2",x"BD",x"A0", -- 0x23E0 - x"00",x"20",x"88",x"E3",x"A9",x"C6",x"A0",x"00", -- 0x23E8 - x"20",x"7B",x"DE",x"A9",x"00",x"85",x"D5",x"A5", -- 0x23F0 - x"2D",x"20",x"03",x"E4",x"A9",x"BD",x"A0",x"00", -- 0x23F8 - x"4C",x"E4",x"DD",x"48",x"4C",x"C4",x"E3",x"81", -- 0x2400 - x"49",x"0F",x"DA",x"A2",x"83",x"49",x"0F",x"DA", -- 0x2408 - x"A2",x"7F",x"00",x"00",x"00",x"00",x"05",x"84", -- 0x2410 - x"E6",x"1A",x"2D",x"1B",x"86",x"28",x"07",x"FB", -- 0x2418 - x"F8",x"87",x"99",x"68",x"89",x"01",x"87",x"23", -- 0x2420 - x"35",x"DF",x"E1",x"86",x"A5",x"5D",x"E7",x"28", -- 0x2428 - x"83",x"49",x"0F",x"DA",x"A2",x"A1",x"54",x"46", -- 0x2430 - x"8F",x"13",x"8F",x"52",x"43",x"89",x"CD",x"A5", -- 0x2438 - x"D5",x"48",x"10",x"03",x"20",x"71",x"E2",x"A5", -- 0x2440 - x"D0",x"48",x"C9",x"81",x"90",x"07",x"A9",x"81", -- 0x2448 - x"A0",x"DC",x"20",x"E4",x"DD",x"A9",x"6F",x"A0", -- 0x2450 - x"E4",x"20",x"FD",x"E2",x"68",x"C9",x"81",x"90", -- 0x2458 - x"07",x"A9",x"07",x"A0",x"E4",x"20",x"0B",x"DB", -- 0x2460 - x"68",x"10",x"03",x"4C",x"71",x"E2",x"60",x"0B", -- 0x2468 - x"76",x"B3",x"83",x"BD",x"D3",x"79",x"1E",x"F4", -- 0x2470 - x"A6",x"F5",x"7B",x"83",x"FC",x"B0",x"10",x"7C", -- 0x2478 - x"0C",x"1F",x"67",x"CA",x"7C",x"DE",x"53",x"CB", -- 0x2480 - x"C1",x"7D",x"14",x"64",x"70",x"4C",x"7D",x"B7", -- 0x2488 - x"EA",x"51",x"7A",x"7D",x"63",x"30",x"88",x"7E", -- 0x2490 - x"7E",x"92",x"44",x"99",x"3A",x"7E",x"4C",x"CC", -- 0x2498 - x"91",x"C7",x"7F",x"AA",x"AA",x"AA",x"13",x"81", -- 0x24A0 - x"00",x"00",x"00",x"00",x"20",x"35",x"E7",x"20", -- 0x24A8 - x"C9",x"E6",x"C9",x"24",x"D0",x"F9",x"8E",x"B1", -- 0x24B0 - x"02",x"A2",x"09",x"20",x"C9",x"E6",x"9D",x"A7", -- 0x24B8 - x"02",x"CA",x"D0",x"F7",x"20",x"C9",x"E6",x"F0", -- 0x24C0 - x"0A",x"E0",x"10",x"B0",x"F7",x"9D",x"93",x"02", -- 0x24C8 - x"E8",x"D0",x"F1",x"9D",x"93",x"02",x"20",x"94", -- 0x24D0 - x"E5",x"20",x"90",x"E7",x"8A",x"D0",x"CD",x"60", -- 0x24D8 - x"AD",x"A9",x"02",x"AC",x"AA",x"02",x"85",x"33", -- 0x24E0 - x"84",x"34",x"A0",x"00",x"20",x"C9",x"E6",x"AE", -- 0x24E8 - x"5B",x"02",x"D0",x"05",x"91",x"33",x"4C",x"05", -- 0x24F0 - x"E5",x"D1",x"33",x"F0",x"08",x"EE",x"5C",x"02", -- 0x24F8 - x"D0",x"03",x"EE",x"5D",x"02",x"20",x"6C",x"E5", -- 0x2500 - x"90",x"E2",x"60",x"10",x"07",x"53",x"65",x"61", -- 0x2508 - x"72",x"63",x"68",x"69",x"6E",x"67",x"20",x"2E", -- 0x2510 - x"2E",x"00",x"10",x"07",x"4C",x"6F",x"61",x"64", -- 0x2518 - x"69",x"6E",x"67",x"20",x"2E",x"2E",x"00",x"0A", -- 0x2520 - x"0D",x"45",x"72",x"72",x"6F",x"72",x"73",x"20", -- 0x2528 - x"66",x"6F",x"75",x"6E",x"64",x"0D",x"0A",x"00", -- 0x2530 - x"10",x"07",x"46",x"6F",x"75",x"6E",x"64",x"20", -- 0x2538 - x"2E",x"2E",x"00",x"10",x"07",x"56",x"65",x"72", -- 0x2540 - x"69",x"66",x"79",x"69",x"6E",x"67",x"20",x"2E", -- 0x2548 - x"2E",x"00",x"20",x"56",x"65",x"72",x"69",x"66", -- 0x2550 - x"79",x"20",x"65",x"72",x"72",x"6F",x"72",x"73", -- 0x2558 - x"20",x"64",x"65",x"74",x"65",x"63",x"74",x"65", -- 0x2560 - x"64",x"0D",x"0A",x"00",x"A5",x"33",x"CD",x"AB", -- 0x2568 - x"02",x"A5",x"34",x"ED",x"AC",x"02",x"E6",x"33", -- 0x2570 - x"D0",x"02",x"E6",x"34",x"60",x"A9",x"0B",x"A0", -- 0x2578 - x"E5",x"20",x"EA",x"E5",x"60",x"A9",x"45",x"A0", -- 0x2580 - x"E6",x"20",x"EA",x"E5",x"A9",x"7F",x"A0",x"02", -- 0x2588 - x"20",x"B6",x"E5",x"60",x"A9",x"38",x"A0",x"E5", -- 0x2590 - x"4C",x"AB",x"E5",x"AD",x"5B",x"02",x"D0",x"07", -- 0x2598 - x"A9",x"1A",x"A0",x"E5",x"4C",x"AB",x"E5",x"A9", -- 0x25A0 - x"43",x"A0",x"E5",x"20",x"EA",x"E5",x"A9",x"93", -- 0x25A8 - x"A0",x"02",x"20",x"B6",x"E5",x"60",x"20",x"65", -- 0x25B0 - x"F8",x"E8",x"A0",x"00",x"8C",x"5F",x"02",x"AD", -- 0x25B8 - x"AE",x"02",x"F0",x"13",x"C8",x"2C",x"AE",x"02", -- 0x25C0 - x"30",x"0D",x"C8",x"2C",x"AF",x"02",x"30",x"07", -- 0x25C8 - x"C8",x"2C",x"B0",x"02",x"30",x"01",x"C8",x"B9", -- 0x25D0 - x"E5",x"E5",x"8D",x"5E",x"02",x"A9",x"5E",x"A0", -- 0x25D8 - x"02",x"20",x"65",x"F8",x"60",x"42",x"43",x"53", -- 0x25E0 - x"49",x"52",x"20",x"F5",x"E5",x"A2",x"00",x"20", -- 0x25E8 - x"65",x"F8",x"E8",x"E8",x"60",x"48",x"AD",x"1F", -- 0x25F0 - x"02",x"D0",x"0A",x"A2",x"22",x"A9",x"10",x"9D", -- 0x25F8 - x"80",x"BB",x"CA",x"10",x"FA",x"68",x"60",x"20", -- 0x2600 - x"5A",x"E7",x"A9",x"24",x"20",x"5E",x"E6",x"A2", -- 0x2608 - x"09",x"BD",x"A7",x"02",x"20",x"5E",x"E6",x"CA", -- 0x2610 - x"D0",x"F7",x"BD",x"7F",x"02",x"F0",x"06",x"20", -- 0x2618 - x"5E",x"E6",x"E8",x"D0",x"F5",x"20",x"5E",x"E6", -- 0x2620 - x"A2",x"00",x"CA",x"D0",x"FD",x"60",x"AD",x"A9", -- 0x2628 - x"02",x"AC",x"AA",x"02",x"85",x"33",x"84",x"34", -- 0x2630 - x"A0",x"00",x"B1",x"33",x"20",x"5E",x"E6",x"20", -- 0x2638 - x"6C",x"E5",x"90",x"F6",x"60",x"10",x"07",x"53", -- 0x2640 - x"61",x"76",x"69",x"6E",x"67",x"20",x"2E",x"2E", -- 0x2648 - x"00",x"AD",x"B1",x"02",x"F0",x"07",x"A9",x"27", -- 0x2650 - x"A0",x"E5",x"20",x"B0",x"CC",x"60",x"85",x"2F", -- 0x2658 - x"8A",x"48",x"98",x"48",x"20",x"C0",x"E6",x"18", -- 0x2660 - x"A0",x"09",x"A9",x"00",x"F0",x"06",x"46",x"2F", -- 0x2668 - x"08",x"69",x"00",x"28",x"20",x"8B",x"E6",x"88", -- 0x2670 - x"D0",x"F4",x"49",x"01",x"4A",x"A0",x"04",x"20", -- 0x2678 - x"8B",x"E6",x"38",x"88",x"D0",x"F9",x"68",x"A8", -- 0x2680 - x"68",x"AA",x"60",x"48",x"08",x"AD",x"4D",x"02", -- 0x2688 - x"D0",x"0A",x"38",x"20",x"B2",x"E6",x"28",x"20", -- 0x2690 - x"B2",x"E6",x"68",x"60",x"20",x"B2",x"E6",x"A2", -- 0x2698 - x"0F",x"28",x"B0",x"02",x"A2",x"07",x"20",x"AB", -- 0x26A0 - x"E6",x"68",x"60",x"20",x"C0",x"E6",x"CA",x"D0", -- 0x26A8 - x"FA",x"60",x"A9",x"D0",x"A2",x"00",x"B0",x"02", -- 0x26B0 - x"0A",x"E8",x"8D",x"06",x"03",x"8E",x"07",x"03", -- 0x26B8 - x"AD",x"04",x"03",x"2C",x"0D",x"03",x"50",x"FB", -- 0x26C0 - x"60",x"98",x"48",x"8A",x"48",x"20",x"1C",x"E7", -- 0x26C8 - x"20",x"1C",x"E7",x"B0",x"FB",x"20",x"FF",x"E6", -- 0x26D0 - x"B0",x"16",x"A9",x"00",x"A0",x"08",x"20",x"FC", -- 0x26D8 - x"E6",x"08",x"66",x"2F",x"28",x"69",x"00",x"88", -- 0x26E0 - x"D0",x"F4",x"20",x"FC",x"E6",x"E9",x"00",x"4A", -- 0x26E8 - x"90",x"03",x"2E",x"B1",x"02",x"68",x"AA",x"68", -- 0x26F0 - x"A8",x"A5",x"2F",x"60",x"20",x"1C",x"E7",x"48", -- 0x26F8 - x"AD",x"4D",x"02",x"F0",x"15",x"20",x"1C",x"E7", -- 0x2700 - x"A2",x"02",x"90",x"02",x"A2",x"06",x"A9",x"00", -- 0x2708 - x"20",x"1C",x"E7",x"69",x"00",x"CA",x"D0",x"F8", -- 0x2710 - x"C9",x"04",x"68",x"60",x"48",x"AD",x"00",x"03", -- 0x2718 - x"AD",x"0D",x"03",x"29",x"10",x"F0",x"F9",x"AD", -- 0x2720 - x"09",x"03",x"48",x"A9",x"FF",x"8D",x"09",x"03", -- 0x2728 - x"68",x"C9",x"FE",x"68",x"60",x"20",x"FC",x"E6", -- 0x2730 - x"66",x"2F",x"A9",x"16",x"C5",x"2F",x"D0",x"F5", -- 0x2738 - x"AD",x"4D",x"02",x"F0",x"08",x"20",x"1C",x"E7", -- 0x2740 - x"20",x"1C",x"E7",x"B0",x"FB",x"A2",x"03",x"20", -- 0x2748 - x"C9",x"E6",x"C9",x"16",x"D0",x"DF",x"CA",x"D0", -- 0x2750 - x"F6",x"60",x"A2",x"02",x"A0",x"03",x"A9",x"16", -- 0x2758 - x"20",x"5E",x"E6",x"88",x"D0",x"F8",x"CA",x"D0", -- 0x2760 - x"F5",x"60",x"20",x"1A",x"EE",x"A0",x"06",x"78", -- 0x2768 - x"BE",x"82",x"E7",x"B9",x"89",x"E7",x"9D",x"00", -- 0x2770 - x"03",x"88",x"10",x"F4",x"A9",x"40",x"8D",x"00", -- 0x2778 - x"03",x"60",x"05",x"04",x"0B",x"02",x"0C",x"08", -- 0x2780 - x"0E",x"00",x"D0",x"C0",x"FF",x"10",x"F4",x"7F", -- 0x2788 - x"A0",x"00",x"A2",x"00",x"AD",x"7F",x"02",x"F0", -- 0x2790 - x"15",x"B9",x"7F",x"02",x"D9",x"93",x"02",x"F0", -- 0x2798 - x"01",x"E8",x"99",x"93",x"02",x"C8",x"C0",x"11", -- 0x27A0 - x"B0",x"04",x"48",x"68",x"D0",x"EB",x"60",x"4C", -- 0x27A8 - x"70",x"D0",x"A9",x"00",x"8D",x"4D",x"02",x"8D", -- 0x27B0 - x"AD",x"02",x"8D",x"AE",x"02",x"8D",x"5B",x"02", -- 0x27B8 - x"8D",x"5A",x"02",x"8D",x"5C",x"02",x"8D",x"5D", -- 0x27C0 - x"02",x"8D",x"B1",x"02",x"20",x"17",x"CF",x"24", -- 0x27C8 - x"28",x"10",x"DC",x"20",x"D0",x"D7",x"AA",x"A0", -- 0x27D0 - x"00",x"E8",x"CA",x"F0",x"0A",x"B1",x"91",x"99", -- 0x27D8 - x"7F",x"02",x"C8",x"C0",x"10",x"D0",x"F3",x"A9", -- 0x27E0 - x"00",x"99",x"7F",x"02",x"20",x"E8",x"00",x"F0", -- 0x27E8 - x"61",x"C9",x"2C",x"D0",x"BA",x"20",x"E2",x"00", -- 0x27F0 - x"F0",x"58",x"C9",x"2C",x"F0",x"F7",x"C9",x"C7", -- 0x27F8 - x"D0",x"05",x"8D",x"AD",x"02",x"B0",x"EE",x"C9", -- 0x2800 - x"53",x"D0",x"05",x"8D",x"4D",x"02",x"B0",x"E5", -- 0x2808 - x"C9",x"56",x"D0",x"05",x"8D",x"5B",x"02",x"B0", -- 0x2810 - x"DC",x"C9",x"4A",x"D0",x"05",x"8D",x"5A",x"02", -- 0x2818 - x"B0",x"D3",x"C9",x"41",x"F0",x"04",x"C9",x"45", -- 0x2820 - x"D0",x"47",x"85",x"0E",x"20",x"E2",x"00",x"A2", -- 0x2828 - x"80",x"8E",x"AE",x"02",x"20",x"53",x"E8",x"A5", -- 0x2830 - x"33",x"A4",x"34",x"A6",x"0E",x"E0",x"41",x"D0", -- 0x2838 - x"08",x"8D",x"A9",x"02",x"8C",x"AA",x"02",x"B0", -- 0x2840 - x"A3",x"8D",x"AB",x"02",x"8C",x"AC",x"02",x"4C", -- 0x2848 - x"EC",x"E7",x"60",x"20",x"03",x"CF",x"20",x"22", -- 0x2850 - x"D9",x"18",x"60",x"08",x"20",x"B2",x"E7",x"AD", -- 0x2858 - x"AD",x"02",x"0D",x"AE",x"02",x"D0",x"0A",x"AD", -- 0x2860 - x"5A",x"02",x"F0",x"08",x"AD",x"5B",x"02",x"F0", -- 0x2868 - x"03",x"4C",x"70",x"D0",x"20",x"6A",x"E7",x"20", -- 0x2870 - x"7D",x"E5",x"20",x"AC",x"E4",x"2C",x"AE",x"02", -- 0x2878 - x"70",x"F8",x"AD",x"5A",x"02",x"F0",x"2C",x"AD", -- 0x2880 - x"AE",x"02",x"D0",x"EE",x"A5",x"9C",x"A4",x"9D", -- 0x2888 - x"38",x"E9",x"02",x"B0",x"01",x"88",x"8D",x"A9", -- 0x2890 - x"02",x"8C",x"AA",x"02",x"38",x"E5",x"9A",x"AA", -- 0x2898 - x"98",x"E5",x"9B",x"A8",x"18",x"8A",x"6D",x"AB", -- 0x28A0 - x"02",x"8D",x"AB",x"02",x"98",x"6D",x"AC",x"02", -- 0x28A8 - x"8D",x"AC",x"02",x"20",x"9B",x"E5",x"20",x"E0", -- 0x28B0 - x"E4",x"20",x"3D",x"E9",x"28",x"AD",x"5B",x"02", -- 0x28B8 - x"F0",x"11",x"AE",x"5C",x"02",x"AD",x"5D",x"02", -- 0x28C0 - x"20",x"C5",x"E0",x"A9",x"52",x"A0",x"E5",x"20", -- 0x28C8 - x"B0",x"CC",x"60",x"20",x"51",x"E6",x"AD",x"AE", -- 0x28D0 - x"02",x"F0",x"0E",x"AD",x"AD",x"02",x"F0",x"08", -- 0x28D8 - x"AD",x"B1",x"02",x"EA",x"EA",x"6C",x"A9",x"02", -- 0x28E0 - x"60",x"AE",x"AB",x"02",x"AD",x"AC",x"02",x"86", -- 0x28E8 - x"9C",x"85",x"9D",x"20",x"5F",x"C5",x"AD",x"AD", -- 0x28F0 - x"02",x"F0",x"08",x"AD",x"B1",x"02",x"EA",x"EA", -- 0x28F8 - x"4C",x"08",x"C7",x"20",x"08",x"C7",x"4C",x"A8", -- 0x2900 - x"C4",x"A5",x"9A",x"A4",x"9B",x"8D",x"A9",x"02", -- 0x2908 - x"8C",x"AA",x"02",x"A5",x"9C",x"A4",x"9D",x"8D", -- 0x2910 - x"AB",x"02",x"8C",x"AC",x"02",x"08",x"20",x"B2", -- 0x2918 - x"E7",x"AD",x"5A",x"02",x"0D",x"5B",x"02",x"F0", -- 0x2920 - x"03",x"4C",x"70",x"D0",x"20",x"6A",x"E7",x"20", -- 0x2928 - x"85",x"E5",x"20",x"07",x"E6",x"20",x"2E",x"E6", -- 0x2930 - x"20",x"3D",x"E9",x"28",x"60",x"20",x"F5",x"E5", -- 0x2938 - x"20",x"AA",x"F9",x"4C",x"E0",x"ED",x"20",x"53", -- 0x2940 - x"E8",x"6C",x"33",x"00",x"A2",x"00",x"86",x"0C", -- 0x2948 - x"86",x"0D",x"F0",x"13",x"A2",x"03",x"0A",x"0A", -- 0x2950 - x"0A",x"0A",x"0A",x"26",x"0C",x"26",x"0D",x"90", -- 0x2958 - x"03",x"4C",x"39",x"DC",x"CA",x"10",x"F3",x"20", -- 0x2960 - x"E2",x"00",x"C9",x"80",x"B0",x"0E",x"09",x"80", -- 0x2968 - x"49",x"B0",x"C9",x"0A",x"90",x"DE",x"69",x"88", -- 0x2970 - x"C9",x"FA",x"B0",x"D8",x"A5",x"0D",x"A4",x"0C", -- 0x2978 - x"60",x"20",x"4C",x"E9",x"4C",x"40",x"DF",x"08", -- 0x2980 - x"20",x"57",x"EA",x"A9",x"40",x"8D",x"AE",x"02", -- 0x2988 - x"A5",x"28",x"8D",x"AF",x"02",x"A5",x"29",x"8D", -- 0x2990 - x"B0",x"02",x"20",x"85",x"E5",x"20",x"07",x"E6", -- 0x2998 - x"20",x"9E",x"EA",x"20",x"2E",x"E6",x"24",x"28", -- 0x29A0 - x"10",x"22",x"A0",x"00",x"B1",x"0C",x"F0",x"17", -- 0x29A8 - x"AA",x"A0",x"02",x"B1",x"0C",x"99",x"D0",x"00", -- 0x29B0 - x"88",x"D0",x"F8",x"E8",x"CA",x"F0",x"08",x"B1", -- 0x29B8 - x"D1",x"20",x"5E",x"E6",x"C8",x"D0",x"F5",x"20", -- 0x29C0 - x"42",x"EA",x"90",x"DE",x"20",x"3D",x"E9",x"28", -- 0x29C8 - x"60",x"20",x"50",x"D6",x"08",x"20",x"57",x"EA", -- 0x29D0 - x"20",x"7D",x"E5",x"20",x"AC",x"E4",x"2C",x"AE", -- 0x29D8 - x"02",x"50",x"F8",x"AD",x"AF",x"02",x"45",x"28", -- 0x29E0 - x"D0",x"F1",x"AD",x"B0",x"02",x"45",x"29",x"D0", -- 0x29E8 - x"EA",x"20",x"9B",x"E5",x"A0",x"02",x"B1",x"CE", -- 0x29F0 - x"CD",x"A9",x"02",x"C8",x"B1",x"CE",x"ED",x"AA", -- 0x29F8 - x"02",x"B0",x"06",x"20",x"3D",x"E9",x"4C",x"7C", -- 0x2A00 - x"C4",x"20",x"9E",x"EA",x"20",x"E0",x"E4",x"24", -- 0x2A08 - x"28",x"10",x"27",x"A0",x"00",x"B1",x"0C",x"F0", -- 0x2A10 - x"1C",x"20",x"AB",x"D5",x"A0",x"00",x"AA",x"E8", -- 0x2A18 - x"CA",x"F0",x"08",x"20",x"C9",x"E6",x"91",x"D1", -- 0x2A20 - x"C8",x"D0",x"F5",x"A0",x"02",x"B9",x"D0",x"00", -- 0x2A28 - x"91",x"0C",x"88",x"D0",x"F8",x"20",x"42",x"EA", -- 0x2A30 - x"90",x"D9",x"20",x"3D",x"E9",x"20",x"51",x"E6", -- 0x2A38 - x"28",x"60",x"18",x"A9",x"03",x"65",x"0C",x"85", -- 0x2A40 - x"0C",x"90",x"02",x"E6",x"0D",x"A8",x"A5",x"0D", -- 0x2A48 - x"CC",x"AB",x"02",x"ED",x"AC",x"02",x"60",x"A9", -- 0x2A50 - x"40",x"85",x"2B",x"20",x"88",x"D1",x"A9",x"00", -- 0x2A58 - x"85",x"2B",x"A0",x"03",x"B1",x"CE",x"8D",x"AA", -- 0x2A60 - x"02",x"88",x"B1",x"CE",x"8D",x"A9",x"02",x"D0", -- 0x2A68 - x"03",x"CE",x"AA",x"02",x"CE",x"A9",x"02",x"20", -- 0x2A70 - x"65",x"D0",x"A5",x"29",x"48",x"A5",x"28",x"48", -- 0x2A78 - x"20",x"B2",x"E7",x"68",x"85",x"28",x"68",x"85", -- 0x2A80 - x"29",x"AD",x"5B",x"02",x"0D",x"AD",x"02",x"0D", -- 0x2A88 - x"AE",x"02",x"0D",x"5A",x"02",x"F0",x"03",x"4C", -- 0x2A90 - x"70",x"D0",x"20",x"6A",x"E7",x"60",x"18",x"A5", -- 0x2A98 - x"CE",x"6D",x"A9",x"02",x"8D",x"AB",x"02",x"A5", -- 0x2AA0 - x"CF",x"6D",x"AA",x"02",x"8D",x"AC",x"02",x"A0", -- 0x2AA8 - x"04",x"B1",x"CE",x"20",x"88",x"D2",x"8D",x"A9", -- 0x2AB0 - x"02",x"8C",x"AA",x"02",x"85",x"0C",x"84",x"0D", -- 0x2AB8 - x"60",x"3F",x"FB",x"17",x"FC",x"CF",x"FB",x"C7", -- 0x2AC0 - x"F0",x"FC",x"F0",x"0F",x"F1",x"7E",x"F3",x"1C", -- 0x2AC8 - x"F1",x"67",x"F2",x"2C",x"F1",x"03",x"F2",x"0F", -- 0x2AD0 - x"F2",x"03",x"04",x"04",x"03",x"03",x"03",x"02", -- 0x2AD8 - x"01",x"03",x"03",x"01",x"01",x"00",x"00",x"00", -- 0x2AE0 - x"00",x"01",x"01",x"00",x"00",x"00",x"00",x"00", -- 0x2AE8 - x"AD",x"C0",x"02",x"29",x"01",x"D0",x"05",x"A2", -- 0x2AF0 - x"A3",x"4C",x"7E",x"C4",x"C0",x"4E",x"B0",x"03", -- 0x2AF8 - x"4C",x"70",x"D0",x"C0",x"66",x"B0",x"F9",x"98", -- 0x2B00 - x"38",x"E9",x"4E",x"A8",x"B9",x"C2",x"EA",x"48", -- 0x2B08 - x"B9",x"C1",x"EA",x"48",x"98",x"4A",x"A8",x"B9", -- 0x2B10 - x"D9",x"EA",x"48",x"B9",x"E5",x"EA",x"8D",x"C3", -- 0x2B18 - x"02",x"A9",x"00",x"8D",x"F0",x"02",x"20",x"03", -- 0x2B20 - x"CF",x"AD",x"C3",x"02",x"D0",x"06",x"20",x"22", -- 0x2B28 - x"D9",x"4C",x"3B",x"EB",x"A5",x"D0",x"C9",x"90", -- 0x2B30 - x"20",x"2A",x"D9",x"AC",x"F0",x"02",x"A5",x"33", -- 0x2B38 - x"99",x"E1",x"02",x"A5",x"34",x"99",x"E2",x"02", -- 0x2B40 - x"C8",x"C8",x"8C",x"F0",x"02",x"68",x"A8",x"88", -- 0x2B48 - x"F0",x"08",x"98",x"48",x"20",x"65",x"D0",x"4C", -- 0x2B50 - x"26",x"EB",x"A9",x"00",x"8D",x"E0",x"02",x"68", -- 0x2B58 - x"AA",x"68",x"A8",x"A9",x"EB",x"48",x"A9",x"6D", -- 0x2B60 - x"48",x"98",x"48",x"8A",x"48",x"60",x"A9",x"01", -- 0x2B68 - x"2C",x"E0",x"02",x"F0",x"F8",x"4C",x"36",x"D3", -- 0x2B70 - x"AD",x"DF",x"02",x"10",x"0B",x"08",x"29",x"7F", -- 0x2B78 - x"48",x"A9",x"00",x"8D",x"DF",x"02",x"68",x"28", -- 0x2B80 - x"60",x"C4",x"9D",x"B0",x"02",x"38",x"60",x"D0", -- 0x2B88 - x"06",x"C5",x"9C",x"90",x"F9",x"F0",x"F7",x"20", -- 0x2B90 - x"B5",x"EB",x"90",x"F2",x"AA",x"AD",x"C0",x"02", -- 0x2B98 - x"29",x"02",x"08",x"8A",x"28",x"D0",x"E6",x"98", -- 0x2BA0 - x"48",x"38",x"E9",x"1C",x"A8",x"8A",x"20",x"B5", -- 0x2BA8 - x"EB",x"68",x"A8",x"8A",x"60",x"CC",x"C2",x"02", -- 0x2BB0 - x"90",x"02",x"F0",x"01",x"60",x"CD",x"C1",x"02", -- 0x2BB8 - x"60",x"AC",x"C2",x"02",x"AD",x"C1",x"02",x"D0", -- 0x2BC0 - x"01",x"88",x"38",x"E9",x"01",x"60",x"20",x"03", -- 0x2BC8 - x"CF",x"20",x"22",x"D9",x"A5",x"33",x"A4",x"34", -- 0x2BD0 - x"20",x"89",x"EB",x"90",x"03",x"4C",x"7C",x"C4", -- 0x2BD8 - x"85",x"A6",x"84",x"A7",x"4C",x"0F",x"C7",x"AD", -- 0x2BE0 - x"60",x"02",x"D0",x"F1",x"AD",x"C0",x"02",x"48", -- 0x2BE8 - x"29",x"01",x"F0",x"05",x"A2",x"A3",x"4C",x"7E", -- 0x2BF0 - x"C4",x"68",x"29",x"FD",x"8D",x"C0",x"02",x"20", -- 0x2BF8 - x"C1",x"EB",x"48",x"98",x"18",x"69",x"1C",x"A8", -- 0x2C00 - x"68",x"4C",x"E0",x"EB",x"20",x"C1",x"EB",x"20", -- 0x2C08 - x"89",x"EB",x"B0",x"C9",x"48",x"AD",x"C0",x"02", -- 0x2C10 - x"09",x"02",x"8D",x"C0",x"02",x"68",x"4C",x"E0", -- 0x2C18 - x"EB",x"AD",x"C0",x"02",x"A8",x"29",x"01",x"F0", -- 0x2C20 - x"09",x"98",x"29",x"FE",x"8D",x"C0",x"02",x"20", -- 0x2C28 - x"67",x"F9",x"60",x"AD",x"C0",x"02",x"48",x"29", -- 0x2C30 - x"02",x"F0",x"B9",x"68",x"09",x"01",x"8D",x"C0", -- 0x2C38 - x"02",x"20",x"20",x"F9",x"60",x"20",x"62",x"D0", -- 0x2C40 - x"20",x"17",x"CF",x"A5",x"34",x"48",x"A5",x"33", -- 0x2C48 - x"48",x"20",x"22",x"D9",x"A5",x"33",x"8D",x"E1", -- 0x2C50 - x"02",x"A5",x"34",x"8D",x"E2",x"02",x"68",x"85", -- 0x2C58 - x"33",x"68",x"85",x"34",x"20",x"65",x"D0",x"20", -- 0x2C60 - x"17",x"CF",x"A5",x"34",x"48",x"A5",x"33",x"48", -- 0x2C68 - x"20",x"22",x"D9",x"A5",x"34",x"8D",x"E4",x"02", -- 0x2C70 - x"A5",x"33",x"8D",x"E3",x"02",x"68",x"85",x"33", -- 0x2C78 - x"68",x"85",x"34",x"20",x"C8",x"F1",x"AC",x"E1", -- 0x2C80 - x"02",x"AD",x"E0",x"02",x"29",x"01",x"D0",x"09", -- 0x2C88 - x"AD",x"E2",x"02",x"20",x"99",x"D4",x"4C",x"5F", -- 0x2C90 - x"D0",x"4C",x"C2",x"D8",x"E6",x"E9",x"D0",x"02", -- 0x2C98 - x"E6",x"EA",x"AD",x"60",x"EA",x"C9",x"20",x"F0", -- 0x2CA0 - x"F3",x"20",x"B9",x"EC",x"60",x"2C",x"60",x"EA", -- 0x2CA8 - x"2C",x"60",x"EA",x"60",x"80",x"4F",x"C7",x"52", -- 0x2CB0 - x"58",x"C9",x"C8",x"F0",x"0E",x"C9",x"27",x"F0", -- 0x2CB8 - x"0A",x"C9",x"3A",x"B0",x"06",x"38",x"E9",x"30", -- 0x2CC0 - x"38",x"E9",x"D0",x"60",x"D8",x"A2",x"FF",x"86", -- 0x2CC8 - x"A9",x"9A",x"A9",x"CC",x"A0",x"EC",x"85",x"1B", -- 0x2CD0 - x"84",x"1C",x"A9",x"4C",x"85",x"1A",x"85",x"C3", -- 0x2CD8 - x"85",x"21",x"8D",x"FB",x"02",x"A9",x"36",x"A0", -- 0x2CE0 - x"D3",x"85",x"22",x"84",x"23",x"8D",x"FC",x"02", -- 0x2CE8 - x"8C",x"FD",x"02",x"8D",x"F5",x"02",x"8C",x"F6", -- 0x2CF0 - x"02",x"A2",x"1C",x"BD",x"9B",x"EC",x"95",x"E1", -- 0x2CF8 - x"CA",x"D0",x"F8",x"A9",x"03",x"85",x"C2",x"8A", -- 0x2D00 - x"85",x"D7",x"85",x"87",x"85",x"2F",x"48",x"85", -- 0x2D08 - x"2E",x"8D",x"F2",x"02",x"A2",x"88",x"86",x"85", -- 0x2D10 - x"A8",x"A9",x"02",x"8D",x"C0",x"02",x"A9",x"28", -- 0x2D18 - x"8D",x"57",x"02",x"A9",x"50",x"8D",x"56",x"02", -- 0x2D20 - x"A9",x"00",x"85",x"30",x"8D",x"58",x"02",x"8D", -- 0x2D28 - x"59",x"02",x"20",x"3E",x"C8",x"20",x"CE",x"CC", -- 0x2D30 - x"A9",x"96",x"A0",x"ED",x"20",x"B0",x"CC",x"20", -- 0x2D38 - x"F0",x"CB",x"A2",x"00",x"A0",x"05",x"86",x"9A", -- 0x2D40 - x"84",x"9B",x"A0",x"00",x"98",x"91",x"9A",x"E6", -- 0x2D48 - x"9A",x"D0",x"02",x"E6",x"9B",x"20",x"F0",x"C6", -- 0x2D50 - x"A5",x"9A",x"A4",x"9B",x"20",x"44",x"C4",x"20", -- 0x2D58 - x"F0",x"CB",x"A5",x"A6",x"38",x"E5",x"9A",x"AA", -- 0x2D60 - x"A5",x"A7",x"E5",x"9B",x"20",x"C5",x"E0",x"A9", -- 0x2D68 - x"88",x"A0",x"ED",x"20",x"B0",x"CC",x"A9",x"B0", -- 0x2D70 - x"A0",x"CC",x"85",x"1B",x"84",x"1C",x"A9",x"10", -- 0x2D78 - x"8D",x"F8",x"02",x"4C",x"A8",x"C4",x"00",x"00", -- 0x2D80 - x"20",x"42",x"59",x"54",x"45",x"53",x"20",x"46", -- 0x2D88 - x"52",x"45",x"45",x"0A",x"0D",x"00",x"4F",x"52", -- 0x2D90 - x"49",x"43",x"20",x"45",x"58",x"54",x"45",x"4E", -- 0x2D98 - x"44",x"45",x"44",x"20",x"42",x"41",x"53",x"49", -- 0x2DA0 - x"43",x"20",x"56",x"31",x"2E",x"31",x"0D",x"0A", -- 0x2DA8 - x"60",x"20",x"31",x"39",x"38",x"33",x"20",x"54", -- 0x2DB0 - x"41",x"4E",x"47",x"45",x"52",x"49",x"4E",x"45", -- 0x2DB8 - x"0D",x"0A",x"00",x"00",x"A2",x"00",x"A0",x"00", -- 0x2DC0 - x"C4",x"10",x"D0",x"04",x"E4",x"11",x"F0",x"0F", -- 0x2DC8 - x"B1",x"0C",x"91",x"0E",x"C8",x"D0",x"F1",x"E6", -- 0x2DD0 - x"0D",x"E6",x"0F",x"E8",x"4C",x"C8",x"ED",x"60", -- 0x2DD8 - x"48",x"20",x"8C",x"EE",x"A9",x"00",x"A2",x"00", -- 0x2DE0 - x"A0",x"03",x"20",x"AB",x"EE",x"A9",x"01",x"A0", -- 0x2DE8 - x"19",x"20",x"AB",x"EE",x"A9",x"00",x"8D",x"71", -- 0x2DF0 - x"02",x"AD",x"0B",x"03",x"29",x"7F",x"09",x"40", -- 0x2DF8 - x"8D",x"0B",x"03",x"A9",x"C0",x"8D",x"0E",x"03", -- 0x2E00 - x"A9",x"10",x"8D",x"06",x"03",x"8D",x"04",x"03", -- 0x2E08 - x"A9",x"27",x"8D",x"07",x"03",x"8D",x"05",x"03", -- 0x2E10 - x"68",x"60",x"48",x"A9",x"40",x"8D",x"0E",x"03", -- 0x2E18 - x"68",x"60",x"48",x"AD",x"0D",x"03",x"29",x"40", -- 0x2E20 - x"F0",x"06",x"8D",x"0D",x"03",x"20",x"34",x"EE", -- 0x2E28 - x"68",x"4C",x"4A",x"02",x"48",x"8A",x"48",x"98", -- 0x2E30 - x"48",x"A0",x"00",x"B9",x"72",x"02",x"38",x"E9", -- 0x2E38 - x"01",x"99",x"72",x"02",x"C8",x"B9",x"72",x"02", -- 0x2E40 - x"E9",x"00",x"99",x"72",x"02",x"C8",x"C0",x"06", -- 0x2E48 - x"D0",x"E9",x"A9",x"00",x"20",x"9D",x"EE",x"C0", -- 0x2E50 - x"00",x"D0",x"10",x"A2",x"00",x"A0",x"03",x"20", -- 0x2E58 - x"AB",x"EE",x"20",x"95",x"F4",x"8A",x"10",x"03", -- 0x2E60 - x"8E",x"DF",x"02",x"A9",x"01",x"20",x"9D",x"EE", -- 0x2E68 - x"C0",x"00",x"D0",x"12",x"A2",x"00",x"A0",x"19", -- 0x2E70 - x"20",x"AB",x"EE",x"AD",x"71",x"02",x"49",x"01", -- 0x2E78 - x"8D",x"71",x"02",x"20",x"01",x"F8",x"68",x"A8", -- 0x2E80 - x"68",x"AA",x"68",x"60",x"48",x"98",x"48",x"A0", -- 0x2E88 - x"05",x"A9",x"00",x"99",x"72",x"02",x"88",x"10", -- 0x2E90 - x"FA",x"68",x"A8",x"68",x"60",x"48",x"0A",x"A8", -- 0x2E98 - x"78",x"B9",x"72",x"02",x"BE",x"73",x"02",x"58", -- 0x2EA0 - x"A8",x"68",x"60",x"48",x"8A",x"48",x"98",x"48", -- 0x2EA8 - x"BA",x"BD",x"03",x"01",x"0A",x"A8",x"68",x"48", -- 0x2EB0 - x"78",x"99",x"72",x"02",x"BD",x"02",x"01",x"99", -- 0x2EB8 - x"73",x"02",x"58",x"68",x"A8",x"68",x"AA",x"68", -- 0x2EC0 - x"60",x"20",x"AB",x"EE",x"20",x"9D",x"EE",x"C0", -- 0x2EC8 - x"00",x"D0",x"F9",x"E0",x"00",x"D0",x"F5",x"60", -- 0x2ED0 - x"AD",x"13",x"02",x"8D",x"14",x"02",x"4E",x"12", -- 0x2ED8 - x"02",x"6E",x"12",x"02",x"6E",x"12",x"02",x"60", -- 0x2EE0 - x"48",x"98",x"48",x"20",x"DE",x"EE",x"20",x"49", -- 0x2EE8 - x"F0",x"20",x"24",x"F0",x"68",x"A8",x"68",x"60", -- 0x2EF0 - x"D8",x"20",x"D8",x"EE",x"2C",x"E2",x"02",x"10", -- 0x2EF8 - x"0A",x"A9",x"FF",x"4D",x"E1",x"02",x"AA",x"E8", -- 0x2F00 - x"8E",x"E1",x"02",x"2C",x"E4",x"02",x"10",x"0A", -- 0x2F08 - x"A9",x"FF",x"4D",x"E3",x"02",x"AA",x"E8",x"8E", -- 0x2F10 - x"E3",x"02",x"AD",x"E1",x"02",x"CD",x"E3",x"02", -- 0x2F18 - x"90",x"0F",x"AE",x"E1",x"02",x"F0",x"09",x"AD", -- 0x2F20 - x"E3",x"02",x"20",x"40",x"EF",x"20",x"84",x"EF", -- 0x2F28 - x"60",x"AE",x"E3",x"02",x"F0",x"09",x"AD",x"E1", -- 0x2F30 - x"02",x"20",x"40",x"EF",x"20",x"5C",x"EF",x"60", -- 0x2F38 - x"85",x"0D",x"8E",x"00",x"02",x"A9",x"00",x"85", -- 0x2F40 - x"0C",x"8D",x"01",x"02",x"20",x"C8",x"EF",x"20", -- 0x2F48 - x"FA",x"EF",x"A9",x"00",x"85",x"0E",x"85",x"0F", -- 0x2F50 - x"8D",x"00",x"02",x"60",x"2C",x"E4",x"02",x"10", -- 0x2F58 - x"06",x"20",x"95",x"F0",x"4C",x"6A",x"EF",x"20", -- 0x2F60 - x"89",x"F0",x"20",x"AC",x"EF",x"F0",x"0E",x"2C", -- 0x2F68 - x"E2",x"02",x"10",x"06",x"20",x"B2",x"F0",x"4C", -- 0x2F70 - x"7D",x"EF",x"20",x"A1",x"F0",x"20",x"16",x"F0", -- 0x2F78 - x"CA",x"D0",x"D9",x"60",x"2C",x"E2",x"02",x"10", -- 0x2F80 - x"06",x"20",x"B2",x"F0",x"4C",x"92",x"EF",x"20", -- 0x2F88 - x"A1",x"F0",x"20",x"AC",x"EF",x"F0",x"0E",x"2C", -- 0x2F90 - x"E4",x"02",x"10",x"06",x"20",x"95",x"F0",x"4C", -- 0x2F98 - x"A5",x"EF",x"20",x"89",x"F0",x"20",x"16",x"F0", -- 0x2FA0 - x"CA",x"D0",x"D9",x"60",x"D8",x"18",x"A5",x"0E", -- 0x2FA8 - x"65",x"0C",x"85",x"0E",x"A5",x"0F",x"65",x"0D", -- 0x2FB0 - x"85",x"0F",x"24",x"0E",x"10",x"03",x"18",x"69", -- 0x2FB8 - x"01",x"CD",x"00",x"02",x"8D",x"00",x"02",x"60", -- 0x2FC0 - x"48",x"8A",x"48",x"98",x"48",x"A9",x"00",x"85", -- 0x2FC8 - x"0E",x"85",x"0F",x"A2",x"10",x"06",x"0C",x"26", -- 0x2FD0 - x"0D",x"26",x"0E",x"26",x"0F",x"A5",x"0E",x"38", -- 0x2FD8 - x"ED",x"00",x"02",x"A8",x"A5",x"0F",x"ED",x"01", -- 0x2FE0 - x"02",x"90",x"06",x"E6",x"0C",x"84",x"0E",x"85", -- 0x2FE8 - x"0F",x"CA",x"D0",x"E1",x"68",x"A8",x"68",x"AA", -- 0x2FF0 - x"68",x"60",x"48",x"0E",x"00",x"02",x"2E",x"01", -- 0x2FF8 - x"02",x"AD",x"00",x"02",x"38",x"E5",x"0E",x"AD", -- 0x3000 - x"01",x"02",x"E5",x"0F",x"B0",x"06",x"E6",x"0C", -- 0x3008 - x"D0",x"02",x"E6",x"0D",x"68",x"60",x"2C",x"14", -- 0x3010 - x"02",x"18",x"10",x"04",x"20",x"24",x"F0",x"38", -- 0x3018 - x"2E",x"14",x"02",x"60",x"A0",x"00",x"B1",x"10", -- 0x3020 - x"29",x"40",x"F0",x"1C",x"AD",x"15",x"02",x"2C", -- 0x3028 - x"12",x"02",x"30",x"0E",x"70",x"07",x"49",x"FF", -- 0x3030 - x"31",x"10",x"91",x"10",x"60",x"11",x"10",x"91", -- 0x3038 - x"10",x"60",x"70",x"04",x"51",x"10",x"91",x"10", -- 0x3040 - x"60",x"D8",x"48",x"98",x"48",x"20",x"31",x"F7", -- 0x3048 - x"18",x"69",x"00",x"85",x"10",x"98",x"69",x"A0", -- 0x3050 - x"85",x"11",x"A9",x"00",x"85",x"0D",x"8D",x"01", -- 0x3058 - x"02",x"86",x"0C",x"A9",x"06",x"8D",x"00",x"02", -- 0x3060 - x"20",x"C8",x"EF",x"18",x"A5",x"0C",x"65",x"10", -- 0x3068 - x"85",x"10",x"A9",x"00",x"65",x"11",x"85",x"11", -- 0x3070 - x"A9",x"20",x"A4",x"0E",x"F0",x"04",x"4A",x"88", -- 0x3078 - x"90",x"FA",x"8D",x"15",x"02",x"68",x"A8",x"68", -- 0x3080 - x"60",x"18",x"A5",x"10",x"69",x"28",x"85",x"10", -- 0x3088 - x"90",x"02",x"E6",x"11",x"60",x"38",x"A5",x"10", -- 0x3090 - x"E9",x"28",x"85",x"10",x"B0",x"02",x"C6",x"11", -- 0x3098 - x"60",x"4E",x"15",x"02",x"90",x"0B",x"A9",x"20", -- 0x30A0 - x"8D",x"15",x"02",x"E6",x"10",x"D0",x"02",x"E6", -- 0x30A8 - x"11",x"60",x"0E",x"15",x"02",x"2C",x"15",x"02", -- 0x30B0 - x"50",x"0D",x"A9",x"01",x"8D",x"15",x"02",x"A5", -- 0x30B8 - x"10",x"D0",x"02",x"C6",x"11",x"C6",x"10",x"60", -- 0x30C0 - x"A9",x"04",x"A2",x"E5",x"20",x"F8",x"F2",x"B0", -- 0x30C8 - x"28",x"AD",x"E5",x"02",x"8D",x"12",x"02",x"A9", -- 0x30D0 - x"F0",x"A2",x"E1",x"20",x"F8",x"F2",x"B0",x"19", -- 0x30D8 - x"A9",x"C8",x"A2",x"E3",x"20",x"F8",x"F2",x"B0", -- 0x30E0 - x"10",x"AE",x"E1",x"02",x"8E",x"19",x"02",x"AC", -- 0x30E8 - x"E3",x"02",x"8C",x"1A",x"02",x"20",x"E8",x"EE", -- 0x30F0 - x"60",x"EE",x"E0",x"02",x"60",x"20",x"0A",x"F3", -- 0x30F8 - x"B0",x"0A",x"AE",x"19",x"02",x"AC",x"1A",x"02", -- 0x3100 - x"20",x"E8",x"EE",x"60",x"EE",x"E0",x"02",x"60", -- 0x3108 - x"20",x"0A",x"F3",x"B0",x"04",x"20",x"F8",x"EE", -- 0x3110 - x"60",x"EE",x"E0",x"02",x"60",x"AE",x"E2",x"02", -- 0x3118 - x"D0",x"07",x"AE",x"E1",x"02",x"8E",x"13",x"02", -- 0x3120 - x"60",x"EE",x"E0",x"02",x"60",x"AE",x"E2",x"02", -- 0x3128 - x"D0",x"3B",x"AE",x"E1",x"02",x"E0",x"20",x"90", -- 0x3130 - x"34",x"E0",x"80",x"B0",x"30",x"A9",x"02",x"A2", -- 0x3138 - x"E3",x"20",x"F8",x"F2",x"B0",x"27",x"A9",x"04", -- 0x3140 - x"A2",x"E5",x"20",x"F8",x"F2",x"B0",x"1E",x"AD", -- 0x3148 - x"19",x"02",x"C9",x"EB",x"B0",x"17",x"AD",x"1A", -- 0x3150 - x"02",x"C9",x"C1",x"B0",x"10",x"20",x"71",x"F1", -- 0x3158 - x"20",x"9B",x"F1",x"AE",x"19",x"02",x"AC",x"1A", -- 0x3160 - x"02",x"20",x"49",x"F0",x"60",x"EE",x"E0",x"02", -- 0x3168 - x"60",x"D8",x"AD",x"E5",x"02",x"8D",x"12",x"02", -- 0x3170 - x"20",x"DE",x"EE",x"AD",x"E1",x"02",x"85",x"0C", -- 0x3178 - x"A9",x"00",x"85",x"0D",x"A2",x"03",x"06",x"0C", -- 0x3180 - x"26",x"0D",x"CA",x"D0",x"F9",x"AD",x"E3",x"02", -- 0x3188 - x"0A",x"0A",x"18",x"69",x"98",x"18",x"65",x"0D", -- 0x3190 - x"85",x"0D",x"60",x"D8",x"A0",x"00",x"84",x"0F", -- 0x3198 - x"B1",x"0C",x"85",x"0E",x"20",x"5D",x"F3",x"26", -- 0x31A0 - x"0E",x"26",x"0E",x"A2",x"06",x"26",x"0E",x"90", -- 0x31A8 - x"03",x"20",x"24",x"F0",x"20",x"A1",x"F0",x"CA", -- 0x31B0 - x"D0",x"F3",x"20",x"6E",x"F3",x"20",x"89",x"F0", -- 0x31B8 - x"A4",x"0F",x"C8",x"C0",x"08",x"D0",x"D7",x"60", -- 0x31C0 - x"A9",x"F0",x"A2",x"E1",x"20",x"F8",x"F2",x"B0", -- 0x31C8 - x"2F",x"A9",x"C8",x"A2",x"E3",x"20",x"F8",x"F2", -- 0x31D0 - x"B0",x"26",x"AE",x"E1",x"02",x"8E",x"19",x"02", -- 0x31D8 - x"AC",x"E3",x"02",x"8C",x"1A",x"02",x"20",x"49", -- 0x31E0 - x"F0",x"A0",x"00",x"B1",x"10",x"2D",x"15",x"02", -- 0x31E8 - x"F0",x"05",x"A9",x"FF",x"4C",x"F9",x"F1",x"A9", -- 0x31F0 - x"00",x"8D",x"E1",x"02",x"8D",x"E2",x"02",x"60", -- 0x31F8 - x"EE",x"E0",x"02",x"60",x"A9",x"10",x"85",x"0C", -- 0x3200 - x"A9",x"00",x"85",x"0D",x"20",x"1C",x"F2",x"60", -- 0x3208 - x"A9",x"00",x"85",x"0C",x"A9",x"01",x"85",x"0D", -- 0x3210 - x"20",x"1C",x"F2",x"60",x"A9",x"08",x"A2",x"E1", -- 0x3218 - x"20",x"F8",x"F2",x"B0",x"3F",x"20",x"5D",x"F3", -- 0x3220 - x"AD",x"E1",x"02",x"05",x"0C",x"8D",x"02",x"02", -- 0x3228 - x"AE",x"1F",x"02",x"D0",x"12",x"A6",x"0D",x"9D", -- 0x3230 - x"6B",x"02",x"A9",x"A8",x"18",x"65",x"0D",x"AA", -- 0x3238 - x"A0",x"BB",x"A9",x"1B",x"4C",x"51",x"F2",x"A9", -- 0x3240 - x"00",x"18",x"65",x"0D",x"AA",x"A0",x"A0",x"A9", -- 0x3248 - x"C8",x"8D",x"00",x"02",x"86",x"10",x"84",x"11", -- 0x3250 - x"A9",x"01",x"8D",x"01",x"02",x"20",x"CD",x"F2", -- 0x3258 - x"20",x"6E",x"F3",x"60",x"EE",x"E0",x"02",x"60", -- 0x3260 - x"D8",x"AD",x"E3",x"02",x"8D",x"01",x"02",x"F0", -- 0x3268 - x"58",x"A0",x"00",x"AD",x"19",x"02",x"38",x"E9", -- 0x3270 - x"06",x"90",x"04",x"C8",x"4C",x"76",x"F2",x"98", -- 0x3278 - x"18",x"6D",x"E3",x"02",x"A8",x"AD",x"E4",x"02", -- 0x3280 - x"69",x"00",x"D0",x"3D",x"C0",x"29",x"B0",x"39", -- 0x3288 - x"AD",x"E6",x"02",x"D0",x"34",x"AD",x"E1",x"02", -- 0x3290 - x"8D",x"00",x"02",x"F0",x"2C",x"18",x"6D",x"1A", -- 0x3298 - x"02",x"A8",x"AD",x"E2",x"02",x"69",x"00",x"D0", -- 0x32A0 - x"20",x"C0",x"C9",x"B0",x"1C",x"C0",x"C8",x"D0", -- 0x32A8 - x"02",x"A0",x"00",x"8C",x"1A",x"02",x"AD",x"E5", -- 0x32B0 - x"02",x"8D",x"02",x"02",x"20",x"CD",x"F2",x"AC", -- 0x32B8 - x"1A",x"02",x"AE",x"19",x"02",x"20",x"49",x"F0", -- 0x32C0 - x"60",x"EE",x"E0",x"02",x"60",x"D8",x"AD",x"02", -- 0x32C8 - x"02",x"A0",x"00",x"91",x"10",x"C8",x"CC",x"01", -- 0x32D0 - x"02",x"D0",x"F8",x"20",x"89",x"F0",x"CE",x"00", -- 0x32D8 - x"02",x"D0",x"EB",x"60",x"8D",x"04",x"02",x"BD", -- 0x32E0 - x"01",x"02",x"D0",x"0A",x"BD",x"00",x"02",x"F0", -- 0x32E8 - x"05",x"CD",x"04",x"02",x"90",x"01",x"38",x"60", -- 0x32F0 - x"8D",x"04",x"02",x"BD",x"01",x"02",x"D0",x"08", -- 0x32F8 - x"BD",x"00",x"02",x"CD",x"04",x"02",x"90",x"01", -- 0x3300 - x"38",x"60",x"A9",x"04",x"A2",x"E5",x"20",x"F8", -- 0x3308 - x"F2",x"B0",x"49",x"18",x"AD",x"E1",x"02",x"6D", -- 0x3310 - x"19",x"02",x"8D",x"00",x"02",x"AD",x"E2",x"02", -- 0x3318 - x"69",x"00",x"8D",x"01",x"02",x"A2",x"00",x"A9", -- 0x3320 - x"F0",x"20",x"F8",x"F2",x"B0",x"2E",x"18",x"AD", -- 0x3328 - x"E3",x"02",x"6D",x"1A",x"02",x"8D",x"02",x"02", -- 0x3330 - x"AD",x"E4",x"02",x"69",x"00",x"8D",x"03",x"02", -- 0x3338 - x"A2",x"02",x"A9",x"C8",x"20",x"F8",x"F2",x"B0", -- 0x3340 - x"13",x"AD",x"E5",x"02",x"8D",x"12",x"02",x"AD", -- 0x3348 - x"00",x"02",x"8D",x"19",x"02",x"AD",x"02",x"02", -- 0x3350 - x"8D",x"1A",x"02",x"18",x"60",x"A5",x"10",x"8D", -- 0x3358 - x"16",x"02",x"A5",x"11",x"8D",x"17",x"02",x"AD", -- 0x3360 - x"15",x"02",x"8D",x"18",x"02",x"60",x"AD",x"16", -- 0x3368 - x"02",x"85",x"10",x"AD",x"17",x"02",x"85",x"11", -- 0x3370 - x"AD",x"18",x"02",x"8D",x"15",x"02",x"60",x"D8", -- 0x3378 - x"AD",x"E2",x"02",x"D0",x"3D",x"AD",x"E1",x"02", -- 0x3380 - x"F0",x"38",x"AD",x"19",x"02",x"CD",x"E1",x"02", -- 0x3388 - x"90",x"30",x"18",x"6D",x"E1",x"02",x"C9",x"F0", -- 0x3390 - x"B0",x"28",x"AD",x"1A",x"02",x"CD",x"E1",x"02", -- 0x3398 - x"90",x"20",x"18",x"6D",x"E1",x"02",x"C9",x"C8", -- 0x33A0 - x"B0",x"18",x"A2",x"E3",x"A9",x"04",x"20",x"F8", -- 0x33A8 - x"F2",x"B0",x"0F",x"AD",x"E3",x"02",x"8D",x"12", -- 0x33B0 - x"02",x"20",x"D8",x"EE",x"20",x"C6",x"F3",x"4C", -- 0x33B8 - x"C5",x"F3",x"EE",x"E0",x"02",x"60",x"20",x"5D", -- 0x33C0 - x"F3",x"AD",x"1A",x"02",x"38",x"ED",x"E1",x"02", -- 0x33C8 - x"A8",x"AE",x"19",x"02",x"20",x"49",x"F0",x"AD", -- 0x33D0 - x"E1",x"02",x"85",x"0F",x"20",x"85",x"F4",x"A9", -- 0x33D8 - x"80",x"8D",x"1B",x"02",x"8D",x"1D",x"02",x"A9", -- 0x33E0 - x"00",x"8D",x"1C",x"02",x"AD",x"E1",x"02",x"8D", -- 0x33E8 - x"1E",x"02",x"A9",x"00",x"85",x"0F",x"20",x"14", -- 0x33F0 - x"F4",x"20",x"44",x"F4",x"A5",x"0F",x"F0",x"03", -- 0x33F8 - x"20",x"16",x"F0",x"AD",x"1C",x"02",x"D0",x"EA", -- 0x3400 - x"AD",x"1E",x"02",x"CD",x"E1",x"02",x"D0",x"E2", -- 0x3408 - x"20",x"6E",x"F3",x"60",x"AD",x"1D",x"02",x"AE", -- 0x3410 - x"1E",x"02",x"20",x"74",x"F4",x"A5",x"0C",x"18", -- 0x3418 - x"6D",x"1B",x"02",x"8D",x"1B",x"02",x"AD",x"1C", -- 0x3420 - x"02",x"85",x"0C",x"65",x"0D",x"8D",x"1C",x"02", -- 0x3428 - x"C5",x"0C",x"F0",x"0F",x"B0",x"06",x"20",x"A1", -- 0x3430 - x"F0",x"4C",x"3F",x"F4",x"20",x"B2",x"F0",x"A9", -- 0x3438 - x"01",x"85",x"0F",x"60",x"AD",x"1B",x"02",x"AE", -- 0x3440 - x"1C",x"02",x"20",x"74",x"F4",x"38",x"AD",x"1D", -- 0x3448 - x"02",x"E5",x"0C",x"8D",x"1D",x"02",x"AD",x"1E", -- 0x3450 - x"02",x"85",x"0C",x"E5",x"0D",x"8D",x"1E",x"02", -- 0x3458 - x"C5",x"0C",x"F0",x"0F",x"B0",x"06",x"20",x"89", -- 0x3460 - x"F0",x"4C",x"6F",x"F4",x"20",x"95",x"F0",x"A9", -- 0x3468 - x"01",x"85",x"0F",x"60",x"85",x"0C",x"86",x"0D", -- 0x3470 - x"A6",x"0E",x"A5",x"0D",x"2A",x"66",x"0D",x"66", -- 0x3478 - x"0C",x"CA",x"D0",x"F6",x"60",x"E6",x"0F",x"A9", -- 0x3480 - x"00",x"85",x"0E",x"A9",x"01",x"0A",x"E6",x"0E", -- 0x3488 - x"C5",x"0F",x"90",x"F9",x"60",x"48",x"08",x"98", -- 0x3490 - x"48",x"D8",x"AD",x"08",x"02",x"10",x"1E",x"29", -- 0x3498 - x"87",x"8D",x"10",x"02",x"AE",x"0A",x"02",x"20", -- 0x34A0 - x"61",x"F5",x"CD",x"10",x"02",x"D0",x"0E",x"CE", -- 0x34A8 - x"0E",x"02",x"D0",x"33",x"AD",x"4F",x"02",x"8D", -- 0x34B0 - x"0E",x"02",x"4C",x"C6",x"F4",x"AD",x"4E",x"02", -- 0x34B8 - x"8D",x"0E",x"02",x"20",x"23",x"F5",x"20",x"EF", -- 0x34C0 - x"F4",x"AA",x"10",x"1D",x"48",x"AD",x"6A",x"02", -- 0x34C8 - x"29",x"08",x"D0",x"0F",x"68",x"48",x"C9",x"A0", -- 0x34D0 - x"90",x"06",x"20",x"14",x"FB",x"4C",x"E3",x"F4", -- 0x34D8 - x"20",x"2A",x"FB",x"68",x"4C",x"E9",x"F4",x"A9", -- 0x34E0 - x"00",x"AA",x"68",x"A8",x"28",x"68",x"60",x"AD", -- 0x34E8 - x"09",x"02",x"A8",x"A9",x"00",x"C0",x"A4",x"F0", -- 0x34F0 - x"04",x"C0",x"A7",x"D0",x"03",x"18",x"69",x"40", -- 0x34F8 - x"18",x"6D",x"08",x"02",x"10",x"1C",x"29",x"7F", -- 0x3500 - x"AA",x"BD",x"78",x"FF",x"2D",x"0C",x"02",x"10", -- 0x3508 - x"03",x"38",x"E9",x"20",x"29",x"7F",x"C0",x"A2", -- 0x3510 - x"D0",x"06",x"C9",x"40",x"30",x"02",x"29",x"1F", -- 0x3518 - x"09",x"80",x"60",x"A9",x"38",x"8D",x"0D",x"02", -- 0x3520 - x"8D",x"08",x"02",x"8D",x"09",x"02",x"A9",x"7F", -- 0x3528 - x"48",x"68",x"48",x"AA",x"A9",x"07",x"20",x"61", -- 0x3530 - x"F5",x"0D",x"0D",x"02",x"10",x"12",x"A2",x"00", -- 0x3538 - x"A0",x"20",x"CC",x"0D",x"02",x"D0",x"01",x"E8", -- 0x3540 - x"9D",x"08",x"02",x"68",x"48",x"9D",x"0A",x"02", -- 0x3548 - x"38",x"68",x"6A",x"48",x"38",x"AD",x"0D",x"02", -- 0x3550 - x"E9",x"08",x"8D",x"0D",x"02",x"10",x"D2",x"68", -- 0x3558 - x"60",x"48",x"A9",x"0E",x"20",x"90",x"F5",x"68", -- 0x3560 - x"29",x"07",x"AA",x"8D",x"11",x"02",x"09",x"B8", -- 0x3568 - x"8D",x"00",x"03",x"A0",x"04",x"88",x"D0",x"FD", -- 0x3570 - x"AD",x"00",x"03",x"29",x"08",x"D0",x"0D",x"CA", -- 0x3578 - x"8A",x"29",x"07",x"AA",x"CD",x"11",x"02",x"D0", -- 0x3580 - x"E5",x"A9",x"00",x"60",x"8A",x"09",x"80",x"60", -- 0x3588 - x"08",x"78",x"8D",x"0F",x"03",x"A8",x"8A",x"C0", -- 0x3590 - x"07",x"D0",x"02",x"09",x"40",x"48",x"AD",x"0C", -- 0x3598 - x"03",x"09",x"EE",x"8D",x"0C",x"03",x"29",x"11", -- 0x35A0 - x"09",x"CC",x"8D",x"0C",x"03",x"AA",x"68",x"8D", -- 0x35A8 - x"0F",x"03",x"8A",x"09",x"EC",x"8D",x"0C",x"03", -- 0x35B0 - x"29",x"11",x"09",x"CC",x"8D",x"0C",x"03",x"28", -- 0x35B8 - x"60",x"08",x"78",x"8D",x"01",x"03",x"AD",x"00", -- 0x35C0 - x"03",x"29",x"EF",x"8D",x"00",x"03",x"AD",x"00", -- 0x35C8 - x"03",x"09",x"10",x"8D",x"00",x"03",x"28",x"AD", -- 0x35D0 - x"0D",x"03",x"29",x"02",x"F0",x"F9",x"AD",x"0D", -- 0x35D8 - x"03",x"60",x"CF",x"CF",x"CF",x"CF",x"A3",x"CF", -- 0x35E0 - x"A6",x"CC",x"00",x"27",x"34",x"0F",x"66",x"99", -- 0x35E8 - x"60",x"CF",x"A7",x"B3",x"CF",x"A8",x"BE",x"CF", -- 0x35F0 - x"CF",x"CF",x"CF",x"CF",x"A5",x"A5",x"CF",x"A4", -- 0x35F8 - x"84",x"CF",x"29",x"1F",x"AA",x"BD",x"E2",x"F5", -- 0x3600 - x"18",x"69",x"2F",x"8D",x"61",x"02",x"A9",x"00", -- 0x3608 - x"69",x"F6",x"8D",x"62",x"02",x"AD",x"6A",x"02", -- 0x3610 - x"48",x"29",x"FE",x"8D",x"6A",x"02",x"68",x"29", -- 0x3618 - x"01",x"8D",x"51",x"02",x"A9",x"00",x"20",x"01", -- 0x3620 - x"F8",x"38",x"A9",x"00",x"6C",x"61",x"02",x"CE", -- 0x3628 - x"69",x"02",x"30",x"05",x"20",x"D7",x"F7",x"D0", -- 0x3630 - x"40",x"A9",x"27",x"8D",x"69",x"02",x"AD",x"68", -- 0x3638 - x"02",x"C9",x"01",x"F0",x"34",x"CE",x"68",x"02", -- 0x3640 - x"38",x"A5",x"12",x"E9",x"28",x"85",x"12",x"B0", -- 0x3648 - x"02",x"C6",x"13",x"4C",x"FE",x"F6",x"EE",x"69", -- 0x3650 - x"02",x"A2",x"27",x"EC",x"69",x"02",x"10",x"19", -- 0x3658 - x"20",x"0D",x"F7",x"AD",x"68",x"02",x"CD",x"7E", -- 0x3660 - x"02",x"F0",x"11",x"EE",x"68",x"02",x"18",x"A5", -- 0x3668 - x"12",x"69",x"28",x"85",x"12",x"90",x"02",x"E6", -- 0x3670 - x"13",x"4C",x"FE",x"F6",x"20",x"5D",x"F3",x"A2", -- 0x3678 - x"06",x"BD",x"77",x"02",x"95",x"0B",x"CA",x"D0", -- 0x3680 - x"F8",x"20",x"C4",x"ED",x"20",x"6E",x"F3",x"20", -- 0x3688 - x"1A",x"F7",x"4C",x"FE",x"F6",x"AE",x"7E",x"02", -- 0x3690 - x"AD",x"7A",x"02",x"85",x"12",x"AD",x"7B",x"02", -- 0x3698 - x"85",x"13",x"20",x"1A",x"F7",x"18",x"A5",x"12", -- 0x36A0 - x"69",x"28",x"85",x"12",x"90",x"02",x"E6",x"13", -- 0x36A8 - x"CA",x"D0",x"EF",x"20",x"0D",x"F7",x"A9",x"01", -- 0x36B0 - x"8D",x"68",x"02",x"AD",x"7A",x"02",x"85",x"12", -- 0x36B8 - x"AD",x"7B",x"02",x"85",x"13",x"4C",x"FE",x"F6", -- 0x36C0 - x"20",x"0D",x"F7",x"8E",x"53",x"02",x"4C",x"FE", -- 0x36C8 - x"F6",x"2A",x"2A",x"2A",x"2A",x"2A",x"2A",x"2A", -- 0x36D0 - x"2A",x"4D",x"6A",x"02",x"8D",x"6A",x"02",x"4C", -- 0x36D8 - x"FE",x"F6",x"AD",x"51",x"02",x"49",x"01",x"8D", -- 0x36E0 - x"51",x"02",x"4C",x"FE",x"F6",x"AD",x"0C",x"02", -- 0x36E8 - x"49",x"80",x"8D",x"0C",x"02",x"20",x"5A",x"F7", -- 0x36F0 - x"4C",x"FE",x"F6",x"20",x"9F",x"FA",x"AD",x"6A", -- 0x36F8 - x"02",x"0D",x"51",x"02",x"8D",x"6A",x"02",x"A9", -- 0x3700 - x"01",x"20",x"01",x"F8",x"60",x"A2",x"00",x"20", -- 0x3708 - x"DE",x"F7",x"D0",x"02",x"E8",x"E8",x"8E",x"69", -- 0x3710 - x"02",x"60",x"A0",x"27",x"A9",x"20",x"91",x"12", -- 0x3718 - x"88",x"10",x"FB",x"A0",x"00",x"AD",x"6B",x"02", -- 0x3720 - x"91",x"12",x"AD",x"6C",x"02",x"C8",x"91",x"12", -- 0x3728 - x"60",x"A0",x"00",x"8C",x"63",x"02",x"8D",x"64", -- 0x3730 - x"02",x"0A",x"2E",x"63",x"02",x"0A",x"2E",x"63", -- 0x3738 - x"02",x"18",x"6D",x"64",x"02",x"90",x"03",x"EE", -- 0x3740 - x"63",x"02",x"0A",x"2E",x"63",x"02",x"0A",x"2E", -- 0x3748 - x"63",x"02",x"0A",x"2E",x"63",x"02",x"AC",x"63", -- 0x3750 - x"02",x"60",x"AD",x"0C",x"02",x"10",x"07",x"A9", -- 0x3758 - x"70",x"A0",x"F7",x"4C",x"6A",x"F7",x"A9",x"76", -- 0x3760 - x"A0",x"F7",x"A2",x"23",x"20",x"65",x"F8",x"60", -- 0x3768 - x"07",x"43",x"41",x"50",x"53",x"00",x"07",x"20", -- 0x3770 - x"20",x"20",x"20",x"00",x"48",x"08",x"98",x"48", -- 0x3778 - x"8A",x"48",x"D8",x"E0",x"13",x"F0",x"46",x"E0", -- 0x3780 - x"14",x"F0",x"42",x"E0",x"06",x"F0",x"3E",x"AD", -- 0x3788 - x"6A",x"02",x"29",x"02",x"F0",x"3A",x"8A",x"C9", -- 0x3790 - x"20",x"90",x"32",x"AD",x"6A",x"02",x"29",x"10", -- 0x3798 - x"F0",x"13",x"8A",x"38",x"E9",x"40",x"30",x"09", -- 0x37A0 - x"29",x"1F",x"20",x"E4",x"F7",x"A9",x"1B",x"D0", -- 0x37A8 - x"1C",x"A9",x"20",x"10",x"F5",x"E0",x"7F",x"F0", -- 0x37B0 - x"08",x"68",x"48",x"20",x"E4",x"F7",x"4C",x"D0", -- 0x37B8 - x"F7",x"A9",x"08",x"20",x"02",x"F6",x"A9",x"20", -- 0x37C0 - x"20",x"E4",x"F7",x"A9",x"08",x"20",x"02",x"F6", -- 0x37C8 - x"68",x"AA",x"68",x"A8",x"28",x"68",x"60",x"AD", -- 0x37D0 - x"69",x"02",x"29",x"FE",x"D0",x"05",x"AD",x"6A", -- 0x37D8 - x"02",x"29",x"20",x"60",x"48",x"AC",x"69",x"02", -- 0x37E0 - x"91",x"12",x"2C",x"6A",x"02",x"50",x"0B",x"AD", -- 0x37E8 - x"69",x"02",x"18",x"69",x"28",x"A8",x"68",x"48", -- 0x37F0 - x"91",x"12",x"A9",x"09",x"20",x"02",x"F6",x"68", -- 0x37F8 - x"60",x"2D",x"6A",x"02",x"4A",x"6A",x"8D",x"65", -- 0x3800 - x"02",x"AC",x"69",x"02",x"B1",x"12",x"29",x"7F", -- 0x3808 - x"0D",x"65",x"02",x"91",x"12",x"60",x"A9",x"00", -- 0x3810 - x"85",x"0C",x"A9",x"B9",x"85",x"0D",x"A9",x"00", -- 0x3818 - x"20",x"2D",x"F8",x"A0",x"BA",x"84",x"0D",x"A9", -- 0x3820 - x"20",x"20",x"2D",x"F8",x"60",x"A0",x"00",x"48", -- 0x3828 - x"20",x"54",x"F8",x"91",x"0C",x"C8",x"68",x"48", -- 0x3830 - x"20",x"52",x"F8",x"68",x"48",x"20",x"50",x"F8", -- 0x3838 - x"91",x"0C",x"C8",x"C0",x"00",x"F0",x"07",x"68", -- 0x3840 - x"18",x"69",x"01",x"4C",x"2F",x"F8",x"68",x"60", -- 0x3848 - x"4A",x"4A",x"4A",x"4A",x"29",x"03",x"AA",x"BD", -- 0x3850 - x"61",x"F8",x"91",x"0C",x"C8",x"91",x"0C",x"C8", -- 0x3858 - x"60",x"00",x"38",x"07",x"3F",x"85",x"0C",x"84", -- 0x3860 - x"0D",x"AD",x"1F",x"02",x"D0",x"0D",x"A0",x"00", -- 0x3868 - x"B1",x"0C",x"F0",x"07",x"9D",x"80",x"BB",x"E8", -- 0x3870 - x"C8",x"D0",x"F5",x"60",x"4C",x"7C",x"F7",x"4C", -- 0x3878 - x"78",x"EB",x"4C",x"C1",x"F5",x"4C",x"65",x"F8", -- 0x3880 - x"4C",x"22",x"EE",x"4C",x"B2",x"F8",x"40",x"A2", -- 0x3888 - x"FF",x"9A",x"58",x"D8",x"A2",x"12",x"BD",x"7C", -- 0x3890 - x"F8",x"9D",x"38",x"02",x"CA",x"10",x"F7",x"A9", -- 0x3898 - x"20",x"8D",x"4E",x"02",x"A9",x"04",x"8D",x"4F", -- 0x38A0 - x"02",x"20",x"14",x"FA",x"20",x"B8",x"F8",x"4C", -- 0x38A8 - x"CC",x"EC",x"20",x"B8",x"F8",x"4C",x"71",x"C4", -- 0x38B0 - x"20",x"AA",x"F9",x"A9",x"07",x"A2",x"40",x"20", -- 0x38B8 - x"90",x"F5",x"20",x"E0",x"ED",x"20",x"0E",x"F9", -- 0x38C0 - x"A9",x"FF",x"8D",x"0C",x"02",x"20",x"C9",x"F9", -- 0x38C8 - x"A2",x"05",x"20",x"82",x"F9",x"20",x"16",x"F8", -- 0x38D0 - x"20",x"5A",x"F7",x"60",x"48",x"8A",x"48",x"A9", -- 0x38D8 - x"01",x"8D",x"1F",x"02",x"A9",x"BF",x"8D",x"7B", -- 0x38E0 - x"02",x"8D",x"79",x"02",x"A9",x"68",x"8D",x"7A", -- 0x38E8 - x"02",x"A9",x"90",x"8D",x"78",x"02",x"A9",x"03", -- 0x38F0 - x"8D",x"7E",x"02",x"A9",x"00",x"8D",x"7D",x"02", -- 0x38F8 - x"A9",x"50",x"8D",x"7C",x"02",x"A2",x"0C",x"20", -- 0x3900 - x"38",x"02",x"68",x"AA",x"68",x"60",x"48",x"A9", -- 0x3908 - x"03",x"8D",x"6A",x"02",x"A9",x"00",x"8D",x"6C", -- 0x3910 - x"02",x"A9",x"17",x"8D",x"6B",x"02",x"68",x"60", -- 0x3918 - x"48",x"AD",x"1F",x"02",x"D0",x"05",x"A2",x"0B", -- 0x3920 - x"20",x"82",x"F9",x"A9",x"FE",x"2D",x"6A",x"02", -- 0x3928 - x"8D",x"6A",x"02",x"A9",x"1E",x"8D",x"DF",x"BF", -- 0x3930 - x"A9",x"40",x"8D",x"00",x"A0",x"A2",x"17",x"20", -- 0x3938 - x"82",x"F9",x"A9",x"00",x"8D",x"19",x"02",x"8D", -- 0x3940 - x"1A",x"02",x"85",x"10",x"A9",x"A0",x"85",x"11", -- 0x3948 - x"A9",x"20",x"8D",x"15",x"02",x"A9",x"FF",x"8D", -- 0x3950 - x"13",x"02",x"20",x"DC",x"F8",x"A9",x"01",x"0D", -- 0x3958 - x"6A",x"02",x"8D",x"6A",x"02",x"68",x"60",x"48", -- 0x3960 - x"A9",x"FE",x"2D",x"6A",x"02",x"8D",x"6A",x"02", -- 0x3968 - x"A2",x"11",x"20",x"82",x"F9",x"20",x"C9",x"F9", -- 0x3970 - x"A9",x"01",x"0D",x"6A",x"02",x"8D",x"6A",x"02", -- 0x3978 - x"68",x"60",x"A0",x"06",x"BD",x"92",x"F9",x"99", -- 0x3980 - x"0B",x"00",x"CA",x"88",x"D0",x"F6",x"20",x"C4", -- 0x3988 - x"ED",x"60",x"78",x"FC",x"00",x"B5",x"00",x"03", -- 0x3990 - x"00",x"B4",x"00",x"98",x"80",x"07",x"00",x"98", -- 0x3998 - x"00",x"B4",x"80",x"07",x"00",x"A0",x"01",x"A0", -- 0x39A0 - x"3F",x"1F",x"A9",x"FF",x"8D",x"03",x"03",x"A9", -- 0x39A8 - x"F7",x"8D",x"02",x"03",x"A9",x"B7",x"8D",x"00", -- 0x39B0 - x"03",x"A9",x"DD",x"8D",x"0C",x"03",x"A9",x"7F", -- 0x39B8 - x"8D",x"0E",x"03",x"A9",x"00",x"8D",x"0B",x"03", -- 0x39C0 - x"60",x"A9",x"1A",x"20",x"07",x"FA",x"A9",x"20", -- 0x39C8 - x"A0",x"28",x"99",x"7F",x"BB",x"88",x"D0",x"FA", -- 0x39D0 - x"A9",x"00",x"8D",x"1F",x"02",x"A9",x"BB",x"8D", -- 0x39D8 - x"7B",x"02",x"8D",x"79",x"02",x"A9",x"A8",x"8D", -- 0x39E0 - x"7A",x"02",x"A9",x"D0",x"8D",x"78",x"02",x"A9", -- 0x39E8 - x"1B",x"8D",x"7E",x"02",x"A9",x"04",x"8D",x"7D", -- 0x39F0 - x"02",x"A9",x"10",x"8D",x"7C",x"02",x"A2",x"0C", -- 0x39F8 - x"20",x"38",x"02",x"20",x"5A",x"F7",x"60",x"8D", -- 0x3A00 - x"DF",x"BF",x"A9",x"02",x"A2",x"00",x"A0",x"03", -- 0x3A08 - x"20",x"C9",x"EE",x"60",x"A0",x"00",x"8C",x"60", -- 0x3A10 - x"02",x"8C",x"20",x"02",x"8C",x"00",x"05",x"84", -- 0x3A18 - x"0E",x"88",x"84",x"0C",x"8C",x"00",x"45",x"AD", -- 0x3A20 - x"00",x"05",x"D0",x"04",x"A9",x"C0",x"D0",x"05", -- 0x3A28 - x"EE",x"20",x"02",x"A9",x"40",x"85",x"0F",x"C8", -- 0x3A30 - x"A9",x"03",x"85",x"0D",x"E6",x"0C",x"D0",x"02", -- 0x3A38 - x"E6",x"0D",x"A5",x"0C",x"C5",x"0E",x"D0",x"06", -- 0x3A40 - x"A5",x"0D",x"C5",x"0F",x"F0",x"0F",x"A9",x"AA", -- 0x3A48 - x"91",x"0C",x"D1",x"0C",x"D0",x"07",x"4A",x"91", -- 0x3A50 - x"0C",x"D1",x"0C",x"F0",x"DF",x"38",x"A5",x"0F", -- 0x3A58 - x"E9",x"28",x"85",x"0F",x"A5",x"0E",x"C5",x"0C", -- 0x3A60 - x"A5",x"0F",x"E5",x"0D",x"90",x"09",x"A5",x"0C", -- 0x3A68 - x"A4",x"0D",x"EE",x"60",x"02",x"D0",x"04",x"A5", -- 0x3A70 - x"0E",x"A4",x"0F",x"85",x"A6",x"84",x"A7",x"8D", -- 0x3A78 - x"C1",x"02",x"8C",x"C2",x"02",x"60",x"08",x"78", -- 0x3A80 - x"86",x"14",x"84",x"15",x"A0",x"00",x"B1",x"14", -- 0x3A88 - x"AA",x"98",x"48",x"20",x"90",x"F5",x"68",x"A8", -- 0x3A90 - x"C8",x"C0",x"0E",x"D0",x"F1",x"28",x"60",x"A2", -- 0x3A98 - x"A7",x"A0",x"FA",x"20",x"86",x"FA",x"60",x"18", -- 0x3AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"3E",x"10", -- 0x3AA8 - x"00",x"00",x"00",x"0F",x"00",x"A2",x"BD",x"A0", -- 0x3AB0 - x"FA",x"20",x"86",x"FA",x"60",x"00",x"00",x"00", -- 0x3AB8 - x"00",x"00",x"00",x"0F",x"07",x"10",x"10",x"10", -- 0x3AC0 - x"00",x"08",x"00",x"A2",x"D3",x"A0",x"FA",x"20", -- 0x3AC8 - x"86",x"FA",x"60",x"00",x"00",x"00",x"00",x"00", -- 0x3AD0 - x"00",x"1F",x"07",x"10",x"10",x"10",x"00",x"18", -- 0x3AD8 - x"00",x"A2",x"06",x"A0",x"FB",x"20",x"86",x"FA", -- 0x3AE0 - x"A9",x"00",x"AA",x"8A",x"48",x"A9",x"00",x"20", -- 0x3AE8 - x"90",x"F5",x"A2",x"00",x"CA",x"D0",x"FD",x"68", -- 0x3AF0 - x"AA",x"E8",x"E0",x"70",x"D0",x"ED",x"A9",x"08", -- 0x3AF8 - x"A2",x"00",x"20",x"90",x"F5",x"60",x"00",x"00", -- 0x3B00 - x"00",x"00",x"00",x"00",x"00",x"3E",x"0F",x"00", -- 0x3B08 - x"00",x"00",x"00",x"00",x"A2",x"1C",x"A0",x"FB", -- 0x3B10 - x"20",x"86",x"FA",x"60",x"1F",x"00",x"00",x"00", -- 0x3B18 - x"00",x"00",x"00",x"3E",x"10",x"00",x"00",x"1F", -- 0x3B20 - x"00",x"00",x"A2",x"32",x"A0",x"FB",x"20",x"86", -- 0x3B28 - x"FA",x"60",x"2F",x"00",x"00",x"00",x"00",x"00", -- 0x3B30 - x"00",x"3E",x"10",x"00",x"00",x"1F",x"00",x"00", -- 0x3B38 - x"AD",x"E1",x"02",x"C9",x"01",x"D0",x"22",x"A9", -- 0x3B40 - x"00",x"AE",x"E3",x"02",x"20",x"90",x"F5",x"A9", -- 0x3B48 - x"01",x"AE",x"E4",x"02",x"20",x"90",x"F5",x"AD", -- 0x3B50 - x"E5",x"02",x"29",x"0F",x"D0",x"04",x"A2",x"10", -- 0x3B58 - x"D0",x"01",x"AA",x"A9",x"08",x"20",x"90",x"F5", -- 0x3B60 - x"60",x"C9",x"02",x"D0",x"22",x"A9",x"02",x"AE", -- 0x3B68 - x"E3",x"02",x"20",x"90",x"F5",x"A9",x"03",x"AE", -- 0x3B70 - x"E4",x"02",x"20",x"90",x"F5",x"AD",x"E5",x"02", -- 0x3B78 - x"29",x"0F",x"D0",x"04",x"A2",x"10",x"D0",x"01", -- 0x3B80 - x"AA",x"A9",x"09",x"20",x"90",x"F5",x"60",x"C9", -- 0x3B88 - x"03",x"D0",x"22",x"A9",x"04",x"AE",x"E3",x"02", -- 0x3B90 - x"20",x"90",x"F5",x"A9",x"05",x"AE",x"E4",x"02", -- 0x3B98 - x"20",x"90",x"F5",x"AD",x"E5",x"02",x"29",x"0F", -- 0x3BA0 - x"D0",x"04",x"A2",x"10",x"D0",x"01",x"AA",x"A9", -- 0x3BA8 - x"0A",x"20",x"90",x"F5",x"60",x"A9",x"06",x"AE", -- 0x3BB0 - x"E3",x"02",x"20",x"90",x"F5",x"AD",x"E1",x"02", -- 0x3BB8 - x"C9",x"04",x"F0",x"93",x"C9",x"05",x"F0",x"B5", -- 0x3BC0 - x"C9",x"06",x"F0",x"D7",x"EE",x"E0",x"02",x"60", -- 0x3BC8 - x"AD",x"E3",x"02",x"0A",x"0A",x"0A",x"0D",x"E1", -- 0x3BD0 - x"02",x"49",x"3F",x"AA",x"A9",x"07",x"20",x"90", -- 0x3BD8 - x"F5",x"18",x"AD",x"E7",x"02",x"0A",x"8D",x"E7", -- 0x3BE0 - x"02",x"AD",x"E8",x"02",x"2A",x"8D",x"E8",x"02", -- 0x3BE8 - x"A9",x"0B",x"AE",x"E7",x"02",x"20",x"90",x"F5", -- 0x3BF0 - x"A9",x"0C",x"AE",x"E8",x"02",x"20",x"90",x"F5", -- 0x3BF8 - x"AD",x"E5",x"02",x"29",x"07",x"A8",x"B9",x"10", -- 0x3C00 - x"FC",x"AA",x"A9",x"0D",x"20",x"90",x"F5",x"60", -- 0x3C08 - x"00",x"00",x"04",x"08",x"0A",x"0B",x"0C",x"0D", -- 0x3C10 - x"A2",x"E1",x"A9",x"04",x"20",x"E4",x"F2",x"B0", -- 0x3C18 - x"39",x"A2",x"E3",x"A9",x"08",x"20",x"F8",x"F2", -- 0x3C20 - x"B0",x"30",x"A2",x"E5",x"A9",x"0D",x"20",x"E4", -- 0x3C28 - x"F2",x"B0",x"27",x"AC",x"E3",x"02",x"AE",x"E5", -- 0x3C30 - x"02",x"BD",x"5E",x"FC",x"8D",x"E4",x"02",x"BD", -- 0x3C38 - x"6B",x"FC",x"8D",x"E3",x"02",x"AD",x"E7",x"02", -- 0x3C40 - x"8D",x"E5",x"02",x"88",x"30",x"09",x"4E",x"E4", -- 0x3C48 - x"02",x"6E",x"E3",x"02",x"4C",x"4B",x"FC",x"4C", -- 0x3C50 - x"40",x"FB",x"EE",x"E0",x"02",x"60",x"00",x"07", -- 0x3C58 - x"07",x"06",x"06",x"05",x"05",x"05",x"04",x"04", -- 0x3C60 - x"04",x"04",x"03",x"00",x"77",x"0B",x"A6",x"47", -- 0x3C68 - x"EC",x"97",x"47",x"FB",x"B3",x"70",x"30",x"F4", -- 0x3C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3C78 - x"08",x"08",x"08",x"08",x"08",x"00",x"08",x"00", -- 0x3C80 - x"14",x"14",x"14",x"00",x"00",x"00",x"00",x"00", -- 0x3C88 - x"14",x"14",x"3E",x"14",x"3E",x"14",x"14",x"00", -- 0x3C90 - x"08",x"1E",x"28",x"1C",x"0A",x"3C",x"08",x"00", -- 0x3C98 - x"30",x"32",x"04",x"08",x"10",x"26",x"06",x"00", -- 0x3CA0 - x"10",x"28",x"28",x"10",x"2A",x"24",x"1A",x"00", -- 0x3CA8 - x"08",x"08",x"08",x"00",x"00",x"00",x"00",x"00", -- 0x3CB0 - x"08",x"10",x"20",x"20",x"20",x"10",x"08",x"00", -- 0x3CB8 - x"08",x"04",x"02",x"02",x"02",x"04",x"08",x"00", -- 0x3CC0 - x"08",x"2A",x"1C",x"08",x"1C",x"2A",x"08",x"00", -- 0x3CC8 - x"00",x"08",x"08",x"3E",x"08",x"08",x"00",x"00", -- 0x3CD0 - x"00",x"00",x"00",x"00",x"00",x"08",x"08",x"10", -- 0x3CD8 - x"00",x"00",x"00",x"3E",x"00",x"00",x"00",x"00", -- 0x3CE0 - x"00",x"00",x"00",x"00",x"00",x"04",x"00",x"00", -- 0x3CE8 - x"00",x"02",x"04",x"08",x"10",x"20",x"00",x"00", -- 0x3CF0 - x"1C",x"22",x"26",x"2A",x"32",x"22",x"1C",x"00", -- 0x3CF8 - x"08",x"18",x"08",x"08",x"08",x"08",x"1C",x"00", -- 0x3D00 - x"1C",x"22",x"02",x"04",x"08",x"10",x"3E",x"00", -- 0x3D08 - x"3E",x"02",x"04",x"0C",x"02",x"22",x"1C",x"00", -- 0x3D10 - x"04",x"0C",x"14",x"24",x"3E",x"04",x"04",x"00", -- 0x3D18 - x"3E",x"20",x"3C",x"02",x"02",x"22",x"1C",x"00", -- 0x3D20 - x"0C",x"10",x"20",x"3C",x"22",x"22",x"1C",x"00", -- 0x3D28 - x"3E",x"02",x"04",x"08",x"10",x"10",x"10",x"00", -- 0x3D30 - x"1C",x"22",x"22",x"1C",x"22",x"22",x"1C",x"00", -- 0x3D38 - x"1C",x"22",x"22",x"1E",x"02",x"04",x"18",x"00", -- 0x3D40 - x"00",x"00",x"08",x"00",x"00",x"08",x"00",x"00", -- 0x3D48 - x"00",x"00",x"08",x"00",x"00",x"08",x"08",x"10", -- 0x3D50 - x"04",x"08",x"10",x"20",x"10",x"08",x"04",x"00", -- 0x3D58 - x"00",x"00",x"3E",x"00",x"3E",x"00",x"00",x"00", -- 0x3D60 - x"10",x"08",x"04",x"02",x"04",x"08",x"10",x"00", -- 0x3D68 - x"1C",x"22",x"04",x"08",x"08",x"00",x"08",x"00", -- 0x3D70 - x"1C",x"22",x"2A",x"2E",x"2C",x"20",x"1E",x"00", -- 0x3D78 - x"08",x"14",x"22",x"22",x"3E",x"22",x"22",x"00", -- 0x3D80 - x"3C",x"22",x"22",x"3C",x"22",x"22",x"3C",x"00", -- 0x3D88 - x"1C",x"22",x"20",x"20",x"20",x"22",x"1C",x"00", -- 0x3D90 - x"3C",x"22",x"22",x"22",x"22",x"22",x"3C",x"00", -- 0x3D98 - x"3E",x"20",x"20",x"3C",x"20",x"20",x"3E",x"00", -- 0x3DA0 - x"3E",x"20",x"20",x"3C",x"20",x"20",x"20",x"00", -- 0x3DA8 - x"1E",x"20",x"20",x"20",x"26",x"22",x"1E",x"00", -- 0x3DB0 - x"22",x"22",x"22",x"3E",x"22",x"22",x"22",x"00", -- 0x3DB8 - x"1C",x"08",x"08",x"08",x"08",x"08",x"1C",x"00", -- 0x3DC0 - x"02",x"02",x"02",x"02",x"02",x"22",x"1C",x"00", -- 0x3DC8 - x"22",x"24",x"28",x"30",x"28",x"24",x"22",x"00", -- 0x3DD0 - x"20",x"20",x"20",x"20",x"20",x"20",x"3E",x"00", -- 0x3DD8 - x"22",x"36",x"2A",x"2A",x"22",x"22",x"22",x"00", -- 0x3DE0 - x"22",x"22",x"32",x"2A",x"26",x"22",x"22",x"00", -- 0x3DE8 - x"1C",x"22",x"22",x"22",x"22",x"22",x"1C",x"00", -- 0x3DF0 - x"3C",x"22",x"22",x"3C",x"20",x"20",x"20",x"00", -- 0x3DF8 - x"1C",x"22",x"22",x"22",x"2A",x"24",x"1A",x"00", -- 0x3E00 - x"3C",x"22",x"22",x"3C",x"28",x"24",x"22",x"00", -- 0x3E08 - x"1C",x"22",x"20",x"1C",x"02",x"22",x"1C",x"00", -- 0x3E10 - x"3E",x"08",x"08",x"08",x"08",x"08",x"08",x"00", -- 0x3E18 - x"22",x"22",x"22",x"22",x"22",x"22",x"1C",x"00", -- 0x3E20 - x"22",x"22",x"22",x"22",x"22",x"14",x"08",x"00", -- 0x3E28 - x"22",x"22",x"22",x"2A",x"2A",x"36",x"22",x"00", -- 0x3E30 - x"22",x"22",x"14",x"08",x"14",x"22",x"22",x"00", -- 0x3E38 - x"22",x"22",x"14",x"08",x"08",x"08",x"08",x"00", -- 0x3E40 - x"3E",x"02",x"04",x"08",x"10",x"20",x"3E",x"00", -- 0x3E48 - x"1E",x"10",x"10",x"10",x"10",x"10",x"1E",x"00", -- 0x3E50 - x"00",x"20",x"10",x"08",x"04",x"02",x"00",x"00", -- 0x3E58 - x"3C",x"04",x"04",x"04",x"04",x"04",x"3C",x"00", -- 0x3E60 - x"08",x"14",x"2A",x"08",x"08",x"08",x"08",x"00", -- 0x3E68 - x"0E",x"10",x"10",x"10",x"3C",x"10",x"3E",x"00", -- 0x3E70 - x"0C",x"12",x"2D",x"29",x"29",x"2D",x"12",x"0C", -- 0x3E78 - x"00",x"00",x"1C",x"02",x"1E",x"22",x"1E",x"00", -- 0x3E80 - x"20",x"20",x"3C",x"22",x"22",x"22",x"3C",x"00", -- 0x3E88 - x"00",x"00",x"1E",x"20",x"20",x"20",x"1E",x"00", -- 0x3E90 - x"02",x"02",x"1E",x"22",x"22",x"22",x"1E",x"00", -- 0x3E98 - x"00",x"00",x"1C",x"22",x"3E",x"20",x"1E",x"00", -- 0x3EA0 - x"0C",x"12",x"10",x"3C",x"10",x"10",x"10",x"00", -- 0x3EA8 - x"00",x"00",x"1C",x"22",x"22",x"1E",x"02",x"1C", -- 0x3EB0 - x"20",x"20",x"3C",x"22",x"22",x"22",x"22",x"00", -- 0x3EB8 - x"08",x"00",x"18",x"08",x"08",x"08",x"1C",x"00", -- 0x3EC0 - x"04",x"00",x"0C",x"04",x"04",x"04",x"24",x"18", -- 0x3EC8 - x"20",x"20",x"22",x"24",x"38",x"24",x"22",x"00", -- 0x3ED0 - x"18",x"08",x"08",x"08",x"08",x"08",x"1C",x"00", -- 0x3ED8 - x"00",x"00",x"36",x"2A",x"2A",x"2A",x"22",x"00", -- 0x3EE0 - x"00",x"00",x"3C",x"22",x"22",x"22",x"22",x"00", -- 0x3EE8 - x"00",x"00",x"1C",x"22",x"22",x"22",x"1C",x"00", -- 0x3EF0 - x"00",x"00",x"3C",x"22",x"22",x"3C",x"20",x"20", -- 0x3EF8 - x"00",x"00",x"1E",x"22",x"22",x"1E",x"02",x"02", -- 0x3F00 - x"00",x"00",x"2E",x"30",x"20",x"20",x"20",x"00", -- 0x3F08 - x"00",x"00",x"1E",x"20",x"1C",x"02",x"3C",x"00", -- 0x3F10 - x"10",x"10",x"3C",x"10",x"10",x"12",x"0C",x"00", -- 0x3F18 - x"00",x"00",x"22",x"22",x"22",x"26",x"1A",x"00", -- 0x3F20 - x"00",x"00",x"22",x"22",x"22",x"14",x"08",x"00", -- 0x3F28 - x"00",x"00",x"22",x"22",x"2A",x"2A",x"36",x"00", -- 0x3F30 - x"00",x"00",x"22",x"14",x"08",x"14",x"22",x"00", -- 0x3F38 - x"00",x"00",x"22",x"22",x"22",x"1E",x"02",x"1C", -- 0x3F40 - x"00",x"00",x"3E",x"04",x"08",x"10",x"3E",x"00", -- 0x3F48 - x"0E",x"18",x"18",x"30",x"18",x"18",x"0E",x"00", -- 0x3F50 - x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x3F58 - x"38",x"0C",x"0C",x"06",x"0C",x"0C",x"38",x"00", -- 0x3F60 - x"2A",x"15",x"2A",x"15",x"2A",x"15",x"2A",x"15", -- 0x3F68 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x3F70 - x"37",x"EA",x"ED",x"EB",x"20",x"F5",x"F9",x"38", -- 0x3F78 - x"EE",x"F4",x"36",x"39",x"2C",x"E9",x"E8",x"EC", -- 0x3F80 - x"35",x"F2",x"E2",x"3B",x"2E",x"EF",x"E7",x"30", -- 0x3F88 - x"F6",x"E6",x"34",x"2D",x"0B",x"F0",x"E5",x"2F", -- 0x3F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3F98 - x"31",x"1B",x"FA",x"00",x"08",x"7F",x"E1",x"0D", -- 0x3FA0 - x"F8",x"F1",x"32",x"5C",x"0A",x"5D",x"F3",x"00", -- 0x3FA8 - x"33",x"E4",x"E3",x"27",x"09",x"5B",x"F7",x"3D", -- 0x3FB0 - x"26",x"4A",x"4D",x"4B",x"20",x"55",x"59",x"2A", -- 0x3FB8 - x"4E",x"54",x"5E",x"28",x"3C",x"49",x"48",x"4C", -- 0x3FC0 - x"25",x"52",x"42",x"3A",x"3E",x"4F",x"47",x"29", -- 0x3FC8 - x"56",x"46",x"24",x"5F",x"0B",x"50",x"45",x"3F", -- 0x3FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x3FD8 - x"21",x"1B",x"5A",x"00",x"08",x"7F",x"41",x"0D", -- 0x3FE0 - x"58",x"51",x"40",x"7C",x"0A",x"7D",x"53",x"00", -- 0x3FE8 - x"23",x"44",x"43",x"22",x"09",x"7B",x"57",x"2B", -- 0x3FF0 - x"D0",x"01",x"47",x"02",x"8F",x"F8",x"44",x"02" -- 0x3FF8 - ); - -begin - - p_rom : process(CLK) -begin - if (rising_edge(CLK)) then - DATA <= ROM(to_integer(unsigned(ADDR))); - end if; - end process; -end RTL; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/roms/basic11b.hex b/Computer_MiST/Oric Atmos_MiST/rtl/roms/basic11b.hex deleted file mode 100644 index 832d8832..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/roms/basic11b.hex +++ /dev/null @@ -1,1026 +0,0 @@ -:020000020000FC -:100000004CCCEC4C71C472C991C686E9D0E915CDCF -:1000100018CD11CA50DAA0DADDD966D984DAA0DAAF -:1000200054C8FCC708C897CE3BCA54CD7DD1CDCCAF -:1000300088CD1BCBE4C9BCC96FCA51C9C7C911CA95 -:1000400098CACDEBE6EB0BEC20EC32ECB4FACAFA32 -:10005000E0FA9EFAFBEAFBEAFBEAEFEAEFEAEFEAF4 -:10006000EFEAEFEAEFEAEFEAFBEAFBEA70C9C1CA9E -:1000700057D95AE808E9B9D44ED9AACB9FC947C77E -:100080000CC745CD45E912CDEDC621DFBDDF49DF07 -:1000900021007ED4A6D4B5D9FB022EE24FE3AFDC1B -:1000A000AAE28BE392E3DBE33FE438D983D9D4DDE2 -:1000B000A6D893D5D7D8B5D816D877DE0FDF0BDF03 -:1000C000DADA3FDA45EC2AD856D861D87924DB79D8 -:1000D0000DDB7BEFDC7BE6DD7F37E250E5D046E2EF -:1000E000D07D70E25A3BD06412D1454EC44544499C -:1000F000D453544F52C5524543414CCC54524FCE29 -:1001000054524F46C6504FD0504C4FD450554CCC03 -:100110004C4F5245D3444F4BC55245504541D455A1 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-:103F2000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA1 -:103F3000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF91 -:103F4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF81 -:103F5000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF71 -:103F6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF61 -:103F7000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF51 -:103F8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF41 -:103F9000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF31 -:103FA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF21 -:103FB000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF11 -:103FC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF01 -:103FD000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1 -:103FE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE1 -:103FF000FFFFFFFFFFFFFFFFFFFF28C055C02BC0E3 -:00000001FF diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/scan_converter.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/scan_converter.vhd deleted file mode 100644 index f3925b3b..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/scan_converter.vhd +++ /dev/null @@ -1,229 +0,0 @@ --- (c) 2012 d18c7db(a)hotmail --- --- This program is free software; you can redistribute it and/or modify it under --- the terms of the GNU General Public License version 3 or, at your option, --- any later version as published by the Free Software Foundation. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. --- --- For full details, see the GNU General Public License at www.gnu.org/licenses - --------------------------------------------------------------------------------- --- Video scan converter --- --- Horizonal Timing --- _____________ ______________________ _____________________ --- VIDEO (last) |____________| VIDEO |____________| VIDEO (next) --- -hD----------|-hA-|hB|-hC-|----------hD----------|-hA-|hB|-hC-|----------hD--------- --- __________________| |________________________________| |__________________________ --- HSYNC |__| HSYNC |__| HSYNC - --- Vertical Timing --- _____________ ______________________ _____________________ --- VIDEO (last)||____________||||||||||VIDEO|||||||||____________||||||||||VIDEO (next) --- -vD----------|-vA-|vB|-vC-|----------vD----------|-vA-|vB|-vC-|----------vD--------- --- __________________| |________________________________| |__________________________ --- VSYNC |__| VSYNC |__| VSYNC - --- Scan converter input and output timings compared to standard VGA --- Resolution - Frame | Pixel | Front | HSYNC | Back | Active | HSYNC | Front | VSYNC | Back | Active | VSYNC --- - Rate | Clock | Porch hA | Pulse hB | Porch hC | Video hD | Polarity | Porch vA | Pulse vB | Porch vC | Video vD | Polarity -------------------------------------------------------------------------------------------------------------------------------------------------------------- --- In 256x224 - 59.18Hz | 6.000 MHz | 38 pixels | 32 pixels | 58 pixels | 256 pixels | negative | 16 lines | 8 lines | 16 lines | 224 lines | negative --- Out 640x480 - 59.18Hz | 24.000 MHz | 2 pixels | 92 pixels | 34 pixels | 640 pixels | negative | 17 lines | 2 lines | 29 lines | 480 lines | negative --- VGA 640x480 - 59.94Hz | 25.175 MHz | 16 pixels | 96 pixels | 48 pixels | 640 pixels | negative | 10 lines | 2 lines | 33 lines | 480 lines | negative - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - ---pragma translate_off - use ieee.std_logic_textio.all; - use std.textio.all; ---pragma translate_on - -entity VGA_SCANCONV is - generic ( - cstart : integer range 0 to 1023 := 144; -- composite sync start - clength : integer range 0 to 1023 := 640; -- composite sync length - - hA : integer range 0 to 1023 := 16; -- h front porch - hB : integer range 0 to 1023 := 96; -- h sync - hC : integer range 0 to 1023 := 48; -- h back porch - hD : integer range 0 to 1023 := 640; -- visible video - --- vA : integer range 0 to 1023 := 16; -- v front porch - vB : integer range 0 to 1023 := 2; -- v sync - vC : integer range 0 to 1023 := 33; -- v back porch - vD : integer range 0 to 1023 := 480; -- visible video - - hpad : integer range 0 to 1023 := 0; -- H black border - vpad : integer range 0 to 1023 := 0 -- V black border - ); - port ( - I_VIDEO : in std_logic_vector(15 downto 0); - I_HSYNC : in std_logic; - I_VSYNC : in std_logic; - -- - O_VIDEO : out std_logic_vector(15 downto 0); - O_HSYNC : out std_logic; - O_VSYNC : out std_logic; - O_CMPBLK_N : out std_logic; - -- - CLK : in std_logic; - CLK_x2 : in std_logic - ); -end; - -architecture RTL of VGA_SCANCONV is - -- - -- input timing - -- - signal ivsync_last_x2 : std_logic := '1'; - signal ihsync_last : std_logic := '1'; - signal hpos_i : std_logic_vector( 9 downto 0) := (others => '0'); - - -- - -- output timing - -- - signal hpos_o : std_logic_vector(9 downto 0) := (others => '0'); - - signal vcnt : integer range 0 to 1023 := 0; - signal hcnt : integer range 0 to 1023 := 0; - signal hcnti : integer range 0 to 1023 := 0; - - signal CLK_x2_n : std_logic := '1'; - -begin - -- dual port line buffer, max line of 1024 pixels - u_ram : entity work.RAMB16_S18_S18 --- generic map (INIT_A => X"00000", INIT_B => X"00000", SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" - port map ( - -- input - q_a => open, - data_a => I_VIDEO, - - - address_a => hpos_i, - wren_a => '1', - rden_a => CLK, - - clock_a => CLK_x2, - - -- output - q_b => O_VIDEO, - data_b => x"0000", - - - address_b => hpos_o, - wren_b => '0', - rden_b => '1', - - clock_b => CLK_x2_n - ); - - CLK_x2_n <= not CLK_x2; - - -- horizontal counter for input video - p_hcounter : process - begin - wait until rising_edge(CLK_x2); - if CLK = '0' then - ihsync_last <= I_HSYNC; - - -- trigger off rising hsync - if I_HSYNC = '1' and ihsync_last = '0' then - hcnti <= 0; - else - hcnti <= hcnti + 1; - end if; - end if; - end process; - - -- increment write position during active video - p_ram_in : process - begin - wait until rising_edge(CLK_x2); - if CLK = '0' then - if (hcnti < cstart) or (hcnti >= (cstart + clength)) then - hpos_i <= (others => '0'); - else - hpos_i <= hpos_i + 1; - end if; - end if; - end process; - - -- VGA H and V counters, synchronized to input frame V sync, then H sync - p_out_ctrs : process - variable trigger : boolean; - begin - wait until rising_edge(CLK_x2); - ivsync_last_x2 <= I_VSYNC; - - if (I_VSYNC = '0') and (ivsync_last_x2 = '1') then - trigger := true; - elsif trigger and I_HSYNC = '0' then - trigger := false; - hcnt <= 0; - vcnt <= 0; - else - hcnt <= hcnt + 1; - if hcnt = (hA+hB+hC+hD+hpad+hpad-1) then - hcnt <= 0; - vcnt <= vcnt + 1; - end if; - end if; - end process; - - -- generate hsync - p_gen_hsync : process - begin - wait until rising_edge(CLK_x2); - -- H sync timing - if (hcnt < hB) then - O_HSYNC <= '0'; - else - O_HSYNC <= '1'; - end if; - end process; - - -- generate vsync - p_gen_vsync : process - begin - wait until rising_edge(CLK_x2); - -- V sync timing - if (vcnt < vB) then - O_VSYNC <= '0'; - else - O_VSYNC <= '1'; - end if; - end process; - - -- generate active output video - p_gen_active_vid : process - begin - wait until rising_edge(CLK_x2); - -- visible video area doubled from the original game - if ((hcnt >= (hB + hC + hpad)) and (hcnt < (hB + hC + hD + hpad))) and ((vcnt > 2*(vB + vC + vpad)) and (vcnt <= 2*(vB + vC + vD + vpad))) then - hpos_o <= hpos_o + 1; - else - hpos_o <= (others => '0'); - end if; - end process; - - -- generate blanking signal including additional borders to pad the input signal to standard VGA resolution - p_gen_blank : process - begin - wait until rising_edge(CLK_X2); - -- active video area 640x480 (VGA) after padding with blank borders - if ((hcnt >= (hB + hC)) and (hcnt < (hB + hC + hD + 2*hpad))) and ((vcnt > 2*(vB + vC)) and (vcnt <= 2*(vB + vC + vD + 2*vpad))) then - O_CMPBLK_N <= '1'; - else - O_CMPBLK_N <= '0'; - end if; - end process; - -end architecture RTL; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/scandoubler.v b/Computer_MiST/Oric Atmos_MiST/rtl/scandoubler.v deleted file mode 100644 index 0213d20c..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,195 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/spram.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/spram.vhd deleted file mode 100644 index d9a003ee..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/spram.vhd +++ /dev/null @@ -1,89 +0,0 @@ -------------------------------------------------------------------------------- --- --- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- --- --- Generic single port RAM. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity spram is - generic ( - addr_width_g : integer := 14; - data_width_g : integer := 8 - ); - port ( - clk_i : in std_logic; - we_i : in std_logic; - addr_i : in std_logic_vector(addr_width_g-1 downto 0); - data_i : in std_logic_vector(data_width_g-1 downto 0); - data_o : out std_logic_vector(data_width_g-1 downto 0) - ); - -end spram; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of spram is - - type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); - signal ram_q : ram_t - -- pragma translate_off - := (others => (others => '0')) - -- pragma translate_on - ; - signal read_addr_q : unsigned(addr_width_g-1 downto 0); - -begin - - process (clk_i) - begin - if rising_edge(clk_i) then - if we_i = '1' then - ram_q(to_integer(unsigned(addr_i))) <= data_i; - end if; - - read_addr_q <= unsigned(addr_i); - end if; - end process; - - data_o <= ram_q(to_integer(read_addr_q)); - -end rtl; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/sprom.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/sprom.vhd deleted file mode 100644 index 06d78cbd..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,77 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - numwords_a : natural := 0; -- not used any more - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - COMPONENT altsyncram - GENERIC ( - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - -END SYN; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/tone_generator.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/tone_generator.vhd deleted file mode 100644 index b21ff828..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/tone_generator.vhd +++ /dev/null @@ -1,59 +0,0 @@ --- --- TONE_GENERATOR.vhd --- --- Generator a tone. --- --- Copyright (C)2001 SEILEBOST --- All rights reserved. --- --- $Id: TONE_GENERATOR.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $ --- --- Question : if WR is set To add one to count ? - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity TONE_GENERATOR is - Port ( CLK : in std_logic; - RST : in std_logic; - WR : in std_logic; - CS_COARSE : in std_logic; - CS_FINE : in std_logic; - DATA_COARSE : in std_logic_vector(7 downto 0); - DATA_FINE : in std_logic_vector(7 downto 0); - OUT_TONE : inout std_logic ); -end TONE_GENERATOR; - -architecture Behavioral of TONE_GENERATOR is - -SIGNAL COUNT : std_logic_vector(15 downto 0); - -begin - - PROCESS(CLK, RST,CS_COARSE, CS_FINE) - BEGIN - if (RST = '1') then - COUNT <= "0000000000000000"; - OUT_TONE <= '0'; - elsif (CLK'event and CLK = '1') then - if (WR = '1') then - if (CS_FINE = '1') then - COUNT(7 downto 0) <= DATA_FINE; - elsif (CS_COARSE = '1') then - COUNT(15 downto 8) <= DATA_COARSE; - end if; - else - if (COUNT = "0000000000000000") then - COUNT(15 downto 8) <= DATA_COARSE; - COUNT(7 downto 0) <= DATA_FINE; - OUT_TONE <= NOT OUT_TONE; - else - COUNT <= COUNT - 1; - end if; - end if; - end if; - end process; - -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/ula.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/ula.vhd deleted file mode 100644 index a9f40015..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/ula.vhd +++ /dev/null @@ -1,525 +0,0 @@ --- --- A simulation model of ULA --- Copyright (c) seilebost - 2001 - 2009 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email seilebost@free.fr --- --- --- --- --- 2013 Significant rewrite by d18c7db(a)hotmail --- --- Combined all ULA submodules into one file --- Elliminated gated clocks --- Overall simplified and streamlined RTL --- Reduced number of synthesis warnings --- Fixed attribute decoding --- Fixed phase1/phase2 address generation --- Changes in timing signal generation --- Fixed attributes not alligned to characters on screen --- Implemented 50/60Hz attribute - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - --- ULA pinout --- 1 MUX U RAM_D1 40 --- 2 RAM_D2 RAM_D0 39 --- 3 RAM_D3 RAM_D7 38 --- 4 RAM_D4 RAM_D5 37 --- 5 D5 RAM_D6 36 --- 6 GND A12 35 --- 7 CLK D6 34 --- 8 D0 A09 33 --- 9 CAS A08 32 --- 10 RAS A10 31 --- 11 D2 A15 30 --- 12 D3 A14 29 --- 13 D4 RAM_R/W 28 --- 14 PHI R/W 27 --- 15 A11 MAP 26 --- 16 SYNC I/O 25 --- 17 D1 Vcc 24 --- 18 D7 ROM_CS 23 --- 19 BLU A13 22 --- 20 GRN RED 21 - -entity ula is -port ( - RESETn : in std_logic; -- RESET master - CLK_4 : out std_logic; -- 4 MHz internal - - CLK : in std_logic; -- 24 MHz -- pin 07 - PHI2 : out std_logic; -- 1 MHz CPU & system -- pin 14 - RW : in std_logic; -- R/W from CPU -- pin 27 - MAPn : in std_logic; -- MAP -- pin 26 - DB : in std_logic_vector( 7 downto 0); -- DATA BUS -- pin 18,34,5,13,12,11,17,8 - ADDR : in std_logic_vector(15 downto 0); -- ADDRESS BUS -- pin 30,29,22,35,15,31,33,32, A7,A6,A5,A4,A3,A2,A1,A0 - - -- SRAM - CSRAMn : out std_logic; - SRAM_AD : out std_logic_vector(15 downto 0); - SRAM_OE : out std_logic; - SRAM_CE : out std_logic; - SRAM_WE : out std_logic; - LATCH_SRAM : out std_logic; - - -- DRAM --- AD_RAM : out std_logic_vector( 7 downto 0); -- ADDRESS BUS for dynamic ram -- pin 38,36,37,4,3,2,40,39 --- RASn : out std_logic; -- RAS for dynamic ram -- pin 10 --- CASn : out std_logic; -- CAS for dynamic ram -- pin 09 --- MUX : out std_logic; -- MUX selector -- pin 01 --- RW_RAM : out std_logic; -- Read/Write for dynamic ram -- pin 28 - - CSIOn : out std_logic; -- Chip select IO (VIA) -- pin 25 - CSROMn : out std_logic; -- ROM select -- pin 23 - R : out std_logic; -- Red -- pin 21 - G : out std_logic; -- Green -- pin 20 - B : out std_logic; -- Blue -- pin 19 - SYNC : out std_logic; -- Synchronisation -- pin 16 - -- VCC -- pin 24 - -- GND -- pin 06 - HSYNC : out std_logic; - VSYNC : out std_logic -); -end; - -architecture RTL of ula is - - -- Signal CLOCK - signal CLK_24 : std_logic; -- CLOCK 24 MHz internal - signal CLK_4_INT : std_logic; -- CLOCK 4 MHz internal - signal CLK_1_INT : std_logic; -- CLOCK 1 MHz internal - signal CLK_PIXEL_INT : std_logic; -- CLOCK PIXEL internal - signal CLK_FLASH : std_logic; -- CLOCK FLASH external - - -- Data Bus Internal - signal DB_INT : std_logic_vector( 7 downto 0); - - -- Manage memory access - signal VAP1 : std_logic_vector(15 downto 0); -- VIDEO ADDRESS PHASE 1 - signal VAP2 : std_logic_vector(15 downto 0); -- VIDEO ADDRESS PHASE 2 - signal lADDR : std_logic_vector(15 downto 0); -- BUS ADDRESS PROCESSOR - signal RW_INT : std_logic; -- Read/Write INTERNAL FROM CPU - - -- local signal - signal lHIRES_SEL : std_logic; -- TXT/HIRES SELECT - signal HIRES_DEC : std_logic; -- TXT/HIRES DECODE - signal lDBLHGT_SEL : std_logic; -- Double Height SELECT - signal lALT_SEL : std_logic; -- Character set select - signal lFORCETXT : std_logic; -- Force text mode - signal isAttrib : std_logic; -- Attrib - signal ATTRIB_DEC : std_logic; -- Attrib decode --- signal LD_REG_0 : std_logic; -- Load zero into video register - signal RELD_REG : std_logic; -- Reload from register to shift - signal DATABUS_EN : std_logic; -- Data bus enable - signal lCOMPSYNC : std_logic; -- Composite Synchronization for video - signal lHSYNCn : std_logic; -- Horizontal Synchronization for video - signal lVSYNC50n : std_logic; -- Vertical Synchronization for 50Hz video - signal lVSYNC60n : std_logic; -- Vertical Synchronization for 60Hz video - signal lVSYNCn : std_logic; -- Vertical Synchronization for video - signal BLANKINGn : std_logic; -- Blanking signal - signal lRELOAD_SEL : std_logic; -- reload register SELECT - signal lFREQ_SEL : std_logic; -- Frequency video SELECT (50 or 60 Hz) - signal LDFROMBUS : std_logic; -- Load from Bus Data - signal CHROWCNT : std_logic_vector( 2 downto 0); -- ch?? row count - signal lCTR_H : std_logic_vector( 6 downto 0); -- Horizontal counter - signal lCTR_V : std_logic_vector( 8 downto 0); -- Vertical counter - - signal rgb_int : std_logic_vector( 2 downto 0); -- Red Green Blue video signal - - -- local select RAM, IO & ROM - signal CSRAMn_INT : std_logic; -- RAM Chip Select - signal CSIOn_INT : std_logic; -- Input/Output Chip Select - signal CSROMn_INT : std_logic; -- ROM Chip select - - -- Bus Address internal - signal AD_RAM_INT : std_logic_vector(15 downto 0); -- RAM ADDRESS BUS - - -- RESET internal - signal RESET_INT : std_logic; - - -- MAP internal - signal lMAPn : std_logic; - - signal DBLHGT_EN : std_logic; -- ENABLE DOUBLE HEIGHT - signal CTR_V_DIV8 : std_logic_vector( 8 downto 0); -- VERTICAL COUNTER DIVIDE OR NOT BY 8 - signal voffset : std_logic_vector(15 downto 0); -- OFFSET SCREEN - signal mulBy40 : std_logic_vector(14 downto 0); -- Used to mult by 40 - - signal c : std_logic_vector(23 downto 0); -- states - signal ph : std_logic_vector( 2 downto 0); -- phases - - signal lCTR_FLASH : std_logic_vector( 4 downto 0); - signal lVBLANKn : std_logic; - signal lHBLANKn : std_logic; - - signal lDATABUS : std_logic_vector( 7 downto 0); - signal lSHFREG : std_logic_vector( 5 downto 0); - signal lREGHOLD : std_logic_vector( 6 downto 0); - signal lRGB : std_logic_vector( 2 downto 0); - signal lREG_INK : std_logic_vector( 2 downto 0); - signal lREG_STYLE : std_logic_vector( 2 downto 0); - signal lREG_PAPER : std_logic_vector( 2 downto 0); - signal lREG_MODE : std_logic_vector( 2 downto 0); - signal ModeStyle : std_logic_vector( 1 downto 0); - signal lADD : std_logic_vector( 5 downto 0); - signal lInv : std_logic; -- inverse signal - signal lInv_hold : std_logic; -- inverse signal hold - signal lBGFG_SEL : std_logic; - signal lFLASH_SEL : std_logic; - -begin - - -- input assignments - lADDR <= ADDR; - DB_INT <= DB; - CLK_24 <= CLK; - RESET_INT <= not RESETn; - lMAPn <= MAPn; - RW_INT <= RW; - - -- output assignments - PHI2 <= CLK_1_INT; --- AD_RAM <= AD_RAM_INT(15 downto 8); - CSIOn <= CSIOn_INT; - CSROMn <= CSROMn_INT; - CSRAMn <= CSRAMn_INT; - CLK_4 <= CLK_4_INT; - - ------------------ - -- SRAM signals -- - ------------------ - SRAM_AD <= AD_RAM_INT; - LATCH_SRAM <= not c(4) and not c(12) and not c(20); - - -- phase 1 phase 2 phase 3 - SRAM_OE <= ph(0) or ph(1) or RW_INT ; - SRAM_CE <= ph(0) or ph(1) or (ph(2) and (not CSRAMn_INT) ); - - SRAM_WE <= (not CSRAMn_INT) and (not RW_INT) and c(17) ; - - -- VIDEO OUT - R <= RGB_INT(0); - G <= RGB_INT(1); - B <= RGB_INT(2); - SYNC <= lCOMPSYNC; - HSYNC <= lHSYNCn; - VSYNC <= lVSYNCn; - - ---------------------- - ---------------------- - -- Address Decoding -- - ---------------------- - ---------------------- - - -- PAGE 3 I/O decoder : 0x300-0x3FF - CSIOn_INT <= '0' when (lADDR(15 downto 8) = x"03") and (CLK_1_INT = '1') else '1'; - - -- PAGE ROM : 0xC000-0xFFFF - CSROMn_INT <= '0' when (lADDR(15 downto 14) = "11" and lMAPn = '1' and CLK_1_INT = '1') else '1'; - - CSRAMn_INT <= '0' when -- shadow RAM section - (lADDR(15 downto 14) = "11" and lMAPn = '0' and CLK_1_INT = '1') - or - -- normal RAM section - (((lADDR(15 downto 8) /= x"03") and (lADDR(15 downto 14) /= "11")) and lMAPn = '1' and CLK_1_INT = '1') - else '1'; - - ---------------------------------------------- - ---------------------------------------------- - -- Control signal generation and sequencing -- - ---------------------------------------------- - ---------------------------------------------- - - -- state and phase shifter - U_TB_CPT: process (CLK_24, RESET_INT) - begin - if (RESET_INT = '1') then - c <= "000000000000000000000001"; - ph <= "001"; - elsif falling_edge(CLK_24) then - -- advance states - c <= c(22 downto 0) & c(23); - if (c(7) or c(15) or c(23)) = '1' then - -- advance phases - ph <= ph(1 downto 0) & ph(2); - end if; - end if; - end process; - - ---------------------- - -- Clock generation -- - ---------------------- - - -- CPU clock -- - CLK_1_INT <= ph(2); - - -- VIA 6522 clock - CLK_4_INT <= c(0) or c(1) or c(2) or c(6) or c(7) or c(8) or c(12) or c(13) or c(14) or c(18) or c(19) or c(20); - --- LD_REG_0 <= isAttrib and c(5); - - CLK_PIXEL_INT <= c(1) or c(5) or c(9) or c(13) or c(17) or c(21); - ATTRIB_DEC <= c(3); - RELD_REG <= c(17); - DATABUS_EN <= c(2) or c(10); - LDFROMBUS <= ((not isAttrib) and c(12) and (not HIRES_DEC)) or ((not isAttrib) and c(5) and HIRES_DEC) or (isAttrib and c(9)); - - ------------------------------------- - ------------------------------------- - -- Video timing signals generation -- - ------------------------------------- - ------------------------------------- - - -- Horizontal Counter - u_CPT_H: process(CLK_1_INT, RESET_INT) - begin - if (RESET_INT = '1') then - lCTR_H <= (others => '0'); - elsif rising_edge(CLK_1_INT) then - if lCTR_H < 63 then - lCTR_H <= lCTR_H + 1; - else - lCTR_H <= (others => '0'); - end if; - end if; - end process; - - -- Vertical Counter - u_CPT_V: process(CLK_1_INT, RESET_INT) - begin - if (RESET_INT = '1') then - lCTR_V <= (others => '0'); - lCTR_FLASH <= (others => '0'); - elsif rising_edge(CLK_1_INT) then - if (lCTR_H = 63) then - -- 50Hz = 312 lines, 60Hz = 260 lines - if ((lCTR_V < 312) and lFREQ_SEL='1') or - ((lCTR_V < 260) and lFREQ_SEL='0') then - lCTR_V <= lCTR_V + 1; - else - lCTR_V <= (others => '0'); - -- increment flash counter every frame - lCTR_FLASH <= lCTR_FLASH + 1; - end if; - end if; - end if; - end process; - - - - -- Horizontal Synchronisation - lHSYNCn <= '0' when (lCTR_H >= 49) and (lCTR_H <= 53) else '1'; - - -- Horizontal Blank - lHBLANKn <= '1' when (lCTR_H >= 1) and (lCTR_H <= 40) else '0'; - - -- Signal to Reload Register to reset attributes - lRELOAD_SEL <= '1' when (lCTR_H >= 49) else '0'; - - -- Vertical Synchronisation - lVSYNC50n <= '0' when (lCTR_V >= 258) and (lCTR_V <= 259) else '1'; -- 50Hz - lVSYNC60n <= '0' when (lCTR_V >= 241) and (lCTR_V <= 242) else '1'; -- 60Hz - lVSYNCn <= lVSYNC50n when lFREQ_SEL='1' else lVSYNC60n; - - -- Vertical Blank - lVBLANKn <= '0' when (lCTR_V >= 224) else '1'; - - -- Signal To Force TEXT MODE - lFORCETXT <= '1' when (lCTR_V > 199) else '0'; - - -- Assign output signals - CLK_FLASH <= lCTR_FLASH(4); -- Flash clock toggles every 16 video frames - lCOMPSYNC <= not (lHSYNCn xor lVSYNCn); - BLANKINGn <= lVBLANKn and lHBLANKn; - - - - ----------------------------- - ----------------------------- - -- Video attribute decoder -- - ----------------------------- - ----------------------------- - - -- Latch data from Data Bus - u_data_bus: process - begin - wait until rising_edge(CLK_24); - if (DATABUS_EN = '1') then - lDATABUS <= DB_INT; - end if; - end process; - - u_isattrib : process(CLK_24, RESET_INT) - begin - if (RESET_INT = '1') then - IsATTRIB <= '0'; - lInv_hold <= '0'; - elsif rising_edge(CLK_24) then - if ATTRIB_DEC = '1' then - IsATTRIB <= not (DB_INT(6) or DB_INT(5)); -- 1 = attribute, 0 = not an attribute - lInv_hold <= DB_INT(7); - end if; - end if; - end process; - - u_lInv_hold : process - begin - wait until rising_edge(CLK_24); - if (CLK_PIXEL_INT = '1' and RELD_REG = '1') then - lInv <= lInv_hold; - end if; - end process; - - -- hold data bus value - u_hold_reg: process(CLK_24, RESET_INT) - begin - if (RESET_INT = '1') then - lREGHOLD <= (others => '0'); - elsif rising_edge(CLK_24) then - if LDFROMBUS = '1' then - lREGHOLD <= lDATABUS(6 downto 0); - end if; - end if; - end process; - - u_ld_reg: process(CLK_24, lRELOAD_SEL, RESET_INT) - begin - if (RESET_INT = '1') then - lREG_INK <= (others=>'1'); - lREG_STYLE <= (others=>'0'); - lREG_PAPER <= (others=>'0'); - lREG_MODE <= (others=>'0'); - elsif (lRELOAD_SEL = '1') then - lREG_INK <= (others=>'1'); - lREG_STYLE <= (others=>'0'); - lREG_PAPER <= (others=>'0'); - elsif rising_edge(CLK_24) then - if (RELD_REG = '1' and isAttrib = '1') then - case lREGHOLD(6 downto 3) is - when "0000" => lREG_INK <= lREGHOLD(2 downto 0); - when "0001" => lREG_STYLE <= lREGHOLD(2 downto 0); - when "0010" => lREG_PAPER <= lREGHOLD(2 downto 0); - when "0011" => lREG_MODE <= lREGHOLD(2 downto 0); - when others => null; - end case; - end if; - end if; - end process; - - -- selector bits in mode/style registers - lALT_SEL <= lREG_STYLE(0); -- Character set select : 0=Standard 1=Alternate - lDBLHGT_SEL <= lREG_STYLE(1); -- Character type select: 0=Standard 1=Double - lFLASH_SEL <= lREG_STYLE(2); -- Flash select : 0=Steady 1=Flashing - lFREQ_SEL <= lREG_MODE(1); -- Frequency select : 0=60Hz 1=50Hz - lHIRES_SEL <= lREG_MODE(2); -- Mode Select : 0=Text 1=Hires - - -- Output signal for text/hires mode decode - HIRES_DEC <= (lHIRES_SEL and (not lFORCETXT)); - DBLHGT_EN <= (lDBLHGT_SEL and (not HIRES_DEC)); - - -- shift video data - u_shf_reg: process - begin - wait until rising_edge(CLK_24); - if CLK_PIXEL_INT = '1' then - -- Load shifter before the rising edge of PHI2 - if (RELD_REG = '1' and isAttrib = '0') then - lSHFREG <= lREGHOLD(5 downto 0); - else - -- send 6 bits - lSHFREG <= lSHFREG(4 downto 0) & '0'; - end if; - end if; - end process; - - lBGFG_SEL <= '0' when ( (CLK_FLASH = '1') and (lFLASH_SEL = '1') ) else lSHFREG(5); - - -- local assign for R(ed)G(reen)B(lue) signal - lRGB <= lREG_INK when lBGFG_SEL = '1' else lREG_PAPER; - - -- Assign out signal - RGB_INT <= lRGB when (lInv = '0' and BLANKINGn = '1') else - not(lRGB) when (lInv = '1' and BLANKINGn = '1') else - (others=>'0'); - - -- Compute offset - ModeStyle <= lHIRES_SEL & lALT_SEL; - with ModeStyle select - lADD <= "100111" when "11", -- HIRES & ALT x9Cxx - "100110" when "10", -- HIRES & STD x98xx - "101110" when "01", -- TEXT & ALT xB8xx - "101101" when others; -- TEXT & STD xB4xx - - ----------------------------- - ----------------------------- - -- Video address generator -- - ----------------------------- - ----------------------------- - - -- divide by 8 in LORES - CTR_V_DIV8 <= lCTR_V when (HIRES_DEC = '1') else "000" & lCTR_V(8 downto 3) ; - - -- to multiply by 40 without using a multiplier we just sum the results of the operations of - -- multiply by 32 by shifting 5 bits and multiply by 8 by shifting 3 bits - mulBy40 <= ("0" & CTR_V_DIV8 & "00000") + ("000" & CTR_V_DIV8 & "000"); - voffset <= X"A000" when (HIRES_DEC = '1') else X"BB80"; - - -- Generate Address Phase 1 - VAP1 <= (voffset + mulBy40) + lCTR_H; - - -- Compute character row counter - CHROWCNT <= lCTR_V(3 downto 1) when (DBLHGT_EN = '1') else lCTR_V(2 downto 0); - -- Generate Address Phase 2 - VAP2 <= lADD & lDATABUS(6 downto 0) & CHROWCNT; - - -- multiplex addresses at rising edge of each phase - addr_latch: process - begin - wait until rising_edge(CLK_24); - if c(0) = '1' then - -- Generate video phase 1 address - AD_RAM_INT <= VAP1; - elsif c(8) = '1' then - -- Generate video phase 2 address - AD_RAM_INT <= VAP2; - elsif c(16) = '1' then - -- Generate CPU phase 3 address - AD_RAM_INT <= lADDR; - end if; - end process; -end architecture RTL; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/vag.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/vag.vhd deleted file mode 100644 index a0b2fa53..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/vag.vhd +++ /dev/null @@ -1,125 +0,0 @@ --- --- vag.vhd --- --- Generate video signals --- --- Copyright (C)2001 - 2005 SEILEBOST --- All rights reserved. --- --- $Id: vag.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $ --- --- TODO : --- Remark : - -library IEEE; -use IEEE.std_logic_1164.all; ---use IEEE.std_logic_arith.all; ---use IEEE.numeric_std.all; -use IEEE.std_logic_unsigned.all; - -entity vag is -port ( CLK_1 : in std_logic; - RESETn : in std_logic; - FREQ_SEL : in std_logic; -- Select 50/60 Hz frequency - CPT_H : out std_logic_vector(6 downto 0); -- Horizontal Counter - CPT_V : out std_logic_vector(8 downto 0); -- Vertical Counter - RELOAD_SEL : out std_logic; -- Reload registe SEL - FORCETXT : out std_logic; -- Force Mode Text - CLK_FLASH : out std_logic; -- Flash Clock - COMPSYNC : out std_logic; -- Composite Synchro signal - BLANKINGn : out std_logic -- Blanking signal - ); -end entity vag; - -architecture vag_arch of vag is - -signal lCPT_H : std_logic_vector(6 downto 0); -signal lCPT_V : std_logic_vector(8 downto 0); -signal lCPT_FLASH : std_logic_vector(5 downto 0); -signal lVSYNCn : std_logic; -signal lVBLANKn : std_logic; -signal lVFRAME : std_logic; -signal lFORCETXT : std_logic; -signal lHSYNCn : std_logic; -signal lHBLANKn : std_logic; -signal lRELOAD_SEL : std_logic; -signal lCLK_V : std_logic; - -begin - --- Horizontal Counter -u_CPT_H: PROCESS(CLK_1, RESETn) -BEGIN - IF (RESETn = '0') THEN - lCPT_H <= (OTHERS => '0'); - ELSIF rising_edge(CLK_1) THEN - IF lCPT_H < 63 then - lCPT_H <= lCPT_H + "0000001"; - ELSE - lCPT_H <= (OTHERS => '0'); - END IF; - END IF; -END PROCESS; - --- Horizontal Synchronisation -lHSYNCn <= '0' when (lCPT_H >= 49) AND (lCPT_H <= 53) ELSE '1'; - --- Horizontal Blank -lHBLANKn <= '0' when (lCPT_H >= 40) AND (lCPT_H <= 63) ELSE '1'; - --- Signal to Reload Register to reset attribut -lRELOAD_SEL <= '1' WHEN (lCPT_H >= 56) AND (lCPT_H <= 63) ELSE '0'; - --- Clock for Vertical counter -lCLK_V <= '1' WHEN (lCPT_H = 63) ELSE '0'; - --- Vertical Counter -u_CPT_V: PROCESS(lCLK_V, RESETn) -BEGIN - IF (RESETn = '0') THEN - lCPT_V <= (OTHERS => '0'); - ELSIF rising_edge(lCLK_V) THEN - IF (lCPT_V < 311) THEN - lCPT_V <= lCPT_V + "000000001"; - ELSE - lCPT_V <= (OTHERS => '0'); - END IF; - END IF; -END PROCESS; - --- Vertical Synchronisation -lVSYNCn <= '0' when(lCPT_V >= 258) AND (lCPT_V <= 259) ELSE '1'; - --- Vertical Blank -lVBLANKn <= '0' when(lCPT_V >= 224) AND (lCPT_V <= 311) ELSE '1'; - --- Clock to Flash Counter -lVFRAME <= '1' WHEN (lCPT_V = 311) ELSE '0'; - --- Signal To Force TEXT MODE -lFORCETXT <= '1' WHEN (lCPT_V > 199) ELSE '0'; - --- Flash Counter -u_FLASH : PROCESS( lVSYNCn, RESETn ) -BEGIN - IF (RESETn = '0') THEN - lCPT_FLASH <= (OTHERS => '0'); - ELSIF rising_edge(lVSYNCn) THEN - lCPT_FLASH <= lCPT_FLASH + "000001"; - END IF; -END PROCESS; - --- Assign signals -FORCETXT <= '1' WHEN ((lFORCETXT = '1') OR (lVFRAME = '1') ) ELSE '0'; -CLK_FLASH <= lCPT_FLASH(5); -RELOAD_SEL <= lRELOAD_SEL; -COMPSYNC <= NOT(lHSYNCn XOR lVSYNCn); - --- Assign counters -CPT_H <= lCPT_H; -CPT_V <= lCPT_V; - --- Assign blanking signal -BLANKINGn <= lVBLANKn AND lHBLANKn; - -end architecture vag_arch; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/video.vhd b/Computer_MiST/Oric Atmos_MiST/rtl/video.vhd deleted file mode 100644 index 28bca2ee..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/video.vhd +++ /dev/null @@ -1,229 +0,0 @@ --- --- video.vhd --- --- Manage video attribute --- --- Copyright (C)2001 - 2005 SEILEBOST --- All rights reserved. --- --- $Id: video.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $ --- --- TODO : --- Remark : - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_STD.all; - -entity video is -port ( RESETn : in std_logic; - CLK_PIXEL : in std_logic; - CLK_FLASH : in std_logic; - -- delete 17/11/2009 FLASH_SEL : in std_logic; - BLANKINGn : in std_logic; - RELOAD_SEL : in std_logic; - DATABUS : in std_logic_vector(7 downto 0); - ATTRIB_DEC : in std_logic; - DATABUS_EN : in std_logic; - LDFROMBUS : in std_logic; - LD_REG_0 : in std_logic; - RELD_REG : in std_logic; - CHROWCNT : in std_logic_vector(2 downto 0); - RGB : out std_logic_vector(2 downto 0); - FREQ_SEL : out std_logic; - TXTHIR_SEL : out std_logic; - isAttrib : out std_logic; - DBLSTD_SEL : out std_logic; - VAP2 : out std_logic_vector(15 downto 0) - ); -end entity video; - -architecture video_arch of video is - --- locals signals -signal lDATABUS : std_logic_vector(7 downto 0); -signal lSHFREG : std_logic_vector(5 downto 0); -signal lREGHOLD : std_logic_vector(5 downto 0); -signal lRGB : std_logic_vector(2 downto 0); -signal lCLK_REG : std_logic_vector(3 downto 0); -signal lREG_0 : std_logic_vector(2 downto 0); -signal lREG_1 : std_logic_vector(2 downto 0); -signal lREG_2 : std_logic_vector(2 downto 0); -signal lREG_3 : std_logic_vector(2 downto 0); -signal tmp : std_logic_vector(1 downto 0); -signal lADD : std_logic_vector(1 downto 0); -signal lDIN : std_logic; -- SET INVERSE SIGNAL -signal lSHFVIDEO : std_logic; -signal lBGFG_SEL : std_logic; -signal lFLASH_SEL : std_logic; -signal lIsATTRIB : std_logic; - -begin - --- Latch data from Data Bus -u_data_bus: PROCESS( DATABUS, DATABUS_EN) -BEGIN - -- Correctif 03/02/09 if (DATABUS_EN = '1') then - if (rising_edge(DATABUS_EN)) then - lDATABUS <= DATABUS; - end if; -END PROCESS; - --- Ajout du 04/02/09 / Commentaire le 05/12/09 ---isAttrib <= not lDATABUS(6); -- =1 is an attribut, = 0 is not an attribut - --- Decode register --- Modification multiple le 03/02/2010 ---u_attr_dec: PROCESS(lDATABUS, ATTRIB_DEC) ---BEGIN - --lCLK_REG <= "0000"; -- Ajout 11/11/09 Suppression 03/02/2010 --- if rising_edge(ATTRIB_DEC) then - -- le 03/02/2010 : commentaire de 9 lignes - -- if (lDATABUS(6 downto 5) = "00") then - -- case lDATABUS(4 downto 3) is - -- when "00" => lCLK_REG <= "0001"; - -- when "01" => lCLK_REG <= "0010"; - -- when "10" => lCLK_REG <= "0100"; - -- when "11" => lCLK_REG <= "1000"; - -- when others => null; --lCLK_REG <= "1111"; -- 11/11/09 null; - -- end case; - --end if; --- case lDATABUS(6 downto 3) is --- when "0000" => lCLK_REG <= "0001"; --- when "0001" => lCLK_REG <= "0010"; --- when "0010" => lCLK_REG <= "0100"; --- when "0011" => lCLK_REG <= "1000"; --- when others => lCLK_REG <= "0000"; --- end case; --- end if; ---END PROCESS; - -lCLK_REG(0) <= '1' when (lDATABUS(6 downto 3) = "0000") and (ATTRIB_DEC = '1') else '0'; -lCLK_REG(1) <= '1' when (lDATABUS(6 downto 3) = "0010") and (ATTRIB_DEC = '1') else '0'; -lCLK_REG(2) <= '1' when (lDATABUS(6 downto 3) = "0100") and (ATTRIB_DEC = '1') else '0'; -lCLK_REG(3) <= '1' when (lDATABUS(6 downto 3) = "1000") and (ATTRIB_DEC = '1') else '0'; - --- ajout le 05/12/09 -u_isattrib : PROCESS(DATABUS_EN, ATTRIB_DEC, RESETn) -BEGIN - if (RESETn = '0') then - lIsATTRIB <= '0'; - elsif rising_edge(ATTRIB_DEC) then - lIsATTRIB <= not (DATABUS(6) or DATABUS(5)); -- =1 is an attribut, = 0 is not an attribut - end if; -END PROCESS; - --- Assignation -isAttrib <= lIsATTRIB; - --- get value for register number 0 : INK -u_ld_reg0: PROCESS(lCLK_REG, RELOAD_SEL, lDATABUS, RESETn) -BEGIN - -- Ajout du 17/11/2009 - if (RESETn = '0') then - lREG_0 <= "000"; - elsif (RELOAD_SEL = '1') then - lREG_0 <= "000"; - -- le 17/11/2009 elsif (lCLK_REG(0) = '1') then - elsif rising_edge(lCLK_REG(0)) then - lREG_0 <= lDATABUS(2 downto 0); - end if; -END PROCESS; - --- get value for register number 1 : STYLE : Alt/std, Dbl/std, Flash sel -u_ld_reg1: PROCESS(lCLK_REG, RELOAD_SEL, lDATABUS, RESETN) -BEGIN - -- Ajout du 17/11/2009 - if (RESETn = '0') then - lREG_1 <= "000"; - elsif (RELOAD_SEL = '1') then - lREG_1 <= "000"; - -- le 17/11/2009 elsif (lCLK_REG(1) = '1') then - elsif rising_edge(lCLK_REG(1)) then - lREG_1 <= lDATABUS(2 downto 0); - end if; -END PROCESS; - --- get value for register number 2 : PAPER -u_ld_reg2: PROCESS(lCLK_REG, RELOAD_SEL, lDATABUS, RESETN) -BEGIN - -- Ajout du 17/11/2009 - if (RESETn = '0') then - lREG_2 <= "111"; - elsif (RELOAD_SEL = '1') then - lREG_2 <= "111"; - -- le 17/11/2009 elsif (lCLK_REG(2) = '1') then - elsif rising_edge(lCLK_REG(2)) then - lREG_2 <= lDATABUS(2 downto 0); - end if; -END PROCESS; - --- get value for register number 3 : Mode -u_ld_reg3: PROCESS(lCLK_REG, lDATABUS, RESETn) -BEGIN - if (RESETn = '0') then - lREG_3 <= "000"; - -- modif 04/02/09 elsif (lCLK_REG(3) = '1') then - elsif rising_edge(lCLK_REG(3)) then - lREG_3 <= lDATABUS(2 downto 0); - end if; -END PROCESS; - --- hold data value -u_hold_reg: PROCESS( LD_REG_0, LDFROMBUS, lDATABUS) -BEGIN - -- Chargement si attribut - if (LD_REG_0 = '1') then - lREGHOLD <= (OTHERS => '0'); - elsif (rising_edge(LDFROMBUS)) then - lREGHOLD <= lDATABUS(5 downto 0); - lDIN <= lDATABUS(7); -- Ajout du 15/12/2009 - end if; - ---mise en commentaire 15/12/2009 lDIN <= lDATABUS(7); -END PROCESS; - --- shift data for video -u_shf_reg: PROCESS(RELD_REG, CLK_PIXEL, lREGHOLD) -BEGIN - -- Chargement du shifter avant le front montant de PHI2 - if (RELD_REG = '1') then - lSHFREG <= lREGHOLD; - -- 6 bits à envoyer - elsif (rising_edge(CLK_PIXEL)) then - lSHFVIDEO <= lSHFREG(5); - lSHFREG <= lSHFREG(4 downto 0) & '0'; - end if; -END PROCESS; - -lFLASH_SEL <= lREG_1(2); -lBGFG_SEL <= NOT(lSHFVIDEO) when ( (CLK_FLASH = '1') AND (lFLASH_SEL = '1') ) else lSHFVIDEO; --- le 17/11/2009 : lBGFG_SEL <= NOT(lSHFVIDEO) when ( (CLK_FLASH = '1') AND (FLASH_SEL = '1') ) else lSHFVIDEO; --- lBGFG_SEL <= lSHFVIDEO and not ( CLK_FLASH AND FLASH_SEL ); - --- local assign for R(ed)G(reen)B(lue) signal -lRGB <= lREG_0 when lBGFG_SEL = '0' else lREG_2; - --- Assign out signal -RGB <= lRGB when (lDIN = '0' and BLANKINGn = '1') else - not(lRGB) when (lDIN = '1' and BLANKINGn = '1') else - "000"; - -DBLSTD_SEL <= lREG_1(1); -- Double/Standard height character select -FREQ_SEL <= lREG_3(1); -- Frenquecy video (50/60Hz) select -TXTHIR_SEL <= lREG_3(2); -- Texte/Hires mode select - --- Compute offset -tmp <= lREG_3(2) & lREG_1(0); -with tmp select -lADD <= "01" when "00", -- TXT & STD - "10" when "01", -- TXT & ALT - "10" when "10", -- HIRES & STD - "11" when "11", -- HIRES & ALT - "01" when others; -- Du fait que le design original de l'ULA - -- n'a pas de reset, nous supposerons que - -- l'ULA est en mode text et standard - --- Generate Address Phase 2 -VAP2 <= "10" & not lREG_3(2) & '1' & lADD & lDATABUS(6 downto 0) & CHROWCNT; - -end architecture video_arch; diff --git a/Computer_MiST/Oric Atmos_MiST/rtl/video_mixer.sv b/Computer_MiST/Oric Atmos_MiST/rtl/video_mixer.sv deleted file mode 100644 index 04cfd4ba..00000000 --- a/Computer_MiST/Oric Atmos_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,242 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Computer_MiST/Oric Atmos_MiST/storage/BRAIN_RAM.txt b/Computer_MiST/Oric Atmos_MiST/storage/BRAIN_RAM.txt deleted file mode 100644 index f7443798..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/BRAIN_RAM.txt +++ /dev/null @@ -1,12 +0,0 @@ -Ram dynamique : - RAS - CAS - R/W - -RAM STATIQUE - CS - R/W - clk - - cs = Page 0-2 + Page 4-BF - CLK = CAS \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/storage/ORIC_pad.txt b/Computer_MiST/Oric Atmos_MiST/storage/ORIC_pad.txt deleted file mode 100644 index 7f7e5ea5..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/ORIC_pad.txt +++ /dev/null @@ -1,286 +0,0 @@ -Release 11.1 - par L.33 (lin) -Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. - -Thu Apr 8 22:11:19 2010 - - -INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: -1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. -2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. -3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. - -INPUT FILE: ORIC_map.ncd -OUTPUT FILE: ORIC_pad.txt -PART TYPE: xa3s1000 -SPEED GRADE: -4 -PACKAGE: ftg256 - -Pinout by Pin Number: - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|A1 | | |GND | | | | | | | | | | | | -|A2 | | |TDI | | | | | | | | | | | | -|A3 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | | -|A4 | |DIFFM |IO_L01P_0/VRN_0 |UNUSED | |0 | | | | | | | | | -|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | | -|A6 | | |VCCAUX | | | | | | | |2.5 | | | | -|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | -|A8 | |DIFFM |IO_L32P_0/GCLK6 |UNUSED | |0 | | | | | | | | | -|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | | -|A10 | |DIFFS |IO_L31N_1/VREF_1 |UNUSED | |1 | | | | | | | | | -|A11 | | |VCCAUX | | | | | | | |2.5 | | | | -|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | | -|A13 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | | -|A14 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | | -|A15 | | |TDO | | | | | | | | | | | | -|A16 | | |GND | | | | | | | | | | | | -|B1 |D<7> |IOB |IO_L01P_7/VRN_7 |BIDIR |LVCMOS25* |7 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE | -|B2 | | |GND | | | | | | | | | | | | -|B3 | | |PROG_B | | | | | | | | | | | | -|B4 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | | -|B5 | |DIFFM |IO_L25P_0 |UNUSED | |0 | | | | | | | | | -|B6 | |DIFFM |IO_L28P_0 |UNUSED | |0 | | | | | | | | | -|B7 | |DIFFM |IO_L30P_0 |UNUSED | |0 | | | | | | | | | -|B8 | |DIFFS |IO_L32N_0/GCLK7 |UNUSED | |0 | | | | | | | | | -|B9 | | |GND | | | | | | | | | | | | -|B10 | |DIFFM |IO_L31P_1 |UNUSED | |1 | | | | | | | | | -|B11 | |DIFFS |IO_L29N_1 |UNUSED | |1 | | | | | | | | | -|B12 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | | -|B13 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | | -|B14 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | | -|B15 | | |GND | | | | | | | | | | | | -|B16 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | | -|C1 |D<6> |IOB |IO_L01N_7/VRP_7 |BIDIR |LVCMOS25* |7 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE | -|C2 |D<5> |IOB |IO_L16N_7 |BIDIR |LVCMOS25* |7 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE | -|C3 | |DIFFM |IO_L16P_7/VREF_7 |UNUSED | |7 | | | | | | | | | -|C4 | | |HSWAP_EN | | | | | | | | | | | | -|C5 | |DIFFS |IO_L25N_0 |UNUSED | |0 | | | | | | | | | -|C6 | |DIFFS |IO_L28N_0 |UNUSED | |0 | | | | | | | | | -|C7 | |DIFFS |IO_L30N_0 |UNUSED | |0 | | | | | | | | | -|C8 | |DIFFM |IO_L31P_0/VREF_0 |UNUSED | |0 | | | | | | | | | -|C9 | |DIFFS |IO_L32N_1/GCLK5 |UNUSED | |1 | | | | | | | | | -|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | | -|C11 | |DIFFM |IO_L29P_1 |UNUSED | |1 | | | | | | | | | -|C12 | |DIFFM |IO_L27P_1 |UNUSED | |1 | | | | | | | | | -|C13 | | |TMS | | | | | | | | | | | | -|C14 | | |TCK | | | | | | | | | | | | -|C15 | |DIFFS |IO_L16N_2 |UNUSED | |2 | | | | | | | | | -|C16 | |DIFFM |IO_L01P_2/VRN_2 |UNUSED | |2 | | | | | | | | | -|D1 | |DIFFS |IO_L17N_7 |UNUSED | |7 | | | | | | | | | -|D2 | |DIFFM |IO_L17P_7 |UNUSED | |7 | | | | | | | | | -|D3 | |DIFFM |IO_L19P_7 |UNUSED | |7 | | | | | | | | | -|D4 | | |VCCINT | | | | | | | |1.2 | | | | -|D5 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | | -|D6 | |DIFFM |IO_L27P_0 |UNUSED | |0 | | | | | | | | | -|D7 | |DIFFM |IO_L29P_0 |UNUSED | |0 | | | | | | | | | -|D8 | |DIFFS |IO_L31N_0 |UNUSED | |0 | | | | | | | | | -|D9 | |DIFFM |IO_L32P_1/GCLK4 |UNUSED | |1 | | | | | | | | | -|D10 | |DIFFS |IO_L30N_1 |UNUSED | |1 | | | | | | | | | -|D11 | |DIFFS |IO_L28N_1 |UNUSED | |1 | | | | | | | | | -|D12 | |IOB |IO/VREF_1 |UNUSED | |1 | | | | | | | | | -|D13 | | |VCCINT | | | | | | | |1.2 | | | | -|D14 |an<0> |IOB |IO_L16P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|D15 | |DIFFS |IO_L17N_2 |UNUSED | |2 | | | | | | | | | -|D16 | |DIFFM |IO_L17P_2/VREF_2 |UNUSED | |2 | | | | | | | | | -|E1 | |DIFFS |IO_L20N_7 |UNUSED | |7 | | | | | | | | | -|E2 | |DIFFM |IO_L20P_7 |UNUSED | |7 | | | | | | | | | -|E3 |AD<8> |IOB |IO_L19N_7/VREF_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|E4 |AD<9> |IOB |IO_L21P_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|E5 | | |VCCINT | | | | | | | |1.2 | | | | -|E6 | |DIFFS |IO_L27N_0 |UNUSED | |0 | | | | | | | | | -|E7 | |DIFFS |IO_L29N_0 |UNUSED | |0 | | | | | | | | | -|E8 | | |VCCO_0 | | |0 | | | | |any******| | | | -|E9 | | |VCCO_1 | | |1 | | | | |any******| | | | -|E10 | |DIFFM |IO_L30P_1 |UNUSED | |1 | | | | | | | | | -|E11 | |DIFFM |IO_L28P_1 |UNUSED | |1 | | | | | | | | | -|E12 | | |VCCINT | | | | | | | |1.2 | | | | -|E13 |an<3> |IOB |IO_L19N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|E14 |sseg<6> |IOB |IO_L19P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|E15 | |DIFFS |IO_L20N_2 |UNUSED | |2 | | | | | | | | | -|E16 | |DIFFM |IO_L20P_2 |UNUSED | |2 | | | | | | | | | -|F1 | | |VCCAUX | | | | | | | |2.5 | | | | -|F2 | |DIFFS |IO_L22N_7 |UNUSED | |7 | | | | | | | | | -|F3 |AD<6> |IOB |IO_L22P_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|F4 |AD<7> |IOB |IO_L21N_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|F5 | |DIFFM |IO_L23P_7 |UNUSED | |7 | | | | | | | | | -|F6 | | |GND | | | | | | | | | | | | -|F7 | | |VCCO_0 | | |0 | | | | |any******| | | | -|F8 | | |VCCO_0 | | |0 | | | | |any******| | | | -|F9 | | |VCCO_1 | | |1 | | | | |any******| | | | -|F10 | | |VCCO_1 | | |1 | | | | |any******| | | | -|F11 | | |GND | | | | | | | | | | | | -|F12 | |DIFFS |IO_L21N_2 |UNUSED | |2 | | | | | | | | | -|F13 |sseg<1> |IOB |IO_L21P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|F14 |an<2> |IOB |IO_L22N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|F15 | |DIFFM |IO_L22P_2 |UNUSED | |2 | | | | | | | | | -|F16 | | |VCCAUX | | | | | | | |2.5 | | | | -|G1 | |DIFFM |IO_L40P_7 |UNUSED | |7 | | | | | | | | | -|G2 | |DIFFS |IO |UNUSED | |7 | | | | | | | | | -|G3 |WE_SRAMn |IOB |IO_L24N_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|G4 |AD<5> |IOB |IO_L24P_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|G5 |AD<10> |IOB |IO_L23N_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|G6 | | |VCCO_7 | | |7 | | | | |2.50 | | | | -|G7 | | |GND | | | | | | | | | | | | -|G8 | | |GND | | | | | | | | | | | | -|G9 | | |GND | | | | | | | | | | | | -|G10 | | |GND | | | | | | | | | | | | -|G11 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|G12 | |DIFFS |IO_L23N_2/VREF_2 |UNUSED | |2 | | | | | | | | | -|G13 |sseg<5> |IOB |IO_L23P_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|G14 |an<1> |IOB |IO_L24N_2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|G15 | |DIFFM |IO_L24P_2 |UNUSED | |2 | | | | | | | | | -|G16 | |DIFFM |IO |UNUSED | |2 | | | | | | | | | -|H1 | |DIFFS |IO_L40N_7/VREF_7 |UNUSED | |7 | | | | | | | | | -|H2 | | |GND | | | | | | | | | | | | -|H3 |AD<11> |IOB |IO_L39N_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|H4 |AD<12> |IOB |IO_L39P_7 |OUTPUT |LVCMOS25* |7 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|H5 | | |VCCO_7 | | |7 | | | | |2.50 | | | | -|H6 | | |VCCO_7 | | |7 | | | | |2.50 | | | | -|H7 | | |GND | | | | | | | | | | | | -|H8 | | |GND | | | | | | | | | | | | -|H9 | | |GND | | | | | | | | | | | | -|H10 | | |GND | | | | | | | | | | | | -|H11 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|H12 | | |VCCO_2 | | |2 | | | | |2.50 | | | | -|H13 | |DIFFS |IO_L39N_2 |UNUSED | |2 | | | | | | | | | -|H14 | |DIFFM |IO_L39P_2 |UNUSED | |2 | | | | | | | | | -|H15 | |DIFFS |IO_L40N_2 |UNUSED | |2 | | | | | | | | | -|H16 | |DIFFM |IO_L40P_2/VREF_2 |UNUSED | |2 | | | | | | | | | -|J1 |VIDEO_R |IOB |IO_L40P_6/VREF_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|J2 |VIDEO_G |IOB |IO_L40N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|J3 |AD<14> |IOB |IO_L39P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|J4 |AD<13> |IOB |IO_L39N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|J5 | | |VCCO_6 | | |6 | | | | |2.50 | | | | -|J6 | | |VCCO_6 | | |6 | | | | |2.50 | | | | -|J7 | | |GND | | | | | | | | | | | | -|J8 | | |GND | | | | | | | | | | | | -|J9 | | |GND | | | | | | | | | | | | -|J10 | | |GND | | | | | | | | | | | | -|J11 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|J12 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|J13 | |DIFFM |IO_L39P_3 |UNUSED | |3 | | | | | | | | | -|J14 | |DIFFS |IO_L39N_3 |UNUSED | |3 | | | | | | | | | -|J15 | | |GND | | | | | | | | | | | | -|J16 | |DIFFS |IO_L40N_3/VREF_3 |UNUSED | |3 | | | | | | | | | -|K1 |VIDEO_B |IOB |IO |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|K2 | |DIFFM |IO_L24P_6 |UNUSED | |6 | | | | | | | | | -|K3 |AD<15> |IOB |IO_L24N_6/VREF_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|K4 |OE_SRAMn |IOB |IO_L23P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|K5 |AD<16> |IOB |IO_L23N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|K6 | | |VCCO_6 | | |6 | | | | |2.50 | | | | -|K7 | | |GND | | | | | | | | | | | | -|K8 | | |GND | | | | | | | | | | | | -|K9 | | |GND | | | | | | | | | | | | -|K10 | | |GND | | | | | | | | | | | | -|K11 | | |VCCO_3 | | |3 | | | | |2.50 | | | | -|K12 | |DIFFS |IO_L23N_3 |UNUSED | |3 | | | | | | | | | -|K13 | |DIFFM |IO_L24P_3 |UNUSED | |3 | | | | | | | | | -|K14 | |DIFFS |IO_L24N_3 |UNUSED | |3 | | | | | | | | | -|K15 | |DIFFS |IO |UNUSED | |3 | | | | | | | | | -|K16 | |DIFFM |IO_L40P_3 |UNUSED | |3 | | | | | | | | | -|L1 | | |VCCAUX | | | | | | | |2.5 | | | | -|L2 |VIDEO_SYNC |IOB |IO_L22P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|L3 |AD<17> |IOB |IO_L22N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|L4 |AD<4> |IOB |IO_L21P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|L5 |AD<0> |IOB |IO_L21N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|L6 | | |GND | | | | | | | | | | | | -|L7 | | |VCCO_5 | | |5 | | | | |2.50 | | | | -|L8 | | |VCCO_5 | | |5 | | | | |2.50 | | | | -|L9 | | |VCCO_4 | | |4 | | | | |2.50 | | | | -|L10 | | |VCCO_4 | | |4 | | | | |2.50 | | | | -|L11 | | |GND | | | | | | | | | | | | -|L12 | |DIFFM |IO_L23P_3/VREF_3 |UNUSED | |3 | | | | | | | | | -|L13 |btn<2> |IOB |IO_L21N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | -|L14 |RESETn |IOB |IO_L22P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | -|L15 | |DIFFS |IO_L22N_3 |UNUSED | |3 | | | | | | | | | -|L16 | | |VCCAUX | | | | | | | |2.5 | | | | -|M1 | |DIFFM |IO_L20P_6 |UNUSED | |6 | | | | | | | | | -|M2 | |DIFFS |IO_L20N_6 |UNUSED | |6 | | | | | | | | | -|M3 |AD<3> |IOB |IO_L19P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|M4 |AD<2> |IOB |IO_L19N_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|M5 | | |VCCINT | | | | | | | |1.2 | | | | -|M6 | |DIFFM |IO_L28P_5/D7 |UNUSED | |5 | | | | | | | | | -|M7 | |DIFFM |IO_L30P_5 |UNUSED | |5 | | | | | | | | | -|M8 | | |VCCO_5 | | |5 | | | | |2.50 | | | | -|M9 | | |VCCO_4 | | |4 | | | | |2.50 | | | | -|M10 | |DIFFS |IO_L29N_4 |UNUSED | |4 | | | | | | | | | -|M11 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | | -|M12 | | |VCCINT | | | | | | | |1.2 | | | | -|M13 |btn<0> |IOB |IO_L21P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | -|M14 |btn<1> |IOB |IO_L19N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | -|M15 |PS2_DATA |IOB |IO_L20P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | -|M16 |PS2_CLK |IOB |IO_L20N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | -|N1 | |DIFFM |IO_L17P_6/VREF_6 |UNUSED | |6 | | | | | | | | | -|N2 | |DIFFS |IO_L17N_6 |UNUSED | |6 | | | | | | | | | -|N3 |AD<1> |IOB |IO_L16P_6 |OUTPUT |LVCMOS25* |6 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|N4 | | |VCCINT | | | | | | | |1.2 | | | | -|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | | -|N6 | |DIFFS |IO_L28N_5/D6 |UNUSED | |5 | | | | | | | | | -|N7 |D<0> |IOB |IO_L30N_5 |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE | -|N8 | |DIFFM |IO_L32P_5/GCLK2 |UNUSED | |5 | | | | | | | | | -|N9 | |DIFFS |IO_L31N_4/INIT_B |UNUSED | |4 | | | | | | | | | -|N10 | |DIFFM |IO_L29P_4 |UNUSED | |4 | | | | | | | | | -|N11 | |DIFFM |IO_L27P_4/D1 |UNUSED | |4 | | | | | | | | | -|N12 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | -|N13 | | |VCCINT | | | | | | | |1.2 | | | | -|N14 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | | -|N15 |sseg<4> |IOB |IO_L17P_3/VREF_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|N16 |sseg<0> |IOB |IO_L17N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|P1 | |DIFFM |IO_L01P_6/VRN_6 |UNUSED | |6 | | | | | | | | | -|P2 | |DIFFS |IO_L16N_6 |UNUSED | |6 | | | | | | | | | -|P3 | | |M0 | | | | | | | | | | | | -|P4 | | |M2 | | | | | | | | | | | | -|P5 | |DIFFM |IO_L27P_5 |UNUSED | |5 | | | | | | | | | -|P6 |LB_SRAMn |IOB |IO_L29P_5/VREF_5 |OUTPUT |LVCMOS25* |5 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|P7 |CE_SRAMn |IOB |IO |OUTPUT |LVCMOS25* |5 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|P8 | |DIFFS |IO_L32N_5/GCLK3 |UNUSED | |5 | | | | | | | | | -|P9 | |DIFFM |IO_L31P_4/DOUT/BUSY|UNUSED | |4 | | | | | | | | | -|P10 | |DIFFS |IO_L30N_4/D2 |UNUSED | |4 | | | | | | | | | -|P11 | |DIFFS |IO_L28N_4 |UNUSED | |4 | | | | | | | | | -|P12 | |DIFFS |IO_L25N_4 |UNUSED | |4 | | | | | | | | | -|P13 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | -|P14 | |DIFFM |IO_L16P_3 |UNUSED | |3 | | | | | | | | | -|P15 |sseg<3> |IOB |IO_L16N_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|P16 |sseg<7> |IOB |IO_L01N_3/VRP_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|R1 | |DIFFS |IO_L01N_6/VRP_6 |UNUSED | |6 | | | | | | | | | -|R2 | | |GND | | | | | | | | | | | | -|R3 | |DIFFM |IO_L01P_5/CS_B |UNUSED | |5 | | | | | | | | | -|R4 | |DIFFM |IO_L10P_5/VRN_5 |UNUSED | |5 | | | | | | | | | -|R5 |D<4> |IOB |IO_L27N_5/VREF_5 |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE | -|R6 |D<2> |IOB |IO_L29N_5 |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE | -|R7 | |DIFFM |IO_L31P_5/D5 |UNUSED | |5 | | | | | | | | | -|R8 | | |GND | | | | | | | | | | | | -|R9 |RW |IOB |IO_L32N_4/GCLK1 |OUTPUT |LVCMOS25* |4 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|R10 | |DIFFM |IO_L30P_4/D3 |UNUSED | |4 | | | | | | | | | -|R11 | |DIFFM |IO_L28P_4 |UNUSED | |4 | | | | | | | | | -|R12 | |DIFFM |IO_L25P_4 |UNUSED | |4 | | | | | | | | | -|R13 | |DIFFS |IO_L01N_4/VRP_4 |UNUSED | |4 | | | | | | | | | -|R14 | | |DONE | | | | | | | | | | | | -|R15 | | |GND | | | | | | | | | | | | -|R16 |sseg<2> |IOB |IO_L01P_3/VRN_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|T1 | | |GND | | | | | | | | | | | | -|T2 | | |M1 | | | | | | | | | | | | -|T3 | |DIFFS |IO_L01N_5/RDWR_B |UNUSED | |5 | | | | | | | | | -|T4 |UB_SRAMn |IOB |IO_L10N_5/VRP_5 |OUTPUT |LVCMOS25* |5 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | -|T5 |D<3> |IOB |IO |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE | -|T6 | | |VCCAUX | | | | | | | |2.5 | | | | -|T7 | |DIFFS |IO_L31N_5/D4 |UNUSED | |5 | | | | | | | | | -|T8 |D<1> |IOB |IO/VREF_5 |BIDIR |LVCMOS25* |5 |12 |SLOW |NONE** |NONE | |LOCATED |NO |NONE | -|T9 |CLK_50 |IOB |IO_L32P_4/GCLK0 |INPUT |LVCMOS25* |4 | | | |NONE | |LOCATED |NO |NONE | -|T10 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | -|T11 | | |VCCAUX | | | | | | | |2.5 | | | | -|T12 | |IOB |IO |UNUSED | |4 | | | | | | | | | -|T13 | |DIFFM |IO_L01P_4/VRN_4 |UNUSED | |4 | | | | | | | | | -|T14 | |DIFFS |IO |UNUSED | |4 | | | | | | | | | -|T15 | | |CCLK | | | | | | | | | | | | -|T16 | | |GND | | | | | | | | | | | | -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -* Default value. -** This default Pullup/Pulldown value can be overridden in Bitgen. -****** Special VCCO requirements may apply. Please consult the device - family datasheet for specific guideline on VCCO requirements. - - diff --git a/Computer_MiST/Oric Atmos_MiST/storage/OricKbd.jpg b/Computer_MiST/Oric Atmos_MiST/storage/OricKbd.jpg deleted file mode 100644 index 37aa1bd8..00000000 Binary files a/Computer_MiST/Oric Atmos_MiST/storage/OricKbd.jpg and /dev/null differ diff --git a/Computer_MiST/Oric Atmos_MiST/storage/OricinFPGA.gise b/Computer_MiST/Oric Atmos_MiST/storage/OricinFPGA.gise deleted file mode 100644 index 5af54d73..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/OricinFPGA.gise +++ /dev/null @@ -1,170 +0,0 @@ - - - - - - - - - - - - - - - - - - - - 11.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Computer_MiST/Oric Atmos_MiST/storage/OricinFPGA.xise b/Computer_MiST/Oric Atmos_MiST/storage/OricinFPGA.xise deleted file mode 100644 index b2995e31..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/OricinFPGA.xise +++ /dev/null @@ -1,497 +0,0 @@ - - - -
- - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/Computer_MiST/Oric Atmos_MiST/storage/apple_interface.jpeg b/Computer_MiST/Oric Atmos_MiST/storage/apple_interface.jpeg deleted file mode 100644 index 400984bf..00000000 Binary files a/Computer_MiST/Oric Atmos_MiST/storage/apple_interface.jpeg and /dev/null differ diff --git a/Computer_MiST/Oric Atmos_MiST/storage/microdisc-1.gif b/Computer_MiST/Oric Atmos_MiST/storage/microdisc-1.gif deleted file mode 100644 index 8136536e..00000000 Binary files a/Computer_MiST/Oric Atmos_MiST/storage/microdisc-1.gif and /dev/null differ diff --git a/Computer_MiST/Oric Atmos_MiST/storage/microdisc-2.gif b/Computer_MiST/Oric Atmos_MiST/storage/microdisc-2.gif deleted file mode 100644 index 7b94d8f5..00000000 Binary files a/Computer_MiST/Oric Atmos_MiST/storage/microdisc-2.gif and /dev/null differ diff --git a/Computer_MiST/Oric Atmos_MiST/storage/oric1-1p.gif b/Computer_MiST/Oric Atmos_MiST/storage/oric1-1p.gif deleted file mode 100644 index 2d88f1af..00000000 Binary files a/Computer_MiST/Oric Atmos_MiST/storage/oric1-1p.gif and /dev/null differ diff --git a/Computer_MiST/Oric Atmos_MiST/storage/oric1-2p.gif b/Computer_MiST/Oric Atmos_MiST/storage/oric1-2p.gif deleted file mode 100644 index 4c6bf166..00000000 Binary files a/Computer_MiST/Oric Atmos_MiST/storage/oric1-2p.gif and /dev/null differ diff --git a/Computer_MiST/Oric Atmos_MiST/storage/oric_PS2_IF_pad.txt b/Computer_MiST/Oric Atmos_MiST/storage/oric_PS2_IF_pad.txt deleted file mode 100644 index 13e28893..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/oric_PS2_IF_pad.txt +++ /dev/null @@ -1,286 +0,0 @@ -Release 11.1 - par L.33 (lin) -Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. - -Thu Jan 28 22:35:29 2010 - - -INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: -1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. -2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. -3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. - -INPUT FILE: oric_PS2_IF_map.ncd -OUTPUT FILE: oric_PS2_IF_pad.txt -PART TYPE: xa3s1000 -SPEED GRADE: -4 -PACKAGE: ftg256 - -Pinout by Pin Number: - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -|A1 | | |GND | | | | | | | | | | | | -|A2 | | |TDI | | | | | | | | | | | | -|A3 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | | -|A4 | |DIFFM |IO_L01P_0/VRN_0 |UNUSED | |0 | | | | | | | | | -|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | | -|A6 | | |VCCAUX | | | | | | | |2.5 | | | | -|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | -|A8 |RESTORE |IOB |IO_L32P_0/GCLK6 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | -|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | | -|A10 | |DIFFS |IO_L31N_1/VREF_1 |UNUSED | |1 | | | | | | | | | -|A11 | | |VCCAUX | | | | | | | |2.5 | | | | -|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | | -|A13 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | | -|A14 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | | -|A15 | | |TDO | | | | | | | | | | | | -|A16 | | |GND | | | | | | | | | | | | -|B1 | |DIFFM |IO_L01P_7/VRN_7 |UNUSED | |7 | | | | | | | | | -|B2 | | |GND | | | | | | | | | | | | -|B3 | | |PROG_B | | | | | | | | | | | | -|B4 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | | -|B5 | |DIFFM |IO_L25P_0 |UNUSED | |0 | | | | | | | | | -|B6 | |DIFFM |IO_L28P_0 |UNUSED | |0 | | | | | | | | | -|B7 | |DIFFM |IO_L30P_0 |UNUSED | |0 | | | | | | | | | -|B8 | |DIFFS |IO_L32N_0/GCLK7 |UNUSED | |0 | | | | | | | | | -|B9 | | |GND | | | | | | | | | | | | -|B10 | |DIFFM |IO_L31P_1 |UNUSED | |1 | | | | | | | | | -|B11 | |DIFFS |IO_L29N_1 |UNUSED | |1 | | | | | | | | | -|B12 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | | -|B13 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | | -|B14 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | | -|B15 | | |GND | | | | | | | | | | | | -|B16 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | | -|C1 | |DIFFS |IO_L01N_7/VRP_7 |UNUSED | |7 | | | | | | | | | -|C2 | |DIFFS |IO_L16N_7 |UNUSED | |7 | | | | | | | | | -|C3 | |DIFFM |IO_L16P_7/VREF_7 |UNUSED | |7 | | | | | | | | | -|C4 | | |HSWAP_EN | | | | | | | | | | | | -|C5 | |DIFFS |IO_L25N_0 |UNUSED | |0 | | | | | | | | | -|C6 | |DIFFS |IO_L28N_0 |UNUSED | |0 | | | | | | | | | -|C7 | |DIFFS |IO_L30N_0 |UNUSED | |0 | | | | | | | | | -|C8 | |DIFFM |IO_L31P_0/VREF_0 |UNUSED | |0 | | | | | | | | | -|C9 | |DIFFS |IO_L32N_1/GCLK5 |UNUSED | |1 | | | | | | | | | -|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | | -|C11 | |DIFFM |IO_L29P_1 |UNUSED | |1 | | | | | | | | | -|C12 | |DIFFM |IO_L27P_1 |UNUSED | |1 | | | | | | | | | -|C13 | | |TMS | | | | | | | | | | | | -|C14 | | |TCK | | | | | | | | | | | | -|C15 | |DIFFS |IO_L16N_2 |UNUSED | |2 | | | | | | | | | -|C16 | |DIFFM |IO_L01P_2/VRN_2 |UNUSED | |2 | | | | | | | | | -|D1 | |DIFFS |IO_L17N_7 |UNUSED | |7 | | | | | | | | | -|D2 | |DIFFM |IO_L17P_7 |UNUSED | |7 | | | | | | | | | -|D3 | |DIFFM |IO_L19P_7 |UNUSED | |7 | | | | | | | | | -|D4 | | |VCCINT | | | | | | | |1.2 | | | | -|D5 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | | -|D6 | |DIFFM |IO_L27P_0 |UNUSED | |0 | | | | | | | | | -|D7 | |DIFFM |IO_L29P_0 |UNUSED | |0 | | | | | | | | | -|D8 | |DIFFS |IO_L31N_0 |UNUSED | |0 | | | | | | | | | -|D9 | |DIFFM |IO_L32P_1/GCLK4 |UNUSED | |1 | | | | | | | | | -|D10 | |DIFFS |IO_L30N_1 |UNUSED | |1 | | | | | | | | | -|D11 | |DIFFS |IO_L28N_1 |UNUSED | |1 | | | | | | | | | -|D12 | |IOB |IO/VREF_1 |UNUSED | |1 | | | | | | | | | -|D13 | | |VCCINT | | | | | | | |1.2 | | | | -|D14 | |DIFFM |IO_L16P_2 |UNUSED | |2 | | | | | | | | | -|D15 | |DIFFS |IO_L17N_2 |UNUSED | |2 | | | | | | | | | -|D16 | |DIFFM |IO_L17P_2/VREF_2 |UNUSED | |2 | | | | | | | | | -|E1 | |DIFFS |IO_L20N_7 |UNUSED | |7 | | | | | | | | | -|E2 | |DIFFM |IO_L20P_7 |UNUSED | |7 | | | | | | | | | -|E3 | |DIFFS |IO_L19N_7/VREF_7 |UNUSED | |7 | | | | | | | | | -|E4 | |DIFFM |IO_L21P_7 |UNUSED | |7 | | | | | | | | | -|E5 | | |VCCINT | | | | | | | |1.2 | | | | -|E6 | |DIFFS |IO_L27N_0 |UNUSED | |0 | | | | | | | | | -|E7 | |DIFFS |IO_L29N_0 |UNUSED | |0 | | | | | | | | | -|E8 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|E9 | | |VCCO_1 | | |1 | | | | |any******| | | | -|E10 | |DIFFM |IO_L30P_1 |UNUSED | |1 | | | | | | | | | -|E11 | |DIFFM |IO_L28P_1 |UNUSED | |1 | | | | | | | | | -|E12 | | |VCCINT | | | | | | | |1.2 | | | | -|E13 | |DIFFS |IO_L19N_2 |UNUSED | |2 | | | | | | | | | -|E14 | |DIFFM |IO_L19P_2 |UNUSED | |2 | | | | | | | | | -|E15 | |DIFFS |IO_L20N_2 |UNUSED | |2 | | | | | | | | | -|E16 | |DIFFM |IO_L20P_2 |UNUSED | |2 | | | | | | | | | -|F1 | | |VCCAUX | | | | | | | |2.5 | | | | -|F2 | |DIFFS |IO_L22N_7 |UNUSED | |7 | | | | | | | | | -|F3 | |DIFFM |IO_L22P_7 |UNUSED | |7 | | | | | | | | | -|F4 | |DIFFS |IO_L21N_7 |UNUSED | |7 | | | | | | | | | -|F5 | |DIFFM |IO_L23P_7 |UNUSED | |7 | | | | | | | | | -|F6 | | |GND | | | | | | | | | | | | -|F7 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|F8 | | |VCCO_0 | | |0 | | | | |2.50 | | | | -|F9 | | |VCCO_1 | | |1 | | | | |any******| | | | -|F10 | | |VCCO_1 | | |1 | | | | |any******| | | | -|F11 | | |GND | | | | | | | | | | | | -|F12 | |DIFFS |IO_L21N_2 |UNUSED | |2 | | | | | | | | | -|F13 | |DIFFM |IO_L21P_2 |UNUSED | |2 | | | | | | | | | -|F14 | |DIFFS |IO_L22N_2 |UNUSED | |2 | | | | | | | | | -|F15 | |DIFFM |IO_L22P_2 |UNUSED | |2 | | | | | | | | | -|F16 | | |VCCAUX | | | | | | | |2.5 | | | | -|G1 | |DIFFM |IO_L40P_7 |UNUSED | |7 | | | | | | | | | -|G2 | |DIFFS |IO |UNUSED | |7 | | | | | | | | | -|G3 | |DIFFS |IO_L24N_7 |UNUSED | |7 | | | | | | | | | -|G4 | |DIFFM |IO_L24P_7 |UNUSED | |7 | | | | | | | | | -|G5 | |DIFFS |IO_L23N_7 |UNUSED | |7 | | | | | | | | | -|G6 | | |VCCO_7 | | |7 | | | | |any******| | | | -|G7 | | |GND | | | | | | | | | | | | -|G8 | | |GND | | | | | | | | | | | | -|G9 | | |GND | | | | | | | | | | | | -|G10 | | |GND | | | | | | | | | | | | -|G11 | | |VCCO_2 | | |2 | | | | |any******| | | | -|G12 | |DIFFS |IO_L23N_2/VREF_2 |UNUSED | |2 | | | | | | | | | -|G13 | |DIFFM |IO_L23P_2 |UNUSED | |2 | | | | | | | | | -|G14 | |DIFFS |IO_L24N_2 |UNUSED | |2 | | | | | | | | | -|G15 | |DIFFM |IO_L24P_2 |UNUSED | |2 | | | | | | | | | -|G16 | |DIFFM |IO |UNUSED | |2 | | | | | | | | | -|H1 | |DIFFS |IO_L40N_7/VREF_7 |UNUSED | |7 | | | | | | | | | -|H2 | | |GND | | | | | | | | | | | | -|H3 | |DIFFS |IO_L39N_7 |UNUSED | |7 | | | | | | | | | -|H4 | |DIFFM |IO_L39P_7 |UNUSED | |7 | | | | | | | | | -|H5 | | |VCCO_7 | | |7 | | | | |any******| | | | -|H6 | | |VCCO_7 | | |7 | | | | |any******| | | | -|H7 | | |GND | | | | | | | | | | | | -|H8 | | |GND | | | | | | | | | | | | -|H9 | | |GND | | | | | | | | | | | | -|H10 | | |GND | | | | | | | | | | | | -|H11 | | |VCCO_2 | | |2 | | | | |any******| | | | -|H12 | | |VCCO_2 | | |2 | | | | |any******| | | | -|H13 | |DIFFS |IO_L39N_2 |UNUSED | |2 | | | | | | | | | -|H14 | |DIFFM |IO_L39P_2 |UNUSED | |2 | | | | | | | | | -|H15 | |DIFFS |IO_L40N_2 |UNUSED | |2 | | | | | | | | | -|H16 | |DIFFM |IO_L40P_2/VREF_2 |UNUSED | |2 | | | | | | | | | -|J1 | |DIFFM |IO_L40P_6/VREF_6 |UNUSED | |6 | | | | | | | | | -|J2 | |DIFFS |IO_L40N_6 |UNUSED | |6 | | | | | | | | | -|J3 | |DIFFM |IO_L39P_6 |UNUSED | |6 | | | | | | | | | -|J4 | |DIFFS |IO_L39N_6 |UNUSED | |6 | | | | | | | | | -|J5 | | |VCCO_6 | | |6 | | | | |any******| | | | -|J6 | | |VCCO_6 | | |6 | | | | |any******| | | | -|J7 | | |GND | | | | | | | | | | | | -|J8 | | |GND | | | | | | | | | | | | -|J9 | | |GND | | | | | | | | | | | | -|J10 | | |GND | | | | | | | | | | | | -|J11 | | |VCCO_3 | | |3 | | | | |any******| | | | -|J12 | | |VCCO_3 | | |3 | | | | |any******| | | | -|J13 | |DIFFM |IO_L39P_3 |UNUSED | |3 | | | | | | | | | -|J14 | |DIFFS |IO_L39N_3 |UNUSED | |3 | | | | | | | | | -|J15 | | |GND | | | | | | | | | | | | -|J16 | |DIFFS |IO_L40N_3/VREF_3 |UNUSED | |3 | | | | | | | | | -|K1 | |DIFFM |IO |UNUSED | |6 | | | | | | | | | -|K2 | |DIFFM |IO_L24P_6 |UNUSED | |6 | | | | | | | | | -|K3 | |DIFFS |IO_L24N_6/VREF_6 |UNUSED | |6 | | | | | | | | | -|K4 | |DIFFM |IO_L23P_6 |UNUSED | |6 | | | | | | | | | -|K5 | |DIFFS |IO_L23N_6 |UNUSED | |6 | | | | | | | | | -|K6 | | |VCCO_6 | | |6 | | | | |any******| | | | -|K7 | | |GND | | | | | | | | | | | | -|K8 | | |GND | | | | | | | | | | | | -|K9 | | |GND | | | | | | | | | | | | -|K10 | | |GND | | | | | | | | | | | | -|K11 | | |VCCO_3 | | |3 | | | | |any******| | | | -|K12 | |DIFFS |IO_L23N_3 |UNUSED | |3 | | | | | | | | | -|K13 | |DIFFM |IO_L24P_3 |UNUSED | |3 | | | | | | | | | -|K14 | |DIFFS |IO_L24N_3 |UNUSED | |3 | | | | | | | | | -|K15 | |DIFFS |IO |UNUSED | |3 | | | | | | | | | -|K16 | |DIFFM |IO_L40P_3 |UNUSED | |3 | | | | | | | | | -|L1 | | |VCCAUX | | | | | | | |2.5 | | | | -|L2 | |DIFFM |IO_L22P_6 |UNUSED | |6 | | | | | | | | | -|L3 | |DIFFS |IO_L22N_6 |UNUSED | |6 | | | | | | | | | -|L4 | |DIFFM |IO_L21P_6 |UNUSED | |6 | | | | | | | | | -|L5 | |DIFFS |IO_L21N_6 |UNUSED | |6 | | | | | | | | | -|L6 | | |GND | | | | | | | | | | | | -|L7 | | |VCCO_5 | | |5 | | | | |any******| | | | -|L8 | | |VCCO_5 | | |5 | | | | |any******| | | | -|L9 | | |VCCO_4 | | |4 | | | | |any******| | | | -|L10 | | |VCCO_4 | | |4 | | | | |any******| | | | -|L11 | | |GND | | | | | | | | | | | | -|L12 | |DIFFM |IO_L23P_3/VREF_3 |UNUSED | |3 | | | | | | | | | -|L13 | |DIFFS |IO_L21N_3 |UNUSED | |3 | | | | | | | | | -|L14 | |DIFFM |IO_L22P_3 |UNUSED | |3 | | | | | | | | | -|L15 | |DIFFS |IO_L22N_3 |UNUSED | |3 | | | | | | | | | -|L16 | | |VCCAUX | | | | | | | |2.5 | | | | -|M1 | |DIFFM |IO_L20P_6 |UNUSED | |6 | | | | | | | | | -|M2 | |DIFFS |IO_L20N_6 |UNUSED | |6 | | | | | | | | | -|M3 | |DIFFM |IO_L19P_6 |UNUSED | |6 | | | | | | | | | -|M4 | |DIFFS |IO_L19N_6 |UNUSED | |6 | | | | | | | | | -|M5 | | |VCCINT | | | | | | | |1.2 | | | | -|M6 | |DIFFM |IO_L28P_5/D7 |UNUSED | |5 | | | | | | | | | -|M7 | |DIFFM |IO_L30P_5 |UNUSED | |5 | | | | | | | | | -|M8 | | |VCCO_5 | | |5 | | | | |any******| | | | -|M9 | | |VCCO_4 | | |4 | | | | |any******| | | | -|M10 | |DIFFS |IO_L29N_4 |UNUSED | |4 | | | | | | | | | -|M11 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | | -|M12 | | |VCCINT | | | | | | | |1.2 | | | | -|M13 | |DIFFM |IO_L21P_3 |UNUSED | |3 | | | | | | | | | -|M14 | |DIFFS |IO_L19N_3 |UNUSED | |3 | | | | | | | | | -|M15 | |DIFFM |IO_L20P_3 |UNUSED | |3 | | | | | | | | | -|M16 | |DIFFS |IO_L20N_3 |UNUSED | |3 | | | | | | | | | -|N1 | |DIFFM |IO_L17P_6/VREF_6 |UNUSED | |6 | | | | | | | | | -|N2 | |DIFFS |IO_L17N_6 |UNUSED | |6 | | | | | | | | | -|N3 | |DIFFM |IO_L16P_6 |UNUSED | |6 | | | | | | | | | -|N4 | | |VCCINT | | | | | | | |1.2 | | | | -|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | | -|N6 | |DIFFS |IO_L28N_5/D6 |UNUSED | |5 | | | | | | | | | -|N7 | |DIFFS |IO_L30N_5 |UNUSED | |5 | | | | | | | | | -|N8 | |DIFFM |IO_L32P_5/GCLK2 |UNUSED | |5 | | | | | | | | | -|N9 | |DIFFS |IO_L31N_4/INIT_B |UNUSED | |4 | | | | | | | | | -|N10 | |DIFFM |IO_L29P_4 |UNUSED | |4 | | | | | | | | | -|N11 | |DIFFM |IO_L27P_4/D1 |UNUSED | |4 | | | | | | | | | -|N12 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | -|N13 | | |VCCINT | | | | | | | |1.2 | | | | -|N14 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | | -|N15 | |DIFFM |IO_L17P_3/VREF_3 |UNUSED | |3 | | | | | | | | | -|N16 | |DIFFS |IO_L17N_3 |UNUSED | |3 | | | | | | | | | -|P1 | |DIFFM |IO_L01P_6/VRN_6 |UNUSED | |6 | | | | | | | | | -|P2 | |DIFFS |IO_L16N_6 |UNUSED | |6 | | | | | | | | | -|P3 | | |M0 | | | | | | | | | | | | -|P4 | | |M2 | | | | | | | | | | | | -|P5 | |DIFFM |IO_L27P_5 |UNUSED | |5 | | | | | | | | | -|P6 | |DIFFM |IO_L29P_5/VREF_5 |UNUSED | |5 | | | | | | | | | -|P7 | |IOB |IO |UNUSED | |5 | | | | | | | | | -|P8 | |DIFFS |IO_L32N_5/GCLK3 |UNUSED | |5 | | | | | | | | | -|P9 | |DIFFM |IO_L31P_4/DOUT/BUSY|UNUSED | |4 | | | | | | | | | -|P10 | |DIFFS |IO_L30N_4/D2 |UNUSED | |4 | | | | | | | | | -|P11 | |DIFFS |IO_L28N_4 |UNUSED | |4 | | | | | | | | | -|P12 | |DIFFS |IO_L25N_4 |UNUSED | |4 | | | | | | | | | -|P13 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | -|P14 | |DIFFM |IO_L16P_3 |UNUSED | |3 | | | | | | | | | -|P15 | |DIFFS |IO_L16N_3 |UNUSED | |3 | | | | | | | | | -|P16 | |DIFFS |IO_L01N_3/VRP_3 |UNUSED | |3 | | | | | | | | | -|R1 | |DIFFS |IO_L01N_6/VRP_6 |UNUSED | |6 | | | | | | | | | -|R2 | | |GND | | | | | | | | | | | | -|R3 | |DIFFM |IO_L01P_5/CS_B |UNUSED | |5 | | | | | | | | | -|R4 | |DIFFM |IO_L10P_5/VRN_5 |UNUSED | |5 | | | | | | | | | -|R5 | |DIFFS |IO_L27N_5/VREF_5 |UNUSED | |5 | | | | | | | | | -|R6 | |DIFFS |IO_L29N_5 |UNUSED | |5 | | | | | | | | | -|R7 | |DIFFM |IO_L31P_5/D5 |UNUSED | |5 | | | | | | | | | -|R8 | | |GND | | | | | | | | | | | | -|R9 | |DIFFS |IO_L32N_4/GCLK1 |UNUSED | |4 | | | | | | | | | -|R10 | |DIFFM |IO_L30P_4/D3 |UNUSED | |4 | | | | | | | | | -|R11 | |DIFFM |IO_L28P_4 |UNUSED | |4 | | | | | | | | | -|R12 | |DIFFM |IO_L25P_4 |UNUSED | |4 | | | | | | | | | -|R13 | |DIFFS |IO_L01N_4/VRP_4 |UNUSED | |4 | | | | | | | | | -|R14 | | |DONE | | | | | | | | | | | | -|R15 | | |GND | | | | | | | | | | | | -|R16 | |DIFFM |IO_L01P_3/VRN_3 |UNUSED | |3 | | | | | | | | | -|T1 | | |GND | | | | | | | | | | | | -|T2 | | |M1 | | | | | | | | | | | | -|T3 | |DIFFS |IO_L01N_5/RDWR_B |UNUSED | |5 | | | | | | | | | -|T4 | |DIFFS |IO_L10N_5/VRP_5 |UNUSED | |5 | | | | | | | | | -|T5 | |IOB |IO |UNUSED | |5 | | | | | | | | | -|T6 | | |VCCAUX | | | | | | | |2.5 | | | | -|T7 | |DIFFS |IO_L31N_5/D4 |UNUSED | |5 | | | | | | | | | -|T8 | |IOB |IO/VREF_5 |UNUSED | |5 | | | | | | | | | -|T9 | |DIFFM |IO_L32P_4/GCLK0 |UNUSED | |4 | | | | | | | | | -|T10 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | -|T11 | | |VCCAUX | | | | | | | |2.5 | | | | -|T12 | |IOB |IO |UNUSED | |4 | | | | | | | | | -|T13 | |DIFFM |IO_L01P_4/VRN_4 |UNUSED | |4 | | | | | | | | | -|T14 | |DIFFS |IO |UNUSED | |4 | | | | | | | | | -|T15 | | |CCLK | | | | | | | | | | | | -|T16 | | |GND | | | | | | | | | | | | -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -* Default value. -** This default Pullup/Pulldown value can be overridden in Bitgen. -****** Special VCCO requirements may apply. Please consult the device - family datasheet for specific guideline on VCCO requirements. - - diff --git a/Computer_MiST/Oric Atmos_MiST/storage/readme.txt b/Computer_MiST/Oric Atmos_MiST/storage/readme.txt deleted file mode 100644 index 3d3e0a8e..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/readme.txt +++ /dev/null @@ -1,26 +0,0 @@ -22/01/2012 : Version 0.91 de travail / release working - FR : - Des mises à jour pour debugger - Correction de bugs. - - GB - Many upadates to debug - Bugs fixes - - -01/02/2010 : Version 0.9 de travail / release working - - Ce n'est pas encore un version fonctionnelle -mais c'est pour bientôt. - It's not running but perhaps tomorrow ? ;-) - -====================================================== -====================================================== - -Merci à / Thanks to : - + MikeJ de www.fpgaarcade.com pour avoir mis à disposition une - version de AY-3-8192 qui a permis de corriger la mienne et pour - le source du VIA 6522, - + Gregory Estrade de www.torlus.com (pour son aide et son libre accès -à son code vhdl) - + Daniel Wallner pour le T65 (www.opencores.org) diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/BMP.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/BMP.vhd deleted file mode 100644 index d53659dd..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/BMP.vhd +++ /dev/null @@ -1,47 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:49:44 12/03/2009 --- Design Name: --- Module Name: BMP - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity BMP is -end BMP; - -architecture Behavioral of BMP is - -begin - --- Header --- MAGIC NUMBER : 2 octets 'BM' --- Size of bitmap : 4 octets --- Reserved : 2 octets --- Reserved : 2 octets --- Offset : 4 octets - - - -end Behavioral; - diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/DISP_HEX.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/DISP_HEX.vhd deleted file mode 100644 index fc91b9a9..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/DISP_HEX.vhd +++ /dev/null @@ -1,80 +0,0 @@ --- Listing 4.15 -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -entity disp_hex_mux is - port( - clk, reset: in std_logic; - hex3, hex2, hex1, hex0: in std_logic_vector(3 downto 0); - dp_in: in std_logic_vector(3 downto 0); - an: out std_logic_vector(3 downto 0); - sseg: out std_logic_vector(7 downto 0) - ); -end disp_hex_mux ; - -architecture arch of disp_hex_mux is - -- each 7-seg led enabled (2^18/4)*25 ns (40 ms) - constant N: integer:=18; - signal q_reg, q_next: unsigned(N-1 downto 0); - signal sel: std_logic_vector(1 downto 0); - signal hex: std_logic_vector(3 downto 0); - signal dp: std_logic; -begin - -- register - process(clk,reset) - begin - if reset='1' then - q_reg <= (others=>'0'); - elsif (clk'event and clk='1') then - q_reg <= q_next; - end if; - end process; - - -- next-state logic for the counter - q_next <= q_reg + 1; - - -- 2 MSBs of counter to control 4-to-1 multiplexing - sel <= std_logic_vector(q_reg(N-1 downto N-2)); - process(sel,hex0,hex1,hex2,hex3,dp_in) - begin - case sel is - when "00" => - an <= "1110"; - hex <= hex0; - dp <= dp_in(0); - when "01" => - an <= "1101"; - hex <= hex1; - dp <= dp_in(1); - when "10" => - an <= "1011"; - hex <= hex2; - dp <= dp_in(2); - when others => - an <= "0111"; - hex <= hex3; - dp <= dp_in(3); - end case; - end process; - -- hex-to-7-segment led decoding - with hex select - sseg(6 downto 0) <= - "0000001" when "0000", - "1001111" when "0001", - "0010010" when "0010", - "0000110" when "0011", - "1001100" when "0100", - "0100100" when "0101", - "0100000" when "0110", - "0001111" when "0111", - "0000000" when "1000", - "0000100" when "1001", - "0001000" when "1010", --a - "1100000" when "1011", --b - "0110001" when "1100", --c - "1000010" when "1101", --d - "0110000" when "1110", --e - "0111000" when others; --f - -- decimal point - sseg(7) <= dp; -end arch; \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/DISP_UNIT.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/DISP_UNIT.vhd deleted file mode 100644 index fc91b9a9..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/DISP_UNIT.vhd +++ /dev/null @@ -1,80 +0,0 @@ --- Listing 4.15 -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -entity disp_hex_mux is - port( - clk, reset: in std_logic; - hex3, hex2, hex1, hex0: in std_logic_vector(3 downto 0); - dp_in: in std_logic_vector(3 downto 0); - an: out std_logic_vector(3 downto 0); - sseg: out std_logic_vector(7 downto 0) - ); -end disp_hex_mux ; - -architecture arch of disp_hex_mux is - -- each 7-seg led enabled (2^18/4)*25 ns (40 ms) - constant N: integer:=18; - signal q_reg, q_next: unsigned(N-1 downto 0); - signal sel: std_logic_vector(1 downto 0); - signal hex: std_logic_vector(3 downto 0); - signal dp: std_logic; -begin - -- register - process(clk,reset) - begin - if reset='1' then - q_reg <= (others=>'0'); - elsif (clk'event and clk='1') then - q_reg <= q_next; - end if; - end process; - - -- next-state logic for the counter - q_next <= q_reg + 1; - - -- 2 MSBs of counter to control 4-to-1 multiplexing - sel <= std_logic_vector(q_reg(N-1 downto N-2)); - process(sel,hex0,hex1,hex2,hex3,dp_in) - begin - case sel is - when "00" => - an <= "1110"; - hex <= hex0; - dp <= dp_in(0); - when "01" => - an <= "1101"; - hex <= hex1; - dp <= dp_in(1); - when "10" => - an <= "1011"; - hex <= hex2; - dp <= dp_in(2); - when others => - an <= "0111"; - hex <= hex3; - dp <= dp_in(3); - end case; - end process; - -- hex-to-7-segment led decoding - with hex select - sseg(6 downto 0) <= - "0000001" when "0000", - "1001111" when "0001", - "0010010" when "0010", - "0000110" when "0011", - "1001100" when "0100", - "0100100" when "0101", - "0100000" when "0110", - "0001111" when "0111", - "0000000" when "1000", - "0000100" when "1001", - "0001000" when "1010", --a - "1100000" when "1011", --b - "0110001" when "1100", --c - "1000010" when "1101", --d - "0110000" when "1110", --e - "0111000" when others; --f - -- decimal point - sseg(7) <= dp; -end arch; \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/RAM.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/RAM.vhd deleted file mode 100644 index 7d19bde6..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/RAM.vhd +++ /dev/null @@ -1,89 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 10:13:33 02/03/2009 --- Design Name: --- Module Name: RAM - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- --- ----------------------------------------------------------------------- --- --- Syntiac's generic VHDL support files. --- --- ----------------------------------------------------------------------- --- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) --- http://www.syntiac.com/fpga64.html --- ----------------------------------------------------------------------- --- --- gen_ram.vhd --- --- ----------------------------------------------------------------------- --- --- Simple dual port ram: One read and one write port --- --- ----------------------------------------------------------------------- -library IEEE; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - --- ----------------------------------------------------------------------- - -entity ram is - generic ( - dWidth : integer := 8; - aWidth : integer := 16 - ); - port ( - clk : in std_logic; - we : in std_logic; - addr : in std_logic_vector((aWidth-1) downto 0); - d : in std_logic_vector((dWidth-1) downto 0); - q : out std_logic_vector((dWidth-1) downto 0) - ); -end entity; - --- ----------------------------------------------------------------------- - -architecture rtl of ram is - type RAM_ARRAY is array(0 to 65535) of std_logic_vector(7 downto 0); - signal RAM : RAM_ARRAY := ((others=> (others=>'0'))); - signal rAddrReg : std_logic_vector((aWidth-1) downto 0); - signal qReg : std_logic_vector((dWidth-1) downto 0); -begin - --- ----------------------------------------------------------------------- --- Memory write --- ----------------------------------------------------------------------- - process(clk) - begin - if rising_edge(clk) then - if we = '0' then - RAM(to_integer(unsigned(addr))) <= d; - end if; - end if; - end process; - --- ----------------------------------------------------------------------- --- Memory read --- ----------------------------------------------------------------------- - process(clk) - begin - if rising_edge(clk) then - rAddrReg <= addr; - end if; - end process; - q <= RAM(to_integer(unsigned(rAddrReg))); -end rtl; - diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/SRAM.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/SRAM.vhd deleted file mode 100644 index a85cba3e..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/SRAM.vhd +++ /dev/null @@ -1,69 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity SRAM is - port( - A : in std_logic_vector(15 downto 0); - - nOE : in std_logic; - nWE : in std_logic; - - nCE1 : in std_logic; - nUB1 : in std_logic; - nLB1 : in std_logic; - - D : inout std_logic_vector(7 downto 0) - ); -end SRAM; - -architecture sim of SRAM is --- write timings : -constant Thzwe : time := 6 ns; -- nWE LOW to High-Z Output --- read timings : -constant Taa : time := 12 ns; -- address access time - -constant numWords : integer := 65536; -- 262144 max; -type memType is array (numWords-1 downto 0) of std_logic_vector( 7 downto 0); -signal memory : memType := (others => (others => '0')); - -begin - -rdMem: process (nCE1, nWE, nOE, nUB1, nLB1, A) -begin - D <= (others => 'Z'); -- defaults to hi-Z - - if nCE1 = '0' then - if nOE = '0' then - if nWE = '1' then - if nUB1 = '1' and nLB1 = '0' then - D <= memory(conv_integer(to_x01(A))) after Taa; - else - assert false report "%W : nUB1 and nLB1 are both deasserted during ram read" severity warning; - end if; - else - assert false report "%W : signal assertion violation : nOE and nWE asserted" severity warning; - end if; - end if; - end if; -end process; - - -wrMem: process (nCE1, nWE, nOE, A, D) -begin -if nCE1 = '0' then - if nWE= '0' then - if nOE = '1' then - memory(conv_integer(to_x01(A))) <= D(7 downto 0) after Thzwe; - else - assert false report "%W : ubL and lbL are both deasserted during ram write" severity warning; - end if; - -- else - -- assert false report "%W : signal assertion violation : oeL and weL asserted" severity warning; - end if; -end if; - -end process; - -end sim; diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/T1.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/T1.vhd deleted file mode 100644 index b92cc357..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/T1.vhd +++ /dev/null @@ -1,152 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 09:44:36 03/10/2011 --- Design Name: --- Module Name: /home/will/Documents/VHDL/PROJET/OricinFPGA/T1.vhd --- Project Name: OricinFPGA --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ORIC --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY T1 IS -END T1; - -ARCHITECTURE behavior OF T1 IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT ORIC - PORT( - AD : INOUT std_logic_vector(17 downto 0); - OE_SRAMn : OUT std_logic; - WE_SRAMn : OUT std_logic; - CE_SRAMn : OUT std_logic; - UB_SRAMn : OUT std_logic; - LB_SRAMn : OUT std_logic; - RW : OUT std_logic; - D : INOUT std_logic_vector(7 downto 0); - RESETn : IN std_logic; - PS2_CLK : IN std_logic; - PS2_DATA : IN std_logic; - VIDEO_R : OUT std_logic; - VIDEO_G : OUT std_logic; - VIDEO_B : OUT std_logic; - VIDEO_SYNC : OUT std_logic; - CLK_50 : IN std_logic; - btn : IN std_logic_vector(3 downto 0); - an : OUT std_logic_vector(3 downto 0); - sseg : OUT std_logic_vector(7 downto 0) - ); - END COMPONENT; - - - --Inputs - signal RESETn : std_logic := '0'; - signal PS2_CLK : std_logic := '0'; - signal PS2_DATA : std_logic := '0'; - signal CLK_50 : std_logic := '0'; - signal btn : std_logic_vector(3 downto 0) := (others => '0'); - - --BiDirs - signal AD : std_logic_vector(17 downto 0); - signal D : std_logic_vector(7 downto 0); - - --Outputs - signal OE_SRAMn : std_logic; - signal WE_SRAMn : std_logic; - signal CE_SRAMn : std_logic; - signal UB_SRAMn : std_logic; - signal LB_SRAMn : std_logic; - signal RW : std_logic; - signal VIDEO_R : std_logic; - signal VIDEO_G : std_logic; - signal VIDEO_B : std_logic; - signal VIDEO_SYNC : std_logic; - signal an : std_logic_vector(3 downto 0); - signal sseg : std_logic_vector(7 downto 0); - - -- Clock period definitions - constant PS2_CLK_period : time := 10 ns; - constant CLK_50_period : time := 10 ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ORIC PORT MAP ( - AD => AD, - OE_SRAMn => OE_SRAMn, - WE_SRAMn => WE_SRAMn, - CE_SRAMn => CE_SRAMn, - UB_SRAMn => UB_SRAMn, - LB_SRAMn => LB_SRAMn, - RW => RW, - D => D, - RESETn => RESETn, - PS2_CLK => PS2_CLK, - PS2_DATA => PS2_DATA, - VIDEO_R => VIDEO_R, - VIDEO_G => VIDEO_G, - VIDEO_B => VIDEO_B, - VIDEO_SYNC => VIDEO_SYNC, - CLK_50 => CLK_50, - btn => btn, - an => an, - sseg => sseg - ); - - -- Clock process definitions - PS2_CLK_process :process - begin - PS2_CLK <= '0'; - wait for PS2_CLK_period/2; - PS2_CLK <= '1'; - wait for PS2_CLK_period/2; - end process; - - CLK_50_process :process - begin - CLK_50 <= '0'; - wait for CLK_50_period/2; - CLK_50 <= '1'; - wait for CLK_50_period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100 ns. - wait for 100 ns; - - wait for PS2_CLK_period*10; - - -- insert stimulus here - - wait; - end process; - -END; diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/ULA_LOG.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/ULA_LOG.vhd deleted file mode 100644 index 51b70067..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/ULA_LOG.vhd +++ /dev/null @@ -1,81 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:12:00 08/14/2011 --- Design Name: --- Module Name: ula_log - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -use std.textio.all; -use work.txt_util.all; - -entity ula_log is - generic ( - log_ula: string := "ula.log" - ); - port( - CLK : in std_logic; - RST : in std_logic; - x1 : in std_logic_vector(7 downto 0); - x2 : in std_logic_vector(15 downto 0); - x3 : in std_logic - ); -end ula_log; - -architecture log_to_file of ula_log is - -file l_file_ula: TEXT open write_mode is log_ula; - -begin - --- write data and control information to a file - -receive_data: process (CLK,RST) - -variable l: line; -variable cnt : integer:=0; - -begin - if (RST = '0') then - print(l_file_ula, "---- 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23"); - - elsif (clk'event and clk='0') then - -- Low period of PHI2 - if (x3 ='0') then - if (cnt = 0) then - write (l, hstr(x2) & " " & hstr(x1) & " "); - else - -- Je récupére que le code ASCII - if (cnt mod 2 = 0) then - write(l, hstr(x1) & " "); - end if; - end if; - - cnt:=cnt+1; - - -- Il y a 64 pixels dont 40 utiles par ligne et deux accès à la mémoire donc 64 X 2 = 128 - if (cnt = 128) then - writeline(l_file_ula, l); - cnt:=0; - end if; - end if; - end if; - -end process receive_data; - -end log_to_file; - \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/U_ULA_LGO.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/U_ULA_LGO.vhd deleted file mode 100644 index 1b8e2174..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/U_ULA_LGO.vhd +++ /dev/null @@ -1,41 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 10:21:17 12/18/2011 --- Design Name: --- Module Name: U_ULA_LGO - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity U_ULA_LGO is -end U_ULA_LGO; - -architecture Behavioral of U_ULA_LGO is - -begin - - -end Behavioral; - diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/file_log.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/file_log.vhd deleted file mode 100644 index f1a5bc64..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/file_log.vhd +++ /dev/null @@ -1,67 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:00:59 03/08/2011 --- Design Name: --- Module Name: file_log - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -use std.textio.all; -use work.txt_util.all; - -entity FILE_LOG is - generic ( - log_file: string := "res.log" - ); - port( - CLK : in std_logic; - RST : in std_logic; - x1 : in std_logic_vector(7 downto 0); - x2 : in std_logic_vector(7 downto 0); - x3 : in std_logic_vector(15 downto 0); - x4 : in std_logic_vector(2 downto 0); - x5 : in std_logic - ); -end FILE_LOG; - - -architecture log_to_file of FILE_LOG is - -file l_file: TEXT open write_mode is log_file; - -begin - --- write data and control information to a file - -receive_data: process (CLK,RST) - -variable l: line; - -begin - if (RST = '0') then - print(l_file, "#x3(AD) x1(IN) x2(OUT) RGB SYNC"); - print(l_file, "#------------------------------------"); - print(l_file, " "); - elsif (clk'event and clk='1') then - write(l, hstr(x3)& " " & hstr(x1) & "h " & hstr(x2)& "h " &hstr(x4)& "h " &chr(x5)); - writeline(l_file, l); - end if; - -end process receive_data; - -end log_to_file; - \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/gen_clk.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/gen_clk.vhd deleted file mode 100644 index 5def2c8d..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/gen_clk.vhd +++ /dev/null @@ -1,44 +0,0 @@ --- --- GEN_CLK.vhd --- --- GENERATOR of CLOCK. --- --- Copyright (C)2001 SEILEBOST --- All rights reserved. --- --- $Id: GEN_CLK.vhd, v0.42 2002/01/03 00:00:00 SEILEBOST $ --- --- Generate secondary CLK from CLK_MASTER --- CLK : Clock Master, 16 MHz --- CLK_16 : for the tone generator, --- CLK_256 : for the envelope generator - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -entity GEN_CLK is - Port ( CLK : in std_logic; - RST : in std_logic; - CLK_16 : out std_logic; - CLK_256 : out std_logic - ); -end GEN_CLK; - -architecture Behavioral of GEN_CLK is - -SIGNAL COUNT : std_logic_vector(7 downto 0); -begin - - PROCESS(CLK, RST) - BEGIN - if (RST = '1') then - COUNT <= (OTHERS => '0'); - elsif (CLK'event and CLK = '1') then - COUNT <= COUNT + 1; - CLK_16 <= COUNT(3); - CLK_256 <= COUNT(7); - end if; - END PROCESS; -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/i_pn_gen.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/i_pn_gen.vhd deleted file mode 100644 index 927558be..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/i_pn_gen.vhd +++ /dev/null @@ -1,100 +0,0 @@ --- --- fg.vhd --- --- Generate a random noise. --- --- Copyright (C)2001 SEILEBOST --- All rights reserved. --- --- $Id: fg.vhd, v0.3 2001/11/14 00:00:00 SEILEBOST $ --- --- from XAPP211.pdf & XAPP211.ZIP (XILINX APPLICATION) --- ---The following is example code that implements one LFSR which can be used as part of pn generators. ---The number of taps, tap points, and LFSR width are parameratizable. When targetting Xilinx (Virtex) ---all the latest synthesis vendors (Leonardo, Synplicity, and FPGA Express) will infer the shift ---register LUTS (SRL16) resulting in a very efficient implementation. --- ---Control signals have been provided to allow external circuitry to control such things as filling, ---puncturing, stalling (augmentation), etc. --- ---Mike Gulotta ---11/4/99 ---Revised 3/17/00: Fixed "commented" block diagram to match polynomial. --- --- ---################################################################################################### --- I Polinomials: # --- I(x) = X**17 + X**2 + 1 # --- # --- LFSR implementation format examples: # ---################################################################################################### --- # --- I(x) = X**17 + X**2 + 1 # --- ________ # --- | |<<......................... # --- | Parity | | # --- .................| |<<... | # --- | |________| | | # --- | | | # --- | __________________ | ___ ___ | # --- |...|\ | | | | | | | | | pn_out_i # --- ||-->>| 16 | - - - -| 2 |-----| 1 | 0 | >>---------->> # ---DataIn_i.|/ |____|________|____| |___|___| # --- | srl_i # --- FillSel..| # --- ---> shifting -->> # - -library ieee ; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity i_pn_gen is - generic(NumOfTaps_i : integer := 2; -- # of taps for I channel LFSR, including output tap. - Width : integer := 17); -- LFSR length (ie, total # of storage elements) - port(clk, ShiftEn, FillSel, DataIn_i, RESET : in std_logic; - pn_out_i : out std_logic); -end i_pn_gen ; - - -architecture rtl of i_pn_gen is - - type TapPointArray_i is array (NumOfTaps_i-1 downto 0) of integer; - constant Tap_i : TapPointArray_i := (2, 0); - signal srl_i : std_logic_vector(Width-1 downto 0); -- shift register. - signal par_fdbk_i : std_logic_vector(NumOfTaps_i downto 0); -- Parity feedback. - signal lfsr_in_i : std_logic; -- mux output. - - -begin - ---------------------------------------------------------------------- ------------------- I Channel ---------------------------------------- ---------------------------------------------------------------------- - - Shift_i : process (clk, reset) - begin - if (RESET = '1') then - SRL_I <= "00000000000000000"; - elsif clk'event and clk = '1' then - if (ShiftEn = '1') then - srl_i <= lfsr_in_i & srl_i(srl_i'high downto 1); - end if; - end if; - end process; - - par_fdbk_i(0) <= '0'; - - fdbk_i : for X in 0 to Tap_i'high generate -- parity generator - par_fdbk_i(X+1) <= par_fdbk_i(X) xor srl_i(Tap_i(X)); - end generate fdbk_i; - - lfsr_in_i <= DataIn_i when FillSel = '1' else par_fdbk_i(par_fdbk_i'high); - - pn_out_i <= srl_i(srl_i'low); -- PN I channel output. - - -end rtl; - - - diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/mixer.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/mixer.vhd deleted file mode 100644 index 7eae38b1..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/mixer.vhd +++ /dev/null @@ -1,80 +0,0 @@ --- --- MIXER.vhd --- --- Mix tone generator and noise generator. --- --- Copyright (C)2001-2010 SEILEBOST --- All rights reserved. --- --- $Id: MIXER.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $ --- --- A lot of work !! --- ATTENTION : IT'S NOT USED !! - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; - -entity MIXER is - Port ( CLK : in std_logic; - CS : in std_logic; - RST : in std_logic; - WR : in std_logic; - IN_A : in std_logic; - IN_B : in std_logic; - IN_C : in std_logic; - IN_NOISE : in std_logic; - DATA : in std_logic_vector(5 downto 0); - OUT_A : out std_logic; - OUT_B : out std_logic; - OUT_C : out std_logic ); -end MIXER; - -architecture Behavioral of MIXER is - - -begin - PROCESS(CLK, RST, CS, WR, DATA, IN_A, IN_B, IN_C, IN_NOISE) - BEGIN - if (RST = '1') then - OUT_A <= '0'; - OUT_B <= '0'; - OUT_C <= '0'; - elsif ( CLK'event and CLK = '1') then - if not (CS = '1' and WR = '1') then --- TONE A - if (DATA(0) = '0') then - if (DATA(3) = '0') then - OUT_A <= IN_A xor IN_NOISE; - else - OUT_A <= IN_A; - end if; - else - OUT_A <= '1'; - end if; - --- TONE B - if (DATA(1) = '0') then - if (DATA(4) = '0') then - OUT_B <= IN_B xor IN_NOISE; - else - OUT_B <= IN_B; - end if; - else - OUT_B <= '1'; - end if; - --- TONE C - if (DATA(2) = '0') then - if (DATA(5) = '0') then - OUT_C <= IN_C xor IN_NOISE; - else - OUT_C <= IN_C; - end if; - else - OUT_C <= '1'; - end if; - end if; - end if; - end process; -end Behavioral; diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/oa_test.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/oa_test.vhd deleted file mode 100644 index 665353b5..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/oa_test.vhd +++ /dev/null @@ -1,313 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 23:36:12 10/10/2009 --- Design Name: --- Module Name: D:/Documents and Settings/JO/Mes documents/Projet/ORICATMOS/VERSION_2009_ISE_10.1/OA200906/tb_oa.vhd --- Project Name: OA2009 --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ORIC --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Revision 0.02 - 18/11/2009 : Test keyboard by PS2 --- Revision 0.03 - 23/11/2009 : Correction protocol PS2 --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -library std; -use std.textio.all; -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; -use ieee.std_logic_textio.all; - -ENTITY oa_test IS -END oa_test; - -ARCHITECTURE behavior OF oa_test IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT ORIC - PORT( - AD : INOUT std_logic_vector(17 downto 0); - OE_SRAMn : out std_logic; - WE_SRAMn : out std_logic; - CE_SRAMn : out std_logic; - --MAPn : IN std_logic; - --ROMDISn : IN std_logic; - --IRQn : IN std_logic; - --CLK_EXT : OUT std_logic; - RW : OUT std_logic; - --IO : OUT std_logic; - --IOCONTROL : IN std_logic; - D : INOUT std_logic_vector(7 downto 0); - RESETn : IN std_logic; - PS2_CLK : IN std_logic; - PS2_DATA : IN std_logic; - --K7_TAPEIN : IN std_logic; - --K7_TAPEOUT : OUT std_logic; - --K7_REMOTE : OUT std_logic; - --K7_AUDIOOUT : OUT std_logic; - --AUDIO_OUT : OUT std_logic_vector(2 downto 0); - VIDEO_R : OUT std_logic; - VIDEO_G : OUT std_logic; - VIDEO_B : OUT std_logic; - --VIDEO_HSYNC : OUT std_logic; - --VIDEO_VSYNC : OUT std_logic; - VIDEO_SYNC : OUT std_logic; - --PRT_DATA : INOUT std_logic_vector(7 downto 0); - --PRT_STR : OUT std_logic; - --PRT_ACK : IN std_logic; - CLK_50 : IN std_logic - --DBG_ROM_DOUT : OUT std_logic_vector(7 downto 0); - --DBG_ULA_AD : OUT std_logic_vector(15 downto 0) - ); - END COMPONENT; - - - --Inputs - --signal MAPn : std_logic := '0'; - --signal ROMDISn : std_logic := '0'; - --signal IRQn : std_logic := '0'; - --signal IOCONTROL : std_logic := '0'; - signal RESETn : std_logic := '0'; - signal PS2_CLK : std_logic := '0'; - signal PS2_DATA : std_logic := '0'; - --signal K7_TAPEIN : std_logic := '0'; - --signal PRT_ACK : std_logic := '0'; - signal CLK_12 : std_logic := '0'; - - --BiDirs - signal AD : std_logic_vector(17 downto 0); - signal D : std_logic_vector(7 downto 0); - --signal PRT_DATA : std_logic_vector(7 downto 0); - - --Outputs - --signal CLK_EXT : std_logic; - signal RW : std_logic; - --signal IO : std_logic; - --signal K7_TAPEOUT : std_logic; - --signal K7_REMOTE : std_logic; - --signal K7_AUDIOOUT : std_logic; - --signal AUDIO_OUT : std_logic_vector(2 downto 0); - signal VIDEO_R : std_logic; - signal VIDEO_G : std_logic; - signal VIDEO_B : std_logic; - --signal VIDEO_HSYNC : std_logic; - --signal VIDEO_VSYNC : std_logic; - signal VIDEO_SYNC : std_logic; - --signal PRT_STR : std_logic; - --signal DBG_ROM_DOUT : std_logic_vector(7 downto 0); - --signal DBG_ULA_AD : std_logic_vector(15 downto 0); - - --signal AD_SRAM : std_logic_vector(15 downto 0); - signal OE_SRAM : std_logic; - signal CE_SRAM : std_logic; - signal WE_SRAM : std_logic; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ORIC PORT MAP ( - --AD => AD, - AD => AD, - OE_SRAMn => OE_SRAM, - WE_SRAMn => WE_SRAM, - CE_SRAMn => CE_SRAM, - --MAPn => MAPn, - --ROMDISn => ROMDISn, - --IRQn => IRQn, - --CLK_EXT => CLK_EXT, - RW => RW, - --IO => IO, - --IOCONTROL => IOCONTROL, - D => D, - RESETn => RESETn, - PS2_CLK => PS2_CLK, - PS2_DATA => PS2_DATA, - --K7_TAPEIN => K7_TAPEIN, - --K7_TAPEOUT => K7_TAPEOUT, - --K7_REMOTE => K7_REMOTE, - --K7_AUDIOOUT => K7_AUDIOOUT, - --AUDIO_OUT => AUDIO_OUT, - VIDEO_R => VIDEO_R, - VIDEO_G => VIDEO_G, - VIDEO_B => VIDEO_B, - --VIDEO_HSYNC => VIDEO_HSYNC, - --VIDEO_VSYNC => VIDEO_VSYNC, - VIDEO_SYNC => VIDEO_SYNC, - --PRT_DATA => PRT_DATA, - --PRT_STR => PRT_STR, - --PRT_ACK => PRT_ACK, - CLK_50 => CLK_12 - --DBG_ROM_DOUT => DBG_ROM_DOUT, - --DBG_ULA_AD => DBG_ULA_AD - ); - - ------------------------------------------------------------ - -- GESTION SRAM - ------------------------------------------------------------ - ramv : entity work.sram - port map - ( - A => AD, - nOE => OE_SRAM, - nWE => WE_SRAM, - nCE1 => CE_SRAM, - nUB1 => '1', - nLB1 => '0', - D => D - ); - - -- No clocks detected in port list. Replace below with - -- appropriate port name - - --18/11/2009 ne fonctionne pas ... constant CLK_12_period : TIME := 2ns; - - CLK_12_process :process - begin - CLK_12 <= '0'; - wait for 20ns; - CLK_12 <= '1'; - wait for 20ns; - end process; - - tb_RESET : PROCESS - BEGIN - RESETn <= '0'; - wait for 1000 ns; - RESETn <= '1'; - wait; -- will wait forever - END PROCESS; - - tb_IN : PROCESS - BEGIN - --MAPn <= '1'; - --ROMDISn <= '1'; - --IRQn <= '1'; - --IOCONTROL <= '0'; - --K7_TAPEIN <= '0'; - --PRT_ACK <= '0'; - wait; -- will wait forever - END PROCESS; - - -- Stimulus process - tb_keyboard : process - file file_in : text open read_mode is "./scenario.txt"; - variable line_in : line; - variable cmd : character; - variable delay : time; - variable sig : std_logic; - variable char : std_logic_vector(7 downto 0); -begin - - loop - readline(file_in, line_in); - --exit when endfile(file_in); - - read(line_in, cmd); - exit when cmd = 'W' -- Wait - or cmd = 'E' -- End - or cmd = 'K'; -- Keyboard - end loop; - - --if not endfile(file_in) then - case cmd is - - when 'W' => - read(line_in, delay); - PS2_CLK <= '1'; -- Ajout du 23/11/2009 - PS2_DATA <= '1'; -- Ajout du 23/11/2009 - wait for delay; - - when 'K' => - read(line_in, char); - -PS2_DATA <= '0'; -- Start Bit - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(0); -- LSB - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(1); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(2); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(3); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(4); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(5); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(6); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(7); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= '0'; -- Parity (don't care) - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= '1'; -- Stop Bit - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; - - when 'E' => - PS2_CLK <= '1'; - PS2_DATA <= 'Z'; - wait; - - when others => - - end case; - --else - -- PS2_CLK <= '1'; - -- PS2_DATA <= 'Z'; - -- wait; - --end if; - -end process; - -END; \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/oric_ps2_if.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/oric_ps2_if.vhd deleted file mode 100644 index cbbd72ce..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/oric_ps2_if.vhd +++ /dev/null @@ -1,311 +0,0 @@ --- --- A simulation model of VIC20 hardware --- Copyright (c) MikeJ - March 2003 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERoricES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email vic20@fpgaarcade.com --- --- --- Revision list --- --- version 001 initial release --- version 002 Modify for oric atmos project - --- ps2 interface returns keyboard press/release scan codes --- these are mapped into a small ram which is harassed by the --- VIA chip in the same way as the original keyboard. --- --- Restore key mapped to PgUp --- --- all cursor keys are directly mapped --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - LIBRARY WORK; - use work.pack_oric_xilinx_prims.all; - LIBRARY WORK; - use work.pkg_oric.all; - -entity oric_PS2_IF is - port ( - PS2_CLK : in std_logic; - PS2_DATA : in std_logic; - - COL_IN : in std_logic_vector(7 downto 0); - ROW_IN : in std_logic_vector(7 downto 0); - RESTORE : out std_logic; - - RESET_L : in std_logic; - ENA_1MHZ : in std_logic; - P2_H : in std_logic; -- high for phase 2 clock ____----__ - CLK_4 : in std_logic -- 4x system clock (4MHZ) _-_-_-_-_- - ); -end; - -architecture RTL of oric_PS2_IF is - - component ps2kbd - port( - Rst_n : in std_logic; - Clk : in std_logic; - Tick1us : in std_logic; - PS2_Clk : in std_logic; - PS2_Data : in std_logic; - Press : out std_logic; - Release : out std_logic; - Reset : out std_logic; - ScanE0 : out std_logic; - ScanCode : out std_logic_vector(7 downto 0)); - end component; - - signal tick_1us : std_logic; - signal kbd_press : std_logic; - signal kbd_release : std_logic; - signal kbd_reset : std_logic; - signal kbd_press_s : std_logic; - signal kbd_release_s : std_logic; - signal kbd_scancode : std_logic_vector(7 downto 0); - signal kbd_scanE0 : std_logic; - - signal rowcol : std_logic_vector(5 downto 0); - - signal ram_w_addr : std_logic_vector(5 downto 0); - signal ram_r_addr : std_logic_vector(5 downto 0); - signal ram_we : std_ulogic; - signal ram_din : std_logic; - signal ram_dout : std_logic; - - signal reset_cnt : std_logic_vector(6 downto 0); - -begin - - -- oric standard: - -- - -- | 1! 2@ 3# 4$ 5% 6^ 7& 8* 9( 0) -£ =+ \| | - -- | ESC q w e r t y u i o p [{ ]} DEL | - -- | CTRL a s d f g h j k l ;: '" RETURN | - -- | SHIFT z x c v b n m ,< .> /? SHIFT | - -- | LFT DWN |___________SPACE___________| UP RGT FUNCT | - ---------------------------------------------------------------- - - tick_1us <= ENA_1MHZ; - --- Keyboard decoder -u_kbd : ps2kbd - port map( - Rst_n => RESET_L, - Clk => CLK_4, - Tick1us => tick_1us, - PS2_Clk => PS2_CLK, - PS2_Data => PS2_DATA, - Press => kbd_press, - Release => kbd_release, - Reset => kbd_reset, - ScanE0 => kbd_scanE0, - ScanCode => kbd_scancode - ); - --- Generate ram for scancode translation ---kbd_ram : RAM64X1D --- port map ( - -- a0 => ram_w_addr(0), - -- a1 => ram_w_addr(1), - -- a2 => ram_w_addr(2), - -- a3 => ram_w_addr(3), - -- a4 => ram_w_addr(4), - -- a5 => ram_w_addr(5), - -- dpra0 => ram_r_addr(0), - -- dpra1 => ram_r_addr(1), - -- dpra2 => ram_r_addr(2), - -- dpra3 => ram_r_addr(3), - -- dpra4 => ram_r_addr(4), - -- dpra5 => ram_r_addr(5), - -- wclk => CLK_4, - -- we => ram_we, - -- d => ram_din, - -- dpo => ram_dout, - -- ); - --- Translate scancode from PS2 to scancode for oric -kbd_decode_scancode : process -begin - wait until rising_edge(CLK_4); - - -- rowcol is valid for lots of clocks, but kbd_press / release are single - -- clock strobes. must sync these to p2_h - if (kbd_press = '1') then - kbd_press_s <= '1'; - elsif (P2_H = '0') then - kbd_press_s <= '0'; - end if; - - if (kbd_release = '1') then - kbd_release_s <= '1'; - elsif (P2_H = '0') then - kbd_release_s <= '0'; - end if; - - -- top bit low for keypress - if (kbd_scanE0 = '0') then - rowcol <= "111111"; - case kbd_scancode is - -- row/col oric ps2 - when x"3D" => rowcol <= "000000";-- 7 7 - when x"31" => rowcol <= "000001";-- n n - when x"2E" => rowcol <= "000010";-- 5 5 - when x"2A" => rowcol <= "000011";-- v v - when x"16" => rowcol <= "000101";-- 1 1 - when x"22" => rowcol <= "000110";-- x x - when x"26" => rowcol <= "000111";-- 3 3 - - when x"3B" => rowcol <= "001000";-- j j - when x"2C" => rowcol <= "001001";-- t t - when x"2D" => rowcol <= "001010";-- r r - when x"2B" => rowcol <= "001011";-- f f - when x"76" => rowcol <= "001101";-- esc esc - when x"15" => rowcol <= "001110";-- q q - when x"23" => rowcol <= "001111";-- d d - - when x"3A" => rowcol <= "010000";-- m m - when x"36" => rowcol <= "010001";-- 6 6 - when x"32" => rowcol <= "010010";-- b b - when x"25" => rowcol <= "010011";-- 4 4 - when x"14" => rowcol <= "010100";-- ctrl left_ctrl - when x"1A" => rowcol <= "010101";-- z z - when x"1E" => rowcol <= "010110";-- 2 2 - when x"21" => rowcol <= "010111";-- c c - - when x"42" => rowcol <= "011000";-- k k - when x"46" => rowcol <= "011001";-- 9 9 - when x"4C" => rowcol <= "011010";-- ; ; - when x"4E" => rowcol <= "011011";-- - - - when x"5D" => rowcol <= "011110";-- \ \ - when x"52" => rowcol <= "011111";-- ' ' - - when x"29" => rowcol <= "100000";-- space space - when x"41" => rowcol <= "100001";-- , , - when x"49" => rowcol <= "100010";-- . . - when x"12" => rowcol <= "100100";-- left_shift left_shift - - when x"3C" => rowcol <= "101000";-- u u - when x"43" => rowcol <= "101001";-- i i - when x"44" => rowcol <= "101010";-- o o - when x"4D" => rowcol <= "101011";-- p p - when x"66" => rowcol <= "101101";-- del backspace - when x"5B" => rowcol <= "101110";-- ] ] - when x"54" => rowcol <= "101111";-- [ [ - - - when x"35" => rowcol <= "110000";-- y y - when x"33" => rowcol <= "110001";-- h h - when x"34" => rowcol <= "110010";-- g g - when x"24" => rowcol <= "110011";-- e e - when x"1C" => rowcol <= "110101";-- a a - when x"1B" => rowcol <= "110110";-- s s - when x"1D" => rowcol <= "110111";-- w w - - when x"3E" => rowcol <= "111000";-- 8 8 - when x"4B" => rowcol <= "111001";-- l l - when x"45" => rowcol <= "111010";-- 0 0 - when x"4A" => rowcol <= "111011";-- / / - when x"59" => rowcol <= "111100";-- right_shift right_shift - when x"5A" => rowcol <= "111101";-- return return - when x"55" => rowcol <= "111111";-- = = - when others => rowcol <= "ZZZZZZ"; - end case; - else - rowcol <= "111111"; - case kbd_scancode is - when x"75" => rowcol <= "100011";-- up up_cursor - when x"6B" => rowcol <= "100101";-- left left_cursor - when x"72" => rowcol <= "100110";-- down down_cursor - when x"74" => rowcol <= "100111";-- right right_cursor - when x"11" => rowcol <= "101100";-- fct right_alt - when others => rowcol <= "111111"; - end case; - end if; -end process; - - --- counter used to reset ram -kbd_reset_cnt : process(RESET_L, CLK_4) -begin - if (RESET_L = '0') then - reset_cnt <= "1000000"; - elsif rising_edge(CLK_4) then - if (kbd_reset = '1') then - reset_cnt <= "1000000"; - elsif (reset_cnt(6) = '1') then - reset_cnt <= reset_cnt + "1"; - end if; - end if; -end process; - --- write scancode is pressed -kbd_write : process(kbd_press_s, kbd_release_s, rowcol, kbd_reset, reset_cnt, P2_H) - variable we : boolean; -begin - - -- valid key ? - we := ((kbd_press_s = '1') or (kbd_release_s = '1')); - - if (reset_cnt(6) = '1') then - ram_w_addr <= reset_cnt(5 downto 0); - ram_din <= '0'; - ram_we <= '1'; - else - ram_w_addr <= rowcol; - - if (kbd_press_s = '1') then - ram_din <= '1'; -- pressed - else - ram_din <= '0'; -- released - end if; - - ram_we <= '0'; - if we and (P2_H = '0')then - ram_we <= '1'; - end if; - end if; - -end process; - --- Manage -RESTORE <= '1'; -- To modify ---ram_r_addr <= ROW_IN & COL_IN; - -end architecture RTL; - diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/pack_oric_xilinx_prims.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/pack_oric_xilinx_prims.vhd deleted file mode 100644 index 5c97b711..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/pack_oric_xilinx_prims.vhd +++ /dev/null @@ -1,412 +0,0 @@ --- --- A simulation model of ORIC hardware --- Copyright (c) seilebost - 2001 - 2009 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email seilebost@free.fr --- --- --- Revision list --- --- version 001 initial release - -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -package pack_oric_xilinx_prims is - - attribute INIT : string; - attribute INIT_00 : string; - attribute INIT_01 : string; - attribute INIT_02 : string; - attribute INIT_03 : string; - attribute INIT_04 : string; - attribute INIT_05 : string; - attribute INIT_06 : string; - attribute INIT_07 : string; - attribute INIT_08 : string; - attribute INIT_09 : string; - attribute INIT_0A : string; - attribute INIT_0B : string; - attribute INIT_0C : string; - attribute INIT_0D : string; - attribute INIT_0E : string; - attribute INIT_0F : string; - - attribute RLOC : string; - attribute HU_SET : string; - - function str2slv (str : string) return std_logic_vector; - - - component RAM16X1D - port ( - A0, A1, A2, A3 : in std_logic; - DPRA0, DPRA1, DPRA2, DPRA3 : in std_logic; - WCLK : in std_logic; - WE : in std_logic; - D : in std_logic; - SPO : out std_logic; - DPO : out std_logic - ); - end component; - - component RAMB4_S1 - --pragma translate_off - generic ( - INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DO : out std_logic_vector (0 downto 0); - DI : in std_logic_vector (0 downto 0); - ADDR : in std_logic_vector (11 downto 0); - WE : in std_logic; - EN : in std_logic; - RST : in std_logic; - CLK : in std_logic - ); - end component; - - component RAMB4_S4 - --pragma translate_off - generic ( - INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DO : out std_logic_vector (3 downto 0); - DI : in std_logic_vector (3 downto 0); - ADDR : in std_logic_vector (9 downto 0); - WE : in std_logic; - EN : in std_logic; - RST : in std_logic; - CLK : in std_logic - ); - end component; - - component RAMB4_S8 - --pragma translate_off - generic ( - INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DO : out std_logic_vector (7 downto 0); - DI : in std_logic_vector (7 downto 0); - ADDR : in std_logic_vector (8 downto 0); - WE : in std_logic; - EN : in std_logic; - RST : in std_logic; - CLK : in std_logic - ); - end component; - - component RAMB4_S1_S1 - --pragma translate_off - generic ( - INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DOB : out std_logic_vector (0 downto 0); - DIB : in std_logic_vector (0 downto 0); - ADDRB : in std_logic_vector (11 downto 0); - WEB : in std_logic; - ENB : in std_logic; - RSTB : in std_logic; - CLKB : in std_logic; - - DOA : out std_logic_vector(0 downto 0); - DIA : in std_logic_vector(0 downto 0); - ADDRA : in std_logic_vector (11 downto 0); - WEA : in std_logic; - ENA : in std_logic; - RSTA : in std_logic; - CLKA : in std_logic - ); - end component; - - component RAMB4_S2_S2 - --pragma translate_off - generic ( - INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DOB : out std_logic_vector (1 downto 0); - DIB : in std_logic_vector (1 downto 0); - ADDRB : in std_logic_vector (10 downto 0); - WEB : in std_logic; - ENB : in std_logic; - RSTB : in std_logic; - CLKB : in std_logic; - - DOA : out std_logic_vector (1 downto 0); - DIA : in std_logic_vector (1 downto 0); - ADDRA : in std_logic_vector (10 downto 0); - WEA : in std_logic; - ENA : in std_logic; - RSTA : in std_logic; - CLKA : in std_logic - ); - end component; - - component RAMB4_S4_S4 - --pragma translate_off - generic ( - INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DOB : out std_logic_vector (3 downto 0); - DIB : in std_logic_vector (3 downto 0); - ADDRB : in std_logic_vector (9 downto 0); - WEB : in std_logic; - ENB : in std_logic; - RSTB : in std_logic; - CLKB : in std_logic; - - DOA : out std_logic_vector (3 downto 0); - DIA : in std_logic_vector (3 downto 0); - ADDRA : in std_logic_vector (9 downto 0); - WEA : in std_logic; - ENA : in std_logic; - RSTA : in std_logic; - CLKA : in std_logic - ); - end component; - - component RAMB4_S8_S8 - --pragma translate_off - generic ( - INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DOB : out std_logic_vector (7 downto 0); - DIB : in std_logic_vector (7 downto 0); - ADDRB : in std_logic_vector (8 downto 0); - WEB : in std_logic; - ENB : in std_logic; - RSTB : in std_logic; - CLKB : in std_logic; - - DOA : out std_logic_vector (7 downto 0); - DIA : in std_logic_vector (7 downto 0); - ADDRA : in std_logic_vector (8 downto 0); - WEA : in std_logic; - ENA : in std_logic; - RSTA : in std_logic; - CLKA : in std_logic - ); - end component; - - component PULLUP - port ( - O : out std_logic - ); - end component; - - component BUFG - port ( - I : in std_logic; O: out std_logic - ); - end component; - - component OBUF - port ( - I : in std_logic; O: out std_logic - ); - end component; - - component IBUFG - port ( - I : in std_logic; O: out std_logic - ); - end component; - - component IBUF - port ( - I : in std_logic; O: out std_logic - ); - end component; - - component CLKDLL - port ( - CLKIN, CLKFB, RST : in std_logic; - CLK0,CLK90,CLK180,CLK270,CLK2X,CLKDV,LOCKED : out std_logic - ); - end component; - -end pack_oric_xilinx_prims; - -package body pack_oric_xilinx_prims is - - function str2slv (str : string) return std_logic_vector is - variable result : std_logic_vector (str'length*4-1 downto 0); - begin - for i in 0 to str'length-1 loop - case str(str'high-i) is - when '0' => result(i*4+3 downto i*4) := x"0"; - when '1' => result(i*4+3 downto i*4) := x"1"; - when '2' => result(i*4+3 downto i*4) := x"2"; - when '3' => result(i*4+3 downto i*4) := x"3"; - when '4' => result(i*4+3 downto i*4) := x"4"; - when '5' => result(i*4+3 downto i*4) := x"5"; - when '6' => result(i*4+3 downto i*4) := x"6"; - when '7' => result(i*4+3 downto i*4) := x"7"; - when '8' => result(i*4+3 downto i*4) := x"8"; - when '9' => result(i*4+3 downto i*4) := x"9"; - when 'a' | 'A' => result(i*4+3 downto i*4) := x"A"; - when 'b' | 'B' => result(i*4+3 downto i*4) := x"B"; - when 'c' | 'C' => result(i*4+3 downto i*4) := x"C"; - when 'd' | 'D' => result(i*4+3 downto i*4) := x"D"; - when 'e' | 'E' => result(i*4+3 downto i*4) := x"E"; - when 'f' | 'F' => result(i*4+3 downto i*4) := x"F"; - when others => result(i*4+3 downto i*4) := "XXXX"; - end case; - end loop; - - return result; - end str2slv; - -end pack_oric_xilinx_prims; diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/ps2kbd.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/ps2kbd.vhd deleted file mode 100644 index f76c56de..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/ps2kbd.vhd +++ /dev/null @@ -1,212 +0,0 @@ --- --- PS/2 serial port, input only --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0242 : First release --- extended key handling added by MIKEJ --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity ps2kbd is - port( - Rst_n : in std_logic; - Clk : in std_logic; - Tick1us : in std_logic; - PS2_Clk : in std_logic; - PS2_Data : in std_logic; - Press : out std_logic; - Release : out std_logic; - Reset : out std_logic; - ScanE0 : out std_logic; - ScanCode : out std_logic_vector(7 downto 0) - ); -end ps2kbd; - -architecture rtl of ps2kbd is - -signal PS2_Sample : std_logic; -signal PS2_Data_s : std_logic; - -signal RX_Bit_Cnt : unsigned(3 downto 0); -signal RX_Byte : unsigned(2 downto 0); -signal RX_ShiftReg : std_logic_vector(7 downto 0); -signal RX_Release : std_logic; -signal RX_Received : std_logic; -signal RX_E0 : std_logic; - -begin - -ScanCode <= RX_ShiftReg; - -process (Clk, Rst_n) - variable PS2_Data_r : std_logic_vector(1 downto 0); - variable PS2_Clk_r : std_logic_vector(1 downto 0); - variable PS2_Clk_State : std_logic; -begin - if Rst_n = '0' then - PS2_Sample <= '0'; - PS2_Data_s <= '0'; - PS2_Data_r := "11"; - PS2_Clk_r := "11"; - PS2_Clk_State := '1'; - elsif Clk'event and Clk = '1' then - if Tick1us = '1' then - PS2_Sample <= '0'; - - -- Deglitch - if PS2_Data_r = "00" then - PS2_Data_s <= '0'; - end if; - if PS2_Data_r = "11" then - PS2_Data_s <= '1'; - end if; - if PS2_Clk_r = "00" then - if PS2_Clk_State = '1' then - PS2_Sample <= '1'; - end if; - PS2_Clk_State := '0'; - end if; - if PS2_Clk_r = "11" then - PS2_Clk_State := '1'; - end if; - - -- Double synchronise - PS2_Data_r(1) := PS2_Data_r(0); - PS2_Clk_r(1) := PS2_Clk_r(0); - PS2_Data_r(0) := PS2_Data; - PS2_Clk_r(0) := PS2_Clk; - end if; - end if; -end process; - -process (Clk, Rst_n) - variable Cnt : integer; -begin - if Rst_n = '0' then - RX_Bit_Cnt <= (others => '0'); - RX_ShiftReg <= (others => '0'); - RX_Received <= '0'; - Cnt := 0; - elsif Clk'event and Clk = '1' then - RX_Received <= '0'; - if Tick1us = '1' then - if PS2_Sample = '1' then - if RX_Bit_Cnt = "0000" then - if PS2_Data_s = '0' then -- Start bit - RX_Bit_Cnt <= RX_Bit_Cnt + 1; - end if; - elsif RX_Bit_Cnt = "1001" then -- Parity bit - RX_Bit_Cnt <= RX_Bit_Cnt + 1; - -- Ignoring parity - elsif RX_Bit_Cnt = "1010" then -- Stop bit - if PS2_Data_s = '1' then - RX_Received <= '1'; - end if; - RX_Bit_Cnt <= "0000"; - else - RX_Bit_Cnt <= RX_Bit_Cnt + 1; - RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1); - RX_ShiftReg(7) <= PS2_Data_s; - end if; - end if; - - -- TimeOut - if PS2_Sample = '1' then - Cnt := 0; - elsif Cnt = 127 then - RX_Bit_Cnt <= "0000"; - Cnt := 0; - else - Cnt := Cnt + 1; - end if; - end if; - end if; -end process; - -process (Clk, Rst_n) -begin - if Rst_n = '0' then - Press <= '0'; - Release <= '0'; - Reset <= '0'; - RX_Byte <= (others => '0'); - RX_Release <= '0'; - ScanE0 <= '0'; - RX_E0 <= '0'; - elsif Clk'event and Clk = '1' then - Press <= '0'; - Release <= '0'; - Reset <= '0'; - if RX_Received = '1' then - RX_Byte <= RX_Byte + 1; - if RX_ShiftReg = x"F0" then - RX_Release <= '1'; - elsif RX_ShiftReg = x"E0" then - RX_E0 <= '1'; - else - ScanE0 <= RX_E0; - RX_E0 <= '0'; - - RX_Release <= '0'; - -- Normal key press - if RX_Release = '0' then - Press <= '1'; - end if; - -- Normal key release - if RX_Release = '1' then - Release <= '1'; - end if; - end if; - if RX_ShiftReg = x"aa" then - Reset <= '1'; - end if; - end if; - end if; -end process; - -end; diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/psg_log.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/psg_log.vhd deleted file mode 100644 index ae53f2f4..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/psg_log.vhd +++ /dev/null @@ -1,60 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:12:00 08/14/2011 --- Design Name: --- Module Name: psg_log - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; - -use std.textio.all; -use work.txt_util.all; - -entity psg_log is - generic ( - log_psg: string := "psg.log" - ); - port( - CLK : in std_logic; - RST : in std_logic; - x1 : in std_logic - ); -end psg_log; - -architecture log_to_file of psg_log is - -file l_file_psg: TEXT open write_mode is log_psg; - -begin - --- write data and control information to a file - -receive_data: process (CLK,RST) - -variable l: line; - -begin - if (RST = '0') then - print(l_file_psg, ""); - elsif (clk'event and clk='1') then - write(l, chr(x1)); - writeline(l_file_psg, l); - end if; - -end process receive_data; - -end log_to_file; - \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/simul_test.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/simul_test.vhd deleted file mode 100644 index 9451b6bf..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/simul_test.vhd +++ /dev/null @@ -1,273 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:22:03 03/08/2011 --- Design Name: --- Module Name: /home/will/Documents/VHDL/PROJET/OricinFPGA/simul_test.vhd --- Project Name: OricinFPGA --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ORIC --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -library std; -use std.textio.all; -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; -use ieee.std_logic_textio.all; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -ENTITY simul_test IS -END simul_test; - -ARCHITECTURE behavior OF simul_test IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT ORIC - PORT( - AD : INOUT std_logic_vector(17 downto 0); - OE_SRAMn : OUT std_logic; - WE_SRAMn : OUT std_logic; - CE_SRAMn : OUT std_logic; - UB_SRAMn : OUT std_logic; - LB_SRAMn : OUT std_logic; - RW : OUT std_logic; - D : INOUT std_logic_vector(7 downto 0); - RESETn : IN std_logic; - PS2_CLK : IN std_logic; - PS2_DATA : IN std_logic; - VIDEO_R : OUT std_logic; - VIDEO_G : OUT std_logic; - VIDEO_B : OUT std_logic; - VIDEO_SYNC : OUT std_logic; - CLK_50 : IN std_logic; - btn : IN std_logic_vector(3 downto 0); - an : OUT std_logic_vector(3 downto 0); - sseg : OUT std_logic_vector(7 downto 0) - ); - END COMPONENT; - - --Inputs - signal RESETn : std_logic := '0'; - signal PS2_CLK : std_logic := '0'; - signal PS2_DATA : std_logic := '0'; - signal CLK_50 : std_logic := '0'; - signal btn : std_logic_vector(3 downto 0) := (others => '0'); - - --BiDirs - signal AD : std_logic_vector(17 downto 0); - signal D : std_logic_vector(7 downto 0); - - --Outputs - signal OE_SRAMn : std_logic; - signal WE_SRAMn : std_logic; - signal CE_SRAMn : std_logic; - signal UB_SRAMn : std_logic; - signal LB_SRAMn : std_logic; - signal RW : std_logic; - signal VIDEO_R : std_logic; - signal VIDEO_G : std_logic; - signal VIDEO_B : std_logic; - signal VIDEO_SYNC : std_logic; - signal an : std_logic_vector(3 downto 0); - signal sseg : std_logic_vector(7 downto 0); - - -- Clock period definitions - constant PS2_CLK_period : time := 10 ns; - constant CLK_50_period : time := 40 ns; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ORIC PORT MAP ( - AD => AD(17 downto 0), - OE_SRAMn => OE_SRAMn, - WE_SRAMn => WE_SRAMn, - CE_SRAMn => CE_SRAMn, - UB_SRAMn => UB_SRAMn, - LB_SRAMn => LB_SRAMn, - RW => RW, - D => D, - RESETn => RESETn, - PS2_CLK => PS2_CLK, - PS2_DATA => PS2_DATA, - VIDEO_R => VIDEO_R, - VIDEO_G => VIDEO_G, - VIDEO_B => VIDEO_B, - VIDEO_SYNC => VIDEO_SYNC, - CLK_50 => CLK_50, - btn => btn, - an => an, - sseg => sseg - ); - - ------------------------------------------------------------ - -- GESTION SRAM - ------------------------------------------------------------ - ramv : entity work.sram - port map - ( - A => AD(15 downto 0), - nOE => OE_SRAMn, - nWE => WE_SRAMn, - nCE1 => CE_SRAMn, - nUB1 => '1', - nLB1 => '0', - D => D - ); - - tb_RESET : PROCESS - BEGIN - RESETn <= '1'; - wait for 1000 ns; - RESETn <= '0'; - wait; -- will wait forever - END PROCESS; - - CLK_50_process :process - begin - -- 10/03/2011 : En fait, pour 24 (2x12) Mhz et pas 50 MHz - CLK_50 <= '0'; - wait for 20ns; - CLK_50 <= '1'; - wait for 20ns; - end process; - - tb_IN : PROCESS - BEGIN - --MAPn <= '1'; - --ROMDISn <= '1'; - --IRQn <= '1'; - --IOCONTROL <= '0'; - --K7_TAPEIN <= '0'; - --PRT_ACK <= '0'; - -- 10/03/2011 : Au supprimer en reel : - btn <= "0000"; - wait; -- will wait forever - END PROCESS; - - -- Stimulus process - tb_keyboard : process - file file_in : text open read_mode is "./scenario.txt"; - variable line_in : line; - variable cmd : character; - variable delay : time; - variable sig : std_logic; - variable char : std_logic_vector(7 downto 0); -begin - - loop - readline(file_in, line_in); - --exit when endfile(file_in); - - read(line_in, cmd); - exit when cmd = 'W' -- Wait - or cmd = 'E' -- End - or cmd = 'K'; -- Keyboard - end loop; - - --if not endfile(file_in) then - case cmd is - - when 'W' => - read(line_in, delay); - PS2_CLK <= '1'; -- Ajout du 23/11/2009 - PS2_DATA <= '1'; -- Ajout du 23/11/2009 - wait for delay; - - when 'K' => - read(line_in, char); - -PS2_DATA <= '0'; -- Start Bit - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(0); -- LSB - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(1); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(2); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(3); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(4); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(5); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(6); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(7); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= '0'; -- Parity (don't care) - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= '1'; -- Stop Bit - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; - - when 'E' => - PS2_CLK <= '1'; - PS2_DATA <= 'Z'; - wait; - - when others => - - end case; - --else - -- PS2_CLK <= '1'; - -- PS2_DATA <= 'Z'; - -- wait; - --end if; -end process; - -END; diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/tb_oa.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/tb_oa.vhd deleted file mode 100644 index 3b1fb90f..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/tb_oa.vhd +++ /dev/null @@ -1,321 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 23:36:12 10/10/2009 --- Design Name: --- Module Name: D:/Documents and Settings/JO/Mes documents/Projet/ORICATMOS/VERSION_2009_ISE_10.1/OA200906/tb_oa.vhd --- Project Name: OA2009 --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ORIC --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Revision 0.02 - 18/11/2009 : Test keyboard by PS2 --- Revision 0.03 - 23/11/2009 : Correction protocol PS2 --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -library std; -use std.textio.all; -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; -use ieee.std_logic_textio.all; - -ENTITY tb_oa IS -END tb_oa; - -ARCHITECTURE behavior OF tb_oa IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT ORIC - PORT( - AD : INOUT std_logic_vector(17 downto 0); - OE_SRAMn : out std_logic; - WE_SRAMn : out std_logic; - CE_SRAMn : out std_logic; - UB_SRAMn : out std_logic; - LB_SRAMn : out std_logic; - --MAPn : IN std_logic; - --ROMDISn : IN std_logic; - --IRQn : IN std_logic; - --CLK_EXT : OUT std_logic; - RW : OUT std_logic; - --IO : OUT std_logic; - --IOCONTROL : IN std_logic; - D : INOUT std_logic_vector(7 downto 0); - RESETn : IN std_logic; - PS2_CLK : IN std_logic; - PS2_DATA : IN std_logic; - --K7_TAPEIN : IN std_logic; - --K7_TAPEOUT : OUT std_logic; - --K7_REMOTE : OUT std_logic; - --K7_AUDIOOUT : OUT std_logic; - --AUDIO_OUT : OUT std_logic_vector(2 downto 0); - VIDEO_R : OUT std_logic; - VIDEO_G : OUT std_logic; - VIDEO_B : OUT std_logic; - --VIDEO_HSYNC : OUT std_logic; - --VIDEO_VSYNC : OUT std_logic; - VIDEO_SYNC : OUT std_logic; - --PRT_DATA : INOUT std_logic_vector(7 downto 0); - --PRT_STR : OUT std_logic; - --PRT_ACK : IN std_logic; - CLK_50 : IN std_logic - --DBG_ROM_DOUT : OUT std_logic_vector(7 downto 0); - --DBG_ULA_AD : OUT std_logic_vector(15 downto 0) - ); - END COMPONENT; - - - --Inputs - --signal MAPn : std_logic := '0'; - --signal ROMDISn : std_logic := '0'; - --signal IRQn : std_logic := '0'; - --signal IOCONTROL : std_logic := '0'; - signal RESETn : std_logic := '0'; - signal PS2_CLK : std_logic := '0'; - signal PS2_DATA : std_logic := '0'; - --signal K7_TAPEIN : std_logic := '0'; - --signal PRT_ACK : std_logic := '0'; - signal CLK_50 : std_logic := '0'; - - --BiDirs - signal AD : std_logic_vector(17 downto 0); - signal D : std_logic_vector(7 downto 0); - --signal PRT_DATA : std_logic_vector(7 downto 0); - - --Outputs - --signal CLK_EXT : std_logic; - signal RW : std_logic; - --signal IO : std_logic; - --signal K7_TAPEOUT : std_logic; - --signal K7_REMOTE : std_logic; - --signal K7_AUDIOOUT : std_logic; - --signal AUDIO_OUT : std_logic_vector(2 downto 0); - signal VIDEO_R : std_logic; - signal VIDEO_G : std_logic; - signal VIDEO_B : std_logic; - --signal VIDEO_HSYNC : std_logic; - --signal VIDEO_VSYNC : std_logic; - signal VIDEO_SYNC : std_logic; - --signal PRT_STR : std_logic; - --signal DBG_ROM_DOUT : std_logic_vector(7 downto 0); - --signal DBG_ULA_AD : std_logic_vector(15 downto 0); - - --signal AD_SRAM : std_logic_vector(15 downto 0); - signal OE_SRAM : std_logic; - signal CE_SRAM : std_logic; - signal WE_SRAM : std_logic; - signal UB_SRAM : std_logic; - signal LB_SRAM : std_logic; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ORIC PORT MAP ( - --AD => AD, - AD => AD, - OE_SRAMn => OE_SRAM, - WE_SRAMn => WE_SRAM, - CE_SRAMn => CE_SRAM, - UB_SRAMn => UB_SRAM, - LB_SRAMn => LB_SRAM, - --MAPn => MAPn, - --ROMDISn => ROMDISn, - --IRQn => IRQn, - --CLK_EXT => CLK_EXT, - RW => RW, - --IO => IO, - --IOCONTROL => IOCONTROL, - D => D, - RESETn => RESETn, - PS2_CLK => PS2_CLK, - PS2_DATA => PS2_DATA, - --K7_TAPEIN => K7_TAPEIN, - --K7_TAPEOUT => K7_TAPEOUT, - --K7_REMOTE => K7_REMOTE, - --K7_AUDIOOUT => K7_AUDIOOUT, - --AUDIO_OUT => AUDIO_OUT, - VIDEO_R => VIDEO_R, - VIDEO_G => VIDEO_G, - VIDEO_B => VIDEO_B, - --VIDEO_HSYNC => VIDEO_HSYNC, - --VIDEO_VSYNC => VIDEO_VSYNC, - VIDEO_SYNC => VIDEO_SYNC, - --PRT_DATA => PRT_DATA, - --PRT_STR => PRT_STR, - --PRT_ACK => PRT_ACK, - CLK_50 => CLK_50 - --DBG_ROM_DOUT => DBG_ROM_DOUT, - --DBG_ULA_AD => DBG_ULA_AD - ); - - ------------------------------------------------------------ - -- GESTION SRAM - ------------------------------------------------------------ - ramv : entity work.sram - port map - ( - A => AD(15 downto 0), - nOE => OE_SRAM, - nWE => WE_SRAM, - nCE1 => CE_SRAM, - nUB1 => UB_SRAM, - nLB1 => LB_SRAM, - D => D - ); - - -- No clocks detected in port list. Replace below with - -- appropriate port name - - --18/11/2009 ne fonctionne pas ... constant CLK_12_period : TIME := 2ns; - - CLK_50_process :process - begin - CLK_50 <= '0'; - wait for 10ns; - CLK_50 <= '1'; - wait for 10ns; - end process; - - tb_RESET : PROCESS - BEGIN - RESETn <= '1'; - wait for 1000 ns; - RESETn <= '0'; - wait; -- will wait forever - END PROCESS; - - tb_IN : PROCESS - BEGIN - --MAPn <= '1'; - --ROMDISn <= '1'; - --IRQn <= '1'; - --IOCONTROL <= '0'; - --K7_TAPEIN <= '0'; - --PRT_ACK <= '0'; - wait; -- will wait forever - END PROCESS; - - -- Stimulus process - tb_keyboard : process - file file_in : text open read_mode is "./scenario.txt"; - variable line_in : line; - variable cmd : character; - variable delay : time; - variable sig : std_logic; - variable char : std_logic_vector(7 downto 0); -begin - - loop - readline(file_in, line_in); - --exit when endfile(file_in); - - read(line_in, cmd); - exit when cmd = 'W' -- Wait - or cmd = 'E' -- End - or cmd = 'K'; -- Keyboard - end loop; - - --if not endfile(file_in) then - case cmd is - - when 'W' => - read(line_in, delay); - PS2_CLK <= '1'; -- Ajout du 23/11/2009 - PS2_DATA <= '1'; -- Ajout du 23/11/2009 - wait for delay; - - when 'K' => - read(line_in, char); - -PS2_DATA <= '0'; -- Start Bit - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(0); -- LSB - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(1); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(2); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(3); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(4); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(5); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(6); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= char(7); - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= '0'; -- Parity (don't care) - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; -PS2_DATA <= '1'; -- Stop Bit - PS2_CLK <= '0'; - wait for 40us; - PS2_CLK <= '1'; - wait for 40us; - - when 'E' => - PS2_CLK <= '1'; - PS2_DATA <= 'Z'; - wait; - - when others => - - end case; - --else - -- PS2_CLK <= '1'; - -- PS2_DATA <= 'Z'; - -- wait; - --end if; - -end process; - - - -END; diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/tb_oatest.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/tb_oatest.vhd deleted file mode 100644 index c2e0c361..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/tb_oatest.vhd +++ /dev/null @@ -1,172 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 22:53:03 11/18/2009 --- Design Name: --- Module Name: D:/Documents and Settings/JO/Mes documents/Projet/ORICATMOS/VERSION_2009_ISE_10.1/OA200906/tb_oatest.vhd --- Project Name: OA2009 --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ORIC --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.std_logic_unsigned.all; -USE ieee.numeric_std.ALL; - -ENTITY tb_oatest IS -END tb_oatest; - -ARCHITECTURE behavior OF tb_oatest IS - - -- Component Declaration for the Unit Under Test (UUT) - - COMPONENT ORIC - PORT( - AD : INOUT std_logic_vector(15 downto 0); - MAPn : IN std_logic; - ROMDISn : IN std_logic; - IRQn : IN std_logic; - CLK_EXT : OUT std_logic; - RW : OUT std_logic; - IO : OUT std_logic; - IOCONTROL : IN std_logic; - D : INOUT std_logic_vector(7 downto 0); - RESETn : IN std_logic; - PS2_CLK : IN std_logic; - PS2_DATA : IN std_logic; - K7_TAPEIN : IN std_logic; - K7_TAPEOUT : OUT std_logic; - K7_REMOTE : OUT std_logic; - K7_AUDIOOUT : OUT std_logic; - AUDIO_OUT : OUT std_logic_vector(3 downto 0); - VIDEO_R : OUT std_logic; - VIDEO_G : OUT std_logic; - VIDEO_B : OUT std_logic; - VIDEO_HSYNC : OUT std_logic; - VIDEO_VSYNC : OUT std_logic; - VIDEO_SYNC : OUT std_logic; - PRT_DATA : INOUT std_logic_vector(7 downto 0); - PRT_STR : OUT std_logic; - PRT_ACK : IN std_logic; - CLK_12 : IN std_logic; - DBG_ROM_DOUT : OUT std_logic_vector(7 downto 0); - DBG_ULA_AD : OUT std_logic_vector(15 downto 0) - ); - END COMPONENT; - - - --Inputs - signal MAPn : std_logic := '0'; - signal ROMDISn : std_logic := '0'; - signal IRQn : std_logic := '0'; - signal IOCONTROL : std_logic := '0'; - signal RESETn : std_logic := '0'; - signal PS2_CLK : std_logic := '0'; - signal PS2_DATA : std_logic := '0'; - signal K7_TAPEIN : std_logic := '0'; - signal PRT_ACK : std_logic := '0'; - signal CLK_12 : std_logic := '0'; - - --BiDirs - signal AD : std_logic_vector(15 downto 0); - signal D : std_logic_vector(7 downto 0); - signal PRT_DATA : std_logic_vector(7 downto 0); - - --Outputs - signal CLK_EXT : std_logic; - signal RW : std_logic; - signal IO : std_logic; - signal K7_TAPEOUT : std_logic; - signal K7_REMOTE : std_logic; - signal K7_AUDIOOUT : std_logic; - signal AUDIO_OUT : std_logic_vector(3 downto 0); - signal VIDEO_R : std_logic; - signal VIDEO_G : std_logic; - signal VIDEO_B : std_logic; - signal VIDEO_HSYNC : std_logic; - signal VIDEO_VSYNC : std_logic; - signal VIDEO_SYNC : std_logic; - signal PRT_STR : std_logic; - signal DBG_ROM_DOUT : std_logic_vector(7 downto 0); - signal DBG_ULA_AD : std_logic_vector(15 downto 0); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ORIC PORT MAP ( - AD => AD, - MAPn => MAPn, - ROMDISn => ROMDISn, - IRQn => IRQn, - CLK_EXT => CLK_EXT, - RW => RW, - IO => IO, - IOCONTROL => IOCONTROL, - D => D, - RESETn => RESETn, - PS2_CLK => PS2_CLK, - PS2_DATA => PS2_DATA, - K7_TAPEIN => K7_TAPEIN, - K7_TAPEOUT => K7_TAPEOUT, - K7_REMOTE => K7_REMOTE, - K7_AUDIOOUT => K7_AUDIOOUT, - AUDIO_OUT => AUDIO_OUT, - VIDEO_R => VIDEO_R, - VIDEO_G => VIDEO_G, - VIDEO_B => VIDEO_B, - VIDEO_HSYNC => VIDEO_HSYNC, - VIDEO_VSYNC => VIDEO_VSYNC, - VIDEO_SYNC => VIDEO_SYNC, - PRT_DATA => PRT_DATA, - PRT_STR => PRT_STR, - PRT_ACK => PRT_ACK, - CLK_12 => CLK_12, - DBG_ROM_DOUT => DBG_ROM_DOUT, - DBG_ULA_AD => DBG_ULA_AD - ); - - -- No clocks detected in port list. Replace below with - -- appropriate port name - - constant _period := 1ns; - - _process :process - begin - <= '0'; - wait for _period/2; - <= '1'; - wait for _period/2; - end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100ms. - wait for 100ms; - - wait for _period*10; - - -- insert stimulus here - - wait; - end process; - -END; diff --git a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/txt_util.vhd b/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/txt_util.vhd deleted file mode 100644 index b5391c60..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/rtl_o/txt_util.vhd +++ /dev/null @@ -1,598 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:59:25 03/08/2011 --- Design Name: --- Module Name: txt_util - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; - - -package txt_util is - - -- prints a message to the screen - procedure print(text: string); - - -- prints the message when active - -- useful for debug switches - procedure print(active: boolean; text: string); - - -- converts std_logic into a character - function chr(sl: std_logic) return character; - - -- converts std_logic into a string (1 to 1) - function str(sl: std_logic) return string; - - -- converts std_logic_vector into a string (binary base) - function str(slv: std_logic_vector) return string; - - -- converts boolean into a string - function str(b: boolean) return string; - - -- converts an integer into a single character - -- (can also be used for hex conversion and other bases) - function chr(int: integer) return character; - - -- converts integer into string using specified base - function str(int: integer; base: integer) return string; - - -- converts integer to string, using base 10 - function str(int: integer) return string; - - -- convert std_logic_vector into a string in hex format - function hstr(slv: std_logic_vector) return string; - - - -- functions to manipulate strings - ----------------------------------- - - -- convert a character to upper case - function to_upper(c: character) return character; - - -- convert a character to lower case - function to_lower(c: character) return character; - - -- convert a string to upper case - function to_upper(s: string) return string; - - -- convert a string to lower case - function to_lower(s: string) return string; - - - - -- functions to convert strings into other formats - -------------------------------------------------- - - -- converts a character into std_logic - function to_std_logic(c: character) return std_logic; - - -- converts a string into std_logic_vector - function to_std_logic_vector(s: string) return std_logic_vector; - - - - -- file I/O - ----------- - - -- read variable length string from input file - procedure str_read(file in_file: TEXT; - res_string: out string); - - -- print string to a file and start new line - procedure print(file out_file: TEXT; - new_string: in string); - - -- print character to a file and start new line - procedure print(file out_file: TEXT; - char: in character); - -end txt_util; - - - - -package body txt_util is - - - - - -- prints text to the screen - - procedure print(text: string) is - variable msg_line: line; - begin - write(msg_line, text); - writeline(output, msg_line); - end print; - - - - - -- prints text to the screen when active - - procedure print(active: boolean; text: string) is - begin - if active then - print(text); - end if; - end print; - - - -- converts std_logic into a character - - function chr(sl: std_logic) return character is - variable c: character; - begin - case sl is - when 'U' => c:= 'U'; - when 'X' => c:= 'X'; - when '0' => c:= '0'; - when '1' => c:= '1'; - when 'Z' => c:= 'Z'; - when 'W' => c:= 'W'; - when 'L' => c:= 'L'; - when 'H' => c:= 'H'; - when '-' => c:= '-'; - end case; - return c; - end chr; - - - - -- converts std_logic into a string (1 to 1) - - function str(sl: std_logic) return string is - variable s: string(1 to 1); - begin - s(1) := chr(sl); - return s; - end str; - - - - -- converts std_logic_vector into a string (binary base) - -- (this also takes care of the fact that the range of - -- a string is natural while a std_logic_vector may - -- have an integer range) - - function str(slv: std_logic_vector) return string is - variable result : string (1 to slv'length); - variable r : integer; - begin - r := 1; - for i in slv'range loop - result(r) := chr(slv(i)); - r := r + 1; - end loop; - return result; - end str; - - - function str(b: boolean) return string is - - begin - if b then - return "true"; - else - return "false"; - end if; - end str; - - - -- converts an integer into a character - -- for 0 to 9 the obvious mapping is used, higher - -- values are mapped to the characters A-Z - -- (this is usefull for systems with base > 10) - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function chr(int: integer) return character is - variable c: character; - begin - case int is - when 0 => c := '0'; - when 1 => c := '1'; - when 2 => c := '2'; - when 3 => c := '3'; - when 4 => c := '4'; - when 5 => c := '5'; - when 6 => c := '6'; - when 7 => c := '7'; - when 8 => c := '8'; - when 9 => c := '9'; - when 10 => c := 'A'; - when 11 => c := 'B'; - when 12 => c := 'C'; - when 13 => c := 'D'; - when 14 => c := 'E'; - when 15 => c := 'F'; - when 16 => c := 'G'; - when 17 => c := 'H'; - when 18 => c := 'I'; - when 19 => c := 'J'; - when 20 => c := 'K'; - when 21 => c := 'L'; - when 22 => c := 'M'; - when 23 => c := 'N'; - when 24 => c := 'O'; - when 25 => c := 'P'; - when 26 => c := 'Q'; - when 27 => c := 'R'; - when 28 => c := 'S'; - when 29 => c := 'T'; - when 30 => c := 'U'; - when 31 => c := 'V'; - when 32 => c := 'W'; - when 33 => c := 'X'; - when 34 => c := 'Y'; - when 35 => c := 'Z'; - when others => c := '?'; - end case; - return c; - end chr; - - - - -- convert integer to string using specified base - -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) - - function str(int: integer; base: integer) return string is - - variable temp: string(1 to 10); - variable num: integer; - variable abs_int: integer; - variable len: integer := 1; - variable power: integer := 1; - - begin - - -- bug fix for negative numbers - abs_int := abs(int); - - num := abs_int; - - while num >= base loop -- Determine how many - len := len + 1; -- characters required - num := num / base; -- to represent the - end loop ; -- number. - - for i in len downto 1 loop -- Convert the number to - temp(i) := chr(abs_int/power mod base); -- a string starting - power := power * base; -- with the right hand - end loop ; -- side. - - -- return result and add sign if required - if int < 0 then - return '-'& temp(1 to len); - else - return temp(1 to len); - end if; - - end str; - - - -- convert integer to string, using base 10 - function str(int: integer) return string is - - begin - - return str(int, 10) ; - - end str; - - - - -- converts a std_logic_vector into a hex string. - function hstr(slv: std_logic_vector) return string is - variable hexlen: integer; - variable longslv : std_logic_vector(67 downto 0) := (others => '0'); - variable hex : string(1 to 16); - variable fourbit : std_logic_vector(3 downto 0); - begin - hexlen := (slv'left+1)/4; - if (slv'left+1) mod 4 /= 0 then - hexlen := hexlen + 1; - end if; - longslv(slv'left downto 0) := slv; - for i in (hexlen -1) downto 0 loop - fourbit := longslv(((i*4)+3) downto (i*4)); - case fourbit is - when "0000" => hex(hexlen -I) := '0'; - when "0001" => hex(hexlen -I) := '1'; - when "0010" => hex(hexlen -I) := '2'; - when "0011" => hex(hexlen -I) := '3'; - when "0100" => hex(hexlen -I) := '4'; - when "0101" => hex(hexlen -I) := '5'; - when "0110" => hex(hexlen -I) := '6'; - when "0111" => hex(hexlen -I) := '7'; - when "1000" => hex(hexlen -I) := '8'; - when "1001" => hex(hexlen -I) := '9'; - when "1010" => hex(hexlen -I) := 'A'; - when "1011" => hex(hexlen -I) := 'B'; - when "1100" => hex(hexlen -I) := 'C'; - when "1101" => hex(hexlen -I) := 'D'; - when "1110" => hex(hexlen -I) := 'E'; - when "1111" => hex(hexlen -I) := 'F'; - when "ZZZZ" => hex(hexlen -I) := 'z'; - when "UUUU" => hex(hexlen -I) := 'u'; - when "XXXX" => hex(hexlen -I) := 'x'; - when others => hex(hexlen -I) := '?'; - end case; - end loop; - return hex(1 to hexlen); - end hstr; - - - - -- functions to manipulate strings - ----------------------------------- - - - -- convert a character to upper case - - function to_upper(c: character) return character is - - variable u: character; - - begin - - case c is - when 'a' => u := 'A'; - when 'b' => u := 'B'; - when 'c' => u := 'C'; - when 'd' => u := 'D'; - when 'e' => u := 'E'; - when 'f' => u := 'F'; - when 'g' => u := 'G'; - when 'h' => u := 'H'; - when 'i' => u := 'I'; - when 'j' => u := 'J'; - when 'k' => u := 'K'; - when 'l' => u := 'L'; - when 'm' => u := 'M'; - when 'n' => u := 'N'; - when 'o' => u := 'O'; - when 'p' => u := 'P'; - when 'q' => u := 'Q'; - when 'r' => u := 'R'; - when 's' => u := 'S'; - when 't' => u := 'T'; - when 'u' => u := 'U'; - when 'v' => u := 'V'; - when 'w' => u := 'W'; - when 'x' => u := 'X'; - when 'y' => u := 'Y'; - when 'z' => u := 'Z'; - when others => u := c; - end case; - - return u; - - end to_upper; - - - -- convert a character to lower case - - function to_lower(c: character) return character is - - variable l: character; - - begin - - case c is - when 'A' => l := 'a'; - when 'B' => l := 'b'; - when 'C' => l := 'c'; - when 'D' => l := 'd'; - when 'E' => l := 'e'; - when 'F' => l := 'f'; - when 'G' => l := 'g'; - when 'H' => l := 'h'; - when 'I' => l := 'i'; - when 'J' => l := 'j'; - when 'K' => l := 'k'; - when 'L' => l := 'l'; - when 'M' => l := 'm'; - when 'N' => l := 'n'; - when 'O' => l := 'o'; - when 'P' => l := 'p'; - when 'Q' => l := 'q'; - when 'R' => l := 'r'; - when 'S' => l := 's'; - when 'T' => l := 't'; - when 'U' => l := 'u'; - when 'V' => l := 'v'; - when 'W' => l := 'w'; - when 'X' => l := 'x'; - when 'Y' => l := 'y'; - when 'Z' => l := 'z'; - when others => l := c; - end case; - - return l; - - end to_lower; - - - - -- convert a string to upper case - - function to_upper(s: string) return string is - - variable uppercase: string (s'range); - - begin - - for i in s'range loop - uppercase(i):= to_upper(s(i)); - end loop; - return uppercase; - - end to_upper; - - - - -- convert a string to lower case - - function to_lower(s: string) return string is - - variable lowercase: string (s'range); - - begin - - for i in s'range loop - lowercase(i):= to_lower(s(i)); - end loop; - return lowercase; - - end to_lower; - - - --- functions to convert strings into other types - - --- converts a character into a std_logic - -function to_std_logic(c: character) return std_logic is - variable sl: std_logic; - begin - case c is - when 'U' => - sl := 'U'; - when 'X' => - sl := 'X'; - when '0' => - sl := '0'; - when '1' => - sl := '1'; - when 'Z' => - sl := 'Z'; - when 'W' => - sl := 'W'; - when 'L' => - sl := 'L'; - when 'H' => - sl := 'H'; - when '-' => - sl := '-'; - when others => - sl := 'X'; - end case; - return sl; - end to_std_logic; - - --- converts a string into std_logic_vector - -function to_std_logic_vector(s: string) return std_logic_vector is - variable slv: std_logic_vector(s'high-s'low downto 0); - variable k: integer; -begin - k := s'high-s'low; - for i in s'range loop - slv(k) := to_std_logic(s(i)); - k := k - 1; - end loop; - return slv; -end to_std_logic_vector; - - - - - - ----------------- --- file I/O -- ----------------- - - - --- read variable length string from input file - -procedure str_read(file in_file: TEXT; - res_string: out string) is - - variable l: line; - variable c: character; - variable is_string: boolean; - - begin - - readline(in_file, l); - -- clear the contents of the result string - for i in res_string'range loop - res_string(i) := ' '; - end loop; - -- read all characters of the line, up to the length - -- of the results string - for i in res_string'range loop - read(l, c, is_string); - res_string(i) := c; - if not is_string then -- found end of line - exit; - end if; - end loop; - -end str_read; - - --- print string to a file -procedure print(file out_file: TEXT; - new_string: in string) is - - variable l: line; - - begin - - write(l, new_string); - writeline(out_file, l); - -end print; - - --- print character to a file and start new line -procedure print(file out_file: TEXT; - char: in character) is - - variable l: line; - - begin - - write(l, char); - writeline(out_file, l); - -end print; - - - --- appends contents of a string to a file until line feed occurs --- (LF is considered to be the end of the string) - -procedure str_write(file out_file: TEXT; - new_string: in string) is - begin - - for i in new_string'range loop - print(out_file, new_string(i)); - if new_string(i) = LF then -- end of string - exit; - end if; - end loop; - -end str_write; - -end txt_util; \ No newline at end of file diff --git a/Computer_MiST/Oric Atmos_MiST/storage/scenario.txt b/Computer_MiST/Oric Atmos_MiST/storage/scenario.txt deleted file mode 100644 index 947b6323..00000000 --- a/Computer_MiST/Oric Atmos_MiST/storage/scenario.txt +++ /dev/null @@ -1,29 +0,0 @@ -W 150 ms -# Press Z (0x1A) -K 00011010 -W 35 ms -# Release Z (0xF0 0x1A) -K 11110000 -K 00011010 -W 100 ms -# Press A (0x1C) -K 00011100 -W 35 ms -# Release A (0xF0 0x1C) -K 11110000 -K 00011100 -W 100 ms -# Press P (0x4D) -K 01001101 -W 35 ms -# Release P (0xF0 0x4D) -K 11110000 -K 01001101 -W 100 ms -# Press RETURN (0x5A) -K 01011010 -W 35 ms -# Release RETURN (0xF0 0x5A) -K 11110000 -K 01011010 -E diff --git a/Console_MiST/Atari - 7800_TeST/Atari7800.qpf b/Console_MiST/Atari - 7800_TeST/Atari7800.qpf deleted file mode 100644 index 086d0dc1..00000000 --- a/Console_MiST/Atari - 7800_TeST/Atari7800.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 23:59:05 March 16, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "23:59:05 March 16, 2017" - -# Revisions - -PROJECT_REVISION = "Atari7800" diff --git a/Console_MiST/Atari - 7800_TeST/Atari7800.qsf b/Console_MiST/Atari - 7800_TeST/Atari7800.qsf deleted file mode 100644 index 679890ef..00000000 --- a/Console_MiST/Atari - 7800_TeST/Atari7800.qsf +++ /dev/null @@ -1,231 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2014 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition -# Date created = 14:33:15 July 17, 2018 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Atari7800_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output_Files -set_global_assignment -name VERILOG_INCLUDE_FILE rtl/atari7800.vh -set_global_assignment -name VERILOG_INCLUDE_FILE rtl/tia.vh -set_global_assignment -name VERILOG_INCLUDE_FILE rtl/riot.vh -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cart_top.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/Atari7800.sv -set_global_assignment -name VERILOG_FILE rtl/BIOS_ROM.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/uv_to_vga.sv -set_global_assignment -name VERILOG_FILE rtl/ram2k.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/maria.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/TIA.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/RIOT.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu_wrapper.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/line_ram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/timing_ctrl.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory_map.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/dma_ctrl.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/audio.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/audio_xformer.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/ALU.sv -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name VERILOG_FILE rtl/defender_rom.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sigma_delta_dac.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_90 -to SPI_SS4 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PIN_31 -to UART_RX -set_location_assignment PIN_46 -to UART_TX - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 -set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name TOP_LEVEL_ENTITY cart_top - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_NCE_PIN OFF -set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ---------------------- -# start ENTITY(cart_top) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(cart_top) -# -------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/Atari7800.srf b/Console_MiST/Atari - 7800_TeST/Atari7800.srf deleted file mode 100644 index 91697a7c..00000000 --- a/Console_MiST/Atari - 7800_TeST/Atari7800.srf +++ /dev/null @@ -1,2 +0,0 @@ -{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Console_MiST/Atari - 7800_TeST/Snapshot/Atari7800.rbf b/Console_MiST/Atari - 7800_TeST/Snapshot/Atari7800.rbf deleted file mode 100644 index 1fb8029e..00000000 Binary files a/Console_MiST/Atari - 7800_TeST/Snapshot/Atari7800.rbf and /dev/null differ diff --git a/Console_MiST/Atari - 7800_TeST/clean.bat b/Console_MiST/Atari - 7800_TeST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Console_MiST/Atari - 7800_TeST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Console_MiST/Atari - 7800_TeST/rtl/ALU.sv b/Console_MiST/Atari - 7800_TeST/rtl/ALU.sv deleted file mode 100644 index 0a5abe18..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/ALU.sv +++ /dev/null @@ -1,110 +0,0 @@ -/* - * ALU. - * - * AI and BI are 8 bit inputs. Result in OUT. - * CI is Carry In. - * CO is Carry Out. - * - * op[3:0] is defined as follows: - * - * 0011 AI + BI - * 0111 AI - BI - * 1011 AI + AI - * 1100 AI | BI - * 1101 AI & BI - * 1110 AI ^ BI - * 1111 AI - * - */ - `timescale 1ns / 1ps - - -module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY ); - input clk; - input right; - input [3:0] op; // operation - input [7:0] AI; - input [7:0] BI; - input CI; - input BCD; // BCD style carry - output [7:0] OUT; - output CO; - output V; - output Z; - output N; - output HC; - input RDY; - -reg [7:0] OUT; -reg CO; -wire V; -wire Z; -reg N; -reg HC; - -reg AI7; -reg BI7; -reg [8:0] temp_logic; -reg [7:0] temp_BI; -reg [4:0] temp_l; -reg [4:0] temp_h; -wire [8:0] temp = { temp_h, temp_l[3:0] }; -wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI; - -// calculate the logic operations. The 'case' can be done in 1 LUT per -// bit. The 'right' shift is a simple mux that can be implemented by -// F5MUX. -always @* begin - case( op[1:0] ) - 2'b00: temp_logic = AI | BI; - 2'b01: temp_logic = AI & BI; - 2'b10: temp_logic = AI ^ BI; - 2'b11: temp_logic = AI; - endcase - - if( right ) - temp_logic = { AI[0], CI, AI[7:1] }; -end - -// Add logic result to BI input. This only makes sense when logic = AI. -// This stage can be done in 1 LUT per bit, using carry chain logic. -always @* begin - case( op[3:2] ) - 2'b00: temp_BI = BI; // A+B - 2'b01: temp_BI = ~BI; // A-B - 2'b10: temp_BI = temp_logic; // A+A - 2'b11: temp_BI = 0; // A+0 - endcase -end - -// HC9 is the half carry bit when doing BCD add -wire HC9 = BCD & (temp_l[3:1] >= 3'd5); - -// CO9 is the carry-out bit when doing BCD add -wire CO9 = BCD & (temp_h[3:1] >= 3'd5); - -// combined half carry bit -wire temp_HC = temp_l[4] | HC9; - -// perform the addition as 2 separate nibble, so we get -// access to the half carry flag -always @* begin - temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI; - temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC; -end - -// calculate the flags -always @(posedge clk) - if( RDY ) begin - AI7 <= AI[7]; - BI7 <= temp_BI[7]; - OUT <= temp[7:0]; - CO <= temp[8] | CO9; - N <= temp[7]; - HC <= temp_HC; - end - -assign V = AI7 ^ BI7 ^ CO ^ N; -assign Z = ~|OUT; - -endmodule \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/Atari7800.sv b/Console_MiST/Atari - 7800_TeST/rtl/Atari7800.sv deleted file mode 100644 index a7e9036c..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/Atari7800.sv +++ /dev/null @@ -1,444 +0,0 @@ -`timescale 1ns / 1ps -`include "atari7800.vh" - - - -module Atari7800( - input logic clock_25, - input logic sysclk_7_143, - input logic clock_divider_locked, - - input logic reset, - output logic [3:0] RED, GREEN, BLUE, - output logic HSync, VSync, - - output logic [15:0] aud_signal_out, - - input logic [7:0] cart_DB_out, - output logic [15:0] AB, - output logic RW, - output logic pclk_0, - - output logic [7:0] ld, - - // Tia inputs - input logic [3:0] idump, - input logic [1:0] ilatch, - - output logic tia_en, - - // Riot inputs - input logic [7:0] PAin, PBin, - output logic [7:0] PAout, PBout -); - - assign ld[0] = lock_ctrl; - - ////////////// - // Signals // - //////////// - - // Clock Signals - - logic pclk_2, tia_clk, sel_slow_clock; - - - // VGA Signals - logic [9:0] vga_row, vga_col; - logic tia_hsync, tia_vsync, vga_hsync, vga_vsync; - - (* keep = "true" *) logic tia_hsync_kept; - (* keep = "true" *) logic tia_vsync_kept; - (* keep = "true" *) logic vga_hsync_kept; - (* keep = "true" *) logic vga_vsync_kept; - - assign tia_hsync_kept = ~tia_hsync; - assign tia_vsync_kept = ~tia_vsync; - assign vga_hsync_kept = vga_hsync; - assign vga_vsync_kept = vga_vsync; - - // MARIA Signals - logic m_int_b, maria_RDY; - logic maria_rw; - logic halt_b, maria_drive_AB; - logic [7:0] uv_display, uv_maria, uv_tia; - logic [15:0] maria_AB_out; - - - - // TIA Signals - logic hblank_tia, vblank_tia, aud0, aud1, tia_RDY; - logic [3:0] audv0, audv1; - logic [7:0] tia_db_out; - - // RIOT Signals - logic riot_RS_b; - - // 6502 Signals - logic RDY, IRQ_n, CPU_NMI; - logic [7:0] core_DB_out; - logic [15:0] core_AB_out; - - logic cpu_reset, core_halt_b, core_latch_data; - logic [2:0] cpu_reset_counter; - - assign IRQ_n = 1'b1; - - //ctrl Signals - logic maria_en, lock_ctrl, bios_en_b; - logic [1:0] ctrl_writes; - - // Buses - // AB and RW defined in port declaration - logic [7:0] read_DB, write_DB; - - logic [7:0] tia_DB_out, riot_DB_out, maria_DB_out, - ram0_DB_out, ram1_DB_out, bios_DB_out; - - `chipselect CS_maria_buf, CS_core_buf, CS_buf, CS; - - logic memclk; - assign memclk = (~halt_b & maria_drive_AB) ? sysclk_7_143 : pclk_0; - - /*always_ff @(posedge sysclk_7_143, posedge reset) begin - if (reset) begin - CS_maria_buf <= `CS_NONE; - CS_core_buf <= `CS_NONE; - end else begin - CS_maria_buf <= CS; - CS_core_buf <= CS; - end - end - - assign CS_buf = maria_drive_AB ? CS_maria_buf : CS_core_buf;*/ - - always_ff @(posedge memclk, posedge reset) - if (reset) - CS_buf <= `CS_NONE; - else - CS_buf <= CS; - - - //CS LOGIC - logic ram0_cs, ram1_cs, bios_cs, tia_cs, riot_cs, riot_ram_cs; - - always_comb begin - ram0_cs = 1'b0; - ram1_cs = 1'b0; - bios_cs = 1'b0; - tia_cs = 1'b0; - riot_cs = 1'b0; - riot_ram_cs = 1'b0; - casex (CS) - `CS_RAM0: ram0_cs = 1'b1; - `CS_RAM1: ram1_cs = 1'b1; - `CS_BIOS: bios_cs = 1'b1; - `CS_TIA: tia_cs = 1'b1; - `CS_RIOT_IO: riot_cs = 1'b1; - `CS_RIOT_RAM: begin riot_cs = 1'b1; riot_ram_cs = 1'b1; end - endcase - end - - - always_comb begin - casex (CS_buf) - `CS_RAM0: read_DB = ram0_DB_out; - `CS_RAM1: read_DB = ram1_DB_out; - `CS_RIOT_IO, - `CS_RIOT_RAM: read_DB = riot_DB_out; - `CS_TIA: read_DB = tia_DB_out; - `CS_BIOS: read_DB = bios_DB_out; - `CS_MARIA: read_DB = maria_DB_out; - `CS_CART: read_DB = cart_DB_out; - // Otherwise, nothing is driving the data bus. THIS SHOULD NEVER HAPPEN - default: read_DB = 8'h46; - endcase - - write_DB = core_DB_out; - - AB = (maria_drive_AB) ? maria_AB_out : core_AB_out; - end - /* - (* ram_style = "distributed" *) - reg [7:0] ram0 [2047:0]; - (* ram_style = "distributed" *) - reg [7:0] ram1 [2047:0]; - integer cnt; - always_ff @(posedge memclk) begin - if (reset) begin - for (cnt = 0; cnt < 2048;cnt = cnt + 1) begin - ram0[cnt] <= 8'b0; - ram1[cnt] <= 8'b0; - end - end - else if(ram0_cs) - if (RW) - ram0_DB_out <= ram0[AB[10:0]]; - else - ram0[AB[10:0]] <= write_DB; - else if (ram1_cs) - if (RW) - ram1_DB_out <= ram1[AB[10:0]]; - else - ram1[AB[10:0]] <= write_DB; - end */ - - ram2k ram0_inst( - .clock(memclk), - //.ena(~ram0_cs_b), - .clken(ram0_cs), - .wren(~RW), - .address(AB[10:0]), - .data(write_DB), - .q(ram0_DB_out) - ); - - ram2k ram1_inst( - .clock(memclk), - //.ena(~ram1_cs_b), - .clken(ram1_cs), - .wren(~RW), - .address(AB[10:0]), - .data(write_DB), - .q(ram1_DB_out) - ); - - //assign bios_cs_b = ~(AB[15] & ~bios_en_b); - - - BIOS_ROM BIOS_ROM( - .clock(memclk), - .clken(bios_cs), - .address(AB[11:0]), - .q(bios_DB_out) - ); - - assign pclk_2 = ~pclk_0; -// console_pll console_pll ( -// .inclk0(CLOCK_PLL), -// .c0(clock_100), -// .c1(clock_25), // 25 MHz -// .c2(sysclk_7_143), // 7.143 MHz. Divide to 1.79 MHz -// .locked(clock_divider_locked) -// ); - - assign VSync = vga_vsync; - assign HSync = vga_hsync; - - // VGA - uv_to_vga vga_out( - .clk(clock_25), .reset(reset), - .uv_in(uv_display), - .row(vga_row), .col(vga_col), - .RED(RED), .GREEN(GREEN), .BLUE(BLUE), - .HSync(vga_hsync), .VSync(vga_vsync), - .tia_en(tia_en), - .tia_hblank(hblank_tia), - .tia_vblank(vblank_tia), - .tia_clk(tia_clk) - ); - - // VIDEO - always_comb case ({maria_en, tia_en}) - 2'b00: uv_display = uv_maria; - 2'b01: uv_display = uv_tia; - 2'b10: uv_display = uv_maria; - 2'b11: uv_display = uv_tia; - default: uv_display = uv_maria; - endcase - - // MARIA - maria maria_inst( - .AB_in(AB), - .AB_out(maria_AB_out), - .drive_AB(maria_drive_AB), - .read_DB_in(read_DB), - .write_DB_in(write_DB), - .DB_out(maria_DB_out), - .bios_en(~bios_en_b), - .reset(reset), - .sysclk(sysclk_7_143), - .pclk_2(pclk_2), - .sel_slow_clock(sel_slow_clock), - .core_latch_data(core_latch_data), - .tia_en(tia_en), - .tia_clk(tia_clk), - .pclk_0(pclk_0), - .CS(CS), - //.ram0_b(ram0_cs_b), - //.ram1_b(ram1_cs_b), - //.p6532_b(riot_cs_b), - //.tia_b(tia_cs_b), - //.riot_ram_b(riot_RS_b), - .RW(RW), - .enable(maria_en), - .vga_row(vga_row), - .vga_col(vga_col), - .UV_out(uv_maria), - .int_b(m_int_b), - .halt_b(halt_b), - .ready(maria_RDY) - ); - - // TIA - TIA tia_inst(.A({(AB[5] & tia_en), AB[4:0]}), // Address bus input - .Din(write_DB), // Data bus input - .Dout(tia_DB_out), // Data bus output - .CS_n({2'b0,~tia_cs}), // Active low chip select input - .CS(tia_cs), // Chip select input - .R_W_n(RW), // Active low read/write input - .RDY(tia_RDY), // CPU ready output - .MASTERCLK(tia_clk), // 3.58 Mhz pixel clock input - .CLK2(pclk_0), // 1.19 Mhz bus clock input - .idump_in(idump), // Dumped I/O - .Ilatch(ilatch), // Latched I/O - .HSYNC(tia_hsync), // Video horizontal sync output - .HBLANK(hblank_tia), // Video horizontal blank output - .VSYNC(tia_vsync), // Video vertical sync output - .VBLANK(vblank_tia), // Video vertical sync output - .COLOROUT(uv_tia), // Indexed color output - .RES_n(~reset), // Active low reset input - .AUD0(aud0), //audio pin 0 - .AUD1(aud1), //audio pin 1 - .audv0(audv0), //audio volume for use with external xformer module - .audv1(audv1) //audio volume for use with external xformer module - ); - - audio_xformer audio_xform(.AUD0(aud0), .AUD1(aud1), .AUDV0(audv0), - .AUDV1(audv1), .AUD_SIGNAL(aud_signal_out)); - - //RIOT - RIOT riot_inst(.A(AB[6:0]), // Address bus input - .Din(write_DB), // Data bus input - .Dout(riot_DB_out), // Data bus output - .CS(riot_cs), // Chip select input - .CS_n(~riot_cs), // Active low chip select input - .R_W_n(RW), // Active high read, active low write input - .RS_n(~riot_ram_cs), // Active low rom select input - .RES_n(~reset), // Active low reset input - .IRQ_n(), // Active low interrupt output - .CLK(pclk_0), // Clock input - .PAin(PAin), // 8 bit port A input - .PAout(PAout), // 8 bit port A output - .PBin(PBin), // 8 bit port B input - .PBout(PBout)); // 8 bit port B output - - //6502 - assign cpu_reset = cpu_reset_counter != 3'b111; - - always_ff @(posedge pclk_0, posedge reset) begin - if (reset) begin - cpu_reset_counter <= 3'b0; - end else begin - if (cpu_reset_counter != 3'b111) - cpu_reset_counter <= cpu_reset_counter + 3'b001; - end - end - - - assign RDY = maria_en ? maria_RDY : ((tia_en) ? tia_RDY : clock_divider_locked); - - assign core_halt_b = (ctrl_writes == 2'd2) ? halt_b : 1'b1; - - /// DEBUG /////////////////////////////////////////// - `ifndef SIM - - (* keep = "true" *) - logic [15:0] pc_temp; - - assign ld[1] = pc_reached_230a; - assign ld[2] = pc_reached_26bc; - //assign ld[3] = pc_reached_fbad; - assign ld[4] = pc_reached_fbbd; - assign ld[5] = pc_reached_faaf; - - - assign ld[6] = tia_en; - assign ld[7] = maria_en; - - logic pc_reached_230a; // Beginning of RAM code - logic pc_reached_26bc; // Exit BIOS - logic pc_reached_fbad; // waiting for VSYNC - logic pc_reached_fbbd; // done waiting for VSYNC - logic pc_reached_faaf; // NMI handler - - always_ff @(posedge sysclk_7_143, posedge reset) begin - if (reset) begin - pc_reached_230a <= 1'b0; - pc_reached_26bc <= 1'b0; - pc_reached_fbad <= 1'b0; - pc_reached_fbbd <= 1'b0; - pc_reached_faaf <= 1'b0; - end else begin - if (pc_temp == 16'h230a) - pc_reached_230a <= 1'b1; - if (pc_temp == 16'h23ee) - pc_reached_26bc <= 1'b1; - if (pc_temp == 16'hfbad) - pc_reached_fbad <= 1'b1; - if (pc_temp == 16'hfbbd) - pc_reached_fbbd <= 1'b1; - if (pc_temp == 16'hfaaf) - pc_reached_faaf <= 1'b1; - end - end - `endif - ////////////////////////////////////////////////////// - - assign CPU_NMI = (lock_ctrl) ? (~m_int_b) : (~m_int_b & ~bios_en_b); - - cpu_wrapper cpu_inst(.clk(pclk_0), - .core_latch_data(core_latch_data), - .sysclk(sysclk_7_143), - .reset(cpu_reset), - .AB(core_AB_out), - .DB_IN(read_DB), - .DB_OUT(core_DB_out), - .RD(RW), - .IRQ(~IRQ_n), - .NMI(CPU_NMI), - .RDY(RDY), - .halt_b(core_halt_b), - .pc_temp(pc_temp)); - - - - ctrl_reg ctrl(.clk(pclk_0), - .lock_in(write_DB[0]), - .maria_en_in(write_DB[1]), - .bios_en_in(write_DB[2]), - .tia_en_in(write_DB[3]), - .latch_b(RW | ~tia_cs | lock_ctrl), - .rst(reset), - .lock_out(lock_ctrl), - .maria_en_out(maria_en), - .bios_en_out(bios_en_b), - .tia_en_out(tia_en), - .writes(ctrl_writes)); - - -endmodule - -module ctrl_reg(input logic clk, lock_in, maria_en_in, bios_en_in, tia_en_in, latch_b, rst, - output logic lock_out, maria_en_out, bios_en_out, tia_en_out, - output logic [1:0] writes); - - - always_ff @(posedge clk, posedge rst) begin - if (rst) begin - lock_out <= 0; - maria_en_out <= 0; - bios_en_out <= 0; - tia_en_out <= 0; - writes <= 0; - end - else if (~latch_b) begin - lock_out <= lock_in; - maria_en_out <= maria_en_in; - bios_en_out <= bios_en_in; - tia_en_out <= tia_en_in; - if (writes < 2'd2) - writes <= writes + 1; - end - end -endmodule diff --git a/Console_MiST/Atari - 7800_TeST/rtl/BIOS_ROM.v b/Console_MiST/Atari - 7800_TeST/rtl/BIOS_ROM.v deleted file mode 100644 index 197fe978..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/BIOS_ROM.v +++ /dev/null @@ -1,169 +0,0 @@ -// megafunction wizard: %ROM: 1-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: BIOS_ROM.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.4 Build 182 03/12/2014 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2014 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module BIOS_ROM ( - address, - clken, - clock, - q); - - input [11:0] address; - input clken; - input clock; - output [7:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clken; - tri1 clock; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] q = sub_wire0[7:0]; - - altsyncram altsyncram_component ( - .address_a (address), - .clock0 (clock), - .clocken0 (clken), - .q_a (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .address_b (1'b1), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_a ({8{1'b1}}), - .data_b (1'b1), - .eccstatus (), - .q_b (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_a (1'b0), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_a = "NONE", - altsyncram_component.clock_enable_input_a = "NORMAL", - altsyncram_component.clock_enable_output_a = "NORMAL", -`ifdef NO_PLI - altsyncram_component.init_file = "../rtl/rom/7800ntsc.rif" -`else - altsyncram_component.init_file = "../rtl/rom/7800ntsc.hex" -`endif -, - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 4096, - altsyncram_component.operation_mode = "ROM", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_reg_a = "CLOCK0", - altsyncram_component.widthad_a = 12, - altsyncram_component.width_a = 8, - altsyncram_component.width_byteena_a = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -// Retrieval info: PRIVATE: AclrByte NUMERIC "0" -// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" -// Retrieval info: PRIVATE: Clken NUMERIC "1" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "../rtl/rom/7800ntsc.hex" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: RegAddr NUMERIC "1" -// Retrieval info: PRIVATE: RegOutput NUMERIC "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: SingleClock NUMERIC "1" -// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" -// Retrieval info: PRIVATE: WidthData NUMERIC "8" -// Retrieval info: PRIVATE: rden NUMERIC "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL" -// Retrieval info: CONSTANT: INIT_FILE STRING "../rtl/rom/7800ntsc.hex" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" -// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_ROM.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_ROM.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_ROM.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_ROM.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_ROM_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL BIOS_ROM_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Console_MiST/Atari - 7800_TeST/rtl/RIOT.sv b/Console_MiST/Atari - 7800_TeST/rtl/RIOT.sv deleted file mode 100644 index 917c7079..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/RIOT.sv +++ /dev/null @@ -1,174 +0,0 @@ -/* Atari on an FPGA -Masters of Engineering Project -Cornell University, 2007 -Daniel Beer - RIOT.v -Redesign of the MOS 6532 chip. Provides RAM, I/O and timers to the Atari. -*/ -`timescale 1ns / 1ps - -`include "riot.vh" -module RIOT(A, // Address bus input - Din, // Data bus input - Dout, // Data bus output - CS, // Chip select input - CS_n, // Active low chip select input - R_W_n, // Active low read/write input - RS_n, // Active low rom select input - RES_n, // Active low reset input - IRQ_n, // Active low interrupt output - CLK, // Clock input - PAin, // 8 bit port A input - PAout, // 8 bit port A output - PBin, // 8 bit port B input - PBout);// 8 bit port B output - input [6:0] A; - input [7:0] Din; - output [7:0] Dout; - input CS, CS_n, R_W_n, RS_n, RES_n, CLK; - output IRQ_n; - input [7:0] PAin, PBin; - output [7:0] PAout, PBout; // Output register - reg [7:0] Dout; // RAM allocation - reg [7:0] RAM[127:0]; // I/O registers - reg [7:0] DRA, DRB; // Data registers - reg [7:0] DDRA, DDRB; // Data direction registers - wire PA7; - reg R_PA7; - assign PA7 = (PAin[7] & ~DDRA[7]) | (DRA[7] & DDRA[7]); - assign PAout = DRA & DDRA; - assign PBout = DRB & DDRB; - // Timer registers - reg [8:0] Timer; - reg [9:0] Prescaler; - reg [1:0] Timer_Mode; - reg Timer_Int_Flag, PA7_Int_Flag, Timer_Int_Enable, PA7_Int_Enable, PA7_Int_Mode; // Timer prescaler constants - wire [9:0] PRESCALER_VALS[3:0]; - assign PRESCALER_VALS[0] = 10'd0; - assign PRESCALER_VALS[1] = 10'd7; - assign PRESCALER_VALS[2] = 10'd63; - assign PRESCALER_VALS[3] = 10'd1023; - // Interrupt - assign IRQ_n = ~(Timer_Int_Flag & Timer_Int_Enable | PA7_Int_Flag & PA7_Int_Enable); - // Operation decoding - wire [6:0] op; - reg [6:0] R_op; - assign op = {RS_n, R_W_n, A[4:0]}; - // Registered data in - reg [7:0] R_Din; - integer cnt; - // Software operations - always @(posedge CLK) - begin - // Reset operation - if (~RES_n) begin - DRA <= 8'b0; - DDRA <= 8'b0; - DRB <= 8'b00010100; - DDRB <= 8'b00010100; - Timer_Int_Flag <= 1'b0; - PA7_Int_Flag <= 1'b0; - PA7_Int_Enable <= 1'b0; - PA7_Int_Mode <= 1'b0; - // Fill RAM with 0s - for (cnt = 0; cnt < 128; cnt = cnt + 1) - RAM[cnt] <= 8'b0; - R_PA7 <= 1'b0; - R_op <= `NOP; - R_Din <= 8'b0; - end - // If the chip is enabled, execute an operation - else if (CS & ~CS_n) begin - // Register inputs for use later - R_PA7 <= PA7; - R_op <= op; - R_Din <= Din; - // Update the timer interrupt flag - casex (op) - `WRITE_TIMER: Timer_Int_Flag <= 1'b0; - `READ_TIMER: Timer_Int_Flag <= 1'b0; - default: if (Timer == 9'b111111111) Timer_Int_Flag <= 1'b1; - endcase - // Update the port A interrupt flag - casex (op) - `READ_INT_FLAG: PA7_Int_Flag <= 1'b0; - default: PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode); - endcase - // Process the current operation - casex(op) // RAM access - `READ_RAM: Dout <= RAM[A]; - `WRITE_RAM: RAM[A] <= Din; - // Port A data access - `READ_DRA : Dout <= (PAin & ~DDRA) | (DRA & DDRA); - `WRITE_DRA: DRA <= Din; - // Port A direction register access - `READ_DDRA: Dout <= DDRA; - `WRITE_DDRA: DDRA <= Din; - // Port B data access - `READ_DRB: Dout <= (PBin & ~DDRB) | (DRB & DDRB); - `WRITE_DRB: DRB <= Din; - // Port B direction register access - `READ_DDRB: Dout <= DDRB; - `WRITE_DDRB: DDRB <= Din; - // Timer access - `READ_TIMER: Dout <= Timer[7:0]; - // Status register access - `READ_INT_FLAG: Dout <= {Timer_Int_Flag, PA7_Int_Flag, 6'b0}; - // Enable the port A interrupt - `WRITE_EDGE_DETECT: begin - PA7_Int_Mode <= A[0]; PA7_Int_Enable <= A[1]; - end - endcase - end - // Even if the chip is not enabled, update background functions - else begin - // Update the timer interrupt - if (Timer == 9'b111111111) - Timer_Int_Flag <= 1'b1; - // Update the port A interrupt - R_PA7 <= PA7; - PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode); - // Set the operation to a NOP - R_op <=`NOP; - end - end - // Update the timer at the negative edge of the clock - always @(negedge CLK)begin - // Reset operation - if (~RES_n) begin - Timer <= 9'b0; - Timer_Mode <= 2'b0; - Prescaler <= 10'b0; - Timer_Int_Enable <= 1'b0; - end - // Otherwise, process timer operations - else - casex - (R_op) - // Write value to the timer and update the prescaler based on the address - `WRITE_TIMER:begin - Timer <= {1'b0, R_Din}; - Timer_Mode <= R_op[1:0]; - Prescaler <= PRESCALER_VALS[R_op[1:0]]; - Timer_Int_Enable <= R_op[3]; - end - // Otherwise decrement the prescaler and if necessary the timer. - // The prescaler holds a variable number of counts that must be - // run before the timer is decremented - default:if (Timer != 9'b100000000) begin - if (Prescaler != 10'b0) - Prescaler <= Prescaler - 10'b1; - else begin - if (Timer == 9'b0) - begin - Prescaler <= 10'b0; - Timer_Mode <= 2'b0; - end - else - Prescaler <= PRESCALER_VALS[Timer_Mode]; - Timer <= Timer - 9'b1; - end - end - endcase - end -endmodule diff --git a/Console_MiST/Atari - 7800_TeST/rtl/TIA.sv b/Console_MiST/Atari - 7800_TeST/rtl/TIA.sv deleted file mode 100644 index 61852f62..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/TIA.sv +++ /dev/null @@ -1,477 +0,0 @@ -/* Atari on an FPGA - Masters of Engineering Project - Cornell University, 2007 - Daniel Beer - TIA.v - Redesign of the Atari TIA chip. Provides the Atari with video generation, - sound generation and I/O. - */ - `timescale 1ns / 1ps - -`include "tia.vh" -module TIA(A, // Address bus input - Din, // Data bus input - Dout, // Data bus output - CS_n, // Active low chip select input - CS, // Chip select input - R_W_n, // Active low read/write input - RDY, // CPU ready output - MASTERCLK, // 3.58 Mhz pixel clock input - CLK2, // 1.19 Mhz bus clock input - idump_in, // Dumped I/O - Ilatch, // Latched I/O - HSYNC, // Video horizontal sync output - HBLANK, // Video horizontal blank output - VSYNC, // Video vertical sync output - VBLANK, // Video vertical sync output - COLOROUT, // Indexed color output - RES_n, // Active low reset input - AUD0, //audio pin 0 - AUD1, //audio pin 1 - audv0, //audio volume for use with external xformer module - audv1); //audio volume for use with external xformer module - input [5:0] A; - input [7:0] Din; - output [7:0] Dout; - input [2:0] CS_n; - input CS; - input R_W_n; - output RDY; - input MASTERCLK; - input CLK2; - input [1:0] Ilatch; - input [3:0] idump_in; - output HSYNC, HBLANK; - output VSYNC, VBLANK; - output [7:0] COLOROUT; - input RES_n; - output AUD0, AUD1; - output reg [3:0] audv0, audv1; - // Data output register - reg [7:0] Dout; - // Video control signal registers - wire HSYNC; - reg VSYNC, VBLANK; - // Horizontal pixel counter - reg [7:0] hCount; - reg [3:0] hCountReset; - reg clk_30; - reg [7:0] clk_30_count; - - wire [3:0] Idump; - - // Pixel counter update - always @(posedge MASTERCLK) - begin - // Reset operation - if (~RES_n) begin - hCount <= 8'd0; - hCountReset[3:1] <= 3'd0; - clk_30 <= 0; - clk_30_count <= 0; - latchedInputs <= 2'b11; - end - else begin - if (inputLatchReset) - latchedInputs <= 2'b11; - else - latchedInputs <= latchedInputs & Ilatch; - - if (clk_30_count == 57) begin - clk_30 <= ~clk_30; - clk_30_count <= 0; - end else begin - clk_30_count <= clk_30_count + 1; - end - // Increment the count and reset if necessary - if ((hCountReset[3]) ||(hCount == 8'd227)) - hCount <= 8'd0; - else - hCount <= hCount + 8'd1; - // Software resets are delayed by three cycles - hCountReset[3:1] <= hCountReset[2:0]; - end - end - assign HSYNC = (hCount >= 8'd20) && (hCount < 8'd36); - assign HBLANK = (hCount < 8'd68); - // Screen object registers - // These registers are set by the software and used to generate pixels - reg [7:0] player0Pos, player1Pos, missile0Pos, missile1Pos, ballPos; - reg [4:0] player0Size, player1Size; - reg [7:0] player0Color, player1Color, ballColor, pfColor, bgColor; - reg [3:0] player0Motion, player1Motion, missile0Motion, missile1Motion, - ballMotion; - reg missile0Enable, missile1Enable, ballEnable, R_ballEnable; - reg [1:0] ballSize; - reg [19:0] pfGraphic; - reg [7:0] player0Graphic, player1Graphic; - reg [7:0] R_player0Graphic, R_player1Graphic; - reg pfReflect, player0Reflect, player1Reflect; - reg prioCtrl; - reg pfColorCtrl; - reg [14:0] collisionLatch; - reg missile0Lock, missile1Lock; - reg player0VertDelay, player1VertDelay, ballVertDelay; - reg [3:0] audc0, audc1; - reg [4:0] audf0, audf1; - // Pixel number calculation - wire [7:0] pixelNum; - - - //audio control - audio audio_ctrl(.AUDC0(audc0), - .AUDC1(audc1), - .AUDF0(audf0), - .AUDF1(audf1), - .CLK_30(clk_30), //30khz clock - .AUD0(AUD0), - .AUD1(AUD1)); - - assign pixelNum = (hCount >= 8'd68) ? (hCount - 8'd68) : 8'd227; - - // Pixel tests. For each pixel and screen object, a test is done based on the - // screen objects register to determine if the screen object should show on that - // pixel. The results of all the tests are fed into logic to pick which displayed - // object has priority and color the pixel the color of that object. - // Playfield pixel test - wire [5:0] pfPixelNum; - wire pfPixelOn, pfLeftPixelVal, pfRightPixelVal; - assign pfPixelNum = pixelNum[7:2]; - assign pfLeftPixelVal = pfGraphic[pfPixelNum]; - assign pfRightPixelVal = (pfReflect == 1'b0)? pfGraphic[pfPixelNum - 6'd20]: - pfGraphic[6'd39 - pfPixelNum]; - assign pfPixelOn = (pfPixelNum < 6'd20)? pfLeftPixelVal : pfRightPixelVal; - // Player 0 sprite pixel test - wire pl0PixelOn; - wire [7:0] pl0Mask, pl0MaskDel; - assign pl0MaskDel = (player0VertDelay)? R_player0Graphic : player0Graphic; - assign pl0Mask = (!player0Reflect)? pl0MaskDel : {pl0MaskDel[0], pl0MaskDel[1], - pl0MaskDel[2], pl0MaskDel[3], - pl0MaskDel[4], pl0MaskDel[5], - pl0MaskDel[6], pl0MaskDel[7]}; - objPixelOn player0_test(pixelNum, player0Pos, player0Size[2:0], pl0Mask, pl0PixelOn); - // Player 1 sprite pixel test - wire pl1PixelOn; - wire [7:0] pl1Mask, pl1MaskDel; - assign pl1MaskDel = (player1VertDelay)? R_player1Graphic : player1Graphic; - assign pl1Mask = (!player1Reflect)? pl1MaskDel : {pl1MaskDel[0], pl1MaskDel[1], - pl1MaskDel[2], pl1MaskDel[3], - pl1MaskDel[4], pl1MaskDel[5], - pl1MaskDel[6], pl1MaskDel[7]}; - objPixelOn player1_test(pixelNum, player1Pos, player1Size[2:0], pl1Mask, pl1PixelOn); - // Missile 0 pixel test - wire mis0PixelOn, mis0PixelOut; - wire [7:0] mis0ActualPos; - reg [7:0] mis0Mask; - always @(player0Size) - begin - case(player0Size[4:3]) - 2'd0: mis0Mask <= 8'h01; - 2'd1: mis0Mask <= 8'h03; - 2'd2: mis0Mask <= 8'h0F; - 2'd3: mis0Mask <= 8'hFF; - endcase - end - assign mis0ActualPos = (missile0Lock)? player0Pos : missile0Pos; - objPixelOn missile0_test(pixelNum, mis0ActualPos, player0Size[2:0], mis0Mask, mis0PixelOut); - assign mis0PixelOn = mis0PixelOut && missile0Enable; - // Missile 1 pixel test - wire mis1PixelOn, mis1PixelOut; - wire [7:0] mis1ActualPos; - reg [7:0] mis1Mask; - always @(player1Size) - begin - case(player1Size[4:3]) - 2'd0: mis1Mask <= 8'h01; - 2'd1: mis1Mask <= 8'h03; - 2'd2: mis1Mask <= 8'h0F; - 2'd3: mis1Mask <= 8'hFF; - endcase - end - assign mis1ActualPos = (missile1Lock)? player1Pos : missile1Pos; - objPixelOn missile1_test(pixelNum, mis1ActualPos, player1Size[2:0], mis1Mask, mis1PixelOut); - assign mis1PixelOn = mis1PixelOut && missile1Enable; - // Ball pixel test - wire ballPixelOut, ballPixelOn, ballEnableDel; - reg [7:0] ballMask; - always @(ballSize) - begin - case(ballSize) - 2'd0: ballMask <= 8'h01; - 2'd1: ballMask <= 8'h03; - 2'd2: ballMask <= 8'h0F; - 2'd3: ballMask <= 8'hFF; - endcase - end - objPixelOn ball_test(pixelNum, ballPos, 3'd0, ballMask, ballPixelOut); - assign ballEnableDel = ((ballVertDelay)? R_ballEnable : ballEnable); - assign ballPixelOn = ballPixelOut && ballEnableDel; - // Playfield color selection - // The programmer can select a unique color for the playfield or have it match - // the player's sprites colors - reg [7:0] pfActualColor; - always @(pfColorCtrl, pfColor, player0Color, player1Color, pfPixelNum) - begin - if (pfColorCtrl) - begin - if (pfPixelNum < 6'd20) - pfActualColor <= player0Color; - else - pfActualColor <= player1Color; - end - else - pfActualColor <= pfColor; - end - // Final pixel color selection - reg [7:0] pixelColor; - assign COLOROUT = (HBLANK)? 8'b0 : pixelColor; - // This combinational logic uses a priority encoder like structure to select - // the highest priority screen object and color the pixel. - always @(prioCtrl, pfPixelOn, pl0PixelOn, pl1PixelOn, mis0PixelOn, mis1PixelOn, - ballPixelOn, pfActualColor, player0Color, player1Color, bgColor) - begin - // Show the playfield behind the players - if (!prioCtrl) - begin - if (pl0PixelOn || mis0PixelOn) - pixelColor <= player0Color; - else if (pl1PixelOn || mis1PixelOn) - pixelColor <= player1Color; - else if (pfPixelOn) - pixelColor <= pfActualColor; - else - pixelColor <= bgColor; - end - // Otherwise, show the playfield in front of the players - else begin - if (pfPixelOn) - pixelColor <= pfActualColor; - else if (pl0PixelOn || mis0PixelOn) - pixelColor <= player0Color; - else if (pl1PixelOn || mis1PixelOn) - pixelColor <= player1Color; - else - pixelColor <= bgColor; - end - end - // Collision register and latching update - wire [14:0] collisions; - reg collisionLatchReset; - assign collisions = {pl0PixelOn && pl1PixelOn, mis0PixelOn && mis1PixelOn, - ballPixelOn && pfPixelOn, - mis1PixelOn && pfPixelOn, mis1PixelOn && ballPixelOn, - mis0PixelOn && pfPixelOn, mis0PixelOn && ballPixelOn, - pl1PixelOn && pfPixelOn, pl1PixelOn && ballPixelOn, - pl0PixelOn && pfPixelOn, pl0PixelOn && ballPixelOn, - mis1PixelOn && pl0PixelOn, mis1PixelOn && pl1PixelOn, - mis0PixelOn && pl1PixelOn, mis0PixelOn && pl0PixelOn}; - always @(posedge MASTERCLK, posedge collisionLatchReset) - begin - if (collisionLatchReset) - collisionLatch <= 15'b000000000000000; - else - collisionLatch <= collisionLatch | collisions; - end - // WSYNC logic - // When a WSYNC is signalled by the programmer, the CPU ready line is lowered - // until the end of a scanline - reg wSync, wSyncReset; - always @(hCount, wSyncReset) - begin - if (hCount == 8'd0) - wSync <= 1'b0; - else if (wSyncReset && hCount > 8'd2) - wSync <= 1'b1; - end - assign RDY = ~wSync; - // Latched input registers and update - wire [1:0] latchedInputsValue; - reg inputLatchEnabled; - reg inputLatchReset; - reg [1:0] latchedInputs; - - /*always_ff @(Ilatch, inputLatchReset) - begin - if (inputLatchReset) - latchedInputs <= 2'b11; - else - latchedInputs <= latchedInputs & Ilatch; - end*/ - - assign latchedInputsValue = (inputLatchEnabled)? latchedInputs : Ilatch; - // Dumped input registers update - reg inputDumpEnabled; - assign Idump = (inputDumpEnabled)? 4'b0000 : idump_in; - // Software operations - always @(posedge CLK2) - begin - // Reset operation - if (~RES_n) begin - inputLatchReset <= 1'b0; - collisionLatchReset <= 1'b0; - hCountReset[0] <= 1'b0; - wSyncReset <= 1'b0; - Dout <= 8'b00000000; - end - // If the chip is enabled, execute an operation - else if (CS) begin - // Software reset signals - inputLatchReset <= ({R_W_n, A[5:0]} == `VBLANK && Din[6] && !inputLatchEnabled); - collisionLatchReset <= ({R_W_n, A[5:0]} == `CXCLR); - hCountReset[0] <= ({R_W_n, A[5:0]} == `RSYNC); - wSyncReset <= ({R_W_n, A[5:0]} == `WSYNC) && !wSync; - case({R_W_n, A[5:0]}) - // Collision latch reads - `CXM0P, `CXM0P_7800: Dout <= {collisionLatch[1:0],6'b000000}; - `CXM1P, `CXM1P_7800: Dout <= {collisionLatch[3:2],6'b000000}; - `CXP0FB, `CXP0FB_7800: Dout <= {collisionLatch[5:4],6'b000000}; - `CXP1FB, `CXP1FB_7800: Dout <= {collisionLatch[7:6],6'b000000}; - `CXM0FB, `CXM0FB_7800: Dout <= {collisionLatch[9:8],6'b000000}; - `CXM1FB, `CXM1FB_7800: Dout <= {collisionLatch[11:10],6'b000000}; - `CXBLPF, `CXBLPF_7800: Dout <= {collisionLatch[12],7'b0000000}; - `CXPPMM, `CXPPMM_7800: Dout <= {collisionLatch[14:13],6'b000000}; - // I/O reads - `INPT0, `INPT0_7800: Dout <= {Idump[0], 7'b0000000}; - `INPT1, `INPT1_7800: Dout <= {Idump[1], 7'b0000000}; - `INPT2, `INPT2_7800: Dout <= {Idump[2], 7'b0000000}; - `INPT3, `INPT3_7800: Dout <= {Idump[3], 7'b0000000}; - `INPT4, `INPT4_7800: Dout <= {latchedInputsValue[0], 7'b0000000}; - `INPT5, `INPT5_7800: Dout <= {latchedInputsValue[1], 7'b0000000}; - // Video signals - `VSYNC: VSYNC <= Din[1]; - `VBLANK: begin - inputLatchEnabled <= Din[6]; - inputDumpEnabled <= Din[7]; - VBLANK <= Din[1]; - end - `WSYNC:; - `RSYNC:; - // Screen object register access - `NUSIZ0: player0Size <= {Din[5:4],Din[2:0]}; - `NUSIZ1: player1Size <= {Din[5:4],Din[2:0]}; - `COLUP0: player0Color <= Din; - `COLUP1: player1Color <= Din; - `COLUPF: pfColor <= Din; - `COLUBK: bgColor <= Din; - `CTRLPF: begin - pfReflect <= Din[0]; - pfColorCtrl <= Din[1]; - prioCtrl <= Din[2]; - ballSize <= Din[5:4]; - end - `REFP0: player0Reflect <= Din[3]; - `REFP1: player1Reflect <= Din[3]; - `PF0: pfGraphic[3:0] <= Din[7:4]; - `PF1: pfGraphic[11:4] <= {Din[0], Din[1], Din[2], Din[3], - Din[4], Din[5], Din[6], Din[7]}; - `PF2: pfGraphic[19:12] <= Din[7:0]; - `RESP0: player0Pos <= pixelNum; - `RESP1: player1Pos <= pixelNum; - `RESM0: missile0Pos <= pixelNum; - `RESM1: missile1Pos <= pixelNum; - `RESBL: ballPos <= pixelNum; - // Audio controls - `AUDC0: audc0 <= Din[3:0]; - `AUDC1: audc1 <= Din[3:0]; - `AUDF0: audf0 <= Din[4:0]; - `AUDF1: audf1 <= Din[4:0]; - `AUDV0: audv0 <= Din[3:0]; - `AUDV1: audv1 <= Din[3:0]; - // Screen object register access - `GRP0: begin - player0Graphic <= {Din[0], Din[1], Din[2], Din[3], - Din[4], Din[5], Din[6], Din[7]}; - R_player1Graphic <= player1Graphic; - end - `GRP1: begin - player1Graphic <= {Din[0], Din[1], Din[2], Din[3], - Din[4], Din[5], Din[6], Din[7]}; - R_player0Graphic <= player0Graphic; - R_ballEnable <= ballEnable; - end - `ENAM0: missile0Enable <= Din[1]; - `ENAM1: missile1Enable <= Din[1]; - `ENABL: ballEnable <= Din[1]; - `HMP0: player0Motion <= Din[7:4]; - `HMP1: player1Motion <= Din[7:4]; - `HMM0: missile0Motion <= Din[7:4]; - `HMM1: missile1Motion <= Din[7:4]; - `HMBL: ballMotion <= Din[7:4]; - `VDELP0: player0VertDelay <= Din[0]; - `VDELP1: player1VertDelay <= Din[0]; - `VDELBL: ballVertDelay <= Din[0]; - `RESMP0: missile0Lock <= Din[1]; - `RESMP1: missile1Lock <= Din[1]; - // Strobed line that initiates an object move - `HMOVE: begin - player0Pos <= player0Pos - {{4{player0Motion[3]}}, - player0Motion[3:0]}; - player1Pos <= player1Pos - {{4{player1Motion[3]}}, - player1Motion[3:0]}; - missile0Pos <= missile0Pos - {{4{missile0Motion[3]}}, - missile0Motion[3:0]}; - missile1Pos <= missile1Pos - {{4{missile1Motion[3]}}, - missile1Motion[3:0]}; - ballPos <= ballPos - {{4{ballMotion[3]}},ballMotion[3:0]}; - end - // Motion register clear - `HMCLR: begin - player0Motion <= Din[7:4]; - player1Motion <= Din[7:4]; - missile0Motion <= Din[7:4]; - missile1Motion <= Din[7:4]; - ballMotion <= Din[7:4]; - end - `CXCLR:; - default: Dout <= 8'b00000000; - endcase - end - // If the chip is not enabled, do nothing - else begin - inputLatchReset <= 1'b0; - collisionLatchReset <= 1'b0; - hCountReset[0] <= 1'b0; - wSyncReset <= 1'b0; - Dout <= 8'b00000000; - end - end -endmodule -// objPixelOn module -// Checks the pixel number against a stretched and possibly duplicated version of the -// object. -module objPixelOn(pixelNum, objPos, objSize, objMask, pixelOn); - input [7:0] pixelNum, objPos, objMask; - input [2:0] objSize; - output pixelOn; - wire [7:0] objIndex; - wire [8:0] objByteIndex; - wire objMaskOn, objPosOn; - reg objSizeOn; - reg [2:0] objMaskSel; - assign objIndex = pixelNum - objPos - 8'd1; - assign objByteIndex = 9'b1 << (objIndex[7:3]); - always @(objSize, objByteIndex) - begin - case (objSize) - 3'd0: objSizeOn <= (objByteIndex & 9'b00000001) != 0; - 3'd1: objSizeOn <= (objByteIndex & 9'b00000101) != 0; - 3'd2: objSizeOn <= (objByteIndex & 9'b00010001) != 0; - 3'd3: objSizeOn <= (objByteIndex & 9'b00010101) != 0; - 3'd4: objSizeOn <= (objByteIndex & 9'b10000001) != 0; - 3'd5: objSizeOn <= (objByteIndex & 9'b00000011) != 0; - 3'd6: objSizeOn <= (objByteIndex & 9'b10010001) != 0; - 3'd7: objSizeOn <= (objByteIndex & 9'b00001111) != 0; - endcase - end - always @(objSize, objIndex) - begin - case (objSize) - 3'd5: objMaskSel <= objIndex[3:1]; - 3'd7: objMaskSel <= objIndex[4:2]; - default: objMaskSel <= objIndex[2:0]; - endcase - end - assign objMaskOn = objMask[objMaskSel]; - assign objPosOn = (pixelNum > objPos) && ({1'b0, pixelNum} <= {1'b0, objPos} + 9'd72); - assign pixelOn = objSizeOn && objMaskOn && objPosOn; -endmodule \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/atari7800.vh b/Console_MiST/Atari - 7800_TeST/rtl/atari7800.vh deleted file mode 100644 index d1d73a75..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/atari7800.vh +++ /dev/null @@ -1,11 +0,0 @@ -`define CS_NONE 'h0 -`define CS_RAM0 'h1 -`define CS_RAM1 'h2 -`define CS_RIOT_IO 'h3 -`define CS_RIOT_RAM 'h4 -`define CS_TIA 'h5 -`define CS_BIOS 'h6 -`define CS_MARIA 'h7 -`define CS_CART 'h8 - -`define chipselect logic[3:0] \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/audio.sv b/Console_MiST/Atari - 7800_TeST/rtl/audio.sv deleted file mode 100644 index e0786a27..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/audio.sv +++ /dev/null @@ -1,93 +0,0 @@ -`timescale 1ns / 1ps - -module audio(input logic [3:0] AUDC0, AUDC1, - input logic [4:0] AUDF0, AUDF1, - input logic CLK_30, //30khz clock - output logic AUD0,AUD1 - ); - - logic [4:0] counter0, counter1 = 5'b0; - integer rep0,rep1,ind0,ind1 = 0; - logic [1:0] pattern45 = 2'b10; - logic pattern0b = 1'b1; - logic [14:0] pattern1 = 15'b111100010011010; - logic [30:0] pattern6a = 31'b1111111111111111110000000000000; - logic [30:0] pattern79 = 31'b1111100011011101010000100101100; - logic [5:0] patterncd = 6'b111000; - logic [92:0] patterne = 93'b111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000000; - logic [92:0] patternf = 93'b111111111100000111000000011110000000000111111000111111000011111111100000011111000000111100000; - logic [464:0] pattern2 = 465'b111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000000000000000000000111111111111100000000000000000000000000000001111111111111111111111111111111000000000000000000111111111111100000000000000000011111111111111111111111111111111111111111111111111111111111111000000000000000000000000000000000000000000001111111111111111110000000000000000000000000000000111111111111111111111111111111100000000000001111111111111111110000000000000; - logic [464:0] pattern3 = 465'b111111000000100011100111110001111111000111100011001100000111111111000100000111011001111111111100000100000111010011111111111100000100111110010111111111111000000100111110110111111111100000011100110000100111111000000000010000110111101111110000000000110000110100001111100000000011100011110101111111100000111110000011110101111111100001100000000111000101111111000011000000011111011101111111000010000111111110010001111000000010001111111000110111111000000110011110000011100; - logic [510:0] pattern8 = 511'b1111111110000011110111110001011100110010000010010100111011010001111001111100110110001010100100011100011011010101110001001100010001000000001000010001100001001110010101011000011011110100110111001000101000010101101001111110110010010010110111111001001101010011001100000001100011001010001101001011111110100010110001110101100101100111100011111011101000001101011011011101100000101101011111010101010000001010010101111001011101110000001110011101001001111010111010100010010000110011100001011110110110011010000111011110000; - - always_comb begin - case (AUDC0) - 4'h0,4'hb: rep0 = 1; - 4'h1: rep0 = 15; - 4'h2,4'h3: rep0 = 465; - 4'h4,4'h5: rep0 = 2; - 4'h6,4'h7,4'h9,4'ha: rep0 = 31; - 4'h8: rep0 = 511; - 4'hc,4'hd: rep0 = 6; - 4'he,4'hf: rep0 = 93; - default: rep0 = 1; - endcase - case (AUDC1) - 4'h0,4'hb: rep1 = 1; - 4'h1: rep1 = 15; - 4'h2,4'h3: rep1 = 465; - 4'h4,4'h5: rep1 = 2; - 4'h6,4'h7,4'h9,4'ha: rep1 = 31; - 4'h8: rep1 = 511; - 4'hc,4'hd: rep1 = 6; - 4'he,4'hf: rep1 = 93; - default: rep0 = 1; - endcase - end - - always_ff @(posedge CLK_30) begin //divide the clk by the frequency value - if (counter0 == AUDF0) begin - case (AUDC0) - 4'h0,4'hb: AUD0 <= pattern0b; - 4'h1: AUD0 <= pattern1[ind0]; - 4'h2: AUD0 <= pattern2[ind0]; - 4'h3: AUD0 <= pattern3[ind0]; - 4'h4,4'h5: AUD0 <= pattern45[ind0]; - 4'h6,4'ha: AUD0 <= pattern6a[ind0]; - 4'h7,4'h9: AUD0 <= pattern79[ind0]; - 4'h8: AUD0 <= pattern8[ind0]; - 4'hc,4'hd: AUD0 <= patterncd[ind0]; - 4'he: AUD0 <= patterne[ind0]; - 4'hf: AUD0 <= patternf[ind0]; - default: AUD0 <= 1'bx; - endcase - ind0 <= (ind0 + 1) % rep0; - counter0 <= 0; - end - else - counter0 <= counter0 + 1; - - if (counter1 == AUDF1) begin - case (AUDC1) - 4'h0,4'hb: AUD1 <= pattern0b; - 4'h1: AUD1 <= pattern1[ind1]; - 4'h2: AUD1 <= pattern2[ind1]; - 4'h3: AUD1 <= pattern3[ind1]; - 4'h4,4'h5: AUD1 <= pattern45[ind1]; - 4'h6,4'ha: AUD1 <= pattern6a[ind1]; - 4'h7,4'h9: AUD1 <= pattern79[ind1]; - 4'h8: AUD1 <= pattern8[ind1]; - 4'hc,4'hd: AUD1 <= patterncd[ind1]; - 4'he: AUD1 <= patterne[ind1]; - 4'hf: AUD1 <= patternf[ind1]; - default: AUD1 <= 1'bx; - endcase - ind1 <= (ind1 + 1) % rep1; - counter1 <= 0; - end - else - counter1 <= counter1 + 1; - end - - -endmodule diff --git a/Console_MiST/Atari - 7800_TeST/rtl/audio_xformer.sv b/Console_MiST/Atari - 7800_TeST/rtl/audio_xformer.sv deleted file mode 100644 index 2ccac83a..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/audio_xformer.sv +++ /dev/null @@ -1,24 +0,0 @@ -`timescale 1ns / 1ps - -module audio_xformer(input logic AUD0, AUD1, - input logic [3:0] AUDV0, AUDV1, - output logic [15:0] AUD_SIGNAL); - - logic [15:0] audio0,audio1; - - - assign AUD_SIGNAL = audio0 + audio1; - - always_comb begin - case (AUD0) - 1: audio0 = 16'h3FF * AUDV0; - 0: audio0 = 16'hFC00 * AUDV0; - endcase - case (AUD1) - 1: audio1 = 16'h3FF * AUDV1; - 0: audio1 = 16'hFC00 * AUDV1; - endcase - end - - -endmodule \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/build_id.tcl b/Console_MiST/Atari - 7800_TeST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/build_id.v b/Console_MiST/Atari - 7800_TeST/rtl/build_id.v deleted file mode 100644 index 3192af89..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/build_id.v +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "180630" -`define BUILD_TIME "212824" diff --git a/Console_MiST/Atari - 7800_TeST/rtl/cart_top.sv b/Console_MiST/Atari - 7800_TeST/rtl/cart_top.sv deleted file mode 100644 index 222f220f..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/cart_top.sv +++ /dev/null @@ -1,257 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 11/02/2015 11:36:06 AM -// Design Name: -// Module Name: cart_top -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - -`include "atari7800.vh" - -`define INPUT_CYCLES 256 -`define INPUT_CYCLES_NBITS 9 - -module cart_top( - input CLOCK_27, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output LED, - output AUDIO_L, - output AUDIO_R, -// output UART_TX,//uses for Tape Record -// input UART_RX,//uses for Tape Play - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input SPI_SS4, - input CONF_DATA0, - - output logic [7:0] ld, - - input logic [7:0] sw, - input logic PB_UP,PB_DOWN,PB_LEFT,PB_RIGHT,PB_CENTER, - - - inout logic [6:0] ctrl_0_fmc, ctrl_1_fmc - ); - -`include "rtl\build_id.v" -assign LED = 1; -localparam CONF_STR = { - "ATARI7800;;", - "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", - "T6,Reset;", - "V,v0.0.",`BUILD_DATE - }; - - - - wire clk25, clk7p143, clk6p25; - wire locked; - - pll pll ( - .inclk0(CLOCK_27), - .c0(clk25), - .c1(clk7p143), - .c2(clk6p25), - .locked(locked) - ); - wire scandoubler_disable; - wire ypbpr; - wire ps2_kbd_clk, ps2_kbd_data; - wire [31:0] status; - wire [1:0] buttons; - wire [1:0] switches; - wire [3:0] r, g, b; - wire hs, vs, hb, vb; - wire blankn = ~(hb | vb); - - - logic [7:0] cart_data_out; - logic [15:0] AB; - logic RW; - logic pclk_0; - reg [`INPUT_CYCLES_NBITS-1:0] paddleA0_ctr = {`INPUT_CYCLES_NBITS{1'b0}}; - reg [`INPUT_CYCLES_NBITS-1:0] paddleB0_ctr = {`INPUT_CYCLES_NBITS{1'b0}}; - reg [`INPUT_CYCLES_NBITS-1:0] paddleA1_ctr = {`INPUT_CYCLES_NBITS{1'b0}}; - reg [`INPUT_CYCLES_NBITS-1:0] paddleB1_ctr = {`INPUT_CYCLES_NBITS{1'b0}}; - - always_ff @(posedge pclk_0) begin - if (~ctrl_0_fmc[6]) - paddleA0_ctr <= 0; - else if (paddleA0_ctr < `INPUT_CYCLES) - paddleA0_ctr <= paddleA0_ctr + 1; - - if (~ctrl_0_fmc[4]) - paddleB0_ctr <= 0; - else if (paddleB0_ctr < `INPUT_CYCLES) - paddleB0_ctr <= paddleB0_ctr + 1; - - if (~ctrl_1_fmc[6]) - paddleA1_ctr <= 0; - else if (paddleA1_ctr < `INPUT_CYCLES) - paddleA1_ctr <= paddleA1_ctr + 1; - - if (~ctrl_1_fmc[4]) - paddleB1_ctr <= 0; - else if (paddleB1_ctr < `INPUT_CYCLES) - paddleB1_ctr <= paddleB1_ctr + 1; - end - - - logic [3:0] idump; - logic [1:0] ilatch; - logic [7:0] PAin, PBin, PAout, PBout; - logic [15:0] audio; - - - logic right_0_b, left_0_b, down_0_b, up_0_b, fire_0_b, paddle_A_0, paddle_B_0; - logic right_1_b, left_1_b, down_1_b, up_1_b, fire_1_b, paddle_A_1, paddle_B_1; - logic player1_2bmode, player2_2bmode; - - assign player1_2bmode = ~PBout[2] & ~tia_en; - assign player2_2bmode = ~PBout[4] & ~tia_en; - - assign {right_0_b, left_0_b, down_0_b, up_0_b} = ctrl_0_fmc[3:0]; - assign {right_1_b, left_1_b, down_1_b, up_1_b} = ctrl_1_fmc[3:0]; - - assign paddle_B_0 = paddleB0_ctr == `INPUT_CYCLES; - assign paddle_B_1 = paddleB1_ctr == `INPUT_CYCLES; - assign paddle_A_0 = paddleA0_ctr == `INPUT_CYCLES; - assign paddle_A_1 = paddleA1_ctr == `INPUT_CYCLES; - - assign fire_0_b = (~paddle_A_0 & ~paddle_B_0); - assign fire_1_b = (~paddle_A_1 & ~paddle_B_1); - logic tia_en; - - assign PAin[7:4] = {right_0_b, left_0_b, down_0_b, up_0_b}; - assign PAin[3:0] = {right_1_b, left_1_b, down_1_b, up_1_b}; - - assign PBin[7] = sw[1]; // RDiff - assign PBin[6] = sw[0]; // LDiff - assign PBin[5] = 1'b0; // Unused - assign PBin[4] = 1'b0; - assign PBin[3] = ~PB_DOWN; // Pause - assign PBin[2] = 1'b0; // 2 Button mode - assign PBin[1] = ~PB_LEFT; // Select - assign PBin[0] = ~PB_UP; // Reset - - - assign ilatch[0] = fire_0_b; - assign ilatch[1] = fire_1_b; - - assign idump = {paddle_A_0, paddle_B_0, paddle_A_1, paddle_B_1}; - - logic [7:0] def_dout; - assign cart_data_out = def_dout; - - defender_rom defender_rom ( - .clock(pclk_0), - .address(AB[11:0]), - .q(def_dout) - ); - - Atari7800 console( - .clock_25(clk25), - .sysclk_7_143(clk7p143), - .clock_divider_locked(locked), - .reset((buttons[1] || status[0] || status[6])), - .RED(r), - .GREEN(g), - .BLUE(b), - .HSync(hs), - .VSync(vs), - .aud_signal_out(audio), - - .cart_DB_out(cart_data_out), - .AB(AB), - .RW(RW), - .pclk_0(pclk_0), - .ld(ld), - .tia_en(tia_en), - - .idump(idump), - .ilatch(ilatch), - .PAin(PAin), - .PBin(PBin), - .PAout(PAout), - .PBout(PBout) - ); - -sigma_delta_dac #(.MSBI(15)) sigma_delta_dac ( - .DACout(AUDIO_L), - .DACin(audio), - .CLK(clk25), - .RESET() -); - -mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io -( - .conf_str(CONF_STR), - .clk_sys(clk25), - .SPI_SCK(SPI_SCK), - .CONF_DATA0(CONF_DATA0), - .SPI_SS2(SPI_SS2), - .SPI_DO(SPI_DO), - .SPI_DI(SPI_DI), - .buttons(buttons), - .switches(switches), - .scandoubler_disable(scandoubler_disable), - .ypbpr(ypbpr), - .status(status), - .ps2_kbd_clk(ps2_kbd_clk), - .ps2_kbd_data(ps2_kbd_data) -); - -video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer -( - .clk_sys(clk25), - .ce_pix(clk6p25), - .ce_pix_actual(clk6p25), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), - .scandoubler_disable(1),//scandoubler_disable), - .hq2x(status[4:3]==1), - .ypbpr(ypbpr), - .ypbpr_full(1), - .R({r,r[1:0]}), - .G({g,g[1:0]}), - .B({b,b[1:0]}), -// .R(blankn ? {r,r[1:0]} : "000000"), -// .G(blankn ? {g,g[1:0]} : "000000"), -// .B(blankn ? {b,b[1:0]} : "000000"), - .mono(0), - .HSync(hs), - .VSync(vs), - .line_start(0), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS) -); - - -assign AUDIO_R = AUDIO_L; - -endmodule diff --git a/Console_MiST/Atari - 7800_TeST/rtl/cpu.sv b/Console_MiST/Atari - 7800_TeST/rtl/cpu.sv deleted file mode 100644 index 64ff3cd8..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/cpu.sv +++ /dev/null @@ -1,1250 +0,0 @@ -/* - * verilog model of 6502 CPU. - * - * (C) Arlet Ottens, - * - * Feel free to use this code in any project (commercial or not), as long as you - * keep this message, and the copyright notice. This code is provided "as is", - * without any warranties of any kind. - * - */ - -/* - * Note that not all 6502 interface signals are supported (yet). The goal - * is to create an Acorn Atom model, and the Atom didn't use all signals on - * the main board. - * - * The data bus is implemented as separate read/write buses. Combine them - * on the output pads if external memory is required. - */ - `timescale 1ns / 1ps -`include "atari7800.vh" - - - - - -module cpu( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY, pc_temp, res); - -input clk; // CPU clock -input reset; // reset signal -output reg [15:0] AB; // address bus -input [7:0] DI; // data in, read bus -output [7:0] DO; // data out, write bus -output WE; // write enable -input IRQ; // interrupt request -input NMI; // non-maskable interrupt request -input RDY; // Ready signal. Pauses CPU when RDY=0 - -output [15:0] pc_temp; -output reg res; - -assign pc_temp = PC_temp; - -/* - * internal signals - */ - -reg [15:0] PC; // Program Counter -reg [7:0] ABL; // Address Bus Register LSB -reg [7:0] ABH; // Address Bus Register MSB -wire [7:0] ADD; // Adder Hold Register (registered in ALU) - -reg [7:0] DIHOLD; // Hold for Data In -reg DIHOLD_valid; // -wire [7:0] DIMUX; // - -reg [7:0] IRHOLD; // Hold for Instruction register -reg IRHOLD_valid; // Valid instruction in IRHOLD - -reg [7:0] AXYS[3:0]; // A, X, Y and S register file - -wire [7:0] AA; -wire [7:0] XX; -wire [7:0] YY; -wire [7:0] SS; -assign YY = AXYS[3]; -assign XX = AXYS[2]; -assign SS = AXYS[1]; -assign AA = AXYS[0]; - -(* keep = "true" *) -wire [15:0] pc_temp_kept; - -assign pc_temp_kept = PC_temp; - -reg C = 0; // carry flag (init at zero to avoid X's in ALU sim) -reg Z = 0; // zero flag -reg I = 0; // interrupt flag -reg D = 0; // decimal flag -reg V = 0; // overflow flag -reg N = 0; // negative flag -wire AZ; // ALU Zero flag -wire AV; // ALU overflow flag -wire AN; // ALU negative flag -wire HC; // ALU half carry - -reg [7:0] AI; // ALU Input A -reg [7:0] BI; // ALU Input B -wire [7:0] DI; // Data In -wire [7:0] IR; // Instruction register -reg [7:0] DO; // Data Out -reg WE; // Write Enable -reg CI; // Carry In -wire CO; // Carry Out -wire [7:0] PCH = PC[15:8]; -wire [7:0] PCL = PC[7:0]; - -reg NMI_edge = 0; // captured NMI edge - -reg [1:0] regsel; // Select A, X, Y or S register -wire [7:0] regfile = AXYS[regsel]; // Selected register output - -parameter - SEL_A = 2'd0, - SEL_S = 2'd1, - SEL_X = 2'd2, - SEL_Y = 2'd3; - -/* - * define some signals for watching in simulator output - */ - - -`ifdef SIM -wire [7:0] A = AXYS[SEL_A]; // Accumulator -wire [7:0] X = AXYS[SEL_X]; // X register -wire [7:0] Y = AXYS[SEL_Y]; // Y register -wire [7:0] S = AXYS[SEL_S]; // Stack pointer -`endif - -wire [7:0] P = { N, V, 2'b11, D, I, Z, C }; - -/* - * instruction decoder/sequencer - */ - -reg [5:0] state; - -/* - * control signals - */ - -reg PC_inc; // Increment PC -reg [15:0] PC_temp; // intermediate value of PC - -reg [1:0] src_reg; // source register index -reg [1:0] dst_reg; // destination register index - -reg index_y; // if set, then Y is index reg rather than X -reg load_reg; // loading a register (A, X, Y, S) in this instruction -reg inc; // increment -reg write_back; // set if memory is read/modified/written -reg load_only; // LDA/LDX/LDY instruction -reg store; // doing store (STA/STX/STY) -reg adc_sbc; // doing ADC/SBC -reg compare; // doing CMP/CPY/CPX -reg shift; // doing shift/rotate instruction -reg rotate; // doing rotate (no shift) -reg backwards; // backwards branch -reg cond_true; // branch condition is true -reg [2:0] cond_code; // condition code bits from instruction -reg shift_right; // Instruction ALU shift/rotate right -reg alu_shift_right; // Current cycle shift right enable -reg [3:0] op; // Main ALU operation for instruction -reg [3:0] alu_op; // Current cycle ALU operation -reg adc_bcd; // ALU should do BCD style carry -reg adj_bcd; // results should be BCD adjusted - -/* - * some flip flops to remember we're doing special instructions. These - * get loaded at the DECODE state, and used later - */ -reg bit_ins; // doing BIT instruction -reg plp; // doing PLP instruction -reg php; // doing PHP instruction -reg clc; // clear carry -reg sec; // set carry -reg cld; // clear decimal -reg sed; // set decimal -reg cli; // clear interrupt -reg sei; // set interrupt -reg clv; // clear overflow -reg brk; // doing BRK - -//reg res; // in reset - -/* - * ALU operations - */ - -parameter - OP_OR = 4'b1100, - OP_AND = 4'b1101, - OP_EOR = 4'b1110, - OP_ADD = 4'b0011, - OP_SUB = 4'b0111, - OP_ROL = 4'b1011, - OP_A = 4'b1111; - -/* - * Microcode state machine. Basically, every addressing mode has its own - * path through the state machine. Additional information, such as the - * operation, source and destination registers are decoded in parallel, and - * kept in separate flops. - */ - -parameter - ABS0 = 6'd0, // ABS - fetch LSB - ABS1 = 6'd1, // ABS - fetch MSB - ABSX0 = 6'd2, // ABS, X - fetch LSB and send to ALU (+X) - ABSX1 = 6'd3, // ABS, X - fetch MSB and send to ALU (+Carry) - ABSX2 = 6'd4, // ABS, X - Wait for ALU (only if needed) - BRA0 = 6'd5, // Branch - fetch offset and send to ALU (+PC[7:0]) - BRA1 = 6'd6, // Branch - fetch opcode, and send PC[15:8] to ALU - BRA2 = 6'd7, // Branch - fetch opcode (if page boundary crossed) - BRK0 = 6'd8, // BRK/IRQ - push PCH, send S to ALU (-1) - BRK1 = 6'd9, // BRK/IRQ - push PCL, send S to ALU (-1) - BRK2 = 6'd10, // BRK/IRQ - push P, send S to ALU (-1) - BRK3 = 6'd11, // BRK/IRQ - write S, and fetch @ fffe - DECODE = 6'd12, // IR is valid, decode instruction, and write prev reg - FETCH = 6'd13, // fetch next opcode, and perform prev ALU op - INDX0 = 6'd14, // (ZP,X) - fetch ZP address, and send to ALU (+X) - INDX1 = 6'd15, // (ZP,X) - fetch LSB at ZP+X, calculate ZP+X+1 - INDX2 = 6'd16, // (ZP,X) - fetch MSB at ZP+X+1 - INDX3 = 6'd17, // (ZP,X) - fetch data - INDY0 = 6'd18, // (ZP),Y - fetch ZP address, and send ZP to ALU (+1) - INDY1 = 6'd19, // (ZP),Y - fetch at ZP+1, and send LSB to ALU (+Y) - INDY2 = 6'd20, // (ZP),Y - fetch data, and send MSB to ALU (+Carry) - INDY3 = 6'd21, // (ZP),Y) - fetch data (if page boundary crossed) - JMP0 = 6'd22, // JMP - fetch PCL and hold - JMP1 = 6'd23, // JMP - fetch PCH - JMPI0 = 6'd24, // JMP IND - fetch LSB and send to ALU for delay (+0) - JMPI1 = 6'd25, // JMP IND - fetch MSB, proceed with JMP0 state - JSR0 = 6'd26, // JSR - push PCH, save LSB, send S to ALU (-1) - JSR1 = 6'd27, // JSR - push PCL, send S to ALU (-1) - JSR2 = 6'd28, // JSR - write S - JSR3 = 6'd29, // JSR - fetch MSB - PULL0 = 6'd30, // PLP/PLA - save next op in IRHOLD, send S to ALU (+1) - PULL1 = 6'd31, // PLP/PLA - fetch data from stack, write S - PULL2 = 6'd32, // PLP/PLA - prefetch op, but don't increment PC - PUSH0 = 6'd33, // PHP/PHA - send A to ALU (+0) - PUSH1 = 6'd34, // PHP/PHA - write A/P, send S to ALU (-1) - READ = 6'd35, // Read memory for read/modify/write (INC, DEC, shift) - REG = 6'd36, // Read register for reg-reg transfers - RTI0 = 6'd37, // RTI - send S to ALU (+1) - RTI1 = 6'd38, // RTI - read P from stack - RTI2 = 6'd39, // RTI - read PCL from stack - RTI3 = 6'd40, // RTI - read PCH from stack - RTI4 = 6'd41, // RTI - read PCH from stack - RTS0 = 6'd42, // RTS - send S to ALU (+1) - RTS1 = 6'd43, // RTS - read PCL from stack - RTS2 = 6'd44, // RTS - write PCL to ALU, read PCH - RTS3 = 6'd45, // RTS - load PC and increment - WRITE = 6'd46, // Write memory for read/modify/write - ZP0 = 6'd47, // Z-page - fetch ZP address - ZPX0 = 6'd48, // ZP, X - fetch ZP, and send to ALU (+X) - ZPX1 = 6'd49; // ZP, X - load from memory - -`ifdef SIM - -/* - * easy to read names in simulator output - */ -reg [8*6-1:0] statename; - -always @* - case( state ) - DECODE: statename = "DECODE"; - REG: statename = "REG"; - ZP0: statename = "ZP0"; - ZPX0: statename = "ZPX0"; - ZPX1: statename = "ZPX1"; - ABS0: statename = "ABS0"; - ABS1: statename = "ABS1"; - ABSX0: statename = "ABSX0"; - ABSX1: statename = "ABSX1"; - ABSX2: statename = "ABSX2"; - INDX0: statename = "INDX0"; - INDX1: statename = "INDX1"; - INDX2: statename = "INDX2"; - INDX3: statename = "INDX3"; - INDY0: statename = "INDY0"; - INDY1: statename = "INDY1"; - INDY2: statename = "INDY2"; - INDY3: statename = "INDY3"; - READ: statename = "READ"; - WRITE: statename = "WRITE"; - FETCH: statename = "FETCH"; - PUSH0: statename = "PUSH0"; - PUSH1: statename = "PUSH1"; - PULL0: statename = "PULL0"; - PULL1: statename = "PULL1"; - PULL2: statename = "PULL2"; - JSR0: statename = "JSR0"; - JSR1: statename = "JSR1"; - JSR2: statename = "JSR2"; - JSR3: statename = "JSR3"; - RTI0: statename = "RTI0"; - RTI1: statename = "RTI1"; - RTI2: statename = "RTI2"; - RTI3: statename = "RTI3"; - RTI4: statename = "RTI4"; - RTS0: statename = "RTS0"; - RTS1: statename = "RTS1"; - RTS2: statename = "RTS2"; - RTS3: statename = "RTS3"; - BRK0: statename = "BRK0"; - BRK1: statename = "BRK1"; - BRK2: statename = "BRK2"; - BRK3: statename = "BRK3"; - BRA0: statename = "BRA0"; - BRA1: statename = "BRA1"; - BRA2: statename = "BRA2"; - JMP0: statename = "JMP0"; - JMP1: statename = "JMP1"; - JMPI0: statename = "JMPI0"; - JMPI1: statename = "JMPI1"; - endcase - -//always @( PC ) -// $display( "%t, PC:%04x IR:%02x A:%02x X:%02x Y:%02x S:%02x C:%d Z:%d V:%d N:%d P:%02x", $time, PC, IR, A, X, Y, S, C, Z, V, N, P ); - -`endif - - - -/* - * Program Counter Increment/Load. First calculate the base value in - * PC_temp. - */ -always @* - case( state ) - DECODE: if( (~I & IRQ) | NMI_edge ) - PC_temp = { ABH, ABL }; - else - PC_temp = PC; - - - JMP1, - JMPI1, - JSR3, - RTS3, - RTI4: PC_temp = { DIMUX, ADD }; - - BRA1: PC_temp = { ABH, ADD }; - - BRA2: PC_temp = { ADD, PCL }; - - BRK2: PC_temp = res ? 16'hfffc : - NMI_edge ? 16'hfffa : 16'hfffe; - - default: PC_temp = PC; - endcase - -/* - * Determine wether we need PC_temp, or PC_temp + 1 - */ -always @* - case( state ) - DECODE: if( (~I & IRQ) | NMI_edge ) - PC_inc = 0; - else - PC_inc = 1; - - ABS0, - ABSX0, - FETCH, - BRA0, - BRA2, - BRK3, - JMPI1, - JMP1, - RTI4, - RTS3: PC_inc = 1; - - BRA1: PC_inc = CO ^~ backwards; - - default: PC_inc = 0; - endcase - -/* - * Set new PC - */ -always @(posedge clk) - if( RDY ) - PC <= PC_temp + PC_inc; - -/* - * Address Generator - */ - -parameter - ZEROPAGE = 8'h00, - STACKPAGE = 8'h01; - -always @* - case( state ) - ABSX1, - INDX3, - INDY2, - JMP1, - JMPI1, - RTI4, - ABS1: AB = { DIMUX, ADD }; - - BRA2, - INDY3, - ABSX2: AB = { ADD, ABL }; - - BRA1: AB = { ABH, ADD }; - - JSR0, - PUSH1, - RTS0, - RTI0, - BRK0: AB = { STACKPAGE, regfile }; - - BRK1, - JSR1, - PULL1, - RTS1, - RTS2, - RTI1, - RTI2, - RTI3, - BRK2: AB = { STACKPAGE, ADD }; - - INDY1, - INDX1, - ZPX1, - INDX2: AB = { ZEROPAGE, ADD }; - - ZP0, - INDY0: AB = { ZEROPAGE, DIMUX }; - - REG, - READ, - WRITE: AB = { ABH, ABL }; - - default: AB = PC; - endcase - -/* - * ABH/ABL pair is used for registering previous address bus state. - * This can be used to keep the current address, freeing up the original - * source of the address, such as the ALU or DI. - */ -always @(posedge clk) - if( state != PUSH0 && state != PUSH1 && RDY && - state != PULL0 && state != PULL1 && state != PULL2 ) - begin - ABL <= AB[7:0]; - ABH <= AB[15:8]; - end - -/* - * Data Out MUX - */ -always @* - case( state ) - WRITE: DO = ADD; - - JSR0, - BRK0: DO = PCH; - - JSR1, - BRK1: DO = PCL; - - PUSH1: DO = php ? P : ADD; - - BRK2: DO = (IRQ | NMI_edge) ? (P & 8'b1110_1111) : P; - - default: DO = regfile; - endcase - -/* - * Write Enable Generator - */ - -always @* - case( state ) - BRK0, // writing to stack or memory - BRK1, - BRK2, - JSR0, - JSR1, - PUSH1, - WRITE: WE = 1; - - INDX3, // only if doing a STA, STX or STY - INDY3, - ABSX2, - ABS1, - ZPX1, - ZP0: WE = store; - - default: WE = 0; - endcase - -/* - * register file, contains A, X, Y and S (stack pointer) registers. At each - * cycle only 1 of those registers needs to be accessed, so they combined - * in a small memory, saving resources. - */ - -reg write_register; // set when register file is written - -always @* - case( state ) - DECODE: write_register = load_reg & ~plp; - - PULL1, - RTS2, - RTI3, - BRK3, - JSR0, - JSR2 : write_register = 1; - - default: write_register = 0; - endcase - -/* - * BCD adjust logic - */ - -always @(posedge clk) - adj_bcd <= adc_sbc & (D | sed); // '1' when doing a BCD instruction - -reg [3:0] ADJL; -reg [3:0] ADJH; - -// adjustment term to be added to ADD[3:0] based on the following -// adj_bcd: '1' if doing ADC/SBC with D=1 -// adc_bcd: '1' if doing ADC with D=1 -// HC : half carry bit from ALU -always @* begin - casex( {adj_bcd, adc_bcd, HC} ) - 3'b0xx: ADJL = 4'd0; // no BCD instruction - 3'b100: ADJL = 4'd10; // SBC, and digital borrow - 3'b101: ADJL = 4'd0; // SBC, but no borrow - 3'b110: ADJL = 4'd0; // ADC, but no carry - 3'b111: ADJL = 4'd6; // ADC, and decimal/digital carry - endcase -end - -// adjustment term to be added to ADD[7:4] based on the following -// adj_bcd: '1' if doing ADC/SBC with D=1 -// adc_bcd: '1' if doing ADC with D=1 -// CO : carry out bit from ALU -always @* begin - casex( {adj_bcd, adc_bcd, CO} ) - 3'b0xx: ADJH = 4'd0; // no BCD instruction - 3'b100: ADJH = 4'd10; // SBC, and digital borrow - 3'b101: ADJH = 4'd0; // SBC, but no borrow - 3'b110: ADJH = 4'd0; // ADC, but no carry - 3'b111: ADJH = 4'd6; // ADC, and decimal/digital carry - endcase -end - -/* - * write to a register. Usually this is the (BCD corrected) output of the - * ALU, but in case of the JSR0 we use the S register to temporarily store - * the PCL. This is possible, because the S register itself is stored in - * the ALU during those cycles. - */ -always @(posedge clk) - if( write_register & RDY ) - AXYS[regsel] <= (state == JSR0) ? DIMUX : { ADD[7:4] + ADJH, ADD[3:0] + ADJL }; - -/* - * register select logic. This determines which of the A, X, Y or - * S registers will be accessed. - */ - -always @* - case( state ) - INDY1, - INDX0, - ZPX0, - ABSX0 : regsel = index_y ? SEL_Y : SEL_X; - - - DECODE : regsel = dst_reg; - - BRK0, - BRK3, - JSR0, - JSR2, - PULL0, - PULL1, - PUSH1, - RTI0, - RTI3, - RTS0, - RTS2 : regsel = SEL_S; - - default: regsel = src_reg; - endcase - -/* - * ALU - */ - -ALU ALU( .clk(clk), - .op(alu_op), - .right(alu_shift_right), - .AI(AI), - .BI(BI), - .CI(CI), - .BCD(adc_bcd & (state == FETCH)), - .CO(CO), - .OUT(ADD), - .V(AV), - .Z(AZ), - .N(AN), - .HC(HC), - .RDY(RDY) ); - -/* - * Select current ALU operation - */ - -always @* - case( state ) - READ: alu_op = op; - - BRA1: alu_op = backwards ? OP_SUB : OP_ADD; - - FETCH, - REG : alu_op = op; - - DECODE, - ABS1: alu_op = 1'bx; - - PUSH1, - BRK0, - BRK1, - BRK2, - JSR0, - JSR1: alu_op = OP_SUB; - - default: alu_op = OP_ADD; - endcase - -/* - * Determine shift right signal to ALU - */ - -always @* - if( state == FETCH || state == REG || state == READ ) - alu_shift_right = shift_right; - else - alu_shift_right = 0; - -/* - * Sign extend branch offset. - */ - -always @(posedge clk) - if( RDY ) - backwards <= DIMUX[7]; - -/* - * ALU A Input MUX - */ - -always @* - case( state ) - JSR1, - RTS1, - RTI1, - RTI2, - BRK1, - BRK2, - INDX1: AI = ADD; - - REG, - ZPX0, - INDX0, - ABSX0, - RTI0, - RTS0, - JSR0, - JSR2, - BRK0, - PULL0, - INDY1, - PUSH0, - PUSH1: AI = regfile; - - BRA0, - READ: AI = DIMUX; - - BRA1: AI = ABH; // don't use PCH in case we're - - FETCH: AI = load_only ? 0 : regfile; - - DECODE, - ABS1: AI = 8'hxx; // don't care - - default: AI = 0; - endcase - - -/* - * ALU B Input mux - */ - -always @* - case( state ) - BRA1, - RTS1, - RTI0, - RTI1, - RTI2, - INDX1, - READ, - REG, - JSR0, - JSR1, - JSR2, - BRK0, - BRK1, - BRK2, - PUSH0, - PUSH1, - PULL0, - RTS0: BI = 8'h00; - - BRA0: BI = PCL; - - DECODE, - ABS1: BI = 8'hxx; - - default: BI = DIMUX; - endcase - -/* - * ALU CI (carry in) mux - */ - -always @* - case( state ) - INDY2, - BRA1, - ABSX1: CI = CO; - - DECODE, - ABS1: CI = 1'bx; - - READ, - REG: CI = rotate ? C : - shift ? 0 : inc; - - FETCH: CI = rotate ? C : - compare ? 1 : - (shift | load_only) ? 0 : C; - - PULL0, - RTI0, - RTI1, - RTI2, - RTS0, - RTS1, - INDY0, - INDX1: CI = 1; - - default: CI = 0; - endcase - -/* - * Processor Status Register update - * - */ - -/* - * Update C flag when doing ADC/SBC, shift/rotate, compare - */ -always @(posedge clk ) - if( shift && state == WRITE ) - C <= CO; - else if( state == RTI2 ) - C <= DIMUX[0]; - else if( ~write_back && state == DECODE ) begin - if( adc_sbc | shift | compare ) - C <= CO; - else if( plp ) - C <= ADD[0]; - else begin - if( sec ) C <= 1; - if( clc ) C <= 0; - end - end - -/* - * Update Z, N flags when writing A, X, Y, Memory, or when doing compare - */ - -always @(posedge clk) - if( state == WRITE ) - Z <= AZ; - else if( state == RTI2 ) - Z <= DIMUX[1]; - else if( state == DECODE ) begin - if( plp ) - Z <= ADD[1]; - else if( (load_reg & (regsel != SEL_S)) | compare | bit_ins ) - Z <= AZ; - end - -always @(posedge clk) - if( state == WRITE ) - N <= AN; - else if( state == RTI2 ) - N <= DIMUX[7]; - else if( state == DECODE ) begin - if( plp ) - N <= ADD[7]; - else if( (load_reg & (regsel != SEL_S)) | compare ) - N <= AN; - end else if( state == FETCH && bit_ins ) - N <= DIMUX[7]; - -/* - * Update I flag - */ - -always @(posedge clk) - if( state == BRK3 ) - I <= 1; - else if( state == RTI2 ) - I <= DIMUX[2]; - else if( state == REG ) begin - if( sei ) I <= 1; - if( cli ) I <= 0; - end else if( state == DECODE ) - if( plp ) I <= ADD[2]; - -/* - * Update D flag - */ -always @(posedge clk ) - if( state == RTI2 ) - D <= DIMUX[3]; - else if( state == DECODE ) begin - if( sed ) D <= 1; - if( cld ) D <= 0; - if( plp ) D <= ADD[3]; - end - -/* - * Update V flag - */ -always @(posedge clk ) - if( state == RTI2 ) - V <= DIMUX[6]; - else if( state == DECODE ) begin - if( adc_sbc ) V <= AV; - if( clv ) V <= 0; - if( plp ) V <= ADD[6]; - end else if( state == FETCH && bit_ins ) - V <= DIMUX[6]; - -/* - * Instruction decoder - */ - -/* - * IR register/mux. Hold previous DI value in IRHOLD in PULL0 and PUSH0 - * states. In these states, the IR has been prefetched, and there is no - * time to read the IR again before the next decode. - */ - -reg RDY1 = 1; - -always @(posedge clk ) - RDY1 <= RDY; - -always @(posedge clk ) - if( ~RDY && RDY1 ) - DIHOLD <= DI; - -always @(posedge clk ) - if( reset ) - IRHOLD_valid <= 0; - else if( RDY ) begin - if( state == PULL0 || state == PUSH0 ) begin - IRHOLD <= DIMUX; - IRHOLD_valid <= 1; - end else if( state == DECODE ) - IRHOLD_valid <= 0; - end - -assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 : - IRHOLD_valid ? IRHOLD : DIMUX; - -assign DIMUX = ~RDY1 ? DIHOLD : DI; - -/* - * Microcode state machine - */ -always @(posedge clk or posedge reset) - if( reset ) - state <= BRK0; - else if( RDY ) case( state ) - DECODE : - casex ( IR ) - 8'b0000_0000: state <= BRK0; - 8'b0010_0000: state <= JSR0; - 8'b0010_1100: state <= ABS0; // BIT abs - 8'b0100_0000: state <= RTI0; // - 8'b0100_1100: state <= JMP0; - 8'b0110_0000: state <= RTS0; - 8'b0110_1100: state <= JMPI0; - 8'b0x00_1000: state <= PUSH0; - 8'b0x10_1000: state <= PULL0; - 8'b0xx1_1000: state <= REG; // CLC, SEC, CLI, SEI - 8'b1xx0_00x0: state <= FETCH; // IMM - 8'b1xx0_1100: state <= ABS0; // X/Y abs - 8'b1xxx_1000: state <= REG; // DEY, TYA, ... - 8'bxxx0_0001: state <= INDX0; - 8'bxxx0_01xx: state <= ZP0; - 8'bxxx0_1001: state <= FETCH; // IMM - 8'bxxx0_1101: state <= ABS0; // even E column - 8'bxxx0_1110: state <= ABS0; // even E column - 8'bxxx1_0000: state <= BRA0; // odd 0 column - 8'bxxx1_0001: state <= INDY0; // odd 1 column - 8'bxxx1_01xx: state <= ZPX0; // odd 4,5,6,7 columns - 8'bxxx1_1001: state <= ABSX0; // odd 9 column - 8'bxxx1_11xx: state <= ABSX0; // odd C, D, E, F columns - 8'bxxxx_1010: state <= REG; // A, TXA, ... NOP - endcase - - ZP0 : state <= write_back ? READ : FETCH; - - ZPX0 : state <= ZPX1; - ZPX1 : state <= write_back ? READ : FETCH; - - ABS0 : state <= ABS1; - ABS1 : state <= write_back ? READ : FETCH; - - ABSX0 : state <= ABSX1; - ABSX1 : state <= (CO | store | write_back) ? ABSX2 : FETCH; - ABSX2 : state <= write_back ? READ : FETCH; - - INDX0 : state <= INDX1; - INDX1 : state <= INDX2; - INDX2 : state <= INDX3; - INDX3 : state <= FETCH; - - INDY0 : state <= INDY1; - INDY1 : state <= INDY2; - INDY2 : state <= (CO | store) ? INDY3 : FETCH; - INDY3 : state <= FETCH; - - READ : state <= WRITE; - WRITE : state <= FETCH; - FETCH : state <= DECODE; - - REG : state <= DECODE; - - PUSH0 : state <= PUSH1; - PUSH1 : state <= DECODE; - - PULL0 : state <= PULL1; - PULL1 : state <= PULL2; - PULL2 : state <= DECODE; - - JSR0 : state <= JSR1; - JSR1 : state <= JSR2; - JSR2 : state <= JSR3; - JSR3 : state <= FETCH; - - RTI0 : state <= RTI1; - RTI1 : state <= RTI2; - RTI2 : state <= RTI3; - RTI3 : state <= RTI4; - RTI4 : state <= DECODE; - - RTS0 : state <= RTS1; - RTS1 : state <= RTS2; - RTS2 : state <= RTS3; - RTS3 : state <= FETCH; - - BRA0 : state <= cond_true ? BRA1 : DECODE; - BRA1 : state <= (CO ^ backwards) ? BRA2 : DECODE; - BRA2 : state <= DECODE; - - JMP0 : state <= JMP1; - JMP1 : state <= DECODE; - - JMPI0 : state <= JMPI1; - JMPI1 : state <= JMP0; - - BRK0 : state <= BRK1; - BRK1 : state <= BRK2; - BRK2 : state <= BRK3; - BRK3 : state <= JMP0; - - endcase - -/* - * Additional control signals - */ - -always @(posedge clk) - if( reset ) - res <= 1; - else if( state == DECODE ) - res <= 0; - -always @(posedge clk) - if( state == DECODE && RDY ) - casex( IR ) - 8'b0xx01010, // ASLA, ROLA, LSRA, RORA - 8'b0xxxxx01, // ORA, AND, EOR, ADC - 8'b100x10x0, // DEY, TYA, TXA, TXS - 8'b1010xxx0, // LDA/LDX/LDY - 8'b10111010, // TSX - 8'b1011x1x0, // LDX/LDY - 8'b11001010, // DEX - 8'b1x1xxx01, // LDA, SBC - 8'bxxx01000: // DEY, TAY, INY, INX - load_reg <= 1; - - default: load_reg <= 0; - endcase - -always @(posedge clk) - if( state == DECODE && RDY ) - casex( IR ) - 8'b1110_1000, // INX - 8'b1100_1010, // DEX - 8'b101x_xx10: // LDX, TAX, TSX - dst_reg <= SEL_X; - - 8'b0x00_1000, // PHP, PHA - 8'b1001_1010: // TXS - dst_reg <= SEL_S; - - 8'b1x00_1000, // DEY, DEX - 8'b101x_x100, // LDY - 8'b1010_x000: // LDY #imm, TAY - dst_reg <= SEL_Y; - - default: dst_reg <= SEL_A; - endcase - -always @(posedge clk) - if( state == DECODE && RDY ) - casex( IR ) - 8'b1011_1010: // TSX - src_reg <= SEL_S; - - 8'b100x_x110, // STX - 8'b100x_1x10, // TXA, TXS - 8'b1110_xx00, // INX, CPX - 8'b1100_1010: // DEX - src_reg <= SEL_X; - - 8'b100x_x100, // STY - 8'b1001_1000, // TYA - 8'b1100_xx00, // CPY - 8'b1x00_1000: // DEY, INY - src_reg <= SEL_Y; - - default: src_reg <= SEL_A; - endcase - -always @(posedge clk) - if( state == DECODE && RDY ) - casex( IR ) - 8'bxxx1_0001, // INDY - 8'b10x1_x110, // LDX/STX zpg/abs, Y - 8'bxxxx_1001: // abs, Y - index_y <= 1; - - default: index_y <= 0; - endcase - - -always @(posedge clk) - if( state == DECODE && RDY ) - casex( IR ) - 8'b100x_x1x0, // STX, STY - 8'b100x_xx01: // STA - store <= 1; - - default: store <= 0; - - endcase - -always @(posedge clk ) - if( state == DECODE && RDY ) - casex( IR ) - 8'b0xxx_x110, // ASL, ROL, LSR, ROR - 8'b11xx_x110: // DEC/INC - write_back <= 1; - - default: write_back <= 0; - endcase - - -always @(posedge clk ) - if( state == DECODE && RDY ) - casex( IR ) - 8'b101x_xxxx: // LDA, LDX, LDY - load_only <= 1; - default: load_only <= 0; - endcase - -always @(posedge clk ) - if( state == DECODE && RDY ) - casex( IR ) - 8'b111x_x110, // INC - 8'b11x0_1000: // INX, INY - inc <= 1; - - default: inc <= 0; - endcase - -always @(posedge clk ) - if( (state == DECODE || state == BRK0) && RDY ) - casex( IR ) - 8'bx11x_xx01: // SBC, ADC - adc_sbc <= 1; - - default: adc_sbc <= 0; - endcase - -always @(posedge clk ) - if( (state == DECODE || state == BRK0) && RDY ) - casex( IR ) - 8'b011x_xx01: // ADC - adc_bcd <= (D | sed); - - default: adc_bcd <= 0; - endcase - -always @(posedge clk ) - if( state == DECODE && RDY ) - casex( IR ) - 8'b0xxx_x110, // ASL, ROL, LSR, ROR (abs, absx, zpg, zpgx) - 8'b0xxx_1010: // ASL, ROL, LSR, ROR (acc) - shift <= 1; - - default: shift <= 0; - endcase - -always @(posedge clk ) - if( state == DECODE && RDY ) - casex( IR ) - 8'b11x0_0x00, // CPX, CPY (imm/zp) - 8'b11x0_1100, // CPX, CPY (abs) - 8'b110x_xx01: // CMP - compare <= 1; - - default: compare <= 0; - endcase - -always @(posedge clk ) - if( state == DECODE && RDY ) - casex( IR ) - 8'b01xx_xx10: // ROR, LSR - shift_right <= 1; - - default: shift_right <= 0; - endcase - -always @(posedge clk ) - if( state == DECODE && RDY ) - casex( IR ) - 8'b0x1x_1010, // ROL A, ROR A - 8'b0x1x_x110: // ROR, ROL - rotate <= 1; - - default: rotate <= 0; - endcase - -always @(posedge clk ) - if( state == DECODE && RDY ) - casex( IR ) - 8'b00xx_xx10: // ROL, ASL - op <= OP_ROL; - - 8'b0010_x100: // BIT zp/abs - op <= OP_AND; - - 8'b01xx_xx10: // ROR, LSR - op <= OP_A; - - 8'b1000_1000, // DEY - 8'b1100_1010, // DEX - 8'b110x_x110, // DEC - 8'b11xx_xx01, // CMP, SBC - 8'b11x0_0x00, // CPX, CPY (imm, zpg) - 8'b11x0_1100: op <= OP_SUB; - - 8'b010x_xx01, // EOR - 8'b00xx_xx01: // ORA, AND - op <= { 2'b11, IR[6:5] }; - - default: op <= OP_ADD; - endcase - -always @(posedge clk ) - if( state == DECODE && RDY ) - casex( IR ) - 8'b0010_x100: // BIT zp/abs - bit_ins <= 1; - - default: bit_ins <= 0; - endcase - -/* - * special instructions - */ -always @(posedge clk ) - if( state == DECODE && RDY ) begin - php <= (IR == 8'h08); - clc <= (IR == 8'h18); - plp <= (IR == 8'h28); - sec <= (IR == 8'h38); - cli <= (IR == 8'h58); - sei <= (IR == 8'h78); - clv <= (IR == 8'hb8); - cld <= (IR == 8'hd8); - sed <= (IR == 8'hf8); - brk <= (IR == 8'h00); - end - -always @(posedge clk) - if( RDY ) - cond_code <= IR[7:5]; - -always @* - case( cond_code ) - 3'b000: cond_true = ~N; - 3'b001: cond_true = N; - 3'b010: cond_true = ~V; - 3'b011: cond_true = V; - 3'b100: cond_true = ~C; - 3'b101: cond_true = C; - 3'b110: cond_true = ~Z; - 3'b111: cond_true = Z; - endcase - - -reg NMI_1 = 0; // delayed NMI signal - -always @(posedge clk) - NMI_1 <= NMI; - -always @(posedge clk ) - if( NMI_edge && state == BRK3 ) - NMI_edge <= 0; - else if( NMI & ~NMI_1 ) - NMI_edge <= 1; - -endmodule \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/cpu_wrapper.sv b/Console_MiST/Atari - 7800_TeST/rtl/cpu_wrapper.sv deleted file mode 100644 index 4e1f5e7c..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/cpu_wrapper.sv +++ /dev/null @@ -1,65 +0,0 @@ -`timescale 1ns / 1ps - - -module cpu_wrapper( clk, sysclk, reset, AB, DB_IN, DB_OUT, RD, IRQ, NMI, RDY, halt_b, pc_temp, core_latch_data); - -input clk; // CPU clock -input sysclk; // MARIA Clock -input reset; // reset signal -output [15:0] AB; // address bus -input [7:0] DB_IN; // data in, -output [7:0] DB_OUT; // data_out, -output RD; // read enable -input IRQ; // interrupt request -input NMI; // non-maskable interrupt request -input RDY; // Ready signal. Pauses CPU when RDY=0 -input halt_b; -input core_latch_data; - -output [15:0] pc_temp; - -logic res; -logic rdy_in; -logic WE_OUT; -logic WE, holding; -logic [7:0] DB_hold, DB_into_cpu; - -cpu core(.clk(clk), .reset(reset),.AB(AB),.DI(DB_hold),.DO(DB_OUT),.WE(WE_OUT),.IRQ(IRQ),.NMI(NMI),.RDY(rdy_in), .pc_temp(pc_temp), .res(res)); - -assign RD = ~(WE & ~res & ~reset); -assign WE = WE_OUT & rdy_in; //& ~core_latch_data; -//assign rdy_in = RDY & halt_b; -assign DB_hold = (holding) ? DB_hold : DB_IN; - -//assign DB_into_cpu = (core_latch_data) ? DB_IN : DB_hold; -//assign DB_into_cpu = DB_hold; - - -/*always_ff @(posedge sysclk) begin - if (core_latch_data & rdy_in) begin - DB_hold <= DB_IN; - end -end*/ - -/*always_ff @(posedge clk) begin - if (rdy_in) - DB_hold <= DB_IN; -end*/ - -/*always_ff @(posedge clk, posedge reset) - if (reset) - holding <= 1'b0; - else - holding <= ~rdy_in;*/ - -assign holding = ~rdy_in; - -always_ff @(negedge clk, posedge reset) - if (reset) - rdy_in <= 1'b1; - else if (halt_b & RDY) - rdy_in <= 1'b1; - else - rdy_in <= 1'b0; - -endmodule: cpu_wrapper \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/defender_rom.v b/Console_MiST/Atari - 7800_TeST/rtl/defender_rom.v deleted file mode 100644 index 0ed1d560..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/defender_rom.v +++ /dev/null @@ -1,164 +0,0 @@ -// megafunction wizard: %ROM: 1-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: defender_rom.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.4 Build 182 03/12/2014 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2014 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module defender_rom ( - address, - clock, - q); - - input [11:0] address; - input clock; - output [7:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clock; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] q = sub_wire0[7:0]; - - altsyncram altsyncram_component ( - .address_a (address), - .clock0 (clock), - .q_a (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .address_b (1'b1), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_a ({8{1'b1}}), - .data_b (1'b1), - .eccstatus (), - .q_b (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_a (1'b0), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_a = "NONE", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", -`ifdef NO_PLI - altsyncram_component.init_file = "../rtl/rom/Defender.rif" -`else - altsyncram_component.init_file = "../rtl/rom/Defender.hex" -`endif -, - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 4096, - altsyncram_component.operation_mode = "ROM", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_reg_a = "CLOCK0", - altsyncram_component.widthad_a = 12, - altsyncram_component.width_a = 8, - altsyncram_component.width_byteena_a = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -// Retrieval info: PRIVATE: AclrByte NUMERIC "0" -// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: Clken NUMERIC "0" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "../rtl/rom/Defender.hex" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: RegAddr NUMERIC "1" -// Retrieval info: PRIVATE: RegOutput NUMERIC "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: SingleClock NUMERIC "1" -// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" -// Retrieval info: PRIVATE: WidthData NUMERIC "8" -// Retrieval info: PRIVATE: rden NUMERIC "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: INIT_FILE STRING "../rtl/rom/Defender.hex" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL defender_rom.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL defender_rom.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL defender_rom.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL defender_rom.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL defender_rom_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL defender_rom_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Console_MiST/Atari - 7800_TeST/rtl/dma_ctrl.sv b/Console_MiST/Atari - 7800_TeST/rtl/dma_ctrl.sv deleted file mode 100644 index 18b4ff8d..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/dma_ctrl.sv +++ /dev/null @@ -1,403 +0,0 @@ -`timescale 1ns / 1ps - -module dma_ctrl( - output logic [15:0] AddrB, - output logic drive_AB, - input logic [7:0] DataB, - // from memory map - input logic [15:0] ZP, - - output logic palette_w, input_w, pixels_w, - output logic wm_w, - - input logic zp_dma_start, dp_dma_start, dp_dma_kill, - output logic zp_dma_done, dp_dma_done, dp_dma_done_dli, - - input logic character_width, - input logic [7:0] char_base, - - input logic sysclk, reset, last_line -); - logic [15:0] DP; - logic [15:0] DP_saved; - logic [15:0] PP; - logic [15:0] ZP_saved, ZP_saved_next; - logic [15:0] CHAR_PTR; - logic [1:0] char_ptr_cycles; - logic char_bytes_fetched; - logic [4:0] WIDTH; - logic [3:0] OFFSET; - - logic INDIRECT_MODE; - - // control regs - logic DLIen, DLIen_prev, A12en, A11en; - - // states - enum logic [1:0] {waiting = 2'b00, zp_dma = 2'b01, dp_dma = 2'b10} state; - enum logic [2:0] {drive_zp_addr = 3'b000, w_offset = 3'b001, w_DPH = 3'b010 ,w_DPL = 3'b100} zp_state; - enum logic [3:0] {drive_dp_addr = 4'h00, - w_PPL = 4'h01, - w_PALETTE_WIDTH = 4'h02, - w_PPH = 4'h03, - w_PALETTE_WIDTH_2 = 4'h04, - w_INPUT = 4'h05, - drive_pp_addr = 4'h06, - w_PIXELS = 4'h07, - w_PIXELS_slow = 4'h08, - drive_char_addr = 4'h09, - w_CHAR_PTR = 4'ha, - w_CHAR_PIXELS = 4'hb, - drive_next_zp_addr = 4'hc, - w_next_offset = 4'hd, - w_next_DPL = 4'he, - w_next_DPH = 4'hf} dp_state; - - logic five_byte_mode, null_width, null_data, zero_offset; - - logic PP_in_cart; - assign PP_in_cart = |(PP_plus_offset[15:14]); - - logic [7:0] CB_plus_offset; - assign CB_plus_offset = char_base + {4'b0, OFFSET}; - - logic CB_in_cart; - assign CB_in_cart = |(CB_plus_offset[7:6]); - - assign null_width = (DataB[4:0] == 5'b0); - assign null_data = (DataB == 8'b0); - assign zero_offset = (OFFSET == 4'b0); - - assign drive_AB = (state != waiting); - - assign ZP_saved_next = ZP_saved + 1; - - logic [15:0] PP_plus_offset; - assign PP_plus_offset = PP + {4'b0, OFFSET, 8'b0}; - - always_comb begin - AddrB = 'h1234; - wm_w = 0; - palette_w = 0; - input_w = 0; - pixels_w = 0; - case (state) - zp_dma: begin - AddrB = ZP_saved; - end - dp_dma: begin - AddrB = 16'hx; - case (dp_state) - drive_dp_addr: begin - AddrB = DP_saved; - end - - w_PPL: begin - AddrB = DP_saved; - end - - w_PALETTE_WIDTH: begin - AddrB = DP_saved; - if (~null_data) begin - wm_w = null_width; - palette_w = ~null_width; - end - end - - w_PPH: begin - AddrB = DP_saved; - end - - w_PALETTE_WIDTH_2: begin - AddrB = DP_saved; - palette_w = 1; - end - - w_INPUT: begin - AddrB = DP_saved; - input_w = 1; - end - - drive_pp_addr: begin - AddrB = PP_plus_offset; - end - - w_PIXELS: begin - AddrB = PP + 1; - pixels_w = 1; - end - - w_PIXELS_slow: begin - if (char_ptr_cycles == 2'b11) begin - pixels_w = 1; - AddrB = PP + 1; - end else begin - AddrB = PP; - end - end - - drive_char_addr: begin - AddrB = PP; - end - - w_CHAR_PTR: begin - AddrB = {CB_plus_offset, DataB}; - end - - w_CHAR_PIXELS: begin - if (char_ptr_cycles == 2'b11) begin - pixels_w = 1; - if (~char_bytes_fetched & character_width) begin - AddrB = CHAR_PTR + 1; - end else begin - AddrB = PP; - end - end else begin - AddrB = CHAR_PTR; - end - end - - drive_next_zp_addr: begin - AddrB = ZP_saved; - end - w_next_offset: begin - AddrB = ZP_saved; - end - w_next_DPL: begin - AddrB = ZP_saved; - end - w_next_DPH: begin - AddrB = ZP_saved; - end - endcase - end - endcase - end - - always_ff @(posedge sysclk, posedge reset) begin - if (reset) begin - state <= waiting; - zp_state <= drive_zp_addr; - dp_state <= drive_dp_addr; - zp_dma_done <= 0; - dp_dma_done <= 0; - dp_dma_done_dli <= 0; - five_byte_mode <= 0; - INDIRECT_MODE <= 0; - end else begin - case (state) - waiting: begin - if (zp_dma_start) begin - state <= zp_dma; - ZP_saved <= ZP; - end else if (dp_dma_start) begin - state <= dp_dma; - DP_saved <= DP; - end - zp_dma_done <= 0; - dp_dma_done <= 0; - dp_dma_done_dli <= 0; - end - //////////////////////////////////////////////////////////// - zp_dma: begin - case (zp_state) - drive_zp_addr: begin // Read zp - zp_state <= w_offset; - // AddrB = ZP_saved; - ZP_saved <= ZP_saved_next; - end - w_offset: begin //write cbits and offset - zp_state <= w_DPH; - {DLIen,A12en,A11en} <= DataB[7:5]; - OFFSET <= DataB[3:0]; - // AddrB = ZP_saved_next; - ZP_saved <= ZP_saved_next; - end - w_DPH: begin //Write DPH - zp_state <= w_DPL; - DP[15:8] <= DataB; - // AddrB = ZP_saved; - ZP_saved <= ZP_saved_next; - end - w_DPL: begin //Write DPL - zp_state <= drive_zp_addr; - state <= waiting; - DP[7:0] <= DataB; - DP_saved <= {DP[15:8], DataB}; - zp_dma_done <= 1'b1; - dp_dma_done_dli <= DLIen; - end - endcase // case (zp_state) - end // case: zp_dma - - ////////////////////////////////////////////////////////////// - dp_dma: begin - if (dp_dma_kill) begin - dp_state <= drive_dp_addr; - state <= waiting; - dp_dma_done <= 1'b1; - end else case (dp_state) - drive_dp_addr: begin //read from dp - dp_state <= w_PPL; - // AddrB = DP_saved; - DP_saved <= DP_saved+1; - five_byte_mode <= 0; - INDIRECT_MODE <= 0; - end - w_PPL: begin //Write PPL - dp_state <= w_PALETTE_WIDTH; - PP[7:0] <= DataB; - // AddrB = DP_saved; - DP_saved <= DP_saved+1; - end - w_PALETTE_WIDTH: - // Write palette/width or determine 5b - // mode or find end of DP list - if (null_data) begin //Found end of DP list - if (last_line) begin // Found end of frame - dp_state <= drive_dp_addr; - state <= waiting; - dp_dma_done <= 1; - dp_dma_done_dli <= 1'b0; - end else if (zero_offset) begin // Found end of zone, but not end of frame - dp_state <= drive_next_zp_addr; - state <= dp_dma; - end else begin // Not at end of zone or frame. Get ready for next line in zone. - state <= waiting; - dp_state <= drive_dp_addr; - OFFSET <= OFFSET - 1; - dp_dma_done <= 1; - end - end else begin - // Write palette and width or determine its 5b mode - dp_state <= w_PPH; - five_byte_mode <= null_width; - INDIRECT_MODE <= null_width & DataB[5]; - // wm_w <= null_width; - // ind_w <= null_width; - // palette_w <= ~null_width; - WIDTH <= DataB[4:0]; - // AddrB <= DP; - DP_saved <= DP_saved+1; - end - w_PPH: begin //Write PPH - dp_state <= (five_byte_mode) ? w_PALETTE_WIDTH_2 : w_INPUT; - PP[15:8] <= DataB; - // AddrB <= DP; - DP_saved <= DP_saved+1; - end - w_PALETTE_WIDTH_2: begin //Write palette and width for realzies - dp_state <= w_INPUT; - // palette_w <= 1; - WIDTH <= DataB[4:0]; - // AddrB <= DP; - DP_saved <= DP_saved+1; - end - w_INPUT: begin //write INPUT - if (INDIRECT_MODE) begin - dp_state <= drive_char_addr; - end else begin - if ((A12en & PP_plus_offset[12]) | (A11en & PP_plus_offset[11])) - dp_state <= drive_dp_addr; - else - dp_state <= drive_pp_addr; - end - // palette_w <= 0; - // AddrB <= DP; - // input_w <= 1; - end - drive_pp_addr: begin //read from pp - if (PP_in_cart) begin - dp_state <= w_PIXELS_slow; - char_ptr_cycles <= 2'b00; - end else begin - dp_state <= w_PIXELS; - end - WIDTH <= WIDTH+1; - PP <= PP_plus_offset; - end - w_PIXELS: begin //Write Pixel data - PP <= PP + 1; - WIDTH <= WIDTH + 1; - dp_state <= (WIDTH == 5'b0) ? drive_dp_addr : w_PIXELS; - end - w_PIXELS_slow: begin - // Similar to w_CHAR_PIXELS in that we wait 4 cycles, - // but similar to w_PIXELS otherwise - if (char_ptr_cycles == 2'b11) begin - // Data is ready on the data bus - WIDTH <= WIDTH + 1; - PP <= PP + 1; - dp_state <= (WIDTH == 5'b0) ? drive_dp_addr: w_PIXELS_slow; - char_ptr_cycles <= 2'b00; - end else begin - char_ptr_cycles <= char_ptr_cycles + 1; - end - end - drive_char_addr: begin // read character pointer from pp - dp_state <= w_CHAR_PTR; - WIDTH <= WIDTH + 1; - PP <= PP + 1; - end - w_CHAR_PTR: begin - dp_state <= w_CHAR_PIXELS; - CHAR_PTR <= {CB_plus_offset, DataB}; - char_bytes_fetched <= 2'b0; - char_ptr_cycles <= (CB_in_cart) ? 2'b00 : 2'b11; - end - - w_CHAR_PIXELS: begin - if (char_ptr_cycles == 2'b11) begin - if (~char_bytes_fetched & character_width) begin - dp_state <= w_CHAR_PIXELS; - char_bytes_fetched <= 1'b1; - CHAR_PTR <= CHAR_PTR + 1; - end else begin - if (WIDTH == 5'b0) begin - dp_state <= drive_dp_addr; - end else begin - dp_state <= w_CHAR_PTR; - WIDTH <= WIDTH + 1; - PP <= PP + 1; - end - end - end else begin - char_ptr_cycles <= char_ptr_cycles + 1; - end - end - - ///////////////////////////////////////////////// - //Loading next zp when OFFSET has been decremented to 0 - drive_next_zp_addr: begin //Read zp - dp_state <= w_next_offset; - // AddrB <= ZP_saved; - ZP_saved <= ZP_saved_next; - end - w_next_offset: begin //write cbits and offset - dp_state <= w_next_DPH; - DLIen_prev <= DLIen; - {DLIen,A12en,A11en} <= DataB[7:5]; - OFFSET <= DataB[3:0]; - // AddrB <= ZP_saved; - ZP_saved <= ZP_saved_next; - end - w_next_DPH: begin //Write DPH - dp_state <= w_next_DPL; - DP[15:8] <= DataB; - // AddrB <= ZP_saved; - ZP_saved <= ZP_saved_next; - end - w_next_DPL: begin //Write DPH - dp_state <= drive_dp_addr; - state <= waiting; - DP[7:0] <= DataB; - DP_saved <= {DP[15:8], DataB}; - dp_dma_done <= 1; - dp_dma_done_dli <= DLIen; - end - endcase // case (dp_state) - end // case: dp_dma - endcase - end - end // always_ff @ -endmodule // dma_ctrl \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/hq2x.sv b/Console_MiST/Atari - 7800_TeST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Console_MiST/Atari - 7800_TeST/rtl/line_ram.sv b/Console_MiST/Atari - 7800_TeST/rtl/line_ram.sv deleted file mode 100644 index 9b9b6f88..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/line_ram.sv +++ /dev/null @@ -1,261 +0,0 @@ -`timescale 1ns / 1ps - -// Graphics Mode Definitions -`define GM_160A 3'b000 -`define GM_160B 3'b100 -`define GM_320A 3'b011 -`define GM_320B 3'b110 -`define GM_320C 3'b111 -`define GM_320D 3'b010 - -module line_ram( - input logic SYSCLK, RESET, - output logic [7:0] PLAYBACK, - // Databus inputs - input logic [7:0] INPUT_ADDR, - input logic [2:0] PALETTE, - input logic [7:0] PIXELS, - input logic WM, - // Write enable for databus inputs - input logic PALETTE_W, INPUT_W, PIXELS_W, WM_W, - // Memory mapped registers - input logic [24:0][7:0] COLOR_MAP, - input logic [1:0] READ_MODE, - input logic KANGAROO_MODE, BORDER_CONTROL, - input logic COLOR_KILL, - input logic LRAM_SWAP, - // VGA Control signal - input logic [8:0] LRAM_OUT_COL -); - - logic [159:0][4:0] lram_in, lram_out; - logic rm_in, rm_out; - - logic [7:0] input_addr; - logic [2:0] palette; - logic wm; - - logic [2:0] display_mode; - assign display_mode = {wm, READ_MODE}; - - logic [2:0] playback_palette; - logic [1:0] playback_color; - logic [4:0] playback_cell; - logic [8:0] playback_ix; - logic [7:0] lram_ix; - - assign playback_ix = (LRAM_OUT_COL < 9'd320) ? LRAM_OUT_COL : 9'd0; - - always_comb begin - if (playback_color == 2'b0) begin - PLAYBACK = COLOR_MAP[0]; - end else begin - PLAYBACK = COLOR_MAP[3 * playback_palette + playback_color]; - end - end - - logic [4:0] cell1, cell2, cell3, cell4; - logic [4:0] pcell1, pcell2, pcell3, pcell4; - - assign cell1 = lram_in[input_addr]; - assign cell2 = lram_in[input_addr+1]; - assign cell3 = lram_in[input_addr+2]; - assign cell4 = lram_in[input_addr+3]; - - assign pcell1 = lram_in[input_addr-4]; - assign pcell2 = lram_in[input_addr-3]; - assign pcell3 = lram_in[input_addr-2]; - assign pcell4 = lram_in[input_addr-1]; - - // Assign playback_color and playback_palette based on - // lram_in and playback_ix and display_mode - always_comb begin - lram_ix = playback_ix[8:1]; // 2 pixels per lram cell - playback_cell = lram_out[lram_ix]; - playback_palette = playback_cell[4:2]; // Default to 160A/B - playback_color = playback_cell[1:0]; - casex (rm_out) - 2'b0x: begin - // 160A is read as four double-pixels per byte: - // - // - // - // - // 160B is read as two double-pixels per byte: - // - // - // In both cases, the lineram cells are stored in - // exactly the order specified above. They can be - // read directly. - playback_palette = playback_cell[4:2]; - playback_color = playback_cell[1:0]; - end - 2'b10: begin - // 320B is read as four pixels per byte: - // - // - // - // - // 320B is stored as two cells per byte (wm=1): - // [P2 D3 D2 D7 D6] - // [P2 D1 D0 D5 D4] - // - // 320D is read as eight pixels per byte: - // - // - // - // - // - // - // - // - // 320D is stored as four cells per byte (wm=0): - // [P2 P1 P0 D7 D6] - // [P2 P1 P0 D5 D4] - // [P2 P1 P0 D3 D2] - // [P2 P1 P0 D1 D0] - // - // In both cases, the palette is always - // For a given pair of pixels, the color selectors - // are, from left to right, and - // Example: Either D7,D3:D6,D2 (320B) or D7,P1:D6,P0 (320D) - playback_palette = {playback_cell[4], 2'b0}; - if (playback_ix[0]) begin - // Right pixel - playback_color = {playback_cell[0], playback_cell[2]}; - end else begin - // Left pixel - playback_color = {playback_cell[1], playback_cell[3]}; - end - end - 2'b11: begin - // 320A is read as eight pixels per byte: - // - // - // - // - // - // - // - // - // 320A is stored as four cells per byte (wm=0): - // [P2 P1 P0 D7 D6] - // [P2 P1 P0 D5 D4] - // [P2 P1 P0 D3 D2] - // [P2 P1 P0 D1 D0] - // - // 320C is read as four pixels per byte: - // - // - // - // - // 320C is stored as two cells per byte (wm=1): - // [P2 D3 D2 D7 D6] - // [P2 D1 D0 D5 D4] - // - // In both cases, the palette is always - // For a given pair of pixels, the color selectors - // are, from left to right, and - playback_palette = playback_cell[4:2]; - if (playback_ix[0]) begin - // Right pixel - playback_color = {playback_cell[0], 1'b0}; - end else begin - // Left pixel - playback_color = {playback_cell[1], 1'b0}; - end - end - endcase - end - - always_ff @(posedge SYSCLK, posedge RESET) begin - if (RESET) begin - input_addr <= 8'b0; - palette <= 3'b0; - wm <= 1'b0; - lram_in <= 800'd0; - lram_out <= 800'd0; - end else begin - input_addr <= INPUT_W ? INPUT_ADDR : input_addr; - palette <= PALETTE_W ? PALETTE : palette; - wm <= WM_W ? WM : wm; - if (LRAM_SWAP) begin - lram_in <= 800'd0; // All background color - lram_out <= lram_in; - rm_out <= rm_in; - end - if (PIXELS_W) begin - // Load PIXELS byte into lram_in - rm_in <= READ_MODE; - case (wm) - 1'b0: begin - // "When wm = 0, each byte specifies four pixel cells - // of the lineram" - // This encompasses: - // 160A: - // [P2 P1 P0 D7 D6] - // [P2 P1 P0 D5 D4] - // [P2 P1 P0 D3 D2] - // [P2 P1 P0 D1 D0] - // 320A: - // [P2 P1 P0 D7 0] - // [P2 P1 P0 D6 0] - // [P2 P1 P0 D5 0] - // [P2 P1 P0 D4 0] - // [P2 P1 P0 D3 0] - // [P2 P1 P0 D2 0] - // [P2 P1 P0 D1 0] - // [P2 P1 P0 D0 0] - // 320D: - // [P2 0 0 D7 P1] - // [P2 0 0 D6 P0] - // [P2 0 0 D5 P1] - // [P2 0 0 D4 P0] - // [P2 0 0 D3 P1] - // [P2 0 0 D2 P0] - // [P2 0 0 D1 P1] - // [P2 0 0 D0 P0] - // These can all be written into the cells using - // the same format and read out differently. - input_addr <= input_addr + 4; - if (|PIXELS[7:6]) - lram_in[input_addr+0] <= {palette, PIXELS[7:6]}; - if (|PIXELS[5:4]) - lram_in[input_addr+1] <= {palette, PIXELS[5:4]}; - if (|PIXELS[3:2]) - lram_in[input_addr+2] <= {palette, PIXELS[3:2]}; - if (|PIXELS[1:0]) - lram_in[input_addr+3] <= {palette, PIXELS[1:0]}; - end - 1'b1: begin - // "When wm = 1, each byte specifies two cells within the lineram." - // This encompasses: - // 160B: - // [P2 D3 D2 D7 D6] - // [P2 D1 D0 D5 D4] - // 320B: - // [P2 0 0 D7 D3] - // [P2 0 0 D6 D2] - // [P2 0 0 D5 D1] - // [P2 0 0 D4 D0] - // 320C: - // [P2 D3 D2 D7 0] - // [P2 D3 D2 D6 0] - // [P2 D1 D0 D5 0] - // [P2 D1 D0 D4 0] - // Again, these can be written into the cells in - // the same format and read out differently. Note: - // transparency may not be correct in 320B mode here - // since the color bits are different than 160B and 320C. - input_addr <= input_addr + 2; - if (|PIXELS[7:6]) - lram_in[input_addr+0] <= {palette[2], PIXELS[3:2], PIXELS[7:6]}; - if (|PIXELS[5:4]) - lram_in[input_addr+1] <= {palette[2], PIXELS[1:0], PIXELS[5:4]}; - end - endcase - end - end - end - -endmodule diff --git a/Console_MiST/Atari - 7800_TeST/rtl/maria.sv b/Console_MiST/Atari - 7800_TeST/rtl/maria.sv deleted file mode 100644 index 2f30002d..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/maria.sv +++ /dev/null @@ -1,178 +0,0 @@ -`timescale 1ns / 1ps -`include "atari7800.vh" - - -module maria( - // Busses ("tristate") - input logic [15:0] AB_in, - output logic [15:0] AB_out, - output logic drive_AB, - - input logic [7:0] read_DB_in, - input logic [7:0] write_DB_in, - output logic [7:0] DB_out, - // inout wire [15:0] AB, - // inout wire [ 7:0] DB, - //inout wire [7:0] DB, - //inout wire [15:0] AB, - - // Clocking - input logic reset, - input logic sysclk, pclk_2, - output logic tia_clk, pclk_0, sel_slow_clock, - - // Memory Map Select lines - output `chipselect CS, - input logic bios_en, - input logic tia_en, - //output logic ram0_b, ram1_b, p6532_b, tia_b, - //output logic riot_ram_b, - - // Maria configuration - input logic RW, enable, - - // VGA Interface - input logic [9:0] vga_row, vga_col, - output logic [7:0] UV_out, - - // Outputs to 6502 - output logic int_b, halt_b, ready, core_latch_data -); - - // Bus interface - // Defined as ports. - //logic drive_AB; - //logic [15:0] AB_in, AB_out; - //logic drive_DB; - //logic [7:0] DB_in, DB_out; - //assign DB = drive_DB ? DB_out : 'bz; - //assign AB = drive_AB ? AB_out : 'bz; - //assign DB_in = DB; - //assign AB_in = AB; - - // For testing DMA. - //assign DB_in = DB; - //assign AB = AB_out; - //assign AB_in = AB_out; - - //// Memory Mapped Registers - // Control register format: - // {CK, DM1, DM0, CW, BC, KM, RM1, RM0} - // CK: Color Kill - // {DM1, DM0}: DMA Control. 0: Test A. 1: Test B. - // 2: Normal DMA. 3: No DMA. - // CW: Character Width (For indirect mode). 0=>2bytes. 1=>1byte. - // BC: Border Control: 0=>Background Color. 1=>Black Border. - // KM: Kangaroo Mode: 0=>Transparency, 1=>No transparency - // {RM1, RM0}: Read mode. - logic [7:0] ctrl; - logic [24:0][7:0] color_map; - logic [7:0] char_base; - logic [15:0] ZP; - - //// Signals from memory_map to timing_ctrl - logic deassert_ready, zp_written; - - // Write enables for internal Display List registers - logic palette_w, input_w, pixels_w, wm_w; - - //// Control signals between timing_ctrl and dma_ctrl - logic zp_dma_start, dp_dma_start; - logic zp_dma_done, dp_dma_done; - // When dp_dma_done is asserted, use this signal to specify - // whether timing_ctrl needs to raise a display list interrupt - logic dp_dma_done_dli; - // If a DMA is taking too long (too many objects,) kill it - logic dp_dma_kill; - // Next-line ZP DMA not needed at end of DP DMA - logic last_line; - - //// Control signals between timing_ctrl and line_ram - logic lram_swap; - - logic VBLANK; - - line_ram line_ram_inst( - .SYSCLK(sysclk), .RESET(reset), - .PLAYBACK(UV_out), - // Databus inputs - .INPUT_ADDR(read_DB_in), .PALETTE(read_DB_in[7:5]), .PIXELS(read_DB_in), - .WM(read_DB_in[7]), - // Write enable for databus inputs - .PALETTE_W(palette_w), .INPUT_W(input_w), .PIXELS_W(pixels_w), - .WM_W(wm_w), - // Memory mapped registers - .COLOR_MAP(color_map), - .READ_MODE(ctrl[1:0]), - .KANGAROO_MODE(ctrl[2]), - .BORDER_CONTROL(ctrl[3]), - .COLOR_KILL(ctrl[7]), - // Control signals from timing_ctrl - .LRAM_SWAP(lram_swap), - .LRAM_OUT_COL(vga_col[9:1]) - ); - - timing_ctrl timing_ctrl_inst( - // Enabled only if men is asserted and display mode is 10 - .enable(enable & ctrl[6] & ~ctrl[5]), - // Clocking - .sysclk(sysclk), .reset(reset), .pclk_2(pclk_2), - .pclk_0(pclk_0), .tia_clk(tia_clk), - // Signals needed to slow pclk_0 - .sel_slow_clock(sel_slow_clock), - // Outputs to 6502 - .halt_b(halt_b), .int_b(int_b), .ready(ready), .core_latch_data(core_latch_data), - .VBLANK(VBLANK), - // Signals to/from dma_ctrl - .zp_dma_start(zp_dma_start), .dp_dma_start(dp_dma_start), - .zp_dma_done(zp_dma_done), .dp_dma_done(dp_dma_done), - .dp_dma_done_dli(dp_dma_done_dli), - .dp_dma_kill(dp_dma_kill), .last_line(last_line), - // Signals to/from line_ram - .lram_swap(lram_swap), - // Signals to/from VGA - .vga_row(vga_row), .vga_col(vga_col), - // Signals from memory map - .deassert_ready(deassert_ready), - .zp_written(zp_written) - ); - - memory_map memory_map_inst( - .maria_en(enable), - .tia_en(tia_en), - .AB(AB_in), - .DB_in(write_DB_in), .DB_out(DB_out), - //.drive_DB(drive_DB), - .halt_b(halt_b), .we_b(RW), - //.tia_b(tia_b), .p6532_b(p6532_b), - //.ram0_b(ram0_b), .ram1_b(ram1_b), - //.riot_ram_b(riot_ram_b), - .cs(CS), .bios_en(bios_en), - .drive_AB(drive_AB), - .ctrl(ctrl), - .color_map(color_map), - .status_read({VBLANK, 7'b0}), - .char_base(char_base), - .ZP(ZP), - .sel_slow_clock(sel_slow_clock), - .deassert_ready(deassert_ready), - .zp_written(zp_written), - .sysclock(sysclk), .reset_b(~reset), - .pclk_0(pclk_0), .pclk_2(pclk_2) - ); - - dma_ctrl dma_ctrl_inst ( - .AddrB(AB_out), .drive_AB(drive_AB), - .DataB(read_DB_in), .ZP(ZP), - .palette_w(palette_w), .input_w(input_w), .pixels_w(pixels_w), - .wm_w(wm_w), - .zp_dma_start(zp_dma_start), .dp_dma_start(dp_dma_start), - .dp_dma_kill(dp_dma_kill), - .zp_dma_done(zp_dma_done), .dp_dma_done(dp_dma_done), - .dp_dma_done_dli(dp_dma_done_dli), - .sysclk(sysclk), .reset(reset), - .last_line(last_line), - .character_width(ctrl[4]), .char_base(char_base) - ); - -endmodule \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/memory_map.sv b/Console_MiST/Atari - 7800_TeST/rtl/memory_map.sv deleted file mode 100644 index 2c993781..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/memory_map.sv +++ /dev/null @@ -1,232 +0,0 @@ -`timescale 1ns / 1ps - -`include "atari7800.vh" - -module memory_map ( - input logic maria_en, - input logic tia_en, - input logic [15:0] AB, - input logic [7:0] DB_in, - output logic [7:0] DB_out, - input logic halt_b, we_b, - - output `chipselect cs, - input logic bios_en, - input logic drive_AB, - - output logic [7:0] ctrl, - output logic [24:0][7:0] color_map, - input logic [7:0] status_read, - output logic [7:0] char_base, - output logic [15:0] ZP, - - // whether to slow pclk_0 for slow memory accesses - output logic sel_slow_clock, - - // when wait_sync is written to, ready is deasserted - output logic deassert_ready, zp_written, - - input logic sysclock, reset_b, pclk_0, pclk_2 -); - - logic [3:0] signals_out; - - // Internal Memory Mapped Registers - logic [7:0] ZPH, ZPL; - logic [7:0] wait_sync; - - logic [7:0] read_addr_found, write_addr_found; - - (* KEEP = "true" *) - logic [7:0] ctrl_kept; - - assign sel_slow_clock = (drive_AB) ? 1'b0 : ((tia_en) ? 1'b1 : ((cs == `CS_TIA) || (cs == `CS_RIOT_IO) || (cs == `CS_RIOT_RAM))); - - assign ZP = {ZPH, ZPL}; - logic [1:0] zp_byte_written; - - assign zp_written = &zp_byte_written; - - always_comb begin - // Generate Chip Select (cs) Signal - cs = `CS_CART; - - if (~tia_en) casex (AB) - // RIOT RAM: "Do Not Use" in 7800 mode. - 16'b0000_010x_1xxx_xxxx: cs = `CS_RIOT_RAM; - 16'b0000_0010_1xxx_xxxx: cs = `CS_RIOT_IO; - - // 1800-1FFF: 2K RAM. - 16'b0001_1xxx_xxxx_xxxx: cs = `CS_RAM1; - - // 0040-00FF: Zero Page (Local variable space) - // 0140-01FF: Stack - 16'b0000_000x_01xx_xxxx, - 16'b0000_000x_1xxx_xxxx, - - // 2000-27FF: 2K RAM. Zero Page and Stack mirrored from here. - 16'b001x_xxxx_xxxx_xxxx: cs = `CS_RAM0; - - // TIA Registers: - // 0000-001F, 0100-001F, 0200-021F, 0300-031F - // All mirrors are ranges of the same registers - 16'b0000_00xx_000x_xxxx: cs = `CS_TIA; - - // MARIA Registers: - // 0020-003F, 0120-003F, 0220-023F, 0320-033F - // All ranges are mirrors of the same registers - 16'b0000_00xx_001x_xxxx: cs = `CS_MARIA; - - endcase else casex (AB) - 16'bxxx0_xx0x_1xxx_xxxx: cs = `CS_RIOT_RAM; - 16'bxxx0_xx1x_1xxx_xxxx: cs = `CS_RIOT_IO; - 16'bxxx0_xxxx_0xxx_xxxx: cs = `CS_TIA; - endcase - - if (bios_en & AB[15]) - cs = `CS_BIOS; - - // If MARIA is selected, handle memory mapped registers - if (cs == `CS_MARIA) begin - if (we_b) begin - read_addr_found = AB[7:0]; - write_addr_found = 8'h0; - end - else begin - write_addr_found = AB[7:0]; - read_addr_found = 8'h0; - end - end else begin - read_addr_found = 8'h0; - write_addr_found = 8'h0; - end - - /* - //Find write addresses on bus to latch data on next tick - casex ({AB, we_b}) - {16'b0000_00xx_001x_xxxx,1'b0}: wr_addr_found = AB[7:0]; - default: wr_addr_found = 8'b0; - endcase - - casex ({AB, we_b}) - {16'b0000_00xx_001x_xxxx,1'b1}: read_addr_found = AB[7:0]; - default: read_addr_found = 8'b0; - endcase - */ - - - end // always_comb - - always_ff @(posedge pclk_0, negedge reset_b) begin - if (~reset_b) begin - ctrl <= {1'b0, 2'b10, 1'b0, 1'b0, 1'b0, 2'b00}; // 8'b0 - ctrl_kept <= 8'b0; - //color_map <= 200'b0; - //////// TESTING COLOR MAP ///////// - // Background - color_map[0] <= 8'h0c; - // Palette 0 - color_map[3:1] <= {8'h32, 8'h55, 8'h55}; - // Palette 1 - color_map[6:4] <= {8'h83, 8'h55, 8'h55}; - // Palette 2 - color_map[9:7] <= {8'h1c, 8'h55, 8'h55}; - // Palette 3 - color_map[12:10] <= {8'h25, 8'h55, 8'h55}; - // Palette 4 - color_map[15:13] <= {8'hda, 8'h55, 8'h55}; - - color_map[24:16] <= 'b0; - - wait_sync <= 8'b0; - char_base <= 8'b0; - {ZPH,ZPL} <= {8'h18, 8'h20}; - zp_byte_written <= 2'b0; - end - - else begin - ctrl_kept <= ctrl; - deassert_ready <= 1'b0; - //Handle writes to mem mapped regs - case(write_addr_found) - 8'h20: color_map[0] <= DB_in; - 8'h21: color_map[1] <= DB_in; - 8'h22: color_map[2] <= DB_in; - 8'h23: color_map[3] <= DB_in; - 8'h24: begin - wait_sync <= DB_in; - deassert_ready <= 1'b1; - end - 8'h25: color_map[4] <= DB_in; - 8'h26: color_map[5] <= DB_in; - 8'h27: color_map[6] <= DB_in; - //8'h28: status_read <= DB_in; Read only - 8'h29: color_map[7] <= DB_in; - 8'h2a: color_map[8] <= DB_in; - 8'h2b: color_map[9] <= DB_in; - 8'h2c: begin - ZPH <= DB_in; - zp_byte_written[1] <= 1'b1; - end - 8'h2d: color_map[10] <= DB_in; - 8'h2e: color_map[11] <= DB_in; - 8'h2f: color_map[12] <= DB_in; - 8'h30: begin - ZPL <= DB_in; - zp_byte_written[0] <= 1'b1; - end - 8'h31: color_map[13] <= DB_in; - 8'h32: color_map[14] <= DB_in; - 8'h33: color_map[15] <= DB_in; - 8'h34: char_base <= DB_in; - 8'h35: color_map[16] <= DB_in; - 8'h36: color_map[17] <= DB_in; - 8'h37: color_map[18] <= DB_in; - //8'h38: NOT USED - 8'h39: color_map[19] <= DB_in; - 8'h3a: color_map[20] <= DB_in; - 8'h3b: color_map[21] <= DB_in; - 8'h3c: ctrl <= DB_in; - 8'h3d: color_map[22] <= DB_in; - 8'h3e: color_map[23] <= DB_in; - 8'h3f: color_map[24] <= DB_in; - default: ; - endcase // case (wr_addr_found) - - case(read_addr_found) - 8'h20: DB_out <= color_map[0]; - 8'h21: DB_out <= color_map[1]; - 8'h22: DB_out <= color_map[2]; - 8'h23: DB_out <= color_map[3]; - 8'h25: DB_out <= color_map[4]; - 8'h26: DB_out <= color_map[5]; - 8'h27: DB_out <= color_map[6]; - 8'h28: DB_out <= status_read; - 8'h29: DB_out <= color_map[7]; - 8'h2a: DB_out <= color_map[8]; - 8'h2b: DB_out <= color_map[9]; - 8'h2c: DB_out <= ZPH; - 8'h2d: DB_out <= color_map[10]; - 8'h2e: DB_out <= color_map[11]; - 8'h2f: DB_out <= color_map[12]; - 8'h30: DB_out <= ZPL; - 8'h31: DB_out <= color_map[13]; - 8'h32: DB_out <= color_map[14]; - 8'h33: DB_out <= color_map[15]; - 8'h34: DB_out <= char_base; - 8'h35: DB_out <= color_map[16]; - 8'h36: DB_out <= color_map[17]; - 8'h37: DB_out <= color_map[18]; - //8'h38: NOT USED - 8'h39: DB_out <= color_map[19]; - 8'h3a: DB_out <= color_map[20]; - 8'h3b: DB_out <= color_map[21]; - 8'h3c: DB_out <= ctrl; - 8'h3d: DB_out <= color_map[22]; - 8'h3e: DB_out <= color_map[23]; - 8'h3f: DB_out <= color_map[24]; - default: DB_out <= 8'hbe; - endcase // case (wr_addr_found) - end // else: !if(~reset_b) - end // always_ff @ -endmodule \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/mist_io.sv b/Console_MiST/Atari - 7800_TeST/rtl/mist_io.sv deleted file mode 100644 index ab9ef8ad..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/mist_io.sv +++ /dev/null @@ -1,532 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoubler_disable, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input sd_rd, - input sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ARM -> FPGA download - input ioctl_force_erase, - output reg ioctl_download = 0, // signal indicating an active download - output reg ioctl_erasing = 0, // signal indicating an active erase - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] b_data; -reg [6:0] sbuf; -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [7:0] byte_cnt; // counts bytes -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; -assign ypbpr = but_sw[5]; - -wire [7:0] spi_dout = { sbuf, SPI_DI}; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -// drive MISO only when transmitting core id -always@(negedge SPI_SCK) begin - if(!CONF_DATA0) begin - // first byte returned is always core type, further bytes are - // command dependent - if(byte_cnt == 0) begin - spi_do <= core_type[~bit_cnt]; - - end else begin - case(cmd) - // reading config string - 8'h14: begin - // returning a byte from string - if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; - else spi_do <= 0; - end - - // reading sd card status - 8'h16: begin - if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; - else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; - else spi_do <= 0; - end - - // reading sd card write data - 8'h18: - spi_do <= b_data[~bit_cnt]; - - default: - spi_do <= 0; - endcase - end - end -end - -reg b_wr2,b_wr3; -always @(negedge clk_sys) begin - b_wr3 <= b_wr2; - sd_buff_wr <= b_wr3; -end - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - - if(CONF_DATA0) begin - b_wr2 <= 0; - bit_cnt <= 0; - byte_cnt <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - end else begin - b_wr2 <= 0; - - sbuf <= spi_dout[6:0]; - bit_cnt <= bit_cnt + 1'd1; - if(bit_cnt == 5) begin - if (byte_cnt == 0) sd_buff_addr <= 0; - if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; - if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; - end - - // finished reading command byte - if(bit_cnt == 7) begin - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - if(byte_cnt == 0) begin - cmd <= spi_dout; - - if(spi_dout == 8'h19) begin - sd_ack_conf <= 1; - sd_buff_addr <= 0; - end - if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin - sd_ack <= 1; - sd_buff_addr <= 0; - end - if(spi_dout == 8'h18) b_data <= sd_buff_din; - - mount_strobe <= 0; - - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_dout; - 8'h02: joystick_0 <= spi_dout; - 8'h03: joystick_1 <= spi_dout; - - // store incoming ps2 mouse bytes - 8'h04: begin - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_dout; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_dout; - b_wr2 <= 1; - end - - 8'h18: b_data <= sd_buff_din; - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; - else if(byte_cnt == 2) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; - end else if(byte_cnt == 3) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; - end - end - - // notify image selection - 8'h1c: mount_strobe <= 1; - - // send image info - 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; - - // status, 32bit version - 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; - default: ; - endcase - end - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - rclk <= 0; - - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // increase target address after write - if(rclk) addr <= addr + 1'd1; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - case(ioctl_index) - 0: addr <= 'h080000; // BOOT ROM - 'h01: addr <= 'h000100; // ROM file - 'h41: addr <= 'h000100; // COM file - 'h81: addr <= 'h000000; // C00 file - 'hC1: addr <= 'h010000; // EDD file - default: addr <= 'h100000; // FDD file - endcase - ioctl_download <= 1; - end else begin - addr_w <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - rclk <= 1; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -reg [24:0] erase_mask; -wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask; - -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - reg old_force = 0; - reg [5:0] erase_clk_div; - reg [24:0] end_addr; - reg erase_trigger = 0; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD & ~rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - - if(ioctl_download) begin - old_force <= 0; - ioctl_erasing <= 0; - erase_trigger <= (ioctl_index == 1); - end else begin - - old_force <= ioctl_force_erase; - - // start erasing - if(erase_trigger) begin - erase_trigger <= 0; - erase_mask <= 'hFFFF; - end_addr <= 'h0100; - erase_clk_div <= 1; - ioctl_erasing <= 1; - end else if((ioctl_force_erase & ~old_force)) begin - erase_trigger <= 0; - ioctl_addr <= 'h1FFFFFF; - erase_mask <= 'h1FFFFFF; - end_addr <= 'h0050000; - erase_clk_div <= 1; - ioctl_erasing <= 1; - end else if(ioctl_erasing) begin - erase_clk_div <= erase_clk_div + 1'd1; - if(!erase_clk_div) begin - if(next_erase == end_addr) ioctl_erasing <= 0; - else begin - ioctl_addr <= next_erase; - ioctl_dout <= 0; - ioctl_wr <= 1; - end - end - end - end -end - -endmodule \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/ram2k.v b/Console_MiST/Atari - 7800_TeST/rtl/ram2k.v deleted file mode 100644 index a57abe06..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/ram2k.v +++ /dev/null @@ -1,177 +0,0 @@ -// megafunction wizard: %RAM: 1-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: ram2k.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.4 Build 182 03/12/2014 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2014 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module ram2k ( - address, - clken, - clock, - data, - wren, - q); - - input [10:0] address; - input clken; - input clock; - input [7:0] data; - input wren; - output [7:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clken; - tri1 clock; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] q = sub_wire0[7:0]; - - altsyncram altsyncram_component ( - .address_a (address), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .clocken0 (clken), - .q_a (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .address_b (1'b1), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b (1'b1), - .eccstatus (), - .q_b (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.clock_enable_input_a = "NORMAL", - altsyncram_component.clock_enable_output_a = "NORMAL", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 2048, - altsyncram_component.operation_mode = "SINGLE_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_reg_a = "CLOCK0", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 11, - altsyncram_component.width_a = 8, - altsyncram_component.width_byteena_a = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -// Retrieval info: PRIVATE: AclrByte NUMERIC "0" -// Retrieval info: PRIVATE: AclrData NUMERIC "0" -// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" -// Retrieval info: PRIVATE: Clken NUMERIC "1" -// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -// Retrieval info: PRIVATE: RegAddr NUMERIC "1" -// Retrieval info: PRIVATE: RegData NUMERIC "1" -// Retrieval info: PRIVATE: RegOutput NUMERIC "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: SingleClock NUMERIC "1" -// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "11" -// Retrieval info: PRIVATE: WidthData NUMERIC "8" -// Retrieval info: PRIVATE: rden NUMERIC "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" -// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0 -// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL ram2k.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram2k.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram2k.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram2k.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram2k_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL ram2k_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Console_MiST/Atari - 7800_TeST/rtl/riot.vh b/Console_MiST/Atari - 7800_TeST/rtl/riot.vh deleted file mode 100644 index 74090777..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/riot.vh +++ /dev/null @@ -1,26 +0,0 @@ -/* Atari on an FPGA -Masters of Engineering Project -Cornell University, 2007 -Daniel Beer - RIOT.h -Header file that contains useful definitions for the RIOT module. -*/ -`define READ_RAM 7'b01xxxxx -`define WRITE_RAM 7'b00xxxxx -`define READ_DRA 7'b11xx000 -`define WRITE_DRA 7'b10xx000 -`define READ_DDRA 7'b11xx001 -`define WRITE_DDRA 7'b10xx001 -`define READ_DRB 7'b11xx010 -`define WRITE_DRB 7'b10xx010 -`define READ_DDRB 7'b11xx011 -`define WRITE_DDRB 7'b10xx011 -`define WRITE_TIMER 7'b101x1xx -`define READ_TIMER 7'b11xx1x0 -`define READ_INT_FLAG 7'b11xx1x1 -`define WRITE_EDGE_DETECT 7'b100x1x0 -`define NOP 7'b0100000 -`define TM_1 2'b00 -`define TM_8 2'b01 -`define TM_64 2'b10 -`define TM_1024 2'b11 \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/rom/7800ntsc.hex b/Console_MiST/Atari - 7800_TeST/rtl/rom/7800ntsc.hex deleted file mode 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-:100F90000E0E0E0E0E4E7E7E4E4E7E72727E7E7255 -:100FA000027E72727E000000000000007985B5A507 -:100FB000B58579171515775555774141414141411F -:100FC00040494949C94949BE555555D955559900D2 -:100FD000C4A4C6A5C60AA00BB00FF00110F00FF113 -:100FE0001FFAAFE06040407B795910CEC6C6C00002 -:100FF000888FFF1D1A3700000000000000F000F08D -:00000001FF diff --git a/Console_MiST/Atari - 7800_TeST/rtl/rom/Joust.a78 b/Console_MiST/Atari - 7800_TeST/rtl/rom/Joust.a78 deleted file mode 100644 index b8104d6f..00000000 Binary files a/Console_MiST/Atari - 7800_TeST/rtl/rom/Joust.a78 and /dev/null differ diff --git a/Console_MiST/Atari - 7800_TeST/rtl/scandoubler.sv b/Console_MiST/Atari - 7800_TeST/rtl/scandoubler.sv deleted file mode 100644 index 5a3ccd17..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/scandoubler.sv +++ /dev/null @@ -1,195 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Console_MiST/Atari - 7800_TeST/rtl/sigma_delta_dac.sv b/Console_MiST/Atari - 7800_TeST/rtl/sigma_delta_dac.sv deleted file mode 100644 index 29daea6e..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/sigma_delta_dac.sv +++ /dev/null @@ -1,33 +0,0 @@ -// -// PWM DAC -// -// MSBI is the highest bit number. NOT amount of bits! -// -module sigma_delta_dac #(parameter MSBI=0) -( - output reg DACout, //Average Output feeding analog lowpass - input [MSBI:0] DACin, //DAC input (excess 2**MSBI) - input CLK, - input RESET -); - -reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder -reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder -reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder -reg [MSBI+2:0] DeltaB; //B input of Delta Adder - -always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); -always @(*) DeltaAdder = DACin + DeltaB; -always @(*) SigmaAdder = DeltaAdder + SigmaLatch; - -always @(posedge CLK or posedge RESET) begin - if(RESET) begin - SigmaLatch <= 1'b1 << (MSBI+1); - DACout <= 1; - end else begin - SigmaLatch <= SigmaAdder; - DACout <= ~SigmaLatch[MSBI+2]; - end -end - -endmodule diff --git a/Console_MiST/Atari - 7800_TeST/rtl/tia.vh b/Console_MiST/Atari - 7800_TeST/rtl/tia.vh deleted file mode 100644 index 04c8510a..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/tia.vh +++ /dev/null @@ -1,81 +0,0 @@ -/* Atari on an FPGA -Masters of Engineering Project -Cornell University, 2007 -Daniel Beer - TIA.h -Header file that contains useful definitions for the TIA module. -*/ -`define CXM0P 7'h70 -`define CXM1P 7'h71 -`define CXP0FB 7'h72 -`define CXP1FB 7'h73 -`define CXM0FB 7'h74 -`define CXM1FB 7'h75 -`define CXBLPF 7'h76 -`define CXPPMM 7'h77 -`define INPT0 7'h78 -`define INPT1 7'h79 -`define INPT2 7'h7A -`define INPT3 7'h7B -`define INPT4 7'h7C -`define INPT5 7'h7D -`define VSYNC 7'h00 -`define VBLANK 7'h01 -`define WSYNC 7'h02 -`define RSYNC 7'h03 -`define NUSIZ0 7'h04 -`define NUSIZ1 7'h05 -`define COLUP0 7'h06 -`define COLUP1 7'h07 -`define COLUPF 7'h08 -`define COLUBK 7'h09 -`define CTRLPF 7'h0A -`define REFP0 7'h0B -`define REFP1 7'h0C -`define PF0 7'h0D -`define PF1 7'h0E -`define PF2 7'h0F -`define RESP0 7'h10 -`define RESP1 7'h11 -`define RESM0 7'h12 -`define RESM1 7'h13 -`define RESBL 7'h14 -`define AUDC0 7'h15 -`define AUDC1 7'h16 -`define AUDF0 7'h17 -`define AUDF1 7'h18 -`define AUDV0 7'h19 -`define AUDV1 7'h1A -`define GRP0 7'h1B -`define GRP1 7'h1C -`define ENAM0 7'h1D -`define ENAM1 7'h1E -`define ENABL 7'h1F -`define HMP0 7'h20 -`define HMP1 7'h21 -`define HMM0 7'h22 -`define HMM1 7'h23 -`define HMBL 7'h24 -`define VDELP0 7'h25 -`define VDELP1 7'h26 -`define VDELBL 7'h27 -`define RESMP0 7'h28 -`define RESMP1 7'h29 -`define HMOVE 7'h2A -`define HMCLR 7'h2B -`define CXCLR 7'h2C - -`define CXM0P_7800 7'h40 -`define CXM1P_7800 7'h41 -`define CXP0FB_7800 7'h42 -`define CXP1FB_7800 7'h43 -`define CXM0FB_7800 7'h44 -`define CXM1FB_7800 7'h45 -`define CXBLPF_7800 7'h46 -`define CXPPMM_7800 7'h47 -`define INPT0_7800 7'h48 -`define INPT1_7800 7'h49 -`define INPT2_7800 7'h4A -`define INPT3_7800 7'h4B -`define INPT4_7800 7'h4C -`define INPT5_7800 7'h4D \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/timing_ctrl.sv b/Console_MiST/Atari - 7800_TeST/rtl/timing_ctrl.sv deleted file mode 100644 index b40e1aef..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/timing_ctrl.sv +++ /dev/null @@ -1,361 +0,0 @@ -`timescale 1ns / 1ps - -// Number of sysclk cycles needed for the halt signal to take on the CPU -`define DMA_STARTUP_CYCLES 9 - -// Number of sysclk cycles that the cpu gets at the start of a line -`define START_OF_LINE_CYCLES 24 - -// At which column we terminate DP DMA -`define DP_DMA_KILL_COL 435 - -// Column to start the ZP DMA, given that about 29 cycles are needed -// and there are 452 columns total. Plus some slack cycles. -// 9 for startup, 7 for access, 13 for shutdown -`define ZP_READY_COL 420 - -// VGA Row to start the ZP DMA. Rows 0-1 are the first visible line, -// rows 523-524 are the virst invisible line, rows 521-522 are buffering -// for the first invisible line, so ZP needs to be fetched by row 521. -`define ZP_READY_ROW 520 - -`define VGA_VISIBLE_COLS 640 - -`define NTSC_SCANLINE_COUNT 242 - -`define COOLDOWN_CYCLES 1 - -//`define OVERCLOCK - - - -module timing_ctrl ( - input logic enable, - - // Clocking - input logic sysclk, reset, pclk_2, - output logic pclk_0, tia_clk, - input logic sel_slow_clock, - - // Outputs to 6502 - output logic halt_b, int_b, ready, core_latch_data, - output logic VBLANK, - - // Signals to/from dma_ctrl - output logic zp_dma_start, dp_dma_start, - input logic zp_dma_done, dp_dma_done, - input logic dp_dma_done_dli, - output logic dp_dma_kill, - output logic last_line, - - // Signals to/from line_ram - output logic lram_swap, - - // VGA Status - input logic [9:0] vga_row, vga_col, - - // Signals from memory map - input logic deassert_ready, zp_written -); - - // Output buffers - logic [5:0] int_b_sr; - assign int_b = &int_b_sr; - - // Current NTSC row and col - logic [8:0] row, col; - - logic [9:0] vga_row_prev, vga_row_prev_prev; - - // Each ntsc line is two vga lines. Asserted => we are on second one - logic second_vga_line; - - // vga_row has changed in the last cycle - logic vga_line_delta; - - // Clock division - `ifndef OVERCLOCK - logic fast_ctr; - `endif - - logic [1:0] slow_ctr; - logic fast_clk, slow_clk; - - logic ready_for_lswap, ready_for_lswap_prev; - - // Ready to move to ZP_DMA_STARTUP - logic zp_ready; - - // interrupt on next cycle - logic dli_next, raise_dli; - - logic [4:0] startup_ctr; - logic cooldown_count; - - enum logic [31:0] { - VWAIT = 'h0, // Waiting for VSYNC to complete before starting ZP DMA - HWAIT = 'h1, // Waiting for HSYNC to complete before starting DP DMA - ZP_DMA_STARTUP = 'h2, // Waiting for HALT to reach CPU before starting ZP DMA - ZP_DMA = 'h3, // Waiting for DMA CTRL to finish ZP DMA - START_OF_LINE = 'h4, // Waiting for first 7 CPU cycles of line before DP DMA - DP_DMA_STARTUP = 'h5, // Waiting for HALT to reach CPU before starting DP DMA - DP_DMA = 'h6, // Waiting for DMA CTRL to finish DP DMA - DP_DMA_WAITSWAP = 'h7, // Done with DP DMA, but not ready to swap linerams yet - VWAIT_COOLDOWN = 'h8, - HWAIT_COOLDOWN = 'h9 - } state; - - assign vga_line_delta = vga_row_prev_prev != vga_row_prev; - - // In general, we are on the second row if the row number is odd (vga_row[0]) - // However, above 512 (521/522, 523/524) we are on the second row if the row - // number is even. - assign second_vga_line = vga_row[9] ^ vga_row[0]; - - assign dp_dma_kill = ((enable) & - (state == DP_DMA) & - (second_vga_line) & - (col == `DP_DMA_KILL_COL)); - - assign zp_ready = ((enable) & (vga_row == `ZP_READY_ROW) & - (col == `ZP_READY_COL)); - - assign last_line = (row == (`NTSC_SCANLINE_COUNT - 1)); - - assign VBLANK = (row >= 9'd241); - - assign pclk_0 = sel_slow_clock ? slow_clk : fast_clk; - - assign ready_for_lswap = ((enable) & second_vga_line & - (vga_col > `VGA_VISIBLE_COLS)); - assign lram_swap = (ready_for_lswap & - (((state == DP_DMA) & (dp_dma_done | dp_dma_kill)) || - (state == DP_DMA_WAITSWAP))); - - - always @(posedge sysclk, posedge reset) begin - if (reset) begin - state <= VWAIT; - row <= 9'b0; - col <= 9'b0; - vga_row_prev <= 10'd0; - fast_clk <= 1'b0; - cooldown_count <= 1'b0; - slow_clk <= 1'b0; - `ifndef OVERCLOCK - fast_ctr <= 1'b0; - `endif - slow_ctr <= 2'b0; - int_b_sr <= 6'b111111; - raise_dli <= 1'b0; - startup_ctr <= 4'd0; - dli_next <= 1'b0; - halt_b <= 1'b1; - zp_dma_start <= 1'b0; - dp_dma_start <= 1'b0; - core_latch_data <= 1'b0; - ready_for_lswap_prev <= 1'b0; - ready <= 1'b1; - tia_clk <= 1'b0; - end else begin - // Clock generation - tia_clk <= ~tia_clk; - core_latch_data <= 1'b0; - if (sel_slow_clock) begin - `ifndef OVERCLOCK - fast_ctr <= 1'b0; - `endif - - fast_clk <= 1'b1; - if (slow_ctr == 2'd2) begin - slow_ctr <= 2'b0; - slow_clk <= ~slow_clk; - if (slow_clk == 1'b0) - core_latch_data <= 1'b1; - end - else - slow_ctr <= slow_ctr + 2'b01; - end - else begin - slow_ctr <= 2'b00; - slow_clk <= 1'b1; - `ifdef OVERCLOCK - fast_clk <= ~fast_clk; - `else - fast_ctr <= ~fast_ctr; - if (fast_ctr) begin - fast_clk <= ~fast_clk; - if (fast_clk == 1'b0) - core_latch_data <= 1'b1; - end - `endif - end - - // Interrupt generation - int_b_sr <= {int_b_sr[4:0], ~(dli_next & enable)}; - //int_b_reg <= ~(dli_next & enable); - - vga_row_prev <= vga_row; - vga_row_prev_prev <= vga_row_prev; - ready_for_lswap_prev <= ready_for_lswap; - - // Column counting - if (vga_line_delta & ~second_vga_line) // Just changed to first line - col <= 0; - else - col <= col + 1; - - // Row counting - if (vga_line_delta & ~second_vga_line) begin - if (vga_row == 10'd521) - row <= 0; - else - row <= row + 1; - end - - // Ready signal - if (enable & deassert_ready) - ready <= 1'b0; - else if (ready_for_lswap & ~ready_for_lswap_prev) - ready <= 1'b1; - - // Next state logic - case (state) - VWAIT: begin - if (zp_ready & zp_written) begin - halt_b <= 1'b0; - raise_dli <= 1'b0; - dli_next <= 1'b0; - state <= ZP_DMA_STARTUP; - startup_ctr <= 1; - end - end - HWAIT: begin - if (~enable) begin - state <= VWAIT_COOLDOWN; - halt_b <= 1'b0; - raise_dli <= 1'b0; - dli_next <= 1'b0; - cooldown_count <= `COOLDOWN_CYCLES; - end else if (vga_line_delta) begin - state <= START_OF_LINE; - startup_ctr <= 1; - end - end - ZP_DMA_STARTUP: begin - startup_ctr <= startup_ctr + 1; - if (~enable) begin - state <= VWAIT_COOLDOWN; - raise_dli <= 1'b0; - halt_b <= 1'b0; - cooldown_count <= `COOLDOWN_CYCLES; - end else if (startup_ctr == `DMA_STARTUP_CYCLES) begin - zp_dma_start <= 1'b1; - state <= ZP_DMA; - end - end - ZP_DMA: begin - zp_dma_start <= 1'b0; - if (~enable) begin - state <= VWAIT_COOLDOWN; - raise_dli <= 1'b0; - halt_b <= 1'b0; - cooldown_count <= `COOLDOWN_CYCLES; - end else if (zp_dma_done) begin - state <= HWAIT_COOLDOWN; - raise_dli <= dp_dma_done_dli; - raise_dli <= 1'b0; - halt_b <= 1'b0; - cooldown_count <= `COOLDOWN_CYCLES; - end - end - START_OF_LINE: begin - startup_ctr <= startup_ctr + 1; - if (~enable) begin - state <= VWAIT_COOLDOWN; - raise_dli <= 1'b0; - halt_b <= 1'b0; - cooldown_count <= `COOLDOWN_CYCLES; - end else if (startup_ctr == `START_OF_LINE_CYCLES) begin - halt_b <= 1'b0; - state <= DP_DMA_STARTUP; - startup_ctr <= 1; - end - end - DP_DMA_STARTUP: begin - startup_ctr <= startup_ctr + 1; - if (~enable) begin - state <= VWAIT_COOLDOWN; - raise_dli <= 1'b0; - halt_b <= 1'b0; - cooldown_count <= `COOLDOWN_CYCLES; - end else if (startup_ctr == `DMA_STARTUP_CYCLES) begin - dp_dma_start <= 1'b1; - raise_dli <= 1'b0; - state <= DP_DMA; - end - end - DP_DMA: begin - dp_dma_start <= 1'b0; - if (~enable) begin - state <= VWAIT_COOLDOWN; - halt_b <= 1'b0; - cooldown_count <= `COOLDOWN_CYCLES; - end else if (dp_dma_done | dp_dma_kill) begin - halt_b <= 1'b0; - raise_dli <= dp_dma_done_dli; - cooldown_count <= `COOLDOWN_CYCLES; - if (ready_for_lswap) begin - state <= last_line ? VWAIT_COOLDOWN : HWAIT_COOLDOWN; - end else begin - state <= DP_DMA_WAITSWAP; - end - end - end - DP_DMA_WAITSWAP: begin - if (~enable) begin - state <= VWAIT_COOLDOWN; - end else if (cooldown_count == 0) begin - if ((sel_slow_clock && slow_ctr != 2'b10) || - (~sel_slow_clock && fast_clk == 1'b1)) begin - halt_b <= 1'b1; - raise_dli <= 1'b0; - dli_next <= raise_dli; - end - end else begin - cooldown_count <= cooldown_count - 1; - end - if (ready_for_lswap) begin - state <= last_line ? VWAIT_COOLDOWN : HWAIT_COOLDOWN; - end - end - VWAIT_COOLDOWN: begin - if (cooldown_count == 0) begin - if ((sel_slow_clock && slow_ctr != 2'b10) || - (~sel_slow_clock && fast_clk == 1'b1)) begin - halt_b <= 1'b1; - raise_dli <= 1'b0; - dli_next <= raise_dli; - state <= VWAIT; - end - end else begin - cooldown_count <= cooldown_count - 1; - end - end - HWAIT_COOLDOWN: begin - if (cooldown_count == 0) begin - if ((sel_slow_clock && slow_ctr != 2'b10) || - (~sel_slow_clock && fast_clk == 1'b1)) begin - halt_b <= 1'b1; - raise_dli <= 1'b0; - dli_next <= raise_dli; - state <= HWAIT; - end - end else begin - cooldown_count <= cooldown_count - 1; - end - end - endcase - end - end -endmodule \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/uv_to_vga.sv b/Console_MiST/Atari - 7800_TeST/rtl/uv_to_vga.sv deleted file mode 100644 index f890e5aa..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/uv_to_vga.sv +++ /dev/null @@ -1,218 +0,0 @@ -`timescale 1ns / 1ps -/** Line buffer to VGA Interface - * - * input lbuffer is the line buffer. - * For column c, 0 <= c < 640, where 0 is left and 639 is right, - * lbuffer[c][0] is RED, where 4'hF is the most intense red and - * 4'h0 is the least intense red. - * lbuffer[c][1] is GREEN and lbuffer[c][2] is BLUE. - * - * output line_number indicates the current row, where the top - * of the screen is 0 and 479 is the bottom of the screen. Other - * values indicate that no line is currently being drawn. - * - * clk should be hooked up to a 25MHz clock (or 25.175 if available.) - * reset should be hooked up to system reset. - * RED, GREEN, BLUE, HSync, and VSync should be hooked up to the - * appropriate VGA pins. - **/ - -//`define FRAMEBUF - -module uv_to_vga ( - input logic clk, reset, - input logic [7:0] uv_in, - - output logic [9:0] row, col, - output logic [3:0] RED, GREEN, BLUE, - output logic HSync, VSync, - - input logic tia_en, tia_clk, - input logic tia_hblank, - input logic tia_vblank -); - - - - logic col_clear, row_clear; - logic col_enable, row_enable; - - // Chrominance-Luminance palettes (represented as rgb) - logic [255:0][3:0] red_palette, green_palette, blue_palette; - - logic [7:0] rbuf, gbuf, bbuf; - logic [7:0] uv; - - logic visible, tia_visible; - assign visible = (row < 10'd480) & (col < 10'd640); - - `ifdef FRAMEBUF - assign tia_visible = (row >= 10'd48) & (row <10'd432) & (col < 10'd640); - - logic [9:0] tia_row, tia_col; - assign tia_row = row - 10'd48; - assign tia_col = col; - - logic [7:0] fbuf_uv1, fbuf_uv2; - (* keep = "true" *) logic [7:0] fbuf_uv1_kept, fbuf_uv2_kept; - assign fbuf_uv1_kept = fbuf_uv1; - assign fbuf_uv2_kept = fbuf_uv2; - - logic [14:0] buf_w_addr, buf_r_addr; - (* keep = "true" *) logic [14:0] buf_w_addr_kept; - (* keep = "true" *) logic [14:0] buf_r_addr_kept; - assign buf_w_addr = tia_write_row*14'd160+tia_write_col; - assign buf_r_addr = tia_row[8:1]*14'd160+tia_col[9:2]; - assign buf_w_addr_kept = buf_w_addr; - assign buf_r_addr_kept = buf_r_addr; - logic write_buf1; - - Frame_Buf frame_buffer1( - .clka(tia_clk), // input wire clka - .ena(~tia_vblank & ~tia_hblank & write_buf1), // input wire ena - .wea(write_buf1), // input wire [0 : 0] wea - .addra(buf_w_addr), // input wire [14 : 0] addra - .dina(uv_in), // input wire [7 : 0] dina - .clkb(clk), // input wire clkb - .enb(tia_visible), // input wire enb - .addrb(buf_r_addr), // input wire [14 : 0] addrb - .doutb(fbuf_uv1) // output wire [7 : 0] doutb - ); - - Frame_Buf frame_buffer2( - .clka(tia_clk), // input wire clka - .ena(~tia_vblank & ~tia_hblank & ~write_buf1), // input wire ena - .wea(~write_buf1), // input wire [0 : 0] wea - .addra(buf_w_addr), // input wire [14 : 0] addra - .dina(uv_in), // input wire [7 : 0] dina - .clkb(clk), // input wire clkb - .enb(tia_visible), // input wire enb - .addrb(buf_r_addr), // input wire [14 : 0] addrb - .doutb(fbuf_uv2) // output wire [7 : 0] doutb - ); - - logic [7:0] tia_write_row; - logic [7:0] tia_write_col; - (* keep = "true" *) logic [7:0] tia_write_row_kept; - (* keep = "true" *) logic [7:0] tia_write_col_kept; - assign tia_write_row_kept = tia_write_row; - assign tia_write_col_kept = tia_write_col; - - logic tia_hblank_buf, tia_vblank_buf; - - always_ff @(posedge tia_clk, posedge reset) begin - if (reset) begin - tia_write_row <= 0; - tia_write_col <= 0; - tia_hblank_buf <= 0; - tia_vblank_buf <= 0; - end else begin - tia_hblank_buf <= tia_hblank; - tia_vblank_buf <= tia_vblank; - if (~tia_vblank_buf & tia_vblank) - write_buf1 <= ~write_buf1; - if (tia_hblank) begin - tia_write_col <= 8'b0; - if (~tia_hblank_buf & ~tia_vblank) begin - tia_write_row <= tia_write_row + 1; - end - end else begin - tia_write_col <= tia_write_col + 1; - end - - if (tia_vblank) - tia_write_row <= 8'd0; - end - end - - logic [7:0] uv_from_fbuf; - assign uv_from_fbuf = (write_buf1) ? fbuf_uv2 : fbuf_uv1; - assign uv = tia_en ? (tia_visible ? uv_from_fbuf : 8'd0) : (visible ? uv_in : 8'd0); - `else - assign uv = uv_in; - `endif - - - assign RED = rbuf; - assign GREEN = gbuf; - assign BLUE = bbuf; - // UV Palette data found at: http://atariage.com/forums/topic/209210-complete-ntsc-pal-color-palettes/ - // These three assign statements generated by Atari7800/palettes.py - assign red_palette = {4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'h2, 4'h1, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'hf, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'hf, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'h2, 4'h1, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'h2, 4'h1, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0}; - assign rbuf = red_palette[uv]; - - assign green_palette = {4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'hf, 4'hf, 4'hf, 4'hf, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'h2, 4'h1, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h2, 4'h1, 4'h0, 4'hf, 4'hf, 4'he, 4'hd, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h1, 4'h0, 4'h0, 4'hf, 4'he, 4'hd, 4'hc, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h1, 4'h0, 4'h0, 4'h0, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'he, 4'hd, 4'hc, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h0, 4'h0, 4'h0, 4'h0, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'hf, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'he, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0}; - assign gbuf = green_palette[uv]; - - assign blue_palette = {4'ha, 4'h9, 4'h8, 4'h7, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'ha, 4'h9, 4'h8, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'hc, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'hf, 4'he, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h4, 4'h3, 4'h2, 4'h1, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'hf, 4'hf, 4'hf, 4'hf, 4'hd, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h4, 4'h3, 4'h2, 4'h1, 4'hf, 4'he, 4'hc, 4'hb, 4'ha, 4'h9, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'hb, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'ha, 4'h9, 4'h8, 4'h7, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'h0, 4'hf, 4'hf, 4'he, 4'hd, 4'hc, 4'hb, 4'ha, 4'h8, 4'h7, 4'h6, 4'h5, 4'h4, 4'h3, 4'h2, 4'h1, 4'h0}; - assign bbuf = blue_palette[uv]; - - - // Row counter counts from 0 to 520 - // count of 0 - 479 is display time (row == line_number here) - // count of 480 - 489 is front porch - // count of 490 - 491 is VS=0 pulse width - // count of 492 - 525 is back porch - - always @(posedge clk, posedge reset) - if (reset) begin - row <= 10'd519; - end else if (row_clear) - row <= 10'd0; - else - row <= row + row_enable; - - assign row_clear = (row == 10'd524) & row_enable; - assign row_enable = (col == 10'd799); - assign VSync = (row < 10'd490) | (row > 10'd491); - - // Col counter counts from 0 to 799 - // count of 0 - 639 is display time - // count of 640 - 655 is front porch - // count of 656 - 751 is HS=0 pulse width - // count of 752 - 799 is back porch - - always @(posedge clk)//, reset) - if (reset | col_clear) - col <= 10'd0; - else - col <= col + col_enable; - - /*logic [7:0] tia_buf_col; - logic write_buf1; - logic [7:0][159:0] tia_buf1; - logic [7:0][159:0] tia_buf2; - integer i; - - always @(posedge tia_hblank) - write_buf1 <= ~write_buf1; - - always @(posedge tia_clk, posedge reset) begin - if (reset) begin - tia_buf_col <= 7'b0; - tia_buf1 <= 1280'b0; - tia_buf2 <= 1280'b0; - end else if (tia_en & tia_vsync_delta) begin - tia_buf_col <= 7'b0; - for (i=0;i<160;i=i+1) begin - tia_buf1[i] <= 8'b0; - tia_buf2[i] <= 8'b0; - end - end else if (tia_hblank) - tia_buf_col <= 8'd160; - else if (tia_buf_col == 8'd227) - tia_buf_col <= 8'd0; - else begin - tia_buf_col <= tia_buf_col + 1; - if (write_buf1) - tia_buf1[tia_buf_col] <= uv_in; - else - tia_buf2[tia_buf_col] <= uv_in; - end - end*/ - - assign col_clear = row_enable; - assign col_enable = 1'b1; - assign HSync = (col < 10'd656) | (col > 10'd751); - -endmodule \ No newline at end of file diff --git a/Console_MiST/Atari - 7800_TeST/rtl/video_mixer.sv b/Console_MiST/Atari - 7800_TeST/rtl/video_mixer.sv deleted file mode 100644 index ec953e53..00000000 --- a/Console_MiST/Atari - 7800_TeST/rtl/video_mixer.sv +++ /dev/null @@ -1,242 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd7, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Console_MiST/Bally - Astrocade_MiST/Bally Arcade - Astrocade Schematic (Excerpt from PA-1 Service Manual).gif b/Console_MiST/Bally - Astrocade_MiST/Bally Arcade - Astrocade Schematic (Excerpt from PA-1 Service Manual).gif deleted file mode 100644 index c25258ee..00000000 Binary files a/Console_MiST/Bally - Astrocade_MiST/Bally Arcade - Astrocade Schematic (Excerpt from PA-1 Service Manual).gif and /dev/null differ diff --git a/Console_MiST/Bally - Astrocade_MiST/ReadMe.txt b/Console_MiST/Bally - Astrocade_MiST/ReadMe.txt deleted file mode 100644 index 2c65d71b..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/ReadMe.txt +++ /dev/null @@ -1,21 +0,0 @@ -Untestet need Feedback - - -Copy from bally_ps2_if.vhd will be changed - - -- port 7 6 5 4 3 2 1 0 - -- x10 tg rt lt dn up | player 1 - -- x11 tg rt lt dn up | player 2 - -- x12 tg rt lt dn up | player 3 - -- x13 tg rt lt dn up | player 4 - - - -- bit x17 x16 x15 x14 maps to pc key - -- - -- 0 c ^ v % z a q 1 - -- 1 mr ms ch / x s w 2 - -- 2 7 8 9 x c d e 3 - -- 3 4 5 6 - v f r 4 - -- 4 1 2 3 + b g t 5 - -- 5 ce 0 . = n h y 6 - diff --git a/Console_MiST/Bally - Astrocade_MiST/Snapshot/bally_mist.rbf b/Console_MiST/Bally - Astrocade_MiST/Snapshot/bally_mist.rbf deleted file mode 100644 index b43d537e..00000000 Binary files a/Console_MiST/Bally - Astrocade_MiST/Snapshot/bally_mist.rbf and /dev/null differ diff --git a/Console_MiST/Bally - Astrocade_MiST/bally_mist.qpf b/Console_MiST/Bally - Astrocade_MiST/bally_mist.qpf deleted file mode 100644 index cd7b5d38..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/bally_mist.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition -# Date created = 20:08:26 November 23, 2017 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.1" -DATE = "20:08:26 November 23, 2017" - -# Revisions - -PROJECT_REVISION = "bally_mist" diff --git a/Console_MiST/Bally - Astrocade_MiST/bally_mist.qsf b/Console_MiST/Bally - Astrocade_MiST/bally_mist.qsf deleted file mode 100644 index 236f41b6..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/bally_mist.qsf +++ /dev/null @@ -1,166 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 13:20:03 July 25, 2018 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# bally_mist_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:08:26 NOVEMBER 23, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY bally_mist - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# ------------------------ -# start ENTITY(bally_mist) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(bally_mist) -# ---------------------- -set_global_assignment -name SYSTEMVERILOG_FILE rtl/bally_mist.sv -set_global_assignment -name VHDL_FILE rtl/bally.vhd -set_global_assignment -name VHDL_FILE rtl/ps2kbd.vhd -set_global_assignment -name VHDL_FILE rtl/bally_rams.vhd -set_global_assignment -name VHDL_FILE rtl/bally_ps2_if.vhd -set_global_assignment -name VHDL_FILE rtl/bally_io.vhd -set_global_assignment -name VHDL_FILE rtl/bally_data.vhd -set_global_assignment -name VHDL_FILE rtl/bally_col_pal.vhd -set_global_assignment -name VHDL_FILE rtl/bally_addr.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/spram.vhd -set_global_assignment -name VHDL_FILE rtl/sprom.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80sed.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/pll.vhd -set_global_assignment -name VERILOG_FILE rtl/game.v -set_global_assignment -name QIP_FILE rtl/cart.qip -set_global_assignment -name VHDL_FILE rtl/bally_check_cart.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Console_MiST/Bally - Astrocade_MiST/bally_mist.srf b/Console_MiST/Bally - Astrocade_MiST/bally_mist.srf deleted file mode 100644 index 269c9bf7..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/bally_mist.srf +++ /dev/null @@ -1,6 +0,0 @@ -{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL information at scandoubler.v(102): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 113007 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 113015 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80.vhd deleted file mode 100644 index da01f6b4..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80.vhd +++ /dev/null @@ -1,1080 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_ALU.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_ALU.vhd deleted file mode 100644 index 95c98dab..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_MCode.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_MCode.vhd deleted file mode 100644 index 43cea1b5..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_MCode.vhd +++ /dev/null @@ -1,1944 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_Pack.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_Pack.vhd deleted file mode 100644 index 42cf6105..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_Pack.vhd +++ /dev/null @@ -1,217 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_Reg.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80sed.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80sed.vhd deleted file mode 100644 index 0c28ec21..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/T80/T80sed.vhd +++ /dev/null @@ -1,179 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ ** --- --- Z80 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original z80 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0238 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0235 : First release --- --- 0236 : Added T2Write generic --- --- 0237 : Fixed T2Write with wait state --- --- 0238 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80sed is - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CLKEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T80sed; - -architecture rtl of T80sed is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - -begin - - u0 : T80 - generic map( - Mode => 0, - IOWait => 1) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if ((TState = "001") or (TState = "010")) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/bally.vhd deleted file mode 100644 index 314778ea..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally.vhd +++ /dev/null @@ -1,450 +0,0 @@ --- --- A simulation model of Bally Astrocade hardware --- Copyright (c) MikeJ - Nov 2004 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 003 spartan3e release --- version 001 initial release --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity BALLY is - port ( - O_AUDIO : out std_logic_vector(7 downto 0); - - O_VIDEO_R : out std_logic_vector(3 downto 0); - O_VIDEO_G : out std_logic_vector(3 downto 0); - O_VIDEO_B : out std_logic_vector(3 downto 0); - - O_HSYNC : out std_logic; - O_VSYNC : out std_logic; - O_COMP_SYNC_L : out std_logic; - O_FPSYNC : out std_logic; - - -- cart slot - O_CAS_ADDR : out std_logic_vector(12 downto 0); - O_CAS_DATA : out std_logic_vector( 7 downto 0); - I_CAS_DATA : in std_logic_vector( 7 downto 0); - O_CAS_CS_L : out std_logic; - - -- exp slot (subset for now) - O_EXP_ADDR : out std_logic_vector(15 downto 0); - O_EXP_DATA : out std_logic_vector( 7 downto 0); - I_EXP_DATA : in std_logic_vector( 7 downto 0); - I_EXP_OE_L : in std_logic; -- expansion slot driving data bus - - O_EXP_M1_L : out std_logic; - O_EXP_MREQ_L : out std_logic; - O_EXP_IORQ_L : out std_logic; - O_EXP_WR_L : out std_logic; - O_EXP_RD_L : out std_logic; - -- - O_SWITCH_COL : out std_logic_vector(7 downto 0); - I_SWITCH_ROW : in std_logic_vector(7 downto 0); - -- - I_RESET_L : in std_logic; - ENA : in std_logic; - pix_ena : out std_logic; - CLK : in std_logic; - CLK7 : in std_logic - ); -end; - -architecture RTL of BALLY is - - -- signals - signal cpu_ena : std_logic; - signal cpu_ena_gated : std_logic; - -- - signal cpu_m1_l : std_logic; - signal cpu_mreq_l : std_logic; - signal cpu_iorq_l : std_logic; - signal cpu_rd_l : std_logic; - signal cpu_wr_l : std_logic; - signal cpu_rfsh_l : std_logic; - signal cpu_halt_l : std_logic; - signal cpu_wait_l : std_logic; - signal cpu_int_l : std_logic; - signal cpu_nmi_l : std_logic; - signal cpu_busrq_l : std_logic; - signal cpu_busak_l : std_logic; - signal cpu_addr : std_logic_vector(15 downto 0); - signal cpu_data_out : std_logic_vector(7 downto 0); - signal cpu_data_in : std_logic_vector(7 downto 0); - - signal mc1 : std_logic; - signal mc0 : std_logic; - --signal mx_bus : std_logic_vector(7 downto 0); -- cpu to customs - signal mx_addr : std_logic_vector(7 downto 0); -- customs to cpu - signal mx_addr_oe_l : std_logic; - signal mx_data : std_logic_vector(7 downto 0); -- customs to cpu - signal mx_data_oe_l : std_logic; - signal mx_io : std_logic_vector(7 downto 0); -- customs to cpu - signal mx_io_oe_l : std_logic; - - signal ma_bus : std_logic_vector(15 downto 0); - signal md_bus_out : std_logic_vector(7 downto 0); - signal md_bus_in : std_logic_vector(7 downto 0); - signal md_bus_in_x : std_logic_vector(7 downto 0); - signal daten_l : std_logic; - signal datwr : std_logic; - - signal horiz_dr : std_logic; - signal vert_dr : std_logic; - signal wrctl_l : std_logic; - signal ltchdo : std_logic; - -- - -- expansion - signal exp_buzoff_l : std_logic; - signal exp_sysen : std_logic; - signal exp_casen : std_logic; - - signal sys_cs_l : std_logic; - signal rom0_dout : std_logic_vector(7 downto 0); - signal rom1_dout : std_logic_vector(7 downto 0); - signal rom_dout : std_logic_vector(7 downto 0); - signal cas_cs_l : std_logic; - - signal video_r : std_logic_vector(3 downto 0); - signal video_g : std_logic_vector(3 downto 0); - signal video_b : std_logic_vector(3 downto 0); - signal hsync : std_logic; - signal vsync : std_logic; - signal fpsync : std_logic; -begin - -- - -- cpu - -- - -- doc - -- memory map - -- 0000 - 0fff os rom / magic ram - -- 1000 - 1fff os rom - -- 2000 - 3fff cas rom - -- 4000 - 4fff screen ram - - -- in hi res screen ram from 4000 - 7fff - -- magic ram 0000 - 3fff - - -- screen - -- low res 40 bytes / line (160 pixels, 2 bits per pixel) - -- vert res 102 lines - - -- high res 80 bytes (320 pixels) and 204 lines. - -- addr 0 top left. lsb 2 bits describe right hand pixel - - -- expansion sigs - exp_buzoff_l <= '1'; -- pull up - exp_sysen <= '1'; -- pull up - exp_casen <= '1'; -- pull up - - -- other cpu signals - cpu_busrq_l <= '1'; - cpu_nmi_l <= '1'; - - cpu_ena_gated <= ENA and cpu_ena; - u_cpu : entity work.T80sed - port map ( - RESET_n => I_RESET_L, - CLK_n => CLK7, - CLKEN => cpu_ena_gated, - WAIT_n => cpu_wait_l, - INT_n => cpu_int_l, - NMI_n => cpu_nmi_l, - BUSRQ_n => cpu_busrq_l, - M1_n => cpu_m1_l, - MREQ_n => cpu_mreq_l, - IORQ_n => cpu_iorq_l, - RD_n => cpu_rd_l, - WR_n => cpu_wr_l, - RFSH_n => cpu_rfsh_l, - HALT_n => cpu_halt_l, - BUSAK_n => cpu_busak_l, - A => cpu_addr, - DI => cpu_data_in, - DO => cpu_data_out - ); - -- - -- primary addr decode - -- - p_mem_decode_comb : process(cpu_rfsh_l, cpu_rd_l, cpu_mreq_l, cpu_addr, exp_sysen, exp_casen) - variable decode : std_logic; - begin - - sys_cs_l <= '1'; -- system rom - cas_cs_l <= '1'; -- game rom - - decode := '0'; - if (cpu_rd_l = '0') and (cpu_mreq_l = '0') and (cpu_addr(15 downto 14) = "00") then - decode := '1'; - end if; - - sys_cs_l <= not (decode and (not cpu_addr(13)) and exp_sysen); - cas_cs_l <= not (decode and ( cpu_addr(13)) and exp_casen); - end process; - - --p_microcycler : process(cpu_rfsh_l, mc0, mc1) - --variable sel : std_logic_vector(1 downto 0); - --begin - --sel := mc0 & mc1; - - --if (cpu_rfsh_l = '0') then - --mx_bus <= cpu_addr(7 downto 0); - --else - --mx_bus <= x"00"; - --case sel is - --when "00" => mx_bus <= cpu_addr( 7 downto 0); - --when "01" => mx_bus <= cpu_addr(15 downto 8); - --when "10" => mx_bus <= cpu_data_out(7 downto 0); - --when "11" => mx_bus <= x"00"; -- to cpu - --when others => null; - --end case; - ---- to cpu data drive when - ----rfsh_l = '1' and mc1 = '1', mc0 direction - --end if; - --end process; - - u_rom0 : entity work.sprom - generic map ( - init_file => ".\roms\bios3159_0.hex", - widthad_a => 12, - width_a => 8 - ) - port map ( - address => cpu_addr(11 downto 0), - clock => CLK7, - q => rom0_dout - ); - - u_rom1 : entity work.sprom - generic map ( - init_file => ".\roms\bios3159_1.hex", - widthad_a => 12, - width_a => 8 - ) - port map ( - address => cpu_addr(11 downto 0), - clock => CLK7, - q => rom1_dout - ); - - p_rom_mux : process(cpu_addr, rom0_dout, rom1_dout) - begin - if (cpu_addr(12) = '0') then - rom_dout <= rom0_dout; - else - rom_dout <= rom1_dout; - end if; - - end process; - - p_cpu_src_data_mux : process(rom_dout, sys_cs_l, I_CAS_DATA, cas_cs_l, I_EXP_OE_L, I_EXP_DATA, exp_buzoff_l, - mx_addr_oe_l, mx_addr, mx_data_oe_l, mx_data, mx_io_oe_l, mx_io) - begin - -- nasty mux - if (I_EXP_OE_L = '0') or (exp_buzoff_l = '0') then - cpu_data_in <= I_EXP_DATA; - elsif (sys_cs_l = '0') then - cpu_data_in <= rom_dout; - elsif (cas_cs_l = '0') then - cpu_data_in <= I_CAS_DATA; - elsif (mx_addr_oe_l = '0') then - cpu_data_in <= mx_addr; - elsif (mx_data_oe_l = '0') then - cpu_data_in <= mx_data; - elsif (mx_io_oe_l = '0') then - cpu_data_in <= mx_io; - else - cpu_data_in <= x"FF"; - end if; - end process; - - u_addr : entity work.BALLY_ADDR - port map ( - I_MXA => cpu_addr, - I_MXD => cpu_data_out, - O_MXD => mx_addr, - O_MXD_OE_L => mx_addr_oe_l, - - -- cpu control signals - I_RFSH_L => cpu_rfsh_l, - I_M1_L => cpu_m1_l, - I_RD_L => cpu_rd_l, - I_MREQ_L => cpu_mreq_l, - I_IORQ_L => cpu_iorq_l, - O_WAIT_L => cpu_wait_l, - O_INT_L => cpu_int_l, - - -- custom - I_HORIZ_DR => horiz_dr, - I_VERT_DR => vert_dr, - O_WRCTL_L => wrctl_l, - O_LTCHDO => ltchdo, - - -- dram address - O_MA => ma_bus, - O_RAS => open, - -- misc - I_LIGHT_PEN_L => '1', - - -- clks - I_CPU_ENA => cpu_ena, - ENA => ENA, - CLK => CLK7 - ); - - u_data : entity work.BALLY_DATA - port map ( - I_MXA => cpu_addr, - I_MXD => cpu_data_out, - O_MXD => mx_data, - O_MXD_OE_L => mx_data_oe_l, - - -- cpu control signals - I_M1_L => cpu_m1_l, - I_RD_L => cpu_rd_l, - I_MREQ_L => cpu_mreq_l, - I_IORQ_L => cpu_iorq_l, - - -- memory - O_DATEN_L => daten_l, - O_DATWR => datwr, -- makes dp ram timing easier - I_MDX => md_bus_in_x, - I_MD => md_bus_in, - O_MD => md_bus_out, - O_MD_OE_L => open, - -- custom - O_MC1 => mc1, - O_MC0 => mc0, - - O_HORIZ_DR => horiz_dr, - O_VERT_DR => vert_dr, - I_WRCTL_L => wrctl_l, - I_LTCHDO => ltchdo, - - I_SERIAL1 => '0', - I_SERIAL0 => '0', - - O_VIDEO_R => video_r, - O_VIDEO_G => video_g, - O_VIDEO_B => video_b, - O_HSYNC => hsync, - O_VSYNC => vsync, - O_FPSYNC => fpsync, - -- clks - O_CPU_ENA => cpu_ena, -- cpu clock ena - O_PIX_ENA => pix_ena, -- pixel clock ena - ENA => ENA, - CLK => CLK7 --- CLK7 => CLK7 - ); - - u_io : entity work.BALLY_IO - port map ( - I_MXA => cpu_addr, - I_MXD => cpu_data_out, - O_MXD => mx_io, - O_MXD_OE_L => mx_io_oe_l, - - -- cpu control signals - I_M1_L => cpu_m1_l, - I_RD_L => cpu_rd_l, - I_IORQ_L => cpu_iorq_l, - I_RESET_L => I_RESET_L, - - -- no pots - student project ? :) - - -- switches - O_SWITCH => O_SWITCH_COL, - I_SWITCH => I_SWITCH_ROW, - -- audio - O_AUDIO => O_AUDIO, - - -- clks - I_CPU_ENA => cpu_ena, - ENA => ENA, - CLK => CLK7 - ); - - p_video_out : process - begin - wait until rising_edge(CLK7); - if (ENA = '1') then - O_HSYNC <= hsync; - O_VSYNC <= vsync; - O_COMP_SYNC_L <= (not vsync) and (not hsync); - - O_VIDEO_R <= video_r; - O_VIDEO_G <= video_g; - O_VIDEO_B <= video_b; - O_FPSYNC <= fpsync; - end if; - end process; - - u_rams : entity work.BALLY_RAMS - port map ( - ADDR => ma_bus, - DIN => md_bus_out, - DOUT => md_bus_in, - DOUTX => md_bus_in_x, - WE => datwr, - WE_ENA_L => daten_l, -- only used for write - ENA => ENA, - CLK => CLK7 - ); - - -- drive cas - O_CAS_ADDR <= cpu_addr(12 downto 0); - O_CAS_DATA <= cpu_data_out; - O_CAS_CS_L <= cas_cs_l; - - -- drive exp - -- all sigs should be bi-dir as exp slot devices can take control of the bus - -- this will be ok for the test cart - O_EXP_ADDR <= cpu_addr; - O_EXP_DATA <= cpu_data_out; -- not quite right, should be resolved data bus so exp slot can read customs / ram - O_EXP_M1_L <= cpu_m1_l; - O_EXP_MREQ_L <= cpu_mreq_l; - O_EXP_IORQ_L <= cpu_iorq_l; - O_EXP_WR_L <= cpu_wr_l; - O_EXP_RD_L <= cpu_rd_l; - - -end RTL; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_addr.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/bally_addr.vhd deleted file mode 100644 index 8b865fd0..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_addr.vhd +++ /dev/null @@ -1,473 +0,0 @@ --- --- A simulation model of Bally Astrocade hardware --- Copyright (c) MikeJ - Nov 2004 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 004 spartan3e hires release --- version 003 spartan3e release --- version 001 initial release --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity BALLY_ADDR is - port ( - I_MXA : in std_logic_vector(15 downto 0); - I_MXD : in std_logic_vector( 7 downto 0); - O_MXD : out std_logic_vector( 7 downto 0); - O_MXD_OE_L : out std_logic; - - -- cpu control signals - I_RFSH_L : in std_logic; - I_M1_L : in std_logic; - I_RD_L : in std_logic; - I_MREQ_L : in std_logic; - I_IORQ_L : in std_logic; - O_WAIT_L : out std_logic; - O_INT_L : out std_logic; - - -- custom - I_HORIZ_DR : in std_logic; - I_VERT_DR : in std_logic; - O_WRCTL_L : out std_logic; -- present ram write data - O_LTCHDO : out std_logic; -- latch ram read data - - -- dram address (sram now) - O_MA : out std_logic_vector(15 downto 0); - O_RAS : out std_logic; -- for simulation - - -- misc - I_LIGHT_PEN_L : in std_logic; - - -- clks - I_CPU_ENA : in std_logic; - ENA : in std_logic; - CLK : in std_logic - ); -end; - -architecture RTL of BALLY_ADDR is - -- Signals - signal mxa_t1 : std_logic_vector(15 downto 0); - signal page_03 : std_logic; - signal page_47 : std_logic; - signal page_8B : std_logic; - signal ports_10_17 : std_logic; - signal vector_read : std_logic; - signal rw : std_logic; - signal iorw : std_logic; - signal mreq_l_e1 : std_logic; - signal iorq_l_e1 : std_logic; - signal start_cpu_cyc : std_logic; - signal delay_cpu_cyc : std_logic; - signal start_cpu_cyc_late : std_logic; - signal cpu_cyc : std_logic; - signal cpu_cyc_t1 : std_logic; - signal start_io_cyc : std_logic; - signal start_io_cyc_e1 : std_logic; - signal start_io_cyc_e2 : std_logic; - signal video_cyc : std_logic; - signal video_cyc_ras : std_logic; - signal video_cyc_ras_t1 : std_logic; - - signal m1_wait : std_logic; - signal io_wait : std_logic; - signal io_wait_t1 : std_logic; - signal io_wait_t2 : std_logic; - signal ras_int : std_logic; - signal ras_int_t1 : std_logic; - signal wrctl_int : std_logic; - signal wrctl_int_t1 : std_logic; - signal ltchdo_int : std_logic; - signal ltchdo_int_t1 : std_logic; - -- - signal cs : std_logic; - signal r_hi_res : std_logic; - signal r_vert_blank : std_logic_vector(7 downto 0) := x"10"; -- line 8 (7..1) - signal r_int_fb : std_logic_vector(7 downto 0); - signal r_int_ena_mode : std_logic_vector(7 downto 0); - signal r_int_line : std_logic_vector(7 downto 0); - - -- - signal horiz_dr_t1 : std_logic; - signal h_start : boolean; - signal horiz_pos : std_logic_vector(7 downto 0) := (others => '0'); - signal vert_pos : std_logic_vector(7 downto 0) := (others => '0'); - signal horiz_eol : boolean; - signal hactv : std_logic; - signal vactv : std_logic; - -- addr gen - signal vert_addr_gen : std_logic_vector(15 downto 0); - signal vert_line_sel : std_logic; - signal addr_gen : std_logic_vector(15 downto 0); - signal addr_gen_t1 : std_logic_vector(15 downto 0); - -- - signal lightpen_int : std_logic := '0'; - signal screen_int : std_logic := '0'; - signal int_out : std_logic; - signal int_auto_clear : std_logic; - signal int_auto_clear_e1 : std_logic; -begin - - p_chip_sel : process(I_CPU_ENA, I_MXA) - begin - cs <= '0'; - if (I_CPU_ENA = '1') then -- cpu access - if (I_MXA(7 downto 4) = "0000") then - cs <= '1'; - end if; - end if; - end process; - - p_reg_write : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_RD_L = '1') and (I_IORQ_L = '0') and (I_M1_L = '1') and (cs = '1') then - case I_MXA(3 downto 0) is - when x"8" => r_hi_res <= I_MXD(0); - when x"A" => r_vert_blank <= I_MXD; - when x"D" => r_int_fb <= I_MXD; -- D int vec. 3..0 set to zero for lightpen - when x"E" => r_int_ena_mode <= I_MXD; -- E - when x"F" => r_int_line <= I_MXD; -- F - when others => null; - end case; - end if; - end if; - end process; - - p_decode_cpu : process(I_MXA, I_RFSH_L, I_M1_L, I_MREQ_L, I_IORQ_L) - begin - page_03 <= '0'; - page_47 <= '0'; - page_8B <= '0'; - ports_10_17 <= '0'; - - if (I_MXA(15 downto 14) = "00") then -- 0x0000 - 0x3FFF - --if (I_MXA(14) = '0') then -- I think magic writes alias (not in high res) - page_03 <= '1'; - end if; - - if (I_MXA(15 downto 14) = "01") then -- 0x4000 - 0x7FFF - page_47 <= '1'; - end if; - - if (I_MXA(15 downto 14) = "10") then -- 0x8000 - 0xBFFF - page_8B <= '1'; - end if; - - if (I_MXA(7 downto 5) = "000") and (I_MXA(3) = '0') then - ports_10_17 <= '1'; - end if; - - vector_read <= not I_IORQ_L and not I_M1_L; -- interrupt ack - iorw <= not I_IORQ_L and I_M1_L; - rw <= not I_MREQ_L and I_RFSH_L; - - - end process; - - -- if start ram cyc and video cyc, assert wait for a clock then kick off - -- start ram cyc a clock later - p_cyc_start : process(page_03, page_47, page_8B, rw, mreq_l_e1, iorw, iorq_l_e1, i_RD_L) - begin - start_cpu_cyc <= (page_8B and rw and mreq_l_e1) or - (page_47 and rw and mreq_l_e1) or - (page_03 and rw and mreq_l_e1 and I_RD_L); -- magic write - - start_io_cyc <= iorw and iorq_l_e1; - end process; - - p_cpu_cyc : process(start_cpu_cyc, start_cpu_cyc_late, video_cyc) - begin - cpu_cyc <= (start_cpu_cyc and not video_cyc) or start_cpu_cyc_late; - delay_cpu_cyc <= start_cpu_cyc and video_cyc; - end process; - - p_ram_control_cpu_ena : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_CPU_ENA = '1') then - start_cpu_cyc_late <= delay_cpu_cyc; - - mreq_l_e1 <= I_MREQ_L; - iorq_l_e1 <= I_IORQ_L; - - ras_int <= cpu_cyc; - wrctl_int <= cpu_cyc and I_RD_L; - ltchdo_int <= cpu_cyc and not I_RD_L; - - m1_wait <= cpu_cyc and not I_M1_L; -- extra wait for instruction fetch - - start_io_cyc_e1 <= start_io_cyc; - start_io_cyc_e2 <= start_io_cyc_e1; - - if (I_RD_L = '0') and (ports_10_17 = '1') then - io_wait <= start_io_cyc or start_io_cyc_e1 or start_io_cyc_e2; - else - io_wait <= start_io_cyc; - end if; - - end if; - end if; - end process; - - p_ram_address : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - mxa_t1 <= I_MXA; - if (video_cyc_ras_t1 = '1') then - -- video addr - if (r_hi_res = '1') then - O_MA <= addr_gen_t1(14 downto 0) & '0'; - else - O_MA <= x"0" & addr_gen_t1(11 downto 0); - end if; - else - O_MA <= mxa_t1(15 downto 0); - end if; - end if; - end process; - - p_ram_control : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - - -- wrctl same timing as RAS for write - -- in real chip I think it's backedge clocked off cpu clk. We will clock it out on clk_7 - - -- ras 0 - 3 would be decoded from top 2 addr bits - -- driven for simluation. - cpu_cyc_t1 <= cpu_cyc; - ras_int_t1 <= ras_int; - - if (video_cyc_ras_t1 = '1') then - O_RAS <= '1'; - else - if (I_RD_L = '0') then - O_RAS <= cpu_cyc_t1; -- clock early for read - else - O_RAS <= ras_int_t1; - end if; - end if; - - wrctl_int_t1 <= wrctl_int; - O_WRCTL_L <= not wrctl_int_t1; - - ltchdo_int_t1 <= ltchdo_int; - O_LTCHDO <= ltchdo_int_t1; - end if; - end process; - - p_mxd_oe : process(vector_read, r_int_fb) - begin - O_MXD <= x"00"; - O_MXD_OE_L <= '1'; - if (vector_read = '1') then - -- if light pen then set bottom 4 bits to 0 (not imp) - O_MXD <= r_int_fb; - O_MXD_OE_L <= '0'; - end if; - end process; - - -- ** our wait is 1/2 cpu cycle late as our cpu drops mreq later than a real one ** - -- two wait states if opcode fetch from ram - -- two wait states for io r/w except reads from addr 10-17 which have four wait states - -- real z80's insert one wait state automatically - O_WAIT_L <= not (cpu_cyc or delay_cpu_cyc or m1_wait or start_io_cyc or io_wait); - - -- video timing - p_start_of_line : process(I_HORIZ_DR, horiz_dr_t1) - begin - h_start <= (I_HORIZ_DR = '1') and (horiz_dr_t1 = '0'); -- rising edge - end process; - - p_active_picture : process - variable vcomp : std_logic_vector(7 downto 0); - begin - wait until rising_edge(CLK); - if (ENA = '1') then - - if (I_HORIZ_DR = '1') then - horiz_pos <= (others => '0'); - elsif (I_CPU_ENA = '1') then -- clk phi - horiz_pos <= horiz_pos + "1"; - end if; - - horiz_dr_t1 <= I_HORIZ_DR; - if (I_VERT_DR = '1') then - vert_pos <= (others => '0'); - elsif h_start then - if (vert_pos = x"ff") then - null; - else - vert_pos <= vert_pos + "1"; - end if; - end if; - - -- bit of guesswork here - horiz_eol <= false; - if (I_CPU_ENA = '1') then - if (horiz_pos = x"01") then - hactv <= '1'; - elsif (horiz_pos = x"51") then - horiz_eol <= true; - hactv <= '0'; - end if; - end if; - vcomp := r_vert_blank(7 downto 0); - -- ADDR chip does video fetch for all lines - 191 lines for boot menu, 190 displayed - --if (r_hi_res = '0') then - --vcomp(0) := '0'; - --end if; - - -- vert_pos gets reset with vert_drv and then must not wrap until the next one. - vactv <= '0'; - if (vert_pos < vcomp) then -- vcomp is x2 as bits 7..1 used - vactv <= '1'; - end if; - end if; - end process; - - p_video_cyc : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_CPU_ENA = '1') then - video_cyc <= '0'; - if (hactv = '1') and (vactv = '1') and (horiz_pos(0) = '0') then - video_cyc <= '1'; - end if; - video_cyc_ras <= video_cyc; - end if; - video_cyc_ras_t1 <= video_cyc_ras; - end if; - end process; - - p_video_addr_gen : process - variable eol : boolean; - begin - wait until rising_edge(CLK); - eol := (horiz_pos = x"60") and (I_CPU_ENA = '1'); -- not critical as long as before h_start - if (ENA = '1') then - if (I_VERT_DR = '1') then - vert_addr_gen <= (others => '0'); - vert_line_sel <= '0'; - elsif eol then - vert_line_sel <= not vert_line_sel; - if (vert_line_sel = '1') or (r_hi_res = '1') then - -- inc line early - vert_addr_gen <= vert_addr_gen + x"0028"; -- 40 decimal - end if; - end if; - - if (I_VERT_DR = '1') then - addr_gen <= (others => '0'); - elsif h_start then - addr_gen <= vert_addr_gen; -- load - elsif (video_cyc_ras = '1') and (I_CPU_ENA = '1') then - addr_gen <= addr_gen + "1"; -- inc - end if; - - addr_gen_t1 <= addr_gen; - end if; - end process; - -- - -- interrupt - -- - p_interrupt : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - -- r_int_ena_mode - -- bit 0 light pen mode (0 continue interrupt, 1 auto int clear at next inst) - -- bit 1 light pen interrupt enable - -- bit 2 screen mode (as 0) - -- bit 3 screen interrupt enable - - -- r_int_fb interrupt vector, set lower 4 bits to 0 for light pen interrupt - -- r_int_line interrupt on line number (7..1) low res - when completes scanning - -- int ack by iorq_l and mreq_l active together - - -- guess where the interrupt happens, lets use the clock right after active video - -- also assuming first 2 lines are line 0 ?? so writing 4 will interrupt after - -- the sixth scan line (3rd whole line) - --screen_int <= '0'; - if horiz_eol then - if (vert_pos(7 downto 0) = (r_int_line(7 downto 1) & '1')) then -- low res - screen_int <= '1'; - end if; - end if; - - if (vector_read = '1') or ((int_auto_clear_e1 = '1') and (r_int_ena_mode(2) = '1')) then - screen_int <= '0'; - end if; - - lightpen_int <= '0'; - - -- auto clear - if (I_CPU_ENA = '1') and (I_M1_L = '0') then - int_auto_clear <= int_out; - int_auto_clear_e1 <= int_auto_clear; - end if; - end if; - end process; - - p_combine_interrupts : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - int_out <= '0'; - if (r_int_ena_mode(1) = '1') then - if (lightpen_int = '1') then int_out <= '1'; end if; - end if; - - if (r_int_ena_mode(3) = '1') then - if (screen_int = '1') then int_out <= '1'; end if; - end if; - end if; - end process; - O_INT_L <= not int_out; - -end architecture RTL; - diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_check_cart.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/bally_check_cart.vhd deleted file mode 100644 index 22dd4812..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_check_cart.vhd +++ /dev/null @@ -1,121 +0,0 @@ --- --- A simulation model of Bally Astrocade hardware --- Copyright (c) MikeJ - Nov 2004 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 003 spartan3e release --- version 001 initial release --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity BALLY_CHECK_CART is - port ( - I_EXP_ADDR : in std_logic_vector(15 downto 0); - I_EXP_DATA : in std_logic_vector( 7 downto 0); - O_EXP_DATA : out std_logic_vector( 7 downto 0); - O_EXP_OE_L : out std_logic; - - I_EXP_M1_L : in std_logic; - I_EXP_MREQ_L : in std_logic; - I_EXP_IORQ_L : in std_logic; - I_EXP_WR_L : in std_logic; - I_EXP_RD_L : in std_logic; - -- - O_CHAR_MSB : out std_logic_vector(3 downto 0); - O_CHAR_LSB : out std_logic_vector(3 downto 0); - -- - I_RESET_L : in std_logic; - ENA : in std_logic; - CLK : in std_logic - ); -end; - -architecture RTL of BALLY_CHECK_CART is - - signal dout : std_logic_vector(7 downto 0); - -begin - -- chars 0-9, a = '-', b = 'E', c = 'H', d = 'L', e = 'P', f = blank - u_rom : entity work.sprom - generic map ( - init_file => ".\roms\balcheck.hex", - widthad_a => 11, - width_a => 8 - ) - port map ( - address => I_EXP_ADDR(10 downto 0), - clock => CLK, - q => dout - ); - - - p_dout : process(dout, I_EXP_ADDR) - begin - O_EXP_DATA <= dout; - -- jump direct for intercept or / xor test - the tricky one ! - --if I_EXP_ADDR = x"20c4" then O_EXP_DATA <= x"31"; end if; - --if I_EXP_ADDR = x"20c5" then O_EXP_DATA <= x"c8"; end if; - --if I_EXP_ADDR = x"20c6" then O_EXP_DATA <= x"4f"; end if; - --if I_EXP_ADDR = x"20c7" then O_EXP_DATA <= x"c3"; end if; - --if I_EXP_ADDR = x"20c8" then O_EXP_DATA <= x"c8"; end if; - --if I_EXP_ADDR = x"20c9" then O_EXP_DATA <= x"21"; end if; - end process; - - p_cs : process(I_EXP_ADDR, I_EXP_RD_L, I_EXP_MREQ_L) - begin - O_EXP_OE_L <= '1'; - if (I_EXP_RD_L = '0') and (I_EXP_MREQ_L = '0') and (I_EXP_ADDR(14 downto 13) = "01") then - O_EXP_OE_L <= '0'; - end if; - end process; - - p_latch : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_EXP_ADDR(7 downto 4) = "1111") and (I_EXP_IORQ_L = '0') and (I_EXP_M1_L = '1') then - O_CHAR_MSB <= I_EXP_DATA(7 downto 4); - O_CHAR_LSB <= I_EXP_DATA(3 downto 0); - end if; - end if; - end process; - -end RTL; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_col_pal.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/bally_col_pal.vhd deleted file mode 100644 index e627943d..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_col_pal.vhd +++ /dev/null @@ -1,101 +0,0 @@ --- --- A simulation model of Bally Astrocade hardware --- Copyright (c) MikeJ - Nov 2004 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 003 spartan3e release --- version 001 initial release --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity BALLY_COL_PAL is - port ( - ADDR : in std_logic_vector(7 downto 0); - DATA : out std_logic_vector(11 downto 0) - ); -end; - -architecture RTL of BALLY_COL_PAL is - - type ROM_ARRAY is array(0 to 255) of std_logic_vector(11 downto 0); - constant ROM : ROM_ARRAY := ( - x"000", x"222", x"444", x"666", x"999", x"BBB", x"DDD", x"FFF", - x"20B", x"40E", x"61F", x"93F", x"B5F", x"D7F", x"FAF", x"FCF", - x"40B", x"60D", x"90F", x"B2F", x"D4F", x"F6F", x"F9F", x"FBF", - x"609", x"80C", x"B0E", x"D1F", x"F3F", x"F6F", x"F8F", x"FAF", - x"808", x"A0A", x"D0D", x"F0F", x"F3F", x"F5F", x"F7F", x"F9F", - x"906", x"C08", x"E0B", x"F0D", x"F2F", x"F5F", x"F7F", x"F9F", - x"B04", x"D06", x"F09", x"F0B", x"F2D", x"F4F", x"F7F", x"F9F", - x"B02", x"E04", x"F06", x"F09", x"F2B", x"F4D", x"F7F", x"F9F", - x"B00", x"E02", x"F04", x"F06", x"F39", x"F5B", x"F7D", x"F9F", - x"B00", x"E00", x"F02", x"F14", x"F36", x"F59", x"F8B", x"FAD", - x"B00", x"D00", x"F00", x"F22", x"F44", x"F66", x"F89", x"FBB", - x"900", x"C00", x"E00", x"F30", x"F52", x"F74", x"F97", x"FC9", - x"800", x"A00", x"D10", x"F40", x"F60", x"F82", x"FA5", x"FD7", - x"600", x"800", x"B30", x"D50", x"F70", x"F91", x"FC3", x"FE5", - x"400", x"620", x"940", x"B60", x"D80", x"FB0", x"FD2", x"FF4", - x"210", x"430", x"650", x"970", x"BA0", x"DC0", x"FE1", x"FF4", - x"020", x"240", x"460", x"690", x"9B0", x"BD0", x"DF1", x"FF3", - x"030", x"050", x"280", x"4A0", x"6C0", x"9E0", x"BF1", x"DF4", - x"040", x"060", x"090", x"2B0", x"4D0", x"6F0", x"9F2", x"BF4", - x"050", x"070", x"090", x"0C0", x"2E0", x"4F1", x"7F3", x"9F5", - x"050", x"080", x"0A0", x"0C0", x"0F0", x"2F2", x"5F5", x"7F7", - x"060", x"080", x"0A0", x"0D0", x"0F2", x"1F4", x"3F7", x"5F9", - x"060", x"080", x"0B0", x"0D2", x"0F4", x"0F6", x"2F9", x"4FB", - x"060", x"080", x"0A2", x"0D4", x"0F6", x"0F9", x"1FB", x"4FD", - x"060", x"082", x"0A4", x"0C6", x"0F9", x"0FB", x"1FD", x"3FF", - x"052", x"074", x"0A6", x"0C9", x"0EB", x"0FD", x"1FF", x"4FF", - x"044", x"076", x"099", x"0BB", x"0DD", x"0FF", x"2FF", x"4FF", - x"036", x"068", x"08B", x"0AD", x"0CF", x"1FF", x"3FF", x"5FF", - x"028", x"04A", x"07D", x"09F", x"0BF", x"2EF", x"5FF", x"7FF", - x"019", x"03C", x"06E", x"08F", x"2AF", x"4CF", x"7FF", x"9FF", - x"00B", x"02D", x"04F", x"27F", x"49F", x"6BF", x"9DF", x"BFF", - x"00B", x"01E", x"23F", x"45F", x"68F", x"9AF", x"BCF", x"DEF" - ); - -begin - - p_rom : process(ADDR) - begin - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_data.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/bally_data.vhd deleted file mode 100644 index 2ecafdad..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_data.vhd +++ /dev/null @@ -1,1039 +0,0 @@ --- --- A simulation model of Bally Astrocade hardware --- Copyright (c) MikeJ - Nov 2004 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 004 spartan3e hires release --- version 003 spartan3e release --- version 001 initial release --- --- microcycler not used -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity BALLY_DATA is - port ( - I_MXA : in std_logic_vector(15 downto 0); - I_MXD : in std_logic_vector( 7 downto 0); - O_MXD : out std_logic_vector( 7 downto 0); - O_MXD_OE_L : out std_logic; - - -- cpu control signals - I_M1_L : in std_logic; - I_RD_L : in std_logic; - I_MREQ_L : in std_logic; - I_IORQ_L : in std_logic; - - -- memory - O_DATEN_L : out std_logic; -- looks like the real chip - O_DATWR : out std_logic; -- ram ena to fake up write at rising edge of DATEN_L - I_MDX : in std_logic_vector( 7 downto 0); -- upper 8 bits for high res - I_MD : in std_logic_vector( 7 downto 0); - O_MD : out std_logic_vector( 7 downto 0); - O_MD_OE_L : out std_logic; - -- custom - O_MC1 : out std_logic; - O_MC0 : out std_logic; - - O_HORIZ_DR : out std_logic; - O_VERT_DR : out std_logic; - I_WRCTL_L : in std_logic; - I_LTCHDO : in std_logic; - - I_SERIAL1 : in std_logic; - I_SERIAL0 : in std_logic; - - O_VIDEO_R : out std_logic_vector(3 downto 0); - O_VIDEO_G : out std_logic_vector(3 downto 0); - O_VIDEO_B : out std_logic_vector(3 downto 0); - O_HSYNC : out std_logic; - O_VSYNC : out std_logic; - O_FPSYNC : out std_logic; -- first active pixel - - -- clks - O_CPU_ENA : out std_logic; -- cpu clock ena - O_PIX_ENA : out std_logic; -- pixel clock ena - ENA : in std_logic; - CLK : in std_logic - ); -end; - -architecture RTL of BALLY_DATA is - - -- const - -- horizontal timing constants - -- approx 78 clocks blanking,34 for sync - - -- original 7.159 Mhz clock - constant H_LINE_SYNCS : std_logic_vector(8 downto 0) := conv_std_logic_vector( 0,9); - constant H_LINE_SYNCR : std_logic_vector(8 downto 0) := conv_std_logic_vector( 33,9); - constant H_BLANK_N1S : std_logic_vector(8 downto 0) := conv_std_logic_vector( 0,9); -- first eq - constant H_BLANK_N1R : std_logic_vector(8 downto 0) := conv_std_logic_vector( 16,9); - constant H_BLANK_N2S : std_logic_vector(8 downto 0) := conv_std_logic_vector(227,9); -- second eq - constant H_BLANK_N2R : std_logic_vector(8 downto 0) := conv_std_logic_vector(243,9); - constant H_BLANK_B1S : std_logic_vector(8 downto 0) := conv_std_logic_vector( 0,9); -- first broad - constant H_BLANK_B1R : std_logic_vector(8 downto 0) := conv_std_logic_vector(193,9); - constant H_BLANK_B2S : std_logic_vector(8 downto 0) := conv_std_logic_vector(227,9); -- second broad - constant H_BLANK_B2R : std_logic_vector(8 downto 0) := conv_std_logic_vector(421,9); - constant H_BLANK_S : std_logic_vector(8 downto 0) := conv_std_logic_vector(444,9); -- horiz blanking - constant H_BLANK_R : std_logic_vector(8 downto 0) := conv_std_logic_vector( 67,9); -- 78 clocks, starting 12 before sync - - constant H_BLANK_LR : std_logic_vector(8 downto 0) := conv_std_logic_vector(245,9); -- half line left reset - constant H_BLANK_RS : std_logic_vector(8 downto 0) := conv_std_logic_vector(225,9); -- half line right set - - --constant H_DRIVE_S : std_logic_vector(8 downto 0) := conv_std_logic_vector( 60,9); -- hdrive pulse - --constant H_DRIVE_R : std_logic_vector(8 downto 0) := conv_std_logic_vector( 63,9); - --constant H_VDRIVE_R : std_logic_vector(8 downto 0) := conv_std_logic_vector( 71,9); - -- frig to get screen centered, above numbers are measured - constant H_DRIVE_S : std_logic_vector(8 downto 0) := conv_std_logic_vector( 60+8,9); -- hdrive pulse - constant H_DRIVE_R : std_logic_vector(8 downto 0) := conv_std_logic_vector( 63+8,9); - constant H_VDRIVE_R : std_logic_vector(8 downto 0) := conv_std_logic_vector( 71+8,9); - - constant H_LEN : std_logic_vector(8 downto 0) := conv_std_logic_vector(454,9); -- line length (455 clocks) - constant V_LEN : std_logic_vector(10 downto 0) := conv_std_logic_vector(525,11); -- frame length - - component BALLY_COL_PAL - port ( - ADDR : in std_logic_vector(7 downto 0); - DATA : out std_logic_vector(11 downto 0) - ); - end component; - - -- Signals - type array_8x8 is array (0 to 7) of std_logic_vector(7 downto 0); - type array_bool8 is array (0 to 7) of boolean; - - signal ena_cnt : std_logic_vector(1 downto 0) := "00"; - signal cpu_ena : std_logic; - signal cpu_ena_t1 : std_logic; - signal pix_ena : std_logic; - signal pix_load : std_logic; - signal cs_w : std_logic; - signal cs_r : std_logic; - -- cpu if - signal col_ld : array_bool8; - signal magic_ld : boolean; - signal r_col : array_8x8 := (x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00"); - signal r_hi_res : std_logic; - signal r_backgnd_col : std_logic_vector(1 downto 0) := "00"; - signal r_horiz_pos : std_logic_vector(5 downto 0) := "010100"; -- 20 - signal r_vert_blank : std_logic_vector(7 downto 0) := x"10"; -- line 8 (7..1) - --signal r_vert_blank : std_logic_vector(7 downto 0) := x"BF"; -- line 191 (7..1) - signal r_magic : std_logic_vector(7 downto 0) := x"00"; - signal r_expand : std_logic_vector(7 downto 0) := x"00"; - signal r_intercept : std_logic_vector(7 downto 0) := x"00"; - -- timing - signal do_horiz_dr : std_logic; - signal do_horiz_dr_t1 : std_logic; - signal do_vert_dr : std_logic; - signal do_vert_dr_int : std_logic; - signal hsync : std_logic; - signal vsync : std_logic := '0'; - signal vsync_t1 : std_logic; - signal v_1st_actv : std_logic; - - signal h_count : std_logic_vector ( 8 downto 0) := (others => '0'); - signal v_count : std_logic_vector (10 downto 0) := "00000000001"; - signal sg_line_sync : std_logic; - signal sg_blank_n1 : std_logic; - signal sg_blank_n2 : std_logic; - signal sg_blank_b1 : std_logic; - signal sg_blank_b2 : std_logic; - signal sg_hstart : std_logic; - signal sg_hstart_t1 : std_logic; - signal sg_hblank : std_logic; - signal sg_hblank_l : std_logic; - signal sg_hblank_r : std_logic; - signal sg_vblank : std_logic; - signal sg_vstart : std_logic; - -- - signal sg_blanking_EQ : std_logic; - signal sg_blanking_BRD : std_logic; - signal sg_line263 : std_logic; - signal sg_line266 : std_logic; - signal sg_line269 : std_logic; - signal sg_line272 : std_logic; - signal sg_line283 : std_logic; - signal sg_sync : std_logic; - signal sg_blank : std_logic; - signal sg_neg_sync : std_logic; - - -- - signal horiz_pos : std_logic_vector(7 downto 0); - signal vert_pos : std_logic_vector(7 downto 0); - signal hactv : std_logic; - signal vactv : std_logic; - - -- data - signal ram_write_reg : std_logic_vector(7 downto 0); - signal datwr : std_logic; - signal ltchdo_t1 : std_logic; - signal mxd_out_ena : std_logic; - signal mxd_out_intercept : std_logic; - signal mxd_out_intercept_e1 : std_logic; - -- video - signal video_cyc : std_logic; - signal video_cyc_ras : std_logic; - signal video_cyc_ras_t1 : std_logic; - signal video_cyc_ras_t2 : std_logic; - signal video_shifter : std_logic_vector(15 downto 0); - signal video_shifter_lflag : std_logic; - signal video_shifter_actv : std_logic; - - signal lflag : std_logic; -- left flag - signal lflag_inhib : std_logic; - signal lflag_e : std_logic_vector(2 downto 0); - signal hactv_e : std_logic_vector(2 downto 0); - signal col_in : std_logic_vector(7 downto 0); - signal col_out : std_logic_vector(11 downto 0); - -- datapath - signal done_magic_write : std_ulogic; - signal done_magic_write_t1 : std_ulogic; - signal expand_lower_sel : std_logic; - - signal expand_out : std_logic_vector(7 downto 0); - signal flopper_out : std_logic_vector(7 downto 0); - signal pixel_collide : std_logic_vector(3 downto 0); - - signal shifter_out : std_logic_vector(13 downto 0); - signal shifter_out_reg : std_logic_vector(5 downto 0); - - signal rotate_cnt : std_logic_vector(2 downto 0); - signal rotate_inhibit_write : std_logic; - signal rotate_pixa : std_logic_vector(7 downto 0) := (others => '0'); - signal rotate_pixb : std_logic_vector(7 downto 0) := (others => '0'); - signal rotate_pixc : std_logic_vector(7 downto 0) := (others => '0'); - signal rotate_pixd : std_logic_vector(7 downto 0) := (others => '0'); - signal rotate_out : std_logic_vector(7 downto 0); - signal magic_final : std_logic_vector(7 downto 0); - signal ram_ip_reg : std_logic_vector(7 downto 0); - signal ram_op_reg : std_logic_vector(7 downto 0); - -begin - - p_chip_sel : process(cpu_ena, I_MXA) - begin - cs_w <= '0'; - cs_r <= '0'; - if (cpu_ena = '1') then -- cpu access - if (I_MXA(7 downto 5) = "000") then - cs_w <= '1'; - end if; - end if; - if (I_MXA(7 downto 4) = "0000") then - cs_r <= '1'; - end if; - - end process; - - -- - -- registers - -- - p_reg_write : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_RD_L = '1') and (I_IORQ_L = '0') and (I_M1_L = '1') and (cs_w = '1') then - case I_MXA(4 downto 0) is - when "01000" => r_hi_res <= I_MXD(0); -- 8 - when "01001" => r_backgnd_col <= I_MXD(7 downto 6); -- 9 - r_horiz_pos <= I_MXD(5 downto 0); - when "01010" => r_vert_blank <= I_MXD; -- A - -- B - when "01100" => r_magic <= I_MXD; -- C - when "11001" => r_expand <= I_MXD; -- 19 - - when others => null; - end case; - end if; - end if; - end process; - - p_reg_write_blk_decode : process(I_RD_L, I_M1_L, I_IORQ_L, cs_w, I_MXA) - begin - -- these writes will last for several cpu_ena cycles, so you - -- will get several load pulses - col_ld <= (others => false); - magic_ld <= false; - if (I_RD_L = '1') and (I_IORQ_L = '0') and (I_M1_L = '1') and (cs_w = '1') and (I_MXA(4) = '0') then - col_ld(0) <= ( I_MXA( 3 downto 0) = x"0") or - ((I_MXA(10 downto 8) = "000") and (I_MXA(3 downto 0) = x"B")); - - col_ld(1) <= ( I_MXA( 3 downto 0) = x"1") or - ((I_MXA(10 downto 8) = "001") and (I_MXA(3 downto 0) = x"B")); - - col_ld(2) <= ( I_MXA( 3 downto 0) = x"2") or - ((I_MXA(10 downto 8) = "010") and (I_MXA(3 downto 0) = x"B")); - - col_ld(3) <= ( I_MXA( 3 downto 0) = x"3") or - ((I_MXA(10 downto 8) = "011") and (I_MXA(3 downto 0) = x"B")); - - col_ld(4) <= ( I_MXA( 3 downto 0) = x"4") or - ((I_MXA(10 downto 8) = "100") and (I_MXA(3 downto 0) = x"B")); - - col_ld(5) <= ( I_MXA( 3 downto 0) = x"5") or - ((I_MXA(10 downto 8) = "101") and (I_MXA(3 downto 0) = x"B")); - - col_ld(6) <= ( I_MXA( 3 downto 0) = x"6") or - ((I_MXA(10 downto 8) = "110") and (I_MXA(3 downto 0) = x"B")); - - col_ld(7) <= ( I_MXA( 3 downto 0) = x"7") or - ((I_MXA(10 downto 8) = "111") and (I_MXA(3 downto 0) = x"B")); - - magic_ld <= ( I_MXA( 3 downto 0) = x"C"); - end if; - end process; - - p_reg_write_blk : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - for i in 0 to 7 loop - if col_ld(i) then r_col(i) <= I_MXD; end if; - end loop; - end if; - end process; - - p_cpu_ena : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (do_horiz_dr = '1') then -- 3 clocks long - ena_cnt <= "00"; - else - ena_cnt <= ena_cnt + "1"; - end if; - - cpu_ena <= '0'; - if (ena_cnt = "10") then - cpu_ena <= '1'; - end if; - - if (r_hi_res = '1') then - pix_ena <= '1'; - else - pix_ena <= ena_cnt(0); - end if; - pix_load <= cpu_ena; - end if; - end process; - O_CPU_ENA <= cpu_ena; - O_PIX_ENA <= pix_ena; - - p_micro_gen : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - -- not used - O_MC1 <= '0'; - O_MC0 <= '0'; - end if; - end process; - -- - -- sync generation - -- - p_hv_count : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (h_count = H_LEN) then - h_count <= (others => '0'); - if (v_count = V_LEN) then - v_count <= "00000000001"; - else - v_count <= v_count + "1"; - end if; - else - h_count <= h_count + "1"; - end if; - end if; - end process; - - p_window_h : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - -- hblank - sg_hstart <= '0'; - if (h_count = H_BLANK_S) then - sg_hblank <= '1'; - elsif h_count = H_BLANK_R then - sg_hstart <= '1'; - sg_hblank <= '0'; - end if; - - if (h_count = H_BLANK_S) then - sg_hblank_l <= '1'; - elsif h_count = H_BLANK_LR then - sg_hblank_l <= '0'; - end if; - - if (h_count = H_BLANK_RS) then - sg_hblank_r <= '1'; - elsif h_count = H_BLANK_R then - sg_hblank_r <= '0'; - end if; - - if (h_count = H_DRIVE_S) then - do_horiz_dr <= '1'; - elsif h_count = H_DRIVE_R then - do_horiz_dr <= '0'; - end if; - - if (h_count = H_DRIVE_S) then - do_vert_dr <= '1'; - elsif h_count = H_VDRIVE_R then - do_vert_dr <= '0'; - end if; - - -- low res 40 bytes / line (160 pixels, 2 bits per pixel) - -- vert res 102 lines - -- two clocks / pixel - end if; - end process; - - p_sync_h : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - -- negative sync pulse - if (h_count = H_LINE_SYNCS) then - sg_line_sync <= '1'; - elsif h_count = H_LINE_SYNCR then - sg_line_sync <= '0'; - end if; - - -- blanking narrow1 - if (h_count = H_BLANK_N1S) then - sg_blank_n1 <= '1'; - elsif h_count = H_BLANK_N1R then - sg_blank_n1 <= '0'; - end if; - - -- blanking narrow2 - if (h_count = H_BLANK_N2S) then - sg_blank_n2 <= '1'; - elsif (h_count = H_BLANK_N2R) then - sg_blank_n2 <= '0'; - end if; - - -- blanking broad1 - if (h_count = H_BLANK_B1S) then - sg_blank_b1 <= '1'; - elsif (h_count = H_BLANK_B1R) then - sg_blank_b1 <= '0'; - end if; - - -- blanking broad2 - if h_count = H_BLANK_B2S then - sg_blank_b2 <= '1'; - elsif (h_count = H_BLANK_B2R) then - sg_blank_b2 <= '0'; - end if; - end if; - end process; - - p_window_v : process - begin - wait until rising_edge(CLK); - -- line 21 first f1 nonblanked video line ** bally chip starts at 20 with a half line - -- line 44 first f1 video line - -- line 234 last f1 video line (power up menu) - -- line 263 last f1 nonblanked video line (half line) - - -- line 283 first f2 nonblanked video line (half line) - -- line 307 first f2 video line (power up menu) - -- line 497 last f2 video line - -- line 525 last f2 nonblanked video line - - -- (vblank reg is written as 191 for boot menu) - -- there are 191 active video lines read from the video store per field (when displaying menu) - -- The bally data chip seems to get the half lines wrong however (283 whole line) - -- and it puts a half line on 20. Or, I've missread the field sync pulses. - -- doesn't really matter as we are driving a vga screen for now .. - - -- 14.2857MHz (7.1428) - -- line / 455 = 15.698 K = 29.9 frames - if (ENA = '1') then - - sg_vstart <= '0'; - if (v_count = conv_std_logic_vector( 21,11)) then - sg_vblank <= '0'; - sg_vstart <= '1'; -- field one sync to scan converter - elsif (v_count = conv_std_logic_vector( 264,11)) then - sg_vblank <= '1'; - elsif (v_count = conv_std_logic_vector( 283,11)) then - sg_vblank <= '0'; - elsif (v_count = conv_std_logic_vector( 1,11)) then - sg_vblank <= '1'; - end if; - - if (v_count = conv_std_logic_vector( 4,11)) then - vsync <= '1'; - elsif (v_count = conv_std_logic_vector( 7,11)) then - vsync <= '0'; - elsif (v_count = conv_std_logic_vector( 267,11)) then - vsync <= '1'; - elsif (v_count = conv_std_logic_vector( 270,11)) then - vsync <= '0'; - end if; - - v_1st_actv <= '0'; - if (v_count = conv_std_logic_vector( 44,11)) or - (v_count = conv_std_logic_vector( 307,11)) then - v_1st_actv <= '1'; - end if; - -- timing from rising edge of v_sync - -- 4 21 263 - -- 1 18 260 - - -- 267 283 525 - -- 1 17 259 - - -- so field 2 is displayed above field 1 - this is the same as ntsc and seems - -- to be necessary to get a correct picture on my monitor taking it's sync from vsync - end if; - end process; - - p_sync_v : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - sg_blanking_eq <= '0'; - if ( (v_count = conv_std_logic_vector( 1,11)) or - (v_count = conv_std_logic_vector( 2,11)) or - (v_count = conv_std_logic_vector( 3,11)) or - (v_count = conv_std_logic_vector( 7,11)) or - (v_count = conv_std_logic_vector( 8,11)) or - (v_count = conv_std_logic_vector( 9,11)) or - (v_count = conv_std_logic_vector(264,11)) or - (v_count = conv_std_logic_vector(265,11)) or - (v_count = conv_std_logic_vector(270,11)) or - (v_count = conv_std_logic_vector(271,11)) ) then - sg_blanking_eq <= '1'; - end if; - - sg_blanking_brd <= '0'; - if ( (v_count = conv_std_logic_vector( 4,11)) or - (v_count = conv_std_logic_vector( 5,11)) or - (v_count = conv_std_logic_vector( 6,11)) or - (v_count = conv_std_logic_vector(267,11)) or - (v_count = conv_std_logic_vector(268,11)) ) then - sg_blanking_brd <= '1'; - end if; - - sg_line263 <= '0'; - if (v_count = (conv_std_logic_vector(263,11))) then - sg_line263 <= '1'; - end if; - - sg_line266 <= '0'; - if (v_count = (conv_std_logic_vector(266,11))) then - sg_line266 <= '1'; - end if; - - sg_line269 <= '0'; - if (v_count = (conv_std_logic_vector(269,11))) then - sg_line269 <= '1'; - end if; - - sg_line272 <= '0'; - if (v_count = (conv_std_logic_vector(272,11))) then - sg_line272 <= '1'; - end if; - - sg_line283 <= '0'; - if (v_count = (conv_std_logic_vector(283,11))) then - sg_line283 <= '1'; - end if; - end if; - end process; - - p_syncgen : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - sg_sync <= '0'; - - if (sg_blanking_eq = '1') then - sg_sync <= sg_blank_n1 or sg_blank_n2; - - elsif (sg_blanking_brd = '1') then - sg_sync <= sg_blank_b1 or sg_blank_b2; - - elsif (sg_line263 = '1') then - sg_sync <= sg_blank_n2 or sg_line_sync; - - elsif (sg_line266 = '1') then - sg_sync <= sg_blank_n1 or sg_blank_b2; - - elsif (sg_line269 = '1') then - sg_sync <= sg_blank_b1 or sg_blank_n2; - - elsif (sg_line272 = '1') then - sg_sync <= sg_blank_n1; - - else - sg_sync <= sg_line_sync; -- normal line. - end if; - - sg_blank <= sg_hblank or sg_vblank; - if (sg_line263 = '1') then - sg_blank <= sg_hblank_r; -- left half line - elsif (sg_line283 = '1') then - sg_blank <= sg_hblank_l; -- right half line - end if; - - hsync <= sg_line_sync; - vsync_t1 <= vsync; - end if; - end process; - - -- code duplicated in addr chip - p_active_picture : process - variable vcomp : std_logic_vector(7 downto 0); - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (do_horiz_dr = '1') then - horiz_pos <= (others => '0'); - elsif (cpu_ena = '1') then -- clk phi - horiz_pos <= horiz_pos + "1"; - end if; - - do_horiz_dr_t1 <= do_horiz_dr; - if (do_vert_dr_int = '1') then - vert_pos <= (others => '0'); - elsif (do_horiz_dr = '1') and (do_horiz_dr_t1 = '0') then -- rising edge - if (vert_pos = x"ff") then - null; - else - vert_pos <= vert_pos + "1"; - end if; - end if; - - -- bit of guesswork here - if (cpu_ena = '1') then - if (horiz_pos = x"01") then - hactv <= '1'; - elsif (horiz_pos = x"51") then - hactv <= '0'; - end if; - end if; - vcomp := r_vert_blank(7 downto 0); - -- DATA chip does line pairs only in low res mode - if (r_hi_res = '0') then - vcomp(0) := '0'; - end if; - - vactv <= '0'; - if (vert_pos < vcomp) then - vactv <= '1'; - end if; - end if; - end process; - - p_video_cyc : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (cpu_ena = '1') then - video_cyc <= '0'; - if (hactv = '1') and (vactv = '1') and (horiz_pos(0) = '0') then - video_cyc <= '1'; - end if; - video_cyc_ras <= video_cyc; - end if; - video_cyc_ras_t1 <= video_cyc_ras; - video_cyc_ras_t2 <= video_cyc_ras_t1; -- match delay to rams - end if; - end process; - - p_left_flag : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - -- apparently horiz_pos 40 or above do not have any effect - if (do_horiz_dr = '1') then - lflag_inhib <= '0'; - elsif (cpu_ena = '1') and (horiz_pos(6 downto 0) = ("1001111")) then - lflag_inhib <= '1'; - end if; - - if (do_horiz_dr = '1') then - lflag <= '1'; - elsif (cpu_ena = '1') and (horiz_pos(6 downto 0) = (r_horiz_pos & '1')) and (lflag_inhib = '0') then - lflag <= '0'; - end if; - - -- pipeline delay - if (do_horiz_dr = '1') then - lflag_e <= "111"; - hactv_e <= "000"; - - elsif (cpu_ena = '1') then - lflag_e(0) <= lflag; - lflag_e(2 downto 1) <= lflag_e(1 downto 0); - hactv_e(0) <= hactv; - hactv_e(2 downto 1) <= hactv_e(1 downto 0); - end if; - end if; - end process; - - p_video_shifter : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - -- video cyc, grab from ram - if (pix_ena = '1') then - if (pix_load = '1') and (video_cyc_ras_t2 = '1') then - video_shifter <= I_MD(7 downto 0) & I_MDX(7 downto 0); - else - -- top left pixel is bits 7,6 - video_shifter <= video_shifter(13 downto 0) & "00"; - end if; - - end if; - - if (do_horiz_dr = '1') then - video_shifter_lflag <= '1'; - video_shifter_actv <= '0'; -- background col - elsif (pix_ena = '1') and (pix_load = '1') then - video_shifter_lflag <= lflag_e(2); - video_shifter_actv <= hactv_e(2) and vactv; - end if; - end if; - end process; - - p_col_sel : process(video_shifter, video_shifter_lflag, video_shifter_actv, - r_col, r_backgnd_col) - variable sel : std_logic_vector(2 downto 0); - begin - if (video_shifter_actv = '0') then - sel := video_shifter_lflag & r_backgnd_col; - else - sel := video_shifter_lflag & video_shifter(7+8 downto 6+8); - end if; - - col_in <= (others => '0'); - case sel is - when "000" => col_in <= r_col(0); - when "001" => col_in <= r_col(1); - when "010" => col_in <= r_col(2); - when "011" => col_in <= r_col(3); - when "100" => col_in <= r_col(4); - when "101" => col_in <= r_col(5); - when "110" => col_in <= r_col(6); - when "111" => col_in <= r_col(7); - when others => null; - end case; - end process; - - u_col : entity work.BALLY_COL_PAL - port map ( - ADDR => col_in, - DATA => col_out - ); - - p_video_out : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - sg_neg_sync <= not sg_sync; - O_HSYNC <= hsync; - O_VSYNC <= vsync_t1; - - if (sg_blank = '1') then - O_VIDEO_R <= "0000"; - O_VIDEO_G <= "0000"; - O_VIDEO_B <= "0000"; - else - O_VIDEO_R <= col_out(11 downto 8); - O_VIDEO_G <= col_out( 7 downto 4); - O_VIDEO_B <= col_out( 3 downto 0); - end if; - do_vert_dr_int <= v_1st_actv and do_vert_dr; - sg_hstart_t1 <= sg_hstart; - O_FPSYNC <= sg_hstart_t1 and sg_vstart; - end if; - end process; - O_VERT_DR <= do_vert_dr_int; - O_HORIZ_DR <= do_horiz_dr; - -- - -- data path - -- - p_ramin : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - ram_write_reg <= I_MXD; - - done_magic_write <= '0'; - if (I_WRCTL_L = '0') and (I_MXA(15 downto 14) = "00") and (cpu_ena = '1') then - done_magic_write <= '1'; - end if; - done_magic_write_t1 <= done_magic_write; -- make sure we have finished ram write - end if; - end process; - - p_expand : process(ram_write_reg, r_magic, r_expand, expand_lower_sel) - variable expand_sel : std_logic_vector(3 downto 0); - begin - if (expand_lower_sel = '1') then -- reg cleared by magic, upper when 0 - expand_sel := ram_write_reg(3 downto 0); - else - expand_sel := ram_write_reg(7 downto 4); - end if; - - if (r_magic(3) = '0') then -- bypass - expand_out <= ram_write_reg; - else - for i in 0 to 3 loop - if (expand_sel(i) = '0') then - expand_out((i*2)+1 downto i*2) <= r_expand(1 downto 0); - else - expand_out((i*2)+1 downto i*2) <= r_expand(3 downto 2); - end if; - end loop; - end if; - end process; - - p_rotate_reg : process - variable shift : std_logic; - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if magic_ld then - rotate_cnt <= "000"; - expand_lower_sel <= '0'; - shifter_out_reg <= (others => '0'); - elsif (done_magic_write_t1 = '1') then - rotate_cnt <= rotate_cnt + "1"; - expand_lower_sel <= not expand_lower_sel; - shifter_out_reg <= shifter_out(5 downto 0); - end if; - - rotate_inhibit_write <= '0'; - shift := '0'; - if (I_MXA(15 downto 14) = "00") then - if (rotate_cnt(2) = '0') then - rotate_inhibit_write <= r_magic(2); -- only if using rotate - if (cpu_ena = '1') and (I_WRCTL_L = '0') then - shift := '1'; - end if; - end if; - end if; - - if (shift = '1') then - rotate_pixa <= expand_out(7 downto 6) & rotate_pixa(7 downto 2); -- top - rotate_pixb <= expand_out(5 downto 4) & rotate_pixb(7 downto 2); - rotate_pixc <= expand_out(3 downto 2) & rotate_pixc(7 downto 2); - rotate_pixd <= expand_out(1 downto 0) & rotate_pixd(7 downto 2); - end if; - end if; - end process; - - p_rotate_shifter : process(expand_out, shifter_out_reg, r_magic, - rotate_cnt, rotate_pixa, rotate_pixb, rotate_pixc, rotate_pixd) - begin - -- r_magic bits 1,0 - shifter_out <= (others => '0'); -- default - case r_magic(1 downto 0) is - when "00" => shifter_out <= expand_out(7 downto 0) & "000000"; - when "01" => shifter_out <= shifter_out_reg(5 downto 4) & expand_out(7 downto 0) & "0000" ; - when "10" => shifter_out <= shifter_out_reg(5 downto 2) & expand_out(7 downto 0) & "00" ; - when "11" => shifter_out <= shifter_out_reg(5 downto 0) & expand_out(7 downto 0); - when others => null; - end case; - - rotate_out <= (others => '0'); -- default - case rotate_cnt(1 downto 0) is - when "00" => rotate_out <= rotate_pixa; - when "01" => rotate_out <= rotate_pixb; - when "10" => rotate_out <= rotate_pixc; - when "11" => rotate_out <= rotate_pixd; - when others => null; - end case; - end process; - - p_flopper : process(shifter_out, rotate_out, r_magic) - variable flopper_src : std_logic_vector(7 downto 0); - begin - if (r_magic(2) = '0') then -- rotate bypass - flopper_src := shifter_out(13 downto 6); - else - flopper_src := rotate_out; - end if; - - if (r_magic(6) = '0') then -- flopper bypass - flopper_out <= flopper_src; - else - flopper_out(7 downto 6) <= flopper_src(1 downto 0); - flopper_out(5 downto 4) <= flopper_src(3 downto 2); - flopper_out(3 downto 2) <= flopper_src(5 downto 4); - flopper_out(1 downto 0) <= flopper_src(7 downto 6); - end if; - end process; - - p_or_xor : process(flopper_out, ram_ip_reg, r_magic) - variable result_or : std_logic_vector(7 downto 0); - variable result_xor : std_logic_vector(7 downto 0); - begin - result_or := flopper_out or ram_ip_reg; - result_xor := flopper_out xor ram_ip_reg; - - magic_final <= (others => '0'); - case r_magic(5 downto 4) is - when "00" => magic_final <= flopper_out; -- none - when "01" => magic_final <= result_or; -- or - when "10" => magic_final <= result_xor; -- xor - when "11" => magic_final <= result_xor; -- xor and or - when others => null; - end case; - end process; - - p_intercept : process(flopper_out, ram_ip_reg) - begin - pixel_collide <= (others => '0'); - for i in 0 to 3 loop - if (flopper_out((i*2)+1 downto (i*2)) /= "00") and - (ram_ip_reg((i*2)+1 downto (i*2)) /= "00") then - pixel_collide(i) <= '1'; - end if; - end loop; - - end process; - - p_intercept_reg : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (cpu_ena = '1') then - mxd_out_intercept_e1 <= mxd_out_intercept; - end if; - - -- reset - if (mxd_out_intercept = '0') and (mxd_out_intercept_e1 = '1') and (cpu_ena = '1') then -- end of read - r_intercept(3 downto 0) <= "0000"; - elsif (datwr = '1') and (I_MXA(15 downto 14) = "00") and (rotate_inhibit_write = '0') then - -- write - if (r_magic(5) = '1') or (r_magic(4) = '1') then -- or/xor write only - r_intercept(0) <= r_intercept(0) or pixel_collide(3); - r_intercept(1) <= r_intercept(1) or pixel_collide(2); - r_intercept(2) <= r_intercept(2) or pixel_collide(1); - r_intercept(3) <= r_intercept(3) or pixel_collide(0); - - r_intercept(4) <= pixel_collide(3); - r_intercept(5) <= pixel_collide(2); - r_intercept(6) <= pixel_collide(1); - r_intercept(7) <= pixel_collide(0); - end if; - end if; - end if; - end process; - - p_output_reg : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (cpu_ena = '1') then - ltchdo_t1 <= I_LTCHDO; - ram_ip_reg <= I_MD(7 downto 0); -- used for or / xor - end if; - - if (I_MXA(15 downto 14) = "00") then -- magic write - ram_op_reg <= magic_final; - else - ram_op_reg <= ram_write_reg; - end if; - - cpu_ena_t1 <= cpu_ena; - datwr <= cpu_ena_t1 and (not I_WRCTL_L); - end if; - end process; - O_DATWR <= datwr; - -- ram out - - p_ramout : process(I_WRCTL_L, ram_op_reg, rotate_inhibit_write) - begin - O_MD_OE_L <= '1'; - O_DATEN_L <= '1'; - O_MD <= (others => 'X'); -- debug - if (I_WRCTL_L = '0') and (rotate_inhibit_write = '0') then - O_MD <= ram_op_reg; - O_MD_OE_L <= '0'; - O_DATEN_L <= '0'; - end if; - end process; - - p_mxd_out_ena : process(I_LTCHDO, ltchdo_t1, I_RD_L, I_IORQ_L, cs_r, I_MXA) - begin - - mxd_out_ena <= '0'; - mxd_out_intercept <= '0'; - - if (I_LTCHDO = '1') or (ltchdo_t1 = '1') then - mxd_out_ena <= '1'; - else - if (I_RD_L = '0') and (I_IORQ_L = '0') and (cs_r = '1') then - if (I_MXA(3 downto 0) = x"8") then -- intercept - mxd_out_ena <= '1'; - mxd_out_intercept <= '1'; - end if; - end if; - end if; - end process; - - p_mxout : process(mxd_out_ena, mxd_out_intercept, I_MD, r_intercept) - begin - O_MXD <= (others => 'X'); - O_MXD_OE_L <= '1'; - if (mxd_out_ena = '1') then - O_MXD_OE_L <= '0'; - if (mxd_out_intercept = '1') then - O_MXD <= r_intercept; - else - O_MXD <= I_MD(7 downto 0); - end if; - end if; - end process; - -end architecture RTL; - diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_io.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/bally_io.vhd deleted file mode 100644 index ec96edcb..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_io.vhd +++ /dev/null @@ -1,405 +0,0 @@ --- --- A simulation model of Bally Astrocade hardware --- Copyright (c) MikeJ - Nov 2004 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 003 spartan3e release --- version 001 initial release --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity BALLY_IO is - port ( - I_MXA : in std_logic_vector(15 downto 0); - I_MXD : in std_logic_vector( 7 downto 0); - O_MXD : out std_logic_vector( 7 downto 0); - O_MXD_OE_L : out std_logic; - - -- cpu control signals - I_M1_L : in std_logic; -- not on real chip - I_RD_L : in std_logic; - I_IORQ_L : in std_logic; - I_RESET_L : in std_logic; - --- I_HANDLE1 : in std_logic_vector( 8 downto 0); --- I_HANDLE2 : in std_logic_vector( 8 downto 0); --- I_HANDLE3 : in std_logic_vector( 8 downto 0); --- I_HANDLE4 : in std_logic_vector( 8 downto 0); - - -- switches - O_SWITCH : out std_logic_vector( 7 downto 0); - I_SWITCH : in std_logic_vector( 7 downto 0); - -- audio - O_AUDIO : out std_logic_vector( 7 downto 0); - -- clks - I_CPU_ENA : in std_logic; - ENA : in std_logic; - CLK : in std_logic - ); -end; - -architecture RTL of BALLY_IO is - -- Signals - type array_8x8 is array (0 to 7) of std_logic_vector(7 downto 0); - type array_4x8 is array (0 to 3) of std_logic_vector(7 downto 0); - type array_3x8 is array (0 to 2) of std_logic_vector(7 downto 0); - type array_4x4 is array (0 to 3) of std_logic_vector(3 downto 0); - - type array_bool8 is array (0 to 7) of boolean; - - signal cs : std_logic; - signal snd_ld : array_bool8; - signal r_snd : array_8x8 := (x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00"); - signal r_pot : array_4x8 := (x"00",x"00",x"00",x"00"); - signal mxd_out_reg : std_logic_vector(7 downto 0); - - signal io_read : std_logic; - signal switch_read : std_logic; - -- audio - signal master_ena : std_logic; - signal master_cnt : std_logic_vector(7 downto 0); - signal master_freq : std_logic_vector(7 downto 0); - - signal vibrato_cnt : std_logic_vector(18 downto 0); - signal vibrato_ena : std_logic; - - signal poly17 : std_logic_vector(16 downto 0); - signal noise_gen : std_logic_vector(7 downto 0); - - signal tone_gen : array_3x8 := (others => (others => '0')); - signal tone_gen_op : std_logic_vector(2 downto 0); -begin - - p_chip_sel : process(I_CPU_ENA, I_MXA) - begin - cs <= '0'; - if (I_CPU_ENA = '1') then -- cpu access - if (I_MXA(7 downto 4) = "0001") then - cs <= '1'; - end if; - end if; - end process; - -- - -- registers - -- - p_reg_write_blk_decode : process(I_CPU_ENA, I_RD_L, I_M1_L, I_IORQ_L, cs, I_MXA) -- no m1 gating on real chip ? - begin - -- these writes will last for several cpu_ena cycles, so you - -- will get several load pulses - snd_ld <= (others => false); - if (I_CPU_ENA = '1') then - if (I_RD_L = '1') and (I_IORQ_L = '0') and (I_M1_L = '1') and (cs = '1') then - snd_ld(0) <= ( I_MXA( 3 downto 0) = x"0") or - ((I_MXA(10 downto 8) = "000") and (I_MXA(3 downto 0) = x"8")); - - snd_ld(1) <= ( I_MXA( 3 downto 0) = x"1") or - ((I_MXA(10 downto 8) = "001") and (I_MXA(3 downto 0) = x"8")); - - snd_ld(2) <= ( I_MXA( 3 downto 0) = x"2") or - ((I_MXA(10 downto 8) = "010") and (I_MXA(3 downto 0) = x"8")); - - snd_ld(3) <= ( I_MXA( 3 downto 0) = x"3") or - ((I_MXA(10 downto 8) = "011") and (I_MXA(3 downto 0) = x"8")); - - snd_ld(4) <= ( I_MXA( 3 downto 0) = x"4") or - ((I_MXA(10 downto 8) = "100") and (I_MXA(3 downto 0) = x"8")); - - snd_ld(5) <= ( I_MXA( 3 downto 0) = x"5") or - ((I_MXA(10 downto 8) = "101") and (I_MXA(3 downto 0) = x"8")); - - snd_ld(6) <= ( I_MXA( 3 downto 0) = x"6") or - ((I_MXA(10 downto 8) = "110") and (I_MXA(3 downto 0) = x"8")); - - snd_ld(7) <= ( I_MXA( 3 downto 0) = x"7") or - ((I_MXA(10 downto 8) = "111") and (I_MXA(3 downto 0) = x"8")); - - end if; - end if; - end process; - - p_reg_write_blk : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_RESET_L = '0') then -- don't know if reset does reset the sound - r_snd <= (others => (others => '0')); - else - for i in 0 to 7 loop - if snd_ld(i) then r_snd(i) <= I_MXD; end if; - end loop; - end if; - end if; - end process; - - p_reg_read : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_MXA(3) = '0') then - mxd_out_reg <= I_SWITCH(7 downto 0); - else - mxd_out_reg <= x"00"; - case I_MXA(2 downto 0) is - when "100" => mxd_out_reg <= r_pot(0); --x1C - when "101" => mxd_out_reg <= r_pot(1); --x1D - when "110" => mxd_out_reg <= r_pot(2); --x1E - when "111" => mxd_out_reg <= r_pot(3); --x1F - when others => null; - end case; - end if; - end if; - end process; - - p_decode_read : process(I_MXA, I_IORQ_L, I_RD_L) - begin - -- we will return 0 for x18-1b - io_read <= '0'; - switch_read <= '0'; - if (I_MXA(7 downto 4) = "0001") then - if (I_IORQ_L = '0') and (I_RD_L = '0') then - io_read <= '1'; - if (I_MXA(3) = '0') then - switch_read <= '1'; - end if; - end if; - end if; - end process; - - p_switch_out : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - O_SWITCH <= x"00"; - if (switch_read = '1') then - case I_MXA(2 downto 0) is - when "000" => O_SWITCH <= "00000001"; - when "001" => O_SWITCH <= "00000010"; - when "010" => O_SWITCH <= "00000100"; - when "011" => O_SWITCH <= "00001000"; - when "100" => O_SWITCH <= "00010000"; - when "101" => O_SWITCH <= "00100000"; - when "110" => O_SWITCH <= "01000000"; - when "111" => O_SWITCH <= "10000000"; - when others => null; - end case; - end if; - end if; - end process; - - p_mxd_oe : process(mxd_out_reg, io_read) - begin - O_MXD <= x"00"; - O_MXD_OE_L <= '1'; - if (io_read = '1') then - O_MXD <= mxd_out_reg; - O_MXD_OE_L <= '0'; - end if; - end process; - -- - - p_pots : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - -- return FF when not plugged in - r_pot(0) <= x"FF"; - r_pot(1) <= x"FF"; - r_pot(2) <= x"FF"; - r_pot(3) <= x"FF"; - end if; - end process; - -- read switches 10-17, pots 1c - 1f - -- port 7 6 5 4 3 2 1 0 - -- x10 tg rt lt dn up | player 1 - -- x11 tg rt lt dn up | player 2 - -- x12 tg rt lt dn up | player 3 - -- x13 tg rt lt dn up | player 4 - -- x14 = + - x / % | keypad (right most col, bit 0 top) - -- x15 . 3 6 9 ch v | keypad - -- x16 0 2 5 8 ms ^ | keypad - -- x17 ce 1 4 7 mr c | keypad (left most col) - - -- write - -- x10 master osc - -- x11 tone a freq - -- x12 tone b freq - -- x13 tone c freq - -- x14 vibrato (7..2 value, 1..0 freq) - -- x15 noise control, tone c volume - -- bit 5 high to enable noise into mix - -- bit 4 high for noise mod, low for vibrato - -- bit 3..0 tone c vol - -- x16 tone b volume, tone a volume (7..4 b vol, 3..0 a vol) - -- x17 noise volume (vol 7..4), 7..0 for master osc modulation - - p_noise_gen : process - variable poly17_zero : std_logic; - begin - -- most probably not correct polynomial - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_CPU_ENA = '1') then - poly17_zero := '0'; - if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; - poly17 <= poly17(15 downto 0) & (poly17(16) xor poly17(2) xor poly17_zero); - end if; - end if; - end process; - noise_gen <= poly17(7 downto 0); - - p_vibrato_osc : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - -- cpu clock period 0.558730s us - - -- 00 toggle output every 18.5 mS bet its 32768 clocks - -- 01 toggle output every 37 mS - -- 10 toggle output every 74 mS - -- 11 toggle output every 148 mS - - -- bit 15 every 32768 clocks - if (I_CPU_ENA = '1') then - vibrato_cnt <= vibrato_cnt + "1"; - vibrato_ena <= '0'; - case r_snd(4)(1 downto 0) is - when "00" => vibrato_ena <= vibrato_cnt(15); - when "01" => vibrato_ena <= vibrato_cnt(16); - when "10" => vibrato_ena <= vibrato_cnt(17); - when "11" => vibrato_ena <= vibrato_cnt(18); - when others => null; - end case; - end if; - end if; - end process; - - p_master_freq : process(vibrato_ena, r_snd, noise_gen) - variable mux : std_logic_vector(7 downto 0); - begin - mux := (others => '0'); -- default - if (r_snd(5)(4) = '1') then -- use noise - mux := noise_gen and r_snd(7); - else - if (vibrato_ena = '1') then - mux := r_snd(4)(7 downto 2) & "00"; - else - mux := (others => '0'); - end if; - end if; - -- add modulation to master osc freq - master_freq <= r_snd(0) + mux; - -- Arcadian mag claims that the counter is preset to the modulation value - -- when the counter hits the master osc reg value. - -- The patent / system descriptions describes an adder .... - end process; - - p_master_osc : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_CPU_ENA = '1') then -- 1.789 Mhz base clock - master_ena <= '0'; - if (master_cnt = "00000000") then - master_cnt <= master_freq; - master_ena <= '1'; - else - master_cnt <= master_cnt - "1"; - end if; - end if; - end if; - end process; - - p_tone_gen : process - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_CPU_ENA = '1') then -- 1.789 Mhz base clock - - for i in 0 to 2 loop - if (master_ena = '1') then - if (tone_gen(i) = "00000000") then - tone_gen(i) <= r_snd(i + 1); -- load - tone_gen_op(i) <= not tone_gen_op(i); - else - tone_gen(i) <= tone_gen(i) - '1'; - end if; - end if; - end loop; - end if; - end if; - end process; - - p_op_mixer : process - variable vol : array_4x4; - variable sum01 : std_logic_vector(4 downto 0); - variable sum23 : std_logic_vector(4 downto 0); - variable sum : std_logic_vector(5 downto 0); - begin - wait until rising_edge(CLK); - if (ENA = '1') then - if (I_CPU_ENA = '1') then - vol(0) := "0000"; - vol(1) := "0000"; - vol(2) := "0000"; - vol(3) := "0000"; - - if (tone_gen_op(0) = '1') then vol(0) := r_snd(6)(3 downto 0); end if; -- A - if (tone_gen_op(1) = '1') then vol(1) := r_snd(6)(7 downto 4); end if; -- B - if (tone_gen_op(2) = '1') then vol(2) := r_snd(5)(3 downto 0); end if; -- C - if (r_snd(5)(5) = '1') then -- noise enable - if (noise_gen(0) = '1') then vol(3) := r_snd(5)(7 downto 4); end if; -- noise - end if; - - sum01 := ('0' & vol(0)) + ('0' & vol(1)); - sum23 := ('0' & vol(2)) + ('0' & vol(3)); - sum := ('0' & sum01) + ('0' & sum23); - - if (I_RESET_L = '0') then - O_AUDIO <= "00000000"; - else - O_AUDIO <= (sum & "00"); - end if; - end if; - end if; - end process; - -end architecture RTL; - diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_mist.sv b/Console_MiST/Bally - Astrocade_MiST/rtl/bally_mist.sv deleted file mode 100644 index 7b7f45bb..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_mist.sv +++ /dev/null @@ -1,246 +0,0 @@ -module bally_mist( - output LED, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - input CLOCK_27 -); - -`include "rtl\build_id.v" - -localparam CONF_STR = { - "BALLY;BIN;", -// "O2,Check Cart, On, Off;", - "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", - "T6,Reset;", - "V,v1.00.",`BUILD_DATE -}; - -wire clk_28;//28.5712 -wire clk_14;//14.2856 -wire clk_7;//7.1428 -wire clk_1;//1.0204 -wire reset = status[0] | status[6] | buttons[1] | ioctl_downl; - -wire [12:0] cart_addr; -wire [7:0] cart_di, cart_do; -wire cart_cs; -wire ioctl_downl; -wire [7:0] ioctl_index; -wire ioctl_wr; -wire [24:0] ioctl_addr; -wire [7:0] ioctl_dout; -assign LED = !ioctl_downl; - -wire [31:0] status; -wire [1:0] buttons; -wire [1:0] switches; -wire [7:0] kbjoy; - -wire [7:0] joystick_0; -wire [7:0] joystick_1; -wire scandoubler_disable; -wire ypbpr; -wire ps2_kbd_clk, ps2_kbd_data; -wire [7:0] switch_col; -wire [7:0] switch_row; -wire [7:0] audio; - -wire pix_ena; -wire hs, vs; -wire [3:0] r,g,b; - -wire [15:0] exp_addr; -wire [7:0] exp_data_out; -wire [7:0] exp_data_in; -wire exp_oe_l; -wire exp_m1_l; -wire exp_mreq_l; -wire exp_iorq_l; -wire exp_wr_l; -wire exp_rd_l; - -wire [3:0] check_cart_msb; -wire [7:4] check_cart_lsb; - - -pll pll -( - .inclk0(CLOCK_27), - .c0(clk_28), - .c1(clk_14), - .c2(clk_7), - .c3(clk_1) - ); - -video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer -( - .clk_sys(clk_28), - .ce_pix(clk_7), - .ce_pix_actual(clk_7), - .SPI_SCK(SPI_SCK), - .SPI_SS3(SPI_SS3), - .SPI_DI(SPI_DI), - .R({r,r[1:0]}), - .G({g,g[1:0]}), - .B({b,b[1:0]}), - .HSync(hs), - .VSync(vs), - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .scandoubler_disable(scandoubler_disable), - .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), - .hq2x(status[4:3]==1), - .ypbpr_full(1), - .line_start(0), - .mono(0) -); - - -mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io -( - .clk_sys (clk_28 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable (scandoubler_disable ), - .ypbpr (ypbpr ), - .ps2_kbd_clk (ps2_kbd_clk ), - .ps2_kbd_data (ps2_kbd_data ), - .joystick_0 (joystick_0 ), - .joystick_1 (joystick_1 ), - .status (status ), - .ioctl_download ( ioctl_downl ), - .ioctl_index ( ioctl_index ), - .ioctl_wr ( ioctl_wr ), - .ioctl_addr ( ioctl_addr ), - .ioctl_dout ( ioctl_dout ) -); - - -cart cart ( - .clock ( clk_14 ), - .address ( ioctl_downl ? ioctl_addr : cart_addr), - .data ( ioctl_dout ), - .rden ( !ioctl_downl && !cart_cs), - .wren ( ioctl_downl && ioctl_wr), - .q ( cart_do ) - ); -/* -BALLY_TOP BALLY_TOP ( - .cas_addr(cart_addr), - .cas_data(cart_do), - .cas_cs_l(cart_cs), - .I_PS2_CLK (ps2_kbd_clk ), - .I_PS2_DATA (ps2_kbd_data ), - .r(r), - .g(g), - .b(b), - .hs(hs), - .vs(vs), - .AUDIO(audio), - .ena(1'b1), - .pix_ena(pix_ena), - .clk_14(clk_14), - .clk_7(clk_7), - .reset(reset) - );*/ - -BALLY_PS2_IF BALLY_PS2_IF ( - .I_PS2_CLK(ps2_kbd_clk), - .I_PS2_DATA(ps2_kbd_data), - .I_COL (switch_col), - .O_ROW (switch_row), - .I_RESET_L (~reset), - .I_1MHZ_ENA(clk_1), - .CLK (clk_7) - ); - -BALLY BALLY ( - .O_AUDIO(audio), - - .O_VIDEO_R(r), - .O_VIDEO_G(g), - .O_VIDEO_B(b), - - .O_HSYNC(hs), - .O_VSYNC(vs), - .O_COMP_SYNC_L(), - .O_FPSYNC(), - - .O_CAS_ADDR(cart_addr), - .O_CAS_DATA(), - .I_CAS_DATA(cart_do), - .O_CAS_CS_L(cart_cs), - - .O_EXP_ADDR(exp_addr), - .O_EXP_DATA(exp_data_out), - .I_EXP_DATA(exp_data_in), - .I_EXP_OE_L(exp_oe_l), - .O_EXP_M1_L(exp_m1_l), - .O_EXP_MREQ_L(exp_mreq_l), - .O_EXP_IORQ_L(exp_iorq_l), - .O_EXP_WR_L(exp_wr_l), - .O_EXP_RD_L(exp_rd_l), - - .O_SWITCH_COL(switch_col), - .I_SWITCH_ROW(switch_row), - - .I_RESET_L(~reset), - .ENA(1'b1), - .pix_ena(pix_ena), - .CLK(clk_14), - .CLK7(clk_7) - ); - -dac dac -( - .clk_i(clk_28), - .res_n_i(~reset), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -assign AUDIO_R = AUDIO_L; -/* -BALLY_CHECK_CART BALLY_CHECK_CART ( - .I_EXP_ADDR(exp_addr), - .I_EXP_DATA(exp_data_out), - .O_EXP_DATA(exp_data_in), - .O_EXP_OE_L(exp_oe_l), - .I_EXP_M1_L(exp_m1_l), - .I_EXP_MREQ_L(exp_mreq_l), - .I_EXP_IORQ_L(exp_iorq_l), - .I_EXP_WR_L(exp_wr_l), - .I_EXP_RD_L(exp_rd_l), - . O_CHAR_MSB(check_cart_msb), - .O_CHAR_LSB(check_cart_lsb), - .I_RESET_L(~reset), - .ENA(status[2]), - .CLK(clk_7) - );*/ - - -// if no expansion cart - assign exp_data_in = 8'hff; - assign exp_oe_l = 1'b1; - -endmodule diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_ps2_if.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/bally_ps2_if.vhd deleted file mode 100644 index 5212017e..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_ps2_if.vhd +++ /dev/null @@ -1,319 +0,0 @@ --- --- A simulation model of Bally Astrocade hardware --- Copyright (c) MikeJ - Nov 2004 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 003 spartan3e release --- version 001 initial release --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -entity BALLY_PS2_IF is - port ( - - I_PS2_CLK : in std_logic; - I_PS2_DATA : in std_logic; - - I_COL : in std_logic_vector(7 downto 0); - O_ROW : out std_logic_vector(7 downto 0); - - I_RESET_L : in std_logic; - I_1MHZ_ENA : in std_logic; - CLK : in std_logic - ); -end; - -architecture RTL of BALLY_PS2_IF is - - signal tick_1us : std_logic; - signal kbd_press : std_logic; - signal kbd_release : std_logic; - signal kbd_reset : std_logic; - signal kbd_press_s : std_logic; - signal kbd_release_s : std_logic; - signal kbd_scancode : std_logic_vector(7 downto 0); - signal kbd_scanE0 : std_logic; - - signal col_addr : std_logic_vector(3 downto 0); - signal rowcol : std_logic_vector(7 downto 0); - signal row_mask : std_logic_vector(7 downto 0); - - signal ram_w_addr : std_logic_vector(3 downto 0); - signal ram_r_addr : std_logic_vector(3 downto 0); - signal ram_we : std_ulogic; - signal ram_din : std_logic_vector(7 downto 0); - signal ram_dout : std_logic_vector(7 downto 0); - - signal reset_cnt : std_logic_vector(4 downto 0); - signal io_ena : std_logic; - -- non-xilinx ram - type slv_array8 is array (natural range <>) of std_logic_vector(7 downto 0); - shared variable ram : slv_array8(7 downto 0) := (others => (others => '0')); - -begin - - -- port 7 6 5 4 3 2 1 0 - -- x10 tg rt lt dn up | player 1 - -- x11 tg rt lt dn up | player 2 - -- x12 tg rt lt dn up | player 3 - -- x13 tg rt lt dn up | player 4 - - - -- bit x17 x16 x15 x14 maps to pc key - -- - -- 0 c ^ v % z a q 1 - -- 1 mr ms ch / x s w 2 - -- 2 7 8 9 x c d e 3 - -- 3 4 5 6 - v f r 4 - -- 4 1 2 3 + b g t 5 - -- 5 ce 0 . = n h y 6 - - tick_1us <= I_1MHZ_ENA; - - -- Keyboard decoder - u_kbd : entity work.ps2kbd - port map( - Rst_n => I_RESET_L, - Clk => CLK, - Tick1us => tick_1us, - PS2_Clk => I_PS2_CLK, - PS2_Data => I_PS2_DATA, - Press => kbd_press, - Release => kbd_release, - Reset => kbd_reset, - ScanE0 => kbd_scanE0, - ScanCode => kbd_scancode - ); - - p_decode_scancode : process - begin - -- hopefully the tools will build a rom for this - wait until rising_edge(CLK); - -- rowcol is valid for lots of clocks, but kbd_press_t1 / release are single - -- clock strobes. must sync these to io_ena - if (kbd_press = '1') then - kbd_press_s <= '1'; - elsif (io_ena = '0') then - kbd_press_s <= '0'; - end if; - - if (kbd_release = '1') then - kbd_release_s <= '1'; - elsif (io_ena = '0') then - kbd_release_s <= '0'; - end if; - - -- top bit low for keypress - if (kbd_scanE0 = '0') then - rowcol <= x"ff"; - case kbd_scancode is - -- player 1 col 0 - when x"29" => rowcol <= x"40";-- space - -- player 2 col 1 - when x"75" => rowcol <= x"01";-- keypad8 - when x"72" => rowcol <= x"11";-- keypad2 - when x"6B" => rowcol <= x"21";-- keypad4 - when x"74" => rowcol <= x"31";-- keypad6 - when x"70" => rowcol <= x"41";-- keypad0 - -- player 3 col 2 not mapped - -- player 4 col 3 not mapped - - -- keypad col 4 - when x"16" => rowcol <= x"04";-- 1 - when x"1E" => rowcol <= x"14";-- 2 - when x"26" => rowcol <= x"24";-- 3 - when x"25" => rowcol <= x"34";-- 4 - when x"2E" => rowcol <= x"44";-- 5 - when x"36" => rowcol <= x"54";-- 6 - -- keypad col 5 - when x"15" => rowcol <= x"05";-- q - when x"1D" => rowcol <= x"15";-- w - when x"24" => rowcol <= x"25";-- e - when x"2D" => rowcol <= x"35";-- r - when x"2C" => rowcol <= x"45";-- t - when x"35" => rowcol <= x"55";-- y - -- keypad col 6 - when x"1C" => rowcol <= x"06";-- a - when x"1B" => rowcol <= x"16";-- s - when x"23" => rowcol <= x"26";-- d - when x"2B" => rowcol <= x"36";-- f - when x"34" => rowcol <= x"46";-- g - when x"33" => rowcol <= x"56";-- h - -- keypad col 7 - when x"1A" => rowcol <= x"07";-- z - when x"22" => rowcol <= x"17";-- x - when x"21" => rowcol <= x"27";-- c - when x"2A" => rowcol <= x"37";-- v - when x"32" => rowcol <= x"47";-- b - when x"31" => rowcol <= x"57";-- n - - when others => rowcol <= x"FF"; - end case; - else - rowcol <= x"ff"; - case kbd_scancode is - when x"75" => rowcol <= x"00";-- curs up - when x"72" => rowcol <= x"10";-- curs dn - when x"6B" => rowcol <= x"20";-- curs left - when x"74" => rowcol <= x"30";-- curs right - when others => rowcol <= x"FF"; - end case; - end if; - end process; - - p_expand_row : process(rowcol) - begin - row_mask <= x"01"; - case rowcol(6 downto 4) is - when "000" => row_mask <= x"01"; - when "001" => row_mask <= x"02"; - when "010" => row_mask <= x"04"; - when "011" => row_mask <= x"08"; - when "100" => row_mask <= x"10"; - when "101" => row_mask <= x"20"; - when "110" => row_mask <= x"40"; - when "111" => row_mask <= x"80"; - when others => null; - end case; - end process; - - p_reset_cnt : process(I_RESET_L, CLK) - begin - if (I_RESET_L = '0') then - reset_cnt <= "00000"; - io_ena <= '0'; - elsif rising_edge(CLK) then - -- counter used to reset ram - if (kbd_reset = '1') then - reset_cnt <= "10000"; - elsif (reset_cnt(4) = '1') then - reset_cnt <= reset_cnt + "1"; - end if; - io_ena <= not io_ena; - end if; - end process; - - p_keybd_write : process(kbd_press_s, kbd_release_s, rowcol, - kbd_reset, reset_cnt, ram_dout, row_mask, io_ena) - variable we : boolean; - begin - -- valid key ? - we := ((kbd_press_s = '1') or (kbd_release_s = '1')) and (rowcol(7) = '0'); - - if (reset_cnt(4) = '1') then - ram_w_addr <= reset_cnt(3 downto 0); - ram_din <= x"00"; - ram_we <= '1'; - else - ram_w_addr <= rowcol(3 downto 0); - - if (kbd_press_s = '1') then - ram_din <= ram_dout or row_mask; -- pressed - else - ram_din <= ram_dout and not row_mask; -- released - end if; - - ram_we <= '0'; - if we and (io_ena = '0')then - ram_we <= '1'; - end if; - end if; - - end process; - - - p_ram_w : process - variable ram_addr : integer := 0; - begin - wait until rising_edge(CLK); - if (ram_we = '1') then - ram_addr := to_integer(unsigned(ram_w_addr(2 downto 0))); - ram(ram_addr) := ram_din; - end if; - end process; - - p_ram_r : process(CLK, ram_r_addr) - variable ram_addr : integer := 0; - begin - ram_addr := to_integer(unsigned(ram_r_addr(2 downto 0))); - ram_dout <= ram(ram_addr); - end process; - - -- the io chip can access the ram when io_ena = '1' - p_ram_read_mux : process(io_ena, col_addr, rowcol) - begin - if (io_ena = '1') then - ram_r_addr <= col_addr; - else - ram_r_addr <= rowcol(3 downto 0); -- write r/m/w - end if; - end process; - - p_via_out_reg : process - begin - wait until rising_edge(CLK); - if (io_ena = '1') then - if (col_addr = x"f") then -- none - O_ROW <= x"00"; - else - O_ROW <= ram_dout; -- switches are active high - end if; - end if; - end process; - - p_col_decode : process(I_COL) - begin - col_addr <= x"F"; - case I_COL is - when x"01" => col_addr <= x"0"; - when x"02" => col_addr <= x"1"; - when x"04" => col_addr <= x"2"; - when x"08" => col_addr <= x"3"; - when x"10" => col_addr <= x"4"; - when x"20" => col_addr <= x"5"; - when x"40" => col_addr <= x"6"; - when x"80" => col_addr <= x"7"; - when others => null; - end case; - end process; - -end architecture RTL; - diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_rams.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/bally_rams.vhd deleted file mode 100644 index 6a583635..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_rams.vhd +++ /dev/null @@ -1,178 +0,0 @@ --- --- A simulation model of Bally Astrocade hardware --- Copyright (c) MikeJ - Nov 2004 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 004 spartan3e hires release --- version 003 spartan3e release --- version 001 initial release --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity BALLY_RAMS is - port ( - ADDR : in std_logic_vector(15 downto 0); - DIN : in std_logic_vector(7 downto 0); - DOUT : out std_logic_vector(7 downto 0); - DOUTX : out std_logic_vector(7 downto 0); -- next byte - WE : in std_logic; - WE_ENA_L : in std_logic; -- used for write enable gate only - ENA : in std_logic; - CLK : in std_logic - ); -end; - -architecture RTL of BALLY_RAMS is - type array_7x8 is array (0 to 6) of std_logic_vector(7 downto 0); - -- - signal dout_int_h : array_7x8; - signal dout_int_l : array_7x8; - signal addr_t1 : std_logic_vector(15 downto 0); - signal int_we_h : std_logic_vector(6 downto 0); - signal int_we_l : std_logic_vector(6 downto 0); - --- we can have 14 rams total --- 4000-4FFF 4K - --- 16K screen ram 4000-7fff this is aliased to 0000-3FFF for magic --- spare 8000-BFFF (but we are only have enough rams to go to AFFF for now) -begin - p_we : process(ADDR, WE, WE_ENA_L) - variable h,l : std_logic; - begin - int_we_h <= (others => '0'); - int_we_l <= (others => '0'); - l := (not ADDR(0)) and WE and (not WE_ENA_L); - h := ADDR(0) and WE and (not WE_ENA_L); - -- - case ADDR(15 downto 12) is - when x"0" => int_we_h(0) <= h; int_we_l(0) <= l; - when x"1" => int_we_h(1) <= h; int_we_l(1) <= l; - when x"2" => int_we_h(2) <= h; int_we_l(2) <= l; - when x"3" => int_we_h(3) <= h; int_we_l(3) <= l; - -- - when x"4" => int_we_h(0) <= h; int_we_l(0) <= l; - when x"5" => int_we_h(1) <= h; int_we_l(1) <= l; - when x"6" => int_we_h(2) <= h; int_we_l(2) <= l; - when x"7" => int_we_h(3) <= h; int_we_l(3) <= l; - -- - when x"8" => int_we_h(4) <= h; int_we_l(4) <= l; - when x"9" => int_we_h(5) <= h; int_we_l(5) <= l; - when x"A" => int_we_h(6) <= h; int_we_l(6) <= l; - --when x"B" => int_we_h(7) <= h; int_we_l(7) <= l; - -- - when others => null; - end case; - end process; - - - - rams : for i in 0 to 6 generate - begin - ram_u : entity work.spram - generic map ( - init_file => "", - widthad_a => 11, - width_a => 8 - ) - port map ( - address => ADDR(11 downto 1), - clock => CLK, - data => DIN(7 downto 0), - wren => int_we_h(i), - q => dout_int_h(i)(7 downto 0) - ); - ram_l : entity work.spram - generic map ( - init_file => "", - widthad_a => 11, - width_a => 8 - ) - port map ( - address => ADDR(11 downto 1), - clock => CLK, - data => DIN(7 downto 0), - wren => int_we_l(i), - q => dout_int_l(i)(7 downto 0) - ); - end generate; - - p_addr_delay : process - begin - wait until rising_edge(CLK); - addr_t1 <= ADDR; - end process; - - p_mux : process(dout_int_l, dout_int_h, addr, addr_t1) - variable mux_h : std_logic_vector(7 downto 0); - variable mux_l : std_logic_vector(7 downto 0); - begin - - mux_h := dout_int_h(0); mux_l := dout_int_l(0); - case addr_t1(15 downto 12) is - when x"0" => mux_h := dout_int_h(0); mux_l := dout_int_l(0); - when x"1" => mux_h := dout_int_h(1); mux_l := dout_int_l(1); - when x"2" => mux_h := dout_int_h(2); mux_l := dout_int_l(2); - when x"3" => mux_h := dout_int_h(3); mux_l := dout_int_l(3); - -- - when x"4" => mux_h := dout_int_h(0); mux_l := dout_int_l(0); - when x"5" => mux_h := dout_int_h(1); mux_l := dout_int_l(1); - when x"6" => mux_h := dout_int_h(2); mux_l := dout_int_l(2); - when x"7" => mux_h := dout_int_h(3); mux_l := dout_int_l(3); - -- - when x"8" => mux_h := dout_int_h(4); mux_l := dout_int_l(4); - when x"9" => mux_h := dout_int_h(5); mux_l := dout_int_l(5); - when x"A" => mux_h := dout_int_h(6); mux_l := dout_int_l(6); - --when x"B" => mux_h := dout_int_h(7); mux_l := dout_int_l(7); - -- - when others => null; - end case; - - if (addr_t1(0) = '0') then - DOUT <= mux_l; - else - DOUT <= mux_h; - end if; - DOUTX <= mux_h; - - end process; - -end architecture RTL; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_top.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/bally_top.vhd deleted file mode 100644 index 29ed228a..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/bally_top.vhd +++ /dev/null @@ -1,199 +0,0 @@ --- --- A simulation model of Bally Astrocade hardware --- Copyright (c) MikeJ - Nov 2004 --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- You are responsible for any legal issues arising from your use of this code. --- --- The latest version of this file can be found at: www.fpgaarcade.com --- --- Email support@fpgaarcade.com --- --- Revision list --- --- version 004 spartan3e hires release --- version 003 spartan3e release --- version 001 initial release --- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; - use ieee.std_logic_unsigned.all; - -entity BALLY_TOP is - port ( - cas_addr : out std_logic_vector(12 downto 0); - cas_data : in std_logic_vector( 7 downto 0); - cas_cs_l : out std_logic; - I_PS2_CLK : in std_logic; - I_PS2_DATA : in std_logic; - r : out std_logic_vector(3 downto 0); - g : out std_logic_vector(3 downto 0); - b : out std_logic_vector(3 downto 0); - hs : out std_logic; - vs : out std_logic; - audio : out std_logic_vector( 7 downto 0); - ena : in std_logic; - pix_ena : out std_logic; - clk_14 : in std_logic; - clk_7 : in std_logic; - reset : in std_logic - ); -end; - -architecture RTL of BALLY_TOP is - - -- - signal switch_col : std_logic_vector(7 downto 0); - signal switch_row : std_logic_vector(7 downto 0); - signal ps2_1mhz_ena : std_logic; - signal ps2_1mhz_cnt : std_logic_vector(5 downto 0); - -- - signal video_r : std_logic_vector(3 downto 0); - signal video_g : std_logic_vector(3 downto 0); - signal video_b : std_logic_vector(3 downto 0); - signal hsync : std_logic; - signal vsync : std_logic; - signal fpsync : std_logic; - - - signal exp_addr : std_logic_vector(15 downto 0); - signal exp_data_out : std_logic_vector(7 downto 0); - signal exp_data_in : std_logic_vector(7 downto 0); - signal exp_oe_l : std_logic; - - signal exp_m1_l : std_logic; - signal exp_mreq_l : std_logic; - signal exp_iorq_l : std_logic; - signal exp_wr_l : std_logic; - signal exp_rd_l : std_logic; - -- - signal check_cart_msb : std_logic_vector(3 downto 0); - signal check_cart_lsb : std_logic_vector(7 downto 4); - - -begin - - - p_ena1mhz : process - begin - wait until rising_edge(clk_7); - -- divide by 7 - ps2_1mhz_ena <= '0'; - if (ps2_1mhz_cnt = "000110") then - ps2_1mhz_cnt <= "000000"; - ps2_1mhz_ena <= '1'; - else - ps2_1mhz_cnt <= ps2_1mhz_cnt + '1'; - end if; - end process; - - - u_bally : entity work.BALLY - port map ( - O_AUDIO => audio, - -- - O_VIDEO_R => r, - O_VIDEO_G => g, - O_VIDEO_B => b, - - O_HSYNC => hs, - O_VSYNC => vs, - O_COMP_SYNC_L => open, - O_FPSYNC => open, - -- - -- cart slot - O_CAS_ADDR => cas_addr, - O_CAS_DATA => open, - I_CAS_DATA => cas_data, - O_CAS_CS_L => cas_cs_l, - - -- exp slot (subset for now) - O_EXP_ADDR => exp_addr, - O_EXP_DATA => exp_data_out, - I_EXP_DATA => exp_data_in, - I_EXP_OE_L => exp_oe_l, - - O_EXP_M1_L => exp_m1_l, - O_EXP_MREQ_L => exp_mreq_l, - O_EXP_IORQ_L => exp_iorq_l, - O_EXP_WR_L => exp_wr_l, - O_EXP_RD_L => exp_rd_l, - -- - O_SWITCH_COL => switch_col, - I_SWITCH_ROW => switch_row, - I_RESET_L => not reset, - ENA => ena, - pix_ena => pix_ena, - CLK => clk_14, - CLK7 => clk_7 - ); - - u_ps2 : entity work.BALLY_PS2_IF - port map ( - - I_PS2_CLK => I_PS2_CLK, - I_PS2_DATA => I_PS2_DATA, - - I_COL => switch_col, - O_ROW => switch_row, - - I_RESET_L => not reset, - I_1MHZ_ENA => ps2_1mhz_ena, - CLK => clk_7 - ); - --- u_check_cart : entity work.BALLY_CHECK_CART --- port map ( - -- I_EXP_ADDR => exp_addr, - -- I_EXP_DATA => exp_data_out, - -- O_EXP_DATA => exp_data_in, - -- O_EXP_OE_L => exp_oe_l, - --- I_EXP_M1_L => exp_m1_l, - -- I_EXP_MREQ_L => exp_mreq_l, - -- I_EXP_IORQ_L => exp_iorq_l, - -- I_EXP_WR_L => exp_wr_l, - -- I_EXP_RD_L => exp_rd_l, - ---- --- O_CHAR_MSB => check_cart_msb, - -- O_CHAR_LSB => check_cart_lsb, - ---- - -- I_RESET_L => not reset, - -- ENA => ena, - -- CLK => clk_7 - -- ); - - -- if no expansion cart - exp_data_in <= x"ff"; - exp_oe_l <= '1'; - - -end RTL; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/build_id.tcl b/Console_MiST/Bally - Astrocade_MiST/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/build_id.v b/Console_MiST/Bally - Astrocade_MiST/rtl/build_id.v deleted file mode 100644 index 12e39796..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/build_id.v +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "180725" -`define BUILD_TIME "170812" diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/cart.qip b/Console_MiST/Bally - Astrocade_MiST/rtl/cart.qip deleted file mode 100644 index 8607b3bf..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/cart.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.0" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cart.v"] diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/cart.v b/Console_MiST/Bally - Astrocade_MiST/rtl/cart.v deleted file mode 100644 index f4a633e7..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/cart.v +++ /dev/null @@ -1,177 +0,0 @@ -// megafunction wizard: %RAM: 1-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: cart.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version -// ************************************************************ - - -//Copyright (C) 1991-2013 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module cart ( - address, - clock, - data, - rden, - wren, - q); - - input [12:0] address; - input clock; - input [7:0] data; - input rden; - input wren; - output [7:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clock; - tri1 rden; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] q = sub_wire0[7:0]; - - altsyncram altsyncram_component ( - .address_a (address), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .rden_a (rden), - .q_a (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .address_b (1'b1), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b (1'b1), - .eccstatus (), - .q_b (), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 8192, - altsyncram_component.operation_mode = "SINGLE_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_reg_a = "CLOCK0", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 13, - altsyncram_component.width_a = 8, - altsyncram_component.width_byteena_a = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -// Retrieval info: PRIVATE: AclrByte NUMERIC "0" -// Retrieval info: PRIVATE: AclrData NUMERIC "0" -// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: Clken NUMERIC "0" -// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -// Retrieval info: PRIVATE: RegAddr NUMERIC "1" -// Retrieval info: PRIVATE: RegData NUMERIC "1" -// Retrieval info: PRIVATE: RegOutput NUMERIC "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: SingleClock NUMERIC "1" -// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" -// Retrieval info: PRIVATE: WidthData NUMERIC "8" -// Retrieval info: PRIVATE: rden NUMERIC "1" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" -// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 -// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL cart.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/dac.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/dac.vhd deleted file mode 100644 index c133f074..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2006/05/10 20:57:06 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 3k3 | --- === 4n7 --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 7 - ); - port ( - clk_i : in std_logic; - res_n_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end dac; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_n_i) - begin - if res_n_i = '0' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end rtl; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/hq2x.sv b/Console_MiST/Bally - Astrocade_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/mist_io.v b/Console_MiST/Bally - Astrocade_MiST/rtl/mist_io.v deleted file mode 100644 index ad233a3b..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/mist_io.v +++ /dev/null @@ -1,491 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoubler_disable, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input sd_rd, - input sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - input ps2_caps_led, - - // ARM -> FPGA download - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output ioctl_wr, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] b_data; -reg [6:0] sbuf; -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; -assign ypbpr = but_sw[5]; - -wire [7:0] spi_dout = { sbuf, SPI_DI}; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; - -// drive MISO only when transmitting core id -always@(negedge SPI_SCK) begin - if(!CONF_DATA0) begin - // first byte returned is always core type, further bytes are - // command dependent - if(byte_cnt == 0) begin - spi_do <= core_type[~bit_cnt]; - - end else begin - case(cmd) - // reading config string - 8'h14: begin - // returning a byte from string - if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; - else spi_do <= 0; - end - - // reading sd card status - 8'h16: begin - if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; - else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; - else spi_do <= 0; - end - - // reading sd card write data - 8'h18: - spi_do <= b_data[~bit_cnt]; - - // reading keyboard LED status - 8'h1f: - spi_do <= kbd_led[~bit_cnt]; - - default: - spi_do <= 0; - endcase - end - end -end - -reg b_wr2,b_wr3; -always @(negedge clk_sys) begin - b_wr3 <= b_wr2; - sd_buff_wr <= b_wr3; -end - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - - if(CONF_DATA0) begin - b_wr2 <= 0; - bit_cnt <= 0; - byte_cnt <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - end else begin - b_wr2 <= 0; - - sbuf <= spi_dout[6:0]; - bit_cnt <= bit_cnt + 1'd1; - if(bit_cnt == 5) begin - if (byte_cnt == 0) sd_buff_addr <= 0; - if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; - if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; - end - - // finished reading command byte - if(bit_cnt == 7) begin - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - if(byte_cnt == 0) begin - cmd <= spi_dout; - - if(spi_dout == 8'h19) begin - sd_ack_conf <= 1; - sd_buff_addr <= 0; - end - if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin - sd_ack <= 1; - sd_buff_addr <= 0; - end - if(spi_dout == 8'h18) b_data <= sd_buff_din; - - mount_strobe <= 0; - - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_dout; - 8'h02: joystick_0 <= spi_dout; - 8'h03: joystick_1 <= spi_dout; - - // store incoming ps2 mouse bytes - 8'h04: begin - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_dout; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_dout; - b_wr2 <= 1; - end - - 8'h18: b_data <= sd_buff_din; - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; - else if(byte_cnt == 2) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; - end else if(byte_cnt == 3) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; - end - end - - // notify image selection - 8'h1c: mount_strobe <= 1; - - // send image info - 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; - - // status, 32bit version - 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; - default: ; - endcase - end - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - rclk <= 0; - - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // increase target address after write - if(rclk) addr <= addr + 1'd1; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - addr <= 0; - ioctl_download <= 1; - end else begin - addr_w <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - rclk <= 1; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -assign ioctl_wr = |ioctl_wrd; -reg [1:0] ioctl_wrd; - -always@(negedge clk_sys) begin - reg rclkD, rclkD2; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wrd<= {ioctl_wrd[0],1'b0}; - - if(rclkD & ~rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wrd <= 2'b11; - end -end - -endmodule diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/osd.v b/Console_MiST/Bally - Astrocade_MiST/rtl/osd.v deleted file mode 100644 index c62c10af..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/osd.v +++ /dev/null @@ -1,179 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [7:0] osd_byte; -always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; - -wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/pll.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/pll.vhd deleted file mode 100644 index 6e93a0d3..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/pll.vhd +++ /dev/null @@ -1,446 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 52, - clk0_duty_cycle => 50, - clk0_multiply_by => 55, - clk0_phase_shift => "0", - clk1_divide_by => 104, - clk1_duty_cycle => 50, - clk1_multiply_by => 55, - clk1_phase_shift => "0", - clk2_divide_by => 208, - clk2_duty_cycle => 50, - clk2_multiply_by => 55, - clk2_phase_shift => "0", - clk3_divide_by => 1456, - clk3_duty_cycle => 50, - clk3_multiply_by => 55, - clk3_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 37037, - intended_device_family => "Cyclone III", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "52" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "208" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1456" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.557692" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.278846" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "7.139423" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "1.019918" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "55" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "55" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "55" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "55" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.57120000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.28560000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "7.14280000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "1.02040000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "52" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "55" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "104" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "55" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "208" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "55" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1456" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "55" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/ps2kbd.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/ps2kbd.vhd deleted file mode 100644 index 028989f8..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/ps2kbd.vhd +++ /dev/null @@ -1,212 +0,0 @@ --- --- PS/2 serial port, input only --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0242 : First release --- extended key handling added by MIKEJ --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity ps2kbd is - port( - Rst_n : in std_logic; - Clk : in std_logic; - Tick1us : in std_logic; - PS2_Clk : in std_logic; - PS2_Data : in std_logic; - Press : out std_logic; - Release : out std_logic; - Reset : out std_logic; - ScanE0 : out std_logic; - ScanCode : out std_logic_vector(7 downto 0)); -end ps2kbd; - -architecture rtl of ps2kbd is - - signal PS2_Sample : std_logic; - signal PS2_Data_s : std_logic; - - signal RX_Bit_Cnt : unsigned(3 downto 0); - signal RX_Byte : unsigned(2 downto 0); - signal RX_ShiftReg : std_logic_vector(7 downto 0); - signal RX_Release : std_logic; - signal RX_Received : std_logic; - signal RX_E0 : std_logic; - -begin - - ScanCode <= RX_ShiftReg; - - process (Clk, Rst_n) - variable PS2_Data_r : std_logic_vector(1 downto 0); - variable PS2_Clk_r : std_logic_vector(1 downto 0); - variable PS2_Clk_State : std_logic; - begin - if Rst_n = '0' then - PS2_Sample <= '0'; - PS2_Data_s <= '0'; - PS2_Data_r := "11"; - PS2_Clk_r := "11"; - PS2_Clk_State := '1'; - elsif Clk'event and Clk = '1' then - if Tick1us = '1' then - PS2_Sample <= '0'; - - -- Deglitch - if PS2_Data_r = "00" then - PS2_Data_s <= '0'; - end if; - if PS2_Data_r = "11" then - PS2_Data_s <= '1'; - end if; - if PS2_Clk_r = "00" then - if PS2_Clk_State = '1' then - PS2_Sample <= '1'; - end if; - PS2_Clk_State := '0'; - end if; - if PS2_Clk_r = "11" then - PS2_Clk_State := '1'; - end if; - - -- Double synchronise - PS2_Data_r(1) := PS2_Data_r(0); - PS2_Clk_r(1) := PS2_Clk_r(0); - PS2_Data_r(0) := PS2_Data; - PS2_Clk_r(0) := PS2_Clk; - end if; - end if; - end process; - - process (Clk, Rst_n) - variable Cnt : integer; - begin - if Rst_n = '0' then - RX_Bit_Cnt <= (others => '0'); - RX_ShiftReg <= (others => '0'); - RX_Received <= '0'; - Cnt := 0; - elsif Clk'event and Clk = '1' then - RX_Received <= '0'; - if Tick1us = '1' then - - if PS2_Sample = '1' then - if RX_Bit_Cnt = "0000" then - if PS2_Data_s = '0' then -- Start bit - RX_Bit_Cnt <= RX_Bit_Cnt + 1; - end if; - elsif RX_Bit_Cnt = "1001" then -- Parity bit - RX_Bit_Cnt <= RX_Bit_Cnt + 1; - -- Ignoring parity - elsif RX_Bit_Cnt = "1010" then -- Stop bit - if PS2_Data_s = '1' then - RX_Received <= '1'; - end if; - RX_Bit_Cnt <= "0000"; - else - RX_Bit_Cnt <= RX_Bit_Cnt + 1; - RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1); - RX_ShiftReg(7) <= PS2_Data_s; - end if; - end if; - - -- TimeOut - if PS2_Sample = '1' then - Cnt := 0; - elsif Cnt = 127 then - RX_Bit_Cnt <= "0000"; - Cnt := 0; - else - Cnt := Cnt + 1; - end if; - end if; - end if; - end process; - - process (Clk, Rst_n) - begin - if Rst_n = '0' then - Press <= '0'; - Release <= '0'; - Reset <= '0'; - RX_Byte <= (others => '0'); - RX_Release <= '0'; - ScanE0 <= '0'; - RX_E0 <= '0'; - elsif Clk'event and Clk = '1' then - Press <= '0'; - Release <= '0'; - Reset <= '0'; - if RX_Received = '1' then - RX_Byte <= RX_Byte + 1; - if RX_ShiftReg = x"F0" then - RX_Release <= '1'; - elsif RX_ShiftReg = x"E0" then - RX_E0 <= '1'; - else - ScanE0 <= RX_E0; - RX_E0 <= '0'; - - RX_Release <= '0'; - -- Normal key press - if RX_Release = '0' then - Press <= '1'; - end if; - -- Normal key release - if RX_Release = '1' then - Release <= '1'; - end if; - end if; - if RX_ShiftReg = x"aa" then - Reset <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/BIOS3159.BIN b/Console_MiST/Bally - Astrocade_MiST/rtl/roms/BIOS3159.BIN deleted file mode 100644 index 9b587b7a..00000000 Binary files a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/BIOS3159.BIN and /dev/null differ diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/balcheck.bin b/Console_MiST/Bally - Astrocade_MiST/rtl/roms/balcheck.bin deleted file mode 100644 index 97ea951c..00000000 Binary files a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/balcheck.bin and /dev/null differ diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/balcheck.hex b/Console_MiST/Bally - Astrocade_MiST/rtl/roms/balcheck.hex deleted file mode 100644 index 8799da19..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/balcheck.hex +++ /dev/null @@ -1,129 +0,0 @@ -:10000000C3AD2087878787C92F0F0F2F0055AAFF01 -:10001000282777271620F308DB15A72029DB16A74A -:100020002030DB17A7200FDB14A72836FE01CA27D4 -:1000300026FE02CABA27FE01CAD925FE02CA4F26E9 -:10004000FE102818181CFE01CA1126FE02CA4827F5 -:100050001810FE01CAEA25FE02CA7326D979E60FF6 -:100060004FD9D9147AFE3C20401600CB4320117999 -:10007000FE8420043EB1180978A720053EA018018F -:10008000AFD3FF1C7BFE3C20201E00247CFE3C20C6 -:100090001826002C7DCD0320FEA0200478C606473C -:1000A0000478FE992003AF476FD908FBC9F3D9AF95 -:1000B000470E81575F676FD93EAAD3FF3E00D30832 -:1000C0003EC8D30AAF0E14ED78A720080C79FE18AD -:1000D000280918F31E0121EF23186CFD21E220C32B -:1000E000642118044E50004F31C84F3E08D30E21F2 -:1000F00014207CED477DD30DAFD30FED5EFB1601D1 -:10010000CDCF25F3D97AA7200E7BA7200AD91E02CE -:100110000EFF21EF2318300E80D9FB0100202100B3 -:1001200000AF8657230D20FA0520F77AFEA4200A97 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Astrocade_MiST/rtl/roms/bally_bios_0.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bally_bios_0.vhd deleted file mode 100644 index a9e484ff..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bally_bios_0.vhd +++ /dev/null @@ -1,493 +0,0 @@ --- generated with romgen v3.0 by MikeJ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -library UNISIM; - use UNISIM.Vcomponents.all; - -entity BALLY_BIOS_0 is - port ( - CLK : in std_logic; - ENA : in std_logic; - ADDR : in std_logic_vector(11 downto 0); - DATA : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of BALLY_BIOS_0 is - - function romgen_str2bv (str : string) return bit_vector is - variable result : bit_vector (str'length*4-1 downto 0); - begin - for i in 0 to str'length-1 loop - case str(str'high-i) is - when '0' => result(i*4+3 downto i*4) := x"0"; - when '1' => result(i*4+3 downto i*4) := x"1"; - when '2' => result(i*4+3 downto i*4) := x"2"; - when '3' => result(i*4+3 downto i*4) := x"3"; - when '4' => result(i*4+3 downto i*4) := x"4"; - when '5' => result(i*4+3 downto i*4) := x"5"; - when '6' => result(i*4+3 downto i*4) := x"6"; - when '7' => result(i*4+3 downto i*4) := x"7"; - when '8' => result(i*4+3 downto i*4) := x"8"; - when '9' => result(i*4+3 downto i*4) := x"9"; - when 'A' => result(i*4+3 downto i*4) := x"A"; - when 'B' => result(i*4+3 downto i*4) := x"B"; - when 'C' => result(i*4+3 downto i*4) := x"C"; - when 'D' => result(i*4+3 downto i*4) := x"D"; - when 'E' => result(i*4+3 downto i*4) := x"E"; - when 'F' => result(i*4+3 downto i*4) := x"F"; - when others => null; - end case; - end loop; - return result; - end romgen_str2bv; - - attribute INIT_00 : string; - attribute INIT_01 : string; - attribute INIT_02 : string; - attribute INIT_03 : string; - attribute INIT_04 : string; - attribute INIT_05 : string; - attribute INIT_06 : string; - attribute INIT_07 : string; - attribute INIT_08 : string; - attribute INIT_09 : string; - attribute INIT_0A : string; - attribute INIT_0B : string; - attribute INIT_0C : string; - attribute INIT_0D : string; - attribute INIT_0E : string; - attribute INIT_0F : string; - attribute INIT_10 : string; - attribute INIT_11 : string; - attribute INIT_12 : string; - attribute INIT_13 : string; - attribute INIT_14 : string; - attribute INIT_15 : string; - attribute INIT_16 : string; - attribute INIT_17 : string; - attribute INIT_18 : string; - attribute INIT_19 : string; - attribute INIT_1A : string; - attribute INIT_1B : string; - attribute INIT_1C : string; - attribute INIT_1D : string; - attribute INIT_1E : string; - attribute INIT_1F : string; - attribute INIT_20 : string; - attribute INIT_21 : string; - attribute INIT_22 : string; - attribute INIT_23 : string; - attribute INIT_24 : string; - attribute INIT_25 : string; - attribute INIT_26 : string; - attribute INIT_27 : string; - attribute INIT_28 : string; - attribute INIT_29 : string; - attribute INIT_2A : string; - attribute INIT_2B : string; - attribute INIT_2C : string; - attribute INIT_2D : string; - attribute INIT_2E : string; - attribute INIT_2F : string; - attribute INIT_30 : string; - attribute INIT_31 : string; - attribute INIT_32 : string; - attribute INIT_33 : string; - attribute INIT_34 : string; - attribute INIT_35 : string; - attribute INIT_36 : string; - attribute INIT_37 : string; - attribute INIT_38 : string; - attribute INIT_39 : string; - attribute INIT_3A : string; - attribute INIT_3B : string; - attribute INIT_3C : string; - attribute INIT_3D : string; - attribute INIT_3E : string; - attribute INIT_3F : string; - - component RAMB16_S4 - --pragma translate_off - generic ( - INIT_00 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_10 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_11 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_12 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_13 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_14 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_15 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_16 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_17 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_18 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_19 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_20 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_21 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_22 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_23 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_24 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_25 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_26 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_27 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_28 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_29 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_30 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_31 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_32 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_33 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_34 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_35 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_36 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_37 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_38 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_39 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DO : out std_logic_vector (3 downto 0); - ADDR : in std_logic_vector (11 downto 0); - CLK : in std_logic; - DI : in std_logic_vector (3 downto 0); - EN : in std_logic; - SSR : in std_logic; - WE : in std_logic - ); - end component; - - signal rom_addr : std_logic_vector(11 downto 0); - -begin - - p_addr : process(ADDR) - begin - rom_addr <= (others => '0'); - rom_addr(11 downto 0) <= ADDR; - end process; - - rom0 : if true generate - attribute INIT_00 of inst : label is "5D5D5553F11B0063F9001033F92330039D06B0D3F27A60A3F0CCC073C1383F30"; - attribute INIT_01 of inst : label is "B3E1194ED56D9ED1D52ED36DAEDB6D563E9FDA30706F70B15568F2A13E9D001D"; - attribute INIT_02 of inst : label is "B0B333315D37D3A27D3AA80B5311A86ED76D9108D69FBA387B1B106B20F50C1F"; - attribute INIT_03 of inst : label is "4712A7D397E7D7C79757B6E62AE1B3F5C584E1B04A4B30D62290B9B60373A308"; - attribute INIT_04 of inst : label is "C36393E3134242E3F31DABBBDBCB0B6C5BC0BD1CBC71A6B6C1CA96366ABA6BB7"; - attribute INIT_05 of inst : label is "BBBB8F0000078FC3000300400F77F3FB3FF330FF0A0040800000020033CC13F3"; - attribute INIT_06 of inst : label is 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"6D2EDE1BD68BD9B511401B0D29BB63E1E83348AF6391280EFE7589C09D881F92"; - attribute INIT_19 of inst : label is "48870FE363C1864BD68BD48CD091C2ED36D0ED16D59D05166D9D031879861D02"; - attribute INIT_1A of inst : label is "F99EDC34BBBEDF9E4BD134D25D33912D03D3FFB7FA8E4BD1E4BD026D30D30886"; - attribute INIT_1B of inst : label is "ED93111070ECF86D7E1EBFFFAFF255F62D7806FF68DFFC3696862DFE7857CF6F"; - attribute INIT_1C of inst : label is "037373A155B9101B98EB120D755F10FBC07BA6D363E1723EF33E561BD6EDB6D0"; - attribute INIT_1D of inst : label is "1BD9B0198E10B080B7B73A155B9C01B98EB1274ABB0D755F60FB9B0198E10308"; - attribute INIT_1E of inst : label is "B98E1B0D755F2B363EB97059C03738F38E064B9F6FC4DB8860BDDEDE6D61BD86"; - attribute INIT_1F of inst : label is "6DB850D1C4D8ED5D00E261D7DA75D553808D08DB377608371D604E7EA87E9201"; - attribute INIT_20 of inst : label is "ED9111DC4D1C057D15ED193ED18CD5546D58ED95ED66D70DD0946D3ED00106F0"; - attribute INIT_21 of inst : label is "93CE15D9D001D5D063ED9FF7B026D1A980EB016D4ED56D88ED97D0F7F7C36776"; - attribute INIT_22 of inst : label is "5BB8D8606936ED04D8ED10DD4900111B8037373A154B92D2D7B7718066EDC38E"; - attribute INIT_23 of inst : label is "88C8C8800000000000000000000091D9D00C311198E1018364ED8037373A1555"; - attribute INIT_24 of inst : label is "0000000000080000808080000000000000000000000808000088000800080080"; - attribute INIT_25 of inst : label is "0008880080080000088088080008800000000088888000000800000000000800"; - attribute INIT_26 of inst : label is "8800008000008080000000000000000000000000888800880880000008808800"; - attribute INIT_27 of inst : label is "8888888008000000088000008088888008000800880880888888080888800000"; - attribute INIT_28 of inst : label is "8888000008808888888888888888888888000000800000808888880000000888"; - attribute INIT_29 of inst : label is "0000880000088880008888888880000888088888800000080880080800088080"; - attribute INIT_2A of inst : label is "0008000080008000080000080000000800000008000000000080000000000008"; - attribute INIT_2B of inst : label is "2BBED58B8D9AFA1D7BDE06B321D654A987FB325CE30997DE9A510689D31D0000"; - attribute INIT_2C of inst : label is "000000000000000000000000000000000000000000000000009C3BED9852D43D"; - attribute INIT_2D of inst : label is "B0655B8BBD911B906FFBFB999D499906A06F38B065536BFC6590D00000000000"; - attribute INIT_2E of inst : label is "06F88C4DB63E92B3B06F917EF6E3806E7777981B199B065591F6FFFF481B1E99"; - attribute INIT_2F of inst : label is "68B401388B70BBDF8DF68FD12671DAE89B1BBDE6BD5FE1262D1D9A5DB4D97DE9"; - attribute INIT_30 of inst : label is "810BB9EBF81078EA36F618FBF8A331603307716E536080ED8971D06280BA6F66"; - attribute INIT_31 of inst : label is "9F750FFC2DFF2002FEBFFE100A3E00A0256F65D177403E484E243FEFC7C805F4"; - attribute INIT_32 of inst : label is "D16D40E728E4F2ED36D2FDE2F0681D191C01D9D55AF281385E3E001D312F0398"; - attribute INIT_33 of inst : label is "9D555952D43D551163E363E3A063EB711982FFE688387E1EFD0111159B05C50E"; - attribute INIT_34 of inst : label is "D618F697EDFD9D994F4E08115D818BF01800BF59F1FEF0011B7114F1D79085FD"; - attribute INIT_35 of inst : label is "C4879A070E97FF7CB4628A61E9890C9FE09BA8C980BD1CD54DF39DC5F0B3F6F5"; - attribute INIT_36 of inst : label is "1A00254E59B03FD17E6C8591AF17FF9FE6C85959916F50F9F688DE0F9BCD9D40"; - attribute INIT_37 of inst : label is "875D170435C5307E9C22923302F41C53C130541DB3583048796E57E9D80038D3"; - attribute INIT_38 of inst : label is "DE890C08E8F8887008E0B0E000B0FE81F3128DFFFFF08791076D09CC120938D8"; - attribute INIT_39 of inst : label is "DF49718BF9DF1FFF84E83E5FFFF9E15FE53F5E812F54BF403DF606DF843DFA46"; - attribute INIT_3A of inst : label is "19D0E195EA155F7F3AE01DE93EC2F319F32F9F624EE89F733337E76E488B6AE8"; - attribute INIT_3B of inst : label is "B806F4DF0992FEFCEDD6D87A15D9B7D05E4BEDA7D308E2AED01DF6F4DF099001"; - attribute INIT_3C of inst : label is "2DAFAEDB6D5006F3DF8F188421FA509CF8F2DF367797AEDB6DF6DF36F77EBBBB"; - attribute INIT_3D of inst : label is "E51F32533787F247FF72533787F2C36288E07FF925E31E01F81CF83115DBC3DD"; - attribute INIT_3E of inst : label is "0ECFC720CE57FADE36E317240EE4A3F2D00E2AFA101DAE2287F2187E583ECA7F"; - attribute INIT_3F of inst : label is "F524E401FDD59DF211EADE61EADE51EADE41F024EDF3AA81EFC2FECF41CFCF31"; - begin - inst : RAMB16_S4 - --pragma translate_off - generic map ( - INIT_00 => romgen_str2bv(inst'INIT_00), - INIT_01 => romgen_str2bv(inst'INIT_01), - INIT_02 => romgen_str2bv(inst'INIT_02), - INIT_03 => romgen_str2bv(inst'INIT_03), - INIT_04 => romgen_str2bv(inst'INIT_04), - INIT_05 => romgen_str2bv(inst'INIT_05), - INIT_06 => romgen_str2bv(inst'INIT_06), - INIT_07 => romgen_str2bv(inst'INIT_07), - INIT_08 => romgen_str2bv(inst'INIT_08), - INIT_09 => romgen_str2bv(inst'INIT_09), - INIT_0A => romgen_str2bv(inst'INIT_0A), - INIT_0B => romgen_str2bv(inst'INIT_0B), - INIT_0C => romgen_str2bv(inst'INIT_0C), - INIT_0D => romgen_str2bv(inst'INIT_0D), - INIT_0E => romgen_str2bv(inst'INIT_0E), - INIT_0F => romgen_str2bv(inst'INIT_0F), - INIT_10 => romgen_str2bv(inst'INIT_10), - INIT_11 => romgen_str2bv(inst'INIT_11), - INIT_12 => romgen_str2bv(inst'INIT_12), - INIT_13 => romgen_str2bv(inst'INIT_13), - INIT_14 => romgen_str2bv(inst'INIT_14), - INIT_15 => romgen_str2bv(inst'INIT_15), - INIT_16 => romgen_str2bv(inst'INIT_16), - INIT_17 => romgen_str2bv(inst'INIT_17), - INIT_18 => romgen_str2bv(inst'INIT_18), - INIT_19 => romgen_str2bv(inst'INIT_19), - INIT_1A => romgen_str2bv(inst'INIT_1A), - INIT_1B => romgen_str2bv(inst'INIT_1B), - INIT_1C => romgen_str2bv(inst'INIT_1C), - INIT_1D => romgen_str2bv(inst'INIT_1D), - INIT_1E => romgen_str2bv(inst'INIT_1E), - INIT_1F => romgen_str2bv(inst'INIT_1F), - INIT_20 => romgen_str2bv(inst'INIT_20), - INIT_21 => romgen_str2bv(inst'INIT_21), - INIT_22 => romgen_str2bv(inst'INIT_22), - INIT_23 => romgen_str2bv(inst'INIT_23), - INIT_24 => romgen_str2bv(inst'INIT_24), - INIT_25 => romgen_str2bv(inst'INIT_25), - INIT_26 => romgen_str2bv(inst'INIT_26), - INIT_27 => romgen_str2bv(inst'INIT_27), - INIT_28 => romgen_str2bv(inst'INIT_28), - INIT_29 => romgen_str2bv(inst'INIT_29), - INIT_2A => romgen_str2bv(inst'INIT_2A), - INIT_2B => romgen_str2bv(inst'INIT_2B), - INIT_2C => romgen_str2bv(inst'INIT_2C), - INIT_2D => romgen_str2bv(inst'INIT_2D), - INIT_2E => romgen_str2bv(inst'INIT_2E), - INIT_2F => romgen_str2bv(inst'INIT_2F), - INIT_30 => romgen_str2bv(inst'INIT_30), - INIT_31 => romgen_str2bv(inst'INIT_31), - INIT_32 => romgen_str2bv(inst'INIT_32), - INIT_33 => romgen_str2bv(inst'INIT_33), - INIT_34 => romgen_str2bv(inst'INIT_34), - INIT_35 => romgen_str2bv(inst'INIT_35), - INIT_36 => romgen_str2bv(inst'INIT_36), - INIT_37 => romgen_str2bv(inst'INIT_37), - INIT_38 => romgen_str2bv(inst'INIT_38), - INIT_39 => romgen_str2bv(inst'INIT_39), - INIT_3A => romgen_str2bv(inst'INIT_3A), - INIT_3B => romgen_str2bv(inst'INIT_3B), - INIT_3C => romgen_str2bv(inst'INIT_3C), - INIT_3D => romgen_str2bv(inst'INIT_3D), - INIT_3E => romgen_str2bv(inst'INIT_3E), - INIT_3F => romgen_str2bv(inst'INIT_3F) - ) - --pragma translate_on - port map ( - DO => DATA(3 downto 0), - ADDR => rom_addr, - CLK => CLK, - DI => "0000", - EN => ENA, - SSR => '0', - WE => '0' - ); - end generate; - rom1 : if true generate - attribute INIT_00 of inst : label is "EFEDDCFEF008021CFC00221CFC72721CCF17F20CF60F020CF213120C06C0DAF0"; - attribute INIT_01 of inst : label is "C27EDC05F05F07FEDD05F05F06F06FD52514F203101500C2DE331071273F002F"; - attribute INIT_02 of inst : label is "CAC2222EEF07F1107F11026CE2DEA104F04F7D0AC404F2027C04200E134D0713"; - attribute INIT_03 of inst : label is "C0E060A0B0907010101000F0B0E0D0C0F0007080A0C0707030707CEF22711033"; - attribute INIT_04 of inst : label is "40502060406080D01020A040B0A0907010C01030F090B00000A0C03050F0F0E0"; - attribute INIT_05 of inst : label is "CCCCCCCCCCC00CEC0CC00DD22CC2CCCC1EEEED22C20F000C0CC0004020604070"; - attribute INIT_06 of inst : label is "1D1DFA22B4E321CAF4F3CFFCDE07C000AC0D330DC34E035EEDCFFCCE02C00C0C"; - attribute INIT_07 of inst : label is "120D0CC4E3F3D1FD1F07F07F0ECCABE0004E24E2F003FE230EC0FC011F17E000"; - attribute INIT_08 of inst : label is "05444424422055454452442204544525441D0C0B33330B0000A0E0000207C0AC"; - attribute INIT_09 of inst : label is "DEDEFEECF1CDEBEE1E4DCA02CD0CC0C2627627030C0BCE05C42020E7027CE05C"; - attribute INIT_0A of inst : label is "51CEE20E72E6F7F61CF3EF223036F7FA11E0C000CE2DCBEE403C700CE0CCCEFC"; - attribute INIT_0B of inst : label is "03C004CDCEEE20E2EF223A6FE02AE270CCED406F06FEEC34F1E766E7FE7F4AED"; - attribute INIT_0C of inst : label is "78F72F1272903ED5F7102266FE6FE6F6FCF1E6F024CEC1F302AF12BA3CCCBE2C"; - attribute INIT_0D of inst : label is "FC07F219FF1211281AC78E700004C03F03C7C12026CF1272903AE03C7C10226C"; - attribute INIT_0E of inst : label is "EA2727EC80F211201A440DCF203031A0274AFE54F210AC54F24E2800100AC4E2"; - attribute INIT_0F of inst : label is "20100DC2010DC014D222CE877ACF102A4070005C0D5E04E00CF1C020EBE4ECFC"; - attribute INIT_10 of inst : label is "7F30101117F121002A7EF01010E07CEC137BC027C74E2E10C74783030D03957E"; - attribute INIT_11 of inst : label is "007C3C0D0740E7AC0D0741E7A1E026CC7F1002A7E2010C747E7A027EAE113800"; - attribute INIT_12 of inst : label is "CE01EED01CEDE02312B74E2ECCC4C4F2C4D3B4D3E11C273022302B7033C014D2"; - attribute INIT_13 of inst : label is "024C4F20172301723725302B7212B272302B7EFC4E2E23300F321D1D023302E7"; - attribute INIT_14 of inst : label is "AE033C00AE033C00AE033C0104D34E305FB274D2D4C2010FC4D2D4D3C8C4F2FC"; - attribute INIT_15 of inst : label is "3BF914D32702A1AE41F0EB1BE0107025C139F0FC1D4D31D4D3E2BF120012033C"; - attribute INIT_16 of inst : label is "D30FE2525D12D06D2D06D020F0E23DFF1222D0203D0281AEAE4D103CF31150E0"; - attribute INIT_17 of inst : label is "4E3AC4D2D4C21D1DA24E3712FFA14F38E4F302E10554000E03EFC107D2D07D2D"; - attribute INIT_18 of inst : label is "3D04D70CDF0CFEEEFD027C07C7CE525DE12202B3E2CD03CF475D7CF17E0104F3"; - attribute INIT_19 of inst : label is "03B03CF24E73240CDB0CF02BF114706D06D05D05DE1D00105C1D001CA7C07F00"; - attribute INIT_1A of inst : label is "0705F0DFCE04CAC90CDE07D07DE2C07D07D1527527C40CDFD0CD003D07D223B4"; - attribute INIT_1B of inst : label is "7DC2ECF160C762C77AAA744F30F3CEA0ECF1CC00020A430E7F10ECF3021533E0"; - attribute INIT_1C of inst : label is "12727114ECECF1CE020ED1BE4DCA125C227C0FC2424F58275827FF0CD05D05D0"; - attribute INIT_1D of inst : label is "0CDCE1C020E727F12727114ECECE1CE020ED105E11AE4DCA125CCE1C020E727F"; - attribute INIT_1E of inst : label is "E020EEBE4DCAFC2424ECF210F12747492300FC0F0434E70270CD06D06DB0CDC7"; - attribute INIT_1F of inst : label is "9D31F23F0FC04CF032F002D0EFAEDECE106C0ACE241EF120EC036F0CFCA7CF1C"; - attribute INIT_20 of inst : label is "7FCCEED0FCDE107F807FC004DE06CEC04DD04C105D05DF20F1104D04D0020150"; - attribute INIT_21 of inst : label is "1D03DED3D002DED0004DC5A5F108D4703AFF108D07F05F403CC4F183A430E000"; - attribute INIT_22 of inst : label is "FE00C0F3E1D07F07C03CE23553002F2CF12727114FBCF4E4EAE0022CE07F0D03"; - attribute INIT_23 of inst : label is "44F4F44000055520222220000000CEDFDE10DFCD020E7020E07FF12727114EDC"; - attribute INIT_24 of inst : label is "04266000022F2200A7D7A042222241222221000066669A4A9619421CC2F07872"; - attribute INIT_25 of inst : label is "437800F8F11F95317803087F8870877222262788888708421006600000000F00"; - attribute INIT_26 of inst : label is "087421012400F0F0012484214266066066066061078877887887444210F788F8"; - attribute INIT_27 of inst : label is "F8887898887888E88FF88E88FF88888F7888887F88F88F888F88778BAB872021"; - attribute INIT_28 of inst : label is "A8887888F88FF88888F8889AC8888AAD8F88888889ACA9878000007222227888"; - attribute INIT_29 of inst : label is "84210F222258888525888DAA88822558887888888222222F780788789AF88F69"; - attribute INIT_2A of inst : label is "020F0200852580021F12027A2222024F4202222A72711111700124807444447F"; - attribute INIT_2B of inst : label is "FC04C0100CC0EEAE7E3232233323332333235525542C07F700D2004EDEED0000"; - attribute INIT_2C of inst : label is "2EAEEAEAE2222EEAE8EE2E8E22EAAE262EE8E2E44444EAAAE0C0D04CC107F07F"; - attribute INIT_2D of inst : label is "C00CE8107CCEFE10153C3C12255222026AC20274EFB0E76FEECBEEEEE404040E"; - attribute INIT_2E of inst : label is "015010FC252511C2C015CE7A0EA01FEA0000024CC03C00CECE0E0000024CC703"; - attribute INIT_2F of inst : label is "CBC12B027C0207C4F33E74E2400ECB3C7CC0ECB0CFC4E240002DC07F07F07F71"; - attribute INIT_30 of inst : label is "1F121CFC4F2D02B1004F1C4C4F322EF1202720C7E00F123D170EC8F027C2C0E0"; - attribute INIT_31 of inst : label is "2B110F4E330F30034C1F4C320CCF2030545404444CF21F021F014F0F054133FF"; - attribute INIT_32 of inst : label is "D06D01158033F06D06D3F233F3C7ED00001101CEE4F012025F272020F1000110"; - attribute INIT_33 of inst : label is "1CCEFC07F07FECFE42425252F1525E4DEE13F3303B02A7C4F411000C3D2B7E06"; - attribute INIT_34 of inst : label is "032C3EA07F409CDC3F00011E5044B1F00B401FDC05F4F331FC4FE3FE0B0203F0"; - attribute INIT_35 of inst : label is "0117DF120C165A51D6002000FD7DC37F0C7C3237C6C061051071C044F004F7FE"; - attribute INIT_36 of inst : label is "0F0254544CF126EF43E37FCC1FD4A4D13E37EDCCDD3FD6FD0E023F4FFC009C02"; - attribute INIT_37 of inst : label is "064444254444504444444545054544544440454444444054444454010E00120D"; - attribute INIT_38 of inst : label is "74E110004E502B10074F10064010F4E34F0024FFFFF033332444254444224205"; - attribute INIT_39 of inst : label is "5F976A7E025FA00A21F70000002C0A4F064FE05204D074635744347422574024"; - attribute INIT_3A of inst : label is "E1D011ED0B1EC444F34F2D0610900D0C4E3AC4D3134E1F722227A0EA025C814E"; - attribute INIT_3B of inst : label is "2C1E4E5F97C1A2F16D16DCA1DEDC17DD5F817D17D039F817D10C0E4E5F97CF1C"; - attribute INIT_3C of inst : label is "7D3F15D15DEC1E4E5F7F0F0000FA50C1F4025F0E007415D15D025F0E40072222"; - attribute INIT_3D of inst : label is "4F109F312777F107F07F312777F130E030F37F06F34F14F2A1E2F000DEDE17D1"; - attribute INIT_3E of inst : label is "A31F759953D601C7244F250D32F80050D35F8040010C14F327F1F20FF20F307F"; - attribute INIT_3F of inst : label is "4D303F1C02CC1DFE140AC0F20AC0E20AC0C205D0F34F321034E3F31F5E1F7599"; - begin - inst : RAMB16_S4 - --pragma translate_off - generic map ( - INIT_00 => romgen_str2bv(inst'INIT_00), - INIT_01 => romgen_str2bv(inst'INIT_01), - INIT_02 => romgen_str2bv(inst'INIT_02), - INIT_03 => romgen_str2bv(inst'INIT_03), - INIT_04 => romgen_str2bv(inst'INIT_04), - INIT_05 => romgen_str2bv(inst'INIT_05), - INIT_06 => romgen_str2bv(inst'INIT_06), - INIT_07 => romgen_str2bv(inst'INIT_07), - INIT_08 => romgen_str2bv(inst'INIT_08), - INIT_09 => romgen_str2bv(inst'INIT_09), - INIT_0A => romgen_str2bv(inst'INIT_0A), - INIT_0B => romgen_str2bv(inst'INIT_0B), - INIT_0C => romgen_str2bv(inst'INIT_0C), - INIT_0D => romgen_str2bv(inst'INIT_0D), - INIT_0E => romgen_str2bv(inst'INIT_0E), - INIT_0F => romgen_str2bv(inst'INIT_0F), - INIT_10 => romgen_str2bv(inst'INIT_10), - INIT_11 => romgen_str2bv(inst'INIT_11), - INIT_12 => romgen_str2bv(inst'INIT_12), - INIT_13 => romgen_str2bv(inst'INIT_13), - INIT_14 => romgen_str2bv(inst'INIT_14), - INIT_15 => romgen_str2bv(inst'INIT_15), - INIT_16 => romgen_str2bv(inst'INIT_16), - INIT_17 => romgen_str2bv(inst'INIT_17), - INIT_18 => romgen_str2bv(inst'INIT_18), - INIT_19 => romgen_str2bv(inst'INIT_19), - INIT_1A => romgen_str2bv(inst'INIT_1A), - INIT_1B => romgen_str2bv(inst'INIT_1B), - INIT_1C => romgen_str2bv(inst'INIT_1C), - INIT_1D => romgen_str2bv(inst'INIT_1D), - INIT_1E => romgen_str2bv(inst'INIT_1E), - INIT_1F => romgen_str2bv(inst'INIT_1F), - INIT_20 => romgen_str2bv(inst'INIT_20), - INIT_21 => romgen_str2bv(inst'INIT_21), - INIT_22 => romgen_str2bv(inst'INIT_22), - INIT_23 => romgen_str2bv(inst'INIT_23), - INIT_24 => romgen_str2bv(inst'INIT_24), - INIT_25 => romgen_str2bv(inst'INIT_25), - INIT_26 => romgen_str2bv(inst'INIT_26), - INIT_27 => romgen_str2bv(inst'INIT_27), - INIT_28 => romgen_str2bv(inst'INIT_28), - INIT_29 => romgen_str2bv(inst'INIT_29), - INIT_2A => romgen_str2bv(inst'INIT_2A), - INIT_2B => romgen_str2bv(inst'INIT_2B), - INIT_2C => romgen_str2bv(inst'INIT_2C), - INIT_2D => romgen_str2bv(inst'INIT_2D), - INIT_2E => romgen_str2bv(inst'INIT_2E), - INIT_2F => romgen_str2bv(inst'INIT_2F), - INIT_30 => romgen_str2bv(inst'INIT_30), - INIT_31 => romgen_str2bv(inst'INIT_31), - INIT_32 => romgen_str2bv(inst'INIT_32), - INIT_33 => romgen_str2bv(inst'INIT_33), - INIT_34 => romgen_str2bv(inst'INIT_34), - INIT_35 => romgen_str2bv(inst'INIT_35), - INIT_36 => romgen_str2bv(inst'INIT_36), - INIT_37 => romgen_str2bv(inst'INIT_37), - INIT_38 => romgen_str2bv(inst'INIT_38), - INIT_39 => romgen_str2bv(inst'INIT_39), - INIT_3A => romgen_str2bv(inst'INIT_3A), - INIT_3B => romgen_str2bv(inst'INIT_3B), - INIT_3C => romgen_str2bv(inst'INIT_3C), - INIT_3D => romgen_str2bv(inst'INIT_3D), - INIT_3E => romgen_str2bv(inst'INIT_3E), - INIT_3F => romgen_str2bv(inst'INIT_3F) - ) - --pragma translate_on - port map ( - DO => DATA(7 downto 4), - ADDR => rom_addr, - CLK => CLK, - DI => "0000", - EN => ENA, - SSR => '0', - WE => '0' - ); - end generate; -end RTL; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bally_bios_1.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bally_bios_1.vhd deleted file mode 100644 index 88ff69a4..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bally_bios_1.vhd +++ /dev/null @@ -1,493 +0,0 @@ --- generated with romgen v3.0 by MikeJ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -library UNISIM; - use UNISIM.Vcomponents.all; - -entity BALLY_BIOS_1 is - port ( - CLK : in std_logic; - ENA : in std_logic; - ADDR : in std_logic_vector(11 downto 0); - DATA : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of BALLY_BIOS_1 is - - function romgen_str2bv (str : string) return bit_vector is - variable result : bit_vector (str'length*4-1 downto 0); - begin - for i in 0 to str'length-1 loop - case str(str'high-i) is - when '0' => result(i*4+3 downto i*4) := x"0"; - when '1' => result(i*4+3 downto i*4) := x"1"; - when '2' => result(i*4+3 downto i*4) := x"2"; - when '3' => result(i*4+3 downto i*4) := x"3"; - when '4' => result(i*4+3 downto i*4) := x"4"; - when '5' => result(i*4+3 downto i*4) := x"5"; - when '6' => result(i*4+3 downto i*4) := x"6"; - when '7' => result(i*4+3 downto i*4) := x"7"; - when '8' => result(i*4+3 downto i*4) := x"8"; - when '9' => result(i*4+3 downto i*4) := x"9"; - when 'A' => result(i*4+3 downto i*4) := x"A"; - when 'B' => result(i*4+3 downto i*4) := x"B"; - when 'C' => result(i*4+3 downto i*4) := x"C"; - when 'D' => result(i*4+3 downto i*4) := x"D"; - when 'E' => result(i*4+3 downto i*4) := x"E"; - when 'F' => result(i*4+3 downto i*4) := x"F"; - when others => null; - end case; - end loop; - return result; - end romgen_str2bv; - - attribute INIT_00 : string; - attribute INIT_01 : string; - attribute INIT_02 : string; - attribute INIT_03 : string; - attribute INIT_04 : string; - attribute INIT_05 : string; - attribute INIT_06 : string; - attribute INIT_07 : string; - attribute INIT_08 : string; - attribute INIT_09 : string; - attribute INIT_0A : string; - attribute INIT_0B : string; - attribute INIT_0C : string; - attribute INIT_0D : string; - attribute INIT_0E : string; - attribute INIT_0F : string; - attribute INIT_10 : string; - attribute INIT_11 : string; - attribute INIT_12 : string; - attribute INIT_13 : string; - attribute INIT_14 : string; - attribute INIT_15 : string; - attribute INIT_16 : string; - attribute INIT_17 : string; - attribute INIT_18 : string; - attribute INIT_19 : string; - attribute INIT_1A : string; - attribute INIT_1B : string; - attribute INIT_1C : string; - attribute INIT_1D : string; - attribute INIT_1E : string; - attribute INIT_1F : string; - attribute INIT_20 : string; - attribute INIT_21 : string; - attribute INIT_22 : string; - attribute INIT_23 : string; - attribute INIT_24 : string; - attribute INIT_25 : string; - attribute INIT_26 : string; - attribute INIT_27 : string; - attribute INIT_28 : string; - attribute INIT_29 : string; - attribute INIT_2A : string; - attribute INIT_2B : string; - attribute INIT_2C : string; - attribute INIT_2D : string; - attribute INIT_2E : string; - attribute INIT_2F : string; - attribute INIT_30 : string; - attribute INIT_31 : string; - attribute INIT_32 : string; - attribute INIT_33 : string; - attribute INIT_34 : string; - attribute INIT_35 : string; - attribute INIT_36 : string; - attribute INIT_37 : string; - attribute INIT_38 : string; - attribute INIT_39 : string; - attribute INIT_3A : string; - attribute INIT_3B : string; - attribute INIT_3C : string; - attribute INIT_3D : string; - attribute INIT_3E : string; - attribute INIT_3F : string; - - component RAMB16_S4 - --pragma translate_off - generic ( - INIT_00 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_10 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_11 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_12 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_13 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_14 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_15 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_16 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_17 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_18 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_19 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_20 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_21 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_22 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_23 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_24 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_25 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_26 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_27 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_28 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_29 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_30 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_31 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_32 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_33 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_34 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_35 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_36 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_37 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_38 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_39 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DO : out std_logic_vector (3 downto 0); - ADDR : in std_logic_vector (11 downto 0); - CLK : in std_logic; - DI : in std_logic_vector (3 downto 0); - EN : in std_logic; - SSR : in std_logic; - WE : in std_logic - ); - end component; - - signal rom_addr : std_logic_vector(11 downto 0); - -begin - - p_addr : process(ADDR) - begin - rom_addr <= (others => '0'); - rom_addr(11 downto 0) <= ADDR; - end process; - - rom0 : if true generate - attribute INIT_00 of inst : label is "3F004E0B3C98F87F9028D0E000B0FE01FFFFFFFFFFFF752875289110010FF759"; - attribute INIT_01 of inst : label is "AD2AD980D0AD78FEBF4138EE9707B287EE21FFFFFEFF60FDF803E243F503116D"; - attribute INIT_02 of inst : label is "1311081A0E00132126543987402111009EE11508BFB1E3127D5ED1EA20010DB0"; - attribute INIT_03 of inst : label is "E4FF26D16F08980EB816402E88EFBBF2AD281E219EF1BD098B6E61001F28080E"; - attribute INIT_04 of inst : label is "B1BEE26FEEAB6E41E82E009EFFF0904326DE025E16D260DF8E029F816D38EF0B"; - attribute INIT_05 of inst : label is "2C71E8F6EB9E40BEFFF8F16F14F12F1B1815129B6E41EF1518BFE0A26DA815D0"; - attribute INIT_06 of inst : label is "811EA1005EFBF52AD206BA8BBBF8FB5E3989F87E38AEEEF1EA12AD580E126DE1"; - attribute INIT_07 of inst : label is "F0606B06F6787E32F0616287EE2157E381B3FDED1943FD33333989637370EE9C"; - attribute INIT_08 of inst : label is "EE41F32F94582E987E3418CEEE4127DE8100C8081F97B7F02EEE112A33EE0A12"; - attribute INIT_09 of inst : label is "F81E016E51181AE50DC000F81F8E48BE6388981C50D08F0081F8E587E387A01B"; - attribute INIT_0A of inst : label is "0A7FC6256FA0914F2419B892F21DF16FB6F08E284E7B60FB6FCE150E6FDEC0D9"; - attribute INIT_0B of inst : label is "6833D50F6EBC83FDEE309E9DD03FD6F3EAFF061B8FD7E9A8FDEE0AEF1D32DB00"; - attribute INIT_0C of inst : label is "00CF6BFF3128DFFC225DFF61FFFF777770269B17B03FD5B569B07DB1790610EE"; - attribute INIT_0D of inst : label is "FC23812F09104D09D0BD09D07D09E0AD5B000D87E7002F2B004F4B57990FF613"; - attribute INIT_0E of inst : label is "2A7F4AF224E285E482EF424E285EF3AFC242C7F2D1D43DF12701FA2F01F32381"; - attribute INIT_0F of inst : label is "1A06A5D514F0E4ED56D41144F66B12F586D7ED2F6EDDD56D4ED16A556BDA06FF"; - attribute INIT_10 of inst : label is "4F81F2F4EFC1065140DF3251F53E001FD467D0E068567D0E980F111D52D999F6"; - attribute INIT_11 of inst : label is "E8E6BD6BDF3236CF3A69D04A343B4394374354B168485F243FFD2F69D43D20D1"; - attribute INIT_12 of inst : label is "6D0ED90D018BF9031E539E330ED9D068B028F363ED6BDF3A98F69D6D3FB564B3"; - attribute INIT_13 of inst : label is "D56D37D17DC069D16D8869D1E869D386BD1ED6ED0E507800D11078F7F3066BD2"; - attribute INIT_14 of inst : label is "5557115E7017C191AF41106B0BF54035FD57DF6A47DF5A4F0E4114ED56D54D4E"; - attribute INIT_15 of inst : label is "810ED4019D001D4ED56D183333378D1113D881171F4F4110E154D4ED56D543A5"; - attribute INIT_16 of inst : label is "594F152D7999F61950688E6BD6BD9D4EE6BD5F414866BD9053D783B3501DD011"; - attribute INIT_17 of inst : label is "D96F2D1D364F3CE86D7ED9B1B409ED8F302FC27DFCA942855F216079E1F152D7"; - attribute INIT_18 of inst : label is "066BD3E883ECEE8CE281ED27D2ED300F6BD94F0E411154D54ED56D7ED3ED8E6B"; - attribute INIT_19 of inst : label is "7FFDF6FFF872787E749111D566BF1D56EBF559F5268EF21682E7F4A6837D1ED3"; - attribute INIT_1A of inst : label is "5912B740568B6FD0FF8658E976BD8EF697206BD8E7D070E4747F86BD816D8870"; - attribute INIT_1B of inst : label is "8F4658BEBA8FB48F4638BEBA87B28746108EAA8FB08746F80EAA87B5ED46D555"; - attribute INIT_1C of inst : label is "0FB7D10FB71107B7919111AB061F62BF52A407E9081C07EB10BF81155382B716"; - attribute INIT_1D of inst : label is "00004101010501500440819875A07EC1DC715D6FC1DC7D82D881C87941ED9751"; - attribute INIT_1E of inst : label is "5DF0EEF55DF0FFF88887823A22A0FCCF33F0A884004451045540154010473737"; - attribute INIT_1F of inst : label is "F9BFF2C3FFC2B2C7F887FCA2D1D01F3983FFFFF0000000055DF044855DF088E5"; - attribute INIT_20 of inst : label is "6FA5D5FC22E280E7FCAD02DA9187E9021987E87A877EDFDFBF8CDF98F9FAF1CD"; - attribute INIT_21 of inst : label is "D31633393D3333163511B9DF199B2FED06B09F608156BAFB9F180E60BD281990"; - attribute INIT_22 of inst : label is "068F11D58F8F81D933D42D85D94DEF0010010EDF81D48F11D989F71F23F06193"; - attribute INIT_23 of inst : label is "E016D9EFDB1016D226DE08E6ED9176D016D8E7BD0F80E061ED9F7DCE20EEFFFF"; - attribute INIT_24 of inst : label is "F6FD8F1DDFC860BDA88EE060BD0EC00E98090630E06F71B0BF5B6DCE07F0AD08"; - attribute INIT_25 of inst : label is "F4F3F21CE2F0EF21D9070E5EEB4F706203E86BED816D026D616DF2FD4F8DDFA8"; - attribute INIT_26 of inst : label is "93CE5D51384E98D8F021E8383E98D305E82E398D304E81E1938E5E419FE21EA1"; - attribute INIT_27 of inst : label is "87F82B006F6B0FF61F442EDF937B6BA33063337A3337A9112F8E7A55385E98D1"; - attribute INIT_28 of inst : label is "1C5BC5F64B287F24B2872D0D00FF2B0C818BF1800BDB0CFAF0F32FF0F23D3986"; - attribute INIT_29 of inst : label is "AD0D006DF81DD0DF51006DF11DF72F42FE98DD910EF5A98DDE18EF1AF02F2DAB"; - attribute INIT_2A of inst : label is "1D0E2082E401F81D021E48AC3F938EB8D0DAB6D866D086D3C6D006DFF1DD87F0"; - attribute INIT_2B of inst : label is "F88BC1B37281DB37BB203D7B10503F82B0F2D1D341FD34E7DDEC09D3C6D176D0"; - attribute INIT_2C of inst : label is "81D89CB89B888F8FBF8AAC32B8F0F8DFEA9D118ED5546021F81D2B452430F208"; - attribute INIT_2D of inst : label is "DE68F4518061BDFF2FD5DD7DF21F38ED34E5D9882222207118A67F48D38578F5"; - attribute INIT_2E of inst : label is "8F819B981DD0DF51D3DE2DEFFC18F64188FC1EFB63E9FED06D7100E1BDEFCC2E"; - attribute INIT_2F of inst : label is "E1BD61BD06C3FEDDEDE6D1861BDF81D46FF2FDAD360613DAD46011F915D55557"; - attribute INIT_30 of inst : label is "D36E28D7DF21109D02161BDE1BDE1BD88706BE9001F7DD3DE2D8F0ED6EDB6DB8"; - attribute INIT_31 of inst : label is "DBD5DC8AD7DF5126A09DE1BD48E7BDEFC8E1BD021DB146F81DBF3AE200E2EBED"; - attribute INIT_32 of inst : label is "61BDE1BD88EFD318861BDE1BDB26D6061BD27D7096D86D46D3ED50E1BDD3261B"; - attribute INIT_33 of inst : label is "111D20DBC525D0DF5100E1BD07DE1BD780EDFED17DE1BDA327DAE62EDC6211ED"; - attribute INIT_34 of inst : label is "1C6D176D016D236D9B73077FED39609418063EE8D0DF21E1BDD5DF51EFD81911"; - attribute INIT_35 of inst : label is "5204574AB9B191D57BBB633E393B92BBEF6873E30F6D315DB26D6F6D8B6D466D"; - attribute INIT_36 of inst : label is "42E3C683D0F304E0F406F0F40800F40B10F40C20F40F30F30B9F071248AF0941"; - attribute INIT_37 of inst : label is "010052AAEC89BEC89EC88BEC811E2E2E4E8E0E6D8FF00000000667CD27BD2FD8"; - attribute INIT_38 of inst : label is "0404050100625A0000000500526A00040500427A050422AA01040032AA000104"; - attribute INIT_39 of inst : label is "050405050552F34B550000040552F24040501001505505153F04000041515A00"; - attribute INIT_3A of inst : label is "00051005100450005400550455058000A240AA102A008A005500450001341042"; - attribute INIT_3B of inst : label is "0CC6220800C155551556158A008A00550045000174D0C2400001000000010005"; - attribute INIT_3C of inst : label is "6400510550510510510550550800A00A20220A2055051040F30011005D04F700"; - attribute INIT_3D of inst : label is "4AA20AA00AA20450055005510545450541054105450545450555055105500050"; - attribute INIT_3E of inst : label is "F9D004D6D2D4D6D2F9D0648662DCE4F9D90901004000400048005AA248004A80"; - attribute INIT_3F of inst : label is "FFFFFFFFFFFFFFFFFFFFF0C5F551FF0005DF0FFF8012E612168286D218161218"; - begin - inst : RAMB16_S4 - --pragma translate_off - generic map ( - INIT_00 => romgen_str2bv(inst'INIT_00), - INIT_01 => romgen_str2bv(inst'INIT_01), - INIT_02 => romgen_str2bv(inst'INIT_02), - INIT_03 => romgen_str2bv(inst'INIT_03), - INIT_04 => romgen_str2bv(inst'INIT_04), - INIT_05 => romgen_str2bv(inst'INIT_05), - INIT_06 => romgen_str2bv(inst'INIT_06), - INIT_07 => romgen_str2bv(inst'INIT_07), - INIT_08 => romgen_str2bv(inst'INIT_08), - INIT_09 => romgen_str2bv(inst'INIT_09), - INIT_0A => romgen_str2bv(inst'INIT_0A), - INIT_0B => romgen_str2bv(inst'INIT_0B), - INIT_0C => romgen_str2bv(inst'INIT_0C), - INIT_0D => romgen_str2bv(inst'INIT_0D), - INIT_0E => romgen_str2bv(inst'INIT_0E), - INIT_0F => romgen_str2bv(inst'INIT_0F), - INIT_10 => romgen_str2bv(inst'INIT_10), - INIT_11 => romgen_str2bv(inst'INIT_11), - INIT_12 => romgen_str2bv(inst'INIT_12), - INIT_13 => romgen_str2bv(inst'INIT_13), - INIT_14 => romgen_str2bv(inst'INIT_14), - INIT_15 => romgen_str2bv(inst'INIT_15), - INIT_16 => romgen_str2bv(inst'INIT_16), - INIT_17 => romgen_str2bv(inst'INIT_17), - INIT_18 => romgen_str2bv(inst'INIT_18), - INIT_19 => romgen_str2bv(inst'INIT_19), - INIT_1A => romgen_str2bv(inst'INIT_1A), - INIT_1B => romgen_str2bv(inst'INIT_1B), - INIT_1C => romgen_str2bv(inst'INIT_1C), - INIT_1D => romgen_str2bv(inst'INIT_1D), - INIT_1E => romgen_str2bv(inst'INIT_1E), - INIT_1F => romgen_str2bv(inst'INIT_1F), - INIT_20 => romgen_str2bv(inst'INIT_20), - INIT_21 => romgen_str2bv(inst'INIT_21), - INIT_22 => romgen_str2bv(inst'INIT_22), - INIT_23 => romgen_str2bv(inst'INIT_23), - INIT_24 => romgen_str2bv(inst'INIT_24), - INIT_25 => romgen_str2bv(inst'INIT_25), - INIT_26 => romgen_str2bv(inst'INIT_26), - INIT_27 => romgen_str2bv(inst'INIT_27), - INIT_28 => romgen_str2bv(inst'INIT_28), - INIT_29 => romgen_str2bv(inst'INIT_29), - INIT_2A => romgen_str2bv(inst'INIT_2A), - INIT_2B => romgen_str2bv(inst'INIT_2B), - INIT_2C => romgen_str2bv(inst'INIT_2C), - INIT_2D => romgen_str2bv(inst'INIT_2D), - INIT_2E => romgen_str2bv(inst'INIT_2E), - INIT_2F => romgen_str2bv(inst'INIT_2F), - INIT_30 => romgen_str2bv(inst'INIT_30), - INIT_31 => romgen_str2bv(inst'INIT_31), - INIT_32 => romgen_str2bv(inst'INIT_32), - INIT_33 => romgen_str2bv(inst'INIT_33), - INIT_34 => romgen_str2bv(inst'INIT_34), - INIT_35 => romgen_str2bv(inst'INIT_35), - INIT_36 => romgen_str2bv(inst'INIT_36), - INIT_37 => romgen_str2bv(inst'INIT_37), - INIT_38 => romgen_str2bv(inst'INIT_38), - INIT_39 => romgen_str2bv(inst'INIT_39), - INIT_3A => romgen_str2bv(inst'INIT_3A), - INIT_3B => romgen_str2bv(inst'INIT_3B), - INIT_3C => romgen_str2bv(inst'INIT_3C), - INIT_3D => romgen_str2bv(inst'INIT_3D), - INIT_3E => romgen_str2bv(inst'INIT_3E), - INIT_3F => romgen_str2bv(inst'INIT_3F) - ) - --pragma translate_on - port map ( - DO => DATA(3 downto 0), - ADDR => rom_addr, - CLK => CLK, - DI => "0000", - EN => ENA, - SSR => '0', - WE => '0' - ); - end generate; - rom1 : if true generate - attribute INIT_00 of inst : label is "000094C111101B1F075010064010F4C3FFFFFFFFFFFF0A600A60CC000007F4CC"; - attribute INIT_01 of inst : label is "CC10C01BE1CC030725372C0F75CA732A74C250000A40E195F7C1F014FE14218C"; - attribute INIT_02 of inst : label is "12111E18200710001000100014553668C74C2D1B5F71DCE1CCE4D24D2002BEE1"; - attribute INIT_03 of inst : label is "4C5F11C03020700F1103020F314C06F10C4174C2C4C2EF114004E2121A131D1D"; - attribute INIT_04 of inst : label is "00E4C36F4C3004C24D34D004C5FCA18C11C4C30314C03C3014C374014C014C00"; - attribute INIT_05 of inst : label is "33703C0E7204C004C5F6F06F06F06F16161616C004C14C2D155F4C311CD117C0"; - attribute INIT_06 of inst : label is "2BC4D20014C1FC10C12B22122E45FE3427CB02A72C0F74C14D210C2100E11C4C"; - attribute INIT_07 of inst : label is "F2C032030C02A723F2C3C02A74C2E00501E10C4D17310C111110103272020F71"; - attribute INIT_08 of inst : label is "74E24E3AC3125F12A723025F74E21CC4524250023FC727AC0F74C218C004C3E3"; - attribute INIT_09 of inst : label is "FD048284E201103F234852FD3F033D0F92114113F234242023F033CA72CA124C"; - attribute INIT_0A of inst : label is "225444545422CF3F1B2DC4C3F1C5FF3F804B0302034C124C5F004F005F00F230"; - attribute INIT_0B of inst : label is "F110C020E7EE210C03F20F700210C5F101FA000E5F004D35F004C34C13662220"; - attribute INIT_0C of inst : label is "000491F4F0024F4D8034F493FFFF00000067CEE7F126EEE00CF16E24A0000C0F"; - attribute INIT_0D of inst : label is "4A23220000200100102100105100107150A00106B10024A10004E111A10F493F"; - attribute INIT_0E of inst : label is "A344A34A303030F030F4A303030F4F34D42043F002D1BC4C24524B21524B2372"; - attribute INIT_0F of inst : label is "24007EDDD2F1306F06F0001150C7D3FD05F05F3F04F1105D05D3C7DC15C70144"; - attribute INIT_10 of inst : label is "1F25F3F402413CFF19C4A305FF03A2BA0107D83001007DC302BACDED1EC00049"; - attribute INIT_11 of inst : label is "E270CD15C4A30E34A314CC185185185185185164F1154F014F4D3A14C1BCE23F"; - attribute INIT_12 of inst : label is "4D04DC0024B1FC1D131D031D07F0F004F10300007D15C4A3C4F14C11C3C1D1BC"; - attribute INIT_13 of inst : label is "D05D07D07D321AC04D021AC4021AC121AC07D17C0002B707D402B744A0270CD0"; - attribute INIT_14 of inst : label is "DCF1B203181160CD2F00100E03FD19C1FC07D4A307D4A32F1300006F06F12C05"; - attribute INIT_15 of inst : label is "B207F0011F002F05F05FD100001023FCDBE010E05F2F00013E12C05D05DC0D1E"; - attribute INIT_16 of inst : label is "C75FC1EC30004927C001270CD15C7000B0CD34A20270CDE212FF172002BE0204"; - attribute INIT_17 of inst : label is "DC3F002D401580305F05FECAC0304F7F14C4D3234D3C302334A2D2B715FC1ECB"; - attribute INIT_18 of inst : label is "270CD0E020E0E020E120AD07D07D02BA15CC2F13000E12CE05D05D12C07DC70C"; - attribute INIT_19 of inst : label is "7F4B4B4A4A16151414CDEEDD175FEFD165FEDC4D39034A20203B4A3B107D07D0"; - attribute INIT_1A of inst : label is "CCD1C3F210271BCA5001D03C41AC0300C4021AC034F10830407FC1AC704D02B2"; - attribute INIT_1B of inst : label is "150C025F7024C1150D120F7024C2150C239F7025C3150D220F7025C05D05DFED"; - attribute INIT_1C of inst : label is "C5C182C4C192C4C182CCDE3C01F4A374A37E2B70020E2B7EE03F55CDD211C3F0"; - attribute INIT_1D of inst : label is "0000404150400540011010511A677710211A8899107119ABBC100119DEEFC192"; - attribute INIT_1E of inst : label is "FFF03E8FFFF03FEFFFF8F6BA88A33F0FCCF22A01551154010010451800080000"; - attribute INIT_1F of inst : label is "FCF0F30DA4D40043F02B4D3002D81FF1ECFFFFF00000000FFFF0344FFFF0384F"; - attribute INIT_20 of inst : label is "260EDE4D3030213B4D302030C02B7101102B7CB0CB07F434D47D0F01414D46D0"; - attribute INIT_21 of inst : label is "C2032001DC0002032EECE1181126605D01F11F302100E3FE1A024370CD061220"; - attribute INIT_22 of inst : label is "EE7462D0127472DC07D07D07D07D7F08208104D472D01462D04C1D0411F83E1D"; - attribute INIT_23 of inst : label is "F003DC3F182803D003D034F07DC003D003DC50CDD022F6E07DC07D03020F0000"; - attribute INIT_24 of inst : label is "4A1A046D0F0270CDD151D270CD41036FCF217B27700FD1E03F105D41CB493135"; - attribute INIT_25 of inst : label is "F3FF102001FC3412D6670C0F725F52C031F0D07D603D813D013D4A1B647D0F01"; - attribute INIT_26 of inst : label is "1D03F1E20D0F1CC04938300D0F1CC030FD0F01CC030FD0FF1D03F1F2C4D303F5"; - attribute INIT_27 of inst : label is "B14F0700D4010F4034F8014FC17E8E020030127120171CFD2F0350DF0D0F1CCF"; - attribute INIT_28 of inst : label is "0231204AC00834AC0003001000841100F461F064011C004D50FF019C4111C10D"; - attribute INIT_29 of inst : label is "313C503D472D13C412103D462D4134134318C1B0414A318C1B0514A3493A0170"; - attribute INIT_2A of inst : label is "7D6002B03020412D0111F0242F1D030115C003D403D403D003D103D482D12B49"; - attribute INIT_2B of inst : label is "F002351503600150B002318004343F0120F002DF65F0D734E13E11D003D003D0"; - attribute INIT_2C of inst : label is "1B51B51201207FC7C4F310C0D1E1D234D31DCD1CCDC00011412D01340140F043"; - attribute INIT_2D of inst : label is "D122F1012240CD0F3A12C16C4120DC30D73EDD0033333C1E51051F5189195185"; - attribute INIT_2E of inst : label is "1102CFD0ED15C41207D07D1F1322F101011021FE525105D011D23260CD1F2216"; - attribute INIT_2F of inst : label is "70CDB0CDC30D07D06D06D1270CD412D000F3A11C00011211C00011412EDEDCFE"; - attribute INIT_30 of inst : label is "0D731216C412B11D011F0CDE0CDB0CD02BC3E7140207D07D07D3F07D05D05D22"; - attribute INIT_31 of inst : label is "DF12C1FC16C41200E11DB0CD0250CD3F0270CD01118200412DF0D6303033F07D"; - attribute INIT_32 of inst : label is "A0CDD0CD023F18221E0CDD0CD413D3260CD07D120BD0BD0BD07D2260CD10C40C"; - attribute INIT_33 of inst : label is "DEED00CF17C015C4122250CD17DD0CD021BD07D17DD0CD1117D11115D1DF917D"; - attribute INIT_34 of inst : label is "003D003D803D303DC272CA7F7DFCF11302AE27D115C41290CD12C4123F172CFC"; - attribute INIT_35 of inst : label is "45254440151CCEDDA7225225FC72C1127502A7720F3DFDED413D003D203D003D"; - attribute INIT_36 of inst : label is "41042140F00000F00000F0000000000000000000000000000509054544020544"; - attribute INIT_37 of inst : label is "05040000A108E730A73006310101413121111101F008003300000867A807A302"; - attribute INIT_38 of inst : label is "0501000040000004050104400000050540010000450500004001050000400000"; - attribute INIT_39 of inst : label is "4001010105000004155555555100000750140540144005000000644140000005"; - attribute INIT_3A of inst : label is "0145010505050505550551055040A050A018A000A000A004550454001010001D"; - attribute INIT_3B of inst : label is "333FFB333200555145A1018000A004550454001000003D500040004000500050"; - attribute INIT_3C of inst : label is "1000500540540545555550510A00A08A00A00A05511510400000000044254433"; - attribute INIT_3D of inst : label is "8AA10AA08AA00510055045505150505150415041505151515550455005500500"; - attribute INIT_3E of inst : label is "19CF7280B182B0B119CF92A091807219CC00B1800001000100218AA5002102A1"; - attribute INIT_3F of inst : label is "FFFFFFFFFFFFFFFFFFFFFF40800E3FBEFFFF03FE8FE1E0E1E0C1C0B1E1E0E1E1"; - begin - inst : RAMB16_S4 - --pragma translate_off - generic map ( - INIT_00 => romgen_str2bv(inst'INIT_00), - INIT_01 => romgen_str2bv(inst'INIT_01), - INIT_02 => romgen_str2bv(inst'INIT_02), - INIT_03 => romgen_str2bv(inst'INIT_03), - INIT_04 => romgen_str2bv(inst'INIT_04), - INIT_05 => romgen_str2bv(inst'INIT_05), - INIT_06 => romgen_str2bv(inst'INIT_06), - INIT_07 => romgen_str2bv(inst'INIT_07), - INIT_08 => romgen_str2bv(inst'INIT_08), - INIT_09 => romgen_str2bv(inst'INIT_09), - INIT_0A => romgen_str2bv(inst'INIT_0A), - INIT_0B => romgen_str2bv(inst'INIT_0B), - INIT_0C => romgen_str2bv(inst'INIT_0C), - INIT_0D => romgen_str2bv(inst'INIT_0D), - INIT_0E => romgen_str2bv(inst'INIT_0E), - INIT_0F => romgen_str2bv(inst'INIT_0F), - INIT_10 => romgen_str2bv(inst'INIT_10), - INIT_11 => romgen_str2bv(inst'INIT_11), - INIT_12 => romgen_str2bv(inst'INIT_12), - INIT_13 => romgen_str2bv(inst'INIT_13), - INIT_14 => romgen_str2bv(inst'INIT_14), - INIT_15 => romgen_str2bv(inst'INIT_15), - INIT_16 => romgen_str2bv(inst'INIT_16), - INIT_17 => romgen_str2bv(inst'INIT_17), - INIT_18 => romgen_str2bv(inst'INIT_18), - INIT_19 => romgen_str2bv(inst'INIT_19), - INIT_1A => romgen_str2bv(inst'INIT_1A), - INIT_1B => romgen_str2bv(inst'INIT_1B), - INIT_1C => romgen_str2bv(inst'INIT_1C), - INIT_1D => romgen_str2bv(inst'INIT_1D), - INIT_1E => romgen_str2bv(inst'INIT_1E), - INIT_1F => romgen_str2bv(inst'INIT_1F), - INIT_20 => romgen_str2bv(inst'INIT_20), - INIT_21 => romgen_str2bv(inst'INIT_21), - INIT_22 => romgen_str2bv(inst'INIT_22), - INIT_23 => romgen_str2bv(inst'INIT_23), - INIT_24 => romgen_str2bv(inst'INIT_24), - INIT_25 => romgen_str2bv(inst'INIT_25), - INIT_26 => romgen_str2bv(inst'INIT_26), - INIT_27 => romgen_str2bv(inst'INIT_27), - INIT_28 => romgen_str2bv(inst'INIT_28), - INIT_29 => romgen_str2bv(inst'INIT_29), - INIT_2A => romgen_str2bv(inst'INIT_2A), - INIT_2B => romgen_str2bv(inst'INIT_2B), - INIT_2C => romgen_str2bv(inst'INIT_2C), - INIT_2D => romgen_str2bv(inst'INIT_2D), - INIT_2E => romgen_str2bv(inst'INIT_2E), - INIT_2F => romgen_str2bv(inst'INIT_2F), - INIT_30 => romgen_str2bv(inst'INIT_30), - INIT_31 => romgen_str2bv(inst'INIT_31), - INIT_32 => romgen_str2bv(inst'INIT_32), - INIT_33 => romgen_str2bv(inst'INIT_33), - INIT_34 => romgen_str2bv(inst'INIT_34), - INIT_35 => romgen_str2bv(inst'INIT_35), - INIT_36 => romgen_str2bv(inst'INIT_36), - INIT_37 => romgen_str2bv(inst'INIT_37), - INIT_38 => romgen_str2bv(inst'INIT_38), - INIT_39 => romgen_str2bv(inst'INIT_39), - INIT_3A => romgen_str2bv(inst'INIT_3A), - INIT_3B => romgen_str2bv(inst'INIT_3B), - INIT_3C => romgen_str2bv(inst'INIT_3C), - INIT_3D => romgen_str2bv(inst'INIT_3D), - INIT_3E => romgen_str2bv(inst'INIT_3E), - INIT_3F => romgen_str2bv(inst'INIT_3F) - ) - --pragma translate_on - port map ( - DO => DATA(7 downto 4), - ADDR => rom_addr, - CLK => CLK, - DI => "0000", - EN => ENA, - SSR => '0', - WE => '0' - ); - end generate; -end RTL; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bally_check.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bally_check.vhd deleted file mode 100644 index c7462864..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bally_check.vhd +++ /dev/null @@ -1,379 +0,0 @@ --- generated with romgen v3.0 by MikeJ -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; - use ieee.numeric_std.all; - -library UNISIM; - use UNISIM.Vcomponents.all; - -entity BALLY_CHECK is - port ( - CLK : in std_logic; - ENA : in std_logic; - ADDR : in std_logic_vector(10 downto 0); - DATA : out std_logic_vector(7 downto 0) - ); -end; - -architecture RTL of BALLY_CHECK is - - function romgen_str2bv (str : string) return bit_vector is - variable result : bit_vector (str'length*4-1 downto 0); - begin - for i in 0 to str'length-1 loop - case str(str'high-i) is - when '0' => result(i*4+3 downto i*4) := x"0"; - when '1' => result(i*4+3 downto i*4) := x"1"; - when '2' => result(i*4+3 downto i*4) := x"2"; - when '3' => result(i*4+3 downto i*4) := x"3"; - when '4' => result(i*4+3 downto i*4) := x"4"; - when '5' => result(i*4+3 downto i*4) := x"5"; - when '6' => result(i*4+3 downto i*4) := x"6"; - when '7' => result(i*4+3 downto i*4) := x"7"; - when '8' => result(i*4+3 downto i*4) := x"8"; - when '9' => result(i*4+3 downto i*4) := x"9"; - when 'A' => result(i*4+3 downto i*4) := x"A"; - when 'B' => result(i*4+3 downto i*4) := x"B"; - when 'C' => result(i*4+3 downto i*4) := x"C"; - when 'D' => result(i*4+3 downto i*4) := x"D"; - when 'E' => result(i*4+3 downto i*4) := x"E"; - when 'F' => result(i*4+3 downto i*4) := x"F"; - when others => null; - end case; - end loop; - return result; - end romgen_str2bv; - - attribute INITP_00 : string; - attribute INITP_01 : string; - attribute INITP_02 : string; - attribute INITP_03 : string; - attribute INITP_04 : string; - attribute INITP_05 : string; - attribute INITP_06 : string; - attribute INITP_07 : string; - - attribute INIT_00 : string; - attribute INIT_01 : string; - attribute INIT_02 : string; - attribute INIT_03 : string; - attribute INIT_04 : string; - attribute INIT_05 : string; - attribute INIT_06 : string; - attribute INIT_07 : string; - attribute INIT_08 : string; - attribute INIT_09 : string; - attribute INIT_0A : string; - attribute INIT_0B : string; - attribute INIT_0C : string; - attribute INIT_0D : string; - attribute INIT_0E : string; - attribute INIT_0F : string; - attribute INIT_10 : string; - attribute INIT_11 : string; - attribute INIT_12 : string; - attribute INIT_13 : string; - attribute INIT_14 : string; - attribute INIT_15 : string; - attribute INIT_16 : string; - attribute INIT_17 : string; - attribute INIT_18 : string; - attribute INIT_19 : string; - attribute INIT_1A : string; - attribute INIT_1B : string; - attribute INIT_1C : string; - attribute INIT_1D : string; - attribute INIT_1E : string; - attribute INIT_1F : string; - attribute INIT_20 : string; - attribute INIT_21 : string; - attribute INIT_22 : string; - attribute INIT_23 : string; - attribute INIT_24 : string; - attribute INIT_25 : string; - attribute INIT_26 : string; - attribute INIT_27 : string; - attribute INIT_28 : string; - attribute INIT_29 : string; - attribute INIT_2A : string; - attribute INIT_2B : string; - attribute INIT_2C : string; - attribute INIT_2D : string; - attribute INIT_2E : string; - attribute INIT_2F : string; - attribute INIT_30 : string; - attribute INIT_31 : string; - attribute INIT_32 : string; - attribute INIT_33 : string; - attribute INIT_34 : string; - attribute INIT_35 : string; - attribute INIT_36 : string; - attribute INIT_37 : string; - attribute INIT_38 : string; - attribute INIT_39 : string; - attribute INIT_3A : string; - attribute INIT_3B : string; - attribute INIT_3C : string; - attribute INIT_3D : string; - attribute INIT_3E : string; - attribute INIT_3F : string; - - component RAMB16_S9 - --pragma translate_off - generic ( - INITP_00 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INITP_01 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INITP_02 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INITP_03 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INITP_04 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INITP_05 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INITP_06 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INITP_07 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - - INIT_00 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_01 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_02 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_03 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_04 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_05 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_06 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_07 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_08 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_09 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_0F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_10 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_11 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_12 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_13 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_14 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_15 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_16 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_17 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_18 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_19 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_1F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_20 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_21 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_22 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_23 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_24 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_25 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_26 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_27 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_28 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_29 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_2F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_30 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_31 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_32 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_33 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_34 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_35 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_36 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_37 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_38 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_39 : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3A : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3B : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3C : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3D : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3E : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"; - INIT_3F : bit_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000" - ); - --pragma translate_on - port ( - DO : out std_logic_vector (7 downto 0); - DOP : out std_logic_vector (0 downto 0); - ADDR : in std_logic_vector (10 downto 0); - CLK : in std_logic; - DI : in std_logic_vector (7 downto 0); - DIP : in std_logic_vector (0 downto 0); - EN : in std_logic; - SSR : in std_logic; - WE : in std_logic - ); - end component; - - signal rom_addr : std_logic_vector(10 downto 0); - -begin - - p_addr : process(ADDR) - begin - rom_addr <= (others => '0'); - rom_addr(10 downto 0) <= ADDR; - end process; - - rom0 : if true generate - attribute INIT_00 of inst : label is "A716DB2920A715DB08F3201627772728FFAA55002F0F0F2FC98787878720ADC3"; - attribute INIT_01 of inst : label is "264FCA02FE25D9CA01FE27BACA02FE2627CA01FE3628A714DB0F20A717DB3020"; - attribute INIT_02 of inst : label is "0FE679D92673CA02FE25EACA01FE10182748CA02FE2611CA01FE1C18182810FE"; - attribute INIT_03 of inst : label is "0118A03E0520A7780918B13E042084FE79112043CB001640203CFE7A14D9D94F"; - attribute INIT_04 of inst : label is "4706C6780420A0FE2003CD7D2C002618203CFE7C24001E20203CFE7B1CFFD3AF"; - attribute INIT_05 of inst : label is "08D3003EFFD3AA3ED96F675F57810E47AFD9F3C9FB08D96F47AF032099FE7804"; - attribute INIT_06 of inst : label is "C320E221FD6C1823EF21011EF318092818FE790C0820A778ED140EAF0AD3C83E"; - attribute INIT_07 of inst : label is "0116FB5EED0FD3AF0DD37D47ED7C2014210ED3083E4FC8314F00504E04182164"; - attribute INIT_08 of inst : label is "0021200001FBD9800E301823EF21FF0E021ED90A20A77B0E20A77AD9F325CFCD"; - attribute INIT_09 of inst : label is "4F08D67C031EE718122828FE7C214AC30A20A4FE7AF72005FA200D235786AF00"; - attribute INIT_0A of inst : label is "68180618215E21FDFB4F00504E04181318215121FDF323E6C3214A21A00E0220"; - attribute INIT_0B of inst : label is "EE2003BEFD7C234B18217921DD0628A87E70046EFD0566FD0106000E40004F3F"; - attribute INIT_0C of inst : label is "FD7C232718218021DDE928AE772F783318219121DD0628A87E162802BEFD7C2B"; - attribute INIT_0D of inst : label is "21041EE9FD0220A779B13020CBEA1877AF151821AF21DD0628AE2F780F2803BE"; - attribute INIT_0E of inst : label is "FD68780077FD6F67AF0CD37901064FAF481021DD081021FDE9DD4FB14F1821C8"; - attribute INIT_0F of inst : label is "20BC017EDD1320BD007EDDF5203D1CCB1DCB1CCB1DCB0B28A7790177FDAF0077"; - attribute INIT_10 of inst : label is "0E224A214810110CD3403E3318221521051E0718C62004FE4F3C79CF3010CB0D"; - attribute INIT_11 of inst : label is "1A18F23039CB230720BE1A0077FD2F7919CBF33021CB231A20BE1A0077FD7901"; - attribute INIT_12 of inst : label is "4FAF0CD3083EBF7FEFDFFBF7FEFD02010804201080404718225A21071E4F2F79"; - attribute INIT_13 of inst : label is "C67AEA10231120BA017EDD1720BA007EDD0177FD0077FD7E040619D3200C2157"; - attribute INIT_14 of inst : label is "FE1C2801FE22E3CD22CECD103E3818229321121E0718DA2014FE4F05C6795755"; - attribute INIT_15 of inst : label is "22A321081E0218101E233AC3122802FE122801FE22E3CD2C22CECD203E142802"; - attribute INIT_16 of inst : label is "C9013EC904066F4F5F57AF01042108DB0CD323E6C3233A21111E0218091E0918"; - attribute INIT_17 of inst : label is "DB0728A779E22000BEDDA97A0218B17A0420BDAF2333CD2333CD2333CDC9023E"; - attribute INIT_18 of inst : label is "20A77B14CBC83024CB24CB3BCB040001D3104F8479D520B908DB0518DC20BB08"; - attribute INIT_19 of inst : label is "0FDB0EDBFF06C90071FD0072DDC9B130881E0400015755C67A3BCB0218881E04"; - attribute INIT_1A of inst : label is "790C7120FFFE78ED1C0E17DB16DB15DB14DBF42014FE790C23C8C2A778ED100E"; - attribute INIT_1B of inst : label is "D3143E07D303D306D302D305D301D304D300D37808D3003EFF06D610F42020FE"; - attribute INIT_1C of inst : label is "14D316D317D3FF3EB3ED180E080623D621B3ED0B0E080623DE21500AD3C83E09"; - attribute INIT_1D of inst : label is "A7FE18FBD9082084FE790C0A287FCB79D9F3BA104215D313D312D311D310D37A"; - attribute INIT_1E of inst : label is "92DBF5F5FDFF003444481018236821141E1718234E21131E211BC3FBD90C0120"; - attribute INIT_1F of inst : label is "3E311823FF21FFD379391823F721FFD37B5028A70FE6D979D9F3004992DB0049"; - attribute INIT_20 of inst : label is "1018FFD3A03E0220A7242021D978D91F18241121FFD3DE3E2818240821FFD3CB"; - attribute INIT_21 of inst : label is "FBE9F42015F9203DFE10FF06FF3E021623EF21FFD3AA3E0718242921FFD3AA3E"; - attribute INIT_22 of inst : label is "4554495257005244444120444145520058454820544749442D342052544E45E9"; - attribute INIT_23 of inst : label is "0054524F5020444145520058454820544749442D322052544E45005244444120"; - attribute INIT_24 of inst : label is "544749442D322052544E45005244444120545254530054524F50204554495257"; - attribute INIT_25 of inst : label is "002A2A2A2A002A2A004554495257204F54204554594200415441440058454820"; - attribute INIT_26 of inst : label is "36313D35313D34313D33313D32313D31313D30312020202020203D46303D4530"; - attribute INIT_27 of inst : label is "AF004E5552204F5420224F47223D46313D45313D44313D43312020203D37313D"; - attribute INIT_28 of inst : label is "35FFC924410C280435FFC9000FB040001BFF03D302D301D30F3E09D300D304D3"; - attribute INIT_29 of inst : label is "DD0C0EC924AA0C320435FF24950C280435FFC924660C280435FFC924510C3204"; - attribute INIT_2A of inst : label is "78F82013FE200843FF4FEC32FF3EE5D5C930C607C6254DFA0AFEC932FF020D21"; - attribute INIT_2B of inst : label is "35FF071824B80C464835FF0920A7F5C9D1E12546CD47256EF214FEAF012010FE"; - attribute INIT_2C of inst : label is "50CD672003CD78253DCD464811E22815FE3E2818FE2550CD00002124BB0C4648"; - attribute INIT_2D of inst : label is "6F2003CD78253DCDC62815FE2550CDF5C90120A7F167B07C253DCDD02815FE25"; - attribute INIT_2E of inst : label is "CD2516CD24FFCDC9F9203DFE10FF06FF3EC9F16FB07D253DCDB72815FE2550CD"; - attribute INIT_2F of inst : label is "16CD24FFCD25CFCDFFD37CE52571CDAF252ECD24FFCDFD187E2571CD013E251E"; - attribute INIT_30 of inst : label is "CDAF24760C320435FF2526CD24FFCDFD1870C12571CD013E245B0C320435FF25"; - attribute INIT_31 of inst : label is "CD25CFCDFFD37CE52571CDAF24800C320435FF2526CD24FFCDFC1878ED4C2571"; - attribute INIT_32 of inst : label is "25CFCDFFD37CE52571CDAF252ECD24FFCDFC1861ED48C12571CDAF252ECD24FF"; - attribute INIT_33 of inst : label is "2126FBCD0A041124C02124FFCDFC187E70C12571CD013E251ECD2516CD24FFCD"; - attribute INIT_34 of inst : label is "11CD321C1110DBFB0ED3033E0DD37D47ED7C20102108AF0826FBCD00501124D8"; - attribute INIT_35 of inst : label is "11CD00681114DB2711CD501C1113DB2711CD461C1112DB2711CD3C1C1111DB27"; - attribute INIT_36 of inst : label is "11CD3268111CDB2711CD1E681117DB2711CD14681116DB2711CD0A681115DB27"; - attribute INIT_37 of inst : label is "3DCD7E03069E182711CD5068111FDB2711CD4668111EDB2711CD3C68111DDB27"; - attribute INIT_38 of inst : label is "E67C253DCD2546CD0F0F0F0FF0E667C9EB205AFE570AC67A5F18D67BF9102325"; - attribute INIT_39 of inst : label is "CD141C1108D60FDB2711CD0A1C113FCB0EDB081728A708F3C9253DCD2546CD0F"; - attribute INIT_3A of inst : label is "ED7C201221B0ED0FDC01400021B0ED00140127A621400011FA18083CC9FB2711"; - attribute INIT_3B of inst : label is "02D33C01D33C00D3F376FB59ED043E500021200011F80F0109D3143E0DD37D47"; - attribute INIT_3C of inst : label is "043E20001127A0C2151C1C1C1C1C1C09C607D33C06D33C05D33C04D3A003D33C"; - attribute INIT_3D of inst : label is "2516CD24FFCDFFFFFFFFFFAAAAAAAAAA5555555555000000000076FBE1DD59ED"; - attribute INIT_3E of inst : label is "0C320435FF24950C280435FF24FFCD25CFCDE5E52571CD013E248B0C320435FF"; - attribute INIT_3F of inst : label is "37EA18D513127CD1E9E1E1032018FE782571CDAF25CFCD24F30C5A0435FF24A5"; - begin - inst : RAMB16_S9 - --pragma translate_off - generic map ( - INITP_00 => x"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => x"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => x"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => x"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => x"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => x"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => x"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => x"0000000000000000000000000000000000000000000000000000000000000000", - - INIT_00 => romgen_str2bv(inst'INIT_00), - INIT_01 => romgen_str2bv(inst'INIT_01), - INIT_02 => romgen_str2bv(inst'INIT_02), - INIT_03 => romgen_str2bv(inst'INIT_03), - INIT_04 => romgen_str2bv(inst'INIT_04), - INIT_05 => romgen_str2bv(inst'INIT_05), - INIT_06 => romgen_str2bv(inst'INIT_06), - INIT_07 => romgen_str2bv(inst'INIT_07), - INIT_08 => romgen_str2bv(inst'INIT_08), - INIT_09 => romgen_str2bv(inst'INIT_09), - INIT_0A => romgen_str2bv(inst'INIT_0A), - INIT_0B => romgen_str2bv(inst'INIT_0B), - INIT_0C => romgen_str2bv(inst'INIT_0C), - INIT_0D => romgen_str2bv(inst'INIT_0D), - INIT_0E => romgen_str2bv(inst'INIT_0E), - INIT_0F => romgen_str2bv(inst'INIT_0F), - INIT_10 => romgen_str2bv(inst'INIT_10), - INIT_11 => romgen_str2bv(inst'INIT_11), - INIT_12 => romgen_str2bv(inst'INIT_12), - INIT_13 => romgen_str2bv(inst'INIT_13), - INIT_14 => romgen_str2bv(inst'INIT_14), - INIT_15 => romgen_str2bv(inst'INIT_15), - INIT_16 => romgen_str2bv(inst'INIT_16), - INIT_17 => romgen_str2bv(inst'INIT_17), - INIT_18 => romgen_str2bv(inst'INIT_18), - INIT_19 => romgen_str2bv(inst'INIT_19), - INIT_1A => romgen_str2bv(inst'INIT_1A), - INIT_1B => romgen_str2bv(inst'INIT_1B), - INIT_1C => romgen_str2bv(inst'INIT_1C), - INIT_1D => romgen_str2bv(inst'INIT_1D), - INIT_1E => romgen_str2bv(inst'INIT_1E), - INIT_1F => romgen_str2bv(inst'INIT_1F), - INIT_20 => romgen_str2bv(inst'INIT_20), - INIT_21 => romgen_str2bv(inst'INIT_21), - INIT_22 => romgen_str2bv(inst'INIT_22), - INIT_23 => romgen_str2bv(inst'INIT_23), - INIT_24 => romgen_str2bv(inst'INIT_24), - INIT_25 => romgen_str2bv(inst'INIT_25), - INIT_26 => romgen_str2bv(inst'INIT_26), - INIT_27 => romgen_str2bv(inst'INIT_27), - INIT_28 => romgen_str2bv(inst'INIT_28), - INIT_29 => romgen_str2bv(inst'INIT_29), - INIT_2A => romgen_str2bv(inst'INIT_2A), - INIT_2B => romgen_str2bv(inst'INIT_2B), - INIT_2C => romgen_str2bv(inst'INIT_2C), - INIT_2D => romgen_str2bv(inst'INIT_2D), - INIT_2E => romgen_str2bv(inst'INIT_2E), - INIT_2F => romgen_str2bv(inst'INIT_2F), - INIT_30 => romgen_str2bv(inst'INIT_30), - INIT_31 => romgen_str2bv(inst'INIT_31), - INIT_32 => romgen_str2bv(inst'INIT_32), - INIT_33 => romgen_str2bv(inst'INIT_33), - INIT_34 => romgen_str2bv(inst'INIT_34), - INIT_35 => romgen_str2bv(inst'INIT_35), - INIT_36 => romgen_str2bv(inst'INIT_36), - INIT_37 => romgen_str2bv(inst'INIT_37), - INIT_38 => romgen_str2bv(inst'INIT_38), - INIT_39 => romgen_str2bv(inst'INIT_39), - INIT_3A => romgen_str2bv(inst'INIT_3A), - INIT_3B => romgen_str2bv(inst'INIT_3B), - INIT_3C => romgen_str2bv(inst'INIT_3C), - INIT_3D => romgen_str2bv(inst'INIT_3D), - INIT_3E => romgen_str2bv(inst'INIT_3E), - INIT_3F => romgen_str2bv(inst'INIT_3F) - ) - --pragma translate_on - port map ( - DO => DATA(7 downto 0), - DOP => open, - ADDR => rom_addr, - CLK => CLK, - DI => "00000000", - DIP => "0", - EN => ENA, - SSR => '0', - WE => '0' - ); - end generate; -end RTL; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bios3159_0.bin b/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bios3159_0.bin deleted file mode 100644 index d35d6a30..00000000 Binary files a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bios3159_0.bin and /dev/null differ diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bios3159_0.hex b/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bios3159_0.hex deleted file mode 100644 index 0968c853..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/roms/bios3159_0.hex +++ /dev/null @@ -1,257 +0,0 @@ -:1000000000F3AFD308C3610CC307201C3C1C20FFC6 -:10001000C30A2006FA0762FFC30D20FB7610FDC954 -:10002000C31020732372C9FFC31320210000C9FF2E -:10003000C31620008B0101FFE3F5C5D5DDE5FDE525 -:10004000FD210000FD397E23117A021F3836E5D5E7 -:1000500021CB00075F16001730032AFD4F195E23DE -:1000600056D5FD660BFD6E0AFD5603FD5E02D5DD1D -:10007000E1FD7E09FD5605FD5E04C9D1E17E23CB7D -:100080003F117C00D54F3012EB0600214B01CB779E -:1000900028032AFB4F0946CDA800D179FD4607FD6C -:1000A0004E0618AAE1D123E5CB60280A1A13FD7782 -:1000B000021A13FD7703FDE5E123232323CBA0CB15 -:1000C0003830031A13772320F6EBC97B007902320C -:1000D000067D00730BC40AA4008B017E040805FC96 -:1000E00005CF03DB01EE0AB206FE060B0715071962 -:1000F000071C077D079E07B903AD076A02E107C425 -:1001000007EB0BF60AFB0A56063306C90AAC010CCC -:10011000060B06BA01970CFB0C310D1B00CC0B151E -:100120000C760B900BAC0BBD0B4B0BAA0D21031FD8 -:1001300003DE028402640341036E03290356034C69 -:10014000037F03410C6C03230040020000C0C00089 -:10015000C0080004F0002AC02F2FD0E3E3EFEF1314 -:10016000CBCFC3CF27C7CF2020D4D00003C0C0003F -:10017000C3ECCF0807C0C0C0C0C0CFC8CBCBCBCB6F -:10018000C80BCB0B0BC82000E0C3C7F3F5C5D5E502 -:10019000ED5E3E00ED473EC8D30F3E34D30DCDA0FB -:1001A000040E0FCD7E04E1D1C1F1FBC93AFA4FFE36 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Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/spram.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/spram.vhd deleted file mode 100644 index d86010fc..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/spram.vhd +++ /dev/null @@ -1,91 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY spram IS - GENERIC - ( - init_file : string := ""; - --numwords_a : natural; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - power_up_uninitialized : STRING; - read_during_write_mode_port_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - wren_a : IN STD_LOGIC ; - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - wren_a => wren, - clock0 => clock, - address_a => address, - data_a => data, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/sprom.vhd b/Console_MiST/Bally - Astrocade_MiST/rtl/sprom.vhd deleted file mode 100644 index 292a214f..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/sprom.vhd +++ /dev/null @@ -1,83 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - --numwords_a : natural; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Console_MiST/Bally - Astrocade_MiST/rtl/video_mixer.sv b/Console_MiST/Bally - Astrocade_MiST/rtl/video_mixer.sv deleted file mode 100644 index ec953e53..00000000 --- a/Console_MiST/Bally - Astrocade_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,242 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd7, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Console_MiST/Coleco - Vision_MiST/ColecoVision_MiST.qpf b/Console_MiST/Coleco - Vision_MiST/ColecoVision_MiST.qpf deleted file mode 100644 index 44433ccb..00000000 --- a/Console_MiST/Coleco - Vision_MiST/ColecoVision_MiST.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 12:51:57 September 10, 2018 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "13.0" -DATE = "12:51:57 September 10, 2018" - -# Revisions -PROJECT_REVISION = "ColecoVision_MiST" diff --git a/Console_MiST/Coleco - Vision_MiST/ColecoVision_MiST.qsf b/Console_MiST/Coleco - Vision_MiST/ColecoVision_MiST.qsf deleted file mode 100644 index 56b3846b..00000000 --- a/Console_MiST/Coleco - Vision_MiST/ColecoVision_MiST.qsf +++ /dev/null @@ -1,238 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version -# Date created = 10:10:49 September 11, 2018 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# ColecoVision_MiST_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:07:56 MARCH 10, 2017" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_top.vhd -set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_tone.vhd -set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_noise.vhd -set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_latch_ctrl.vhd -set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_comp_pack.vhd -set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_clock_div.vhd -set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_attenuator.vhd -set_global_assignment -name VHDL_FILE rtl/vdp18/vdp18_sprite.vhd -set_global_assignment -name VHDL_FILE rtl/vdp18/vdp18_pattern.vhd -set_global_assignment -name VHDL_FILE "rtl/vdp18/vdp18_pack-p.vhd" -set_global_assignment -name VHDL_FILE rtl/vdp18/vdp18_hor_vert.vhd -set_global_assignment -name VHDL_FILE rtl/vdp18/vdp18_ctrl.vhd -set_global_assignment -name VHDL_FILE rtl/vdp18/vdp18_cpuio.vhd -set_global_assignment -name VHDL_FILE "rtl/vdp18/vdp18_core_comp_pack-p.vhd" -set_global_assignment -name VHDL_FILE rtl/vdp18/vdp18_core.vhd -set_global_assignment -name VHDL_FILE "rtl/vdp18/vdp18_comp_pack-p.vhd" -set_global_assignment -name VHDL_FILE "rtl/vdp18/vdp18_col_pack-p.vhd" -set_global_assignment -name VHDL_FILE rtl/vdp18/vdp18_col_mux.vhd -set_global_assignment -name VHDL_FILE rtl/vdp18/vdp18_clk_gen.vhd -set_global_assignment -name VHDL_FILE rtl/vdp18/vdp18_addr_mux.vhd -set_global_assignment -name VHDL_FILE rtl/T80/t80a.vhd -set_global_assignment -name VHDL_FILE rtl/T80/t80_reg.vhd -set_global_assignment -name VHDL_FILE rtl/T80/t80_pack.vhd -set_global_assignment -name VHDL_FILE rtl/T80/t80_mcode.vhd -set_global_assignment -name VHDL_FILE rtl/T80/t80_alu.vhd -set_global_assignment -name VHDL_FILE rtl/T80/t80.vhd -set_global_assignment -name VHDL_FILE rtl/colecovision.vhd -set_global_assignment -name VHDL_FILE rtl/cv_ctrl.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/ColecoVision_MiST.sv -set_global_assignment -name VHDL_FILE rtl/clocks.vhd -set_global_assignment -name VHDL_FILE rtl/cvBios.vhd -set_global_assignment -name VHDL_FILE rtl/dpSDRAM64Mb.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name VERILOG_FILE rtl/mist_io.v -set_global_assignment -name VERILOG_FILE rtl/osd.v -set_global_assignment -name VERILOG_FILE rtl/scandoubler.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name VHDL_FILE rtl/dac.vhd -set_global_assignment -name VHDL_FILE rtl/keyboard.vhd -set_global_assignment -name VHDL_FILE rtl/ps2kbd.vhd -set_global_assignment -name VHDL_FILE rtl/ps2kbd_pkg.vhd -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name QIP_FILE rtl/cart.qip - -# Pin & Location Assignments -# ========================== -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_54 -to CLOCK_27 -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_13 -to CONF_DATA0 -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" - -# Classic Timing Assignments -# ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY ColecoVision_MiST -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON - -# Power Estimation Assignments -# ============================ -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" - -# Advanced I/O Timing Assignments -# =============================== -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -# start EDA_TOOL_SETTINGS(eda_simulation) -# --------------------------------------- - - # EDA Netlist Writer Assignments - # ============================== - set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -# end EDA_TOOL_SETTINGS(eda_simulation) -# ------------------------------------- - -# ------------------------------- -# start ENTITY(ColecoVision_MiST) - - # start DESIGN_PARTITION(Top) - # --------------------------- - - # Incremental Compilation Assignments - # =================================== - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top - set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top - set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - - # end DESIGN_PARTITION(Top) - # ------------------------- - -# end ENTITY(ColecoVision_MiST) -# ----------------------------- -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Console_MiST/Coleco - Vision_MiST/ColecoVision_MiST.srf b/Console_MiST/Coleco - Vision_MiST/ColecoVision_MiST.srf deleted file mode 100644 index 87f3faf9..00000000 --- a/Console_MiST/Coleco - Vision_MiST/ColecoVision_MiST.srf +++ /dev/null @@ -1,9 +0,0 @@ -{ "" "" "" "Verilog HDL or VHDL warning at vdp18_ctrl.vhd(156): conditional expression evaluates to a constant" { } { } 0 10037 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL information at scandoubler.v(102): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Output pins are stuck at VCC or GND" { } { } 0 13024 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Tri-state node(s) do not directly drive top-level pin(s)" { } { } 0 13046 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "5 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13049 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 13410 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/Console_MiST/Coleco - Vision_MiST/README.txt b/Console_MiST/Coleco - Vision_MiST/README.txt deleted file mode 100644 index 560080bb..00000000 --- a/Console_MiST/Coleco - Vision_MiST/README.txt +++ /dev/null @@ -1,3 +0,0 @@ -Coleco Vision Port to Mist FPGA by Gehstock - -32k Roms will not work at this Time \ No newline at end of file diff --git a/Console_MiST/Coleco - Vision_MiST/Snapshot/ColecoVision_MiST.rbf b/Console_MiST/Coleco - Vision_MiST/Snapshot/ColecoVision_MiST.rbf deleted file mode 100644 index 63b9885e..00000000 Binary files a/Console_MiST/Coleco - Vision_MiST/Snapshot/ColecoVision_MiST.rbf and /dev/null differ diff --git a/Console_MiST/Coleco - Vision_MiST/clean.bat b/Console_MiST/Coleco - Vision_MiST/clean.bat deleted file mode 100644 index 748b4d5b..00000000 --- a/Console_MiST/Coleco - Vision_MiST/clean.bat +++ /dev/null @@ -1,38 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del *.cdf -del *.rpt -del /s new_rtl_netlist -del /s old_rtl_netlist -pause diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/ColecoVision_MiST.sv b/Console_MiST/Coleco - Vision_MiST/rtl/ColecoVision_MiST.sv deleted file mode 100644 index ccafeb3b..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/ColecoVision_MiST.sv +++ /dev/null @@ -1,423 +0,0 @@ -module ColecoVision_MiST( - input CLOCK_27, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_HS, - output VGA_VS, - output LED, - output AUDIO_L, - output AUDIO_R, - input SPI_SCK, - output SPI_DO, - input SPI_DI, - input SPI_SS2, - input SPI_SS3, - input CONF_DATA0, - output [12:0] SDRAM_A, - inout [15:0] SDRAM_DQ, - output SDRAM_DQML, - output SDRAM_DQMH, - output SDRAM_nWE, - output SDRAM_nCAS, - output SDRAM_nRAS, - output SDRAM_nCS, - output [1:0] SDRAM_BA, - output SDRAM_CLK, - output SDRAM_CKE - ); - -`include "build_id.v" -localparam CONF_STR = -{ - "CVision;;", - "F,COLBINROM;", - "O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", - "O4,Switch Joystick,Off,On;", - "T6,Reset;", - "V,v1.0.",`BUILD_DATE -}; - - -wire clk_sys, clk_pix, clock_mem_s; -wire clock_vdp_en_s, clock_5m_en_s, clock_3m_en_s; -wire pll_locked_s; -wire reset_s = status[0] | status[6] | buttons[1] | ioctl_download; -wire [7:0]r, g, b; -wire hs, vs; -wire ypbpr; -wire [31:0]status; -wire scandoubler_disable; -wire [1:0] buttons, switches; -wire [7:0]audio; -assign SDRAM_A[12] = 1'b0; -assign LED = ~ioctl_download; -wire ioctl_download; -wire [7:0] ioctl_index; -wire ioctl_ce, ioctl_wr; -wire [24:0] ioctl_addr; -wire [7:0] ioctl_dout; -wire [7:0] joy1, joy2; -wire [7:0] joya = status[4] ? joy2 : joy1; -wire [7:0] joyb = status[4] ? joy1 : joy2; -wire [1:0]ctrl_p1_s; -wire [1:0]ctrl_p2_s; -wire [1:0]ctrl_p3_s; -wire [1:0]ctrl_p4_s; -wire [1:0]ctrl_p5_s; -wire [1:0]ctrl_p6_s; -wire [1:0]ctrl_p7_s = 2'b11; -wire [1:0]ctrl_p8_s; -wire [1:0]ctrl_p9_s = 2'b11; -wire [14:0]cart_addr; -wire [7:0]cart_do; -wire cart_en_80_n_s; -wire cart_en_a0_n_s; -wire cart_en_c0_n_s; -wire cart_en_e0_n_s; -wire [10:0]ps2_key; -wire pressed = ps2_key[9]; -wire [8:0] code = ps2_key[8:0]; -wire [16:0]ram_addr_s;//128K ??? -wire [7:0]ram_do_s; -wire [7:0]ram_di_s; -wire ram_ce_s; -wire ram_oe_s; -wire ram_we_s; -wire [13:0]vram_addr_s;//16K -wire [7:0]vram_do_s; -wire [7:0]vram_di_s; -wire vram_ce_s; -wire vram_oe_s; -wire vram_we_s; - -pll pll ( - .inclk0 (CLOCK_27), - .c0 (clk_sys),//21.428571 - .c1 (clk_pix),//5.35714275 - .c2 (clock_mem_s),//100 MHz 0º - .c3 (SDRAM_CLK),// 100 MHz -90° - .locked (pll_locked_s) - ); - -clocks clocks ( - .clock_i (clk_sys), - .por_i (~pll_locked_s), - .clock_vdp_en_o(clock_vdp_en_s), - .clock_5m_en_o (clock_5m_en_s), - .clock_3m_en_o (clock_3m_en_s) - ); - -colecovision #( - .num_maq_g (5), - .compat_rgb_g (0)) -colecovision ( - .clock_i (clk_sys), - .clk_en_10m7_i (clock_vdp_en_s), - .clk_en_5m37_i (clock_5m_en_s), - .clk_en_3m58_i (clock_3m_en_s), - .reset_i (reset_s), - .por_n_i (pll_locked_s), -//Controller Interface - .ctrl_p1_i (ctrl_p1_s), - .ctrl_p2_i (ctrl_p2_s), - .ctrl_p3_i (ctrl_p3_s), - .ctrl_p4_i (ctrl_p4_s), - .ctrl_p5_o (ctrl_p5_s), - .ctrl_p6_i (ctrl_p6_s), - .ctrl_p7_i (ctrl_p7_s), - .ctrl_p8_o (ctrl_p8_s), - .ctrl_p9_i (ctrl_p9_s), -//CPU RAM Interface - .ram_addr_o (ram_addr_s), - .ram_ce_o (ram_ce_s), - .ram_we_o (ram_we_s), - .ram_oe_o (ram_oe_s), - .ram_data_i (ram_do_s), - .ram_data_o (ram_di_s), -//Video RAM Interface - .vram_addr_o (vram_addr_s), - .vram_ce_o (vram_ce_s), - .vram_oe_o (vram_oe_s), - .vram_we_o (vram_we_s), - .vram_data_i (vram_do_s), - .vram_data_o (vram_di_s), -//Cartridge ROM Interface - .cart_addr_o (cart_addr), - .cart_data_i (cart_do), - .cart_en_80_n_o (cart_en_80_n_s), - .cart_en_a0_n_o (cart_en_a0_n_s), - .cart_en_c0_n_o (cart_en_c0_n_s), - .cart_en_e0_n_o (cart_en_e0_n_s), -//Audio Interface - .audio_o (audio), -//RGB Video Interface - .col_o (), - .rgb_r_o (r), - .rgb_g_o (g), - .rgb_b_o (b), - .hsync_n_o (hs), - .vsync_n_o (vs), - .comp_sync_n_o (), -//DEBUG - .D_cpu_addr () - ); - -dac #( - .msbi_g (15)) -dac ( - .clk_i (clk_sys), - .res_i (reset_s), - .dac_i ({~audio[7], audio[6:0], 8'b00000000}), - .dac_o (AUDIO_L) - ); - -assign AUDIO_R = AUDIO_L; - -dpSDRAM64Mb #( - .freq_g (100)) -dpSDRAM64Mb ( - .clock_i (clock_mem_s), - .reset_i (reset_s), - .refresh_i (1'b1), -//Port 0 - .port0_cs_i (vram_ce_s), - .port0_oe_i (vram_oe_s), - .port0_we_i (vram_we_s), - .port0_addr_i ({"000011111",vram_addr_s}), - .port0_data_i (vram_di_s), - .port0_data_o (vram_do_s), -//Port 1 - .port1_cs_i (ram_ce_s), - .port1_oe_i (ram_oe_s), - .port1_we_i (ram_we_s), - .port1_addr_i ({"000000",ram_addr_s}), - .port1_data_i (ram_di_s), - .port1_data_o (ram_do_s), -//SDRAM in board - .mem_cke_o (SDRAM_CKE), - .mem_cs_n_o (SDRAM_nCS), - .mem_ras_n_o (SDRAM_nRAS), - .mem_cas_n_o (SDRAM_nCAS), - .mem_we_n_o (SDRAM_nWE), - .mem_udq_o (SDRAM_DQMH), - .mem_ldq_o (SDRAM_DQML), - .mem_ba_o (SDRAM_BA), - .mem_addr_o (SDRAM_A[11:0]), - .mem_data_io (SDRAM_DQ) - ); - -cart cart ( - .clock(clk_sys), - .address(ioctl_download ? ioctl_addr[14:0] : cart_addr), - .data(ioctl_dout), - .wren(ioctl_wr), - .q(cart_do) - ); - - -always @(posedge clk_sys) begin - reg old_state; - old_state <= ps2_key[10]; - - if(old_state != ps2_key[10]) begin - casex(code) - 'hX75: btn_up <= pressed; - 'hX72: btn_down <= pressed; - 'hX6B: btn_left <= pressed; - 'hX74: btn_right <= pressed; - 'hX16: btn_1 <= pressed; // 1 - 'hX1E: btn_2 <= pressed; // 2 - 'hX26: btn_3 <= pressed; // 3 - 'hX15: btn_4 <= pressed; // q - 'hX1D: btn_5 <= pressed; // w - 'hX24: btn_6 <= pressed; // e - 'hX1C: btn_7 <= pressed; // a - 'hX1B: btn_8 <= pressed; // s - 'hX23: btn_9 <= pressed; // d - 'hX1A: btn_s <= pressed; // z - 'hX22: btn_0 <= pressed; // x - 'hX21: btn_p <= pressed; // c - 'hX1F: btn_pt <= pressed; // gui l - 'hX27: btn_pt <= pressed; // gui r - 'hX11: btn_bt <= pressed; // alt - - 'hX25: btn_4 <= pressed; // 4 - 'hX2E: btn_5 <= pressed; // 5 - 'hX36: btn_6 <= pressed; // 6 - 'hX3D: btn_7 <= pressed; // 7 - 'hX3E: btn_8 <= pressed; // 8 - 'hX46: btn_9 <= pressed; // 9 - 'hX45: btn_0 <= pressed; // 0 - - 'h012: btn_arm <= pressed; // shift l - 'h059: btn_arm <= pressed; // shift r - 'hX14: btn_fire <= pressed; // ctrl - endcase - end -end - -reg btn_up = 0; -reg btn_down = 0; -reg btn_left = 0; -reg btn_right = 0; -reg btn_1 = 0; -reg btn_2 = 0; -reg btn_3 = 0; -reg btn_4 = 0; -reg btn_5 = 0; -reg btn_6 = 0; -reg btn_7 = 0; -reg btn_8 = 0; -reg btn_9 = 0; -reg btn_s = 0; -reg btn_0 = 0; -reg btn_p = 0; -reg btn_pt = 0; -reg btn_bt = 0; -reg btn_arm = 0; -reg btn_fire = 0; - -wire m_right = btn_right | joya[0]; -wire m_left = btn_left | joya[1]; -wire m_down = btn_down | joya[2]; -wire m_up = btn_up | joya[3]; -wire m_fire = btn_fire | joya[4]; -wire m_arm = btn_arm | joya[5]; -wire m_1 = btn_1; -wire m_2 = btn_2; -wire m_3 = btn_3; -wire m_s = btn_s | joya[6]; -wire m_0 = btn_0; -wire m_p = btn_p | joya[7]; -wire m_pt = btn_pt; -wire m_bt = btn_bt; - -wire [0:19] keypad0 = {m_0,m_1,m_2, m_3,btn_4,btn_5, btn_6,btn_7,btn_8, btn_9,m_s,m_p, m_pt,m_bt,m_up, m_down,m_left,m_right, m_fire,m_arm}; -wire [0:19] keypad1 = {1'b0,1'b0,1'b0, 1'b0,1'b0,1'b0, 1'b0,1'b0,1'b0, 1'b0,joyb[6],joyb[7], 1'b0,1'b0,joyb[3], joyb[2],joyb[1],joyb[0], joyb[4],joyb[5]}; -wire [0:19] keypad[2] = '{keypad0,keypad1}; - -reg [3:0] ctrl1[2] = '{'0,'0}; -assign {ctrl_p1_s[0],ctrl_p2_s[0],ctrl_p3_s[0],ctrl_p4_s[0]} = ctrl1[0]; -assign {ctrl_p1_s[1],ctrl_p2_s[1],ctrl_p3_s[1],ctrl_p4_s[1]} = ctrl1[1]; - -localparam cv_key_0_c = 4'b0011; -localparam cv_key_1_c = 4'b1110; -localparam cv_key_2_c = 4'b1101; -localparam cv_key_3_c = 4'b0110; -localparam cv_key_4_c = 4'b0001; -localparam cv_key_5_c = 4'b1001; -localparam cv_key_6_c = 4'b0111; -localparam cv_key_7_c = 4'b1100; -localparam cv_key_8_c = 4'b1000; -localparam cv_key_9_c = 4'b1011; -localparam cv_key_asterisk_c = 4'b1010; -localparam cv_key_number_c = 4'b0101; -localparam cv_key_pt_c = 4'b0100; -localparam cv_key_bt_c = 4'b0010; -localparam cv_key_none_c = 4'b1111; - -generate - genvar i; - for (i = 0; i <= 1; i++) begin : ctl - always_comb begin - reg [3:0] ctl1, ctl2; - reg p61,p62; - - ctl1 = 4'b1111; - ctl2 = 4'b1111; - p61 = 1; - p62 = 1; - - if (~ctrl_p5_s[i]) begin - casex(keypad[i][0:13]) - 'b1xxxxxxxxxxxxx: ctl1 = cv_key_0_c; - 'b01xxxxxxxxxxxx: ctl1 = cv_key_1_c; - 'b001xxxxxxxxxxx: ctl1 = cv_key_2_c; - 'b0001xxxxxxxxxx: ctl1 = cv_key_3_c; - 'b00001xxxxxxxxx: ctl1 = cv_key_4_c; - 'b000001xxxxxxxx: ctl1 = cv_key_5_c; - 'b0000001xxxxxxx: ctl1 = cv_key_6_c; - 'b00000001xxxxxx: ctl1 = cv_key_7_c; - 'b000000001xxxxx: ctl1 = cv_key_8_c; - 'b0000000001xxxx: ctl1 = cv_key_9_c; - 'b00000000001xxx: ctl1 = cv_key_asterisk_c; - 'b000000000001xx: ctl1 = cv_key_number_c; - 'b0000000000001x: ctl1 = cv_key_pt_c; - 'b00000000000001: ctl1 = cv_key_bt_c; - 'b00000000000000: ctl1 = cv_key_none_c; - endcase - p61 = ~keypad[i][19]; // button 2 - end - - if (~ctrl_p8_s[i]) begin - ctl2 = ~keypad[i][14:17]; - p62 = ~keypad[i][18]; // button 1 - end - - ctrl1[i] = ctl1 & ctl2; - ctrl_p6_s[i] = p61 & p62; - end - end -endgenerate - - - -mist_io #( - .STRLEN ($size(CONF_STR)>>3) - ) -user_io ( - .clk_sys (clk_sys ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SCK (SPI_SCK ), - .SPI_DI (SPI_DI ), - .SPI_DO (SPI_DO ), - .SPI_SS2 (SPI_SS2 ), - .conf_str (CONF_STR ), - .ypbpr (ypbpr ), - .status (status ), - .scandoubler_disable(scandoubler_disable), - .buttons (buttons ), - .switches (switches ), - .ps2_key (ps2_key ), - .joystick_0 (joy1 ), - .joystick_1 (joy2 ), - .ioctl_ce (ioctl_ce ), - .ioctl_wr (ioctl_wr ), - .ioctl_index (ioctl_index ), - .ioctl_download(ioctl_download), - .ioctl_addr (ioctl_addr ), - .ioctl_dout (ioctl_dout ) - ); - -video_mixer #( - .LINE_LENGTH (290 ), - .HALF_DEPTH (0 ) - ) -video_mixer ( - .clk_sys (clk_sys ), - .ce_pix (clk_pix ), - .ce_pix_actual (clk_pix ), - .SPI_SCK (SPI_SCK ), - .SPI_SS3 (SPI_SS3 ), - .SPI_DI (SPI_DI ), - .R (r[7:2]), - .G (g[7:2]), - .B (b[7:2]), - .HSync (hs ), - .VSync (vs ), - .VGA_R (VGA_R ), - .VGA_G (VGA_G ), - .VGA_B (VGA_B ), - .VGA_VS (VGA_VS ), - .VGA_HS (VGA_HS ), - .scanlines (scandoubler_disable ? 2'b00 : {status[3:2] == 3, status[3:2] == 2}), - .scandoubler_disable(scandoubler_disable), - .hq2x (status[3:2]==1), - .ypbpr (ypbpr ), - .ypbpr_full (1 ), - .line_start (0 ), - .mono (0 ) - ); - -endmodule \ No newline at end of file diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/ColecoVision_MiST.sv.bak b/Console_MiST/Coleco - Vision_MiST/rtl/ColecoVision_MiST.sv.bak deleted file mode 100644 index 4b5e55ed..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/ColecoVision_MiST.sv.bak +++ /dev/null @@ -1,84 +0,0 @@ -module ColecoVision_MiST( - input CLOCK_27 - -); - -wire clock_master_s, clock_mem_s, sdram_clock_o; -wire pll_locked_s; - -pll pll ( - .inclk0 (CLOCK_27), - .c0 (clock_master_s),//21.428571 - .c1 (clock_mem_s),//100 MHz 0º - .c2 (sdram_clock_o),// 100 MHz -90° - .locked (pll_locked_s) - ); - -wire por_n_s; -wire clock_vdp_en_s, clock_5m_en_s, clock_3m_en_s; - -clocks clocks ( - .clock_i (clock_master_s), - .por_i (~por_n_s), - .clock_vdp_en_o(clock_vdp_en_s), - .clock_5m_en_o (clock_5m_en_s), - .clock_3m_en_o (clock_3m_en_s) - ); - -colecovision #( - .num_maq_g (5), - .compat_rgb_g (0)) -colecovision ( - .clock_i (clock_master_s), - .clk_en_10m7_i (clock_vdp_en_s), - .clk_en_5m37_i (clock_5m_en_s), - .clk_en_3m58_i (clock_3m_en_s), - .reset_i (reset_s), - .por_n_i (por_n_s), -//Controller Interface - .ctrl_p1_i => ctrl_p1_s, - .ctrl_p2_i => ctrl_p2_s, - .ctrl_p3_i => ctrl_p3_s, - .ctrl_p4_i => ctrl_p4_s, - .ctrl_p5_o => ctrl_p5_s, - .ctrl_p6_i => ctrl_p6_s, - .ctrl_p7_i => ctrl_p7_s, - .ctrl_p8_o => ctrl_p8_s, - .ctrl_p9_i => ctrl_p9_s, -//CPU RAM Interface - .ram_addr_o => ram_addr_s, - .ram_ce_o => ram_ce_s, - .ram_we_o => ram_we_s, - .ram_oe_o => ram_oe_s, - .ram_data_i => d_from_ram_s, - .ram_data_o => d_to_ram_s, -//Video RAM Interface - .vram_addr_o => vram_addr_s, - .vram_ce_o => vram_ce_s, - .vram_oe_o => vram_oe_s, - .vram_we_o => vram_we_s, - .vram_data_i => vram_do_s, - .vram_data_o => vram_di_s, -//Cartridge ROM Interface - .cart_addr_o => open, - .cart_data_i => (others => '1'), - .cart_en_80_n_o => open, - .cart_en_a0_n_o => open, - .cart_en_c0_n_o => open, - .cart_en_e0_n_o => open, -//Audio Interface - .audio_o => open, - .audio_signed_o => audio_signed_s, -//RGB Video Interface - .col_o => rgb_col_s, - .rgb_r_o => open, - .rgb_g_o => open, - .rgb_b_o => open, - .hsync_n_o => rgb_hsync_n_s, - .vsync_n_o => rgb_vsync_n_s, - .comp_sync_n_o => open, -//DEBUG - .D_cpu_addr () - ); - -endmodule \ No newline at end of file diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80.vhd deleted file mode 100644 index 18a053a3..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80.vhd +++ /dev/null @@ -1,1094 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0249 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- --- 0248 : add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- --- 0249 : add undocumented XY-Flags for CPI/CPD by TobiFlex 22.07.2012 --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal ALU_cpi_r : std_logic; - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal ALU_cpi : std_logic; - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - ALU_cpi => ALU_cpi, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_cpi => ALU_cpi_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - ALU_cpi_r <= '0'; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - ALU_cpi_r <= '0'; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_cpi_r <= ALU_cpi; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 and Auto_Wait_t1 = '0' then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if T_Res = '1' then - Auto_Wait_t1 <= '0'; - else - Auto_Wait_t1 <= Auto_Wait or IORQ_i; - end if; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor - (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_alu.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_alu.vhd deleted file mode 100644 index ce8f9755..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_alu.vhd +++ /dev/null @@ -1,362 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0249 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- --- 0249 : add undocumented XY-Flags for CPI/CPD by TobiFlex 22.07.2012 --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_cpi : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - signal Q_cpi : std_logic_vector(4 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - AddSub(BusA(3 downto 0), BusB(3 downto 0), '1', HalfCarry_v, Q_cpi(3 downto 0), Q_cpi(4)); - - process (Arith16, ALU_OP, ALU_cpi, F_In, BusA, BusB, IR, Q_v, Q_cpi, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - if ALU_cpi='1' then --CPI - F_Out(Flag_X) <= Q_cpi(3); - F_Out(Flag_Y) <= Q_cpi(1); - else - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; - -end; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_mcode.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_mcode.vhd deleted file mode 100644 index 5b18e674..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_mcode.vhd +++ /dev/null @@ -1,2014 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0249 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes --- --- 0242 : Fixed I/O instruction timing, cleanup --- --- 0242a: 31st of August, 2003 by Kazuhiro Tsujikawa (tujikawa@hat.hi-ho.ne.jp) --- Fixed INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR instructions --- --- 0248 : add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- --- 0249 : add undocumented XY-Flags for CPI/CPD by TobiFlex 22.07.2012 --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - ALU_cpi : out std_logic; --for undoc XY-Flags - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - ALU_cpi <= '0'; - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - ALU_cpi <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- 0242a - else - IncDec_16 <= "1110"; -- 0242a - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- 0242a - else - IncDec_16 <= "1110"; -- 0242a - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_pack.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_pack.vhd deleted file mode 100644 index 95a03bea..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_pack.vhd +++ /dev/null @@ -1,212 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - ALU_cpi : out std_logic; - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_cpi : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_reg.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_reg.vhd deleted file mode 100644 index 52417e36..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80_reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80a.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80a.vhd deleted file mode 100644 index 77293494..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/T80/t80a.vhd +++ /dev/null @@ -1,286 +0,0 @@ --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247a (+k01) --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- --- 0247a: 7th of September, 2003 by Kazuhiro Tsujikawa (tujikawa@hat.hi-ho.ne.jp) --- Fixed IORQ_n, RD_n, WR_n bus timing --- -------------------------------------------------------------------------------- --- +k01 : 2010.10.25 by KdL --- Added RstKeyLock and swioRESET_n --- --- 2016.08 by Fabio Belavenuto: Refactoring signal names --- --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80a is - generic( - mode_g : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - reset_n_i : in std_logic; - clock_i : in std_logic; - clock_en_i : in std_logic; - address_o : out std_logic_vector(15 downto 0); - data_i : in std_logic_vector(7 downto 0); - data_o : out std_logic_vector(7 downto 0); - wait_n_i : in std_logic; - int_n_i : in std_logic; - nmi_n_i : in std_logic; - m1_n_o : out std_logic; - mreq_n_o : out std_logic; - iorq_n_o : out std_logic; - rd_n_o : out std_logic; - wr_n_o : out std_logic; - refresh_n_o : out std_logic; - halt_n_o : out std_logic; - busrq_n_i : in std_logic; - busak_n_o : out std_logic - ); -end T80a; - -architecture rtl of T80a is - - signal reset_s : std_logic; - signal int_cycle_n_s : std_logic; - signal iorq_s : std_logic; - signal noread_s : std_logic; - signal write_s : std_logic; - signal mreq_s : std_logic; - signal mreq_inhibit_s : std_logic; - signal ireq_inhibit_n_s : std_logic; -- 0247a - signal req_inhibit_s : std_logic; - signal rd_s : std_logic; - signal mreq_n_s : std_logic; - signal iorq_n_s : std_logic; - signal rd_n_s : std_logic; - signal wr_n_s : std_logic; - signal wr_n_j_s : std_logic; -- 0247a - signal rfsh_n_s : std_logic; - signal busak_n_s : std_logic; - signal address_s : std_logic_vector(15 downto 0); - signal data_out_s : std_logic_vector(7 downto 0); - signal data_r : std_logic_vector (7 downto 0); -- Input synchroniser - signal wait_s : std_logic; - signal m_cycle_s : std_logic_vector(2 downto 0); - signal t_state_s : std_logic_vector(2 downto 0); - -begin - - mreq_n_s <= not mreq_s or (req_inhibit_s and mreq_inhibit_s); - rd_n_s <= not rd_s or req_inhibit_s; - wr_n_j_s <= wr_n_s; -- 0247a (why ???) - - busak_n_o <= busak_n_s; - mreq_n_o <= mreq_n_s when busak_n_s = '1' else 'Z'; - iorq_n_o <= iorq_n_s or ireq_inhibit_n_s when busak_n_s = '1' else 'Z'; -- 0247a - rd_n_o <= rd_n_s when busak_n_s = '1' else 'Z'; - wr_n_o <= wr_n_j_s when busak_n_s = '1' else 'Z'; -- 0247a - refresh_n_o <= rfsh_n_s when busak_n_s = '1' else 'Z'; - address_o <= address_s when busak_n_s = '1' else (others => 'Z'); - data_o <= data_out_s; - - process (reset_n_i, clock_i) - begin - if reset_n_i = '0' then - reset_s <= '0'; - elsif rising_edge(clock_i) then - reset_s <= '1'; - end if; - end process; - - u0 : T80 - generic map( - Mode => mode_g, - IOWait => 1 - ) - port map( - CEN => clock_en_i, - M1_n => m1_n_o, - IORQ => iorq_s, - NoRead => noread_s, - Write => write_s, - RFSH_n => rfsh_n_s, - HALT_n => halt_n_o, - WAIT_n => wait_s, - INT_n => int_n_i, - NMI_n => nmi_n_i, - RESET_n => reset_s, - BUSRQ_n => busrq_n_i, - BUSAK_n => busak_n_s, - CLK_n => clock_i, - A => address_s, - DInst => data_i, - DI => data_r, - DO => data_out_s, - MC => m_cycle_s, - TS => t_state_s, - IntCycle_n => int_cycle_n_s - ); - - process (clock_i, clock_en_i) - begin - if falling_edge(clock_i) and clock_en_i = '1' then - wait_s <= wait_n_i; - if t_state_s = "011" and busak_n_s = '1' then - data_r <= data_i; - end if; - end if; - end process; - - process (clock_i) -- 0247a - begin - if rising_edge(clock_i) then - ireq_inhibit_n_s <= not iorq_s; - end if; - end process; - - process (reset_s, clock_i, clock_en_i) -- 0247a - begin - if reset_s = '0' then - wr_n_s <= '1'; - elsif falling_edge(clock_i) and clock_en_i = '1' then - if iorq_s = '0' then - if t_state_s = "010" then - wr_n_s <= not write_s; - elsif t_state_s = "011" then - wr_n_s <= '1'; - end if; - else - if t_state_s = "001" and iorq_n_s = '0' then - wr_n_s <= not write_s; - elsif t_state_s = "011" then - wr_n_s <= '1'; - end if; - end if; - end if; - end process; - - process (reset_s, clock_i, clock_en_i) -- 0247a - begin - if reset_s = '0' then - req_inhibit_s <= '0'; - elsif rising_edge(clock_i) and clock_en_i = '1' then - if m_cycle_s = "001" and t_state_s = "010" and wait_s = '1' then - req_inhibit_s <= '1'; - else - req_inhibit_s <= '0'; - end if; - end if; - end process; - - process (reset_s, clock_i, clock_en_i) - begin - if reset_s = '0' then - mreq_inhibit_s <= '0'; - elsif falling_edge(clock_i) and clock_en_i = '1' then - if m_cycle_s = "001" and t_state_s = "010" then - mreq_inhibit_s <= '1'; - else - mreq_inhibit_s <= '0'; - end if; - end if; - end process; - - process(reset_s, clock_i, clock_en_i) -- 0247a - begin - if reset_s = '0' then - rd_s <= '0'; - iorq_n_s <= '1'; - mreq_s <= '0'; - elsif falling_edge(clock_i) and clock_en_i = '1' then - if m_cycle_s = "001" then - if t_state_s = "001" then - rd_s <= int_cycle_n_s; - mreq_s <= int_cycle_n_s; - iorq_n_s <= int_cycle_n_s; - end if; - if t_state_s = "011" then - rd_s <= '0'; - iorq_n_s <= '1'; - mreq_s <= '1'; - end if; - if t_state_s = "100" then - mreq_s <= '0'; - end if; - else - if t_state_s = "001" and noread_s = '0' then - iorq_n_s <= not iorq_s; - mreq_s <= not iorq_s; - if iorq_s = '0' then - rd_s <= not write_s; - elsif iorq_n_s = '0' then - rd_s <= not write_s; - end if; - end if; - if t_state_s = "011" then - rd_s <= '0'; - iorq_n_s <= '1'; - mreq_s <= '0'; - end if; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/build_id.tcl b/Console_MiST/Coleco - Vision_MiST/rtl/build_id.tcl deleted file mode 100644 index 481e9ebf..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "sys/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/build_id.v b/Console_MiST/Coleco - Vision_MiST/rtl/build_id.v deleted file mode 100644 index 6efa26c3..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/build_id.v +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "180816" -`define BUILD_TIME "200421" diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/cart.qip b/Console_MiST/Coleco - Vision_MiST/rtl/cart.qip deleted file mode 100644 index 8607b3bf..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/cart.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "13.0" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cart.v"] diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/cart.v b/Console_MiST/Coleco - Vision_MiST/rtl/cart.v deleted file mode 100644 index 7c93cc39..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/cart.v +++ /dev/null @@ -1,172 +0,0 @@ -// megafunction wizard: %RAM: 1-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: cart.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version -// ************************************************************ - - -//Copyright (C) 1991-2013 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module cart ( - address, - clock, - data, - wren, - q); - - input [14:0] address; - input clock; - input [7:0] data; - input wren; - output [7:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clock; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] q = sub_wire0[7:0]; - - altsyncram altsyncram_component ( - .address_a (address), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .q_a (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .address_b (1'b1), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b (1'b1), - .eccstatus (), - .q_b (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 32768, - altsyncram_component.operation_mode = "SINGLE_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_reg_a = "CLOCK0", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 15, - altsyncram_component.width_a = 8, - altsyncram_component.width_byteena_a = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -// Retrieval info: PRIVATE: AclrByte NUMERIC "0" -// Retrieval info: PRIVATE: AclrData NUMERIC "0" -// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: Clken NUMERIC "0" -// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -// Retrieval info: PRIVATE: RegAddr NUMERIC "1" -// Retrieval info: PRIVATE: RegData NUMERIC "1" -// Retrieval info: PRIVATE: RegOutput NUMERIC "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: SingleClock NUMERIC "1" -// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "15" -// Retrieval info: PRIVATE: WidthData NUMERIC "8" -// Retrieval info: PRIVATE: rden NUMERIC "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" -// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL cart.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL cart_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/clocks.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/clocks.vhd deleted file mode 100644 index 645740b4..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/clocks.vhd +++ /dev/null @@ -1,125 +0,0 @@ -------------------------------------------------------------------------------- --- --- CoelcoFPGA project --- --- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity clocks is - port ( - clock_i : in std_logic; -- 21 MHz - por_i : in std_logic; - clock_vdp_en_o : out std_logic; - clock_5m_en_o : out std_logic; - clock_3m_en_o : out std_logic - ); -end entity; - -architecture rtl of clocks is - - -- Clocks - signal clk1_cnt_q : unsigned(1 downto 0); - signal clk2_cnt_q : unsigned(1 downto 0); - signal clock_vdp_en_s : std_logic := '0'; -- 10.7 MHz - signal clock_5m_en_s : std_logic := '0'; - signal clock_3m_en_s : std_logic := '0'; - -begin - - ----------------------------------------------------------------------------- - process (clock_i, por_i) - begin - if por_i = '1' then - clk1_cnt_q <= (others => '0'); - clock_vdp_en_s <= '0'; - clock_5m_en_s <= '0'; - - elsif rising_edge(clock_i) then - - -- Clock counter -------------------------------------------------------- - if clk1_cnt_q = 3 then - clk1_cnt_q <= (others => '0'); - else - clk1_cnt_q <= clk1_cnt_q + 1; - end if; - - -- 10.7 MHz clock enable ------------------------------------------------ - case clk1_cnt_q is - when "01" | "11" => - clock_vdp_en_s <= '1'; - when others => - clock_vdp_en_s <= '0'; - end case; - - -- 5.37 MHz clock enable ------------------------------------------------ - case clk1_cnt_q is - when "11" => - clock_5m_en_s <= '1'; - when others => - clock_5m_en_s <= '0'; - end case; - end if; - end process; - - - ----------------------------------------------------------------------------- - process (clock_i, por_i) - begin - if por_i = '1' then - clk2_cnt_q <= (others => '0'); - elsif rising_edge(clock_i) then - if clock_vdp_en_s = '1' then - if clk2_cnt_q = 0 then - clk2_cnt_q <= "10"; - else - clk2_cnt_q <= clk2_cnt_q - 1; - end if; - end if; - end if; - end process; - - clock_3m_en_s <= clock_vdp_en_s when clk2_cnt_q = 0 else '0'; - - -- - clock_vdp_en_o <= clock_vdp_en_s; - clock_5m_en_o <= clock_5m_en_s; - clock_3m_en_o <= clock_3m_en_s; - -end architecture; \ No newline at end of file diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/colecovision.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/colecovision.vhd deleted file mode 100644 index 2c81895c..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/colecovision.vhd +++ /dev/null @@ -1,435 +0,0 @@ -------------------------------------------------------------------------------- --- --- ColecoFPGA project --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity colecovision is - generic ( - num_maq_g : integer := 0; - compat_rgb_g : integer := 0 - ); - port ( - clock_i : in std_logic; - clk_en_10m7_i : in std_logic; - clk_en_5m37_i : in std_logic; - clk_en_3m58_i : in std_logic; - reset_i : in std_logic; -- Reset, tbem acionado quando por_n_i for 0 - por_n_i : in std_logic; -- Power-on Reset - -- Controller Interface --------------------------------------------------- - ctrl_p1_i : in std_logic_vector( 1 downto 0); - ctrl_p2_i : in std_logic_vector( 1 downto 0); - ctrl_p3_i : in std_logic_vector( 1 downto 0); - ctrl_p4_i : in std_logic_vector( 1 downto 0); - ctrl_p5_o : out std_logic_vector( 1 downto 0); - ctrl_p6_i : in std_logic_vector( 1 downto 0); - ctrl_p7_i : in std_logic_vector( 1 downto 0); - ctrl_p8_o : out std_logic_vector( 1 downto 0); - ctrl_p9_i : in std_logic_vector( 1 downto 0); - -- CPU RAM Interface ------------------------------------------------------ - ram_addr_o : out std_logic_vector(16 downto 0); -- 128K - ram_ce_o : out std_logic; - ram_oe_o : out std_logic; - ram_we_o : out std_logic; - ram_data_i : in std_logic_vector( 7 downto 0); - ram_data_o : out std_logic_vector( 7 downto 0); - -- Video RAM Interface ---------------------------------------------------- - vram_addr_o : out std_logic_vector(13 downto 0); -- 16K - vram_ce_o : out std_logic; - vram_oe_o : out std_logic; - vram_we_o : out std_logic; - vram_data_i : in std_logic_vector( 7 downto 0); - vram_data_o : out std_logic_vector( 7 downto 0); - -- Cartridge ROM Interface ------------------------------------------------ - cart_addr_o : out std_logic_vector(14 downto 0); -- 32K - cart_data_i : in std_logic_vector( 7 downto 0); - cart_oe_n_o : out std_logic; - cart_en_80_n_o : out std_logic; - cart_en_a0_n_o : out std_logic; - cart_en_c0_n_o : out std_logic; - cart_en_e0_n_o : out std_logic; - -- Audio Interface -------------------------------------------------------- - audio_o : out std_logic_vector(7 downto 0); - -- RGB Video Interface ---------------------------------------------------- - col_o : out std_logic_vector( 3 downto 0); - cnt_hor_o : out std_logic_vector( 8 downto 0); - cnt_ver_o : out std_logic_vector( 7 downto 0); - rgb_r_o : out std_logic_vector( 7 downto 0); - rgb_g_o : out std_logic_vector( 7 downto 0); - rgb_b_o : out std_logic_vector( 7 downto 0); - hsync_n_o : out std_logic; - vsync_n_o : out std_logic; - comp_sync_n_o : out std_logic; - -- DEBUG - D_cpu_addr : out std_logic_vector(15 downto 0) - ); - -end entity; - --- pragma translate_off -use std.textio.all; --- pragma translate_on - -architecture Behavior of colecovision is - - -- Reset - signal reset_n_s : std_logic; - - -- CPU signals - signal clk_en_cpu_s : std_logic; - signal nmi_n_s : std_logic; - signal iorq_n_s : std_logic; - signal m1_n_s : std_logic; - signal m1_wait_q : std_logic; - signal rd_n_s : std_logic; - signal wr_n_s : std_logic; - signal mreq_n_s : std_logic; - signal rfsh_n_s : std_logic; - signal cpu_addr_s : std_logic_vector(15 downto 0); - signal d_to_cpu_s : std_logic_vector( 7 downto 0); - signal d_from_cpu_s : std_logic_vector( 7 downto 0); - - -- Address Decoder - signal mem_access_s : std_logic; - signal io_access_s : std_logic; - signal io_read_s : std_logic; - signal io_write_s : std_logic; - - -- machine id --- signal machine_id_cs_s : std_logic; --- constant machine_id_c : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(num_maq_g, 8)); - - -- Config port - signal cfg_port_cs_s : std_logic; - signal cfg_page_cs_s : std_logic; - signal cfg_page_r : std_logic_vector(7 downto 0); - - -- BIOS - signal bios_data_i : std_logic_vector( 7 downto 0); - signal multcart_q : std_logic; - signal bios_ce_s : std_logic; - signal bios_oe_s : std_logic; - signal bios_we_s : std_logic; - - -- RAM - signal ram_ce_s : std_logic; - - -- VDP18 signal - signal d_from_vdp_s : std_logic_vector( 7 downto 0); - signal vdp_r_n_s : std_logic; - signal vdp_w_n_s : std_logic; - - -- SN76489 signal - signal audio_s : signed(7 downto 0); - signal psg_ready_s : std_logic; - signal psg_we_n_s : std_logic; - - -- Controller signals - signal d_from_ctrl_s : std_logic_vector( 7 downto 0); - signal ctrl_r_n_s : std_logic; - signal ctrl_en_key_n_s : std_logic; - signal ctrl_en_joy_n_s : std_logic; - - -- Cartridge - signal cart_en_q : std_logic; - signal cart_en_80_n_s : std_logic; - signal cart_en_a0_n_s : std_logic; - signal cart_en_c0_n_s : std_logic; - signal cart_en_e0_n_s : std_logic; - signal ext_cart_ce_s : std_logic; - signal cart_ce_s : std_logic; - signal cart_oe_s : std_logic; - signal cart_we_s : std_logic; - -begin - - -- CPU - cpu: entity work.T80a - generic map ( - mode_g => 0 - ) - port map ( - clock_i => clock_i, - clock_en_i => clk_en_cpu_s, - reset_n_i => reset_n_s, - address_o => cpu_addr_s, - data_i => d_to_cpu_s, - data_o => d_from_cpu_s, - wait_n_i => '1', - int_n_i => '1', - nmi_n_i => nmi_n_s, - m1_n_o => m1_n_s, - mreq_n_o => mreq_n_s, - iorq_n_o => iorq_n_s, - rd_n_o => rd_n_s, - wr_n_o => wr_n_s, - refresh_n_o => rfsh_n_s, - halt_n_o => open, - busrq_n_i => '1', - busak_n_o => open - ); - - lr: entity work.cvBios - port map ( - clock => clock_i, - address => cpu_addr_s(12 downto 0), - q => bios_data_i - ); - - ----------------------------------------------------------------------------- - -- TMS9928A Video Display Processor - ----------------------------------------------------------------------------- - vdp18_b : entity work.vdp18_core - generic map ( - compat_rgb_g => compat_rgb_g - ) - port map ( - clock_i => clock_i, - clk_en_10m7_i => clk_en_10m7_i, - clk_en_5m37_i => clk_en_5m37_i, - reset_n_i => por_n_i, - csr_n_i => vdp_r_n_s, - csw_n_i => vdp_w_n_s, - mode_i => cpu_addr_s(0), - int_n_o => nmi_n_s, - cd_i => d_from_cpu_s, - cd_o => d_from_vdp_s, - vram_ce_o => vram_ce_o, - vram_oe_o => vram_oe_o, - vram_we_o => vram_we_o, - vram_a_o => vram_addr_o, - vram_d_o => vram_data_o, - vram_d_i => vram_data_i, - -- - col_o => col_o, - cnt_hor_o => cnt_hor_o, - cnt_ver_o => cnt_ver_o, - rgb_r_o => rgb_r_o, - rgb_g_o => rgb_g_o, - rgb_b_o => rgb_b_o, - hsync_n_o => hsync_n_o, - vsync_n_o => vsync_n_o, - comp_sync_n_o => comp_sync_n_o - ); - - ----------------------------------------------------------------------------- - -- SN76489 Programmable Sound Generator - ----------------------------------------------------------------------------- - psg_b : entity work.sn76489_top - generic map ( - clock_div_16_g => 1 - ) - port map ( - clock_i => clock_i, - clock_en_i => clk_en_3m58_i, - res_n_i => reset_n_s, - ce_n_i => psg_we_n_s, - we_n_i => psg_we_n_s, - ready_o => psg_ready_s, - d_i => d_from_cpu_s, - aout_o => audio_s - ); - - audio_o <= std_logic_vector(audio_s); - - ----------------------------------------------------------------------------- - -- Controller ports - ----------------------------------------------------------------------------- - ctrl_b : entity work.cv_ctrl - port map ( - clock_i => clock_i, - clk_en_3m58_i => clk_en_3m58_i, - reset_n_i => reset_n_s, - ctrl_en_key_n_i => ctrl_en_key_n_s, - ctrl_en_joy_n_i => ctrl_en_joy_n_s, - a1_i => cpu_addr_s(1), - ctrl_p1_i => ctrl_p1_i, - ctrl_p2_i => ctrl_p2_i, - ctrl_p3_i => ctrl_p3_i, - ctrl_p4_i => ctrl_p4_i, - ctrl_p5_o => ctrl_p5_o, - ctrl_p6_i => ctrl_p6_i, - ctrl_p7_i => ctrl_p7_i, - ctrl_p8_o => ctrl_p8_o, - ctrl_p9_i => ctrl_p9_i, - d_o => d_from_ctrl_s - ); - - -- Glue - reset_n_s <= not reset_i; - clk_en_cpu_s <= clk_en_3m58_i and psg_ready_s and not m1_wait_q; - - - ----------------------------------------------------------------------------- - -- Process m1_wait - -- - -- Purpose: - -- Implements flip-flop U8A which asserts a wait states controlled by M1. - -- - m1_wait: process (clock_i, reset_n_s, m1_n_s) - begin - if reset_n_s = '0' or m1_n_s = '1' then - m1_wait_q <= '0'; - elsif rising_edge(clock_i) then - if clk_en_3m58_i = '1' then - m1_wait_q <= not m1_wait_q; - end if; - end if; - end process m1_wait; - - ----------------------------------------------------------------------------- - -- Misc outputs - ----------------------------------------------------------------------------- - --loader_ce_s <= not rd_n_s and bios_ce_s when loader_q = '1' else '0'; - bios_we_s <= not wr_n_s and bios_ce_s;-- when loader_q = '1' else '0'; - bios_oe_s <= not rd_n_s and bios_ce_s; - - cart_ce_s <= not (cart_en_80_n_s and cart_en_A0_n_s and cart_en_C0_n_s and cart_en_E0_n_s);-- and not ext_cart_en_q; - cart_oe_s <= (not rd_n_s) and cart_ce_s; - cart_we_s <= (not wr_n_s) and cart_ce_s when multcart_q = '1' else '0'; - - -- RAM map - -- 1111111 - -- 65432109876543210 - -- 00000 - 01FFF = BIOS (8K) 0000xxxxxxxxxxxxx - -- 02000 - 03FFF = RAM (8K) 0001xxxxxxxxxxxxx - -- 08000 - 0FFFF = Multicart (32K) 01xxxxxxxxxxxxxxx - -- 10000 - 17FFF = Cartridge (32K) 10xxxxxxxxxxxxxxx - -- - ram_addr_o <= - -- 1111111 - -- 6543210 - "0000" & cpu_addr_s(12 downto 0) when bios_ce_s = '1' else --- "0001" & cpu_addr_s(12 downto 0) when ram_ce_s = '1' else -- 8K linear RAM - "0001" & cpu_addr_s(12 downto 0) when ram_ce_s = '1' and multcart_q = '1' else -- 8K linear RAM - "0001100" & cpu_addr_s( 9 downto 0) when ram_ce_s = '1' and multcart_q = '0' else -- 1K mirrored RAM - -- "01" & cpu_addr_s(14 downto 0) when cart_ce_s = '1' and bios_q = '1' else - "01" & cpu_addr_s(14 downto 0) when cart_ce_s = '1' and multcart_q = '1' and cart_oe_s = '1' else - "10" & cpu_addr_s(14 downto 0) when cart_ce_s = '1' and multcart_q = '1' and cart_we_s = '1' else - "10" & cpu_addr_s(14 downto 0) when cart_ce_s = '1' and multcart_q = '0' else - (others => '0'); - - ram_data_o <= d_from_cpu_s; - ram_ce_o <= ram_ce_s or bios_ce_s or cart_ce_s; - ram_we_o <= (not wr_n_s and ram_ce_s) or bios_we_s or cart_we_s; - ram_oe_o <= (not rd_n_s and ram_ce_s) or bios_oe_s or cart_oe_s; - - cart_addr_o <= cpu_addr_s(14 downto 0); - cart_oe_n_o <= not cart_oe_s; - cart_en_80_n_o <= cart_en_80_n_s or rd_n_s when cart_en_q = '1' else '1'; - cart_en_a0_n_o <= cart_en_A0_n_s or rd_n_s when cart_en_q = '1' else '1'; - cart_en_c0_n_o <= cart_en_C0_n_s or rd_n_s when cart_en_q = '1' else '1'; - cart_en_e0_n_o <= cart_en_E0_n_s or rd_n_s when cart_en_q = '1' else '1'; - - -- Address decoding - mem_access_s <= '1' when mreq_n_s = '0' and rfsh_n_s = '1' else '0'; - io_access_s <= '1' when iorq_n_s = '0' and m1_n_s = '1' else '0'; - io_read_s <= '1' when iorq_n_s = '0' and m1_n_s = '1' and rd_n_s = '0' else '0'; - io_write_s <= '1' when iorq_n_s = '0' and m1_n_s = '1' and wr_n_s = '0' else '0'; - - -- memory - bios_ce_s <= '1' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "000" else '0'; -- BIOS => 0000 to 1FFF - ram_ce_s <= '1' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "011" else '0'; -- RAM => 6000 to 7FFF - cart_en_80_n_s <= '0' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "100" else '1'; -- Cartridge 80 => 8000 to 9FFF - cart_en_a0_n_s <= '0' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "101" else '1'; -- Cartridge A0 => A000 to BFFF - cart_en_c0_n_s <= '0' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "110" else '1'; -- Cartridge C0 => C000 to DFFF - cart_en_e0_n_s <= '0' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "111" else '1'; -- Cartridge E0 => E000 to FFFF - - -- I/O - cfg_port_cs_s <= '1' when io_write_s = '1' and cpu_addr_s(7 downto 0) = X"52" else '0'; -- Config Port => 52 - ---machine_id_cs_s <= '1' when io_read_s = '1' and cpu_addr_s(7 downto 0) = X"53" else '0'; -- Machine ID read => 53 - cfg_page_cs_s <= '1' when io_access_s = '1' and cpu_addr_s(7 downto 0) = X"54" else '0'; -- Page port => 54 - ctrl_en_key_n_s <= '0' when io_write_s = '1' and cpu_addr_s(7 downto 5) = "100" else '1'; -- Controller key set => 80 to 9F - vdp_w_n_s <= '0' when io_write_s = '1' and cpu_addr_s(7 downto 5) = "101" else '1'; -- VDP write => A0 to BF - vdp_r_n_s <= '0' when io_read_s = '1' and cpu_addr_s(7 downto 5) = "101" else '1'; -- VDP read => A0 to BF - ctrl_en_joy_n_s <= '0' when io_write_s = '1' and cpu_addr_s(7 downto 5) = "110" else '1'; -- Controller joy set => C0 to DF - psg_we_n_s <= '0' when io_write_s = '1' and cpu_addr_s(7 downto 5) = "111" else '1'; -- PSG write => E0 to FF - ctrl_r_n_s <= '0' when io_read_s = '1' and cpu_addr_s(7 downto 5) = "111" else '1'; -- Controller read => E0 to FF - - -- Write I/O port 52 - process (por_n_i, reset_i, clock_i) - begin - if por_n_i = '0' then - cart_en_q <= '1'; - multcart_q <= '1'; - -- bios_q <= '1'; - elsif reset_i = '1' then - multcart_q <= '1'; - elsif rising_edge(clock_i) then - if clk_en_3m58_i = '1' and cfg_port_cs_s = '1' then - cart_en_q <= d_from_cpu_s(2); - multcart_q <= d_from_cpu_s(1); - -- bios_q <= d_from_cpu_s(0); - end if; - end if; - end process; - - -- Write I/O port 54 - process (por_n_i, clock_i) - begin - if por_n_i = '0' then - cfg_page_r <= (others => '0'); - elsif rising_edge(clock_i) then - if clk_en_3m58_i = '1' and cfg_page_cs_s = '1' and wr_n_s = '0' then - cfg_page_r <= d_from_cpu_s; - end if; - end if; - end process; - - -- MUX data CPU - d_to_cpu_s <= -- Memory - -- d_from_loader_s when loader_ce_s = '1' else - bios_data_i when bios_ce_s = '1' else - ram_data_i when ram_ce_s = '1' else - cart_data_i when cart_ce_s = '1' else - -- I/O - d_from_vdp_s when vdp_r_n_s = '0' else - d_from_ctrl_s when ctrl_r_n_s = '0' else - --machine_id_c when machine_id_cs_s = '1' else - cfg_page_r when cfg_page_cs_s = '1' else - (others => '1'); - - -- Debug - D_cpu_addr <= cpu_addr_s; - - -end architecture; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/colecovision.vhd.bak b/Console_MiST/Coleco - Vision_MiST/rtl/colecovision.vhd.bak deleted file mode 100644 index f737e1ae..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/colecovision.vhd.bak +++ /dev/null @@ -1,478 +0,0 @@ -------------------------------------------------------------------------------- --- --- ColecoFPGA project --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity colecovision is - generic ( - num_maq_g : integer := 0; - compat_rgb_g : integer := 0 - ); - port ( - clock_i : in std_logic; - clk_en_10m7_i : in std_logic; - clk_en_5m37_i : in std_logic; - clk_en_3m58_i : in std_logic; - reset_i : in std_logic; -- Reset, tbem acionado quando por_n_i for 0 - por_n_i : in std_logic; -- Power-on Reset - -- Controller Interface --------------------------------------------------- - ctrl_p1_i : in std_logic_vector( 1 downto 0); - ctrl_p2_i : in std_logic_vector( 1 downto 0); - ctrl_p3_i : in std_logic_vector( 1 downto 0); - ctrl_p4_i : in std_logic_vector( 1 downto 0); - ctrl_p5_o : out std_logic_vector( 1 downto 0); - ctrl_p6_i : in std_logic_vector( 1 downto 0); - ctrl_p7_i : in std_logic_vector( 1 downto 0); - ctrl_p8_o : out std_logic_vector( 1 downto 0); - ctrl_p9_i : in std_logic_vector( 1 downto 0); - -- CPU RAM Interface ------------------------------------------------------ - ram_addr_o : out std_logic_vector(16 downto 0); -- 128K - ram_ce_o : out std_logic; - ram_oe_o : out std_logic; - ram_we_o : out std_logic; - ram_data_i : in std_logic_vector( 7 downto 0); - ram_data_o : out std_logic_vector( 7 downto 0); - -- Video RAM Interface ---------------------------------------------------- - vram_addr_o : out std_logic_vector(13 downto 0); -- 16K - vram_ce_o : out std_logic; - vram_oe_o : out std_logic; - vram_we_o : out std_logic; - vram_data_i : in std_logic_vector( 7 downto 0); - vram_data_o : out std_logic_vector( 7 downto 0); - -- Cartridge ROM Interface ------------------------------------------------ - cart_addr_o : out std_logic_vector(14 downto 0); -- 32K - cart_data_i : in std_logic_vector( 7 downto 0); - cart_oe_n_o : out std_logic; - cart_en_80_n_o : out std_logic; - cart_en_a0_n_o : out std_logic; - cart_en_c0_n_o : out std_logic; - cart_en_e0_n_o : out std_logic; - -- Audio Interface -------------------------------------------------------- - audio_o : out std_logic_vector(7 downto 0); - audio_signed_o : out signed(7 downto 0); - -- RGB Video Interface ---------------------------------------------------- - col_o : out std_logic_vector( 3 downto 0); - cnt_hor_o : out std_logic_vector( 8 downto 0); - cnt_ver_o : out std_logic_vector( 7 downto 0); - rgb_r_o : out std_logic_vector( 7 downto 0); - rgb_g_o : out std_logic_vector( 7 downto 0); - rgb_b_o : out std_logic_vector( 7 downto 0); - hsync_n_o : out std_logic; - vsync_n_o : out std_logic; - comp_sync_n_o : out std_logic; - -- SPI - spi_miso_i : in std_logic; - spi_mosi_o : out std_logic; - spi_sclk_o : out std_logic; - spi_cs_n_o : out std_logic; - sd_cd_n_i : in std_logic; - -- DEBUG - D_cpu_addr : out std_logic_vector(15 downto 0) - ); - -end entity; - --- pragma translate_off -use std.textio.all; --- pragma translate_on - -architecture Behavior of colecovision is - - -- Reset - signal reset_n_s : std_logic; - - -- CPU signals - signal clk_en_cpu_s : std_logic; - signal nmi_n_s : std_logic; - signal iorq_n_s : std_logic; - signal m1_n_s : std_logic; - signal m1_wait_q : std_logic; - signal rd_n_s : std_logic; - signal wr_n_s : std_logic; - signal mreq_n_s : std_logic; - signal rfsh_n_s : std_logic; - signal cpu_addr_s : std_logic_vector(15 downto 0); - signal d_to_cpu_s : std_logic_vector( 7 downto 0); - signal d_from_cpu_s : std_logic_vector( 7 downto 0); - - -- Address Decoder - signal mem_access_s : std_logic; - signal io_access_s : std_logic; - signal io_read_s : std_logic; - signal io_write_s : std_logic; - - -- machine id - signal machine_id_cs_s : std_logic; - constant machine_id_c : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(num_maq_g, 8)); - - -- Config port - signal cfg_port_cs_s : std_logic; - signal cfg_page_cs_s : std_logic; - signal cfg_page_r : std_logic_vector(7 downto 0); - - -- BIOS - signal loader_ce_s : std_logic; - signal d_from_loader_s : std_logic_vector( 7 downto 0); - signal loader_q : std_logic; - signal multcart_q : std_logic; - signal bios_ce_s : std_logic; - signal bios_oe_s : std_logic; - signal bios_we_s : std_logic; - - -- RAM - signal ram_ce_s : std_logic; - - -- VDP18 signal - signal d_from_vdp_s : std_logic_vector( 7 downto 0); - signal vdp_r_n_s : std_logic; - signal vdp_w_n_s : std_logic; - - -- SN76489 signal - signal audio_s : signed(7 downto 0); - signal psg_ready_s : std_logic; - signal psg_we_n_s : std_logic; - - -- Controller signals - signal d_from_ctrl_s : std_logic_vector( 7 downto 0); - signal ctrl_r_n_s : std_logic; - signal ctrl_en_key_n_s : std_logic; - signal ctrl_en_joy_n_s : std_logic; - - -- SPI - signal d_from_spi_s : std_logic_vector( 7 downto 0); - signal spi_cs_s : std_logic; - signal spi_wr_s : std_logic; - signal spi_rd_s : std_logic; - - -- Cartridge - signal ext_cart_en_q : std_logic; - signal cart_en_80_n_s : std_logic; - signal cart_en_a0_n_s : std_logic; - signal cart_en_c0_n_s : std_logic; - signal cart_en_e0_n_s : std_logic; - signal ext_cart_ce_s : std_logic; - signal cart_ce_s : std_logic; - signal cart_oe_s : std_logic; - signal cart_we_s : std_logic; - -begin - - -- CPU - cpu: entity work.T80a - generic map ( - mode_g => 0 - ) - port map ( - clock_i => clock_i, - clock_en_i => clk_en_cpu_s, - reset_n_i => reset_n_s, - address_o => cpu_addr_s, - data_i => d_to_cpu_s, - data_o => d_from_cpu_s, - wait_n_i => '1', - int_n_i => '1', - nmi_n_i => nmi_n_s, - m1_n_o => m1_n_s, - mreq_n_o => mreq_n_s, - iorq_n_o => iorq_n_s, - rd_n_o => rd_n_s, - wr_n_o => wr_n_s, - refresh_n_o => rfsh_n_s, - halt_n_o => open, - busrq_n_i => '1', - busak_n_o => open - ); - - -- Loader - lr: entity work.loaderrom - port map ( - clk => clock_i, - addr => cpu_addr_s(12 downto 0), - data => d_from_loader_s - ); - - ----------------------------------------------------------------------------- - -- TMS9928A Video Display Processor - ----------------------------------------------------------------------------- - vdp18_b : entity work.vdp18_core - generic map ( - compat_rgb_g => compat_rgb_g - ) - port map ( - clock_i => clock_i, - clk_en_10m7_i => clk_en_10m7_i, - clk_en_5m37_i => clk_en_5m37_i, - reset_n_i => por_n_i, - csr_n_i => vdp_r_n_s, - csw_n_i => vdp_w_n_s, - mode_i => cpu_addr_s(0), - int_n_o => nmi_n_s, - cd_i => d_from_cpu_s, - cd_o => d_from_vdp_s, - vram_ce_o => vram_ce_o, - vram_oe_o => vram_oe_o, - vram_we_o => vram_we_o, - vram_a_o => vram_addr_o, - vram_d_o => vram_data_o, - vram_d_i => vram_data_i, - -- - col_o => col_o, - cnt_hor_o => cnt_hor_o, - cnt_ver_o => cnt_ver_o, - rgb_r_o => rgb_r_o, - rgb_g_o => rgb_g_o, - rgb_b_o => rgb_b_o, - hsync_n_o => hsync_n_o, - vsync_n_o => vsync_n_o, - comp_sync_n_o => comp_sync_n_o - ); - - ----------------------------------------------------------------------------- - -- SN76489 Programmable Sound Generator - ----------------------------------------------------------------------------- - psg_b : entity work.sn76489_top - generic map ( - clock_div_16_g => 1 - ) - port map ( - clock_i => clock_i, - clock_en_i => clk_en_3m58_i, - res_n_i => reset_n_s, - ce_n_i => psg_we_n_s, - we_n_i => psg_we_n_s, - ready_o => psg_ready_s, - d_i => d_from_cpu_s, - aout_o => audio_s - ); - - audio_o <= std_logic_vector(audio_s); - audio_signed_o <= audio_s; - - ----------------------------------------------------------------------------- - -- Controller ports - ----------------------------------------------------------------------------- - ctrl_b : entity work.cv_ctrl - port map ( - clock_i => clock_i, - clk_en_3m58_i => clk_en_3m58_i, - reset_n_i => reset_n_s, - ctrl_en_key_n_i => ctrl_en_key_n_s, - ctrl_en_joy_n_i => ctrl_en_joy_n_s, - a1_i => cpu_addr_s(1), - ctrl_p1_i => ctrl_p1_i, - ctrl_p2_i => ctrl_p2_i, - ctrl_p3_i => ctrl_p3_i, - ctrl_p4_i => ctrl_p4_i, - ctrl_p5_o => ctrl_p5_o, - ctrl_p6_i => ctrl_p6_i, - ctrl_p7_i => ctrl_p7_i, - ctrl_p8_o => ctrl_p8_o, - ctrl_p9_i => ctrl_p9_i, - d_o => d_from_ctrl_s - ); - - -- SPI - sd: entity work.spi - port map ( - clock_i => clk_en_3m58_i, - reset_i => reset_i, - addr_i => cpu_addr_s(0), - cs_i => spi_cs_s, - wr_i => spi_wr_s, - rd_i => spi_rd_s, - data_i => d_from_cpu_s, - data_o => d_from_spi_s, - -- SD card interface - spi_cs_o => spi_cs_n_o, - spi_sclk_o => spi_sclk_o, - spi_mosi_o => spi_mosi_o, - spi_miso_i => spi_miso_i, - sd_cd_n_i => sd_cd_n_i - ); - - spi_wr_s <= not wr_n_s; - spi_rd_s <= not rd_n_s; - - -- Glue - reset_n_s <= not reset_i; - clk_en_cpu_s <= clk_en_3m58_i and psg_ready_s and not m1_wait_q; - - - ----------------------------------------------------------------------------- - -- Process m1_wait - -- - -- Purpose: - -- Implements flip-flop U8A which asserts a wait states controlled by M1. - -- - m1_wait: process (clock_i, reset_n_s, m1_n_s) - begin - if reset_n_s = '0' or m1_n_s = '1' then - m1_wait_q <= '0'; - elsif rising_edge(clock_i) then - if clk_en_3m58_i = '1' then - m1_wait_q <= not m1_wait_q; - end if; - end if; - end process m1_wait; - - ----------------------------------------------------------------------------- - -- Misc outputs - ----------------------------------------------------------------------------- - loader_ce_s <= not rd_n_s and bios_ce_s when loader_q = '1' else '0'; - bios_we_s <= not wr_n_s and bios_ce_s when loader_q = '1' else '0'; - bios_oe_s <= not rd_n_s and bios_ce_s; - - cart_ce_s <= not (cart_en_80_n_s and cart_en_A0_n_s and cart_en_C0_n_s and cart_en_E0_n_s) and not ext_cart_en_q; - ext_cart_ce_s <= not (cart_en_80_n_s and cart_en_A0_n_s and cart_en_C0_n_s and cart_en_E0_n_s) and ext_cart_en_q; - cart_oe_s <= (not rd_n_s) and cart_ce_s; - cart_we_s <= (not wr_n_s) and cart_ce_s when multcart_q = '1' else '0'; - - -- RAM map - -- 1111111 - -- 65432109876543210 - -- 00000 - 01FFF = BIOS (8K) 0000xxxxxxxxxxxxx - -- 02000 - 03FFF = RAM (8K) 0001xxxxxxxxxxxxx - -- 08000 - 0FFFF = Multicart (32K) 01xxxxxxxxxxxxxxx - -- 10000 - 17FFF = Cartridge (32K) 10xxxxxxxxxxxxxxx - -- - ram_addr_o <= - -- 1111111 - -- 6543210 - "0000" & cpu_addr_s(12 downto 0) when bios_ce_s = '1' else --- "0001" & cpu_addr_s(12 downto 0) when ram_ce_s = '1' else -- 8K linear RAM - "0001" & cpu_addr_s(12 downto 0) when ram_ce_s = '1' and multcart_q = '1' else -- 8K linear RAM - "0001100" & cpu_addr_s( 9 downto 0) when ram_ce_s = '1' and multcart_q = '0' else -- 1K mirrored RAM - "01" & cpu_addr_s(14 downto 0) when cart_ce_s = '1' and loader_q = '1' else - "01" & cpu_addr_s(14 downto 0) when cart_ce_s = '1' and multcart_q = '1' and cart_oe_s = '1' else - "10" & cpu_addr_s(14 downto 0) when cart_ce_s = '1' and multcart_q = '1' and cart_we_s = '1' else - "10" & cpu_addr_s(14 downto 0) when cart_ce_s = '1' and multcart_q = '0' else - (others => '0'); - - ram_data_o <= d_from_cpu_s; - ram_ce_o <= ram_ce_s or bios_ce_s or cart_ce_s; - ram_we_o <= (not wr_n_s and ram_ce_s) or bios_we_s or cart_we_s; - ram_oe_o <= (not rd_n_s and ram_ce_s) or bios_oe_s or cart_oe_s; - - cart_addr_o <= cpu_addr_s(14 downto 0); - cart_oe_n_o <= not cart_oe_s; - cart_en_80_n_o <= cart_en_80_n_s or rd_n_s when ext_cart_en_q = '1' else '1'; - cart_en_a0_n_o <= cart_en_A0_n_s or rd_n_s when ext_cart_en_q = '1' else '1'; - cart_en_c0_n_o <= cart_en_C0_n_s or rd_n_s when ext_cart_en_q = '1' else '1'; - cart_en_e0_n_o <= cart_en_E0_n_s or rd_n_s when ext_cart_en_q = '1' else '1'; - - -- Address decoding - mem_access_s <= '1' when mreq_n_s = '0' and rfsh_n_s = '1' else '0'; - io_access_s <= '1' when iorq_n_s = '0' and m1_n_s = '1' else '0'; - io_read_s <= '1' when iorq_n_s = '0' and m1_n_s = '1' and rd_n_s = '0' else '0'; - io_write_s <= '1' when iorq_n_s = '0' and m1_n_s = '1' and wr_n_s = '0' else '0'; - - -- memory - bios_ce_s <= '1' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "000" else '0'; -- BIOS => 0000 to 1FFF - ram_ce_s <= '1' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "011" else '0'; -- RAM => 6000 to 7FFF - cart_en_80_n_s <= '0' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "100" else '1'; -- Cartridge 80 => 8000 to 9FFF - cart_en_a0_n_s <= '0' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "101" else '1'; -- Cartridge A0 => A000 to BFFF - cart_en_c0_n_s <= '0' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "110" else '1'; -- Cartridge C0 => C000 to DFFF - cart_en_e0_n_s <= '0' when mem_access_s = '1' and cpu_addr_s(15 downto 13) = "111" else '1'; -- Cartridge E0 => E000 to FFFF - - -- I/O - spi_cs_s <= '1' when io_access_s = '1' and cpu_addr_s(7 downto 1) = "0101000" else '0'; -- SPI (R/W) => 50 to 51 - cfg_port_cs_s <= '1' when io_write_s = '1' and cpu_addr_s(7 downto 0) = X"52" else '0'; -- Config Port => 52 - machine_id_cs_s <= '1' when io_read_s = '1' and cpu_addr_s(7 downto 0) = X"53" else '0'; -- Machine ID read => 53 - cfg_page_cs_s <= '1' when io_access_s = '1' and cpu_addr_s(7 downto 0) = X"54" else '0'; -- Page port => 54 - ctrl_en_key_n_s <= '0' when io_write_s = '1' and cpu_addr_s(7 downto 5) = "100" else '1'; -- Controller key set => 80 to 9F - vdp_w_n_s <= '0' when io_write_s = '1' and cpu_addr_s(7 downto 5) = "101" else '1'; -- VDP write => A0 to BF - vdp_r_n_s <= '0' when io_read_s = '1' and cpu_addr_s(7 downto 5) = "101" else '1'; -- VDP read => A0 to BF - ctrl_en_joy_n_s <= '0' when io_write_s = '1' and cpu_addr_s(7 downto 5) = "110" else '1'; -- Controller joy set => C0 to DF - psg_we_n_s <= '0' when io_write_s = '1' and cpu_addr_s(7 downto 5) = "111" else '1'; -- PSG write => E0 to FF - ctrl_r_n_s <= '0' when io_read_s = '1' and cpu_addr_s(7 downto 5) = "111" else '1'; -- Controller read => E0 to FF - - -- Write I/O port 52 - process (por_n_i, reset_i, clock_i) - begin - if por_n_i = '0' then - ext_cart_en_q <= '1'; - multcart_q <= '1'; - loader_q <= '1'; - elsif reset_i = '1' then - multcart_q <= '1'; - elsif rising_edge(clock_i) then - if clk_en_3m58_i = '1' and cfg_port_cs_s = '1' then - ext_cart_en_q <= d_from_cpu_s(2); - multcart_q <= d_from_cpu_s(1); - loader_q <= d_from_cpu_s(0); - end if; - end if; - end process; - - -- Write I/O port 54 - process (por_n_i, clock_i) - begin - if por_n_i = '0' then - cfg_page_r <= (others => '0'); - elsif rising_edge(clock_i) then - if clk_en_3m58_i = '1' and cfg_page_cs_s = '1' and wr_n_s = '0' then - cfg_page_r <= d_from_cpu_s; - end if; - end if; - end process; - - -- MUX data CPU - d_to_cpu_s <= -- Memory - d_from_loader_s when loader_ce_s = '1' else - ram_data_i when bios_ce_s = '1' else - ram_data_i when ram_ce_s = '1' else - ram_data_i when cart_ce_s = '1' else - cart_data_i when ext_cart_ce_s = '1' else - -- I/O - d_from_vdp_s when vdp_r_n_s = '0' else - d_from_ctrl_s when ctrl_r_n_s = '0' else - d_from_spi_s when spi_cs_s = '1' else - machine_id_c when machine_id_cs_s = '1' else - cfg_page_r when cfg_page_cs_s = '1' else - (others => '1'); - - -- Debug - D_cpu_addr <= cpu_addr_s; - - -end architecture; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/cv_ctrl.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/cv_ctrl.vhd deleted file mode 100644 index 5714c7c4..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/cv_ctrl.vhd +++ /dev/null @@ -1,152 +0,0 @@ -------------------------------------------------------------------------------- --- --- FPGA Colecovision --- --- $Id: cv_ctrl.vhd,v 1.3 2006/01/08 23:58:04 arnim Exp $ --- --- Controller Interface Module --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity cv_ctrl is - - port ( - clock_i : in std_logic; - clk_en_3m58_i : in std_logic; - reset_n_i : in std_logic; - ctrl_en_key_n_i : in std_logic; - ctrl_en_joy_n_i : in std_logic; - a1_i : in std_logic; - ctrl_p1_i : in std_logic_vector(2 downto 1); - ctrl_p2_i : in std_logic_vector(2 downto 1); - ctrl_p3_i : in std_logic_vector(2 downto 1); - ctrl_p4_i : in std_logic_vector(2 downto 1); - ctrl_p5_o : out std_logic_vector(2 downto 1); - ctrl_p6_i : in std_logic_vector(2 downto 1); - ctrl_p7_i : in std_logic_vector(2 downto 1); - ctrl_p8_o : out std_logic_vector(2 downto 1); - ctrl_p9_i : in std_logic_vector(2 downto 1); - d_o : out std_logic_vector(7 downto 0) - ); - -end cv_ctrl; - - -architecture rtl of cv_ctrl is - - signal sel_q : std_logic; - -begin - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the R/S flip-flop which selects the controller function. - -- - seq: process (clock_i, reset_n_i) - variable ctrl_en_v : std_logic_vector(1 downto 0); - begin - if reset_n_i = '0' then - sel_q <= '0'; - - elsif clock_i'event and clock_i = '1' then - if clk_en_3m58_i = '1' then - ctrl_en_v := ctrl_en_key_n_i & ctrl_en_joy_n_i; - case ctrl_en_v is - when "01" => - sel_q <= '0'; - when "10" => - sel_q <= '1'; - when others => - null; - end case; - end if; - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Controller select - ----------------------------------------------------------------------------- - ctrl_p5_o(1) <= sel_q; - ctrl_p5_o(2) <= sel_q; - ctrl_p8_o(1) <= not sel_q; - ctrl_p8_o(2) <= not sel_q; - - - ----------------------------------------------------------------------------- - -- Process ctrl_read - -- - -- Purpose: - -- Read multiplexer for the controller lines. - -- NOTE: The quadrature decoders are not implemented! - -- - ctrl_read: process (a1_i, - ctrl_p1_i, ctrl_p2_i, ctrl_p3_i, ctrl_p4_i, - ctrl_p6_i, ctrl_p7_i) - variable idx_v : natural range 1 to 2; - begin - if a1_i = '0' then - -- read controller #1 - idx_v := 1; - else - -- read controller #2 - idx_v := 2; - end if; - - d_o <= '0' & -- quadrature information - ctrl_p6_i(idx_v) & - ctrl_p7_i(idx_v) & - '1' & -- quadrature information - ctrl_p3_i(idx_v) & - ctrl_p2_i(idx_v) & - ctrl_p4_i(idx_v) & - ctrl_p1_i(idx_v); - end process ctrl_read; - -- - ----------------------------------------------------------------------------- - - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/dac.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/dac.vhd deleted file mode 100644 index 560e85e2..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2006/11/29 14:17:19 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 2K2 | --- === 10n --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 7 - ); - port ( - clk_i : in std_logic; - res_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end entity; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_i) - begin - if res_i = '1' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end architecture; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/dpSDRAM64Mb.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/dpSDRAM64Mb.vhd deleted file mode 100644 index 9d5ccfb7..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/dpSDRAM64Mb.vhd +++ /dev/null @@ -1,371 +0,0 @@ -------------------------------------------------------------------------------- --- --- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- --- --- SDRAM dual-port emulation --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -entity dpSDRAM64Mb is - generic ( - freq_g : integer := 100 - ); - port ( - clock_i : in std_logic; - reset_i : in std_logic; - refresh_i : in std_logic := '1'; - -- Port 0 - port0_cs_i : in std_logic; - port0_oe_i : in std_logic; - port0_we_i : in std_logic; - port0_addr_i : in std_logic_vector(22 downto 0); - port0_data_i : in std_logic_vector( 7 downto 0); - port0_data_o : out std_logic_vector( 7 downto 0); - -- Port 1 - port1_cs_i : in std_logic; - port1_oe_i : in std_logic; - port1_we_i : in std_logic; - port1_addr_i : in std_logic_vector(22 downto 0); - port1_data_i : in std_logic_vector( 7 downto 0); - port1_data_o : out std_logic_vector( 7 downto 0); - -- SDRAM in board - mem_cke_o : out std_logic; - mem_cs_n_o : out std_logic; - mem_ras_n_o : out std_logic; - mem_cas_n_o : out std_logic; - mem_we_n_o : out std_logic; - mem_udq_o : out std_logic; - mem_ldq_o : out std_logic; - mem_ba_o : out std_logic_vector( 1 downto 0); - mem_addr_o : out std_logic_vector(11 downto 0); - mem_data_io : inout std_logic_vector(15 downto 0) - ); -end entity; - -architecture Behavior of dpSDRAM64Mb is - - constant SdrCmd_de_c : std_logic_vector(3 downto 0) := "1111"; -- deselect - constant SdrCmd_xx_c : std_logic_vector(3 downto 0) := "0111"; -- no operation - constant SdrCmd_rd_c : std_logic_vector(3 downto 0) := "0101"; -- read - constant SdrCmd_wr_c : std_logic_vector(3 downto 0) := "0100"; -- write - constant SdrCmd_ac_c : std_logic_vector(3 downto 0) := "0011"; -- activate - constant SdrCmd_pr_c : std_logic_vector(3 downto 0) := "0010"; -- precharge all - constant SdrCmd_re_c : std_logic_vector(3 downto 0) := "0001"; -- refresh - constant SdrCmd_ms_c : std_logic_vector(3 downto 0) := "0000"; -- mode regiser set - -- SD-RAM control signals - signal SdrCmd_s : std_logic_vector(3 downto 0); - signal SdrBa_s : std_logic_vector(1 downto 0); - signal SdrUdq_s : std_logic; - signal SdrLdq_s : std_logic; - signal SdrAdr_s : std_logic_vector(11 downto 0); - signal SdrDat_s : std_logic_vector(15 downto 0); - - signal ram0_req_s : std_logic; - signal ram0_ack_s : std_logic; - signal ram0_addr_s : std_logic_vector(22 downto 0); - signal ram0_din_s : std_logic_vector( 7 downto 0); - signal ram0_dout_s : std_logic_vector( 7 downto 0); - signal ram0_we_s : std_logic; - - signal ram1_req_s : std_logic; - signal ram1_ack_s : std_logic; - signal ram1_addr_s : std_logic_vector(22 downto 0); - signal ram1_din_s : std_logic_vector( 7 downto 0); - signal ram1_dout_s : std_logic_vector( 7 downto 0); - signal ram1_we_s : std_logic; - -begin - - -- Detectar pedido na porta 0 - process (reset_i, clock_i) - variable pcs_v : std_logic_vector(1 downto 0); - variable acesso_v : std_logic; - begin - if reset_i = '1' then - port0_data_o <= (others => '1'); - ram0_we_s <= '0'; - ram0_req_s <= '0'; - pcs_v := "00"; - elsif rising_edge(clock_i) then - if ram0_req_s = '1' and ram0_ack_s = '1' then - if ram0_we_s = '0' then - port0_data_o <= ram0_dout_s; - end if; - ram0_req_s <= '0'; - end if; - - if pcs_v = "01" then - ram0_addr_s <= port0_addr_i; - ram0_req_s <= '1'; - if port0_we_i = '1' then - ram0_din_s <= port0_data_i; - ram0_we_s <= '1'; - else - ram0_we_s <= '0'; - end if; - end if; - - acesso_v := port0_cs_i and (port0_oe_i or port0_we_i); - pcs_v := pcs_v(0) & acesso_v; - - end if; - end process; - - -- Detectar pedido na porta 1 - process (reset_i, clock_i) - variable pcs_v : std_logic_vector(1 downto 0); - variable acesso_v : std_logic; - begin - if reset_i = '1' then - port1_data_o <= (others => '1'); - ram1_we_s <= '0'; - ram1_req_s <= '0'; - pcs_v := "00"; - elsif rising_edge(clock_i) then - if ram1_req_s = '1' and ram1_ack_s = '1' then - if ram1_we_s = '0' then - port1_data_o <= ram1_dout_s; - end if; - ram1_req_s <= '0'; - end if; - - if pcs_v = "01" then - ram1_addr_s <= port1_addr_i; - ram1_req_s <= '1'; - if port1_we_i = '1' then - ram1_din_s <= port1_data_i; - ram1_we_s <= '1'; - else - ram1_we_s <= '0'; - end if; - end if; - - acesso_v := port1_cs_i and (port1_oe_i or port1_we_i); - pcs_v := pcs_v(0) & acesso_v; - - end if; - end process; - - ---------------------------- - process (clock_i) - - type typSdrRoutine_t is ( SdrRoutine_Null, SdrRoutine_Init, SdrRoutine_Idle, SdrRoutine_RefreshAll, SdrRoutine_ReadOne, SdrRoutine_WriteOne ); - variable SdrRoutine_v : typSdrRoutine_t := SdrRoutine_Null; - variable SdrRoutineSeq_v : unsigned( 7 downto 0) := X"00"; - variable refreshDelayCounter_v : unsigned(23 downto 0) := x"000000"; - variable SdrRefreshCounter_v : unsigned(15 downto 0) := X"0000"; - variable SdrPort_v : std_logic := '0'; - variable SdrAddress_v : std_logic_vector(22 downto 0); - - begin - - if rising_edge(clock_i) then - - ram0_ack_s <= '0'; - ram1_ack_s <= '0'; - - case SdrRoutine_v is - - when SdrRoutine_Null => - SdrCmd_s <= SdrCmd_xx_c; - SdrDat_s <= (others => 'Z'); - - if refreshDelayCounter_v = 0 then - SdrRoutine_v := SdrRoutine_Init; - end if; - - when SdrRoutine_Init => - if SdrRoutineSeq_v = X"00" then - SdrCmd_s <= SdrCmd_pr_c; - SdrAdr_s <= (others => '1'); - SdrBa_s <= "00"; - SdrUdq_s <= '1'; - SdrLdq_s <= '1'; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"04" or SdrRoutineSeq_v = X"0C" then - SdrCmd_s <= SdrCmd_re_c; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"14" then - SdrCmd_s <= SdrCmd_ms_c; - SdrAdr_s <= "00" & "1" & "00" & "010" & "0" & "000"; -- Single, Standard, CAS Latency=2, WT=0(seq), BL=1 - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"17" then - SdrCmd_s <= SdrCmd_xx_c; - SdrRoutineSeq_v := X"00"; - SdrRoutine_v := SdrRoutine_Idle; - else - SdrCmd_s <= SdrCmd_xx_c; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - end if; - - when SdrRoutine_Idle => - SdrCmd_s <= SdrCmd_xx_c; - SdrDat_s <= (others => 'Z'); - - if ram0_req_s = '1' and ram0_ack_s = '0' then - SdrPort_v := '0'; - SdrAddress_v := ram0_addr_s; - if ram0_we_s = '1' then - SdrRoutine_v := SdrRoutine_WriteOne; - else - SdrRoutine_v := SdrRoutine_ReadOne; - end if; - elsif ram1_req_s = '1' and ram1_ack_s = '0' then - SdrPort_v := '1'; - SdrAddress_v := ram1_addr_s; - if ram1_we_s = '1' then - SdrRoutine_v := SdrRoutine_WriteOne; - else - SdrRoutine_v := SdrRoutine_ReadOne; - end if; - elsif SdrRefreshCounter_v < 4096 and refresh_i = '1' then - SdrRoutine_v := SdrRoutine_RefreshAll; - SdrRefreshCounter_v := SdrRefreshCounter_v + 1; - end if; - when SdrRoutine_RefreshAll => - if SdrRoutineSeq_v = X"00" then - SdrCmd_s <= SdrCmd_re_c; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"06" then - SdrCmd_s <= SdrCmd_xx_c; - SdrRoutineSeq_v := X"00"; - SdrRoutine_v := SdrRoutine_Idle; - else - SdrCmd_s <= SdrCmd_xx_c; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - end if; - - when SdrRoutine_ReadOne => - if SdrRoutineSeq_v = X"00" then - SdrCmd_s <= SdrCmd_ac_c; - SdrBa_s <= SdrAddress_v(22 downto 21); - SdrAdr_s <= SdrAddress_v(20 downto 9); -- Row (12 bits) - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"02" then - SdrCmd_s <= SdrCmd_rd_c; - SdrAdr_s(11 downto 8) <= "0100"; -- A10 = '1' => Auto Pre-charge - SdrAdr_s(7 downto 0) <= SdrAddress_v(8 downto 1); -- Col (8 bits) - SdrUdq_s <= '0'; - SdrLdq_s <= '0'; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"05" then - if SdrPort_v = '0' then - if SdrAddress_v(0) = '0' then - ram0_dout_s <= mem_data_io(7 downto 0); - else - ram0_dout_s <= mem_data_io(15 downto 8); - end if; - ram0_ack_s <= '1'; - else - if SdrAddress_v(0) = '0' then - ram1_dout_s <= mem_data_io(7 downto 0); - else - ram1_dout_s <= mem_data_io(15 downto 8); - end if; - ram1_ack_s <= '1'; - end if; - SdrCmd_s <= SdrCmd_xx_c; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"06" then - SdrRoutineSeq_v := X"00"; - SdrRoutine_v := SdrRoutine_Idle; - else - SdrCmd_s <= SdrCmd_xx_c; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - end if; - - when SdrRoutine_WriteOne => - if SdrRoutineSeq_v = X"00" then - SdrCmd_s <= SdrCmd_ac_c; - SdrBa_s <= SdrAddress_v(22 downto 21); - SdrAdr_s <= SdrAddress_v(20 downto 9); - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"02" then - SdrCmd_s <= SdrCmd_wr_c; - SdrAdr_s(11 downto 8) <= "0100"; -- A10 = '1' => Auto Pre-charge - SdrAdr_s(7 downto 0) <= SdrAddress_v(8 downto 1); - SdrUdq_s <= not SdrAddress_v(0); - SdrLdq_s <= SdrAddress_v(0); - if SdrPort_v = '0' then - SdrDat_s <= ram0_din_s & ram0_din_s; - else - SdrDat_s <= ram1_din_s & ram1_din_s; - end if; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"03" then - if SdrPort_v = '0' then - ram0_ack_s <= '1'; - else - ram1_ack_s <= '1'; - end if; - SdrCmd_s <= SdrCmd_xx_c; - SdrDat_s <= (others => 'Z'); - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - elsif SdrRoutineSeq_v = X"05" then - SdrRoutineSeq_v := X"00"; - SdrRoutine_v := SdrRoutine_Idle; - else - SdrCmd_s <= SdrCmd_xx_c; - SdrRoutineSeq_v := SdrRoutineSeq_v + 1; - end if; - end case; - - refreshDelayCounter_v := refreshDelayCounter_v + 1; - - if refreshDelayCounter_v >= ( freq_g * 1000 * 64 ) then - refreshDelayCounter_v := x"000000"; - SdrRefreshCounter_v := x"0000"; - end if; - end if; - end process; - - mem_cke_o <= '1'; - mem_cs_n_o <= SdrCmd_s(3); - mem_ras_n_o <= SdrCmd_s(2); - mem_cas_n_o <= SdrCmd_s(1); - mem_we_n_o <= SdrCmd_s(0); - mem_udq_o <= SdrUdq_s; - mem_ldq_o <= SdrLdq_s; - mem_ba_o <= SdrBa_s; - mem_addr_o <= SdrAdr_s; - mem_data_io <= SdrDat_s; - -end architecture; \ No newline at end of file diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/hq2x.sv b/Console_MiST/Coleco - Vision_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/keyboard.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/keyboard.vhd deleted file mode 100644 index f6b3ff87..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/keyboard.vhd +++ /dev/null @@ -1,206 +0,0 @@ -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.all; - -use work.kbd_pkg.all; - -entity colecoKeyboard is - port ( - clk : in std_logic; - reset : in std_logic; - -- inputs from PS/2 port - ps2_clk : inout std_logic; - ps2_data : inout std_logic; - -- user outputs - keys : out std_logic_vector(15 downto 0); - joy : out std_logic_vector(15 downto 0); - core_reload_o : out std_logic; - home_o : out std_logic - - ); -end colecoKeyboard; - -architecture SYN of colecoKeyboard is - - component ps2kbd - port ( - clk : in std_logic; - rst_n : in std_logic; - tick1us : in std_logic; - ps2_clk : in std_logic; - ps2_data : in std_logic; - - reset : out std_logic; - press : out std_logic; - release : out std_logic; - scancode : out std_logic_vector(7 downto 0) - ); - end component; - - signal rst_n : std_logic; - - -- 1us tick for PS/2 interface - signal tick1us : std_logic; - - signal ps2_reset : std_logic; - signal ps2_press : std_logic; - signal ps2_release : std_logic; - signal ps2_scancode : std_logic_vector(7 downto 0); - signal ctrl_s : std_logic := '0'; - signal alt_s : std_logic := '0'; - signal home_s : std_logic := '0'; - -begin - - rst_n <= not reset; - - -- produce a 1us tick from the 20MHz ref clock - process (clk, reset) - variable count : integer range 0 to 19; - begin - if reset = '1' then - tick1us <= '0'; - count := 0; - elsif rising_edge (clk) then - if count = 19 then - tick1us <= '1'; - count := 0; - else - tick1us <= '0'; - count := count + 1; - end if; - end if; - end process; - - latchInputs: process (clk, rst_n) - begin - -- note: all inputs are active HIGH - - if rst_n = '0' then - keys <= (others => '0'); - joy <= (others => '0'); - core_reload_o <= '0'; - home_s <= '0'; - elsif rising_edge (clk) then - core_reload_o <= '0'; - - if (ps2_press or ps2_release) = '1' then - case ps2_scancode is - -- this is not a valid scancode - -- but stuff the right button in here - when SCANCODE_X => - keys(0) <= ps2_press; - when SCANCODE_8 => - keys(1) <= ps2_press; - when SCANCODE_4 => - keys(2) <= ps2_press; - when SCANCODE_5 => - keys(3) <= ps2_press; - when SCANCODE_7 => - keys(5) <= ps2_press; - when SCANCODE_Q => -- '#' - keys(6) <= ps2_press; - when SCANCODE_2 => - keys(7) <= ps2_press; - when SCANCODE_W => -- '*' - keys(9) <= ps2_press; - when SCANCODE_0 => - keys(10) <= ps2_press; - when SCANCODE_9 => - keys(11) <= ps2_press; - when SCANCODE_3 => - keys(12) <= ps2_press; - when SCANCODE_1 => - keys(13) <= ps2_press; - when SCANCODE_6 => - keys(14) <= ps2_press; - ------------------------------------------------ - when SCANCODE_ESC => -- soft reset key : ESC - keys(8) <= ps2_press; - ------------------------------------------------- - when SCANCODE_UP => - joy(0) <= ps2_press; - when SCANCODE_DOWN => - joy(1) <= ps2_press; - when SCANCODE_LEFT => - joy(2) <= ps2_press; - when SCANCODE_RIGHT => - joy(3) <= ps2_press; - when SCANCODE_Z => - joy(4) <= ps2_press; - when SCANCODE_LCTRL => - ctrl_s <= ps2_press; - when SCANCODE_LALT => - alt_s <= ps2_press; - when SCANCODE_BACKSPACE => - if alt_s = '1' and ctrl_s = '1' then - core_reload_o <= '1'; - end if; - when SCANCODE_HOME => - home_s <= ps2_press; - when others => - null; - end case; - end if; -- ps2_press or release - if (ps2_reset = '1') then - keys <= (others => '0'); - joy <= (others => '0'); - end if; - end if; -- rising_edge (clk) - end process latchInputs; - - ps2kbd_inst : ps2kbd - port map ( - clk => clk, - rst_n => rst_n, - tick1us => tick1us, - ps2_clk => ps2_clk, - ps2_data => ps2_data, - - reset => ps2_reset, - press => ps2_press, - release => ps2_release, - scancode => ps2_scancode - ); - - home_o <= home_s; - -end SYN; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/mist_io.v b/Console_MiST/Coleco - Vision_MiST/rtl/mist_io.v deleted file mode 100644 index 1cfcb753..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/mist_io.v +++ /dev/null @@ -1,496 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoubler_disable, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - input ioctl_wait, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [13:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; - - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [13:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin -// addr <= ioctl_index ? 14'd9 : 14'd0; //.p files loaded at $4009, ROM is at 0 - addr <= 14'd0; - ioctl_download <= 1; - end else begin - ioctl_addr <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - ioctl_addr <= addr; - ioctl_dout <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - ioctl_wr <= 1; - end else - ioctl_wr <= 0; - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -endmodule diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/osd.v b/Console_MiST/Coleco - Vision_MiST/rtl/osd.v deleted file mode 100644 index c62c10af..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/osd.v +++ /dev/null @@ -1,179 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [7:0] osd_byte; -always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; - -wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/pll.v b/Console_MiST/Coleco - Vision_MiST/rtl/pll.v deleted file mode 100644 index 6fa5c561..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/pll.v +++ /dev/null @@ -1,393 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: pll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version -// ************************************************************ - - -//Copyright (C) 1991-2013 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module pll ( - inclk0, - c0, - c1, - c2, - c3, - locked); - - input inclk0; - output c0; - output c1; - output c2; - output c3; - output locked; - - wire [4:0] sub_wire0; - wire sub_wire3; - wire [0:0] sub_wire8 = 1'h0; - wire [2:2] sub_wire5 = sub_wire0[2:2]; - wire [0:0] sub_wire4 = sub_wire0[0:0]; - wire [3:3] sub_wire2 = sub_wire0[3:3]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; - wire c3 = sub_wire2; - wire locked = sub_wire3; - wire c0 = sub_wire4; - wire c2 = sub_wire5; - wire sub_wire6 = inclk0; - wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; - - altpll altpll_component ( - .inclk (sub_wire7), - .clk (sub_wire0), - .locked (sub_wire3), - .activeclock (), - .areset (1'b0), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b0), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbmimicbidir (), - .fbout (), - .fref (), - .icdrclk (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 63, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 50, - altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 126, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 25, - altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 27, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 100, - altpll_component.clk2_phase_shift = "0", - altpll_component.clk3_divide_by = 27, - altpll_component.clk3_duty_cycle = 50, - altpll_component.clk3_multiply_by = 100, - altpll_component.clk3_phase_shift = "-2500", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 37037, - altpll_component.intended_device_family = "Cyclone III", - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_UNUSED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_USED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", - altpll_component.port_clk3 = "PORT_USED", - altpll_component.port_clk4 = "PORT_UNUSED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena2 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED", - altpll_component.self_reset_on_loss_lock = "OFF", - altpll_component.width_clock = 5; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "63" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "126" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27" -// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "21.428572" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "5.357143" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "100.000000" -// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" -// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "100" -// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "100" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "21.42857100" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "5.35714300" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" -// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-2500.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" -// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" -// Retrieval info: PRIVATE: USE_CLK3 STRING "1" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" -// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "63" -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "126" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "100" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27" -// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "100" -// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-2500" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 -// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf -// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/pll.vhd.bak b/Console_MiST/Coleco - Vision_MiST/rtl/pll.vhd.bak deleted file mode 100644 index c0171a21..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/pll.vhd.bak +++ /dev/null @@ -1,424 +0,0 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll1.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll1 IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END pll1; - - -ARCHITECTURE SYN OF pll1 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - locked <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 16000000, - clk0_duty_cycle => 50, - clk0_multiply_by => 7142857, - clk0_phase_shift => "0", - clk1_divide_by => 12, - clk1_duty_cycle => 50, - clk1_multiply_by => 25, - clk1_phase_shift => "0", - clk2_divide_by => 12, - clk2_duty_cycle => 50, - clk2_multiply_by => 25, - clk2_phase_shift => "-2500", - compensate_clock => "CLK0", - inclk0_input_frequency => 20833, - intended_device_family => "Cyclone IV E", - lpm_hint => "CBX_MODULE_PREFIX=pll1", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "OFF", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire6, - clk => sub_wire0, - locked => sub_wire2 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "21.428572" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "21.42857100" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll1.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "16000000" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7142857" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "12" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "12" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2500" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/ps2kbd.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/ps2kbd.vhd deleted file mode 100644 index f3cbeaaa..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/ps2kbd.vhd +++ /dev/null @@ -1,202 +0,0 @@ --- PS/2 serial port, input only --- --- Version : 0242 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.fpgaarcade.com --- --- Limitations : --- --- File history : --- --- 0242 : First release --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity ps2kbd is - port( - Rst_n : in std_logic; - Clk : in std_logic; - Tick1us : in std_logic; - PS2_Clk : in std_logic; - PS2_Data : in std_logic; - Press : out std_logic; - Release : out std_logic; - Reset : out std_logic; - ScanCode : out std_logic_vector(7 downto 0)); -end ps2kbd; - -architecture rtl of ps2kbd is - - signal PS2_Sample : std_logic; - signal PS2_Data_s : std_logic; - - signal RX_Bit_Cnt : unsigned(3 downto 0); - signal RX_Byte : unsigned(2 downto 0); - signal RX_ShiftReg : std_logic_vector(7 downto 0); - signal RX_Release : std_logic; - signal RX_Received : std_logic; - -begin - - ScanCode <= RX_ShiftReg; - - process (Clk, Rst_n) - variable PS2_Data_r : std_logic_vector(1 downto 0); - variable PS2_Clk_r : std_logic_vector(1 downto 0); - variable PS2_Clk_State : std_logic; - begin - if Rst_n = '0' then - PS2_Sample <= '0'; - PS2_Data_s <= '0'; - PS2_Data_r := "11"; - PS2_Clk_r := "11"; - PS2_Clk_State := '1'; - elsif Clk'event and Clk = '1' then - if Tick1us = '1' then - PS2_Sample <= '0'; - - -- Deglitch - if PS2_Data_r = "00" then - PS2_Data_s <= '0'; - end if; - if PS2_Data_r = "11" then - PS2_Data_s <= '1'; - end if; - if PS2_Clk_r = "00" then - if PS2_Clk_State = '1' then - PS2_Sample <= '1'; - end if; - PS2_Clk_State := '0'; - end if; - if PS2_Clk_r = "11" then - PS2_Clk_State := '1'; - end if; - - -- Double synchronise - PS2_Data_r(1) := PS2_Data_r(0); - PS2_Clk_r(1) := PS2_Clk_r(0); - PS2_Data_r(0) := PS2_Data; - PS2_Clk_r(0) := PS2_Clk; - end if; - end if; - end process; - - process (Clk, Rst_n) - variable Cnt : integer; - begin - if Rst_n = '0' then - RX_Bit_Cnt <= (others => '0'); - RX_ShiftReg <= (others => '0'); - RX_Received <= '0'; - Cnt := 0; - elsif Clk'event and Clk = '1' then - RX_Received <= '0'; - if Tick1us = '1' then - - if PS2_Sample = '1' then - if RX_Bit_Cnt = "0000" then - if PS2_Data_s = '0' then -- Start bit - RX_Bit_Cnt <= RX_Bit_Cnt + 1; - end if; - elsif RX_Bit_Cnt = "1001" then -- Parity bit - RX_Bit_Cnt <= RX_Bit_Cnt + 1; - -- Ignoring parity - elsif RX_Bit_Cnt = "1010" then -- Stop bit - if PS2_Data_s = '1' then - RX_Received <= '1'; - end if; - RX_Bit_Cnt <= "0000"; - else - RX_Bit_Cnt <= RX_Bit_Cnt + 1; - RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1); - RX_ShiftReg(7) <= PS2_Data_s; - end if; - end if; - - -- TimeOut - if PS2_Sample = '1' then - Cnt := 0; - elsif Cnt = 127 then - RX_Bit_Cnt <= "0000"; - Cnt := 0; - else - Cnt := Cnt + 1; - end if; - end if; - end if; - end process; - - process (Clk, Rst_n) - begin - if Rst_n = '0' then - Press <= '0'; - Release <= '0'; - Reset <= '0'; - RX_Byte <= (others => '0'); - RX_Release <= '0'; - elsif Clk'event and Clk = '1' then - Press <= '0'; - Release <= '0'; - Reset <= '0'; - if RX_Received = '1' then - RX_Byte <= RX_Byte + 1; - if RX_ShiftReg = x"F0" then - RX_Release <= '1'; - elsif RX_ShiftReg = x"E0" then - else - RX_Release <= '0'; - -- Normal key press - if RX_Release = '0' then - Press <= '1'; - end if; - -- Normal key release - if RX_Release = '1' then - Release <= '1'; - end if; - end if; - if RX_ShiftReg = x"aa" then - Reset <= '1'; - end if; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/ps2kbd_pkg.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/ps2kbd_pkg.vhd deleted file mode 100644 index 44c59f3f..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/ps2kbd_pkg.vhd +++ /dev/null @@ -1,140 +0,0 @@ -------------------------------------------------------------------------------- --- --- Copyright (c) 2002, Daniel Wallner (jesus@opencores.org) --- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package kbd_pkg is - - constant SCANCODE_BACKQUOTE : std_logic_vector(7 downto 0) := X"0E"; - constant SCANCODE_A : std_logic_vector(7 downto 0) := X"1C"; - constant SCANCODE_B : std_logic_vector(7 downto 0) := X"32"; - constant SCANCODE_C : std_logic_vector(7 downto 0) := X"21"; - constant SCANCODE_D : std_logic_vector(7 downto 0) := X"23"; - constant SCANCODE_E : std_logic_vector(7 downto 0) := X"24"; - constant SCANCODE_F : std_logic_vector(7 downto 0) := X"2B"; - constant SCANCODE_G : std_logic_vector(7 downto 0) := X"34"; - constant SCANCODE_H : std_logic_vector(7 downto 0) := X"33"; - constant SCANCODE_I : std_logic_vector(7 downto 0) := X"43"; - constant SCANCODE_J : std_logic_vector(7 downto 0) := X"3B"; - constant SCANCODE_K : std_logic_vector(7 downto 0) := X"42"; - constant SCANCODE_L : std_logic_vector(7 downto 0) := X"4B"; - constant SCANCODE_M : std_logic_vector(7 downto 0) := X"3A"; - constant SCANCODE_N : std_logic_vector(7 downto 0) := X"31"; - constant SCANCODE_O : std_logic_vector(7 downto 0) := X"44"; - constant SCANCODE_P : std_logic_vector(7 downto 0) := X"4D"; - constant SCANCODE_Q : std_logic_vector(7 downto 0) := X"15"; - constant SCANCODE_R : std_logic_vector(7 downto 0) := X"2D"; - constant SCANCODE_S : std_logic_vector(7 downto 0) := X"1B"; - constant SCANCODE_T : std_logic_vector(7 downto 0) := X"2C"; - constant SCANCODE_U : std_logic_vector(7 downto 0) := X"3C"; - constant SCANCODE_V : std_logic_vector(7 downto 0) := X"2A"; - constant SCANCODE_W : std_logic_vector(7 downto 0) := X"1D"; - constant SCANCODE_X : std_logic_vector(7 downto 0) := X"22"; - constant SCANCODE_Y : std_logic_vector(7 downto 0) := X"35"; - constant SCANCODE_Z : std_logic_vector(7 downto 0) := X"1A"; - constant SCANCODE_0 : std_logic_vector(7 downto 0) := X"45"; - constant SCANCODE_1 : std_logic_vector(7 downto 0) := X"16"; - constant SCANCODE_2 : std_logic_vector(7 downto 0) := X"1E"; - constant SCANCODE_3 : std_logic_vector(7 downto 0) := X"26"; - constant SCANCODE_4 : std_logic_vector(7 downto 0) := X"25"; - constant SCANCODE_5 : std_logic_vector(7 downto 0) := X"2E"; - constant SCANCODE_6 : std_logic_vector(7 downto 0) := X"36"; - constant SCANCODE_7 : std_logic_vector(7 downto 0) := X"3D"; - constant SCANCODE_8 : std_logic_vector(7 downto 0) := X"3E"; - constant SCANCODE_9 : std_logic_vector(7 downto 0) := X"46"; - constant SCANCODE_QUOTE : std_logic_vector(7 downto 0) := X"52"; - constant SCANCODE_SEMICOLON : std_logic_vector(7 downto 0) := X"4C"; - constant SCANCODE_COMMA : std_logic_vector(7 downto 0) := X"41"; - constant SCANCODE_MINUS : std_logic_vector(7 downto 0) := X"4E"; - constant SCANCODE_PERIOD : std_logic_vector(7 downto 0) := X"49"; - constant SCANCODE_SLASH : std_logic_vector(7 downto 0) := X"4A"; - constant SCANCODE_ENTER : std_logic_vector(7 downto 0) := X"5A"; - constant SCANCODE_HOME : std_logic_vector(7 downto 0) := X"6C"; - constant SCANCODE_INS : std_logic_vector(7 downto 0) := X"70"; -- E0 - constant SCANCODE_PGUP : std_logic_vector(7 downto 0) := X"7D"; -- E0 - constant SCANCODE_PGDN : std_logic_vector(7 downto 0) := X"7A"; -- E0 - constant SCANCODE_UP : std_logic_vector(7 downto 0) := X"75"; -- E0 - constant SCANCODE_DOWN : std_logic_vector(7 downto 0) := X"72"; -- E0 - constant SCANCODE_LEFT : std_logic_vector(7 downto 0) := X"6B"; -- E0 - constant SCANCODE_BACKSPACE : std_logic_vector(7 downto 0) := X"66"; - constant SCANCODE_RIGHT : std_logic_vector(7 downto 0) := X"74"; -- E0 - constant SCANCODE_SPACE : std_logic_vector(7 downto 0) := X"29"; - constant SCANCODE_LSHIFT : std_logic_vector(7 downto 0) := X"12"; - constant SCANCODE_RSHIFT : std_logic_vector(7 downto 0) := X"59"; - constant SCANCODE_TAB : std_logic_vector(7 downto 0) := X"0D"; - constant SCANCODE_ESC : std_logic_vector(7 downto 0) := X"76"; - constant SCANCODE_EQUALS : std_logic_vector(7 downto 0) := X"55"; - constant SCANCODE_F1 : std_logic_vector(7 downto 0) := X"05"; - constant SCANCODE_F2 : std_logic_vector(7 downto 0) := X"06"; - constant SCANCODE_F3 : std_logic_vector(7 downto 0) := X"04"; - constant SCANCODE_F4 : std_logic_vector(7 downto 0) := X"0C"; - constant SCANCODE_F5 : std_logic_vector(7 downto 0) := X"03"; - constant SCANCODE_F6 : std_logic_vector(7 downto 0) := X"0B"; - constant SCANCODE_F7 : std_logic_vector(7 downto 0) := X"83"; - constant SCANCODE_F8 : std_logic_vector(7 downto 0) := X"0A"; - constant SCANCODE_F9 : std_logic_vector(7 downto 0) := X"01"; - constant SCANCODE_F10 : std_logic_vector(7 downto 0) := X"09"; - constant SCANCODE_F11 : std_logic_vector(7 downto 0) := X"78"; - constant SCANCODE_F12 : std_logic_vector(7 downto 0) := X"07"; - constant SCANCODE_CAPSLOCK : std_logic_vector(7 downto 0) := X"58"; - constant SCANCODE_BACKSLASH : std_logic_vector(7 downto 0) := X"5D"; - constant SCANCODE_LCTRL : std_logic_vector(7 downto 0) := X"14"; - constant SCANCODE_LALT : std_logic_vector(7 downto 0) := X"11"; - alias SCANCODE_TILDE : std_logic_vector(7 downto 0) is SCANCODE_BACKQUOTE; - constant SCANCODE_OPENBRKT : std_logic_vector(7 downto 0) := X"54"; - alias SCANCODE_OPENBRACE : std_logic_vector(7 downto 0) is SCANCODE_OPENBRKT; - constant SCANCODE_CLOSEBRKT : std_logic_vector(7 downto 0) := X"5B"; - alias SCANCODE_CLOSEBRACE : std_logic_vector(7 downto 0) is SCANCODE_CLOSEBRKT; - constant SCANCODE_END : std_logic_vector(7 downto 0) := X"69"; -- E0 - alias SCANCODE_PAD0 : std_logic_vector(7 downto 0) is SCANCODE_INS; - alias SCANCODE_PAD1 : std_logic_vector(7 downto 0) is SCANCODE_END; - alias SCANCODE_PAD2 : std_logic_vector(7 downto 0) is SCANCODE_DOWN; - alias SCANCODE_PAD3 : std_logic_vector(7 downto 0) is SCANCODE_PGDN; - alias SCANCODE_PAD4 : std_logic_vector(7 downto 0) is SCANCODE_LEFT; - constant SCANCODE_PAD5 : std_logic_vector(7 downto 0) := X"73"; - alias SCANCODE_PAD6 : std_logic_vector(7 downto 0) is SCANCODE_RIGHT; - alias SCANCODE_PAD7 : std_logic_vector(7 downto 0) is SCANCODE_HOME; - alias SCANCODE_PAD8 : std_logic_vector(7 downto 0) is SCANCODE_UP; - alias SCANCODE_PAD9 : std_logic_vector(7 downto 0) is SCANCODE_PGUP; - - type kbd_row is array (natural range <>) of std_logic_vector(7 downto 0); - type kbd_col is array (natural range <>) of std_logic_vector(7 downto 0); - -end; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/roms/COLECO-SHORT-DELAY.BIO b/Console_MiST/Coleco - Vision_MiST/rtl/roms/COLECO-SHORT-DELAY.BIO deleted file mode 100644 index 6a967b55..00000000 Binary files a/Console_MiST/Coleco - Vision_MiST/rtl/roms/COLECO-SHORT-DELAY.BIO and /dev/null differ diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/roms/COLECO.BIO b/Console_MiST/Coleco - Vision_MiST/rtl/roms/COLECO.BIO deleted file mode 100644 index ba4b278e..00000000 Binary files a/Console_MiST/Coleco - Vision_MiST/rtl/roms/COLECO.BIO and /dev/null differ diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/roms/CVbios.hex b/Console_MiST/Coleco - Vision_MiST/rtl/roms/CVbios.hex deleted file mode 100644 index e9c2fd9c..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/roms/CVbios.hex +++ /dev/null @@ -1,258 +0,0 @@ -:020000040000FA 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Vision_MiST/rtl/roms/coleco29.asm b/Console_MiST/Coleco - Vision_MiST/rtl/roms/coleco29.asm deleted file mode 100644 index 6e1f725d..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/roms/coleco29.asm +++ /dev/null @@ -1,4939 +0,0 @@ -;*************************************** -; -; Note: Markers like [1] indicate bytes that can be -; saved by obvious (or nearly so) optimizations, -; and [0] indicates that cycles can be saved. -; -; Some of the optimizations can't be made because -; they will change locked address, and some are -; so non-obvious that I can't figure out what I -; was thinking when I marked them! -; -;*************************************** - -; LOCKED ADDRESSES -- THESE *MUST* BE CORRECT OR SOME CARTRIDGES WILL NOT RUN! -; -; In order to allow easy verification, these addresses have labels -; starting with an 'A' and containing the locked address. -; -; These are the important addresses (like vectors), plus a few used by the -; small-time offenders. -; -; 0000 0066 080B 18A3 -; 0008 0069 08C0 18D4. -; 0010 006A 143B 18F7* -; 0018 006C 144D 1968 -; 0020 01B1* 1463 196B -; 0028 01D5 14B4 1CCA. -; 0030 023B. 14C1 1D43 -; 0038 02EE 14C3 1D47 -; 003B. 07E8* 15A3 1F61 -; 158B* -; -; ...and these are the addresses used by three of the four Interphase -; games, most of which have vectors available. -; -; 0213. 114A*. 1BAA* 1D3E*. -; 025E. 18E9. 1C27. 1D57. -; 027F. 1979*. 1C4F* 1D5A. -; 0300. 1B1D*. 1C82*. 1D60*. -; 1105* 1BA3. 1D01*. 1D66*. -; -; These two were called from Boulder Dash, but the call instructions -; themselves may be unreachable from the rest of the game. -; -; 01C1* 026A* -; -; Any address with a '*' is only referenced by ONE game that I can find. -; Note that Interphase games account for 11 out of 15 of these. Any address -; with a '.' has a vector available. Note also that all but two Interphase- -; only addresses (18 of 20) have vectors! Oh the humanity! -; -; These are in the "OS7SYM" file which was provided to Adam programmers: -; -;FREQ_SWEEP EQU 000FCH ! -;ATN_SWEEP EQU 0012FH ! -;DECLSN EQU 00190H ! -;DECMSN EQU 0019BH ! -;MSNTOLSN EQU 001A6H ! - - - -O EQU 0FFH ; filler for unused bytes - -;*************************************** -; RAM usage -;*************************************** - - ORG 7000H - - DS 12 ; default CtlState storage? - DS 20 -SndArray DS 2 ; music array pointer? -NoiseP DS 2 ; Pointer to program for noise generator -Tone1P DS 2 ; Pointer to program for tone1 generator -Tone2P DS 2 ; Pointer to program for tone2 generator -Tone3P DS 2 ; Pointer to program for tone3 generator -NoiseCtlShad DS 1 ; Noise control register shadow - - ORG 73B9H - -Stack DS 1 ; Default initial stack pointer -ParmArea DS 9 ; Parameter storage for PCOPY parameters -VDP0Shad DS 1 ; VDP register 0 shadow -VDP1Shad DS 1 ; VDP register 1 shadow - DS 1 ; unused? -D73C6 DS 1 ; flag byte? -WrtRAMSprt DS 1 ; BlkWrtVRAM to RAM sprite attr table if =1 -RandSeed DS 2 ; Random number seed -D73CA DS 1 ; unknown -D73CB DS 1 ; unknown -D73CC DS 1 ; unknown -D73CD DS 2 ; unknown -D73CF DS 2 ; unknown -D73D1 DS 2 ; unknown -TimerList DS 2 ; Pointer to timer list -TimerAux DS 2 ; Pointer to end of timer aux storage -RawCtlState DS 20 ; Raw controller state table (2 x 10 bytes) -PulseCnt1 DS 1 ; Pulse counter #1 -PulseCnt2 DS 1 ; Pulse counter #2 - DS 1 ; unused? -Joy1Shad DS 1 ; shadow for joystick #1 -Joy2Shad DS 1 ; shadow for joystick #2 -Key1Shad DS 1 ; shadow for keypad #1 -Key2Shad DS 1 ; shadow for keypad #2 -VDPBaseShad EQU $ ; shadow for VDP table base addresses -SprtTabShad DS 2 ; shadow for sprite table VRAM base addr -SprtPatTabShad DS 2 ; shadow for sprite pattern generator VRAM base addr -NameTabShad DS 2 ; shadow for name table VRAM base address -PatGenTabShad DS 2 ; shadow for pattern generator VRAM base addr -ClrTabShad DS 2 ; shadow for color table VRAM base address - DS 2 ; unused? -D73FE DS 2 ; temp3 - -;*************************************** -; Cartridge header addresses -;*************************************** - - ORG 8000H - -Cart_Sig DS 2 ; AA55 = title screen, 55AA = no screen -RamSprtTab DS 2 ; RAM sprite attribute table pointer -RAMSprtIdx DS 2 ; sprite index table pointer -VDP_Temp DS 2 ; pointer to temp image storage (up to 40 bytes used) -CtlState DS 2 ; pointer to controller state table (2 + 2x5 bytes) -Cart_Start DS 2 ; start of cart code -V_RST_08H DS 3 ; RST 08H vector -V_RST_10H DS 3 ; RST 10H vector -V_RST_18H DS 3 ; RST 18H vector -V_RST_20H DS 3 ; RST 20H vector -V_RST_28H DS 3 ; RST 28H vector -V_RST_30H DS 3 ; RST 30H vector -V_RST_38H DS 3 ; RST 38H vector -V_NMI DS 3 ; NMI vector (vertical blank interrupt) -Cart_Title DS 0 ; Title string "LINE 3/LINE 2/yyyy" - -;*************************************** -; Offsets into data blocks -;*************************************** - -; Offsets into RawCtlState - -RawCtlLeft EQU 00H ; raw left controller state -RawCtlRight EQU 0AH ; raw right controller state - -; Offsets into RawCtlLeft and RawCtlRight - -RawCtlLFBit EQU 00H ; previous left fire bit -RawCtlLFState EQU 01H ; left fire button state -RawCtlDBits EQU 02H ; previous directional bits -RawCtlDState EQU 03H ; directionals state -; EQU 04H ; unused? -; EQU 05H ; unused? -RawCtlRFBit EQU 06H ; previous right fire bit -RawCtlRFState EQU 07H ; right fire button state -RawCtlKPBit EQU 08H ; previous keypad bits -RawCtlKPState EQU 09H ; keypad state - -; Offsets into CtlState table - -CtlStateLFlag EQU 00H ; left controller flags -CtlStateRFlag EQU 01H ; right controller flags -CtlStateLeft EQU 02H ; left controller state -CtlStateRight EQU 07H ; right controller state - -; CtlStateLF/CtlStateRF bits - -CtlCheckMe EQU 80H ; 7 ; if =0, do not check this ctrl at all -; EQU 40H ; 6 ; unused? -; EQU 20H ; 5 ; unused? -CtlCheckKP EQU 10H ; 4 ; check keypad -CtlCheckRFire EQU 08H ; 3 ; check right fire button -CtlCheckSpinner EQU 04H ; 2 ; check spinner -CtlCheckDir EQU 02H ; 1 ; check directionals -CtlCheckLFire EQU 01H ; 0 ; check left fire button - -; Offsets into CtlStateLeft and CtlStateRight - -CtlStateLFire EQU 00H ; left fire button -CtlStateDir EQU 01H ; directionals -CtlStateSpin EQU 02H ; spinner value -CtlStateRFire EQU 03H ; right fire button -CtlStateKey EQU 04H ; key code - -;*************************************** -; I/O port addresses -;*************************************** - -IO_KP_Select EQU 080H ; Keypad select output port -IO_Joy_Select EQU 0C0H ; Joystick select output port -IO_Joy1 EQU 0FCH ; Joystick 1 input port -IO_Joy2 EQU 0FFH ; Joystick 2 input port -IO_Sound EQU 0FFH ; Sound chip output port -IO_VDP_Data EQU 0BEH ; VDP data port -IO_VDP_Addr EQU 0BFH ; VDP VRAM address output port -IO_VDP_Status EQU 0BFH ; VDP status input port - - - ORG 0000H - -;*************************************** -; Everything starts here -;*************************************** -A0000 LD SP,Stack ; Initialize stack pointer - JR L006E ; Go to rest of cold-start code - -;*************************************** -; These are the RST vectors, mixed with some (formerly) wasted bytes -;*************************************** -P_AddSound -P_StopTimer -P_TestTimer -P_InitRAMSprt -P_CopyRAMSprt DB 1 - DW 1 - -A0008 JP V_RST_08H - -P_InitSound -P_StartTimer -P_BaseLoad DB 2 - DW 1,2 - -A0010 JP V_RST_10H - -D0482 DB 2 - DW -2,1 - -A0018 JP V_RST_18H - -D064F DB 2 - DW 1,-2 - -A0020 JP V_RST_20H - -D06C1 DB 2 - DW 2,1 - -A0028 JP V_RST_28H - -P_InitTimers DB 2 - DW 2,2 - -A0030 JP V_RST_30H - -P_WriteReg DB 2 - DW 1,1 - -A0038 JP V_RST_38H - -;*************************************** -; 1FFD Random -; -; Returns a random number in A. This routine apparently -; uses a pseudo-random shift register algorithm based on -; the XOR of bits 8 and 15. -;*************************************** -A003B -_Random LD HL,(RandSeed) - BIT 7,H ; Set the carry flag to - JR Z,L0048 ; bit 8 XOR bit 15 - BIT 0,H - JR Z,L004C -L004F OR A ; Clear carry flag -L0050 RL L ; Rotate the carry into HL - RL H - LD (RandSeed),HL ; Update the random number seed - LD A,L ; Return the LSB - RET - -L0048 BIT 0,H - JR Z,L004F -D1AC4 ; DB '7' -L004C SCF ; Set carry flag - JR L0050 - -; DE = DE + IX - -L0478 PUSH IX - EX (SP),HL -L047C ADD HL,DE - EX DE,HL - POP HL - RET - -P_WrtVRAM -P_ReadVRAM DB 3 - DW -2,2,2 - - DB O - -;*************************************** -; NMI vector -;*************************************** -A0066 JP V_NMI - -;*************************************** -; I'm not really sure what these are for, but aside from the -; jump vectors at the end of the ROM, they are probably the -; only ROM addresses that you should reference directly. -;*************************************** -A0069 DB 60 ; this might mean a 60hz display (NTSC) -A006A DW D16AB ; this points to the font bitmap for 'A' -A006C DW D1623 ; this points to the font bitmap for '0' - -;*************************************** -; -; First part of cold start code -; -;*************************************** -L006E LD HL,(Cart_Sig) ; Check first word of cart for 55AAH - LD A,L ; 8000=55H and 8001=AAH - CP 55H - JR NZ,L0081 - LD A,H - CP 0AAH - JR NZ,L0081 - LD HL,(Cart_Start) ; If 55H/AAH, jump into cartridge - JP (HL) - -L0081 CALL NoSound ; Turn off sound -D1AC0 EQU $+1 ; DB '3' - LD HL,0033H ; Initialize random seed - LD (RandSeed),HL - CALL InitCtlState ; Clear all controller state flags -; XOR A ; (A-reg is already = 00H) -D1ABF ; DB '2' - LD (D73C6),A ; Clear some unknown flags - LD (WrtRAMSprt),A ; Clear BlkWrtVRAM RAM sprite attr flag - JP L1319 ; Go display copyright screen - -;*************************************** -; PCopy -; -; This routine copies in-line paramters for the subroutines. -; -; The descriptor table entries are 2 bytes each. The first word -; of the descriptor list is the number of descriptors in the list. -; -; (Note: for optimization purposes, the number of descriptors is now a byte) -; -; If an entry is positive, it contains the number of bytes to copy -; to the storage area. -; -; The parameters are 2 bytes each and normally contain the -; address of the data to be copied into the storage area. -; -; If a descriptor table entry is negative, the next parameter -; is taken as a 2-byte literal and stored directly in the data area. -; -; If a parameter word is zero, the next parameter word contains the -; address of the real parameter word to use. This is done before -; checking for a negative descriptor table entry. -; -; ENTRY BC points to parameter descriptor table -; DE points to parameter storage area -; (SP+2) = return address of calling routine -; EXIT: DE points to first unused byte of storage area -;*************************************** -PCopy POP HL ; Swap caller's return address - EX (SP),HL ; (the parameter pointer) to - PUSH HL ; the top of the stack - LD A,(BC) ; HL = first descriptor table word - LD L,A - INC BC - LD H,00H - EX (SP),HL ; Swap parameter pointer - PUSH DE ; with storage pointer - -; Get next parameter word - -L00A3 LD E,(HL) ; DE = next parameter word - INC HL - LD D,(HL) - INC HL - PUSH HL ; Save parameter pointer - LD A,E ; Check if parameter = 0 - OR D - JR NZ,L00B7 ; Branch if = 0 - -; Handle zero parameter word - - POP HL ; Get back parameter pointer - LD E,(HL) ; DE = next parameter word - INC HL - LD D,(HL) - INC HL - PUSH HL ; Save parameter pointer - EX DE,HL ; DE = (DE) - LD E,(HL) - INC HL - LD D,(HL) - -; Check sign of descriptor word - -L00B7 INC BC ; Get MSB of descriptor - LD A,(BC) - RLCA - JR NC,L00DA ; Branch if positive - -; Handle negative descriptor word - - INC BC ; Point to next descriptor word - POP HL ; HL = parameter pointer - EX (SP),HL ; Swap with storage pointer - LD (HL),E ; Store DE in storage area - INC HL - LD (HL),D - INC HL -L00C4 POP DE ; DE = storage pointer - EX (SP),HL ; Swap it with parameter counter - DEC HL ; Decrement count - LD A,H ; Test for zero count - OR L - JR Z,L00D6 -L00D0 EX (SP),HL ; Swap counter back on stack - PUSH HL ; Put storage pointer back on stack - EX DE,HL ; HL = parameter pointer - JR L00A3 ; Go back for next parameter - -L00D6 POP HL ; Get storage pointer - EX DE,HL ; DE = storage pointer, HL = parm pointer - EX (SP),HL ; Put parm pointer back on stack - JP (HL) ; Return to caller - -; Handle positive descriptor word - -L00DA POP HL ; Swap parameter pointer - EX (SP),HL ; and storage pointer - PUSH HL - RRCA ; Restore value of MSB - LD H,A ; H = MSB - DEC BC ; L = LSB - LD A,(BC) - LD L,A - EX (SP),HL ; HL = storage pointer, TOS = count - INC BC ; Point to next descriptor - INC BC -L00E5 LD A,(DE) ; Copy next parameter byte - LD (HL),A - INC HL - INC DE - EX (SP),HL ; HL = count, TOS = storage pointer - DEC HL ; Decrement counter - LD A,H ; Loop until count is zero - OR L - JR Z,L00F8 ; Branch if count = 0 -L00F4 EX (SP),HL ; HL = storage pointer, TOS = count - JR L00E5 ; Go back to copy next byte - -L00F8 POP HL ; HL = storage pointer - JR L00C4 ; Go check for end of parameter list - -;*************************************** -; -; SOUND ROUTINES BEGIN HERE -; -;*************************************** - -; Process the duration and twang values? - -L00FC LD A,(IX+07H) - OR A - JR NZ,L010C - LD A,(IX+05H) - DEC A - RET Z - LD (IX+05H),A - RET - -L010C PUSH IX - POP HL - LD DE,0006H - ADD HL,DE - CALL L0190 - RET NZ - CALL L01A6 - DEC HL - LD A,(HL) - DEC A - RET Z - LD (HL),A - DEC HL - DEC HL - LD A,(IX+07H) - CALL A01B1 - INC HL - RES 2,(HL) - JR L015D - -; Process the decay? - -L012F LD A,(IX+08H) - OR A - RET Z - PUSH IX - POP HL - LD DE,0009H - ADD HL,DE - CALL L0190 - RET NZ - CALL L01A6 - DEC HL - CALL L0190 - JR Z,L0161 - LD A,(HL) - AND 0F0H - LD E,A - DEC HL - DEC HL - DEC HL - DEC HL - LD A,(HL) - AND 0F0H - ADD A,E - LD E,A - LD A,(HL) - AND 0FH - OR E - LD (HL),A -L015D OR 0FFH - RET - -D1AC3 ; DB '6' -L0161 LD (HL),00H - RET - -;*************************************** -; -; Put up the introduction screen -; -;*************************************** -L1352 POP HL ; End of list, clean up - - LD HL,Title_Msgs ; Put up "COLECOVISION" title screen - CALL ScrnMsgs - - LD HL,A143B ; Point to color table -; LD DE,0000H ; Table index - LD D,B ; (BC=0 from ScrnMsgs) - LD E,C - LD IY,0012H ; Byte count - CALL _BlkWrtVRAM4 ; Color table - LD BC,01C0H ; Unblank the screen - CALL _WriteReg - LD HL,Cart_Sig ; Check first 2 bytes of cartridge - LD A,(HL) ; If 8000<>AA or 8001<>55, - CP 0AAH - JR NZ,L13B7 ; put up "please turn machine off - INC HL ; before inserting cartridge" msg - LD A,(HL) - CP 55H -L13B7 JP NZ,L13FF - - LD HL,Cart_Title ; Find name string - LD D,H ; Display address = first string - LD E,L - CALL L1946 ; Scan for first '/' - PUSH HL ; Save address of first '/' - LD HL,0201H ; Screen address for first string - CALL L1951 ; Display first string centered - - POP HL ; Recover address of first '/' - INC HL ; Adjust for second string - LD D,H ; Display address = second string - LD E,L - CALL L1946 ; Scan for second '/' - PUSH HL ; Save address of second '/' - LD HL,01C1H ; Screen address for second string - CALL L1951 ; Display second string centered - - POP HL ; Recover address of second '/' - INC HL ; Adjust for third string - LD DE,02ACH ; Screen address for copyright date - LD IY,0004H ; 4 bytes - CALL _BlkWrtVRAM2 - - CALL A1968 ; "Respect the seven second delay we - ; use" - Donald Fagen, "The Nightfly" - - LD BC,0180H ; Blank screen - CALL _WriteReg - - LD HL,(Cart_Start) ; Get start address - JP (HL) ; Jump into cartridge - - DB O,O,O,O,O,O,O,O,O,O - DB O - - -; Add A (signed byte) to (HL) - -A01B1 LD B,00H ; sign-extend A -> BA - BIT 7,A - JR Z,L01B9 - DEC B -L01B9 ADD A,(HL) - LD (HL),A - INC HL - LD A,(HL) - ADC A,B - LD (HL),A - DEC HL - RET - - DB O - -; Index into the 7020H array using B as the index -; B = 1 returns HL = (7020H)+2 and IX = (HL) - -A01C1 LD HL,(SndArray) ; HL = (7020H)-2 + B*4 - DEC HL - DEC HL - LD C,B - LD B,00H - ADD HL,BC - ADD HL,BC - ADD HL,BC - ADD HL,BC - LD E,(HL) ; IX = (HL) - INC HL - LD D,(HL) - PUSH DE - POP IX - RET - - DB O - -; Update function code? (Used by Carnival!) - -A01D5 LD (IX+01H),L - LD (IX+02H),H - LD A,(DE) - AND 3FH - LD B,A - LD A,(IX+00H) - AND 0C0H - OR B - LD (IX+00H),A - RET - -; Get command list pointer? - -L01E9 LD A,(IX+00H) - CP 0FFH - RET Z - AND 3FH - CP 3EH - RET NZ - PUSH IX - POP HL - INC HL - LD E,(HL) - INC HL - LD D,(HL) - EX DE,HL - RET - - DB O,O,O,O,O,O - -;*************************************** -; 1FB2 PInitSound -; -; Parameter block version of 1FEE -; -; Parm 1 (byte) = number of array elements -; Parm 2 (word) = pointer to array of pointers -; -;*************************************** -_PInitSound LD BC,P_InitSound - LD DE,ParmArea - CALL PCopy - LD A,(ParmArea) - LD B,A - LD HL,(ParmArea+1) - -;*************************************** -; 1FEE InitSound -; -; Initializes 7020 with HL, clears out the array pointed to by -; (HL+2) to contain an FF every ten bytes for B times, then stores -; a zero at the end. Then the sound variables are initialized and -; the sound chip is silenced. -; -; Array at 7020H contains a list of four-byte entries. The -; second word of the list contains a pointer to a list of -; 10-byte blocks, and the second word of each other entry -; probably contains a pointer into this list as well. The -; first word of each four-byte entry is apparently a pointer -; to a list of command bytes. -; -; Each 10 byte block has the following format: -; -; +0 bits 0-5 = function code (3EH is special) -; bits 6-7 = channel code (0=noise, else tone channel number) -; +1,+2 pointer to list of command bytes -; +3 low 8 bits of frequency -; +4 bits 0-3 = high 2 bits of frequency or noise control -; bits 4-7 = amplitude (00H=max, 0FH=off) -; +5 duration counter? -; +6 bits 0-3 = twang time counter? -; bits 4-7 = twang time? -; +7 twang offset? (signed byte) -; +8 bits 0-3 = decay high counter? -; bits 4-7 = decay high nibble? -; +9 bits 0-3 = decay low counter? -; bits 4-7 = decay low nibble? -; -; ENTRY B = number of array elements -; HL = pointer to array of pointers -;*************************************** -A0213 -_InitSound LD (SndArray),HL - INC HL - INC HL - LD E,(HL) - INC HL - LD D,(HL) - EX DE,HL - LD DE,000AH -NoSoundP EQU $+1 ; null sound program = single FFH byte -L0220 LD (HL),0FFH - ADD HL,DE - DJNZ L0220 - LD (HL),D - CALL L0297 - LD A,(HL) ; = 0FFH - LD (NoiseCtlShad),A - JR A023B - - DB O,O,O,O,O,O,O,O,O,O - DB O,O,O - -;*************************************** -; 1FD6 NoSound -; -; This routine silences the sound chip. -;*************************************** -A023B -_NoSound LD A,9FH - OUT (IO_Sound),A - LD A,0BFH - OUT (IO_Sound),A - LD A,0DFH - OUT (IO_Sound),A - LD A,0FFH - OUT (IO_Sound),A - RET - - DB O,O,O,O,O - -;*************************************** -; 1FB5 PAddSound -; -; Parameter block version of 1FF1 -; -; Parm 1 (byte) = index into array at 7020H -;*************************************** -_PAddSound LD BC,P_AddSound - LD DE,ParmArea - CALL PCopy - LD A,(ParmArea) - LD B,A - -;*************************************** -; 1FF1 AddSound -; -; This routine seets up a new entry in the sound list. (?) -; -; ENTRY B = index into array at 7020H, 1 = first entry -;*************************************** -A025E -_AddSound PUSH BC - CALL A01C1 - LD A,(IX+00H) - AND 3FH - POP BC - CP B - RET Z -A026A LD (IX+00H),B - DEC HL - DEC HL - LD D,(HL) - DEC HL - LD E,(HL) - LD (IX+01H),E - LD (IX+02H),D - CALL L035F - JR L0295 - - DB O,O - -;*************************************** -; 1FF4 UpdateSound -; -; This routine updates the current sound pointers -; by searching through the sound list. -;*************************************** -A027F -_UpdateSound LD B,01H - CALL A01C1 -L0284 XOR A - CP (IX+00H) - RET Z - CALL L02D6 - LD DE,000AH - ADD IX,DE - JR L0284 - -; Update stream pointers - -L0295 CALL L0297 - PUSH IX - - LD B,01H - CALL A01C1 -L02AB LD A,(IX+00H) - OR A - JR Z,L02D3 - INC A - JR Z,L02CB - LD A,(IX+00H) - AND 0C0H - RLCA - RLCA - RLCA - LD E,A - LD D,00H - LD HL,NoiseP - ADD HL,DE - PUSH IX - POP DE - LD (HL),E - INC HL - LD (HL),D -L02CB LD DE,000AH - ADD IX,DE - JR L02AB - -L02D3 POP IX - RET - -L02D6 CALL L01E9 - CP 0FFH - RET Z - CP 3EH - JR NZ,L02E6 - LD DE,0007H - ADD HL,DE - JP (HL) - -L0297 LD HL,NoSoundP - LD (NoiseP),HL - LD (Tone1P),HL - LD (Tone2P),HL - LD (Tone3P),HL - RET - - DB O,O,O - -L02E6 CALL L012F - CALL L00FC - RET NZ -A02EE LD A,(IX+00H) ; (called by Carnival) - PUSH AF - CALL L035F - POP BC - LD A,(IX+00H) - CP B - RET Z - JR L0295 - -D1AC6 DB 'TWO' - -;*************************************** -; 1F61 DoSound -; -; This updates the sound chip registers based on the -; current sound array pointers for each channel. -;*************************************** -A0300 -_DoSound LD A,9FH - LD C,90H -D0587 EQU $+1 - LD D,80H - LD IX,(Tone1P) - CALL L034E - LD A,0BFH - LD C,0B0H - LD D,0A0H - LD IX,(Tone2P) - CALL L034E - LD A,0DFH - LD C,0D0H - LD D,0C0H - LD IX,(Tone3P) - CALL L034E - LD A,0FFH - LD C,0F0H - LD IX,(NoiseP) - LD E,(IX+00H) - INC E - JR Z,L0335 - CALL L0164 - LD A,(IX+04H) - AND 0FH - LD HL,NoiseCtlShad - CP (HL) - RET Z - LD (HL),A - LD C,0E0H - -; Send amplitude or noise control to sound chip - -L0164 LD A,(IX+04H) - BIT 4,C - JR Z,L016F - RRCA - RRCA - RRCA - RRCA -L016F AND 0FH - OR C -L0335 OUT (IO_Sound),A - RET - -L034E LD E,(IX+00H) - INC E - JR Z,L0335 - CALL L0164 - -; Send freqency to sound chip - -L0175 LD A,(IX+03H) - AND 0FH - OR D - OUT (IO_Sound),A - LD A,(IX+03H) - AND 0F0H - LD D,A - LD A,(IX+04H) - AND 0FH - OR D - RRCA - RRCA - RRCA - RRCA - JR L0335 - -L035F LD A,(IX+00H) - AND 3FH - PUSH AF - LD (IX+00H),0FFH - LD L,(IX+01H) - LD H,(IX+02H) - LD A,(HL) - LD B,A - BIT 5,A - JR Z,L0391 - PUSH BC - AND 1FH - INC HL - LD (IX+01H),L - LD (IX+02H),H - LD (IX+04H),0F0H - LD (IX+05H),A - JR L03F0 - -L0391 BIT 4,A - JR Z,L03A4 - BIT 3,A - JR Z,L039E - POP BC - JP _AddSound - -L039E LD A,0FFH - PUSH AF - JR L03F8 - -L03A4 AND 3CH - CP 04H - JR NZ,L03D2 - POP IY - PUSH IY - PUSH BC - INC HL - LD E,(HL) - LD (IX+01H),E - INC HL - LD D,(HL) - LD (IX+02H),D - INC HL - PUSH IY - POP AF - PUSH DE - POP IY - LD DE,L03C6 - PUSH DE - JP (IY) - -L03C6 LD DE,0007H - ADD IY,DE - LD DE,L0461 - PUSH DE - JP (IY) - -L03D2 PUSH BC - LD A,B - AND 03H - JR NZ,L03FA - INC HL - INC HL - INC HL - INC HL - LD (IX+01H),L - LD (IX+02H),H - DEC HL - LD DE,0005H - CALL L0478 ; DE = DE + IX - LD BC,0003H - LDDR -L03F0 LD (IX+07H),00H -L03F4 LD (IX+08H),00H -L03F8 JR L0461 - -L03FA DEC A ; CP 01H - JR NZ,L0419 - LD DE,0006H - ADD HL,DE - LD (IX+01H),L - LD (IX+02H),H - DEC HL - INC E - CALL L0478 ; DE = DE + IX - LD BC,0005H - LDDR - JR L03F4 - -L0419 DEC A ; CP 02H - JR NZ,L0445 - LD DE,0006H - ADD HL,DE - POP AF - PUSH AF - AND 0C0H - JR NZ,L0429 - DEC HL -L0429 LD (IX+01H),L - LD (IX+02H),H - DEC HL - LD E,09H - CALL L0478 ; DE = DE + IX - LD BC,0002H - LDDR - XOR A - LD (DE),A - DEC DE - DEC DE - LD C,03H - LDDR - JR L0461 - -L0445 LD DE,0008H - ADD HL,DE - LD (IX+01H),L - LD (IX+02H),H - DEC HL - INC E - CALL L0478 ; DE = DE + IX - LD BC,0007H - LDDR -L0461 PUSH IX - POP HL - POP AF - POP BC - CP 0FFH - RET Z - LD D,A - AND 3FH - CP 04H - JR NZ,L0472 - LD B,3EH -L0472 LD A,D - AND 0C0H - OR B - LD (HL),A - RET - -;*************************************** -; -; VIDEO ROUTINES BEGIN HERE -; -;*************************************** - -;*************************************** -; 1F64 -; -; Parameter block version of 1FF7 -; -; Parm 1 (lit) = ? -; Parm 2 (byte) = ? -;*************************************** -L0488 LD BC,D0482 - LD DE,ParmArea - CALL PCopy - LD HL,(ParmArea) - LD E,(HL) - INC HL - LD D,(HL) - EX DE,HL - LD A,(ParmArea+2) - OR A ; (clears carry) - JR Z,L04A3 - SCF - -;*************************************** -; 1FF7 -; -; ENTRY HL = ? -; C-flag = ? -;*************************************** -L04A3 LD E,(HL) - INC HL - LD D,(HL) - INC HL - LD C,(HL) - INC HL - LD B,(HL) - INC HL - LD A,00H ; note: must preserve carry here! - LD (BC),A - LD A,(DE) - PUSH AF - AND 0FH - JR Z,L04E7 - DEC A - JR Z,L05F1 - DEC A - JR Z,L0600 - DEC A - JR Z,L0600 - DEC A - JR NZ,L04E5 - -; 04A3/1FF7 Function 4 - -L04C6 LD A,(DE) - RRA - RRA - RRA - RRA - AND 0FH - LD B,A - LD E,(HL) - INC HL - LD D,(HL) - INC HL - OR A - JR Z,L04E5 -L04D5 POP AF - PUSH AF - PUSH HL - PUSH BC - EX DE,HL - CALL L04A3 - POP BC - POP HL - LD E,(HL) - INC HL - LD D,(HL) - INC HL - DJNZ L04D5 -L04E5 POP AF - RET - -; 04A3/1FF7 Function 1 - -L05F1 CALL L0572 - INC DE - LD A,(DE) - LD (IY+05H),A - INC DE - LD A,(DE) - LD (IY+06H),A - POP AF - RET - -; 04A3/1FF7 Functions 2 & 3 - -L0600 INC BC - INC BC - INC BC - INC BC - INC BC - EX DE,HL - INC HL - LD A,(HL) - LD E,A - LD D,00H - PUSH DE - INC HL - LD E,(HL) - INC HL - LD D,(HL) - INC HL - ADD A,(HL) - LD (BC),A - LD C,(HL) - LD B,00H - PUSH BC - POP IY - EX DE,HL - POP DE - POP AF - RET NC - LD A,01H ; Sprite pattern gen table - JP _BlkWrtVRAM - -; 04A3/1FF7 Function 0 - -L04E7 CALL L0572 - LD A,(DE) - LD L,A - INC DE - LD A,(DE) - ADD A,L - LD (IY+05H),A - LD H,00H - POP AF - RET NC ; this is the carry flag from L04A3 - PUSH AF - LD A,(VDP0Shad) ; Check for hi-res graphics - BIT 1,A - JR Z,L0530 ; Branch if not - EX DE,HL - LD B,H - LD C,L - LD L,(HL) - LD H,00H - PUSH HL - ADD HL,HL - ADD HL,HL - ADD HL,HL - PUSH HL - INC BC - LD A,(BC) - LD L,A - INC BC - LD A,(BC) - LD H,A - POP BC - POP IY - POP AF - BIT 7,A - CALL NZ,L0594 - INC D ; DE = DE + 0100H - BIT 6,A - CALL NZ,L0594 - INC D ; DE = DE + 0100H - BIT 5,A - RET Z -L0594 PUSH AF - PUSH BC - PUSH IY - PUSH DE - PUSH HL - CALL _BlkWrtVRAM3 ; Pattern generator table - POP HL - POP DE - POP IY - POP BC - POP AF - PUSH AF - PUSH BC - PUSH IY - PUSH DE - PUSH HL - BIT 4,A - JR NZ,L05BC - ADD HL,BC - CALL _BlkWrtVRAM4 ; Color table -L05B5 POP HL - POP DE - POP IY - POP BC - POP AF - RET - -L0530 EX DE,HL - LD C,(HL) - LD B,00H - PUSH BC - POP IY - INC HL - LD A,(HL) - INC HL - LD H,(HL) - LD L,A - PUSH HL - PUSH BC - PUSH DE - PUSH IY - CALL _BlkWrtVRAM3 ; Pattern generator table - POP BC - POP HL - LD E,L - LD D,H - ADD HL,BC - DEC HL - SRL H - RR L - SRL H - RR L - SRL H - RR L - SRA E - SRA E - SRA E - OR A - SBC HL,DE - INC HL - PUSH HL - POP IY - POP HL - ADD HL,HL - ADD HL,HL - ADD HL,HL - POP BC - ADD HL,BC - CALL _BlkWrtVRAM4 ; Color table - POP AF - RET - -L05BC ADD HL,BC - LD C,L - LD B,H - PUSH IY - POP HL -L05C2 PUSH HL - LD A,(BC) - PUSH BC - LD BC,0008H - LD HL,(VDP_Temp) - ADD HL,BC - LD B,C -L05CE DEC HL - LD (HL),A - DJNZ L05CE - PUSH DE - CALL L1EA5 ; LD A,04H LD IY,0001H JP _BlkWrtVRAM - POP DE - POP BC - INC DE - INC BC - POP HL - DEC HL - LD A,H - OR L - JR NZ,L05C2 - JR L05B5 - -L0572 PUSH BC - POP IY - PUSH DE - LD E,(HL) - INC HL - LD D,(HL) - BIT 7,D - JR NZ,L0591 - LD A,D - CP 70H - JR C,L0588 - LD A,80H - LD (DE),A - JR L0591 - -L0588 LD HL,D0587 - LD BC,0001H - CALL _WrtVRAM -L0591 POP DE - INC DE - RET - -;*************************************** -; 1F67 -; -; Parameter block version of 1FFA -; -; Parm 1 (word) = ??? -; Parm 2 (byte) = ??? -;*************************************** -L06C7 LD BC,D06C1 - LD DE,ParmArea - CALL PCopy - LD IX,(ParmArea) - LD A,(ParmArea+2) - LD B,A - -;*************************************** -; 1FFA -; -; ENTRY IX = ??? -; A = ??? -;*************************************** -L06D8 LD A,(D73C6) - DEC A - JR NZ,L06E3 - -L0623 PUSH IX - LD HL,(73CDH) - POP DE - LD (HL),E - INC HL - LD (HL),D - INC HL - LD (HL),B - INC HL - EX DE,HL - LD A,(73CBH) - INC A - LD HL,73CAH - CP (HL) - EX DE,HL - JR NZ,L0669 - XOR A - LD HL,(73D1H) -L0669 LD (73CDH),HL - LD (73CBH),A - RET - -L06E3 LD L,(IX+00H) - LD H,(IX+01H) - LD A,(HL) - LD C,A - AND 0FH - JR Z,L06FF - DEC A - JP Z,L0A87 - DEC A - JR Z,L08DF - DEC A - JP Z,L0955 - JP L0EA2 - -L08DF LD E,0F9H - CALL L08E0 - LD HL,0008H - JP L0999 - -L06FF LD E,(IX+02H) - LD D,(IX+03H) - PUSH DE - POP IY - LD E,(IY+01H) - LD D,(IY+02H) - CALL A07E8 - LD C,E - LD E,(IY+03H) - LD D,(IY+04H) - CALL A07E8 - LD B,E - LD E,(IY+00H) - LD D,00H - ADD HL,DE - ADD HL,DE - LD E,05H - ADD HL,DE - LD E,(HL) - INC HL - LD D,(HL) - EX DE,HL - PUSH BC - POP DE - LD C,(HL) - INC HL - LD B,(HL) - INC HL - LD A,(IX+05H) - BIT 7,A - JP NZ,A080B - PUSH BC - PUSH DE - PUSH HL - CP 70H - JR Z,L0744 - JR C,L074B -L0744 LD H,A - LD L,(IX+04H) - JR L0780 - -L074B LD HL,(VDP_Temp) - LD E,(IX+04H) - LD D,(IX+05H) - PUSH HL - PUSH DE - PUSH HL - LD BC,0004H - CALL _ReadVRAM - POP HL - LD A,(HL) - CP 80H - JR NZ,L0766 - POP DE - JR L077F - -L0766 INC HL - INC HL - LD B,(HL) - INC HL - LD E,(HL) - LD D,00H - INC HL - EX DE,HL - DB 0FEH ; CP n - skips the ADD HL,HL -L0771 ADD HL,HL - DJNZ L0771 - PUSH HL - POP BC - EX DE,HL - POP DE - INC DE - INC DE - INC DE - INC DE - CALL _ReadVRAM -L077F POP HL -L0780 LD A,(HL) - CP 80H - JR Z,L0794 - LD E,(HL) - INC HL - LD D,(HL) - INC HL - LD C,(HL) - INC HL - LD B,(HL) - INC HL - PUSH IX - CALL A080B - POP IX -L0794 POP HL - POP DE - POP BC - PUSH BC - PUSH DE - PUSH HL - LD L,(IX+04H) - LD H,(IX+05H) - LD A,70H - CP H - JR C,L07A8 - LD HL,(VDP_Temp) -L07A8 LD (HL),E - INC HL - LD (HL),D - INC HL - LD (HL),C - INC HL - LD (HL),B - INC HL - PUSH IX - CALL L0898 - POP IX - POP HL - POP DE - POP BC - PUSH IX - CALL A080B - POP IX - LD D,(IX+05H) - LD A,70H - CP D - RET Z - RET C - LD E,(IX+04H) - EXX - LD HL,(VDP_Temp) - PUSH HL - INC HL - INC HL - LD E,(HL) - LD D,00H - INC HL - LD B,(HL) - EX DE,HL - DB 0FEH ; CP n - skips the ADD HL,HL -L07DD ADD HL,HL - DJNZ L07DD - PUSH HL - EXX - POP BC - POP HL - JP _WrtVRAM - -L08E0 LD IY,(VDP_Temp) - LD L,(IX+02H) - LD H,(IX+03H) - INC HL - LD C,(HL) - INC HL - LD B,(HL) - LD A,B - OR A - JR Z,L0900 - INC A - JR NZ,L0A54 - LD A,C - CP E - JP M,L0A54 -L0900 INC HL - LD C,(HL) - INC HL - LD B,(HL) - LD A,B - OR A - JR Z,L0914 - INC A - JR NZ,L0A54 - LD A,C - CP E - JP M,L0A54 -L0914 DEC HL - DEC HL - LD A,(HL) - OR A - JR Z,L09CA - DEC HL - LD C,(HL) - INC HL - LD B,(HL) - RET - -L09CA POP HL ; get rid of return address - LD L,(IX+02H) - LD H,(IX+03H) - INC HL - LD A,(HL) - CALL L09D5 - LD A,(HL) -L09FD LD (IY+03H),A -L0A00 LD L,(IX+02H) - LD H,(IX+03H) - INC HL - INC HL - INC HL - LD A,(HL) - LD (IY+00H),A - CALL L09D8 - INC HL - LD A,(HL) - LD L,(IX+00H) - LD H,(IX+01H) - INC HL - ADD A,(HL) - LD (IY+02H),A - XOR A ; Sprite attribute table - LD D,A - LD E,(IX+04H) - PUSH IY - JR L0A7E - -L0A54 POP DE ; get rid of return address - PUSH IY - PUSH IX - PUSH IY - PUSH IY - XOR A ; Sprite attribute table - LD D,A - LD E,(IX+04H) - POP HL - CALL L1E92 ; LD IY,0001H / JP _BlkReadVRAM - XOR A - POP IY - LD (IY+01H),A - LD A,80H - LD (IY+03H),A - XOR A ; Sprite attribute table - LD D,A - POP IX - LD E,(IX+04H) -L0A7E POP HL - JP L1EA7 ; LD IY,0001H / JP _BlkWrtVRAM - -;*************************************** -; -; Initialize the video chip -; -;*************************************** -L1319 CALL InitScrn - -; Initialize the character cells for "COLECOVISION" - - LD HL,A18A3 ; Point to character cell usage list - LD DE,0060H ; Starting character code = 60H -L1330 PUSH HL - LD A,(HL) ; Get block ID - RLCA ; Multiply index by 8 - JP C,L1352 ; Check for end of list - RLCA - RLCA - LD C,A ; Load BC with block offset - LD B,D ; (D-reg = 00H here) - LD HL,A14C3 ; Point to block data -L1356 ADD HL,BC ; Point HL to block image - PUSH DE - CALL _BlkWrtVRAM31 ; LD A,03H LD IY,0001H JP _BlkWrtVRAM - POP DE - POP HL - INC DE - INC HL - JR L1330 - -InitScrn XOR A ; Fill VRAM from address 0000H - LD H,A ; with 00H - LD L,A ; - LD DE,4000H ; length 4000H - CALL _FillVRAM ; Do the fill - CALL _InitVDP ; Initialize the video chip - JP _InitFont ; Initialize the text font - - DB O,O,O,O,O,O,O,O,O,O - -A07E8 PUSH HL - SRA D - RR E - SRA D - RR E - SRA D - RR E - BIT 7,D - LD HL,0FF80H - JR NZ,L0802 - ADD HL,DE - POP HL - RET NC - LD E,7FH - RET - -L0802 LD H,00H ; LD HL,0080H - ADD HL,DE - POP HL - RET C - LD E,80H - RET - - DB O - -A080B PUSH BC ; (called by Antarctic Adventure and Destructor) - PUSH DE - PUSH HL - EXX - POP HL - POP DE - POP BC - CALL A08C0 - EXX - LD A,E - BIT 7,A - JR NZ,L081E - CP 20H - RET NC -L081E ADD A,C - BIT 7,A - RET NZ - OR A - RET Z - BIT 7,E - JR Z,L0848 - LD A,C - ADD A,E - PUSH DE - CP 21H - JR C,L0831 - LD A,20H -L0831 LD E,A - LD D,00H - PUSH DE - POP IY - POP DE - LD A,E - EXX - PUSH BC - NEG - LD C,A - LD B,00H - ADD HL,BC - EX DE,HL - ADD HL,BC - EX DE,HL - POP BC - EXX - JR L0864 - -L0848 LD A,E - ADD A,C - CP 1FH - JR Z,L085D - JR C,L085D - LD A,20H - SUB E - PUSH DE - LD E,A - LD D,00H - PUSH DE - POP IY - POP DE - JR L0864 - -L085D PUSH BC - LD B,00H - PUSH BC - POP IY - POP BC -L0864 LD E,00H -L0866 LD A,D - ADD A,E - BIT 7,A - JR NZ,L0885 - CP 18H - JR NC,L0885 - PUSH BC - PUSH DE - EXX - PUSH BC - PUSH DE - PUSH HL - PUSH IY - CALL _BlkWrtVRAM2 - POP IY - POP HL - POP DE - POP BC - EXX - POP DE - POP BC -L0885 EXX - PUSH BC - LD B,00H - ADD HL,BC - EX DE,HL - LD C,20H - ADD HL,BC - EX DE,HL - POP BC - EXX - INC E - LD A,E - CP B - JR NZ,L0866 - RET - -L0898 CALL A08C0 - PUSH BC - LD B,00H - PUSH BC - POP IY - POP BC -L08A2 PUSH BC - PUSH DE - PUSH HL - PUSH IY - LD A,02H ; Name table - CALL _BlkReadVRAM - POP IY - POP HL - POP DE - POP BC - PUSH BC - LD B,00H - ADD HL,BC - LD C,20H - EX DE,HL - ADD HL,BC - EX DE,HL - POP BC - DEC B - JR NZ,L08A2 - RET - - DB O,O,O,O - -A08C0 PUSH HL - LD H,00H ; sign-extend D -> HL - BIT 7,D - JR Z,L08CB - DEC H -L08CB LD L,D - ADD HL,HL ; HL = D * 32 (signed multiply) - ADD HL,HL - ADD HL,HL - ADD HL,HL - ADD HL,HL - LD D,00H ; sign-extend E -> DE - BIT 7,E - JR Z,L08DB - DEC D -L08DB JP L047C ; DE = (D * 32) + E (signed arithmetic) - -L0955 LD E,0E1H - CALL L08E0 - LD HL,0020H -L0999 ADD HL,BC - LD A,L - CALL L09D5 - LD A,(HL) - OR 80H - JP L09FD - -L0A87 LD IY,(VDP_Temp) - LD A,(VDP0Shad) ; Check for hi-res graphics - BIT 1,A - SET 7,B - JR NZ,L0A98 ; Branch if so - RES 7,B -L0A98 LD (IY+03H),B - PUSH HL - LD L,(IX+02H) - LD H,(IX+03H) - LD A,(HL) - LD (IY+04H),A - XOR 80H - LD (HL),A - INC HL - LD E,(HL) - LD A,E - AND 07H - NEG - ADD A,08H - LD (IY+01H),A - INC HL - LD D,(HL) - CALL A07E8 - LD (IY+11H),E - INC HL - LD E,(HL) - LD A,E - AND 07H - LD (IY+00H),A - INC HL - LD D,(HL) - CALL A07E8 - LD (IY+12H),E - LD HL,(VDP_Temp) - LD DE,0013H - ADD HL,DE - LD E,(IY+11H) - LD D,(IY+12H) - LD BC,0303H - CALL L0898 - LD E,(IX+04H) - LD D,(IX+05H) - LD A,(IX+06H) - POP IX - LD IY,(VDP_Temp) - LD (IY+05H),A - PUSH DE - LD HL,(VDP_Temp) - LD BC,0006H - ADD HL,BC - LD C,0BH - LD A,D - CP 70H - JR NC,L0B07 - CALL _ReadVRAM - JR L0B0A - -L0B07 EX DE,HL - LDIR -L0B0A LD HL,(VDP_Temp) - PUSH HL - LD DE,0013H - ADD HL,DE - EXX - POP DE - LD HL,0008H - ADD HL,DE - EX DE,HL - EXX - LD IY,(VDP_Temp) - LD C,(IY+05H) - LD B,09H -L0B25 LD A,(HL) - SUB C - CP 12H - JR NC,L0B39 - CP 09H - JR C,L0B31 - SUB 09H -L0B31 EXX - LD L,A - LD H,00H - ADD HL,DE - LD A,(HL) - EXX - LD (HL),A -L0B39 INC HL - DJNZ L0B25 - POP DE - LD HL,(VDP_Temp) - PUSH HL - LD BC,0011H - ADD HL,BC - LD C,0BH - LD A,D - CP 70H - JR NC,L0B51 - CALL _WrtVRAM - DB 11H ; LD DE,n - skips LDIR instruction -L0B51 LDIR - POP DE - PUSH IX - LD HL,0013H - ADD HL,DE - EX DE,HL - LD BC,0014H - ADD HL,BC - LD B,09H -L0B64 LD A,(DE) - INC DE - PUSH DE - LD DE,0008H - ADD HL,DE - PUSH HL - LD E,A -; LD D,00H - LD C,A - PUSH BC - LD A,09H - SUB B - LD B,D -L0B76 SUB 03H - JR C,L0B7D - INC B - JR L0B76 - -L0B7D LD A,B - LD IY,(VDP_Temp) - ADD A,(IY+12H) - BIT 7,(IY+03H) - JR NZ,L0BB8 - LD A,03H ; Pattern generator table - CALL L1E92 ; LD IY,0001H / JP _BlkReadVRAM - POP BC - LD HL,(VDP_Temp) - PUSH BC - LD DE,0084H - ADD HL,DE - LD E,C - SRL E - SRL E - SRL E -; LD D,00H - LD A,09H - SUB B - LD C,A - LD B,D - ADD HL,BC - JR L0BD6 - -L0BB8 SRA A - SRA A - SRA A - CP 03H - JR NC,L0BD9 - LD D,A - PUSH DE - PUSH HL - LD A,03H ; Pattern generator table - CALL L1E92 ; LD IY,0001H / JP _BlkReadVRAM - POP HL - LD DE,0068H - ADD HL,DE - POP DE -L0BD6 CALL L1E90 ; LD A,04H LD IY,0001H JP _BlkReadVRAM -L0BD9 POP BC - POP HL - POP DE - DJNZ L0B64 - POP IX - EXX - LD E,(IX+02H) - LD D,(IX+03H) - LD C,(IX+04H) - LD B,(IX+05H) - EXX - PUSH IX - POP HL - LD IY,(VDP_Temp) - LD A,(IY+04H) - ADD A,A - LD C,A - LD DE,0006H - LD B,D - ADD HL,DE - ADD HL,BC - LD E,(HL) - INC HL - LD D,(HL) - LD HL,(VDP_Temp) - LD BC,007CH - ADD HL,BC - PUSH HL - PUSH BC - LD C,05H - LD A,D - CP 70H - JR NC,L0C1A - CALL _ReadVRAM - JR L0C1D - -L0C1A EX DE,HL - LDIR -L0C1D LD IY,(VDP_Temp) - POP BC - ADD IY,BC - LD A,(IY+04H) - LD IY,(VDP_Temp) - LD (IY+02H),A - POP DE - LD HL,(VDP_Temp) - LD BC,0064H - ADD HL,BC - LD B,04H -L0C38 LD A,(DE) - CP (IX+01H) - PUSH DE - EXX - LD H,00H - JR NC,L0C55 - ADD A,A - ADD A,A - ADD A,A - LD L,A - ADD HL,BC - PUSH HL - EXX - POP DE -L0C7C EX DE,HL - PUSH BC - LD BC,0008H - LDIR - EX DE,HL - JR L0C84 - -L0C55 SUB (IX+01H) - ADD A,A - ADD A,A - ADD A,A - LD L,A - ADD HL,DE - PUSH HL - EXX - POP DE - LD A,D - CP 70H - JR NC,L0C7C - PUSH BC - PUSH HL - PUSH DE - LD BC,0008H - PUSH BC - CALL _ReadVRAM - POP BC - POP HL - ADD HL,BC - EX DE,HL - POP HL - ADD HL,BC -L0C84 POP BC - POP DE - INC DE - DJNZ L0C38 - LD IY,(VDP_Temp) - LD DE,(VDP_Temp) - LD HL,001CH - ADD HL,DE - LD C,(IY+00H) - LD B,00H - ADD HL,BC - PUSH HL - POP IX - LD HL,0064H - ADD HL,DE - PUSH HL - LD A,10H -L0CA5 EX AF,AF' - POP HL - LD D,(HL) - INC HL - PUSH HL - LD BC,000FH - ADD HL,BC - LD E,(HL) - EX DE,HL - LD B,(IY+01H) - XOR A -L0CB4 DEC B ; cheap HL=HL< - HEX 3C 66 06 0C 18 00 18 00 ; ? - HEX 3E 63 67 6B 6E 60 3E 00 ; @ -D16AB HEX 1C 36 63 63 7F 63 63 00 ; A - HEX 7E 63 63 7E 63 63 7E 00 ; B - HEX 1E 33 60 60 60 33 1E 00 ; C - HEX 7C 66 63 63 63 66 7C 00 ; D - HEX 7F 60 60 7E 60 60 7F 00 ; E - HEX 7F 60 60 7E 60 60 60 00 ; F - HEX 1F 30 60 67 63 33 1F 00 ; G - HEX 63 63 63 7F 63 63 63 00 ; H - HEX 3F 0C 0C 0C 0C 0C 3F 00 ; I - HEX 03 03 03 03 03 63 3E 00 ; J - HEX 63 66 6C 78 7C 6E 67 00 ; K - HEX 60 60 60 60 60 60 7F 00 ; L - HEX 63 77 7F 7F 6B 63 63 00 ; M - HEX 63 73 7B 7F 6F 67 63 00 ; N - HEX 3E 63 63 63 63 63 3E 00 ; O - HEX 7E 63 63 63 7E 60 60 00 ; P - HEX 3E 63 63 63 6F 66 3D 00 ; Q - HEX 7E 63 63 67 7C 6E 67 00 ; R - HEX 3C 66 60 3E 03 63 3E 00 ; S - HEX 3F 0C 0C 0C 0C 0C 0C 00 ; T - HEX 63 63 63 63 63 63 3E 00 ; U - HEX 63 63 63 77 3E 1C 08 00 ; V - HEX 63 63 6B 7F 7F 77 63 00 ; W - HEX 63 77 3E 1C 3E 77 63 00 ; X - HEX 33 33 33 1E 0C 0C 0C 00 ; Y - HEX 7F 07 0E 1C 38 70 7F 00 ; Z - HEX 1E 18 18 18 18 18 1E 00 ; [ - HEX 00 60 30 18 0C 06 03 00 ; \ - HEX 3C 0C 0C 0C 0C 0C 3C 00 ; ] - HEX 08 1C 36 63 00 00 00 00 ; ^ - HEX 00 00 00 00 00 00 7F 00 ; _ - HEX 18 18 0C 00 00 00 00 00 ; ` - HEX 00 00 3C 06 3E 66 3E 00 ; a - HEX 60 60 7C 66 66 66 7C 00 ; b - HEX 00 00 3C 66 60 66 3C 00 ; c - HEX 06 06 3E 66 66 66 3E 00 ; d - HEX 00 00 3C 66 7E 60 3C 00 ; e - HEX 1C 36 30 78 30 30 30 00 ; f - HEX 00 00 3E 66 66 3E 06 3C ; g - HEX 60 60 7C 66 66 66 66 00 ; h - HEX 18 00 38 18 18 18 3C 00 ; i - HEX 06 00 0E 06 06 66 3C 00 ; j - HEX 60 60 66 6C 78 6C 66 00 ; k - HEX 38 18 18 18 18 18 3C 00 ; l - HEX 00 00 76 7F 6B 63 63 00 ; m - HEX 00 00 7C 66 66 66 66 00 ; n - HEX 00 00 3C 66 66 66 3C 00 ; o - HEX 00 00 7C 66 66 7C 60 60 ; p - HEX 00 00 3E 66 66 3E 06 03 ; q - HEX 00 00 7C 66 60 60 60 00 ; r - HEX 00 00 3E 60 3C 06 7C 00 ; s - HEX 00 18 3C 18 18 18 0C 00 ; t - HEX 00 00 66 66 66 66 3E 00 ; u - HEX 00 00 66 66 66 3C 18 00 ; v - HEX 00 00 63 63 6B 7F 36 00 ; w - HEX 00 00 66 3C 18 3C 66 00 ; x - HEX 00 00 66 66 66 3E 06 7C ; y - HEX 00 00 7E 0C 18 30 7E 00 ; z - HEX 0C 18 18 30 18 18 0C 00 ; { - HEX 18 18 18 00 18 18 18 00 ; | - HEX 30 18 18 0C 18 18 30 00 ; } - HEX 30 5A 0C 00 00 00 00 00 ; ~ - HEX 54 28 54 28 54 28 54 00 ; del - -; Character cell to font data mapping for COLECOVISION - -A18A3 HEX 01 02 0E 0F 08 09 12 13 ; CV - HEX 03 04 0E 0F 05 14 00 00 ; OI - HEX 05 00 10 11 0A 0B 15 16 ; LS - HEX 06 07 10 11 05 14 00 00 ; EI - HEX 01 02 0E 0F 03 04 0E 0F ; CO - HEX 03 04 0E 0F 0C 0D 17 18 ; ON - HEX FF ; end of list - -;*************************************** -; 1F82 FillVRAM -; -; Fills a block of VRAM with the same byte -; -; ENTRY HL = start VRAM address -; DE = count -; A = fill byte -; EXIT AF, C, DE destroyed -;*************************************** -A18D4 -_FillVRAM LD C,A ; Save fill byte - LD A,L ; Output low byte of VRAM address - OUT (IO_VDP_Addr),A - LD A,H ; Output high byte of VRAM address - OR 40H ; set "this is an address" bit - OUT (IO_VDP_Addr),A -L18DD LD A,C ; Get back fill byte (and delay?) - OUT (IO_VDP_Data),A ; Store data byte - DEC DE ; Decrement count - LD A,D - OR E - JR NZ,L18DD ; Store bytes until done - JP _VDP_Status ; Read VDP status register - - DB O - -;*************************************** -; 1F85 InitVDP -; -; Initialize the VDP chip -;*************************************** -A18E9 -_InitVDP LD BC,0000H ; Register 0: half-text 32x24 mode - CALL _WriteReg - - LD BC,0180H ; Reg 1, 32x24 mode, 16K DRAM, blank - CALL _WriteReg - NOP - NOP - -A18F7 ; (called by Tomarc the Barbarian) - - LD A,03H ; Pattern generator table - LD HL,0000H ; VRAM address 0000H - CALL _BaseLoad - - LD A,02H ; Name table (display) - LD HL,1800H ; VRAM address 1800H - CALL _BaseLoad - - XOR A ; Sprite attribute table - LD HL,1B00H ; VRAM address 1B00H - CALL _BaseLoad - - LD A,04H ; Color table - LD HL,2000H ; VRAM address 2000H - CALL _BaseLoad - - LD A,01H ; Sprite pattern generator -D1AC5 EQU $+2 ; DB '8' - LD HL,3800H ; VRAM address 3800H - CALL _BaseLoad - - LD BC,0700H ; Reg 7 (FG/BG color), set both to 0 - JP _WriteReg - -;*************************************** -; 1F7F InitFont -; -; Initialize pattern generator (font) table -;*************************************** -_InitFont LD HL,A158B ; Point to main ASCII bitmaps - LD DE,001DH ; First character code = 1DH - LD IY,0063H ; bug fixed (was 0060) - CALL _BlkWrtVRAM3 ; Pattern generator table - - LD HL,A15A3 ; Point to blank bitmap - LD DE,0000H ; First character code = 00H -_BlkWrtVRAM31 LD A,03H ; Pattern generator table - JP L1EA7 ; LD IY,0001H / JP _BlkWrtVRAM - -;*************************************** -; -; Search for '/' character in text pointed to by HL. -; -; ENTRY HL points to text -; -; EXIT: HL points to '/' character -; BC = number of bytes before '/' character -; -;*************************************** -L1946 LD BC,0000H ; Initialize count to zero -L1949 LD A,(HL) ; Get next byte - CP '/' ; Return if '/' character - RET Z - INC HL ; Point to next byte - INC BC ; Increment count - JR L1949 ; Go back for more - -;*************************************** -; -; Center a line of text on the screen. -; -; ENTRY BC = length of text -; DE = pointer to text -; HL = screen position at left end of line -; -;*************************************** -L1951 PUSH BC ; Move BC to IY (count) - POP IY - LD A,20H ; A = (20H - C) / 2 - SBC A,C ; (centering offset) - RRA - LD B,00H - LD C,A - ADD HL,BC ; HL = HL + BC - EX DE,HL ; HL = text ptr, DE = scrn position - JP _BlkWrtVRAM2 ; LD A,02H / JP _BlkWrtVRAM - -;*************************************** -; -; Delay routines -; -; 1968 is the infamous "seven second delay" and is apparently -; not called elsewhere in the ROM and shouldn't be called by -; "well behaved" cartridges. Which means that it would be safe -; to change, except that some Xonox cartridges call it. However, -; shortening the delay would probably make some of those games -; more playable, so we can change it in the name of humanity. -; -; 196B delays using a count in the HL register. The delay is -; approximately H/3 seconds. -; -;*************************************** -;A1968 LD HL,1700H ; Too long -;A196B LD DE,00FFH ; Load inner loop count -;L196E DEC DE -; LD A,D -; OR E -; JR NZ,L196E -; DEC HL -; LD A,H -; OR L -; JR NZ,A196B -; RET - -; This replacement is based on Kev's patch. Every outer loop it checks -; both left fire buttons and aborts the delay loop if either is pressed. -; -; The main difference is that I save the AF and BC registers on the -; assumption that anyone "byte-fisted" enough to call the ROM instead of -; spending a few bytes to write his own might also expect it not to mess -; with the A register or B register. -; -; The other side-effect of this replacement delay routine is that the -; joystick ports are left in stick mode, but this is probably okay. - -L196C JR Z,L1978 ; exit if pressed - - LD DE,00E8H ; load inner loop counter (about 10% less) -L196E DEC DE ; do inner loop - LD A,D - OR E - JR NZ,L196E - - DEC HL ; do outer loop - LD A,H - OR L - JR NZ,L196B - -L1978 POP BC ; restore regs & return - POP AF - RET - -A1968 LD HL,1700H ; startup screen delay timer -A196B PUSH AF ; original routine didn't mess with A or B! - PUSH BC - -L196B OUT (0C0H),A ; select left fire/stick mode - IN A,(0FCH) ; read left fire button - LD B,A - IN A,(0FFH) ; read right fire button - AND B ; OR the two sticks together - AND 40H ; mask out the fire button bit - JR L196C - -;*************************************** -; 1F7C SkillScrn -; -; Displays the skill select screen and returns -;*************************************** -A1979 -_SkillScrn CALL InitScrn ; Clear VRAM and initialize the VDP - - LD BC,0F04H ; Reg 0FH (FG/BG color), value = 4 - CALL _WriteReg ; write it - - LD HL,Skill_Msgs ; Put up skill screen messages - CALL ScrnMsgs - - LD HL,(ClrTabShad) ; Get color table VRAM addr - LD DE,0020H ; 32 bytes - LD A,0F4H ; Fill with F4H - CALL _FillVRAM ; fill it - - LD BC,01C0H ; Unblank the screen - JP _WriteReg - -D1AC9 EQU $+3 ; DB 'S' -D1A7C DB 'TO SELECT GAME OPTION,' -D1AA9 DB '1 = SKILL 1/ONE PLAYER' - -; HL=msg,IY=len,DE=scrn -Skill_Msgs DW D1A7C,22*1024+0025H ; 'TO SELECT GAME OPTION,' - DW D1A92,23*1024+0065H ; 'PRESS BUTTON ON KEYPAD.' - DW D1AA9,22*1024+00C5H ; '1 = SKILL 1/ONE PLAYER' - DW D1AA9,22*1024+0105H ; '1 = SKILL 1/ONE PLAYER' - DW D1AA9,22*1024+0145H ; '1 = SKILL 1/ONE PLAYER' - DW D1AA9,22*1024+0185H ; '1 = SKILL 1/ONE PLAYER' - DW D1AA9,22*1024+01E5H ; '1 = SKILL 1/ONE PLAYER' - DW D1AA9,22*1024+0225H ; '1 = SKILL 1/ONE PLAYER' - DW D1AA9,22*1024+0265H ; '1 = SKILL 1/ONE PLAYER' - DW D1AA9,22*1024+02A5H ; '1 = SKILL 1/ONE PLAYER' - DW D1ABF,01*1024+0105H ; '2' - DW D1AC0,01*1024+0145H ; '3' - DW D1AC1,01*1024+0185H ; '4' - DW D1AC2,01*1024+01E5H ; '5' - DW D1AC3,01*1024+0225H ; '6' - DW D1AC4,01*1024+0265H ; '7' - DW D1AC5,01*1024+02A5H ; '8' - DW D1ABF,01*1024+010FH ; '2' - DW D1AC0,01*1024+014FH ; '3' - DW D1AC1,01*1024+018FH ; '4' - DW D1AC6,03*1024+01F1H ; 'TWO' - DW D1AC6,03*1024+0231H ; 'TWO' - DW D1AC6,03*1024+0271H ; 'TWO' - DW D1AC6,03*1024+02B1H ; 'TWO' - DW D1ABF,01*1024+022FH ; '2' - DW D1AC0,01*1024+026FH ; '3' - DW D1AC1,01*1024+02AFH ; '4' - DW D1AC9,01*1024+01FBH ; 'S' - DW D1AC9,01*1024+023BH ; 'S' - DW D1AC9,01*1024+027BH ; 'S' - DW D1AC9,01*1024+02BBH ; 'S' - DW 0 ; End of table - -;*************************************** -; Put up the "no cartridge" message -;*************************************** - -L13FF LD HL,No_Cart_Msgs ; Put up "TURN GAME OFF" messages - CALL ScrnMsgs - - LD HL,8A00H ; Wait a long time for the user to see - CALL A196B - - LD BC,0180H ; Then blank the screen - CALL _WriteReg - -L1439 JR L1439 ; and go to sleep - NOP ; to allow for patching - -; HL=msg,IY=len,DE=scrn -No_Cart_Msgs DW D1479,13*1024+01AAH ; 'TURN GAME OFF' - DW D1486,26*1024+01E4H ; 'BEFORE INSERTING CARTRIDGE' - DW D14A0,20*1024+0227H ; 'OR EXPANSION MODULE.' - DW 0 ; End of table - -;*************************************** -; Display a bunch of text all over the screen -; -; ENTRY: HL=table pointer -; EXIT: BC=0 -; -; The table is a bunch of 4-byte entries: -; 0-1 address of message text data -; 2 low byte of screen address -; 3 high byte of screen address in low 2 bits -; message text length in high 6 bits -;*************************************** - -ScrnMsgs LD C,(HL) ; Get message address to BC - INC HL - LD B,(HL) - INC HL - - LD A,C ; Test for end of table - OR B - RET Z - - LD E,(HL) ; Get display address to DE - INC HL - LD A,(HL) - AND 03H - LD D,A - - LD A,(HL) ; Get message length to A - INC HL - RRCA - RRCA - AND 3FH - - PUSH BC ; Save message address - EX (SP),HL ; Msg addr to HL, save table pointer - - LD C,A ; Move message length to IY - LD B,0 - PUSH BC - POP IY - - CALL _BlkWrtVRAM2 ; LD A,02H/JP _BlkWrtVRAM - - POP HL ; Recover table pointer - JR ScrnMsgs ; Loop for next message - -;*************************************** -; 1FAF -; -; Parameter block version of 1FE5 -; -; Parm 1 (byte) = ? -; Parm 2 (lit) = ? -;*************************************** -L0655 LD BC,D064F - LD DE,ParmArea - CALL PCopy - LD A,(ParmArea) - LD HL,(ParmArea+1) - -;*************************************** -; 1FE5 -; -; ENTRY A = ? -; HL = ? -;*************************************** -L0664 LD (73CAH),A - XOR A -; LD (73CBH),A - LD (73CCH),A - LD (73D1H),HL -; LD (73CDH),HL - LD (73CFH),HL - JP L0669 - -;*************************************** -; 1F88 ReadSpinner -; -; This was included to support the "spinner" control that -; was originally planned to be in the regular controllers. -; It was later included in the Super Action controllers. -; Early versions of the controller circuit board even have -; circuit traces and holes for the spinner parts. -; -; Apparently the 20H bit is a direction bit, and the 10H -; bit is a "pulse" bit. -;*************************************** -_ReadSpinner LD HL,PulseCnt1 ; Point to first pulse counter - IN A,(IO_Joy1) ; Read joystick 1 - CALL L117D ; Do first pulse counter - INC HL ; Point to second pulse counter - IN A,(IO_Joy2) ; Read joystick 2 - -L117D BIT 4,A ; Test 10H bit - RET NZ ; Return if set (no pulse) -L1182 BIT 5,A ; Test 20H bit - JR NZ,L1189 ; Inc counter if set - DEC (HL) ; Dec counter if clear - RET - -D1AC1 ; DB '4' -L1189 INC (HL) - RET - -;*************************************** -; 1FE8 -; -; -;*************************************** -L0679 LD A,(D73C6) - PUSH AF - XOR A - LD (D73C6),A -L0682 LD A,(73CCH) - LD HL,73CBH - CP (HL) - JR Z,L06BC - LD HL,(73CFH) - LD E,(HL) - INC HL - LD D,(HL) - INC HL - LD B,(HL) - INC HL - PUSH DE - POP IX - PUSH HL - CALL L06E3 - LD A,(73CCH) - INC A - LD HL,73CAH - CP (HL) - JR NZ,L06B3 - XOR A - LD HL,(73D1H) - LD (73CFH),HL - POP HL - JR L06B9 - -L06B3 POP HL - LD (73CFH),HL -L06B9 LD (73CCH),A - JR L0682 - -L06BC POP AF - LD (D73C6),A - RET - - DB O,O,O,O,O,O,O,O,O,O - DB O,O,O,O,O - -;*************************************** -; 1F8B PBaseLoad -; -; Parameter block version of 1FB8 -; -; P1 (byte) = base register code -; P2 (word) = raw unshifted VRAM address -;*************************************** -_PBaseLoad LD BC,P_BaseLoad - LD DE,ParmArea - CALL PCopy - LD A,(ParmArea) - LD HL,(ParmArea+1) - -;*************************************** -; 1FB8 BaseLoad -; -; This routine loads a VDP base register with the -; specified base address. The base address is stored -; in one of the shadow registers at 73F2. -; -; ENTRY A = base register code -; HL = raw unshifted VRAM address -;*************************************** -A1B1D -_BaseLoad LD C,A ; VDP register code to BC - LD B,00H - LD IX,VDPBaseShad - ADD IX,BC ; Index into shadow address table - ADD IX,BC - LD (IX+00H),L ; Store shadow copy of base address - LD (IX+01H),H - LD A,(VDP0Shad) ; Get current graphics mode - BIT 1,A - JR Z,L1B5C ; If not in hi-res graphics, go shift - LD A,C - CP 03H ; Special handling for pattern gen - JR Z,L1B40 - CP 04H ; and color tables - JR NZ,L1B5C ; Else branch to go shift - -; Set color table base address in hi-res graphics mode - - LD B,03H ; VDP register 3 = color table - LD A,L ; If VRAM addr = 0, - OR H - LD C,7FH ; set base register to 7FH (1FC0H) - JR Z,L1B72 - LD C,0FFH ; Else set it to FFH (3FC0H) - JR L1B72 - -; Set pattern generator base address in hi-res graphics mode - -L1B40 LD B,04H ; VDP register 4 = pattern generator - LD A,L ; If VRAM addr = 0, - OR H - LD C,03H ; set base register to 03H (1800H) - JR Z,L1B72 - LD C,07H ; Else set it to 07H (3800H) - JR L1B72 - -L1B5C LD IY,D1B76 ; Get address of shift table - ADD IY,BC ; Index into it - ADD IY,BC - LD A,(IY+00H) ; Get shift count - LD B,(IY+01H) ; Get VDP register number -L1B6A SRL H ; Shift the base address right - RR L ; to adjust for VDP register - DEC A - JR NZ,L1B6A - LD C,L ; Get shifted VDP register data -L1B72 JP _WriteReg ; Write it to the VDP chip - -; Shift table for VDP base addresses (shift, reg num) - -D1B76 DB 7,5 ; 0 = Sprite attribute table - DB 11,6 ; 1 = Sprite pattern generator - DB 10,2 ; 2 = Name table - DB 11,4 ; 3 = Pattern generator - DB 6,3 ; 4 = Color table - -; ReadVRAM with the bug fixed - -XReadVRAM LD A,C ; no bug if C=00H - OR A - JR Z,XReadVRAM_a - - INC B ; else account for the missing page - -XReadVRAM_a JP ReadVRAM - -;*************************************** -; 1F8E PBlkReadVRAM -; -; Parameter block version of 1FBB -; -; Parm 1 (byte) = VDP table number (0-4) -; Parm 2 (byte) = VDP table index LSB -; Parm 3 (byte) = VDP table index MSB -; Parm 4 (lit) = pointer to data buffer -; Parm 5 (word) = VDP table entry count -;*************************************** -P_BlkReadVRAM -P_BlkWrtVRAM DB 5 - DW 1,1,1,-2,2 - -_PBlkReadVRAM LD BC,P_BlkReadVRAM - LD DE,ParmArea - CALL PCopy - LD A,(ParmArea) - LD DE,(ParmArea+1) - LD IY,(ParmArea+5) - LD HL,(ParmArea+3) - -;*************************************** -; 1FBB BlkReadVRAM -; -; ENTRY A = VDP table number (0-4) -; DE = VDP table index -; HL points to data buffer -; IY = VDP table entry count -;*************************************** -A1BA3 -_BlkReadVRAM CALL VRAM_Index - JR XReadVRAM - - DB O,O - -;*************************************** -; VRAM_Index -; -; This routine returns the actual VRAM address and size -; of a block of VDP table entries. -; -; ENTRY DE = VDP table index -; IY = number of VDP table entries -; A = VDP table number (0-4) -; -; EXIT: BC = number of bytes to move to VRAM -; DE = VRAM address -; HL register is not changed -;*************************************** -A1BAA -VRAM_Index LD (D73FE),IY ; Save byte count - LD IX,VDPBaseShad ; VDP base addr shadow array - LD C,A ; BC = VRAM table index - LD B,00H - CP 04H ; Check if color table - JR NZ,L1BC0 - LD A,(VDP0Shad) ; Yes, check for hi-res graphics - BIT 1,A ; Don't shift color table unless - JR Z,L1BEC ; using hi-res graphics -L1BC0 LD IY,D1BFF ; Point to shift table - ADD IY,BC ; Index into shift table - LD A,(IY+00H) ; Get shift value - OR A - JR Z,L1BEC ; Branch if no shift -L1BCD SLA E ; Shift VRAM offset - RL D - DEC A - JR NZ,L1BCD ; until done - PUSH BC ; Save VRAM table index - LD BC,(D73FE) ; Get original byte count - LD A,(IY+00H) ; Get shift value - OR A - JR Z,L1BEB ; Branch if no shift -L1BE0 SLA C ; Shift byte count - RL B - DEC A - JR NZ,L1BE0 ; until done - LD (D73FE),BC ; Save shifted byte count -L1BEB POP BC ; Get back VRAM table index -L1BEC PUSH HL ; Save HL - ADD IX,BC ; Index into base addr shadow array - ADD IX,BC - LD L,(IX+00H) ; Get base VRAM address from shadow - LD H,(IX+01H) - ADD HL,DE ; Add shifted offset to base addr - EX DE,HL ; Put VRAM address in DE - POP HL ; Restore HL - LD BC,(D73FE) ; Get byte count - RET - -; Shift table for indexes into VDP tables (1, 4, or 8 bytes per entry) - -D1BFF DB 2 ; 0 = Sprite attribute table - DB 3 ; 1 = Sprite pattern generator table - DB 0 ; 2 = Name table - DB 3 ; 3 = Pattern generator table - DB 3 ; 4 = Color table - -; Copy high 4 bits of (HL) into low 4 bits of (HL) - -L01A6 LD A,(HL) - AND 0F0H - LD B,A - RRCA - RRCA - RRCA - RRCA - OR B - LD (HL),A - RET - -;*************************************** -; 1F91 PBlkWrtVRAM -; -; Parameter block version of 1FBE -; -; Parm 1 (byte) = VDP table number (0-4) -; Parm 2 (byte) = VDP table index LSB -; Parm 3 (byte) = VDP table index MSB -; Parm 4 (lit) = pointer to data to be written -; Parm 5 (word) = VDP table entry count -;*************************************** -_PBlkWrtVRAM LD BC,P_BlkWrtVRAM - LD DE,ParmArea - CALL PCopy - LD A,(ParmArea) - LD DE,(ParmArea+1) - LD IY,(ParmArea+5) - LD HL,(ParmArea+3) - - DB 01H ; LD BC,nnnn -_BlkWrtVRAM2 LD A,02H ; name table (character cells) - -;*************************************** -; 1FBE BlkWrtVRAM -; -; ENTRY A = VDP table number (0-4) -; DE = VDP table index -; HL points to data to be written -; IY = VDP table entry count -; 73C7H = 01H to write to RAM sprite attr table -;*************************************** -A1C27 -_BlkWrtVRAM PUSH AF ; Save VDP table number - OR A ; If not sprite attribute table, - JR NZ,L1C4E ; always write to the VDP - LD A,(WrtRAMSprt) ; Check RAM sprite attr table flag - DEC A - JR NZ,L1C4E ; Write to VDP if not 01H - EX (SP),HL ; Clean up stack and save data pointer - LD HL,(RamSprtTab) ; Get pointer at 8002H - ADD HL,DE ; DE*4 = sprite table - ADD HL,DE - ADD HL,DE - ADD HL,DE ; dest addr = (8002H) + DE - EX DE,HL - PUSH IY ; BC = table entry count - POP BC - SLA C ; C = C * 4 for sprite table - SLA C ; I hope BC was <= 3FH! - POP HL ; Restore (source) data pointer - LDIR ; Copy it - RET - -_BlkWrtVRAM3 LD A,03H ; Pattern generator table - DB 01H ; LD BC,nnnn -_BlkWrtVRAM4 LD A,04H ; Color table - JR _BlkWrtVRAM - - DB O,O - -L1C4E POP AF ; Restore VDP table number -A1C4F ; (Called by Aquattack) - CALL VRAM_Index ; Adjust for VDP table size - JR XWrtVRAM ; Write the data to VRAM - -;*************************************** -; 1F94 PInitRAMSprt -; -; Parameter block version of 1FC1 -; -; Parm 1 (byte) = number of sprites -;*************************************** -_PInitRAMSprt LD BC,P_InitRAMSprt - LD DE,ParmArea - CALL PCopy - LD A,(ParmArea) - -;*************************************** -; 1FC1 InitRAMSprt -; -; This routine initializes the RAM sprite index table -; pointed to by 8004H with values from 00H to A-1 -; -; ENTRY A = number of sprites -;*************************************** -_InitRAMSprt LD B,A ; B = count - XOR A ; Init fill to zero - LD HL,(RAMSprtIdx) ; Get pointer to RAM sprite index table -L1C6B LD (HL),A ; Initialize array entry - INC HL ; Increment array pointer - INC A ; Increment fill value - CP B ; Go back until done - JR NZ,L1C6B - RET - -; WrtVRAM with the bug fixed - -XWrtVRAM LD A,C ; no bug if C=00H - OR A - JR Z,XWrtVRAM_a - - INC B ; else account for the missing page - -XWrtVRAM_a JP _WrtVRAM - - DB O,O - -;*************************************** -; 1F97 PCopyRAMSprt -; -; Parameter block version of 1FC4 -; -; Parm 1 (byte) = number of sprites -;*************************************** -_PCopyRAMSprt LD BC,P_CopyRAMSprt - LD DE,ParmArea - CALL PCopy - LD A,(ParmArea) - -;*************************************** -; 1FC4 CopyRAMSprt -; -; This routine copies data from the RAM sprite attribute -; table at (8002H) to VRAM. The RAM sprite index table at -; (8004H) contains a list of one byte indexes into the RAM -; sprite attribute table. Each byte corresponds to one real -; (VRAM) sprite attr table entry and references one RAM -; sprite attr table entry to use as a template. -; -; ENTRY A = number of sprites -;*************************************** -A1C82 -_CopyRAMSprt LD IX,(RAMSprtIdx) ; Get pointer to RAM sprite index table - PUSH AF - LD IY,SprtTabShad ; Get sprite table base VRAM address - LD E,(IY+00H) - LD D,(IY+01H) - LD A,E ; Send LSB of address - OUT (IO_VDP_Addr),A - LD A,D - OR 40H ; Set write flag - OUT (IO_VDP_Addr),A ; Send MSB of address - POP AF -L1C9A LD HL,(RamSprtTab) ; Get pointer at 8002H - LD C,(IX+00H) ; Get next index byte from 8004H table - INC IX - LD B,00H ; HL = (8002H) + (IX)*4 - ADD HL,BC - ADD HL,BC - ADD HL,BC - ADD HL,BC - LD B,04H ; B = count for 4 bytes of data - LD C,IO_VDP_Data ; C = output port -L1CAC OUTI ; Output a byte of data - NOP ; Wait for the VDP to catch up - NOP - JR NZ,L1CAC ; Loop until 4 bytes copied - DEC A - JR NZ,L1C9A ; Loop until all sprites copied - RET - - DB O,O,O,O,O,O - -;*************************************** -; 1FA6 PWriteReg -; -; Parameter block version of 1FD9 -; -; Parm 1 (byte) = VDP register number -; Parm 2 (byte) = data to write to register -;*************************************** - -_PWriteReg LD BC,P_WriteReg - LD DE,ParmArea - CALL PCopy - LD HL,(ParmArea) - LD C,H - LD B,L - -;*************************************** -; 1FD9 WriteReg -; -; ENTRY B = VDP register number -; C = data to write to register -;*************************************** -A1CCA -_WriteReg LD A,C ; Send VDP register data - OUT (IO_VDP_Addr),A - LD A,B - ADD A,80H ; Set "write register" bit - OUT (IO_VDP_Addr),A ; Send register number - LD A,B ; If register 0... - OR A - JR NZ,L1CDB - LD A,C - LD (VDP0Shad),A ; ...update register 0 shadow -L1CDB LD A,B ; If register 1... - CP 01H ; If this is changed to DEC A, Smurf won't work! - RET NZ - LD A,C - LD (VDP1Shad),A ; ...update register 1 shadow - RET - -; Decrement low 4 bits of (HL) - -L0190 XOR A - RRD - SUB 01H - PUSH AF - RLD - POP AF - RET - -; Decrement high 4 bits of (HL) (NOT USED!) -; -;L019B XOR A -; RLD -; SUB 01H -; PUSH AF -; RRD -; POP AF -; RET - -;*************************************** -; 1FA9 PWrtVRAM -; -; Parameter block version of 1FDF -; -; Parm 1 (lit) = pointer to data to be written -; Parm 2 (word) = VRAM address -; Parm 3 (word) = byte count -;*************************************** -_PWrtVRam LD BC,P_WrtVRAM - LD DE,ParmArea - CALL PCopy - LD HL,(ParmArea) - LD DE,(ParmArea+2) - LD BC,(ParmArea+4) - -;*************************************** -; 1FDF WrtVRAM -; -; ENTRY HL points to data to be written -; DE = VRAM address -; BC = byte count (see note) -; EXIT: HL = first byte after data that was written -; AF, B, D destroyed -; -; Note: there is a bug which causes 256 too few bytes to be -; copied if the B and C registers are both non-zero, -; and there are games which do depend on this! -; BlkWrtVRAM is also affected by this, but is -; probably never called with enough bytes to matter. -;*************************************** -A1D01 -_WrtVRAM LD A,E ; Send LSB of address - OUT (IO_VDP_Addr),A - LD A,D - ADD A,40H ; Send MSB of address + 40H - OUT (IO_VDP_Addr),A - LD D,B ; D = MSB of byte count - LD B,C ; B = LSB of byte count - LD C,IO_VDP_Data ; C = port address -L1D14 OUTI ; Output a byte of data - NOP ; Wait for the VDP to catch up - NOP - JR NZ,L1D14 ; LSB loop - DEC D ; Decrement MSB of count - RET M ; MSB loop - JR NZ,L1D14 ; BUG: should have been JR L1D14 - RET - -; HL=msg,IY=len,DE=scrn -Title_Msgs DW A144D,22*1024+0085H ; first row of COLECOVISION - DW A1463,22*1024+00A5H ; second row of COLECOVISION - DW A14C1,02*1024+009BH ; TM - DW A14B4,13*1024+02AAH ; 'c 1982 COLECO' - DW 0 ; End of table - -;*************************************** -; 1FAC PReadVRAM -; -; Parameter block version of 1FE2 -; -; Parm 1 (lit) = pointer to data buffer -; Parm 2 (word) = VRAM address -; Parm 3 (word) = byte count -;*************************************** - -_PReadVRAM LD BC,P_ReadVRam - LD DE,ParmArea - CALL PCopy - LD HL,(ParmArea) - LD DE,(ParmArea+2) - LD BC,(ParmArea+4) - -;*************************************** -; 1FE2 ReadVRAM -; -; ENTRY HL points to data buffer -; DE = VRAM address -; BC = byte count (see note) -; EXIT: HL = first byte after data that was read -; AF, B, D destroyed -; -; Note: there is a bug which causes 256 too few bytes to be -; copied if the B and C registers are both non-zero, -; and there are games which do depend on this! -; BlkReadVRAM is also affected by this, but is -; probably never called with enough bytes to matter. -;*************************************** -A1D3E -_ReadVRAM LD A,E ; Send LSB of address - OUT (IO_VDP_Addr),A - LD A,D ; Send MSB of address -A1D43 EQU $+1 ; (Used by many Coleco carts) - OUT (IO_VDP_Addr),A - LD D,B ; D = MSB of byte count - LD B,C ; B = LSB of byte count -A1D47 EQU $+1 ; (Used by many Coleco carts) - LD C,IO_VDP_Data ; C = port address -L1D49 INI ; Input a byte of data - NOP ; Wait for the VDP to catch up - NOP - JR NZ,L1D49 ; LSB loop - DEC D ; Decrement MSB of count - RET M ; MSB loop - JR NZ,L1D49 ; BUG: should have been JR L1D49 - RET - - DB O,O,O,O - -;*************************************** -; 1FDC VDP_Status -; -; This routine returns the VDP status byte in A. -; -; EXIT: A = VDP status byte -;*************************************** -A1D57 -_VDP_Status IN A,(IO_VDP_Status) ; Get VDP status - RET ; and return - -;*************************************** -; 1F6A FlipRL -; -; Right/Left flip a list of images -; -; ENTRY A = VDP table code (0-4) -; BC = number of VDP table entries -; DE = source VDP table index -; HL = destination VDP table index -;*************************************** -A1D5A -_FlipRL LD IX,__FlipRL - JR L1D70 - -;*************************************** -; 1F6D FlipUD -; -; Up/Down flip a list of images -; -; ENTRY A = VDP table code (0-4) -; BC = number of VDP table entries -; DE = source VDP table index -; HL = destination VDP table index -;*************************************** -A1D60 -_FlipUD LD IX,__FlipUD - JR L1D70 - -;*************************************** -; 1F70 Rotate -; -; Rotate a list of images by 90 degrees clockwise -; -; ENTRY A = VDP table code (0-4) -; BC = number of VDP table entries -; DE = source VDP table index -; HL = destination VDP table index -;*************************************** -A1D66 -_Rotate LD IX,__Rotate - JR L1D70 - -;*************************************** -; 1F73 Expand -; -; Expand a list of 8x8 images to 16x16 -; -; ENTRY A = VDP table code (0-4) -; BC = number of VDP table entries -; DE = source VDP table index -; HL = destination VDP table index -;*************************************** -_Expand LD IX,__Expand -L1D70 EXX ; Swap register sets - EX AF,AF' ; AF' = VDP table - PUSH IX ; Save routine address -L1D74 EX AF,AF' ; AF = VDP table - PUSH AF - EX AF,AF' - POP AF - EXX ; DE = original DE - PUSH DE - EXX - POP DE - LD HL,(VDP_Temp) ; HL = (VDP_Temp) - CALL L1E92 ; LD IY,0001H / JP _BlkReadVRAM - POP IX ; IX = routine address - PUSH IX - JP (IX) ; Jump into the routine - -__Rotate LD HL,(VDP_Temp) ; HL = temp - LD BC,0008H ; DE = temp + 8 - LD E,L - LD D,H - ADD HL,BC - EX DE,HL - CALL DoRotate ; Rotate the image - CALL L1E72 ; Copy the image back to VRAM - CALL L1E5D ; Check for hi-res graphics - JR Z,L1E02 ; Exit if not hi-res graphics - CALL L1E89 ; Read the source color table entry - CALL L1E9A ; Write the dest color table entry -L1E02 JR L1D8CEXX ; Done with routine - -__FlipRL LD HL,(VDP_Temp) ; DE = temp - LD BC,0008H ; HL = temp + 8 - LD E,L - LD D,H - ADD HL,BC - EX DE,HL - CALL DoFlipLR ; Flip the image - CALL L1E72 ; Copy the image back to VRAM - CALL L1E5D ; Check for hi-res grahpics - JR Z,L1DB3 ; Exit if not hi-res graphics - CALL L1E89 ; Read source color table entry - CALL L1E9A ; Write dest color table entry -L1DB3 EXX ; Swap register set - JR L1D8CHL ; Done with routine - -__FlipUD LD HL,(VDP_Temp) ; DE = temp - LD BC,0008H ; HL = temp + 8 - LD E,L - LD D,H - ADD HL,BC - EX DE,HL - CALL DoFlipUD ; Flip the image - CALL L1E72 ; Copy the image back to VRAM - CALL L1E5D ; Check for hi-res graphics - JR Z,L1D8CEXX ; Exit if not hi-res graphics - CALL L1E89 ; Read source color table entry - LD HL,(VDP_Temp) ; HL = temp - LD BC,0008H ; DE = temp + 8 - LD E,L - LD D,H - ADD HL,BC - EX DE,HL - CALL DoFlipUD ; Flip the color table - CALL L1E9A ; Write dest color table entry -L1D8CEXX EXX ; Swap register set -L1D8CHL INC HL ; Increment dest index -L1D8C INC DE ; Increment VDP table index - DEC BC ; Decrement count - LD A,B ; Check for count = 0 - OR C - EXX ; Swap register set - JR NZ,L1D74 ; Go back until count = 0 - POP IX ; Clean up stack - RET - -__Expand LD HL,(VDP_Temp) ; HL = temp - LD BC,0008H ; DE = temp + 8 - LD E,L - LD D,H - ADD HL,BC - EX DE,HL - CALL DoExpand ; Expand the image - EX AF,AF' ; A = VDP table code - PUSH AF - EX AF,AF' - POP AF - EXX ; DE = dest index - PUSH HL - EXX - POP DE - LD HL,(VDP_Temp) ; HL = temp + 8 - LD BC,0008H - ADD HL,BC - LD IY,0004H ; Write 4 entries - CALL _BlkWrtVRAM ; to the VRAM table - CALL L1E5D ; Check for hi-res graphics - JR Z,L1E55 ; Exit if not hi-res graphics - CALL L1E89 ; Read source color table entry - LD HL,(VDP_Temp) ; HL = temp - LD BC,0008H ; DE = temp + 8 - LD E,L - LD D,H - ADD HL,BC - EX DE,HL - CALL DoExpandCT ; Expand the color table - LD A,04H ; A = VDP color table code - EXX ; DE = dest index - PUSH HL - EXX - POP DE - LD HL,(VDP_Temp) ; HL = temp + 8 - LD BC,0008H - ADD HL,BC - LD IY,0004H ; Write 4 entries back - CALL _BlkWrtVRAM -L1E55 EXX ; Swap register set - INC HL ; Increment dest index - INC HL ; four times - INC HL ; - JR L1D8CHL ; Done with routine - -L1E5D EX AF,AF' ; A = VDP table code - PUSH AF - EX AF,AF' - POP AF - CP 03H ; Pattern generator table? - JP NZ,L10E6 ; Return zero if not - LD HL,VDP0Shad ; Check for hi-res mode - XOR A ; Prepare to return zero - BIT 1,(HL) - RET Z ; Return zero if not - INC A ; Return 1 if in hi-res mode - RET ; (Z-flag set according to A-reg) - -L1E72 EX AF,AF' ; A = VDP table code - PUSH AF - EX AF,AF' - POP AF - EXX ; DE = dest index - PUSH HL - EXX - POP DE - LD HL,(VDP_Temp) ; HL = temp + 8 - LD BC,0008H - ADD HL,BC - JR L1EA7 - -L1E89 EXX ; DE = source index - PUSH DE - EXX - POP DE - LD HL,(VDP_Temp) ; HL = temp -L1E90 LD A,04H ; A = VDP color table code -L1E92 LD IY,0001H ; Read one entry - JP _BlkReadVRAM ; from the color table - -L1E9A EXX ; DE = dest index - PUSH HL - EXX - POP DE - LD HL,(VDP_Temp) ; HL = temp -L1EA5 LD A,04H ; A = VDP color table code -L1EA7 LD IY,0001H ; Write one entry - JP _BlkWrtVRAM ; to the color table - -DoExpand PUSH HL ; IX = source - POP IX - PUSH DE ; IY = dest - POP IY - LD B,08H ; Initialize count -L1EB4 LD A,(IX+00H) ; Get source byte - INC IX - LD D,A ; Copy source byte into D - LD E,04H ; Initialize bit count -L1EBC RL A ; Shift source bit into H - RL H - RL D ; Shift copy of bit into H - RL H - DEC E ; Loop for four bits - JR NZ,L1EBC - LD E,04H ; Initialize bit count -L1EC9 RL A ; Shift source bit into L - RL L - RL D ; Shift copy of bit into L - RL L - DEC E ; Loop for four bits - JR NZ,L1EC9 - LD (IY+00H),H ; Store bits in first row - LD (IY+10H),L - INC IY - LD (IY+00H),H ; Store bits in second row - LD (IY+10H),L - INC IY - DJNZ L1EB4 ; Loop until done - RET - -DoExpandCT LD B,10H ; Initialize count - PUSH HL ; Save source addr -L1EEE LD A,(HL) ; Get next source byte - INC HL - LD (DE),A ; Store it twice - INC DE - LD (DE),A - INC DE - DEC BC ; Decrement count - LD A,B - CP 08H ; If count = 8 - JR NZ,L1EFB - POP HL ; get back source addr -L1EFB DJNZ L1EEE ; Loop until done - RET - -DoFlipLR LD B,08H ; Initialize count -L1F03 LD C,(HL) ; Get next byte - LD A,80H ; Set terminator bit -L1F06 RL C ; Shift a bit out - RRA ; Shift it in - JR NC,L1F06 ; Loop until done - LD (DE),A ; Save byte - INC HL ; Point to next bytes - INC DE - DJNZ L1F03 ; Loop until done - RET - -DoRotate PUSH HL ; IX = source - POP IX - EX DE,HL ; HL = destination - LD B,08H ; Initialize count -L1F19 RL (IX+00H) ; Shift a column of bits from the - RR (HL) ; source into a row of bits in - RL (IX+01H) ; the destination - RR (HL) - RL (IX+02H) - RR (HL) - RL (IX+03H) - RR (HL) - RL (IX+04H) - RR (HL) - RL (IX+05H) - RR (HL) - RL (IX+06H) - RR (HL) - RL (IX+07H) - RR (HL) - INC HL ; Increment destination - DJNZ L1F19 ; Loop until done - RET - -DoFlipUD LD BC,0008H ; Dest = dest + 8 - ADD HL,BC - LD B,C ; Initialize count = 8 -L1F53 DEC HL ; Decrement source - LD A,(HL) ; Get source byte - LD (DE),A ; Store in destination - INC DE ; Increment destination - DJNZ L1F53 ; Loop until done - RET - -;*************************************** -; 1F79 ReadCtl -; -; Read a joystick or keypad controller and a fire button -; -; ENTRY H = 0 for left control, 1 for right -; L = 0 for joystick/left fire, 1 for keypad/right fire -; EXIT: H = fire button in 40H bit -; L = joystick directionals or key code -; E = old pulse counter (only if L=0) -;*************************************** -_ReadCtl LD A,L ; Check if reading keypad - CP 01H - JR Z,L11AA ; Branch if reading keypad - LD BC,PulseCnt1 ; Point BC to pulse counter - LD A,H - OR A - JR Z,L1199 ; branch if left controller - INC BC ; Point BC to PulseCnt2 -L1199 LD A,(BC) ; E = old pulse counter value - LD E,A - XOR A ; Clear pulse counter - LD (BC),A - CALL L113D ; Read joystick port - LD D,A ; Save port bits in D - AND 0FH - LD L,A ; L = directional bits - JR L11BC - -; Read the keypad - -L11AA OUT (IO_KP_Select),A ; Select keypad mode - CALL L113D ; Read joystick port - LD D,A ; Save port bits in D - OUT (IO_Joy_Select),A ; Select joystick mode - AND 0FH ; Mask off keypad bits - LD HL,Keypad_Table ; Index into keypad table - LD B,00H - LD C,A - ADD HL,BC - LD L,(HL) ; L = key code (or 0FH if none) -L11BC LD A,D - AND 40H - LD H,A ; H = right fire button bit - RET - -; Jump vectors. Please call these instead of using addresses -; within the ROM itself. Since the code is so sloppy that -; hundreds of bytes can be squeezed out of it, it's too tempting -; to reassemble an optimized ROM with room to add something cool. - -A1F61 -DoSound JP _DoSound -L1F64 JP L0488 ; video P04A3 -L1F67 JP L06C7 ; video P06D8 -FlipRL JP _FlipRL -FlipUD JP _FlipUD -Rotate JP _Rotate -Expand JP _Expand -ReadCtlRaw JP _ReadCtlRaw -ReadCtl JR _ReadCtl - DB O -SkillScrn JP _SkillScrn -InitFont JP _InitFont -FillVRAM JP _FillVRAM -InitVDP JP _InitVDP -ReadSpinner JP _ReadSpinner -PBaseLoad JP _PBaseLoad -PBlkReadVRAM JP _PBlkReadVRAM -PBlkWrtVRAM JP _PBlkWrtVRAM -PInitRAMSprt JP _PInitRAMSprt -PCopyRAMSprt JP _PCopyRAMSprt -PInitTimers JP _PInitTimers -PStopTimer JP _PStopTimer -PStartTimer JP _PStartTimer -PTestTimer JP _PTestTimer -PWriteReg JP _PWriteReg -PWrtVRAM JP _PWrtVRam -PReadVRAM JP _PReadVRAM -L1FAF JP L0655 ; video P0664 -PInitSound JP _PInitSound -PAddSound JP _PAddSound -BaseLoad JP _BaseLoad -BlkReadVRAM JP _BlkReadVRAM -BlkWrtVRAM JP _BlkWrtVRAM -InitRAMSprt JP _InitRAMSprt -CopyRAMSprt JP _CopyRAMSprt -InitTimers JP _InitTimers -StopTimer JP _StopTimer -StartTimer JP _StartTimer -TestTimer JP _TestTimer -RunTimers JP _RunTimers -NoSound JP _NoSound -WriteReg JP _WriteReg -VDP_Status JP _VDP_Status -WrtVRAM JP _WrtVRAM -ReadVRAM JP _ReadVRAM -L1FE5 JP L0664 ; video -L1FE8 JP L0679 ; video (no P) -ReadCtlState JP _ReadCtlState -InitSound JP _InitSound -AddSound JP _AddSound ; 1FF1-1FF3 -UpdateSound JP _UpdateSound ; 1FF4-1FF6 -L1FF7 JP L04A3 ; video -L1FFA JP L06D8 ; video -Random JP _Random - -D2000 END \ No newline at end of file diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/scandoubler.v b/Console_MiST/Coleco - Vision_MiST/rtl/scandoubler.v deleted file mode 100644 index e85cba43..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/scandoubler.v +++ /dev/null @@ -1,183 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/COPYING b/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/COPYING deleted file mode 100644 index 60549be5..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/COPYING +++ /dev/null @@ -1,340 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. 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If this is what you want to do, use the GNU Library General -Public License instead of this License. diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/README b/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/README deleted file mode 100644 index 33630144..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/README +++ /dev/null @@ -1,143 +0,0 @@ - -An SN76489AN Compatible Implementation in VHDL -============================================== -Version: $Date: 2006/06/18 19:28:40 $ - -Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) -See the file COPYING. - - -Integration ------------ - -The sn76489 design exhibits all interface signals as the original chip. It -only differs in the audio data output which is provided as an 8 bit signed -vector instead of an analog output pin. - - generic ( - clock_div_16_g : integer := 1 - -- Set to '1' when operating the design in SN76489 mode. The primary clock - -- input is divided by 16 in this variant. The data sheet mentions the - -- SN76494 which contains a divide-by-2 clock input stage. Set the generic - -- to '0' to enable this mode. - ); - port ( - clock_i : in std_logic; - -- Primary clock input - -- Drive with the target frequency or any integer multiple of it. - - clock_en_i : in std_logic; - -- Clock enable - -- A '1' on this input qualifies a valid rising edge on clock_i. A '0' - -- disables the next rising clock edge, effectivley halting the design - -- until the next enabled rising clock edge. - -- Can be used to run the core at lower frequencies than applied on - -- clock_i. - - res_n_i : in std_logic; - -- Asynchronous low active reset input. - -- Sets all sequential elements to a known state. - - ce_n_i : in std_logic; - -- Chip enable, low active. - - we_n_i : in std_logic; - -- Write enable, low active. - - ready_o : out std_logic; - -- Ready indication to microprocessor. - - d_i : in std_logic_vector(0 to 7); - -- Data input - -- MSB 0 ... 7 LSB - - aout_o : out signed(0 to 7) - -- Audio output, signed vector - -- MSB/SIGN 0 ... 7 LSB - ); - - -Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the -MSB and bit 7 to be the LSB. This has been implemented according to TI's data -sheet, thus all register/data format figures apply 1:1 for this design. -Many systems will flip the system data bus bit wise before it is connected to -this PSG. This is simply achieved with the following VHDL construct: - - signal data_s : std_logic_vector(7 downto 0); - - ... - d_i => data_s, - ... - -d_i and data_s will be assigned from left to right, resulting in the expected -bit assignment: - - d_i data_s - 0 7 - 1 6 - ... - 6 1 - 7 0 - - -As this design is fully synchronous, care has to be taken when the design -replaces an SN76489 in asynchronous mode. No problems are expected when -interfacing the code to other synchronous components. - - -Design Hierarchy ----------------- - - sn76489_top - | - +-- sn76489_latch_ctrl - | - +-- sn76489_clock_div - | - +-- sn76489_tone - | | - | \-- sn76489_attentuator - | - +-- sn76489_tone - | | - | \-- sn76489_attentuator - | - +-- sn76489_tone - | | - | \-- sn76489_attentuator - | - \-- sn76489_noise - | - \-- sn76489_attentuator - -Resulting compilation sequence: - - sn76489_comp_pack-p.vhd - sn76489_top.vhd - sn76489_latch_ctrl.vhd - sn76489_latch_ctrl-c.vhd - sn76489_clock_div.vhd - sn76489_clock_div-c.vhd - sn76489_attenuator.vhd - sn76489_attenuator-c.vhd - sn76489_tone.vhd - sn76489_tone-c.vhd - sn76489_noise.vhd - sn76489_noise-c.vhd - sn76489_top-c.vhd - -Skip the files containing VHDL configurations when analyzing the code for -synthesis. - - -References ----------- - -* TI Data sheet SN76489.pdf - ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf - -* John Kortink's article on the SN76489: - http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ - -* Maxim's "SN76489 notes" in - http://www.smspower.org/maxim/docs/SN76489.txt diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_attenuator.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_attenuator.vhd deleted file mode 100644 index 444064e5..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_attenuator.vhd +++ /dev/null @@ -1,114 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's SN76489AN. --- --- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $ --- --- Attenuator Module --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity sn76489_attenuator is - - port ( - attenuation_i : in std_logic_vector(0 to 3); - factor_i : in signed(0 to 1); - product_o : out signed(0 to 7) - ); - -end sn76489_attenuator; - - -architecture rtl of sn76489_attenuator is - -begin - - ----------------------------------------------------------------------------- - -- Process attenuate - -- - -- Purpose: - -- Determine the attenuation and generate the resulting product. - -- - -- The maximum attenuation value is 31 which corresponds to volume off. - -- As described in the data sheet, the maximum "playing" attenuation is - -- 28 = 16 + 8 + 4 - -- - -- The table for the volume constants is derived from the following - -- formula (each step is 2dB voltage): - -- v(0) = 31 - -- v(n+1) = v(n) * 0.79432823 - -- - attenuate: process (attenuation_i, - factor_i) - - type volume_t is array (natural range 0 to 15) of natural; - constant volume_c : volume_t := - (31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0); - - variable attenuation_v : unsigned(attenuation_i'range); - variable volume_v : signed(product_o'range); - - begin - - attenuation_v := unsigned(attenuation_i); - - -- volume look-up table - volume_v := to_signed(volume_c(to_integer(attenuation_v)), - product_o'length); - - -- this replaces a multiplier and consumes a bit fewer - -- resources - case to_integer(factor_i) is - when +1 => - product_o <= volume_v; - when -1 => - product_o <= -volume_v; - when others => - product_o <= (others => '0'); - end case; - - end process attenuate; - -- - ----------------------------------------------------------------------------- - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_clock_div.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_clock_div.vhd deleted file mode 100644 index eab86beb..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_clock_div.vhd +++ /dev/null @@ -1,134 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's SN76489AN. --- --- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $ --- --- Clock Divider Circuit --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity sn76489_clock_div is - - generic ( - clock_div_16_g : integer := 1 - ); - port ( - clock_i : in std_logic; - clock_en_i : in std_logic; - res_n_i : in std_logic; - clk_en_o : out boolean - ); - -end sn76489_clock_div; - - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of sn76489_clock_div is - - signal cnt_s, - cnt_q : unsigned(3 downto 0); - -begin - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the sequential counter element. - -- - seq: process (clock_i, res_n_i) - begin - if res_n_i = '0' then - cnt_q <= (others => '0'); - elsif clock_i'event and clock_i = '1' then - cnt_q <= cnt_s; - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process comb - -- - -- Purpose: - -- Implements the combinational counter logic. - -- - comb: process (clock_en_i, - cnt_q) - begin - -- default assignments - cnt_s <= cnt_q; - clk_en_o <= false; - - if clock_en_i = '1' then - - if cnt_q = 0 then - clk_en_o <= true; - - if clock_div_16_g = 1 then - cnt_s <= to_unsigned(15, cnt_q'length); - elsif clock_div_16_g = 0 then - cnt_s <= to_unsigned( 1, cnt_q'length); - else - -- pragma translate_off - assert false - report "Generic clock_div_16_g must be either 0 or 1." - severity failure; - -- pragma translate_on - end if; - - else - cnt_s <= cnt_q - 1; - - end if; - - end if; - - end process comb; - -- - ----------------------------------------------------------------------------- - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_comp_pack.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_comp_pack.vhd deleted file mode 100644 index 06b12c83..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_comp_pack.vhd +++ /dev/null @@ -1,96 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id: sn76489_comp_pack-p.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ --- --- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package sn76489_comp_pack is - - component sn76489_attenuator - port ( - attenuation_i : in std_logic_vector(0 to 3); - factor_i : in signed(0 to 1); - product_o : out signed(0 to 7) - ); - end component; - - component sn76489_tone - port ( - clock_i : in std_logic; - clk_en_i : in boolean; - res_n_i : in std_logic; - we_i : in boolean; - d_i : in std_logic_vector(0 to 7); - r2_i : in std_logic; - ff_o : out std_logic; - tone_o : out signed(0 to 7) - ); - end component; - - component sn76489_noise - port ( - clock_i : in std_logic; - clk_en_i : in boolean; - res_n_i : in std_logic; - we_i : in boolean; - d_i : in std_logic_vector(0 to 7); - r2_i : in std_logic; - tone3_ff_i : in std_logic; - noise_o : out signed(0 to 7) - ); - end component; - - component sn76489_latch_ctrl - port ( - clock_i : in std_logic; - clk_en_i : in boolean; - res_n_i : in std_logic; - ce_n_i : in std_logic; - we_n_i : in std_logic; - d_i : in std_logic_vector(0 to 7); - ready_o : out std_logic; - tone1_we_o : out boolean; - tone2_we_o : out boolean; - tone3_we_o : out boolean; - noise_we_o : out boolean; - r2_o : out std_logic - ); - end component; - - component sn76489_clock_div - generic ( - clock_div_16_g : integer := 1 - ); - port ( - clock_i : in std_logic; - clock_en_i : in std_logic; - res_n_i : in std_logic; - clk_en_o : out boolean - ); - end component; - - component sn76489_top - generic ( - clock_div_16_g : integer := 1 - ); - port ( - clock_i : in std_logic; - clock_en_i : in std_logic; - res_n_i : in std_logic; - ce_n_i : in std_logic; - we_n_i : in std_logic; - ready_o : out std_logic; - d_i : in std_logic_vector(0 to 7); - aout_o : out signed(0 to 7) - ); - end component; - -end sn76489_comp_pack; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd deleted file mode 100644 index 789720c2..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_latch_ctrl.vhd +++ /dev/null @@ -1,138 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's SN76489AN. --- --- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ --- --- Latch Control Unit --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity sn76489_latch_ctrl is - - port ( - clock_i : in std_logic; - clk_en_i : in boolean; - res_n_i : in std_logic; - ce_n_i : in std_logic; - we_n_i : in std_logic; - d_i : in std_logic_vector(0 to 7); - ready_o : out std_logic; - tone1_we_o : out boolean; - tone2_we_o : out boolean; - tone3_we_o : out boolean; - noise_we_o : out boolean; - r2_o : out std_logic - ); - -end sn76489_latch_ctrl; - - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of sn76489_latch_ctrl is - - signal reg_q : std_logic_vector(0 to 2); - signal we_q : boolean; - signal ready_q : std_logic; - -begin - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the sequential elements. - -- - seq: process (clock_i, res_n_i) - begin - if res_n_i = '0' then - reg_q <= (others => '0'); - we_q <= false; - ready_q <= '0'; - - elsif clock_i'event and clock_i = '1' then - -- READY Flag Output ---------------------------------------------------- - if ready_q = '0' and we_q then - if clk_en_i then - -- assert READY when write access happened - ready_q <= '1'; - end if; - elsif ce_n_i = '1' then - -- deassert READY when access has finished - ready_q <= '0'; - end if; - - -- Register Selection --------------------------------------------------- - if ce_n_i = '0' and we_n_i = '0' then - if clk_en_i then - if d_i(0) = '1' then - reg_q <= d_i(1 to 3); - end if; - we_q <= true; - end if; - else - we_q <= false; - end if; - - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output mapping - ----------------------------------------------------------------------------- - tone1_we_o <= reg_q(0 to 1) = "00" and we_q; - tone2_we_o <= reg_q(0 to 1) = "01" and we_q; - tone3_we_o <= reg_q(0 to 1) = "10" and we_q; - noise_we_o <= reg_q(0 to 1) = "11" and we_q; - - r2_o <= reg_q(2); - - ready_o <= ready_q - when ce_n_i = '0' else - '1'; - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_noise.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_noise.vhd deleted file mode 100644 index 647d3cdc..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_noise.vhd +++ /dev/null @@ -1,281 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's SN76489AN. --- --- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $ --- --- Noise Generator --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity sn76489_noise is - - port ( - clock_i : in std_logic; - clk_en_i : in boolean; - res_n_i : in std_logic; - we_i : in boolean; - d_i : in std_logic_vector(0 to 7); - r2_i : in std_logic; - tone3_ff_i : in std_logic; - noise_o : out signed(0 to 7) - ); - -end sn76489_noise; - - ---use work.sn76489_comp_pack.sn76489_attenuator; - -architecture rtl of sn76489_noise is - - signal nf_q : std_logic_vector(0 to 1); - signal fb_q : std_logic; - signal a_q : std_logic_vector(0 to 3); - signal freq_cnt_q : unsigned(0 to 6); - signal freq_ff_q : std_logic; - - signal shift_source_s, - shift_source_q : std_logic; - signal shift_rise_edge_s : boolean; - - signal lfsr_q : std_logic_vector(0 to 15); - - signal freq_s : signed(0 to 1); - -begin - - ----------------------------------------------------------------------------- - -- Process cpu_regs - -- - -- Purpose: - -- Implements the registers writable by the CPU. - -- - cpu_regs: process (clock_i, res_n_i) - begin - if res_n_i = '0' then - nf_q <= (others => '0'); - fb_q <= '0'; - a_q <= (others => '1'); - - elsif clock_i'event and clock_i = '1' then - if clk_en_i and we_i then - if r2_i = '0' then - -- access to control register - -- both access types can write to the control register! - nf_q <= d_i(6 to 7); - fb_q <= d_i(5); - - else - -- access to attenuator register - -- both access types can write to the attenuator register! - a_q <= d_i(4 to 7); - - end if; - end if; - end if; - end process cpu_regs; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process freq_gen - -- - -- Purpose: - -- Implements the frequency generation components. - -- - freq_gen: process (clock_i, res_n_i) - begin - if res_n_i = '0' then - freq_cnt_q <= (others => '0'); - freq_ff_q <= '0'; - - elsif clock_i'event and clock_i = '1' then - if clk_en_i then - if freq_cnt_q = 0 then - -- reload frequency counter according to NF setting - case nf_q is - when "00" => - freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length); - when "01" => - freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length); - when "10" => - freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length); - when others => - null; - end case; - - freq_ff_q <= not freq_ff_q; - - else - -- decrement frequency counter - freq_cnt_q <= freq_cnt_q - 1; - - end if; - - end if; - end if; - end process freq_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Multiplex the source of the LFSR's shift enable - ----------------------------------------------------------------------------- - shift_source_s <= tone3_ff_i - when nf_q = "11" else - freq_ff_q; - - ----------------------------------------------------------------------------- - -- Process rise_edge - -- - -- Purpose: - -- Detect the rising edge of the selected LFSR shift source. - -- - rise_edge: process (clock_i, res_n_i) - begin - if res_n_i = '0' then - shift_source_q <= '0'; - - elsif clock_i'event and clock_i = '1' then - if clk_en_i then - shift_source_q <= shift_source_s; - end if; - end if; - end process rise_edge; - -- - ----------------------------------------------------------------------------- - - -- detect rising edge on shift source - shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1'; - - - ----------------------------------------------------------------------------- - -- Process lfsr - -- - -- Purpose: - -- Implements the LFSR that generates noise. - -- Note: This implementation shifts the register right, i.e. from index - -- 15 towards 0 => bit 15 is the input, bit 0 is the output - -- - -- Tapped bits according to MAME's sn76496.c, implemented in function - -- lfsr_tapped_f. - -- - lfsr: process (clock_i, res_n_i) - - function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is - constant tapped_bits_c : std_logic_vector(0 to 15) - -- tapped bits are 0, 2, 15 - := "1010000000000001"; - variable parity_v : std_logic; - begin - parity_v := '0'; - - for idx in lfsr'low to lfsr'high loop - parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx)); - end loop; - - return parity_v; - end; - - begin - if res_n_i = '0' then - -- reset LFSR to "0000000000000001" - lfsr_q <= (others => '0'); - lfsr_q(lfsr_q'right) <= '1'; - - elsif clock_i'event and clock_i = '1' then - if clk_en_i then - if we_i and r2_i = '0' then - -- write to noise register - -- -> reset LFSR - lfsr_q <= (others => '0'); - lfsr_q(lfsr_q'right) <= '1'; - - elsif shift_rise_edge_s then - - -- shift LFSR left towards MSB - for idx in lfsr_q'right-1 downto lfsr_q'left loop - lfsr_q(idx) <= lfsr_q(idx+1); - end loop; - - -- determine input bit - if fb_q = '0' then - -- "Periodic" Noise - -- -> input to LFSR is output - lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left); - else - -- "White" Noise - -- -> input to LFSR is parity of tapped bits - lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q); - end if; - - end if; - - end if; - end if; - end process lfsr; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Map output of LFSR to signed value for attenuator. - ----------------------------------------------------------------------------- - freq_s <= to_signed(+1, 2) - when lfsr_q(0) = '1' else - to_signed( 0, 2); - - - ----------------------------------------------------------------------------- - -- The attenuator itself - ----------------------------------------------------------------------------- - attenuator_b : entity work.sn76489_attenuator - port map ( - attenuation_i => a_q, - factor_i => freq_s, - product_o => noise_o - ); - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_tone.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_tone.vhd deleted file mode 100644 index 4d39a5a4..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_tone.vhd +++ /dev/null @@ -1,189 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's SN76489AN. --- --- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $ --- --- Tone Generator --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; ---use work.sn76489_comp_pack.all; - -entity sn76489_tone is - - port ( - clock_i : in std_logic; - clk_en_i : in boolean; - res_n_i : in std_logic; - we_i : in boolean; - d_i : in std_logic_vector(0 to 7); - r2_i : in std_logic; - ff_o : out std_logic; - tone_o : out signed(0 to 7) - ); - -end sn76489_tone; - -architecture rtl of sn76489_tone is - - signal f_q : std_logic_vector(0 to 9); - signal a_q : std_logic_vector(0 to 3); - signal freq_cnt_q : unsigned(0 to 9); - signal freq_ff_q : std_logic; - - signal freq_s : signed(0 to 1); - - function all_zero(a : in std_logic_vector) return boolean is - variable result_v : boolean; - begin - result_v := true; - - for idx in a'low to a'high loop - if a(idx) /= '0' then - result_v := false; - end if; - end loop; - - return result_v; - end; - -begin - - ----------------------------------------------------------------------------- - -- Process cpu_regs - -- - -- Purpose: - -- Implements the registers writable by the CPU. - -- - cpu_regs: process (clock_i, res_n_i) - begin - if res_n_i = '0' then - f_q <= (others => '0'); - a_q <= (others => '1'); - - elsif clock_i'event and clock_i = '1' then - if clk_en_i and we_i then - if r2_i = '0' then - -- access to frequency register - if d_i(0) = '0' then - f_q(0 to 5) <= d_i(2 to 7); - else - f_q(6 to 9) <= d_i(4 to 7); - end if; - - else - -- access to attenuator register - -- both access types can write to the attenuator register! - a_q <= d_i(4 to 7); - - end if; - end if; - end if; - end process cpu_regs; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process freq_gen - -- - -- Purpose: - -- Implements the frequency generation components. - -- - freq_gen: process (clock_i, res_n_i) - begin - if res_n_i = '0' then - freq_cnt_q <= (others => '0'); - freq_ff_q <= '0'; - - elsif clock_i'event and clock_i = '1' then - if clk_en_i then - if freq_cnt_q = 0 then - -- update counter from frequency register - freq_cnt_q <= unsigned(f_q); - - -- and toggle the frequency flip-flop if enabled - if not all_zero(f_q) then - freq_ff_q <= not freq_ff_q; - else - -- if frequency setting is 0, then keep flip-flop at +1 - freq_ff_q <= '1'; - end if; - - else - -- decrement frequency counter - freq_cnt_q <= freq_cnt_q - 1; - - end if; - end if; - end if; - end process freq_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Map frequency flip-flop to signed value for attenuator. - ----------------------------------------------------------------------------- - freq_s <= to_signed(+1, 2) - when freq_ff_q = '1' else - to_signed(-1, 2); - - - ----------------------------------------------------------------------------- - -- The attenuator itself - ----------------------------------------------------------------------------- - attenuator_b : entity work.sn76489_attenuator - port map ( - attenuation_i => a_q, - factor_i => freq_s, - product_o => tone_o - ); - - - ----------------------------------------------------------------------------- - -- Output mapping - ----------------------------------------------------------------------------- - ff_o <= freq_ff_q; - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_top.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_top.vhd deleted file mode 100644 index 04b8ca41..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/sn76489/sn76489_top.vhd +++ /dev/null @@ -1,197 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's SN76489AN. --- --- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $ --- --- Chip Toplevel --- --- References: --- --- * TI Data sheet SN76489.pdf --- ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf --- --- * John Kortink's article on the SN76489: --- http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/ --- --- * Maxim's "SN76489 notes" in --- http://www.smspower.org/maxim/docs/SN76489.txt --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity sn76489_top is - - generic ( - clock_div_16_g : integer := 1 - ); - port ( - clock_i : in std_logic; -- Normally 3.58 MHz - clock_en_i : in std_logic; -- For high clocks - res_n_i : in std_logic; - ce_n_i : in std_logic; - we_n_i : in std_logic; - ready_o : out std_logic; - d_i : in std_logic_vector(0 to 7); - aout_o : out signed(0 to 7) - ); - -end entity; - -architecture struct of sn76489_top is - - signal clk_en_s : boolean; - - signal tone1_we_s, - tone2_we_s, - tone3_we_s, - noise_we_s : boolean; - signal r2_s : std_logic; - - signal tone1_s, - tone2_s, - tone3_s, - noise_s : signed(0 to 7); - - signal tone3_ff_s : std_logic; - -begin - - ----------------------------------------------------------------------------- - -- Clock Divider - ----------------------------------------------------------------------------- - clock_div_b : entity work.sn76489_clock_div - generic map ( - clock_div_16_g => clock_div_16_g - ) - port map ( - clock_i => clock_i, - clock_en_i => clock_en_i, - res_n_i => res_n_i, - clk_en_o => clk_en_s - ); - - - ----------------------------------------------------------------------------- - -- Latch Control = CPU Interface - ----------------------------------------------------------------------------- - latch_ctrl_b : entity work.sn76489_latch_ctrl - port map ( - clock_i => clock_i, - clk_en_i => clk_en_s, - res_n_i => res_n_i, - ce_n_i => ce_n_i, - we_n_i => we_n_i, - d_i => d_i, - ready_o => ready_o, - tone1_we_o => tone1_we_s, - tone2_we_o => tone2_we_s, - tone3_we_o => tone3_we_s, - noise_we_o => noise_we_s, - r2_o => r2_s - ); - - - ----------------------------------------------------------------------------- - -- Tone Channel 1 - ----------------------------------------------------------------------------- - tone1_b : entity work.sn76489_tone - port map ( - clock_i => clock_i, - clk_en_i => clk_en_s, - res_n_i => res_n_i, - we_i => tone1_we_s, - d_i => d_i, - r2_i => r2_s, - ff_o => open, - tone_o => tone1_s - ); - - ----------------------------------------------------------------------------- - -- Tone Channel 2 - ----------------------------------------------------------------------------- - tone2_b : entity work.sn76489_tone - port map ( - clock_i => clock_i, - clk_en_i => clk_en_s, - res_n_i => res_n_i, - we_i => tone2_we_s, - d_i => d_i, - r2_i => r2_s, - ff_o => open, - tone_o => tone2_s - ); - - ----------------------------------------------------------------------------- - -- Tone Channel 3 - ----------------------------------------------------------------------------- - tone3_b : entity work.sn76489_tone - port map ( - clock_i => clock_i, - clk_en_i => clk_en_s, - res_n_i => res_n_i, - we_i => tone3_we_s, - d_i => d_i, - r2_i => r2_s, - ff_o => tone3_ff_s, - tone_o => tone3_s - ); - - ----------------------------------------------------------------------------- - -- Noise Channel - ----------------------------------------------------------------------------- - noise_b : entity work.sn76489_noise - port map ( - clock_i => clock_i, - clk_en_i => clk_en_s, - res_n_i => res_n_i, - we_i => noise_we_s, - d_i => d_i, - r2_i => r2_s, - tone3_ff_i => tone3_ff_s, - noise_o => noise_s - ); - - - aout_o <= tone1_s + tone2_s + tone3_s + noise_s; - -end architecture; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_addr_mux.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_addr_mux.vhd deleted file mode 100644 index 9ff8c8f8..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_addr_mux.vhd +++ /dev/null @@ -1,228 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A. --- --- $Id: vdp18_addr_mux.vhd,v 1.10 2006/06/18 10:47:01 arnim Exp $ --- --- Address Multiplexer / Generator --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.vdp18_pack.access_t; -use work.vdp18_pack.opmode_t; -use work.vdp18_pack.hv_t; - -entity vdp18_addr_mux is - - port ( - access_type_i : in access_t; - opmode_i : in opmode_t; - num_line_i : in hv_t; - reg_ntb_i : in std_logic_vector(0 to 3); - reg_ctb_i : in std_logic_vector(0 to 7); - reg_pgb_i : in std_logic_vector(0 to 2); - reg_satb_i : in std_logic_vector(0 to 6); - reg_spgb_i : in std_logic_vector(0 to 2); - reg_size1_i : in boolean; - cpu_vram_a_i : in std_logic_vector(0 to 13); - pat_table_i : in std_logic_vector(0 to 9); - pat_name_i : in std_logic_vector(0 to 7); - spr_num_i : in std_logic_vector(0 to 4); - spr_line_i : in std_logic_vector(0 to 3); - spr_name_i : in std_logic_vector(0 to 7); - vram_a_o : out std_logic_vector(0 to 13) - ); - -end vdp18_addr_mux; - - -use work.vdp18_pack.all; - -architecture rtl of vdp18_addr_mux is - -begin - - ----------------------------------------------------------------------------- - -- Process mux - -- - -- Purpose: - -- Generates the VRAM address based on the current access type. - -- - mux: process (access_type_i, opmode_i, - num_line_i, - reg_ntb_i, reg_ctb_i, reg_pgb_i, - reg_satb_i, reg_spgb_i, - reg_size1_i, - cpu_vram_a_i, - pat_table_i, pat_name_i, - spr_num_i, spr_name_i, - spr_line_i) - variable num_line_v : std_logic_vector(num_line_i'range); - begin - -- default assignment - vram_a_o <= (others => '0'); - num_line_v := std_logic_vector(num_line_i); - - case access_type_i is - -- CPU Access ----------------------------------------------------------- - when AC_CPU => - vram_a_o <= cpu_vram_a_i; - - -- Pattern Name Table Access -------------------------------------------- - when AC_PNT => - vram_a_o(0 to 3) <= reg_ntb_i; - vram_a_o(4 to 13) <= pat_table_i; - - -- Pattern Color Table Access ------------------------------------------- - when AC_PCT => - case opmode_i is - when OPMODE_GRAPH1 => - vram_a_o( 0 to 7) <= reg_ctb_i; - vram_a_o( 8) <= '0'; - vram_a_o( 9 to 13) <= pat_name_i(0 to 4); - - when OPMODE_GRAPH2 => - vram_a_o( 0) <= reg_ctb_i(0); - vram_a_o( 1 to 2) <= num_line_v(1 to 2) and - -- remaining bits in CTB mask color - -- lookups - (reg_ctb_i(1) & reg_ctb_i(2)); - vram_a_o( 3 to 10) <= pat_name_i and - -- remaining bits in CTB mask color - -- lookups - (reg_ctb_i(3) & reg_ctb_i(4) & - reg_ctb_i(5) & reg_ctb_i(6) & - reg_ctb_i(7) & "111"); - vram_a_o(11 to 13) <= num_line_v(6 to 8); - - when others => - null; - end case; - - -- Pattern Generator Table Access --------------------------------------- - when AC_PGT => - case opmode_i is - when OPMODE_TEXTM | - OPMODE_GRAPH1 => - vram_a_o( 0 to 2) <= reg_pgb_i; - vram_a_o( 3 to 10) <= pat_name_i; - vram_a_o(11 to 13) <= num_line_v(6 to 8); - - when OPMODE_MULTIC => - vram_a_o( 0 to 2) <= reg_pgb_i; - vram_a_o( 3 to 10) <= pat_name_i; - vram_a_o(11 to 13) <= num_line_v(4 to 6); - - when OPMODE_GRAPH2 => - vram_a_o( 0) <= reg_pgb_i(0); - vram_a_o( 1 to 2) <= num_line_v(1 to 2) and - -- remaining bits in PGB mask pattern - -- lookups - (reg_pgb_i(1) & reg_pgb_i(2)); - vram_a_o( 3 to 10) <= pat_name_i and - -- remaining bits in CTB mask pattern - -- lookups - (reg_ctb_i(3) & reg_ctb_i(4) & - reg_ctb_i(5) & reg_ctb_i(6) & - reg_ctb_i(7) & "111"); - vram_a_o(11 to 13) <= num_line_v(6 to 8); - - when others => - null; - end case; - - -- Sprite Test ---------------------------------------------------------- - when AC_STST | - AC_SATY => - vram_a_o( 0 to 6) <= reg_satb_i; - vram_a_o( 7 to 11) <= spr_num_i; - vram_a_o(12 to 13) <= "00"; - - -- Sprite Attribute Table: X -------------------------------------------- - when AC_SATX => - vram_a_o( 0 to 6) <= reg_satb_i; - vram_a_o( 7 to 11) <= spr_num_i; - vram_a_o(12 to 13) <= "01"; - - -- Sprite Attribute Table: Name ----------------------------------------- - when AC_SATN => - vram_a_o( 0 to 6) <= reg_satb_i; - vram_a_o( 7 to 11) <= spr_num_i; - vram_a_o(12 to 13) <= "10"; - - -- Sprite Attribute Table: Color ---------------------------------------- - when AC_SATC => - vram_a_o( 0 to 6) <= reg_satb_i; - vram_a_o( 7 to 11) <= spr_num_i; - vram_a_o(12 to 13) <= "11"; - - -- Sprite Pattern, Upper Part ------------------------------------------- - when AC_SPTH => - vram_a_o( 0 to 2) <= reg_spgb_i; - if not reg_size1_i then - -- 8x8 sprite - vram_a_o( 3 to 10) <= spr_name_i; - vram_a_o(11 to 13) <= spr_line_i(1 to 3); - else - -- 16x16 sprite - vram_a_o( 3 to 8) <= spr_name_i(0 to 5); - vram_a_o( 9) <= '0'; - vram_a_o(10 to 13) <= spr_line_i; - end if; - - -- Sprite Pattern, Lower Part ------------------------------------------- - when AC_SPTL => - vram_a_o( 0 to 2) <= reg_spgb_i; - vram_a_o( 3 to 8) <= spr_name_i(0 to 5); - vram_a_o( 9) <= '1'; - vram_a_o(10 to 13) <= spr_line_i; - - when others => - null; - - end case; - - end process mux; - -- - ----------------------------------------------------------------------------- - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_clk_gen.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_clk_gen.vhd deleted file mode 100644 index 6c208907..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_clk_gen.vhd +++ /dev/null @@ -1,154 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A. --- --- $Id: vdp18_clk_gen.vhd,v 1.8 2006/06/18 10:47:01 arnim Exp $ --- --- Clock Generator --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity vdp18_clk_gen is - - port ( - clock_i : in std_logic; - clk_en_10m7_i : in std_logic; - reset_i : in boolean; - clk_en_5m37_o : out boolean; - clk_en_3m58_o : out boolean; - clk_en_2m68_o : out boolean - ); - -end vdp18_clk_gen; - - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of vdp18_clk_gen is - - signal cnt_q : unsigned(3 downto 0); - -begin - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the sequential elements. - -- * clock counter - -- - seq: process (clock_i, reset_i) - variable cnt_v : integer range -256 to 255; - begin - if reset_i then - cnt_q <= (others => '0'); - - elsif clock_i'event and clock_i = '1' then - if clk_en_10m7_i = '1' then - if cnt_q = 11 then - -- wrap after counting 12 clocks - cnt_q <= (others => '0'); - else - cnt_q <= cnt_q + 1; - end if; - end if; - - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process clk_en - -- - -- Purpose: - -- Generates the derived clock enable signals. - -- - clk_en: process (clk_en_10m7_i, - cnt_q) - variable cnt_v : integer range -256 to 255; - begin - cnt_v := to_integer(cnt_q); - - -- 5.37 MHz clock enable -------------------------------------------------- - if clk_en_10m7_i = '1' then - case cnt_v is - when 1 | 3 | 5 | 7 | 9 | 11 => - clk_en_5m37_o <= true; - when others => - clk_en_5m37_o <= false; - end case; - else - clk_en_5m37_o <= false; - end if; - - -- 3.58 MHz clock enable -------------------------------------------------- - if clk_en_10m7_i = '1' then - case cnt_v is - when 2 | 5 | 8 | 11 => - clk_en_3m58_o <= true; - when others => - clk_en_3m58_o <= false; - end case; - else - clk_en_3m58_o <= false; - end if; - - -- 2.68 MHz clock enable -------------------------------------------------- - if clk_en_10m7_i = '1' then - case cnt_v is - when 3 | 7 | 11 => - clk_en_2m68_o <= true; - when others => - clk_en_2m68_o <= false; - end case; - else - clk_en_2m68_o <= false; - end if; - - end process clk_en; - -- - ----------------------------------------------------------------------------- - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_col_mux.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_col_mux.vhd deleted file mode 100644 index e8c40327..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_col_mux.vhd +++ /dev/null @@ -1,184 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A. --- --- $Id: vdp18_col_mux.vhd,v 1.10 2006/06/18 10:47:01 arnim Exp $ --- --- Color Information Multiplexer --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity vdp18_col_mux is - - generic ( - compat_rgb_g : integer := 0 - ); - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - reset_i : in boolean; - vert_active_i : in boolean; - hor_active_i : in boolean; - blank_i : in boolean; - reg_col0_i : in std_logic_vector(0 to 3); - pat_col_i : in std_logic_vector(0 to 3); - spr0_col_i : in std_logic_vector(0 to 3); - spr1_col_i : in std_logic_vector(0 to 3); - spr2_col_i : in std_logic_vector(0 to 3); - spr3_col_i : in std_logic_vector(0 to 3); - col_o : out std_logic_vector(0 to 3); - rgb_r_o : out std_logic_vector(0 to 7); - rgb_g_o : out std_logic_vector(0 to 7); - rgb_b_o : out std_logic_vector(0 to 7) - ); - -end vdp18_col_mux; - - -library ieee; -use ieee.numeric_std.all; - -use work.vdp18_col_pack.all; - -architecture rtl of vdp18_col_mux is - - signal col_s : std_logic_vector(0 to 3); - -begin - - ----------------------------------------------------------------------------- - -- Process col_mux - -- - -- Purpose: - -- Multiplexes the color information from different sources. - -- - col_mux: process (blank_i, - hor_active_i, vert_active_i, - spr0_col_i, spr1_col_i, - spr2_col_i, spr3_col_i, - pat_col_i, - reg_col0_i) - begin - if not blank_i then - if hor_active_i and vert_active_i then - -- priority decoder - if spr0_col_i /= "0000" then - col_s <= spr0_col_i; - elsif spr1_col_i /= "0000" then - col_s <= spr1_col_i; - elsif spr2_col_i /= "0000" then - col_s <= spr2_col_i; - elsif spr3_col_i /= "0000" then - col_s <= spr3_col_i; - elsif pat_col_i /= "0000" then - col_s <= pat_col_i; - else - col_s <= reg_col0_i; - end if; - - else - -- display border - col_s <= reg_col0_i; - end if; - - else - -- blank color channels during horizontal and vertical - -- trace back - -- required to initialize colors for each new scan line - col_s <= (others => '0'); - end if; - end process col_mux; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process rgb_reg - -- - -- Purpose: - -- Converts the color information to simple RGB and saves these in - -- output registers. - -- - rgb_reg: process (clock_i, reset_i) - variable col_v : natural range 0 to 15; - variable rgb_r_v, - rgb_g_v, - rgb_b_v : rgb_val_t; - variable rgb_table_v : rgb_table_t; - begin - if reset_i then - rgb_r_o <= (others => '0'); - rgb_g_o <= (others => '0'); - rgb_b_o <= (others => '0'); - - elsif clock_i'event and clock_i = '1' then - if clk_en_5m37_i then - -- select requested RGB table - if compat_rgb_g = 1 then - rgb_table_v := compat_rgb_table_c; - else - rgb_table_v := full_rgb_table_c; - end if; - - -- assign color to RGB channels - col_v := to_integer(unsigned(col_s)); - rgb_r_v := rgb_table_v(col_v)(r_c); - rgb_g_v := rgb_table_v(col_v)(g_c); - rgb_b_v := rgb_table_v(col_v)(b_c); - -- - rgb_r_o <= std_logic_vector(to_unsigned(rgb_r_v, 8)); - rgb_g_o <= std_logic_vector(to_unsigned(rgb_g_v, 8)); - rgb_b_o <= std_logic_vector(to_unsigned(rgb_b_v, 8)); - end if; - - end if; - end process rgb_reg; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output mapping - ----------------------------------------------------------------------------- - col_o <= col_s; - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_col_pack-p.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_col_pack-p.vhd deleted file mode 100644 index 1d179def..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_col_pack-p.vhd +++ /dev/null @@ -1,83 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id: vdp18_col_pack-p.vhd,v 1.3 2006/02/28 22:30:41 arnim Exp $ --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package vdp18_col_pack is - - constant r_c : natural := 0; - constant g_c : natural := 1; - constant b_c : natural := 2; - - subtype rgb_val_t is natural range 0 to 255; - type rgb_triple_t is array (natural range 0 to 2) of - rgb_val_t; - type rgb_table_t is array (natural range 0 to 15) of - rgb_triple_t; - - ----------------------------------------------------------------------------- - -- Simple RGB Value Array - -- - -- Refer to http://junior.apk.net/~drushel/pub/coleco/twwmca/wk970202.html - -- This is the MF & MdK variant. Note: only the upper three bits are used. - -- - -- - constant compat_rgb_table_c : rgb_table_t := ( - -- R G B - ( 0, 0, 0), -- Transparent - ( 0, 0, 0), -- Black - ( 32, 192, 32), -- Medium Green - ( 96, 224, 96), -- Light Green - ( 32, 32, 224), -- Dark Blue - ( 64, 96, 224), -- Light Blue - (160, 32, 32), -- Dark Red - ( 64, 192, 224), -- Cyan - (224, 32, 32), -- Medium Red - (224, 96, 96), -- Light Red - (192, 192, 32), -- Dark Yellow - (192, 192, 128), -- Light Yellow - ( 32, 128, 32), -- Dark Green - (192, 64, 160), -- Magenta - (160, 160, 160), -- Gray - (224, 224, 224) -- White - ); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Full RGB Value Array - -- - -- Refer to tms9928a.c of the MAME source distribution. - -- - constant full_rgb_table_c : rgb_table_t := ( - -- R G B - ( 0, 0, 0), -- Transparent RGB - ( 0, 0, 0), -- Black 000 - ( 33, 200, 66), -- Medium Green 162 - ( 94, 220, 120), -- Light Green 263 - ( 84, 85, 237), -- Dark Blue 227 - (125, 118, 252), -- Light Blue 337 - (212, 82, 77), -- Dark Red 622 - ( 66, 235, 245), -- Cyan 277 - (252, 85, 84), -- Medium Red 722 - (255, 121, 120), -- Light Red 733 - (212, 193, 84), -- Dark Yellow 662 - (230, 206, 128), -- Light Yellow 764 - ( 33, 176, 59), -- Dark Green 151 - (201, 91, 186), -- Magenta 625 - (204, 204, 204), -- Gray 333 - (255, 255, 255) -- White 777 - ); - -- - ----------------------------------------------------------------------------- - -end vdp18_col_pack; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_comp_pack-p.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_comp_pack-p.vhd deleted file mode 100644 index b24b866a..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_comp_pack-p.vhd +++ /dev/null @@ -1,205 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id: vdp18_comp_pack-p.vhd,v 1.23 2006/02/28 22:30:41 arnim Exp $ --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.vdp18_pack.opmode_t; -use work.vdp18_pack.hv_t; -use work.vdp18_pack.access_t; - -package vdp18_comp_pack is - - component vdp18_clk_gen - port ( - clock_i : in std_logic; - clk_en_10m7_i : in std_logic; - reset_i : in boolean; - clk_en_5m37_o : out boolean; - clk_en_3m58_o : out boolean; - clk_en_2m68_o : out boolean - ); - end component; - - component vdp18_hor_vert - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - reset_i : in boolean; - opmode_i : in opmode_t; - ntsc_pal_i : in std_logic; - num_pix_o : out hv_t; - num_line_o : out hv_t; - vert_inc_o : out boolean; - hsync_n_o : out std_logic; - vsync_n_o : out std_logic; - blank_o : out boolean; - cnt_hor_o : out std_logic_vector(8 downto 0); - cnt_ver_o : out std_logic_vector(7 downto 0) - ); - end component; - - component vdp18_ctrl - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - reset_i : in boolean; - opmode_i : in opmode_t; - vram_read_i : in boolean; - vram_write_i : in boolean; - vram_ce_o : out std_logic; - vram_oe_o : out std_logic; - num_pix_i : in hv_t; - num_line_i : in hv_t; - vert_inc_i : in boolean; - reg_blank_i : in boolean; - reg_size1_i : in boolean; - stop_sprite_i : in boolean; - clk_en_acc_o : out boolean; - access_type_o : out access_t; - vert_active_o : out boolean; - hor_active_o : out boolean; - irq_o : out boolean - ); - end component; - - component vdp18_cpuio - port ( - clock_i : in std_logic; - clk_en_10m7_i : in boolean; - clk_en_acc_i : in boolean; - reset_i : in boolean; - rd_i : in boolean; - wr_i : in boolean; - mode_i : in std_logic; - cd_i : in std_logic_vector(0 to 7); - cd_o : out std_logic_vector(0 to 7); - cd_oe_o : out std_logic; - access_type_i : in access_t; - opmode_o : out opmode_t; - vram_read_o : out boolean; - vram_write_o : out boolean; - vram_we_o : out std_logic; - vram_a_o : out std_logic_vector(0 to 13); - vram_d_o : out std_logic_vector(0 to 7); - vram_d_i : in std_logic_vector(0 to 7); - spr_coll_i : in boolean; - spr_5th_i : in boolean; - spr_5th_num_i : in std_logic_vector(0 to 4); - reg_ev_o : out boolean; - reg_16k_o : out boolean; - reg_blank_o : out boolean; - reg_size1_o : out boolean; - reg_mag1_o : out boolean; - reg_ntb_o : out std_logic_vector(0 to 3); - reg_ctb_o : out std_logic_vector(0 to 7); - reg_pgb_o : out std_logic_vector(0 to 2); - reg_satb_o : out std_logic_vector(0 to 6); - reg_spgb_o : out std_logic_vector(0 to 2); - reg_col1_o : out std_logic_vector(0 to 3); - reg_col0_o : out std_logic_vector(0 to 3); - irq_i : in boolean; - int_n_o : out std_logic - ); - end component; - - component vdp18_addr_mux - port ( - access_type_i : in access_t; - opmode_i : in opmode_t; - num_line_i : in hv_t; - reg_ntb_i : in std_logic_vector(0 to 3); - reg_ctb_i : in std_logic_vector(0 to 7); - reg_pgb_i : in std_logic_vector(0 to 2); - reg_satb_i : in std_logic_vector(0 to 6); - reg_spgb_i : in std_logic_vector(0 to 2); - reg_size1_i : in boolean; - cpu_vram_a_i : in std_logic_vector(0 to 13); - pat_table_i : in std_logic_vector(0 to 9); - pat_name_i : in std_logic_vector(0 to 7); - spr_num_i : in std_logic_vector(0 to 4); - spr_line_i : in std_logic_vector(0 to 3); - spr_name_i : in std_logic_vector(0 to 7); - vram_a_o : out std_logic_vector(0 to 13) - ); - end component; - - component vdp18_pattern - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - clk_en_acc_i : in boolean; - reset_i : in boolean; - opmode_i : in opmode_t; - access_type_i : in access_t; - num_line_i : in hv_t; - vram_d_i : in std_logic_vector(0 to 7); - vert_inc_i : in boolean; - vsync_n_i : in std_logic; - reg_col1_i : in std_logic_vector(0 to 3); - reg_col0_i : in std_logic_vector(0 to 3); - pat_table_o : out std_logic_vector(0 to 9); - pat_name_o : out std_logic_vector(0 to 7); - pat_col_o : out std_logic_vector(0 to 3) - ); - end component; - - component vdp18_sprite - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - clk_en_acc_i : in boolean; - reset_i : in boolean; - access_type_i : in access_t; - num_pix_i : in hv_t; - num_line_i : in hv_t; - vram_d_i : in std_logic_vector(0 to 7); - vert_inc_i : in boolean; - reg_size1_i : in boolean; - reg_mag1_i : in boolean; - spr_5th_o : out boolean; - spr_5th_num_o : out std_logic_vector(0 to 4); - stop_sprite_o : out boolean; - spr_coll_o : out boolean; - spr_num_o : out std_logic_vector(0 to 4); - spr_line_o : out std_logic_vector(0 to 3); - spr_name_o : out std_logic_vector(0 to 7); - spr0_col_o : out std_logic_vector(0 to 3); - spr1_col_o : out std_logic_vector(0 to 3); - spr2_col_o : out std_logic_vector(0 to 3); - spr3_col_o : out std_logic_vector(0 to 3) - ); - end component; - - component vdp18_col_mux - generic ( - compat_rgb_g : integer := 0 - ); - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - reset_i : in boolean; - vert_active_i : in boolean; - hor_active_i : in boolean; - blank_i : in boolean; - reg_col0_i : in std_logic_vector(0 to 3); - pat_col_i : in std_logic_vector(0 to 3); - spr0_col_i : in std_logic_vector(0 to 3); - spr1_col_i : in std_logic_vector(0 to 3); - spr2_col_i : in std_logic_vector(0 to 3); - spr3_col_i : in std_logic_vector(0 to 3); - col_o : out std_logic_vector(0 to 3); - rgb_r_o : out std_logic_vector(0 to 7); - rgb_g_o : out std_logic_vector(0 to 7); - rgb_b_o : out std_logic_vector(0 to 7) - ); - end component; - -end vdp18_comp_pack; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_core.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_core.vhd deleted file mode 100644 index d263b914..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_core.vhd +++ /dev/null @@ -1,394 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A. --- --- $Id: vdp18_core.vhd,v 1.28 2006/06/18 10:47:01 arnim Exp $ --- --- Core Toplevel --- --- Notes: --- This core implements a simple VRAM interface which is suitable for a --- synchronous SRAM component. There is currently no support of the --- original DRAM interface. --- --- Please be aware that the colors might me slightly different from the --- original TMS9918. It is assumed that the simplified conversion to RGB --- encoding is equivalent to the compatability mode of the V9938. --- Implementing a 100% correct color encoding for RGB would require --- significantly more logic and 8-bit wide RGB DACs. --- --- References: --- --- * TI Data book TMS9918.pdf --- http://www.bitsavers.org/pdf/ti/_dataBooks/TMS9918.pdf --- --- * Sean Young's tech article: --- http://bifi.msxnet.org/msxnet/tech/tms9918a.txt --- --- * Paul Urbanus' discussion of the timing details --- http://bifi.msxnet.org/msxnet/tech/tmsposting.txt --- --- * Richard F. Drushel's article series --- "This Week With My Coleco ADAM" --- http://junior.apk.net/~drushel/pub/coleco/twwmca/index.html --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity vdp18_core is - generic ( - compat_rgb_g : integer := 0 - ); - port ( - -- Global Interface ------------------------------------------------------- - clock_i : in std_logic; - clk_en_10m7_i : in std_logic; - clk_en_5m37_i : in std_logic; - reset_n_i : in std_logic; - -- CPU Interface ---------------------------------------------------------- - csr_n_i : in std_logic; - csw_n_i : in std_logic; - mode_i : in std_logic; - int_n_o : out std_logic; - cd_i : in std_logic_vector(0 to 7); - cd_o : out std_logic_vector(0 to 7); - -- VRAM Interface --------------------------------------------------------- - vram_ce_o : out std_logic; - vram_oe_o : out std_logic; - vram_we_o : out std_logic; - vram_a_o : out std_logic_vector(0 to 13); - vram_d_o : out std_logic_vector(0 to 7); - vram_d_i : in std_logic_vector(0 to 7); - -- Video Interface -------------------------------------------------------- - col_o : out std_logic_vector(0 to 3); - cnt_hor_o : out std_logic_vector(8 downto 0); - cnt_ver_o : out std_logic_vector(7 downto 0); - rgb_r_o : out std_logic_vector(0 to 7); - rgb_g_o : out std_logic_vector(0 to 7); - rgb_b_o : out std_logic_vector(0 to 7); - hsync_n_o : out std_logic; - vsync_n_o : out std_logic; - comp_sync_n_o : out std_logic - ); - -end vdp18_core; - - -use work.vdp18_comp_pack.all; -use work.vdp18_pack.opmode_t; -use work.vdp18_pack.hv_t; -use work.vdp18_pack.access_t; -use work.vdp18_pack.to_boolean_f; - -architecture struct of vdp18_core is - - signal reset_s : boolean; - - signal clk_en_10m7_s, - clk_en_5m37_s, - clk_en_acc_s : boolean; - - signal opmode_s : opmode_t; - - signal access_type_s : access_t; - - signal num_pix_s, - num_line_s : hv_t; - signal hsync_n_s, - vsync_n_s : std_logic; - signal blank_s : boolean; - - signal vert_inc_s : boolean; - - signal reg_blank_s, - reg_size1_s, - reg_mag1_s : boolean; - - signal spr_5th_s : boolean; - signal spr_5th_num_s : std_logic_vector(0 to 4); - - signal stop_sprite_s : boolean; - signal vert_active_s, - hor_active_s : boolean; - - signal rd_s, - wr_s : boolean; - - signal reg_ntb_s : std_logic_vector(0 to 3); - signal reg_ctb_s : std_logic_vector(0 to 7); - signal reg_pgb_s : std_logic_vector(0 to 2); - signal reg_satb_s : std_logic_vector(0 to 6); - signal reg_spgb_s : std_logic_vector(0 to 2); - signal reg_col1_s, - reg_col0_s : std_logic_vector(0 to 3); - signal cpu_vram_a_s : std_logic_vector(0 to 13); - - signal pat_table_s : std_logic_vector(0 to 9); - signal pat_name_s : std_logic_vector(0 to 7); - signal pat_col_s : std_logic_vector(0 to 3); - - signal spr_num_s : std_logic_vector(0 to 4); - signal spr_line_s : std_logic_vector(0 to 3); - signal spr_name_s : std_logic_vector(0 to 7); - signal spr0_col_s, - spr1_col_s, - spr2_col_s, - spr3_col_s : std_logic_vector(0 to 3); - signal spr_coll_s : boolean; - - signal irq_s : boolean; - --- signal false_s : boolean; - - signal vram_read_s : boolean; - signal vram_write_s : boolean; - -begin - - -- temporary defaults - -- false_s <= false; - - clk_en_10m7_s <= to_boolean_f(clk_en_10m7_i); - clk_en_5m37_s <= to_boolean_f(clk_en_5m37_i); - rd_s <= not to_boolean_f(csr_n_i); - wr_s <= not to_boolean_f(csw_n_i); - - reset_s <= reset_n_i = '0'; - - ----------------------------------------------------------------------------- - -- Horizontal and Vertical Timing Generator - ----------------------------------------------------------------------------- - hor_vert_b : vdp18_hor_vert - port map ( - clock_i => clock_i, - clk_en_5m37_i => clk_en_5m37_s, - reset_i => reset_s, - opmode_i => opmode_s, - ntsc_pal_i => '0', -- NTSC - num_pix_o => num_pix_s, - num_line_o => num_line_s, - vert_inc_o => vert_inc_s, - hsync_n_o => hsync_n_s, - vsync_n_o => vsync_n_s, - blank_o => blank_s, - cnt_hor_o => cnt_hor_o, - cnt_ver_o => cnt_ver_o - ); - - hsync_n_o <= hsync_n_s; - vsync_n_o <= vsync_n_s; - comp_sync_n_o <= not (hsync_n_s xor vsync_n_s); - - - ----------------------------------------------------------------------------- - -- Control Module - ----------------------------------------------------------------------------- - ctrl_b : vdp18_ctrl - port map ( - clock_i => clock_i, - clk_en_5m37_i => clk_en_5m37_s, - reset_i => reset_s, - opmode_i => opmode_s, - vram_read_i => vram_read_s, - vram_write_i => vram_write_s, - vram_ce_o => vram_ce_o, - vram_oe_o => vram_oe_o, - num_pix_i => num_pix_s, - num_line_i => num_line_s, - vert_inc_i => vert_inc_s, - reg_blank_i => reg_blank_s, - reg_size1_i => reg_size1_s, - stop_sprite_i => stop_sprite_s, - clk_en_acc_o => clk_en_acc_s, - access_type_o => access_type_s, - vert_active_o => vert_active_s, - hor_active_o => hor_active_s, - irq_o => irq_s - ); - - - ----------------------------------------------------------------------------- - -- CPU I/O Module - ----------------------------------------------------------------------------- - cpu_io_b : vdp18_cpuio - port map ( - clock_i => clock_i, - clk_en_10m7_i => clk_en_10m7_s, - clk_en_acc_i => clk_en_acc_s, - reset_i => reset_s, - rd_i => rd_s, - wr_i => wr_s, - mode_i => mode_i, - cd_i => cd_i, - cd_o => cd_o, - cd_oe_o => open, - access_type_i => access_type_s, - opmode_o => opmode_s, - vram_read_o => vram_read_s, - vram_write_o => vram_write_s, - vram_we_o => vram_we_o, - vram_a_o => cpu_vram_a_s, - vram_d_o => vram_d_o, - vram_d_i => vram_d_i, - spr_coll_i => spr_coll_s, - spr_5th_i => spr_5th_s, - spr_5th_num_i => spr_5th_num_s, - reg_ev_o => open, - reg_16k_o => open, - reg_blank_o => reg_blank_s, - reg_size1_o => reg_size1_s, - reg_mag1_o => reg_mag1_s, - reg_ntb_o => reg_ntb_s, - reg_ctb_o => reg_ctb_s, - reg_pgb_o => reg_pgb_s, - reg_satb_o => reg_satb_s, - reg_spgb_o => reg_spgb_s, - reg_col1_o => reg_col1_s, - reg_col0_o => reg_col0_s, - irq_i => irq_s, - int_n_o => int_n_o - ); - - - ----------------------------------------------------------------------------- - -- VRAM Address Multiplexer - ----------------------------------------------------------------------------- - addr_mux_b : vdp18_addr_mux - port map ( - access_type_i => access_type_s, - opmode_i => opmode_s, - num_line_i => num_line_s, - reg_ntb_i => reg_ntb_s, - reg_ctb_i => reg_ctb_s, - reg_pgb_i => reg_pgb_s, - reg_satb_i => reg_satb_s, - reg_spgb_i => reg_spgb_s, - reg_size1_i => reg_size1_s, - cpu_vram_a_i => cpu_vram_a_s, - pat_table_i => pat_table_s, - pat_name_i => pat_name_s, - spr_num_i => spr_num_s, - spr_line_i => spr_line_s, - spr_name_i => spr_name_s, - vram_a_o => vram_a_o - ); - - - ----------------------------------------------------------------------------- - -- Pattern Generator - ----------------------------------------------------------------------------- - pattern_b : vdp18_pattern - port map ( - clock_i => clock_i, - clk_en_5m37_i => clk_en_5m37_s, - clk_en_acc_i => clk_en_acc_s, - reset_i => reset_s, - opmode_i => opmode_s, - access_type_i => access_type_s, - num_line_i => num_line_s, - vram_d_i => vram_d_i, - vert_inc_i => vert_inc_s, - vsync_n_i => vsync_n_s, - reg_col1_i => reg_col1_s, - reg_col0_i => reg_col0_s, - pat_table_o => pat_table_s, - pat_name_o => pat_name_s, - pat_col_o => pat_col_s - ); - - - ----------------------------------------------------------------------------- - -- Sprite Generator - ----------------------------------------------------------------------------- - sprite_b : vdp18_sprite - port map ( - clock_i => clock_i, - clk_en_5m37_i => clk_en_5m37_s, - clk_en_acc_i => clk_en_acc_s, - reset_i => reset_s, - access_type_i => access_type_s, - num_pix_i => num_pix_s, - num_line_i => num_line_s, - vram_d_i => vram_d_i, - vert_inc_i => vert_inc_s, - reg_size1_i => reg_size1_s, - reg_mag1_i => reg_mag1_s, - spr_5th_o => spr_5th_s, - spr_5th_num_o => spr_5th_num_s, - stop_sprite_o => stop_sprite_s, - spr_coll_o => spr_coll_s, - spr_num_o => spr_num_s, - spr_line_o => spr_line_s, - spr_name_o => spr_name_s, - spr0_col_o => spr0_col_s, - spr1_col_o => spr1_col_s, - spr2_col_o => spr2_col_s, - spr3_col_o => spr3_col_s - ); - - - ----------------------------------------------------------------------------- - -- Color Multiplexer - ----------------------------------------------------------------------------- - col_mux_b : vdp18_col_mux - generic map ( - compat_rgb_g => compat_rgb_g - ) - port map ( - clock_i => clock_i, - clk_en_5m37_i => clk_en_5m37_s, - reset_i => reset_s, - vert_active_i => vert_active_s, - hor_active_i => hor_active_s, - blank_i => blank_s, - reg_col0_i => reg_col0_s, - pat_col_i => pat_col_s, - spr0_col_i => spr0_col_s, - spr1_col_i => spr1_col_s, - spr2_col_i => spr2_col_s, - spr3_col_i => spr3_col_s, - col_o => col_o, - rgb_r_o => rgb_r_o, - rgb_g_o => rgb_g_o, - rgb_b_o => rgb_b_o - ); - -end struct; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_core_comp_pack-p.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_core_comp_pack-p.vhd deleted file mode 100644 index 8cf260c0..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_core_comp_pack-p.vhd +++ /dev/null @@ -1,49 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id: vdp18_core_comp_pack-p.vhd,v 1.10 2006/02/28 22:30:41 arnim Exp $ --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -package vdp18_core_comp_pack is - - component vdp18_core - generic ( - is_pal_g : boolean := false; - compat_rgb_g : integer := 0 - ); - port ( - clock_i : in std_logic; - clk_en_10m7_i : in std_logic; - reset_n_i : in std_logic; - csr_n_i : in std_logic; - csw_n_i : in std_logic; - mode_i : in std_logic; - int_n_o : out std_logic; - cd_i : in std_logic_vector(0 to 7); - cd_o : out std_logic_vector(0 to 7); - vram_ce_o : out std_logic; - vram_oe_o : out std_logic; - vram_we_o : out std_logic; - vram_a_o : out std_logic_vector(0 to 13); - vram_d_o : out std_logic_vector(0 to 7); - vram_d_i : in std_logic_vector(0 to 7); - col_o : out std_logic_vector(0 to 3); - cnt_hor_o : out std_logic_vector(8 downto 0); - cnt_ver_o : out std_logic_vector(7 downto 0); - rgb_r_o : out std_logic_vector(0 to 7); - rgb_g_o : out std_logic_vector(0 to 7); - rgb_b_o : out std_logic_vector(0 to 7); - hsync_n_o : out std_logic; - vsync_n_o : out std_logic; - comp_sync_n_o : out std_logic - ); - end component; - -end vdp18_core_comp_pack; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_cpuio.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_cpuio.vhd deleted file mode 100644 index bdf78042..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_cpuio.vhd +++ /dev/null @@ -1,572 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A. --- --- $Id: vdp18_cpuio.vhd,v 1.17 2006/06/18 10:47:01 arnim Exp $ --- --- CPU I/O Interface Module --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.vdp18_pack.access_t; -use work.vdp18_pack.opmode_t; - -entity vdp18_cpuio is - - port ( - clock_i : in std_logic; - clk_en_10m7_i : in boolean; - clk_en_acc_i : in boolean; - reset_i : in boolean; - rd_i : in boolean; - wr_i : in boolean; - mode_i : in std_logic; - cd_i : in std_logic_vector(0 to 7); - cd_o : out std_logic_vector(0 to 7); - cd_oe_o : out std_logic; - access_type_i : in access_t; - opmode_o : out opmode_t; - vram_read_o : out boolean; - vram_write_o : out boolean; - vram_we_o : out std_logic; - vram_a_o : out std_logic_vector(0 to 13); - vram_d_o : out std_logic_vector(0 to 7); - vram_d_i : in std_logic_vector(0 to 7); - spr_coll_i : in boolean; - spr_5th_i : in boolean; - spr_5th_num_i : in std_logic_vector(0 to 4); - reg_ev_o : out boolean; - reg_16k_o : out boolean; - reg_blank_o : out boolean; - reg_size1_o : out boolean; - reg_mag1_o : out boolean; - reg_ntb_o : out std_logic_vector(0 to 3); - reg_ctb_o : out std_logic_vector(0 to 7); - reg_pgb_o : out std_logic_vector(0 to 2); - reg_satb_o : out std_logic_vector(0 to 6); - reg_spgb_o : out std_logic_vector(0 to 2); - reg_col1_o : out std_logic_vector(0 to 3); - reg_col0_o : out std_logic_vector(0 to 3); - irq_i : in boolean; - int_n_o : out std_logic - ); - -end vdp18_cpuio; - - -library ieee; -use ieee.numeric_std.all; - -use work.vdp18_pack.all; - -architecture rtl of vdp18_cpuio is - - type state_t is (ST_IDLE, - ST_RD_MODE0, ST_WR_MODE0, - ST_RD_MODE1, - ST_WR_MODE1_1ST, ST_WR_MODE1_1ST_IDLE, - ST_WR_MODE1_2ND_VREAD, ST_WR_MODE1_2ND_VWRITE, - ST_WR_MODE1_2ND_RWRITE); - signal state_s, - state_q : state_t; - - signal buffer_q : std_logic_vector(0 to 7); - - signal addr_q : unsigned(0 to 13); - - signal incr_addr_s, - load_addr_s : boolean; - - signal wrbuf_cpu_s : boolean; - signal sched_rdvram_s, - rdvram_sched_q, - rdvram_q : boolean; - signal abort_wrvram_s, - sched_wrvram_s, - wrvram_sched_q, - wrvram_q : boolean; - - signal write_tmp_s : boolean; - signal tmp_q : std_logic_vector(0 to 7); - signal write_reg_s : boolean; - - -- control register bits ---------------------------------------------------- - type ctrl_reg_t is array (natural range 7 downto 0) of - std_logic_vector(0 to 7); - signal ctrl_reg_q : ctrl_reg_t; - - -- status register ---------------------------------------------------------- - signal status_reg_s : std_logic_vector(0 to 7); - signal destr_rd_status_s : boolean; - signal sprite_5th_q : boolean; - signal sprite_5th_num_q : std_logic_vector(0 to 4); - signal sprite_coll_q : boolean; - signal int_n_q : std_logic; - - - type read_mux_t is (RDMUX_STATUS, RDMUX_READAHEAD); - signal read_mux_s : read_mux_t; - -begin - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the sequential elements. - -- - seq: process (clock_i, reset_i) - variable incr_addr_v : boolean; - begin - if reset_i then - state_q <= ST_IDLE; - buffer_q <= (others => '0'); - addr_q <= (others => '0'); - rdvram_sched_q <= false; - rdvram_q <= false; - wrvram_sched_q <= false; - wrvram_q <= false; - - elsif clock_i'event and clock_i = '1' then - -- default assignments - incr_addr_v := incr_addr_s; - - if clk_en_10m7_i then - -- update state vector ------------------------------------------------ - state_q <= state_s; - - -- buffer and flag control -------------------------------------------- - if wrbuf_cpu_s then - -- write read-ahead buffer from CPU bus - buffer_q <= cd_i; - -- immediately stop read-ahead - rdvram_sched_q <= false; - rdvram_q <= false; - elsif clk_en_acc_i and rdvram_q and access_type_i = AC_CPU then - -- write read-ahead buffer from VRAM during CPU access slot - buffer_q <= vram_d_i; - -- stop scanning for CPU data - rdvram_q <= false; - -- increment read-ahead address - incr_addr_v := true; - end if; - - if sched_rdvram_s then - -- immediately stop write-back - wrvram_sched_q <= false; - wrvram_q <= false; - -- schedule read-ahead - rdvram_sched_q <= true; - end if; - - if sched_wrvram_s then - -- schedule write-back - wrvram_sched_q <= true; - end if; - - if abort_wrvram_s then - -- stop scanning for write-back - wrvram_q <= false; - end if; - - if rdvram_sched_q and clk_en_acc_i then - -- align scheduled read-ahead with access slot phase - rdvram_sched_q <= false; - rdvram_q <= true; - end if; - if wrvram_sched_q and clk_en_acc_i then - -- align scheduled write-back with access slot phase - wrvram_sched_q <= false; - wrvram_q <= true; - end if; - - -- manage address ----------------------------------------------------- - if load_addr_s then - addr_q(6 to 13) <= unsigned(tmp_q); - addr_q(0 to 5) <= unsigned(cd_i(2 to 7)); - elsif incr_addr_v then - addr_q <= addr_q + 1; - end if; - - end if; - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - vram_read_o <= rdvram_q; - vram_write_o <= wrvram_q; - - ----------------------------------------------------------------------------- - -- Process wback_ctrl - -- - -- Purpose: - -- Write-back control. - -- - wback_ctrl: process (clk_en_acc_i, - access_type_i, - wrvram_q) - begin - -- default assignments - abort_wrvram_s <= false; - incr_addr_s <= false; - vram_we_o <= '0'; - - if wrvram_q then - if access_type_i = AC_CPU then - -- signal write access to VRAM - vram_we_o <= '1'; - - if clk_en_acc_i then - -- clear write-back flag and increment address - abort_wrvram_s <= true; - incr_addr_s <= true; - end if; - end if; - end if; - end process wback_ctrl; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process reg_if - -- - -- Purpose: - -- Implements the register interface. - -- - reg_if: process (clock_i, reset_i) - variable reg_addr_v : unsigned(0 to 2); - begin - if reset_i then - tmp_q <= (others => '0'); - ctrl_reg_q <= (others => (others => '0')); - sprite_coll_q <= false; - sprite_5th_q <= false; - sprite_5th_num_q <= (others => '0'); - int_n_q <= '1'; - ctrl_reg_q(1) <= X"C0"; - ctrl_reg_q(2) <= X"02"; - ctrl_reg_q(3) <= X"2C"; - ctrl_reg_q(7) <= X"F7"; - - elsif clock_i'event and clock_i = '1' then - if clk_en_10m7_i then - -- Temporary register ------------------------------------------------- - if write_tmp_s then - tmp_q <= cd_i; - end if; - - -- Registers 0 to 7 --------------------------------------------------- - if write_reg_s then - reg_addr_v := unsigned(cd_i(5 to 7)); - ctrl_reg_q(to_integer(reg_addr_v)) <= tmp_q; - end if; - - end if; - - -- Fifth sprite handling ------------------------------------------------ - if spr_5th_i and not sprite_5th_q then - sprite_5th_q <= true; - sprite_5th_num_q <= spr_5th_num_i; - elsif destr_rd_status_s then - sprite_5th_q <= false; - end if; - - -- Sprite collision flag ------------------------------------------------ - if spr_coll_i then - sprite_coll_q <= true; - elsif destr_rd_status_s then - sprite_coll_q <= false; - end if; - - -- Interrupt ------------------------------------------------------------ - if irq_i then - int_n_q <= '0'; - elsif destr_rd_status_s then - int_n_q <= '1'; - end if; - end if; - end process reg_if; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process access_ctrl - -- - -- Purpose: - -- Implements the combinational logic for the CPU I/F FSM. - -- Decodes the CPU I/F FSM state and generates the control signals for the - -- register and VRAM logic. - -- - access_ctrl: process (state_q, - rd_i, wr_i, - mode_i, - cd_i) - type transfer_mode_t is (TM_NONE, - TM_RD_MODE0, TM_WR_MODE0, - TM_RD_MODE1, TM_WR_MODE1); - variable transfer_mode_v : transfer_mode_t; - begin - -- default assignments - state_s <= state_q; - sched_rdvram_s <= false; - sched_wrvram_s <= false; - wrbuf_cpu_s <= false; - write_tmp_s <= false; - write_reg_s <= false; - load_addr_s <= false; - read_mux_s <= RDMUX_STATUS; - destr_rd_status_s <= false; - - -- determine transfer mode - transfer_mode_v := TM_NONE; - if mode_i = '0' then - if rd_i then - transfer_mode_v := TM_RD_MODE0; - end if; - if wr_i then - transfer_mode_v := TM_WR_MODE0; - end if; - else - if rd_i then - transfer_mode_v := TM_RD_MODE1; - end if; - if wr_i then - transfer_mode_v := TM_WR_MODE1; - end if; - end if; - - -- FSM state transitions - case state_q is - -- ST_IDLE: waiting for CPU access -------------------------------------- - when ST_IDLE => - case transfer_mode_v is - when TM_RD_MODE0 => - state_s <= ST_RD_MODE0; - when TM_WR_MODE0 => - state_s <= ST_WR_MODE0; - when TM_RD_MODE1 => - state_s <= ST_RD_MODE1; - when TM_WR_MODE1 => - state_s <= ST_WR_MODE1_1ST; - when others => - null; - end case; - - -- ST_RD_MODE0: read from VRAM ------------------------------------------ - when ST_RD_MODE0 => - -- set read mux - read_mux_s <= RDMUX_READAHEAD; - - if transfer_mode_v = TM_NONE then - -- CPU finished read access: - -- schedule new read-ahead and return to idle - state_s <= ST_IDLE; - sched_rdvram_s <= true; - end if; - - -- ST_WR_MODE0: write to VRAM ------------------------------------------- - when ST_WR_MODE0 => - -- write data from CPU to write-back/read-ahead buffer - wrbuf_cpu_s <= true; - - if transfer_mode_v = TM_NONE then - -- CPU finished write access: - -- schedule new write-back and return to idle - state_s <= ST_IDLE; - sched_wrvram_s <= true; - end if; - - -- ST_RD_MODE1: read from status register ------------------------------- - when ST_RD_MODE1 => - -- set read mux - read_mux_s <= RDMUX_STATUS; - - if transfer_mode_v = TM_NONE then - -- CPU finished read access: - -- destructive read of status register and return to IDLE - destr_rd_status_s <= true; - state_s <= ST_IDLE; - end if; - - -- ST_WR_MODE1_1ST: save first byte ------------------------------------- - when ST_WR_MODE1_1ST => - -- update temp register - write_tmp_s <= true; - - if transfer_mode_v = TM_NONE then - -- CPU finished write access: - -- become idle but remember that the first byte of a paired write - -- has been written - state_s <= ST_WR_MODE1_1ST_IDLE; - end if; - - -- ST_WR_MODE1_1ST_IDLE: wait for next access --------------------------- - when ST_WR_MODE1_1ST_IDLE => - -- determine type of next access - case transfer_mode_v is - when TM_RD_MODE0 => - state_s <= ST_RD_MODE0; - when TM_WR_MODE0 => - state_s <= ST_WR_MODE0; - when TM_RD_MODE1 => - state_s <= ST_RD_MODE1; - when TM_WR_MODE1 => - case cd_i(0 to 1) is - when "00" => - state_s <= ST_WR_MODE1_2ND_VREAD; - when "01" => - state_s <= ST_WR_MODE1_2ND_VWRITE; - when "10" | "11" => - state_s <= ST_WR_MODE1_2ND_RWRITE; - when others => - null; - end case; - when others => - null; - end case; - - -- ST_WR_MODE1_2ND_VREAD: write second byte of address, then read ahead - - when ST_WR_MODE1_2ND_VREAD => - load_addr_s <= true; - - if transfer_mode_v = TM_NONE then - -- CPU finished write access: - -- schedule new read-ahead and return to idle - sched_rdvram_s <= true; - state_s <= ST_IDLE; - end if; - - -- ST_WR_MODE1_2ND_VWRITE: write second byte of address - when ST_WR_MODE1_2ND_VWRITE => - load_addr_s <= true; - - if transfer_mode_v = TM_NONE then - -- CPU finished write access: - -- return to idle - state_s <= ST_IDLE; - end if; - - -- ST_WR_MODE1_2ND_RWRITE: write to register ---------------------------- - when ST_WR_MODE1_2ND_RWRITE => - write_reg_s <= true; - - if transfer_mode_v = TM_NONE then - -- CPU finished write access: - -- return to idle - state_s <= ST_IDLE; - end if; - - when others => - null; - - end case; - - end process access_ctrl; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process mode_decode - -- - -- Purpose: - -- Decodes the display mode from the M1, M2, M3 bits. - -- - mode_decode: process (ctrl_reg_q) - variable mode_v : std_logic_vector(0 to 2); - begin - mode_v := ctrl_reg_q(1)(3) & -- M1 - ctrl_reg_q(1)(4) & -- M2 - ctrl_reg_q(0)(6); -- M3 - - case mode_v is - when "000" => - opmode_o <= OPMODE_GRAPH1; - when "001" => - opmode_o <= OPMODE_GRAPH2; - when "010" => - opmode_o <= OPMODE_MULTIC; - when "100" => - opmode_o <= OPMODE_TEXTM; - when others => - opmode_o <= OPMODE_TEXTM; - end case; - end process mode_decode; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Build status register - ----------------------------------------------------------------------------- - status_reg_s <= not int_n_q & - to_std_logic_f(sprite_5th_q) & - to_std_logic_f(sprite_coll_q) & - sprite_5th_num_q; - - ----------------------------------------------------------------------------- - -- Output mapping - ----------------------------------------------------------------------------- - vram_a_o <= std_logic_vector(addr_q); - vram_d_o <= buffer_q; - - cd_o <= buffer_q when read_mux_s = RDMUX_READAHEAD else status_reg_s; - cd_oe_o <= '1' when rd_i else '0'; - - reg_ev_o <= to_boolean_f(ctrl_reg_q(0)(7)); - reg_16k_o <= to_boolean_f(ctrl_reg_q(1)(0)); - reg_blank_o <= not to_boolean_f(ctrl_reg_q(1)(1)); - reg_size1_o <= to_boolean_f(ctrl_reg_q(1)(6)); - reg_mag1_o <= to_boolean_f(ctrl_reg_q(1)(7)); - reg_ntb_o <= ctrl_reg_q(2)(4 to 7); - reg_ctb_o <= ctrl_reg_q(3); - reg_pgb_o <= ctrl_reg_q(4)(5 to 7); - reg_satb_o <= ctrl_reg_q(5)(1 to 7); - reg_spgb_o <= ctrl_reg_q(6)(5 to 7); - reg_col1_o <= ctrl_reg_q(7)(0 to 3); - reg_col0_o <= ctrl_reg_q(7)(4 to 7); - int_n_o <= int_n_q or not ctrl_reg_q(1)(2); - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_ctrl.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_ctrl.vhd deleted file mode 100644 index 6b6f8b23..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_ctrl.vhd +++ /dev/null @@ -1,410 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A. --- --- $Id: vdp18_ctrl.vhd,v 1.26 2006/06/18 10:47:01 arnim Exp $ --- --- Timing Controller --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.vdp18_pack.opmode_t; -use work.vdp18_pack.hv_t; -use work.vdp18_pack.access_t; - -entity vdp18_ctrl is - - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - reset_i : in boolean; - opmode_i : in opmode_t; - vram_read_i : in boolean; - vram_write_i : in boolean; - vram_ce_o : out std_logic; - vram_oe_o : out std_logic; - num_pix_i : in hv_t; - num_line_i : in hv_t; - vert_inc_i : in boolean; - reg_blank_i : in boolean; - reg_size1_i : in boolean; - stop_sprite_i : in boolean; - clk_en_acc_o : out boolean; - access_type_o : out access_t; - vert_active_o : out boolean; - hor_active_o : out boolean; - irq_o : out boolean - ); - -end vdp18_ctrl; - - -use work.vdp18_pack.all; - -architecture rtl of vdp18_ctrl is - - ----------------------------------------------------------------------------- - -- This enables a workaround for a bug in XST. - -- ISE 8.1.02i implements wrong functionality otherwise :-( - -- - constant xst_bug_wa_c : boolean := true; - -- - ----------------------------------------------------------------------------- - - signal access_type_s : access_t; - - -- pragma translate_off - -- Testbench signals -------------------------------------------------------- - -- - signal ac_s : std_logic_vector(3 downto 0); - -- - ----------------------------------------------------------------------------- - -- pragma translate_on - - signal vert_active_q, - hor_active_q : boolean; - signal sprite_active_q : boolean; - signal sprite_line_act_q : boolean; - -begin - - -- pragma translate_off - -- Testbench signals -------------------------------------------------------- - -- - ac_s <= enum_to_vec_f(access_type_s); - -- - ----------------------------------------------------------------------------- - -- pragma translate_on - - - ----------------------------------------------------------------------------- - -- Process decode_access - -- - -- Purpose: - -- Decode horizontal counter value to access type. - -- - decode_access: process (opmode_i, - num_pix_i, - vert_active_q, - sprite_line_act_q, - reg_size1_i) - variable num_pix_plus_6_v : hv_t; - variable mod_6_v : hv_t; - variable num_pix_plus_8_v : hv_t; - variable num_pix_plus_32_v : hv_t; - variable num_pix_spr_v : integer; - begin - -- default assignment - access_type_s <= AC_CPU; - - -- prepare number of pixels for pattern operations - num_pix_plus_6_v := num_pix_i + 6; - num_pix_plus_8_v := num_pix_i + 8; - num_pix_plus_32_v := num_pix_i + 32; - num_pix_spr_v := to_integer(num_pix_i and "111111110"); - - case opmode_i is - -- Graphics I, II and Multicolor Mode ----------------------------------- - when OPMODE_GRAPH1 | - OPMODE_GRAPH2 | - OPMODE_MULTIC => - -- - -- Patterns - -- - if vert_active_q then - if num_pix_plus_8_v(0) = '0' then - if not xst_bug_wa_c then - - -- original code, we want this - case num_pix_plus_8_v(6 to 7) is - when "01" => - access_type_s <= AC_PNT; - when "10" => - if opmode_i /= OPMODE_MULTIC then - -- no access to pattern color table in multicolor mode - access_type_s <= AC_PCT; - end if; - when "11" => - access_type_s <= AC_PGT; - when others => - null; - end case; - - else - - -- workaround for XST bug, we need this - if num_pix_plus_8_v(6 to 7) = "01" then - access_type_s <= AC_PNT; - elsif num_pix_plus_8_v(6 to 7) = "10" then - if opmode_i /= OPMODE_MULTIC then - access_type_s <= AC_PCT; - end if; - elsif num_pix_plus_8_v(6 to 7) = "11" then - access_type_s <= AC_PGT; - end if; - - end if; - end if; - end if; - - -- - -- Sprite test - -- - if sprite_line_act_q then - if num_pix_i(0) = '0' and - num_pix_i(0 to 5) /= "011111" and - num_pix_i(6 to 7) = "00" and - num_pix_i(4 to 5) /= "00" then - -- sprite test interleaved with pattern accesses - access_type_s <= AC_STST; - end if; - if (num_pix_plus_32_v(0 to 4) = "00000" or - num_pix_plus_32_v(0 to 5) = "000010") and - num_pix_plus_32_v(6 to 7) /= "00" then - -- sprite tests before starting pattern phase - access_type_s <= AC_STST; - end if; - - -- - -- Sprite Attribute Table and Sprite Pattern Table - -- - case num_pix_spr_v is - when 250 | -78 | - -62 | -46 => - access_type_s <= AC_SATY; - when 254 | -76 | - -60 | -44 => - access_type_s <= AC_SATX; - when 252 | -74 | - -58 | -42 => - access_type_s <= AC_SATN; - when -86 | -70 | - -54 | -38 => - access_type_s <= AC_SATC; - when -84 | -68 | - -52 | -36 => - access_type_s <= AC_SPTH; - when -82 | -66 | - -50 | -34 => - if reg_size1_i then - access_type_s <= AC_SPTL; - end if; - when others => - null; - end case; - end if; - - -- Text Mode ------------------------------------------------------------ - when OPMODE_TEXTM => - if vert_active_q and - num_pix_plus_6_v(0) = '0' and - num_pix_plus_6_v(0 to 4) /= "01111" then - mod_6_v := mod_6_f(num_pix_plus_6_v); - case mod_6_v(6 to 7) is - when "00" => - access_type_s <= AC_PNT; - when "10" => - access_type_s <= AC_PGT; - when others => - null; - end case; - end if; - - -- Unknown -------------------------------------------------------------- --- when others => --- null; - - end case; - - end process decode_access; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process vert_flags - -- - -- Purpose: - -- Track the vertical position with flags. - -- - vert_flags: process (clock_i, reset_i) - begin - if reset_i then - vert_active_q <= false; - sprite_active_q <= false; - sprite_line_act_q <= false; - - elsif clock_i'event and clock_i = '1' then - if clk_en_5m37_i then - -- line-local sprite processing - if sprite_active_q then - -- sprites are globally enabled - if vert_inc_i then - -- reload at beginning of every new line - -- => scan with STST - sprite_line_act_q <= true; - end if; - - if num_pix_i = hv_sprite_start_c then - -- reload when access to sprite memory starts - sprite_line_act_q <= true; - end if; - end if; - - if vert_inc_i then - -- global sprite processing - if reg_blank_i then - sprite_active_q <= false; - sprite_line_act_q <= false; - elsif num_line_i = -2 then - -- start at line -1 - sprite_active_q <= true; - -- initialize immediately - sprite_line_act_q <= true; - elsif num_line_i = 191 then - -- stop at line 192 - sprite_active_q <= false; - -- force stop - sprite_line_act_q <= false; - end if; - - -- global vertical display - if reg_blank_i then - vert_active_q <= false; - elsif num_line_i = -1 then - -- start vertical display at line 0 - vert_active_q <= true; - elsif num_line_i = 191 then - -- stop at line 192 - vert_active_q <= false; - end if; - end if; - - if stop_sprite_i then - -- stop processing of sprites in this line - sprite_line_act_q <= false; - end if; - - end if; - end if; - end process vert_flags; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process hor_flags - -- - -- Purpose: - -- Track the horizontal position. - -- - hor_flags: process (clock_i, reset_i) - begin - if reset_i then - hor_active_q <= false; - - elsif clock_i'event and clock_i = '1' then - if clk_en_5m37_i then - if not reg_blank_i and - num_pix_i = -1 then - hor_active_q <= true; - end if; - - if opmode_i = OPMODE_TEXTM then - if num_pix_i = 239 then - hor_active_q <= false; - end if; - else - if num_pix_i = 255 then - hor_active_q <= false; - end if; - end if; - end if; - end if; - end process hor_flags; - -- - ----------------------------------------------------------------------------- - - vram_ctrl: process (clock_i) - variable read_b_v : boolean; - begin - if rising_edge(clock_i) then - if clk_en_5m37_i then - vram_ce_o <= '0'; - vram_oe_o <= '0'; - if access_type_s = AC_CPU then - if vram_read_i and not read_b_v then - vram_ce_o <= '1'; - vram_oe_o <= '1'; - read_b_v := true; - elsif vram_write_i and not read_b_v then - vram_ce_o <= '1'; - -- - read_b_v := true; - else - read_b_v := false; - end if; - else - if not read_b_v then - vram_ce_o <= '1'; - vram_oe_o <= '1'; - read_b_v := true; - else - read_b_v := false; - end if; - end if; - end if; - end if; - end process; - - ----------------------------------------------------------------------------- - -- Ouput mapping - ----------------------------------------------------------------------------- - -- generate clock enable for flip-flops working on access_type - clk_en_acc_o <= clk_en_5m37_i and num_pix_i(8) = '1'; - access_type_o <= access_type_s; - vert_active_o <= vert_active_q; - hor_active_o <= hor_active_q; - irq_o <= vert_inc_i and num_line_i = 191; - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_hor_vert.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_hor_vert.vhd deleted file mode 100644 index 07c7e63c..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_hor_vert.vhd +++ /dev/null @@ -1,243 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A. --- --- $Id: vdp18_hor_vert.vhd,v 1.11 2006/06/18 10:47:01 arnim Exp $ --- --- Horizontal / Vertical Timing Generator --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.vdp18_pack.opmode_t; -use work.vdp18_pack.hv_t; - -entity vdp18_hor_vert is - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - reset_i : in boolean; - opmode_i : in opmode_t; - ntsc_pal_i : in std_logic; - num_pix_o : out hv_t; - num_line_o : out hv_t; - vert_inc_o : out boolean; - hsync_n_o : out std_logic; - vsync_n_o : out std_logic; - blank_o : out boolean; - cnt_hor_o : out std_logic_vector(8 downto 0); - cnt_ver_o : out std_logic_vector(7 downto 0) - ); - -end vdp18_hor_vert; - - -use work.vdp18_pack.all; - -architecture rtl of vdp18_hor_vert is - - signal last_line_s : hv_t; - signal first_line_s : hv_t; - - signal first_pix_s : hv_t; - signal last_pix_s : hv_t; - - signal cnt_hor_q : hv_t; - signal cnt_vert_q : hv_t; - - signal vert_inc_s : boolean; - - signal hblank_q, - vblank_q : boolean; - - signal cnt_hor_s : unsigned(8 downto 0); - signal cnt_ver_s : unsigned(7 downto 0); - -begin - - ----------------------------------------------------------------------------- - -- Prepare comparison signals for NTSC and PAL. - -- - first_line_s <= hv_first_line_ntsc_c when ntsc_pal_i = '0' else hv_first_line_pal_c; - last_line_s <= hv_last_line_ntsc_c when ntsc_pal_i = '0' else hv_last_line_pal_c; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process opmode_mux - -- - -- Purpose: - -- Generates the horizontal counter limits based on the current operating - -- mode. - -- - opmode_mux: process (opmode_i) - begin - if opmode_i = OPMODE_TEXTM then - first_pix_s <= hv_first_pix_text_c; - last_pix_s <= hv_last_pix_text_c; - else - first_pix_s <= hv_first_pix_graph_c; - last_pix_s <= hv_last_pix_graph_c; - end if; - end process opmode_mux; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process counters - -- - -- Purpose: - -- Implements the horizontal and vertical counters. - -- - counters: process (clock_i, reset_i, first_line_s) - begin - if reset_i then - cnt_hor_q <= hv_first_pix_text_c; - cnt_vert_q <= first_line_s; - hsync_n_o <= '1'; - vsync_n_o <= '1'; - hblank_q <= false; - vblank_q <= false; - - elsif clock_i'event and clock_i = '1' then - if clk_en_5m37_i then - -- The horizontal counter --------------------------------------------- - if cnt_hor_q = last_pix_s then - cnt_hor_q <= first_pix_s; - else - cnt_hor_q <= cnt_hor_q + 1; - end if; - - -- The vertical counter ----------------------------------------------- - if cnt_vert_q = last_line_s then - cnt_vert_q <= first_line_s; - elsif vert_inc_s then - -- increment when horizontal counter is at trigger position - cnt_vert_q <= cnt_vert_q + 1; - end if; - - -- Horizontal sync ---------------------------------------------------- - if cnt_hor_q = -64 then -- -64 -44 -56 - hsync_n_o <= '0'; - elsif cnt_hor_q = -38 then -- -38 -18 -30 - hsync_n_o <= '1'; - end if; - if cnt_hor_q = -72 then -- -72 -62 -69 - hblank_q <= true; - elsif cnt_hor_q = -13 then -- -14 -4 -11 - hblank_q <= false; - end if; - - -- Vertical sync ------------------------------------------------------ - if ntsc_pal_i = '1' then - if cnt_vert_q = 244 then - vsync_n_o <= '0'; - elsif cnt_vert_q = 247 then - vsync_n_o <= '1'; - end if; - - if cnt_vert_q = 242 then - vblank_q <= true; - elsif cnt_vert_q = first_line_s + 13 then - vblank_q <= false; - end if; - else - if cnt_vert_q = 218 then - vsync_n_o <= '0'; - elsif cnt_vert_q = 221 then - vsync_n_o <= '1'; - end if; - - if cnt_vert_q = 215 then - vblank_q <= true; - elsif cnt_vert_q = first_line_s + 13 then - vblank_q <= false; - end if; - end if; - end if; - end if; - end process counters; - -- - ----------------------------------------------------------------------------- - - - -- comparator for vertical line increment - vert_inc_s <= clk_en_5m37_i and cnt_hor_q = hv_vertical_inc_c; - - ----------------------------------------------------------------------------- - -- Output mapping - ----------------------------------------------------------------------------- - num_pix_o <= cnt_hor_q; - num_line_o <= cnt_vert_q; - vert_inc_o <= vert_inc_s; - blank_o <= hblank_q or vblank_q; - - -- Generate horizontal and vertical counters for VGA/HDMI (in top) - process (reset_i, clock_i) - begin - if reset_i then - cnt_hor_s <= (others => '0'); - cnt_ver_s <= (others => '0'); - elsif rising_edge(clock_i) then - if clk_en_5m37_i then - if cnt_hor_q = -12 then - cnt_hor_s <= (others => '0'); - else - cnt_hor_s <= cnt_hor_s + 1; - end if; - if vert_inc_s then - if cnt_vert_q = -12 then - cnt_ver_s <= (others => '0'); - else - cnt_ver_s <= cnt_ver_s + 1; - end if; - end if; - end if; - end if; - end process; - - cnt_hor_o <= std_logic_vector(cnt_hor_s); - cnt_ver_o <= std_logic_vector(cnt_ver_s); - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_pack-p.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_pack-p.vhd deleted file mode 100644 index 74448868..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_pack-p.vhd +++ /dev/null @@ -1,281 +0,0 @@ -------------------------------------------------------------------------------- --- --- $Id: vdp18_pack-p.vhd,v 1.14 2006/02/22 23:07:05 arnim Exp $ --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package vdp18_pack is - - ----------------------------------------------------------------------------- - -- Subtype for horizontal/vertical counters/positions. - -- - subtype hv_t is signed(0 to 8); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Constants for first and last vertical line of NTSC and PAL mode. - -- - constant hv_first_line_ntsc_c : hv_t := to_signed(-40, hv_t'length); -- 262 - constant hv_last_line_ntsc_c : hv_t := to_signed(221, hv_t'length); - -- - constant hv_first_line_pal_c : hv_t := to_signed(-65, hv_t'length); -- 312 - constant hv_last_line_pal_c : hv_t := to_signed(247, hv_t'length); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Constants for first and last horizontal pixel in text and graphics. - -- - constant hv_first_pix_text_c : hv_t := to_signed(-102, hv_t'length); -- 342 - constant hv_last_pix_text_c : hv_t := to_signed(239, hv_t'length); - -- - constant hv_first_pix_graph_c : hv_t := to_signed(-86, hv_t'length); -- 342 - constant hv_last_pix_graph_c : hv_t := to_signed(255, hv_t'length); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Miscellaneous constants for horizontal phases. - -- - constant hv_vertical_inc_c : hv_t := to_signed(-32, hv_t'length); - constant hv_sprite_start_c : hv_t := to_signed(247, hv_t'length); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Operating modes of the VDP18 core. - -- - type opmode_t is (OPMODE_GRAPH1, OPMODE_GRAPH2, - OPMODE_MULTIC, OPMODE_TEXTM); - -- - constant opmode_graph1_c : std_logic_vector(0 to 2) := "000"; - constant opmode_graph2_c : std_logic_vector(0 to 2) := "001"; - constant opmode_multic_c : std_logic_vector(0 to 2) := "010"; - constant opmode_textm_c : std_logic_vector(0 to 2) := "100"; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Access types. - -- - type access_t is (-- pattern access - -- read Pattern Name Table - AC_PNT, - -- read Pattern Generator Table - AC_PGT, - -- read Pattern Color Table - AC_PCT, - -- sprite access - -- sprite test read (y coordinate) - AC_STST, - -- read Sprite Attribute Table/Y - AC_SATY, - -- read Sprite Attribute Table/X - AC_SATX, - -- read Sprite Attribute Table/N - AC_SATN, - -- read Sprite Attribute Table/C - AC_SATC, - -- read Sprite Pattern Table/high quadrant - AC_SPTH, - -- read Sprite Pattern Table/low quadrant - AC_SPTL, - -- - -- CPU access - AC_CPU, - -- - -- no access at all - AC_NONE - ); - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Function enum_to_vec_f - -- - -- Purpose: - -- Translate access_t enumeration type to std_logic_vector. - -- - function enum_to_vec_f(enum : in access_t) return - std_logic_vector; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Function to_boolean_f - -- - -- Purpose: - -- Converts a std_logic value to boolean. - -- - function to_boolean_f(val : in std_logic) return boolean; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Function to_std_logic_f - -- - -- Purpose: - -- Converts a boolean value to std_logic. - -- - function to_std_logic_f(val : in boolean) return std_logic; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Function mod_6_f - -- - -- Purpose: - -- Calculate the modulo of 6. - -- Only the positive part is considered. - -- - function mod_6_f(val : in hv_t) return hv_t; - -- - ----------------------------------------------------------------------------- - -end vdp18_pack; - - -package body vdp18_pack is - - ----------------------------------------------------------------------------- - -- Function enum_to_vec_f - -- - -- Purpose: - -- Translate access_t enumeration type to std_logic_vector. - -- - function enum_to_vec_f(enum : in access_t) return - std_logic_vector is - variable result_v : std_logic_vector(3 downto 0); - begin - case enum is - when AC_NONE => - result_v := "0000"; - when AC_PNT => - result_v := "0001"; - when AC_PGT => - result_v := "0010"; - when AC_PCT => - result_v := "0011"; - when AC_STST => - result_v := "0100"; - when AC_SATY => - result_v := "0101"; - when AC_SATX => - result_v := "0110"; - when AC_SATN => - result_v := "0111"; - when AC_SATC => - result_v := "1000"; - when AC_SPTL => - result_v := "1001"; - when AC_SPTH => - result_v := "1010"; - when AC_CPU => - result_v := "1111"; - when others => - result_v := "UUUU"; - end case; - - return result_v; - end; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Function to_boolean_f - -- - -- Purpose: - -- Converts a std_logic value to boolean. - -- - function to_boolean_f(val : in std_logic) return boolean is - variable result_v : boolean; - begin - case to_X01(val) is - when '1' => - result_v := true; - when '0' => - result_v := false; - when others => - result_v := false; - end case; - - return result_v; - end; - -- - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- Function to_std_logic_f - -- - -- Purpose: - -- Converts a boolean value to std_logic. - -- - function to_std_logic_f(val : in boolean) return std_logic is - variable result_v : std_logic; - begin - case val is - when true => - result_v := '1'; - when false => - result_v := '0'; - end case; - - return result_v; - end; - -- - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- Function mod_6_f - -- - -- Purpose: - -- Calculate the modulo of 6. - -- Only the positive part is considered. - -- - function mod_6_f(val : in hv_t) return hv_t is - variable mod_v : natural; - variable result_v : hv_t; - begin - if val(0) = '0' then - result_v := (others => '0'); - mod_v := 0; - for idx in 0 to 255 loop - if val = idx then - result_v := to_signed(mod_v, hv_t'length); - end if; - - if mod_v < 5 then - mod_v := mod_v + 1; - else - mod_v := 0; - end if; - end loop; - else - result_v := (others => '-'); - end if; - - return result_v; - end; - -- - ----------------------------------------------------------------------------- - -end vdp18_pack; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_pattern.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_pattern.vhd deleted file mode 100644 index 08b22092..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_pattern.vhd +++ /dev/null @@ -1,233 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A. --- --- $Id: vdp18_pattern.vhd,v 1.8 2006/06/18 10:47:06 arnim Exp $ --- --- Pattern Generation Controller --- -------------------------------------------------------------------------------- --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.vdp18_pack.opmode_t; -use work.vdp18_pack.access_t; -use work.vdp18_pack.hv_t; - -entity vdp18_pattern is - - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - clk_en_acc_i : in boolean; - reset_i : in boolean; - opmode_i : in opmode_t; - access_type_i : in access_t; - num_line_i : in hv_t; - vram_d_i : in std_logic_vector(0 to 7); - vert_inc_i : in boolean; - vsync_n_i : in std_logic; - reg_col1_i : in std_logic_vector(0 to 3); - reg_col0_i : in std_logic_vector(0 to 3); - pat_table_o : out std_logic_vector(0 to 9); - pat_name_o : out std_logic_vector(0 to 7); - pat_col_o : out std_logic_vector(0 to 3) - ); - -end vdp18_pattern; - - -library ieee; -use ieee.numeric_std.all; - -use work.vdp18_pack.all; - -architecture rtl of vdp18_pattern is - - signal pat_cnt_q : unsigned(0 to 9); - signal pat_name_q, - pat_tmp_q, - pat_shift_q, - pat_col_q : std_logic_vector(0 to 7); - -begin - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the sequential elements: - -- * pattern shift register - -- * pattern color register - -- * pattern counter - -- - seq: process (clock_i, reset_i) - begin - if reset_i then - pat_cnt_q <= (others => '0'); - pat_name_q <= (others => '0'); - pat_tmp_q <= (others => '0'); - pat_shift_q <= (others => '0'); - pat_col_q <= (others => '0'); - - elsif clock_i'event and clock_i = '1' then - if clk_en_5m37_i then - -- shift pattern with every pixel clock - pat_shift_q(0 to 6) <= pat_shift_q(1 to 7); - end if; - - if clk_en_acc_i then - -- determine register update based on current access type ------------- - case access_type_i is - when AC_PNT => - -- store pattern name - pat_name_q <= vram_d_i; - -- increment pattern counter - pat_cnt_q <= pat_cnt_q + 1; - - when AC_PCT => - -- store pattern color in temporary register - pat_tmp_q <= vram_d_i; - - when AC_PGT => - if opmode_i = OPMODE_MULTIC then - -- set shift register to constant value - -- this value generates 4 bits of color1 - -- followed by 4 bits of color0 - pat_shift_q <= "11110000"; - -- set pattern color from pattern generator memory - pat_col_q <= vram_d_i; - else - -- all other modes: - -- store pattern line in shift register - pat_shift_q <= vram_d_i; - -- move pattern color from temporary register to color register - pat_col_q <= pat_tmp_q; - end if; - - when others => - null; - - end case; - - end if; - - if vert_inc_i then - -- redo patterns of if there are more lines inside this pattern - if num_line_i(0) = '0' then - case opmode_i is - when OPMODE_TEXTM => - if num_line_i(6 to 8) /= "111" then - pat_cnt_q <= pat_cnt_q - 40; - end if; - - when OPMODE_GRAPH1 | - OPMODE_GRAPH2 | - OPMODE_MULTIC => - if num_line_i(6 to 8) /= "111" then - pat_cnt_q <= pat_cnt_q - 32; - end if; - end case; - end if; - end if; - - if vsync_n_i = '0' then - -- reset pattern counter at end of active display area - pat_cnt_q <= (others => '0'); - end if; - - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process col_gen - -- - -- Purpose: - -- Generates the color of the current pattern pixel. - -- - col_gen: process (opmode_i, - pat_shift_q, - pat_col_q, - reg_col1_i, - reg_col0_i) - variable pix_v : std_logic; - begin - -- default assignment - pat_col_o <= "0000"; - pix_v := pat_shift_q(0); - - case opmode_i is - -- Text Mode ------------------------------------------------------------ - when OPMODE_TEXTM => - if pix_v = '1' then - pat_col_o <= reg_col1_i; - else - pat_col_o <= reg_col0_i; - end if; - - -- Graphics I, II and Multicolor Mode ----------------------------------- - when OPMODE_GRAPH1 | - OPMODE_GRAPH2 | - OPMODE_MULTIC => - if pix_v = '1' then - pat_col_o <= pat_col_q(0 to 3); - else - pat_col_o <= pat_col_q(4 to 7); - end if; - - when others => - null; - - end case; - end process col_gen; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output Mapping - ----------------------------------------------------------------------------- - pat_table_o <= std_logic_vector(pat_cnt_q); - pat_name_o <= pat_name_q; - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_sprite.vhd b/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_sprite.vhd deleted file mode 100644 index d198f310..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/vdp18/vdp18_sprite.vhd +++ /dev/null @@ -1,441 +0,0 @@ -------------------------------------------------------------------------------- --- --- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A. --- --- $Id: vdp18_sprite.vhd,v 1.11 2006/06/18 10:47:06 arnim Exp $ --- --- Sprite Generation Controller --- --- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -use work.vdp18_pack.hv_t; -use work.vdp18_pack.access_t; - -entity vdp18_sprite is - - port ( - clock_i : in std_logic; - clk_en_5m37_i : in boolean; - clk_en_acc_i : in boolean; - reset_i : in boolean; - access_type_i : in access_t; - num_pix_i : in hv_t; - num_line_i : in hv_t; - vram_d_i : in std_logic_vector(0 to 7); - vert_inc_i : in boolean; - reg_size1_i : in boolean; - reg_mag1_i : in boolean; - spr_5th_o : out boolean; - spr_5th_num_o : out std_logic_vector(0 to 4); - stop_sprite_o : out boolean; - spr_coll_o : out boolean; - spr_num_o : out std_logic_vector(0 to 4); - spr_line_o : out std_logic_vector(0 to 3); - spr_name_o : out std_logic_vector(0 to 7); - spr0_col_o : out std_logic_vector(0 to 3); - spr1_col_o : out std_logic_vector(0 to 3); - spr2_col_o : out std_logic_vector(0 to 3); - spr3_col_o : out std_logic_vector(0 to 3) - ); - -end vdp18_sprite; - - -library ieee; -use ieee.numeric_std.all; - -use work.vdp18_pack.all; - -architecture rtl of vdp18_sprite is - - subtype sprite_number_t is unsigned(0 to 4); - type sprite_numbers_t is array (natural range 0 to 3) of sprite_number_t; - signal sprite_numbers_q : sprite_numbers_t; - - signal sprite_num_q : unsigned(0 to 4); - signal sprite_idx_q : unsigned(0 to 2); - signal sprite_name_q : std_logic_vector(0 to 7); - - subtype sprite_x_pos_t is unsigned(0 to 7); - type sprite_xpos_t is array (natural range 0 to 3) of sprite_x_pos_t; - signal sprite_xpos_q : sprite_xpos_t; - type sprite_ec_t is array (natural range 0 to 3) of std_logic; - signal sprite_ec_q : sprite_ec_t; - type sprite_xtog_t is array (natural range 0 to 3) of std_logic; - signal sprite_xtog_q : sprite_xtog_t; - - subtype sprite_col_t is std_logic_vector(0 to 3); - type sprite_cols_t is array (natural range 0 to 3) of sprite_col_t; - signal sprite_cols_q : sprite_cols_t; - - subtype sprite_pat_t is std_logic_vector(0 to 15); - type sprite_pats_t is array (natural range 0 to 3) of sprite_pat_t; - signal sprite_pats_q : sprite_pats_t; - - signal sprite_line_s, - sprite_line_q : std_logic_vector(0 to 3); - signal sprite_visible_s : boolean; - -begin - - ----------------------------------------------------------------------------- - -- Process seq - -- - -- Purpose: - -- Implements the sequential elements. - -- - seq: process (clock_i, reset_i) - variable sprite_idx_inc_v, - sprite_idx_dec_v : unsigned(sprite_idx_q'range); - variable sprite_idx_v : natural range 0 to 3; - begin - if reset_i then - sprite_numbers_q <= (others => (others => '0')); - sprite_num_q <= (others => '0'); - sprite_idx_q <= (others => '0'); - sprite_line_q <= (others => '0'); - sprite_name_q <= (others => '0'); - sprite_cols_q <= (others => (others => '0')); - sprite_xpos_q <= (others => (others => '0')); - sprite_ec_q <= (others => '0'); - sprite_xtog_q <= (others => '0'); - sprite_pats_q <= (others => (others => '0')); - - elsif clock_i'event and clock_i = '1' then - -- sprite index will be incremented during sprite tests - sprite_idx_inc_v := sprite_idx_q + 1; - -- sprite index will be decremented at end of sprite pattern data - sprite_idx_dec_v := sprite_idx_q - 1; - -- just save typing - sprite_idx_v := to_integer(sprite_idx_q(1 to 2)); - - if clk_en_5m37_i then - -- pre-decrement index counter when sprite reading starts - if num_pix_i = hv_sprite_start_c and sprite_idx_q > 0 then - sprite_idx_q <= sprite_idx_dec_v; - end if; - - ----------------------------------------------------------------------- - -- X position counters - ----------------------------------------------------------------------- - for idx in 0 to 3 loop - if num_pix_i(0) = '0' or - (sprite_ec_q(idx) = '1' and num_pix_i(0 to 3) = "1111") then - if sprite_xpos_q(idx) /= 0 then - -- decrement counter until 0 - sprite_xpos_q(idx) <= sprite_xpos_q(idx) - 1; - else - -- toggle magnification flag - sprite_xtog_q(idx) <= not sprite_xtog_q(idx); - end if; - end if; - end loop; - - ----------------------------------------------------------------------- - -- Sprite pattern shift registers - ----------------------------------------------------------------------- - for idx in 0 to 3 loop - if sprite_xpos_q(idx) = 0 then -- x counter elapsed - -- decide when to shift pattern information - -- case 1: pixel number is >= 0 - -- => active display area - -- case 2: early clock bit is set and pixel number is between - -- -32 and 0 - -- shift if - -- magnification not enbled - -- or - -- magnification enabled and toggle marker true - if (num_pix_i(0) = '0' or - (sprite_ec_q(idx) = '1' and num_pix_i(0 to 3) = "1111")) and - (sprite_xtog_q(idx) = '1' or not reg_mag1_i) then - -- - -- shift pattern left and fill vacated position with - -- transparent information - sprite_pats_q(idx)(0 to 14) <= sprite_pats_q(idx)(1 to 15); - sprite_pats_q(idx)(15) <= '0'; - end if; - end if; - - -- clear pattern at end of visible display - -- this removes "left-overs" when a sprite overlaps the right border - if num_pix_i = "011111111" then - sprite_pats_q(idx) <= (others => '0'); - end if; - end loop; - end if; - - - if vert_inc_i then - -- reset sprite num counter and sprite index counter - sprite_num_q <= (others => '0'); - sprite_idx_q <= (others => '0'); - - elsif clk_en_acc_i then - case access_type_i is - when AC_STST => - -- increment sprite number counter - sprite_num_q <= sprite_num_q + 1; - - if sprite_visible_s then - if sprite_idx_q < 4 then - -- store sprite number - sprite_numbers_q(sprite_idx_v) <= sprite_num_q; - -- and increment index counter - sprite_idx_q <= sprite_idx_inc_v; - end if; - end if; - - when AC_SATY => - -- store sprite line - sprite_line_q <= sprite_line_s; - - when AC_SATX => - -- save x position - sprite_xpos_q(sprite_idx_v) <= unsigned(vram_d_i); - -- reset toggle flag for magnified sprites - sprite_xtog_q(sprite_idx_v) <= '0'; - - when AC_SATN => - -- save sprite name - sprite_name_q <= vram_d_i; - - when AC_SATC => - -- save sprite color - sprite_cols_q(sprite_idx_v) <= vram_d_i(4 to 7); - -- and save early clock bit - sprite_ec_q(sprite_idx_v) <= vram_d_i(0); - - when AC_SPTH => - -- save upper pattern data - sprite_pats_q(sprite_idx_v)(0 to 7) - <= vram_d_i; - -- set lower part to transparent - sprite_pats_q(sprite_idx_v)(8 to 15) - <= (others => '0'); - - if not reg_size1_i then - -- decrement index counter in 8-bit mode - sprite_idx_q <= sprite_idx_dec_v; - end if; - - when AC_SPTL => - -- save lower pattern data - sprite_pats_q(sprite_idx_v)(8 to 15) <= vram_d_i; - - -- always decrement index counter - sprite_idx_q <= sprite_idx_dec_v; - - when others => - null; - end case; - - end if; - - end if; - end process seq; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process calc_vert - -- - -- Purpose: - -- Calculates the displayed line of the sprite and determines whether it - -- is visible on the current line or not. - -- - calc_vert: process (clk_en_acc_i, access_type_i, - vram_d_i, - num_pix_i, num_line_i, - sprite_num_q, sprite_idx_q, - reg_size1_i, reg_mag1_i) - variable sprite_line_v : signed(0 to 8); - variable vram_d_v : signed(0 to 8); - begin - -- default assignments - sprite_visible_s <= false; - stop_sprite_o <= false; - - vram_d_v := resize(signed(vram_d_i), 9); - -- determine if y information from VRAM should be treated - -- as a signed or unsigned number - if vram_d_v < -31 then - -- treat as unsigned number - vram_d_v(0) := '0'; - end if; - - sprite_line_v := num_line_i - vram_d_v; - if reg_mag1_i then - -- unmagnify line number - sprite_line_v := shift_right(sprite_line_v, 1); - end if; - - -- check result bounds - if sprite_line_v >= 0 then - if reg_size1_i then - -- double sized sprite: 16 data lines - if sprite_line_v < 16 then - sprite_visible_s <= true; - end if; - else - -- standard sized sprite: 8 data lines - if sprite_line_v < 8 then - sprite_visible_s <= true; - end if; - end if; - end if; - - -- finally: line number of current sprite - sprite_line_s <= std_logic_vector(sprite_line_v(5 to 8)); - - if clk_en_acc_i then - -- determine when to stop sprite scanning - if access_type_i = AC_STST then - if vram_d_v = 208 then - -- stop upon Y position 208 - stop_sprite_o <= true; - end if; - - if sprite_idx_q = 4 then - -- stop when all sprite positions have been vacated - stop_sprite_o <= true; - end if; - - if sprite_num_q = 31 then - -- stop when all sprites have been read - stop_sprite_o <= true; - end if; - end if; - - -- stop sprite reading when last active sprite has been processed - if sprite_idx_q = 0 and - ( access_type_i = AC_SPTL or - (access_type_i = AC_SPTH and not reg_size1_i)) then - stop_sprite_o <= true; - end if; - end if; - - -- stop sprite reading when no sprite is active on current line - if num_pix_i = hv_sprite_start_c and sprite_idx_q = 0 then - stop_sprite_o <= true; - end if; - end process calc_vert; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process fifth - -- - -- Purpose: - -- Detects the fifth sprite. - -- - fifth: process (clk_en_acc_i, access_type_i, - sprite_visible_s, - sprite_idx_q, - sprite_num_q) - begin - -- default assignments - spr_5th_o <= false; - spr_5th_num_o <= (others => '0'); - - if clk_en_acc_i and access_type_i = AC_STST then - if sprite_visible_s and sprite_idx_q = 4 then - spr_5th_o <= true; - spr_5th_num_o <= std_logic_vector(sprite_num_q); - end if; - end if; - end process fifth; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Process col_mux - -- - -- Purpose: - -- Implements the color multiplexers. - -- - col_mux: process (sprite_cols_q, - sprite_pats_q, - sprite_xpos_q) - variable num_spr_pix_v : unsigned(0 to 2); - begin - -- default assignments - -- sprite colors are set to transparent - spr0_col_o <= (others => '0'); - spr1_col_o <= (others => '0'); - spr2_col_o <= (others => '0'); - spr3_col_o <= (others => '0'); - num_spr_pix_v := (others => '0'); - - if sprite_xpos_q(0) = 0 and sprite_pats_q(0)(0) = '1' then - spr0_col_o <= sprite_cols_q(0); - num_spr_pix_v := num_spr_pix_v + 1; - end if; - if sprite_xpos_q(1) = 0 and sprite_pats_q(1)(0) = '1' then - spr1_col_o <= sprite_cols_q(1); - num_spr_pix_v := num_spr_pix_v + 1; - end if; - if sprite_xpos_q(2) = 0 and sprite_pats_q(2)(0) = '1' then - spr2_col_o <= sprite_cols_q(2); - num_spr_pix_v := num_spr_pix_v + 1; - end if; - if sprite_xpos_q(3) = 0 and sprite_pats_q(3)(0) = '1' then - spr3_col_o <= sprite_cols_q(3); - num_spr_pix_v := num_spr_pix_v + 1; - end if; - - spr_coll_o <= num_spr_pix_v > 1; - end process col_mux; - -- - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- Output mapping - ----------------------------------------------------------------------------- - spr_num_o <= std_logic_vector(sprite_num_q) - when access_type_i = AC_STST else - std_logic_vector(sprite_numbers_q(to_integer(sprite_idx_q(1 to 2)))); - spr_line_o <= sprite_line_q; - spr_name_o <= sprite_name_q; - -end rtl; diff --git a/Console_MiST/Coleco - Vision_MiST/rtl/video_mixer.sv b/Console_MiST/Coleco - Vision_MiST/rtl/video_mixer.sv deleted file mode 100644 index 04cfd4ba..00000000 --- a/Console_MiST/Coleco - Vision_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,242 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/Release/gb.rbf b/Console_MiST/Nintendo - Gameboy_MiST/Release/gb.rbf deleted file mode 100644 index ae8fab57..00000000 Binary files a/Console_MiST/Nintendo - Gameboy_MiST/Release/gb.rbf and /dev/null differ diff --git a/Console_MiST/Nintendo - Gameboy_MiST/Snapshot/gb1.rbf b/Console_MiST/Nintendo - Gameboy_MiST/Snapshot/gb1.rbf deleted file mode 100644 index cdc72cf1..00000000 Binary files a/Console_MiST/Nintendo - Gameboy_MiST/Snapshot/gb1.rbf and /dev/null differ diff --git a/Console_MiST/Nintendo - Gameboy_MiST/Snapshot/gb2.rbf b/Console_MiST/Nintendo - Gameboy_MiST/Snapshot/gb2.rbf deleted file mode 100644 index 5097ab3c..00000000 Binary files a/Console_MiST/Nintendo - Gameboy_MiST/Snapshot/gb2.rbf and /dev/null differ diff --git a/Console_MiST/Nintendo - Gameboy_MiST/clean.bat b/Console_MiST/Nintendo - Gameboy_MiST/clean.bat deleted file mode 100644 index b3b7c3b5..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/clean.bat +++ /dev/null @@ -1,37 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del /s new_rtl_netlist -del /s old_rtl_netlist - -pause diff --git a/Console_MiST/Nintendo - Gameboy_MiST/gb.qpf b/Console_MiST/Nintendo - Gameboy_MiST/gb.qpf deleted file mode 100644 index ed107778..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/gb.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2010 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 10.1 Build 153 11/29/2010 SJ Full Version -# Date created = 11:11:11 June 13, 2011 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "10.1" -DATE = "11:11:11 June 13, 2011" - -# Revisions - -PROJECT_REVISION = "gb" diff --git a/Console_MiST/Nintendo - Gameboy_MiST/gb.qsf b/Console_MiST/Nintendo - Gameboy_MiST/gb.qsf deleted file mode 100644 index 4e9e909e..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/gb.qsf +++ /dev/null @@ -1,191 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2011 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 11.0 Build 157 04/27/2011 SJ Full Version -# Date created = 17:14:01 April 10, 2012 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# led_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name TOP_LEVEL_ENTITY gb_mist -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files - -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:14:01 APRIL 10, 2012" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" - -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_22 -to CLOCK_50[0] -set_location_assignment PIN_23 -to CLOCK_50[1] -set_location_assignment PIN_128 -to CLOCK_32[0] -set_location_assignment PIN_129 -to CLOCK_32[1] -set_location_assignment PIN_54 -to CLOCK_27[0] -set_location_assignment PIN_55 -to CLOCK_27[1] -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_46 -to UART_TX -set_location_assignment PIN_31 -to UART_RX -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_90 -to SPI_SS4 -set_location_assignment PIN_13 -to CONF_DATA0 - -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK - - -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name FITTER_EFFORT "FAST FIT" -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* -set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 -set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name SYSTEMVERILOG_FILE rtl/gb_mist.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/gb.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/lcd.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprites.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprite_sort.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprite.sv -set_global_assignment -name VHDL_FILE rtl/gbc_snd.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/timer.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/zpram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/vram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/iram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv -set_global_assignment -name VERILOG_FILE rtl/pll.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/data_io.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv -set_global_assignment -name VHDL_FILE rtl/BROM.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80_Reg.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80_Pack.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80_MCode.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80_ALU.vhd -set_global_assignment -name VHDL_FILE rtl/t80/T80.vhd -set_global_assignment -name VHDL_FILE rtl/t80/GBse.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Console_MiST/Nintendo - Gameboy_MiST/readme.txt b/Console_MiST/Nintendo - Gameboy_MiST/readme.txt deleted file mode 100644 index f8c9535e..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/readme.txt +++ /dev/null @@ -1,43 +0,0 @@ ---------------------------------------------------------------------------------- --- --- Gameboy Core for MiST by Till Harbaum --- Changed by Gehstock --- 19 December 2017 --- ---------------------------------------------------------------------------------- - --- This is source code of a gameboy implementation for the MIST. - - - --- It's based on the [t80](http://opencores.com/project,t80) CPU core. - --- A minor -fix was needed for the "LD ($FF00+C)" instruction. - - - --- The audio implementation has been taken from the PACE framework. - --- The -original file is available in the [pacedev svn] --- (https://svn.pacedev.net/repos/pace/sw/src/component/sound/gb/gbc_snd.vhd). - - ---------------------------------------------------------------------------------- --- --- --- Keyboard inputs : --- --- ESC: : Start --- TAB: : Select --- SPACE : Button A --- LALT : Button B --- ARROW KEYS : Movements --- --- Joystick support. --- ---------------------------------------------------------------------------------- - -ToDo: Mappers - diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/BROM.vhd b/Console_MiST/Nintendo - Gameboy_MiST/rtl/BROM.vhd deleted file mode 100644 index ae9ac80b..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/BROM.vhd +++ /dev/null @@ -1,56 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all,ieee.numeric_std.all; - -entity BROM is -port ( - clk : in std_logic; - addr : in std_logic_vector(7 downto 0); - data : out std_logic_vector(7 downto 0) -); -end entity; - -architecture prom of BROM is - type ROM_ARRAY is array(0 to 255) of std_logic_vector(7 downto 0); - signal ROM : ROM_ARRAY := ( - x"31",x"FE",x"FF",x"AF",x"21",x"FF",x"9F",x"32", -- 0x0000 - x"CB",x"7C",x"20",x"FB",x"21",x"26",x"FF",x"0E", -- 0x0008 - x"11",x"3E",x"80",x"32",x"E2",x"0C",x"3E",x"F3", -- 0x0010 - x"E2",x"32",x"3E",x"77",x"77",x"3E",x"FC",x"E0", -- 0x0018 - x"47",x"F0",x"50",x"FE",x"42",x"28",x"75",x"11", -- 0x0020 - x"04",x"01",x"21",x"10",x"80",x"1A",x"4F",x"CD", -- 0x0028 - x"A0",x"00",x"CD",x"A0",x"00",x"13",x"7B",x"FE", -- 0x0030 - x"34",x"20",x"F2",x"11",x"B2",x"00",x"06",x"08", -- 0x0038 - x"1A",x"22",x"22",x"13",x"05",x"20",x"F9",x"3E", -- 0x0040 - x"19",x"EA",x"10",x"99",x"21",x"2F",x"99",x"0E", -- 0x0048 - x"0C",x"3D",x"28",x"08",x"32",x"0D",x"20",x"F9", -- 0x0050 - x"2E",x"0F",x"18",x"F3",x"67",x"3E",x"64",x"57", -- 0x0058 - x"E0",x"42",x"3E",x"91",x"E0",x"40",x"04",x"1E", -- 0x0060 - x"02",x"0E",x"0C",x"F0",x"44",x"FE",x"90",x"20", -- 0x0068 - x"FA",x"0D",x"20",x"F7",x"1D",x"20",x"F2",x"0E", -- 0x0070 - x"13",x"24",x"7C",x"1E",x"83",x"FE",x"62",x"28", -- 0x0078 - x"06",x"1E",x"C1",x"FE",x"64",x"20",x"06",x"7B", -- 0x0080 - x"E2",x"0C",x"3E",x"87",x"E2",x"F0",x"42",x"90", -- 0x0088 - x"E0",x"42",x"15",x"20",x"D2",x"05",x"20",x"64", -- 0x0090 - x"16",x"20",x"18",x"CB",x"E0",x"40",x"18",x"5C", -- 0x0098 - x"06",x"04",x"C5",x"CB",x"11",x"17",x"C1",x"CB", -- 0x00A0 - x"11",x"17",x"05",x"20",x"F5",x"22",x"22",x"22", -- 0x00A8 - x"22",x"C9",x"3C",x"42",x"A5",x"81",x"A5",x"99", -- 0x00B0 - x"42",x"3C",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00B8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00C0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00C8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00D0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00D8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00E0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00E8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00F0 - x"FF",x"FF",x"FF",x"FF",x"3E",x"01",x"E0",x"50" -- 0x00F8 - ); - -begin -process(clk) -begin - if rising_edge(clk) then - data <= ROM (to_integer(unsigned(addr))); - end if; -end process; -end architecture; diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/build_id.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/build_id.sv deleted file mode 100644 index 1d53a3f2..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/build_id.sv +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "171221" -`define BUILD_TIME "172231" diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/data_io.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/data_io.sv deleted file mode 100644 index c1a3ffca..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/data_io.sv +++ /dev/null @@ -1,118 +0,0 @@ -// -// data_io.v -// -// io controller writable ram for the MiST board -// https://github.com/mist-devel -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module data_io ( - // io controller spi interface - input sck, - input ss, - input sdi, - - output downloading, // signal indicating an active download - output reg [4:0] index, // menu index used to upload the file - - // external ram interface - input clk, - output reg wr, - output reg [23:0] addr, - output reg [15:0] data -); - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg [14:0] sbuf; -reg [7:0] cmd; -reg [4:0] cnt; -reg rclk; - -reg [23:0] laddr; -reg [15:0] ldata; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -assign downloading = downloading_reg; -reg downloading_reg = 1'b0; - -// data_io has its own SPI interface to the io controller -always@(posedge sck, posedge ss) begin - if(ss == 1'b1) - cnt <= 5'd0; - else begin - rclk <= 1'b0; - - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 23) - sbuf <= { sbuf[13:0], sdi}; - - // count 0-7 8-15 16-23 8-15 16-23 ... - if(cnt < 23) cnt <= cnt + 4'd1; - else cnt <= 4'd8; - - // finished command byte - if(cnt == 7) - cmd <= {sbuf[6:0], sdi}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(sdi) begin - // download rom to address 0 - laddr <= 24'h0 - 24'd1; - downloading_reg <= 1'b1; - end else - downloading_reg <= 1'b0; - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 23)) begin - ldata <= {sbuf, sdi}; - laddr <= laddr + 24'd1; - rclk <= 1'b1; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) - index <= {sbuf[3:0], sdi}; - end -end - -reg rclkD, rclkD2; -always@(posedge clk) begin - // bring all signals from spi clock domain into local clock domain - rclkD <= rclk; - rclkD2 <= rclkD; - wr <= 1'b0; - - if(rclkD && !rclkD2) begin - addr <= laddr; - data <= ldata; - wr <= 1'b1; - end -end - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/gb.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/gb.sv deleted file mode 100644 index e31a9936..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/gb.sv +++ /dev/null @@ -1,359 +0,0 @@ -// -// gb.v -// -// Gameboy for the MIST board https://github.com/mist-devel -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module gb ( - input reset, - input clk, - - input fast_boot, - input [7:0] joystick, - - // cartridge interface - // can adress up to 1MB ROM - output [15:0] cart_addr, - output cart_rd, - output cart_wr, - input [7:0] cart_do, - output [7:0] cart_di, - - // audio - output [15:0] audio_l, - output [15:0] audio_r, - - // lcd interface - output lcd_clkena, - output [1:0] lcd_data, - output [1:0] lcd_mode, - output lcd_on -); - -// include cpu -wire [15:0] cpu_addr; -wire [7:0] cpu_do; - -wire sel_timer = (cpu_addr[15:4] == 12'hff0) && (cpu_addr[3:2] == 2'b01); -wire sel_video_reg = cpu_addr[15:4] == 12'hff4; -wire sel_video_oam = cpu_addr[15:8] == 8'hfe; -wire sel_joy = cpu_addr == 16'hff00; // joystick controller -wire sel_rom = !cpu_addr[15]; // lower 32k are rom -wire sel_cram = cpu_addr[15:13] == 3'b101; // 8k cart ram at $a000 -wire sel_vram = cpu_addr[15:13] == 3'b100; // 8k video ram at $8000 -wire sel_ie = cpu_addr == 16'hffff; // interupt enable -wire sel_if = cpu_addr == 16'hff0f; // interupt flag -wire sel_iram = (cpu_addr[15:14] == 2'b11) && (cpu_addr[15:8] != 8'hff); // 8k internal ram at $c000 -wire sel_zpram = (cpu_addr[15:7] == 9'b111111111) && // 127 bytes zero pageram at $ff80 - (cpu_addr != 16'hffff); -wire sel_audio = (cpu_addr[15:8] == 8'hff) && // audio reg ff10 - ff3f - ((cpu_addr[7:5] == 3'b001) || (cpu_addr[7:4] == 4'b0001)); - -// the boot roms sees a special $42 flag in $ff50 if it's supposed to to a fast boot -wire sel_fast = fast_boot && cpu_addr == 16'hff50 && boot_rom_enabled; - -// http://gameboy.mongenel.com/dmg/asmmemmap.html -wire [7:0] cpu_di = - irq_ack?irq_vec: - sel_fast?8'h42: // fast boot flag - sel_joy?joy_do: // joystick register - sel_timer?timer_do: // timer registers - sel_video_reg?video_do: // video registers - sel_video_oam?video_do: // video object attribute memory - sel_audio?audio_do: // audio registers - sel_rom?rom_do: // boot rom + cartridge rom - sel_cram?rom_do: // cartridge ram - sel_vram?vram_do: // vram - sel_zpram?zpram_do: // zero page ram - sel_iram?iram_do: // internal ram - sel_ie?{3'b000, ie_r}: // interrupt enable register - sel_if?{3'b000, if_r}: // interrupt flag register - 8'hff; - -wire cpu_wr_n; -wire cpu_rd_n; -wire cpu_iorq_n; -wire cpu_m1_n; -wire cpu_mreq_n; - -GBse cpu ( - .RESET_n ( !reset ), - .CLK_n ( clk ), - .CLKEN ( 1'b1 ), - .WAIT_n ( 1'b1 ), - .INT_n ( irq_n ), - .NMI_n ( 1'b1 ), - .BUSRQ_n ( 1'b1 ), - .M1_n ( cpu_m1_n ), - .MREQ_n ( cpu_mreq_n ), - .IORQ_n ( cpu_iorq_n ), - .RD_n ( cpu_rd_n ), - .WR_n ( cpu_wr_n ), - .RFSH_n ( ), - .HALT_n ( ), - .BUSAK_n ( ), - .A ( cpu_addr ), - .DI ( cpu_di ), - .DO ( cpu_do ) -); - -// -------------------------------------------------------------------- -// ------------------------------ audio ------------------------------- -// -------------------------------------------------------------------- - -wire audio_rd = !cpu_rd_n && sel_audio; -wire audio_wr = !cpu_wr_n && sel_audio; -wire [7:0] audio_do; - -gbc_snd audio ( - .clk ( clk ), - .reset ( reset ), - - .s1_read ( audio_rd ), - .s1_write ( audio_wr ), - .s1_addr ( cpu_addr[5:0] ), - .s1_readdata ( audio_do ), - .s1_writedata ( cpu_do ), - - .snd_left ( audio_l ), - .snd_right ( audio_r ) -); - -// -------------------------------------------------------------------- -// ------------------------------ inputs ------------------------------ -// -------------------------------------------------------------------- - -wire [3:0] joy_p4 = { !joystick[2], !joystick[3], !joystick[1], !joystick[0] }; -wire [3:0] joy_p5 = { !joystick[7], !joystick[6], !joystick[5], !joystick[4] }; -reg [1:0] p54; - -always @(posedge clk) begin - if(reset) - p54 <= 2'b11; - else if(sel_joy && !cpu_wr_n) - p54 <= cpu_do[5:4]; -end - -wire [7:0] joy_do = { 2'b11, p54, - ((!p54[0])?joy_p4:4'hf) & ((!p54[1])?joy_p5:4'hf) }; - -// -------------------------------------------------------------------- -// ---------------------------- interrupts ---------------------------- -// -------------------------------------------------------------------- - -// interrupt flags are set when the event happens or when the cpu writes -// the register to 1. The "highest" one active is cleared when the cpu -// runs an interrupt ack cycle or when it writes a 0 to the register - -wire irq_ack = !cpu_iorq_n && !cpu_m1_n; - -// latch irq vector at the begin of the irq ack -reg [7:0] irq_vec; -always @(posedge irq_ack) - irq_vec <= - if_r[0]?8'h40: // vsync - if_r[1]?8'h48: // lcdc - if_r[2]?8'h50: // timer - if_r[3]?8'h58: // serial - if_r[4]?8'h60: // input - 8'h55; - -wire vs = (lcd_mode == 2'b01); -reg vsD, vsD2; -reg [3:0] inputD, inputD2; - -// irq is low when an enable irq is active -wire irq_n = !(ie_r & if_r); - -reg [4:0] if_r; -reg [4:0] ie_r; // writing $ffff sets the irq enable mask -always @(posedge clk) begin - if(reset) begin - ie_r <= 5'h00; - if_r <= 5'h00; - end - - // rising edge on vs - vsD <= vs; - vsD2 <= vsD; - if(vsD && !vsD2) if_r[0] <= 1'b1; - - // video irq already is a 1 clock event - if(video_irq) if_r[1] <= 1'b1; - - // timer_irq already is a 1 clock event - if(timer_irq) if_r[2] <= 1'b1; - - // falling edge on any input line P10..P13 - inputD <= joy_p4 | joy_p5; - inputD2 <= inputD; - if(~inputD & inputD2) if_r[4] <= 1'b1; - - // cpu acknowledges irq. this clears the active irq with hte - // highest priority - if(irq_ack) begin - if(if_r[0] && ie_r[0]) if_r[0] <= 1'b0; - else if(if_r[1] && ie_r[1]) if_r[1] <= 1'b0; - else if(if_r[2] && ie_r[2]) if_r[2] <= 1'b0; - else if(if_r[3] && ie_r[3]) if_r[3] <= 1'b0; - else if(if_r[4] && ie_r[4]) if_r[4] <= 1'b0; - end - - // cpu writes interrupt enable register - if(sel_ie && !cpu_wr_n) - ie_r <= cpu_do[4:0]; - - // cpu writes interrupt flag register - if(sel_if && !cpu_wr_n) - if_r <= cpu_do[4:0]; -end - -// -------------------------------------------------------------------- -// ------------------------------ timer ------------------------------- -// -------------------------------------------------------------------- - -wire timer_irq; -wire [7:0] timer_do; -timer timer ( - .reset ( reset ), - .clk ( clk ), - - .irq ( timer_irq ), - - .cpu_sel ( sel_timer ), - .cpu_addr ( cpu_addr[1:0] ), - .cpu_wr ( !cpu_wr_n ), - .cpu_di ( cpu_do ), - .cpu_do ( timer_do ) -); - -// -------------------------------------------------------------------- -// ------------------------------ video ------------------------------- -// -------------------------------------------------------------------- - -// cpu tries to read or write the lcd controller registers -wire video_irq; -wire [7:0] video_do; -wire [12:0] video_addr; -wire [15:0] dma_addr; -wire video_rd, dma_rd; -wire [7:0] dma_data = (dma_addr[15:14]==2'b11)?iram_do:cart_do; - -video video ( - .reset ( reset ), - .clk ( clk ), - - .irq ( video_irq ), - - .cpu_sel_reg ( sel_video_reg ), - .cpu_sel_oam ( sel_video_oam ), - .cpu_addr ( cpu_addr[7:0] ), - .cpu_wr ( !cpu_wr_n ), - .cpu_di ( cpu_do ), - .cpu_do ( video_do ), - - .lcd_on ( lcd_on ), - .lcd_clkena ( lcd_clkena ), - .lcd_data ( lcd_data ), - .mode ( lcd_mode ), - - .vram_rd ( video_rd ), - .vram_addr ( video_addr ), - .vram_data ( vram_do ), - - .dma_rd ( dma_rd ), - .dma_addr ( dma_addr ), - .dma_data ( dma_data ) -); - -// total 8k vram from $8000 to $9fff -wire cpu_wr_vram = sel_vram && !cpu_wr_n; -wire [7:0] vram_do; -wire vram_wren = video_rd?1'b0:cpu_wr_vram; -wire [12:0] vram_addr = video_rd?video_addr:cpu_addr[12:0]; - -vram vram ( - .clock ( clk ), - .address ( vram_addr ), - .wren ( vram_wren ), - .data ( cpu_do ), - .q ( vram_do ) -); - -// -------------------------------------------------------------------- -// -------------------------- zero page ram --------------------------- -// -------------------------------------------------------------------- - -// 127 bytes internal zero page ram from $ff80 to $fffe -wire cpu_wr_zpram = sel_zpram && !cpu_wr_n; -wire [7:0] zpram_do; -zpram zpram ( - .clock ( clk ), - .address ( cpu_addr[6:0] ), - .wren ( cpu_wr_zpram ), - .data ( cpu_do ), - .q ( zpram_do ) -); - -// -------------------------------------------------------------------- -// ------------------------- 8k internal ram -------------------------- -// -------------------------------------------------------------------- - -wire iram_wren = dma_rd?1'b0:cpu_wr_iram; -wire [12:0] iram_addr = dma_rd?dma_addr[12:0]:cpu_addr[12:0]; - -wire cpu_wr_iram = sel_iram && !cpu_wr_n; -wire [7:0] iram_do; -iram iram ( - .clock ( clk ), - .address ( iram_addr[12:0]), - .wren ( iram_wren ), - .data ( cpu_do ), - .q ( iram_do ) -); - -// -------------------------------------------------------------------- -// ------------------------ internal boot rom ------------------------- -// -------------------------------------------------------------------- - -// writing 01 to $ff50 disables the internal rom -reg boot_rom_enabled; -always @(posedge clk) begin - if(reset) - boot_rom_enabled <= 1'b1; - else if((cpu_addr == 16'hff50) && !cpu_wr_n && cpu_do[0]) - boot_rom_enabled <= 1'b0; -end - -// combine boot rom data with cartridge data -wire [7:0] rom_do = ((cpu_addr[14:8] == 7'h00) && boot_rom_enabled)?boot_rom_do:cart_do; - -assign cart_di = cpu_do; -assign cart_addr = dma_rd?dma_addr:cpu_addr; -assign cart_rd = dma_rd || ((sel_rom || sel_cram) && !cpu_rd_n); -assign cart_wr = (sel_rom || sel_cram) && !cpu_wr_n; - -wire [7:0] boot_rom_do; -BROM BROM ( - .addr ( cpu_addr[7:0] ), - .clk ( clk ), - .data ( boot_rom_do ) -); - - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/gb_mist.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/gb_mist.sv deleted file mode 100644 index b24049f3..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/gb_mist.sv +++ /dev/null @@ -1,439 +0,0 @@ -// -// gb_mist.v -// -// Gameboy for the MIST board https://github.com/mist-devel -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module gb_mist ( - input [1:0] CLOCK_27, - - output LED, - - // SPI interface to arm io controller - output SPI_DO, - input SPI_DI, - input SPI_SCK, - input SPI_SS2, - input SPI_SS3, - input SPI_SS4, - input CONF_DATA0, - - // SDRAM interface - inout [15:0] SDRAM_DQ, // SDRAM Data bus 16 Bits - output [12:0] SDRAM_A, // SDRAM Address bus 13 Bits - output SDRAM_DQML, // SDRAM Low-byte Data Mask - output SDRAM_DQMH, // SDRAM High-byte Data Mask - output SDRAM_nWE, // SDRAM Write Enable - output SDRAM_nCAS, // SDRAM Column Address Strobe - output SDRAM_nRAS, // SDRAM Row Address Strobe - output SDRAM_nCS, // SDRAM Chip Select - output [1:0] SDRAM_BA, // SDRAM Bank Address - output SDRAM_CLK, // SDRAM Clock - output SDRAM_CKE, // SDRAM Clock Enable - - // audio - output AUDIO_L, - output AUDIO_R, - - // video - output VGA_HS, - output VGA_VS, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B -); - -assign LED = !dio_download; - -`include "rtl/build_id.sv" -localparam CONF_STR = { - "GAMEBOY;GBCSGB;", - "F,GB;", - "O12,LCD ,white,yellow,invert;", - "O3,Boot,Normal,Fast;", - "O45,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", - "O6,Mapper,Detect,Force MBC1;", - "T7,Reset;", - "V,v1.00.",`BUILD_DATE -}; - -wire clk32; -reg clk4; // 4.194304 MHz CPU clock and GB pixel clock -reg clk8; // 8.388608 MHz VGA pixel clock -reg clk16; // 16.777216 MHz -wire pll_locked; -wire reset = (reset_cnt != 0); -reg [9:0] reset_cnt; - -wire [31:0] status; -wire [1:0] buttons, switches; -wire [7:0] kbjoy; -wire [7:0] joy_0, joy_1; -wire scandoubler_disable; -wire ypbpr; -wire ps2_kbd_clk, ps2_kbd_data; -wire hs, vs; -wire [5:0] r,g,b; -wire [15:0] audio_left; -wire [15:0] audio_right; - -wire [7:0] cart_di; // data from cpu to cart -wire [7:0] cart_do = cart_addr[0]?sdram_do[7:0]:sdram_do[15:8]; -wire [15:0] cart_addr; -wire cart_rd; -wire cart_wr; -reg eject = 1'b0; - -wire lcd_clkena; -wire [1:0] lcd_data; -wire [1:0] lcd_mode; -wire lcd_on; -wire invert; -wire color; - -// TODO: ds for cart ram write -wire [1:0] sdram_ds = dio_download?2'b11:{!cart_addr[0], cart_addr[0]}; -wire [15:0] sdram_do; -wire [15:0] sdram_di = dio_download?dio_data:{cart_di, cart_di}; -wire [23:0] sdram_addr = dio_download?dio_addr:{3'b000, mbc_bank, cart_addr[12:1]}; -wire sdram_oe = !dio_download && cart_rd; -wire sdram_we = (dio_download && dio_write) || (!dio_download && cart_ram_wr); -assign SDRAM_CKE = 1'b1; - -wire dio_download; -wire [23:0] dio_addr; -wire [15:0] dio_data; -wire dio_write; - -pll pll ( - .inclk0(CLOCK_27), - .c0(clk32), // 33.557143 MHz - .c1(SDRAM_CLK), // 33.557143 Mhz phase shifted - .locked(pll_locked) - ); - -always @(posedge clk8) - clk4 <= !clk4; - -always @(posedge clk16) - clk8 <= !clk8; - -always @(posedge clk32) - clk16 <= !clk16; - - -always @(posedge clk4) begin - if(status[0] || status[7] || buttons[1] || !pll_locked || dio_download) - reset_cnt <= 10'd1023; - else - if(reset_cnt != 0) - reset_cnt <= reset_cnt - 10'd1; -end - -gb gb ( - .reset ( reset ), - .clk ( clk4 ), - .fast_boot ( status[3] ), - .joystick ( joy0 | joy_1 | kbjoy), - .cart_addr ( cart_addr ), - .cart_rd ( cart_rd ), - .cart_wr ( cart_wr ), - .cart_do ( cart_do ), - .cart_di ( cart_di ), - .audio_l ( audio_left ), - .audio_r ( audio_right ), - .lcd_clkena ( lcd_clkena ), - .lcd_data ( lcd_data ), - .lcd_mode ( lcd_mode ), - .lcd_on ( lcd_on ) -); - -dac dacL( - .CLK ( clk32 ), - .RESET ( reset ), - .DACin ( audio_left[15:1] ), - .DACout ( AUDIO_L ) - ); - -dac dacR( - .CLK ( clk32 ), - .RESET ( reset ), - .DACin ( audio_right[15:1] ), - .DACout ( AUDIO_R ) - ); - -lcd lcd ( - .pclk ( clk8 ), - .clk ( clk4 ), - .tint ( status[2:1] == 1 ? 1 : 0 ), - .inv ( status[2:1] == 2 ? 1 : 0 ), - .clkena ( lcd_clkena), - .data ( lcd_data ), - .mode ( lcd_mode ), // used to detect begin of new lines and frames - .on ( lcd_on ), - .hs ( hs ), - .vs ( vs ), - .r ( r ), - .g ( g ), - .b ( b ) - ); - -mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io -( - .clk_sys (clk32 ), - .conf_str (CONF_STR ), - .SPI_SCK (SPI_SCK ), - .CONF_DATA0 (CONF_DATA0 ), - .SPI_SS2 (SPI_SS2 ), - .SPI_DO (SPI_DO ), - .SPI_DI (SPI_DI ), - .buttons (buttons ), - .switches (switches ), - .scandoubler_disable(scandoubler_disable), - .ypbpr (ypbpr ), - .ps2_kbd_clk (ps2_kbd_clk ), - .ps2_kbd_data (ps2_kbd_data ), - .joystick_0 (joy_0 ), - .joystick_1 (joy_1 ), - .status (status ) - ); - -sdram sdram ( - .sd_data (SDRAM_DQ ), - .sd_addr (SDRAM_A ), - .sd_dqm ({SDRAM_DQMH, SDRAM_DQML} ), - .sd_cs (SDRAM_nCS ), - .sd_ba (SDRAM_BA ), - .sd_we (SDRAM_nWE ), - .sd_ras (SDRAM_nRAS ), - .sd_cas (SDRAM_nCAS ), - .clk (clk32 ), - .clkref (clk4 ), - .init (!pll_locked | eject ), - .din (sdram_di ), - .addr (sdram_addr ), - .ds (sdram_ds ), - .we (sdram_we ), - .oe (sdram_oe ), - .dout (sdram_do ) - ); - -// include ROM download helper -data_io data_io ( - - .sck (SPI_SCK ), - .ss ( SPI_SS2 ), - .sdi ( SPI_DI ), - .downloading ( dio_download ), - .clk ( clk4 ), - .wr ( dio_write ), - .addr ( dio_addr ), - .data ( dio_data ) - ); - -video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(0)) video_mixer -( - .clk_sys (clk32 ), - .ce_pix (clk16 ), - .ce_pix_actual (clk16 ), - .SPI_SCK (SPI_SCK ), - .SPI_SS3 (SPI_SS3 ), - .SPI_DI (SPI_DI ), - .R (r ), - .G (g ), - .B (b ), - .HSync (hs ), - .VSync (vs ), - .VGA_R (VGA_R ), - .VGA_G (VGA_G ), - .VGA_B (VGA_B ), - .VGA_VS (VGA_VS ), - .VGA_HS (VGA_HS ), - .scandoubler_disable(1 ),//(scandoubler_disable), //VGA Only - .scanlines(scandoubler_disable ? 2'b00 : {status[5:4] == 3, status[5:4] == 2}), - .hq2x (status[5:4]==1), - .ypbpr_full (1 ), - .line_start (0 ), - .mono (0 ) - ); - -keyboard keyboard( - .clk(clk32), - .reset(), - .ps2_kbd_clk(ps2_kbd_clk), - .ps2_kbd_data(ps2_kbd_data), - .joystick(kbjoy) - ); - - -// TODO: RAM bank -// http://fms.komkon.org/GameBoy/Tech/Carts.html - -// 32MB SDRAM memory map using word addresses -// 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D -// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 S -// ------------------------------------------------- -// 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as ROM -// 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as RAM -// 0 0 0 0 R R B B B B B C C C C C C C C C C C C C C MBC1 ROM (R=RAM bank in mode 0) -// 0 0 0 1 0 0 0 0 0 0 R R C C C C C C C C C C C C C MBC1 RAM (R=RAM bank in mode 1) - -// --------------------------------------------------------------- -// ----------------------------- MBC1 ---------------------------- -// --------------------------------------------------------------- - -wire [8:0] mbc1_addr = - (cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0 - (cart_addr[15:14] == 2'b01)?{1'b0, mbc1_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127 - (cart_addr[15:13] == 3'b101)?{7'b1000000, mbc1_ram_bank}: // 8k RAM Bank 0-3 - 9'd0; - -wire [8:0] mbc2_addr = - (cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0 - (cart_addr[15:14] == 2'b01)?{1'b0, mbc2_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-15 - //todo // 512x4bits RAM, built-in into the MBC2 chip (Read/Write) - 9'd0; - -// -------------------------- RAM banking ------------------------ - -// in mode 0 (16/8 mode) the ram is not banked -// in mode 1 (4/32 mode) four ram banks are used -wire [1:0] mbc1_ram_bank = (mbc1_mode ? mbc1_ram_bank_reg:2'b00) & ram_mask; -wire [1:0] mbc2_ram_bank = (mbc2_mode ? mbc2_ram_bank_reg:2'b00) & ram_mask;//todo -// -------------------------- ROM banking ------------------------ - -// in mode 0 (16/8 mode) the ram bank select signals are the upper rom address lines -// in mode 1 (4/32 mode) the upper two rom address lines are 2'b00 -wire [6:0] mbc1_rom_bank_mode = { mbc1_mode?2'b00:mbc1_ram_bank_reg, mbc1_rom_bank_reg}; -wire [6:0] mbc2_rom_bank_mode = { mbc2_mode?2'b00:mbc2_ram_bank_reg, mbc2_rom_bank_reg};//todo -// mask address lines to enable proper mirroring -wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask;//128 -wire [6:0] mbc2_rom_bank = mbc2_rom_bank_mode & rom_mask;//16 -// --------------------- CPU register interface ------------------ -reg mbc1_ram_enable; -reg mbc1_mode; -reg [4:0] mbc1_rom_bank_reg; -reg [1:0] mbc1_ram_bank_reg; - -reg mbc2_ram_enable; -reg mbc2_mode; -reg [4:0] mbc2_rom_bank_reg;//todo -reg [1:0] mbc2_ram_bank_reg;//todo - - -// MBC2 todo -always @(posedge clk4) begin - if(reset) begin - mbc1_rom_bank_reg <= 5'd1; - mbc1_ram_bank_reg <= 2'd0; - mbc1_ram_enable <= 1'b0; - mbc1_mode <= 1'b0; - end else begin - if(cart_wr && (cart_addr[15:13] == 3'b000)) - mbc1_ram_enable <= (cart_di[3:0] == 4'ha); - if(cart_wr && (cart_addr[15:13] == 3'b001)) begin - if(cart_di[4:0]==0) mbc1_rom_bank_reg <= 5'd1; - else mbc1_rom_bank_reg <= cart_di[4:0]; - end - if(cart_wr && (cart_addr[15:13] == 3'b010)) - mbc1_ram_bank_reg <= cart_di[1:0]; - if(cart_wr && (cart_addr[15:13] == 3'b011)) - mbc1_mode <= cart_di[0]; - end -// eject <= status[8]; -end - -// extract header fields extracted from cartridge -// during download -reg [7:0] cart_mbc_type; -reg [7:0] cart_rom_size; -reg [7:0] cart_ram_size; -reg [7:0] cgb_flag;//$80 = GBC but GB compatible, $C0 GBC Only, $00 or other = GB -reg [7:0] sgb_flag;//GB/SGB Indicator (00 = GameBoy, 03 = Super GameBoy functions) - //(Super GameBoy functions won't work if <> $03.) - -// only write sdram if the write attept comes from the cart ram area -wire cart_ram_wr = cart_wr && mbc1_ram_enable && (cart_addr[15:13] == 3'b101); - -// RAM size - todo -wire [1:0] ram_mask = // 0 - no ram - (cart_ram_size == 1)?2'b00: // 1 - 2k, 1 bank - (cart_ram_size == 2)?2'b00: // 2 - 8k, 1 bank - 2'b11; // 3 - 32k, 4 banks - // 4 - 128k, ?? banks - // 5 - 64k, ?? banks - -// ROM size -wire [6:0] rom_mask = // 0 - 2 banks, 32k direct mapped - (cart_rom_size == 1)?7'b0000011: // 1 - 4 banks = 64k - (cart_rom_size == 2)?7'b0000111: // 2 - 8 banks = 128k - (cart_rom_size == 3)?7'b0001111: // 3 - 16 banks = 256k - (cart_rom_size == 4)?7'b0011111: // 4 - 32 banks = 512k - (cart_rom_size == 5)?7'b0111111: // 5 - 64 banks = 1M - (cart_rom_size == 6)?7'b1111111: // 6 - 128 banks = 2M -//? (cart_rom_size == 6)?7'b1111111: // 7 - ??? banks = 4M -//? (cart_rom_size == 6)?7'b1111111: // 8 - ??? banks = 8M - (cart_rom_size == 82)?7'b1000111: //$52 - 72 banks = 1.1M - (cart_rom_size == 83)?7'b1001111: //$53 - 80 banks = 1.2M -// (cart_rom_size == 84)?7'b1011111: - 7'b1011111; //$54 - 96 banks = 1.5M - -wire mbc1 = (cart_mbc_type == 1) || (cart_mbc_type == 2) || (cart_mbc_type == 3) || ~status[6]; -wire mbc2 = (cart_mbc_type == 5) || (cart_mbc_type == 6); -wire mmm01 = (cart_mbc_type == 11) || (cart_mbc_type == 12) || (cart_mbc_type == 13) || (cart_mbc_type == 14); -wire mbc3 = (cart_mbc_type == 15) || (cart_mbc_type == 16) || (cart_mbc_type == 17) || (cart_mbc_type == 18) || (cart_mbc_type == 19); -wire mbc4 = (cart_mbc_type == 21) || (cart_mbc_type == 22) || (cart_mbc_type == 23); -wire mbc5 = (cart_mbc_type == 25) || (cart_mbc_type == 26) || (cart_mbc_type == 27) || (cart_mbc_type == 28) || (cart_mbc_type == 29) || (cart_mbc_type == 30); -wire tama5 = (cart_mbc_type == 253); -//wire tama6 = (cart_mbc_type == ???); -wire HuC1 = (cart_mbc_type == 254); -wire HuC3 = (cart_mbc_type == 255); - -wire [8:0] mbc_bank = - mbc1?mbc1_addr: // MBC1, 16k bank 0, 16k bank 1-127 + ram - mbc2?mbc2_addr: // MBC2, 16k bank 0, 16k bank 1-15 + ram -// mbc3?mbc3_addr: -// mbc4?mbc4_addr: -// mbc5?mbc5_addr: -// tama5?tama5_addr: -// HuC1?HuC1_addr: -// HuC3?HuC3_addr: - {7'b0000000, cart_addr[14:13]}; // no MBC, 32k linear address - - -always @(posedge clk4) begin - if(!pll_locked) begin - cart_mbc_type <= 8'h00; - cart_rom_size <= 8'h00; - cart_ram_size <= 8'h00; - end else begin - if(dio_download && dio_write) begin - // cart is stored in 16 bit wide sdram, so addresses are shifted right - case(dio_addr) - 24'h9f: cgb_flag <= dio_data[7:0]; // $143 - 24'ha2: sgb_flag <= dio_data[7:0]; // $146 - 24'ha3: cart_mbc_type <= dio_data[7:0]; // $147 - 24'ha4: { cart_rom_size, cart_ram_size } <= dio_data; // $148/$149 - endcase - end - end -end - - - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/gbc_snd.vhd b/Console_MiST/Nintendo - Gameboy_MiST/rtl/gbc_snd.vhd deleted file mode 100644 index 2a9f8cdf..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/gbc_snd.vhd +++ /dev/null @@ -1,935 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.numeric_std.all; - -library work; - - -entity gbc_snd is - generic - ( - CLK_FREQ : integer := 100000000 - ); - port - ( - clk : in std_logic; - reset : in std_logic; - - s1_read : in std_logic; - s1_write : in std_logic; - s1_addr : in std_logic_vector(5 downto 0); - s1_readdata : out std_logic_vector(7 downto 0); - s1_writedata : in std_logic_vector(7 downto 0); - - snd_left : out std_logic_vector(15 downto 0); - snd_right : out std_logic_vector(15 downto 0) - ); - -end gbc_snd; - -architecture SYN of gbc_snd is - - subtype wav_t is std_logic_vector(3 downto 0); - type wav_arr_t is array(0 to 31) of wav_t; - - --constant clk_freq : integer := 100000000; - constant snd_freq : integer := 4194304; - - signal en_snd : boolean; -- Enable at base sound frequency (4.19MHz) - signal en_snd2 : boolean; -- Enable at clk/2 - signal en_snd4 : boolean; -- Enable at clk/4 - signal en_512 : boolean; -- 512Hz enable - - signal en_snden2 : boolean; -- Enable at clk/2 - signal en_snden4 : boolean; -- Enable at clk/4 - - signal en_len : boolean; -- Sample length - signal en_env : boolean; -- Envelope - signal en_sweep : boolean; -- Sweep - - signal snd_enable : std_logic; - - signal sq1_swper : std_logic_vector(2 downto 0); -- Sq1 sweep period - signal sq1_swdir : std_logic; -- Sq1 sweep direction - signal sq1_swshift : std_logic_vector(2 downto 0); -- Sq1 sweep frequency shift - signal sq1_duty : std_logic_vector(1 downto 0); -- Sq1 duty cycle - signal sq1_slen : std_logic_vector(5 downto 0); -- Sq1 play length - signal sq1_svol : std_logic_vector(3 downto 0); -- Sq1 initial volume - signal sq1_envsgn : std_logic; -- Sq1 envelope sign - signal sq1_envper : std_logic_vector(2 downto 0); -- Sq1 envelope period - signal sq1_freq : std_logic_vector(10 downto 0); -- Sq1 frequency - signal sq1_trigger : std_logic; -- Sq1 trigger play note - signal sq1_lenchk : std_logic; -- Sq1 length check enable - - signal sq1_fr2 : std_logic_vector(10 downto 0); -- Sq1 frequency (shadow copy) - signal sq1_vol : std_logic_vector(3 downto 0); -- Sq1 initial volume - signal sq1_playing : std_logic; -- Sq1 channel active - signal sq1_wav : std_logic_vector(5 downto 0); -- Sq1 output waveform - - signal sq2_duty : std_logic_vector(1 downto 0); -- Sq2 duty cycle - signal sq2_slen : std_logic_vector(5 downto 0); -- Sq2 play length - signal sq2_svol : std_logic_vector(3 downto 0); -- Sq2 initial volume - signal sq2_envsgn : std_logic; -- Sq2 envelope sign - signal sq2_envper : std_logic_vector(2 downto 0); -- Sq2 envelope period - signal sq2_freq : std_logic_vector(10 downto 0); -- Sq2 frequency - signal sq2_trigger : std_logic; -- Sq2 trigger play note - signal sq2_lenchk : std_logic; -- Sq2 length check enable - - signal sq2_fr2 : std_logic_vector(10 downto 0); -- Sq2 frequency (shadow copy) - signal sq2_vol : std_logic_vector(3 downto 0); -- Sq2 initial volume - signal sq2_playing : std_logic; -- Sq2 channel active - signal sq2_wav : std_logic_vector(5 downto 0); -- Sq2 output waveform - - signal wav_enable : std_logic; -- Wave enable - signal wav_slen : std_logic_vector(7 downto 0); -- Wave play length - signal wav_volsh : std_logic_vector(1 downto 0); -- Wave volume shift - signal wav_freq : std_logic_vector(10 downto 0); -- Wave frequency - signal wav_trigger : std_logic; -- Wave trigger play note - signal wav_lenchk : std_logic; -- Wave length check enable - - signal wav_fr2 : std_logic_vector(10 downto 0); -- Wave frequency (shadow copy) - signal wav_playing : std_logic; - signal wav_wav : std_logic_vector(5 downto 0); -- Wave output waveform - signal wav_ram : wav_arr_t; -- Wave table - signal wav_shift : boolean; - - signal noi_slen : std_logic_vector(5 downto 0); - signal noi_svol : std_logic_vector(3 downto 0); - signal noi_envsgn : std_logic; - signal noi_envper : std_logic_vector(2 downto 0); - signal noi_freqsh : std_logic_vector(3 downto 0); - signal noi_short : std_logic; - signal noi_div : std_logic_vector(2 downto 0); - signal noi_trigger : std_logic; - signal noi_lenchk : std_logic; - - signal noi_fr2 : std_logic_vector(10 downto 0); -- Noise frequency (shadow copy) - signal noi_vol : std_logic_vector(3 downto 0); -- Noise initial volume - signal noi_playing : std_logic; -- Noise channel active - signal noi_wav : std_logic_vector(5 downto 0); -- Noise output waveform - -begin - - en_snd2 <= en_snd and en_snden2; - en_snd4 <= en_snd and en_snden4; - - en_snd <= true; - - -- Calculate base clock enable (4.194304MHz) --- process(clk, reset) --- --to_unsigned(snd_freq * 65536 / clk_freq, 16); - --constant clk_frac : unsigned(15 downto 0) := X"0ABD"; -- clk_freq=100MHz --- constant clk_frac : unsigned(15 downto 0) := X"1991"; -- clk_freq=42MHz --- variable divacc : unsigned(15 downto 0); --- variable acc : unsigned(16 downto 0); --- begin --- if reset = '1' then --- divacc := (others => '0'); --- elsif rising_edge(clk) then - -- Sound base divider clock enable --- acc := ('0'&divacc) + ('0'&clk_frac); --- en_snd <= (acc(16) = '1'); --- divacc := acc(15 downto 0); --- end if; --- end process; - - -- Calculate divided and frame sequencer clock enables - process(clk, en_snd, reset) - variable clkcnt : unsigned(1 downto 0); - variable cnt_512 : unsigned(12 downto 0); - variable temp_512 : unsigned(13 downto 0); - variable framecnt : integer range 0 to 7 := 0; - begin - if reset = '1' then - clkcnt := "00"; - cnt_512 := (others => '0'); - framecnt := 0; - - elsif rising_edge(clk) then - -- Base clock divider - if en_snd then - clkcnt := clkcnt + 1; - if clkcnt(0) = '1' then - en_snden2 <= true; - else - en_snden2 <= false; - end if; - if clkcnt = "11" then - en_snden4 <= true; - else - en_snden4 <= false; - end if; - end if; - - -- Frame sequencer (length, envelope, sweep) clock enables - en_len <= false; - en_env <= false; - en_sweep <= false; - if en_512 then - if framecnt = 0 or framecnt = 2 or framecnt = 4 or framecnt = 6 then - en_len <= true; - end if; - if framecnt = 2 or framecnt = 6 then - en_sweep <= true; - end if; - if framecnt = 7 then - en_env <= true; - end if; - - if framecnt < 7 then - framecnt := framecnt + 1; - else - framecnt := 0; - end if; - end if; - - -- - en_512 <= false; - if en_snd then - temp_512 := ('0'&cnt_512) + to_unsigned(1, temp_512'length); - cnt_512 := temp_512(temp_512'high-1 downto temp_512'low); - en_512 <= (temp_512(13) = '1'); - end if; - end if; - end process; - - -- Registers - registers : process(clk, snd_enable, reset) - variable wav_shift_r : boolean; - variable wav_temp : wav_t; - begin - - -- Registers - if snd_enable = '0' then - -- Reset register values - sq1_swper <= (others => '0'); - sq1_swdir <= '0'; - sq1_swshift <= (others => '0'); - sq1_duty <= (others => '0'); - sq1_slen <= (others => '0'); - sq1_svol <= (others => '0'); - sq1_envsgn <= '0'; - sq1_envper <= (others => '0'); - sq1_freq <= (others => '0'); - sq1_lenchk <= '0'; - sq1_trigger <= '0'; - - sq2_duty <= (others => '0'); - sq2_slen <= (others => '0'); - sq2_svol <= (others => '0'); - sq2_envsgn <= '0'; - sq2_envper <= (others => '0'); - sq2_freq <= (others => '0'); - sq2_lenchk <= '0'; - sq2_trigger <= '0'; - - wav_enable <= '0'; - wav_volsh <= (others => '0'); - wav_freq <= (others => '0'); - wav_trigger <= '0'; - wav_lenchk <= '0'; - wav_shift_r := false; - - noi_slen <= (others => '0'); - noi_svol <= (others => '0'); - noi_envsgn <= '0'; - noi_envper <= (others => '0'); - noi_freqsh <= (others => '0'); - noi_short <= '0'; - noi_div <= (others => '0'); - noi_trigger <= '0'; - noi_lenchk <= '0'; - - elsif rising_edge(clk) then - if en_snd then - sq1_trigger <= '0'; - sq2_trigger <= '0'; - wav_trigger <= '0'; - noi_trigger <= '0'; - end if; - - -- Rotate wave table on rising edge of wav_shift - if wav_shift and not wav_shift_r then - wav_temp := wav_ram(0); - for I in 0 to 30 loop - wav_ram(I) <= wav_ram(I+1); - end loop; - wav_ram(31) <= wav_temp; - end if; - - if s1_write = '1' then - case s1_addr is - -- Square 1 - when "010000" => -- NR10 FF10 -PPP NSSS Sweep period, negate, shift - sq1_swper <= s1_writedata(6 downto 4); - sq1_swdir <= s1_writedata(3); - sq1_swshift <= s1_writedata(2 downto 0); - when "010001" => -- NR11 FF11 DDLL LLLL Duty, Length load (64-L) - sq1_duty <= s1_writedata(7 downto 6); - sq1_slen <= s1_writedata(5 downto 0); - when "010010" => -- NR12 FF12 VVVV APPP Starting volume, Envelope add mode, period - sq1_svol <= s1_writedata(7 downto 4); - sq1_envsgn <= s1_writedata(3); - sq1_envper <= s1_writedata(2 downto 0); - when "010011" => -- NR13 FF13 FFFF FFFF Frequency LSB - sq1_freq(7 downto 0) <= s1_writedata; - when "010100" => -- NR14 FF14 TL-- -FFF Trigger, Length enable, Frequency MSB - sq1_trigger <= s1_writedata(7); - sq1_lenchk <= s1_writedata(6); - sq1_freq(10 downto 8) <= s1_writedata(2 downto 0); - - -- Square 2 - when "010110" => -- NR21 FF16 DDLL LLLL Duty, Length load (64-L) - sq2_duty <= s1_writedata(7 downto 6); - sq2_slen <= s1_writedata(5 downto 0); - when "010111" => -- NR22 FF17 VVVV APPP Starting volume, Envelope add mode, period - sq2_svol <= s1_writedata(7 downto 4); - sq2_envsgn <= s1_writedata(3); - sq2_envper <= s1_writedata(2 downto 0); - when "011000" => -- NR23 FF18 FFFF FFFF Frequency LSB - sq2_freq(7 downto 0) <= s1_writedata; - when "011001" => -- NR24 FF19 TL-- -FFF Trigger, Length enable, Frequency MSB - sq2_trigger <= s1_writedata(7); - sq2_lenchk <= s1_writedata(6); - sq2_freq(10 downto 8) <= s1_writedata(2 downto 0); - - -- Wave - when "011010" => -- NR30 FF1A E--- ---- DAC power - wav_enable <= s1_writedata(7); - when "011011" => -- NR31 FF1B LLLL LLLL Length load (256-L) - wav_slen <= s1_writedata; - when "011100" => -- NR32 FF1C -VV- ---- Volume code (00=0%, 01=100%, 10=50%, 11=25%) - wav_volsh <= s1_writedata(6 downto 5); - when "011101" => -- NR33 FF1D FFFF FFFF Frequency LSB - wav_freq(7 downto 0) <= s1_writedata; - when "011110" => -- NR34 FF1E TL-- -FFF Trigger, Length enable, Frequency MSB - wav_trigger <= s1_writedata(7); - wav_lenchk <= s1_writedata(6); - wav_freq(10 downto 8) <= s1_writedata(2 downto 0); - - -- Noise - when "100000" => -- NR41 FF20 --LL LLLL Length load (64-L) - noi_slen <= s1_writedata(5 downto 0); - when "100001" => -- NR42 FF21 VVVV APPP Starting volume, Envelope add mode, period - noi_svol <= s1_writedata(7 downto 4); - noi_envsgn <= s1_writedata(3); - noi_envper <= s1_writedata(2 downto 0); - when "100010" => -- NR43 FF22 SSSS WDDD Clock shift, Width mode of LFSR, Divisor code - noi_freqsh <= s1_writedata(7 downto 4); - noi_short <= s1_writedata(3); - noi_div <= s1_writedata(2 downto 0); - when "100011" => -- NR44 FF23 TL-- ---- Trigger, Length enable - noi_trigger <= s1_writedata(7); - noi_lenchk <= s1_writedata(6); - --- -- Control/Status --- when "100100" => -- NR50 FF24 ALLL BRRR Vin L enable, Left vol, Vin R enable, Right vol --- when "100101" => -- NR51 FF25 NW21 NW21 Left enables, Right enables --- - -- Wave Table - when "110000" => -- FF30 0000 1111 Samples 0 and 1 - wav_ram(0) <= s1_writedata(7 downto 4); - wav_ram(1) <= s1_writedata(3 downto 0); - when "110001" => -- FF31 0000 1111 Samples 2 and 3 - wav_ram(2) <= s1_writedata(7 downto 4); - wav_ram(3) <= s1_writedata(3 downto 0); - when "110010" => -- FF32 0000 1111 Samples 4 and 5 - wav_ram(4) <= s1_writedata(7 downto 4); - wav_ram(5) <= s1_writedata(3 downto 0); - when "110011" => -- FF33 0000 1111 Samples 6 and 31 - wav_ram(6) <= s1_writedata(7 downto 4); - wav_ram(7) <= s1_writedata(3 downto 0); - when "110100" => -- FF34 0000 1111 Samples 8 and 31 - wav_ram(8) <= s1_writedata(7 downto 4); - wav_ram(9) <= s1_writedata(3 downto 0); - when "110101" => -- FF35 0000 1111 Samples 10 and 11 - wav_ram(10) <= s1_writedata(7 downto 4); - wav_ram(11) <= s1_writedata(3 downto 0); - when "110110" => -- FF36 0000 1111 Samples 12 and 13 - wav_ram(12) <= s1_writedata(7 downto 4); - wav_ram(13) <= s1_writedata(3 downto 0); - when "110111" => -- FF37 0000 1111 Samples 14 and 15 - wav_ram(14) <= s1_writedata(7 downto 4); - wav_ram(15) <= s1_writedata(3 downto 0); - when "111000" => -- FF38 0000 1111 Samples 16 and 17 - wav_ram(16) <= s1_writedata(7 downto 4); - wav_ram(17) <= s1_writedata(3 downto 0); - when "111001" => -- FF39 0000 1111 Samples 18 and 19 - wav_ram(18) <= s1_writedata(7 downto 4); - wav_ram(19) <= s1_writedata(3 downto 0); - when "111010" => -- FF3A 0000 1111 Samples 20 and 21 - wav_ram(20) <= s1_writedata(7 downto 4); - wav_ram(21) <= s1_writedata(3 downto 0); - when "111011" => -- FF3B 0000 1111 Samples 22 and 23 - wav_ram(22) <= s1_writedata(7 downto 4); - wav_ram(23) <= s1_writedata(3 downto 0); - when "111100" => -- FF3C 0000 1111 Samples 24 and 25 - wav_ram(24) <= s1_writedata(7 downto 4); - wav_ram(25) <= s1_writedata(3 downto 0); - when "111101" => -- FF3D 0000 1111 Samples 26 and 27 - wav_ram(26) <= s1_writedata(7 downto 4); - wav_ram(27) <= s1_writedata(3 downto 0); - when "111110" => -- FF3E 0000 1111 Samples 28 and 29 - wav_ram(28) <= s1_writedata(7 downto 4); - wav_ram(29) <= s1_writedata(3 downto 0); - when "111111" => -- FF3F 0000 1111 Samples 30 and 31 - wav_ram(30) <= s1_writedata(7 downto 4); - wav_ram(31) <= s1_writedata(3 downto 0); - - when others => - null; - end case; - end if; - - if s1_read = '1' then - case s1_addr is - -- Square 1 - when "010000" => -- NR10 FF10 -PPP NSSS Sweep period, negate, shift - s1_readdata <= '1' & sq1_swper & sq1_swdir & sq1_swshift; - when "010001" => -- NR11 FF11 DDLL LLLL Duty, Length load (64-L) - s1_readdata <= sq1_duty & "111111"; - when "010010" => -- NR12 FF12 VVVV APPP Starting volume, Envelope add mode, period - s1_readdata <= sq1_vol & sq1_envsgn & sq1_envper; - when "010011" => -- NR13 FF13 FFFF FFFF Frequency LSB - s1_readdata <= X"FF"; - when "010100" => -- NR14 FF14 TL-- -FFF Trigger, Length enable, Frequency MSB - s1_readdata <= '0' & sq1_lenchk & "111111"; - - -- Square 2 - when "010110" => -- NR21 FF16 DDLL LLLL Duty, Length load (64-L) - s1_readdata <= sq2_duty & "111111"; - when "010111" => -- NR22 FF17 VVVV APPP Starting volume, Envelope add mode, period - s1_readdata <= sq2_vol & sq2_envsgn & sq2_envper; - when "011000" => -- NR23 FF18 FFFF FFFF Frequency LSB - s1_readdata <= X"FF"; - when "011001" => -- NR24 FF19 TL-- -FFF Trigger, Length enable, Frequency MSB - s1_readdata <= '0' & sq2_lenchk & "111111"; - - when "100110" => -- NR52 FF26 P--- NW21 Power control/status, Channel length statuses - s1_readdata <= snd_enable & "00000" & sq2_playing & sq1_playing; - - -- Wave - when "011010" => -- NR30 FF1A E--- ---- DAC power - s1_readdata <= wav_enable & "1111111"; - when "011011" => -- NR31 FF1B LLLL LLLL Length load (256-L) - s1_readdata <= X"FF"; - when "011100" => -- NR32 FF1C -VV- ---- Volume code (00=0%, 01=100%, 10=50%, 11=25%) - s1_readdata <= '1' & wav_volsh & "11111"; - when "011101" => -- NR33 FF1D FFFF FFFF Frequency LSB - s1_readdata <= X"FF"; - when "011110" => -- NR34 FF1E TL-- -FFF Trigger, Length enable, Frequency MSB - s1_readdata <= wav_trigger & wav_lenchk & "111111"; - - -- Noise - when "100000" => -- NR41 FF20 --LL LLLL Length load (64-L) - s1_readdata <= X"FF"; - when "100001" => -- NR42 FF21 VVVV APPP Starting volume, Envelope add mode, period - s1_readdata <= noi_svol & noi_envsgn & noi_envper; - when "100010" => -- NR43 FF22 SSSS WDDD Clock shift, Width mode of LFSR, Divisor code - s1_readdata <= noi_freqsh & noi_short & noi_div; - when "100011" => -- NR44 FF23 TL-- ---- Trigger, Length enable - s1_readdata <= noi_trigger & noi_lenchk & "111111"; - - -- Wave Table - when "110000" => -- FF30 0000 1111 Samples 0 and 1 - s1_readdata <= wav_ram(0) & wav_ram(1); - when "110001" => -- FF31 0000 1111 Samples 2 and 3 - s1_readdata <= wav_ram(2) & wav_ram(3); - when "110010" => -- FF32 0000 1111 Samples 4 and 5 - s1_readdata <= wav_ram(4) & wav_ram(5); - when "110011" => -- FF33 0000 1111 Samples 6 and 31 - s1_readdata <= wav_ram(6) & wav_ram(7); - when "110100" => -- FF34 0000 1111 Samples 8 and 31 - s1_readdata <= wav_ram(8) & wav_ram(9); - when "110101" => -- FF35 0000 1111 Samples 10 and 11 - s1_readdata <= wav_ram(10) & wav_ram(11); - when "110110" => -- FF36 0000 1111 Samples 12 and 13 - s1_readdata <= wav_ram(12) & wav_ram(13); - when "110111" => -- FF37 0000 1111 Samples 14 and 15 - s1_readdata <= wav_ram(14) & wav_ram(15); - when "111000" => -- FF38 0000 1111 Samples 16 and 17 - s1_readdata <= wav_ram(16) & wav_ram(17); - when "111001" => -- FF39 0000 1111 Samples 18 and 19 - s1_readdata <= wav_ram(18) & wav_ram(19); - when "111010" => -- FF3A 0000 1111 Samples 20 and 21 - s1_readdata <= wav_ram(20) & wav_ram(21); - when "111011" => -- FF3B 0000 1111 Samples 22 and 23 - s1_readdata <= wav_ram(22) & wav_ram(23); - when "111100" => -- FF3C 0000 1111 Samples 24 and 25 - s1_readdata <= wav_ram(24) & wav_ram(25); - when "111101" => -- FF3D 0000 1111 Samples 26 and 27 - s1_readdata <= wav_ram(26) & wav_ram(27); - when "111110" => -- FF3E 0000 1111 Samples 28 and 29 - s1_readdata <= wav_ram(28) & wav_ram(29); - when "111111" => -- FF3F 0000 1111 Samples 30 and 31 - s1_readdata <= wav_ram(30) & wav_ram(31); - - when others => - s1_readdata <= X"FF"; - end case; - - end if; - - wav_shift_r := wav_shift; - end if; - - if reset = '1' then - snd_enable <= '0'; - elsif rising_edge(clk) then - if s1_write = '1' and s1_addr = "100110" then - -- NR52 FF26 P--- NW21 Power control/status, Channel length statuses - snd_enable <= s1_writedata(7); - end if; - end if; - end process; - - sound : process(clk, snd_enable, en_snd, en_len, en_env, en_sweep) - constant duty_0 : std_logic_vector(0 to 7) := "00000001"; - constant duty_1 : std_logic_vector(0 to 7) := "10000001"; - constant duty_2 : std_logic_vector(0 to 7) := "10000111"; - constant duty_3 : std_logic_vector(0 to 7) := "01111110"; - variable sq1_fcnt : unsigned(10 downto 0); - variable sq1_phase : integer range 0 to 7; - variable sq1_len : std_logic_vector(6 downto 0); - variable sq1_envcnt : std_logic_vector(2 downto 0); -- Sq1 envelope timer count - variable sq1_swcnt : std_logic_vector(2 downto 0); -- Sq1 sweep timer count - variable sq1_swoffs : unsigned(11 downto 0); - variable sq1_swfr : unsigned(11 downto 0); - variable sq1_out : std_logic; - - variable sq2_fcnt : unsigned(10 downto 0); - variable sq2_phase : integer range 0 to 7; - variable sq2_len : std_logic_vector(6 downto 0); - variable sq2_envcnt : std_logic_vector(2 downto 0); -- Sq2 envelope timer count - variable sq2_out : std_logic; - - variable wav_fcnt : unsigned(10 downto 0); - variable wav_len : std_logic_vector(8 downto 0); - - variable noi_divisor: unsigned(10 downto 0); -- Noise frequency divisor - variable noi_freq : unsigned(10 downto 0); -- Noise frequency (calculated) - variable noi_fcnt : unsigned(10 downto 0); - variable noi_lfsr : unsigned(15 downto 0); - variable noi_len : std_logic_vector(6 downto 0); - variable noi_envcnt : std_logic_vector(2 downto 0); -- Noise envelope timer count - variable noi_out : std_logic; - - variable acc_fcnt : unsigned(11 downto 0); - begin - -- Sound processing - if snd_enable = '0' then - sq1_playing <= '0'; - sq1_fr2 <= (others => '0'); - sq1_fcnt := (others => '0'); - sq1_phase := 0; - sq1_len := (others => '0'); - sq1_vol <= "0000"; - sq1_envcnt := "000"; - sq1_swcnt := "000"; - sq1_swoffs := (others => '0'); - sq1_swfr := (others => '0'); - sq1_out := '0'; - - sq2_playing <= '0'; - sq2_fr2 <= (others => '0'); - sq2_fcnt := (others => '0'); - sq2_phase := 0; - sq2_len := (others => '0'); - sq2_vol <= "0000"; - sq2_envcnt := "000"; - sq2_out := '0'; - - wav_fcnt := (others => '0'); - wav_len := (others => '0'); - - noi_playing <= '0'; - noi_fr2 <= (others => '0'); - noi_fcnt := (others => '0'); - noi_lfsr := (others => '1'); - noi_len := (others => '0'); - noi_vol <= "0000"; - noi_envcnt := "000"; - noi_out := '0'; - - elsif rising_edge(clk) then - if en_snd4 then - -- Sq1 frequency timer - if sq1_playing = '1' then - acc_fcnt := ('0'&sq1_fcnt) + to_unsigned(1, acc_fcnt'length); - if acc_fcnt(acc_fcnt'high) = '1' then - if sq1_phase < 7 then - sq1_phase := sq1_phase + 1; - else - sq1_phase := 0; - end if; - sq1_fcnt := unsigned(sq1_fr2); - else - sq1_fcnt := acc_fcnt(sq1_fcnt'range); - end if; - end if; - - -- Sq2 frequency timer - if sq2_playing = '1' then - acc_fcnt := ('0'&sq2_fcnt) + to_unsigned(1, acc_fcnt'length); - if acc_fcnt(acc_fcnt'high) = '1' then - if sq2_phase < 7 then - sq2_phase := sq2_phase + 1; - else - sq2_phase := 0; - end if; - sq2_fcnt := unsigned(sq2_fr2); - else - sq2_fcnt := acc_fcnt(sq2_fcnt'range); - end if; - end if; - - -- Noi frequency timer - if noi_playing = '1' then - acc_fcnt := ('0'&noi_fcnt) + to_unsigned(1, acc_fcnt'length); - if acc_fcnt(acc_fcnt'high) = '1' then - -- Noise LFSR - if noi_short = '1' then - noi_lfsr := (noi_lfsr(0) xor noi_lfsr(1)) & noi_lfsr(15 downto 8) & (noi_lfsr(0) xor noi_lfsr(1)) & noi_lfsr(6 downto 1); - else - noi_lfsr := (noi_lfsr(0) xor noi_lfsr(1)) & noi_lfsr(15 downto 1); - end if; - - noi_out := not noi_lfsr(0); - noi_fcnt := unsigned(noi_fr2); - else - noi_fcnt := acc_fcnt(noi_fcnt'range); - end if; - end if; - - case sq1_duty is - when "00" => sq1_out := duty_0(sq1_phase); - when "01" => sq1_out := duty_1(sq1_phase); - when "10" => sq1_out := duty_2(sq1_phase); - when "11" => sq1_out := duty_3(sq1_phase); - when others => null; - end case; - - if sq1_out = '1' then - sq1_wav <= sq1_vol & "00"; - else - sq1_wav <= "000000"; - end if; - - case sq2_duty is - when "00" => sq2_out := duty_0(sq2_phase); - when "01" => sq2_out := duty_1(sq2_phase); - when "10" => sq2_out := duty_2(sq2_phase); - when "11" => sq2_out := duty_3(sq2_phase); - when others => null; - end case; - - if sq2_out = '1' then - sq2_wav <= sq2_vol & "00"; - else - sq2_wav <= "000000"; - end if; - - if noi_out = '1' then - noi_wav <= noi_vol & "00"; - else - noi_wav <= "000000"; - end if; - - end if; - - -- Square channel 1 - if sq1_playing = '1' then - -- Length counter - if en_len then - if sq1_len(6) = '0' then - sq1_len := std_logic_vector(unsigned(sq1_len) + to_unsigned(1, sq1_len'length)); - end if; - end if; - - -- Envelope counter - if en_env then - if sq1_envper /= "000" then - sq1_envcnt := std_logic_vector(unsigned(sq1_envcnt) + to_unsigned(1, sq1_envcnt'length)); - if sq1_envcnt = sq1_envper then - if sq1_envsgn = '1' then - if sq1_vol /= "1111" then - sq1_vol <= std_logic_vector(unsigned(sq1_vol) + to_unsigned(1, sq1_vol'length)); - end if; - else - if sq1_vol /= "0000" then - sq1_vol <= std_logic_vector(unsigned(sq1_vol) - to_unsigned(1, sq1_vol'length)); - end if; - end if; - sq1_envcnt := "000"; - end if; - end if; - end if; - - -- Sweep processing - if en_sweep or sq1_trigger = '1' then - case sq1_swshift is - when "000" => sq1_swoffs := unsigned('0' & sq1_fr2); - when "001" => sq1_swoffs := "00" & unsigned(sq1_fr2(10 downto 1)); - when "010" => sq1_swoffs := "000" & unsigned(sq1_fr2(10 downto 2)); - when "011" => sq1_swoffs := "0000" & unsigned(sq1_fr2(10 downto 3)); - when "100" => sq1_swoffs := "00000" & unsigned(sq1_fr2(10 downto 4)); - when "101" => sq1_swoffs := "000000" & unsigned(sq1_fr2(10 downto 5)); - when "110" => sq1_swoffs := "0000000" & unsigned(sq1_fr2(10 downto 6)); - when "111" => sq1_swoffs := "00000000" & unsigned(sq1_fr2(10 downto 7)); - when others => sq1_swoffs := unsigned('0' & sq1_fr2); - end case; - - -- Calculate next sweep frequency - if sq1_swper /= "000" then - if sq1_swdir = '0' then - sq1_swfr := ('0' & unsigned(sq1_fr2)) - sq1_swoffs; - else - sq1_swfr := ('0' & unsigned(sq1_fr2)) + sq1_swoffs; - end if; - else -- Sweep disabled - sq1_swfr := unsigned('0' & sq1_fr2); - end if; - - -- Sweep counter - if sq1_swper /= "000" then - sq1_swcnt := std_logic_vector(unsigned(sq1_swcnt) + to_unsigned(1, sq1_swcnt'length)); - if sq1_swcnt = sq1_swper then - sq1_fr2 <= std_logic_vector(sq1_swfr(10 downto 0)); - sq1_swcnt := "000"; - end if; - end if; - end if; - - -- Check for end of playing conditions - if sq1_vol = X"0" -- Volume == 0 - or (sq1_lenchk = '1' and sq1_len(6) = '1') -- Play length timer overrun - or (sq1_swper /= "000" and sq1_swfr(11) = '1') -- Sweep frequency overrun - then - sq1_playing <= '0'; - sq1_envcnt := "000"; - sq1_swcnt := "000"; - --sq1_wav <= "000000"; - end if; - end if; - - -- Check sample trigger and start playing - if sq1_trigger = '1' then - sq1_fr2 <= sq1_freq; - sq1_fcnt := unsigned(sq1_freq); - noi_lfsr := (others => '1'); - sq1_playing <= '1'; - sq1_vol <= sq1_svol; - sq1_envcnt := "000"; - sq1_swcnt := "000"; - sq1_len := '0' & sq1_slen; - sq1_phase := 0; - end if; - - -- Square channel 2 - if sq2_playing = '1' then - -- Length counter - if en_len then - if sq2_len(6) = '0' then - sq2_len := std_logic_vector(unsigned(sq2_len) + to_unsigned(1, sq2_len'length)); - end if; - end if; - - -- Envelope counter - if en_env then - if sq2_envper /= "000" then - sq2_envcnt := std_logic_vector(unsigned(sq2_envcnt) + to_unsigned(1, sq2_envcnt'length)); - if sq2_envcnt = sq2_envper then - if sq2_envsgn = '1' then - if sq2_vol /= "1111" then - sq2_vol <= std_logic_vector(unsigned(sq2_vol) + to_unsigned(1, sq2_vol'length)); - end if; - else - if sq2_vol /= "0000" then - sq2_vol <= std_logic_vector(unsigned(sq2_vol) - to_unsigned(1, sq2_vol'length)); - end if; - end if; - sq2_envcnt := "000"; - end if; - end if; - end if; - - -- Check for end of playing conditions - if sq2_vol = X"0" -- Volume == 0 - or (sq2_lenchk = '1' and sq2_len(6) = '1') -- Play length timer overrun - then - sq2_playing <= '0'; - sq2_envcnt := "000"; - --sq2_wav <= "000000"; - end if; - end if; - - -- Check sample trigger and start playing - if sq2_trigger = '1' then - sq2_fr2 <= sq2_freq; - sq2_fcnt := unsigned(sq2_freq); - sq2_playing <= '1'; - sq2_vol <= sq2_svol; - sq2_envcnt := "000"; - sq2_len := '0' & sq2_slen; - sq2_phase := 0; - end if; - - -- Noise channel - if noi_playing = '1' then - -- Length counter - if en_len then - if noi_len(6) = '0' then - noi_len := std_logic_vector(unsigned(noi_len) + to_unsigned(1, noi_len'length)); - end if; - end if; - - -- Envelope counter - if en_env then - if noi_envper /= "000" then - noi_envcnt := std_logic_vector(unsigned(noi_envcnt) + to_unsigned(1, noi_envcnt'length)); - if noi_envcnt = noi_envper then - if noi_envsgn = '1' then - if noi_vol /= "1111" then - noi_vol <= std_logic_vector(unsigned(noi_vol) + to_unsigned(1, noi_vol'length)); - end if; - else - if noi_vol /= "0000" then - noi_vol <= std_logic_vector(unsigned(noi_vol) - to_unsigned(1, noi_vol'length)); - end if; - end if; - noi_envcnt := "000"; - end if; - end if; - end if; - - -- Check for end of playing conditions - if noi_vol = X"0" -- Volume == 0 - or (noi_lenchk = '1' and noi_len(6) = '1') -- Play length timer overrun - then - noi_playing <= '0'; - noi_envcnt := "000"; - --sq2_wav <= "000000"; - end if; - end if; - - -- Check sample trigger and start playing - if noi_trigger = '1' then - -- Calculate noise frequency - case noi_div is - when "000" => noi_divisor := to_unsigned(2048 - 8, noi_divisor'length); - when "001" => noi_divisor := to_unsigned(2048 - 16, noi_divisor'length); - when "010" => noi_divisor := to_unsigned(2048 - 32, noi_divisor'length); - when "011" => noi_divisor := to_unsigned(2048 - 48, noi_divisor'length); - when "100" => noi_divisor := to_unsigned(2048 - 64, noi_divisor'length); - when "101" => noi_divisor := to_unsigned(2048 - 80, noi_divisor'length); - when "110" => noi_divisor := to_unsigned(2048 - 96, noi_divisor'length); - when others => noi_divisor := to_unsigned(2048 - 112, noi_divisor'length); - end case; - --- case noi_freqsh is --- when "000" => noi_freq := unsigned(noi_divisor); --- when "001" => noi_freq := '0' & unsigned(noi_divisor(10 downto 1)); --- when "010" => noi_freq := "00" & unsigned(noi_divisor(10 downto 2)); --- when "011" => noi_freq := "000" & unsigned(noi_divisor(10 downto 3)); --- when "100" => noi_freq := "0000" & unsigned(noi_divisor(10 downto 4)); --- when "101" => noi_freq := "00000" & unsigned(noi_divisor(10 downto 5)); --- when "110" => noi_freq := "000000" & unsigned(noi_divisor(10 downto 6)); --- when "111" => noi_freq := "0000000" & unsigned(noi_divisor(10 downto 7)); --- when others => noi_freq := unsigned(noi_divisor); --- end case; - noi_freq := noi_divisor sll to_integer(unsigned(noi_freqsh)); - - noi_fr2 <= std_logic_vector(noi_freq); - noi_fcnt := noi_freq; - noi_playing <= '1'; - noi_vol <= noi_svol; - noi_envcnt := "000"; - noi_len := '0' & noi_slen; - end if; - - if en_snd2 then - -- Wave frequency timer - wav_shift <= false; - if wav_playing = '1' then - acc_fcnt := ('0'&wav_fcnt) + to_unsigned(1, acc_fcnt'length); - if acc_fcnt(acc_fcnt'high) = '1' then - wav_shift <= true; - wav_fcnt := unsigned(wav_fr2); - else - wav_fcnt := acc_fcnt(wav_fcnt'range); - end if; - end if; - end if; - - -- Wave channel - if wav_playing = '1' then - -- Length counter - if en_len then - if wav_len(8) = '0' then - wav_len := std_logic_vector(unsigned(wav_len) + to_unsigned(1, wav_len'length)); - end if; - end if; - - -- Check for end of playing conditions - if (wav_lenchk = '1' and wav_len(8) = '1') then - wav_playing <= '0'; - wav_wav <= "000000"; - end if; - end if; - - -- Check sample trigger and start playing - if wav_trigger = '1' then - wav_fr2 <= wav_freq; - wav_fcnt := unsigned(wav_freq); - wav_playing <= '1'; - wav_len := '0' & wav_slen; - end if; - - if wav_enable = '1' and wav_volsh /= "00" then - case wav_volsh is - when "01" => wav_wav <= wav_ram(0) & "00"; - when "10" => wav_wav <= '0' & wav_ram(0) & '0'; - when "11" => wav_wav <= "00" & wav_ram(0); - when others => wav_wav <= (others => 'X'); - end case; - else - wav_wav <= "000000"; - end if; - - end if; -- snd_enable - end process sound; - - -- Test - process(clk, en_512, reset) - variable l : std_logic_vector(15 downto 0); - begin - if reset = '1' then - l := x"4000"; - - elsif rising_edge(clk) then - if en_512 then - l := not l; - end if; --- snd_left <= l; - end if; - end process; - - -- Mixer - mixer : process(sq1_wav, sq2_wav, noi_wav, wav_wav) - variable snd_left_in : unsigned(7 downto 0); - variable snd_right_in : unsigned(7 downto 0); - begin - snd_left_in := (others => '0'); - snd_right_in := (others => '0'); - - snd_left_in := snd_left_in + ("00"&unsigned(sq1_wav)); - snd_left_in := snd_left_in + ("00"&unsigned(wav_wav)); - snd_right_in := snd_right_in + ("00"&unsigned(sq2_wav)); - snd_right_in := snd_right_in + ("00"&unsigned(noi_wav)); - - snd_left <= std_logic_vector(snd_left_in) & X"00"; - snd_right <= std_logic_vector(snd_right_in) & X"00"; - end process; - -end SYN; diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/hq2x.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/iram.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/iram.sv deleted file mode 100644 index 744357db..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/iram.sv +++ /dev/null @@ -1,172 +0,0 @@ -// megafunction wizard: %RAM: 1-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: iram.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.4 Build 182 03/12/2014 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2014 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module iram ( - address, - clock, - data, - wren, - q); - - input [12:0] address; - input clock; - input [7:0] data; - input wren; - output [7:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clock; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] q = sub_wire0[7:0]; - - altsyncram altsyncram_component ( - .address_a (address), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .q_a (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .address_b (1'b1), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b (1'b1), - .eccstatus (), - .q_b (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 8192, - altsyncram_component.operation_mode = "SINGLE_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_reg_a = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 13, - altsyncram_component.width_a = 8, - altsyncram_component.width_byteena_a = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -// Retrieval info: PRIVATE: AclrByte NUMERIC "0" -// Retrieval info: PRIVATE: AclrData NUMERIC "0" -// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: Clken NUMERIC "0" -// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -// Retrieval info: PRIVATE: RegAddr NUMERIC "1" -// Retrieval info: PRIVATE: RegData NUMERIC "1" -// Retrieval info: PRIVATE: RegOutput NUMERIC "0" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: SingleClock NUMERIC "1" -// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" -// Retrieval info: PRIVATE: WidthData NUMERIC "8" -// Retrieval info: PRIVATE: rden NUMERIC "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL iram.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL iram.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL iram.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL iram.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL iram_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL iram_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/lcd.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/lcd.sv deleted file mode 100644 index df77d663..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/lcd.sv +++ /dev/null @@ -1,147 +0,0 @@ -// Gameboy for the MiST -// (c) 2015 Till Harbaum - -// The gameboy lcd runs from a shift register which is filled at 4194304 pixels/sec - -module lcd ( - input clk, - input clkena, - input [1:0] data, - input [1:0] mode, - - input tint, - input inv, - // pixel clock - input pclk, - input on, - - // VGA output - output reg hs, - output reg vs, - output [5:0] r, - output [5:0] g, - output [5:0] b -); - -// Mode 00: h-blank -// Mode 01: v-blank -// Mode 10: oam -// Mode 11: oam and vram - -// space for 2*160 pixel -reg [7:0] shift_reg_wptr; -reg p_toggle; -reg [1:0] shift_reg [511:0]; -reg [1:0] last_mode_in; - -// shift register input -always @(posedge clk) begin - last_mode_in <= mode; - - // end of vsync - if(clkena) begin - shift_reg[{p_toggle, shift_reg_wptr}] <= data; - shift_reg_wptr <= shift_reg_wptr + 8'd1; - end - - // reset write pointer at end of hsync phase - if((mode != 2'b00) && (last_mode_in == 2'b00)) begin - shift_reg_wptr <= 8'd0; - p_toggle <= !p_toggle; - end -end - -// -parameter H = 160; // width of visible area -parameter HFP = 24; // unused time before hsync -parameter HS = 20; // width of hsync -parameter HBP = 24; // unused time after hsync -// total = 228 - -parameter V = 576; // height of visible area -parameter VFP = 2; // unused time before vsync -parameter VS = 2; // width of vsync -parameter VBP = 36; // unused time after vsync -// total = 616 - -reg[7:0] h_cnt; // horizontal pixel counter -reg[9:0] v_cnt; // vertical pixel counter - -// horizontal pixel counter -reg [1:0] last_mode_h; -always@(posedge pclk) begin - last_mode_h <= mode; - - if(h_cnt==H+HFP+HS+HBP-1) h_cnt <= 0; - else h_cnt <= h_cnt + 1; - - // generate negative hsync signal - if(h_cnt == H+HFP) hs <= 1'b0; - if(h_cnt == H+HFP+HS) hs <= 1'b1; - - // synchronize to input mode - // end of hblank - if((mode == 2'b10) && (last_mode_h == 2'b00)) - h_cnt <= 0; -end - -// veritical pixel counter -reg [1:0] last_mode_v; -always@(posedge pclk) begin - // the vertical counter is processed at the begin of each hsync - if(h_cnt == H+HFP+HS+HBP-1) begin - if(v_cnt==VS+VFP+V+VBP-1) v_cnt <= 0; - else v_cnt <= v_cnt + 1; - - // generate positive vsync signal - if(v_cnt == V+VFP) vs <= 1'b1; - if(v_cnt == V+VFP+VS) vs <= 1'b0; - - last_mode_v <= mode; - - // synchronize to input mode - // end of mode 01 (vblank) - // make and offset of - 4 for the 4 line delay of the scandoubler - if((mode != 2'b01) && (last_mode_v == 2'b01)) - v_cnt <= 616-4; - end -end - -// ------------------------------------------------------------------------------- -// ------------------------------- pixel generator ------------------------------- -// ------------------------------------------------------------------------------- -reg blank; -reg [1:0] pixel_reg; -reg [7:0] shift_reg_rptr; - -always@(posedge pclk) begin - // visible area? - if((v_cnt < V) && (h_cnt < H)) begin - blank <= 1'b0; - pixel_reg <= shift_reg[{!p_toggle, shift_reg_rptr}]; - shift_reg_rptr <= shift_reg_rptr + 8'd1; - end else begin - blank <= 1'b1; - shift_reg_rptr <= 8'd0; - end -end - -//wire [1:0] pixel = on?pixel_reg:2'b00; -wire [1:0] pixel = on? (pixel_reg ^ {inv,inv}) :2'b00; - -// gameboy "color" palette -wire [5:0] yellow_r = (pixel==0)?6'b100111:(pixel==1)?6'b100000: // 1:100011 - (pixel==2)?6'b001100:6'b000111; -wire [5:0] yellow_g = (pixel==0)?6'b101111:(pixel==1)?6'b101000: // 1:101011 - (pixel==2)?6'b011001:6'b000100; -wire [5:0] yellow_b = (pixel==0)?6'b000100:(pixel==1)?6'b000010: // 1:000100 - (pixel==2)?6'b001100:6'b000100; - -// greyscale -wire [5:0] grey = (pixel==0)?6'd63:(pixel==1)?6'd42:(pixel==2)?6'd24:6'd0; - -assign r = blank?6'b000000:tint?yellow_r:grey; -assign g = blank?6'b000000:tint?yellow_g:grey; -assign b = blank?6'b000000:tint?yellow_b:grey; - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/osd.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/osd.sv deleted file mode 100644 index c62c10af..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/osd.sv +++ /dev/null @@ -1,179 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [7:0] osd_byte; -always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; - -wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/pll.v b/Console_MiST/Nintendo - Gameboy_MiST/rtl/pll.v deleted file mode 100644 index 47c2b50d..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/pll.v +++ /dev/null @@ -1,421 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: pll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.0 Build 162 10/23/2013 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2013 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module pll ( - inclk0, - c0, - c1, - c2, - c3, - c4, - locked); - - input inclk0; - output c0; - output c1; - output c2; - output c3; - output c4; - output locked; - - wire [4:0] sub_wire0; - wire sub_wire3; - wire [0:0] sub_wire9 = 1'h0; - wire [4:4] sub_wire6 = sub_wire0[4:4]; - wire [2:2] sub_wire5 = sub_wire0[2:2]; - wire [0:0] sub_wire4 = sub_wire0[0:0]; - wire [3:3] sub_wire2 = sub_wire0[3:3]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; - wire c3 = sub_wire2; - wire locked = sub_wire3; - wire c0 = sub_wire4; - wire c2 = sub_wire5; - wire c4 = sub_wire6; - wire sub_wire7 = inclk0; - wire [1:0] sub_wire8 = {sub_wire9, sub_wire7}; - - altpll altpll_component ( - .inclk (sub_wire8), - .clk (sub_wire0), - .locked (sub_wire3), - .activeclock (), - .areset (1'b0), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b0), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbmimicbidir (), - .fbout (), - .fref (), - .icdrclk (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 62, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 77, - altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 62, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 77, - altpll_component.clk1_phase_shift = "-2500", - altpll_component.clk2_divide_by = 130, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 77, - altpll_component.clk2_phase_shift = "0", - altpll_component.clk3_divide_by = 260, - altpll_component.clk3_duty_cycle = 50, - altpll_component.clk3_multiply_by = 77, - altpll_component.clk3_phase_shift = "0", - altpll_component.clk4_divide_by = 520, - altpll_component.clk4_duty_cycle = 50, - altpll_component.clk4_multiply_by = 77, - altpll_component.clk4_phase_shift = "0", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 37037, - altpll_component.intended_device_family = "Cyclone III", - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_UNUSED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_USED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", - altpll_component.port_clk3 = "PORT_USED", - altpll_component.port_clk4 = "PORT_USED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena2 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED", - altpll_component.self_reset_on_loss_lock = "OFF", - altpll_component.width_clock = 5; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "62" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "62" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "130" -// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "260" -// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "520" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "33.532257" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "33.532257" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "15.992308" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "7.996154" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "3.998077" -// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" -// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "77" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "77" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "77" -// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "77" -// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "77" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "33.55714300" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "33.55714300" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "16.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "8.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "4.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" -// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2500.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps" -// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" -// Retrieval info: PRIVATE: USE_CLK3 STRING "1" -// Retrieval info: PRIVATE: USE_CLK4 STRING "1" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" -// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "62" -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "77" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "62" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "77" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2500" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "130" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "77" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "260" -// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "77" -// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "520" -// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "77" -// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 -// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 -// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf -// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/sdram.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/sdram.sv deleted file mode 100644 index 5af8c5cd..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/sdram.sv +++ /dev/null @@ -1,150 +0,0 @@ -// -// sdram.v -// -// sdram controller implementation for the MiST board -// https://github.com/mist-devel -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module sdram ( - - // interface to the MT48LC16M16 chip - inout [15:0] sd_data, // 16 bit bidirectional data bus - output reg [12:0] sd_addr, // 13 bit multiplexed address bus - output reg [1:0] sd_dqm, // two byte masks - output reg[1:0] sd_ba, // two banks - output sd_cs, // a single chip select - output sd_we, // write enable - output sd_ras, // row address select - output sd_cas, // columns address select - - // cpu/chipset interface - input init, // init signal after FPGA config to initialize RAM - input clk, // sdram is accessed at up to 128MHz - input clkref, // reference clock to sync to - - input [15:0] din, // data input from chipset/cpu - output [15:0] dout, // data output to chipset/cpu - input [23:0] addr, // 24 bit word address - input [1:0] ds, // data strobe for hi/low byte - input oe, // cpu/chipset requests read - input we // cpu/chipset requests write -); - -// no burst configured -localparam RASCAS_DELAY = 3'd3; // tRCD>=20ns -> 2 cycles@64MHz -localparam BURST_LENGTH = 3'b000; // 000=none, 001=2, 010=4, 011=8 -localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved -localparam CAS_LATENCY = 3'd3; // 2/3 allowed -localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed -localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write - -localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; - -// --------------------------------------------------------------------- -// ------------------------ cycle state machine ------------------------ -// --------------------------------------------------------------------- - -localparam STATE_IDLE = 3'd0; // first state in cycle -localparam STATE_CMD_START = 3'd1; // state in which a new command can be started -localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY - 3'd1; // 4 command can be continued -localparam STATE_LAST = 3'd7; // last state in cycle - -reg [2:0] q; -always @(posedge clk) begin - // 32Mhz counter synchronous to 4 Mhz clock - // force counter to pass state 5->6 exactly after the rising edge of clkref - // since clkref is two clocks early - if(((q == 7) && ( clkref == 0)) || - ((q == 0) && ( clkref == 1)) || - ((q != 7) && (q != 0))) - q <= q + 3'd1; -end - -// --------------------------------------------------------------------- -// --------------------------- startup/reset --------------------------- -// --------------------------------------------------------------------- - -// wait 1ms (32 clkref cycles) after FPGA config is done before going -// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) -reg [4:0] reset; -always @(posedge clk) begin - if(init) reset <= 5'h1f; - else if((q == STATE_LAST) && (reset != 0)) - reset <= reset - 5'd1; -end - -// --------------------------------------------------------------------- -// ------------------ generate ram control signals --------------------- -// --------------------------------------------------------------------- - -// all possible commands -localparam CMD_INHIBIT = 4'b1111; -localparam CMD_NOP = 4'b0111; -localparam CMD_ACTIVE = 4'b0011; -localparam CMD_READ = 4'b0101; -localparam CMD_WRITE = 4'b0100; -localparam CMD_BURST_TERMINATE = 4'b0110; -localparam CMD_PRECHARGE = 4'b0010; -localparam CMD_AUTO_REFRESH = 4'b0001; -localparam CMD_LOAD_MODE = 4'b0000; - -reg [3:0] sd_cmd; // current command sent to sd ram - -// drive control signals according to current command -assign sd_cs = sd_cmd[3]; -assign sd_ras = sd_cmd[2]; -assign sd_cas = sd_cmd[1]; -assign sd_we = sd_cmd[0]; - -assign sd_data = we?din:16'bZZZZZZZZZZZZZZZZ; - -assign dout = sd_data; - -always @(posedge clk) begin - sd_cmd <= CMD_INHIBIT; - - if(reset != 0) begin - sd_ba <= 2'b00; - sd_dqm <= 2'b00; - - if(reset == 13) sd_addr <= 13'b0010000000000; - else sd_addr <= MODE; - - if(q == STATE_IDLE) begin - if(reset == 13) sd_cmd <= CMD_PRECHARGE; - if(reset == 2) sd_cmd <= CMD_LOAD_MODE; - end - end else begin - if(q <= STATE_CMD_START) begin - sd_addr <= addr[20:8]; - sd_ba <= addr[22:21]; - sd_dqm <= { !ds[1], !ds[0] }; - end else - sd_addr <= { 4'b0010, addr[23], addr[7:0]}; - - if(q == STATE_IDLE) begin - if(we || oe) sd_cmd <= CMD_ACTIVE; - else sd_cmd <= CMD_AUTO_REFRESH; - end else if(q == STATE_CMD_CONT) begin - if(we) sd_cmd <= CMD_WRITE; - else if(oe) sd_cmd <= CMD_READ; - end - end -end - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/sprite.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/sprite.sv deleted file mode 100644 index 81ed82f8..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/sprite.sv +++ /dev/null @@ -1,107 +0,0 @@ -// -// sprite.v -// -// Gameboy for the MIST board https://github.com/mist-devel -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module sprite ( - input clk, - input size16, - - input [7:0] v_cnt, - input [7:0] h_cnt, - - output [7:0] x, - - // interface to read pixel data from memory - output [10:0] addr, - input [1:0] ds, - input [7:0] data, - - output pixel_active, - output pixel_cmap, - output pixel_prio, - output [1:0] pixel_data, - - input oam_wr, - input [1:0] oam_addr, - input [7:0] oam_di, - output [7:0] oam_do -); - -// x position for priority detection. Invisible sprites are far to the right and -// have minimum priority -assign x = v_visible?x_pos:8'hff; - -// register used to store pixel data for current line -reg [7:0] data0; -reg [7:0] data1; - -always @(posedge clk) begin - if(ds[0]) data0 <= data; - if(ds[1]) data1 <= data; -end - -wire [7:0] height = size16?8'd16:8'd8; - -wire v_visible = (v_cnt + 8'd16 >= y_pos) && (v_cnt + 8'd16 < y_pos + height); -wire visible = v_visible && (h_cnt + 8'd8 >= x_pos) && (h_cnt < x_pos); - -// x position within sprite, mirror horizontally if required -wire [2:0] col_n = h_cnt - x_pos; -wire [2:0] col = flags[1]?col_n:~col_n; - -assign pixel_data = { data1[col], data0[col] }; -assign pixel_active = (pixel_data != 0) && visible; - -// y position within sprite, mirror vertically if required -wire [3:0] row_n = v_cnt - y_pos; -wire [3:0] row = flags[2]?~row_n:row_n; - -// 16 pixel tall sprites use one more rwo counter bit and the lsb -// of the tile index is ignored -wire [10:0] addr8 = { tile , row[2:0]}; -wire [10:0] addr16 = { tile[7:1] , row}; -assign addr = size16?addr16:addr8; - -assign pixel_cmap = flags[0]; -assign pixel_prio = flags[3]; - -reg [7:0] y_pos; -reg [7:0] x_pos; -reg [7:0] tile; -reg [3:0] flags; - -always @(posedge clk) begin - if(oam_wr) begin - case(oam_addr) - 0: y_pos <= oam_di; - 1: x_pos <= oam_di; - 2: tile <= oam_di; - 3: flags <= oam_di[7:4]; - endcase - end -end - -assign oam_do = - (oam_addr == 0)?y_pos: - (oam_addr == 1)?x_pos: - (oam_addr == 2)?tile: - { flags, 4'h0 }; - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/sprite_sort.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/sprite_sort.sv deleted file mode 100644 index a3626eee..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/sprite_sort.sv +++ /dev/null @@ -1,100 +0,0 @@ -// -// sprite_sort.v -// -// Gameboy for the MIST board https://github.com/mist-devel -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module sprite_sort #( - parameter WIDTH = 40 -)( - // system signals - input clk, - input load, - - // sort - input [8*WIDTH-1:0] x, - output [6*WIDTH-1:0] idx -); - -wire [7:0] in [WIDTH-1:0]; - -generate -genvar i; - -// map 1d input array onto 2d work array -// and 2d result array into 1d output array -for(i=0;i values[2*i+1]; - assign int_val[2*i+0] = swap0[i]?values[2*i+1]:values[2*i+0]; - assign int_val[2*i+1] = swap0[i]?values[2*i+0]:values[2*i+1]; - assign int_idx[2*i+0] = swap0[i]?index[2*i+1]:index[2*i+0]; - assign int_idx[2*i+1] = swap0[i]?index[2*i+0]:index[2*i+1]; - end - - // 2nd stage - assign sort_val[0] = int_val[0]; - assign sort_idx[0] = int_idx[0]; - assign sort_val[WIDTH-1] = int_val[WIDTH-1]; - assign sort_idx[WIDTH-1] = int_idx[WIDTH-1]; - for(i=0;i int_val[2*i+2]; - assign sort_val[2*i+1] = swap1[i]?int_val[2*i+2]:int_val[2*i+1]; - assign sort_val[2*i+2] = swap1[i]?int_val[2*i+1]:int_val[2*i+2]; - assign sort_idx[2*i+1] = swap1[i]?int_idx[2*i+2]:int_idx[2*i+1]; - assign sort_idx[2*i+2] = swap1[i]?int_idx[2*i+1]:int_idx[2*i+2]; - end - - for(i=0;i -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module sprites ( - input clk, - input size16, - - // pixel position input which the current pixel is generated for - input [7:0] v_cnt, - input [7:0] h_cnt, - - // pixel output - output pixel_active, // current pixel - output [1:0] pixel_data, - output pixel_cmap, - output pixel_prio, - - input sort, - input [3:0] index, // index of sprite which video wants to read data for - output [10:0] addr, - input [1:0] dvalid, - input [7:0] data, - - // oam memory interface - input oam_wr, - input [7:0] oam_addr, - input [7:0] oam_di, - output [7:0] oam_do -); - -localparam SPRITES = 40; - -// ------------------------------------------------------------------------ -// ---------------------------- priority sorting -------------------------- -// ------------------------------------------------------------------------ - -// sprites have priority from left to right and the leftmost 10 are -// being displayed. We thus need to sort them -wire [SPRITES*8-1:0] sprite_x; -wire [SPRITES*6-1:0] sprite_idx; - -sprite_sort #(.WIDTH(SPRITES)) sprite_sort ( - .clk ( clk ), - .load ( sort ), // begin of oam phase - .x ( sprite_x ), - .idx ( sprite_idx ) -); - -wire [SPRITES-1:0] sprite_pixel_active; -wire [SPRITES-1:0] sprite_pixel_cmap; -wire [SPRITES-1:0] sprite_pixel_prio; -wire [1:0] sprite_pixel_data [SPRITES-1:0]; - -wire [10:0] sprite_addr [SPRITES-1:0]; -wire [7:0] sprite_oam_do [SPRITES-1:0]; - -assign oam_do = sprite_oam_do[oam_addr[7:2]]; - -// address where the sprite wants to read data from -wire [5:0] sprite_idx_array [SPRITES-1:0]; -wire [5:0] prio_index = sprite_idx_array[index]; -assign addr = sprite_addr[prio_index]; - - -generate -genvar i; -for(i=0;i WR_n active in T3, /=0 => WR_n active in T2 - IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CLKEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end GBse; - -architecture rtl of GBse is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - -begin - - u0 : T80 - generic map - ( - Mode => 3, - IOWait => IOWait, - Flag_S => 0, - Flag_P => 0, - Flag_X => 0, - Flag_Y => 0, - Flag_C => 4, - Flag_H => 5, - Flag_N => 6, - Flag_Z => 7 - ) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80.vhd b/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80.vhd deleted file mode 100644 index 1ea66542..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80.vhd +++ /dev/null @@ -1,1088 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems --- --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - signal XYbit_undoc : std_logic; - - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - XY_State => XY_State, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write, - XYbit_undoc => XYbit_undoc); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if Mode = 3 then - IStatus <= "10"; - elsif IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - if XYbit_undoc='1' then - DO <= ALU_Q; - end if; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusA <= "--------"; - end case; - if XYbit_undoc='1' then - BusA <= DI_Reg; - BusB <= DI_Reg; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - Auto_Wait_t1 <= Auto_Wait; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then - - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_ALU.vhd b/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_ALU.vhd deleted file mode 100644 index 95c98dab..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_ALU.vhd +++ /dev/null @@ -1,371 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - - -- bug fix - parity flag is just parity for 8080, also overflow for Z80 - process (Carry_v, Carry7_v, Q_v) - begin - if(Mode=2) then - OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor - Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else - OverFlow_v <= Carry_v xor Carry7_v; - end if; - end process; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; -end; diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_MCode.vhd b/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_MCode.vhd deleted file mode 100644 index 22e6ef99..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_MCode.vhd +++ /dev/null @@ -1,2026 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 302 fixed IO cycle timing, tested thanks to Alessandro. --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes - --- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - XYbit_undoc <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - --I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - if mode = 3 then - MCycles <= "011"; - else - MCycles <= "101"; - end if; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - IORQ <= '1'; --TH must be earlier to be stable when address is generated - when 2 => - Write <= '1'; ---TH this is too late IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - IORQ <= '1'; --TH must be earlier to be stable when address is generated - when 2 => - Read_To_Acc <= '1'; ---TH this is too late IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- R/S (IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if XY_State="00" then - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - else - -- BIT b,(IX+d), undocumented - MCycles <= "010"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => null; - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- SET b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if XY_State="00" then - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - else - -- RES b,(IX+d),Reg, undocumented - MCycles <= "011"; - XYbit_undoc <= '1'; - case to_integer(unsigned(MCycle)) is - when 1 | 7=> - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end if; - - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => null; - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - -- note B is decremented AFTER being put on the bus - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "1010"; - IncDec_16 <= "1110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - -- note B is decremented BEFORE being put on the bus. - -- mikej fix for hl inc - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - IncDec_16 <= "0110"; -- mikej - else - IncDec_16 <= "1110"; -- mikej - end if; - TStates <= "100"; -- MIKEJ should be 4 for IO cycle - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_Pack.vhd b/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_Pack.vhd deleted file mode 100644 index 907db408..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_Pack.vhd +++ /dev/null @@ -1,228 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - XY_State : in std_logic_vector(1 downto 0); - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - XYbit_undoc : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_Reg.vhd b/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_Reg.vhd deleted file mode 100644 index 1c0f2638..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/t80/T80_Reg.vhd +++ /dev/null @@ -1,114 +0,0 @@ --- **** --- T80(b) core. In an effort to merge and maintain bug fixes .... --- --- --- Ver 300 started tidyup --- MikeJ March 2005 --- Latest version from www.fpgaarcade.com (original www.opencores.org) --- --- **** --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/timer.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/timer.sv deleted file mode 100644 index 23d5999c..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/timer.sv +++ /dev/null @@ -1,103 +0,0 @@ -// -// timer.v -// -// Gameboy for the MIST board https://github.com/mist-devel -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module timer ( - input reset, - input clk, // 4 Mhz cpu clock - - output reg irq, - - // cpu register interface - input cpu_sel, - input [1:0] cpu_addr, - input cpu_wr, - input [7:0] cpu_di, - output [7:0] cpu_do -); - -// input: 4Mhz -// clk_div[0] = 2Mhz -// clk_div[1] = 1Mhz -// clk_div[2] = 524khz -// clk_div[3] = 262khz -// clk_div[4] = 131khz -// clk_div[5] = 65khz -// clk_div[6] = 32khz -// clk_div[7] = 16khz -// clk_div[8] = 8khz -// clk_div[9] = 4khz - -reg [9:0] clk_div; -always @(posedge clk) - clk_div <= clk_div + 10'd1; - -reg [7:0] div; -reg [7:0] tma; -reg [7:0] tima; -reg [2:0] tac; - -always @(posedge clk) begin - if(reset) begin - tima <= 8'h00; - tma <= 8'h00; - tac <= 8'h00; - irq <= 1'b0; - end else begin - irq <= 1'b0; - - if(clk_div[7:0] == 0) // 16kHz - div <= div + 8'd1; - - // timer enabled? - if(tac[2]) begin - // timer frequency - if(((tac[1:0] == 2'b00) && (clk_div[9:0] == 0)) || // 4 khz - ((tac[1:0] == 2'b01) && (clk_div[3:0] == 0)) || // 262 khz - ((tac[1:0] == 2'b10) && (clk_div[5:0] == 0)) || // 65 khz - ((tac[1:0] == 2'b11) && (clk_div[7:0] == 0))) begin // 16 khz - - if(tima != 8'hff) - tima <= tima + 8'd1; - else begin - irq <= 1'b1; // irq when timer overflows - tima <= tma; // reload timer - end - end - end - - if(cpu_sel && cpu_wr) begin - case(cpu_addr) - 2'b00: div <= 8'h00; // writing clears counter - 2'b01: tima <= cpu_di; - 2'b10: tma <= cpu_di; - 2'b11: tac <= cpu_di[2:0]; - endcase - end - end -end - -assign cpu_do = - (cpu_addr == 2'b00)?div: - (cpu_addr == 2'b01)?tima: - (cpu_addr == 2'b10)?tma: - {5'b00000, tac}; - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/video.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/video.sv deleted file mode 100644 index 7a84f8b0..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/video.sv +++ /dev/null @@ -1,513 +0,0 @@ -// -// video.v -// -// Gameboy for the MIST board https://github.com/mist-devel -// -// Copyright (c) 2015 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module video ( - input reset, - input clk, // 4 Mhz cpu clock - - // cpu register adn oam interface - input cpu_sel_oam, - input cpu_sel_reg, - input [7:0] cpu_addr, - input cpu_wr, - input [7:0] cpu_di, - output [7:0] cpu_do, - - // output to lcd - output lcd_on, - output lcd_clkena, - output [1:0] lcd_data, - output reg irq, - - // vram connection - output [1:0] mode, - output vram_rd, - output [12:0] vram_addr, - input [7:0] vram_data, - - // dma connection - output dma_rd, - output [15:0] dma_addr, - input [7:0] dma_data -); - -localparam STAGE2 = 9'd250; // oam + disp + pause -localparam OAM_LEN = 80; - -wire sprite_pixel_active; -wire [1:0] sprite_pixel_data; -wire sprite_pixel_cmap; -wire sprite_pixel_prio; - -wire [7:0] oam_do; -wire [3:0] sprite_index = h_cnt[7:4]-(OAM_LEN/16); // memory io starts at h_cnt == 16 -wire [10:0] sprite_addr; - -// "data strobe" for the two bytes each sprite line consists of -wire [1:0] sprite_dvalid = { - (h_cnt[3:0] == 4'hf) && !vblank && !hblank, - (h_cnt[3:0] == 4'h7) && !vblank && !hblank }; - -sprites sprites ( - .clk ( clk ), - .size16 ( lcdc_spr_siz ), - - .v_cnt ( v_cnt ), - .h_cnt ( h_cnt-STAGE2 ), // sprites are added in second stage - .sort ( h_cnt == 0 ), // start of oam phase - - .pixel_active ( sprite_pixel_active ), - .pixel_data ( sprite_pixel_data ), - .pixel_cmap ( sprite_pixel_cmap ), - .pixel_prio ( sprite_pixel_prio ), - - .index ( sprite_index ), - .addr ( sprite_addr ), - .dvalid ( sprite_dvalid), - .data ( vram_data ), - - .oam_wr ( oam_wr ), - .oam_addr ( oam_addr ), - .oam_di ( oam_di ), - .oam_do ( oam_do ) -); - -// give dma access to oam -wire [7:0] oam_addr = dma_active?dma_addr[7:0]:cpu_addr; -wire oam_wr = dma_active?(dma_cnt[1:0] == 2):(cpu_wr && cpu_sel_oam); -wire [7:0] oam_di = dma_active?dma_data:cpu_di; - - -assign lcd_on = lcdc_on; - -// $ff40 LCDC -wire lcdc_on = lcdc[7]; -wire lcdc_win_tile_map_sel = lcdc[6]; -wire lcdc_win_ena = lcdc[5]; -wire lcdc_tile_data_sel = lcdc[4]; -wire lcdc_bg_tile_map_sel = lcdc[3]; -wire lcdc_spr_siz = lcdc[2]; -wire lcdc_spr_ena = lcdc[1]; -wire lcdc_bg_ena = lcdc[0]; -reg [7:0] lcdc; - -// ff41 STAT -reg [7:0] stat; - -// ff42, ff43 background scroll registers -reg [7:0] scy; -reg [7:0] scy_r; // stable over entire image -reg [7:0] scx; -reg [7:0] scx_r; // stable over line - -// ff44 line counter -reg [7:0] ly; - -// ff45 line counter compare -wire lyc_match = (ly == lyc); -reg [7:0] lyc; - -reg [7:0] bgp; -reg [7:0] obp0; -reg [7:0] obp1; - -reg [7:0] wy; -reg [7:0] wy_r; // stable over entire image -reg [7:0] wx; -reg [7:0] wx_r; // stable over line - -// -------------------------------------------------------------------- -// ----------------------------- DMA engine --------------------------- -// -------------------------------------------------------------------- - -assign dma_addr = { dma, dma_cnt[9:2] }; -assign dma_rd = dma_active; - -reg dma_active; -reg [7:0] dma; -reg [9:0] dma_cnt; // dma runs 4*160 clock cycles = 160us @ 4MHz -always @(posedge clk) begin - if(reset) - dma_active <= 1'b0; - else begin - // writing the dma register engages the dma engine - if(cpu_sel_reg && cpu_wr && (cpu_addr[3:0] == 4'h6)) begin - dma_active <= 1'b1; - dma_cnt <= 10'd0; - end else if(dma_cnt != 160*4-1) - dma_cnt <= dma_cnt + 10'd1; - else - dma_active <= 1'b0; - end -end - -// -------------------------------------------------------------------- -// ------------------------------- IRQs ------------------------------- -// -------------------------------------------------------------------- - -always @(posedge clk) begin - irq <= 1'b0; - - // lyc=ly coincidence - if(stat[6] && (h_cnt == 0) && lyc_match) - irq <= 1'b1; - - // begin of oam phase - if(stat[5] && (h_cnt == 0)) - irq <= 1'b1; - - // begin of vblank - if(stat[4] && (h_cnt == 455) && (v_cnt == 143)) - irq <= 1'b1; - - // begin of hblank - if(stat[3] && (h_cnt == OAM_LEN + 160 + hextra)) - irq <= 1'b1; -end - -// -------------------------------------------------------------------- -// --------------------- CPU register interface ----------------------- -// -------------------------------------------------------------------- - -always @(posedge clk) begin - if(reset) begin - lcdc <= 8'h00; // screen must be off since dmg rom writes to vram - scy <= 8'h00; - scx <= 8'h00; - wy <= 8'h00; - wx <= 8'h00; - bgp <= 8'hfc; - obp0 <= 8'hff; - obp1 <= 8'hff; - end else begin - if(cpu_sel_reg && cpu_wr) begin - case(cpu_addr[3:0]) - 4'h0: lcdc <= cpu_di; - 4'h1: stat <= cpu_di; - 4'h2: scy <= cpu_di; - 4'h3: scx <= cpu_di; - // a write to 4 is supposed to reset the v_cnt - 4'h5: lyc <= cpu_di; - 4'h6: dma <= cpu_di; - 4'h7: bgp <= cpu_di; - 4'h8: obp0 <= cpu_di; - 4'h9: obp1 <= cpu_di; - 4'ha: wy <= cpu_di; - 4'hb: wx <= cpu_di; - endcase - end - end -end - -assign cpu_do = - cpu_sel_oam?oam_do: - (cpu_addr[3:0] == 4'h0)?lcdc: - (cpu_addr[3:0] == 4'h1)?{stat[7:3], lyc_match, mode}: - (cpu_addr[3:0] == 4'h2)?scy: - (cpu_addr[3:0] == 4'h3)?scx: - (cpu_addr[3:0] == 4'h4)?ly: - (cpu_addr[3:0] == 4'h5)?lyc: - (cpu_addr[3:0] == 4'h6)?dma: - (cpu_addr[3:0] == 4'h7)?bgp: - (cpu_addr[3:0] == 4'h8)?obp0: - (cpu_addr[3:0] == 4'h9)?obp1: - (cpu_addr[3:0] == 4'ha)?wy: - (cpu_addr[3:0] == 4'hb)?wx: - 8'hff; - -// -------------------------------------------------------------------- -// ----------------- second output stage: sprites --------------------- -// -------------------------------------------------------------------- - -assign lcd_data = stage2_data; -assign lcd_clkena = stage2_clkena; - -reg [1:0] stage2_data; -reg stage2_clkena; - -reg [1:0] stage2_buffer [159:0]; -reg [7:0] stage2_wptr; -reg [7:0] stage2_rptr; - -// apply bg palette -wire [1:0] stage2_bg_pix = (!lcdc_bg_ena && !window_ena)?2'b11: // background off? - (stage2_buffer[stage2_rptr] == 2'b00)?bgp[1:0]: - (stage2_buffer[stage2_rptr] == 2'b01)?bgp[3:2]: - (stage2_buffer[stage2_rptr] == 2'b10)?bgp[5:4]: - bgp[7:6]; - -// apply sprite palette -wire [7:0] obp = sprite_pixel_cmap?obp1:obp0; -wire [1:0] sprite_pix = - (sprite_pixel_data == 2'b00)?obp[1:0]: - (sprite_pixel_data == 2'b01)?obp[3:2]: - (sprite_pixel_data == 2'b10)?obp[5:4]: - obp[7:6]; - -// a sprite pixel is visible if -// - sprites are enabled -// - there's a sprite at the current position -// - the sprites prioroty bit is 0, or -// - the prites priority is 1 and the backrgound color is 00 - -wire sprite_pixel_visible = - sprite_pixel_active && lcdc_spr_ena && - ((!sprite_pixel_prio) || (stage2_buffer[stage2_rptr] == 2'b00)); - -always @(posedge clk) begin - if(h_cnt == 455) begin - stage2_wptr <= 8'h00; - stage2_rptr <= 8'h00; - end - - if(stage1_clkena) begin - stage2_buffer[stage2_wptr] <= stage1_data; - stage2_wptr <= stage2_wptr + 8'd1; - end - - stage2_clkena = !vblank && stage2; - if(stage2) begin - // mix sprites and bg - if(sprite_pixel_visible) stage2_data <= sprite_pix; - else stage2_data <= stage2_bg_pix; - - stage2_rptr <= stage2_rptr + 8'd1; - end -end - -// -------------------------------------------------------------------- -// --------------- first output stage: bg and window ------------------ -// -------------------------------------------------------------------- - -reg window_ena; - -// output shift registers for both video data bits -reg [7:0] tile_shift_0; -reg [7:0] tile_shift_1; - -reg [7:0] bg_tile; -reg [7:0] bg_tile_data0; -reg [7:0] bg_tile_data1; - -wire stage1_clkena = !vblank && hdvalid; -wire [1:0] stage1_data = { tile_shift_1[7], tile_shift_0[7] }; - -// read data half a clock cycle after ram has been selected -always @(posedge clk) begin - - // every memory access is two pixel cycles - if(h_cnt[0]) begin - if(bg_tile_map_rd) bg_tile <= vram_data; - if(bg_tile_data0_rd) bg_tile_data0 <= vram_data; - if(bg_tile_data1_rd) bg_tile_data1 <= vram_data; - // sprite data is evaluated inside the sprite engine - end - - // shift bg/window pixels out - if(bg_tile_obj_rd && h_cnt[0]) begin - tile_shift_0 <= bg_tile_data0; - tile_shift_1 <= bg_tile_data1; - end else begin - tile_shift_0 <= { tile_shift_0[6:0], 1'b0 }; - tile_shift_1 <= { tile_shift_1[6:0], 1'b0 }; - end -end - -assign vram_rd = lcdc_on && (bg_tile_map_rd || bg_tile_data0_rd || - bg_tile_data1_rd || bg_tile_obj_rd); - -wire bg_tile_a12 = !lcdc_tile_data_sel?(~bg_tile[7]):1'b0; - -wire tile_map_sel = window_ena?lcdc_win_tile_map_sel:lcdc_bg_tile_map_sel; - -assign vram_addr = - bg_tile_map_rd?{2'b11, tile_map_sel, bg_tile_map_addr}: - bg_tile_data0_rd?{bg_tile_a12, bg_tile, tile_line, 1'b0}: - bg_tile_data1_rd?{bg_tile_a12, bg_tile, tile_line, 1'b1}: - {1'b0, sprite_addr, h_cnt[3]}; - -reg [9:0] bg_tile_map_addr; - -wire vblank = (v_cnt >= 144); - -// x scroll & 7 needs one more memory read per line -reg [1:0] hextra_tiles; -wire [7:0] hextra = { 3'b000, hextra_tiles, 3'b000 }; -wire hblank = ((h_cnt < OAM_LEN) || (h_cnt >= 160+OAM_LEN+hextra)); -wire oam = (h_cnt < OAM_LEN); // 80 clocks oam -wire stage2 = ((h_cnt >= STAGE2) && (h_cnt < STAGE2+160)); // output out of stage2 - -// first valid pixels are delivered 8 clocks after end of hblank -// wire hdvalid = ((h_cnt >= OAM_LEN+8) && (h_cnt < 160+OAM_LEN+8)); -wire hdvalid = de; - -reg de; -reg [7:0] skip; -reg [7:0] pcnt; - -localparam STATE_HBLANK = 0; -localparam STATE_OAM = 1; -localparam STATE_ACTIVE = 2; - -always @(negedge clk) begin - if(h_cnt == 455) begin - // end of line - - de <= 1'b0; - hextra_tiles <= 2'd0; - pcnt <= 8'd0; - skip <= 8'd0; - end else if(h_cnt == OAM_LEN) begin - // start of line - - // skip entire oam time plus time until first data is delivered plus - // time to skip the pixels according to the horizontal scroll position - // (or the window start if line starts with window) - if(lcdc_win_ena && (v_cnt >= wy_r) && (wx_r < 8)) - skip <= 8'd8 + (8'd7 - wx_r) - 8'd1; - else - skip <= 8'd8 + scx_r[2:0] - 8'd1; - - // calculate how many extra tiles will have to be read in this line - if(lcdc_win_ena && (v_cnt >= wy_r) && (wx_r < 168)) begin - // window needs at least one extra cycle, two if bg scroll position or - // window are not 8 pixel aligned - if((wx_r[2:0] != 3'd7) || (scx_r[2:0] != 3'd0)) begin - if(wx_r[2:0] > ~scx_r[2:0]) - hextra_tiles <= 2'd3; - else - hextra_tiles <= 2'd2; - end else - hextra_tiles <= 2'd1; - end else - if(scx_r[2:0] != 3'd0) - hextra_tiles <= 2'd1; - end else begin - if(win_start) begin - // if window starts skip until end of current cycle and skip - // pixels until new window data is ready - skip <= { 5'b00000 ,~h_cnt[2:0] } + 8'd8; - de <= 1'b0; - end - - if(skip) skip <= skip - 8'd1; - - // (re-)enable display at the end of the wait phase - if(skip == 1) - de <= 1'b1; - - if(de) begin - if(pcnt != 160) - pcnt <= pcnt + 8'd1; - else - de <= 1'b0; - end - end -end - -// cycle through the B01s states -wire bg_tile_map_rd = (!vblank) && (!hblank) && (h_cnt[2:1] == 2'b00); -wire bg_tile_data0_rd = (!vblank) && (!hblank) && (h_cnt[2:1] == 2'b01); -wire bg_tile_data1_rd = (!vblank) && (!hblank) && (h_cnt[2:1] == 2'b10); -wire bg_tile_obj_rd = (!vblank) && (!hblank) && (h_cnt[2:1] == 2'b11); - -// Mode 00: h-blank -// Mode 01: v-blank -// Mode 10: oam -// Mode 11: oam and vram -assign mode = - vblank?2'b01: - oam?2'b10: - hblank?2'b00: - 2'b11; - -reg [8:0] h_cnt; // max 455 -reg [7:0] v_cnt; // max 153 - -// line inside the background/window currently being drawn -wire [7:0] win_line = v_cnt - wy_r; -wire [7:0] bg_line = v_cnt + scy_r; -wire [2:0] tile_line = window_ena?win_line[2:0]:bg_line[2:0]; - -wire win_start = lcdc_win_ena && (v_cnt >= wy_r) && de && (wx_r >= 7) && (pcnt == wx_r-8); - -// each memory access takes two cycles -always @(negedge clk) begin - // this ly change h_cnt is wrong!!! - if(h_cnt == 0) - ly <= (v_cnt >= 153)?(v_cnt-8'd153):(v_cnt+8'd1); - - if(h_cnt != 455) begin - h_cnt <= h_cnt + 9'd1; - - // make sure sginals don't change during the line - // latch at latest possible moment (one clock before display starts) - if(h_cnt == OAM_LEN-2) begin - scx_r <= scx; - wx_r <= wx; - scy_r <= scy; - end - - // increment address at the end of each 8-pixel-cycle. But don't - // increment while waiting for current cycle to end due to window start - if(!hblank && h_cnt[2:0] == 3'b111 && (skip <= 8)) - bg_tile_map_addr[4:0] <= bg_tile_map_addr[4:0] + 10'd1; - - // begin of line - if(h_cnt == OAM_LEN-1) begin - // set tile map address for this line, assume there is no window - bg_tile_map_addr[9:5] <= bg_line[7:3]; - bg_tile_map_addr[4:0] <= scx_r[7:3]; - - // special case wx < 8: line starts with window, no background - // visible at all - if(lcdc_win_ena && (v_cnt >= wy_r) && (wx_r < 8)) begin - window_ena <= 1'b1; - bg_tile_map_addr[9:5] <= win_line[7:3]; - bg_tile_map_addr[4:0] <= 5'd0; // window always start with its very left - end - end - - // check if the window starts here - if(win_start) begin - window_ena <= 1'b1; - bg_tile_map_addr[9:5] <= win_line[7:3]; - bg_tile_map_addr[4:0] <= 5'd0; // window always start with its very left - end - end else begin - window_ena <= 1'b0; // next line starts with background - - // end of line reached - h_cnt <= 9'd0; - - if(v_cnt != 153) - v_cnt <= v_cnt + 8'd1; - else begin - // start of new image - v_cnt <= 8'd0; - - // make sure sginals don't change during the image - wy_r <= wy; - end - end -end - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/video_mixer.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/video_mixer.sv deleted file mode 100644 index 04cfd4ba..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/video_mixer.sv +++ /dev/null @@ -1,242 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/vram.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/vram.sv deleted file mode 100644 index 1fe1f976..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/vram.sv +++ /dev/null @@ -1,172 +0,0 @@ -// megafunction wizard: %RAM: 1-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: vram.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.4 Build 182 03/12/2014 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2014 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module vram ( - address, - clock, - data, - wren, - q); - - input [12:0] address; - input clock; - input [7:0] data; - input wren; - output [7:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clock; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] q = sub_wire0[7:0]; - - altsyncram altsyncram_component ( - .address_a (address), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .q_a (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .address_b (1'b1), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b (1'b1), - .eccstatus (), - .q_b (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 8192, - altsyncram_component.operation_mode = "SINGLE_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_reg_a = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 13, - altsyncram_component.width_a = 8, - altsyncram_component.width_byteena_a = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -// Retrieval info: PRIVATE: AclrByte NUMERIC "0" -// Retrieval info: PRIVATE: AclrData NUMERIC "0" -// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: Clken NUMERIC "0" -// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -// Retrieval info: PRIVATE: RegAddr NUMERIC "1" -// Retrieval info: PRIVATE: RegData NUMERIC "1" -// Retrieval info: PRIVATE: RegOutput NUMERIC "0" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: SingleClock NUMERIC "1" -// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "13" -// Retrieval info: PRIVATE: WidthData NUMERIC "8" -// Retrieval info: PRIVATE: rden NUMERIC "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL vram.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL vram.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL vram.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL vram.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL vram_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL vram_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Console_MiST/Nintendo - Gameboy_MiST/rtl/zpram.sv b/Console_MiST/Nintendo - Gameboy_MiST/rtl/zpram.sv deleted file mode 100644 index 5714f7bf..00000000 --- a/Console_MiST/Nintendo - Gameboy_MiST/rtl/zpram.sv +++ /dev/null @@ -1,172 +0,0 @@ -// megafunction wizard: %RAM: 1-PORT% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altsyncram - -// ============================================================ -// File Name: zpram.v -// Megafunction Name(s): -// altsyncram -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.1.4 Build 182 03/12/2014 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2014 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module zpram ( - address, - clock, - data, - wren, - q); - - input [7:0] address; - input clock; - input [7:0] data; - input wren; - output [7:0] q; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri1 clock; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif - - wire [7:0] sub_wire0; - wire [7:0] q = sub_wire0[7:0]; - - altsyncram altsyncram_component ( - .address_a (address), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .q_a (sub_wire0), - .aclr0 (1'b0), - .aclr1 (1'b0), - .address_b (1'b1), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b (1'b1), - .eccstatus (), - .q_b (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_output_a = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 256, - altsyncram_component.operation_mode = "SINGLE_PORT", - altsyncram_component.outdata_aclr_a = "NONE", - altsyncram_component.outdata_reg_a = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 8, - altsyncram_component.width_a = 8, - altsyncram_component.width_byteena_a = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -// Retrieval info: PRIVATE: AclrByte NUMERIC "0" -// Retrieval info: PRIVATE: AclrData NUMERIC "0" -// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -// Retrieval info: PRIVATE: Clken NUMERIC "0" -// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MIFfilename STRING "" -// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -// Retrieval info: PRIVATE: RegAddr NUMERIC "1" -// Retrieval info: PRIVATE: RegData NUMERIC "1" -// Retrieval info: PRIVATE: RegOutput NUMERIC "0" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: SingleClock NUMERIC "1" -// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -// Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -// Retrieval info: PRIVATE: WidthData NUMERIC "8" -// Retrieval info: PRIVATE: rden NUMERIC "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" -// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" -// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" -// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 -// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL zpram.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL zpram.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL zpram.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL zpram.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL zpram_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL zpram_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf diff --git a/Console_MiST/Sega - Game Gear_TeST/Snapshot/SGG.rbf b/Console_MiST/Sega - Game Gear_TeST/Snapshot/SGG.rbf deleted file mode 100644 index d09dd65f..00000000 Binary files a/Console_MiST/Sega - Game Gear_TeST/Snapshot/SGG.rbf and /dev/null differ diff --git a/Console_MiST/Sega - SG1000/ReadMe.txt b/Console_MiST/Sega - SG1000/ReadMe.txt deleted file mode 100644 index 228701c4..00000000 --- a/Console_MiST/Sega - SG1000/ReadMe.txt +++ /dev/null @@ -1 +0,0 @@ -WIP not Working \ No newline at end of file diff --git a/Console_MiST/Sega - SG1000/Schematic/card.png b/Console_MiST/Sega - SG1000/Schematic/card.png deleted file mode 100644 index 253d9403..00000000 Binary files a/Console_MiST/Sega - SG1000/Schematic/card.png and /dev/null differ diff --git a/Console_MiST/Sega - SG1000/Schematic/sgcon.png b/Console_MiST/Sega - SG1000/Schematic/sgcon.png deleted file mode 100644 index 139213dd..00000000 Binary files a/Console_MiST/Sega - SG1000/Schematic/sgcon.png and /dev/null differ diff --git a/Console_MiST/Sega - SG1000/Schematic/sgcpu.png b/Console_MiST/Sega - SG1000/Schematic/sgcpu.png deleted file mode 100644 index 663c8d61..00000000 Binary files a/Console_MiST/Sega - SG1000/Schematic/sgcpu.png and /dev/null differ diff --git a/Console_MiST/Sega - SG1000/Schematic/sgio.png b/Console_MiST/Sega - SG1000/Schematic/sgio.png deleted file mode 100644 index 3d62c982..00000000 Binary files a/Console_MiST/Sega - SG1000/Schematic/sgio.png and /dev/null differ diff --git a/Console_MiST/Sega - SG1000/Schematic/sgjoy.png b/Console_MiST/Sega - SG1000/Schematic/sgjoy.png deleted file mode 100644 index 4d374b1a..00000000 Binary files a/Console_MiST/Sega - SG1000/Schematic/sgjoy.png and /dev/null differ diff --git a/Console_MiST/Sega - SG1000/Schematic/sgpsg.png b/Console_MiST/Sega - SG1000/Schematic/sgpsg.png deleted file mode 100644 index ee68df3d..00000000 Binary files a/Console_MiST/Sega - SG1000/Schematic/sgpsg.png and /dev/null differ diff --git a/Console_MiST/Sega - SG1000/Schematic/sgvdp.png b/Console_MiST/Sega - SG1000/Schematic/sgvdp.png deleted file mode 100644 index 06abf901..00000000 Binary files a/Console_MiST/Sega - SG1000/Schematic/sgvdp.png and /dev/null differ diff --git a/Console_MiST/Sega - SG1000/clean.bat b/Console_MiST/Sega - SG1000/clean.bat deleted file mode 100644 index 748b4d5b..00000000 --- a/Console_MiST/Sega - SG1000/clean.bat +++ /dev/null @@ -1,38 +0,0 @@ -@echo off -del /s *.bak -del /s *.orig -del /s *.rej -del /s *~ -rmdir /s /q db -rmdir /s /q incremental_db -rmdir /s /q output_files -rmdir /s /q simulation -rmdir /s /q greybox_tmp -rmdir /s /q hc_output -rmdir /s /q .qsys_edit -rmdir /s /q hps_isw_handoff -rmdir /s /q sys\.qsys_edit -rmdir /s /q sys\vip -cd sys -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -cd .. -for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" -del build_id.v -del c5_pin_model_dump.txt -del PLLJ_PLLSPE_INFO.txt -del /s *.qws -del /s *.ppf -del /s *.ddb -del /s *.csv -del /s *.cmp -del /s *.sip -del /s *.spd -del /s *.bsf -del /s *.f -del /s *.sopcinfo -del /s *.xml -del *.cdf -del *.rpt -del /s new_rtl_netlist -del /s old_rtl_netlist -pause diff --git a/Console_MiST/Sega - SG1000/rtl/SG1000_MiST.sv b/Console_MiST/Sega - SG1000/rtl/SG1000_MiST.sv deleted file mode 100644 index ba5ec49d..00000000 --- a/Console_MiST/Sega - SG1000/rtl/SG1000_MiST.sv +++ /dev/null @@ -1,155 +0,0 @@ -module SG1000_MiST( - input CLOCK_27, - output LED, - output VGA_HS, - output VGA_VS, - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - inout SPI_DO, - input SPI_DI, - input SPI_SCK, - input SPI_SS2, - input SPI_SS3, - input SPI_SS4, - input CONF_DATA0, - output AUDIO_L, - output AUDIO_R -); - -assign LED = ~ioctl_download; -`include "build_id.v" -localparam CONF_STR = -{ - "SG1000;BINSG ;", - "O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", - "O4,Video,NTSC,PAL;", - "O5,Pause,Off,On;", - "T6,Reset;", - "V,v1.0.",`BUILD_DATE -}; - -wire [1:0] buttons, switches; -wire [31:0] status; -wire ypbpr; -wire scandoubler_disable; -wire ps2_kbd_data, ps2_kbd_clk; -wire ioctl_ce; -wire ioctl_download; -wire [7:0] ioctl_index; -wire ioctl_wr; -wire [24:0] ioctl_addr; -wire [7:0] ioctl_dout; -wire [1:0] r, g, b; -wire hb, vb, hs, vs; -wire blankn = ~(hb | vb); -wire [5:0] audio; -wire [7:0] joystick_0, joystick_1; -wire clk_8, clk_16, clk_64; - -pll pll ( - .inclk0(CLOCK_27), - .c0(clk_64), - .c1(clk_16), - .c2(clk_8) - ); - -mist_io #( - .STRLEN($size(CONF_STR)>>3)) -user_io ( - .clk_sys(clk_64), - .CONF_DATA0(CONF_DATA0), - .SPI_SCK(SPI_SCK), - .SPI_DI(SPI_DI), - .SPI_DO(SPI_DO), - .SPI_SS2(SPI_SS2), - .conf_str(CONF_STR), - .ypbpr(ypbpr), - .status(status), - .scandoubler_disable(scandoubler_disable), - .buttons(buttons), - .switches(switches), - .ps2_kbd_clk(ps2_kbd_clk), - .ps2_kbd_data(ps2_kbd_data), - .joystick_0(joystick_0), - .joystick_1(joystick_1), - .ioctl_ce(1'b1), - .ioctl_wr(ioctl_wr), - .ioctl_index(ioctl_index), - .ioctl_download(ioctl_download), - .ioctl_addr(ioctl_addr), - .ioctl_dout(ioctl_dout) - ); - -video_mixer #( - .LINE_LENGTH(480), - .HALF_DEPTH(0)) -video_mixer ( - .clk_sys ( clk_64 ), - .ce_pix ( clk_16 ), - .ce_pix_actual ( clk_16 ), - .SPI_SCK ( SPI_SCK ), - .SPI_SS3 ( SPI_SS3 ), - .SPI_DI ( SPI_DI ), - .R (blankn ? {r,r,r} : "000000" ), - .G (blankn ? {g,g,g} : "000000" ), - .B (blankn ? {b,b,b} : "000000" ), - .HSync ( hs ), - .VSync ( vs ), - .VGA_R ( VGA_R ), - .VGA_G ( VGA_G ), - .VGA_B ( VGA_B ), - .VGA_VS ( VGA_VS ), - .VGA_HS ( VGA_HS ), - .scanlines (scandoubler_disable ? 2'b00 : {status[3:2] == 3, status[3:2] == 2}), - .scandoubler_disable(1'b1),//scandoubler_disable), - .hq2x (status[3:2]==1), - .ypbpr ( ypbpr ), - .ypbpr_full ( 1 ), - .line_start ( 0 ), - .mono ( 0 ) - ); - - -sg1000_top sg1000_top ( - .RESET_n(~(status[0] | status[6] | buttons[1])), - .sys_clk(clk_8), - .vdp_clk(clk_16), - .vid_clk(clk_64), - .pal(status[4]), - .pause(status[5]), - .ps2_kbd_clk(ps2_kbd_clk), - .ps2_kbd_data(ps2_kbd_data), -// .Cart_In(Cart_In), -// .Cart_Out(Cart_Out), -// .Cart_Addr(Cart_Addr), -// .Cart_We(Cart_We), - .audio(audio), - .vblank(vb), - .hblank(hb), - .vga_hs(hs), - .vga_vs(vs), - .vga_r(r), - .vga_g(g), - .vga_b(b), -// .rgb_r(r), -// .rgb_g(g), -// .rgb_b(b), -// .csync(vs), - .Joy_A(joystick_0[5:0]), - .Joy_B(joystick_1[5:0]) -); -//assign hs= 1'b1; - -dac #( - .msbi_g(5)) -dac ( - .clk_i(clk_64), - .res_i(1'b0), - .dac_i(audio), - .dac_o(AUDIO_L) - ); - -assign AUDIO_R = AUDIO_L; - -endmodule \ No newline at end of file diff --git a/Console_MiST/Sega - SG1000/rtl/TTL74_257.v b/Console_MiST/Sega - SG1000/rtl/TTL74_257.v deleted file mode 100644 index c557b072..00000000 --- a/Console_MiST/Sega - SG1000/rtl/TTL74_257.v +++ /dev/null @@ -1,90 +0,0 @@ - -module TTL74_257( - GN, - SEL, - B4, - A4, - B3, - A3, - B2, - A2, - B1, - A1, - Y4, - Y3, - Y2, - Y1 -); - - -input wire GN; -input wire SEL; -input wire B4; -input wire A4; -input wire B3; -input wire A3; -input wire B2; -input wire A2; -input wire B1; -input wire A1; -output wire Y4; -output wire Y3; -output wire Y2; -output wire Y1; - -wire SYNTHESIZED_WIRE_0; -wire SYNTHESIZED_WIRE_1; -wire SYNTHESIZED_WIRE_2; -wire SYNTHESIZED_WIRE_20; -wire SYNTHESIZED_WIRE_4; -wire SYNTHESIZED_WIRE_5; -wire SYNTHESIZED_WIRE_6; -wire SYNTHESIZED_WIRE_8; -wire SYNTHESIZED_WIRE_9; -wire SYNTHESIZED_WIRE_10; -wire SYNTHESIZED_WIRE_12; -wire SYNTHESIZED_WIRE_14; -wire SYNTHESIZED_WIRE_15; -wire SYNTHESIZED_WIRE_21; - - - - -assign SYNTHESIZED_WIRE_2 = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1; - -assign SYNTHESIZED_WIRE_1 = B1 & SEL; - -assign Y1 = SYNTHESIZED_WIRE_20 ? SYNTHESIZED_WIRE_2 : 1'bz; - -assign SYNTHESIZED_WIRE_6 = SYNTHESIZED_WIRE_4 | SYNTHESIZED_WIRE_5; - -assign Y2 = SYNTHESIZED_WIRE_20 ? SYNTHESIZED_WIRE_6 : 1'bz; - -assign SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_9; - -assign Y3 = SYNTHESIZED_WIRE_20 ? SYNTHESIZED_WIRE_10 : 1'bz; - -assign Y4 = SYNTHESIZED_WIRE_20 ? SYNTHESIZED_WIRE_12 : 1'bz; - -assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15; - -assign SYNTHESIZED_WIRE_20 = ~GN; - -assign SYNTHESIZED_WIRE_21 = ~SEL; - -assign SYNTHESIZED_WIRE_0 = A1 & SYNTHESIZED_WIRE_21; - -assign SYNTHESIZED_WIRE_4 = A2 & SYNTHESIZED_WIRE_21; - -assign SYNTHESIZED_WIRE_8 = A3 & SYNTHESIZED_WIRE_21; - -assign SYNTHESIZED_WIRE_14 = A4 & SYNTHESIZED_WIRE_21; - -assign SYNTHESIZED_WIRE_5 = B2 & SEL; - -assign SYNTHESIZED_WIRE_9 = B3 & SEL; - -assign SYNTHESIZED_WIRE_15 = B4 & SEL; - - -endmodule diff --git a/Console_MiST/Sega - SG1000/rtl/build_id.tcl b/Console_MiST/Sega - SG1000/rtl/build_id.tcl deleted file mode 100644 index 938515d8..00000000 --- a/Console_MiST/Sega - SG1000/rtl/build_id.tcl +++ /dev/null @@ -1,35 +0,0 @@ -# ================================================================================ -# -# Build ID Verilog Module Script -# Jeff Wiencrot - 8/1/2011 -# -# Generates a Verilog module that contains a timestamp, -# from the current build. These values are available from the build_date, build_time, -# physical_address, and host_name output ports of the build_id module in the build_id.v -# Verilog source file. -# -# ================================================================================ - -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] - - # Create a Verilog file for output - set outputFileName "rtl/build_id.v" - set outputFile [open $outputFileName "w"] - - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" -} - -# Comment out this line to prevent the process from automatically executing when the file is sourced: -generateBuildID_Verilog \ No newline at end of file diff --git a/Console_MiST/Sega - SG1000/rtl/build_id.v b/Console_MiST/Sega - SG1000/rtl/build_id.v deleted file mode 100644 index 9612c4d0..00000000 --- a/Console_MiST/Sega - SG1000/rtl/build_id.v +++ /dev/null @@ -1,2 +0,0 @@ -`define BUILD_DATE "181109" -`define BUILD_TIME "113105" diff --git a/Console_MiST/Sega - SG1000/rtl/cart.sv b/Console_MiST/Sega - SG1000/rtl/cart.sv deleted file mode 100644 index a7651254..00000000 --- a/Console_MiST/Sega - SG1000/rtl/cart.sv +++ /dev/null @@ -1,58 +0,0 @@ -module cart( -input clk_cpu, - input DSRAM_n, - input EXM1_n, - input RD_n, - input WR_n, - input RFSH_n, - input MREQ_n, - output CON, - input EXM2_n, - input M1_n, - input [14:0] Cart_Addr, - input [7:0] Cart_In, - input [7:0] Cart_Ram_In, - output [7:0] Cart_Ram_Out, - output [7:0] Cart_Rom_Out, - input Cart_We -); -/* -wire [5:0]bank0; -wire [5:0]bank1; -wire [5:0]bank2; - -always @(clk_cpu, WR_n) begin - if (~WR_n & Cart_Addr[14:2] == "1111111111111") - case (Cart_Addr[1:0]) - 2'b01 : bank0 = Cart_In[5:0]; - 2'b10 : bank1 = Cart_In[5:0]; - 2'b11 : bank2 = Cart_In[5:0]; - default : ; - endcase; -end*/ - -spram #( - .init_file("/roms/[BIOS]OthelloMultivision.hex"), - .widthad_a(14),//16k for test - .width_a(8)) -ROM ( - .address(Cart_Addr), - .clock(clk_cpu), - .data(Cart_In), - .wren(~WR_n), - .q(Cart_Rom_Out) - ); -/* - spram #( - .init_file(""), - .widthad_a(11),//2k for test - .width_a(8)) -RAM ( - .address(Cart_Addr), - .clock(clk_cpu), - .data(Cart_Ram_In), - .wren(~WR_n), - .q(Cart_Ram_Out) - );*/ - -endmodule \ No newline at end of file diff --git a/Console_MiST/Sega - SG1000/rtl/color_encoder.vhd b/Console_MiST/Sega - SG1000/rtl/color_encoder.vhd deleted file mode 100644 index d4836130..00000000 --- a/Console_MiST/Sega - SG1000/rtl/color_encoder.vhd +++ /dev/null @@ -1,136 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - --- clk must be a 64Mhz clock --- sync is the sync signal (0 for 0V, 1 for 0.3V) --- line_visible is 1 for lines that are displayed (only sync when 0) --- line_even should be toggled every line --- color: 222 RGB (b1b0g1g0r1r0) --- output: 6 bit linear output, "000000" is 0v, "111111" is 1.3V (step is 0.02V) -entity color_encoder is - Port ( - clk: in STD_LOGIC; - pal: in STD_LOGIC; - sync: in STD_LOGIC; - line_visible: in STD_LOGIC; - line_even: in STD_LOGIC; - color: in STD_LOGIC_VECTOR (5 downto 0); - outputs: out STD_LOGIC_VECTOR (5 downto 0)); -end color_encoder; - -architecture Behavioral of color_encoder is - - component yuv_table - port (color : in std_logic_vector(5 downto 0); - y : out std_logic_vector(5 downto 0); - u : out std_logic_vector(5 downto 0); - v : out std_logic_vector(5 downto 0)); - end component; - - signal counter : integer range 0 to 4096; - signal phase : unsigned (20 downto 0) := (others=>'0'); - - signal y1: std_logic_vector (5 downto 0); - signal u1: std_logic_vector (5 downto 0); - signal v1: std_logic_vector (5 downto 0); - signal y : unsigned (5 downto 0); - signal u : unsigned (5 downto 0); - signal v : unsigned (5 downto 0); - - signal uv : unsigned (5 downto 0); - -begin - yuv_table_inst : yuv_table - port map ( - color => color, - y => y1, - u => u1, - v => v1); - - process (clk, sync, line_visible) - begin - if rising_edge(clk) then - if sync='0' then - counter <= 0; - --phase <= (others=>'0'); - else - if line_visible='1' then - counter <= counter+1; - end if; - end if; - if pal='1' then - phase <= phase+145281; - else - phase <= phase+117295; - end if; - end if; - end process; - - process (clk,counter,color) - --variable yuv : unsigned(17 downto 0); - begin - if rising_edge(clk) then - -- color burst - if counter>=2*29 and counter<2*(29+72) then - -- black - y <= "000000"; - -- reference phase - if pal='1' then - u <= "111100"; - v <= "000100"; - else - u <= "111000"; - v <= "000000"; - end if; - - -- visible pixels - elsif counter>=2*(29+72+85) and counter<2*(29+72+85+1664) then - --yuv := yuv_table(to_integer(unsigned(color))); - y <= unsigned(y1); - u <= unsigned(u1); - v <= unsigned(v1); - - -- front porch, sync and back porch - else - y <= (others=>'0'); - u <= (others=>'0'); - v <= (others=>'0'); - end if; - end if; - end process; - - process (phase, line_even, u, v) - begin - if pal='1' then - case line_even&phase(20 downto 19) is - when "000" => uv <= u; - when "001" => uv <= v; - when "010" => uv <= 0-u; - when "011" => uv <= 0-v; - when "100" => uv <= u; - when "101" => uv <= 0-v; - when "110" => uv <= 0-u; - when "111" => uv <= v; - when others => uv <= (others=>'0'); - end case; - else - case phase(20 downto 19) is - when "00" => uv <= u; - when "01" => uv <= 0-v; - when "10" => uv <= 0-u; - when "11" => uv <= v; - when others => uv <= (others=>'0'); - end case; - end if; - end process; - - process (clk,sync,y,uv) - begin - if rising_edge(clk) then - outputs <= std_logic_vector(("0"&sync&"0000")+y+uv); - end if; - end process; - -end Behavioral; - diff --git a/Console_MiST/Sega - SG1000/rtl/dac.vhd b/Console_MiST/Sega - SG1000/rtl/dac.vhd deleted file mode 100644 index 560e85e2..00000000 --- a/Console_MiST/Sega - SG1000/rtl/dac.vhd +++ /dev/null @@ -1,71 +0,0 @@ -------------------------------------------------------------------------------- --- --- Delta-Sigma DAC --- --- $Id: dac.vhd,v 1.1 2006/11/29 14:17:19 arnim Exp $ --- --- Refer to Xilinx Application Note XAPP154. --- --- This DAC requires an external RC low-pass filter: --- --- dac_o 0---XXXXX---+---0 analog audio --- 2K2 | --- === 10n --- | --- GND --- -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -entity dac is - - generic ( - msbi_g : integer := 7 - ); - port ( - clk_i : in std_logic; - res_i : in std_logic; - dac_i : in std_logic_vector(msbi_g downto 0); - dac_o : out std_logic - ); - -end entity; - -library ieee; -use ieee.numeric_std.all; - -architecture rtl of dac is - - signal DACout_q : std_logic; - signal DeltaAdder_s, - SigmaAdder_s, - SigmaLatch_q, - DeltaB_s : unsigned(msbi_g+2 downto 0); - -begin - - DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) & - SigmaLatch_q(msbi_g+2); - DeltaB_s(msbi_g downto 0) <= (others => '0'); - - DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s; - - SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q; - - seq: process (clk_i, res_i) - begin - if res_i = '1' then - SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length); - DACout_q <= '0'; - - elsif clk_i'event and clk_i = '1' then - SigmaLatch_q <= SigmaAdder_s; - DACout_q <= SigmaLatch_q(msbi_g+2); - end if; - end process seq; - - dac_o <= DACout_q; - -end architecture; diff --git a/Console_MiST/Sega - SG1000/rtl/hq2x.sv b/Console_MiST/Sega - SG1000/rtl/hq2x.sv deleted file mode 100644 index f17732b6..00000000 --- a/Console_MiST/Sega - SG1000/rtl/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/Console_MiST/Sega - SG1000/rtl/keyboard.sv b/Console_MiST/Sega - SG1000/rtl/keyboard.sv deleted file mode 100644 index 2715dd87..00000000 --- a/Console_MiST/Sega - SG1000/rtl/keyboard.sv +++ /dev/null @@ -1,15 +0,0 @@ -module keyboard( - input [2:0] Addr, - input JOY_SEL_n, - input KB_SEL_n, - output Kb_Out, - input RD_n, - input WR_n, - input CON,//not sure - input IORQ_n, - input ps2_kbd_clk, - input ps2_kbd_data -); - - -endmodule \ No newline at end of file diff --git a/Console_MiST/Sega - SG1000/rtl/mist_io.v b/Console_MiST/Sega - SG1000/rtl/mist_io.v deleted file mode 100644 index 1cfcb753..00000000 --- a/Console_MiST/Sega - SG1000/rtl/mist_io.v +++ /dev/null @@ -1,496 +0,0 @@ -// -// mist_io.v -// -// mist_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -// -// Use buffer to access SD card. It's time-critical part. -// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK -// (Sorgelig) -// -// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. -// clk_ps2 = clk_sys/(PS2DIV*2) -// - -module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) -( - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, - - // Global clock. It should be around 100MHz (higher is better). - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - - input CONF_DATA0, - input SPI_SS2, - output SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoubler_disable, - output ypbpr, - - output reg [31:0] status, - - // SD config - input sd_conf, - input sd_sdhc, - output [1:0] img_mounted, // signaling that new image has been mounted - output reg [31:0] img_size, // size of image in bytes - - // SD block level access - input [31:0] sd_lba, - input [1:0] sd_rd, - input [1:0] sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [8:0] sd_buff_addr, - output reg [7:0] sd_buff_dout, - input [7:0] sd_buff_din, - output reg sd_buff_wr, - - // ps2 keyboard emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // ps2 alternative interface. - - // [8] - extended, [9] - pressed, [10] - toggles with every press/release - output reg [10:0] ps2_key = 0, - - // [24] - toggles with every event - output reg [24:0] ps2_mouse = 0, - - // ARM -> FPGA download - input ioctl_ce, - input ioctl_wait, - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [13:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg [1:0] mount_strobe = 0; -assign img_mounted = mount_strobe; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire drive_sel = sd_rd[1] | sd_wr[1]; -wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; - -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes - -reg spi_do; -assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; - -reg [7:0] spi_data_out; - -// SPI transmitter -always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; - -reg [7:0] spi_data_in; -reg spi_data_ready = 0; - -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - reg [6:0] sbuf; - reg [31:0] sd_lba_r; - reg drive_sel_r; - - if(CONF_DATA0) begin - bit_cnt <= 0; - byte_cnt <= 0; - spi_data_out <= core_type; - end - else - begin - bit_cnt <= bit_cnt + 1'd1; - sbuf <= {sbuf[5:0], SPI_DI}; - - // finished reading command byte - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_DI}; - - spi_data_in <= {sbuf, SPI_DI}; - spi_data_ready <= ~spi_data_ready; - if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; - - spi_data_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_data_out <= sd_cmd; - sd_lba_r <= sd_lba; - drive_sel_r <= drive_sel; - end else if (byte_cnt == 1) begin - spi_data_out <= drive_sel_r; - end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_data_out <= sd_buff_din; - endcase - end - end -end - -reg [31:0] ps2_key_raw = 0; -wire pressed = (ps2_key_raw[15:8] != 8'hf0); -wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); - -// transfer to clk_sys domain -always@(posedge clk_sys) begin - reg old_ss1, old_ss2; - reg old_ready1, old_ready2; - reg [2:0] b_wr; - reg got_ps2 = 0; - - old_ss1 <= CONF_DATA0; - old_ss2 <= old_ss1; - old_ready1 <= spi_data_ready; - old_ready2 <= old_ready1; - - sd_buff_wr <= b_wr[0]; - if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; - b_wr <= (b_wr<<1); - - if(old_ss2) begin - got_ps2 <= 0; - sd_ack <= 0; - sd_ack_conf <= 0; - sd_buff_addr <= 0; - if(got_ps2) begin - if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; - if(cmd == 5) begin - ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; - if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed - if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released - if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed - end - end - end - else - if(old_ready2 ^ old_ready1) begin - - if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - - if(byte_cnt < 2) begin - - if (cmd == 8'h19) sd_ack_conf <= 1; - if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; - mount_strobe <= 0; - - if(cmd == 5) ps2_key_raw <= 0; - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= spi_data_in; - 8'h02: joystick_0 <= spi_data_in; - 8'h03: joystick_1 <= spi_data_in; - - // store incoming ps2 mouse bytes - 8'h04: begin - got_ps2 <= 1; - case(byte_cnt) - 2: ps2_mouse[7:0] <= spi_data_in; - 3: ps2_mouse[15:8] <= spi_data_in; - 4: ps2_mouse[23:16] <= spi_data_in; - endcase - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - end - - // store incoming ps2 keyboard bytes - 8'h05: begin - got_ps2 <= 1; - ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - 8'h15: status[7:0] <= spi_data_in; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_buff_dout <= spi_data_in; - b_wr <= 1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; - else if(byte_cnt == 3) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; - end else if(byte_cnt == 4) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; - else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; - end - end - - // notify image selection - 8'h1c: mount_strobe[spi_data_in[0]] <= 1; - - // send image info - 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; - - // status, 32bit version - 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; - default: ; - endcase - end - end -end - - -/////////////////////////////// PS2 /////////////////////////////// -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg clk_ps2; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - clk_ps2 <= ~clk_ps2; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; - else ps2_kbd_tx_state <= 0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; - else ps2_mouse_tx_state <= 0; - end - end -end - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [13:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin -// addr <= ioctl_index ? 14'd9 : 14'd0; //.p files loaded at $4009, ROM is at 0 - addr <= 14'd0; - ioctl_download <= 1; - end else begin - ioctl_addr <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - ioctl_addr <= addr; - ioctl_dout <= {sbuf, SPI_DI}; - addr <= addr + 1'd1; - ioctl_wr <= 1; - end else - ioctl_wr <= 0; - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -endmodule diff --git a/Console_MiST/Sega - SG1000/rtl/osd.v b/Console_MiST/Sega - SG1000/rtl/osd.v deleted file mode 100644 index c62c10af..00000000 --- a/Console_MiST/Sega - SG1000/rtl/osd.v +++ /dev/null @@ -1,179 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [7:0] osd_byte; -always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; - -wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/Console_MiST/Sega - SG1000/rtl/pll.v b/Console_MiST/Sega - SG1000/rtl/pll.v deleted file mode 100644 index f0d3343f..00000000 --- a/Console_MiST/Sega - SG1000/rtl/pll.v +++ /dev/null @@ -1,357 +0,0 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: pll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version -// ************************************************************ - - -//Copyright (C) 1991-2013 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module pll ( - inclk0, - c0, - c1, - c2); - - input inclk0; - output c0; - output c1; - output c2; - - wire [4:0] sub_wire0; - wire [0:0] sub_wire6 = 1'h0; - wire [2:2] sub_wire3 = sub_wire0[2:2]; - wire [0:0] sub_wire2 = sub_wire0[0:0]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; - wire c0 = sub_wire2; - wire c2 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; - - altpll altpll_component ( - .inclk (sub_wire5), - .clk (sub_wire0), - .activeclock (), - .areset (1'b0), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b0), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbmimicbidir (), - .fbout (), - .fref (), - .icdrclk (), - .locked (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 27, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 64, - altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 27, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 16, - altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 27, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 8, - altpll_component.clk2_phase_shift = "0", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 37037, - altpll_component.intended_device_family = "Cyclone III", - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_UNUSED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_UNUSED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", - altpll_component.port_clk3 = "PORT_UNUSED", - altpll_component.port_clk4 = "PORT_UNUSED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena2 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED", - altpll_component.width_clock = 5; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "64.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "8.000000" -// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" -// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "64" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "8" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "64.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "8.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" -// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "64" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf -// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Console_MiST/Sega - SG1000/rtl/psg/psg.vhd b/Console_MiST/Sega - SG1000/rtl/psg/psg.vhd deleted file mode 100644 index 688dcd10..00000000 --- a/Console_MiST/Sega - SG1000/rtl/psg/psg.vhd +++ /dev/null @@ -1,135 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity psg is - port (clk : in STD_LOGIC; - WR_n : in STD_LOGIC; - CS_n : in STD_LOGIC; - D_in : in STD_LOGIC_VECTOR (7 downto 0); - outputs: out STD_LOGIC_VECTOR (5 downto 0) - ); - -end psg; - -architecture rtl of psg is - - signal clk_divide : unsigned(5 downto 0) := "000000"; - signal clk32 : std_logic; - signal regn : std_logic_vector(2 downto 0); - signal tone0 : std_logic_vector(9 downto 0):="0000100000"; - signal tone1 : std_logic_vector(9 downto 0):="0000100000"; - signal tone2 : std_logic_vector(9 downto 0):="0000100000"; - signal ctrl3 : std_logic_vector(2 downto 0):="100"; - signal volume0 : std_logic_vector(3 downto 0):="1111"; - signal volume1 : std_logic_vector(3 downto 0):="1111"; - signal volume2 : std_logic_vector(3 downto 0):="1111"; - signal volume3 : std_logic_vector(3 downto 0):="1111"; - signal output0 : std_logic_vector(3 downto 0); - signal output1 : std_logic_vector(3 downto 0); - signal output2 : std_logic_vector(3 downto 0); - signal output3 : std_logic_vector(3 downto 0); - --- signal outputs : std_logic_vector(5 downto 0); - - component psg_tone is - port (clk : in STD_LOGIC; - tone : in STD_LOGIC_VECTOR (9 downto 0); - volume: in STD_LOGIC_VECTOR (3 downto 0); - output: out STD_LOGIC_VECTOR (3 downto 0)); - end component; - - component psg_noise is - port (clk : in STD_LOGIC; - style : in STD_LOGIC_VECTOR (2 downto 0); - tone : in STD_LOGIC_VECTOR (9 downto 0); - volume: in STD_LOGIC_VECTOR (3 downto 0); - output: out STD_LOGIC_VECTOR (3 downto 0)); - end component; - - component dac is - port (clk : in STD_LOGIC; - input : in STD_LOGIC_VECTOR (5 downto 0); - output: out STD_LOGIC); - end component; -begin - - t0: psg_tone - port map ( - clk => clk32, - tone => tone0, - volume => volume0, - output => output0); - - t1: psg_tone - port map ( - clk => clk32, - tone => tone1, - volume => volume1, - output => output1); - - t2: psg_tone - port map ( - clk => clk32, - tone => tone2, - volume => volume2, - output => output2); - - t3: psg_noise - port map( - clk => clk32, - style => ctrl3, - tone => tone2, - volume => volume3, - output => output3); - - - process (clk) - begin - if rising_edge(clk) then - clk_divide <= clk_divide+1; - end if; - end process; - clk32 <= std_logic(clk_divide(5)); - - process (clk, WR_n, CS_n) - begin - if rising_edge(clk) and WR_n='0' and CS_n='0' then - if D_in(7)='1' then - case D_in(6 downto 4) is - when "000" => tone0(3 downto 0) <= D_in(3 downto 0); - when "010" => tone1(3 downto 0) <= D_in(3 downto 0); - when "100" => tone2(3 downto 0) <= D_in(3 downto 0); - when "110" => ctrl3 <= D_in(2 downto 0); - when "001" => volume0 <= D_in(3 downto 0); - when "011" => volume1 <= D_in(3 downto 0); - when "101" => volume2 <= D_in(3 downto 0); - when "111" => volume3 <= D_in(3 downto 0); - when others => - end case; - regn <= D_in(6 downto 4); - else - case regn is - when "000" => tone0(9 downto 4) <= D_in(5 downto 0); - when "010" => tone1(9 downto 4) <= D_in(5 downto 0); - when "100" => tone2(9 downto 4) <= D_in(5 downto 0); - when "110" => - when "001" => volume0 <= D_in(3 downto 0); - when "011" => volume1 <= D_in(3 downto 0); - when "101" => volume2 <= D_in(3 downto 0); - when "111" => volume3 <= D_in(3 downto 0); - when others => - end case; - end if; - end if; - end process; - - outputs <= std_logic_vector( - unsigned("00"&output0) - + unsigned("00"&output1) - + unsigned("00"&output2) - + unsigned("00"&output3) - ); - -end rtl; - diff --git a/Console_MiST/Sega - SG1000/rtl/psg/psg_noise.vhd b/Console_MiST/Sega - SG1000/rtl/psg/psg_noise.vhd deleted file mode 100644 index 7dee6168..00000000 --- a/Console_MiST/Sega - SG1000/rtl/psg/psg_noise.vhd +++ /dev/null @@ -1,56 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity psg_noise is -port ( - clk : in STD_LOGIC; - style : in STD_LOGIC_VECTOR (2 downto 0); - tone : in STD_LOGIC_VECTOR (9 downto 0); - volume : in STD_LOGIC_VECTOR (3 downto 0); - output : out STD_LOGIC_VECTOR (3 downto 0)); -end psg_noise; - -architecture rtl of psg_noise is - - signal counter : unsigned(9 downto 0); - signal v : std_logic; - signal shift : std_logic_vector(15 downto 0) := "1000000000000000"; - -begin - - process (clk, tone) - begin - if rising_edge(clk) then - if counter="000000001" then - v <= not v; - case style(1 downto 0) is - when "00" => counter <= "0000010000"; - when "01" => counter <= "0000100000"; - when "10" => counter <= "0001000000"; - when "11" => counter <= unsigned(tone); - when others => - end case; - else - counter <= counter-1; - end if; - end if; - end process; - - process (v) - variable feedback: std_logic; - begin - if rising_edge(v) then - if (style(2)='1') then - feedback := shift(0) xor shift(3); - else - feedback := shift(0); - end if; - shift <= feedback & shift(15 downto 1); - end if; - end process; - - output <= (shift(0)&shift(0)&shift(0)&shift(0)) or volume; - -end rtl; - diff --git a/Console_MiST/Sega - SG1000/rtl/psg/psg_tone.vhd b/Console_MiST/Sega - SG1000/rtl/psg/psg_tone.vhd deleted file mode 100644 index 7ec6b552..00000000 --- a/Console_MiST/Sega - SG1000/rtl/psg/psg_tone.vhd +++ /dev/null @@ -1,34 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity psg_tone is - Port ( - clk : in STD_LOGIC; - tone : in STD_LOGIC_VECTOR (9 downto 0); - volume: in STD_LOGIC_VECTOR (3 downto 0); - output: out STD_LOGIC_VECTOR (3 downto 0)); -end psg_tone; - -architecture rtl of psg_tone is - - signal counter : unsigned(9 downto 0) := (0=>'1', others=>'0'); - signal v : std_logic := '0'; - -begin - - process (clk, tone) - begin - if rising_edge(clk) then - if counter="000000000" then - v <= not v; - counter <= unsigned(tone); - else - counter <= counter-1; - end if; - end if; - end process; - - output <= (v&v&v&v) or volume; -end rtl; - diff --git a/Console_MiST/Sega - SG1000/rtl/roms/32.hex b/Console_MiST/Sega - SG1000/rtl/roms/32.hex deleted file mode 100644 index cc0b6834..00000000 --- a/Console_MiST/Sega - SG1000/rtl/roms/32.hex +++ /dev/null @@ -1,2049 +0,0 @@ -:10000000F3ED56C3D611FFFF22188BE3D5C3C10011 -:10001000E1C1D1E3C920080E3AC98ACB47C9FFFF25 -:10002000CD603CC93D080E09CD2A41C94E204F4044 -:100030003200C1C94D415040F3F5C5D5E5DDE5FDC0 -:10004000E508D9F5C5D5CD7702DBBFCD5B09D1C1B8 -:10005000F1D908FDE1DDE1E1D1C1F1FBC93A39385F -:10006000393837363534F53A228BFEFF20123A17ED -:100070008BFE20380B3A238B2F32238BAF32178B1A -:10008000F1ED453A1A8BB72807324383AF324483E8 -:10009000C90000FF910003010301030003010301F4 -:1000A0000300030003010301030003000301030134 -:1000B0000300030003010301030103000300030025 -:1000C000FEC5E52A188BC93A0B8BE6BF18053A0B1B -:1000D0008BF640320B8B470E0178D3BF79F680D375 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b/Console_MiST/Sega - SG1000/rtl/scandoubler.v deleted file mode 100644 index e85cba43..00000000 --- a/Console_MiST/Sega - SG1000/rtl/scandoubler.v +++ /dev/null @@ -1,183 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/Console_MiST/Sega - SG1000/rtl/sg1000_top.sv b/Console_MiST/Sega - SG1000/rtl/sg1000_top.sv deleted file mode 100644 index df5973c0..00000000 --- a/Console_MiST/Sega - SG1000/rtl/sg1000_top.sv +++ /dev/null @@ -1,229 +0,0 @@ -module sg1000_top( -input RESET_n, -input sys_clk,//8 -input vdp_clk,//16 -input vid_clk,//64 -input pal, -input pause, -input ps2_kbd_clk, -input ps2_kbd_data, -input [7:0] Cart_In, -output [14:0] Cart_Addr, -output Cart_We, -output [5:0] audio, -output vblank, -output hblank, -output vga_hs, -output vga_vs, -output [1:0] vga_r, -output [1:0] vga_g, -output [1:0] vga_b, -output [1:0] rgb_r, -output [1:0] rgb_g, -output [1:0] rgb_b, -output csync, -input [5:0] Joy_A, -input [5:0] Joy_B -); - -wire DSRAM_n = CS_WRAM_n; -wire CS_WRAM_n = (~MREQ_n) & (Addr[15:14] == "11") ? 1'b0 : 1'b1; -wire M1_n; -wire MREQ_n; -wire IORQ_n; -wire RD_n; -wire WR_n; -wire RFSH_n; -wire WAIT_n; -wire INT_n; -wire NMI_n = pause;//todo -wire [15:0]Addr; -wire [7:0]D_in; -wire [7:0]D_out; - - - -T80se #( - .Mode(0), - .T2Write(0), - .IOWait(1)) -CPU ( - .RESET_n(RESET_n), - .CLK_n(sys_clk), - .CLKEN(1'b1), - .INT_n(INT_n), - .NMI_n(NMI_n), - .BUSRQ_n(1'b1), - .M1_n(M1_n), - .MREQ_n(MREQ_n), - .IORQ_n(IORQ_n), - .RD_n(RD_n), - .WR_n(WR_n), - .RFSH_n(RFSH_n), - .HALT_n(WAIT_n), - .A(Addr), - .DI(D_in), - .DO(D_out) - ); - -wire [7:0]RAM_D_out; - -spram #( - .widthad_a(11),//2k - .width_a(8)) -MRAM ( - .address(Addr[10:0]), - .clock(sys_clk), - .data(D_out), - .wren(~WR_n), - .q(RAM_D_out) - ); - -wire CS_PSG_n = (~IORQ_n) & (Addr[7:6] == "01") ? 1'b0 : 1'b1; -psg PSG ( - .clk(sys_clk), - .CS_n(CS_PSG_n), - .WR_n(WR_n), - .D_in(D_out), - .outputs(audio) - ); - -wire [7:0]vdp_D_out; -wire [8:0]x; -wire [7:0]y; -wire [5:0] color; -wire VDP_RD_n = (~IORQ_n) & (Addr[7:6] == "10") | RD_n ? 1'b0 : 1'b1; -wire VDP_WR_n = (~IORQ_n) & (Addr[7:6] == "10") | WR_n ? 1'b0 : 1'b1; - -vdp vdp ( - .cpu_clk(sys_clk), - .vdp_clk(vdp_clk), - .RD_n(VDP_RD_n), - .WR_n(VDP_WR_n), - .IRQ_n(IORQ_n), - .A(Addr[7:0]), - .D_in(D_out), - .D_out(vdp_D_out), - .x(x), - .y(y), - .vblank(vblank), - .hblank(hblank), - .color(color) - ); - -vga_video vga_video ( - .clk16(vdp_clk), - .x(x), - .y(y), - .vblank(vblank), - .hblank(hblank), - .color(color), - .hsync(vga_hs), - .vsync(vga_vs), - .red(vga_r), - .green(vga_g), - .blue(vga_b) - ); - /* -tv_video tv_video ( - .clk8(sys_clk), - .clk64(vid_clk), - .pal(pal), - .x(x), - .y(y), - .vblank(vblank), - .hblank(hblank), - .csync(csync), - .color(color), - .video({rgb_b,rgb_g,rgb_r}) - );*/ - - -wire [7:0]Joy_Out; -wire JOY_SEL_n = (~IORQ_n) & (Addr[7:6] == "11") | RD_n ? 1'b0 : 1'b1; -wire CON; -TTL74_257 IC18( - .GN(JOY_SEL_n), - .SEL(Addr[0]), - .B4(Joy_B[5]), - .A4(Joy_A[2]), - .B3(Joy_B[4]), - .A3(Joy_A[3]), - .B2(Joy_B[3]), - .A2(Joy_A[5]), - .B1(Joy_B[2]), - .A1(Joy_A[4]), - .Y4(Joy_Out[3]), - .Y3(Joy_Out[2]), - .Y2(Joy_Out[1]), - .Y1(Joy_Out[0]) -); - -TTL74_257 IC21( - .GN(JOY_SEL_n), - .SEL(Addr[0]), - .B4(), - .A4(Joy_B[1]), - .B3(), - .A3(Joy_B[0]), - .B2(), - .A2(Joy_A[0]), - .B1(CON), - .A1(Joy_A[1]), - .Y4(Joy_Out[7]), - .Y3(Joy_Out[6]), - .Y2(Joy_Out[5]), - .Y1(Joy_Out[4]) -); - -wire KB_SEL_n = (~IORQ_n) & (Addr[7:6] == "11") ? 1'b0 : 1'b1; -wire [7:0]Kb_Out; - -keyboard keyboard( - .Addr(Addr[2:0]), - .JOY_SEL_n(JOY_SEL_n), - .KB_SEL_n(KB_SEL_n), - .Kb_Out(Kb_Out), - .RD_n(RD_n), - .WR_n(WR_n), - .CON(CON), - .IORQ_n(IORQ_n), - .ps2_kbd_clk(ps2_kbd_clk), - .ps2_kbd_data(ps2_kbd_data) -); - -wire EXM1_n = (~MREQ_n) & (Addr[15:14] == "10") ? 1'b0 : 1'b1; -wire EXM2_n = (~MREQ_n) | (Addr[15]) ? 1'b0 : 1'b1; -wire [7:0]Cart_Rom_Out, Cart_Ram_Out; - -cart cart( - .DSRAM_n(DSRAM_n), - .EXM1_n(EXM1_n), - .RD_n(RD_n), - .WR_n(WR_n), - .RFSH_n(RFSH_n), - .MREQ_n(MREQ_n), - .CON(CON), - .EXM2_n(EXM2_n), - .M1_n, - .Cart_Addr(Addr[14:0]), - .Cart_Rom_Out(Cart_Rom_Out), - .Cart_Ram_Out(Cart_Ram_Out), - .Cart_In(Cart_In), - .Cart_We(Cart_We) -); - -//todo -always @(sys_clk) begin - D_in = ~CS_WRAM_n ? RAM_D_out : - ~VDP_RD_n ? vdp_D_out : - ~EXM1_n ? Cart_Rom_Out : - ~EXM2_n ? Cart_Ram_Out : - ~JOY_SEL_n ? Joy_Out : - ~KB_SEL_n ? Kb_Out : - 1'hz; -end - -endmodule - - diff --git a/Console_MiST/Sega - SG1000/rtl/spram.vhd b/Console_MiST/Sega - SG1000/rtl/spram.vhd deleted file mode 100644 index d4e8dd90..00000000 --- a/Console_MiST/Sega - SG1000/rtl/spram.vhd +++ /dev/null @@ -1,90 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY spram IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - wren : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END spram; - - -ARCHITECTURE SYN OF spram IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - power_up_uninitialized : STRING; - read_during_write_mode_port_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - wren_a : IN STD_LOGIC ; - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "SINGLE_PORT", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - power_up_uninitialized => "FALSE", - read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - wren_a => wren, - clock0 => clock, - address_a => address, - data_a => data, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Console_MiST/Sega - SG1000/rtl/sprom.vhd b/Console_MiST/Sega - SG1000/rtl/sprom.vhd deleted file mode 100644 index a81ac959..00000000 --- a/Console_MiST/Sega - SG1000/rtl/sprom.vhd +++ /dev/null @@ -1,82 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - - - COMPONENT altsyncram - GENERIC ( - address_aclr_a : STRING; - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - address_aclr_a => "NONE", - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone III", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - - - -END SYN; diff --git a/Console_MiST/Sega - SG1000/rtl/t80/T80.vhd b/Console_MiST/Sega - SG1000/rtl/t80/T80.vhd deleted file mode 100644 index 398fa0df..00000000 --- a/Console_MiST/Sega - SG1000/rtl/t80/T80.vhd +++ /dev/null @@ -1,1073 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0210 : Fixed wait and halt --- --- 0211 : Fixed Refresh addition and IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson --- --- 0235 : Added clock enable and IM 2 fix by Mike Johnson --- --- 0237 : Changed 8080 I/O address output, added IntE output --- --- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag --- --- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode --- --- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80 is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); -end T80; - -architecture rtl of T80 is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; - - -- Registers - signal ACC, F : std_logic_vector(7 downto 0); - signal Ap, Fp : std_logic_vector(7 downto 0); - signal I : std_logic_vector(7 downto 0); - signal R : unsigned(7 downto 0); - signal SP, PC : unsigned(15 downto 0); - signal RegDIH : std_logic_vector(7 downto 0); - signal RegDIL : std_logic_vector(7 downto 0); - signal RegBusA : std_logic_vector(15 downto 0); - signal RegBusB : std_logic_vector(15 downto 0); - signal RegBusC : std_logic_vector(15 downto 0); - signal RegAddrA_r : std_logic_vector(2 downto 0); - signal RegAddrA : std_logic_vector(2 downto 0); - signal RegAddrB_r : std_logic_vector(2 downto 0); - signal RegAddrB : std_logic_vector(2 downto 0); - signal RegAddrC : std_logic_vector(2 downto 0); - signal RegWEH : std_logic; - signal RegWEL : std_logic; - signal Alternate : std_logic; - - -- Help Registers - signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register - signal IR : std_logic_vector(7 downto 0); -- Instruction register - signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector - signal RegBusA_r : std_logic_vector(15 downto 0); - - signal ID16 : signed(15 downto 0); - signal Save_Mux : std_logic_vector(7 downto 0); - - signal TState : unsigned(2 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal IntE_FF1 : std_logic; - signal IntE_FF2 : std_logic; - signal Halt_FF : std_logic; - signal BusReq_s : std_logic; - signal BusAck : std_logic; - signal ClkEn : std_logic; - signal NMI_s : std_logic; - signal INT_s : std_logic; - signal IStatus : std_logic_vector(1 downto 0); - - signal DI_Reg : std_logic_vector(7 downto 0); - signal T_Res : std_logic; - signal XY_State : std_logic_vector(1 downto 0); - signal Pre_XY_F_M : std_logic_vector(2 downto 0); - signal NextIs_XY_Fetch : std_logic; - signal XY_Ind : std_logic; - signal No_BTR : std_logic; - signal BTR_r : std_logic; - signal Auto_Wait : std_logic; - signal Auto_Wait_t1 : std_logic; - signal Auto_Wait_t2 : std_logic; - signal IncDecZ : std_logic; - - -- ALU signals - signal BusB : std_logic_vector(7 downto 0); - signal BusA : std_logic_vector(7 downto 0); - signal ALU_Q : std_logic_vector(7 downto 0); - signal F_Out : std_logic_vector(7 downto 0); - - -- Registered micro code outputs - signal Read_To_Reg_r : std_logic_vector(4 downto 0); - signal Arith16_r : std_logic; - signal Z16_r : std_logic; - signal ALU_Op_r : std_logic_vector(3 downto 0); - signal Save_ALU_r : std_logic; - signal PreserveC_r : std_logic; - signal MCycles : std_logic_vector(2 downto 0); - - -- Micro code outputs - signal MCycles_d : std_logic_vector(2 downto 0); - signal TStates : std_logic_vector(2 downto 0); - signal IntCycle : std_logic; - signal NMICycle : std_logic; - signal Inc_PC : std_logic; - signal Inc_WZ : std_logic; - signal IncDec_16 : std_logic_vector(3 downto 0); - signal Prefix : std_logic_vector(1 downto 0); - signal Read_To_Acc : std_logic; - signal Read_To_Reg : std_logic; - signal Set_BusB_To : std_logic_vector(3 downto 0); - signal Set_BusA_To : std_logic_vector(3 downto 0); - signal ALU_Op : std_logic_vector(3 downto 0); - signal Save_ALU : std_logic; - signal PreserveC : std_logic; - signal Arith16 : std_logic; - signal Set_Addr_To : std_logic_vector(2 downto 0); - signal Jump : std_logic; - signal JumpE : std_logic; - signal JumpXY : std_logic; - signal Call : std_logic; - signal RstP : std_logic; - signal LDZ : std_logic; - signal LDW : std_logic; - signal LDSPHL : std_logic; - signal IORQ_i : std_logic; - signal Special_LD : std_logic_vector(2 downto 0); - signal ExchangeDH : std_logic; - signal ExchangeRp : std_logic; - signal ExchangeAF : std_logic; - signal ExchangeRS : std_logic; - signal I_DJNZ : std_logic; - signal I_CPL : std_logic; - signal I_CCF : std_logic; - signal I_SCF : std_logic; - signal I_RETN : std_logic; - signal I_BT : std_logic; - signal I_BC : std_logic; - signal I_BTR : std_logic; - signal I_RLD : std_logic; - signal I_RRD : std_logic; - signal I_INRC : std_logic; - signal SetDI : std_logic; - signal SetEI : std_logic; - signal IMode : std_logic_vector(1 downto 0); - signal Halt : std_logic; - -begin - - mcode : T80_MCode - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - IR => IR, - ISet => ISet, - MCycle => MCycle, - F => F, - NMICycle => NMICycle, - IntCycle => IntCycle, - MCycles => MCycles_d, - TStates => TStates, - Prefix => Prefix, - Inc_PC => Inc_PC, - Inc_WZ => Inc_WZ, - IncDec_16 => IncDec_16, - Read_To_Acc => Read_To_Acc, - Read_To_Reg => Read_To_Reg, - Set_BusB_To => Set_BusB_To, - Set_BusA_To => Set_BusA_To, - ALU_Op => ALU_Op, - Save_ALU => Save_ALU, - PreserveC => PreserveC, - Arith16 => Arith16, - Set_Addr_To => Set_Addr_To, - IORQ => IORQ_i, - Jump => Jump, - JumpE => JumpE, - JumpXY => JumpXY, - Call => Call, - RstP => RstP, - LDZ => LDZ, - LDW => LDW, - LDSPHL => LDSPHL, - Special_LD => Special_LD, - ExchangeDH => ExchangeDH, - ExchangeRp => ExchangeRp, - ExchangeAF => ExchangeAF, - ExchangeRS => ExchangeRS, - I_DJNZ => I_DJNZ, - I_CPL => I_CPL, - I_CCF => I_CCF, - I_SCF => I_SCF, - I_RETN => I_RETN, - I_BT => I_BT, - I_BC => I_BC, - I_BTR => I_BTR, - I_RLD => I_RLD, - I_RRD => I_RRD, - I_INRC => I_INRC, - SetDI => SetDI, - SetEI => SetEI, - IMode => IMode, - Halt => Halt, - NoRead => NoRead, - Write => Write); - - alu : T80_ALU - generic map( - Mode => Mode, - Flag_C => Flag_C, - Flag_N => Flag_N, - Flag_P => Flag_P, - Flag_X => Flag_X, - Flag_H => Flag_H, - Flag_Y => Flag_Y, - Flag_Z => Flag_Z, - Flag_S => Flag_S) - port map( - Arith16 => Arith16_r, - Z16 => Z16_r, - ALU_Op => ALU_Op_r, - IR => IR(5 downto 0), - ISet => ISet, - BusA => BusA, - BusB => BusB, - F_In => F, - Q => ALU_Q, - F_Out => F_Out); - - ClkEn <= CEN and not BusAck; - - T_Res <= '1' when TState = unsigned(TStates) else '0'; - - NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and - ((Set_Addr_To = aXY) or - (MCycle = "001" and IR = "11001011") or - (MCycle = "001" and IR = "00110110")) else '0'; - - Save_Mux <= BusB when ExchangeRp = '1' else - DI_Reg when Save_ALU_r = '0' else - ALU_Q; - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - PC <= (others => '0'); -- Program Counter - A <= (others => '0'); - TmpAddr <= (others => '0'); - IR <= "00000000"; - ISet <= "00"; - XY_State <= "00"; - IStatus <= "00"; - MCycles <= "000"; - DO <= "00000000"; - - ACC <= (others => '1'); - F <= (others => '1'); - Ap <= (others => '1'); - Fp <= (others => '1'); - I <= (others => '0'); - R <= (others => '0'); - SP <= (others => '1'); - Alternate <= '0'; - - Read_To_Reg_r <= "00000"; - F <= (others => '1'); - Arith16_r <= '0'; - BTR_r <= '0'; - Z16_r <= '0'; - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - PreserveC_r <= '0'; - XY_Ind <= '0'; - - elsif CLK_n'event and CLK_n = '1' then - - if ClkEn = '1' then - - ALU_Op_r <= "0000"; - Save_ALU_r <= '0'; - Read_To_Reg_r <= "00000"; - - MCycles <= MCycles_d; - - if IMode /= "11" then - IStatus <= IMode; - end if; - - Arith16_r <= Arith16; - PreserveC_r <= PreserveC; - if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then - Z16_r <= '1'; - else - Z16_r <= '0'; - end if; - - if MCycle = "001" and TState(2) = '0' then - -- MCycle = 1 and TState = 1, 2, or 3 - - if TState = 2 and Wait_n = '1' then - if Mode < 2 then - A(7 downto 0) <= std_logic_vector(R); - A(15 downto 8) <= I; - R(6 downto 0) <= R(6 downto 0) + 1; - end if; - - if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then - PC <= PC + 1; - end if; - - if IntCycle = '1' and IStatus = "01" then - IR <= "11111111"; - elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then - IR <= "00000000"; - else - IR <= DInst; - end if; - - ISet <= "00"; - if Prefix /= "00" then - if Prefix = "11" then - if IR(5) = '1' then - XY_State <= "10"; - else - XY_State <= "01"; - end if; - else - if Prefix = "10" then - XY_State <= "00"; - XY_Ind <= '0'; - end if; - ISet <= Prefix; - end if; - else - XY_State <= "00"; - XY_Ind <= '0'; - end if; - end if; - - else - -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) - - if MCycle = "110" then - XY_Ind <= '1'; - if Prefix = "01" then - ISet <= "01"; - end if; - end if; - - if T_Res = '1' then - BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; - if Jump = '1' then - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(DI_Reg); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - elsif JumpXY = '1' then - A <= RegBusC; - PC <= unsigned(RegBusC); - elsif Call = '1' or RstP = '1' then - A <= TmpAddr; - PC <= unsigned(TmpAddr); - elsif MCycle = MCycles and NMICycle = '1' then - A <= "0000000001100110"; - PC <= "0000000001100110"; - elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then - A(15 downto 8) <= I; - A(7 downto 0) <= TmpAddr(7 downto 0); - PC(15 downto 8) <= unsigned(I); - PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); - else - case Set_Addr_To is - when aXY => - if XY_State = "00" then - A <= RegBusC; - else - if NextIs_XY_Fetch = '1' then - A <= std_logic_vector(PC); - else - A <= TmpAddr; - end if; - end if; - when aIOA => - if Mode = 3 then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - elsif Mode = 2 then - -- Duplicate I/O address on 8080 - A(15 downto 8) <= DI_Reg; - else - A(15 downto 8) <= ACC; - end if; - A(7 downto 0) <= DI_Reg; - when aSP => - A <= std_logic_vector(SP); - when aBC => - if Mode = 3 and IORQ_i = '1' then - -- Memory map I/O on GBZ80 - A(15 downto 8) <= (others => '1'); - A(7 downto 0) <= RegBusC(7 downto 0); - else - A <= RegBusC; - end if; - when aDE => - A <= RegBusC; - when aZI => - if Inc_WZ = '1' then - A <= std_logic_vector(unsigned(TmpAddr) + 1); - else - A(15 downto 8) <= DI_Reg; - A(7 downto 0) <= TmpAddr(7 downto 0); - end if; - when others => - A <= std_logic_vector(PC); - end case; - end if; - - Save_ALU_r <= Save_ALU; - ALU_Op_r <= ALU_Op; - - if I_CPL = '1' then - -- CPL - ACC <= not ACC; - F(Flag_Y) <= not ACC(5); - F(Flag_H) <= '1'; - F(Flag_X) <= not ACC(3); - F(Flag_N) <= '1'; - end if; - if I_CCF = '1' then - -- CCF - F(Flag_C) <= not F(Flag_C); - F(Flag_Y) <= ACC(5); - F(Flag_H) <= F(Flag_C); - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - if I_SCF = '1' then - -- SCF - F(Flag_C) <= '1'; - F(Flag_Y) <= ACC(5); - F(Flag_H) <= '0'; - F(Flag_X) <= ACC(3); - F(Flag_N) <= '0'; - end if; - end if; - - if TState = 2 and Wait_n = '1' then - if ISet = "01" and MCycle = "111" then - IR <= DInst; - end if; - if JumpE = '1' then - PC <= unsigned(signed(PC) + signed(DI_Reg)); - elsif Inc_PC = '1' then - PC <= PC + 1; - end if; - if BTR_r = '1' then - PC <= PC - 2; - end if; - if RstP = '1' then - TmpAddr <= (others =>'0'); - TmpAddr(5 downto 3) <= IR(5 downto 3); - end if; - end if; - if TState = 3 and MCycle = "110" then - TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); - end if; - - if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then - if IncDec_16(2 downto 0) = "111" then - if IncDec_16(3) = '1' then - SP <= SP - 1; - else - SP <= SP + 1; - end if; - end if; - end if; - - if LDSPHL = '1' then - SP <= unsigned(RegBusC); - end if; - if ExchangeAF = '1' then - Ap <= ACC; - ACC <= Ap; - Fp <= F; - F <= Fp; - end if; - if ExchangeRS = '1' then - Alternate <= not Alternate; - end if; - end if; - - if TState = 3 then - if LDZ = '1' then - TmpAddr(7 downto 0) <= DI_Reg; - end if; - if LDW = '1' then - TmpAddr(15 downto 8) <= DI_Reg; - end if; - - if Special_LD(2) = '1' then - case Special_LD(1 downto 0) is - when "00" => - ACC <= I; - F(Flag_P) <= IntE_FF2; - when "01" => - ACC <= std_logic_vector(R); - F(Flag_P) <= IntE_FF2; - when "10" => - I <= ACC; - when others => - R <= unsigned(ACC); - end case; - end if; - end if; - - if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then - if Mode = 3 then - F(6) <= F_Out(6); - F(5) <= F_Out(5); - F(7) <= F_Out(7); - if PreserveC_r = '0' then - F(4) <= F_Out(4); - end if; - else - F(7 downto 1) <= F_Out(7 downto 1); - if PreserveC_r = '0' then - F(Flag_C) <= F_Out(0); - end if; - end if; - end if; - if T_Res = '1' and I_INRC = '1' then - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - if DI_Reg(7 downto 0) = "00000000" then - F(Flag_Z) <= '1'; - else - F(Flag_Z) <= '0'; - end if; - F(Flag_S) <= DI_Reg(7); - F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor - DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); - end if; - - if TState = 1 and Auto_Wait_t1 = '0' then - DO <= BusB; - if I_RLD = '1' then - DO(3 downto 0) <= BusA(3 downto 0); - DO(7 downto 4) <= BusB(3 downto 0); - end if; - if I_RRD = '1' then - DO(3 downto 0) <= BusB(7 downto 4); - DO(7 downto 4) <= BusA(3 downto 0); - end if; - end if; - - if T_Res = '1' then - Read_To_Reg_r(3 downto 0) <= Set_BusA_To; - Read_To_Reg_r(4) <= Read_To_Reg; - if Read_To_Acc = '1' then - Read_To_Reg_r(3 downto 0) <= "0111"; - Read_To_Reg_r(4) <= '1'; - end if; - end if; - - if TState = 1 and I_BT = '1' then - F(Flag_X) <= ALU_Q(3); - F(Flag_Y) <= ALU_Q(1); - F(Flag_H) <= '0'; - F(Flag_N) <= '0'; - end if; - if I_BC = '1' or I_BT = '1' then - F(Flag_P) <= IncDecZ; - end if; - - if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10111" => - ACC <= Save_Mux; - when "10110" => - DO <= Save_Mux; - when "11000" => - SP(7 downto 0) <= unsigned(Save_Mux); - when "11001" => - SP(15 downto 8) <= unsigned(Save_Mux); - when "11011" => - F <= Save_Mux; - when others => - end case; - end if; - - end if; - - end if; - - end process; - ---------------------------------------------------------------------------- --- --- BC('), DE('), HL('), IX and IY --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - -- Bus A / Write - RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then - RegAddrA_r <= XY_State(1) & "11"; - end if; - - -- Bus B - RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); - if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then - RegAddrB_r <= XY_State(1) & "11"; - end if; - - -- Address from register - RegAddrC <= Alternate & Set_Addr_To(1 downto 0); - -- Jump (HL), LD SP,HL - if (JumpXY = '1' or LDSPHL = '1') then - RegAddrC <= Alternate & "10"; - end if; - if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then - RegAddrC <= XY_State(1) & "11"; - end if; - - if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then - IncDecZ <= F_Out(Flag_Z); - end if; - if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then - if ID16 = 0 then - IncDecZ <= '0'; - else - IncDecZ <= '1'; - end if; - end if; - - RegBusA_r <= RegBusA; - end if; - end if; - end process; - - RegAddrA <= - -- 16 bit increment/decrement - Alternate & IncDec_16(1 downto 0) when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else - XY_State(1) & "11" when (TState = 2 or - (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else - -- EX HL,DL - Alternate & "10" when ExchangeDH = '1' and TState = 3 else - Alternate & "01" when ExchangeDH = '1' and TState = 4 else - -- Bus A / Write - RegAddrA_r; - - RegAddrB <= - -- EX HL,DL - Alternate & "01" when ExchangeDH = '1' and TState = 3 else - -- Bus B - RegAddrB_r; - - ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else - signed(RegBusA) + 1; - - process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegWEH <= '0'; - RegWEL <= '0'; - if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or - (Save_ALU_r = '1' and ALU_OP_r /= "0111") then - case Read_To_Reg_r is - when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => - RegWEH <= not Read_To_Reg_r(0); - RegWEL <= Read_To_Reg_r(0); - when others => - end case; - end if; - - if ExchangeDH = '1' and (TState = 3 or TState = 4) then - RegWEH <= '1'; - RegWEL <= '1'; - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - case IncDec_16(1 downto 0) is - when "00" | "01" | "10" => - RegWEH <= '1'; - RegWEL <= '1'; - when others => - end case; - end if; - end process; - - process (Save_Mux, RegBusB, RegBusA_r, ID16, - ExchangeDH, IncDec_16, MCycle, TState, Wait_n) - begin - RegDIH <= Save_Mux; - RegDIL <= Save_Mux; - - if ExchangeDH = '1' and TState = 3 then - RegDIH <= RegBusB(15 downto 8); - RegDIL <= RegBusB(7 downto 0); - end if; - if ExchangeDH = '1' and TState = 4 then - RegDIH <= RegBusA_r(15 downto 8); - RegDIL <= RegBusA_r(7 downto 0); - end if; - - if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then - RegDIH <= std_logic_vector(ID16(15 downto 8)); - RegDIL <= std_logic_vector(ID16(7 downto 0)); - end if; - end process; - - Regs : T80_Reg - port map( - Clk => CLK_n, - CEN => ClkEn, - WEH => RegWEH, - WEL => RegWEL, - AddrA => RegAddrA, - AddrB => RegAddrB, - AddrC => RegAddrC, - DIH => RegDIH, - DIL => RegDIL, - DOAH => RegBusA(15 downto 8), - DOAL => RegBusA(7 downto 0), - DOBH => RegBusB(15 downto 8), - DOBL => RegBusB(7 downto 0), - DOCH => RegBusC(15 downto 8), - DOCL => RegBusC(7 downto 0)); - ---------------------------------------------------------------------------- --- --- Buses --- ---------------------------------------------------------------------------- - process (CLK_n) - begin - if CLK_n'event and CLK_n = '1' then - if ClkEn = '1' then - case Set_BusB_To is - when "0111" => - BusB <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusB_To(0) = '1' then - BusB <= RegBusB(7 downto 0); - else - BusB <= RegBusB(15 downto 8); - end if; - when "0110" => - BusB <= DI_Reg; - when "1000" => - BusB <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusB <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusB <= "00000001"; - when "1011" => - BusB <= F; - when "1100" => - BusB <= std_logic_vector(PC(7 downto 0)); - when "1101" => - BusB <= std_logic_vector(PC(15 downto 8)); - when "1110" => - BusB <= "00000000"; - when others => - BusB <= "--------"; - end case; - - case Set_BusA_To is - when "0111" => - BusA <= ACC; - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => - if Set_BusA_To(0) = '1' then - BusA <= RegBusA(7 downto 0); - else - BusA <= RegBusA(15 downto 8); - end if; - when "0110" => - BusA <= DI_Reg; - when "1000" => - BusA <= std_logic_vector(SP(7 downto 0)); - when "1001" => - BusA <= std_logic_vector(SP(15 downto 8)); - when "1010" => - BusA <= "00000000"; - when others => - BusB <= "--------"; - end case; - end if; - end if; - end process; - ---------------------------------------------------------------------------- --- --- Generate external control signals --- ---------------------------------------------------------------------------- - process (RESET_n,CLK_n) - begin - if RESET_n = '0' then - RFSH_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then - RFSH_n <= '0'; - else - RFSH_n <= '1'; - end if; - end if; - end if; - end process; - - MC <= std_logic_vector(MCycle); - TS <= std_logic_vector(TState); - DI_Reg <= DI; - HALT_n <= not Halt_FF; - BUSAK_n <= not BusAck; - IntCycle_n <= not IntCycle; - IntE <= IntE_FF1; - IORQ <= IORQ_i; - Stop <= I_DJNZ; - -------------------------------------------------------------------------- --- --- Syncronise inputs --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - variable OldNMI_n : std_logic; - begin - if RESET_n = '0' then - BusReq_s <= '0'; - INT_s <= '0'; - NMI_s <= '0'; - OldNMI_n := '0'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - BusReq_s <= not BUSRQ_n; - INT_s <= not INT_n; - if NMICycle = '1' then - NMI_s <= '0'; - elsif NMI_n = '0' and OldNMI_n = '1' then - NMI_s <= '1'; - end if; - OldNMI_n := NMI_n; - end if; - end if; - end process; - -------------------------------------------------------------------------- --- --- Main state machine --- -------------------------------------------------------------------------- - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - MCycle <= "001"; - TState <= "000"; - Pre_XY_F_M <= "000"; - Halt_FF <= '0'; - BusAck <= '0'; - NMICycle <= '0'; - IntCycle <= '0'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - No_BTR <= '0'; - Auto_Wait_t1 <= '0'; - Auto_Wait_t2 <= '0'; - M1_n <= '1'; - elsif CLK_n'event and CLK_n = '1' then - if CEN = '1' then - if T_Res = '1' then - Auto_Wait_t1 <= '0'; - else - Auto_Wait_t1 <= Auto_Wait or IORQ_i; - end if; - Auto_Wait_t2 <= Auto_Wait_t1; - No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or - (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or - (I_BTR and (not IR(4) or F(Flag_Z))); - if TState = 2 then - if SetEI = '1' then - IntE_FF1 <= '1'; - IntE_FF2 <= '1'; - end if; - if I_RETN = '1' then - IntE_FF1 <= IntE_FF2; - end if; - end if; - if TState = 3 then - if SetDI = '1' then - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - end if; - if IntCycle = '1' or NMICycle = '1' then - Halt_FF <= '0'; - end if; - if MCycle = "001" and TState = 2 and Wait_n = '1' then - M1_n <= '1'; - end if; - if BusReq_s = '1' and BusAck = '1' then - else - BusAck <= '0'; - if TState = 2 and Wait_n = '0' then - elsif T_Res = '1' then - if Halt = '1' then - Halt_FF <= '1'; - end if; - if BusReq_s = '1' then - BusAck <= '1'; - else - TState <= "001"; - if NextIs_XY_Fetch = '1' then - MCycle <= "110"; - Pre_XY_F_M <= MCycle; - if IR = "00110110" and Mode = 0 then - Pre_XY_F_M <= "010"; - end if; - elsif (MCycle = "111") or - (MCycle = "110" and Mode = 1 and ISet /= "01") then - MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); - elsif (MCycle = MCycles) or - No_BTR = '1' or - (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then - M1_n <= '0'; - MCycle <= "001"; - IntCycle <= '0'; - NMICycle <= '0'; - if NMI_s = '1' and Prefix = "00" then - NMICycle <= '1'; - IntE_FF1 <= '0'; - elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then - IntCycle <= '1'; - IntE_FF1 <= '0'; - IntE_FF2 <= '0'; - end if; - else - MCycle <= std_logic_vector(unsigned(MCycle) + 1); - end if; - end if; - else - if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor - (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then - TState <= TState + 1; - end if; - end if; - end if; - if TState = 0 then - M1_n <= '0'; - end if; - end if; - end if; - end process; - - process (IntCycle, NMICycle, MCycle) - begin - Auto_Wait <= '0'; - if IntCycle = '1' or NMICycle = '1' then - if MCycle = "001" then - Auto_Wait <= '1'; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Sega - SG1000/rtl/t80/T80_ALU.vhd b/Console_MiST/Sega - SG1000/rtl/t80/T80_ALU.vhd deleted file mode 100644 index 86fddce7..00000000 --- a/Console_MiST/Sega - SG1000/rtl/t80/T80_ALU.vhd +++ /dev/null @@ -1,351 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0238 : Fixed zero flag for 16 bit SBC and ADC --- --- 0240 : Added GB operations --- --- 0242 : Cleanup --- --- 0247 : Cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_ALU is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); -end T80_ALU; - -architecture rtl of T80_ALU is - - procedure AddSub(A : std_logic_vector; - B : std_logic_vector; - Sub : std_logic; - Carry_In : std_logic; - signal Res : out std_logic_vector; - signal Carry : out std_logic) is - variable B_i : unsigned(A'length - 1 downto 0); - variable Res_i : unsigned(A'length + 1 downto 0); - begin - if Sub = '1' then - B_i := not unsigned(B); - else - B_i := unsigned(B); - end if; - Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); - Carry <= Res_i(A'length + 1); - Res <= std_logic_vector(Res_i(A'length downto 1)); - end; - - -- AddSub variables (temporary signals) - signal UseCarry : std_logic; - signal Carry7_v : std_logic; - signal Overflow_v : std_logic; - signal HalfCarry_v : std_logic; - signal Carry_v : std_logic; - signal Q_v : std_logic_vector(7 downto 0); - - signal BitMask : std_logic_vector(7 downto 0); - -begin - - with IR(5 downto 3) select BitMask <= "00000001" when "000", - "00000010" when "001", - "00000100" when "010", - "00001000" when "011", - "00010000" when "100", - "00100000" when "101", - "01000000" when "110", - "10000000" when others; - - UseCarry <= not ALU_Op(2) and ALU_Op(0); - AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); - AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); - AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); - OverFlow_v <= Carry_v xor Carry7_v; - - process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) - variable Q_t : std_logic_vector(7 downto 0); - variable DAA_Q : unsigned(8 downto 0); - begin - Q_t := "--------"; - F_Out <= F_In; - DAA_Q := "---------"; - case ALU_Op is - when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => - F_Out(Flag_N) <= '0'; - F_Out(Flag_C) <= '0'; - case ALU_OP(2 downto 0) is - when "000" | "001" => -- ADD, ADC - Q_t := Q_v; - F_Out(Flag_C) <= Carry_v; - F_Out(Flag_H) <= HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "010" | "011" | "111" => -- SUB, SBC, CP - Q_t := Q_v; - F_Out(Flag_N) <= '1'; - F_Out(Flag_C) <= not Carry_v; - F_Out(Flag_H) <= not HalfCarry_v; - F_Out(Flag_P) <= OverFlow_v; - when "100" => -- AND - Q_t(7 downto 0) := BusA and BusB; - F_Out(Flag_H) <= '1'; - when "101" => -- XOR - Q_t(7 downto 0) := BusA xor BusB; - F_Out(Flag_H) <= '0'; - when others => -- OR "110" - Q_t(7 downto 0) := BusA or BusB; - F_Out(Flag_H) <= '0'; - end case; - if ALU_Op(2 downto 0) = "111" then -- CP - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - else - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - end if; - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - if Z16 = '1' then - F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC - end if; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - case ALU_Op(2 downto 0) is - when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP - when others => - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - end case; - if Arith16 = '1' then - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - F_Out(Flag_P) <= F_In(Flag_P); - end if; - when "1100" => - -- DAA - F_Out(Flag_H) <= F_In(Flag_H); - F_Out(Flag_C) <= F_In(Flag_C); - DAA_Q(7 downto 0) := unsigned(BusA); - DAA_Q(8) := '0'; - if F_In(Flag_N) = '0' then - -- After addition - -- Alow > 9 or H = 1 - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if (DAA_Q(3 downto 0) > 9) then - F_Out(Flag_H) <= '1'; - else - F_Out(Flag_H) <= '0'; - end if; - DAA_Q := DAA_Q + 6; - end if; - -- new Ahigh > 9 or C = 1 - if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q + 96; -- 0x60 - end if; - else - -- After subtraction - if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then - if DAA_Q(3 downto 0) > 5 then - F_Out(Flag_H) <= '0'; - end if; - DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; - end if; - if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then - DAA_Q := DAA_Q - 352; -- 0x160 - end if; - end if; - F_Out(Flag_X) <= DAA_Q(3); - F_Out(Flag_Y) <= DAA_Q(5); - F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); - Q_t := std_logic_vector(DAA_Q(7 downto 0)); - if DAA_Q(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= DAA_Q(7); - F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor - DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); - when "1101" | "1110" => - -- RLD, RRD - Q_t(7 downto 4) := BusA(7 downto 4); - if ALU_Op(0) = '1' then - Q_t(3 downto 0) := BusB(7 downto 4); - else - Q_t(3 downto 0) := BusB(3 downto 0); - end if; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_S) <= Q_t(7); - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - when "1001" => - -- BIT - Q_t(7 downto 0) := BusB and BitMask; - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - F_Out(Flag_P) <= '1'; - else - F_Out(Flag_Z) <= '0'; - F_Out(Flag_P) <= '0'; - end if; - F_Out(Flag_H) <= '1'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= '0'; - F_Out(Flag_Y) <= '0'; - if IR(2 downto 0) /= "110" then - F_Out(Flag_X) <= BusB(3); - F_Out(Flag_Y) <= BusB(5); - end if; - when "1010" => - -- SET - Q_t(7 downto 0) := BusB or BitMask; - when "1011" => - -- RES - Q_t(7 downto 0) := BusB and not BitMask; - when "1000" => - -- ROT - case IR(5 downto 3) is - when "000" => -- RLC - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := BusA(7); - F_Out(Flag_C) <= BusA(7); - when "010" => -- RL - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(7); - when "001" => -- RRC - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(0); - F_Out(Flag_C) <= BusA(0); - when "011" => -- RR - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := F_In(Flag_C); - F_Out(Flag_C) <= BusA(0); - when "100" => -- SLA - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '0'; - F_Out(Flag_C) <= BusA(7); - when "110" => -- SLL (Undocumented) / SWAP - if Mode = 3 then - Q_t(7 downto 4) := BusA(3 downto 0); - Q_t(3 downto 0) := BusA(7 downto 4); - F_Out(Flag_C) <= '0'; - else - Q_t(7 downto 1) := BusA(6 downto 0); - Q_t(0) := '1'; - F_Out(Flag_C) <= BusA(7); - end if; - when "101" => -- SRA - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := BusA(7); - F_Out(Flag_C) <= BusA(0); - when others => -- SRL - Q_t(6 downto 0) := BusA(7 downto 1); - Q_t(7) := '0'; - F_Out(Flag_C) <= BusA(0); - end case; - F_Out(Flag_H) <= '0'; - F_Out(Flag_N) <= '0'; - F_Out(Flag_X) <= Q_t(3); - F_Out(Flag_Y) <= Q_t(5); - F_Out(Flag_S) <= Q_t(7); - if Q_t(7 downto 0) = "00000000" then - F_Out(Flag_Z) <= '1'; - else - F_Out(Flag_Z) <= '0'; - end if; - F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor - Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); - if ISet = "00" then - F_Out(Flag_P) <= F_In(Flag_P); - F_Out(Flag_S) <= F_In(Flag_S); - F_Out(Flag_Z) <= F_In(Flag_Z); - end if; - when others => - null; - end case; - Q <= Q_t; - end process; - -end; diff --git a/Console_MiST/Sega - SG1000/rtl/t80/T80_MCode.vhd b/Console_MiST/Sega - SG1000/rtl/t80/T80_MCode.vhd deleted file mode 100644 index 7322994a..00000000 --- a/Console_MiST/Sega - SG1000/rtl/t80/T80_MCode.vhd +++ /dev/null @@ -1,1938 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed IM 1 --- --- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test --- --- 0235 : Added IM 2 fix by Mike Johnson --- --- 0238 : Added NoRead signal --- --- 0238b: Fixed instruction timing for POP and DJNZ --- --- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes --- --- 0242 : Fixed I/O instruction timing, cleanup --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_MCode is - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); -end T80_MCode; - -architecture rtl of T80_MCode is - - constant aNone : std_logic_vector(2 downto 0) := "111"; - constant aBC : std_logic_vector(2 downto 0) := "000"; - constant aDE : std_logic_vector(2 downto 0) := "001"; - constant aXY : std_logic_vector(2 downto 0) := "010"; - constant aIOA : std_logic_vector(2 downto 0) := "100"; - constant aSP : std_logic_vector(2 downto 0) := "101"; - constant aZI : std_logic_vector(2 downto 0) := "110"; --- constant aNone : std_logic_vector(2 downto 0) := "000"; --- constant aXY : std_logic_vector(2 downto 0) := "001"; --- constant aIOA : std_logic_vector(2 downto 0) := "010"; --- constant aSP : std_logic_vector(2 downto 0) := "011"; --- constant aBC : std_logic_vector(2 downto 0) := "100"; --- constant aDE : std_logic_vector(2 downto 0) := "101"; --- constant aZI : std_logic_vector(2 downto 0) := "110"; - - function is_cc_true( - F : std_logic_vector(7 downto 0); - cc : bit_vector(2 downto 0) - ) return boolean is - begin - if Mode = 3 then - case cc is - when "000" => return F(7) = '0'; -- NZ - when "001" => return F(7) = '1'; -- Z - when "010" => return F(4) = '0'; -- NC - when "011" => return F(4) = '1'; -- C - when "100" => return false; - when "101" => return false; - when "110" => return false; - when "111" => return false; - end case; - else - case cc is - when "000" => return F(6) = '0'; -- NZ - when "001" => return F(6) = '1'; -- Z - when "010" => return F(0) = '0'; -- NC - when "011" => return F(0) = '1'; -- C - when "100" => return F(2) = '0'; -- PO - when "101" => return F(2) = '1'; -- PE - when "110" => return F(7) = '0'; -- P - when "111" => return F(7) = '1'; -- M - end case; - end if; - end; - -begin - - process (IR, ISet, MCycle, F, NMICycle, IntCycle) - variable DDD : std_logic_vector(2 downto 0); - variable SSS : std_logic_vector(2 downto 0); - variable DPair : std_logic_vector(1 downto 0); - variable IRB : bit_vector(7 downto 0); - begin - DDD := IR(5 downto 3); - SSS := IR(2 downto 0); - DPair := IR(5 downto 4); - IRB := to_bitvector(IR); - - MCycles <= "001"; - if MCycle = "001" then - TStates <= "100"; - else - TStates <= "011"; - end if; - Prefix <= "00"; - Inc_PC <= '0'; - Inc_WZ <= '0'; - IncDec_16 <= "0000"; - Read_To_Acc <= '0'; - Read_To_Reg <= '0'; - Set_BusB_To <= "0000"; - Set_BusA_To <= "0000"; - ALU_Op <= "0" & IR(5 downto 3); - Save_ALU <= '0'; - PreserveC <= '0'; - Arith16 <= '0'; - IORQ <= '0'; - Set_Addr_To <= aNone; - Jump <= '0'; - JumpE <= '0'; - JumpXY <= '0'; - Call <= '0'; - RstP <= '0'; - LDZ <= '0'; - LDW <= '0'; - LDSPHL <= '0'; - Special_LD <= "000"; - ExchangeDH <= '0'; - ExchangeRp <= '0'; - ExchangeAF <= '0'; - ExchangeRS <= '0'; - I_DJNZ <= '0'; - I_CPL <= '0'; - I_CCF <= '0'; - I_SCF <= '0'; - I_RETN <= '0'; - I_BT <= '0'; - I_BC <= '0'; - I_BTR <= '0'; - I_RLD <= '0'; - I_RRD <= '0'; - I_INRC <= '0'; - SetDI <= '0'; - SetEI <= '0'; - IMode <= "11"; - Halt <= '0'; - NoRead <= '0'; - Write <= '0'; - - case ISet is - when "00" => - ------------------------------------------------------------------------------- --- --- Unprefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is --- 8 BIT LOAD GROUP - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- LD r,r' - Set_BusB_To(2 downto 0) <= SSS; - ExchangeRp <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => - -- LD r,n - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => - -- LD r,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - when others => null; - end case; - when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => - -- LD (HL),r - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110110" => - -- LD (HL),n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aXY; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00001010" => - -- LD A,(BC) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00011010" => - -- LD A,(DE) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - when 2 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "00111010" => - if Mode = 3 then - -- LDD A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end if; - when "00000010" => - -- LD (BC),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00010010" => - -- LD (DE),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aDE; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - when others => null; - end case; - when "00110010" => - if Mode = 3 then - -- LDD (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "1110"; - when others => null; - end case; - else - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - end if; - --- 16 BIT LOAD GROUP - when "00000001"|"00010001"|"00100001"|"00110001" => - -- LD dd,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1000"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - Inc_PC <= '1'; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1001"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "00101010" => - if Mode = 3 then - -- LDI A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Acc <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD HL,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end if; - when "00100010" => - if Mode = 3 then - -- LDI (HL),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IncDec_16 <= "0110"; - when others => null; - end case; - else - -- LD (nn),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "0101"; -- L - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "0100"; -- H - when 5 => - Write <= '1'; - when others => null; - end case; - end if; - when "11111001" => - -- LD SP,HL - TStates <= "110"; - LDSPHL <= '1'; - when "11000101"|"11010101"|"11100101"|"11110101" => - -- PUSH qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "0111"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 2 => - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - if DPAIR = "11" then - Set_BusB_To <= "1011"; - else - Set_BusB_To(2 downto 1) <= DPAIR; - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - Write <= '1'; - when 3 => - Write <= '1'; - when others => null; - end case; - when "11000001"|"11010001"|"11100001"|"11110001" => - -- POP qq - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "1011"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '1'; - end if; - when 3 => - IncDec_16 <= "0111"; - Read_To_Reg <= '1'; - if DPAIR = "11" then - Set_BusA_To(3 downto 0) <= "0111"; - else - Set_BusA_To(2 downto 1) <= DPAIR; - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - --- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP - when "11101011" => - if Mode /= 3 then - -- EX DE,HL - ExchangeDH <= '1'; - end if; - when "00001000" => - if Mode = 3 then - -- LD (nn),SP - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - Set_BusB_To <= "1000"; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - Set_BusB_To <= "1001"; - when 5 => - Write <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EX AF,AF' - ExchangeAF <= '1'; - end if; - when "11011001" => - if Mode = 3 then - -- RETI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - SetEI <= '1'; - when others => null; - end case; - elsif Mode < 2 then - -- EXX - ExchangeRS <= '1'; - end if; - when "11100011" => - if Mode /= 3 then - -- EX (SP),HL - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aSP; - when 2 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0101"; - Set_BusB_To <= "0101"; - Set_Addr_To <= aSP; - when 3 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - TStates <= "100"; - Write <= '1'; - when 4 => - Read_To_Reg <= '1'; - Set_BusA_To <= "0100"; - Set_BusB_To <= "0100"; - Set_Addr_To <= aSP; - when 5 => - IncDec_16 <= "1111"; - TStates <= "101"; - Write <= '1'; - when others => null; - end case; - end if; - --- 8 BIT ARITHMETIC AND LOGICAL GROUP - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- ADD A,r - -- ADC A,r - -- SUB A,r - -- SBC A,r - -- AND A,r - -- OR A,r - -- XOR A,r - -- CP A,r - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- ADD A,(HL) - -- ADC A,(HL) - -- SUB A,(HL) - -- SBC A,(HL) - -- AND A,(HL) - -- OR A,(HL) - -- XOR A,(HL) - -- CP A,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - when others => null; - end case; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- ADD A,n - -- ADC A,n - -- SUB A,n - -- SBC A,n - -- AND A,n - -- OR A,n - -- XOR A,n - -- CP A,n - MCycles <= "010"; - if MCycle = "010" then - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusA_To(2 downto 0) <= "111"; - end if; - when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => - -- INC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - when "00110100" => - -- INC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0000"; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => - -- DEC r - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - ALU_Op <= "0010"; - when "00110101" => - -- DEC (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - when 2 => - TStates <= "100"; - Set_Addr_To <= aXY; - ALU_Op <= "0010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - PreserveC <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= DDD; - when 3 => - Write <= '1'; - when others => null; - end case; - --- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS - when "00100111" => - -- DAA - Set_BusA_To(2 downto 0) <= "111"; - Read_To_Reg <= '1'; - ALU_Op <= "1100"; - Save_ALU <= '1'; - when "00101111" => - -- CPL - I_CPL <= '1'; - when "00111111" => - -- CCF - I_CCF <= '1'; - when "00110111" => - -- SCF - I_SCF <= '1'; - when "00000000" => - if NMICycle = '1' then - -- NMI - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when others => null; - end case; - elsif IntCycle = '1' then - -- INT (IM 2) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 1 => - LDZ <= '1'; - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - TStates <= "100"; - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - TStates <= "100"; - Write <= '1'; - when 4 => - Inc_PC <= '1'; - LDZ <= '1'; - when 5 => - Jump <= '1'; - when others => null; - end case; - else - -- NOP - end if; - when "01110110" => - -- HALT - Halt <= '1'; - when "11110011" => - -- DI - SetDI <= '1'; - when "11111011" => - -- EI - SetEI <= '1'; - --- 16 BIT ARITHMETIC GROUP - when "00001001"|"00011001"|"00101001"|"00111001" => - -- ADD HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - Arith16 <= '1'; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - Arith16 <= '1'; - when others => - end case; - when "00000011"|"00010011"|"00100011"|"00110011" => - -- INC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "01"; - IncDec_16(1 downto 0) <= DPair; - when "00001011"|"00011011"|"00101011"|"00111011" => - -- DEC ss - TStates <= "110"; - IncDec_16(3 downto 2) <= "11"; - IncDec_16(1 downto 0) <= DPair; - --- ROTATE AND SHIFT GROUP - when "00000111" - -- RLCA - |"00010111" - -- RLA - |"00001111" - -- RRCA - |"00011111" => - -- RRA - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - --- JUMP GROUP - when "11000011" => - -- JP nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - Jump <= '1'; - when others => null; - end case; - when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+C),A - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "0111"; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "01" => - -- LD (nn),A - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - Set_BusB_To <= "0111"; - when 4 => - Write <= '1'; - when others => null; - end case; - when "10" => - -- LD A,($FF00+C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => - end case; - when "11" => - -- LD A,(nn) - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - when 4 => - Read_To_Acc <= '1'; - when others => null; - end case; - end case; - else - -- JP cc,nn - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Jump <= '1'; - end if; - when others => null; - end case; - end if; - when "00011000" => - if Mode /= 2 then - -- JR e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00111000" => - if Mode /= 2 then - -- JR C,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00110000" => - if Mode /= 2 then - -- JR NC,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_C) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00101000" => - if Mode /= 2 then - -- JR Z,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '0' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "00100000" => - if Mode /= 2 then - -- JR NZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - if F(Flag_Z) = '1' then - MCycles <= "010"; - end if; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - when "11101001" => - -- JP (HL) - JumpXY <= '1'; - when "00010000" => - if Mode = 3 then - I_DJNZ <= '1'; - elsif Mode < 2 then - -- DJNZ,e - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - I_DJNZ <= '1'; - Set_BusB_To <= "1010"; - Set_BusA_To(2 downto 0) <= "000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - I_DJNZ <= '1'; - Inc_PC <= '1'; - when 3 => - NoRead <= '1'; - JumpE <= '1'; - TStates <= "101"; - when others => null; - end case; - end if; - --- CALL AND RETURN GROUP - when "11001101" => - -- CALL nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - IncDec_16 <= "1111"; - Inc_PC <= '1'; - TStates <= "100"; - Set_Addr_To <= aSP; - LDW <= '1'; - Set_BusB_To <= "1101"; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => - if IR(5) = '0' or Mode /= 3 then - -- CALL cc,nn - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Inc_PC <= '1'; - LDW <= '1'; - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - IncDec_16 <= "1111"; - Set_Addr_TO <= aSP; - TStates <= "100"; - Set_BusB_To <= "1101"; - else - MCycles <= "011"; - end if; - when 4 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 5 => - Write <= '1'; - Call <= '1'; - when others => null; - end case; - end if; - when "11001001" => - -- RET - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => - if IR(5) = '1' and Mode = 3 then - case IRB(4 downto 3) is - when "00" => - -- LD ($FF00+nn),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - when others => null; - end case; - when "01" => - -- ADD SP,n - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - ALU_Op <= "0000"; - Inc_PC <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To <= "1000"; - Set_BusB_To <= "0110"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To <= "1001"; - Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! - when others => - end case; - when "10" => - -- LD A,($FF00+nn) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - when others => null; - end case; - when "11" => - -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Set_BusA_To(2 downto 0) <= "101"; -- L - Read_To_Reg <= '1'; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Set_BusA_To(2 downto 0) <= "100"; -- H - Read_To_Reg <= '1'; - when others => null; - end case; - end case; - else - -- RET cc - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - if is_cc_true(F, to_bitvector(IR(5 downto 3))) then - Set_Addr_TO <= aSP; - else - MCycles <= "001"; - end if; - TStates <= "101"; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - when others => null; - end case; - end if; - when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => - -- RST p - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1101"; - when 2 => - Write <= '1'; - IncDec_16 <= "1111"; - Set_Addr_To <= aSP; - Set_BusB_To <= "1100"; - when 3 => - Write <= '1'; - RstP <= '1'; - when others => null; - end case; - --- INPUT AND OUTPUT GROUP - when "11011011" => - if Mode /= 3 then - -- IN A,(n) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - when 3 => - Read_To_Acc <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - when "11010011" => - if Mode /= 3 then - -- OUT (n),A - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - Set_Addr_To <= aIOA; - Set_BusB_To <= "0111"; - when 3 => - Write <= '1'; - IORQ <= '1'; - when others => null; - end case; - end if; - ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- MULTIBYTE INSTRUCTIONS ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- - - when "11001011" => - if Mode /= 2 then - Prefix <= "01"; - end if; - - when "11101101" => - if Mode < 2 then - Prefix <= "10"; - end if; - - when "11011101"|"11111101" => - if Mode < 2 then - Prefix <= "11"; - end if; - - end case; - - when "01" => - ------------------------------------------------------------------------------- --- --- CB prefixed instructions --- ------------------------------------------------------------------------------- - - Set_BusA_To(2 downto 0) <= IR(2 downto 0); - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => - -- RLC r - -- RL r - -- RRC r - -- RR r - -- SLA r - -- SRA r - -- SRL r - -- SLL r (Undocumented) / SWAP r - if MCycle = "001" then - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => - -- RLC (HL) - -- RL (HL) - -- RRC (HL) - -- RR (HL) - -- SRA (HL) - -- SRL (HL) - -- SLA (HL) - -- SLL (HL) (Undocumented) / SWAP (HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" - |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" - |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" - |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" - |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" - |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" - |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" - |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => - -- BIT b,r - if MCycle = "001" then - Set_BusB_To(2 downto 0) <= IR(2 downto 0); - ALU_Op <= "1001"; - end if; - when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => - -- BIT b,(HL) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1001"; - TStates <= "100"; - when others => - end case; - when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => - -- SET b,r - if MCycle = "001" then - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => - -- SET b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1010"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" - |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" - |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" - |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" - |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => - -- RES b,r - if MCycle = "001" then - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - end if; - when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => - -- RES b,(HL) - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 | 7 => - Set_Addr_To <= aXY; - when 2 => - ALU_Op <= "1011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_Addr_To <= aXY; - TStates <= "100"; - when 3 => - Write <= '1'; - when others => - end case; - end case; - - when others => - ------------------------------------------------------------------------------- --- --- ED prefixed instructions --- ------------------------------------------------------------------------------- - - case IRB is - when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" - |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" - |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" - |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" - |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" - |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" - |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" - |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" - - - |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" - |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" - |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" - |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" - | "10100100"|"10100101"|"10100110"|"10100111" - | "10101100"|"10101101"|"10101110"|"10101111" - | "10110100"|"10110101"|"10110110"|"10110111" - | "10111100"|"10111101"|"10111110"|"10111111" - |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" - |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" - |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" - |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" - |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" - |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" - |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" - |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => - null; -- NOP, undocumented - when "01111110"|"01111111" => - -- NOP, undocumented - null; --- 8 BIT LOAD GROUP - when "01010111" => - -- LD A,I - Special_LD <= "100"; - TStates <= "101"; - when "01011111" => - -- LD A,R - Special_LD <= "101"; - TStates <= "101"; - when "01000111" => - -- LD I,A - Special_LD <= "110"; - TStates <= "101"; - when "01001111" => - -- LD R,A - Special_LD <= "111"; - TStates <= "101"; --- 16 BIT LOAD GROUP - when "01001011"|"01011011"|"01101011"|"01111011" => - -- LD dd,(nn) - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - when 4 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1000"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '1'; - end if; - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - when 5 => - Read_To_Reg <= '1'; - if IR(5 downto 4) = "11" then - Set_BusA_To <= "1001"; - else - Set_BusA_To(2 downto 1) <= IR(5 downto 4); - Set_BusA_To(0) <= '0'; - end if; - when others => null; - end case; - when "01000011"|"01010011"|"01100011"|"01110011" => - -- LD (nn),dd - MCycles <= "101"; - case to_integer(unsigned(MCycle)) is - when 2 => - Inc_PC <= '1'; - LDZ <= '1'; - when 3 => - Set_Addr_To <= aZI; - Inc_PC <= '1'; - LDW <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1000"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - Set_BusB_To(3) <= '0'; - end if; - when 4 => - Inc_WZ <= '1'; - Set_Addr_To <= aZI; - Write <= '1'; - if IR(5 downto 4) = "11" then - Set_BusB_To <= "1001"; - else - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - Set_BusB_To(3) <= '0'; - end if; - when 5 => - Write <= '1'; - when others => null; - end case; - when "10100000" | "10101000" | "10110000" | "10111000" => - -- LDI, LDD, LDIR, LDDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0000"; - Set_Addr_To <= aDE; - if IR(3) = '0' then - IncDec_16 <= "0110"; -- IX - else - IncDec_16 <= "1110"; - end if; - when 3 => - I_BT <= '1'; - TStates <= "101"; - Write <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0101"; -- DE - else - IncDec_16 <= "1101"; - end if; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100001" | "10101001" | "10110001" | "10111001" => - -- CPI, CPD, CPIR, CPDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aXY; - IncDec_16 <= "1100"; -- BC - when 2 => - Set_BusB_To <= "0110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "0111"; - Save_ALU <= '1'; - PreserveC <= '1'; - if IR(3) = '0' then - IncDec_16 <= "0110"; - else - IncDec_16 <= "1110"; - end if; - when 3 => - NoRead <= '1'; - I_BC <= '1'; - TStates <= "101"; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => - -- NEG - Alu_OP <= "0010"; - Set_BusB_To <= "0111"; - Set_BusA_To <= "1010"; - Read_To_Acc <= '1'; - Save_ALU <= '1'; - when "01000110"|"01001110"|"01100110"|"01101110" => - -- IM 0 - IMode <= "00"; - when "01010110"|"01110110" => - -- IM 1 - IMode <= "01"; - when "01011110"|"01110111" => - -- IM 2 - IMode <= "10"; --- 16 bit arithmetic - when "01001010"|"01011010"|"01101010"|"01111010" => - -- ADC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0001"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0001"; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '0'; - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01000010"|"01010010"|"01100010"|"01110010" => - -- SBC HL,ss - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "101"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - Set_BusB_To(0) <= '1'; - when others => - Set_BusB_To <= "1000"; - end case; - TStates <= "100"; - when 3 => - NoRead <= '1'; - ALU_Op <= "0011"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - Set_BusA_To(2 downto 0) <= "100"; - case to_integer(unsigned(IR(5 downto 4))) is - when 0|1|2 => - Set_BusB_To(2 downto 1) <= IR(5 downto 4); - when others => - Set_BusB_To <= "1001"; - end case; - when others => - end case; - when "01101111" => - -- RLD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - NoRead <= '1'; - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1101"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RLD <= '1'; - Write <= '1'; - when others => - end case; - when "01100111" => - -- RRD - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 2 => - Set_Addr_To <= aXY; - when 3 => - Read_To_Reg <= '1'; - Set_BusB_To(2 downto 0) <= "110"; - Set_BusA_To(2 downto 0) <= "111"; - ALU_Op <= "1110"; - TStates <= "100"; - Set_Addr_To <= aXY; - Save_ALU <= '1'; - when 4 => - I_RRD <= '1'; - Write <= '1'; - when others => - end case; - when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => - -- RETI, RETN - MCycles <= "011"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_TO <= aSP; - when 2 => - IncDec_16 <= "0111"; - Set_Addr_To <= aSP; - LDZ <= '1'; - when 3 => - Jump <= '1'; - IncDec_16 <= "0111"; - I_RETN <= '1'; - when others => null; - end case; - when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => - -- IN r,(C) - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - when 2 => - IORQ <= '1'; - if IR(5 downto 3) /= "110" then - Read_To_Reg <= '1'; - Set_BusA_To(2 downto 0) <= IR(5 downto 3); - end if; - I_INRC <= '1'; - when others => - end case; - when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => - -- OUT (C),r - -- OUT (C),0 - MCycles <= "010"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To(2 downto 0) <= IR(5 downto 3); - if IR(5 downto 3) = "110" then - Set_BusB_To(3) <= '1'; - end if; - when 2 => - Write <= '1'; - IORQ <= '1'; - when others => - end case; - when "10100010" | "10101010" | "10110010" | "10111010" => - -- INI, IND, INIR, INDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - Set_Addr_To <= aBC; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - IORQ <= '1'; - Set_BusB_To <= "0110"; - Set_Addr_To <= aXY; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - end if; - TStates <= "100"; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - when "10100011" | "10101011" | "10110011" | "10111011" => - -- OUTI, OUTD, OTIR, OTDR - MCycles <= "100"; - case to_integer(unsigned(MCycle)) is - when 1 => - TStates <= "101"; - Set_Addr_To <= aXY; - Set_BusB_To <= "1010"; - Set_BusA_To <= "0000"; - Read_To_Reg <= '1'; - Save_ALU <= '1'; - ALU_Op <= "0010"; - when 2 => - Set_BusB_To <= "0110"; - Set_Addr_To <= aBC; - when 3 => - if IR(3) = '0' then - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - else - --IncDec_16 <= "0010"; - IncDec_16 <= "0110"; - end if; - IORQ <= '1'; - Write <= '1'; - I_BTR <= '1'; - when 4 => - NoRead <= '1'; - TStates <= "101"; - when others => null; - end case; - end case; - - end case; - - if Mode = 1 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "011"; - end if; - end if; - - if Mode = 3 then - if MCycle = "001" then --- TStates <= "100"; - else - TStates <= "100"; - end if; - end if; - - if Mode < 2 then - if MCycle = "110" then - Inc_PC <= '1'; - if Mode = 1 then - Set_Addr_To <= aXY; - TStates <= "100"; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - end if; - if IRB = "00110110" or IRB = "11001011" then - Set_Addr_To <= aNone; - end if; - end if; - if MCycle = "111" then - if Mode = 0 then - TStates <= "101"; - end if; - if ISet /= "01" then - Set_Addr_To <= aXY; - end if; - Set_BusB_To(2 downto 0) <= SSS; - Set_BusB_To(3) <= '0'; - if IRB = "00110110" or ISet = "01" then - -- LD (HL),n - Inc_PC <= '1'; - else - NoRead <= '1'; - end if; - end if; - end if; - - end process; - -end; diff --git a/Console_MiST/Sega - SG1000/rtl/t80/T80_Pack.vhd b/Console_MiST/Sega - SG1000/rtl/t80/T80_Pack.vhd deleted file mode 100644 index ac7d34da..00000000 --- a/Console_MiST/Sega - SG1000/rtl/t80/T80_Pack.vhd +++ /dev/null @@ -1,208 +0,0 @@ --- --- Z80 compatible microprocessor core --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- - -library IEEE; -use IEEE.std_logic_1164.all; - -package T80_Pack is - - component T80 - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - IORQ : out std_logic; - NoRead : out std_logic; - Write : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DInst : in std_logic_vector(7 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0); - MC : out std_logic_vector(2 downto 0); - TS : out std_logic_vector(2 downto 0); - IntCycle_n : out std_logic; - IntE : out std_logic; - Stop : out std_logic - ); - end component; - - component T80_Reg - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); - end component; - - component T80_MCode - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - IR : in std_logic_vector(7 downto 0); - ISet : in std_logic_vector(1 downto 0); - MCycle : in std_logic_vector(2 downto 0); - F : in std_logic_vector(7 downto 0); - NMICycle : in std_logic; - IntCycle : in std_logic; - MCycles : out std_logic_vector(2 downto 0); - TStates : out std_logic_vector(2 downto 0); - Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD - Inc_PC : out std_logic; - Inc_WZ : out std_logic; - IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc - Read_To_Reg : out std_logic; - Read_To_Acc : out std_logic; - Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F - Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 - ALU_Op : out std_logic_vector(3 downto 0); - -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None - Save_ALU : out std_logic; - PreserveC : out std_logic; - Arith16 : out std_logic; - Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI - IORQ : out std_logic; - Jump : out std_logic; - JumpE : out std_logic; - JumpXY : out std_logic; - Call : out std_logic; - RstP : out std_logic; - LDZ : out std_logic; - LDW : out std_logic; - LDSPHL : out std_logic; - Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None - ExchangeDH : out std_logic; - ExchangeRp : out std_logic; - ExchangeAF : out std_logic; - ExchangeRS : out std_logic; - I_DJNZ : out std_logic; - I_CPL : out std_logic; - I_CCF : out std_logic; - I_SCF : out std_logic; - I_RETN : out std_logic; - I_BT : out std_logic; - I_BC : out std_logic; - I_BTR : out std_logic; - I_RLD : out std_logic; - I_RRD : out std_logic; - I_INRC : out std_logic; - SetDI : out std_logic; - SetEI : out std_logic; - IMode : out std_logic_vector(1 downto 0); - Halt : out std_logic; - NoRead : out std_logic; - Write : out std_logic - ); - end component; - - component T80_ALU - generic( - Mode : integer := 0; - Flag_C : integer := 0; - Flag_N : integer := 1; - Flag_P : integer := 2; - Flag_X : integer := 3; - Flag_H : integer := 4; - Flag_Y : integer := 5; - Flag_Z : integer := 6; - Flag_S : integer := 7 - ); - port( - Arith16 : in std_logic; - Z16 : in std_logic; - ALU_Op : in std_logic_vector(3 downto 0); - IR : in std_logic_vector(5 downto 0); - ISet : in std_logic_vector(1 downto 0); - BusA : in std_logic_vector(7 downto 0); - BusB : in std_logic_vector(7 downto 0); - F_In : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(7 downto 0); - F_Out : out std_logic_vector(7 downto 0) - ); - end component; - -end; diff --git a/Console_MiST/Sega - SG1000/rtl/t80/T80_Reg.vhd b/Console_MiST/Sega - SG1000/rtl/t80/T80_Reg.vhd deleted file mode 100644 index 828485fb..00000000 --- a/Console_MiST/Sega - SG1000/rtl/t80/T80_Reg.vhd +++ /dev/null @@ -1,105 +0,0 @@ --- --- T80 Registers, technology independent --- --- Version : 0244 --- --- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t51/ --- --- Limitations : --- --- File history : --- --- 0242 : Initial release --- --- 0244 : Changed to single register file --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity T80_Reg is - port( - Clk : in std_logic; - CEN : in std_logic; - WEH : in std_logic; - WEL : in std_logic; - AddrA : in std_logic_vector(2 downto 0); - AddrB : in std_logic_vector(2 downto 0); - AddrC : in std_logic_vector(2 downto 0); - DIH : in std_logic_vector(7 downto 0); - DIL : in std_logic_vector(7 downto 0); - DOAH : out std_logic_vector(7 downto 0); - DOAL : out std_logic_vector(7 downto 0); - DOBH : out std_logic_vector(7 downto 0); - DOBL : out std_logic_vector(7 downto 0); - DOCH : out std_logic_vector(7 downto 0); - DOCL : out std_logic_vector(7 downto 0) - ); -end T80_Reg; - -architecture rtl of T80_Reg is - - type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); - signal RegsH : Register_Image(0 to 7); - signal RegsL : Register_Image(0 to 7); - -begin - - process (Clk) - begin - if Clk'event and Clk = '1' then - if CEN = '1' then - if WEH = '1' then - RegsH(to_integer(unsigned(AddrA))) <= DIH; - end if; - if WEL = '1' then - RegsL(to_integer(unsigned(AddrA))) <= DIL; - end if; - end if; - end if; - end process; - - DOAH <= RegsH(to_integer(unsigned(AddrA))); - DOAL <= RegsL(to_integer(unsigned(AddrA))); - DOBH <= RegsH(to_integer(unsigned(AddrB))); - DOBL <= RegsL(to_integer(unsigned(AddrB))); - DOCH <= RegsH(to_integer(unsigned(AddrC))); - DOCL <= RegsL(to_integer(unsigned(AddrC))); - -end; diff --git a/Console_MiST/Sega - SG1000/rtl/t80/T80a.vhd b/Console_MiST/Sega - SG1000/rtl/t80/T80a.vhd deleted file mode 100644 index 5e189020..00000000 --- a/Console_MiST/Sega - SG1000/rtl/t80/T80a.vhd +++ /dev/null @@ -1,253 +0,0 @@ --- --- Z80 compatible microprocessor core, asynchronous top level --- --- Version : 0247 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0208 : First complete release --- --- 0211 : Fixed interrupt cycle --- --- 0235 : Updated for T80 interface change --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- --- 0247 : Fixed bus req/ack cycle --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80a is - generic( - Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - D : inout std_logic_vector(7 downto 0) - ); -end T80a; - -architecture rtl of T80a is - - signal CEN : std_logic; - signal Reset_s : std_logic; - signal IntCycle_n : std_logic; - signal IORQ : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal MREQ : std_logic; - signal MReq_Inhibit : std_logic; - signal Req_Inhibit : std_logic; - signal RD : std_logic; - signal MREQ_n_i : std_logic; - signal IORQ_n_i : std_logic; - signal RD_n_i : std_logic; - signal WR_n_i : std_logic; - signal RFSH_n_i : std_logic; - signal BUSAK_n_i : std_logic; - signal A_i : std_logic_vector(15 downto 0); - signal DO : std_logic_vector(7 downto 0); - signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser - signal Wait_s : std_logic; - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - -begin - - CEN <= '1'; - - BUSAK_n <= BUSAK_n_i; - MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); - RD_n_i <= not RD or Req_Inhibit; - - MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; - IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; - RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; - WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; - RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; - A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); - D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - Reset_s <= '0'; - elsif CLK_n'event and CLK_n = '1' then - Reset_s <= '1'; - end if; - end process; - - u0 : T80 - generic map( - Mode => Mode, - IOWait => 1) - port map( - CEN => CEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n_i, - HALT_n => HALT_n, - WAIT_n => Wait_s, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => Reset_s, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n_i, - CLK_n => CLK_n, - A => A_i, - DInst => D, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (CLK_n) - begin - if CLK_n'event and CLK_n = '0' then - Wait_s <= WAIT_n; - if TState = "011" and BUSAK_n_i = '1' then - DI_Reg <= to_x01(D); - end if; - end if; - end process; - - process (Reset_s,CLK_n) - begin - if Reset_s = '0' then - WR_n_i <= '1'; - elsif CLK_n'event and CLK_n = '1' then - WR_n_i <= '1'; - if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! - WR_n_i <= not Write; - end if; - end if; - end process; - - process (Reset_s,CLK_n) - begin - if Reset_s = '0' then - Req_Inhibit <= '0'; - elsif CLK_n'event and CLK_n = '1' then - if MCycle = "001" and TState = "010" then - Req_Inhibit <= '1'; - else - Req_Inhibit <= '0'; - end if; - end if; - end process; - - process (Reset_s,CLK_n) - begin - if Reset_s = '0' then - MReq_Inhibit <= '0'; - elsif CLK_n'event and CLK_n = '0' then - if MCycle = "001" and TState = "010" then - MReq_Inhibit <= '1'; - else - MReq_Inhibit <= '0'; - end if; - end if; - end process; - - process(Reset_s,CLK_n) - begin - if Reset_s = '0' then - RD <= '0'; - IORQ_n_i <= '1'; - MREQ <= '0'; - elsif CLK_n'event and CLK_n = '0' then - - if MCycle = "001" then - if TState = "001" then - RD <= IntCycle_n; - MREQ <= IntCycle_n; - IORQ_n_i <= IntCycle_n; - end if; - if TState = "011" then - RD <= '0'; - IORQ_n_i <= '1'; - MREQ <= '1'; - end if; - if TState = "100" then - MREQ <= '0'; - end if; - else - if TState = "001" and NoRead = '0' then - RD <= not Write; - IORQ_n_i <= not IORQ; - MREQ <= not IORQ; - end if; - if TState = "011" then - RD <= '0'; - IORQ_n_i <= '1'; - MREQ <= '0'; - end if; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Sega - SG1000/rtl/t80/T80se.vhd b/Console_MiST/Sega - SG1000/rtl/t80/T80se.vhd deleted file mode 100644 index ac8886a8..00000000 --- a/Console_MiST/Sega - SG1000/rtl/t80/T80se.vhd +++ /dev/null @@ -1,184 +0,0 @@ --- --- Z80 compatible microprocessor core, synchronous top level with clock enable --- Different timing than the original z80 --- Inputs needs to be synchronous and outputs may glitch --- --- Version : 0242 --- --- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --- --- All rights reserved --- --- Redistribution and use in source and synthezised forms, with or without --- modification, are permitted provided that the following conditions are met: --- --- Redistributions of source code must retain the above copyright notice, --- this list of conditions and the following disclaimer. --- --- Redistributions in synthesized form must reproduce the above copyright --- notice, this list of conditions and the following disclaimer in the --- documentation and/or other materials provided with the distribution. --- --- Neither the name of the author nor the names of other contributors may --- be used to endorse or promote products derived from this software without --- specific prior written permission. --- --- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR --- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE --- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR --- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF --- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS --- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN --- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) --- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE --- POSSIBILITY OF SUCH DAMAGE. --- --- Please report bugs to the author, but before you do so, please --- make sure that this is not a derivative work and that --- you have the latest version of this file. --- --- The latest version of this file can be found at: --- http://www.opencores.org/cvsweb.shtml/t80/ --- --- Limitations : --- --- File history : --- --- 0235 : First release --- --- 0236 : Added T2Write generic --- --- 0237 : Fixed T2Write with wait state --- --- 0238 : Updated for T80 interface change --- --- 0240 : Updated for T80 interface change --- --- 0242 : Updated for T80 interface change --- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.T80_Pack.all; - -entity T80se is - generic( - Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB - T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 - IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle - ); - port( - RESET_n : in std_logic; - CLK_n : in std_logic; - CLKEN : in std_logic; - WAIT_n : in std_logic; - INT_n : in std_logic; - NMI_n : in std_logic; - BUSRQ_n : in std_logic; - M1_n : out std_logic; - MREQ_n : out std_logic; - IORQ_n : out std_logic; - RD_n : out std_logic; - WR_n : out std_logic; - RFSH_n : out std_logic; - HALT_n : out std_logic; - BUSAK_n : out std_logic; - A : out std_logic_vector(15 downto 0); - DI : in std_logic_vector(7 downto 0); - DO : out std_logic_vector(7 downto 0) - ); -end T80se; - -architecture rtl of T80se is - - signal IntCycle_n : std_logic; - signal NoRead : std_logic; - signal Write : std_logic; - signal IORQ : std_logic; - signal DI_Reg : std_logic_vector(7 downto 0); - signal MCycle : std_logic_vector(2 downto 0); - signal TState : std_logic_vector(2 downto 0); - -begin - - u0 : T80 - generic map( - Mode => Mode, - IOWait => IOWait) - port map( - CEN => CLKEN, - M1_n => M1_n, - IORQ => IORQ, - NoRead => NoRead, - Write => Write, - RFSH_n => RFSH_n, - HALT_n => HALT_n, - WAIT_n => Wait_n, - INT_n => INT_n, - NMI_n => NMI_n, - RESET_n => RESET_n, - BUSRQ_n => BUSRQ_n, - BUSAK_n => BUSAK_n, - CLK_n => CLK_n, - A => A, - DInst => DI, - DI => DI_Reg, - DO => DO, - MC => MCycle, - TS => TState, - IntCycle_n => IntCycle_n); - - process (RESET_n, CLK_n) - begin - if RESET_n = '0' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - DI_Reg <= "00000000"; - elsif CLK_n'event and CLK_n = '1' then - if CLKEN = '1' then - RD_n <= '1'; - WR_n <= '1'; - IORQ_n <= '1'; - MREQ_n <= '1'; - if MCycle = "001" then - if TState = "001" or (TState = "010" and Wait_n = '0') then - RD_n <= not IntCycle_n; - MREQ_n <= not IntCycle_n; - IORQ_n <= IntCycle_n; - end if; - if TState = "011" then - MREQ_n <= '0'; - end if; - else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then - RD_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - if T2Write = 0 then - if TState = "010" and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - else - if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then - WR_n <= '0'; - IORQ_n <= not IORQ; - MREQ_n <= IORQ; - end if; - end if; - end if; - if TState = "010" and Wait_n = '1' then - DI_Reg <= DI; - end if; - end if; - end if; - end process; - -end; diff --git a/Console_MiST/Sega - SG1000/rtl/tv_video.vhd b/Console_MiST/Sega - SG1000/rtl/tv_video.vhd deleted file mode 100644 index b75ce0d4..00000000 --- a/Console_MiST/Sega - SG1000/rtl/tv_video.vhd +++ /dev/null @@ -1,121 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity tv_video is - Port ( - clk8: in STD_LOGIC; - clk64: in STD_LOGIC; - pal: in STD_LOGIC; - x: out unsigned(8 downto 0); - y: out unsigned(7 downto 0); - vblank: out STD_LOGIC; - hblank: out STD_LOGIC; - color: in STD_LOGIC_VECTOR(5 downto 0); - csync: out STD_LOGIC; - video: out STD_LOGIC_VECTOR(6 downto 1)); -end tv_video; - -architecture Behavioral of tv_video is - - component color_encoder is - Port ( - clk: in STD_LOGIC; - pal: in STD_LOGIC; - sync: in STD_LOGIC; - line_visible: in STD_LOGIC; - line_even: in STD_LOGIC; - color: in STD_LOGIC_VECTOR (5 downto 0); - outputs: out STD_LOGIC_VECTOR (5 downto 0)); - end component; - - signal hcount: unsigned(8 downto 0) := (others => '0'); - signal vcount: unsigned(8 downto 0) := (others => '0'); - signal y9: unsigned(8 downto 0); - - signal in_vbl: std_logic; - signal screen_sync: std_logic; - signal vbl_sync: std_logic; - - signal sync: std_logic; - signal line_visible: std_logic; - signal line_even: std_logic; - -begin - csync <= sync; - - process (clk8) - begin - if rising_edge(clk8) then - if hcount=507 then - hcount <= (others => '0'); - if vcount=261 then - vcount <= (others=>'0'); - else - vcount <= vcount + 1; - end if; - else - hcount <= hcount + 1; - end if; - end if; - end process; - - process (hcount) - begin - if hcount<38 then - screen_sync <= '0'; - else - screen_sync <= '1'; - end if; - end process; - - in_vbl <= '1' when vcount<9 else '0'; - - x <= hcount-166; - y9 <= vcount-40; - y <= y9(7 downto 0); - vblank <= '1' when hcount=0 and vcount=0 else '0'; - hblank <= '1' when hcount=0 else '0'; - line_visible <= not in_vbl; - line_even <= not vcount(0); - - process (vcount,hcount) - begin - if vcount<3 or (vcount>=6 and vcount<9) then - -- _^^^^^_^^^^^ : low pulse = 2.35us - if hcount<19 or (hcount>=254 and hcount<254+19) then - vbl_sync <= '0'; - else - vbl_sync <= '1'; - end if; - else - -- ____^^ : high pulse = 4.7us - if hcount<(254-38) or (hcount>=254 and hcount<508-38) then - vbl_sync <= '0'; - else - vbl_sync <= '1'; - end if; - end if; - end process; - - process (in_vbl,screen_sync,vbl_sync) - begin - if in_vbl='1' then - sync <= vbl_sync; - else - sync <= screen_sync; - end if; - end process; - - encode_inst: color_encoder - port map ( - clk => clk64, - pal => pal, - sync => sync, - line_visible => line_visible, - line_even => line_even, - color => color, - outputs => video); - -end Behavioral; - diff --git a/Console_MiST/Sega - SG1000/rtl/vdp/vdp.vhd b/Console_MiST/Sega - SG1000/rtl/vdp/vdp.vhd deleted file mode 100644 index 5deab954..00000000 --- a/Console_MiST/Sega - SG1000/rtl/vdp/vdp.vhd +++ /dev/null @@ -1,296 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity vdp is - port ( - cpu_clk: in STD_LOGIC; - vdp_clk: in STD_LOGIC; - RD_n: in STD_LOGIC; - WR_n: in STD_LOGIC; - IRQ_n: out STD_LOGIC; - A: in STD_LOGIC_VECTOR (7 downto 0); - D_in: in STD_LOGIC_VECTOR (7 downto 0); - D_out: out STD_LOGIC_VECTOR (7 downto 0); - x: unsigned(8 downto 0); - y: unsigned(7 downto 0); - vblank: std_logic; - hblank: std_logic; - color: out std_logic_vector (5 downto 0)); -end vdp; - -architecture Behavioral of vdp is - - component vdp_main is - port ( - clk: in std_logic; - vram_A: out std_logic_vector(13 downto 0); - vram_D: in std_logic_vector(7 downto 0); - cram_A: out std_logic_vector(4 downto 0); - cram_D: in std_logic_vector(5 downto 0); - - x: unsigned(8 downto 0); - y: unsigned(7 downto 0); - - color: out std_logic_vector (5 downto 0); - - display_on: in std_logic; - mask_column0: in std_logic; - overscan: in std_logic_vector (3 downto 0); - - bg_address: in std_logic_vector (2 downto 0); - bg_scroll_x: in unsigned(7 downto 0); - bg_scroll_y: in unsigned(7 downto 0); - disable_hscroll: in std_logic; - - spr_address: in std_logic_vector (5 downto 0); - spr_high_bit: in std_logic; - spr_shift: in std_logic; - spr_tall: in std_logic); - end component; - - component vdp_cram is - port ( - cpu_clk: in STD_LOGIC; - cpu_WE: in std_logic; - cpu_A: in std_logic_vector(4 downto 0); - cpu_D: in std_logic_vector(5 downto 0); - vdp_clk: in STD_LOGIC; - vdp_A: in std_logic_vector(4 downto 0); - vdp_D: out std_logic_vector(5 downto 0)); - end component; - - -- helper bits - signal data_write: std_logic; - signal address_ff: std_logic := '0'; - signal to_cram: boolean := false; - - -- vram and cram lines for the cpu interface - signal xram_cpu_A: std_logic_vector(13 downto 0); - signal vram_cpu_WE: std_logic; - signal cram_cpu_WE: std_logic; - signal vram_cpu_D_out: std_logic_vector(7 downto 0); - signal xram_cpu_A_incr: std_logic := '0'; - - -- vram and cram lines for the video interface - signal vram_vdp_A: std_logic_vector(13 downto 0); - signal vram_vdp_D: std_logic_vector(7 downto 0); - signal cram_vdp_A: std_logic_vector(4 downto 0); - signal cram_vdp_D: std_logic_vector(5 downto 0); - - -- control bits - signal display_on: std_logic := '1'; - signal disable_hscroll: std_logic := '0'; - signal mask_column0: std_logic := '0'; - signal overscan: std_logic_vector (3 downto 0) := "0000"; - signal irq_frame_en: std_logic := '0'; - signal irq_line_en: std_logic := '0'; - signal irq_line_count: unsigned(7 downto 0) := (others=>'1'); - signal bg_address: std_logic_vector (2 downto 0) := (others=>'0'); - signal bg_scroll_x: unsigned(7 downto 0) := (others=>'0'); - signal bg_scroll_y: unsigned(7 downto 0) := (others=>'0'); - signal spr_address: std_logic_vector (5 downto 0) := (others=>'0'); - signal spr_shift: std_logic := '0'; - signal spr_tall: std_logic := '0'; - signal spr_high_bit: std_logic := '0'; - - -- various counters - signal last_y0: std_logic := '0'; - signal virq_flag: std_logic := '0'; - signal reset_virq_flag: boolean := false; - signal irq_counter: unsigned(4 downto 0) := (others=>'0'); - signal hbl_counter: unsigned(7 downto 0) := (others=>'0'); - signal vbl_irq: std_logic; - signal hbl_irq: std_logic; - -begin - - vdp_main_inst: vdp_main - port map( - clk => vdp_clk, - vram_A => vram_vdp_A, - vram_D => vram_vdp_D, - cram_A => cram_vdp_A, - cram_D => cram_vdp_D, - - x => x, - y => y, - color => color, - - display_on => display_on, - mask_column0 => mask_column0, - overscan => overscan, - - bg_address => bg_address, - bg_scroll_x => bg_scroll_x, - bg_scroll_y => bg_scroll_y, - disable_hscroll=>disable_hscroll, - - spr_address => spr_address, - spr_high_bit => spr_high_bit, - spr_shift => spr_shift, - spr_tall => spr_tall); - - - vdp_vram_inst : entity work.dpram - generic map - ( - init_file => "vram.hex", - widthad_a => 14 - ) - port map - ( - clock_a => cpu_clk, - address_a => xram_cpu_A(13 downto 0), - wren_a => vram_cpu_WE, - data_a => D_in, - q_a => vram_cpu_D_out, - - clock_b => not vdp_clk, - address_b => vram_vdp_A, - wren_b => '0', - data_b => (others => '0'), - q_b => vram_vdp_D - ); - - vdp_cram_inst: vdp_cram - port map ( - cpu_clk => cpu_clk, - cpu_WE => cram_cpu_WE, - cpu_A => xram_cpu_A(4 downto 0), - cpu_D => D_in(5 downto 0), - vdp_clk => vdp_clk, - vdp_A => cram_vdp_A, - vdp_D => cram_vdp_D); - - - data_write <= not WR_n and not A(0); - cram_cpu_WE <= data_write when to_cram else '0'; - vram_cpu_WE <= data_write when not to_cram else '0'; - - process (cpu_clk) - begin - if rising_edge(cpu_clk) then - if WR_n='0' then - if A(0)='0' then - xram_cpu_A_incr <= '1'; - - else - if address_ff='0' then - xram_cpu_A(7 downto 0) <= D_in; - else - xram_cpu_A(13 downto 8) <= D_in(5 downto 0); - to_cram <= D_in(7 downto 6)="11"; - case D_in is - when "10000000" => - disable_hscroll<= xram_cpu_A(6); - mask_column0 <= xram_cpu_A(5); - irq_line_en <= xram_cpu_A(4); - spr_shift <= xram_cpu_A(3); - when "10000001" => - display_on <= xram_cpu_A(6); - irq_frame_en <= xram_cpu_A(5); - spr_tall <= xram_cpu_A(1); - when "10000010" => - bg_address <= xram_cpu_A(3 downto 1); - when "10000101" => - spr_address <= xram_cpu_A(6 downto 1); - when "10000110" => - spr_high_bit <= xram_cpu_A(2); - when "10000111" => - overscan <= xram_cpu_A(3 downto 0); - when "10001000" => - bg_scroll_x <= unsigned(xram_cpu_A(7 downto 0)); - when "10001001" => - bg_scroll_y <= unsigned(xram_cpu_A(7 downto 0)); - when "10001010" => - irq_line_count <= unsigned(xram_cpu_A(7 downto 0)); - when others => - end case; - end if; - address_ff <= not address_ff; - end if; - - elsif RD_n='0' then - case A(7 downto 6)&A(0) is - when "010" => - D_out <= std_logic_vector(y); - when "011" => - D_out <= std_logic_vector(x(7 downto 0)); - when "100" => - D_out <= vram_cpu_D_out; - xram_cpu_A_incr <= '1'; - when "101" => - D_out(7) <= virq_flag; - D_out(6 downto 0) <= (others=>'0'); - reset_virq_flag <= true; - when others => - end case; - - elsif xram_cpu_A_incr='1' then - xram_cpu_A <= std_logic_vector(unsigned(xram_cpu_A) + 1); - xram_cpu_A_incr <= '0'; - - else - reset_virq_flag <= false; - end if; - end if; - end process; - - - process (vdp_clk) - begin - if rising_edge(vdp_clk) then - if vblank='1' then - vbl_irq <= irq_frame_en; - else - vbl_irq <= '0'; - end if; - end if; - end process; - - process (vdp_clk) - begin - if rising_edge(vdp_clk) then - if x=256 and not (last_y0=std_logic(y(0))) then - last_y0 <= std_logic(y(0)); - if y<192 then - if hbl_counter=0 then - hbl_irq <= irq_line_en; - hbl_counter <= irq_line_count; - else - hbl_counter <= hbl_counter-1; - end if; - else - hbl_counter <= irq_line_count; - end if; - else - hbl_irq <= '0'; - end if; - end if; - end process; - - process (vdp_clk) - begin - if rising_edge(vdp_clk) then - if vbl_irq='1' then - virq_flag <= '1'; - elsif reset_virq_flag then - virq_flag <= '0'; - end if; - end if; - end process; - - process (vdp_clk) - begin - if rising_edge(vdp_clk) then - if vbl_irq='1' or hbl_irq='1' then - irq_counter <= (others=>'1'); - elsif irq_counter>0 then - irq_counter <= irq_counter-1; - end if; - end if; - end process; - IRQ_n <= '0' when irq_counter>0 else '1'; - -end Behavioral; diff --git a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_background.vhd b/Console_MiST/Sega - SG1000/rtl/vdp/vdp_background.vhd deleted file mode 100644 index 6049b89f..00000000 --- a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_background.vhd +++ /dev/null @@ -1,136 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use IEEE.NUMERIC_STD.ALL; - -entity vdp_background is -port ( - clk: in std_logic; - reset: in std_logic; - table_address: in std_logic_vector(13 downto 11); - scroll_x: in unsigned(7 downto 0); - disable_hscroll: in std_logic; - y: in unsigned(7 downto 0); - - vram_A: out std_logic_vector(13 downto 0); - vram_D: in std_logic_vector(7 downto 0); - - color: out std_logic_vector(4 downto 0); - priority: out std_logic -); -end entity; - -architecture rtl of vdp_background is - - signal tile_index : std_logic_vector (8 downto 0); - signal x : unsigned (7 downto 0); - signal tile_y : std_logic_vector (2 downto 0); - signal palette : std_logic; - signal priority_latch: std_logic; - signal flip_x : std_logic; - - signal data0 : std_logic_vector(7 downto 0); - signal data1 : std_logic_vector(7 downto 0); - signal data2 : std_logic_vector(7 downto 0); - signal data3 : std_logic_vector(7 downto 0); - - signal shift0 : std_logic_vector(7 downto 0); - signal shift1 : std_logic_vector(7 downto 0); - signal shift2 : std_logic_vector(7 downto 0); - signal shift3 : std_logic_vector(7 downto 0); - -begin - - process (clk) begin - if (rising_edge(clk)) then - if (reset='1') then - if disable_hscroll='0' or y>=16 then - x <= 240-scroll_x; - else - x <= "11110000"; -- 240 - end if; - else - x <= x + 1; - end if; - end if; - end process; - - process (clk) - variable char_address : std_logic_vector(12 downto 0); - variable data_address : std_logic_vector(11 downto 0); - begin - if (rising_edge(clk)) then - char_address(12 downto 10) := table_address; - char_address(9 downto 5) := std_logic_vector(y(7 downto 3)); - char_address(4 downto 0) := std_logic_vector(x(7 downto 3) + 1); - data_address := tile_index & tile_y; - - case x(2 downto 0) is - when "000" => vram_A <= char_address & "0"; - when "001" => vram_A <= char_address & "1"; - when "011" => vram_A <= data_address & "00"; - when "100" => vram_A <= data_address & "01"; - when "101" => vram_A <= data_address & "10"; - when "110" => vram_A <= data_address & "11"; - when others => - end case; - end if; - end process; - - process (clk) begin - if (rising_edge(clk)) then - case x(2 downto 0) is - when "001" => - tile_index(7 downto 0) <= vram_D; - when "010" => - tile_index(8) <= vram_D(0); - flip_x <= vram_D(1); - tile_y(0) <= y(0) xor vram_D(2); - tile_y(1) <= y(1) xor vram_D(2); - tile_y(2) <= y(2) xor vram_D(2); - palette <= vram_D(3); - priority_latch <= vram_D(4); - when "100" => - data0 <= vram_D; - when "101" => - data1 <= vram_D; - when "110" => - data2 <= vram_D; --- when "111" => --- data3 <= vram_D; - when others => - end case; - end if; - end process; - - process (clk) begin - if (rising_edge(clk)) then - case x(2 downto 0) is - when "111" => - if flip_x='0' then - shift0 <= data0; - shift1 <= data1; - shift2 <= data2; - shift3 <= vram_D; - else - shift0 <= data0(0)&data0(1)&data0(2)&data0(3)&data0(4)&data0(5)&data0(6)&data0(7); - shift1 <= data1(0)&data1(1)&data1(2)&data1(3)&data1(4)&data1(5)&data1(6)&data1(7); - shift2 <= data2(0)&data2(1)&data2(2)&data2(3)&data2(4)&data2(5)&data2(6)&data2(7); - shift3 <= vram_D(0)&vram_D(1)&vram_D(2)&vram_D(3)&vram_D(4)&vram_D(5)&vram_D(6)&vram_D(7); - end if; - color(4) <= palette; - priority <= priority_latch; - when others => - shift0(7 downto 1) <= shift0(6 downto 0); - shift1(7 downto 1) <= shift1(6 downto 0); - shift2(7 downto 1) <= shift2(6 downto 0); - shift3(7 downto 1) <= shift3(6 downto 0); - end case; - end if; - end process; - - color(0) <= shift0(7); - color(1) <= shift1(7); - color(2) <= shift2(7); - color(3) <= shift3(7); -end architecture; - diff --git a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_cram.vhd b/Console_MiST/Sega - SG1000/rtl/vdp/vdp_cram.vhd deleted file mode 100644 index 781a1e35..00000000 --- a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_cram.vhd +++ /dev/null @@ -1,44 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity vdp_cram is - port ( - cpu_clk: in STD_LOGIC; - cpu_WE: in STD_LOGIC; - cpu_A: in STD_LOGIC_VECTOR (4 downto 0); - cpu_D: in STD_LOGIC_VECTOR (5 downto 0); - vdp_clk: in STD_LOGIC; - vdp_A: in STD_LOGIC_VECTOR (4 downto 0); - vdp_D: out STD_LOGIC_VECTOR (5 downto 0)); -end vdp_cram; - -architecture Behavioral of vdp_cram is - - type t_ram is array (0 to 31) of std_logic_vector(5 downto 0); - signal ram : t_ram := (others => "111111"); - -begin - - process (cpu_clk) - variable i : integer range 0 to 31; - begin - if rising_edge(cpu_clk) then - if cpu_WE='1'then - i := to_integer(unsigned(cpu_A)); - ram(i) <= cpu_D; - end if; - end if; - end process; - - process (vdp_clk) - variable i : integer range 0 to 31; - begin - if rising_edge(vdp_clk) then - i := to_integer(unsigned(vdp_A)); - vdp_D <= ram(i); - end if; - end process; - -end Behavioral; - diff --git a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_main.vhd b/Console_MiST/Sega - SG1000/rtl/vdp/vdp_main.vhd deleted file mode 100644 index c89bfe2c..00000000 --- a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_main.vhd +++ /dev/null @@ -1,135 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity vdp_main is - port ( - clk: in std_logic; - vram_A: out std_logic_vector(13 downto 0); - vram_D: in std_logic_vector(7 downto 0); - cram_A: out std_logic_vector(4 downto 0); - cram_D: in std_logic_vector(5 downto 0); - - x: unsigned(8 downto 0); - y: unsigned(7 downto 0); - - color: out std_logic_vector (5 downto 0); - - display_on: in std_logic; - mask_column0: in std_logic; - overscan: in std_logic_vector (3 downto 0); - - bg_address: in std_logic_vector (2 downto 0); - bg_scroll_x: in unsigned(7 downto 0); - bg_scroll_y: in unsigned(7 downto 0); - disable_hscroll: in std_logic; - - spr_address: in std_logic_vector (5 downto 0); - spr_high_bit: in std_logic; - spr_shift: in std_logic; - spr_tall: in std_logic); -end vdp_main; - -architecture Behavioral of vdp_main is - - component vdp_background is - port ( - clk: in std_logic; - reset: in std_logic; - table_address: in std_logic_vector(13 downto 11); - scroll_x: in unsigned(7 downto 0); - disable_hscroll: in std_logic; - y: in unsigned(7 downto 0); - vram_A: out std_logic_vector(13 downto 0); - vram_D: in std_logic_vector(7 downto 0); - color: out std_logic_vector(4 downto 0); - priority: out std_logic); - end component; - - component vdp_sprites is - port ( - clk: in std_logic; - table_address: in std_logic_vector(13 downto 8); - char_high_bit: in std_logic; - tall: in std_logic; - x: in unsigned(8 downto 0); - y: in unsigned(7 downto 0); - vram_A: out std_logic_vector(13 downto 0); - vram_D: in std_logic_vector(7 downto 0); - color: out std_logic_vector(3 downto 0)); - end component; - - signal bg_y: unsigned(7 downto 0); - signal bg_vram_A: std_logic_vector(13 downto 0); - signal bg_color: std_logic_vector(4 downto 0); - signal bg_priority: std_logic; - - signal spr_vram_A: std_logic_vector(13 downto 0); - signal spr_color: std_logic_vector(3 downto 0); - - signal line_reset: std_logic; - -begin - - process (y,bg_scroll_y) - variable sum: unsigned(8 downto 0); - begin - sum := ('0'&y)+('0'&bg_scroll_y); - if (sum>=224) then - sum := sum-224; - end if; - bg_y <= sum(7 downto 0); - end process; - - line_reset <= '1' when x=512-16 else '0'; - - vdp_bg_inst: vdp_background - port map ( - clk => clk, - table_address => bg_address, - reset => line_reset, - disable_hscroll=> disable_hscroll, - scroll_x => bg_scroll_x, - y => bg_y, - - vram_A => bg_vram_A, - vram_D => vram_D, - color => bg_color, - priority => bg_priority); - - vdp_spr_inst: vdp_sprites - port map ( - clk => clk, - table_address => spr_address, - char_high_bit => spr_high_bit, - tall => spr_tall, - x => x, - y => y, - - vram_A => spr_vram_A, - vram_D => vram_D, - color => spr_color); - - process (x, y, bg_priority, spr_color, bg_color, overscan) - variable spr_active : boolean; - variable bg_active : boolean; - begin - if x<256 and y<192 and (mask_column0='0' or x>=8) then - spr_active := not (spr_color="0000"); - bg_active := not (bg_color(3 downto 0)="0000"); - if (bg_priority='0' and spr_active) or (bg_priority='1' and not bg_active) then - cram_A <= "1"&spr_color; - else - cram_A <= bg_color; - end if; - else - cram_A <= "1"&overscan; - end if; - end process; - - vram_A <= spr_vram_A when x>=256 and x<384 else bg_vram_A; - - color <= cram_D; - -end Behavioral; - diff --git a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_sprite_shifter.vhd b/Console_MiST/Sega - SG1000/rtl/vdp/vdp_sprite_shifter.vhd deleted file mode 100644 index 8c8d4e9c..00000000 --- a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_sprite_shifter.vhd +++ /dev/null @@ -1,48 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity vpd_sprite_shifter is - Port( clk : in std_logic; - x : in unsigned (7 downto 0); - spr_x : in unsigned (7 downto 0); - spr_d0: in std_logic_vector (7 downto 0); - spr_d1: in std_logic_vector (7 downto 0); - spr_d2: in std_logic_vector (7 downto 0); - spr_d3: in std_logic_vector (7 downto 0); - color : out std_logic_vector (3 downto 0); - active: out std_logic); -end vpd_sprite_shifter; - -architecture Behavioral of vpd_sprite_shifter is - - signal count : integer range 0 to 8; - signal shift0 : std_logic_vector (7 downto 0) := (others=>'0'); - signal shift1 : std_logic_vector (7 downto 0) := (others=>'0'); - signal shift2 : std_logic_vector (7 downto 0) := (others=>'0'); - signal shift3 : std_logic_vector (7 downto 0) := (others=>'0'); - -begin - - process (clk) - begin - if rising_edge(clk) then - if spr_x=x then - shift0 <= spr_d0; - shift1 <= spr_d1; - shift2 <= spr_d2; - shift3 <= spr_d3; - else - shift0 <= shift0(6 downto 0)&"0"; - shift1 <= shift1(6 downto 0)&"0"; - shift2 <= shift2(6 downto 0)&"0"; - shift3 <= shift3(6 downto 0)&"0"; - end if; - end if; - end process; - - color <= shift3(7)&shift2(7)&shift1(7)&shift0(7); - active <= shift3(7) or shift2(7) or shift1(7) or shift0(7); - -end Behavioral; - diff --git a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_sprites.vhd b/Console_MiST/Sega - SG1000/rtl/vdp/vdp_sprites.vhd deleted file mode 100644 index 18dbdd95..00000000 --- a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_sprites.vhd +++ /dev/null @@ -1,188 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity vdp_sprites is - port (clk : in std_logic; - table_address : in STD_LOGIC_VECTOR (13 downto 8); - char_high_bit : in std_logic; - tall : in std_logic; - vram_A : out STD_LOGIC_VECTOR (13 downto 0); - vram_D : in STD_LOGIC_VECTOR (7 downto 0); - x : in unsigned (8 downto 0); - y : in unsigned (7 downto 0); - color : out STD_LOGIC_VECTOR (3 downto 0)); -end vdp_sprites; - -architecture Behavioral of vdp_sprites is - - component vpd_sprite_shifter is - port( clk : in std_logic; - x : in unsigned (7 downto 0); - spr_x : in unsigned (7 downto 0); - spr_d0: in std_logic_vector (7 downto 0); - spr_d1: in std_logic_vector (7 downto 0); - spr_d2: in std_logic_vector (7 downto 0); - spr_d3: in std_logic_vector (7 downto 0); - color : out std_logic_vector (3 downto 0); - active: out std_logic); - end component; - - constant WAITING: integer := 0; - constant COMPARE: integer := 1; - constant LOAD_N: integer := 2; - constant LOAD_X: integer := 3; - constant LOAD_0: integer := 4; - constant LOAD_1: integer := 5; - constant LOAD_2: integer := 6; - constant LOAD_3: integer := 7; - - signal state: integer := WAITING; - signal count: integer range 0 to 7; - signal index: unsigned(5 downto 0); - signal data_address: std_logic_vector(13 downto 2); - - type tenable is array (0 to 7) of boolean; - type tx is array (0 to 7) of unsigned(7 downto 0); - type tdata is array (0 to 7) of std_logic_vector(7 downto 0); - signal enable: tenable; - signal spr_x: tx; - signal spr_d0: tdata; - signal spr_d1: tdata; - signal spr_d2: tdata; - signal spr_d3: tdata; - - type tcolor is array (0 to 7) of std_logic_vector(3 downto 0); - signal spr_color: tcolor; - signal active: std_logic_vector(7 downto 0); - -begin - shifters: - for i in 0 to 7 generate - begin - shifter: vpd_sprite_shifter - port map(clk => clk, - x => x(7 downto 0), - spr_x => spr_x(i), - spr_d0=> spr_d0(i), - spr_d1=> spr_d1(i), - spr_d2=> spr_d2(i), - spr_d3=> spr_d3(i), - color => spr_color(i), - active=> active(i)); - end generate; - - with state select - vram_a <= table_address&"00"&std_logic_vector(index) when COMPARE, - table_address&"1"&std_logic_vector(index)&"1" when LOAD_N, - table_address&"1"&std_logic_vector(index)&"0" when LOAD_X, - data_address&"00" when LOAD_0, - data_address&"01" when LOAD_1, - data_address&"10" when LOAD_2, - data_address&"11" when LOAD_3, - (others=>'0') when others; - - process (clk) - variable y9 : unsigned(8 downto 0); - variable d9 : unsigned(8 downto 0); - variable delta : unsigned(8 downto 0); - begin - if rising_edge(clk) then - - if x=255 then - count <= 0; - enable <= (others=>false); - state <= COMPARE; - index <= (others=>'0'); - - else - y9 := "0"&y; - d9 := "0"&unsigned(vram_D); - if d9>=240 then - d9 := d9-256; - end if; - delta := y9-d9; - - case state is - when COMPARE => - if d9=208 then - state <= WAITING; -- stop - elsif 0<=delta and ((delta<8 and tall='0') or (delta<16 and tall='1')) then - enable(count) <= true; - data_address(5 downto 2) <= std_logic_vector(delta(3 downto 0)); - state <= LOAD_N; - else - if index<63 then - index <= index+1; - else - state <= WAITING; - end if; - end if; - - when LOAD_N => - data_address(13) <= char_high_bit; - data_address(12 downto 6) <= vram_d(7 downto 1); - if tall='0' then - data_address(5) <= vram_d(0); - end if; - state <= LOAD_X; - - when LOAD_X => - spr_x(count) <= unsigned(vram_d); - state <= LOAD_0; - - when LOAD_0 => - spr_d0(count) <= vram_d; - state <= LOAD_1; - - when LOAD_1 => - spr_d1(count) <= vram_d; - state <= LOAD_2; - - when LOAD_2 => - spr_d2(count) <= vram_d; - state <= LOAD_3; - - when LOAD_3 => - spr_d3(count) <= vram_d; - if (count<7) then - state <= COMPARE; - index <= index+1; - count <= count+1; - else - state <= WAITING; - end if; - - when others => - end case; - end if; - end if; - end process; - - process (clk) - begin - if rising_edge(clk) then - if enable(0) and active(0)='1' then - color <= spr_color(0); - elsif enable(1) and active(1)='1' then - color <= spr_color(1); - elsif enable(2) and active(2)='1' then - color <= spr_color(2); - elsif enable(3) and active(3)='1' then - color <= spr_color(3); - elsif enable(4) and active(4)='1' then - color <= spr_color(4); - elsif enable(5) and active(5)='1' then - color <= spr_color(5); - elsif enable(6) and active(6)='1' then - color <= spr_color(6); - elsif enable(7) and active(7)='1' then - color <= spr_color(7); - else - color <= (others=>'0'); - end if; - end if; - end process; - -end Behavioral; - diff --git a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_vram.vhd b/Console_MiST/Sega - SG1000/rtl/vdp/vdp_vram.vhd deleted file mode 100644 index 10bfd18a..00000000 --- a/Console_MiST/Sega - SG1000/rtl/vdp/vdp_vram.vhd +++ /dev/null @@ -1,44 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity vdp_vram is - port ( - cpu_clk: in STD_LOGIC; - cpu_WE: in STD_LOGIC; - cpu_A: in STD_LOGIC_VECTOR (13 downto 0); - cpu_D_in: in STD_LOGIC_VECTOR (7 downto 0); - cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0); - vdp_clk: in STD_LOGIC; - vdp_A: in STD_LOGIC_VECTOR (13 downto 0); - vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0)); -end vdp_vram; - -architecture Behavioral of vdp_vram is -begin - ram_blocks: - for b in 0 to 7 generate - begin - inst: RAMB16_S1_S1 - port map ( - CLKA => cpu_clk, - ADDRA => cpu_A, - DIA => cpu_D_in(b downto b), - DOA => cpu_D_out(b downto b), - ENA => '1', - SSRA => '0', - WEA => cpu_WE, - - CLKB => not vdp_clk, - ADDRB => vdp_A, - DIB => "0", - DOB => vdp_D_out(b downto b), - ENB => '1', - SSRB => '0', - WEB => '0' - ); - end generate; - -end Behavioral; diff --git a/Console_MiST/Sega - SG1000/rtl/vdp/vram.hex b/Console_MiST/Sega - SG1000/rtl/vdp/vram.hex deleted file mode 100644 index f2bf746c..00000000 --- a/Console_MiST/Sega - SG1000/rtl/vdp/vram.hex +++ /dev/null @@ -1,98 +0,0 @@ -:020000040000FA -:2084000000000000000000000000000000000000000000000000000000000000000000005C -:208420001818181818181818181818181818181818181818000000001818181800000000FC -:208440006C6C6C6C6C6C6C6C000000000000000000000000000000000000000000000000BC -:208460006C6C6C6C6C6C6C6CFEFEFEFE6C6C6C6CFEFEFEFE6C6C6C6C6C6C6C6C000000009C -:20848000181818183E3E3E3E606060603C3C3C3C060606067C7C7C7C1818181800000000AC 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-:00000001FF diff --git a/Console_MiST/Sega - SG1000/rtl/vga_video.vhd b/Console_MiST/Sega - SG1000/rtl/vga_video.vhd deleted file mode 100644 index 04e82973..00000000 --- a/Console_MiST/Sega - SG1000/rtl/vga_video.vhd +++ /dev/null @@ -1,93 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:59:35 01/22/2012 --- Design Name: --- Module Name: vdp_vga_timing - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity vga_video is - port ( - clk16: in std_logic; - x: out unsigned(8 downto 0); - y: out unsigned(7 downto 0); - vblank: out std_logic; - hblank: out std_logic; - color: in std_logic_vector(5 downto 0); - hsync: out std_logic; - vsync: out std_logic; - red: out std_logic_vector(1 downto 0); - green: out std_logic_vector(1 downto 0); - blue: out std_logic_vector(1 downto 0)); -end vga_video; - -architecture Behavioral of vga_video is - - signal hcount: unsigned (8 downto 0) := (others=>'0'); - signal vcount: unsigned (9 downto 0) := (others=>'0'); - signal visible: boolean; - - signal y9: unsigned (8 downto 0); - -begin - - process (clk16) - begin - if rising_edge(clk16) then - if hcount=507 then - hcount <= (others => '0'); - if vcount=523 then - vcount <= (others=>'0'); - else - vcount <= vcount + 1; - end if; - else - hcount <= hcount + 1; - end if; - end if; - end process; - - x <= hcount-(91+75); - y9 <= vcount(9 downto 1)-(13+27); - y <= y9(7 downto 0); - hblank <= '1' when hcount=0 and vcount(0 downto 0)=0 else '0'; - vblank <= '1' when hcount=0 and vcount=0 else '0'; - - hsync <= '0' when hcount<61 else '1'; - vsync <= '0' when vcount<2 else '1'; - - visible <= vcount>=35 and vcount<35+480 and hcount>=91 and hcount<91+406; - - process (clk16) - variable pixel_n: std_logic_vector(1 downto 0); - begin - if rising_edge(clk16) then - if visible then - red <= color(1 downto 0); - green <= color(3 downto 2); - blue <= color(5 downto 4); - else - red <= (others=>'0'); - green <= (others=>'0'); - blue <= (others=>'0'); - end if; - end if; - end process; - -end Behavioral; - diff --git a/Console_MiST/Sega - SG1000/rtl/video_mixer.sv b/Console_MiST/Sega - SG1000/rtl/video_mixer.sv deleted file mode 100644 index 04cfd4ba..00000000 --- a/Console_MiST/Sega - SG1000/rtl/video_mixer.sv +++ /dev/null @@ -1,242 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/Console_MiST/Sega - SG1000/rtl/yuv_table.vhd b/Console_MiST/Sega - SG1000/rtl/yuv_table.vhd deleted file mode 100644 index 4279b9ac..00000000 --- a/Console_MiST/Sega - SG1000/rtl/yuv_table.vhd +++ /dev/null @@ -1,229 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity yuv_table is - Port (color : in std_logic_vector (5 downto 0); - y : out std_logic_vector (5 downto 0); - u : out std_logic_vector (5 downto 0); - v : out std_logic_vector (5 downto 0)); -end yuv_table; - -architecture Behavioral of yuv_table is -begin - - process (color) - begin - case color is - when "000000" => y <= "000000"; - when "000001" => y <= "000011"; - when "000010" => y <= "000110"; - when "000011" => y <= "001001"; - when "000100" => y <= "000110"; - when "000101" => y <= "001001"; - when "000110" => y <= "001100"; - when "000111" => y <= "001111"; - when "001000" => y <= "001100"; - when "001001" => y <= "001111"; - when "001010" => y <= "010010"; - when "001011" => y <= "010101"; - when "001100" => y <= "010010"; - when "001101" => y <= "010101"; - when "001110" => y <= "011000"; - when "001111" => y <= "011011"; - when "010000" => y <= "000001"; - when "010001" => y <= "000100"; - when "010010" => y <= "000111"; - when "010011" => y <= "001010"; - when "010100" => y <= "000111"; - when "010101" => y <= "001010"; - when "010110" => y <= "001101"; - when "010111" => y <= "010000"; - when "011000" => y <= "001101"; - when "011001" => y <= "010000"; - when "011010" => y <= "010011"; - when "011011" => y <= "010110"; - when "011100" => y <= "010011"; - when "011101" => y <= "010110"; - when "011110" => y <= "011001"; - when "011111" => y <= "011100"; - when "100000" => y <= "000010"; - when "100001" => y <= "000101"; - when "100010" => y <= "001000"; - when "100011" => y <= "001011"; - when "100100" => y <= "001000"; - when "100101" => y <= "001011"; - when "100110" => y <= "001110"; - when "100111" => y <= "010001"; - when "101000" => y <= "001110"; - when "101001" => y <= "010001"; - when "101010" => y <= "010100"; - when "101011" => y <= "010111"; - when "101100" => y <= "010100"; - when "101101" => y <= "010111"; - when "101110" => y <= "011010"; - when "101111" => y <= "011101"; - when "110000" => y <= "000011"; - when "110001" => y <= "000110"; - when "110010" => y <= "001001"; - when "110011" => y <= "001100"; - when "110100" => y <= "001001"; - when "110101" => y <= "001100"; - when "110110" => y <= "001111"; - when "110111" => y <= "010010"; - when "111000" => y <= "001111"; - when "111001" => y <= "010010"; - when "111010" => y <= "010101"; - when "111011" => y <= "011000"; - when "111100" => y <= "010101"; - when "111101" => y <= "011000"; - when "111110" => y <= "011011"; - when "111111" => y <= "011110"; - when others => - end case; - end process; - - process (color) - begin - case color is - when "000000" => u <= "000000"; - when "000001" => u <= "111111"; - when "000010" => u <= "111101"; - when "000011" => u <= "111100"; - when "000100" => u <= "111101"; - when "000101" => u <= "111100"; - when "000110" => u <= "111010"; - when "000111" => u <= "111001"; - when "001000" => u <= "111010"; - when "001001" => u <= "111001"; - when "001010" => u <= "110111"; - when "001011" => u <= "110110"; - when "001100" => u <= "110111"; - when "001101" => u <= "110110"; - when "001110" => u <= "110100"; - when "001111" => u <= "110011"; - when "010000" => u <= "000100"; - when "010001" => u <= "000011"; - when "010010" => u <= "000001"; - when "010011" => u <= "000000"; - when "010100" => u <= "000001"; - when "010101" => u <= "000000"; - when "010110" => u <= "111111"; - when "010111" => u <= "111101"; - when "011000" => u <= "111111"; - when "011001" => u <= "111101"; - when "011010" => u <= "111100"; - when "011011" => u <= "111010"; - when "011100" => u <= "111100"; - when "011101" => u <= "111010"; - when "011110" => u <= "111001"; - when "011111" => u <= "110111"; - when "100000" => u <= "001001"; - when "100001" => u <= "000111"; - when "100010" => u <= "000110"; - when "100011" => u <= "000100"; - when "100100" => u <= "000110"; - when "100101" => u <= "000100"; - when "100110" => u <= "000011"; - when "100111" => u <= "000001"; - when "101000" => u <= "000011"; - when "101001" => u <= "000001"; - when "101010" => u <= "000000"; - when "101011" => u <= "111111"; - when "101100" => u <= "000000"; - when "101101" => u <= "111111"; - when "101110" => u <= "111101"; - when "101111" => u <= "111100"; - when "110000" => u <= "001101"; - when "110001" => u <= "001100"; - when "110010" => u <= "001010"; - when "110011" => u <= "001001"; - when "110100" => u <= "001010"; - when "110101" => u <= "001001"; - when "110110" => u <= "000111"; - when "110111" => u <= "000110"; - when "111000" => u <= "000111"; - when "111001" => u <= "000110"; - when "111010" => u <= "000100"; - when "111011" => u <= "000011"; - when "111100" => u <= "000100"; - when "111101" => u <= "000011"; - when "111110" => u <= "000001"; - when "111111" => u <= "000000"; - when others => - end case; - end process; - - process (color) - begin - case color is - when "000000" => v <= "000000"; - when "000001" => v <= "000110"; - when "000010" => v <= "001100"; - when "000011" => v <= "010010"; - when "000100" => v <= "111011"; - when "000101" => v <= "000001"; - when "000110" => v <= "000111"; - when "000111" => v <= "001101"; - when "001000" => v <= "110110"; - when "001001" => v <= "111100"; - when "001010" => v <= "000010"; - when "001011" => v <= "001000"; - when "001100" => v <= "110001"; - when "001101" => v <= "110111"; - when "001110" => v <= "111101"; - when "001111" => v <= "000011"; - when "010000" => v <= "111111"; - when "010001" => v <= "000101"; - when "010010" => v <= "001011"; - when "010011" => v <= "010001"; - when "010100" => v <= "111010"; - when "010101" => v <= "000000"; - when "010110" => v <= "000110"; - when "010111" => v <= "001100"; - when "011000" => v <= "110101"; - when "011001" => v <= "111011"; - when "011010" => v <= "000001"; - when "011011" => v <= "000111"; - when "011100" => v <= "110000"; - when "011101" => v <= "110110"; - when "011110" => v <= "111100"; - when "011111" => v <= "000010"; - when "100000" => v <= "111110"; - when "100001" => v <= "000100"; - when "100010" => v <= "001010"; - when "100011" => v <= "010000"; - when "100100" => v <= "111001"; - when "100101" => v <= "111111"; - when "100110" => v <= "000101"; - when "100111" => v <= "001011"; - when "101000" => v <= "110100"; - when "101001" => v <= "111010"; - when "101010" => v <= "000000"; - when "101011" => v <= "000110"; - when "101100" => v <= "101111"; - when "101101" => v <= "110101"; - when "101110" => v <= "111011"; - when "101111" => v <= "000001"; - when "110000" => v <= "111101"; - when "110001" => v <= "000011"; - when "110010" => v <= "001001"; - when "110011" => v <= "001111"; - when "110100" => v <= "111000"; - when "110101" => v <= "111110"; - when "110110" => v <= "000100"; - when "110111" => v <= "001010"; - when "111000" => v <= "110011"; - when "111001" => v <= "111001"; - when "111010" => v <= "111111"; - when "111011" => v <= "000101"; - when "111100" => v <= "101110"; - when "111101" => v <= "110100"; - when "111110" => v <= "111010"; - when "111111" => v <= "000000"; - when others => - end case; - end process; - - -end Behavioral; - diff --git a/Console_MiST/Sega - SG1000/sg1000.srf b/Console_MiST/Sega - SG1000/sg1000.srf deleted file mode 100644 index 2ac32dec..00000000 --- a/Console_MiST/Sega - SG1000/sg1000.srf +++ /dev/null @@ -1,8 +0,0 @@ -{ "" "" "" "Verilog HDL macro warning at hq2x.sv(26): overriding existing definition for macro \"BITS_TO_FIT\", which was defined in \"rtl/scandoubler.v\", line 109" { } { } 0 10274 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Output port \"Cart_In\" at sg1000_top.sv(8) has no driver" { } { } 0 10034 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL information at scandoubler.v(102): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Net \"Cart_ram_Out\" at sg1000_top.sv(25) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "VHDL Process Statement warning at vdp_main.vhd(117): signal \"mask_column0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 14284 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""}