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Druaga: register video output, adjust hblank

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This commit is contained in:
Gyorgy Szombathelyi
2022-12-12 11:49:24 +01:00
parent 50b8be555e
commit 2505ca737e
2 changed files with 3 additions and 3 deletions
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4
Arcade_MiST/Namco Super Pacman Hardware/rtl/druaga_video.v
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@@ -17,7 +17,7 @@ module DRUAGA_VIDEO
input [8:0] PV,
output PCLK,
output PCLK_EN,
output [7:0] POUT, // pixel colour output
output reg [7:0]POUT, // pixel colour output
output VB,
output [10:0] VRAM_A,
@@ -134,9 +134,9 @@ DRUAGA_SPRITE spr
//----------------------------------------
always @(posedge VCLKx8) if (VCLK_EN) begin
PALT_A <= BGHI ? BGCOL : ((SPCOL[3:0]==4'd15) ? BGCOL : SPCOL );
POUT <= PALT_D;
end
assign POUT = oHB ? 8'd0 : PALT_D;
assign PCLK = VCLK;
assign PCLK_EN = VCLK_EN;

2
Arcade_MiST/Namco Super Pacman Hardware/rtl/hvgen.v
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@@ -25,7 +25,7 @@ assign VPOS = vcnt;
always @(posedge MCLK) begin
if (PCLK_EN)
case (hcnt)
1: begin HBLK <= 0; hcnt <= hcnt+1'd1; end
2: begin HBLK <= 0; hcnt <= hcnt+1'd1; end
290: begin HBLK <= 1; hcnt <= hcnt+1'd1; end
311: begin HSYN <= 0; hcnt <= hcnt+1'd1; end
342: begin HSYN <= 1; hcnt <= 9'd470; end