From 2620dc9fc684424a7c9ef930a8f67b0611d63ae4 Mon Sep 17 00:00:00 2001 From: Gehstock Date: Wed, 1 Jan 2020 18:39:12 +0100 Subject: [PATCH] CleanUp --- .../TropicalAngel_MiST/ReadMe.txt | 10 +- .../TropicalAngel_MiST/Release/TROPANG.ROM | Bin 115488 -> 90112 bytes .../TropicalAngel_MiST/TropicalAngel_MiST.qpf | 29 +- .../TropicalAngel_MiST/TropicalAngel_MiST.qsf | 63 +-- .../TropicalAngel_MiST/TropicalAngel_MiST.sdc | 12 +- .../rtl/Rom/tropical_chr_bit1.vhd | 534 ++++++++++++++++++ .../rtl/Rom/tropical_chr_bit2.vhd | 534 ++++++++++++++++++ .../rtl/Rom/tropical_chr_bit3.vhd | 534 ++++++++++++++++++ .../rtl/Rom/tropical_chr_palette_h.vhd | 38 ++ .../rtl/Rom/tropical_chr_palette_l.vhd | 38 ++ .../rtl/Rom/tropical_spr_bit1.vhd | 534 ++++++++++++++++++ .../rtl/Rom/tropical_spr_bit2.vhd | 534 ++++++++++++++++++ .../rtl/Rom/tropical_spr_bit3.vhd | 534 ++++++++++++++++++ .../rtl/Rom/tropical_spr_bit4.vhd | 534 ++++++++++++++++++ .../rtl/Rom/tropical_spr_bit5.vhd | 534 ++++++++++++++++++ .../rtl/Rom/tropical_spr_bit6.vhd | 534 ++++++++++++++++++ .../rtl/Rom/tropical_spr_palette.vhd | 38 ++ .../rtl/Rom/tropical_spr_rgb_lut.vhd | 24 + .../{traverse_usa.vhd => TropicalAngel.vhd} | 332 +++++------ ...verseUSA_MiST.sv => TropicalAngel_MiST.sv} | 124 ++-- .../TropicalAngel_MiST/rtl/dpram.vhd | 81 --- .../rtl/moon_patrol_sound_board.vhd | 18 +- .../TropicalAngel_MiST/rtl/pll_mist.vhd | 70 ++- .../TropicalAngel_MiST/rtl/sdram.sv | 101 ++-- 24 files changed, 5297 insertions(+), 487 deletions(-) create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_chr_bit1.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_chr_bit2.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_chr_bit3.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_chr_palette_h.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_chr_palette_l.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_spr_bit1.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_spr_bit2.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_spr_bit3.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_spr_bit4.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_spr_bit5.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_spr_bit6.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_spr_palette.vhd create mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/Rom/tropical_spr_rgb_lut.vhd rename Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/{traverse_usa.vhd => TropicalAngel.vhd} (78%) rename Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/{TraverseUSA_MiST.sv => TropicalAngel_MiST.sv} (77%) delete mode 100644 Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/dpram.vhd diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/ReadMe.txt b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/ReadMe.txt index eff56ba4..ce5b8844 100644 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/ReadMe.txt +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/ReadMe.txt @@ -1,16 +1,14 @@ -Traverse USA by Dar (darfpga@aol.fr) (16/03/2019) +Tropica Angel by Dar (darfpga@aol.fr) (16/03/2019) Port to MiST -TRAVRUSA.ROM or SHTRIDER.ROM is required at the root of the SD-Card. +TROPANG.ROM is required at the root of the SD-Card. Creating in Windows: -copy /B zr1-0.m3 + zr1-5.l3 + zr1-6a.k3 + zr1-7.j3 + mr10.1a + mr10.1a + zippyrac.001 + mr8.3c + mr9.3a + zr1-8.n3 + zr1-9.l3 + zr1-10.k3 + mmi6349.ij + tbp24s10.3 + tbp18s.2 > TRAVRUSA.ROM -copy /B sr01a.bin + sr02a.bin + sr03a.bin + sr04a.bin + sr11a.bin + sr05a.bin + sr06a.bin + sr07a.bin + sr08a.bin + sr09a.bin + sr10b.bin + 1.bpr + 2.bpr + 3.bpr + 4.bpr > SHTRIDER.ROM +copy /B zr1-0.m3 + zr1-5.l3 + zr1-6a.k3 + zr1-7.j3 TRAVERSE.ROM Creating in Linux: -cat zr1-0.m3 zr1-5.l3 zr1-6a.k3 zr1-7.j3 mr10.1a mr10.1a zippyrac.001 mr8.3c mr9.3a zr1-8.n3 zr1-9.l3 zr1-10.k3 mmi6349.ij tbp24s10.3 tbp18s.2 > TRAVRUSA.ROM -cat sr01a.bin sr02a.bin sr03a.bin sr04a.bin sr11a.bin sr05a.bin sr06a.bin sr07a.bin sr08a.bin sr09a.bin sr10b.bin 1.bpr 2.bpr 3.bpr 4.bpr > SHTRIDER.ROM +cat zr1-0.m3 zr1-5.l3 zr1-6a.k3 zr1-7.j3 > TRAVERSE.ROM Some ROM files contain different names, like: zippyrac.000 diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/Release/TROPANG.ROM b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/Release/TROPANG.ROM index 3ccdd717cf07166ce2f1b7160c0dd965880be249..7003915518087a8e598a562e9941fd42b1382226 100644 GIT binary patch delta 18 acmZ3`#@=v%b%Vr$$se|HY*k=h#_fW7Qa}VMYB9=ySI*U9&LPE7Z#fuCm}%? z7Z$VZj1aMCLlLcVD_k2SyZyxNy{S#&q$UNkBa2AHp$Ip*wbKxGWD$g8kVXj5$UE9| zzvs-Z5V^11Kkfm|ncsQ-&g1txzw`ag>PA)P^U|Skr#3NOL>L_-gc!PEq%~DdJ{wEN zD5ZHtQS-Fql$;_hrATClsZYzt$kL_JhOBw>7YdYWs)BM9B^=v%A)eU0bx={2HHAV) z-WeY)j*SgdB8cAE@mQ=xX%Xe@7iTnecMF0*>2O~muWBlFC~aMF9lE@mMzP*wRLrZXxo-$BgnEMM^MOo|7bSrI1XM}5S(l@81(rbcz5Jbh&cQxa>L0|AV6%x4g^kSNHT3WJxDM01j496GRMzl4nChn#h#om zkl~H9_E{&aW7bc|??plm{|IB0C6UBRL>O^$`3o<<{KE2NVna_)si%jaaYw@+Nj_y5 z##2dRp9F^|ZQ>Y)Z5Sm|G7P*Lq#UpYxAQ$yekqrPN@UhU7Aw4JGx9l^g2+AUq zNY7BI^zSIwbN*WC?5Q5cFhZ7f*nKS3xZ?9cs=C>TKShr`&p z^_U=}Xtu##O!k-z5ltW@5MJbzLWd6R+jnB6Jx-~8(IDhJb@~Pj@>rv7>L&4iuad5^ zx~U=7A9;EyM1qmmUZ+$f!u0$w#qMAI(Mk_1#RHQX7TEr~G2#D0mp3z|rsBlVDdbN(ctBl~pD12AU!ZIs zAz&UlQPa<%jYqGSR+)6VM2YFsitPP zckkXvII-YSqIsAuxglVr{^-)P!-c(HD%n^#cSPMI7rsUG*`)#>k<|U&4^~EN$jYHM z@6kPfGCul&v>UAJD~G6zk^b#zop|eS-QwI%sfEUQdsFDtg^7c_omPzw@Xk#uL-Kpq zOh8LYEWumt^0l*mGtb{y|D>P2EIZ6r2xHop;4vZHBaA^wRyZwyF+w8ST!vUu_Xr-k z0frdG@;gt?d+WJlUn`J3j~~^BwtiZT>JT3EQ<&dkN7J#{J_|$vR3x`Niy-Hwf2>d zO?Urc^N~F-=@@;Am1d!(Z{q9utv9;_o?~N!!x+nC`1v{`#WGpK*=uiIb2BdG-Mvpp zX(JOA#6w5ULx1sd^mBjj7E`}K=~({K=Vv2bE57!}wU|&hXUvT#wt*Xt@mBEQub zR3+hhECiy99ZjkBlJJvW65Z~+hJh^G6Yk863^`AqeEwbk8}dpFrD1;6rX zLHtoi>o4onrvh?hXh*_-?ljqL8AM-!)lWYpVHHI$6t?MQD_$+?T`gSxF=<{=G7Zyc z<*F%auY__H#H!XP9nX)F&Tv*$xA*A8Z@qKzgm5kEckGw$2uzROo$@Z&w)iIX%MB4( zsuk8(w`D%je17qs7nh0sx_o zj>m|u88L$GmV$~)|1cV3>leN|a~ctN^2je`?u^L(M;mICTYYBRgW`i~I26;XC9!p) zQT3c1TTh)tFr||d))A)iN$iA$p~gEK4MTr>cW!k2oYhdebm(_yd2d}ilKc3jkMGgc zzRj=hzB+KEN2yaA>NP1}QqS(XeBn3_BCsLogrxmY&pv-#AhEamv602w<>%RU`rvq@ zVQTc-gzO$smF*3xJU4DSc_oqlz`4A{N}sdM#A9*OKv5QS{$zrnG}LYz{m1p|=$i4Q ztd=g#659HU&eP6wrT4XKDjn_}8F;gAH23NEv&k*VQugp|mi6O-w+z%5u{HHX*?- zdTs1f%P$}*G)srJc8^f{LZ32RaxP@GaSQ8incYH*dP$m_w6=-j&E1&aUcG64VMKEV z3mv_~bfg>7*BvR@cG7Y72OP`L@z3;$Dt(H+K29f`lXf;_A9gNa8$s2ubwrRn0;v+E z;4fR1CAD{IS^C~vZxtymOh5_-M{)cL8m!3%$3ETP*(B~1M74zdN+e|~oygN+su541 zE_!qwHa-s?s0!?2yo+-3>$ao1$-Fn%tZZ8&3$dtddy{_LQDCI3+`oxuAjgdf^mRQ< z=WmrJ&p)hiD*_HlF!(icMzx>C>HY#MP2Fny}U-qBA?y&bhL+H zgo2X(b2Mdqqno$=uu@|Uw46I(>Rr&Y4-+zDpo@O!N-C~P8S?`N`<6*+CT^OByZ!>x zjI23H$vJBVuMYgUq>YYmOVZ+-tEBneZ_@EAjk>MAAXuPp<+9`Sm%}Xsl-}9VVB4py(Q{ZP-7s22IZGCW8@r04xU5%}lvW~SN5&`w zRcYyS1+`SNEoX|LGS)CVe9wro%%wo^$v6;HZFC{M(xKGL8vR$gdbBLaPNRJqone+G zJ}#eJB?{9exqgYFZe94Nm|6NyJGSFFx{V96+kq%so!!es2@)?Ve@1h3fjUf!8ZB_u z3`wj}s-EFReWJ3FKIeSV>cse2u*_vG%|3a$6!dbM?kLbPdgPOd(>pEh!K_;#99)PDN{_AfAN{VTZQZaIlux;43>El~8Y(t-)RJmr8DAfdOs-zlO@`-{J)qZD}k+zSIEIOe( zmU+lrq*sYw&e6W3b5$kkGtx758rI*5a&7nb%~KkUwu~ClrQ_+-PU2Z8jFIy{)0uE% z=J+09=AJ(qNIz=4%sC|Dd|C8qk>o8TW#8SPwa&%ld6F`!+!~eDiLq`ecvHg;8pM^QV`9gmGZmZfoS-{?q>et5C^n2a6eJXyUMa1;>`vHGl77 zra55XRTO#}Y2U8~H`C#>>XOJtI{MML-T(dsoya9y8?t#jZCMro0P8X| zMASa2z;yDn+lw%;>AWDy`CK9p)>Li6vK@t;;#!9<5C#6j3<5CXgxifI7aFAiEX3wNI~wUbe$Eqtxj|BjDfN0dJsY+Jh^D?z?dX8w?G@o z80BwjBZeF$DrN(lB?P_?p@YCI0yINV)MRaRBe+uU2bV9>Z@bFKc@&e=iTwy28%dz7 zR8v1)5^ICXlC2GNW8o(S^f>X$?b|gv3N(NYvi8utG^tW#N&PiIG^#O`0-M7Pm}XxU zo8=VoF34=&c!#QeIhS0l$m(s;YAizc{Jnpf5=_j`1>$*_-flbD(eqGvi%F9tzpAv> zsA~f6ic2s##|^_uoYSGhPU|{3zTa)XO7wZlT?NpK5z|+&F@rI)-`HnnRubKMI!l$i zNI;=argWG>4o4KsHR&9(O{W{Wl@W^#JRj$(KdYnvy(op

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zgfh^ENslp>rnUWxT=z!LE2{;~CwOj#JLw;U`R~2ORhDihg0)}8SIxs8yGr8jN9vFC zU#9u(j3JLNP!9(!ozRZFx&1QdIc?b=ocVK+7PquAK3IE`^l2x*^|c*tJN+Fj);ld5 zKnU?1`eiF*Qe#cJkWKXmdw9X>4_@MD(!K{5aXOVYc+41M9ahQ{FjirRrC0I^7-F=W zk64%)LvCuu?l0i7iX{r&#*M$&-+Mx=f0kCUVOU2YJrwIe>=*prah8oBhGktKDT%%+?d#R=WKG3<-^`>(0*r*JpZ#E_%2j+ zmB#Ih{JVkXn<(C|7HOWVij4;@!_#S(hDHJXm#(clq_1SZroin6**oqxAN7ZqH}MX1 z$lzZr^Hkry{5s>%48WE!L;i?=Q8U%M@NsN$3=G5%O4F+pw;sRKC7e^|aV`smwV!xC^NH_lf#g??mv;F@WTXILhhE|om5wzI4wN>nUD4fwZzJ(jI{cE361EY& zwY7We@Ozhd${_pFyvi&xN51`c*(;nhL7xX&o|}^Y*8X?j6vg>i1Yj)5qYSasy_GXs zXXOdG`9c1PUmgF(FS=*H#a2DSvxG9l$xPlU%zg=ySkcj3OLNvMFnp85)B`@2v8%WrhIg1tObqzFpCx8g?VLm zVsWNJ`|R-vLh`NfWwMHuql+n2Rb}=5m({SGT>}(9-zY2AO0~+7sj&_z!5P%tEZ$N+ zN+E~rOyxPW(A(17%rZEqZ;a&Ms;usx32^#0x$FtT+9#pW5P(gpntLji&pedScb{eH`2)kMqLe2B=_4Z(V4%?3+=Th9u3`09c1MBrRNe+dL+%S1 zx_A-qGlt7sWN6480J~BxdL!0p=5d#*)+&3F$9{H(Pn(VpSA5mPOR58yWbnuTVq=I-t8fQYF5RKW#Xw0q8GWkx`xF8 zQD!ueYvk%GkB{>pivbU+$|686Put7 128+256 = 384 pixels, 384/6.144Mhz => 1 line is 62.5us (16.000KHz) -- vcnt [x0E6..x0FF-x100..x1FF] => 26+256 = 282 lines, 1 frame is 260 x 62.5us = 17.625ms (56.74Hz) -process (reset, clock_36, pix_ena) +process (reset, clock_36) begin if reset='1' then hcnt <= (others=>'0'); @@ -347,13 +332,12 @@ end process; flip <= flip_int xor dip_switch_2(0); hcnt_flip <= '0'&hcnt(7 downto 0) when flip ='1' else '0' & not hcnt(7 downto 0); -vflip <= flip xor shtrider; -vcnt_flip <= vcnt when vflip ='1' else not vcnt; +vcnt_flip <= vcnt when flip ='1' else not vcnt; -------------------- -- players inputs -- -------------------- -input_0 <= "1111" & not coin1 & '1' & not start2 & not start1; +input_0 <= "1111" & not coin1 & service & not start2 & not start1; input_1 <= not brake1 & '1' & not accel1 & "111" & not left1 & not right1; input_2 <= not brake2 & '1' & not accel2 & "111" & not left2 & not right2; @@ -382,13 +366,13 @@ begin if cpu_m1_n = '0' and cpu_ioreq_n = '0' then cpu_irq_n <= '1'; else -- lauch irq and end of frame - if ((vcnt = 230 and vflip = '0') or (vcnt = 448 and vflip = '1')) and (hcnt = '0'&X"80") then + if ((vcnt = 230 and flip = '0') or (vcnt = 448 and flip = '1')) and (hcnt = '0'&X"80") then cpu_irq_n <= '0'; end if; end if; - if cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"9" then scroll_x(7 downto 0) <= cpu_do; end if; - if cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"A" then scroll_x(8) <= cpu_do(0); end if; + if cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"9" then scroll_x(7 downto 0) <= cpu_do; end if;--scrollram +-- if cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"A" then scroll_x(8) <= cpu_do(0); end if; if cpu_wr_n = '0' and cpu_addr(15 downto 0) = X"D000" then sound_cmd <= cpu_do; end if; if cpu_wr_n = '0' and cpu_addr(15 downto 0) = X"D001" then flip_int <= cpu_do(0); end if; @@ -400,7 +384,7 @@ end process; -- write enable to working ram from CPU -- ------------------------------------------ wram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"E" else '0'; - +--sram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"9" else '0'; ---------------------- --- sprite machine --- ---------------------- @@ -434,14 +418,15 @@ end process; -- from x080 to x0FF and from x1C0 to x1FF when not flipped (scrolling zone from x100 to x1BF) -- within scrolling zone sprite data ram is accessed by sprite data scanner (spr_hcnt) -cpu_has_spr_ram <= '1' when ( vcnt < '1'&x"3F" and vflip = '0') or - ((vcnt > '1'&x"C0" or vcnt < '0'&x"FF") and vflip = '1') else '0'; +cpu_has_spr_ram <= '1' when ( vcnt < '1'&x"3F" and flip = '0') or + ((vcnt > '1'&x"C0" or vcnt < '0'&x"FF") and flip = '1') else '0'; sprram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 11) = X"C"&"1" and cpu_has_spr_ram = '1' else '0'; sprram_addr <= '0' & spr_hcnt(10 downto 4) & spr_hcnt(2 downto 1) when cpu_has_spr_ram = '0' else cpu_addr(9 downto 0); + -- latch current sprite data with respect to pixel and hcnt in relation with sprite data ram addressing process (clock_36) begin @@ -465,8 +450,7 @@ end process; spr_vcnt <= vcnt_flip(7 downto 0) + spr_posv_r - 1 ; spr_on_line <= '1' when spr_vcnt(7 downto 4) = x"F" and cpu_has_spr_ram = '0' else '0'; spr_line_cnt <= spr_vcnt(4 downto 0) xor (spr_attr_r(7) & spr_attr_r(7) & spr_attr_r(7) & spr_attr_r(7) & spr_attr_r(7)); -spr_code_line <= spr_code_r & (spr_attr_r(6) xor not spr_hcnt(3)) & spr_line_cnt(3 downto 0) when shtrider = '0' else - spr_code_r & spr_line_cnt(3) & (spr_attr_r(6) xor not spr_hcnt(3)) & spr_line_cnt(2 downto 0); +spr_code_line <= spr_code_r & (spr_attr_r(6) xor not spr_hcnt(3)) & spr_line_cnt(3 downto 0); -- get and serialise sprite graphics data and w.r.t enable (attr(5)) and h_flip (attr(6)) -- and compute palette address from graphics bits and color set# @@ -582,9 +566,9 @@ hcnt_scrolled_flip <= hcnt_scrolled(2 downto 0) when flip = '1' else not (hcnt_s -- address char code at pixel # 4 -- give access to CPU for all other pixels with hcnt_scrolled_flip(2 downto 0) select -chrram_addr <= vcnt_flip(6 downto 3) & hcnt_scrolled(8 downto 3) & '1' when "000", - vcnt_flip(6 downto 3) & hcnt_scrolled(8 downto 3) & '0' when "100", - cpu_addr(10 downto 0) when others; +chrram_addr <= vcnt_flip(7 downto 3) & hcnt_scrolled(8 downto 3) & '1' when "000", + vcnt_flip(7 downto 3) & hcnt_scrolled(8 downto 3) & '0' when "100", + cpu_addr(11 downto 0) when others; -- write enable to char tile ram from CPU chrram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"8" and hcnt_scrolled_flip(1 downto 0) /= "00" else '0'; @@ -618,6 +602,7 @@ begin if pix_ena = '1' then chr_palette_addr(6 downto 3) <= chr_color; chr_palette_addr(7) <= '0'; +-- chr_palette_addr(8) <= '0'; if chr_flip_h = '0' then chr_palette_addr(0) <= chr_graphx1_do(to_integer(unsigned(not(hcnt_scrolled(2 downto 0))))); chr_palette_addr(1) <= chr_graphx2_do(to_integer(unsigned(not(hcnt_scrolled(2 downto 0))))); @@ -647,17 +632,13 @@ begin video_r <= spr_rgb_lut_do(7 downto 6); video_g <= spr_rgb_lut_do(5 downto 3); video_b <= spr_rgb_lut_do(2 downto 0); - elsif shtrider = '0' then -- 1x8 bit in Traverse USA - video_r <= chr_palette_1_do(7 downto 6); - video_g <= chr_palette_1_do(5 downto 3); - video_b <= chr_palette_1_do(2 downto 0); - else -- 2x4 bit in Shot Rider - video_r <= chr_palette_1_do(3 downto 2); - video_g <= chr_palette_1_do(1 downto 0) & chr_palette_2_do(3); - video_b <= chr_palette_2_do(2 downto 0); + else + video_r <= chr_palette_do(7 downto 6); + video_g <= chr_palette_do(5 downto 3); + video_b <= chr_palette_do(2 downto 0); end if; end if; - + end if; end process; @@ -666,19 +647,14 @@ end process; --------------------------------------------------------- moon_patrol_sound_board : entity work.moon_patrol_sound_board port map( - clock_E => clock_0p895, - areset => reset, - - select_sound => sound_cmd, -- not(key(1)) & sw(6 downto 0), - audio_out => audio, - - rom_addr => snd_rom_addr, - rom_do => snd_rom_do, - - dbg_cpu_addr => open --dbg_cpu_addr + clock_E => clock_0p895, + areset => reset, + select_sound => sound_cmd, + snd_rom_addr => snd_rom_addr, + snd_rom_do => snd_rom_do, + audio_out => audio ); - audio_out <= audio(11 downto 1); ---------------------------- @@ -687,7 +663,7 @@ audio_out <= audio(11 downto 1); video_csync <= csync; -process(clock_36, pix_ena) +process(clock_36) constant hcnt_base : integer := 180; variable hsync_cnt : std_logic_vector(8 downto 0); variable vsync_cnt : std_logic_vector(3 downto 0); @@ -764,12 +740,12 @@ end process; ------------------------------ -- microprocessor Z80 -cpu : entity work.T80s +cpu : entity work.T80se generic map(Mode => 0, T2Write => 1, IOWait => 1) port map( RESET_n => reset_n, - CLK => clock_36, - CEN => cpu_ena, + CLK_n => not clock_36, + CLKEN => cpu_ena, WAIT_n => '1', INT_n => cpu_irq_n, NMI_n => '1', --cpu_nmi_n, @@ -787,50 +763,31 @@ port map( DO => cpu_do ); --- cpu program ROM 0x0000-0x7FFF ---rom_cpu : entity work.travusa_cpu ---port map( --- clk => clock_36n, --- addr => cpu_addr(14 downto 0), --- data => cpu_rom_do ---); cpu_rom_addr <= cpu_addr(14 downto 0); -cpu_rom_rd <= '1' when cpu_mreq_n = '0' and cpu_addr(15) = '0'; --- working RAM 0xE000-0xEFFF +-- working RAM 0xE000-0xE7FF wram : entity work.gen_ram -generic map( dWidth => 8, aWidth => 12) +generic map( dWidth => 8, aWidth => 11) port map( clk => clock_36n, we => wram_we, - addr => cpu_addr(11 downto 0), + addr => cpu_addr(10 downto 0), d => cpu_do, q => wram_do ); --- char RAM 0x8000-0x91FF -scrollram : entity work.gen_ram -generic map( dWidth => 8, aWidth => 9) -port map( - clk => clock_36n, - we => scroll_we, - addr => scroll_addr, - d => cpu_do, - q => scroll_do -); - --- scoll RAM 0x9000-0x87FF +-- char RAM 0x8000-0x87FF chrram : entity work.gen_ram generic map( dWidth => 8, aWidth => 11) port map( clk => clock_36n, we => chrram_we, - addr => chrram_addr, + addr => chrram_addr(10 downto 0), d => cpu_do, q => chrram_do ); --- sprite RAM 0xC800-0xCBFF +-- sprite RAM 0xC820-0xC8FF sprite_ram : entity work.gen_ram generic map( dWidth => 8, aWidth => 10) port map( @@ -864,143 +821,106 @@ port map( ); -- char graphics ROM 3E -char_graphics_1 : entity work.dpram -generic map( dWidth => 8, aWidth => 13) +char_graphics_1 : entity work.tropical_chr_bit1 port map( - clk_a => clock_36n, - addr_a => chr_code_line, - q_a => chr_graphx1_do, - clk_b => clock_36, - we_b => char_graphics_1_we, - addr_b => dl_addr(12 downto 0), - d_b => dl_data + clk => clock_36n, + addr => chr_code_line, + data => chr_graphx1_do ); -char_graphics_1_we <= '1' when dl_addr(16 downto 13) = "0101" and dl_wr = '1' else '0'; -- 0A000-0BFFF --- char graphics ROM 3E -char_graphics_2 : entity work.dpram -generic map( dWidth => 8, aWidth => 13) +-- char graphics ROM 3D +char_graphics_2 : entity work.tropical_chr_bit2 port map( - clk_a => clock_36n, - addr_a => chr_code_line, - q_a => chr_graphx2_do, - clk_b => clock_36, - we_b => char_graphics_2_we, - addr_b => dl_addr(12 downto 0), - d_b => dl_data + clk => clock_36n, + addr => chr_code_line, + data => chr_graphx2_do ); -char_graphics_2_we <= '1' when dl_addr(16 downto 13) = "0110" and dl_wr = '1' else '0'; -- 0C000-0DFFF --- char graphics ROM 3E -char_graphics_3 : entity work.dpram -generic map( dWidth => 8, aWidth => 13) +-- char graphics ROM 3C +char_graphics_3 : entity work.tropical_chr_bit3 port map( - clk_a => clock_36n, - addr_a => chr_code_line, - q_a => chr_graphx3_do, - clk_b => clock_36, - we_b => char_graphics_3_we, - addr_b => dl_addr(12 downto 0), - d_b => dl_data + clk => clock_36n, + addr => chr_code_line, + data => chr_graphx3_do ); -char_graphics_3_we <= '1' when dl_addr(16 downto 13) = "0111" and dl_wr = '1' else '0'; -- 0E000-0FFFF --char palette ROM -char_palette_1 : entity work.dpram -generic map( dWidth => 8, aWidth => 8) +char_palette_l : entity work.tropical_chr_palette_l port map( - clk_a => clock_36n, - addr_a => chr_palette_addr, - q_a => chr_palette_1_do, - clk_b => clock_36, - we_b => chr_palette_1_we, - addr_b => dl_addr(7 downto 0), - d_b => dl_data + clk => clock_36n, + addr => chr_palette_addr, + data => chr_palette1_do ); -chr_palette_1_we <= '1' when dl_addr(16 downto 8) = "101100000" and dl_wr = '1' else '0'; -- 16000-160FF -char_palette_2 : entity work.dpram -generic map( dWidth => 8, aWidth => 8) +char_palette_h : entity work.tropical_chr_palette_h port map( - clk_a => clock_36n, - addr_a => chr_palette_addr, - q_a => chr_palette_2_do, - clk_b => clock_36, - we_b => chr_palette_2_we, - addr_b => dl_addr(7 downto 0), - d_b => dl_data + clk => clock_36n, + addr => chr_palette_addr, + data => chr_palette2_do ); -chr_palette_2_we <= '1' when dl_addr(16 downto 8) = "101100001" and dl_wr = '1' else '0'; -- 16100-161FF - +chr_palette_do <= chr_palette2_do(3 downto 0) & chr_palette1_do(3 downto 0); -- sprite graphics ROM 3N -sprite_graphics_1 : entity work.dpram -generic map( dWidth => 8, aWidth => 13) +sprite_graphics_1 : entity work.tropical_spr_bit1 port map( - clk_a => clock_36n, - addr_a => spr_code_line, - q_a => spr_graphx1_do, - clk_b => clock_36, - we_b => sprite_graphics_1_we, - addr_b => dl_addr(12 downto 0), - d_b => dl_data + clk => clock_36n, + addr => spr_code_line, + data => spr_graphx1_do ); -sprite_graphics_1_we <= '1' when dl_addr(16 downto 13) = "1000" and dl_wr = '1' else '0'; -- 10000-11FFF -- sprite graphics ROM 3L or 3M -sprite_graphics_2 : entity work.dpram -generic map( dWidth => 8, aWidth => 13) +sprite_graphics_2 : entity work.tropical_spr_bit2 port map( - clk_a => clock_36n, - addr_a => spr_code_line, - q_a => spr_graphx2_do, - clk_b => clock_36, - we_b => sprite_graphics_2_we, - addr_b => dl_addr(12 downto 0), - d_b => dl_data + clk => clock_36n, + addr => spr_code_line, + data => spr_graphx2_do ); -sprite_graphics_2_we <= '1' when dl_addr(16 downto 13) = "1001" and dl_wr = '1' else '0'; -- 12000-13FFF -- sprite graphics ROM 3K -sprite_graphics_3 : entity work.dpram -generic map( dWidth => 8, aWidth => 13) +sprite_graphics_3 : entity work.tropical_spr_bit3 port map( - clk_a => clock_36n, - addr_a => spr_code_line, - q_a => spr_graphx3_do, - clk_b => clock_36, - we_b => sprite_graphics_3_we, - addr_b => dl_addr(12 downto 0), - d_b => dl_data + clk => clock_36n, + addr => spr_code_line, + data => spr_graphx3_do +); + +-- sprite graphics ROM 3N +sprite_graphics_4 : entity work.tropical_spr_bit4 +port map( + clk => clock_36n, + addr => spr_code_line, + data => spr_graphx4_do +); + +-- sprite graphics ROM 3L or 3M +sprite_graphics_5 : entity work.tropical_spr_bit5 +port map( + clk => clock_36n, + addr => spr_code_line, + data => spr_graphx5_do +); + +-- sprite graphics ROM 3K +sprite_graphics_6 : entity work.tropical_spr_bit6 +port map( + clk => clock_36n, + addr => spr_code_line, + data => spr_graphx6_do ); -sprite_graphics_3_we <= '1' when dl_addr(16 downto 13) = "1010" and dl_wr = '1' else '0'; -- 14000-15FFF -- sprite palette ROM 2H -spr_palette : entity work.dpram -generic map( dWidth => 8, aWidth => 8) +spr_palette: entity work.tropical_spr_palette port map( - clk_a => clock_36n, - addr_a => spr_palette_addr, - q_a => spr_palette_do, - clk_b => clock_36, - we_b => spr_palette_we, - addr_b => dl_addr(7 downto 0), - d_b => dl_data + clk => clock_36n, + addr => spr_palette_addr, + data => spr_palette_do ); -spr_palette_we <= '1' when dl_addr(16 downto 8) = "101100010" and dl_wr = '1' else '0'; -- 16200-162FF -- sprite rgb lut ROM 1F -spr_rgb_lut : entity work.dpram -generic map( dWidth => 8, aWidth => 8) +spr_rgb_lut: entity work.tropical_spr_rgb_lut port map( - clk_a => clock_36n, - addr_a => "000"&spr_rgb_lut_addr, -- extended to 8 bit, prevents segfault of Quartus - q_a => spr_rgb_lut_do, - clk_b => clock_36, - we_b => spr_lut_we, - addr_b => "000"&dl_addr(4 downto 0), - d_b => dl_data, - q_b => open + clk => clock_36n, + addr => spr_rgb_lut_addr, + data => spr_rgb_lut_do ); -spr_lut_we <= '1' when dl_addr(16 downto 5) = "101100011000" and dl_wr = '1' else '0'; -- 16300-1631F end struct; \ No newline at end of file diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TraverseUSA_MiST.sv b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel_MiST.sv similarity index 77% rename from Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TraverseUSA_MiST.sv rename to Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel_MiST.sv index 6f25bfa1..42e17c64 100644 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TraverseUSA_MiST.sv +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/TropicalAngel_MiST.sv @@ -1,5 +1,5 @@ //============================================================================ -// Arcade: TraverseUSA, ShotRider +// Arcade: Tropical Angel // // DarFPGA's core ported to MiST by (C) 2019 Szombathelyi György // @@ -18,7 +18,7 @@ // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. //============================================================================ -module TraverseUSA_MiST( +module TropicalAngel_MiST( output LED, output [5:0] VGA_R, output [5:0] VGA_G, @@ -50,33 +50,30 @@ module TraverseUSA_MiST( `include "rtl/build_id.v" -reg shtrider = 1; - -wire [7:0] dip1 = 8'hff; -reg [7:0] dip2 = 8'hff; - - localparam CONF_STR = { - "TROPANG;rom;", + "TROPANG;;", "O2,Rotate Controls,Off,On;", "O34,Scanlines,Off,25%,50%,75%;", - "OA,Blending,Off,On;", + "O5,Analog Accelarator,Off,On;", + "O6,Stop Mode,Off,On;", + "O7,Invulnerability,Off,On;", + "O9,Test mode,Off,On;", "T0,Reset;", "V,v1.0.",`BUILD_DATE }; -assign LED = 1; -assign AUDIO_R = AUDIO_L; -assign SDRAM_CLK = clk_sys; -assign SDRAM_CKE = 1; +assign LED = ~ioctl_downl; +assign SDRAM_CLK = clk_sd; +assign SDRAM_CKE = 1; -wire clk_sys, clk_aud; +wire clk_sys, clk_aud, clk_sd; wire pll_locked; pll_mist pll( .inclk0(CLOCK_27), .areset(0), .c0(clk_sys), .c1(clk_aud), + .c2(clk_sd), .locked(pll_locked) ); @@ -94,28 +91,19 @@ wire blankn; wire [2:0] g,b; wire [1:0] r; -wire [14:0] cart_addr; -wire [15:0] sdram_do; -wire cart_rd; +wire [14:0] rom_addr; +wire [15:0] rom_do; wire [12:0] snd_addr; wire [15:0] snd_do; - +wire [14:0] sp_addr; +wire [31:0] sp_do; wire ioctl_downl; wire [7:0] ioctl_index; wire ioctl_wr; wire [24:0] ioctl_addr; wire [7:0] ioctl_dout; -/* ROM structure -00000-07FFF CPU ROM 32k zr1-0.m3 zr1-5.l3 zr1-6a.k3 zr1-7.j3 -08000-09FFF SND ROM 8k mr10.1a mr10.1a -0A000-0FFFF GFX1 24k zippyrac.001 mr8.3c mr9.3a -10000-15FFF GFX2 24k zr1-8.n3 zr1-9.l3 zr1-10.k3 -16000-161FF CHR PAL 512b mmi6349.ij -16200-162FF SPR PAL 256b tbp24s10.3 -16300-1631F SPR LUT 32b tbp18s.2 -*/ -data_io data_io ( +data_io data_io( .clk_sys ( clk_sys ), .SPI_SCK ( SPI_SCK ), .SPI_SS2 ( SPI_SS2 ), @@ -127,13 +115,15 @@ data_io data_io ( .ioctl_dout ( ioctl_dout ) ); +wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h11000; //SP ROM offset: 0x11000 + reg port1_req, port2_req; sdram sdram( .*, .init_n ( pll_locked ), - .clk ( clk_sys ), + .clk ( clk_sd ), - // port1 used for main CPU + // port1 used for main + sound CPU .port1_req ( port1_req ), .port1_ack ( ), .port1_a ( ioctl_addr[23:1] ), @@ -142,23 +132,26 @@ sdram sdram( .port1_d ( {ioctl_dout, ioctl_dout} ), .port1_q ( ), - .cpu1_addr ( ioctl_downl ? 15'h7fff : {1'b0, cart_addr[14:1]} ), - .cpu1_q ( sdram_do ), - - // port2 for sound board + .cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, rom_addr[14:1]} ), + .cpu1_q ( rom_do ), + .cpu2_addr ( ioctl_downl ? 16'hffff : (16'h4000 + snd_addr[12:1]) ), + .cpu2_q ( snd_do ), + + // port2 for sprite graphics .port2_req ( port2_req ), .port2_ack ( ), - .port2_a ( ioctl_addr[23:1] - 16'h4000 ), - .port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port2_a ( {sp_ioctl_addr[14:0], sp_ioctl_addr[16]} ), // merge sprite roms to 32-bit wide words + .port2_ds ( {sp_ioctl_addr[15], ~sp_ioctl_addr[15]} ), .port2_we ( ioctl_downl ), .port2_d ( {ioctl_dout, ioctl_dout} ), .port2_q ( ), - .snd_addr ( ioctl_downl ? 15'h7fff : {3'b000, snd_addr[12:1]} ), - .snd_q ( snd_do ) + .sp_addr ( ioctl_downl ? 15'h7fff : sp_addr ), + .sp_q ( sp_do ) ); -always @(posedge clk_sys) begin +// ROM download controller +always @(posedge clk_sd) begin reg ioctl_wr_last = 0; ioctl_wr_last <= ioctl_wr; @@ -170,41 +163,53 @@ always @(posedge clk_sys) begin end end +// reset signal generation reg reset = 1; reg rom_loaded = 0; always @(posedge clk_sys) begin reg ioctl_downlD; + reg [15:0] reset_count; ioctl_downlD <= ioctl_downl; + // generate a second reset signal - needed for some reason + if (status[0] | buttons[1] | ~rom_loaded) reset_count <= 16'hffff; + else if (reset_count != 0) reset_count <= reset_count - 1'd1; + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; - reset <= status[0] | buttons[1] | ~rom_loaded; + reset <= status[0] | buttons[1] | ~rom_loaded | (reset_count == 16'h0001); + end +wire [7:0] dip1 = "00000010"; +//Diag(7) / Demo(6) / Zippy(5) / Freeze (4) / M-Km(3) / Coin mode (2) / Cocktail(1) / Flip(0) +wire [7:0] dip2 = { 1'b1, ~status[7],1'b1, ~status[6], ~status[5], 3'b011}; -// Traverse_usa -traverse_usa traverse_usa ( +TropicalAngel TropicalAngel( .clock_36 ( clk_sys ), .clock_0p895 ( clk_aud ), - .reset ( reset ), + .reset ( reset ), - .shtrider ( shtrider ), - .video_r ( r ), .video_g ( g ), .video_b ( b ), - .video_hs ( hs ), + .video_hs ( hs ), .video_vs ( vs ), .video_blankn ( blankn ), .audio_out ( audio ), + .cpu_rom_addr ( rom_addr ), + .cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ), + .snd_rom_addr ( snd_addr ), + .snd_rom_do ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ), + .dip_switch_1 ( dip1 ), .dip_switch_2 ( dip2 ), .start2 ( btn_two_players ), .start1 ( btn_one_player ), .coin1 ( btn_coin ), - + .service ( ~status[9] ), .right1 ( m_right ), .left1 ( m_left ), .brake1 ( m_down ), @@ -213,16 +218,7 @@ traverse_usa traverse_usa ( .right2 ( m_right ), .left2 ( m_left ), .brake2 ( m_down ), - .accel2 ( m_up ), - - .cpu_rom_addr ( cart_addr ), - .cpu_rom_do ( cart_addr[0] ? sdram_do[15:8] : sdram_do[7:0] ), - .cpu_rom_rd ( cart_rd ), - .snd_rom_addr ( snd_addr ), - .snd_rom_do ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ), - .dl_addr ( ioctl_addr[16:0]), - .dl_data ( ioctl_dout ), - .dl_wr ( ioctl_wr ) + .accel2 ( m_up ) ); mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( @@ -243,9 +239,7 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( .rotate ( {1'b1,status[2]} ), .scandoubler_disable( scandoublerD ), .scanlines ( status[4:3] ), - .ypbpr ( ypbpr ), - .ce_divider ( 1'b0 ), - .blend ( status[10] ) + .ypbpr ( ypbpr ) ); user_io #( @@ -269,13 +263,17 @@ user_io( .status (status ) ); +wire dac_o; +assign AUDIO_L = dac_o; +assign AUDIO_R = dac_o; + dac #( .C_bits(11)) dac( .clk_i(clk_aud), - .res_n_i(~reset), + .res_n_i(1), .dac_i(audio), - .dac_o(AUDIO_L) + .dac_o(dac_o) ); // Rotated Normal diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/dpram.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/dpram.vhd deleted file mode 100644 index 284194c5..00000000 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/dpram.vhd +++ /dev/null @@ -1,81 +0,0 @@ --- ----------------------------------------------------------------------- --- --- Syntiac's generic VHDL support files. --- --- ----------------------------------------------------------------------- --- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) --- http://www.syntiac.com/fpga64.html --- --- Modified April 2016 by Dar (darfpga@aol.fr) --- http://darfpga.blogspot.fr --- Remove address register when writing --- --- ----------------------------------------------------------------------- --- --- dpram.vhd --- --- ----------------------------------------------------------------------- --- --- generic ram. --- --- ----------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - --- ----------------------------------------------------------------------- - -entity dpram is - generic ( - dWidth : integer := 8; - aWidth : integer := 10 - ); - port ( - clk_a : in std_logic; - we_a : in std_logic := '0'; - addr_a : in std_logic_vector((aWidth-1) downto 0); - d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); - q_a : out std_logic_vector((dWidth-1) downto 0); - - clk_b : in std_logic; - we_b : in std_logic := '0'; - addr_b : in std_logic_vector((aWidth-1) downto 0); - d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); - q_b : out std_logic_vector((dWidth-1) downto 0) - ); -end entity; - --- ----------------------------------------------------------------------- - -architecture rtl of dpram is - subtype addressRange is integer range 0 to ((2**aWidth)-1); - type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); - signal ram: ramDef; - signal addr_a_reg: std_logic_vector((aWidth-1) downto 0); - signal addr_b_reg: std_logic_vector((aWidth-1) downto 0); -begin - --- ----------------------------------------------------------------------- - process(clk_a) - begin - if rising_edge(clk_a) then - if we_a = '1' then - ram(to_integer(unsigned(addr_a))) <= d_a; - end if; - q_a <= ram(to_integer(unsigned(addr_a))); - end if; - end process; - - process(clk_b) - begin - if rising_edge(clk_b) then - if we_b = '1' then - ram(to_integer(unsigned(addr_b))) <= d_b; - end if; - q_b <= ram(to_integer(unsigned(addr_b))); - end if; - end process; - -end architecture; - diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/moon_patrol_sound_board.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/moon_patrol_sound_board.vhd index 509e1825..b4cdb314 100644 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/moon_patrol_sound_board.vhd +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/moon_patrol_sound_board.vhd @@ -31,10 +31,8 @@ port( select_sound : in std_logic_vector(7 downto 0); audio_out : out std_logic_vector(11 downto 0); - - rom_addr : out std_logic_vector(12 downto 0); - rom_do : in std_logic_vector( 7 downto 0); - + snd_rom_addr: out std_logic_vector(12 downto 0); + snd_rom_do : in std_logic_vector(7 downto 0); dbg_cpu_addr : out std_logic_vector(15 downto 0) ); end moon_patrol_sound_board; @@ -86,7 +84,7 @@ architecture struct of moon_patrol_sound_board is signal wram_do : std_logic_vector( 7 downto 0); signal rom_cs : std_logic; --- signal rom_do : std_logic_vector( 7 downto 0); + signal rom_do : std_logic_vector( 7 downto 0); signal ay1_chan_a : std_logic_vector(7 downto 0); signal ay1_chan_b : std_logic_vector(7 downto 0); @@ -164,7 +162,7 @@ wram_cs <= '1' when cpu_addr(15 downto 7) = X"00"&'1' else '0'; -- 0080-00FF ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F adpcm_cs <= '1' when cpu_addr(14 downto 11) = "0001" else '0'; -- 0800-0FFF / 8800-8FFF irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001" else '0'; -- 1000-1FFF / 9000-9FFF -rom_cs <= '1' when cpu_addr(14 downto 13) = "11" else '0'; -- 6000-7FFF / E000-FFFF +rom_cs <= '1' when cpu_addr(14 downto 12) = "111" else '0'; -- 7000-7FFF / F000-FFFF -- write enables wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0'; @@ -179,7 +177,7 @@ cpu_di <= port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else - rom_do when rom_cs = '1' else X"55"; + snd_rom_do when rom_cs = '1' else X"55"; process (clock_E) begin @@ -351,10 +349,12 @@ port map( --cpu_prog_rom : entity work.travusa_sound --port map( -- clk => clock_E, --- addr => cpu_addr(11 downto 0), +-- addr => cpu_addr(12 downto 0), -- data => rom_do --); -rom_addr <= cpu_addr(12 downto 0); + + +snd_rom_addr <= cpu_addr(12 downto 0); -- cpu wram cpu_ram : entity work.gen_ram diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/pll_mist.vhd b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/pll_mist.vhd index 7afa03b7..b8b54173 100644 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/pll_mist.vhd +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/pll_mist.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2013 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -46,6 +46,7 @@ ENTITY pll_mist IS inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END pll_mist; @@ -58,9 +59,10 @@ ARCHITECTURE SYN OF pll_mist IS SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -75,6 +77,10 @@ ARCHITECTURE SYN OF pll_mist IS clk1_duty_cycle : NATURAL; clk1_multiply_by : NATURAL; clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; @@ -135,15 +141,17 @@ ARCHITECTURE SYN OF pll_mist IS END COMPONENT; BEGIN - sub_wire6_bv(0 DOWNTO 0) <= "0"; - sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); sub_wire3 <= sub_wire0(0); sub_wire1 <= sub_wire0(1); c1 <= sub_wire1; locked <= sub_wire2; c0 <= sub_wire3; - sub_wire4 <= inclk0; - sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; altpll_component : altpll GENERIC MAP ( @@ -152,10 +160,14 @@ BEGIN clk0_duty_cycle => 50, clk0_multiply_by => 41, clk0_phase_shift => "0", - clk1_divide_by => 1200, + clk1_divide_by => 2475, clk1_duty_cycle => 50, - clk1_multiply_by => 41, + clk1_multiply_by => 82, clk1_phase_shift => "0", + clk2_divide_by => 26, + clk2_duty_cycle => 50, + clk2_multiply_by => 71, + clk2_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 37037, intended_device_family => "Cyclone III", @@ -190,7 +202,7 @@ BEGIN port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", + port_clk2 => "PORT_USED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", @@ -209,7 +221,7 @@ BEGIN ) PORT MAP ( areset => areset, - inclk => sub_wire5, + inclk => sub_wire6, clk => sub_wire0, locked => sub_wire2 ); @@ -238,11 +250,14 @@ END SYN; -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "30" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1200" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2475" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "26" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.900002" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.922500" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.894545" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "73.730766" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -264,25 +279,33 @@ END SYN; -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "41" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "82" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "71" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.86400000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.89500000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "73.72000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -306,13 +329,16 @@ END SYN; -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -321,10 +347,14 @@ END SYN; -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1200" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2475" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "41" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "82" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "26" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "71" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -358,7 +388,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -379,6 +409,7 @@ END SYN; -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 @@ -386,6 +417,7 @@ END SYN; -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE diff --git a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/sdram.sv b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/sdram.sv index baeb7b5e..41f5b7a8 100644 --- a/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/sdram.sv +++ b/Arcade_MiST/IremM57 Hardware/TropicalAngel_MiST/rtl/sdram.sv @@ -44,10 +44,12 @@ module sdram ( input [23:1] port1_a, input [1:0] port1_ds, input [15:0] port1_d, - output [15:0] port1_q, + output reg [15:0] port1_q, - input [15:1] cpu1_addr, + input [16:1] cpu1_addr, output reg [15:0] cpu1_q, + input [16:1] cpu2_addr, + output reg [15:0] cpu2_q, input port2_req, output reg port2_ack, @@ -55,14 +57,14 @@ module sdram ( input [23:1] port2_a, input [1:0] port2_ds, input [15:0] port2_d, - output [15:0] port2_q, - - input [15:1] snd_addr, - output reg [15:0] snd_q + output reg [31:0] port2_q, + + input [16:2] sp_addr, + output reg [31:0] sp_q ); localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz -localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8 localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved localparam CAS_LATENCY = 3'd2; // 2/3 allowed localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed @@ -81,21 +83,24 @@ localparam RFRSH_CYCLES = 10'd842; SDRAM state machine for 2 bank interleaved access 1 word burst, CL2 cmd issued registered - 0 RAS0 cas1 + 0 RAS0 cas1 - data0 read burst terminated 1 ras0 - 2 CAS0 data1 returned - 3 RAS1 cas0 - 4 ras1 - 5 CAS1 data0 returned + 2 data1 returned + 3 CAS0 data1 returned + 4 RAS1 cas0 + 5 ras1 + 6 CAS1 data0 returned */ localparam STATE_RAS0 = 3'd0; // first state in cycle -localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns) -localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3 -localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5 -localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7 +localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns) +localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3 +localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6 +localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7 localparam STATE_READ1 = 3'd3; -localparam STATE_LAST = 3'd5; +localparam STATE_DS1b = 3'd0; +localparam STATE_READ1b = 3'd4; +localparam STATE_LAST = 3'd6; reg [2:0] t; @@ -137,7 +142,7 @@ localparam CMD_PRECHARGE = 4'b0010; localparam CMD_AUTO_REFRESH = 4'b0001; localparam CMD_LOAD_MODE = 4'b0000; -reg [3:0] sd_cmd; // current command sent to sd ram +reg [3:0] sd_cmd; // current command sent to sd ram reg [15:0] sd_din; // drive control signals according to current command assign SDRAM_nCS = sd_cmd[3]; @@ -147,24 +152,25 @@ assign SDRAM_nWE = sd_cmd[0]; reg [24:1] addr_latch[2]; reg [24:1] addr_latch_next[2]; -reg [15:1] addr_last[2]; -reg [15:1] addr_last2[2]; +reg [16:1] addr_last[2]; +reg [16:2] addr_last2[2]; reg [15:0] din_latch[2]; reg [1:0] oe_latch; reg [1:0] we_latch; reg [1:0] ds[2]; -localparam PORT_NONE = 2'd0; -localparam PORT_CPU1 = 2'd1; -localparam PORT_REQ = 2'd2; - -localparam PORT_SND = 2'd1; - -reg [2:0] next_port[2]; -reg [2:0] port[2]; reg port1_state; reg port2_state; +localparam PORT_NONE = 2'd0; +localparam PORT_CPU1 = 2'd1; +localparam PORT_CPU2 = 2'd2; +localparam PORT_SP = 2'd1; +localparam PORT_REQ = 2'd3; + +reg [1:0] next_port[2]; +reg [1:0] port[2]; + reg refresh; reg [10:0] refresh_cnt; wire need_refresh = (refresh_cnt >= RFRSH_CYCLES); @@ -179,21 +185,24 @@ always @(*) begin addr_latch_next[0] = { 1'b0, port1_a }; end else if (cpu1_addr != addr_last[PORT_CPU1]) begin next_port[0] = PORT_CPU1; - addr_latch_next[0] = { 9'd0, cpu1_addr }; + addr_latch_next[0] = { 8'd0, cpu1_addr }; + end else if (cpu2_addr != addr_last[PORT_CPU2]) begin + next_port[0] = PORT_CPU2; + addr_latch_next[0] = { 8'd0, cpu2_addr }; end else begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; end end -// PORT2: bank 2,3 +// PORT1: bank 2,3 always @(*) begin if (port2_req ^ port2_state) begin next_port[1] = PORT_REQ; addr_latch_next[1] = { 1'b1, port2_a }; - end else if (snd_addr != addr_last2[PORT_SND]) begin - next_port[1] = PORT_SND; - addr_latch_next[1] = { 1'b1, 8'd0, snd_addr }; + end else if (sp_addr != addr_last2[PORT_SP]) begin + next_port[1] = PORT_SP; + addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 }; end else begin next_port[1] = PORT_NONE; addr_latch_next[1] = addr_latch[1]; @@ -237,15 +246,15 @@ always @(posedge clk) begin { oe_latch[0], we_latch[0] } <= 2'b00; if (next_port[0] != PORT_NONE) begin - port1_state <= port1_req; sd_cmd <= CMD_ACTIVE; SDRAM_A <= addr_latch_next[0][22:10]; SDRAM_BA <= addr_latch_next[0][24:23]; - addr_last[next_port[0]] <= addr_latch_next[0][15:1]; + addr_last[next_port[0]] <= addr_latch_next[0][16:1]; if (next_port[0] == PORT_REQ) begin { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; ds[0] <= port1_ds; din_latch[0] <= port1_d; + port1_state <= port1_req; end else begin { oe_latch[0], we_latch[0] } <= 2'b10; ds[0] <= 2'b11; @@ -261,15 +270,15 @@ always @(posedge clk) begin port[1] <= next_port[1]; if (next_port[1] != PORT_NONE) begin - port2_state <= port2_req; sd_cmd <= CMD_ACTIVE; SDRAM_A <= addr_latch_next[1][22:10]; SDRAM_BA <= addr_latch_next[1][24:23]; - addr_last2[next_port[1]] <= addr_latch_next[1][15:1]; + addr_last2[next_port[1]] <= addr_latch_next[1][16:2]; if (next_port[1] == PORT_REQ) begin - { oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we }; + { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; ds[1] <= port2_ds; din_latch[1] <= port2_d; + port2_state <= port2_req; end else begin { oe_latch[1], we_latch[1] } <= 2'b10; ds[1] <= 2'b11; @@ -311,13 +320,25 @@ always @(posedge clk) begin case(port[0]) PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end PORT_CPU1: begin cpu1_q <= sd_din; end + PORT_CPU2: begin cpu2_q <= sd_din; end default: ; endcase; end + if(t == STATE_READ1 && oe_latch[1]) begin case(port[1]) - PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end - PORT_SND: begin snd_q <= sd_din; end + PORT_REQ: port2_q[15:0] <= sd_din; + PORT_SP : sp_q[15:0] <= sd_din; + default: ; + endcase; + end + + if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + + if(t == STATE_READ1b && oe_latch[1]) begin + case(port[1]) + PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end + PORT_SP : begin sp_q[31:16] <= sd_din; end default: ; endcase; end