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Vectrex: make it compile again
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@@ -36,7 +36,8 @@ reg [5:0] red_last;
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reg [5:0] green_last;
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reg [5:0] blue_last;
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always @(posedge clk) if (pix_ce) begin
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wire ce = enable ? pix_ce : 1'b1;
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always @(posedge clk) if (ce) begin
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hblank_out <= hblank;
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vblank_out <= vblank;
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