From 2690dc04da5a69407e053340fbda02b458aec2a7 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sun, 31 May 2020 21:19:22 +0200 Subject: [PATCH] Add a good version of YM2149 to common --- common/Sound/YM2149.sv | 326 ------------------ .../YM2149.vhd} | 278 +++++++++++---- common/Sound/ym2149/vol_table_array.vhd | 293 ++++++++++++++++ 3 files changed, 513 insertions(+), 384 deletions(-) delete mode 100644 common/Sound/YM2149.sv rename common/Sound/{YM2149_linmix_sep.vhd => ym2149/YM2149.vhd} (71%) create mode 100644 common/Sound/ym2149/vol_table_array.vhd diff --git a/common/Sound/YM2149.sv b/common/Sound/YM2149.sv deleted file mode 100644 index e4cf9525..00000000 --- a/common/Sound/YM2149.sv +++ /dev/null @@ -1,326 +0,0 @@ -// -// Copyright (c) MikeJ - Jan 2005 -// Copyright (c) 2016-2018 Sorgelig -// -// All rights reserved -// -// Redistribution and use in source and synthezised forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// Redistributions in synthesized form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// Neither the name of the author nor the names of other contributors may -// be used to endorse or promote products derived from this software without -// specific prior written permission. -// -// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// - - -// BDIR BC MODE -// 0 0 inactive -// 0 1 read value -// 1 0 write value -// 1 1 set address -// - -module YM2149 -( - input CLK, // Global clock - input CE, // PSG Clock enable - input RESET, // Chip RESET (set all Registers to '0', active hi) - input BDIR, // Bus Direction (0 - read , 1 - write) - input BC, // Bus control - input [7:0] DI, // Data In - output [7:0] DO, // Data Out - output [7:0] CHANNEL_A, // PSG Output channel A - output [7:0] CHANNEL_B, // PSG Output channel B - output [7:0] CHANNEL_C, // PSG Output channel C - - input SEL, - input MODE, - - output [5:0] ACTIVE, - - input [7:0] IOA_in, - output [7:0] IOA_out, - - input [7:0] IOB_in, - output [7:0] IOB_out -); - -assign ACTIVE = ~ymreg[7][5:0]; -assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff; -assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff; - -reg [7:0] addr; -reg [7:0] ymreg[16]; - -// Write to PSG -reg env_reset; -always @(posedge CLK) begin - if(RESET) begin - ymreg <= '{default:0}; - ymreg[7] <= '1; - addr <= '0; - env_reset <= 0; - end else begin - env_reset <= 0; - if(BDIR) begin - if(BC) addr <= DI; - else if(!addr[7:4]) begin - ymreg[addr[3:0]] <= DI; - env_reset <= (addr == 13); - end - end - end -end - -// Read from PSG -assign DO = dout; -reg [7:0] dout; -always_comb begin - dout = 8'hFF; - if(~BDIR & BC & !addr[7:4]) begin - case(addr[3:0]) - 0: dout = ymreg[0]; - 1: dout = ymreg[1][3:0]; - 2: dout = ymreg[2]; - 3: dout = ymreg[3][3:0]; - 4: dout = ymreg[4]; - 5: dout = ymreg[5][3:0]; - 6: dout = ymreg[6][4:0]; - 7: dout = ymreg[7]; - 8: dout = ymreg[8][4:0]; - 9: dout = ymreg[9][4:0]; - 10: dout = ymreg[10][4:0]; - 11: dout = ymreg[11]; - 12: dout = ymreg[12]; - 13: dout = ymreg[13][3:0]; - 14: dout = ymreg[7][6] ? ymreg[14] : IOA_in; - 15: dout = ymreg[7][7] ? ymreg[15] : IOB_in; - endcase - end -end - -reg ena_div; -reg ena_div_noise; - -// p_divider -always @(posedge CLK) begin - reg [3:0] cnt_div; - reg noise_div; - - if(CE) begin - ena_div <= 0; - ena_div_noise <= 0; - if(!cnt_div) begin - cnt_div <= {SEL, 3'b111}; - ena_div <= 1; - - noise_div <= (~noise_div); - if (noise_div) ena_div_noise <= 1; - end else begin - cnt_div <= cnt_div - 1'b1; - end - end -end - - -reg [2:0] noise_gen_op; - -// p_noise_gen -always @(posedge CLK) begin - reg [16:0] poly17; - reg [4:0] noise_gen_cnt; - - if(CE) begin - if (ena_div_noise) begin - if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin - noise_gen_cnt <= 0; - poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]}; - end else begin - noise_gen_cnt <= noise_gen_cnt + 1'd1; - end - noise_gen_op <= {3{poly17[0]}}; - end - end -end - -wire [11:0] tone_gen_freq[1:3]; -assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]}; -assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]}; -assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]}; - -reg [3:1] tone_gen_op; - -//p_tone_gens -always @(posedge CLK) begin - integer i; - reg [11:0] tone_gen_cnt[1:3]; - - if(CE) begin - // looks like real chips count up - we need to get the Exact behaviour .. - - for (i = 1; i <= 3; i = i + 1) begin - if(ena_div) begin - if (tone_gen_freq[i]) begin - if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin - tone_gen_cnt[i] <= 0; - tone_gen_op[i] <= ~tone_gen_op[i]; - end else begin - tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1; - end - end else begin - tone_gen_op[i] <= ymreg[7][i]; - tone_gen_cnt[i] <= 0; - end - end - end - end -end - -reg env_ena; -wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0; - -//p_envelope_freq -always @(posedge CLK) begin - reg [15:0] env_gen_cnt; - - if(CE) begin - env_ena <= 0; - if(ena_div) begin - if (env_gen_cnt >= env_gen_comp) begin - env_gen_cnt <= 0; - env_ena <= 1; - end else begin - env_gen_cnt <= (env_gen_cnt + 1'd1); - end - end - end -end - -reg [4:0] env_vol; - -wire is_bot = (env_vol == 5'b00000); -wire is_bot_p1 = (env_vol == 5'b00001); -wire is_top_m1 = (env_vol == 5'b11110); -wire is_top = (env_vol == 5'b11111); - -always @(posedge CLK) begin - reg env_hold; - reg env_inc; - - // envelope shapes - // C AtAlH - // 0 0 x x \___ - // - // 0 1 x x /___ - // - // 1 0 0 0 \\\\ - // - // 1 0 0 1 \___ - // - // 1 0 1 0 \/\/ - // ___ - // 1 0 1 1 \ - // - // 1 1 0 0 //// - // ___ - // 1 1 0 1 / - // - // 1 1 1 0 /\/\ - // - // 1 1 1 1 /___ - - if(env_reset | RESET) begin - // load initial state - if(!ymreg[13][2]) begin // attack - env_vol <= 5'b11111; - env_inc <= 0; // -1 - end else begin - env_vol <= 5'b00000; - env_inc <= 1; // +1 - end - env_hold <= 0; - end - else if(CE) begin - if (env_ena) begin - if (!env_hold) begin - if (env_inc) env_vol <= (env_vol + 5'b00001); - else env_vol <= (env_vol + 5'b11111); - end - - // envelope shape control. - if(!ymreg[13][3]) begin - if(!env_inc) begin // down - if(is_bot_p1) env_hold <= 1; - end else if (is_top) env_hold <= 1; - end else if(ymreg[13][0]) begin // hold = 1 - if(!env_inc) begin // down - if(ymreg[13][1]) begin // alt - if(is_bot) env_hold <= 1; - end else if(is_bot_p1) env_hold <= 1; - end else if(ymreg[13][1]) begin // alt - if(is_top) env_hold <= 1; - end else if(is_top_m1) env_hold <= 1; - end else if(ymreg[13][1]) begin // alternate - if(env_inc == 1'b0) begin // down - if(is_bot_p1) env_hold <= 1; - if(is_bot) begin - env_hold <= 0; - env_inc <= 1; - end - end else begin - if(is_top_m1) env_hold <= 1; - if(is_top) begin - env_hold <= 0; - env_inc <= 0; - end - end - end - end - end -end - -reg [5:0] A,B,C; -always @(posedge CLK) begin - A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}}; - B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}}; - C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}}; -end - -wire [7:0] volTable[64] = '{ - //YM2149 - 8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, - 8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, - 8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, - 8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff, - - //AY8910 - 8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, - 8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, - 8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, - 8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff -}; - -assign CHANNEL_A = volTable[A]; -assign CHANNEL_B = volTable[B]; -assign CHANNEL_C = volTable[C]; - -endmodule diff --git a/common/Sound/YM2149_linmix_sep.vhd b/common/Sound/ym2149/YM2149.vhd similarity index 71% rename from common/Sound/YM2149_linmix_sep.vhd rename to common/Sound/ym2149/YM2149.vhd index 27f26749..b5e463cc 100644 --- a/common/Sound/YM2149_linmix_sep.vhd +++ b/common/Sound/ym2149/YM2149.vhd @@ -51,31 +51,42 @@ -- to produced all the required values. -- (The first part of the curve is a bit steeper and the last bit is more linear than expected) -- --- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only --- accurate for designs where the outputs are buffered and not simply wired together. --- The ouput level is more complex in that case and requires a larger table. +-- NOTE, when MIXER_VOLTABLE = '0', this component uses LINEAR mixing of the three analogue channels, +-- and is only accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table (MIXER_VOLTABLE = '1'). library ieee; use ieee.std_logic_1164.all; - use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; entity YM2149 is + generic ( + MIXER_VOLTABLE : std_logic := '0' + ); port ( -- data bus I_DA : in std_logic_vector(7 downto 0); O_DA : out std_logic_vector(7 downto 0); O_DA_OE_L : out std_logic; -- control - I_A9_L : in std_logic; - I_A8 : in std_logic; + I_A9_L : in std_logic := '0'; + I_A8 : in std_logic := '1'; I_BDIR : in std_logic; - I_BC2 : in std_logic; + I_BC2 : in std_logic := '1'; I_BC1 : in std_logic; - I_SEL_L : in std_logic; + I_SEL_L : in std_logic := '1'; + I_STEREO : in std_logic := '0'; + + -- separate channel output O_AUDIO : out std_logic_vector(7 downto 0); O_CHAN : out std_logic_vector(1 downto 0); + + -- mixed output + O_AUDIO_L : out std_logic_vector(9 downto 0); + O_AUDIO_R : out std_logic_vector(9 downto 0); + -- port a I_IOA : in std_logic_vector(7 downto 0); O_IOA : out std_logic_vector(7 downto 0); @@ -87,7 +98,7 @@ entity YM2149 is ENA : in std_logic; -- clock enable for higher speed operation RESET_L : in std_logic; - CLK : in std_logic -- note 6 Mhz + CLK : in std_logic ); end; @@ -130,6 +141,17 @@ architecture RTL of YM2149 is signal chan_vol : std_logic_vector(4 downto 0); signal dac_amp : std_logic_vector(7 downto 0); + + signal vol_l : std_logic_vector(9 downto 0); + signal vol_r : std_logic_vector(9 downto 0); + signal vol_mixer_l : std_logic_vector(9 downto 0); + signal vol_mixer_r : std_logic_vector(9 downto 0); + + signal vol_table_in_l : std_logic_vector(11 downto 0); + signal vol_table_in_r : std_logic_vector(11 downto 0); + signal vol_table_out_l : std_logic_vector(9 downto 0); + signal vol_table_out_r : std_logic_vector(9 downto 0); + begin -- cpu i/f p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) @@ -183,10 +205,8 @@ begin if (RESET_L = '0') then addr <= (others => '0'); elsif rising_edge(CLK) then - if (ENA = '1') then - if (busctrl_addr = '1') then - addr <= I_DA; - end if; + if (busctrl_addr = '1') then + addr <= I_DA; end if; end if; end process; @@ -197,28 +217,11 @@ begin reg <= (others => (others => '0')); env_reset <= '1'; elsif rising_edge(CLK) then - if (ENA = '1') then - env_reset <= '0'; - if (busctrl_we = '1') then - case addr(3 downto 0) is - when x"0" => reg(0) <= I_DA; - when x"1" => reg(1) <= I_DA; - when x"2" => reg(2) <= I_DA; - when x"3" => reg(3) <= I_DA; - when x"4" => reg(4) <= I_DA; - when x"5" => reg(5) <= I_DA; - when x"6" => reg(6) <= I_DA; - when x"7" => reg(7) <= I_DA; - when x"8" => reg(8) <= I_DA; - when x"9" => reg(9) <= I_DA; - when x"A" => reg(10) <= I_DA; - when x"B" => reg(11) <= I_DA; - when x"C" => reg(12) <= I_DA; - when x"D" => reg(13) <= I_DA; env_reset <= '1'; - when x"E" => reg(14) <= I_DA; - when x"F" => reg(15) <= I_DA; - when others => null; - end case; + env_reset <= '0'; + if (busctrl_we = '1') then + reg(to_integer(unsigned(addr(3 downto 0)))) <= I_DA; + if addr(3 downto 0) = x"D" then + env_reset <= '1'; end if; end if; end if; @@ -246,12 +249,12 @@ begin when x"E" => if (reg(7)(6) = '0') then -- input O_DA <= ioa_inreg; else - O_DA <= reg(14); -- read output reg + O_DA <= reg(14) and ioa_inreg; -- read output reg end if; when x"F" => if (Reg(7)(7) = '0') then O_DA <= iob_inreg; else - O_DA <= reg(15); + O_DA <= reg(15) and iob_inreg; end if; when others => null; end case; @@ -372,25 +375,46 @@ begin variable is_top_m1 : boolean; variable is_top : boolean; begin - if (env_reset = '1') then - -- load initial state - if (reg(13)(2) = '0') then -- attack - env_vol <= "11111"; - env_inc <= '0'; -- -1 + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if rising_edge(CLK) then + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + else - env_vol <= "00000"; - env_inc <= '1'; -- +1 - end if; - env_hold <= '0'; + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); - elsif rising_edge(CLK) then - is_bot := (env_vol = "00000"); - is_bot_p1 := (env_vol = "00001"); - is_top_m1 := (env_vol = "11110"); - is_top := (env_vol = "11111"); - - if (ENA = '1') then - if (env_ena = '1') then + if (ENA = '1' and env_ena = '1') then if (env_hold = '0') then if (env_inc = '1') then env_vol <= (env_vol + "00001"); @@ -438,6 +462,8 @@ begin end if; end process; +-- output mixer + p_chan_mixer : process(cnt_div, reg, tone_gen_op) begin tone_ena_l <= '1'; tone_src <= '1'; @@ -531,9 +557,147 @@ begin O_AUDIO <= dac_amp(7 downto 0); O_CHAN <= cnt_div_t1(1 downto 0); end if; + end if; end process; + -- output mixer(s) + + p_chan_mixer_linear : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + vol_l <= (others => '0'); + vol_r <= (others => '0'); + vol_mixer_l <= (others => '0'); + vol_mixer_r <= (others => '0'); + elsif rising_edge(CLK) then + + if (ENA = '1') then + case cnt_div_t1(1 downto 0) is + when "10" => -- Channel C + vol_r <= "00" & dac_amp; + if I_STEREO = '0' then + vol_l <= "00" & dac_amp; + else + vol_l <= (others => '0'); + end if; + when "01" => -- Channel B + vol_l <= vol_l + dac_amp; + vol_r <= vol_r + dac_amp; + when "00" => -- Channel A + if I_STEREO = '0' then + vol_mixer_l <= vol_l + dac_amp; + else + vol_mixer_l <= vol_l; + end if; + vol_mixer_r <= vol_r + dac_amp; + when others => null; + end case; + end if; + end if; + end process; + + VOLTABLE: if MIXER_VOLTABLE = '1' generate + + p_chan_mixer_table : process + variable chan_mixed : std_logic_vector(2 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + chan_mixed(0) := (reg(7)(0) or tone_gen_op(1)) and (reg(7)(3) or noise_gen_op); + chan_mixed(1) := (reg(7)(1) or tone_gen_op(2)) and (reg(7)(4) or noise_gen_op); + chan_mixed(2) := (reg(7)(2) or tone_gen_op(3)) and (reg(7)(5) or noise_gen_op); + + vol_table_in_l <= x"000"; + vol_table_in_r <= x"000"; + + if (chan_mixed(0) = '1') then + if(I_STEREO = '1') then + if (reg(8)(4) = '0') then + vol_table_in_l(3 downto 0) <= reg(8)(3 downto 0); + else + vol_table_in_l(3 downto 0) <= env_vol(4 downto 1); + end if; + else + if (reg(8)(4) = '0') then + vol_table_in_l(3 downto 0) <= reg(8)(3 downto 0); + vol_table_in_r(3 downto 0) <= reg(8)(3 downto 0); + else + vol_table_in_l(3 downto 0) <= env_vol(4 downto 1); + vol_table_in_r(3 downto 0) <= env_vol(4 downto 1); + end if; + end if; + end if; + + if (chan_mixed(1) = '1') then + if (reg(9)(4) = '0') then + vol_table_in_l(7 downto 4) <= reg(9)(3 downto 0); + vol_table_in_r(7 downto 4) <= reg(9)(3 downto 0); + else + vol_table_in_l(7 downto 4) <= env_vol(4 downto 1); + vol_table_in_r(7 downto 4) <= env_vol(4 downto 1); + end if; + end if; + + if (chan_mixed(2) = '1') then + if(I_STEREO = '1') then + if (reg(10)(4) = '0') then + vol_table_in_r(11 downto 8) <= reg(10)(3 downto 0); + else + vol_table_in_r(11 downto 8) <= env_vol(4 downto 1); + end if; + else + if (reg(10)(4) = '0') then + vol_table_in_l(11 downto 8) <= reg(10)(3 downto 0); + vol_table_in_r(11 downto 8) <= reg(10)(3 downto 0); + else + vol_table_in_l(11 downto 8) <= env_vol(4 downto 1); + vol_table_in_r(11 downto 8) <= env_vol(4 downto 1); + end if; + end if; + end if; + end if; + end process; + + u_vol_table : work.vol_table + port map ( + CLK => clk, + ADDR_A => vol_table_in_l, + DATA_A => vol_table_out_l, + ADDR_B => vol_table_in_r, + DATA_B => vol_table_out_r + ); + end generate; -- VOLTABLE + + NO_VOLTABLE: if MIXER_VOLTABLE = '0' generate + vol_table_out_l <= (others => '0'); + vol_table_out_r <= (others => '0'); + end generate; + + -- mixed audio output + + p_vol_out : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + + if (RESET_L = '0') then + O_AUDIO_L <= (others => '0'); + O_AUDIO_R <= (others => '0'); + else + if (MIXER_VOLTABLE = '1') then + O_AUDIO_L <= vol_table_out_l; + O_AUDIO_R <= vol_table_out_r; + else + O_AUDIO_L <= vol_mixer_l; + O_AUDIO_R <= vol_mixer_r; + end if; + end if; + end process; + + -- IO ports + p_io_ports : process(reg) begin O_IOA <= reg(14); @@ -545,9 +709,7 @@ begin p_io_ports_inreg : process begin wait until rising_edge(CLK); - if (ENA = '1') then -- resync - ioa_inreg <= I_IOA; - iob_inreg <= I_IOB; - end if; + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; end process; end architecture RTL; diff --git a/common/Sound/ym2149/vol_table_array.vhd b/common/Sound/ym2149/vol_table_array.vhd new file mode 100644 index 00000000..6f64d956 --- /dev/null +++ b/common/Sound/ym2149/vol_table_array.vhd @@ -0,0 +1,293 @@ +-- Sixteen level by Three voice YM2149 volume_table[C][B][A] +-- Data measured by Paulo Simoes. Copyright 2012 Paulo Simoes. +-- original 16 bit data reduced to 10 bit + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vol_table is + port ( + CLK : in std_logic; + ADDR_A : in std_logic_vector(11 downto 0); + DATA_A : out std_logic_vector(9 downto 0); + ADDR_B : in std_logic_vector(11 downto 0); + DATA_B : out std_logic_vector(9 downto 0) + ); +end; + +architecture RTL of vol_table is + + + type ROM_ARRAY is array(0 to 4095) of std_logic_vector(9 downto 0); + constant voltable : ROM_ARRAY := ( + "00"&x"00","00"&x"01","00"&x"03","00"&x"06","00"&x"09","00"&x"0d","00"&x"13","00"&x"1a","00"&x"27","00"&x"36","00"&x"50","00"&x"6e","00"&x"a1","00"&x"e4","01"&x"66","10"&x"1a", + "00"&x"01","00"&x"04","00"&x"06","00"&x"08","00"&x"0c","00"&x"0f","00"&x"16","00"&x"1d","00"&x"2a","00"&x"38","00"&x"52","00"&x"70","00"&x"a4","00"&x"e6","01"&x"67","10"&x"1a", + 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