diff --git a/.gitignore b/.gitignore
index 06fe373b..fc217d13 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,4 @@
 Robotron - Z1013_MiST/Z1013_Mist.pti_db_list.ddb
 Robotron - Z1013_MiST/Z1013_Mist.tis_db_list.ddb
 Sharp - MZ-80K_MiST/mz80k.qws
+Robotron - Z1013_MiST/Z1013_Mist.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/Snapshot/galaga.rbf b/Arcade_MiST/Custom Hardware/Galaga_MIST/Snapshot/galaga.rbf
deleted file mode 100644
index b04a2353..00000000
Binary files a/Arcade_MiST/Custom Hardware/Galaga_MIST/Snapshot/galaga.rbf and /dev/null differ
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/Snapshot/galaga_mist.rbf b/Arcade_MiST/Custom Hardware/Galaga_MIST/Snapshot/galaga_mist.rbf
new file mode 100644
index 00000000..d4587015
Binary files /dev/null and b/Arcade_MiST/Custom Hardware/Galaga_MIST/Snapshot/galaga_mist.rbf differ
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qpf b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qpf
index 0ec77b14..82a737e3 100644
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qpf	
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qpf	
@@ -1,29 +1,30 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
+# Copyright (C) 2016  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
 # and other software and tools, and its AMPP partner logic 
 # functions, and any output files from any of the foregoing 
 # (including device programming or simulation files), and any 
 # associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Intel and sold by Intel or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
 #
 # -------------------------------------------------------------------------- #
 #
-# Quartus II 64-Bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-# Date created = 20:10:08  November 14, 2016
+# Quartus Prime
+# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+# Date created = 11:01:44  November 04, 2017
 #
 # -------------------------------------------------------------------------- #
 
-QUARTUS_VERSION = "13.0"
-DATE = "20:10:08  November 14, 2016"
+QUARTUS_VERSION = "16.1"
+DATE = "11:01:44  November 04, 2017"
 
 # Revisions
 
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qsf b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qsf
index 274d00aa..01c085d2 100644
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qsf	
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qsf	
@@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 1991-2014 Altera Corporation
+# Copyright (C) 1991-2013 Altera Corporation
 # Your use of Altera Corporation's design tools, logic functions 
 # and other software and tools, and its AMPP partner logic 
 # functions, and any output files from any of the foregoing 
@@ -17,23 +17,27 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 08:30:59  December 07, 2015
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 15:12:41  May 07, 2018
 #
 # -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24  MAY 17, 2014"
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		galaga_mist_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
 set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-
-# Pin & Location Assignments
-# ==========================
 set_location_assignment PIN_7 -to LED
 set_location_assignment PIN_54 -to CLOCK_27
 set_location_assignment PIN_144 -to VGA_R[5]
@@ -61,143 +65,74 @@ set_location_assignment PIN_80 -to AUDIO_R
 set_location_assignment PIN_105 -to SPI_DO
 set_location_assignment PIN_88 -to SPI_DI
 set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
 set_location_assignment PIN_91 -to SPI_SS3
 set_location_assignment PIN_13 -to CONF_DATA0
 set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
 set_global_assignment -name FAMILY "Cyclone III"
 set_global_assignment -name TOP_LEVEL_ENTITY galaga_mist
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
 set_global_assignment -name DEVICE EP3C25E144C8
 set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
 set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
 set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
-
-# Power Estimation Assignments
-# ============================
+set_global_assignment -name GENERATE_RBF_FILE ON
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
 set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
 set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+	set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE10_LITE_Default -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity DE10_LITE_Default -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -entity DE10_LITE_Default -section_id Top
+		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE10_LITE_Default -section_id Top
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
-# ------------------------
-# start ENTITY(galaga_mist)
-
-# Pin & Location Assignments
-# ==========================
-
-# Fitter Assignments
-# ==================
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
-
-# end ENTITY(galaga_mist)
-# ----------------------
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VHDL_FILE rtl/ROM/sp_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/sp_graphx.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/sound_seq.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/sound_samples.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/galaga_cpu3.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/galaga_cpu2.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/galaga_cpu1.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/bg_palette.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/bg_graphx.vhd
-set_global_assignment -name VHDL_FILE rtl/CPU/T80se.vhd
-set_global_assignment -name VHDL_FILE rtl/CPU/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/CPU/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/CPU/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/CPU/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/CPU/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/mb88.vhd
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
 set_global_assignment -name VHDL_FILE rtl/stars_machine.vhd
 set_global_assignment -name VHDL_FILE rtl/stars.vhd
+set_global_assignment -name VHDL_FILE rtl/sp_palette.vhd
+set_global_assignment -name VHDL_FILE rtl/sp_graphx.vhd
+set_global_assignment -name VHDL_FILE rtl/sound_seq.vhd
+set_global_assignment -name VHDL_FILE rtl/sound_samples.vhd
 set_global_assignment -name VHDL_FILE rtl/sound_machine.vhd
 set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
 set_global_assignment -name VHDL_FILE rtl/rgb.vhd
 set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_global_assignment -name VERILOG_FILE rtl/osd.v
 set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
-set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
 set_global_assignment -name VHDL_FILE rtl/galaga_mist.vhd
+set_global_assignment -name VHDL_FILE rtl/galaga_cpu3.vhd
+set_global_assignment -name VHDL_FILE rtl/galaga_cpu2.vhd
+set_global_assignment -name VHDL_FILE rtl/galaga_cpu1.vhd
 set_global_assignment -name VHDL_FILE rtl/galaga.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
 set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_global_assignment -name VHDL_FILE rtl/cs54xx_prog.vhd
+set_global_assignment -name VHDL_FILE rtl/bg_palette.vhd
+set_global_assignment -name VHDL_FILE rtl/bg_graphx.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_video.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.srf b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.srf
new file mode 100644
index 00000000..f5b4c3aa
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.srf	
@@ -0,0 +1 @@
+{ "" "" "" "*" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/bg_palette.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/bg_palette.vhd
deleted file mode 100644
index b7edf1e5..00000000
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/bg_palette.vhd	
+++ /dev/null
@@ -1,38 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity bg_palette is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(7 downto 0);
-	data : out std_logic_vector(3 downto 0)
-);
-end entity;
-
-architecture prom of bg_palette is
-	type rom is array(0 to  255) of std_logic_vector(3 downto 0);
-	signal rom_data: rom := (
-		X"F",X"0",X"0",X"6",X"F",X"D",X"1",X"0",X"F",X"2",X"C",X"D",X"F",X"B",X"1",X"0",
-		X"F",X"1",X"0",X"1",X"F",X"0",X"0",X"2",X"F",X"0",X"0",X"3",X"F",X"0",X"0",X"5",
-		X"F",X"0",X"0",X"9",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"F",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"F",X"B",X"7",X"6",X"F",X"6",X"B",X"7",X"F",X"7",X"6",X"B",X"F",X"F",X"F",X"1",
-		X"F",X"F",X"B",X"F",X"F",X"2",X"F",X"F",X"F",X"6",X"6",X"B",X"F",X"6",X"B",X"B",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sound_samples.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sound_samples.vhd
deleted file mode 100644
index b983efbd..00000000
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sound_samples.vhd	
+++ /dev/null
@@ -1,38 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity sound_samples is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(7 downto 0);
-	data : out std_logic_vector(3 downto 0)
-);
-end entity;
-
-architecture prom of sound_samples is
-	type rom is array(0 to  255) of std_logic_vector(3 downto 0);
-	signal rom_data: rom := (
-		X"7",X"9",X"A",X"B",X"C",X"D",X"D",X"E",X"E",X"E",X"D",X"D",X"C",X"B",X"A",X"9",
-		X"7",X"5",X"4",X"3",X"2",X"1",X"1",X"0",X"0",X"0",X"1",X"1",X"2",X"3",X"4",X"5",
-		X"7",X"9",X"A",X"B",X"7",X"D",X"D",X"7",X"E",X"7",X"D",X"D",X"7",X"B",X"A",X"9",
-		X"7",X"5",X"7",X"3",X"7",X"1",X"7",X"0",X"7",X"0",X"7",X"1",X"7",X"3",X"7",X"5",
-		X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",X"E",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"B",X"D",X"E",X"D",X"C",X"A",X"8",X"8",X"8",X"A",X"C",X"D",X"E",X"D",X"B",X"8",
-		X"4",X"2",X"1",X"2",X"3",X"5",X"7",X"7",X"7",X"5",X"3",X"2",X"1",X"2",X"4",X"7",
-		X"7",X"A",X"C",X"D",X"E",X"D",X"C",X"A",X"7",X"4",X"2",X"1",X"0",X"1",X"2",X"4",
-		X"7",X"B",X"D",X"E",X"D",X"B",X"7",X"3",X"1",X"0",X"1",X"3",X"7",X"E",X"7",X"0",
-		X"7",X"E",X"C",X"9",X"C",X"E",X"A",X"7",X"C",X"F",X"D",X"8",X"A",X"B",X"7",X"2",
-		X"8",X"D",X"9",X"4",X"5",X"7",X"2",X"0",X"3",X"8",X"5",X"1",X"3",X"6",X"3",X"1",
-		X"7",X"8",X"A",X"C",X"E",X"D",X"C",X"C",X"B",X"A",X"8",X"7",X"5",X"6",X"7",X"8",
-		X"8",X"9",X"A",X"B",X"9",X"8",X"6",X"5",X"4",X"4",X"3",X"2",X"4",X"6",X"8",X"9",
-		X"A",X"C",X"C",X"A",X"7",X"7",X"8",X"B",X"D",X"E",X"D",X"A",X"6",X"5",X"5",X"7",
-		X"9",X"9",X"8",X"4",X"1",X"0",X"1",X"3",X"6",X"7",X"7",X"4",X"2",X"2",X"4",X"7");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sound_seq.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sound_seq.vhd
deleted file mode 100644
index 50ca39f7..00000000
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sound_seq.vhd	
+++ /dev/null
@@ -1,30 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity sound_seq is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(6 downto 0);
-	data : out std_logic_vector(3 downto 0)
-);
-end entity;
-
-architecture prom of sound_seq is
-	type rom is array(0 to  127) of std_logic_vector(3 downto 0);
-	signal rom_data: rom := (
-		X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",
-		X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",
-		X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",
-		X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",X"F",X"D",X"F",X"F",
-		X"7",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D",
-		X"F",X"F",X"E",X"D",X"F",X"F",X"F",X"B",X"7",X"F",X"E",X"D",X"F",X"F",X"E",X"D",
-		X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"F",X"B",X"7",X"F",X"E",X"D",
-		X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"E",X"D",X"F",X"F",X"F",X"B");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sp_palette.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sp_palette.vhd
deleted file mode 100644
index 006b8ab1..00000000
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sp_palette.vhd	
+++ /dev/null
@@ -1,38 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity sp_palette is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(7 downto 0);
-	data : out std_logic_vector(3 downto 0)
-);
-end entity;
-
-architecture prom of sp_palette is
-	type rom is array(0 to  255) of std_logic_vector(3 downto 0);
-	signal rom_data: rom := (
-		X"F",X"8",X"E",X"2",X"F",X"5",X"B",X"C",X"F",X"0",X"B",X"1",X"F",X"1",X"B",X"2",
-		X"F",X"8",X"D",X"2",X"F",X"6",X"1",X"4",X"F",X"9",X"1",X"5",X"F",X"7",X"B",X"1",
-		X"F",X"1",X"6",X"B",X"F",X"1",X"B",X"0",X"F",X"1",X"2",X"0",X"F",X"0",X"1",X"6",
-		X"F",X"0",X"0",X"6",X"F",X"3",X"B",X"9",X"F",X"6",X"2",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",
-		X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0",X"0");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80_ALU.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80_ALU.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80_MCode.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80_MCode.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Pack.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Pack.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Reg.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80_Reg.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80se.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80se.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/CPU/T80se.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/T80/T80se.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/bg_graphx.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/bg_graphx.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/bg_graphx.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/bg_graphx.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/bg_palette.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/bg_palette.vhd
new file mode 100644
index 00000000..579ca20f
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/bg_palette.vhd	
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity bg_palette is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(7 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of bg_palette is
+	type rom is array(0 to  255) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"00",X"00",X"06",X"0F",X"0D",X"01",X"00",X"0F",X"02",X"0C",X"0D",X"0F",X"0B",X"01",X"00",
+		X"0F",X"01",X"00",X"01",X"0F",X"00",X"00",X"02",X"0F",X"00",X"00",X"03",X"0F",X"00",X"00",X"05",
+		X"0F",X"00",X"00",X"09",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"0F",X"0B",X"07",X"06",X"0F",X"06",X"0B",X"07",X"0F",X"07",X"06",X"0B",X"0F",X"0F",X"0F",X"01",
+		X"0F",X"0F",X"0B",X"0F",X"0F",X"02",X"0F",X"0F",X"0F",X"06",X"06",X"0B",X"0F",X"06",X"0B",X"0B",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga.vhd
index b6d04f39..3627d8a9 100644
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga.vhd	
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga.vhd	
@@ -17,9 +17,14 @@
 -- Do not redistribute roms whatever the form
 -- Use at your own risk
 ---------------------------------------------------------------------------------
------------------
 -- Galaga releases
 --
+-- Release 0.3 - 06/05/2018 - Dar
+--    add mb88 explosion sound ship 
+--
+-- Release 0.2 - 06/11/2017 - Dar
+--    fixes twice bullets on single shot => add edge detection en fire
+--
 -- Release 0.1 - 04/11/2017 - Dar
 --		fixes 2 ships bullet bug (swap 2xH/2xV command bits)
 --
@@ -29,14 +34,14 @@
 --  Features :
 --   TV 15KHz mode only (atm)
 --   Coctail mode ok
---   Sound ok, Ship explode missing (custom chip 0x54XX todo)
+--   Sound ok
 --   Starfield from MAME information  
 
 --  Use with MAME roms from galagamw.zip
 --
 --  Use make_galaga_proms.bat to build vhd file from binaries
 
--- 	 galaga_cpu1.vhd   : 3200a.bin, 3300b.bin, 3400c.bin,3500d.bin, 
+--   galaga_cpu1.vhd   : 3200a.bin, 3300b.bin, 3400c.bin,3500d.bin, 
 --   galaga_cpu2.vhd   : 3600e.bin
 --   galaga_cpu3.vhd   : 3700g.bin
 --   bg_graphx.vhd     : 2600j.bin
@@ -77,7 +82,7 @@
 --      simplified emulation in vhdl : 1coin/1credit, 1 or 2 players start
 --
 --    Namco 54XX for sound effects 
---      no emulation in vhdl atm
+--      m88 ok
 --
 --    Namco sound waveform and frequency synthetizer
 --      full original emulation in vhdl
@@ -99,14 +104,15 @@ use ieee.numeric_std.all;
 
 entity galaga is
 port(
- clock_18       : in std_logic;
- reset          : in std_logic;
+ clock_18     : in std_logic;
+ reset        : in std_logic;
+-- tv15Khz_mode : in std_logic;
  video_r        : out std_logic_vector(2 downto 0);
  video_g        : out std_logic_vector(2 downto 0);
  video_b        : out std_logic_vector(1 downto 0);
- video_hs       : out std_logic;
- video_vs       : out std_logic;
  video_blankn   : out std_logic;
+ video_hs     : out std_logic;
+ video_vs     : out std_logic;
  pix_ce         : out std_logic;
  audio          : out std_logic_vector(9 downto 0);
 
@@ -125,7 +131,6 @@ port(
 end galaga;
 
 architecture struct of galaga is
-
  signal reset_n: std_logic;
  signal clock_18n : std_logic;
 
@@ -144,7 +149,7 @@ architecture struct of galaga is
  signal cpu1_mreq_n : std_logic;
  signal cpu1_irq_n  : std_logic;
  signal cpu1_nmi_n  : std_logic;
-
+ signal cpu1_m1_n   : std_logic;
 
  signal cpu2_addr   : std_logic_vector(15 downto 0);
  signal cpu2_di     : std_logic_vector( 7 downto 0);
@@ -152,7 +157,7 @@ architecture struct of galaga is
  signal cpu2_wr_n   : std_logic;
  signal cpu2_mreq_n : std_logic;
  signal cpu2_irq_n : std_logic;
-
+ signal cpu2_m1_n   : std_logic;
  
  signal cpu3_addr   : std_logic_vector(15 downto 0);
  signal cpu3_di     : std_logic_vector( 7 downto 0);
@@ -160,7 +165,7 @@ architecture struct of galaga is
  signal cpu3_wr_n   : std_logic;
  signal cpu3_mreq_n : std_logic;
  signal cpu3_nmi_n  : std_logic;
-
+ signal cpu3_m1_n   : std_logic;
 
  signal bgtile_addr : std_logic_vector(15 downto 0);
  signal sprite_addr : std_logic_vector(15 downto 0);
@@ -191,10 +196,10 @@ architecture struct of galaga is
  signal cs06XX_do      : std_logic_vector( 7 downto 0);
  signal cs06XX_di      : std_logic_vector( 7 downto 0);
 
- signal cs51XX_data_cnt           : std_logic_vector( 1 downto 0);
- signal cs51XX_coin_mode_cnt      : std_logic_vector( 2 downto 0);
- signal cs51XX_switch_mode        : std_logic;
- signal cs51XX_credit_mode        : std_logic;
+ signal cs51XX_data_cnt           : std_logic_vector( 1 downto 0) := "00";
+ signal cs51XX_coin_mode_cnt      : std_logic_vector( 2 downto 0) := "000";
+ signal cs51XX_switch_mode        : std_logic := '0';
+ signal cs51XX_credit_mode        : std_logic := '1';
  signal cs51XX_do                 : std_logic_vector( 7 downto 0);
  signal cs51XX_switch_mode_do     : std_logic_vector( 7 downto 0);
  signal cs51XX_non_switch_mode_do : std_logic_vector( 7 downto 0);
@@ -202,8 +207,23 @@ architecture struct of galaga is
  signal credit_bcd_0              : std_logic_vector( 3 downto 0);
  signal credit_bcd_1              : std_logic_vector( 3 downto 0);
  
- signal cs54XX_cmd        : std_logic_vector( 3 downto 0);
- signal cs54XX_do         : std_logic_vector( 7 downto 0);
+-- signal cs54xx_cmd        : std_logic_vector( 3 downto 0);
+ signal cs54xx_do         : std_logic_vector( 7 downto 0);
+ 
+ signal cs54xx_ena      : std_logic;
+ signal cs54xx_ena_div  : std_logic_vector(2 downto 0) := "000";
+ signal cs5Xxx_rw       : std_logic;
+ 
+ signal cs54xx_rom_addr : std_logic_vector(10 downto 0); 
+ signal cs54xx_rom_do   : std_logic_vector( 7 downto 0); 
+ 
+ signal cs54xx_irq_n      : std_logic := '1'; 
+ signal cs54xx_irq_cnt    : std_logic_vector( 3 downto 0); 
+ signal cs54xx_k_port_in  : std_logic_vector( 3 downto 0); 
+ signal cs54xx_r0_port_in : std_logic_vector( 3 downto 0); 
+ signal cs54xx_audio_1    : std_logic_vector( 3 downto 0); 
+ signal cs54xx_audio_2    : std_logic_vector( 3 downto 0); 
+ signal cs54xx_audio_3    : std_logic_vector( 3 downto 0); 
 
  signal cs05XX_ctrl       : std_logic_vector( 5 downto 0);
  
@@ -218,7 +238,7 @@ architecture struct of galaga is
  signal bggraphx_addr  : std_logic_vector(11 downto 0);
  signal bggraphx_do    : std_logic_vector( 7 downto 0);
  signal bgpalette_addr : std_logic_vector( 7 downto 0);
- signal bgpalette_do   : std_logic_vector( 3 downto 0); 
+ signal bgpalette_do   : std_logic_vector( 7 downto 0); 
  signal bgbits         : std_logic_vector( 3 downto 0);
 
  signal rgb_palette_addr : std_logic_vector( 4 downto 0);
@@ -239,7 +259,7 @@ architecture struct of galaga is
  signal spgraphx_addr  : std_logic_vector(12 downto 0);
  signal spgraphx_do    : std_logic_vector(7 downto 0);
  signal sppalette_addr : std_logic_vector(7 downto 0);
- signal sppalette_do   : std_logic_vector(3 downto 0); 
+ signal sppalette_do   : std_logic_vector(7 downto 0); 
  signal spbits_wr      : std_logic_vector(3 downto 0);
  signal spbits_rd      : std_logic_vector(3 downto 0);
  signal spflip_V ,spflip_H  : std_logic;
@@ -282,13 +302,19 @@ architecture struct of galaga is
 
  signal snd_ram_0_we : std_logic;
  signal snd_ram_1_we : std_logic;
+ signal snd_audio    : std_logic_vector(9 downto 0);
 
  signal coin_r   : std_logic;
  signal start1_r : std_logic;
  signal start2_r : std_logic;
+ 
+ signal fire1_r   : std_logic;
+ signal fire2_r   : std_logic;
+ signal fire1_mem : std_logic;
+ signal fire2_mem : std_logic;
+ 
 
 begin
-
 pix_ce <= ena_vidgen;
 clock_18n <= not clock_18;
 reset_n   <= not reset;
@@ -298,6 +324,10 @@ dip_switch_b <= "10010111"; --lives:7-6/ bonus:5-3 / coinage:2-0
 dip_switch_do <= 	dip_switch_a(to_integer(unsigned(mux_addr(3 downto 0)))) & 
 									dip_switch_b(to_integer(unsigned(mux_addr(3 downto 0))));
 
+audio <= ("00" & cs54xx_audio_1 &  "0000" ) + ("00" & cs54xx_audio_2 &  "0000" )+ ('0'&snd_audio(9 downto 1));
+--audio <= ("00" & cs54xx_audio_1 &  "00000" ) + ('0'&snd_audio);
+--audio <= ('0'&snd_audio);
+
 -- make access slots from 18MHz
 -- 6MHz for pixel clock and sound machine
 -- 3MHz for cpu, background and sprite machine
@@ -312,14 +342,16 @@ process (clock_18)
 begin
  if rising_edge(clock_18) then
   ena_vidgen      <= '0';
-	ena_snd_machine <= '0';
+  ena_snd_machine <= '0';
   cpu1_ena   <= '0';
   cpu2_ena   <= '0';
   cpu3_ena   <= '0';
+  cs54xx_ena <= '0';
 	
   if slot = "101" then
    slot <= (others => '0');
-	else
+	cs54xx_ena_div <= cs54xx_ena_div +'1';
+  else
 		slot <= std_logic_vector(unsigned(slot) + 1);
   end if;   
 	
@@ -328,6 +360,8 @@ begin
 	if slot = "101" then cpu1_ena <= '1';	end if;
 	if slot = "000" then cpu2_ena <= '1';	end if;	
 	if slot = "001" then cpu3_ena <= '1';	end if;
+	
+	if slot = "000" and cs54xx_ena_div = "000" then cs54xx_ena <= '1'; end if;
 		
  end if;
 end process;
@@ -439,15 +473,15 @@ spflips <= 	"0000000"                       & spflip_V & spflip_2H & spflip_V &
 
 with spdata(3 downto 2) select
 spgraphx_addr <=  (sptile_num(6 downto 0)                             & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when "00",
-									(sptile_num(6 downto 1) & 						sphcnt(4)     & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when "01",
-									(sptile_num(6 downto 2) & spvcnt(4) & sptile_num(0) & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when "10",
-									(sptile_num(6 downto 2) & spvcnt(4) & sphcnt(4)     & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when others;
+						(sptile_num(6 downto 1) & 						sphcnt(4) & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when "01",
+						(sptile_num(6 downto 2) & spvcnt(4) & sptile_num(0) & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when "10",
+						(sptile_num(6 downto 2) & spvcnt(4) & sphcnt(4)     & spvcnt(3) & sphcnt(3 downto 2) & spvcnt(2 downto 0) ) xor spflips when others;
 
 sppalette_addr <= sptile_color(5 downto 0) &
 									spgraphx_do(to_integer(unsigned('1' & ((not sphcnt(1 downto 0)) xor spflip_2H )))) &
 									spgraphx_do(to_integer(unsigned('0' & ((not sphcnt(1 downto 0)) xor spflip_2H )))); 
 
-spbits_wr <= 	sppalette_do;
+spbits_wr <= 	sppalette_do(3 downto 0);
 
 --- BACKGROUND TILES MACHINE ---
 -----------------------_--------
@@ -456,12 +490,12 @@ spbits_wr <= 	sppalette_do;
 -- 0x8400-0x87FF : tile color
 
 bgtile_addr <= 	"10000" & hcnt(1) & vcnt(7 downto 3) & hcnt(7 downto 3)                                when (hcnt(8)='1' and flip_h='0') else
-								"10000" & hcnt(1) & hcnt(4) & hcnt(4) & hcnt(4) & hcnt(4) & hcnt(3) & vcnt(7 downto 3) when (hcnt(8)='0' and flip_h='0') else
-								"10000" & hcnt(1) & not( vcnt(7 downto 3) & hcnt(7 downto 3))                          when (hcnt(8)='1' and flip_h='1') else
-								"10000" & hcnt(1) & not( hcnt(4) & hcnt(4) & hcnt(4) & hcnt(4) & hcnt(3) & vcnt(7 downto 3));
+						"10000" & hcnt(1) & hcnt(4) & hcnt(4) & hcnt(4) & hcnt(4) & hcnt(3) & vcnt(7 downto 3) when (hcnt(8)='0' and flip_h='0') else
+						"10000" & hcnt(1) & not( vcnt(7 downto 3) & hcnt(7 downto 3))                          when (hcnt(8)='1' and flip_h='1') else
+						"10000" & hcnt(1) & not( hcnt(4) & hcnt(4) & hcnt(4) & hcnt(4) & hcnt(3) & vcnt(7 downto 3));
 								
 
--- Attention : slot et hcnt ne sont pas entierement synchronisés
+-- Attention : slot et hcnt ne sont pas entierement synchronisés
 -- slot  |0 |1 | 2 |3 |4 |5 | ...
 -- hcnt  | 0 or 1  | 1 or 2 | ...
 
@@ -488,7 +522,7 @@ bgpalette_addr <= bgtile_color_r(5 downto 0) &
 									bggraphx_do(to_integer(unsigned('1' & (hcnt(1 downto 0)) xor (flip_h & flip_h)))) &
 									bggraphx_do(to_integer(unsigned('0' & (hcnt(1 downto 0)) xor (flip_h & flip_h)))); 
 
-bgbits <= bgpalette_do;
+bgbits <= bgpalette_do(3 downto 0);
 
 --- STARS MACHINE --- 
 ---------------------
@@ -557,7 +591,7 @@ port  map(
 process (clock_18)
 	subtype speed is integer range -3 to 3;
 	type speed_array is array(0 to 7) of speed; 
-	constant speeds : speed_array := ( -1, -2, -3, 0, 3, 2, 1, 0 ); 
+	variable speeds : speed_array := ( -1, -2, -3, 0, 3, 2, 1, 0 ); 
 begin
  if rising_edge(clock_18) then 
 
@@ -591,20 +625,19 @@ end process;
 
 rgb_palette_addr <= ('0' & spbits_rd) when bgbits = "1111" else ('1' & bgbits);
 
-process (clock_18) begin
-	if rising_edge(clock_18) then
-		if ena_vidgen = '1' then
-			if rgb_palette_addr(3 downto 0) = "1111" then
-				video_r <= star_color(1 downto 0) & star_color(1);
-				video_g <= star_color(3 downto 2) & star_color(3);
-				video_b <= star_color(5 downto 4);
-			else
-				video_r <= rgb_palette_do(2 downto 0);
-				video_g <= rgb_palette_do(5 downto 3);
-				video_b <= rgb_palette_do(7 downto 6);
-			end if;
-		end if;
+process (clock_18, rgb_palette_addr)
+begin
+ if rising_edge(clock_18)then
+  if rgb_palette_addr(3 downto 0) = "1111" then
+		video_r <= star_color(1 downto 0) & "0";
+		video_g <= star_color(3 downto 2) & "0";
+		video_b <= star_color(5 downto 4);		
+	else
+		video_r <= rgb_palette_do(2 downto 0);
+		video_g <= rgb_palette_do(5 downto 3);
+		video_b <= rgb_palette_do(7 downto 6);	
 	end if;
+ end if;
 end process;
 
 
@@ -620,7 +653,7 @@ cpu_addr  => mux_addr(3 downto 0),
 cpu_do    => mux_cpu_do(3 downto 0), 
 ram_0_we  => snd_ram_0_we,
 ram_1_we  => snd_ram_1_we,
-audio     => audio
+audio     => snd_audio
 );
 
 --- CPUS -------------
@@ -636,17 +669,17 @@ mux_addr <= 	cpu1_addr   when "000",
 
 with slot select
 mux_cpu_do <= 	cpu1_do when "000",
-								cpu2_do when "001",
-								cpu3_do when "010",
-								X"00"   when others;
+					cpu2_do when "001",
+					cpu3_do when "010",
+					X"00"   when others;
 
 mux_cpu_we <= 	(not cpu1_wr_n and cpu1_ena)or
-								(not cpu2_wr_n and cpu2_ena)or
-								(not cpu3_wr_n and cpu3_ena);
+					(not cpu2_wr_n and cpu2_ena)or
+					(not cpu3_wr_n and cpu3_ena);
 
 mux_cpu_mreq <= 	(not cpu1_mreq_n and cpu1_ena) or
-									(not cpu2_mreq_n and cpu2_ena) or
-									(not cpu3_mreq_n and cpu3_ena);
+						(not cpu2_mreq_n and cpu2_ena) or
+						(not cpu3_mreq_n and cpu3_ena);
 									
 latch_we <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "01101" else '0';
 io_we    <= '1' when mux_cpu_we = '1' and mux_addr(15 downto 11) = "01110" else '0';
@@ -671,8 +704,13 @@ begin
 			cpu2_irq_n  <= '1';
 			cs51XX_coin_mode_cnt <= "000";
 			cs51XX_data_cnt <= "00";
+			cs51XX_switch_mode <= '0';
+			cs51XX_credit_mode <= '1';
 			cs05XX_ctrl <= "000000";
 			flip_h <= '0';
+			cs54xx_irq_n <= '1';
+			cs54xx_irq_cnt <= X"0";
+			
  else 
   if rising_edge(clock_18n) then 
 		if latch_we ='1' and mux_addr(5 downto 4) = "10" then 
@@ -696,10 +734,26 @@ begin
 		elsif vcnt = std_logic_vector(to_unsigned(240,9)) then cpu2_irq_n <= '0';
 		end if;
 		
+		if cs54xx_irq_cnt = X"0" then 
+		  cs54xx_irq_n <= '1';
+		else 
+			if cs54xx_ena = '1' then
+				cs54xx_irq_cnt <= cs54xx_irq_cnt - '1';
+			end if;
+		end if;
+		
 		-- write to cs06XX
 		if io_we = '1' then 
 			-- write to data register (0x7000)
 		  if mux_addr(8) = '0' then
+				-- write data to device#4 (cs54XX)
+				if cs06XX_control(3 downto 0) = "1000" then
+						-- write data for k and r#0 port and launch irq to advice cs50xx
+						cs54xx_k_port_in <= mux_cpu_do(7 downto 4);
+						cs54xx_r0_port_in <= mux_cpu_do(3 downto 0);
+						cs54xx_irq_n <= '0';
+						cs54xx_irq_cnt <= X"7";						
+				end if;		  
 				-- write data to device#1 (cs51XX)
 				if cs06XX_control(3 downto 0) = "0001" then
 					-- when not in coin mode
@@ -745,7 +799,7 @@ begin
 		-- generate periodic nmi when timer is on
 		if cs06XX_nmi_cnt >= 1 then
 			if cpu1_ena = '1' then  -- to get 333ns tick
-				-- 600 * 333ns = 200µs
+				-- 600 * 333ns = 200µs
 				if cs06XX_nmi_cnt < 600 then  
 					cs06XX_nmi_cnt := cs06XX_nmi_cnt + 1;
 					cpu1_nmi_n <= '1';
@@ -763,13 +817,25 @@ begin
 				change_next <= '1';
 			end if;
 		end if ;
-		-- cycle data_cnt at each read
+		-- cycle data_cnt at each read and clear firex_mem in switch mode
 		if change_next = '1' then
 			if cs06XX_control(3 downto 0) = "0001" then
+			
 				if cs51XX_data_cnt = "10" then cs51XX_data_cnt <= "00"; 
 				else cs51XX_data_cnt <= cs51XX_data_cnt + "01"; end if;
+				
+				if cs51XX_data_cnt = "10" then 
+					fire1_mem <= '0';
+					fire2_mem <= '0';
+				end if;
+				
 			end if;				
 		end if;
+		-- manage fire button rising edge detection
+		fire1_r <= fire1;
+		fire2_r <= fire2;
+		if fire1_r ='0' and fire1 ='1' then fire1_mem <= '1'; end if;
+		if fire2_r ='0' and fire2 ='1' then fire2_mem <= '1'; end if;
 		
 		-- manage credit count (bcd)
 		--   increase at each coin up to 99
@@ -787,7 +853,7 @@ begin
 			end if; 
 		end if;
 		
-	  --   decrease only when in credit mode
+	   --   decrease only when in credit mode
 		if cs51XX_credit_mode = '1' then
 			if (start1 = '1' and start1_r = '0') then
 				cs51XX_credit_mode <= '0';
@@ -825,37 +891,35 @@ end process;
 
 with cs51XX_data_cnt select
 cs51XX_switch_mode_do <= 	not (left2 & '0' & right2 & '0' & left1 & '0' & right1 & '0' )       when "00",
-													not (b_test & b_svce & '0' & coin & start2 & start1 & fire2 & fire1) when "01",
-													X"00" when others;	
+									not (b_test & b_svce & '0' & coin & start2 & start1 & fire2_mem & fire1_mem) when "01",
+									X"00" when others;	
 
 with cs51XX_data_cnt select
 cs51XX_non_switch_mode_do <= 	credit_bcd_1 & credit_bcd_0 when "00", -- credits (cpu spy this)
-															not ("110" & fire1 & left1 & '0' & right1 & '0' ) when "01",
-															not ("110" & fire2 & left2 & '0' & right2 & '0' ) when "10",
-															X"00" when "11"; -- N.U.	
+										not ("110" & fire1_mem & left1 & '0' & right1 & '0' ) when "01",
+										not ("110" & fire2_mem & left2 & '0' & right2 & '0' ) when "10",
+										X"00" when "11"; -- N.U.	
 
 cs51XX_do <= cs51XX_switch_mode_do when cs51XX_switch_mode = '1' else cs51XX_non_switch_mode_do;
 
-cs54XX_do <= X"FF"; -- todo (maybe)
+cs54XX_do <= X"FF"; -- no data from CS54XX
 
 with cs06XX_control(3 downto 0) select
 cs06XX_di <= cs51XX_do when "0001",
-						 cs54XX_do when "1000",
-						 X"00" when others;
+				 cs54XX_do when "1000",
+				 X"00" when others;
 
 cs06XX_do <= cs06XX_di when mux_addr(8)= '0' else cs06XX_control;
 
 process (clock_18, nmion_n)
 begin
-	if nmion_n = '1' then
-	elsif rising_edge(clock_18) then
-		if ena_vidgen = '1' then
-			if hcnt = "100000000" then
-				if vcnt = "001000000" or vcnt = "011000000" then cpu3_nmi_n <= '0'; end if;
-				if vcnt = "001000001" or vcnt = "011000001" then cpu3_nmi_n <= '1'; end if;
-			end if;
+ if nmion_n = '1' then
+ elsif rising_edge(clock_18) and ena_vidgen = '1' then
+		if hcnt = "100000000" then
+			if vcnt = "001000000" or vcnt = "011000000" then cpu3_nmi_n <= '0'; end if;
+			if vcnt = "001000001" or vcnt = "011000001" then cpu3_nmi_n <= '1'; end if;
 		end if;
-	end if;
+ end if;
 end process;
 
 with cpu1_addr(15 downto 11) select
@@ -920,7 +984,7 @@ port map(
   INT_n   => cpu1_irq_n,
   NMI_n   => cpu1_nmi_n,
   BUSRQ_n => '1',
-  M1_n    => open,
+  M1_n    => cpu1_m1_n,
   MREQ_n  => cpu1_mreq_n,
   IORQ_n  => open,
   RD_n    => open,
@@ -945,7 +1009,7 @@ port map(
   INT_n   => cpu2_irq_n,
   NMI_n   => '1', --cpu_int_n,
   BUSRQ_n => '1',
-  M1_n    => open,
+  M1_n    => cpu2_m1_n,
   MREQ_n  => cpu2_mreq_n,
   IORQ_n  => open,
   RD_n    => open,
@@ -970,7 +1034,7 @@ port map(
   INT_n   => '1',
   NMI_n   => cpu3_nmi_n,
   BUSRQ_n => '1',
-  M1_n    => open,
+  M1_n    => cpu3_m1_n,
   MREQ_n  => cpu3_mreq_n,
   IORQ_n  => open,
   RD_n    => open,
@@ -983,6 +1047,47 @@ port map(
   DO      => cpu3_do
 );
 
+-- mb88 - cs54xx (28 pins IC, 1024 bytes rom)
+mb88_54xx : entity work.mb88
+port map(
+ reset_n    => reset_cpu_n, --reset_n,
+ clock      => clock_18,
+ ena        => cs54xx_ena,
+
+ r0_port_in  => cs54xx_r0_port_in, -- pin 12,13,15,16
+ r1_port_in  => X"0",
+ r2_port_in  => X"0",
+ r3_port_in  => X"0",
+ r0_port_out => open,
+ r1_port_out => cs54xx_audio_3,   -- pin 17,18,19,20 (resistor divider )
+ r2_port_out => open,
+ r3_port_out => open,
+ k_port_in   => cs54xx_k_port_in, -- pin 24,25,26,27
+ ol_port_out => cs54xx_audio_1,   -- pin  4, 5, 6, 7 (resistor divider 150K/22K)
+ oh_port_out => cs54xx_audio_2,   -- pin  8, 9,10,11 (resistor divider  47K/10K)
+ p_port_out  => open,
+
+ stby_n    => '0',
+ tc_n      => '0',
+ irq_n     => cs54xx_irq_n,
+ sc_in_n   => '0',
+ si_n      => '0',
+ sc_out_n  => open,
+ so_n      => open,
+ to_n      => open,
+ 
+ rom_addr  => cs54xx_rom_addr,
+ rom_data  => cs54xx_rom_do
+);
+
+-- cs54xx program ROM
+cs54xx_prog : entity work.cs54xx_prog
+port map(
+ clk  => clock_18n,
+ addr => cs54xx_rom_addr(9 downto 0),
+ data => cs54xx_rom_do
+);
+
 -- cpu1 program ROM
 rom_cpu1 : entity work.galaga_cpu1
 port map(
@@ -1109,4 +1214,4 @@ port map(
  data => rgb_palette_do
 );
 
-end struct;
+end struct;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu1.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu1.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu1.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu1.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu2.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu2.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu2.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu2.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu3.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu3.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/galaga_cpu3.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_cpu3.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd
index 6e089ceb..0fdbb774 100644
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd	
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd	
@@ -1,37 +1,3 @@
----------------------------------------------------------------------------------
--- Mist FPGA Top level for Galaga Midway by Gehstock. Original DE2 Toplevel by Dar (darfpga@aol.fr) (December 2016)
--- http://darfpga.blogspot.fr
----------------------------------------------------------------------------------
--- Educational use only
--- Do not redistribute synthetized file with roms
--- Do not redistribute roms whatever the form
--- Use at your own risk
----------------------------------------------------------------------------------
---
--- Main features :
---  PS2 keyboard input
---  Joystick input
---  Sigma Delta sound output
---  NO board SRAM/Flash used
---
--- Uses 1 pll for 18MHz, 11MHz and 14khz generation from 27MHz
---
--- Board key :
---      0 : reset
---
--- Keyboard inputs :
---   ESC : Add coin
---   1 : Start 1 player
---   2 : Start 2 players
---   SPACE       : Fire player 1 & 2
---   UP arrow : Move right player 1 & 2
---   DOWN arrow  : Move left player 1 & 2
---
--- Dip switch and other details : see galaga.vhd
-
----------------------------------------------------------------------------------
-
-
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.ALL;
@@ -235,8 +201,8 @@ galaga : entity work.galaga
 		pix_ce       => pix_ce,
 
 		audio        => audio,
-		b_test       => '0', --no Function at all
-		b_svce       => '0', --no Function at all 
+		b_test       => '0',
+		b_svce       => '0',
 		coin         => kbd_joy(3) or status(1),
 		start1       => kbd_joy(1) or status(2),
 		start2       => kbd_joy(2) or status(3), 
@@ -248,9 +214,9 @@ galaga : entity work.galaga
 		fire2        => joy0(4) or joy1(4) or kbd_joy(0)
 );
 
-VGA_R_O <= r        when blankn = '1' else "000";
-VGA_G_O <= g        when blankn = '1' else "000";
-VGA_B_O <= b & b(1) when blankn = '1' else "000";
+VGA_R_O <= r        	when blankn = '1' else "000";
+VGA_G_O <= g        	when blankn = '1' else "000";
+VGA_B_O <= b&b(1) 	when blankn = '1' else "000";
 
 u_dac : entity work.dac
 	port  map(
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd
index e8df4c1a..d4cfda81 100644
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd	
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_machine.vhd	
@@ -38,10 +38,11 @@ architecture struct of sound_machine is
  signal snd_ram_0_do : std_logic_vector(3 downto 0);
  signal snd_ram_1_do : std_logic_vector(3 downto 0);
  
- signal snd_seq_do   : std_logic_vector(3 downto 0);
+ signal snd_seq_addr : std_logic_vector(7 downto 0);
+ signal snd_seq_do   : std_logic_vector(7 downto 0);
 
  signal snd_samples_addr : std_logic_vector(7 downto 0);
- signal snd_samples_do   : std_logic_vector(3 downto 0);
+ signal snd_samples_do   : std_logic_vector(7 downto 0);
  
  signal sum      : std_logic_vector(4 downto 0) := (others => '0');
  signal sum_r    : std_logic_vector(4 downto 0) := (others => '0');
@@ -58,6 +59,8 @@ begin
 
 clock_18n <= not clock_18;
 
+snd_seq_addr <= '0' & not ram_0_we & hcnt(5 downto 0);
+
 snd_ram_addr <= cpu_addr when (ram_0_we = '1' or ram_1_we = '1') else hcnt(5 downto 2);
 snd_ram_di   <= cpu_do   when (ram_0_we = '1' or ram_1_we = '1') else sum_r(3 downto 0);
 
@@ -67,49 +70,38 @@ snd_ram_1_we <= ram_1_we;
 sum <= ('0' & snd_ram_0_do) + ('0' & snd_ram_1_do) + ("0000" & sum_r(4));
 
 process (clock_18)
-	function mul4x4(arg1, arg2: std_logic_vector(3 downto 0)) return std_logic_vector is
-		variable rval: std_logic_vector(9 downto 0);
-	begin
-		rval := "0000000000";
-		if arg2(3) = '1' then rval := rval + (arg1 & "000"); end if;
-		if arg2(2) = '1' then rval := rval + (arg1 & "00"); end if;
-		if arg2(1) = '1' then rval := rval + (arg1 & "0"); end if;
-		if arg2(0) = '1' then rval := rval + arg1; end if;
-		return rval;
-	end mul4x4;
 begin
-	if rising_edge(clock_18) then
-		if ena = '1' then
-			if snd_seq_do(3) = '0' then
-				sum_r <= (others => '0');
-				sum_3_rr <= '0';
-			elsif snd_seq_do(0) = '0' then
-				sum_r <= sum;
-				sum_3_rr <= sum_r(3);
-			end if ;
+ if rising_edge(clock_18) and ena = '1' then
+	if snd_seq_do(3) = '0' then
+		sum_r <= (others => '0');
+		sum_3_rr <= '0';
+	elsif snd_seq_do(0) = '0' then
+		sum_r <= sum;
+		sum_3_rr <= sum_r(3);
+	end if ;
 
-			snd_samples_addr <= snd_ram_0_do(2 downto 0) & sum_r(3 downto 0) & sum_3_rr;
-
-			if snd_seq_do(2) = '0' then
-				if hcnt(5 downto 2) = X"5" then
-					samples_ch0 <= snd_samples_do(3 downto 0);
-					volume_ch0  <= snd_ram_1_do;
-				end if;
-				if hcnt(5 downto 2) = X"A" then
-					samples_ch1 <= snd_samples_do(3 downto 0);
-					volume_ch1  <= snd_ram_1_do;
-				end if;
-				if hcnt(5 downto 2) = X"F" then
-					samples_ch2 <= snd_samples_do(3 downto 0);
-					volume_ch2  <= snd_ram_1_do;
-				end if;
-			end if;
+	snd_samples_addr <= snd_ram_0_do(2 downto 0) & sum_r(3 downto 0) & sum_3_rr;
 	
-			audio <= mul4x4(samples_ch0, volume_ch0) +
-						mul4x4(samples_ch1, volume_ch1) +
-						mul4x4(samples_ch2, volume_ch2);
+	if snd_seq_do(2) = '0' then
+		if hcnt(5 downto 2) = X"5" then
+			samples_ch0 <= snd_samples_do(3 downto 0);
+			volume_ch0  <= snd_ram_1_do;
+		end if;
+		if hcnt(5 downto 2) = X"A" then
+			samples_ch1 <= snd_samples_do(3 downto 0);
+			volume_ch1  <= snd_ram_1_do;
+		end if;
+		if hcnt(5 downto 2) = X"F" then
+			samples_ch2 <= snd_samples_do(3 downto 0);
+			volume_ch2  <= snd_ram_1_do;
 		end if;
 	end if;
+	
+	audio <= ("00" & samples_ch0) * volume_ch0 +
+	         ("00" & samples_ch1) * volume_ch1 +
+				   ("00" & samples_ch2) * volume_ch2;
+	
+ end if;
 end process;
 
 -- sound register RAM0
@@ -146,7 +138,7 @@ port map(
 sound_seq : entity work.sound_seq
 port map(
  clk  => clock_18n,
- addr => not ram_0_we & hcnt(5 downto 0),
+ addr => snd_seq_addr,
  data => snd_seq_do
 );
 
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_samples.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_samples.vhd
new file mode 100644
index 00000000..b1f03df1
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_samples.vhd	
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity sound_samples is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(7 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of sound_samples is
+	type rom is array(0 to  255) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"07",X"09",X"0A",X"0B",X"0C",X"0D",X"0D",X"0E",X"0E",X"0E",X"0D",X"0D",X"0C",X"0B",X"0A",X"09",
+		X"07",X"05",X"04",X"03",X"02",X"01",X"01",X"00",X"00",X"00",X"01",X"01",X"02",X"03",X"04",X"05",
+		X"07",X"09",X"0A",X"0B",X"07",X"0D",X"0D",X"07",X"0E",X"07",X"0D",X"0D",X"07",X"0B",X"0A",X"09",
+		X"07",X"05",X"07",X"03",X"07",X"01",X"07",X"00",X"07",X"00",X"07",X"01",X"07",X"03",X"07",X"05",
+		X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"0B",X"0D",X"0E",X"0D",X"0C",X"0A",X"08",X"08",X"08",X"0A",X"0C",X"0D",X"0E",X"0D",X"0B",X"08",
+		X"04",X"02",X"01",X"02",X"03",X"05",X"07",X"07",X"07",X"05",X"03",X"02",X"01",X"02",X"04",X"07",
+		X"07",X"0A",X"0C",X"0D",X"0E",X"0D",X"0C",X"0A",X"07",X"04",X"02",X"01",X"00",X"01",X"02",X"04",
+		X"07",X"0B",X"0D",X"0E",X"0D",X"0B",X"07",X"03",X"01",X"00",X"01",X"03",X"07",X"0E",X"07",X"00",
+		X"07",X"0E",X"0C",X"09",X"0C",X"0E",X"0A",X"07",X"0C",X"0F",X"0D",X"08",X"0A",X"0B",X"07",X"02",
+		X"08",X"0D",X"09",X"04",X"05",X"07",X"02",X"00",X"03",X"08",X"05",X"01",X"03",X"06",X"03",X"01",
+		X"07",X"08",X"0A",X"0C",X"0E",X"0D",X"0C",X"0C",X"0B",X"0A",X"08",X"07",X"05",X"06",X"07",X"08",
+		X"08",X"09",X"0A",X"0B",X"09",X"08",X"06",X"05",X"04",X"04",X"03",X"02",X"04",X"06",X"08",X"09",
+		X"0A",X"0C",X"0C",X"0A",X"07",X"07",X"08",X"0B",X"0D",X"0E",X"0D",X"0A",X"06",X"05",X"05",X"07",
+		X"09",X"09",X"08",X"04",X"01",X"00",X"01",X"03",X"06",X"07",X"07",X"04",X"02",X"02",X"04",X"07");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_seq.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_seq.vhd
new file mode 100644
index 00000000..ee3785a1
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sound_seq.vhd	
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity sound_seq is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(7 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of sound_seq is
+	type rom is array(0 to  255) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
+		X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
+		X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
+		X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",X"0F",X"0D",X"0F",X"0F",
+		X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",
+		X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",
+		X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",X"07",X"0F",X"0E",X"0D",
+		X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0E",X"0D",X"0F",X"0F",X"0F",X"0B",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sp_graphx.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sp_graphx.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/ROM/sp_graphx.vhd
rename to Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sp_graphx.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sp_palette.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sp_palette.vhd
new file mode 100644
index 00000000..2d6637ce
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/sp_palette.vhd	
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity sp_palette is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(7 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of sp_palette is
+	type rom is array(0 to  255) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"0F",X"08",X"0E",X"02",X"0F",X"05",X"0B",X"0C",X"0F",X"00",X"0B",X"01",X"0F",X"01",X"0B",X"02",
+		X"0F",X"08",X"0D",X"02",X"0F",X"06",X"01",X"04",X"0F",X"09",X"01",X"05",X"0F",X"07",X"0B",X"01",
+		X"0F",X"01",X"06",X"0B",X"0F",X"01",X"0B",X"00",X"0F",X"01",X"02",X"00",X"0F",X"00",X"01",X"06",
+		X"0F",X"00",X"00",X"06",X"0F",X"03",X"0B",X"09",X"0F",X"06",X"02",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/stars.vhd b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/stars.vhd
index ba229cb1..04f46591 100644
--- a/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/stars.vhd	
+++ b/Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/stars.vhd	
@@ -45,7 +45,7 @@ end entity;
 
 architecture stars_table of stars is
 
-type table0 is array(0 to 127) of std_logic_vector(15 downto 0);
+type table0 is array(0 to  119) of std_logic_vector(15 downto 0);
 signal data0 : table0 := (
 X"8006",  -- line 0x06 
 X"3584",  -- one star at 0x84, color is 0x35
@@ -166,18 +166,9 @@ X"80F7",
 X"2B4E",
 X"80FF",
 X"2AFA",
-X"C000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000"
-);
+X"C000");
 
-type table1 is array(0 to  127) of std_logic_vector(15 downto 0);
+type table1 is array(0 to  118) of std_logic_vector(15 downto 0);
 signal data1 : table1 := (
 X"8004",
 X"3DFD",
@@ -297,19 +288,9 @@ X"80FB",
 X"3338",
 X"80FC",
 X"2727",
-X"C000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000"
-);
+X"C000");
 
-type table2 is array(0 to  127) of std_logic_vector(15 downto 0);
+type table2 is array(0 to  122) of std_logic_vector(15 downto 0);
 signal data2 : table2 := (
 X"8006",
 X"19F9",
@@ -433,15 +414,9 @@ X"80F9",
 X"2268",
 X"80FF",
 X"243E",
-X"C000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000"
-);
+X"C000");
 
-type table3 is array(0 to  127) of std_logic_vector(15 downto 0);
+type table3 is array(0 to  122) of std_logic_vector(15 downto 0);
 signal data3 : table3 := (
 X"8010",
 X"3470",
@@ -565,13 +540,7 @@ X"80F9",
 X"1DDD",
 X"80FA",
 X"132B",
-X"C000",
-X"0000",
-X"0000",
-X"0000",
-X"0000",
-X"0000"
-);
+X"C000");
 
 begin
 process(clk)