diff --git a/Sharp - MZ-80K_MiST/Release/mz80k_mist.rbf b/Sharp - MZ-80K_MiST/Release/mz80k_mist.rbf index 68fe4d8b..2e164658 100644 Binary files a/Sharp - MZ-80K_MiST/Release/mz80k_mist.rbf and b/Sharp - MZ-80K_MiST/Release/mz80k_mist.rbf differ diff --git a/Sharp - MZ-80K_MiST/clean.bat b/Sharp - MZ-80K_MiST/clean.bat index 78fefc16..33f055f1 100644 --- a/Sharp - MZ-80K_MiST/clean.bat +++ b/Sharp - MZ-80K_MiST/clean.bat @@ -1,4 +1,5 @@ @echo off +del /s PLLJ_PLLSPE_INFO.txt del /s *.bak del /s *.orig del /s *.rej diff --git a/Sharp - MZ-80K_MiST/mz80k_mist.qsf b/Sharp - MZ-80K_MiST/mz80k_mist.qsf index da78897d..64d627a2 100644 --- a/Sharp - MZ-80K_MiST/mz80k_mist.qsf +++ b/Sharp - MZ-80K_MiST/mz80k_mist.qsf @@ -207,10 +207,13 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(mz80k_mist) -# ---------------------- \ No newline at end of file +# ---------------------- +set_global_assignment -name VHDL_FILE rtl/spram.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Color_Card.sv +set_global_assignment -name VHDL_FILE rtl/CPLD_74LS245.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Sharp - MZ-80K_MiST/rtl/CPLD_74LS245.vhd b/Sharp - MZ-80K_MiST/rtl/CPLD_74LS245.vhd new file mode 100644 index 00000000..01dd9083 --- /dev/null +++ b/Sharp - MZ-80K_MiST/rtl/CPLD_74LS245.vhd @@ -0,0 +1,26 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity CPLD_74LS245 is + Port ( nE : in STD_LOGIC; + dir : in STD_LOGIC; + Bin : in STD_LOGIC_VECTOR (7 downto 0); + Ain : in STD_LOGIC_VECTOR (7 downto 0); + Bout :out STD_LOGIC_VECTOR (7 downto 0); + Aout : out STD_LOGIC_VECTOR (7 downto 0)); +end CPLD_74LS245; + +architecture Behavioral of CPLD_74LS245 is +begin + + -- if nE = 1 or dir = '1' then HighZ + -- else B + Aout <= (7 downto 0 => 'Z') when nE = '1' OR dir = '1' else Bin; + + -- if nE = 1 or dir = '1' then HighZ + -- wlse A + Bout <= (7 downto 0 => 'Z') when nE = '1' OR dir = '0' else Ain; + +end Behavioral; \ No newline at end of file diff --git a/Sharp - MZ-80K_MiST/rtl/Color_Card.sv b/Sharp - MZ-80K_MiST/rtl/Color_Card.sv new file mode 100644 index 00000000..7efb67d4 --- /dev/null +++ b/Sharp - MZ-80K_MiST/rtl/Color_Card.sv @@ -0,0 +1,59 @@ +module Color_Card( +input CLK, +input CSX_n, +input WR_n, +input CSD_n, +input Sync, +input RD_n, +input Video, +input [7:0] Din, +input [7:0] Dout, +input [9:0] Addr, +output CSDo, +output Synco_n, +output [1:0] R, +output [1:0] G, +output [1:0] B +); + +assign Synco_n = ~Sync; +assign CSDo = CSX_n & CSD_n; +assign R = {Bout[7], Bout[1]}; +assign G = {Bout[6], Bout[2]}; +assign B = {Bout[5], Bout[3]}; + +wire [7:0] Ain, Bin, Aout, Bout; +CPLD_74LS245 IC2 ( + .nE(CSX_n), + .dir(RD_n), + .Bin(Bin), + .Ain(Din), + .Bout(Bout), + .Aout(Dout), + ); + +spram #( + .addr_width_g(10), + .data_width_g(4)) +IC1 ( + .clk_i(CLK), + .we_i(~CSX_n | ~WR_n), + .addr_i(Addr), + .data_i({Bout[0],Bout[1],Bout[2],Bout[3]}), + .data_o({Bin[0],Bin[1],Bin[2],Bin[3]}), + ); + +spram #( + .addr_width_g(10), + .data_width_g(4)) +IC3 ( + .clk_i(CLK), + .we_i(~CSX_n | ~WR_n), + .addr_i(Addr), + .data_i({Bout[4],Bout[5],Bout[6],Bout[7]}), + .data_o({Bin[4],Bin[5],Bin[6],Bin[7]}), + ); + + + +endmodule \ No newline at end of file diff --git a/Sharp - MZ-80K_MiST/rtl/build_id.v b/Sharp - MZ-80K_MiST/rtl/build_id.v index 7da6cc7b..a2379c62 100644 --- a/Sharp - MZ-80K_MiST/rtl/build_id.v +++ b/Sharp - MZ-80K_MiST/rtl/build_id.v @@ -1,2 +1,2 @@ `define BUILD_DATE "180929" -`define BUILD_TIME "130303" +`define BUILD_TIME "144420" diff --git a/Sharp - MZ-80K_MiST/rtl/mz80k_mist.sv b/Sharp - MZ-80K_MiST/rtl/mz80k_mist.sv index 3fdf77ec..1355c3ac 100644 --- a/Sharp - MZ-80K_MiST/rtl/mz80k_mist.sv +++ b/Sharp - MZ-80K_MiST/rtl/mz80k_mist.sv @@ -32,15 +32,15 @@ module mz80k_mist( assign LED = 1; localparam CONF_STR = { "Sharp MZ80K;MZF;", - // "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", "O2,CPU Clock, 3Mhz, 6Mhz;", + "O34,Screen, Gray, Green, Color;", "T5,Reset;", - "V,v0.2.",`BUILD_DATE + "V,v0.4.",`BUILD_DATE }; wire clk_sys; -wire clk_12p5; +wire clk_25, clk_12p5, clk_6p25; wire locked; wire scandoubler_disable; wire ypbpr; @@ -49,14 +49,16 @@ wire [31:0] status; wire [1:0] buttons; wire [1:0] switches; wire audio; -wire r, g, b; +wire [1:0] r, g, b; wire hs, vs; wire [7:0] kb_ext; pll pll( .areset(), .inclk0(CLOCK_27), .c0(clk_sys),//50.0Mhz - .c1(clk_12p5),//12.5Mhz + .c1(clk_25),//25.0Mhz + .c2(clk_12p5),//12.5Mhz + .c3(clk_6p25),//6.25Mhz .locked(locked) ); @@ -73,7 +75,7 @@ wire reset = (reset_cnt != 8'd255); mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io ( .conf_str(CONF_STR), - .clk_sys(clk_sys), + .clk_sys(clk_25), .SPI_SCK(SPI_SCK), .CONF_DATA0(CONF_DATA0), .SPI_SS2(SPI_SS2), @@ -89,15 +91,13 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer ( - .clk_sys(clk_sys), - .ce_pix(clk_12p5), - .ce_pix_actual(clk_12p5), + .clk_sys(clk_25), + .ce_pix(clk_6p25), + .ce_pix_actual(clk_6p25), .SPI_SCK(SPI_SCK), .SPI_SS3(SPI_SS3), .SPI_DI(SPI_DI), - .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), .scandoubler_disable(1),//scandoubler_disable), - .hq2x(status[4:3]==1), .ypbpr(ypbpr), .ypbpr_full(1), .R({r,r,r}), @@ -118,7 +118,7 @@ sigma_delta_dac #(.MSBI(2)) sigma_delta_dac ( .DACout(AUDIO_L), .DACin({audio,audio,audio}), - .CLK(clk_sys), + .CLK(clk_25), .RESET(0) ); @@ -127,6 +127,7 @@ assign AUDIO_R = AUDIO_L; mz80k_top mz80k_top( .CLK_50MHZ(clk_sys), .RESET(reset), + .color(status[4:3]), .PS2_KEY(PS2_KEY), .VGA_RED(r), .VGA_GREEN(g), diff --git a/Sharp - MZ-80K_MiST/rtl/mz80k_top.v b/Sharp - MZ-80K_MiST/rtl/mz80k_top.v index 88686f8b..fed2cf9a 100644 --- a/Sharp - MZ-80K_MiST/rtl/mz80k_top.v +++ b/Sharp - MZ-80K_MiST/rtl/mz80k_top.v @@ -3,6 +3,7 @@ module mz80k_top( input CLK_50MHZ, input RESET, input [10:0] PS2_KEY, + input [1:0] color, output VGA_RED, output VGA_GREEN, output VGA_BLUE, @@ -149,7 +150,10 @@ keymatrix keymatrix( // VGA wire [11:0] vga_addr; vga vga1( - .CLK_50MHZ(CLK_50MHZ), + .CLK_50MHZ(CLK_50MHZ), + .color(color), + .RD_n(~rd), + .WR_n(~wr), .VGA_RED(VGA_RED), .VGA_GREEN(VGA_GREEN), .VGA_BLUE(VGA_BLUE), diff --git a/Sharp - MZ-80K_MiST/rtl/nu/monrom.v b/Sharp - MZ-80K_MiST/rtl/nu/monrom.v deleted file mode 100644 index 033cadbd..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/monrom.v +++ /dev/null @@ -1,110 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file monrom.v when simulating -// the core, monrom. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module monrom( - addr, - clk, - din, - dout, - en, - we); - - -input [15 : 0] addr; -input clk; -input [7 : 0] din; -output [7 : 0] dout; -input en; -input we; - -// synthesis translate_off - - BLKMEMSP_V6_2 #( - .c_addr_width(16), - .c_default_data("0"), - .c_depth(36864), - .c_enable_rlocs(0), - .c_has_default_data(0), - .c_has_din(1), - .c_has_en(1), - .c_has_limit_data_pitch(0), - .c_has_nd(0), - .c_has_rdy(0), - .c_has_rfd(0), - .c_has_sinit(0), - .c_has_we(1), - .c_limit_data_pitch(18), - .c_mem_init_file("monrom.mif"), - .c_pipe_stages(0), - .c_reg_inputs(0), - .c_sinit_value("0"), - .c_width(8), - .c_write_mode(0), - .c_ybottom_addr("0"), - .c_yclk_is_rising(1), - .c_yen_is_high(1), - .c_yhierarchy("hierarchy1"), - .c_ymake_bmm(0), - .c_yprimitive_type("16kx1"), - .c_ysinit_is_high(1), - .c_ytop_addr("1024"), - .c_yuse_single_primitive(0), - .c_ywe_is_high(1), - .c_yydisable_warnings(1)) - inst ( - .ADDR(addr), - .CLK(clk), - .DIN(din), - .DOUT(dout), - .EN(en), - .WE(we), - .ND(), - .RFD(), - .RDY(), - .SINIT()); - - -// synthesis translate_on - -// XST black box declaration -// box_type "black_box" -// synthesis attribute box_type of monrom is "black_box" - -endmodule - diff --git a/Sharp - MZ-80K_MiST/rtl/nu/monrom.vhd b/Sharp - MZ-80K_MiST/rtl/nu/monrom.vhd deleted file mode 100644 index cfaad054..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/monrom.vhd +++ /dev/null @@ -1,113 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file monrom.vhd when simulating --- the core, monrom. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synthesis translate_off -Library XilinxCoreLib; --- synthesis translate_on -ENTITY monrom IS - port ( - addr: IN std_logic_VECTOR(15 downto 0); - clk: IN std_logic; - din: IN std_logic_VECTOR(7 downto 0); - dout: OUT std_logic_VECTOR(7 downto 0); - en: IN std_logic; - we: IN std_logic); -END monrom; - -ARCHITECTURE monrom_a OF monrom IS --- synthesis translate_off -component wrapped_monrom - port ( - addr: IN std_logic_VECTOR(15 downto 0); - clk: IN std_logic; - din: IN std_logic_VECTOR(7 downto 0); - dout: OUT std_logic_VECTOR(7 downto 0); - en: IN std_logic; - we: IN std_logic); -end component; - --- Configuration specification - for all : wrapped_monrom use entity XilinxCoreLib.blkmemsp_v6_2(behavioral) - generic map( - c_sinit_value => "0", - c_has_en => 1, - c_reg_inputs => 0, - c_yclk_is_rising => 1, - c_ysinit_is_high => 1, - c_ywe_is_high => 1, - c_yprimitive_type => "16kx1", - c_ytop_addr => "1024", - c_yhierarchy => "hierarchy1", - c_has_limit_data_pitch => 0, - c_has_rdy => 0, - c_write_mode => 0, - c_width => 8, - c_yuse_single_primitive => 0, - c_has_nd => 0, - c_has_we => 1, - c_enable_rlocs => 0, - c_has_rfd => 0, - c_has_din => 1, - c_ybottom_addr => "0", - c_pipe_stages => 0, - c_yen_is_high => 1, - c_depth => 36864, - c_has_default_data => 0, - c_limit_data_pitch => 18, - c_has_sinit => 0, - c_mem_init_file => "monrom.mif", - c_yydisable_warnings => 1, - c_default_data => "0", - c_ymake_bmm => 0, - c_addr_width => 16); --- synthesis translate_on -BEGIN --- synthesis translate_off -U0 : wrapped_monrom - port map ( - addr => addr, - clk => clk, - din => din, - dout => dout, - en => en, - we => we); --- synthesis translate_on - -END monrom_a; - diff --git a/Sharp - MZ-80K_MiST/rtl/nu/monrom.xco b/Sharp - MZ-80K_MiST/rtl/nu/monrom.xco deleted file mode 100644 index 908ee347..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/monrom.xco +++ /dev/null @@ -1,64 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version J.40 -# Date: Mon Feb 25 18:49:53 2008 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = VHDL -SET device = xc3s500e -SET devicefamily = spartan3e -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg320 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = True -SET vhdlsim = True -# END Project Options -# BEGIN Select -SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 -# END Select -# BEGIN Parameters -CSET active_clock_edge=Rising_Edge_Triggered -CSET additional_output_pipe_stages=0 -CSET coefficient_file=C:\FPGA\mycom\mz-sp5030.coe -CSET component_name=monrom -CSET depth=36864 -CSET disable_warning_messages=true -CSET enable_pin=true -CSET enable_pin_polarity=Active_High -CSET global_init_value=0 -CSET handshaking_pins=false -CSET has_limit_data_pitch=false -CSET init_pin=false -CSET init_value=0 -CSET initialization_pin_polarity=Active_High -CSET limit_data_pitch=18 -CSET load_init_file=true -CSET port_configuration=Read_And_Write -CSET primitive_selection=Optimize_For_Area -CSET register_inputs=false -CSET select_primitive=16kx1 -CSET width=8 -CSET write_enable_polarity=Active_High -CSET write_mode=Read_After_Write -# END Parameters -GENERATE -# CRC: 71eb081a - diff --git a/Sharp - MZ-80K_MiST/rtl/nu/mycom_bench.v b/Sharp - MZ-80K_MiST/rtl/nu/mycom_bench.v deleted file mode 100644 index a3ab4fa8..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/mycom_bench.v +++ /dev/null @@ -1,32 +0,0 @@ -`timescale 1ns/1ns -module mycom_bench; - reg CLK_50MHZ; - reg BTN_NORTH,BTN_EAST,BTN_SOUTH,BTN_WEST; - reg [3:0] SW; - wire [7:0] LED; - wire VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC; - reg PS2_CLK, PS2_DATA; - wire TP1; - - mycom mycom_1(CLK_50MHZ, BTN_NORTH,BTN_EAST,BTN_SOUTH,BTN_WEST, - VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC, - PS2_CLK, PS2_DATA, - SW, LED, TP1); - - initial begin - CLK_50MHZ <= 0; - BTN_NORTH <= 1; - BTN_EAST <= 0; - BTN_SOUTH <= 0; - BTN_WEST <= 0; - PS2_CLK <= 0; - PS2_DATA <= 0; - SW <= 5; - #400000 - $finish; - end - - always #1 begin - CLK_50MHZ <= ~CLK_50MHZ; - end -endmodule diff --git a/Sharp - MZ-80K_MiST/rtl/nu/ram2.v b/Sharp - MZ-80K_MiST/rtl/nu/ram2.v deleted file mode 100644 index c5cd0367..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/ram2.v +++ /dev/null @@ -1,110 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file ram2.v when simulating -// the core, ram2. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module ram2( - addr, - clk, - din, - dout, - en, - we); - - -input [10 : 0] addr; -input clk; -input [7 : 0] din; -output [7 : 0] dout; -input en; -input we; - -// synthesis translate_off - - BLKMEMSP_V6_2 #( - .c_addr_width(11), - .c_default_data("0"), - .c_depth(2048), - .c_enable_rlocs(0), - .c_has_default_data(1), - .c_has_din(1), - .c_has_en(1), - .c_has_limit_data_pitch(0), - .c_has_nd(0), - .c_has_rdy(0), - .c_has_rfd(0), - .c_has_sinit(0), - .c_has_we(1), - .c_limit_data_pitch(18), - .c_mem_init_file("mif_file_16_1"), - .c_pipe_stages(0), - .c_reg_inputs(0), - .c_sinit_value("0"), - .c_width(8), - .c_write_mode(0), - .c_ybottom_addr("0"), - .c_yclk_is_rising(1), - .c_yen_is_high(1), - .c_yhierarchy("hierarchy1"), - .c_ymake_bmm(0), - .c_yprimitive_type("16kx1"), - .c_ysinit_is_high(1), - .c_ytop_addr("1024"), - .c_yuse_single_primitive(0), - .c_ywe_is_high(1), - .c_yydisable_warnings(1)) - inst ( - .ADDR(addr), - .CLK(clk), - .DIN(din), - .DOUT(dout), - .EN(en), - .WE(we), - .ND(), - .RFD(), - .RDY(), - .SINIT()); - - -// synthesis translate_on - -// XST black box declaration -// box_type "black_box" -// synthesis attribute box_type of ram2 is "black_box" - -endmodule - diff --git a/Sharp - MZ-80K_MiST/rtl/nu/ram2.vhd b/Sharp - MZ-80K_MiST/rtl/nu/ram2.vhd deleted file mode 100644 index ae14fb79..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/ram2.vhd +++ /dev/null @@ -1,113 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file ram2.vhd when simulating --- the core, ram2. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synthesis translate_off -Library XilinxCoreLib; --- synthesis translate_on -ENTITY ram2 IS - port ( - addr: IN std_logic_VECTOR(10 downto 0); - clk: IN std_logic; - din: IN std_logic_VECTOR(7 downto 0); - dout: OUT std_logic_VECTOR(7 downto 0); - en: IN std_logic; - we: IN std_logic); -END ram2; - -ARCHITECTURE ram2_a OF ram2 IS --- synthesis translate_off -component wrapped_ram2 - port ( - addr: IN std_logic_VECTOR(10 downto 0); - clk: IN std_logic; - din: IN std_logic_VECTOR(7 downto 0); - dout: OUT std_logic_VECTOR(7 downto 0); - en: IN std_logic; - we: IN std_logic); -end component; - --- Configuration specification - for all : wrapped_ram2 use entity XilinxCoreLib.blkmemsp_v6_2(behavioral) - generic map( - c_sinit_value => "0", - c_has_en => 1, - c_reg_inputs => 0, - c_yclk_is_rising => 1, - c_ysinit_is_high => 1, - c_ywe_is_high => 1, - c_yprimitive_type => "16kx1", - c_ytop_addr => "1024", - c_yhierarchy => "hierarchy1", - c_has_limit_data_pitch => 0, - c_has_rdy => 0, - c_write_mode => 0, - c_width => 8, - c_yuse_single_primitive => 0, - c_has_nd => 0, - c_has_we => 1, - c_enable_rlocs => 0, - c_has_rfd => 0, - c_has_din => 1, - c_ybottom_addr => "0", - c_pipe_stages => 0, - c_yen_is_high => 1, - c_depth => 2048, - c_has_default_data => 1, - c_limit_data_pitch => 18, - c_has_sinit => 0, - c_yydisable_warnings => 1, - c_mem_init_file => "mif_file_16_1", - c_default_data => "0", - c_ymake_bmm => 0, - c_addr_width => 11); --- synthesis translate_on -BEGIN --- synthesis translate_off -U0 : wrapped_ram2 - port map ( - addr => addr, - clk => clk, - din => din, - dout => dout, - en => en, - we => we); --- synthesis translate_on - -END ram2_a; - diff --git a/Sharp - MZ-80K_MiST/rtl/nu/ram2.xco b/Sharp - MZ-80K_MiST/rtl/nu/ram2.xco deleted file mode 100644 index 3e011199..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/ram2.xco +++ /dev/null @@ -1,63 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version J.40 -# Date: Sun Feb 24 16:19:11 2008 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = VHDL -SET device = xc3s500e -SET devicefamily = spartan3e -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg320 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = True -SET vhdlsim = True -# END Project Options -# BEGIN Select -SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 -# END Select -# BEGIN Parameters -CSET active_clock_edge=Rising_Edge_Triggered -CSET additional_output_pipe_stages=0 -CSET component_name=ram2 -CSET depth=2048 -CSET disable_warning_messages=true -CSET enable_pin=true -CSET enable_pin_polarity=Active_High -CSET global_init_value=0 -CSET handshaking_pins=false -CSET has_limit_data_pitch=false -CSET init_pin=false -CSET init_value=0 -CSET initialization_pin_polarity=Active_High -CSET limit_data_pitch=18 -CSET load_init_file=false -CSET port_configuration=Read_And_Write -CSET primitive_selection=Optimize_For_Area -CSET register_inputs=false -CSET select_primitive=16kx1 -CSET width=8 -CSET write_enable_polarity=Active_High -CSET write_mode=Read_After_Write -# END Parameters -GENERATE -# CRC: 2b8d682f - diff --git a/Sharp - MZ-80K_MiST/rtl/nu/rom.v b/Sharp - MZ-80K_MiST/rtl/nu/rom.v deleted file mode 100644 index 567927e6..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/rom.v +++ /dev/null @@ -1,21 +0,0 @@ -module rom(clk, addr, data); - input clk; - input [10:0] addr; - output [7:0] data; - reg [7:0] data; - always @(posedge clk) begin - case (addr) - 11'h000: data = 8'h21; - 11'h001: data = 8'h00; - 11'h002: data = 8'hd0; - 11'h003: data = 8'h3e; - 11'h004: data = 8'h00; - 11'h005: data = 8'h77; - 11'h006: data = 8'h23; - 11'h007: data = 8'h3c; - 11'h008: data = 8'h18; - 11'h009: data = 8'hfb; - default: data = 8'hXX; - endcase - end -endmodule \ No newline at end of file diff --git a/Sharp - MZ-80K_MiST/rtl/nu/rom_2k.v b/Sharp - MZ-80K_MiST/rtl/nu/rom_2k.v deleted file mode 100644 index f3a91ecd..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/rom_2k.v +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2007 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synthesis directives "translate_off/translate_on" specified below are -// supported by Xilinx, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file rom_2k.v when simulating -// the core, rom_2k. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module rom_2k( - addr, - clk, - dout, - en); - - -input [10 : 0] addr; -input clk; -output [7 : 0] dout; -input en; - -// synthesis translate_off - - BLKMEMSP_V6_2 #( - .c_addr_width(11), - .c_default_data("0"), - .c_depth(2048), - .c_enable_rlocs(0), - .c_has_default_data(0), - .c_has_din(0), - .c_has_en(1), - .c_has_limit_data_pitch(0), - .c_has_nd(0), - .c_has_rdy(0), - .c_has_rfd(0), - .c_has_sinit(0), - .c_has_we(0), - .c_limit_data_pitch(18), - .c_mem_init_file("rom_2k.mif"), - .c_pipe_stages(0), - .c_reg_inputs(0), - .c_sinit_value("0"), - .c_width(8), - .c_write_mode(0), - .c_ybottom_addr("0"), - .c_yclk_is_rising(1), - .c_yen_is_high(1), - .c_yhierarchy("hierarchy1"), - .c_ymake_bmm(0), - .c_yprimitive_type("16kx1"), - .c_ysinit_is_high(1), - .c_ytop_addr("1024"), - .c_yuse_single_primitive(0), - .c_ywe_is_high(1), - .c_yydisable_warnings(1)) - inst ( - .ADDR(addr), - .CLK(clk), - .DOUT(dout), - .EN(en), - .DIN(), - .ND(), - .RFD(), - .RDY(), - .SINIT(), - .WE()); - - -// synthesis translate_on - -// XST black box declaration -// box_type "black_box" -// synthesis attribute box_type of rom_2k is "black_box" - -endmodule - diff --git a/Sharp - MZ-80K_MiST/rtl/nu/rom_2k.vhd b/Sharp - MZ-80K_MiST/rtl/nu/rom_2k.vhd deleted file mode 100644 index f292dfea..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/rom_2k.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- --- This file is owned and controlled by Xilinx and must be used -- --- solely for design, simulation, implementation and creation of -- --- design files limited to Xilinx devices or technologies. Use -- --- with non-Xilinx devices or technologies is expressly prohibited -- --- and immediately terminates your license. -- --- -- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- --- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- --- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- --- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- --- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- --- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- --- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- --- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- --- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- --- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- --- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- --- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- --- FOR A PARTICULAR PURPOSE. -- --- -- --- Xilinx products are not intended for use in life support -- --- appliances, devices, or systems. Use in such applications are -- --- expressly prohibited. -- --- -- --- (c) Copyright 1995-2007 Xilinx, Inc. -- --- All rights reserved. -- --------------------------------------------------------------------------------- --- You must compile the wrapper file rom_2k.vhd when simulating --- the core, rom_2k. When compiling the wrapper file, be sure to --- reference the XilinxCoreLib VHDL simulation library. For detailed --- instructions, please refer to the "CORE Generator Help". - --- The synthesis directives "translate_off/translate_on" specified --- below are supported by Xilinx, Mentor Graphics and Synplicity --- synthesis tools. Ensure they are correct for your synthesis tool(s). - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; --- synthesis translate_off -Library XilinxCoreLib; --- synthesis translate_on -ENTITY rom_2k IS - port ( - addr: IN std_logic_VECTOR(10 downto 0); - clk: IN std_logic; - dout: OUT std_logic_VECTOR(7 downto 0); - en: IN std_logic); -END rom_2k; - -ARCHITECTURE rom_2k_a OF rom_2k IS --- synthesis translate_off -component wrapped_rom_2k - port ( - addr: IN std_logic_VECTOR(10 downto 0); - clk: IN std_logic; - dout: OUT std_logic_VECTOR(7 downto 0); - en: IN std_logic); -end component; - --- Configuration specification - for all : wrapped_rom_2k use entity XilinxCoreLib.blkmemsp_v6_2(behavioral) - generic map( - c_sinit_value => "0", - c_has_en => 1, - c_reg_inputs => 0, - c_yclk_is_rising => 1, - c_ysinit_is_high => 1, - c_ywe_is_high => 1, - c_yprimitive_type => "16kx1", - c_ytop_addr => "1024", - c_yhierarchy => "hierarchy1", - c_has_limit_data_pitch => 0, - c_has_rdy => 0, - c_write_mode => 0, - c_width => 8, - c_yuse_single_primitive => 0, - c_has_nd => 0, - c_has_we => 0, - c_enable_rlocs => 0, - c_has_rfd => 0, - c_has_din => 0, - c_ybottom_addr => "0", - c_pipe_stages => 0, - c_yen_is_high => 1, - c_depth => 2048, - c_has_default_data => 0, - c_limit_data_pitch => 18, - c_has_sinit => 0, - c_mem_init_file => "rom_2k.mif", - c_yydisable_warnings => 1, - c_default_data => "0", - c_ymake_bmm => 0, - c_addr_width => 11); --- synthesis translate_on -BEGIN --- synthesis translate_off -U0 : wrapped_rom_2k - port map ( - addr => addr, - clk => clk, - dout => dout, - en => en); --- synthesis translate_on - -END rom_2k_a; - diff --git a/Sharp - MZ-80K_MiST/rtl/nu/rom_2k.xco b/Sharp - MZ-80K_MiST/rtl/nu/rom_2k.xco deleted file mode 100644 index c13dca24..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/rom_2k.xco +++ /dev/null @@ -1,64 +0,0 @@ -############################################################## -# -# Xilinx Core Generator version J.40 -# Date: Fri Feb 22 02:27:21 2008 -# -############################################################## -# -# This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended -# that you do not manually alter this file as it may cause -# unexpected and unsupported behavior. -# -############################################################## -# -# BEGIN Project Options -SET addpads = False -SET asysymbol = True -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False -SET designentry = VHDL -SET device = xc3s500e -SET devicefamily = spartan3e -SET flowvendor = Foundation_iSE -SET formalverification = False -SET foundationsym = False -SET implementationfiletype = Ngc -SET package = fg320 -SET removerpms = False -SET simulationfiles = Behavioral -SET speedgrade = -4 -SET verilogsim = True -SET vhdlsim = True -# END Project Options -# BEGIN Select -SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 -# END Select -# BEGIN Parameters -CSET active_clock_edge=Rising_Edge_Triggered -CSET additional_output_pipe_stages=0 -CSET coefficient_file=C:\FPGA\mycom\cg_rom.coe -CSET component_name=rom_2k -CSET depth=2048 -CSET disable_warning_messages=true -CSET enable_pin=true -CSET enable_pin_polarity=Active_High -CSET global_init_value=0 -CSET handshaking_pins=false -CSET has_limit_data_pitch=false -CSET init_pin=false -CSET init_value=0 -CSET initialization_pin_polarity=Active_High -CSET limit_data_pitch=18 -CSET load_init_file=true -CSET port_configuration=Read_Only -CSET primitive_selection=Optimize_For_Area -CSET register_inputs=false -CSET select_primitive=16kx1 -CSET width=8 -CSET write_enable_polarity=Active_High -CSET write_mode=Read_After_Write -# END Parameters -GENERATE -# CRC: e5516405 - diff --git a/Sharp - MZ-80K_MiST/rtl/nu/spartan3e.ucf b/Sharp - MZ-80K_MiST/rtl/nu/spartan3e.ucf deleted file mode 100644 index a0c87e43..00000000 --- a/Sharp - MZ-80K_MiST/rtl/nu/spartan3e.ucf +++ /dev/null @@ -1,276 +0,0 @@ -##################################################### -### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE -##################################################### -# ==== Analog-to-Digital Converter (ADC) ==== -# some connections shared with SPI Flash, DAC, ADC, and AMP -NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; -# ==== Programmable Gain Amplifier (AMP) ==== -# some connections shared with SPI Flash, DAC, ADC, and AMP -NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; -NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ; -NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; -# ==== Pushbuttons (BTN) ==== -NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; -NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ; -NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; -NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; -# ==== Clock inputs (CLK) ==== -NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ; -# Define clock period for 50 MHz oscillator (40%/60% duty-cycle) -#NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%; -NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ; -NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ; -# ==== Digital-to-Analog Converter (DAC) ==== -# some connections shared with SPI Flash, DAC, ADC, and AMP -NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -# ==== 1-Wire Secure EEPROM (DS) -NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -# ==== Ethernet PHY (E) ==== -NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ; -NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ; -NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ; -NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ; -NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ; -NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ; -NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ; -NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ; -NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ; -NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ; -NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ==== -NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; -NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; -NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ; -# ==== FX2 Connector (FX2) ==== -NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ; -NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -# These four connections are shared with the J1 6-pin accessory header -NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -# These four connections are shared with the J2 6-pin accessory header -NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -# These four connections are shared with the J4 6-pin accessory header -NET "TP1" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -# The discrete LEDs are shared with the following 8 FX2 connections -#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; -# ==== 6-pin header J1 ==== -# These are shared connections with the FX2 connector -#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -# ==== 6-pin header J2 ==== -# These are shared connections with the FX2 connector -#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -# ==== 6-pin header J4 ==== -# These are shared connections with the FX2 connector -#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; -# ==== Character LCD (LCD) ==== -NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -# LCD data connections are shared with StrataFlash connections SF_D<11:8> -#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -# ==== Discrete LEDs (LED) ==== -# These are shared connections with the FX2 connector -NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; -# ==== PS/2 Mouse/Keyboard Port (PS2) ==== -NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; -NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; -# ==== Rotary Pushbutton Switch (ROT) ==== -NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ; -NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ; -NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ; -# ==== RS-232 Serial Ports (RS232) ==== -NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ; -NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; -NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ; -NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; -# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V) -NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ; -NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ; -NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ; -NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ; -NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ; -NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ; -NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ; -NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ; -NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ; -NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ; -NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ; -NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ; -NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ; -NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ; -NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ; -NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ; -NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ; -NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ; -NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ; -NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ; -NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ; -NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ; -NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ; -NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ; -NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ; -NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ; -NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ; -# Path to allow connection to top DCM connection -NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ; -# Prohibit VREF pins -CONFIG PROHIBIT = D2; -CONFIG PROHIBIT = G4; -CONFIG PROHIBIT = J6; -CONFIG PROHIBIT = L5; -CONFIG PROHIBIT = R4; -# ==== Intel StrataFlash Parallel NOR Flash (SF) ==== -NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ; -NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -# ==== STMicro SPI serial Flash (SPI) ==== -# some connections shared with SPI Flash, DAC, ADC, and AMP -NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; -NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; -NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; -NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; -NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; -# ==== Slide Switches (SW) ==== -NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; -NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; -NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; -NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; -# ==== VGA Port (VGA) ==== -NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; -NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; -NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; -NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; -NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; -# ==== Xilinx CPLD (XC) ==== -NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; -NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; -NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ; -NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; -NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; -NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; -NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ; -NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; -NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; \ No newline at end of file diff --git a/Sharp - MZ-80K_MiST/rtl/pll.v b/Sharp - MZ-80K_MiST/rtl/pll.v index 6bb0861c..672bc223 100644 --- a/Sharp - MZ-80K_MiST/rtl/pll.v +++ b/Sharp - MZ-80K_MiST/rtl/pll.v @@ -14,11 +14,11 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version // ************************************************************ -//Copyright (C) 1991-2014 Altera Corporation +//Copyright (C) 1991-2013 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing @@ -41,12 +41,16 @@ module pll ( inclk0, c0, c1, + c2, + c3, locked); input areset; input inclk0; output c0; output c1; + output c2; + output c3; output locked; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off @@ -57,21 +61,25 @@ module pll ( `endif wire [4:0] sub_wire0; - wire sub_wire2; - wire [0:0] sub_wire6 = 1'h0; - wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire sub_wire3; + wire [0:0] sub_wire8 = 1'h0; + wire [2:2] sub_wire5 = sub_wire0[2:2]; + wire [0:0] sub_wire4 = sub_wire0[0:0]; + wire [3:3] sub_wire2 = sub_wire0[3:3]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; - wire locked = sub_wire2; - wire c0 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + wire c3 = sub_wire2; + wire locked = sub_wire3; + wire c0 = sub_wire4; + wire c2 = sub_wire5; + wire sub_wire6 = inclk0; + wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; altpll altpll_component ( .areset (areset), - .inclk (sub_wire5), + .inclk (sub_wire7), .clk (sub_wire0), - .locked (sub_wire2), + .locked (sub_wire3), .activeclock (), .clkbad (), .clkena ({6{1'b1}}), @@ -111,10 +119,18 @@ module pll ( altpll_component.clk0_duty_cycle = 50, altpll_component.clk0_multiply_by = 50, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 54, + altpll_component.clk1_divide_by = 27, altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 25, altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 54, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 25, + altpll_component.clk2_phase_shift = "0", + altpll_component.clk3_divide_by = 108, + altpll_component.clk3_duty_cycle = 50, + altpll_component.clk3_multiply_by = 25, + altpll_component.clk3_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -149,8 +165,8 @@ module pll ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_UNUSED", - altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_USED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", altpll_component.port_clkena0 = "PORT_UNUSED", @@ -189,11 +205,17 @@ endmodule // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "54" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "54" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "108" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.500000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.500000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.250000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -215,25 +237,41 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "25" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.50000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.50000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.25000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -257,13 +295,19 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -272,10 +316,18 @@ endmodule // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "54" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "108" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "25" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -309,8 +361,8 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -329,6 +381,8 @@ endmodule // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 @@ -336,6 +390,8 @@ endmodule // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE diff --git a/Sharp - MZ-80K_MiST/rtl/spram.vhd b/Sharp - MZ-80K_MiST/rtl/spram.vhd new file mode 100644 index 00000000..d9a003ee --- /dev/null +++ b/Sharp - MZ-80K_MiST/rtl/spram.vhd @@ -0,0 +1,89 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +------------------------------------------------------------------------------- +-- +-- Generic single port RAM. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity spram is + generic ( + addr_width_g : integer := 14; + data_width_g : integer := 8 + ); + port ( + clk_i : in std_logic; + we_i : in std_logic; + addr_i : in std_logic_vector(addr_width_g-1 downto 0); + data_i : in std_logic_vector(data_width_g-1 downto 0); + data_o : out std_logic_vector(data_width_g-1 downto 0) + ); + +end spram; + +library ieee; +use ieee.numeric_std.all; + +architecture rtl of spram is + + type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0); + signal ram_q : ram_t + -- pragma translate_off + := (others => (others => '0')) + -- pragma translate_on + ; + signal read_addr_q : unsigned(addr_width_g-1 downto 0); + +begin + + process (clk_i) + begin + if rising_edge(clk_i) then + if we_i = '1' then + ram_q(to_integer(unsigned(addr_i))) <= data_i; + end if; + + read_addr_q <= unsigned(addr_i); + end if; + end process; + + data_o <= ram_q(to_integer(read_addr_q)); + +end rtl; diff --git a/Sharp - MZ-80K_MiST/rtl/vga.v b/Sharp - MZ-80K_MiST/rtl/vga.v index 862b9316..f0e8441e 100644 --- a/Sharp - MZ-80K_MiST/rtl/vga.v +++ b/Sharp - MZ-80K_MiST/rtl/vga.v @@ -20,9 +20,12 @@ ////////////////////////////////////////////////////////////////////////////////// module vga( input CLK_50MHZ, - output VGA_RED, - output VGA_GREEN, - output VGA_BLUE, + input [1:0] color, + input RD_n, + input WR_n, + output [1:0] VGA_RED, + output [1:0] VGA_GREEN, + output [1:0] VGA_BLUE, output VGA_HSYNC, output VGA_VSYNC, output VGA_VBLANK, @@ -66,19 +69,39 @@ module vga( .clken(1'b1) ); +wire [1:0] R, G, B; + Color_Card Color_Card( + .CLK(CLK_50MHZ), + .CSX_n(), + .WR_n(WR_n), + .CSD_n(), + .Sync(), + .RD_n(RD_n), + .Video(video), + .Din(VGA_DATA), + .Dout(), + .Addr(VGA_ADDR[11:0]), + .CSDo(), + .Synco_n(), + .R(R), + .G(G), + .B(B) +); wire [5:0] cx, cy; //(0,0)-(79,24) assign cx = gx >> 4; assign cy = gy >> 4; assign VGA_ADDR = (cy * 40) + cx; assign cgrom_addr = {VGA_DATA, gy[3:1]}; - + wire video = display & (y[0] & 1) ? cgrom_data[7-(((gx+15)>>1) & 7)] : 0; // assign BUS_REQ = ( (96+48-8) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400)); assign BUS_REQ = ( (96+48-16) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400)); assign display =( (96+48) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400)); - assign VGA_RED = 0; //display ? (cgrom_data[7-((gx>>1) & 7)]) : 0; - assign VGA_GREEN = display & (y[0] & 1) ? cgrom_data[7-(((gx+15)>>1) & 7)] : 0; - assign VGA_BLUE = 0; //display ? (cgrom_data[7-((gx>>1) & 7)]) : 0; + + assign VGA_RED = color[1] ? R : color[0] ? 2'b00 : {video,video}; + assign VGA_GREEN = color[1] ? G : {video,video}; + assign VGA_BLUE = color[1] ? B : color[0] ? 2'b00 : {video,video}; + assign VGA_HSYNC = x < 96 ? 0 : 1; assign VGA_VSYNC = y < 2 ? 0 : 1; assign VGA_VBLANK = (x == 639 & y == 499) ? 1 : 0;