diff --git a/Arcade_MiST/Midway MCR 2/Journey_MiST/README.txt b/Arcade_MiST/Midway MCR 2/Journey_MiST/README.txt
index b7d5620b..9d3489bf 100644
--- a/Arcade_MiST/Midway MCR 2/Journey_MiST/README.txt
+++ b/Arcade_MiST/Midway MCR 2/Journey_MiST/README.txt
@@ -13,6 +13,10 @@
-- MRA utilty: https://github.com/sebdel/mra-tools-c
--
-- Based on Kickman/Timber by Dar
+-- Tape Support by Alastair M. Robinson
+
+
+For Use oft the Tape Audio, you need the Sample File sepways.wav. Rename it to Journey.vhd and Copy it to the SD Card
---------------------------------------------------------------------------------
-- DE10_lite Top level for Kick (Midway MCR) by Dar (darfpga@aol.fr) (19/10/2019)
-- http://darfpga.blogspot.fr
diff --git a/Arcade_MiST/Midway MCR 2/Journey_MiST/rtl/Journey_MiST.sv b/Arcade_MiST/Midway MCR 2/Journey_MiST/rtl/Journey_MiST.sv
index 974305d4..78a09603 100644
--- a/Arcade_MiST/Midway MCR 2/Journey_MiST/rtl/Journey_MiST.sv
+++ b/Arcade_MiST/Midway MCR 2/Journey_MiST/rtl/Journey_MiST.sv
@@ -317,7 +317,7 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.rotate ( { orientation[1], rotate } ),
.ce_divider ( 1'b1 ),
.blend ( blend ),
- .scandoubler_disable(1),//scandoublerD ),
+ .scandoubler_disable(1'b1),//scandoublerD ),
.no_csync ( 1'b1 ),
.scanlines ( ),
.ypbpr ( ypbpr )
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/README.txt b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/README.txt
new file mode 100644
index 00000000..1c84ed26
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/README.txt
@@ -0,0 +1,338 @@
+-- Satan's Hollow/Tron/Wacko/Kozmik Krooz'r/Two Tigers/Domino Man Arcade
+-- Based on Dar's Satan's Hollow VHDL code
+-- Interlaced 15kHz/31kHz VGA
+--
+-- Controls: joystick, mouse, standard MAME keys
+-- Coin: ESC, 5, 6
+-- Start: F1, F2, 1, 2
+
+-- Tron: Joystick 1 for movement, Joystick 2 (MAME keys: D, G) or Buttons B and C for turret
+-- Wacko: control Captain Krooz'r with the mouse, shoot with the joystick
+-- Kozmik Krooz'r: use the mouse for movement and shoot, rotate the turret with the joystick
+
+-- Create ROM and ARC files from MAME ROM zip files using the mra utility and the MRA files.
+-- Copy the RBF and the ARC files to the same folder.
+-- Example: mra -A -z /path/to/mame/roms Tron.mra
+-- Copy the ROM files to the root of the SD Card.
+--
+-- MRA utilty: https://github.com/sebdel/mra-tools-c
+--
+-- Some games are storing settings/high scores in a non-volatile RAM. It can be saved to
+-- the SD Card with the "Save NVRAM" option in the OSD menu. It'll be restored when
+-- the core is loaded next time.
+--
+---------------------------------------------------------------------------------
+-- DE10_lite Top level for Satan Hollow (Midway MCR) by Dar (darfpga@aol.fr) (19/10/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+--
+-- release rev 02 : add TV 15kHz mode
+-- (22/11/2019) use merged sprite 8bits roms (make it easier to externalize)
+--
+-- release 01 : improve ssio read input (fix mirror addressing)
+-- improve memory access (fix mirror addressing)
+--
+-- release 00 : initial release
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+-- Use satan_hollow_de10_lite.sdc to compile (Timequest constraints)
+-- /!\
+-- Don't forget to set device configuration mode with memory initialization
+-- (Assignments/Device/Pin options/Configuration mode)
+---------------------------------------------------------------------------------
+--
+-- Main features :
+-- PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection)
+-- Audio pwm output @gpio pins 1/3 (beware voltage translation/protection)
+--
+-- Video : 31Khz/60Hz
+-- Cocktail mode : NO
+-- Sound : OK
+--
+-- For hardware schematic see my other project : NES
+--
+-- Uses 1 pll 40MHz from 50MHz to make 20MHz and 8Mhz
+--
+-- Board key :
+-- 0 : reset game
+--
+-- Keyboard players inputs :
+--
+-- F1 : Add coin
+-- F2 : Start 1 player
+-- F3 : Start 2 players
+-- F5 : Sevice mode ON/OFF
+-- SPACE : fire
+-- RIGHT arrow : move right
+-- LEFT arrow : move left
+-- UP arrow : shield
+--
+-- Other details : see satans_hollow.vhd
+-- For USB inputs and SGT5000 audio output see my other project: xevious_de10_lite
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+-- Satans Hollow by Dar (darfpga@aol.fr) (09/11/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- gen_ram.vhd & io_ps2_keyboard
+--------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- T80/T80se - Version : 304
+-----------------------------
+-- Z80 compatible microprocessor core
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+---------------------------------------------------------------------------------
+-- YM2149 (AY-3-8910)
+-- Copyright (c) MikeJ - Jan 2005
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+--
+-- release rev 02 : add TV 15kHz mode
+-- (22/11/2019) use merged sprite 8bits roms (make it easier to externalize)
+--
+-- release rev 01 : improve ssio read input (fix mirror addressing)
+-- improve memory access (fix mirror addressing)
+--
+-- release rev 00 : initial release
+--
+---------------------------------------------------------------------------------
+-- Features :
+-- Video : 31Khz/60Hz
+-- Coctail mode : NO
+-- Sound : OK
+
+-- Use with MAME roms from shollow.zip
+--
+-- Use make_satans_hollow_proms.bat to build vhd file from binaries
+-- (CRC list included)
+
+-- Satans hollow (midway mcr) Hardware caracteristics :
+--
+-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram,
+-- sprite data ram, I/O, sound board register and trigger.
+-- 48Kx8bits program rom
+--
+-- One char/background tile map 30x32
+-- 2x8Kx8bits graphics rom 4bits/pixel
+-- rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
+--
+-- 128 sprites, up to ~15/line, 32x32 with flip H/V
+-- 4x8Kx8bits graphics rom 4bits/pixel
+-- rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
+--
+-- Working ram : 2Kx8bits
+-- video (char/background) ram : 2Kx8bits
+-- Sprites ram : 512x8bits + 512x8bits cache buffer
+
+-- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x8bits
+--
+-- SOUND : see satans_hollow_sound_board.vhd
+
+---------------------------------------------------------------------------------
+-- Schematics remarks :
+--
+-- Display is 512x480 pixels (video 635x525 lines @ 20MHz )
+
+-- 635/20e6 = 31.75us per line (31.750KHz)
+-- 31.75*525 = 16.67ms per frame (59.99Hz)
+--
+-- Original video is interlaced 240 display lines per 1/2 frame
+--
+-- H0 and V0 are not use for background => each bg tile is 16x16 pixel but
+-- background graphics is 2x2 pixels defintion.
+--
+-- Sprite are 32x32 pixels with 1x1 pixel definition, 16 lines for odd 1/2
+-- frame and 16 lines for even 2/2 frame thanks to V8 on sprite rom ROMAD2
+-- (look at 74ls86 G1 pin 9 on video genration board schematics)
+--
+-- *H and V stand for Horizontal en Vertical counter (Hcnt, Vcnt in VHDL code)
+--
+-- /!\ For VHDL port interlaced video mode is replaced with progressive video
+-- mode.
+--
+-- Real hardware uses background ram access after each 1/2 frame (~line 240
+-- and 480). In these areas cpu can access ram since scanlines are out of
+-- visible display. In progessive mode there are video access around lines 240.
+-- These accesses will create video artfacts aound mid display. In VHDL code
+-- ram access is muliplexed between cpu and scanlines by using hcnt(0) in
+-- order to avoid these artefacts.
+--
+-- Sprite data are stored first by cpu into a 'cache' buffer (staging ram at
+-- K6/L6) this buffer is read and write for cpu. After visible display, cache
+-- buffer (512x8) is moved to actual sprite ram buffer (512x8). Actual sprite
+-- buffer is access by transfer address counter during 2 scanlines after
+-- visible area and only by sprite machine during visible area.
+--
+-- Thus cpu can read and update sprites position during entire frame except
+-- during 2 lines.
+--
+-- Sprite data are organised (as seen by cpu F000-F1FF) into 128 * 4bytes.
+-- bytes #1 : Vertical position
+-- bytes #2 : code and attribute
+-- bytes #3 : Horizontal position
+-- bytes #4 : not used
+--
+-- Athough 1x1 pixel defintion sprite position horizontal/vertical is made on
+-- on a 2x2 grid (due to only 8bits for position data)
+--
+-- Z80-CTC : interruption ar managed by CTC chip. ONly channel 3 is trigered
+-- by hardware signal line 493. channel 0 to 2 are in timer mode. Schematic
+-- show zc/to of channel 0 connected to clk/trg of channel 1. This seems to be
+-- unsued for that (Kick) game.
+--
+-- Z80-CTC VHDL port keep separated interrupt controler and each counter so
+-- one can use them on its own. Priority daisy-chain is not done (not used in
+-- that game). clock polarity selection is not done since it has no meaning
+-- with digital clock/enable (e.g cpu_ena signal) method.
+--
+-- Ressource : input clock 40MHz is chosen to allow easy making of 20MHz for
+-- pixel clock and 8MHz signal for amplitude modulation circuit of ssio board
+--
+-- TODO :
+-- Working ram could be initialized to set initial difficulty level and
+-- initial bases (live) number. Otherwise one can set it up by using service
+-- menu at each power up.
+--
+
++----------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+---------------------------------------------+
+; Fitter Status ; Successful - Wed Nov 13 19:50:34 2019 ;
+; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
+; Revision Name ; satans_hollow_de10_lite ;
+; Top-level Entity Name ; satans_hollow_de10_lite ;
+; Family ; MAX 10 ;
+; Device ; 10M50DAF484C6GES ;
+; Timing Models ; Preliminary ;
+; Total logic elements ; 6,545 / 49,760 ( 13 % ) ;
+; Total combinational functions ; 6,307 / 49,760 ( 13 % ) ;
+; Dedicated logic registers ; 1,671 / 49,760 ( 3 % ) ;
+; Total registers ; 1671 ;
+; Total pins ; 105 / 360 ( 29 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 938,560 / 1,677,312 ( 56 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
+; Total PLLs ; 1 / 4 ( 25 % ) ;
+; UFM blocks ; 0 / 1 ( 0 % ) ;
+; ADC blocks ; 0 / 2 ( 0 % ) ;
++------------------------------------+---------------------------------------------+
+
+
+---------------
+VHDL File list
+---------------
+
+de10_lite/max10_pll_40M.vhd Pll 40MHz from 50MHz altera mf
+
+rtl_dar/satans_hollow_de10_lite.vhd Top level for de10_lite board
+rtl_dar/satans_hollow.vhd Main CPU and video boards logic
+rtl_dar/satans_hollow_sound_board.vhd Main sound board logic
+rtl_dar/ctc_controler.vhd Z80-CTC controler
+rtl_dar/ctc_counter.vhd Z80-CTC counter
+
+rtl_mikej/YM2149_linmix.vhd Copyright (c) MikeJ - Jan 2005
+
+rtl_T80_304/T80se.vhdT80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+rtl_T80_304/T80_Reg.vhd
+rtl_T80_304/T80_Pack.vhd
+rtl_T80_304/T80_MCode.vhd
+rtl_T80_304/T80_ALU.vhd
+rtl_T80_304/T80.vhd
+
+rtl_dar/kbd_joystick.vhd Keyboard key to player/coin input
+rtl_dar/io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification)
+rtl_dar/decodeur_7_seg.vhd 7 segments display decoder
+
+rtl_dar/proms/satans_hollow_cpu.vhd CPU board PROMS
+rtl_dar/proms/satans_hollow_bg_bits_2.vhd
+rtl_dar/proms/satans_hollow_bg_bits_1.vhd
+
+rtl_dar/proms/satans_hollow_sp_bits.vhd Video board PROMS
+
+rtl_dar/proms/satans_hollow_sound_cpu.vhd Sound board PROMS
+rtl_dar/proms/midssio_82s123.vhd
+
+----------------------
+Quartus project files
+----------------------
+de10_lite/satans_hollow_de10_lite.sdc Timequest constraints file
+de10_lite/satans_hollow_de10_lite.qsf de10_lite settings (files,pins...)
+de10_lite/satans_hollow_de10_lite.qpf de10_lite project
+
+-----------------------------
+Required ROMs (Not included)
+-----------------------------
+You need the following 16 ROMs binary files from satans_hollow.zip and midssio.zip(MAME)
+
+sh-pro.00 CRC 95e2b800
+sh-pro.01 CRC b99f6ff8
+sh-pro.02 CRC 1202c7b2
+sh-pro.03 CRC 0a64afb9
+sh-pro.04 CRC 22fa9175
+sh-pro.05 CRC 1716e2bb
+
+sh-snd.01 CRC 55a297cc
+sh-snd.02 CRC 46fc31f6
+sh-snd.03 CRC b1f4a6a8
+
+sh-bg.00 CRC 3e2b333c
+sh-bg.01 CRC d1d70cc4
+
+sh-fg.00 CRC 33f4554e
+sh-fg.01 CRC ba1a38b4
+sh-fg.02 CRC 6b57f6da
+sh-fg.03 CRC 37ea9d07
+
+midssio_82s123.12d CRC e1281ee9
+
+------
+Tools
+------
+You need to build vhdl files from the binary file :
+ - Unzip the roms file in the tools/satans_hollow_unzip directory
+ - Double click (execute) the script tools/make_satans_hollow_proms.bat to get the following 6 files
+
+satans_hollow_cpu.vhd
+satans_hollow_sound_cpu.vhd
+satans_hollow_bg_bits_1.vhd
+satans_hollow_bg_bits_2.vhd
+satans_hollow_sp_bits.vhd
+
+make_vhdl_prom midssio_82s123.12d midssio_82s123.vhd
+
+
+*DO NOT REDISTRIBUTE THESE FILES*
+
+VHDL files are needed to compile and include roms into the project
+
+The script make_satans_hollow_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux.
+
+Source code of make_vhdl_prom.c is also delivered.
+
+---------------------------------
+Compiling for de10_lite
+---------------------------------
+You can build the project with ROM image embeded in the sof file.
+*DO NOT REDISTRIBUTE THESE FILES*
+
+3 steps
+
+ - put the VHDL ROM files (.vhd) into the rtl_dar/proms directory
+ - build satans_hollow_de10_lite
+ - program satans_hollow_de10_lite.sof
+
+------------------------
+------------------------
+End of file
+------------------------
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/TwoTigers.qpf b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/TwoTigers.qpf
new file mode 100644
index 00000000..c07f553d
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/TwoTigers.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 13:02:51 November 09, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "13:02:51 November 09, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "TwoTigers"
\ No newline at end of file
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/TwoTigers.qsf b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/TwoTigers.qsf
new file mode 100644
index 00000000..11d2aa55
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/TwoTigers.qsf
@@ -0,0 +1,233 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 12:02:23 November 13, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# mcr2_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY TwoTigers_MiST
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# -------------------------------
+# start ENTITY(SatansHollow_MiST)
+
+ # start DESIGN_PARTITION(Top)
+ # ---------------------------
+
+ # Incremental Compilation Assignments
+ # ===================================
+
+ # end DESIGN_PARTITION(Top)
+ # -------------------------
+
+# end ENTITY(SatansHollow_MiST)
+# -----------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/TwoTigers_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/satans_hollow.vhd
+set_global_assignment -name VHDL_FILE rtl/satans_hollow_sound_board.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/spinner.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/midssio_82s123.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
+set_global_assignment -name QIP_FILE ../../../common/IO/Z80CTC/z80ctc.qip
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/vol_table_array.vhd
+set_global_assignment -name VHDL_FILE ../../../common/Sound/ym2149/YM2149.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../common/Sound/wave_sound.sv
+set_global_assignment -name VHDL_FILE ../../../common/Sound/diskimage_by_byte.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/TwoTigers.sdc b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/TwoTigers.sdc
new file mode 100644
index 00000000..80fe5371
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/TwoTigers.sdc
@@ -0,0 +1,134 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions
+## and other software and tools, and its AMPP partner logic
+## functions, and any output files from any of the foregoing
+## (including device programming or simulation files), and any
+## associated documentation or information are expressly subject
+## to the terms and conditions of the Altera Program License
+## Subscription Agreement, Altera MegaCore Function License
+## Agreement, or other applicable license agreement, including,
+## without limitation, that your use is for the sole purpose of
+## programming logic devices manufactured by Altera and sold by
+## Altera or its authorized distributors. Please refer to the
+## applicable agreement for further details.
+
+
+## VENDOR "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
+
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/clean.bat b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/clean.bat
new file mode 100644
index 00000000..b3b7c3b5
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/clean.bat
@@ -0,0 +1,37 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+
+pause
diff --git a/Arcade_MiST/Midway MCR 2/MCR2/meta/Two Tigers.mra b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/meta/Two Tigers.mra
similarity index 98%
rename from Arcade_MiST/Midway MCR 2/MCR2/meta/Two Tigers.mra
rename to Arcade_MiST/Midway MCR 2/TwoTigers_MiST/meta/Two Tigers.mra
index bd3a8212..bf111c9d 100644
--- a/Arcade_MiST/Midway MCR 2/MCR2/meta/Two Tigers.mra
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/meta/Two Tigers.mra
@@ -5,7 +5,7 @@
1984
Bally Midway
Shooter
- MCR2
+ twotigers
twotigerc
2
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/TwoTigers_MiST.sv b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/TwoTigers_MiST.sv
new file mode 100644
index 00000000..83619540
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/TwoTigers_MiST.sv
@@ -0,0 +1,494 @@
+//============================================================================
+// Midway SatansHollow/Tron/DominoMan/Wacko/Kozmik Krooz'r/Two Tigers
+// arcade top-level for MiST
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+// more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this program; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+`default_nettype none
+
+module TwoTigers_MiST(
+ output LED,
+ output [5:0] VGA_R,
+ output [5:0] VGA_G,
+ output [5:0] VGA_B,
+ output VGA_HS,
+ output VGA_VS,
+ output AUDIO_L,
+ output AUDIO_R,
+ input SPI_SCK,
+ output SPI_DO,
+ input SPI_DI,
+ input SPI_SS2,
+ input SPI_SS3,
+ input CONF_DATA0,
+ input CLOCK_27,
+ output [12:0] SDRAM_A,
+ inout [15:0] SDRAM_DQ,
+ output SDRAM_DQML,
+ output SDRAM_DQMH,
+ output SDRAM_nWE,
+ output SDRAM_nCAS,
+ output SDRAM_nRAS,
+ output SDRAM_nCS,
+ output [1:0] SDRAM_BA,
+ output SDRAM_CLK,
+ output SDRAM_CKE
+);
+
+`include "rtl/build_id.v"
+
+localparam CONF_STR = {
+ "TWOTIGERC;;",
+ "O2,Rotate Controls,Off,On;",
+ "O5,Blend,Off,On;",
+ "O6,Swap Joysticks,Off,On;",
+ "O4,Spinner speed,Low,High;",
+ "DIP;",
+ "O7,Service,Off,On;",
+ "R2048,Save NVRAM;",
+ "T0,Reset;",
+ "V,v2.0.",`BUILD_DATE
+};
+
+wire rotate = status[2];
+wire blend = status[5];
+wire joyswap = status[6];
+wire service = status[7];
+wire spinspd = status[4];
+
+wire oneplayer = 1'b0;
+wire [1:0] orientation; //left/right / portrait/landscape
+wire [7:0] input_0 = ~{ service, 1'b0, m_tilt, m_three_players, m_two_players, m_one_player, m_coin2, m_coin1 };
+wire [7:0] input_1 = ~{ 1'b0, spin_angle1 };
+wire [7:0] input_2 = ~{ 4'b0000, m_fire2B, m_fire2A, m_fireB, m_fireA };
+wire [7:0] input_3 = 8'hFF;
+wire [7:0] input_4 = ~{ 1'b0, spin_angle2 };
+
+
+
+assign LED = ~ioctl_downl;
+assign SDRAM_CLK = clk_sys;
+assign SDRAM_CKE = 1;
+
+wire clk_sys;
+wire pll_locked;
+pll_mist pll(
+ .inclk0(CLOCK_27),
+ .areset(0),
+ .c0(clk_sys),
+ .locked(pll_locked)
+ );
+
+wire [31:0] status;
+wire [1:0] buttons;
+wire [1:0] switches;
+wire [7:0] joystick_0;
+wire [7:0] joystick_1;
+wire scandoublerD;
+wire ypbpr;
+wire no_csync;
+wire key_pressed;
+wire [7:0] key_code;
+wire key_strobe;
+wire signed [8:0] mouse_x;
+wire signed [8:0] mouse_y;
+wire mouse_strobe;
+reg [7:0] mouse_flags;
+
+wire [31:0] sd_lba;
+wire sd_rd;
+wire sd_ack;
+wire sd_ack_conf;
+wire [7:0] sd_dout;
+wire sd_dout_strobe;
+wire img_mounted;
+wire [63:0] img_size;
+
+user_io #(
+ .STRLEN(($size(CONF_STR)>>3)),
+ .SD_IMAGES(1))
+user_io(
+ .clk_sys (clk_sys ),
+ .conf_str (CONF_STR ),
+ .SPI_CLK (SPI_SCK ),
+ .SPI_SS_IO (CONF_DATA0 ),
+ .SPI_MISO (SPI_DO ),
+ .SPI_MOSI (SPI_DI ),
+ .buttons (buttons ),
+ .switches (switches ),
+ .scandoubler_disable (scandoublerD ),
+ .ypbpr (ypbpr ),
+ .no_csync (no_csync ),
+ .key_strobe (key_strobe ),
+ .key_pressed (key_pressed ),
+ .key_code (key_code ),
+ .mouse_x (mouse_x ),
+ .mouse_y (mouse_y ),
+ .mouse_strobe (mouse_strobe ),
+ .mouse_flags (mouse_flags ),
+ .joystick_0 (joystick_0 ),
+ .joystick_1 (joystick_1 ),
+
+ // SD CARD
+ .sd_lba (sd_lba ),
+ .sd_rd (sd_rd ),
+ .sd_wr (1'b0 ),
+ .sd_ack (sd_ack ),
+ .sd_ack_conf (sd_ack_conf ),
+ .sd_conf (1'b0 ),
+ .sd_sdhc (1'b1 ),
+ .sd_dout (sd_dout ),
+ .sd_dout_strobe (sd_dout_strobe),
+ .sd_din ( ),
+ .sd_din_strobe ( ),
+ .sd_buff_addr ( ),
+ .img_mounted (img_mounted ),
+ .img_size (img_size ),
+
+ .status (status )
+ );
+
+wire [15:0] rom_addr;
+wire [15:0] rom_do;
+wire [13:0] snd_addr;
+wire [15:0] snd_do;
+wire ioctl_downl;
+wire ioctl_upl;
+wire [7:0] ioctl_index;
+wire ioctl_wr;
+wire [24:0] ioctl_addr;
+wire [7:0] ioctl_dout;
+wire [7:0] ioctl_din;
+
+/* ROM structure
+00000 - 0BFFF 48k CPU1
+0C000 - 0FFFF 16k CPU2
+10000 - 13FFF 16k GFX1
+14000 - 1BFFF 32k GFX2
+*/
+
+data_io data_io(
+ .clk_sys ( clk_sys ),
+ .SPI_SCK ( SPI_SCK ),
+ .SPI_SS2 ( SPI_SS2 ),
+ .SPI_DI ( SPI_DI ),
+ .SPI_DO ( SPI_DO ),
+ .ioctl_download( ioctl_downl ),
+ .ioctl_upload ( ioctl_upl ),
+ .ioctl_index ( ioctl_index ),
+ .ioctl_wr ( ioctl_wr ),
+ .ioctl_addr ( ioctl_addr ),
+ .ioctl_dout ( ioctl_dout ),
+ .ioctl_din ( ioctl_din )
+);
+reg port1_req, port2_req;
+sdram sdram(
+ .*,
+ .init_n ( pll_locked ),
+ .clk ( clk_sys ),
+
+ // port1 used for main CPU
+ .port1_req ( port1_req ),
+ .port1_ack ( ),
+ .port1_a ( ioctl_addr[23:1] ),
+ .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
+ .port1_we ( ioctl_downl ),
+ .port1_d ( {ioctl_dout, ioctl_dout} ),
+ .port1_q ( ),
+
+ .cpu1_addr ( ioctl_downl ? 15'h7fff : rom_addr[15:1] ),
+ .cpu1_q ( rom_do ),
+
+ // port2 for sound board
+ .port2_req ( port2_req ),
+ .port2_ack ( ),
+ .port2_a ( ioctl_addr[23:1] - 16'h6000 ),
+ .port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
+ .port2_we ( ioctl_downl ),
+ .port2_d ( {ioctl_dout, ioctl_dout} ),
+ .port2_q ( ),
+
+ .snd_addr ( ioctl_downl ? 15'h7fff : {2'b00, snd_addr[13:1]} ),
+ .snd_q ( snd_do )
+);
+
+always @(posedge clk_sys) begin
+ reg ioctl_wr_last = 0;
+
+ ioctl_wr_last <= ioctl_wr;
+ if (ioctl_downl) begin
+ if (~ioctl_wr_last && ioctl_wr && ioctl_index == 0) begin
+ port1_req <= ~port1_req;
+ port2_req <= ~port2_req;
+ end
+ end
+end
+
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge clk_sys) begin
+ reg ioctl_downlD;
+ ioctl_downlD <= ioctl_downl;
+
+ if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+ reset <= status[0] | buttons[1] | ioctl_downl | ~rom_loaded;
+end
+
+wire [15:0] audio_l, audio_r;
+wire hs, vs, cs;
+wire blankn;
+wire [2:0] g, r, b;
+wire [7:0] output_4;
+
+satans_hollow satans_hollow(
+ .clock_40(clk_sys),
+ .reset(reset),
+ .video_r(r),
+ .video_g(g),
+ .video_b(b),
+ .video_blankn(blankn),
+ .video_hs(hs),
+ .video_vs(vs),
+ .video_csync(cs),
+ .tv15Khz_mode(scandoublerD),
+ .separate_audio(1'b1),
+ .audio_out_l(audio_l),
+ .audio_out_r(audio_r),
+
+ .input_0 ( input_0 ),
+ .input_1 ( input_1 ),
+ .input_2 ( input_2 ),
+ .input_3 ( input_3 ),
+ .input_4 ( input_4 ),
+
+
+
+ .cpu_rom_addr ( rom_addr ),
+ .cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
+ .snd_rom_addr ( snd_addr ),
+ .snd_rom_do ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ),
+
+ .dl_addr ( ioctl_addr[16:0]),
+ .dl_wr ( ioctl_wr && ioctl_index == 0 ),
+ .dl_data ( ioctl_dout ),
+ .up_data ( ioctl_din ),
+ .cmos_wr ( ioctl_wr && ioctl_index == 8'hff )
+);
+
+wire vs_out;
+wire hs_out;
+always @(posedge clk_sys) begin
+ VGA_HS <= (~no_csync & scandoublerD & ~ypbpr)? cs : hs_out;
+ VGA_VS <= (~no_csync & scandoublerD & ~ypbpr)? 1'b1 : vs_out;
+end
+
+mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
+ .clk_sys ( clk_sys ),
+ .SPI_SCK ( SPI_SCK ),
+ .SPI_SS3 ( SPI_SS3 ),
+ .SPI_DI ( SPI_DI ),
+ .R ( blankn ? r : 0 ),
+ .G ( blankn ? g : 0 ),
+ .B ( blankn ? b : 0 ),
+ .HSync ( hs ),
+ .VSync ( vs ),
+ .VGA_R ( VGA_R ),
+ .VGA_G ( VGA_G ),
+ .VGA_B ( VGA_B ),
+ .VGA_VS ( vs_out ),
+ .VGA_HS ( hs_out ),
+ .rotate ( { orientation[1], rotate } ),
+ .ce_divider ( 1'b1 ),
+ .blend ( blend ),
+ .scandoubler_disable( 1'b1 ),
+ .no_csync ( 1'b1 ),
+ .scanlines ( ),
+ .ypbpr ( ypbpr )
+ );
+
+// Wave sound
+
+wire wav_mounted;
+wire [31:0] wav_addr;
+wire wav_rd;
+wire wav_rd_next;
+wire [7:0] wav_d;
+wire wav_ack;
+
+assign wav_addr[31:28] = 4'h0;
+assign sd_lba[31:23] = 8'h00;
+
+// Bytewise interface to disk images
+diskimage_by_byte waveinterface (
+ .clk(clk_sys),
+ .reset_n(~reset),
+
+ .sd_lba(sd_lba),
+ .sd_rd(sd_rd),
+ .sd_ack(sd_ack),
+ .sd_d(sd_dout),
+ .sd_d_strobe(sd_dout_strobe),
+ .sd_imgsize(img_size),
+ .sd_imgmounted(img_mounted),
+
+ .client_mounted(wav_mounted),
+ .client_addr(wav_addr),
+ .client_rd(wav_rd),
+ .client_rd_next(wav_rd_next),
+ .client_q(wav_d),
+ .client_ack(wav_ack)
+);
+
+// Wave player
+
+wire [15:0] wav_out_l;
+wire [15:0] wav_out_r;
+
+wire playing;
+
+assign playing = wav_mounted && output_4[1];
+
+wave_sound #(.SYSCLOCK(40000000)) waveplayer
+(
+ .I_CLK(clk_sys),
+ .I_RST(reset | img_mounted),
+
+ .I_BASE_ADDR(0),
+ .I_LOOP(1'b1),
+ .I_PAUSE(~playing),
+
+ .O_ADDR(wav_addr),
+ .O_READ(wav_rd),
+ .O_READNEXT(wav_rd_next),
+ .I_DATA(wav_d),
+ .I_READY(wav_ack),
+
+ .O_PCM_L(wav_out_l),
+ .O_PCM_R(wav_out_r)
+);
+
+
+reg [16:0] audio_l_sum;
+reg [16:0] audio_r_sum;
+
+reg [16:0] dac_in_l;
+reg [16:0] dac_in_r;
+
+always @(posedge clk_sys) begin
+
+ audio_l_sum <= {wav_out_l[15],wav_out_l} + {audio_l,1'b0} - 16'h4000;
+ audio_r_sum <= {wav_out_r[15],wav_out_r} + {audio_r,1'b0} - 16'h4000;
+
+ dac_in_l <= {~audio_l_sum[16],audio_l_sum[15:0]};
+ dac_in_r <= {~audio_r_sum[16],audio_r_sum[15:0]};
+end
+
+
+dac #(
+ .C_bits(17))
+dac_l(
+ .clk_i(clk_sys),
+ .res_n_i(1),
+ .dac_i(dac_in_l),
+ .dac_o(AUDIO_L)
+ );
+
+dac #(
+ .C_bits(17))
+dac_r(
+ .clk_i(clk_sys),
+ .res_n_i(1),
+ .dac_i(dac_in_r),
+ .dac_o(AUDIO_R)
+ );
+
+// Mouse controls for Wacko
+reg signed [10:0] x_pos;
+reg signed [10:0] y_pos;
+
+always @(posedge clk_sys) begin
+ if (mouse_strobe) begin
+ if (rotate) begin
+ x_pos <= x_pos - mouse_y;
+ y_pos <= y_pos + mouse_x;
+ end else begin
+ x_pos <= x_pos + mouse_x;
+ y_pos <= y_pos + mouse_y;
+ end
+ end
+end
+
+// Controls for Kozmik Krooz'r
+reg signed [9:0] x_pos_kroozr;
+reg signed [9:0] y_pos_kroozr;
+wire signed [8:0] move_x = rotate ? -mouse_y : mouse_x;
+wire signed [8:0] move_y = rotate ? mouse_x : mouse_y;
+wire signed [9:0] x_pos_new = x_pos_kroozr - move_x;
+wire signed [9:0] y_pos_new = y_pos_kroozr + move_y;
+reg [1:0] mouse_btns;
+
+always @(posedge clk_sys) begin
+ if (mouse_strobe) begin
+ mouse_btns <= mouse_flags[1:0];
+ if (!((move_x[8] & ~x_pos_kroozr[9] & x_pos_new[9]) || (~move_x[8] & x_pos_kroozr[9] & ~x_pos_new[9]))) x_pos_kroozr <= x_pos_new;
+ if (!((move_y[8] & y_pos_kroozr[9] & ~y_pos_new[9]) || (~move_y[8] & ~y_pos_kroozr[9] & y_pos_new[9]))) y_pos_kroozr <= y_pos_new;
+ end
+end
+
+// Spinners for Tron, Two Tigers, Krooz'r
+wire [6:0] spin_angle1;
+spinner spinner1 (
+ .clock_40(clk_sys),
+ .reset(reset),
+ .btn_acc(spinspd),
+ .btn_left(m_left | m_up),
+ .btn_right(m_right | m_down),
+ .ctc_zc_to_2(vs),
+ .spin_angle(spin_angle1)
+);
+
+wire [6:0] spin_angle2;
+spinner spinner2 (
+ .clock_40(clk_sys),
+ .reset(reset),
+ .btn_acc(spinspd),
+ .btn_left(m_left2 | m_up2),
+ .btn_right(m_right2 | m_down2),
+ .ctc_zc_to_2(vs),
+ .spin_angle(spin_angle2)
+);
+
+// Arcade inputs
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+ .clk ( clk_sys ),
+ .key_strobe ( key_strobe ),
+ .key_pressed ( key_pressed ),
+ .key_code ( key_code ),
+ .joystick_0 ( joystick_0 ),
+ .joystick_1 ( joystick_1 ),
+ .rotate ( rotate ),
+ .orientation ( orientation ),
+ .joyswap ( joyswap ),
+ .oneplayer ( oneplayer ),
+ .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+ .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+ .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
+
+endmodule
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/build_id.tcl
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+ # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+ set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+ set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+ # Create a Verilog file for output
+ set outputFileName "rtl/build_id.v"
+ set outputFile [open $outputFileName "w"]
+
+ # Output the Verilog source
+ puts $outputFile "`define BUILD_DATE \"$buildDate\""
+ puts $outputFile "`define BUILD_TIME \"$buildTime\""
+ close $outputFile
+
+ # Send confirmation message to the Messages window
+ post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+ post_message "Date: $buildDate"
+ post_message "Time: $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/cmos_ram.vhd b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/cmos_ram.vhd
new file mode 100644
index 00000000..c5e34893
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/cmos_ram.vhd
@@ -0,0 +1,356 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr)
+-- http://darfpga.blogspot.fr
+-- Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- gen_rwram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cmos_ram is
+ generic (
+ dWidth : integer := 8;
+ aWidth : integer := 10
+ );
+ port (
+ clk : in std_logic;
+ we : in std_logic;
+ addr : in std_logic_vector((aWidth-1) downto 0);
+ d : in std_logic_vector((dWidth-1) downto 0);
+ q : out std_logic_vector((dWidth-1) downto 0)
+ );
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of cmos_ram is
+ subtype addressRange is integer range 0 to ((2**aWidth)-1);
+ type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+ signal ram: ramDef:= (
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --000-00F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --010-01F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --020-02F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --030-03F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --040-04F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --050-05F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --060-06F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --070-07F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --080-08F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --090-09F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0A0-0AF
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0B0-0BF
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0C0-0CF
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0D0-0DF
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0E0-0EF
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --0F0-0FF
+
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --100-10F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --1F0-1FF
+
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --200-20F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --2F0-2FF
+
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --300-30F
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
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+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --AF0-AFF
+--
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --B00-B0F
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --BF0-BFF
+--
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --C00-C0F
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --CF0-CFF
+--
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --D00-D0F
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --DF0-DFF
+--
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --E00-E0F
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --EF0-EFF
+--
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", --F00-F0F
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+-- X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF" --FF0-FFF
+);
+
+ signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
+ signal qReg : std_logic_vector((dWidth-1) downto 0);
+begin
+-- -----------------------------------------------------------------------
+-- Signals to entity interface
+-- -----------------------------------------------------------------------
+-- q <= qReg;
+
+-- -----------------------------------------------------------------------
+-- Memory write
+-- -----------------------------------------------------------------------
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ if we = '1' then
+ ram(to_integer(unsigned(addr))) <= d;
+ end if;
+ end if;
+ end process;
+
+-- -----------------------------------------------------------------------
+-- Memory read
+-- -----------------------------------------------------------------------
+process(clk)
+ begin
+ if rising_edge(clk) then
+-- qReg <= ram(to_integer(unsigned(rAddrReg)));
+-- rAddrReg <= addr;
+---- qReg <= ram(to_integer(unsigned(addr)));
+ q <= ram(to_integer(unsigned(addr)));
+ end if;
+ end process;
+--q <= ram(to_integer(unsigned(addr)));
+end architecture;
+
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/dpram.vhd b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..284194c5
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/dpram.vhd
@@ -0,0 +1,81 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr)
+-- http://darfpga.blogspot.fr
+-- Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- dpram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity dpram is
+ generic (
+ dWidth : integer := 8;
+ aWidth : integer := 10
+ );
+ port (
+ clk_a : in std_logic;
+ we_a : in std_logic := '0';
+ addr_a : in std_logic_vector((aWidth-1) downto 0);
+ d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
+ q_a : out std_logic_vector((dWidth-1) downto 0);
+
+ clk_b : in std_logic;
+ we_b : in std_logic := '0';
+ addr_b : in std_logic_vector((aWidth-1) downto 0);
+ d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
+ q_b : out std_logic_vector((dWidth-1) downto 0)
+ );
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of dpram is
+ subtype addressRange is integer range 0 to ((2**aWidth)-1);
+ type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+ signal ram: ramDef;
+ signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
+ signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
+begin
+
+-- -----------------------------------------------------------------------
+ process(clk_a)
+ begin
+ if rising_edge(clk_a) then
+ if we_a = '1' then
+ ram(to_integer(unsigned(addr_a))) <= d_a;
+ end if;
+ q_a <= ram(to_integer(unsigned(addr_a)));
+ end if;
+ end process;
+
+ process(clk_b)
+ begin
+ if rising_edge(clk_b) then
+ if we_b = '1' then
+ ram(to_integer(unsigned(addr_b))) <= d_b;
+ end if;
+ q_b <= ram(to_integer(unsigned(addr_b)));
+ end if;
+ end process;
+
+end architecture;
+
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/gen_ram.vhd
new file mode 100644
index 00000000..f1a95608
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/gen_ram.vhd
@@ -0,0 +1,84 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr)
+-- http://darfpga.blogspot.fr
+-- Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- gen_rwram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity gen_ram is
+ generic (
+ dWidth : integer := 8;
+ aWidth : integer := 10
+ );
+ port (
+ clk : in std_logic;
+ we : in std_logic;
+ addr : in std_logic_vector((aWidth-1) downto 0);
+ d : in std_logic_vector((dWidth-1) downto 0);
+ q : out std_logic_vector((dWidth-1) downto 0)
+ );
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of gen_ram is
+ subtype addressRange is integer range 0 to ((2**aWidth)-1);
+ type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+ signal ram: ramDef;
+
+ signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
+ signal qReg : std_logic_vector((dWidth-1) downto 0);
+begin
+-- -----------------------------------------------------------------------
+-- Signals to entity interface
+-- -----------------------------------------------------------------------
+-- q <= qReg;
+
+-- -----------------------------------------------------------------------
+-- Memory write
+-- -----------------------------------------------------------------------
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ if we = '1' then
+ ram(to_integer(unsigned(addr))) <= d;
+ end if;
+ end if;
+ end process;
+
+-- -----------------------------------------------------------------------
+-- Memory read
+-- -----------------------------------------------------------------------
+process(clk)
+ begin
+ if rising_edge(clk) then
+-- qReg <= ram(to_integer(unsigned(rAddrReg)));
+-- rAddrReg <= addr;
+---- qReg <= ram(to_integer(unsigned(addr)));
+ q <= ram(to_integer(unsigned(addr)));
+ end if;
+ end process;
+--q <= ram(to_integer(unsigned(addr)));
+end architecture;
+
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/pll_mist.qip b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/pll_mist.qip
new file mode 100644
index 00000000..d4720390
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/pll_mist.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/pll_mist.vhd b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/pll_mist.vhd
new file mode 100644
index 00000000..15c5571c
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/pll_mist.vhd
@@ -0,0 +1,397 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll
+
+-- ============================================================
+-- File Name: pll_mist.vhd
+-- Megafunction Name(s):
+-- altpll
+--
+-- Simulation Library Files(s):
+-- altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_mist IS
+ PORT
+ (
+ areset : IN STD_LOGIC := '0';
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ c1 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+END pll_mist;
+
+
+ARCHITECTURE SYN OF pll_mist IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC ;
+ SIGNAL sub_wire4 : STD_LOGIC ;
+ SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+ COMPONENT altpll
+ GENERIC (
+ bandwidth_type : STRING;
+ clk0_divide_by : NATURAL;
+ clk0_duty_cycle : NATURAL;
+ clk0_multiply_by : NATURAL;
+ clk0_phase_shift : STRING;
+ clk1_divide_by : NATURAL;
+ clk1_duty_cycle : NATURAL;
+ clk1_multiply_by : NATURAL;
+ clk1_phase_shift : STRING;
+ compensate_clock : STRING;
+ inclk0_input_frequency : NATURAL;
+ intended_device_family : STRING;
+ lpm_hint : STRING;
+ lpm_type : STRING;
+ operation_mode : STRING;
+ pll_type : STRING;
+ port_activeclock : STRING;
+ port_areset : STRING;
+ port_clkbad0 : STRING;
+ port_clkbad1 : STRING;
+ port_clkloss : STRING;
+ port_clkswitch : STRING;
+ port_configupdate : STRING;
+ port_fbin : STRING;
+ port_inclk0 : STRING;
+ port_inclk1 : STRING;
+ port_locked : STRING;
+ port_pfdena : STRING;
+ port_phasecounterselect : STRING;
+ port_phasedone : STRING;
+ port_phasestep : STRING;
+ port_phaseupdown : STRING;
+ port_pllena : STRING;
+ port_scanaclr : STRING;
+ port_scanclk : STRING;
+ port_scanclkena : STRING;
+ port_scandata : STRING;
+ port_scandataout : STRING;
+ port_scandone : STRING;
+ port_scanread : STRING;
+ port_scanwrite : STRING;
+ port_clk0 : STRING;
+ port_clk1 : STRING;
+ port_clk2 : STRING;
+ port_clk3 : STRING;
+ port_clk4 : STRING;
+ port_clk5 : STRING;
+ port_clkena0 : STRING;
+ port_clkena1 : STRING;
+ port_clkena2 : STRING;
+ port_clkena3 : STRING;
+ port_clkena4 : STRING;
+ port_clkena5 : STRING;
+ port_extclk0 : STRING;
+ port_extclk1 : STRING;
+ port_extclk2 : STRING;
+ port_extclk3 : STRING;
+ self_reset_on_loss_lock : STRING;
+ width_clock : NATURAL
+ );
+ PORT (
+ areset : IN STD_LOGIC ;
+ clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+BEGIN
+ sub_wire6_bv(0 DOWNTO 0) <= "0";
+ sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
+ sub_wire3 <= sub_wire0(0);
+ sub_wire1 <= sub_wire0(1);
+ c1 <= sub_wire1;
+ locked <= sub_wire2;
+ c0 <= sub_wire3;
+ sub_wire4 <= inclk0;
+ sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+
+ altpll_component : altpll
+ GENERIC MAP (
+ bandwidth_type => "AUTO",
+ clk0_divide_by => 27,
+ clk0_duty_cycle => 50,
+ clk0_multiply_by => 40,
+ clk0_phase_shift => "0",
+ clk1_divide_by => 27,
+ clk1_duty_cycle => 50,
+ clk1_multiply_by => 80,
+ clk1_phase_shift => "0",
+ compensate_clock => "CLK0",
+ inclk0_input_frequency => 37037,
+ intended_device_family => "Cyclone III",
+ lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
+ lpm_type => "altpll",
+ operation_mode => "NORMAL",
+ pll_type => "AUTO",
+ port_activeclock => "PORT_UNUSED",
+ port_areset => "PORT_USED",
+ port_clkbad0 => "PORT_UNUSED",
+ port_clkbad1 => "PORT_UNUSED",
+ port_clkloss => "PORT_UNUSED",
+ port_clkswitch => "PORT_UNUSED",
+ port_configupdate => "PORT_UNUSED",
+ port_fbin => "PORT_UNUSED",
+ port_inclk0 => "PORT_USED",
+ port_inclk1 => "PORT_UNUSED",
+ port_locked => "PORT_USED",
+ port_pfdena => "PORT_UNUSED",
+ port_phasecounterselect => "PORT_UNUSED",
+ port_phasedone => "PORT_UNUSED",
+ port_phasestep => "PORT_UNUSED",
+ port_phaseupdown => "PORT_UNUSED",
+ port_pllena => "PORT_UNUSED",
+ port_scanaclr => "PORT_UNUSED",
+ port_scanclk => "PORT_UNUSED",
+ port_scanclkena => "PORT_UNUSED",
+ port_scandata => "PORT_UNUSED",
+ port_scandataout => "PORT_UNUSED",
+ port_scandone => "PORT_UNUSED",
+ port_scanread => "PORT_UNUSED",
+ port_scanwrite => "PORT_UNUSED",
+ port_clk0 => "PORT_USED",
+ port_clk1 => "PORT_USED",
+ port_clk2 => "PORT_UNUSED",
+ port_clk3 => "PORT_UNUSED",
+ port_clk4 => "PORT_UNUSED",
+ port_clk5 => "PORT_UNUSED",
+ port_clkena0 => "PORT_UNUSED",
+ port_clkena1 => "PORT_UNUSED",
+ port_clkena2 => "PORT_UNUSED",
+ port_clkena3 => "PORT_UNUSED",
+ port_clkena4 => "PORT_UNUSED",
+ port_clkena5 => "PORT_UNUSED",
+ port_extclk0 => "PORT_UNUSED",
+ port_extclk1 => "PORT_UNUSED",
+ port_extclk2 => "PORT_UNUSED",
+ port_extclk3 => "PORT_UNUSED",
+ self_reset_on_loss_lock => "OFF",
+ width_clock => 5
+ )
+ PORT MAP (
+ areset => areset,
+ inclk => sub_wire5,
+ clk => sub_wire0,
+ locked => sub_wire2
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "80.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "40"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "80"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "80.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "80"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/rom/midssio_82s123.vhd b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/rom/midssio_82s123.vhd
new file mode 100644
index 00000000..daecc05c
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/rom/midssio_82s123.vhd
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity midssio_82s123 is
+port (
+ clk : in std_logic;
+ addr : in std_logic_vector(4 downto 0);
+ data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of midssio_82s123 is
+ type rom is array(0 to 31) of std_logic_vector(7 downto 0);
+ signal rom_data: rom := (
+ X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"FF",X"FF",X"FE",X"FF",X"FF",X"FD",X"FF",X"FE",X"FF",X"F7",
+ X"FB",X"EF",X"6D",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+ if rising_edge(clk) then
+ data <= rom_data(to_integer(unsigned(addr)));
+ end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/satans_hollow.vhd b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/satans_hollow.vhd
new file mode 100644
index 00000000..51091359
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/satans_hollow.vhd
@@ -0,0 +1,834 @@
+---------------------------------------------------------------------------------
+-- Midway 90010 CPU board, 91399 Video board, 90913 Sound board
+-- Satans Hollow by Dar (darfpga@aol.fr) (09/11/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- gen_ram.vhd & io_ps2_keyboard
+--------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- T80/T80se - Version : 304
+-----------------------------
+-- Z80 compatible microprocessor core
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+---------------------------------------------------------------------------------
+-- YM2149 (AY-3-8910)
+-- Copyright (c) MikeJ - Jan 2005
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+--
+-- release rev 02 : add TV 15kHz mode
+-- (22/11/2019) use merged sprite 8bits roms (make it easier to externalize)
+--
+-- release rev 01 : improve ssio read input (fix mirror addressing)
+-- improve memory access (fix mirror addressing)
+--
+-- release rev 00 : initial release
+--
+--
+-- Features :
+-- Video : VGA 31Khz/60Hz and TV 15kHz
+-- Coctail mode : NO
+-- Sound : OK
+
+-- Use with MAME roms from shollow.zip
+--
+-- Use make_satans_hollow_proms.bat to build vhd file from binaries
+-- (CRC list included)
+
+-- Satans hollow (midway mcr) Hardware caracteristics :
+--
+-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram,
+-- sprite data ram, I/O, sound board register and trigger.
+-- 48Kx8bits program rom
+--
+-- One char/background tile map 30x32
+-- 2x8Kx8bits graphics rom 4bits/pixel
+-- rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
+--
+-- 128 sprites, up to ~15/line, 32x32 with flip H/V
+-- 4x8Kx8bits graphics rom 4bits/pixel
+-- rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
+--
+-- Working ram : 2Kx8bits
+-- video (char/background) ram : 2Kx8bits
+-- Sprites ram : 512x8bits + 512x8bits cache buffer
+
+-- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x8bits
+--
+-- SOUND : see satans_hollow_sound_board.vhd
+
+---------------------------------------------------------------------------------
+-- Schematics remarks :
+--
+-- Display is 512x480 pixels (video 635x525 lines @ 20MHz )
+
+-- 635/20e6 = 31.75us per line (31.750KHz)
+-- 31.75*525 = 16.67ms per frame (59.99Hz)
+--
+-- Original video is interlaced 240 display lines per 1/2 frame
+--
+-- H0 and V0 are not use for background => each bg tile is 16x16 pixel but
+-- background graphics is 2x2 pixels defintion.
+--
+-- Sprite are 32x32 pixels with 1x1 pixel definition, 16 lines for odd 1/2
+-- frame and 16 lines for even 2/2 frame thanks to V8 on sprite rom ROMAD2
+-- (look at 74ls86 G1 pin 9 on video genration board schematics)
+--
+-- *H and V stand for Horizontal en Vertical counter (Hcnt, Vcnt in VHDL code)
+--
+-- /!\ For VHDL port interlaced video mode is replaced with progressive video
+-- mode.
+--
+-- Real hardware uses background ram access after each 1/2 frame (~line 240
+-- and 480). In these areas cpu can access ram since scanlines are out of
+-- visible display. In progessive mode there are video access around lines 240.
+-- These accesses will create video artfacts aound mid display. In VHDL code
+-- ram access is muliplexed between cpu and scanlines by using hcnt(0) in
+-- order to avoid these artefacts.
+--
+-- Sprite data are stored first by cpu into a 'cache' buffer (staging ram at
+-- K6/L6) this buffer is read and write for cpu. After visible display, cache
+-- buffer (512x8) is moved to actual sprite ram buffer (512x8). Actual sprite
+-- buffer is access by transfer address counter during 2 scanlines after
+-- visible area and only by sprite machine during visible area.
+--
+-- Thus cpu can read and update sprites position during entire frame except
+-- during 2 lines.
+--
+-- Sprite data are organised (as seen by cpu F000-F1FF) into 128 * 4bytes.
+-- bytes #1 : Vertical position
+-- bytes #2 : code and attribute
+-- bytes #3 : Horizontal position
+-- bytes #4 : not used
+--
+-- Athough 1x1 pixel defintion sprite position horizontal/vertical is made on
+-- on a 2x2 grid (due to only 8bits for position data)
+--
+-- Z80-CTC : interruption ar managed by CTC chip. ONly channel 3 is trigered
+-- by hardware signal line 493. channel 0 to 2 are in timer mode. Schematic
+-- show zc/to of channel 0 connected to clk/trg of channel 1. This seems to be
+-- unsued for that (Kick) game.
+--
+-- Z80-CTC VHDL port keep separated interrupt controler and each counter so
+-- one can use them on its own. Priority daisy-chain is not done (not used in
+-- that game). clock polarity selection is not done since it has no meaning
+-- with digital clock/enable (e.g cpu_ena signal) method.
+--
+-- Ressource : input clock 40MHz is chosen to allow easy making of 20MHz for
+-- pixel clock and 8MHz signal for amplitude modulation circuit of ssio board
+--
+-- TODO :
+-- Working ram could be initialized to set initial difficulty level and
+-- initial bases (live) number. Otherwise one can set it up by using service
+-- menu at each power up.
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity satans_hollow is
+port(
+ clock_40 : in std_logic;
+ reset : in std_logic;
+ tv15Khz_mode : in std_logic;
+ video_r : out std_logic_vector(2 downto 0);
+ video_g : out std_logic_vector(2 downto 0);
+ video_b : out std_logic_vector(2 downto 0);
+ video_clk : out std_logic;
+ video_csync : out std_logic;
+ video_blankn : out std_logic;
+ video_hs : out std_logic;
+ video_vs : out std_logic;
+
+ separate_audio : in std_logic;
+ audio_out_l : out std_logic_vector(15 downto 0);
+ audio_out_r : out std_logic_vector(15 downto 0);
+
+ input_0 : in std_logic_vector( 7 downto 0);
+ input_1 : in std_logic_vector( 7 downto 0);
+ input_2 : in std_logic_vector( 7 downto 0);
+ input_3 : in std_logic_vector( 7 downto 0);
+ input_4 : in std_logic_vector( 7 downto 0);
+
+ output_4 : out std_logic_vector( 7 downto 0);
+
+ cpu_rom_addr : out std_logic_vector(15 downto 0);
+ cpu_rom_do : in std_logic_vector(7 downto 0);
+ cpu_rom_rd : out std_logic;
+
+ snd_rom_addr : out std_logic_vector(13 downto 0);
+ snd_rom_do : in std_logic_vector(7 downto 0);
+ snd_rom_rd : out std_logic;
+
+ dl_addr : in std_logic_vector(16 downto 0);
+ dl_wr : in std_logic;
+ dl_data : in std_logic_vector( 7 downto 0);
+ up_data : out std_logic_vector(7 downto 0);
+ cmos_wr : in std_logic
+ );
+end satans_hollow;
+
+architecture struct of satans_hollow is
+
+ signal reset_n : std_logic;
+ signal clock_vid : std_logic;
+ signal clock_vidn: std_logic;
+ signal clock_cnt : std_logic_vector(3 downto 0) := "0000";
+
+ signal hcnt : std_logic_vector(9 downto 0) := (others=>'0'); -- horizontal counter
+ signal vcnt : std_logic_vector(9 downto 0) := (others=>'0'); -- vertical counter
+ signal vflip : std_logic_vector(9 downto 0) := (others=>'0'); -- vertical counter flip
+
+ signal hs_cnt, vs_cnt :std_logic_vector(9 downto 0) ;
+ signal hsync0, hsync1, hsync2, hsync3, hsync4 : std_logic;
+ signal top_frame : std_logic := '0';
+
+ signal pix_ena : std_logic;
+ signal cpu_ena : std_logic;
+
+ signal cpu_addr : std_logic_vector(15 downto 0);
+ signal cpu_di : std_logic_vector( 7 downto 0);
+ signal cpu_do : std_logic_vector( 7 downto 0);
+ signal cpu_wr_n : std_logic;
+ signal cpu_rd_n : std_logic;
+ signal cpu_mreq_n : std_logic;
+ signal cpu_ioreq_n : std_logic;
+ signal cpu_irq_n : std_logic;
+ signal cpu_m1_n : std_logic;
+ signal cpu_int_ack_n : std_logic;
+
+ signal ctc_controler_we : std_logic;
+ signal ctc_controler_do : std_logic_vector(7 downto 0);
+ signal ctc_int_ack : std_logic;
+ signal ctc_int_ack_phase : std_logic_vector(1 downto 0);
+
+ signal ctc_counter_1_trg : std_logic;
+ signal ctc_counter_3_trg : std_logic;
+
+ signal ctc_ce : std_logic;
+ signal ctc_do : std_logic_vector(7 downto 0);
+
+-- signal cpu_rom_do : std_logic_vector( 7 downto 0);
+
+ signal wram_we : std_logic;
+ signal wram_do : std_logic_vector( 7 downto 0);
+
+ signal bg_ram_addr: std_logic_vector(10 downto 0);
+ signal bg_ram_we : std_logic;
+ signal bg_ram_do : std_logic_vector(7 downto 0);
+ signal bg_ram_do_r: std_logic_vector(7 downto 0); -- registred ram data for cpu
+
+ signal bg_code : std_logic_vector(7 downto 0);
+ signal bg_code_r : std_logic_vector(7 downto 0);
+ signal bg_attr : std_logic_vector(7 downto 0);
+
+ signal bg_code_line : std_logic_vector(12 downto 0);
+ signal bg_graphx1_do : std_logic_vector( 7 downto 0);
+ signal bg_graphx2_do : std_logic_vector( 7 downto 0);
+ signal bg_palette_addr : std_logic_vector( 5 downto 0);
+
+ signal sp_ram_cache_addr : std_logic_vector(8 downto 0);
+ signal sp_ram_cache_we : std_logic;
+ signal sp_ram_cache_do : std_logic_vector(7 downto 0);
+ signal sp_ram_cache_do_r : std_logic_vector(7 downto 0);-- registred ram data for cpu
+
+ signal move_buf : std_logic;
+ signal sp_ram_addr : std_logic_vector(8 downto 0);
+ signal sp_ram_we : std_logic;
+ signal sp_ram_do : std_logic_vector(7 downto 0);
+
+ signal sp_cnt : std_logic_vector(6 downto 0);
+ signal sp_code : std_logic_vector( 7 downto 0);
+ signal sp_input_phase : std_logic_vector( 5 downto 0);
+
+ signal sp_done : std_logic;
+ signal sp_vcnt : std_logic_vector( 9 downto 0);
+ signal sp_line : std_logic_vector( 4 downto 0);
+ signal sp_hcnt : std_logic_vector( 8 downto 0); -- lsb used to mux rd/wr line buffer
+ signal sp_on_line : std_logic;
+ signal sp_on_line_r : std_logic;
+ signal sp_byte_cnt : std_logic_vector( 1 downto 0);
+ signal sp_code_line : std_logic_vector(12 downto 0);
+ signal sp_code_line_mux: std_logic_vector(14 downto 0);
+ signal sp_hflip : std_logic_vector( 1 downto 0);
+ signal sp_vflip : std_logic_vector( 4 downto 0);
+
+ signal sp_graphx_do : std_logic_vector( 7 downto 0);
+ signal sp_mux_roms : std_logic_vector( 1 downto 0);
+ signal sp_graphx_flip : std_logic_vector( 7 downto 0);
+
+ signal sp_buffer_ram1_addr : std_logic_vector(7 downto 0);
+ signal sp_buffer_ram1_we : std_logic;
+ signal sp_buffer_ram1_di : std_logic_vector(7 downto 0);
+ signal sp_buffer_ram1_do : std_logic_vector(7 downto 0);
+ signal sp_buffer_ram1_do_r : std_logic_vector(7 downto 0);
+
+ signal sp_buffer_ram2_addr : std_logic_vector(7 downto 0);
+ signal sp_buffer_ram2_we : std_logic;
+ signal sp_buffer_ram2_di : std_logic_vector(7 downto 0);
+ signal sp_buffer_ram2_do : std_logic_vector(7 downto 0);
+ signal sp_buffer_ram2_do_r : std_logic_vector(7 downto 0);
+
+ signal sp_buffer_sel : std_logic;
+
+ signal sp_vid : std_logic_vector(3 downto 0);
+
+ signal palette_addr : std_logic_vector(5 downto 0);
+ signal palette_we : std_logic;
+ signal palette_do : std_logic_vector(8 downto 0);
+
+ signal ssio_iowe : std_logic;
+ signal ssio_do : std_logic_vector(7 downto 0);
+
+ signal bg_graphics_1_we : std_logic;
+ signal bg_graphics_2_we : std_logic;
+ signal sprite_graphics_we : std_logic;
+
+begin
+
+clock_vid <= clock_40;
+clock_vidn <= not clock_40;
+reset_n <= not reset;
+
+-- make enables clock from clock_vid
+process (clock_vid, reset)
+begin
+ if reset='1' then
+ clock_cnt <= (others=>'0');
+ else
+ if rising_edge(clock_vid) then
+ if clock_cnt = "1111" then -- divide by 16
+ clock_cnt <= (others=>'0');
+ else
+ clock_cnt <= clock_cnt + 1;
+ end if;
+ end if;
+ end if;
+end process;
+--
+cpu_ena <= '1' when clock_cnt = "1111" else '0'; -- (2.5MHz)
+pix_ena <= '1' when (clock_cnt(1 downto 0) = "11" and tv15Khz_mode = '1') or -- (10MHz)
+ (clock_cnt(0) = '1' and tv15Khz_mode = '0') else '0'; -- (20MHz)
+
+-----------------------------------
+-- Video scanner 634x525 @20Mhz --
+-- display 512x480 --
+-----------------------------------
+process (reset, clock_vid)
+begin
+ if reset='1' then
+ hcnt <= (others=>'0');
+ vcnt <= (others=>'0');
+ top_frame <= '0';
+ elsif rising_edge(clock_vid) then
+ if pix_ena = '1' then
+
+ hcnt <= hcnt + 1;
+ if hcnt = 633 then
+ hcnt <= (others=>'0');
+ vcnt <= vcnt + 1;
+ if (vcnt = 524 and tv15Khz_mode = '0') or (vcnt = 263 and tv15Khz_mode = '1') then
+ vcnt <= (others=>'0');
+ top_frame <= not top_frame;
+ end if;
+ end if;
+
+ if tv15Khz_mode = '0' then
+ -- progessive mode
+
+ if vcnt = 490-1 then video_vs <= '0'; end if; -- front porch 10
+ if vcnt = 492-1 then video_vs <= '1'; end if; -- sync pulse 2
+ -- back porch 33
+
+ if hcnt = 512+13+9 then video_hs <= '0'; end if; -- front porch 16/25*20 = 13
+ if hcnt = 512+90+9 then video_hs <= '1'; end if; -- sync pulse 96/25*20 = 77
+ -- back porch 48/25*20 = 38
+ video_blankn <= '0';
+ if hcnt >= 2+16 and hcnt < 514+16 and
+ vcnt >= 2 and vcnt < 481 then video_blankn <= '1';end if;
+
+ else -- interlaced mode
+
+ if hcnt = 530+18 then
+ hs_cnt <= (others => '0');
+ if (vcnt = 240) then
+ vs_cnt <= (others => '0');
+ else
+ vs_cnt <= vs_cnt +1;
+ end if;
+ else
+ hs_cnt <= hs_cnt + 1;
+ end if;
+
+ if vcnt = 260 then video_vs <= '0'; end if;
+ if vcnt = 262 then video_vs <= '1'; end if;
+
+ video_blankn <= '0';
+ if hcnt >= 2+16 and hcnt < 514+16 and
+ vcnt >= 1 and vcnt < 241 then video_blankn <= '1';end if;
+
+
+ if hs_cnt = 0 then hsync0 <= '0'; video_hs <= '0';
+ elsif hs_cnt = 47 then hsync0 <= '1'; video_hs <= '1';
+ end if;
+
+ if hs_cnt = 0 then hsync1 <= '0';
+ elsif hs_cnt = 23 then hsync1 <= '1';
+ elsif hs_cnt = 317+ 0 then hsync1 <= '0';
+ elsif hs_cnt = 317+23 then hsync1 <= '1';
+ end if;
+
+ if hs_cnt = 0 then hsync2 <= '0';
+ elsif hs_cnt = 317-47 then hsync2 <= '1';
+ elsif hs_cnt = 317 then hsync2 <= '0';
+ elsif hs_cnt = 634-47 then hsync2 <= '1';
+ end if;
+
+
+ if hs_cnt = 0 then hsync3 <= '0';
+ elsif hs_cnt = 23 then hsync3 <= '1';
+ elsif hs_cnt = 317 then hsync3 <= '0';
+ elsif hs_cnt = 634-47 then hsync3 <= '1';
+ end if;
+
+ if hs_cnt = 0 then hsync4 <= '0';
+ elsif hs_cnt = 317-47 then hsync4 <= '1';
+ elsif hs_cnt = 317 then hsync4 <= '0';
+ elsif hs_cnt = 317+23 then hsync4 <= '1';
+ end if;
+
+
+ if vs_cnt = 1 then video_csync <= hsync1;
+ elsif vs_cnt = 2 then video_csync <= hsync1;
+ elsif vs_cnt = 3 then video_csync <= hsync1;
+ elsif vs_cnt = 4 and top_frame = '1' then video_csync <= hsync3;
+ elsif vs_cnt = 4 and top_frame = '0' then video_csync <= hsync1;
+ elsif vs_cnt = 5 then video_csync <= hsync2;
+ elsif vs_cnt = 6 then video_csync <= hsync2;
+ elsif vs_cnt = 7 and top_frame = '1' then video_csync <= hsync4;
+ elsif vs_cnt = 7 and top_frame = '0' then video_csync <= hsync2;
+ elsif vs_cnt = 8 then video_csync <= hsync1;
+ elsif vs_cnt = 9 then video_csync <= hsync1;
+ elsif vs_cnt = 10 then video_csync <= hsync1;
+ elsif vs_cnt = 11 then video_csync <= hsync0;
+ else video_csync <= hsync0;
+ end if;
+
+ end if;
+ end if;
+ end if;
+end process;
+
+------------------------------------------
+-- cpu data input with address decoding --
+------------------------------------------
+cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"C" else -- 0000-BFFF
+ wram_do when cpu_mreq_n = '0' and (cpu_addr and X"E000") = x"C000" else -- C000-C7FF + mirroring 1800
+ sp_ram_cache_do_r when cpu_mreq_n = '0' and (cpu_addr and x"E800") = x"E000" else -- sprite ram E000-E1FF + mirroring 1600
+ bg_ram_do_r when cpu_mreq_n = '0' and (cpu_addr and x"E800") = x"E800" else -- video ram E800-EFFF + mirroring 1000
+ ctc_do when cpu_int_ack_n = '0' or ctc_ce = '1' else -- ctc (interrupt vector or counter data)
+ ssio_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 5) = "000" else -- 0x00-0x1F
+ X"FF";
+
+------------------------------------------------------------------------
+-- Misc registers : ctc write enable / interrupt acknowledge
+------------------------------------------------------------------------
+ctc_counter_3_trg <= '1' when top_frame = '1' and ((vcnt = 246 and tv15Khz_mode = '1') or (vcnt = 493 and tv15Khz_mode = '0')) else '0';
+cpu_int_ack_n <= cpu_ioreq_n or cpu_m1_n;
+ctc_ce <= '1' when cpu_ioreq_n = '0' and cpu_addr(7 downto 4) = x"F" else '0';
+
+------------------------------------------
+-- write enable / ram access from CPU --
+------------------------------------------
+wram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"E000") = x"C000" else '0';
+sp_ram_cache_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"E800") = x"E000" and hcnt(0) = '0' else '0';
+bg_ram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"E800") = x"E800" and hcnt(0) = '0' else '0';
+
+ssio_iowe <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' else '0';
+
+----------------------
+--- sprite machine ---
+----------------------
+vflip <= vcnt(8 downto 0) & top_frame when tv15Khz_mode = '1' else vcnt; -- do not apply mirror flip
+
+sp_buffer_sel <= vflip(1) when tv15Khz_mode = '1' else vflip(0);
+
+process (clock_vid)
+begin
+ if rising_edge(clock_vid) then
+
+ if pix_ena = '1' then
+ if hcnt = 0 then
+ sp_cnt <= (others => '0');
+ sp_input_phase <= (others => '0');
+ sp_on_line <= '0';
+ sp_done <= '0';
+ end if;
+
+ if sp_done = '0' then
+ sp_input_phase <= sp_input_phase + 1 ;
+ sp_hcnt <= sp_hcnt + 1;
+ case sp_input_phase is
+ when "000000" =>
+ if sp_vcnt(8 downto 5) = x"F" then
+ sp_line <= sp_vcnt(4 downto 0);
+ else
+ sp_input_phase <= (others => '0');
+ sp_cnt <= sp_cnt + 1;
+ if sp_cnt = "1111111" then sp_done <= '1'; end if;
+ end if;
+ sp_byte_cnt <= (others => '0');
+ when "000001" =>
+ sp_code <= sp_ram_do;
+ when "000010" =>
+ sp_hcnt <= sp_ram_do & '0';
+ sp_on_line <= '1';
+ when "001001"|"010001"|"011001" =>
+ sp_byte_cnt <= sp_byte_cnt + 1;
+ when "100001" =>
+ sp_on_line <= '0';
+ sp_input_phase <= (others => '0');
+ sp_cnt <= sp_cnt + 1;
+ if sp_cnt = "1111111" then sp_done <= '1'; end if;
+ when others =>
+ null;
+ end case;
+ sp_mux_roms <= sp_input_phase(2 downto 1);
+ end if;
+
+ if hcnt(0) = '0' then
+ sp_buffer_ram1_do_r <= sp_buffer_ram1_do;
+ sp_buffer_ram2_do_r <= sp_buffer_ram2_do;
+ end if;
+
+ end if;
+
+ end if;
+end process;
+
+-- sp_ram_cache can be read/write by cpu when hcnt(0) = 0;
+-- sp_ram_cache can be read by sprite machine when hcnt(0) = 1;
+
+sp_ram_cache_addr <= cpu_addr(8 downto 0) when hcnt(0) = '0' else sp_ram_addr;
+
+--sp_ram_cache_addr <= cpu_addr(8 downto 0) when sp_ram_cache_cpu_access = '1' else sp_ram_addr;
+
+move_buf <= '1' when (vcnt(8 downto 1) = 250 and tv15Khz_mode = '0') or (vcnt(7 downto 1) = 125 and tv15Khz_mode = '1') else '0'; -- line 500-501
+sp_ram_addr <= vcnt(0) & hcnt(8 downto 1) when move_buf = '1' else sp_cnt & sp_input_phase(1 downto 0);
+sp_ram_we <= hcnt(0) when move_buf = '1' else '0';
+
+sp_vcnt <= vflip + (sp_ram_do & '0'); -- valid when sp_input_phase = 0
+
+sp_hflip <= (others => sp_code(6));
+sp_vflip <= (others => sp_code(7));
+
+sp_code_line <= sp_code(5 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt xor sp_hflip); -- sprite graphics roms addr
+
+sp_code_line_mux <= "00" & sp_code_line when (sp_hflip(0) = '0' and sp_mux_roms = "01") or
+ (sp_hflip(0) = '1' and sp_mux_roms = "00") else
+ "01" & sp_code_line when (sp_hflip(0) = '0' and sp_mux_roms = "10") or
+ (sp_hflip(0) = '1' and sp_mux_roms = "11") else
+ "10" & sp_code_line when (sp_hflip(0) = '0' and sp_mux_roms = "11") or
+ (sp_hflip(0) = '1' and sp_mux_roms = "10") else
+ "11" & sp_code_line;-- when (sp_hflip(0) = '0' and sp_mux_roms = "00") or
+ --(sp_hflip(0) = '1' and sp_mux_roms = "01") ;
+
+sp_graphx_flip <= sp_graphx_do when sp_hflip(0) = '0' else
+ sp_graphx_do(3 downto 0) & sp_graphx_do(7 downto 4);
+
+sp_buffer_ram1_di <= sp_buffer_ram1_do or sp_graphx_flip when sp_buffer_sel = '1' else "00000000";
+sp_buffer_ram1_addr <= sp_hcnt(8 downto 1) when sp_buffer_sel = '1' else hcnt(8 downto 1) - X"05";
+sp_buffer_ram1_we <= not sp_hcnt(0) and sp_on_line and pix_ena when sp_buffer_sel = '1' else hcnt(0);
+
+sp_buffer_ram2_di <= sp_buffer_ram2_do or sp_graphx_flip when sp_buffer_sel = '0' else "00000000";
+sp_buffer_ram2_addr <= sp_hcnt(8 downto 1) when sp_buffer_sel = '0' else hcnt(8 downto 1) - X"05";
+sp_buffer_ram2_we <= not sp_hcnt(0) and sp_on_line and pix_ena when sp_buffer_sel = '0' else hcnt(0);
+
+sp_vid <= sp_buffer_ram1_do_r(7 downto 4) when (sp_buffer_sel = '0') and (hcnt(0) = '1') else
+ sp_buffer_ram1_do_r(3 downto 0) when (sp_buffer_sel = '0') and (hcnt(0) = '0') else
+ sp_buffer_ram2_do_r(7 downto 4) when (sp_buffer_sel = '1') and (hcnt(0) = '1') else
+ sp_buffer_ram2_do_r(3 downto 0);-- when (sp_buffer_sel = '1') and (hcnt(0) = '0');
+
+--------------------
+--- char machine ---
+--------------------
+bg_ram_addr <= cpu_addr(10 downto 0) when hcnt(0) = '0' else vflip(8 downto 4) & hcnt(8 downto 4) & hcnt(1);
+
+bg_code_line <= bg_attr(0) & bg_code_r & (vflip(3 downto 1) xor (bg_attr(2) & bg_attr(2) & bg_attr(2) ) ) & (hcnt(3) xor bg_attr(1));
+
+process (clock_vid)
+begin
+ if rising_edge(clock_vid) then
+
+ -- catch ram data for cpu
+ if hcnt(0) = '0' then
+ bg_ram_do_r <= bg_ram_do;
+ sp_ram_cache_do_r <= sp_ram_cache_do;
+ end if;
+
+ if pix_ena = '1' then
+
+ if hcnt(0) = '1' then
+ case hcnt(3 downto 1) is
+ when "110" => bg_code <= bg_ram_do;
+ when "111" => bg_attr <= bg_ram_do;
+ bg_code_r <= bg_code;
+ when others => null;
+ end case;
+
+ case hcnt(2 downto 1) xor (bg_attr(1) & bg_attr(1)) is
+ when "00" => bg_palette_addr <= bg_attr(4 downto 3) & bg_graphx2_do(7 downto 6) & bg_graphx1_do(7 downto 6);
+ when "01" => bg_palette_addr <= bg_attr(4 downto 3) & bg_graphx2_do(5 downto 4) & bg_graphx1_do(5 downto 4);
+ when "10" => bg_palette_addr <= bg_attr(4 downto 3) & bg_graphx2_do(3 downto 2) & bg_graphx1_do(3 downto 2);
+ when others => bg_palette_addr <= bg_attr(4 downto 3) & bg_graphx2_do(1 downto 0) & bg_graphx1_do(1 downto 0);
+ end case;
+ end if;
+
+ end if;
+
+ end if;
+end process;
+
+---------------------------
+-- mux char/sprite video --
+---------------------------
+palette_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 7) = X"FF"&'1' else '0'; -- 0xFF80-FFFF
+
+palette_addr <= cpu_addr(6 downto 1) when palette_we = '1' else bg_palette_addr when sp_vid(2 downto 0) = "000" else bg_attr(7 downto 6) & sp_vid;
+
+process (clock_vid)
+begin
+ if rising_edge(clock_vid) then
+ video_g <= palette_do(2 downto 0);
+ video_b <= palette_do(5 downto 3);
+ video_r <= palette_do(8 downto 6);
+ end if;
+end process;
+
+------------------------------
+-- components & sound board --
+------------------------------
+
+-- microprocessor Z80
+cpu : entity work.T80se
+generic map(Mode => 0, T2Write => 1, IOWait => 1)
+port map(
+ RESET_n => reset_n,
+ CLK_n => clock_vid,
+ CLKEN => cpu_ena,
+ WAIT_n => '1',
+ INT_n => cpu_irq_n,
+ NMI_n => '1', --cpu_nmi_n,
+ BUSRQ_n => '1',
+ M1_n => cpu_m1_n,
+ MREQ_n => cpu_mreq_n,
+ IORQ_n => cpu_ioreq_n,
+ RD_n => cpu_rd_n,
+ WR_n => cpu_wr_n,
+ RFSH_n => open,
+ HALT_n => open,
+ BUSAK_n => open,
+ A => cpu_addr,
+ DI => cpu_di,
+ DO => cpu_do
+);
+
+-- Z80-CTC (MK3882)
+z80ctc : entity work.z80ctc_top
+port map (
+ clock => clock_vid,
+ clock_ena => cpu_ena,
+ reset => reset,
+ din => cpu_do,
+ cpu_din => cpu_di,
+ dout => ctc_do,
+ ce_n => not ctc_ce,
+ cs => cpu_addr(1 downto 0),
+ m1_n => cpu_m1_n,
+ iorq_n => cpu_ioreq_n,
+ rd_n => cpu_rd_n,
+ int_n => cpu_irq_n,
+ trg0 => '0',
+ to0 => ctc_counter_1_trg,
+ trg1 => ctc_counter_1_trg,
+ to1 => open,
+ trg2 => '0',
+ to2 => open,
+ trg3 => ctc_counter_3_trg
+);
+
+-- cpu program ROM 0x0000-0xBFFF
+--rom_cpu : entity work.satans_hollow_cpu
+--port map(
+-- clk => clock_vidn,
+-- addr => cpu_addr(15 downto 0),
+-- data => cpu_rom_do
+--);
+cpu_rom_addr <= cpu_addr(15 downto 0);
+cpu_rom_rd <= '1' when cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_addr(15 downto 12) < X"C" else '0';
+
+-- working RAM 0xC000-0xC7FF + mirroring adresses
+wram : entity work.dpram
+generic map( dWidth => 8, aWidth => 11)
+port map(
+ clk_a => clock_vidn,
+ addr_a => cpu_addr(10 downto 0),
+ d_a => cpu_do,
+ we_a => wram_we,
+ q_a => wram_do,
+ clk_b => clock_vid,
+ we_b => cmos_wr,
+ addr_b => dl_addr(10 downto 0),
+ d_b => dl_data,
+ q_b => up_data
+);
+
+-- video RAM 0xE800-0xEFFF + mirroring adresses
+video_ram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 11)
+port map(
+ clk => clock_vidn,
+ we => bg_ram_we,
+ addr => bg_ram_addr,
+ d => cpu_do,
+ q => bg_ram_do
+);
+
+-- sprite RAM (no cpu access)
+sprite_ram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 9)
+port map(
+ clk => clock_vidn,
+ we => sp_ram_we,
+ addr => sp_ram_addr,
+ d => sp_ram_cache_do,
+ q => sp_ram_do
+);
+
+-- sprite RAM 0xE000-0xE1FF + mirroring adresses
+sprites_ram_cache : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 9)
+port map(
+ clk => clock_vidn,
+ we => sp_ram_cache_we,
+ addr => sp_ram_cache_addr,
+ d => cpu_do,
+ q => sp_ram_cache_do
+);
+
+-- sprite line buffer 1
+sprlinebuf1 : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 8)
+port map(
+ clk => clock_vidn,
+ we => sp_buffer_ram1_we,
+ addr => sp_buffer_ram1_addr,
+ d => sp_buffer_ram1_di,
+ q => sp_buffer_ram1_do
+);
+
+-- sprite line buffer 2
+sprlinebuf2 : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 8)
+port map(
+ clk => clock_vidn,
+ we => sp_buffer_ram2_we,
+ addr => sp_buffer_ram2_addr,
+ d => sp_buffer_ram2_di,
+ q => sp_buffer_ram2_do
+);
+
+-- background graphics ROM G3
+bg_graphics_1 : entity work.dpram
+generic map( dWidth => 8, aWidth => 13)
+port map(
+ clk_a => clock_vidn,
+ addr_a => bg_code_line,
+ q_a => bg_graphx1_do,
+ clk_b => clock_vid,
+ addr_b => dl_addr(12 downto 0),
+ we_b => bg_graphics_1_we,
+ d_b => dl_data
+);
+bg_graphics_1_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1000" else '0'; -- 10000-11FFF
+
+-- background graphics ROM G4
+bg_graphics_2 : entity work.dpram
+generic map( dWidth => 8, aWidth => 13)
+port map(
+ clk_a => clock_vidn,
+ addr_a => bg_code_line,
+ q_a => bg_graphx2_do,
+ clk_b => clock_vid,
+ addr_b => dl_addr(12 downto 0),
+ we_b => bg_graphics_2_we,
+ d_b => dl_data
+);
+bg_graphics_2_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1001" else '0'; -- 12000-13FFF
+
+-- sprite graphics ROM 1E/1D/1B/1A
+sprite_graphics : entity work.dpram
+generic map( dWidth => 8, aWidth => 15)
+port map(
+ clk_a => clock_vidn,
+ addr_a => sp_code_line_mux,
+ q_a => sp_graphx_do,
+ clk_b => clock_vid,
+ addr_b => not dl_addr(14) & dl_addr(13 downto 0),
+ we_b => sprite_graphics_we,
+ d_b => dl_data
+);
+sprite_graphics_we <= '1' when dl_wr = '1' and dl_addr(16) = '1' else '0'; -- 14000-1BFFF
+
+--satans_hollow_sound_board
+sound_board : entity work.satans_hollow_sound_board
+port map(
+ clock_40 => clock_40,
+ reset => reset,
+
+ main_cpu_addr => cpu_addr(7 downto 0),
+
+ ssio_iowe => ssio_iowe,
+ ssio_di => cpu_do,
+ ssio_do => ssio_do,
+
+ input_0 => input_0,
+ input_1 => input_1,
+ input_2 => input_2,
+ input_3 => input_3,
+ input_4 => input_4,
+
+ output_4 => output_4,
+
+ separate_audio => separate_audio,
+ audio_out_l => audio_out_l,
+ audio_out_r => audio_out_r,
+
+ cpu_rom_addr => snd_rom_addr,
+ cpu_rom_do => snd_rom_do,
+ cpu_rom_rd => snd_rom_rd,
+
+ dbg_cpu_addr => open --dbg_cpu_addr
+);
+
+-- background & sprite palette
+palette : entity work.gen_ram
+generic map( dWidth => 9, aWidth => 6)
+port map(
+ clk => clock_vidn,
+ we => palette_we,
+ addr => palette_addr,
+ d => cpu_addr(0) & cpu_do,
+ q => palette_do
+);
+
+end struct;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/satans_hollow_sound_board.vhd b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/satans_hollow_sound_board.vhd
new file mode 100644
index 00000000..00d63c11
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/satans_hollow_sound_board.vhd
@@ -0,0 +1,558 @@
+---------------------------------------------------------------------------------
+-- Kick_sound_board by Dar (darfpga@aol.fr) (19/10/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- gen_ram.vhd & io_ps2_keyboard
+--------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- T80/T80se - Version : 304
+-----------------------------
+-- Z80 compatible microprocessor core
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+---------------------------------------------------------------------------------
+-- YM2149 (AY-3-8910)
+-- Copyright (c) MikeJ - Jan 2005
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+--
+-- SOUND : 1xZ80 @ 2.0MHz CPU accessing its program rom, working ram, 2x-AY3-8910
+-- 8Kx8bits program rom
+-- 1Kx8bits working ram
+--
+-- 1xAY-3-8910
+-- 3 sound channels
+--
+-- 1xAY-3-8910
+-- 3 sound channels
+--
+-- 6 sound modulation (required 8MHz signal => 40MHz/5)
+-- 2 global volume control (not activated - not sure it was used for kick )
+--
+-- I/O :
+-- 4x8bits command registers from main cpu board (IRAM)
+-- 1x8bits status registers to main cpu board (STAT)
+-- 5x8bits input buffers to main cpu board (IP0-IP5)
+-- 2x8bits output registers from main cpu board (OP0/OP4)
+--
+---------------------------------------------------------------------------------
+-- Schematics remarks :
+-- Not sure global volume are used => both deactivated
+-- Not sure if global channels are mixed together or not => allow for
+-- external control mixed/separated
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity satans_hollow_sound_board is
+port(
+ clock_40 : in std_logic;
+ reset : in std_logic;
+
+ main_cpu_addr : in std_logic_vector(7 downto 0);
+
+ ssio_iowe : in std_logic;
+ ssio_di : in std_logic_vector(7 downto 0);
+ ssio_do : out std_logic_vector(7 downto 0);
+
+ input_0 : in std_logic_vector(7 downto 0);
+ input_1 : in std_logic_vector(7 downto 0);
+ input_2 : in std_logic_vector(7 downto 0);
+ input_3 : in std_logic_vector(7 downto 0);
+ input_4 : in std_logic_vector(7 downto 0);
+ output_4 : out std_logic_vector(7 downto 0);
+ separate_audio : in std_logic;
+
+ audio_out_l : out std_logic_vector(15 downto 0);
+ audio_out_r : out std_logic_vector(15 downto 0);
+ cpu_rom_addr : out std_logic_vector(13 downto 0);
+ cpu_rom_do : in std_logic_vector(7 downto 0);
+ cpu_rom_rd : out std_logic;
+ dbg_cpu_addr : out std_logic_vector(15 downto 0)
+ );
+end satans_hollow_sound_board;
+
+architecture struct of satans_hollow_sound_board is
+
+ signal reset_n : std_logic;
+ signal clock_snd : std_logic;
+ signal clock_sndn: std_logic;
+
+ signal clock_cnt1 : std_logic_vector(4 downto 0) := "00000";
+
+ signal cpu_ena : std_logic;
+ signal ena_4Mhz : std_logic;
+ signal clk_8Mhz : std_logic;
+
+ signal cpu_addr : std_logic_vector(15 downto 0);
+ signal cpu_di : std_logic_vector( 7 downto 0);
+ signal cpu_do : std_logic_vector( 7 downto 0);
+ signal cpu_wr_n : std_logic;
+ signal cpu_rd_n : std_logic;
+ signal cpu_mreq_n : std_logic;
+ signal cpu_ioreq_n : std_logic;
+ signal cpu_irq_n : std_logic;
+ signal cpu_m1_n : std_logic;
+
+
+ signal wram_we : std_logic;
+ signal wram_do : std_logic_vector( 7 downto 0);
+
+ signal iram_0_do : std_logic_vector( 7 downto 0);
+ signal iram_1_do : std_logic_vector( 7 downto 0);
+ signal iram_2_do : std_logic_vector( 7 downto 0);
+ signal iram_3_do : std_logic_vector( 7 downto 0);
+
+ signal ssio_status : std_logic_vector( 7 downto 0);
+
+ signal div_E11 : std_logic_vector(2 downto 0); -- binary counter 3msb of E11 - 74161
+ signal div_D11 : std_logic_vector(3 downto 0); -- decade counter - D11 - 74160
+ signal div_C12 : std_logic_vector(6 downto 0); -- stage ripple counter - C12 - MC140247
+ signal clr_int : std_logic;
+
+ signal ay1_audio_chan : std_logic_vector( 1 downto 0);
+ signal ay1_audio_muxed: std_logic_vector( 7 downto 0);
+ signal ay1_bc1 : std_logic;
+ signal ay1_bdir : std_logic;
+ signal ay1_do : std_logic_vector( 7 downto 0);
+ signal ay1_cs : std_logic;
+ signal ay1_port_a : std_logic_vector( 7 downto 0);
+ signal ay1_port_b : std_logic_vector( 7 downto 0);
+
+ signal ay2_audio_chan : std_logic_vector( 1 downto 0);
+ signal ay2_audio_muxed: std_logic_vector( 7 downto 0);
+ signal ay2_bc1 : std_logic;
+ signal ay2_bdir : std_logic;
+ signal ay2_do : std_logic_vector( 7 downto 0);
+ signal ay2_cs : std_logic;
+ signal ay2_port_a : std_logic_vector( 7 downto 0);
+ signal ay2_port_b : std_logic_vector( 7 downto 0);
+
+ signal ssio_82s123_addr : std_logic_vector(4 downto 0);
+ signal ssio_82s123_do : std_logic_vector(7 downto 0);
+ signal ssio_modulation_clock : std_logic;
+ signal ssio_modulation_clock_r : std_logic;
+ signal ssio_modulation_load : std_logic;
+ signal modulation_counter_a1 : std_logic_vector(3 downto 0);
+ signal modulation_counter_b1 : std_logic_vector(3 downto 0);
+ signal modulation_counter_c1 : std_logic_vector(3 downto 0);
+ signal modulation_counter_a2 : std_logic_vector(3 downto 0);
+ signal modulation_counter_b2 : std_logic_vector(3 downto 0);
+ signal modulation_counter_c2 : std_logic_vector(3 downto 0);
+
+ signal ch_a1 : std_logic_vector(7 downto 0);
+ signal ch_b1 : std_logic_vector(7 downto 0);
+ signal ch_c1 : std_logic_vector(7 downto 0);
+ signal ch_a2 : std_logic_vector(7 downto 0);
+ signal ch_b2 : std_logic_vector(7 downto 0);
+ signal ch_c2 : std_logic_vector(7 downto 0);
+
+ -- K volume data : 148 138 127 112 95 72 42 0
+ type bytes_array is array(0 to 7) of std_logic_vector(7 downto 0);
+ signal K_volume : bytes_array := (X"94",X"8A",X"7F",X"70",X"5F",X"48",X"2A",X"00");
+
+ signal volume_ch1 : std_logic_vector(7 downto 0);
+ signal volume_ch2 : std_logic_vector(7 downto 0);
+
+ signal snd_1 : std_logic_vector(17 downto 0);
+ signal snd_2 : std_logic_vector(17 downto 0);
+ signal snd_mono : std_logic_vector(18 downto 0);
+
+begin
+
+clock_snd <= clock_40;
+clock_sndn <= not clock_40;
+reset_n <= not reset;
+
+-- debug
+process (reset, clock_snd)
+begin
+ if rising_edge(clock_snd) and cpu_ena ='1' and cpu_mreq_n ='0' then
+ dbg_cpu_addr <= cpu_addr;
+ end if;
+end process;
+
+-- make enables clock from clock_snd
+process (clock_snd, reset)
+begin
+ if reset='1' then
+ clock_cnt1 <= (others=>'0');
+ clk_8Mhz <= '0';
+ else
+ if rising_edge(clock_snd) then
+ if clock_cnt1 = "10011" then -- divide by 20
+ clock_cnt1 <= (others=>'0');
+ else
+ clock_cnt1 <= clock_cnt1 + 1;
+ end if;
+
+ if clock_cnt1 = "10011" or
+ clock_cnt1 = "00100" or
+ clock_cnt1 = "01001" or
+ clock_cnt1 = "01110" then
+
+ clk_8Mhz <= not clk_8Mhz; -- (50% duty cycle)
+ end if;
+
+ end if;
+ end if;
+end process;
+--
+cpu_ena <= '1' when clock_cnt1 = "00000" else '0'; -- (2.0MHz)
+
+ena_4Mhz <= '1' when clock_cnt1 = "00000" or
+ clock_cnt1 = "01010" else '0'; -- (4.0MHz)
+
+------------------------------------------
+-- cpu data input with address decoding --
+------------------------------------------
+cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 14) = "00" else -- 0x0000-0x3FFF
+ wram_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"8" else -- 0x8000-0x83FF
+ iram_0_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9000" else
+ iram_1_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9001" else
+ iram_2_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9002" else
+ iram_3_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9003" else
+ ay1_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12)= X"A" else
+ ay2_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12)= X"B" else
+ x"FF" when cpu_mreq_n = '0' and cpu_addr(15 downto 12)= X"F" else -- 0xF000 (sw3 dip - D14)
+ X"FF";
+
+------------------------------------------
+-- write enable to working ram from CPU --
+------------------------------------------
+wram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"8" else '0'; -- 0x8000-0x83FF
+clr_int <= '1' when cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_addr(15 downto 12) = X"E" else '0'; -- 0xE000-0xEFFF
+
+ay1_cs <= '1' when cpu_mreq_n = '0' and (cpu_rd_n = '0' or cpu_wr_n = '0') and cpu_addr(15 downto 12) = X"A" else '0'; -- 0xA000-0xAFFF
+ay2_cs <= '1' when cpu_mreq_n = '0' and (cpu_rd_n = '0' or cpu_wr_n = '0') and cpu_addr(15 downto 12) = X"B" else '0'; -- 0xB000-0xBFFF
+
+ay1_bdir <= not (not ay1_cs or cpu_addr(0) );
+ay1_bc1 <= not (not ay1_cs or cpu_addr(1) );
+ay2_bdir <= not (not ay2_cs or cpu_addr(0) );
+ay2_bc1 <= not (not ay2_cs or cpu_addr(1) );
+
+ssio_do <= input_0 when main_cpu_addr(2 downto 0) = "000" else -- Input 0 -- players, coins, ...
+ input_1 when main_cpu_addr(2 downto 0) = "001" else -- Input 1
+ input_2 when main_cpu_addr(2 downto 0) = "010" else -- Input 2
+ input_3 when main_cpu_addr(2 downto 0) = "011" else -- Input 3 -- sw1 dip
+ input_4 when main_cpu_addr(2 downto 0) = "100" else -- Input 4
+ ssio_status when main_cpu_addr(2 downto 0) = "111" else -- ssio status
+ x"FF";
+
+process (clock_snd)
+begin
+ if rising_edge(clock_snd) then
+ if cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"C" then ssio_status <= cpu_do; end if; -- 0xC000-0xCFFF
+ end if;
+end process;
+
+------------------------------------------------------------------------
+-- Misc registers : interrupt, counters E11/D11/C12
+------------------------------------------------------------------------
+process (clock_snd, reset, clr_int, ena_4Mhz)
+begin
+ if reset = '1' then
+ div_E11 <= (others => '0'); -- 3msb of E11
+ div_D11 <= (others => '0'); -- decade counter
+ div_C12 <= (others => '0'); -- MC14024
+ else
+ if rising_edge(clock_snd) then
+
+ if ena_4Mhz = '1' then
+
+ div_E11 <= div_E11 + 1;
+
+ if div_E11 = "111" then
+ if div_D11 = "1001" then
+ div_D11 <= (others => '0');
+ else
+ div_D11 <= div_D11 + 1;
+ end if;
+
+ if div_D11 = "0100" then
+ div_C12 <= div_C12 + 1;
+ end if;
+
+ end if;
+
+ end if;
+
+ if clr_int = '1' then
+ div_C12 <= (others => '0');
+ end if;
+
+ end if;
+ end if;
+end process;
+
+cpu_irq_n <= not div_C12(6);
+
+-------------------------------
+-- sound modulation / volume --
+-------------------------------
+
+ssio_82s123_addr <= div_D11 & div_E11(2);
+
+--74166 8 bits shift register (D13)
+ssio_modulation_clock <= ssio_82s123_do(7-to_integer(unsigned(div_E11(1 downto 0) & clk_8Mhz)));
+ssio_modulation_load <= '1' when div_D11 = "1001" else '0';
+
+-- AY-3-8910 #1
+-- ch A (pin 4) modulated by counter controled by port A3-0 (pin 18->21)
+-- ch B (pin 3) modulated by counter controled by port A7-4 (pin 14->17)
+-- ch C (pin 38) modulated by counter controled by port B3-0 (pin 10->13)
+-- mute left and right port B7 (pin 6)
+-- volume#1 contoled by port B6-4 (pin 7->9)
+
+-- AY-3-8910 #2
+-- ch A (pin 4) modulated by counter controled by port A3-0 (pin 18->21)
+-- ch B (pin 3) modulated by counter controled by port A7-4 (pin 14->17)
+-- ch C (pin 38) modulated by counter controled by port B3-0 (pin 10->13)
+-- mute global port B7 (pin 6)
+-- volume#2 contoled by port B6-4 (pin 7->9)
+
+-- 4051 cmos mux (D5 and E3)
+-- CBA
+-- 000 => switch X0 (pin 13) ON others OFF
+-- 001 => switch X1 (pin 14) ON others OFF
+-- ...
+-- 111 => switch X7 (pin 4) ON others OFF
+
+-- Assuming R179 to R187 equivalent to
+--
+-- --------
+-- --------| R2 |-------- -- with R1 = 24k + n*4.7k
+-- ^ | -------- | ^ -- R2 = 24k
+-- | --- --- | -- R3 = (7-n)*4.7
+-- | | | | | | --
+-- Vin | | | R1 R3 | | | Vout -- n being 4051 CBA value
+-- | | | | | | --
+-- | --- --- | -- which gives
+-- | | | | -- Vout = Vin * (7-n)*4.7/(24+(7-n)*4.7)
+-- ------------------------
+--
+-- let : Vout = Vin * K(n) = Vin * (7-n)*4.7/(24+(7-n)*4.7) * 256
+--
+-- with K(n) = [148 138 127 112 95 72 42 0]
+--
+
+process (clock_snd, ssio_modulation_clock, ssio_modulation_load)
+begin
+ if rising_edge(clock_snd) then
+ ssio_modulation_clock_r <= ssio_modulation_clock;
+
+ if ssio_modulation_load = '1' then
+ modulation_counter_a1 <= ay1_port_a(3 downto 0);
+ modulation_counter_b1 <= ay1_port_a(7 downto 4);
+ modulation_counter_c1 <= ay1_port_b(3 downto 0);
+ modulation_counter_a2 <= ay2_port_a(3 downto 0);
+ modulation_counter_b2 <= ay2_port_a(7 downto 4);
+ modulation_counter_c2 <= ay2_port_b(3 downto 0);
+ else
+ if ssio_modulation_clock = '1' and ssio_modulation_clock_r = '0' then
+ if modulation_counter_a1 > X"0" then modulation_counter_a1 <= modulation_counter_a1 - 1; end if;
+ if modulation_counter_b1 > X"0" then modulation_counter_b1 <= modulation_counter_b1 - 1; end if;
+ if modulation_counter_c1 > X"0" then modulation_counter_c1 <= modulation_counter_c1 - 1; end if;
+ if modulation_counter_a2 > X"0" then modulation_counter_a2 <= modulation_counter_a2 - 1; end if;
+ if modulation_counter_b2 > X"0" then modulation_counter_b2 <= modulation_counter_b2 - 1; end if;
+ if modulation_counter_c2 > X"0" then modulation_counter_c2 <= modulation_counter_c2 - 1; end if;
+ end if;
+ end if;
+
+ case ay1_audio_chan is
+ when "00" => if modulation_counter_a1 = x"0" then ch_a1 <= ay1_audio_muxed; else ch_a1 <= (others => '0'); end if;
+ when "01" => if modulation_counter_b1 = x"0" then ch_b1 <= ay1_audio_muxed; else ch_b1 <= (others => '0'); end if;
+ when "10" => if modulation_counter_c1 = x"0" then ch_c1 <= ay1_audio_muxed; else ch_c1 <= (others => '0'); end if;
+ when others => null;
+ end case;
+
+ case ay2_audio_chan is
+ when "00" => if modulation_counter_a2 = x"0" then ch_a2 <= ay2_audio_muxed; else ch_a2 <= (others => '0'); end if;
+ when "01" => if modulation_counter_b2 = x"0" then ch_b2 <= ay2_audio_muxed; else ch_b2 <= (others => '0'); end if;
+ when "10" => if modulation_counter_c2 = x"0" then ch_c2 <= ay2_audio_muxed; else ch_c2 <= (others => '0'); end if;
+ when others => null;
+ end case;
+
+-- volume_ch1 <= K_volume(to_integer(unsigned(ay1_port_b(6 downto 4))));
+---- volume_ch2 <= K_volume(to_integer(unsigned(ay2_port_b(6 downto 4))));
+-- volume_ch2 <= K_volume(to_integer(unsigned(ay1_port_b(6 downto 4)))); -- use ch1 control otherwise ch2 is always OFF!
+
+ volume_ch1 <= X"FF"; -- finaly don't use volume controls
+ volume_ch2 <= X"FF";
+
+ if ay1_audio_chan = "00" then
+ snd_1 <= (("00"&ch_a1) + ("00"&ch_b1) + ("00"&ch_c1)) * volume_ch1;
+ end if;
+
+ if ay2_audio_chan = "00" then
+ snd_2 <= (("00"&ch_a2) + ("00"&ch_b2) + ("00"&ch_c2)) * volume_ch2;
+ end if;
+
+ end if;
+end process;
+
+snd_mono <= ('0'&snd_1) + ('0'&snd_2);
+
+audio_out_l <= snd_1(17 downto 2) when separate_audio = '1' else snd_mono(18 downto 3);
+audio_out_r <= snd_2(17 downto 2) when separate_audio = '1' else snd_mono(18 downto 3);
+
+------------------------------
+-- components & sound board --
+------------------------------
+
+-- microprocessor Z80
+cpu : entity work.T80se
+generic map(Mode => 0, T2Write => 1, IOWait => 1)
+port map(
+ RESET_n => reset_n,
+ CLK_n => clock_snd,
+ CLKEN => cpu_ena,
+ WAIT_n => '1',
+ INT_n => cpu_irq_n,
+ NMI_n => '1', --cpu_nmi_n,
+ BUSRQ_n => '1',
+ M1_n => cpu_m1_n,
+ MREQ_n => cpu_mreq_n,
+ IORQ_n => cpu_ioreq_n,
+ RD_n => cpu_rd_n,
+ WR_n => cpu_wr_n,
+ RFSH_n => open,
+ HALT_n => open,
+ BUSAK_n => open,
+ A => cpu_addr,
+ DI => cpu_di,
+ DO => cpu_do
+);
+
+-- cpu program ROM 0x0000-0x2FFF
+--rom_cpu : entity work.satans_hollow_sound_cpu
+--port map(
+-- clk => clock_sndn,
+-- addr => cpu_addr(13 downto 0),
+-- data => cpu_rom_do
+--);
+
+cpu_rom_addr <= cpu_addr(13 downto 0);
+cpu_rom_rd <= '1' when cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_addr(15 downto 14) = "00" else '0'; -- 0x0000-0x2FFF
+
+
+-- working RAM 0x8000-0x83FF
+wram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 10)
+port map(
+ clk => clock_sndn,
+ we => wram_we,
+ addr => cpu_addr(9 downto 0),
+ d => cpu_do,
+ q => wram_do
+);
+
+-- iram (command from main cpu to sound cpu)
+process (clock_snd, reset, ssio_iowe)
+begin
+ if reset = '1' then
+ iram_0_do <= (others => '0');
+ iram_1_do <= (others => '0');
+ iram_2_do <= (others => '0');
+ iram_3_do <= (others => '0');
+ output_4 <= (others => '0');
+ else
+ if rising_edge(clock_snd) then
+ if ssio_iowe = '1' and main_cpu_addr(7 downto 2) = "000001" then -- 0x04 - 0x07
+ output_4 <= ssio_di;
+ end if;
+ if ssio_iowe = '1' and main_cpu_addr(7 downto 2) = "000111" then -- 0x1C - 0x1F
+ case main_cpu_addr(1 downto 0) is
+ when "00" => iram_0_do <= ssio_di;
+ when "01" => iram_1_do <= ssio_di;
+ when "10" => iram_2_do <= ssio_di;
+ when "11" => iram_3_do <= ssio_di;
+ when others => null;
+ end case;
+ end if;
+ end if;
+ end if;
+end process;
+
+-- AY-3-8910 # 1
+ay_3_8910_1 : entity work.YM2149
+port map(
+ -- data bus
+ I_DA => cpu_do, -- in std_logic_vector(7 downto 0); -- pin 37 to 30
+ O_DA => ay1_do, -- out std_logic_vector(7 downto 0); -- pin 37 to 30
+ O_DA_OE_L => open, -- out std_logic;
+ -- control
+ I_A9_L => '0', -- in std_logic; -- pin 24
+ I_A8 => '1', -- in std_logic; -- pin 25
+ I_BDIR => ay1_bdir, -- in std_logic; -- pin 27
+ I_BC2 => '1', -- in std_logic; -- pin 28
+ I_BC1 => ay1_bc1, -- in std_logic; -- pin 29
+ I_SEL_L => '1', -- in std_logic;
+
+ O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0);
+ O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0);
+
+ -- port a
+ I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); -- pin 21 to 14
+ O_IOA => ay1_port_a, -- out std_logic_vector(7 downto 0); -- pin 21 to 14
+ O_IOA_OE_L => open, -- out std_logic;
+ -- port b
+ I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); -- pin 13 to 6
+ O_IOB => ay1_port_b, -- out std_logic_vector(7 downto 0); -- pin 13 to 6
+ O_IOB_OE_L => open, -- out std_logic;
+
+ ENA => cpu_ena, -- in std_logic; -- clock enable for higher speed operation
+ RESET_L => reset_n, -- in std_logic;
+ CLK => clock_snd -- in std_logic -- note 6 Mhz
+);
+
+
+-- AY-3-8910 # 2
+ay_3_8910_2 : entity work.YM2149
+port map(
+ -- data bus
+ I_DA => cpu_do, -- in std_logic_vector(7 downto 0); -- pin 37 to 30
+ O_DA => ay2_do, -- out std_logic_vector(7 downto 0); -- pin 37 to 30
+ O_DA_OE_L => open, -- out std_logic;
+ -- control
+ I_A9_L => '0', -- in std_logic; -- pin 24
+ I_A8 => '1', -- in std_logic; -- pin 25
+ I_BDIR => ay2_bdir, -- in std_logic; -- pin 27
+ I_BC2 => '1', -- in std_logic; -- pin 28
+ I_BC1 => ay2_bc1, -- in std_logic; -- pin 29
+ I_SEL_L => '1', -- in std_logic;
+
+ O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0);
+ O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0);
+
+ -- port a
+ I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0); -- pin 21 to 14
+ O_IOA => ay2_port_a, -- out std_logic_vector(7 downto 0); -- pin 21 to 14
+ O_IOA_OE_L => open, -- out std_logic;
+ -- port b
+ I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0); -- pin 13 to 6
+ O_IOB => ay2_port_b, -- out std_logic_vector(7 downto 0); -- pin 13 to 6
+ O_IOB_OE_L => open, -- out std_logic;
+
+ ENA => cpu_ena, -- in std_logic; -- clock enable for higher speed operation
+ RESET_L => reset_n, -- in std_logic;
+ CLK => clock_snd -- in std_logic -- note 6 Mhz
+);
+
+-- midway ssio sound modulation prom
+midssio : entity work.midssio_82s123
+port map(
+ clk => clock_sndn,
+ addr => ssio_82s123_addr,
+ data => ssio_82s123_do
+);
+
+end struct;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/sdram.sv b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..e99f4621
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/sdram.sv
@@ -0,0 +1,329 @@
+//
+// sdram.v
+//
+// sdram controller implementation for the MiST board
+// https://github.com/mist-devel/mist-board
+//
+// Copyright (c) 2013 Till Harbaum
+// Copyright (c) 2019 Gyorgy Szombathelyi
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+
+module sdram (
+
+ // interface to the MT48LC16M16 chip
+ inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
+ output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
+ output reg SDRAM_DQML, // two byte masks
+ output reg SDRAM_DQMH, // two byte masks
+ output reg [1:0] SDRAM_BA, // two banks
+ output SDRAM_nCS, // a single chip select
+ output SDRAM_nWE, // write enable
+ output SDRAM_nRAS, // row address select
+ output SDRAM_nCAS, // columns address select
+
+ // cpu/chipset interface
+ input init_n, // init signal after FPGA config to initialize RAM
+ input clk, // sdram clock
+
+ input port1_req,
+ output reg port1_ack,
+ input port1_we,
+ input [23:1] port1_a,
+ input [1:0] port1_ds,
+ input [15:0] port1_d,
+ output [15:0] port1_q,
+
+ input [15:1] cpu1_addr,
+ output reg [15:0] cpu1_q,
+
+ input port2_req,
+ output reg port2_ack,
+ input port2_we,
+ input [23:1] port2_a,
+ input [1:0] port2_ds,
+ input [15:0] port2_d,
+ output [15:0] port2_q,
+
+ input [15:1] snd_addr,
+ output reg [15:0] snd_q
+);
+
+parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
+
+localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
+localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
+localparam CAS_LATENCY = 3'd2; // 2/3 allowed
+localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
+
+localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
+
+// 64ms/8192 rows = 7.8us
+localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
+
+// ---------------------------------------------------------------------
+// ------------------------ cycle state machine ------------------------
+// ---------------------------------------------------------------------
+
+/*
+ SDRAM state machine for 2 bank interleaved access
+ 1 word burst, CL2
+cmd issued registered
+ 0 RAS0 cas1
+ 1 ras0
+ 2 CAS0 data1 returned
+ 3 RAS1 cas0
+ 4 ras1
+ 5 CAS1 data0 returned
+*/
+
+localparam STATE_RAS0 = 3'd0; // first state in cycle
+localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3
+localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
+localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7
+localparam STATE_READ1 = 3'd3;
+localparam STATE_LAST = 3'd5;
+
+reg [2:0] t;
+
+always @(posedge clk) begin
+ t <= t + 1'd1;
+ if (t == STATE_LAST) t <= STATE_RAS0;
+end
+
+// ---------------------------------------------------------------------
+// --------------------------- startup/reset ---------------------------
+// ---------------------------------------------------------------------
+
+// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
+// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
+reg [4:0] reset;
+reg init = 1'b1;
+always @(posedge clk, negedge init_n) begin
+ if(!init_n) begin
+ reset <= 5'h1f;
+ init <= 1'b1;
+ end else begin
+ if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
+ init <= !(reset == 0);
+ end
+end
+
+// ---------------------------------------------------------------------
+// ------------------ generate ram control signals ---------------------
+// ---------------------------------------------------------------------
+
+// all possible commands
+localparam CMD_INHIBIT = 4'b1111;
+localparam CMD_NOP = 4'b0111;
+localparam CMD_ACTIVE = 4'b0011;
+localparam CMD_READ = 4'b0101;
+localparam CMD_WRITE = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE = 4'b0010;
+localparam CMD_AUTO_REFRESH = 4'b0001;
+localparam CMD_LOAD_MODE = 4'b0000;
+
+reg [3:0] sd_cmd; // current command sent to sd ram
+reg [15:0] sd_din;
+// drive control signals according to current command
+assign SDRAM_nCS = sd_cmd[3];
+assign SDRAM_nRAS = sd_cmd[2];
+assign SDRAM_nCAS = sd_cmd[1];
+assign SDRAM_nWE = sd_cmd[0];
+
+reg [24:1] addr_latch[2];
+reg [24:1] addr_latch_next[2];
+reg [15:1] addr_last[2];
+reg [15:1] addr_last2[2];
+reg [15:0] din_latch[2];
+reg [1:0] oe_latch;
+reg [1:0] we_latch;
+reg [1:0] ds[2];
+
+localparam PORT_NONE = 2'd0;
+localparam PORT_CPU1 = 2'd1;
+localparam PORT_REQ = 2'd2;
+
+localparam PORT_SND = 2'd1;
+
+reg [2:0] next_port[2];
+reg [2:0] port[2];
+reg port1_state;
+reg port2_state;
+
+reg refresh;
+reg [10:0] refresh_cnt;
+wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
+
+// PORT1: bank 0,1
+always @(*) begin
+ if (refresh) begin
+ next_port[0] = PORT_NONE;
+ addr_latch_next[0] = addr_latch[0];
+ end else if (port1_req ^ port1_state) begin
+ next_port[0] = PORT_REQ;
+ addr_latch_next[0] = { 1'b0, port1_a };
+ end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
+ next_port[0] = PORT_CPU1;
+ addr_latch_next[0] = { 9'd0, cpu1_addr };
+ end else begin
+ next_port[0] = PORT_NONE;
+ addr_latch_next[0] = addr_latch[0];
+ end
+end
+
+// PORT2: bank 2,3
+always @(*) begin
+ if (port2_req ^ port2_state) begin
+ next_port[1] = PORT_REQ;
+ addr_latch_next[1] = { 1'b1, port2_a };
+ end else if (snd_addr != addr_last2[PORT_SND]) begin
+ next_port[1] = PORT_SND;
+ addr_latch_next[1] = { 1'b1, 8'd0, snd_addr };
+ end else begin
+ next_port[1] = PORT_NONE;
+ addr_latch_next[1] = addr_latch[1];
+ end
+end
+
+always @(posedge clk) begin
+
+ // permanently latch ram data to reduce delays
+ sd_din <= SDRAM_DQ;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ { SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
+ sd_cmd <= CMD_NOP; // default: idle
+ refresh_cnt <= refresh_cnt + 1'd1;
+
+ if(init) begin
+ // initialization takes place at the end of the reset phase
+ if(t == STATE_RAS0) begin
+
+ if(reset == 15) begin
+ sd_cmd <= CMD_PRECHARGE;
+ SDRAM_A[10] <= 1'b1; // precharge all banks
+ end
+
+ if(reset == 10 || reset == 8) begin
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+
+ if(reset == 2) begin
+ sd_cmd <= CMD_LOAD_MODE;
+ SDRAM_A <= MODE;
+ SDRAM_BA <= 2'b00;
+ end
+ end
+ end else begin
+ // RAS phase
+ // bank 0,1
+ if(t == STATE_RAS0) begin
+ addr_latch[0] <= addr_latch_next[0];
+ port[0] <= next_port[0];
+ { oe_latch[0], we_latch[0] } <= 2'b00;
+
+ if (next_port[0] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[0][22:10];
+ SDRAM_BA <= addr_latch_next[0][24:23];
+ addr_last[next_port[0]] <= addr_latch_next[0][15:1];
+ if (next_port[0] == PORT_REQ) begin
+ { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
+ ds[0] <= port1_ds;
+ din_latch[0] <= port1_d;
+ port1_state <= port1_req;
+ end else begin
+ { oe_latch[0], we_latch[0] } <= 2'b10;
+ ds[0] <= 2'b11;
+ end
+ end
+ end
+
+ // bank 2,3
+ if(t == STATE_RAS1) begin
+ refresh <= 1'b0;
+ addr_latch[1] <= addr_latch_next[1];
+ { oe_latch[1], we_latch[1] } <= 2'b00;
+ port[1] <= next_port[1];
+
+ if (next_port[1] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[1][22:10];
+ SDRAM_BA <= addr_latch_next[1][24:23];
+ addr_last2[next_port[1]] <= addr_latch_next[1][15:1];
+ if (next_port[1] == PORT_REQ) begin
+ { oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
+ ds[1] <= port2_ds;
+ din_latch[1] <= port2_d;
+ port2_state <= port2_req;
+ end else begin
+ { oe_latch[1], we_latch[1] } <= 2'b10;
+ ds[1] <= 2'b11;
+ end
+ end
+
+ if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
+ refresh <= 1'b1;
+ refresh_cnt <= 0;
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+ end
+
+ // CAS phase
+ if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
+ sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
+ if (we_latch[0]) begin
+ SDRAM_DQ <= din_latch[0];
+ port1_ack <= port1_req;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[0][24:23];
+ end
+
+ if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
+ sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+ if (we_latch[1]) begin
+ SDRAM_DQ <= din_latch[1];
+ port2_ack <= port2_req;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[1][24:23];
+ end
+
+ // Data returned
+ if(t == STATE_READ0 && oe_latch[0]) begin
+ case(port[0])
+ PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
+ PORT_CPU1: begin cpu1_q <= sd_din; end
+ default: ;
+ endcase;
+ end
+ if(t == STATE_READ1 && oe_latch[1]) begin
+ case(port[1])
+ PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end
+ PORT_SND: begin snd_q <= sd_din; end
+ default: ;
+ endcase;
+ end
+ end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/spinner.vhd b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/spinner.vhd
new file mode 100644
index 00000000..0bf503e0
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 2/TwoTigers_MiST/rtl/spinner.vhd
@@ -0,0 +1,46 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity spinner is
+port(
+ clock_40 : in std_logic;
+ reset : in std_logic;
+ btn_left : in std_logic;
+ btn_right : in std_logic;
+ btn_acc : in std_logic; -- speed up button
+ ctc_zc_to_2 : in std_logic;
+ spin_angle : out std_logic_vector(6 downto 0)
+);
+end spinner;
+
+architecture rtl of spinner is
+
+signal ctc_zc_to_2_r : std_logic;
+signal spin_count : std_logic_vector(9 downto 0);
+
+begin
+
+spin_angle <= spin_count(9 downto 3);
+
+process (clock_40, reset)
+begin
+ if reset = '1' then
+ spin_count <= (others => '0');
+ elsif rising_edge(clock_40) then
+ ctc_zc_to_2_r <= ctc_zc_to_2;
+
+ if ctc_zc_to_2_r ='0' and ctc_zc_to_2 = '1' then
+ if btn_acc = '0' then -- space -- speed up
+ if btn_left = '1' then spin_count <= spin_count - 20; end if; -- left
+ if btn_right = '1' then spin_count <= spin_count + 20; end if; -- right
+ else
+ if btn_left = '1' then spin_count <= spin_count - 40; end if;
+ if btn_right = '1' then spin_count <= spin_count + 40; end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+end rtl;
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