diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf
index 0c5f2290..071ae6c2 100644
--- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf	
+++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.qsf	
@@ -41,7 +41,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:07:52  FEBRUARY 01, 2013"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:src/build_id.tcl"
@@ -224,7 +224,8 @@ set_global_assignment -name VHDL_FILE src/bitmap1_ctl.vhd
 set_global_assignment -name VHDL_FILE src/i82c55.vhd
 set_global_assignment -name VERILOG_FILE src/keyboard.v
 set_global_assignment -name VHDL_FILE src/sprite_array.vhd
-set_global_assignment -name VHDL_FILE src/Clock.vhd
+set_global_assignment -name QIP_FILE src/Clock.qip
+set_global_assignment -name QIP_FILE src/pll_aud.qip
 set_global_assignment -name VHDL_FILE src/build_id.vhd
 set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
 set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.sdc b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.sdc
index 3fb2db8c..b0d94432 100644
--- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.sdc	
+++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/mpatrol.sdc	
@@ -53,6 +53,11 @@ set_time_format -unit ns -decimal_places 3
 
 create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
 
+set vid_clk   "Clock_inst|altpll_component|auto_generated|pll1|clk[1]"
+set game_clk  "Clock_inst|altpll_component|auto_generated|pll1|clk[0]"
+set aud_clk   "pll_aud_inst|altpll_component|auto_generated|pll1|clk[0]"
+set dac_clk   "pll_aud_inst|altpll_component|auto_generated|pll1|clk[1]"
+
 #**************************************************************
 # Create Generated Clock
 #**************************************************************
@@ -83,17 +88,20 @@ set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [ge
 # Set Output Delay
 #**************************************************************
 
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[2]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock [get_clocks $dac_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock [get_clocks $dac_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock [get_clocks $game_clk] 1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock [get_clocks $vid_clk]  1.000 [get_ports {VGA_*}]
+
 
 #**************************************************************
 # Set Clock Groups
 #**************************************************************
 
+set_clock_groups -asynchronous -group [get_clocks $game_clk] -group [get_clocks $aud_clk]
 set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {Clock_inst|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_aud_inst|altpll_component|auto_generated|pll1|clk[*]}]
 
 #**************************************************************
 # Set False Path
diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd
index 7313fdec..f616bfa8 100644
--- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd	
+++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/Clock.vhd	
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
@@ -149,13 +149,13 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 5400,
+		clk0_divide_by => 9,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 179,
+		clk0_multiply_by => 2,
 		clk0_phase_shift => "0",
 		clk1_divide_by => 9,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
+		clk1_multiply_by => 8,
 		clk1_phase_shift => "0",
 		clk2_divide_by => 9,
 		clk2_duty_cycle => 50,
@@ -239,14 +239,14 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1396"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.895000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "6.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -274,12 +274,12 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "185"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "8"
 -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "37"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.89500000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "6.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
@@ -333,13 +333,13 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5400"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "179"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd
index a85f82d6..7eacfefa 100644
--- a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd	
+++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/mpatrol.vhd	
@@ -38,6 +38,7 @@ architecture SYN of mpatrol is
   signal init       		: std_logic := '1';  
   signal clk_sys        : std_logic;
   signal clk_aud        : std_logic;
+  signal clk_dac        : std_logic;
   signal clk_vid        : std_logic;
   signal rst_audD       : std_logic;
   signal rst_aud        : std_logic;
@@ -107,11 +108,17 @@ begin
 
 --CLOCK
 Clock_inst : entity work.Clock
+	port map (
+		inclk0  => CLOCK_27,
+		c0      => clk_sys,    -- 6
+		c1      => clk_vid     -- 24
+	);
+
+pll_aud_inst : entity work.pll_aud
 	port map (
 		inclk0  => CLOCK_27,
 		c0      => clk_aud,    -- 3.58/4
-		c1      => clk_sys,    -- 6
-		c2      => clk_vid     -- 24
+		c1      => clk_dac     -- clk_aud * 100
 	);
 
 	clkrst_i.clk(0)	<=	clk_sys;
@@ -240,7 +247,7 @@ dac : entity work.dac
 		C_bits    => 12
 	)
 	port map (
-		clk_i     => clk_aud,
+		clk_i     => clk_dac,
 		res_n_i   => not rst_aud,
 		dac_i     => audio_out,
 		dac_o     => audio
diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pll_aud.qip b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pll_aud.qip
new file mode 100644
index 00000000..7f9f1053
--- /dev/null
+++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pll_aud.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_aud.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_aud.ppf"]
diff --git a/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pll_aud.vhd b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pll_aud.vhd
new file mode 100644
index 00000000..8988613f
--- /dev/null
+++ b/Arcade_MiST/IremM52 Hardware/MoonPatrol_MIST/src/pll_aud.vhd	
@@ -0,0 +1,397 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_aud.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_aud IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_aud;
+
+
+ARCHITECTURE SYN OF pll_aud IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire6_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire6_bv(0 DOWNTO 0) <= "0";
+	sub_wire6    <= To_stdlogicvector(sub_wire6_bv);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	sub_wire4    <= inclk0;
+	sub_wire5    <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 5400,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 179,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 54,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 179,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_aud",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire5,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.895000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "89.500000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.89500000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "89.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_aud.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5400"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "179"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "179"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/TraverseUSA_MiST.qsf b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/TraverseUSA_MiST.qsf
index 33433b50..2554f240 100644
--- a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/TraverseUSA_MiST.qsf	
+++ b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/TraverseUSA_MiST.qsf	
@@ -188,7 +188,8 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/TraverseUSA_MiST.sv
 set_global_assignment -name VHDL_FILE rtl/traverse_usa.vhd
 set_global_assignment -name VHDL_FILE rtl/moon_patrol_sound_board.vhd
 set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
+set_global_assignment -name QIP_FILE rtl/pll_mist.qip
+set_global_assignment -name QIP_FILE rtl/pll_aud.qip
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/TraverseUSA_MiST.sdc b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/TraverseUSA_MiST.sdc
index 405fa6c6..cfb8f90b 100644
--- a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/TraverseUSA_MiST.sdc	
+++ b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/TraverseUSA_MiST.sdc	
@@ -53,6 +53,11 @@ set_time_format -unit ns -decimal_places 3
 
 create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
 
+set game_clk  "pll|altpll_component|auto_generated|pll1|clk[0]"
+set sdram_clk  "pll|altpll_component|auto_generated|pll1|clk[0]"
+set aud_clk   "pll_aud|altpll_component|auto_generated|pll1|clk[0]"
+set dac_clk   "pll_aud|altpll_component|auto_generated|pll1|clk[1]"
+
 #**************************************************************
 # Create Generated Clock
 #**************************************************************
@@ -79,27 +84,29 @@ set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [ge
 set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
 set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
 
-set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]]
-set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]]
 
 #**************************************************************
 # Set Output Delay
 #**************************************************************
 
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {AUDIO_L}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {AUDIO_R}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
-set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+set_output_delay -add_delay  -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock [get_clocks $dac_clk]   1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock [get_clocks $dac_clk]   1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock [get_clocks $game_clk]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock [get_clocks $game_clk]  1.000 [get_ports {VGA_*}]
 
-set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
 
 #**************************************************************
 # Set Clock Groups
 #**************************************************************
 
 set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_aud|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks $game_clk] -group [get_clocks $aud_clk]
 
 #**************************************************************
 # Set False Path
@@ -114,8 +121,6 @@ set_false_path -to [get_ports {SDRAM_CLK}]
 set_multicycle_path -to {VGA_*[*]} -setup 2
 set_multicycle_path -to {VGA_*[*]} -hold 1
 
-set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 2
-set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -hold 1
 
 #**************************************************************
 # Set Maximum Delay
diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/TraverseUSA_MiST.sv b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/TraverseUSA_MiST.sv
index c7963b9a..7753678a 100644
--- a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/TraverseUSA_MiST.sv	
+++ b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/TraverseUSA_MiST.sv	
@@ -94,16 +94,22 @@ assign AUDIO_R = AUDIO_L;
 assign SDRAM_CLK = clk_sys;
 assign SDRAM_CKE = 1;
 
-wire clk_sys, clk_aud;
+wire clk_sys, clk_aud, clk_dac;
 wire pll_locked;
 pll_mist pll(
 	.inclk0(CLOCK_27),
 	.areset(0),
 	.c0(clk_sys),
-	.c1(clk_aud),
 	.locked(pll_locked)
 	);
 
+pll_aud pll_aud(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clk_aud),
+	.c1(clk_dac)
+	);
+
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
@@ -142,8 +148,9 @@ user_io(
 wire [14:0] cart_addr;
 wire [15:0] sdram_do;
 wire        cart_rd;
-wire [12:0] snd_addr;
+wire [12:0] snd_addr, snd_rom_addr;
 wire [15:0] snd_do;
+wire        snd_vma, snd_vma_r, snd_vma_r2;
 
 wire        ioctl_downl;
 wire  [7:0] ioctl_index;
@@ -213,6 +220,11 @@ always @(posedge clk_sys) begin
 			port2_req <= ~port2_req;
 		end
 	end
+
+	// async clock domain crossing here (clk_aud -> clk_sys)
+	snd_vma_r <= snd_vma;
+	snd_vma_r2 <= snd_vma_r;
+	if (snd_vma_r2) snd_addr <= snd_rom_addr;
 end
 
 reg reset = 1;
@@ -235,7 +247,7 @@ wire  [1:0] r;
 traverse_usa traverse_usa (
 	.clock_36     ( clk_sys         ),
 	.clock_0p895  ( clk_aud         ),
-	.reset        ( reset 				  ),
+	.reset        ( reset           ),
 
 	.palmode      ( pal             ),
 	.shtrider     ( shtrider        ),
@@ -269,8 +281,9 @@ traverse_usa traverse_usa (
 	.cpu_rom_addr ( cart_addr       ),
 	.cpu_rom_do   ( cart_addr[0] ? sdram_do[15:8] : sdram_do[7:0] ),
 	.cpu_rom_rd   ( cart_rd         ),
-	.snd_rom_addr ( snd_addr        ),
-	.snd_rom_do   ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ),
+	.snd_rom_addr ( snd_rom_addr    ),
+	.snd_rom_do   ( snd_rom_addr[0] ? snd_do[15:8] : snd_do[7:0] ),
+	.snd_rom_vma  ( snd_vma         ),
 	.dl_addr      ( ioctl_addr[16:0]),
 	.dl_data      ( ioctl_dout      ),
 	.dl_wr        ( ioctl_wr        )
@@ -303,8 +316,8 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
 dac #(
 	.C_bits(11))
 dac(
-	.clk_i(clk_aud),
-	.res_n_i(~reset),
+	.clk_i(clk_dac),
+	.res_n_i(1'b1),
 	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/moon_patrol_sound_board.vhd b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/moon_patrol_sound_board.vhd
index da6dc19b..095b17e8 100644
--- a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/moon_patrol_sound_board.vhd	
+++ b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/moon_patrol_sound_board.vhd	
@@ -34,6 +34,7 @@ port(
 
  rom_addr     : out std_logic_vector(12 downto 0);
  rom_do       : in  std_logic_vector( 7 downto 0);
+ rom_vma      : out std_logic;
 
  dbg_cpu_addr : out std_logic_vector(15 downto 0)
 );
@@ -51,6 +52,7 @@ architecture struct of moon_patrol_sound_board is
  signal cpu_rw     : std_logic;
  signal cpu_irq    : std_logic;
  signal cpu_nmi    : std_logic;
+ signal cpu_vma    : std_logic;
  
  signal irqraz_cs : std_logic;
  signal irqraz_we : std_logic;
@@ -232,7 +234,7 @@ begin
 end process;
 
 -- adcpm clocks and computation -- make 24kHz and vclk 8/6/4kHz
-adpcm_clocks : process(clock_E, ay1_port_b_do)
+adpcm_clocks : process(reset, clock_E)
 	variable clock_div_a : integer range 0 to 148 := 0;
 	variable clock_div_b : integer range 0 to 5 := 0;
 	variable step   : integer range  0 to 48;
@@ -311,10 +313,10 @@ audio_out <= audio(12 downto 1);
 -- microprocessor 6800/01/03
 main_cpu : entity work.cpu68
 port map(	
-	clk      => clock_E,   -- E clock input (falling edge)
+	clk      => clock_E,  -- E clock input (falling edge)
 	rst      => reset,    -- reset input (active high)
 	rw       => cpu_rw,   -- read not write output
-	vma      => open,     -- valid memory address (active high)
+	vma      => cpu_vma,  -- valid memory address (active high)
 	address  => cpu_addr, -- address bus output
 	data_in  => cpu_di,   -- data bus input
 	data_out => cpu_do,   -- data bus output
@@ -334,6 +336,7 @@ port map(
 -- data => rom_do
 --);
 rom_addr <= cpu_addr(12 downto 0);
+rom_vma <= rom_cs and cpu_vma;
 
 -- cpu wram
 cpu_ram : entity work.gen_ram
diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_aud.qip b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_aud.qip
new file mode 100644
index 00000000..7f9f1053
--- /dev/null
+++ b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_aud.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_aud.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_aud.ppf"]
diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_aud.vhd b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_aud.vhd
new file mode 100644
index 00000000..8988613f
--- /dev/null
+++ b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_aud.vhd	
@@ -0,0 +1,397 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_aud.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_aud IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_aud;
+
+
+ARCHITECTURE SYN OF pll_aud IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire6_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire6_bv(0 DOWNTO 0) <= "0";
+	sub_wire6    <= To_stdlogicvector(sub_wire6_bv);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	sub_wire4    <= inclk0;
+	sub_wire5    <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 5400,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 179,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 54,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 179,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_aud",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire5,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.895000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "89.500000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.89500000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "89.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_aud.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5400"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "179"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "179"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_aud_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_mist.qip b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_mist.qip
new file mode 100644
index 00000000..d4720390
--- /dev/null
+++ b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_mist.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_mist.vhd b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_mist.vhd
index 7afa03b7..48c2358a 100644
--- a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_mist.vhd	
+++ b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/pll_mist.vhd	
@@ -45,7 +45,6 @@ ENTITY pll_mist IS
 		areset		: IN STD_LOGIC  := '0';
 		inclk0		: IN STD_LOGIC  := '0';
 		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
 		locked		: OUT STD_LOGIC 
 	);
 END pll_mist;
@@ -53,14 +52,13 @@ END pll_mist;
 
 ARCHITECTURE SYN OF pll_mist IS
 
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (4 DOWNTO 0);
 	SIGNAL sub_wire2	: STD_LOGIC ;
 	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire6_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -71,10 +69,6 @@ ARCHITECTURE SYN OF pll_mist IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
 		compensate_clock		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
@@ -135,15 +129,13 @@ ARCHITECTURE SYN OF pll_mist IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire6_bv(0 DOWNTO 0) <= "0";
-	sub_wire6    <= To_stdlogicvector(sub_wire6_bv);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	locked    <= sub_wire2;
-	c0    <= sub_wire3;
-	sub_wire4    <= inclk0;
-	sub_wire5    <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	locked    <= sub_wire0;
+	sub_wire2    <= sub_wire1(0);
+	c0    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
 
 	altpll_component : altpll
 	GENERIC MAP (
@@ -152,10 +144,6 @@ BEGIN
 		clk0_duty_cycle => 50,
 		clk0_multiply_by => 41,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 1200,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 41,
-		clk1_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
 		intended_device_family => "Cyclone III",
@@ -189,7 +177,7 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
 		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
@@ -209,9 +197,9 @@ BEGIN
 	)
 	PORT MAP (
 		areset => areset,
-		inclk => sub_wire5,
-		clk => sub_wire0,
-		locked => sub_wire2
+		inclk => sub_wire4,
+		locked => sub_wire0,
+		clk => sub_wire1
 	);
 
 
@@ -238,11 +226,8 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "30"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1200"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.900002"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.922500"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -263,26 +248,18 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "41"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.86400000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.89500000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -305,14 +282,11 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -321,10 +295,6 @@ END SYN;
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1200"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "41"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -357,7 +327,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -378,14 +348,12 @@ END SYN;
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
diff --git a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/traverse_usa.vhd b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/traverse_usa.vhd
index 2cf28dde..93c92276 100644
--- a/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/traverse_usa.vhd	
+++ b/Arcade_MiST/IremM52 Hardware/TraverseUSA_MiST/rtl/traverse_usa.vhd	
@@ -148,6 +148,7 @@ port(
  cpu_rom_rd     : out std_logic;
  snd_rom_addr   : out std_logic_vector(12 downto 0);
  snd_rom_do     : in  std_logic_vector( 7 downto 0);
+ snd_rom_vma    : out std_logic;
  
  dl_addr        : in  std_logic_vector(16 downto 0);
  dl_data        : in  std_logic_vector( 7 downto 0);
@@ -675,6 +676,7 @@ port map(
 
  rom_addr     => snd_rom_addr,
  rom_do       => snd_rom_do,
+ rom_vma      => snd_rom_vma,
 
  dbg_cpu_addr => open --dbg_cpu_addr
 );