From 2aeee7f0b17497924ed5d30c0caa70ff71079ff8 Mon Sep 17 00:00:00 2001
From: Gehstock <marceljenke@gmail.com>
Date: Sat, 9 Feb 2019 15:36:17 +0100
Subject: [PATCH] Some Changes

---
 .../Sprint2_MiST/README.txt                   |    3 +-
 .../Sprint2_MiST/Release/sprint2.rbf          |  Bin 0 -> 252470 bytes
 .../Sprint2_MiST/rtl/cpu_mem.vhd              |   69 +-
 .../Sprint2_MiST/rtl/dac.sv                   |    2 +-
 .../Sprint2_MiST/rtl/gearshift.sv             |   94 +
 .../Sprint2_MiST/rtl/joy2quad.sv              |  100 +
 .../Sprint2_MiST/rtl/motion.vhd               |   43 +-
 .../Sprint2_MiST/rtl/playfield.vhd            |   43 +-
 .../Sprint2_MiST/rtl/pll.v                    |    2 +-
 .../Sprint2_MiST/rtl/roms/Char_LSB.qip        |    3 -
 .../Sprint2_MiST/rtl/roms/Char_LSB.vhd        |  141 -
 .../Sprint2_MiST/rtl/roms/Char_MSB.qip        |    3 -
 .../Sprint2_MiST/rtl/roms/Char_MSB.vhd        |  141 -
 .../Sprint2_MiST/rtl/roms/addec_prom.qip      |    3 -
 .../Sprint2_MiST/rtl/roms/addec_prom.vhd      |  141 -
 .../Sprint2_MiST/rtl/roms/j6_prom.qip         |    3 -
 .../Sprint2_MiST/rtl/roms/j6_prom.vhd         |  141 -
 .../Sprint2_MiST/rtl/roms/k6_prom.qip         |    3 -
 .../Sprint2_MiST/rtl/roms/k6_prom.vhd         |  141 -
 .../Sprint2_MiST/rtl/roms/prog_rom1.qip       |    3 -
 .../Sprint2_MiST/rtl/roms/prog_rom1.vhd       |  141 -
 .../Sprint2_MiST/rtl/roms/prog_rom2.qip       |    3 -
 .../Sprint2_MiST/rtl/roms/prog_rom2.vhd       |  141 -
 .../Sprint2_MiST/rtl/roms/prog_rom3.qip       |    3 -
 .../Sprint2_MiST/rtl/roms/prog_rom3.vhd       |  141 -
 .../Sprint2_MiST/rtl/roms/prog_rom4.qip       |    3 -
 .../Sprint2_MiST/rtl/roms/prog_rom4.vhd       |  141 -
 .../Sprint2_MiST/rtl/roms/sync_prom.qip       |    3 -
 .../Sprint2_MiST/rtl/roms/sync_prom.vhd       |  141 -
 .../Sprint2_MiST/rtl/sprint1.vhd              |  313 --
 .../Sprint2_MiST/rtl/sprint2.vhd              |   14 +-
 .../Sprint2_MiST/rtl/sprint2_mist.sv          |  144 +-
 .../Sprint2_MiST}/rtl/sprom.vhd               |    0
 .../Sprint2_MiST/rtl/sync.vhd                 |   14 +-
 .../Sprint2_MiST/snapshot/sprint2.rbf         |  Bin 251840 -> 0 bytes
 .../Sprint2_MiST/sprint2.qsf                  |   13 +-
 .../SprintOne_MiST/README.txt                 |    3 +-
 .../SprintOne_MiST/Release/sprint1.rbf        |  Bin 0 -> 251539 bytes
 .../SprintOne_MiST/rtl/gearshift.sv           |   94 +
 .../SprintOne_MiST/rtl/joy2quad.sv            |  100 +
 .../SprintOne_MiST/rtl/sprint1.vhd            |    2 -
 .../SprintOne_MiST/rtl/sprint1_mist.sv        |   70 +-
 .../SprintOne_MiST/snapshot/sprint1.rbf       |  Bin 250642 -> 0 bytes
 .../SprintOne_MiST/sprint1.qsf                |    2 +
 .../SuperBreakout_MiST/SuperBreakout.srf      |   10 +
 .../rtl/super_breakout_mist.sv                |   32 +-
 .../UltraTank_MiST/rtl/keyboard.sv            |    2 -
 .../UltraTank_MiST/rtl/ultratank_mist.sv      |   72 +-
 .../UltraTank_MiST/ultratank.srf              |    5 +
 .../rtl/address_decoder.sv                    |    2 +-
 .../rtl/programm_memory.sv                    |    6 +-
 .../KingBaloon_MiST/Release/KingBaloon.rbf    |  Bin 0 -> 308524 bytes
 .../KingBaloon_MiST/Snapshot/KingBaloon.rbf   |  Bin 312140 -> 0 bytes
 .../rtl/ROM/{prom.hex => col.hex}             |    0
 .../rtl/ROM/{GALAXIAN_1H.hex => h.hex}        |    0
 .../rtl/ROM/{GALAXIAN_1K.hex => k.hex}        |    0
 .../rtl/ROM/{kb_prog.hex => prog.hex}         |    0
 .../KingBaloon_MiST/rtl/build_id.v            |    4 +-
 .../KingBaloon_MiST/rtl/kingballon.vhd        |   12 +-
 .../KingBaloon_MiST/rtl/mc_col_pal.vhd        |    9 +-
 .../KingBaloon_MiST/rtl/mc_video.vhd          |   20 +-
 .../Midway8080v2_MiST/rtl/invaders_memory.sv  |    8 +-
 .../rtl/roms/BlueShark/blueshrk_f.hex         |  129 +
 .../rtl/roms/BlueShark/blueshrk_g.hex         |  129 +
 .../rtl/roms/BlueShark/blueshrk_h.hex         |  129 +
 .../Midway8080v2_Mist/Invaders.qsf            |    2 +-
 .../Midway8080v2_Mist/rtl/Invaders_mist.sv    |   15 +-
 .../Midway8080v2_Mist/rtl/build_id.v          |    4 +-
 .../Midway8080v2_Mist/rtl/invaders.vhd        |   10 +-
 .../Midway8080v2_Mist/rtl/invaders_video.vhd  |    9 +-
 .../Jupiter Cantab - JupiterACE_MiST/ace.qsf  |   45 +-
 .../rtl/T80/T80.vhd                           | 1175 +++++++
 .../rtl/T80/T80_ALU.vhd                       |  376 +++
 .../rtl/T80/T80_MCode.vhd                     | 2035 ++++++++++++
 .../rtl/T80/T80_Reg.vhd                       |  152 +
 .../rtl/T80/T80pa.vhd                         |  216 ++
 .../rtl/T80/tv80_alu.v                        |  442 ---
 .../rtl/T80/tv80_core.v                       | 1351 --------
 .../rtl/T80/tv80_mcode.v                      | 2724 -----------------
 .../rtl/T80/tv80_reg.v                        |   68 -
 .../rtl/T80/tv80n.v                           |  182 --
 .../rtl/ace.mif                               |  353 +++
 .../rtl/ace_mist.sv                           |  235 +-
 .../rtl/build_id.v                            |    4 +-
 .../rtl/dpram.v                               |   80 +
 .../rtl/jupiter_ace.v                         |  431 +--
 .../rtl/keyboard.v                            |  843 ++---
 .../rtl/mist_io.v                             |  385 ++-
 .../rtl/pll.qip                               |    2 +-
 .../rtl/pll.v                                 |  120 +-
 .../rtl/sprom.vhd                             |   82 +
 .../rtl/video.sv                              |   75 +
 Computer_MiST/ORAO_MiST/db/Orao_MiST.db_info  |    3 +
 .../Release/mz80k_mist.rbf                    |  Bin
 .../clean.bat                                 |    0
 .../mz80k_mist.qpf                            |    0
 .../mz80k_mist.qsf                            |    0
 .../mz80k_mist.srf                            |    0
 .../rtl/CPLD_74LS245.vhd                      |    0
 .../rtl/Color_Card.sv                         |    0
 .../rtl/HighResCard.sv                        |    0
 .../rtl/TTL74LS245.sv                         |    0
 .../rtl/TTL74LS373.sv                         |    0
 .../rtl/build_id.tcl                          |    0
 .../rtl/build_id.v                            |    0
 .../rtl/cg_rom.v                              |    0
 .../rtl/fz80.v                                |    0
 .../rtl/fz80c.v                               |    0
 .../rtl/hq2x.sv                               |    0
 .../rtl/i8253.v                               |    0
 .../rtl/i8255.vhd                             |    0
 .../rtl/keymatrix.vhd                         |    0
 .../rtl/mist_io.v                             |    0
 .../rtl/monrom.v                              |    0
 .../rtl/mz80k_mist.sv                         |    0
 .../rtl/mz80k_top.v                           |    0
 .../rtl/osd.v                                 |    0
 .../rtl/pll.v                                 |    0
 .../rtl/ram2.v                                |    0
 .../rtl/roms/80ktc.zip                        |  Bin
 .../rtl/roms/CG.ROM                           |  Bin
 .../rtl/roms/MZ80K2E Jap CG                   |  Bin
 .../rtl/roms/MZ80K2E Jap CG.zip               |  Bin
 .../rtl/roms/MZ80K2E ROM                      |  Bin
 .../rtl/roms/MZ80K2E ROM.zip                  |  Bin
 .../rtl/roms/Mon.hex                          |    0
 .../rtl/roms/cg.hex                           |    0
 .../rtl/roms/cg_jp.HEX                        |    0
 .../rtl/roms/cg_jp_hex.hex                    |    0
 .../rtl/roms/cgrom.v                          |    0
 .../rtl/roms/combined_keymap.mif              |    0
 .../rtl/roms/mon_jp.HEX                       |    0
 .../rtl/roms/mon_rom_jp.hex.hex               |    0
 .../rtl/roms/mram.v                           |    0
 .../rtl/roms/newMon.hex                       |    0
 .../rtl/roms/ram.v                            |    0
 .../rtl/scandoubler.v                         |    0
 .../rtl/sigma_delta_dac.v                     |    0
 .../rtl/sound.v                               |    0
 .../rtl/spram.vhd                             |    0
 .../Sharp - MZ-80_MiST_New/rtl/sprom.vhd      |   82 +
 .../rtl/vga.v                                 |    0
 .../rtl/video_mixer.sv                        |    0
 .../suc_hires2.jpg                            |  Bin
 144 files changed, 6636 insertions(+), 7999 deletions(-)
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/Release/sprint2.rbf
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/gearshift.sv
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/joy2quad.sv
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_LSB.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_LSB.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_MSB.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_MSB.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/addec_prom.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/addec_prom.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/j6_prom.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/j6_prom.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/k6_prom.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/k6_prom.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom1.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom1.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom2.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom2.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom3.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom3.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom4.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom4.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/sync_prom.qip
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/sync_prom.vhd
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint1.vhd
 rename {Computer_MiST/Sharp - MZ-80K_MiST => Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST}/rtl/sprom.vhd (100%)
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/snapshot/sprint2.rbf
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/Release/sprint1.rbf
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/gearshift.sv
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/joy2quad.sv
 delete mode 100644 Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/snapshot/sprint1.rbf
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/SuperBreakout.srf
 create mode 100644 Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/ultratank.srf
 create mode 100644 Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/Release/KingBaloon.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/Snapshot/KingBaloon.rbf
 rename Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/{prom.hex => col.hex} (100%)
 rename Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/{GALAXIAN_1H.hex => h.hex} (100%)
 rename Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/{GALAXIAN_1K.hex => k.hex} (100%)
 rename Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/{kb_prog.hex => prog.hex} (100%)
 create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_f.hex
 create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_g.hex
 create mode 100644 Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_h.hex
 create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80.vhd
 create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_ALU.vhd
 create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_MCode.vhd
 create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_Reg.vhd
 create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80pa.vhd
 delete mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_alu.v
 delete mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_core.v
 delete mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_mcode.v
 delete mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_reg.v
 delete mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80n.v
 create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.mif
 create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/dpram.v
 create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/sprom.vhd
 create mode 100644 Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/video.sv
 create mode 100644 Computer_MiST/ORAO_MiST/db/Orao_MiST.db_info
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/Release/mz80k_mist.rbf (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/clean.bat (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/mz80k_mist.qpf (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/mz80k_mist.qsf (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/mz80k_mist.srf (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/CPLD_74LS245.vhd (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/Color_Card.sv (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/HighResCard.sv (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/TTL74LS245.sv (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/TTL74LS373.sv (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/build_id.tcl (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/build_id.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/cg_rom.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/fz80.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/fz80c.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/hq2x.sv (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/i8253.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/i8255.vhd (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/keymatrix.vhd (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/mist_io.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/monrom.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/mz80k_mist.sv (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/mz80k_top.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/osd.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/pll.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/ram2.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/80ktc.zip (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/CG.ROM (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/MZ80K2E Jap CG (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/MZ80K2E Jap CG.zip (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/MZ80K2E ROM (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/MZ80K2E ROM.zip (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/Mon.hex (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/cg.hex (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/cg_jp.HEX (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/cg_jp_hex.hex (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/cgrom.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/combined_keymap.mif (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/mon_jp.HEX (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/mon_rom_jp.hex.hex (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/mram.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/newMon.hex (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/roms/ram.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/scandoubler.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/sigma_delta_dac.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/sound.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/spram.vhd (100%)
 create mode 100644 Computer_MiST/Sharp - MZ-80_MiST_New/rtl/sprom.vhd
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/vga.v (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/rtl/video_mixer.sv (100%)
 rename Computer_MiST/{Sharp - MZ-80K_MiST => Sharp - MZ-80_MiST_New}/suc_hires2.jpg (100%)

diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/README.txt b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/README.txt
index 79fe7910..8a8bf8a2 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/README.txt	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/README.txt	
@@ -14,5 +14,4 @@
 -- Joystick support.
 -- 
 -- 
----------------------------------------------------------------------------------
-todo: Fix Controls
\ No newline at end of file
+----------------------------------------------------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/Release/sprint2.rbf b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/Release/sprint2.rbf
new file mode 100644
index 0000000000000000000000000000000000000000..f53b67969c09922002be93f88496ed3a1756b06c
GIT binary patch
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z^UOEC@z4MKwQoN2jc331wSW2gGhhG4GhYY323*%Tc}4%ff9e4V(0kVPSvWHalym4U
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zjPUtmV`nUWL%@PZW;uI?%*meJgexa8=w)-4vsz(w*7fq`IBJ{TIgs!B({7*V7tG^T
z;@#^vdhX|WG*;1*dSR_Se~tp+bl;?iouLrqJZ6`VkJ%>P+9W7+lfX6?xM%6mA~EZf
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zYb>#rit2Xq&^$I38U-oXL!9ke9XD9)k&yCvUs#+E--cbV3>8c9vB#FVHE!lOtAUX<
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zGW5dGsNhrZ)Y$>Z-7ssEH<W^4B}Snega!Xv$4UflD31Ugz-KG}358v??3l`xy&INx
zbqv2}<>sY8FIWgEp^(elf>o7kD$9Bobq60C>1)5H3!&VN42RuqwWX`aR#k#!y@!=X
zJ8FG5^x~IP&|OmrAkF1teIvcsb*&m3+c3CtdD|C<hbt$Rf^Hzz{<){`g0Cl*@zbDT
z2X9bH$cs{Lua$yYdqA~GaQead5Ew4EsUr>>tQ$apJ@t|H5Xu&Wy;wxP3_|anGD4xg
zXiB9_5UT@_7eVq`8>Afs2)Q!mzF`o7W3_gu55&J`&)ifJ_x;^8Y!e>|3-P?1G(mdd
W+mLj|YS0(`oh}sK^RxO)VeWrvx%3<W

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/cpu_mem.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/cpu_mem.vhd
index d7a2374b..3d258d2e 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/cpu_mem.vhd	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/cpu_mem.vhd	
@@ -217,33 +217,78 @@ end process;
 		
 
 -- Program ROMs
-A1: entity work.prog_rom1
+A1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6290-01b1.hex",
+		widthad_a => 11,
+		width_a => 8)
 port map(
 		clock => clk6,
 		address => A(10) & ADR(9 downto 0),
 		q => rom1_dout
 		);
 		
-C1: entity work.prog_rom2
+--A1: entity work.prog_rom1
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom1_dout
+--		);
+
+C1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6291-01c1.hex",
+		widthad_a => 11,
+		width_a => 8)
 port map(
 		clock => clk6,
 		address => A(10) & ADR(9 downto 0),
 		q => rom2_dout
 		);
+		
+--C1: entity work.prog_rom2
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom2_dout
+--		);
 
-D1: entity work.prog_rom3
+D1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6404d1.hex",
+		widthad_a => 11,
+		width_a => 8)
 port map(
 		clock => clk6,
 		address => A(10) & ADR(9 downto 0),
 		q => rom3_dout
 		);
 
-E1: entity work.prog_rom4
+--D1: entity work.prog_rom3
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom3_dout
+--		);
+
+E1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6405-02e1.hex",
+		widthad_a => 11,
+		width_a => 8)
 port map(
 		clock => clk6,
 		address => A(10) & ADR(9 downto 0),
 		q => rom4_dout
 		);
+		
+--E1: entity work.prog_rom4
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom4_dout
+--		);
+
 
 -- ROM data mux
 ROM_mux_in <= (ROM1 & ROM2 & ROM3 & ROM4);
@@ -302,12 +347,24 @@ end process;
 -- Original circuit uses a bipolar PROM in the address decoder, this could be replaced with combinational logic
 
 -- E2 PROM 
-E2: entity work.addec_prom
+K6: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6401-01e2.hex",
+		widthad_a => 5,
+		width_a => 8)
 port map(
-	clock => clk12,
+		clock => clk12,
 	address => A(13 downto 9),
 	q => addec_bus
 	);
+		
+--E2: entity work.addec_prom
+--port map(
+--	clock => clk12,
+--	address => A(13 downto 9),
+--	q => addec_bus
+--	);
+
 
 F2_in <= addec_bus(0) & addec_bus(1) & addec_bus(2) & addec_bus(3);	
 WRAM <= addec_bus(4);
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/dac.sv b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/dac.sv
index 22ae8f07..5dea333e 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/dac.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/dac.sv	
@@ -3,7 +3,7 @@
 //
 // MSBI is the highest bit number. NOT amount of bits!
 //
-module dac #(parameter MSBI=6, parameter INV=1'b1)
+module dac #(parameter MSBI=15, parameter INV=1'b1)
 (
    output reg      DACout, //Average Output feeding analog lowpass
    input  [MSBI:0] DACin,  //DAC input (excess 2**MSBI)
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/gearshift.sv b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/gearshift.sv
new file mode 100644
index 00000000..da7ec335
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/gearshift.sv	
@@ -0,0 +1,94 @@
+//============================================================================
+//  gearshift
+//
+//  Turn gearup and geardown buttons into state that can flip the correct switches
+//  for sprint
+//
+//
+//  Copyright (c) 2019 Alan Steremberg - alanswx
+//
+//   
+//============================================================================
+
+module gearshift
+(
+	input CLK,
+	
+	input gearup,
+	input geardown,
+	
+	output gear1,
+	output gear2,
+	output gear3
+);
+
+reg [2:0] gear=3'b0;
+
+always @(posedge CLK) begin
+  	reg old_gear_up;
+	reg old_gear_down;
+	
+	if (gearup==1)
+	begin
+	   if (old_gear_up==0)
+		begin
+			old_gear_up=1;
+			if (gear<4)
+			begin
+				gear=gear+1;
+			end
+		end
+	end
+	else
+	begin
+		old_gear_up=0;
+	end
+	if (geardown==1)
+	begin
+	   if (old_gear_down==0)
+		begin
+			old_gear_down=1;
+			if (gear>0)
+			begin
+			gear=gear-1;
+			end
+		end
+	end
+	else
+	begin
+		old_gear_up=0;
+	end
+
+	
+	casex(gear)
+	3'b000: 
+	begin
+		gear1=0;
+		gear2=1;
+		gear3=1;
+	end
+	3'b001:
+	begin
+		gear1=1;
+		gear2=0;
+		gear3=1;
+
+	end
+	3'b010: 
+	begin
+		gear1=1;
+		gear2=1;
+		gear3=0;
+	end
+	3'b011:
+	begin
+		gear1=1;
+		gear2=1;
+		gear3=1;
+	end
+		endcase
+
+end
+
+
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/joy2quad.sv b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/joy2quad.sv
new file mode 100644
index 00000000..dae1fa5f
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/joy2quad.sv	
@@ -0,0 +1,100 @@
+//============================================================================
+//  joy2quad
+//
+//  Take in digital joystick buttons, and try to estimate a quadrature encoder
+//
+// 
+//  This makes an offset wave pattern for each keyboard stroke.  It might
+//  be a good extension to change the size of the wave based on how long the joystick
+//  is held down. 
+//
+//  Copyright (c) 2019 Alan Steremberg - alanswx
+//
+//   
+//============================================================================
+// digital joystick button to quadrature encoder
+
+module joy2quad
+(
+	input CLK,
+	input [31:0] clkdiv,
+	
+	input right,
+	input left,
+	
+	output reg [1:0] steer
+);
+
+
+reg [3:0] state = 0;
+
+always @(posedge CLK) begin
+ reg [31:0] count = 0;
+ if (count >0)
+  begin 
+	count=count-1;
+ end
+ else
+ begin
+ count=clkdiv;
+ casex(state)
+	4'b0000: 
+	  begin
+	    steer=2'b00;
+		 if (left==1)
+		 begin
+			state=4'b0001;
+		 end
+		 if (right==1)
+		 begin
+			state=4'b0101;
+		 end
+
+		 end
+	4'b0001: 
+	  begin
+	    steer=2'b00;
+		 state=4'b0010;
+	  end
+	4'b0010: 
+	  begin
+	    steer=2'b01;
+		 state=3'b0011;
+	  end
+	4'b0011: 
+	  begin
+	    steer=2'b11;
+		 state=4'b0100;
+	  end
+	4'b0100: 
+	  begin
+	    steer=2'b10;
+		 state=4'b000;
+	  end
+	4'b0101: 
+	  begin
+	    steer=2'b00;
+		 state=4'b0110;
+	  end
+	4'b0110: 
+	  begin
+	    steer=2'b10;
+		 state=4'b0111;
+	  end
+	4'b0111: 
+	  begin
+	    steer=2'b11;
+		 state=4'b1000;
+	  end
+	4'b1000: 
+	  begin
+	    steer=2'b01;
+		 state=4'b0000;
+		 
+	  end
+
+ endcase
+ end
+end
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/motion.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/motion.vhd
index f9010db1..2cca16fc 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/motion.vhd	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/motion.vhd	
@@ -123,19 +123,42 @@ end process;
 
 
 -- Motion object PROMs - These contain the car images for all 32 possible orientations
-J6: entity work.j6_prom
+J6: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6399-01j6.hex",
+		widthad_a => 9,
+		width_a => 4)
 port map(
-	clock => clk6,
-	address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
-	q => Vid(7 downto 4)
-	);
+		clock => clk6,
+		address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+		q => Vid(7 downto 4)
+		);
+		
+--J6: entity work.j6_prom
+--port map(
+--	clock => clk6,
+--	address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+--	q => Vid(7 downto 4)
+--	);
 
-K6: entity work.k6_prom
+K6: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6398-01k6.hex",
+		widthad_a => 9,
+		width_a => 4)
 port map(
-	clock => clk6,
-	address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
-	q => Vid(3 downto 0)
-	);
+		clock => clk6,
+		address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+		q => Vid(3 downto 0)
+		);
+		
+--K6: entity work.k6_prom
+--port map(
+--	clock => clk6,
+--	address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+--	q => Vid(3 downto 0)
+--	);
+
 
 	
 -- Some glue logic
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/playfield.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/playfield.vhd
index 86425cbc..7cd68716 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/playfield.vhd	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/playfield.vhd	
@@ -93,19 +93,42 @@ P3_6 <= (HBlank or VBlank);
 char_addr <= display(5 downto 0) & V4 & V2 & V1;
 
 -- Background character ROMs
-R4: entity work.Char_MSB
+R4: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6397-01r4.hex",
+		widthad_a => 9,
+		width_a => 4)
 port map(
-	clock => clk6,
-	Address => char_addr,
-	q => char_data(3 downto 0) 
-	);
+		clock => clk6,
+		Address => char_addr,
+		q => char_data(3 downto 0) 
+		);
+		
+--R4: entity work.Char_MSB
+--port map(
+--	clock => clk6,
+--	Address => char_addr,
+--	q => char_data(3 downto 0) 
+--	);
 
-P4: entity work.Char_LSB
+P4: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6396-01p4.hex",
+		widthad_a => 9,
+		width_a => 4)
 port map(
-	clock => clk6,
-	Address => char_addr,
-	q => char_data(7 downto 4) 
-	);
+		clock => clk6,
+		Address => char_addr,
+		q => char_data(7 downto 4) 
+		);
+
+--P4: entity work.Char_LSB
+--port map(
+--	clock => clk6,
+--	Address => char_addr,
+--	q => char_data(7 downto 4) 
+--	);
+
 
 
 -- 74LS166 video shift register	
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/pll.v b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/pll.v
index 95460fd9..aec82b25 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/pll.v	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/pll.v	
@@ -243,7 +243,7 @@ endmodule
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_LSB.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_LSB.qip
deleted file mode 100644
index 2ce4cc47..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_LSB.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Char_LSB.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_LSB.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_LSB.vhd
deleted file mode 100644
index 9c7bdfc3..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_LSB.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: Char_LSB.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY Char_LSB IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
-	);
-END Char_LSB;
-
-
-ARCHITECTURE SYN OF char_lsb IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(3 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6396-01p4.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 512,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "CLOCK0",
-		widthad_a => 9,
-		width_a => 4,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6396-01p4.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
--- Retrieval info: PRIVATE: WidthData NUMERIC "4"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6396-01p4.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
--- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_MSB.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_MSB.qip
deleted file mode 100644
index 9c809207..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_MSB.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Char_MSB.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_MSB.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_MSB.vhd
deleted file mode 100644
index bfa538dd..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/Char_MSB.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: Char_MSB.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY Char_MSB IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
-	);
-END Char_MSB;
-
-
-ARCHITECTURE SYN OF char_msb IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(3 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6397-01r4.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 512,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "CLOCK0",
-		widthad_a => 9,
-		width_a => 4,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6397-01r4.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
--- Retrieval info: PRIVATE: WidthData NUMERIC "4"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6397-01r4.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
--- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/addec_prom.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/addec_prom.qip
deleted file mode 100644
index 81a66586..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/addec_prom.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "addec_prom.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/addec_prom.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/addec_prom.vhd
deleted file mode 100644
index 6cd74f62..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/addec_prom.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: addec_prom.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY addec_prom IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
-END addec_prom;
-
-
-ARCHITECTURE SYN OF addec_prom IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(7 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6401-01e2.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 32,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		widthad_a => 5,
-		width_a => 8,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6401-01e2.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
--- Retrieval info: PRIVATE: WidthData NUMERIC "8"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6401-01e2.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
--- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/j6_prom.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/j6_prom.qip
deleted file mode 100644
index a6b355f4..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/j6_prom.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "j6_prom.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/j6_prom.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/j6_prom.vhd
deleted file mode 100644
index cc6c3558..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/j6_prom.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: j6_prom.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY j6_prom IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
-	);
-END j6_prom;
-
-
-ARCHITECTURE SYN OF j6_prom IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(3 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6399-01j6.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 512,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "CLOCK0",
-		widthad_a => 9,
-		width_a => 4,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6399-01j6.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
--- Retrieval info: PRIVATE: WidthData NUMERIC "4"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6399-01j6.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
--- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/k6_prom.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/k6_prom.qip
deleted file mode 100644
index 9735dccb..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/k6_prom.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "k6_prom.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/k6_prom.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/k6_prom.vhd
deleted file mode 100644
index 5c772b25..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/k6_prom.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: k6_prom.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY k6_prom IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
-	);
-END k6_prom;
-
-
-ARCHITECTURE SYN OF k6_prom IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(3 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6398-01k6.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 512,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "CLOCK0",
-		widthad_a => 9,
-		width_a => 4,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6398-01k6.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
--- Retrieval info: PRIVATE: WidthData NUMERIC "4"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6398-01k6.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
--- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom1.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom1.qip
deleted file mode 100644
index ca8648de..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom1.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom1.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom1.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom1.vhd
deleted file mode 100644
index 0539e859..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom1.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: prog_rom1.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY prog_rom1 IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
-END prog_rom1;
-
-
-ARCHITECTURE SYN OF prog_rom1 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(7 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6290-01b1.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2048,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "CLOCK0",
-		widthad_a => 11,
-		width_a => 8,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6290-01b1.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
--- Retrieval info: PRIVATE: WidthData NUMERIC "8"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6290-01b1.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
--- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom2.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom2.qip
deleted file mode 100644
index aefde75d..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom2.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom2.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom2.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom2.vhd
deleted file mode 100644
index d2ee7a7e..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom2.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: prog_rom2.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY prog_rom2 IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
-END prog_rom2;
-
-
-ARCHITECTURE SYN OF prog_rom2 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(7 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6291-01c1.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2048,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "CLOCK0",
-		widthad_a => 11,
-		width_a => 8,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6291-01c1.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
--- Retrieval info: PRIVATE: WidthData NUMERIC "8"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6291-01c1.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
--- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom3.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom3.qip
deleted file mode 100644
index 562f4ad7..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom3.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom3.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom3.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom3.vhd
deleted file mode 100644
index 41a5470c..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom3.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: prog_rom3.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY prog_rom3 IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
-END prog_rom3;
-
-
-ARCHITECTURE SYN OF prog_rom3 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(7 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6404d1.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2048,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "CLOCK0",
-		widthad_a => 11,
-		width_a => 8,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6404d1.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
--- Retrieval info: PRIVATE: WidthData NUMERIC "8"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6404d1.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
--- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom4.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom4.qip
deleted file mode 100644
index 30906c90..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom4.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom4.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom4.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom4.vhd
deleted file mode 100644
index b71ccb64..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/prog_rom4.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: prog_rom4.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY prog_rom4 IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
-END prog_rom4;
-
-
-ARCHITECTURE SYN OF prog_rom4 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(7 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6405-02e1.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2048,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "CLOCK0",
-		widthad_a => 11,
-		width_a => 8,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6405-02e1.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
--- Retrieval info: PRIVATE: WidthData NUMERIC "8"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6405-02e1.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
--- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/sync_prom.qip b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/sync_prom.qip
deleted file mode 100644
index 9a31148f..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/sync_prom.qip	
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sync_prom.vhd"]
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/sync_prom.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/sync_prom.vhd
deleted file mode 100644
index b078c62d..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/roms/sync_prom.vhd	
+++ /dev/null
@@ -1,141 +0,0 @@
--- megafunction wizard: %ROM: 1-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: sync_prom.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.4 Build 182 03/12/2014 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2014 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY sync_prom IS
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		clock		: IN STD_LOGIC  := '1';
-		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
-	);
-END sync_prom;
-
-
-ARCHITECTURE SYN OF sync_prom IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
-
-BEGIN
-	q    <= sub_wire0(3 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => "./rtl/roms/6400-01m2.hex",
-		intended_device_family => "Cyclone II",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 256,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		widthad_a => 8,
-		width_a => 4,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
--- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
--- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clken NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6400-01m2.hex"
--- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
--- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
--- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
--- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
--- Retrieval info: PRIVATE: WidthData NUMERIC "4"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6400-01m2.hex"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
--- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
--- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint1.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint1.vhd
deleted file mode 100644
index 83424a60..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint1.vhd	
+++ /dev/null
@@ -1,313 +0,0 @@
--- Top level file for Kee Games Sprint 1 
--- (c) 2017 James Sweet
---
--- This is free software: you can redistribute
--- it and/or modify it under the terms of the GNU General
--- Public License as published by the Free Software
--- Foundation, either version 3 of the License, or (at your
--- option) any later version.
---
--- This is distributed in the hope that it will
--- be useful, but WITHOUT ANY WARRANTY; without even the
--- implied warranty of MERCHANTABILITY or FITNESS FOR A
--- PARTICULAR PURPOSE. See the GNU General Public License
--- for more details.
-
--- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple
--- See Sprint 1 manual for video output details. Resistor values listed here have been scaled 
--- for 3.3V logic. 
--- R48 1k Ohm
--- R49 1k Ohm
--- R50 680R
--- R51 330R
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-
-entity sprint1 is 
-port(		
-			Clk_50_I		: in	std_logic;	-- 50MHz input clock
-			clk_12		: in	std_logic;	-- 12MHz input clock
-			Reset_n		: in	std_logic;	-- Reset button (Active low)
-			
-			
-			VideoW_O		: out std_logic;  -- White video output (680 Ohm)
-			VideoB_O		: out std_logic;	-- Black video output (1.2k)
-			Sync_O		: out std_logic;  -- Composite sync output (1.2k)
-			
-			
-			Hs				: out std_logic;
-			Vs				: out std_logic;
-			Vb				: out std_logic;			
-			Hb				: out std_logic;	
-			Video			: out std_logic;
-			
-			Audio			: out std_logic_vector(6 downto 0);
-			Coin1_I		: in  std_logic;  -- Coin switches (Active low)
-			Coin2_I		: in  std_logic;
-			Start_I		: in  std_logic;  -- Start button
-			Gas_I			: in  std_logic;	-- Gas pedal
-			Gear1_I		: in  std_logic;  -- Gear shifter, 4th gear = no other gear selected
-			Gear2_I		: in  std_logic;
-			Gear3_I		: in  std_logic;
-			Test_I		: in  std_logic;  -- Self-test switch
-			SteerA_I		: in  std_logic;	-- Steering wheel inputs, these are quadrature encoders
-			SteerB_I		: in	std_logic;
-			StartLamp_O	: out std_logic	-- Start button lamp
-			);
-end sprint1;
-
-architecture rtl of sprint1 is
-
-signal clk_6			: std_logic;
-signal phi1 			: std_logic;
-signal phi2				: std_logic;
-
-signal Hcount		   : std_logic_vector(8 downto 0) := (others => '0');
-signal H256				: std_logic;
-signal H256_s			: std_logic;
-signal H256_n			: std_logic;
-signal H128				: std_logic;
-signal H64				: std_logic;
-signal H32				: std_logic;
-signal H16				: std_logic;
-signal H8				: std_logic;
-signal H8_n				: std_logic;
-signal H4				: std_logic;
-signal H4_n				: std_logic;
-signal H2				: std_logic;
-signal H1				: std_logic;
-
-
-
-signal Vcount  		: std_logic_vector(7 downto 0) := (others => '0');
-signal V128				: std_logic;
-signal V64				: std_logic;
-signal V32				: std_logic;
-signal V16				: std_logic;
-signal V8				: std_logic;
-signal V4				: std_logic;
-signal V2				: std_logic;
-signal V1				: std_logic;
-
-
-signal Vreset			: std_logic;
-signal Vblank_s		: std_logic;
-signal Vblank_n_s		: std_logic;
-signal Vblank			: std_logic;			
-signal Hblank			: std_logic;
-signal Hsync			: std_logic;
-signal Vsync			: std_logic;
-
-signal CompBlank_s	: std_logic;
-signal CompSync_n_s	: std_logic;
-
-signal WhitePF_n		: std_logic;
-signal BlackPF_n		: std_logic;
-
-signal Display			: std_logic_vector(7 downto 0);
-
--- Address decoder
-signal addec_bus		: std_logic_vector(7 downto 0);
-signal RnW				: std_logic;
-signal Write_n			: std_logic;
-signal ROM1				: std_logic;
-signal ROM2				: std_logic;
-signal ROM3				: std_logic;
-signal WRAM				: std_logic;
-signal RAM_n			: std_logic;
-signal Sync_n			: std_logic;
-signal Switch_n		: std_logic;
-signal Collision1_n	: std_logic;
-signal Collision2_n	: std_logic;
-signal Display_n		: std_logic;
-signal TimerReset_n	: std_logic;
-signal CollRst1_n		: std_logic;
-signal CollRst2_n		: std_logic;
-signal SteerRst1_n	: std_logic;
-signal SteerRst2_n	: std_logic;
-signal NoiseRst_n		: std_logic;
-signal Attract			: std_logic;	
-signal Skid1			: std_logic;
-signal Skid2			: std_logic;
-
-signal Crash_n			: std_logic;
-signal Motor1_n 		: std_logic;
-signal Motor2_n		: std_logic;
-signal Car1				: std_logic;
-signal Car1_n			: std_logic;
-signal Car2				: std_logic;
-signal Car2_n			: std_logic;
-signal Car3_4_n		: std_logic;	
-
-signal NMI_n			: std_logic;
-
-signal Adr				: std_logic_vector(9 downto 0);
-
-signal SW1				: std_logic_vector(7 downto 0);
-
-signal Inputs			: std_logic_vector(1 downto 0);
-signal Collisions1	: std_logic_vector(1 downto 0);
-signal Collisions2	: std_logic_vector(1 downto 0);
-
-begin
--- Configuration DIP switches, these can be brought out to external switches if desired
--- See Sprint 2 manual page 11 for complete information. Active low (0 = On, 1 = Off)
---    1 								Oil slicks			(0 - Oil slicks enabled)
---			2							Cycle tracks      (0/1 - Cycle every lap/every two laps)
---   			3	4					Coins per play		(00 - 1 Coin per player) 
---						5				Extended Play		(0 - Extended Play enabled)
---							6			Not used				(X - Don't care)
---								7	8	Game time			(01 - 120 Seconds)
-SW1 <= "11000101"; -- Config dip switches
-		
-		
-Vid_sync: entity work.synchronizer
-port map(
-		clk_12 => clk_12,
-		clk_6 => clk_6,
-		hcount => hcount,
-		vcount => vcount,
-		hsync => hsync,
-		hblank => hblank,
-		vblank_s => vblank_s,
-		vblank_n_s => vblank_n_s,
-		vblank => vblank,
-		vsync => vsync,
-		vreset => vreset
-		);
-
-
-Background: entity work.playfield
-port map( 
-		clk6 => clk_6,
-		display => display,
-		HCount => HCount,
-		VCount => VCount,
-		HBlank => HBlank,		
-		H256_s => H256_s,
-		VBlank => VBlank,
-		VBlank_n_s => Vblank_n_s,
-		HSync => Hsync,
-		VSync => VSync,
-		CompSync_n_s => CompSync_n_s,
-		CompBlank_s => CompBlank_s,
-		WhitePF_n => WhitePF_n,
-		BlackPF_n => BlackPF_n 
-		);
-
-		
-Cars: entity work.motion
-port map(
-		CLK6 => clk_6,
-		CLK12 => clk_12,
-		PHI2 => phi2,
-		DISPLAY => Display,
-		H256_s => H256_s,
-		VCount => VCount,
-		HCount => HCount,
-		Crash_n => Crash_n,
-		Motor1_n => Motor1_n,
-		Car1 => Car1,
-		Car1_n => Car1_n,
-		Car2 => Car2,
-		Car2_n => Car2_n,
-		Car3_4_n => Car3_4_n	
-		);
-		
-		
-PF_Comparator: entity work.collision_detect
-port map(
-		Clk6 => Clk_6,
-		Car1 => Car1,
-		Car1_n => Car1_n,
-		Car2 => Car2,
-		Car2_n => Car2_n,
-		Car3_4_n	=> Car3_4_n,
-		WhitePF_n => WhitePF_n,
-		BlackPF_n => BlackPF_n,
-		CollRst1_n => CollRst1_n,
-		Collisions1 => Collisions1
-		);
-	
-	
-CPU: entity work.cpu_mem
-port map(
-		Clk12 => clk_12,
-		Clk6 => clk_6,
-		Reset_n => reset_n,
-		VCount => VCount,
-		HCount => HCount,
-		Hsync_n => not Hsync,
-		Vblank_s => Vblank_s,
-		Vreset => Vreset,
-		Test_n => not Test_I,
-		Attract => Attract,
-		Skid1 => Skid1,
-		Skid2 => Skid2,
-		NoiseReset_n => NoiseRst_n,
-		CollRst1_n => CollRst1_n,
-		CollRst2_n => CollRst2_n,
-		SteerRst1_n => SteerRst1_n,
-		Lamp1 => StartLamp_O,
-		Phi1_o => Phi1,
-		Phi2_o => Phi2,
-		Display => Display,
-		IO_Adr => Adr,
-		Collisions1 => Collisions1,
-		Collisions2 => Collisions2,
-		Inputs => Inputs
-		);
-
-
-Input: entity work.Control_Inputs
-port map(
-		clk6 => clk_6,
-		SW1 => SW1, -- DIP switches
-		Coin1_n => Coin1_I,
-		Coin2_n => Coin2_I,
-		Start => not Start_I, -- Active high in real hardware, inverting these makes more sense with the FPGA
-		Gas => not Gas_I,
-		Gear1 => not Gear1_I,
-		Gear2 => not Gear2_I,
-		Gear3 => not Gear3_I,
-		Self_Test => not Test_I,
-		Steering1A_n => SteerA_I,
-		Steering1B_n => SteerB_I,
-		SteerRst1_n => SteerRst1_n,
-		Adr => Adr,
-		Inputs => Inputs
-	);	
-
-	
-Sound: entity work.audio
-port map( 
-		Clk_50 => Clk_50_I,
-		Clk_6 => Clk_6,
-		Reset_n => Reset_n,
-		Motor1_n => Motor1_n,
-		Skid1 => Skid1,
-		Crash_n => Crash_n,
-		NoiseReset_n => NoiseRst_n,
-		Attract => Attract,
-		Display => Display,
-		HCount => HCount,
-		VCount => VCount,
-		Audio1 => Audio
-		);
-
--- Video mixing	
-VideoB_O <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s;	
-VideoW_O <= not(WhitePF_n and Car1_n);  
-Sync_O <= CompSync_n_s;
-
-Vb <= VBLANK;
-Hb <= HBLANK;
-Hs <= Hsync;
-Vs <= Vsync;
-Video <= (WhitePF_n and blackpf_n and car1_n and Car2_n and Car3_4_n) nor CompBlank_s;
-
-end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint2.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint2.vhd
index 74f6bb76..e422e553 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint2.vhd	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint2.vhd	
@@ -31,16 +31,14 @@ entity sprint2 is
 port(		
 			clk_12		: in	std_logic;	-- 12MHz input clock
 			Reset_n		: in	std_logic;	-- Reset button (Active low)
-			Video		: out std_logic_vector(1 downto 0);
+			Video			: out std_logic_vector(1 downto 0);
 			Sync_O		: out std_logic;  -- Composite sync output (1.2k)
 			Audio1_O		: out std_logic_vector(6 downto 0);  -- Ideally this should have a simple low pass filter
-			Audio2_O		: out std_logic_vector(6 downto 0);
-			
+			Audio2_O		: out std_logic_vector(6 downto 0);			
 			Hs				: out std_logic;
 			Vs				: out std_logic;
 			Vb				: out std_logic;			
 			Hb				: out std_logic;	
-
 			Coin1_I		: in  std_logic;  -- Coin switches (Active low)
 			Coin2_I		: in  std_logic;
 			Start1_I		: in  std_logic;  -- Start buttons
@@ -322,16 +320,12 @@ port map(
 		);
 
 -- Video mixing	
---VideoB_O <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s;	
---VideoW_O <= not(WhitePF_n and Car1_n and Car3_4_n);  
+Video(0) <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s;	
+Video(1) <= not(WhitePF_n and Car1_n and Car3_4_n);  
 Sync_O <= CompSync_n_s;
-
-
 Vb <= VBLANK;
 Hb <= HBLANK;
 Hs <= Hsync;
 Vs <= Vsync;
-Video(0) <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s;	
-Video(1) <= not(WhitePF_n and Car1_n and Car3_4_n);  
 
 end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint2_mist.sv b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint2_mist.sv
index 1dd37a39..e9560183 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint2_mist.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprint2_mist.sv	
@@ -21,91 +21,141 @@ module sprint2_mist(
 localparam CONF_STR = {
 	"Sprint2;;",
 	"O1,Test Mode,Off,On;",
-//	"T2,Next Track;",
+	"T2,Next Track;",
 	"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
 	"T6,Reset;",
-	"V,v1.00.",`BUILD_DATE
+	"V,v1.10.",`BUILD_DATE
 };
 
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [9:0] kbjoy;
+wire  [11:0] kbjoy;
 wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoubler_disable;
 wire        ypbpr;
 wire        ps2_kbd_clk, ps2_kbd_data;
 wire  [6:0] audio1, audio2;
-wire	[1:0] video;
-
+wire	[1:0] Video;
+assign LED = 1'b1;
 wire clk_24, clk_12, clk_6;
 wire locked;
 pll pll
 (
 	.inclk0(CLOCK_27),
-	.c0(clk_24),
-	.c1(clk_12),
-	.c2(clk_6),
+	.c0(clk_24),//24.192
+	.c1(clk_12),//12.096
+	.c2(clk_6),//6.048
 	.locked(locked)
 );
 
-wire led1, led2;
-assign LED = (led1 | led2);
+wire m_up1     = (kbjoy[3] | joystick_1[3]);
+wire m_down1   = (kbjoy[2] | joystick_1[2]);
+wire m_left1   = (kbjoy[1] | joystick_1[1]);
+wire m_right1  = (kbjoy[0] | joystick_1[0]);
+
+wire m_up2     = (joystick_0[3]);
+wire m_down2   = (joystick_0[2]);
+wire m_left2   = (joystick_0[1]);
+wire m_right2  = (joystick_0[0]);
+
+wire m_fire1   = ~(kbjoy[4] | joystick_1[4]);
+wire m_fire2   = ~(joystick_0[4]);
+wire m_start1 = ~(kbjoy[5]);
+wire m_start2 = ~(kbjoy[6]);
+wire m_coin = ~(kbjoy[7]);
+wire m_gearup1 = (kbjoy[8] | joystick_1[5]);
+wire m_geardown1 = (kbjoy[9] | joystick_1[6]);
+wire m_gearup2 = (joystick_0[5]);
+wire m_geardown2 = (joystick_0[6]);
+
+wire [1:0] steer1;
+joy2quad steerp1
+(
+	.CLK(clk_24),
+	.clkdiv('d22500),	
+	.right(m_right1),
+	.left(m_left1),	
+	.steer(steer1)
+);
+
+wire [1:0] steer2;
+joy2quad steerp2
+(
+	.CLK(clk_24),
+	.clkdiv('d22500),	
+	.right(m_right2),
+	.left(m_left2),	
+	.steer(steer2)
+);
+
+wire gear11,gear12,gear13;
+gearshift gearshiftp1
+(
+	.CLK(clk_12),	
+	.gearup(m_gearup1),
+	.geardown(m_geardown1),	
+	.gear1(gear11),
+	.gear2(gear12),
+	.gear3(gear13)
+);
+
+wire gear21,gear22,gear23;
+gearshift gearshiftp2
+(
+	.CLK(clk_12),	
+	.gearup(m_gearup2),
+	.geardown(m_geardown2),	
+	.gear1(gear21),
+	.gear2(gear22),
+	.gear3(gear23)
+);
 
 sprint2 sprint2 (
 	.clk_12(clk_12),
-	.Reset_n(~(status[0] | status[6] | buttons[1])),
-	.VideoW_O(),
-	.VideoB_O(),
-	.Sync_O(),					
+	.Reset_n(~(status[0] | status[6] | buttons[1])),			
 	.Hs(hs),
 	.Vs(vs),
 	.Vb(vb),		
 	.Hb(hb),
-	.Video(video),			
+	.Video(Video),			
 	.Audio1_O(audio1),
 	.Audio2_O(audio2),
 	.Coin1_I(~kbjoy[7]),
-	.Coin2_I(~kbjoy[7]),
+	.Coin2_I(1'b1),
 	.Start1_I(~kbjoy[5]),
 	.Start2_I(~kbjoy[6]),
-	.Trak_Sel_I(),//~status[2]),
-	.Gas1_I(~kbjoy[4]),
-	.Gas2_I(),
-//	.Gear1_1_I(),//                                                                                                                                                                                                                                                                                                           Gear shifters, 4th gear = no other gear selected
-//	.Gear1_2_I(),
-//	.Gear1_3_I(),
-//	.Gear2_1_I(),
-//	.Gear2_2_I(),
-//	.Gear2_3_I(),
+	.Trak_Sel_I(~status[2]),
+	.Gas1_I(m_fire1),
+	.Gas2_I(m_fire2),
+	.Gear1_1_I(gear11),
+	.Gear1_2_I(gear21),	
+	.Gear2_1_I(gear12),
+	.Gear2_2_I(gear22),	
+	.Gear3_1_I(gear13),
+	.Gear3_2_I(gear23),
 	.Test_I(~status[1]),
-	.Steer_1A_I(~kbjoy[1]),// Steering wheel inputs, these are quadrature encoders
-	.Steer_1B_I(~kbjoy[0]),
-//	.Steer_2A_I(),
-//	.Steer_2B_I(),
-	.Lamp1_O(led1),
-	.Lamp2_O(led2)
+	.Steer_1A_I(steer1[1]),
+	.Steer_1B_I(steer1[0]),
+	.Steer_2A_I(steer2[1]),
+	.Steer_2B_I(steer2[0]),
+	.Lamp1_O(),
+	.Lamp2_O()
 );
 
-dac dac1 (
+dac dac (
 	.CLK(clk_24),
 	.RESET(1'b0),
-	.DACin(audio1),
+	.DACin({audio1,"00",audio2}),
 	.DACout(AUDIO_L)
 	);
 	
-dac dacr (
-	.CLK(clk_24),
-	.RESET(1'b0),
-	.DACin(audio2),
-	.DACout(AUDIO_R)
-	);	
-
+assign AUDIO_R = AUDIO_L;
 wire hs, vs;
 wire hb, vb;
 wire blankn = ~(hb | vb);
-video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
+video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer
 (
 	.clk_sys(clk_24),
 	.ce_pix(clk_6),
@@ -113,12 +163,12 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({video,video,video}),
-	.G({video,video,video}),
-	.B({video,video,video}),
-//	.R(blankn ? {video,video,video} : "000"),
-//	.G(blankn ? {video,video,video} : "000"),
-//	.B(blankn ? {video,video,video} : "000"),
+	.R({Video,Video,Video,Video,Video,Video}),
+	.G({Video,Video,Video,Video,Video,Video}),
+	.B({Video,Video,Video,Video,Video,Video}),
+//	.R(blankn ? {video,video,video} : "000000"),
+//	.G(blankn ? {video,video,video} : "000000"),
+//	.B(blankn ? {video,video,video} : "000000"),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/sprom.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprom.vhd
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/sprom.vhd
rename to Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sprom.vhd
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sync.vhd b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sync.vhd
index 544cee27..9a9ea9f1 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sync.vhd	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/rtl/sync.vhd	
@@ -99,12 +99,24 @@ end process;
 
 -- Many Atari raster games use a 256 x 4 bit prom to decode vertical sync signals
 -- This could be replaced by combinatorial logic
-M2: entity work.sync_prom
+M2: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6400-01m2.hex",
+		widthad_a => 8,
+		width_a => 4)
 port map(
 		clock => clk_12, 
 		address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
 		q => sync_bus
 		);
+		
+--M2: entity work.sync_prom
+--port map(
+--		clock => clk_12, 
+--		address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
+--		q => sync_bus
+--		);
+
 
 -- Register fed by the sync PROM, in the original hardware this also creates the complements of these signals
 sync_register: process(hsync_int)
diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/snapshot/sprint2.rbf b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/snapshot/sprint2.rbf
deleted file mode 100644
index 0ede27569ed5ee6a3360832927893d0e589a7424..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/sprint2.qsf b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/sprint2.qsf
index c34032c8..cfecf867 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/sprint2.qsf	
+++ b/Arcade_MiST/Atari BW Raster Hardware/Sprint2_MiST/sprint2.qsf	
@@ -153,6 +153,8 @@ set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
 set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
 set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
 set_global_assignment -name VHDL_FILE rtl/sync.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/joy2quad.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/gearshift.sv
 set_global_assignment -name VHDL_FILE rtl/playfield.vhd
 set_global_assignment -name VHDL_FILE rtl/motion.vhd
 set_global_assignment -name VHDL_FILE rtl/collision.vhd
@@ -168,16 +170,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv
-set_global_assignment -name QIP_FILE rtl/roms/addec_prom.qip
-set_global_assignment -name QIP_FILE rtl/roms/Char_LSB.qip
-set_global_assignment -name QIP_FILE rtl/roms/Char_MSB.qip
-set_global_assignment -name QIP_FILE rtl/roms/j6_prom.qip
-set_global_assignment -name QIP_FILE rtl/roms/k6_prom.qip
-set_global_assignment -name QIP_FILE rtl/roms/prog_rom1.qip
-set_global_assignment -name QIP_FILE rtl/roms/prog_rom2.qip
-set_global_assignment -name QIP_FILE rtl/roms/prog_rom3.qip
-set_global_assignment -name QIP_FILE rtl/roms/prog_rom4.qip
-set_global_assignment -name QIP_FILE rtl/roms/sync_prom.qip
 set_global_assignment -name VERILOG_FILE rtl/pll.v
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/README.txt b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/README.txt
index d7d623d5..fc4945b6 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/README.txt	
+++ b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/README.txt	
@@ -14,5 +14,4 @@
 -- Joystick support.
 -- 
 -- 
----------------------------------------------------------------------------------
-todo: Fix Controls
\ No newline at end of file
+----------------------------------------------------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/Release/sprint1.rbf b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/Release/sprint1.rbf
new file mode 100644
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/gearshift.sv b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/gearshift.sv
new file mode 100644
index 00000000..fe34be50
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/gearshift.sv	
@@ -0,0 +1,94 @@
+//============================================================================
+//  gearshift
+//
+//  Turn gearup and geardown buttons into state that can flip the correct switches
+//  for sprint
+//
+//
+//  Copyright (c) 2019 Alan Steremberg - alanswx
+//
+//   
+//============================================================================
+
+module gearshift
+(
+	input CLK,
+	
+	input gearup,
+	input geardown,
+	
+	output gear1,
+	output gear2,
+	output gear3
+);
+
+reg [2:0] gear=3'b0;
+
+always @(posedge CLK) begin
+  	reg old_gear_up;
+	reg old_gear_down;
+	
+	if (gearup==1)
+	begin
+	   if (old_gear_up==0)
+		begin
+			old_gear_up=1;
+			if (gear<4)
+			begin
+				gear=gear+1;
+			end
+		end
+	end
+	else
+	begin
+		old_gear_up=0;
+	end
+	if (geardown==1)
+	begin
+	   if (old_gear_down==0)
+		begin
+			old_gear_down=1;
+			if (gear>0)
+			begin
+			gear=gear-1;
+			end
+		end
+	end
+	else
+	begin
+		old_gear_up=0;
+	end
+
+	
+	casex(gear)
+	3'b000: 
+	begin
+		gear1=0;
+		gear2=1;
+		gear3=1;
+	end
+	3'b001:
+	begin
+		gear1=1;
+		gear2=0;
+		gear3=1;
+
+	end
+	3'b010: 
+	begin
+		gear1=1;
+		gear2=1;
+		gear3=0;
+	end
+	3'b011:
+	begin
+		gear1=1;
+		gear2=1;
+		gear3=1;
+	end
+		endcase
+
+end
+
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/joy2quad.sv b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/joy2quad.sv
new file mode 100644
index 00000000..dae1fa5f
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/joy2quad.sv	
@@ -0,0 +1,100 @@
+//============================================================================
+//  joy2quad
+//
+//  Take in digital joystick buttons, and try to estimate a quadrature encoder
+//
+// 
+//  This makes an offset wave pattern for each keyboard stroke.  It might
+//  be a good extension to change the size of the wave based on how long the joystick
+//  is held down. 
+//
+//  Copyright (c) 2019 Alan Steremberg - alanswx
+//
+//   
+//============================================================================
+// digital joystick button to quadrature encoder
+
+module joy2quad
+(
+	input CLK,
+	input [31:0] clkdiv,
+	
+	input right,
+	input left,
+	
+	output reg [1:0] steer
+);
+
+
+reg [3:0] state = 0;
+
+always @(posedge CLK) begin
+ reg [31:0] count = 0;
+ if (count >0)
+  begin 
+	count=count-1;
+ end
+ else
+ begin
+ count=clkdiv;
+ casex(state)
+	4'b0000: 
+	  begin
+	    steer=2'b00;
+		 if (left==1)
+		 begin
+			state=4'b0001;
+		 end
+		 if (right==1)
+		 begin
+			state=4'b0101;
+		 end
+
+		 end
+	4'b0001: 
+	  begin
+	    steer=2'b00;
+		 state=4'b0010;
+	  end
+	4'b0010: 
+	  begin
+	    steer=2'b01;
+		 state=3'b0011;
+	  end
+	4'b0011: 
+	  begin
+	    steer=2'b11;
+		 state=4'b0100;
+	  end
+	4'b0100: 
+	  begin
+	    steer=2'b10;
+		 state=4'b000;
+	  end
+	4'b0101: 
+	  begin
+	    steer=2'b00;
+		 state=4'b0110;
+	  end
+	4'b0110: 
+	  begin
+	    steer=2'b10;
+		 state=4'b0111;
+	  end
+	4'b0111: 
+	  begin
+	    steer=2'b11;
+		 state=4'b1000;
+	  end
+	4'b1000: 
+	  begin
+	    steer=2'b01;
+		 state=4'b0000;
+		 
+	  end
+
+ endcase
+ end
+end
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/sprint1.vhd b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/sprint1.vhd
index d4245fcb..cc760a20 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/sprint1.vhd	
+++ b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/sprint1.vhd	
@@ -294,11 +294,9 @@ port map(
 Video(0) <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s;	
 Video(1) <= not(WhitePF_n and Car1_n);  
 Sync_O <= CompSync_n_s;
-
 Vb <= VBLANK;
 Hb <= HBLANK;
 Hs <= Hsync;
 Vs <= Vsync;
 
-
 end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/sprint1_mist.sv b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/sprint1_mist.sv
index 8f9c27b3..ee0568c7 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/sprint1_mist.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/rtl/sprint1_mist.sv	
@@ -36,9 +36,9 @@ wire        scandoubler_disable;
 wire        ypbpr;
 wire        ps2_kbd_clk, ps2_kbd_data;
 wire  [6:0] audio;
-wire	[1:0] video;
-
-wire clk_48, clk_12, clk_6;
+wire	[1:0] Video;
+assign LED = 1'b1;
+wire clk_24, clk_12, clk_6;
 wire locked;
 pll pll
 (
@@ -49,30 +49,47 @@ pll pll
 	.locked(locked)
 );
 
+wire [1:0] steer;
+joy2quad steer1
+(
+	.CLK(clk_24),
+	.clkdiv('d22500),	
+	.right(m_right),
+	.left(m_left),	
+	.steer(steer)
+);
+
+wire gear1,gear2,gear3;
+gearshift gearshift1
+(
+	.CLK(clk_12),	
+	.gearup(m_gearup),
+	.geardown(m_geardown),	
+	.gear1(gear1),
+	.gear2(gear2),
+	.gear3(gear3)
+);
 
 sprint1 sprint1 (
 	.clk_12(clk_12),
 	.Reset_n(~(status[0] | status[6] | buttons[1])),
-	.VideoW_O(),
-	.VideoB_O(),
-	.Sync_O(),					
+	.Video(Video),		
 	.Hs(hs),
 	.Vs(vs),
 	.Vb(vb),		
-	.Hb(hb),
-	.Video(video),			
+	.Hb(hb),	
 	.Audio(audio),
-	.Coin1_I(~kbjoy[7]),
-	.Coin2_I(~kbjoy[7]),
-	.Start_I(~kbjoy[5]),
-	.Gas_I(~kbjoy[4]),
-//	.Gear1_I(~kbjoy[8]),
-//	.Gear2_I(~kbjoy[9]),
-//	.Gear3_I(~kbjoy[10]),
+	.Coin1_I(m_coin),
+	.Coin2_I(1'b1),
+	.Start_I(m_start1),
+	.Gas_I(m_fire),
+	.Gear1_I(gear1),
+	.Gear2_I(gear2),
+	.Gear3_I(gear3),
 	.Test_I(~status[1]),
-	.SteerA_I(),
-	.SteerB_I(),
-	.StartLamp_O(~LED)
+	.SteerA_I(steer[1]),
+	.SteerB_I(steer[0]),
+	.StartLamp_O()
 );
 
 dac dac (
@@ -95,9 +112,9 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({video,video,video}),
-	.G({video,video,video}),
-	.B({video,video,video}),
+	.R({Video,Video,Video,Video,Video,Video}),
+	.G({Video,Video,Video,Video,Video,Video}),
+	.B({Video,Video,Video,Video,Video,Video}),
 //	.R(blankn ? {video,video,video} : "000000"),
 //	.G(blankn ? {video,video,video} : "000000"),
 //	.B(blankn ? {video,video,video} : "000000"),
@@ -116,6 +133,17 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer
 	.mono(0)
 );
 
+wire m_up     = (kbjoy[3] | joystick_0[3] | joystick_1[3]);
+wire m_down   = (kbjoy[2] | joystick_0[2] | joystick_1[2]);
+wire m_left   = (kbjoy[1] | joystick_0[1] | joystick_1[1]);
+wire m_right  = (kbjoy[0] | joystick_0[0] | joystick_1[0]);
+
+wire m_fire   = ~(kbjoy[4] | joystick_0[4] | joystick_1[4]);
+wire m_start1 = ~(kbjoy[5]);
+wire m_start2 = ~(kbjoy[6]);
+wire m_coin = ~(kbjoy[7]);
+wire m_gearup = (kbjoy[8] | joystick_0[5] | joystick_1[5]);
+wire m_geardown = (kbjoy[9] | joystick_0[6] | joystick_1[6]);
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
 	.clk_sys        (clk_24   	     ),
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/snapshot/sprint1.rbf b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/snapshot/sprint1.rbf
deleted file mode 100644
index 3be3f76572bd7be079c4f81bdb6f4795c128ed59..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/sprint1.qsf b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/sprint1.qsf
index e6723c1f..a5a86cf8 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/sprint1.qsf	
+++ b/Arcade_MiST/Atari BW Raster Hardware/SprintOne_MiST/sprint1.qsf	
@@ -154,6 +154,8 @@ set_global_assignment -name VHDL_FILE rtl/playfield.vhd
 set_global_assignment -name VHDL_FILE rtl/EngineSound.vhd
 set_global_assignment -name VHDL_FILE rtl/Inputs.vhd
 set_global_assignment -name VHDL_FILE rtl/motion.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/gearshift.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/joy2quad.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/SuperBreakout.srf b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/SuperBreakout.srf
new file mode 100644
index 00000000..d8fdffa5
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/SuperBreakout.srf	
@@ -0,0 +1,10 @@
+{ "" "" "" "Verilog HDL information at scandoubler.sv(102): always construct contains both blocking and non-blocking assignments" {  } {  } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" {  } {  } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "VHDL warning at dpram.vhd(10): ignored assignment of value to null range" {  } {  } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "VHDL warning at T65.vhd(185): comparison between unequal length operands always returns TRUE" {  } {  } 0 10620 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "VHDL warning at dpram.vhd(94): ignored assignment of value to null range" {  } {  } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "VHDL Process Statement warning at audio.vhd(54): inferring latch(es) for signal or variable \"tone_reg\", which holds its previous value in one or more paths through the process" {  } {  } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "VHDL Process Statement warning at playfield.vhd(128): signal \"shift_data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } {  } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 113007 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 113015 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv
index 024bcd50..fdafe76f 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv	
@@ -37,7 +37,7 @@ wire        ypbpr;
 wire        ps2_kbd_clk, ps2_kbd_data;
 wire  [7:0] audio;
 wire			video;
-
+assign LED = 1'b1;
 wire clk_24, clk_12, clk_6;
 wire locked;
 pll pll
@@ -49,6 +49,16 @@ pll pll
 	.locked(locked)
 );
 
+wire m_up     = (kbjoy[3] | joystick_0[3] | joystick_1[3]);
+wire m_down   = (kbjoy[2] | joystick_0[2] | joystick_1[2]);
+wire m_left   = (kbjoy[1] | joystick_0[1] | joystick_1[1]);
+wire m_right  = (kbjoy[0] | joystick_0[0] | joystick_1[0]);
+
+wire m_fire   = ~(kbjoy[4] | joystick_0[4] | joystick_1[4]);
+wire m_start1 = ~(kbjoy[5]);
+wire m_start2 = ~(kbjoy[6]);
+wire m_coin = ~(kbjoy[7]);
+
 
 super_breakout super_breakout (
 	.clk_12(clk_12),
@@ -60,17 +70,17 @@ super_breakout super_breakout (
 	.HB(hb),
 	.Video_O(video),			
 	.Audio_O(audio),
-	.Coin1_I(~kbjoy[7]),
-	.Coin2_I(~kbjoy[7]),
-	.Start1_I(~kbjoy[5]),
-	.Start2_I(~kbjoy[6]),
+	.Coin1_I(m_coin),
+	.Coin2_I(1'b1),
+	.Start1_I(m_start1),
+	.Start2_I(m_start2),
 	.Select1_I(),
 	.Select2_I(),
 	.Enc_A(),
 	.Enc_B(),
 	.Pot_Comp1_I(),
 	.Slam_I(),
-	.Serve_I(~kbjoy[4]),
+	.Serve_I(m_fire),
 	.Test_I(~status[1]),	
 	.Lamp1_O(),
 	.Lamp2_O(),
@@ -79,7 +89,7 @@ super_breakout super_breakout (
 	);
 
 dac dac (
-	.CLK(clk_48),
+	.CLK(clk_24),
 	.RESET(1'b0),
 	.DACin(audio),
 	.DACout(AUDIO_L)
@@ -90,7 +100,7 @@ assign AUDIO_R = AUDIO_L;
 wire hs, vs;
 wire hb, vb;
 wire blankn = ~(hb | vb);
-video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
+video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(0)) video_mixer
 (
 	.clk_sys(clk_24),
 	.ce_pix(clk_6),
@@ -98,9 +108,9 @@ video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({video,video,video}),
-	.G({video,video,video}),
-	.B({video,video,video}),
+	.R({video,video,video,video,video,video}),
+	.G({video,video,video,video,video,video}),
+	.B({video,video,video,video,video,video}),
 //	.R(blankn ? {video,video,video} : "000"),
 //	.G(blankn ? {video,video,video} : "000"),
 //	.B(blankn ? {video,video,video} : "000"),
diff --git a/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/keyboard.sv b/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/keyboard.sv
index ce182b0a..1cf205f8 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/keyboard.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/keyboard.sv	
@@ -41,8 +41,6 @@ always @(negedge clk) begin
 			
 			'h69: joystick[8] <= ~release_btn; // 1
 			'h72: joystick[9] <= ~release_btn; // 2
-			'h7A: joystick[10] <= ~release_btn; // 3
-			'h6B: joystick[11] <= ~release_btn; // 4
 		endcase
 	end
 end
diff --git a/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/ultratank_mist.sv b/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/ultratank_mist.sv
index 19a7a420..b1238b68 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/ultratank_mist.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/ultratank_mist.sv	
@@ -36,9 +36,9 @@ wire        scandoubler_disable;
 wire        ypbpr;
 wire        ps2_kbd_clk, ps2_kbd_data;
 wire  [6:0] audio1, audio2;
-wire	[1:0] video;
-
-wire clk_48, clk_12;
+wire	[1:0] Video;
+assign LED = 1'b1;
+wire clk_24, clk_12, clk_6;
 wire locked;
 pll pll
 (
@@ -49,10 +49,31 @@ pll pll
 	.locked(locked)
 );
 
+wire m_up1     = (kbjoy[3] | joystick_1[3]);
+wire m_down1   = (kbjoy[2] | joystick_1[2]);
+wire m_left1   = (kbjoy[1] | joystick_1[1]);
+wire m_right1  = (kbjoy[0] | joystick_1[0]);
+
+wire m_up2     = (joystick_0[3]);
+wire m_down2   = (joystick_0[2]);
+wire m_left2   = (joystick_0[1]);
+wire m_right2  = (joystick_0[0]);
+
+wire m_fire1   = ~(kbjoy[4] | joystick_1[4]);
+wire m_fire2   = ~(joystick_0[4]);
+wire m_start1 = ~(kbjoy[5]);
+wire m_start2 = ~(kbjoy[6]);
+wire m_coin = ~(kbjoy[7]);
+wire m_gearup1 = (kbjoy[8] | joystick_1[5]);
+wire m_geardown1 = (kbjoy[9] | joystick_1[6]);
+wire m_gearup2 = (joystick_0[5]);
+wire m_geardown2 = (joystick_0[6]);
+
+
 ultra_tank ultra_tank (
 	.clk_12(clk_12),
 	.Reset_n(~(status[0] | status[6] | buttons[1])),
-	.Video(video),
+	.Video(Video),
 	.Sync_O(),
 	.Blank_O(),
 	.HS(hs),
@@ -66,10 +87,10 @@ ultra_tank ultra_tank (
 	.White_O(),
 	.Audio1_O(audio1),
 	.Audio2_O(audio2),
-	.Coin1_I(~kbjoy[7]),
-	.Coin2_I(~kbjoy[7]),
-	.Start1_I(~kbjoy[5]),
-	.Start2_I(~kbjoy[6]),
+	.Coin1_I(m_coin),
+	.Coin2_I(1'b1),
+	.Start1_I(m_start1),
+	.Start2_I(m_start2),
 	.Invisible_I(),// Invisible tanks switch
 	.Rebound_I(),// Rebounding shells switch
 	.Barrier_I(),// Barriers switch
@@ -77,12 +98,12 @@ ultra_tank ultra_tank (
 	.JoyW_Bk_I(~kbjoy[2]),
 	.JoyY_Fw_I(~kbjoy[1]),
 	.JoyY_Bk_I(~kbjoy[0]),
-	.JoyX_Fw_I(),
-	.JoyX_Bk_I(),
-	.JoyZ_Fw_I(),
-	.JoyZ_Bk_I(),
-	.FireA_I(~kbjoy[4]),
-	.FireB_I(),
+	.JoyX_Fw_I(1'b1),
+	.JoyX_Bk_I(1'b1),
+	.JoyZ_Fw_I(1'b1),
+	.JoyZ_Bk_I(1'b1),
+	.FireA_I(m_fire1),
+	.FireB_I(m_fire2),
 	.Test_I(~status[1]),
 	.Slam_I(),
 	.LED1_O(),
@@ -90,26 +111,20 @@ ultra_tank ultra_tank (
 	.Lockout_O()
 );
 
-dac dac1 (
+dac dac (
 	.CLK(clk_24),
 	.RESET(1'b0),
-	.DACin(audio1),
+	.DACin({audio1,"00",audio2}),
 	.DACout(AUDIO_L)
 	);
 	
-dac dac2 (
-	.CLK(clk_24),
-	.RESET(1'b0),
-	.DACin(audio2),
-	.DACout(AUDIO_R)
-	);
-
+assign AUDIO_R = AUDIO_L;
 wire hs, vs;
 wire hb, vb;
 wire blankn = ~(hb | vb);
 video_mixer #(
 	.LINE_LENGTH(480), 
-	.HALF_DEPTH(1)) // to dark if set to 0
+	.HALF_DEPTH(0))
 video_mixer(
 	.clk_sys(clk_24),
 	.ce_pix(clk_6),
@@ -117,9 +132,12 @@ video_mixer(
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R({video&video,video}),
-	.G({video&video,video}),
-	.B({video&video,video}),
+	.R({Video,Video,Video,Video,Video,Video}),
+	.G({Video,Video,Video,Video,Video,Video}),
+	.B({Video,Video,Video,Video,Video,Video}),
+//	.R(blankn ? {video,video,video} : "000000"),
+//	.G(blankn ? {video,video,video} : "000000"),
+//	.B(blankn ? {video,video,video} : "000000"),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
diff --git a/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/ultratank.srf b/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/ultratank.srf
new file mode 100644
index 00000000..b45d8241
--- /dev/null
+++ b/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/ultratank.srf	
@@ -0,0 +1,5 @@
+{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" {  } {  } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "Verilog HDL information at scandoubler.sv(102): always construct contains both blocking and non-blocking assignments" {  } {  } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "VHDL warning at T65.vhd(185): comparison between unequal length operands always returns TRUE" {  } {  } 0 10620 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/address_decoder.sv b/Arcade_MiST/Exidy-6502 Hardware/rtl/address_decoder.sv
index f87c5c25..4a8888e5 100644
--- a/Arcade_MiST/Exidy-6502 Hardware/rtl/address_decoder.sv	
+++ b/Arcade_MiST/Exidy-6502 Hardware/rtl/address_decoder.sv	
@@ -14,7 +14,7 @@ reg [3:0]prom_do;
 sprom #(
 	.init_file("./rom/prom5c.hex"),
 	.widthad_a(7),
-	.width_a(8))
+	.width_a(4))
 c5C(
 	.address(addr[15:9]),
 	.clock(clk),
diff --git a/Arcade_MiST/Exidy-6502 Hardware/rtl/programm_memory.sv b/Arcade_MiST/Exidy-6502 Hardware/rtl/programm_memory.sv
index 51271a00..2cc11a7a 100644
--- a/Arcade_MiST/Exidy-6502 Hardware/rtl/programm_memory.sv	
+++ b/Arcade_MiST/Exidy-6502 Hardware/rtl/programm_memory.sv	
@@ -79,7 +79,7 @@ c9A(
 	.q(rom5_do)
 	);
 
-`ifndef targ	
+`ifdef targ	
 sprom #(
 	.init_file(""),
 	.widthad_a(10),
@@ -94,7 +94,7 @@ sprom #(
 	.init_file(""),
 	.widthad_a(10),
 	.width_a(8))
-c8A(
+c7A(
 	.address(addr[9:0]),
 	.clock(clk),//pcs[6]
 	.q(rom7_do)
@@ -104,7 +104,7 @@ sprom #(
 	.init_file(""),
 	.widthad_a(10),
 	.width_a(8))
-c8A(
+c6A(
 	.address(addr[9:0]),
 	.clock(clk),//pcs[7]
 	.q(rom8_do)
diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/Release/KingBaloon.rbf b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/Release/KingBaloon.rbf
new file mode 100644
index 0000000000000000000000000000000000000000..c773732f51ae22b33d4c5a662cbbff0f92adbbb1
GIT binary patch
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diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/Snapshot/KingBaloon.rbf b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/Snapshot/KingBaloon.rbf
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diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/prom.hex b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/col.hex
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/prom.hex
rename to Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/col.hex
diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/GALAXIAN_1H.hex b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/h.hex
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/GALAXIAN_1H.hex
rename to Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/h.hex
diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/GALAXIAN_1K.hex b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/k.hex
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/GALAXIAN_1K.hex
rename to Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/k.hex
diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/kb_prog.hex b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/prog.hex
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/kb_prog.hex
rename to Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/ROM/prog.hex
diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/build_id.v b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/build_id.v
index f6d22cf2..adcfa042 100644
--- a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/build_id.v	
+++ b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/build_id.v	
@@ -1,2 +1,2 @@
-`define BUILD_DATE "181028"
-`define BUILD_TIME "105037"
+`define BUILD_DATE "190101"
+`define BUILD_TIME "170231"
diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/kingballon.vhd b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/kingballon.vhd
index 2238dae1..3bfa76cb 100644
--- a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/kingballon.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/kingballon.vhd	
@@ -342,19 +342,9 @@ port map(
 		O_SDAT        => W_SDAT_B
 	);
 
---------- ROM           -------------------------------------------------------
---	mc_roms : entity work.ROM_PGM_0
---	port map (
---		CLK  => W_CLK_12M,
---		ADDR => W_A(13 downto 0),
---		DATA => W_CPU_ROM_DO
---	);
-
-
-
 	mc_roms : entity work.sprom
 	generic map (
-		init_file  => "./ROM/kb_prog.hex",
+		init_file  => "./ROM/prog.hex",
 		widthad_a  => 14,
 		width_a  => 8)
 	port map (
diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/mc_col_pal.vhd
index 756e7cc0..0b4ac592 100644
--- a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/mc_col_pal.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/mc_col_pal.vhd	
@@ -63,16 +63,9 @@ begin
 	---    COL ROM     --------------------------------------------------------
 --wire   W_COL_ROM_OEn = W_6M_DO[1];
 
---	galaxian_6l : entity work.GALAXIAN_6L
---	port map (
---		CLK  => I_CLK_12M,
---		ADDR => W_6M_DO(6 downto 2),
---		DATA => W_COL_ROM_DO
---	);
-	
 	galaxian_6l : entity work.sprom
 	generic map (
-		init_file  => "./ROM/prom.hex",
+		init_file  => "./ROM/col.hex",
 		widthad_a  => 5,
 		width_a  => 8)
 	port map (
diff --git a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/mc_video.vhd
index e521fb71..11ce2940 100644
--- a/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/mc_video.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/KingBaloon_MiST/rtl/mc_video.vhd	
@@ -219,25 +219,9 @@ begin
 		O_DB    => W_VID_RAM_DOB
 	);
 
-	-- 1K VID-Rom
---	k_rom : entity work.GALAXIAN_1K 
---	port map (
---		CLK  => I_CLK_12M,
---		ADDR => W_O_OBJ_ROM_A,
---		DATA => W_1K_D
---	);
-
-	-- 1H VID-Rom
---	h_rom : entity work.GALAXIAN_1H
---	port map(
---		CLK  => I_CLK_12M,
---		ADDR => W_O_OBJ_ROM_A,
---		DATA => W_1H_D
---	);
-	
 	k_rom : entity work.sprom
 	generic map (
-		init_file  => "./ROM/GALAXIAN_1K.hex",
+		init_file  => "./ROM/k.hex",
 		widthad_a  => 11,
 		width_a  => 8)
 	port map (
@@ -248,7 +232,7 @@ begin
 	
 	h_rom : entity work.sprom
 	generic map (
-		init_file  => "./ROM/GALAXIAN_1H.hex",
+		init_file  => "./ROM/h.hex",
 		widthad_a  => 11,
 		width_a  => 8)
 	port map (
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/invaders_memory.sv b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/invaders_memory.sv
index ce66bd1d..ef52cf36 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/invaders_memory.sv	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/invaders_memory.sv	
@@ -30,7 +30,8 @@ sprom #(
 `ifdef seawolf		.init_file("./roms/Seawolf/sw0041_h.hex"), `endif//not working
 `ifdef dogpatch	.init_file("./roms/Dogpatch/dogpatch_h.hex"), `endif//not working
 `ifdef jspecter	.init_file("./roms/jspecter/rom_h.hex"), `endif//not working
-`ifdef invadrev	.init_file("./roms/InvadersRevenge/invrvnge_e.hex"), `endif//not working
+`ifdef invadrev	.init_file("./roms/InvadersRevenge/invrvnge_e.hex"), `endif//not 
+`ifdef blueshark	.init_file("./roms/BlueShark/blueshrk_h.hex"), `endif//
 `ifdef zzzap280	.widthad_a(10), `endif//
 `ifdef generic	.widthad_a(11), `endif//
 //	.widthad_a(11), 
@@ -54,6 +55,7 @@ sprom #(
 `ifdef dogpatch	.init_file("./roms/Dogpatch/dogpatch_g.hex"), `endif//not working
 `ifdef jspecter	.init_file("./roms/jspecter/rom_g.hex"), `endif//not working
 `ifdef invadrev	.init_file("./roms/InvadersRevenge/invrvnge_f.hex"), `endif//not working
+`ifdef blueshark	.init_file("./roms/BlueShark/blueshrk_g.hex"), `endif//
 `ifdef zzzap280	.widthad_a(10), `endif//
 `ifdef generic	.widthad_a(11), `endif//
 //	.widthad_a(11), 
@@ -77,6 +79,7 @@ sprom #(
 `ifdef dogpatch	.init_file("./roms/Dogpatch/dogpatch_f.hex"), `endif//not working
 `ifdef jspecter	.init_file("./roms/jspecter/rom_f.hex"), `endif//not working
 `ifdef invadrev	.init_file("./roms/InvadersRevenge/invrvnge_g.hex"), `endif//not working
+`ifdef blueshark	.init_file("./roms/BlueShark/blueshrk_f.hex"), `endif//
 `ifdef zzzap280	.widthad_a(10), `endif//
 `ifdef generic	.widthad_a(11), `endif//
 //	.widthad_a(11), 
@@ -88,6 +91,7 @@ u_rom_f (
 	.q(rom_data_2)
 	);
 	
+`ifndef blueshark
 sprom #(
 `ifdef sflush	.init_file("./roms/Strightflush/fr04_sc3.hex"), `endif//
 `ifdef zzzap280	.init_file("./roms/280zzz/zzzap_f.hex"), `endif//not working
@@ -109,7 +113,7 @@ u_rom_e (
 `ifdef generic	.Address(Addr[10:0]), `endif
 	.q(rom_data_3)
 	);
-	
+	`endif//	
 `ifndef generic
 sprom #(
 `ifdef sflush	.init_file("./roms/Strightflush/fr05_sc2.hex"), `endif//
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_f.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_f.hex
new file mode 100644
index 00000000..557f06b1
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_f.hex	
@@ -0,0 +1,129 @@
+:1000000066667E3C181C1818181818183C3C3C7E74
+:1000100066607C3E06067E7E3C7E66603878606662
+:100020007E3C666666667E7E606060603E3E06067A
+:100030003E7E60667E3C3C3E06063E7E66667E3CBC
+:100040007E7E60703038181C0C0C3C7E66663C7EF0
+:1000500066667E3C3C7E66667E7C60667E3C00001A
+:100060000000000000000000183C7E6666667E7E90
+:1000700066663E7E66663E7E66667E3E3C7E6606C2
+:10008000060606667E3C3E7E6666666666667E3E62
+:100090007E7E06063E3E06067E7E7E7E06063E3E50
+:1000A000060606063C7E6606067676667E3C666634
+:1000B00066667E7E666666663C3C181818181818D8
+:1000C0003C3C60606060606060667E3C6666763E78
+:1000D0001E1E3E76666606060606060606067E7E38
+:1000E000C3C3E7E7FFFFDBC3C3C366666E6E7E7EF6
+:1000F000767666663E7E66667E3E060606063C7E32
+:100100006666666666767E5C3E7E66667E3E766681
+:1001100066663C7E66063E7C60667E3C7E7E181887
+:1001200018181818181866666666666666667E3C55
+:1001300066666666667E3C3C1818C3C3C3DBFFFF79
+:10014000E7E7C3C366667E3C18183C7E6666666653
+:100150007E3C1818181818187E7E6070381C0E0621
+:100160007E7E3C7E6666703818001818000000001D
+:100170003C3C00000000050D0000C000000100F83C
+:1001800001000300FF030086E0FF0F000CFFFF7F6C
+:1001900000FCFFFFDF01F8FFFFFFFF18FFFF7F00FC
+:1001A0008C01FFFF00068001060003000002000131
+:1001B000000001000000800000050D00008001002B
+:1001C0004000F003004000FE070040C4FF1F00C0D5
+:1001D000F8FF7F0080FFFFDF0180FFFFFFFFC0F817
+:1001E000FFFF004008FCFF014000060C0040000239
+:1001F000060000000003000000000000041E0001D3
+:1002000000000000000000000000000000000000EE
+:10021000000000400000000000000000000000009E
+:1002200000000000000000000000000000000000CE
+:100230000E0000FC1E0000CC1E0000301E0000FE60
+:100240000F0000F7C77F00FF6F0280F71F07800FC6
+:10025000FC03C107F800FF030000FF010000FF00DE
+:10026000000001000000010000000100000001008A
+:10027000000000000000041E00000000000000005C
+:10028000000000000004000000000000000000006A
+:10029000000000000000010000400000000000001D
+:1002A000000002000000000000001C0000F83D00FB
+:1002B00000983D0004603C000EFC1F001EEE8FFF06
+:1002C0003BFFDF04F1EF3F0EE11FF807C003F00131
+:1002D0008000000020000000700000001C000000F2
+:1002E0000C000000040000000400000004000000F6
+:1002F00002118003C007E007E007A006E0036003E7
+:10030000C0018003C007F60FEC5BB073D8064E0C3B
+:100310004238C000021100008007C00FE00F400FFC
+:10032000F00FF0C78483CCC7F06FD83BED06A74D24
+:1003300030791003180E0000021500002000200084
+:1003400038003C0060006001C000C000C000C00177
+:10035000C001D009700D200740034001C001C0005A
+:10036000C001800102150001000100010007800F9B
+:10037000A001C000C000C000E000E000E402AC0347
+:100380003801B000A000E000C000E0006000000004
+:1003900002158001C001C000C001400140032007D8
+:1003A000700DD009C001C001C000C000C0006001D4
+:1003B00060003C0038002000200000000215000012
+:1003C0006000E000C000E000A000B0003801AC0315
+:1003D000E402E000E000C000C000C000A001800F07
+:1003E0000007000100010001040C000008000100EA
+:1003F00018000300380006007C008CC0FF071CFFBB
+:10040000FF3FF8FFFFDFF8FFFFFF0C81DF3F06C073
+:10041000C0000000600000003000040C000010006C
+:1004200000003000200070002000F8002084FF0F42
+:1004300060FCFF3FC0FFFFDFC0FFFFFF6004BF1F86
+:10044000200081012000C0000000400003100000D7
+:10045000E00000F800F0BF00E07F00C01F00E00FE8
+:1004600000F809047F080C5E00980700F005007092
+:1004700000002000002000002000002000000310E9
+:10048000080000180000300000600000C00402F006
+:100490000502001F03007E0300F90300E00700F0DF
+:1004A0001F00803F00007E0000FF0080D90000E0B8
+:1004B000040B0000080060001800C0003800800134
+:1004C00078000013FC0300FFFF3F00FFFFDF8013F5
+:1004D000FF7FC08000030000800100008000011346
+:1004E0000814080808080808080808080808080880
+:1004F000080808011008140808080808080808086F
+:100500000808080808010D08000808080808080875
+:1005100008080808010A0800080808080808080868
+:10052000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDB
+:10053000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCB
+:10054000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB
+:10055000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAB
+:10056000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9B
+:10057000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8B
+:10058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B
+:10059000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6B
+:1005A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5B
+:1005B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4B
+:1005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B
+:1005D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2B
+:1005E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1B
+:1005F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0B
+:10060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA
+:10061000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEA
+:10062000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA
+:10063000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCA
+:10064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA
+:10065000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAA
+:10066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A
+:10067000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8A
+:10068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A
+:10069000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6A
+:1006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A
+:1006B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4A
+:1006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A
+:1006D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2A
+:1006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A
+:1006F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0A
+:10070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9
+:10071000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9
+:10072000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9
+:10073000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC9
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+:1007E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF19
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+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_g.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_g.hex
new file mode 100644
index 00000000..8923d41f
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_g.hex	
@@ -0,0 +1,129 @@
+:10000000A7F2050837171213230605CD7D0F21022D
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+:10074000816FC5E51AD302DB00AE77132B0DC244CF
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+:10076000420FC92100240120E0C5E53600230DC257
+:100770006B0FE101200009C105C2690FC97E121388
+:100780002305C27D0FC9E52A0520291717AD17AD2E
+:100790001F1F2FE601B56F220520E1C9171213258F
+:1007A0001C0D001B0F0A0A0A1D13170F0A0A0A1C48
+:1007B0000D001B0F07251C1D0B1B1D2509110B17F9
+:1007C0000F0A001F0F1B061B0F19160B220B110B14
+:1007D000170F0A1B0F0B0E22240302000003030055
+:1007E00000030500000304000004250500000B13AE
+:1007F000181C0F1B1D0A0D0013183C7E66666666EA
+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_h.hex b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_h.hex
new file mode 100644
index 00000000..212503d2
--- /dev/null
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_MiST/rtl/roms/BlueShark/blueshrk_h.hex	
@@ -0,0 +1,129 @@
+:10000000310024C31800FFFFF5E5D5C5FBC342024C
+:10001000F5E5D5C5FBC3710321002001201FCD6983
+:100020000FDB02E680CA3300CDC60CAFD302D30388
+:10003000C3B100CD630FFBC33700AF3200200120F6
+:1000400018211420F3CD690FAFD303FBCD630F113B
+:100050000A20210F2006031ABECA6200DA6B00D202
+:100060007300132305C25700C373007E12132305C8
+:10007000C26B00CDC60C11BC0F210630CD2C0D3E3D
+:10008000783208203A0820A7D304C2840001201443
+:10009000210630CD690F210220AFBECAA60036006E
+:1000A0002B3600C3B1002BBECAB1002336FFC313E9
+:1000B00001012018211420F3CD690FAFD303FBCD2C
+:1000C000C60C3E20323E203A0420A7C23901F3CDAF
+:1000D000FB00FB11EE0F210430CD2C0D3E783208D1
+:1000E000203A0420A7C239013A0820A7D304C2E16C
+:1000F00000213E2035C2D300C3B10021018022007F
+:100100002121010022082121010022102121222089
+:100110003618C9CD630F11C60F210A2CCD2C0D1135
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+:1007A0000DAF323820210821360B237EE64007C2E8
+:1007B000B4073EFF3228207EE6F0F6077706F7C33F
+:1007C000FF0C06FBCDFF0C1AE64007C2D0073EFF28
+:1007D000322720210400220821C9CD860FE638FEE9
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+:00000001FF
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf
index b18fc331..3bd720e6 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/Invaders.qsf	
@@ -48,7 +48,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/Invaders_mist.sv
 set_global_assignment -name VHDL_FILE rtl/invaders.vhd
 set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
 set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
-set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv
 set_global_assignment -name QIP_FILE rtl/pll.qip
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
@@ -177,4 +176,5 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 # end ENTITY(Invaders_mist)
 # -------------------------
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu8080.sv
+set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv
index 80f095d6..eada9535 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/Invaders_mist.sv	
@@ -1,21 +1,25 @@
 `define generic
+//`define noDIP
 `define invaders
 `ifdef invaders 
 	`define dip = 8'b00000000 
 `endif
+
 //`define supearth
 `ifdef supearth 
 	`define dip = 8'b11000000 //4 lifes check this
 `endif
+
 //`define slaser
 `ifdef slaser 
 	`define dip = 8'b00000000 //untested
 `endif
 
-//`define sflush
-`ifdef sflush 
-	`define dip = 8'b00000000 //untested
+//`define blueshark  Sync Problems
+`ifdef blueshark 
+	`define dip = "00100100" //todo
 `endif
+
 //TODO
 //`define lrescue
 
@@ -58,9 +62,11 @@ localparam CONF_STR = {
 `ifdef invaders "Space Inv.;;", `endif
 `ifdef supearth "SEarthInv.;;", `endif
 `ifdef slaser "Space Laser;;", `endif
-	"Midway 8080.;;",
+`ifdef blueshark "Blue Shark;;", `endif
+`ifdef noDIP "Midway 8080.;;", `endif
 	"O2,Joystick Control,Upright,Normal;",
 	"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+	"O5,Overlay, On, Off;",
 	"T6,Reset;",
 	"V,v1.00.",`BUILD_DATE
 };
@@ -221,6 +227,7 @@ invaders_audio invaders_audio (
 	  
 invaders_video invaders_video (
 	.Video(Video),
+	.Overlay(~status[5]),
 	.CLK(clk_sys),
 	.Rst_n_s(Rst_n_s),
 	.HSync(HSync),
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v
index 28058561..21a4b647 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/build_id.v	
@@ -1,2 +1,2 @@
-`define BUILD_DATE "181229"
-`define BUILD_TIME "040306"
+`define BUILD_DATE "190102"
+`define BUILD_TIME "031130"
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders.vhd
index 2bf98881..21326c26 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders.vhd	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders.vhd	
@@ -210,20 +210,20 @@ begin
 	GDB1(0) <= not Coin;-- Active High !
 	GDB1(1) <= not Sel2Player;
 	GDB1(2) <= not Sel1Player;
-	GDB1(3) <= '1';             -- Unused ?
+	GDB1(3) <= '1';-- Unused ?
 	GDB1(4) <= not Fire;
 	GDB1(5) <= not MoveLeft;
 	GDB1(6) <= not MoveRight;
-	GDB1(7) <= '1';             -- Unused ?
+	GDB1(7) <= '1';-- Unused ?
 
 	GDB2(0) <= DIP(4);  -- LSB Lives 3-6
 	GDB2(1) <= DIP(3);  -- MSB Lives 3-6
-	GDB2(2) <= '0';             -- Tilt ?
-	GDB2(3) <= DIP(2);  -- Bonus life at 1000 or 1500
+	GDB2(2) <= '0';-- Tilt ?
+	GDB2(3) <= '0';--DIP(2);  -- Bonus life at 1000 or 1500
 	GDB2(4) <= not Fire;
 	GDB2(5) <= not MoveLeft;
 	GDB2(6) <= not MoveRight;
-	GDB2(7) <= DIP(1);  -- Coin info
+	GDB2(7) <= '1';--DIP(1);  -- Coin info
 
 	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
 	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
diff --git a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_video.vhd b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_video.vhd
index ed3007f7..77ac2478 100644
--- a/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_video.vhd	
+++ b/Arcade_MiST/Midway8080 Hardware/Midway8080v2_Mist/rtl/invaders_video.vhd	
@@ -6,7 +6,8 @@ library ieee;
 
 entity invaders_video is
 	port(
-		Video             : in    std_logic;	
+		Video             : in    std_logic;
+		Overlay           : in    std_logic;
 		CLK               : in    std_logic;
 		Rst_n_s           : in    std_logic;
 		HSync             : in    std_logic;
@@ -116,9 +117,9 @@ begin
   end process;
 
 
-  O_VIDEO_R <= VideoRGB(2);
-  O_VIDEO_G <= VideoRGB(1);
-  O_VIDEO_B <= VideoRGB(0);
+  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
+  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
   O_HSYNC   <= not HSync;
   O_VSYNC   <= not VSync;
 
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/ace.qsf b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/ace.qsf
index dba20537..06907e8f 100644
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/ace.qsf	
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/ace.qsf	
@@ -44,25 +44,6 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05  MARCH 16, 2017
 set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/glue.v
-set_global_assignment -name VERILOG_FILE rtl/T80/tv80n.v
-set_global_assignment -name VERILOG_FILE rtl/T80/tv80_reg.v
-set_global_assignment -name VERILOG_FILE rtl/T80/tv80_mcode.v
-set_global_assignment -name VERILOG_FILE rtl/T80/tv80_core.v
-set_global_assignment -name VERILOG_FILE rtl/T80/tv80_alu.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/ace_mist.sv
-set_global_assignment -name QIP_FILE rtl/pll.qip
-set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
-set_global_assignment -name VERILOG_FILE rtl/jupiter_ace.v
-set_global_assignment -name VERILOG_FILE rtl/keyboard.v
-set_global_assignment -name VERILOG_FILE rtl/rom_ram.v
-set_global_assignment -name VERILOG_FILE rtl/ps2_port.v
-set_global_assignment -name VERILOG_FILE rtl/io_write_to_rom.v
 
 # Pin & Location Assignments
 # ==========================
@@ -202,14 +183,32 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulati
 
 		# Incremental Compilation Assignments
 		# ===================================
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(ace_mist)
 # --------------------
-set_global_assignment -name VERILOG_FILE rtl/sram.v
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/ace_mist.sv
+set_global_assignment -name VERILOG_FILE rtl/jupiter_ace.v
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80pa.vhd
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name QIP_FILE rtl/pll.qip
+set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video.sv
+set_global_assignment -name VERILOG_FILE rtl/dpram.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80.vhd b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80.vhd
new file mode 100644
index 00000000..bb300321
--- /dev/null
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80.vhd	
@@ -0,0 +1,1175 @@
+--------------------------------------------------------------------------------
+-- ****
+-- T80(c) core. Attempt to finish all undocumented features and provide
+--              accurate timings.
+-- Version 350.
+-- Copyright (c) 2018 Sorgelig
+--  Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
+--  (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
+--      correct implementation is still unclear.
+--
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup.
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--      0210 : Fixed wait and halt
+--      0211 : Fixed Refresh addition and IM 1
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--      0237 : Changed 8080 I/O address output, added IntE output
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 0 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n    : in  std_logic;
+		CLK_n      : in  std_logic;
+		CEN        : in  std_logic;
+		WAIT_n     : in  std_logic;
+		INT_n      : in  std_logic;
+		NMI_n      : in  std_logic;
+		BUSRQ_n    : in  std_logic;
+		M1_n       : out std_logic;
+		IORQ       : out std_logic;
+		NoRead     : out std_logic;
+		Write      : out std_logic;
+		RFSH_n     : out std_logic;
+		HALT_n     : out std_logic;
+		BUSAK_n    : out std_logic;
+		A          : out std_logic_vector(15 downto 0);
+		DInst      : in  std_logic_vector(7 downto 0);
+		DI         : in  std_logic_vector(7 downto 0);
+		DO         : out std_logic_vector(7 downto 0);
+		MC         : out std_logic_vector(2 downto 0);
+		TS         : out std_logic_vector(2 downto 0);
+		IntCycle_n : out std_logic;
+		IntE       : out std_logic;
+		Stop       : out std_logic;
+		out0       : in  std_logic := '0';  -- 0 => OUT(C),0, 1 => OUT(C),255
+		REG        : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
+
+		DIRSet     : in  std_logic := '0';
+		DIR        : in  std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	constant aNone              : std_logic_vector(2 downto 0) := "111";
+	constant aBC                : std_logic_vector(2 downto 0) := "000";
+	constant aDE                : std_logic_vector(2 downto 0) := "001";
+	constant aXY                : std_logic_vector(2 downto 0) := "010";
+	constant aIOA               : std_logic_vector(2 downto 0) := "100";
+	constant aSP                : std_logic_vector(2 downto 0) := "101";
+	constant aZI                : std_logic_vector(2 downto 0) := "110";
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal WZ                   : std_logic_vector(15 downto 0);        -- MEMPTR register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_RXDD               : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetWZ                : std_logic_vector(1 downto 0);
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+	signal XYbit_undoc          : std_logic;
+	signal DOR                  : std_logic_vector(127 downto 0);
+
+begin
+
+	REG <= IntE_FF2 & IntE_FF1 & IStatus & DOR & std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC when Alternate = '0' 
+			 else IntE_FF2 & IntE_FF1 & IStatus & DOR(127 downto 112) & DOR(47 downto 0) & DOR(63 downto 48) & DOR(111 downto 64) & 
+						std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC;
+
+	mcode : work.T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			XY_State    => XY_State,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetWZ       => SetWZ,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write,
+			XYbit_undoc => XYbit_undoc);
+
+	alu : work.T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			WZ      => WZ,
+			XY_State=> XY_State,
+			ALU_Op  => ALU_Op_r,
+			IR      => IR(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+	process (RESET_n, CLK_n)
+		variable n : std_logic_vector(7 downto 0);
+		variable ioq : std_logic_vector(8 downto 0);
+	begin
+		if RESET_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			A <= (others => '0');
+			WZ <= (others => '0');
+			IR <= "00000000";
+			ISet <= "00";
+			XY_State <= "00";
+			IStatus <= "00";
+			MCycles <= "000";
+			DO <= "00000000";
+
+			ACC <= (others => '1');
+			F <= (others => '1');
+			Ap <= (others => '1');
+			Fp <= (others => '1');
+			I <= (others => '0');
+			R <= (others => '0');
+			SP <= (others => '1');
+			Alternate <= '0';
+
+			Read_To_Reg_r <= "00000";
+			Arith16_r <= '0';
+			BTR_r <= '0';
+			Z16_r <= '0';
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			PreserveC_r <= '0';
+			XY_Ind <= '0';
+			I_RXDD <= '0';
+
+		elsif rising_edge(CLK_n) then
+		
+			if DIRSet = '1' then
+				ACC <= DIR( 7 downto  0);
+				F   <= DIR(15 downto  8);
+				Ap  <= DIR(23 downto 16);
+				Fp  <= DIR(31 downto 24);
+				I   <= DIR(39 downto 32);
+				R   <= unsigned(DIR(47 downto 40));
+				SP  <= unsigned(DIR(63 downto 48));
+				PC  <= unsigned(DIR(79 downto 64));
+				A   <= DIR(79 downto 64);
+				IStatus <= DIR(209 downto 208);
+
+			elsif ClkEn = '1' then
+				ALU_Op_r <= "0000";
+				Save_ALU_r <= '0';
+				Read_To_Reg_r <= "00000";
+
+				MCycles <= MCycles_d;
+
+				if IMode /= "11" then
+					IStatus <= IMode;
+				end if;
+
+				Arith16_r <= Arith16;
+				PreserveC_r <= PreserveC;
+				if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+					Z16_r <= '1';
+				else
+					Z16_r <= '0';
+				end if;
+
+				if MCycle  = "001" and TState(2) = '0' then
+				-- MCycle = 1 and TState = 1, 2, or 3
+
+					if TState = 2 and Wait_n = '1' then
+						if Mode < 2 then
+							A(7 downto 0) <= std_logic_vector(R);
+							A(15 downto 8) <= I;
+							R(6 downto 0) <= R(6 downto 0) + 1;
+						end if;
+
+						if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
+							PC <= PC + 1;
+						end if;
+
+						if IntCycle = '1' and IStatus = "01" then
+							IR <= "11111111";
+						elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
+							IR <= "00000000";
+						else
+							IR <= DInst;
+						end if;
+
+						ISet <= "00";
+						if Prefix /= "00" then
+							if Prefix = "11" then
+								if IR(5) = '1' then
+									XY_State <= "10";
+								else
+									XY_State <= "01";
+								end if;
+							else
+								if Prefix = "10" then
+									XY_State <= "00";
+									XY_Ind <= '0';
+								end if;
+								ISet <= Prefix;
+							end if;
+						else
+							XY_State <= "00";
+							XY_Ind <= '0';
+						end if;
+					end if;
+
+				else
+				-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+					if MCycle = "110" then
+						XY_Ind <= '1';
+						if Prefix = "01" then
+							ISet <= "01";
+						end if;
+					end if;
+
+					if T_Res = '1' then
+						BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+						if Jump = '1' then
+							A(15 downto 8) <= DI_Reg;
+							A(7 downto 0) <= WZ(7 downto 0);
+							PC(15 downto 8) <= unsigned(DI_Reg);
+							PC(7 downto 0) <= unsigned(WZ(7 downto 0));
+						elsif JumpXY = '1' then
+							A <= RegBusC;
+							PC <= unsigned(RegBusC);
+						elsif Call = '1' or RstP = '1' then
+							A <= WZ;
+							PC <= unsigned(WZ);
+						elsif MCycle = MCycles and NMICycle = '1' then
+							A <= "0000000001100110";
+							PC <= "0000000001100110";
+						elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
+							A(15 downto 8) <= I;
+							A(7 downto 0) <= WZ(7 downto 0);
+							PC(15 downto 8) <= unsigned(I);
+							PC(7 downto 0) <= unsigned(WZ(7 downto 0));
+						else
+							case Set_Addr_To is
+							when aXY =>
+								if XY_State = "00" then
+									A <= RegBusC;
+								else
+									if NextIs_XY_Fetch = '1' then
+										A <= std_logic_vector(PC);
+									else
+										A <= WZ;
+									end if;
+								end if;
+							when aIOA =>
+								if Mode = 3 then
+									-- Memory map I/O on GBZ80
+									A(15 downto 8) <= (others => '1');
+								elsif Mode = 2 then
+									-- Duplicate I/O address on 8080
+									A(15 downto 8) <= DI_Reg;
+								else
+									A(15 downto 8) <= ACC;
+								end if;
+								A(7 downto 0) <= DI_Reg;
+								WZ <= (ACC & DI_Reg) + "1";
+							when aSP =>
+								A <= std_logic_vector(SP);
+							when aBC =>
+								if Mode = 3 and IORQ_i = '1' then
+									-- Memory map I/O on GBZ80
+									A(15 downto 8) <= (others => '1');
+									A(7 downto 0) <= RegBusC(7 downto 0);
+								else
+									A <= RegBusC;
+									if SetWZ = "01" then
+										WZ <= RegBusC + "1";
+									end if;
+									if SetWZ = "10" then
+										WZ(7 downto 0) <= RegBusC(7 downto 0) + "1";
+										WZ(15 downto 8) <= ACC;
+									end if;
+								end if;
+							when aDE =>
+								A <= RegBusC;
+								if SetWZ = "10" then
+									WZ(7 downto 0) <= RegBusC(7 downto 0) + "1";
+									WZ(15 downto 8) <= ACC;
+								end if;
+							when aZI =>
+								if Inc_WZ = '1' then
+									A <= std_logic_vector(unsigned(WZ) + 1);
+								else
+									A(15 downto 8) <= DI_Reg;
+									A(7 downto 0) <= WZ(7 downto 0);
+									if SetWZ = "10" then
+										WZ(7 downto 0) <= WZ(7 downto 0) + "1";
+										WZ(15 downto 8) <= ACC;
+									end if;
+								end if;
+							when others =>
+								A <= std_logic_vector(PC);
+							end case;
+						end if;
+						
+						if SetWZ = "11" then
+							WZ <= std_logic_vector(ID16);
+						end if;
+
+						Save_ALU_r <= Save_ALU;
+						ALU_Op_r <= ALU_Op;
+
+						if I_CPL = '1' then
+							-- CPL
+							ACC <= not ACC;
+							F(Flag_Y) <= not ACC(5);
+							F(Flag_H) <= '1';
+							F(Flag_X) <= not ACC(3);
+							F(Flag_N) <= '1';
+						end if;
+						if I_CCF = '1' then
+							-- CCF
+							F(Flag_C) <= not F(Flag_C);
+							F(Flag_Y) <= ACC(5);
+							F(Flag_H) <= F(Flag_C);
+							F(Flag_X) <= ACC(3);
+							F(Flag_N) <= '0';
+						end if;
+						if I_SCF = '1' then
+							-- SCF
+							F(Flag_C) <= '1';
+							F(Flag_Y) <= ACC(5);
+							F(Flag_H) <= '0';
+							F(Flag_X) <= ACC(3);
+							F(Flag_N) <= '0';
+						end if;
+					end if;
+					
+					if (TState = 2 and I_BTR = '1' and IR(0) = '1') or (TState = 1 and I_BTR = '1' and IR(0) = '0') then
+						ioq := ('0' & DI_Reg) + ('0' & std_logic_vector(ID16(7 downto 0)));
+						F(Flag_N) <= DI_Reg(7);
+						F(Flag_C) <= ioq(8);
+						F(Flag_H) <= ioq(8);
+						ioq := (ioq and x"7") xor ('0'&BusA);
+						F(Flag_P) <= not (ioq(0) xor ioq(1) xor ioq(2) xor ioq(3) xor ioq(4) xor ioq(5) xor ioq(6) xor ioq(7));
+					end if;
+
+					if TState = 2 and Wait_n = '1' then
+						if ISet = "01" and MCycle = "111" then
+							IR <= DInst;
+						end if;
+						if JumpE = '1' then
+							PC <= unsigned(signed(PC) + signed(DI_Reg));
+							WZ <= std_logic_vector(signed(PC) + signed(DI_Reg));
+						elsif Inc_PC = '1' then
+							PC <= PC + 1;
+						end if;
+						if BTR_r = '1' then
+							PC <= PC - 2;
+						end if;
+						if RstP = '1' then
+							WZ <= (others =>'0');
+							WZ(5 downto 3) <= IR(5 downto 3);
+						end if;
+					end if;
+					if TState = 3 and MCycle = "110" then
+						WZ <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+					end if;
+
+					if MCycle = "011" and TState = 4 and No_BTR = '0' then
+						if I_BT = '1' or I_BC = '1' then
+							WZ <= std_logic_vector(PC)-"1";
+						end if;
+					end if;
+
+					if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
+						if IncDec_16(2 downto 0) = "111" then
+							if IncDec_16(3) = '1' then
+								SP <= SP - 1;
+							else
+								SP <= SP + 1;
+							end if;
+						end if;
+					end if;
+
+					if LDSPHL = '1' then
+						SP <= unsigned(RegBusC);
+					end if;
+					if ExchangeAF = '1' then
+						Ap <= ACC;
+						ACC <= Ap;
+						Fp <= F;
+						F <= Fp;
+					end if;
+					if ExchangeRS = '1' then
+						Alternate <= not Alternate;
+					end if;
+				end if;
+
+				if TState = 3 then
+					if LDZ = '1' then
+						WZ(7 downto 0) <= DI_Reg;
+					end if;
+					if LDW = '1' then
+						WZ(15 downto 8) <= DI_Reg;
+					end if;
+
+					if Special_LD(2) = '1' then
+						case Special_LD(1 downto 0) is
+						when "00" =>
+							ACC <= I;
+							F(Flag_P) <= IntE_FF2;
+							F(Flag_S) <= I(7);
+							
+							if I = x"00" then 
+								F(Flag_Z) <= '1';
+							else
+								F(Flag_Z) <= '0';
+							end if;
+
+							F(Flag_Y) <= I(5);
+							F(Flag_H) <= '0';
+							F(Flag_X) <= I(3);
+							F(Flag_N) <= '0';
+
+
+						when "01" =>
+							ACC <= std_logic_vector(R);
+							F(Flag_P) <= IntE_FF2;
+							F(Flag_S) <= R(7);
+							
+							if R = x"00" then 
+								F(Flag_Z) <= '1';
+							else
+								F(Flag_Z) <= '0';
+							end if;
+							
+							F(Flag_Y) <= R(5);
+							F(Flag_H) <= '0';
+							F(Flag_X) <= R(3);
+							F(Flag_N) <= '0';
+
+						when "10" =>
+							I <= ACC;
+						when others =>
+							R <= unsigned(ACC);
+						end case;
+					end if;
+				end if;
+
+				if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+					if Mode = 3 then
+						F(6) <= F_Out(6);
+						F(5) <= F_Out(5);
+						F(7) <= F_Out(7);
+						if PreserveC_r = '0' then
+							F(4) <= F_Out(4);
+						end if;
+					else
+						F(7 downto 1) <= F_Out(7 downto 1);
+						if PreserveC_r = '0' then
+							F(Flag_C) <= F_Out(0);
+						end if;
+					end if;
+				end if;
+				if T_Res = '1' and I_INRC = '1' then
+					F(Flag_H) <= '0';
+					F(Flag_N) <= '0';
+					F(Flag_X) <= DI_Reg(3);
+					F(Flag_Y) <= DI_Reg(5);
+					if DI_Reg(7 downto 0) = "00000000" then
+						F(Flag_Z) <= '1';
+					else
+						F(Flag_Z) <= '0';
+					end if;
+					F(Flag_S) <= DI_Reg(7);
+					F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+						DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+				end if;
+
+				if TState = 1 and Auto_Wait_t1 = '0' then
+					-- Keep D0 from M3 for RLD/RRD (Sorgelig)
+					I_RXDD <= I_RLD or I_RRD;
+					if I_RXDD='0' then
+						DO <= BusB;
+					end if;
+					if I_RLD = '1' then
+						DO(3 downto 0) <= BusA(3 downto 0);
+						DO(7 downto 4) <= BusB(3 downto 0);
+					end if;
+					if I_RRD = '1' then
+						DO(3 downto 0) <= BusB(7 downto 4);
+						DO(7 downto 4) <= BusA(3 downto 0);
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+					Read_To_Reg_r(4) <= Read_To_Reg;
+					if Read_To_Acc = '1' then
+						Read_To_Reg_r(3 downto 0) <= "0111";
+						Read_To_Reg_r(4) <= '1';
+					end if;
+				end if;
+
+				if TState = 1 and I_BT = '1' then
+					F(Flag_X) <= ALU_Q(3);
+					F(Flag_Y) <= ALU_Q(1);
+					F(Flag_H) <= '0';
+					F(Flag_N) <= '0';
+				end if;
+				if TState = 1 and I_BC = '1' then
+					n := ALU_Q - ("0000000" & F_Out(Flag_H));
+					F(Flag_X) <= n(3);
+					F(Flag_Y) <= n(1);
+				end if;
+				if I_BC = '1' or I_BT = '1' then
+					F(Flag_P) <= IncDecZ;
+				end if;
+
+				if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
+					(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+					case Read_To_Reg_r is
+					when "10111" =>
+						ACC <= Save_Mux;
+					when "10110" =>
+						DO <= Save_Mux;
+					when "11000" =>
+						SP(7 downto 0) <= unsigned(Save_Mux);
+					when "11001" =>
+						SP(15 downto 8) <= unsigned(Save_Mux);
+					when "11011" =>
+						F <= Save_Mux;
+					when others =>
+					end case;
+					if XYbit_undoc='1' then
+						DO <= ALU_Q;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if rising_edge(CLK_n) then
+			if ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : work.T80_Reg
+		port map(
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0),
+			DOR  => DOR,
+			DIRSet => DIRSet,
+			DIR  => DIR(207 downto 80));
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+	process (CLK_n)
+	begin
+		if rising_edge(CLK_n) then
+			if ClkEn = '1' then
+				case Set_BusB_To is
+				when "0111" =>
+					BusB <= ACC;
+				when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+					if Set_BusB_To(0) = '1' then
+						BusB <= RegBusB(7 downto 0);
+					else
+						BusB <= RegBusB(15 downto 8);
+					end if;
+				when "0110" =>
+					BusB <= DI_Reg;
+				when "1000" =>
+					BusB <= std_logic_vector(SP(7 downto 0));
+				when "1001" =>
+					BusB <= std_logic_vector(SP(15 downto 8));
+				when "1010" =>
+					BusB <= "00000001";
+				when "1011" =>
+					BusB <= F;
+				when "1100" =>
+					BusB <= std_logic_vector(PC(7 downto 0));
+				when "1101" =>
+					BusB <= std_logic_vector(PC(15 downto 8));
+				when "1110" =>
+					if IR = x"71" and out0 = '1' then
+						BusB <= "11111111";
+					else
+					BusB <= "00000000";
+					end if;
+				when others =>
+					BusB <= "--------";
+				end case;
+
+				case Set_BusA_To is
+				when "0111" =>
+					BusA <= ACC;
+				when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+					if Set_BusA_To(0) = '1' then
+						BusA <= RegBusA(7 downto 0);
+					else
+						BusA <= RegBusA(15 downto 8);
+					end if;
+				when "0110" =>
+					BusA <= DI_Reg;
+				when "1000" =>
+					BusA <= std_logic_vector(SP(7 downto 0));
+				when "1001" =>
+					BusA <= std_logic_vector(SP(15 downto 8));
+				when "1010" =>
+					BusA <= "00000000";
+				when others =>
+					BusA <= "--------";
+				end case;
+				if XYbit_undoc='1' then
+					BusA <= DI_Reg;
+					BusB <= DI_Reg;
+				end if;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+	process (RESET_n,CLK_n)
+	begin
+		if RESET_n = '0' then
+			RFSH_n <= '1';
+		elsif rising_edge(CLK_n) then
+			if DIRSet = '0' and CEN = '1' then
+				if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+					RFSH_n <= '0';
+				else
+					RFSH_n <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+	process (RESET_n, CLK_n)
+		variable OldNMI_n : std_logic;
+	begin
+		if RESET_n = '0' then
+			MCycle <= "001";
+			TState <= "000";
+			Pre_XY_F_M <= "000";
+			Halt_FF <= '0';
+			BusAck <= '0';
+			NMICycle <= '0';
+			IntCycle <= '0';
+			IntE_FF1 <= '0';
+			IntE_FF2 <= '0';
+			No_BTR <= '0';
+			Auto_Wait_t1 <= '0';
+			Auto_Wait_t2 <= '0';
+			M1_n <= '1';
+			BusReq_s <= '0';
+			NMI_s <= '0';
+		elsif rising_edge(CLK_n) then
+		
+			if DIRSet = '1' then
+				IntE_FF2 <= DIR(211);
+				IntE_FF1 <= DIR(210);
+			else
+				if NMI_n = '0' and OldNMI_n = '1' then
+					NMI_s <= '1';
+				end if;
+				OldNMI_n := NMI_n;
+				
+				if CEN = '1' then
+					BusReq_s <= not BUSRQ_n;
+					Auto_Wait_t2 <= Auto_Wait_t1;
+					if T_Res = '1' then
+						Auto_Wait_t1 <= '0';
+						Auto_Wait_t2 <= '0';
+					else
+						Auto_Wait_t1 <= Auto_Wait or IORQ_i;
+					end if;
+					No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+							(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+							(I_BTR and (not IR(4) or F(Flag_Z)));
+					if TState = 2 then
+						if SetEI = '1' then
+							IntE_FF1 <= '1';
+							IntE_FF2 <= '1';
+						end if;
+						if I_RETN = '1' then
+							IntE_FF1 <= IntE_FF2;
+						end if;
+					end if;
+					if TState = 3 then
+						if SetDI = '1' then
+							IntE_FF1 <= '0';
+							IntE_FF2 <= '0';
+						end if;
+					end if;
+					if IntCycle = '1' or NMICycle = '1' then
+						Halt_FF <= '0';
+					end if;
+					if MCycle = "001" and TState = 2 and Wait_n = '1' then
+						M1_n <= '1';
+					end if;
+					if BusReq_s = '1' and BusAck = '1' then
+					else
+						BusAck <= '0';
+						if TState = 2 and Wait_n = '0' then
+						elsif T_Res = '1' then
+							if Halt = '1' then
+								Halt_FF <= '1';
+							end if;
+							if BusReq_s = '1' then
+								BusAck <= '1';
+							else
+								TState <= "001";
+								if NextIs_XY_Fetch = '1' then
+									MCycle <= "110";
+									Pre_XY_F_M <= MCycle;
+									if IR = "00110110" and Mode = 0 then
+										Pre_XY_F_M <= "010";
+									end if;
+								elsif (MCycle = "111") or (MCycle = "110" and Mode = 1 and ISet /= "01") then
+									MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+								elsif (MCycle = MCycles) or No_BTR = '1' or (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+									M1_n <= '0';
+									MCycle <= "001";
+									IntCycle <= '0';
+									NMICycle <= '0';
+									if NMI_s = '1' and Prefix = "00" then
+										NMI_s    <= '0';
+										NMICycle <= '1';
+										IntE_FF1 <= '0';
+									elsif IntE_FF1 = '1' and INT_n='0' and Prefix = "00" and SetEI = '0' then
+										IntCycle <= '1';
+										IntE_FF1 <= '0';
+										IntE_FF2 <= '0';
+									end if;
+								else
+									MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+								end if;
+							end if;
+						else
+							if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
+								(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
+								TState <= TState + 1;
+							end if;
+						end if;
+					end if;
+					if TState = 0 then
+						M1_n <= '0';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	Auto_Wait <= '1' when IntCycle = '1' and MCycle = "001" else '0';
+end;
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_ALU.vhd b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_ALU.vhd
new file mode 100644
index 00000000..a9438aed
--- /dev/null
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_ALU.vhd	
@@ -0,0 +1,376 @@
+--------------------------------------------------------------------------------
+-- ****
+-- T80(c) core. Attempt to finish all undocumented features and provide
+--              accurate timings.
+-- Version 350.
+-- Copyright (c) 2018 Sorgelig
+--  Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
+--  (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
+--      correct implementation is still unclear.
+--
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--      0240 : Added GB operations
+--      0242 : Cleanup
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16         : in  std_logic;
+		Z16             : in  std_logic;
+		WZ              : in  std_logic_vector(15 downto 0);
+		XY_State		    : in  std_logic_vector(1 downto 0);
+		ALU_Op          : in  std_logic_vector(3 downto 0);
+		IR              : in  std_logic_vector(5 downto 0);
+		ISet            : in  std_logic_vector(1 downto 0);
+		BusA            : in  std_logic_vector(7 downto 0);
+		BusB            : in  std_logic_vector(7 downto 0);
+		F_In            : in  std_logic_vector(7 downto 0);
+		Q               : out std_logic_vector(7 downto 0);
+		F_Out           : out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A        : std_logic_vector;
+					 B        : std_logic_vector;
+					 Sub      : std_logic;
+					 Carry_In : std_logic;
+			  signal Res      : out std_logic_vector;
+			  signal Carry    : out std_logic) is
+
+		variable B_i          : unsigned(A'length - 1 downto 0);
+		variable Res_i        : unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+
+	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
+	process (Carry_v, Carry7_v, Q_v)
+	begin
+		if(Mode=2) then
+			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
+					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
+			OverFlow_v <= Carry_v xor Carry7_v;
+		end if;
+	end process;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			if IR(2 downto 0) = "110" or XY_State /= "00" then
+				F_Out(Flag_X) <= WZ(11);
+				F_Out(Flag_Y) <= WZ(13);
+			else
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_MCode.vhd b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_MCode.vhd
new file mode 100644
index 00000000..f5312bd6
--- /dev/null
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_MCode.vhd	
@@ -0,0 +1,2035 @@
+--------------------------------------------------------------------------------
+-- ****
+-- T80(c) core. Attempt to finish all undocumented features and provide
+--              accurate timings.
+-- Version 350.
+-- Copyright (c) 2018 Sorgelig
+--  Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
+--  (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
+--      correct implementation is still unclear.
+--
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--      0211 : Fixed IM 1
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--      0235 : Added IM 2 fix by Mike Johnson
+--      0238 : Added NoRead signal
+--      0238b: Fixed instruction timing for POP and DJNZ
+--      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+--      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
+--      0242 : Fixed I/O instruction timing, cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_MCode is
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+      IR          : in std_logic_vector(7 downto 0);
+      ISet        : in std_logic_vector(1 downto 0);
+      MCycle      : in std_logic_vector(2 downto 0);
+      F           : in std_logic_vector(7 downto 0);
+      NMICycle    : in std_logic;
+      IntCycle    : in std_logic;
+      XY_State    : in std_logic_vector(1 downto 0);
+      MCycles     : out std_logic_vector(2 downto 0);
+      TStates     : out std_logic_vector(2 downto 0);
+      Prefix      : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
+      Inc_PC      : out std_logic;
+      Inc_WZ      : out std_logic;
+      IncDec_16   : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+      Read_To_Reg : out std_logic;
+      Read_To_Acc : out std_logic;
+      Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+      Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+      ALU_Op      : out std_logic_vector(3 downto 0);
+         -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+      Save_ALU    : out std_logic;
+      PreserveC   : out std_logic;
+      Arith16     : out std_logic;
+      Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+      IORQ        : out std_logic;
+      Jump        : out std_logic;
+      JumpE       : out std_logic;
+      JumpXY      : out std_logic;
+      Call        : out std_logic;
+      RstP        : out std_logic;
+      LDZ         : out std_logic;
+      LDW         : out std_logic;
+      LDSPHL      : out std_logic;
+      Special_LD  : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+      ExchangeDH  : out std_logic;
+      ExchangeRp  : out std_logic;
+      ExchangeAF  : out std_logic;
+      ExchangeRS  : out std_logic;
+      I_DJNZ      : out std_logic;
+      I_CPL       : out std_logic;
+      I_CCF       : out std_logic;
+      I_SCF       : out std_logic;
+      I_RETN      : out std_logic;
+      I_BT        : out std_logic;
+      I_BC        : out std_logic;
+      I_BTR       : out std_logic;
+      I_RLD       : out std_logic;
+      I_RRD       : out std_logic;
+      I_INRC      : out std_logic;
+      SetWZ       : out std_logic_vector(1 downto 0);
+      SetDI       : out std_logic;
+      SetEI       : out std_logic;
+      IMode       : out std_logic_vector(1 downto 0);
+      Halt        : out std_logic;
+      NoRead      : out std_logic;
+      Write       : out std_logic;
+      XYbit_undoc : out std_logic
+   );
+end T80_MCode;
+
+architecture rtl of T80_MCode is
+
+	constant aNone : std_logic_vector(2 downto 0) := "111";
+	constant aBC   : std_logic_vector(2 downto 0) := "000";
+	constant aDE   : std_logic_vector(2 downto 0) := "001";
+	constant aXY   : std_logic_vector(2 downto 0) := "010";
+	constant aIOA  : std_logic_vector(2 downto 0) := "100";
+	constant aSP   : std_logic_vector(2 downto 0) := "101";
+	constant aZI   : std_logic_vector(2 downto 0) := "110";
+
+	function is_cc_true(
+		F : std_logic_vector(7 downto 0);
+		cc : bit_vector(2 downto 0)
+		) return boolean is
+	begin
+		if Mode = 3 then
+			case cc is
+			when "000" => return F(Flag_S) = '0'; -- NZ
+			when "001" => return F(Flag_S) = '1'; -- Z
+			when "010" => return F(Flag_H) = '0'; -- NC
+			when "011" => return F(Flag_H) = '1'; -- C
+			when "100" => return false;
+			when "101" => return false;
+			when "110" => return false;
+			when "111" => return false;
+			end case;
+		else
+			case cc is
+			when "000" => return F(Flag_Z) = '0'; -- NZ
+			when "001" => return F(Flag_Z) = '1'; -- Z
+			when "010" => return F(Flag_C) = '0'; -- NC
+			when "011" => return F(Flag_C) = '1'; -- C
+			when "100" => return F(Flag_P) = '0'; -- PO
+			when "101" => return F(Flag_P) = '1'; -- PE
+			when "110" => return F(Flag_S) = '0'; -- P
+			when "111" => return F(Flag_S) = '1'; -- M
+			end case;
+		end if;
+	end;
+
+begin
+
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
+		variable DDD   : std_logic_vector(2 downto 0);
+		variable SSS   : std_logic_vector(2 downto 0);
+		variable DPair : std_logic_vector(1 downto 0);
+		variable IRB   : bit_vector(7 downto 0);
+	begin
+		DDD := IR(5 downto 3);
+		SSS := IR(2 downto 0);
+		DPair := IR(5 downto 4);
+		IRB := to_bitvector(IR);
+
+		MCycles <= "001";
+		if MCycle = "001" then
+			TStates <= "100";
+		else
+			TStates <= "011";
+		end if;
+		Prefix <= "00";
+		Inc_PC <= '0';
+		Inc_WZ <= '0';
+		IncDec_16 <= "0000";
+		Read_To_Acc <= '0';
+		Read_To_Reg <= '0';
+		Set_BusB_To <= "0000";
+		Set_BusA_To <= "0000";
+		ALU_Op <= "0" & IR(5 downto 3);
+		Save_ALU <= '0';
+		PreserveC <= '0';
+		Arith16 <= '0';
+		IORQ <= '0';
+		Set_Addr_To <= aNone;
+		Jump <= '0';
+		JumpE <= '0';
+		JumpXY <= '0';
+		Call <= '0';
+		RstP <= '0';
+		LDZ <= '0';
+		LDW <= '0';
+		LDSPHL <= '0';
+		Special_LD <= "000";
+		ExchangeDH <= '0';
+		ExchangeRp <= '0';
+		ExchangeAF <= '0';
+		ExchangeRS <= '0';
+		I_DJNZ <= '0';
+		I_CPL <= '0';
+		I_CCF <= '0';
+		I_SCF <= '0';
+		I_RETN <= '0';
+		I_BT <= '0';
+		I_BC <= '0';
+		I_BTR <= '0';
+		I_RLD <= '0';
+		I_RRD <= '0';
+		I_INRC <= '0';
+		SetDI <= '0';
+		SetEI <= '0';
+		IMode <= "11";
+		Halt <= '0';
+		NoRead <= '0';
+		Write <= '0';
+		XYbit_undoc <= '0';
+		SetWZ <= "00";
+
+		case ISet is
+		when "00" =>
+
+------------------------------------------------------------------------------
+--
+--	Unprefixed instructions
+--
+------------------------------------------------------------------------------
+
+		case IRB is
+-- 8 BIT LOAD GROUP
+		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+			-- LD r,r'
+			Set_BusB_To(2 downto 0) <= SSS;
+			ExchangeRp <= '1';
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
+			-- LD r,n
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
+			-- LD r,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Set_BusA_To(2 downto 0) <= DDD;
+				Read_To_Reg <= '1';
+			when others => null;
+			end case;
+		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
+			-- LD (HL),r
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110110" =>
+			-- LD (HL),n
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Set_Addr_To <= aXY;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00001010" =>
+			-- LD A,(BC)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00011010" =>
+			-- LD A,(DE)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+			when 2 =>
+				Read_To_Acc <= '1';
+			when others => null;
+			end case;
+		when "00111010" =>
+			if Mode = 3 then
+				-- LDD A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD A,(nn)
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+				when 4 =>
+					Read_To_Acc <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00000010" =>
+			-- LD (BC),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aBC;
+				Set_BusB_To <= "0111";
+				SetWZ <= "10";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00010010" =>
+			-- LD (DE),A
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aDE;
+				Set_BusB_To <= "0111";
+				SetWZ <= "10";
+			when 2 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00110010" =>
+			if Mode = 3 then
+				-- LDD (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),A
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					SetWZ <= "10";
+					Inc_PC <= '1';
+					Set_BusB_To <= "0111";
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 16 BIT LOAD GROUP
+		when "00000001"|"00010001"|"00100001"|"00110001" =>
+			-- LD dd,nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1000";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1001";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+		when "00101010" =>
+			if Mode = 3 then
+				-- LDI A,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Acc <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD HL,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Set_BusA_To(2 downto 0) <= "101"; -- L
+					Read_To_Reg <= '1';
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Set_BusA_To(2 downto 0) <= "100"; -- H
+					Read_To_Reg <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "00100010" =>
+			if Mode = 3 then
+				-- LDI (HL),A
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "0111";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "0110";
+				when others => null;
+				end case;
+			else
+				-- LD (nn),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "0101"; -- L
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "0100"; -- H
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11111001" =>
+			-- LD SP,HL
+			TStates <= "110";
+			LDSPHL <= '1';
+		when "11000101"|"11010101"|"11100101"|"11110101" =>
+			-- PUSH qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_TO <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "0111";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '0';
+					Set_BusB_To(3) <= '0';
+				end if;
+			when 2 =>
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				if DPAIR = "11" then
+					Set_BusB_To <= "1011";
+				else
+					Set_BusB_To(2 downto 1) <= DPAIR;
+					Set_BusB_To(0) <= '1';
+					Set_BusB_To(3) <= '0';
+				end if;
+				Write <= '1';
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "11000001"|"11010001"|"11100001"|"11110001" =>
+			-- POP qq
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "1011";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '1';
+				end if;
+			when 3 =>
+				IncDec_16 <= "0111";
+				Read_To_Reg <= '1';
+				if DPAIR = "11" then
+					Set_BusA_To(3 downto 0) <= "0111";
+				else
+					Set_BusA_To(2 downto 1) <= DPAIR;
+					Set_BusA_To(0) <= '0';
+				end if;
+			when others => null;
+			end case;
+
+-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
+		when "11101011" =>
+			if Mode /= 3 then
+				-- EX DE,HL
+				ExchangeDH <= '1';
+			end if;
+		when "00001000" =>
+			if Mode = 3 then
+				-- LD (nn),SP
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					Set_BusB_To <= "1000";
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					Set_BusB_To <= "1001";
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EX AF,AF'
+				ExchangeAF <= '1';
+			end if;
+		when "11011001" =>
+			if Mode = 3 then
+				-- RETI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					I_RETN <= '1';
+					SetEI <= '1';
+				when others => null;
+				end case;
+			elsif Mode < 2 then
+				-- EXX
+				ExchangeRS <= '1';
+			end if;
+		when "11100011" =>
+			if Mode /= 3 then
+				-- EX (SP),HL
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aSP;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0101";
+					Set_BusB_To <= "0101";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					Set_BusA_To <= "0100";
+					Set_BusB_To <= "0100";
+					Set_Addr_To <= aSP;
+					LDW <= '1';
+				when 5 =>
+					IncDec_16 <= "1111";
+					TStates <= "101";
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
+-- 8 BIT ARITHMETIC AND LOGICAL GROUP
+		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+			-- ADD A,r
+			-- ADC A,r
+			-- SUB A,r
+			-- SBC A,r
+			-- AND A,r
+			-- OR A,r
+			-- XOR A,r
+			-- CP A,r
+			Set_BusB_To(2 downto 0) <= SSS;
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+			-- ADD A,(HL)
+			-- ADC A,(HL)
+			-- SUB A,(HL)
+			-- SBC A,(HL)
+			-- AND A,(HL)
+			-- OR A,(HL)
+			-- XOR A,(HL)
+			-- CP A,(HL)
+			MCycles <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			when others => null;
+			end case;
+		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+			-- ADD A,n
+			-- ADC A,n
+			-- SUB A,n
+			-- SBC A,n
+			-- AND A,n
+			-- OR A,n
+			-- XOR A,n
+			-- CP A,n
+			MCycles <= "010";
+			if MCycle = "010" then
+				Inc_PC <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusA_To(2 downto 0) <= "111";
+			end if;
+		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
+			-- INC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0000";
+		when "00110100" =>
+			-- INC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				ALU_Op <= "0000";
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
+			-- DEC r
+			Set_BusB_To <= "1010";
+			Set_BusA_To(2 downto 0) <= DDD;
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+			PreserveC <= '1';
+			ALU_Op <= "0010";
+		when "00110101" =>
+			-- DEC (HL)
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				Set_Addr_To <= aXY;
+			when 2 =>
+				TStates <= "100";
+				Set_Addr_To <= aXY;
+				ALU_Op <= "0010";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				PreserveC <= '1';
+				Set_BusB_To <= "1010";
+				Set_BusA_To(2 downto 0) <= DDD;
+			when 3 =>
+				Write <= '1';
+			when others => null;
+			end case;
+
+-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
+		when "00100111" =>
+			-- DAA
+			Set_BusA_To(2 downto 0) <= "111";
+			Read_To_Reg <= '1';
+			ALU_Op <= "1100";
+			Save_ALU <= '1';
+		when "00101111" =>
+			-- CPL
+			I_CPL <= '1';
+		when "00111111" =>
+			-- CCF
+			I_CCF <= '1';
+		when "00110111" =>
+			-- SCF
+			I_SCF <= '1';
+		when "00000000" =>
+			if NMICycle = '1' then
+				-- NMI
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			elsif IntCycle = '1' then
+				-- INT (IM 2)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					LDZ <= '1';
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1101";
+				when 2 =>
+					--TStates <= "100";
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 3 =>
+					--TStates <= "100";
+					Write <= '1';
+				when 4 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 5 =>
+					Jump <= '1';
+				when others => null;
+				end case;
+			else
+				-- NOP
+			end if;
+		when "01110110" =>
+			-- HALT
+			Halt <= '1';
+		when "11110011" =>
+			-- DI
+			SetDI <= '1';
+		when "11111011" =>
+			-- EI
+			SetEI <= '1';
+
+-- 16 BIT ARITHMETIC GROUP
+		when "00001001"|"00011001"|"00101001"|"00111001" =>
+			-- ADD HL,ss
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				NoRead <= '1';
+				ALU_Op <= "0000";
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				Set_BusA_To(2 downto 0) <= "101";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					Set_BusB_To(0) <= '1';
+				when others =>
+					Set_BusB_To <= "1000";
+				end case;
+				TStates <= "100";
+				Arith16 <= '1';
+				SetWZ <= "11";
+			when 3 =>
+				NoRead <= '1';
+				Read_To_Reg <= '1';
+				Save_ALU <= '1';
+				ALU_Op <= "0001";
+				Set_BusA_To(2 downto 0) <= "100";
+				case to_integer(unsigned(IR(5 downto 4))) is
+				when 0|1|2 =>
+					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+				when others =>
+					Set_BusB_To <= "1001";
+				end case;
+				Arith16 <= '1';
+			when others =>
+			end case;
+		when "00000011"|"00010011"|"00100011"|"00110011" =>
+			-- INC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "01";
+			IncDec_16(1 downto 0) <= DPair;
+		when "00001011"|"00011011"|"00101011"|"00111011" =>
+			-- DEC ss
+			TStates <= "110";
+			IncDec_16(3 downto 2) <= "11";
+			IncDec_16(1 downto 0) <= DPair;
+
+-- ROTATE AND SHIFT GROUP
+		when "00000111"
+			-- RLCA
+			|"00010111"
+			-- RLA
+			|"00001111"
+			-- RRCA
+			|"00011111" =>
+			-- RRA
+			Set_BusA_To(2 downto 0) <= "111";
+			ALU_Op <= "1000";
+			Read_To_Reg <= '1';
+			Save_ALU <= '1';
+
+-- JUMP GROUP
+		when "11000011" =>
+			-- JP nn
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				Inc_PC <= '1';
+				Jump <= '1';
+				LDW <= '1';
+			when others => null;
+			end case;
+		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+C),A
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+						Set_BusB_To	<= "0111";
+					when 2 =>
+						Write <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "01" =>
+					-- LD (nn),A
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						Set_BusB_To <= "0111";
+					when 4 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "10" =>
+					-- LD A,($FF00+C)
+					MCycles <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Set_Addr_To <= aBC;
+					when 2 =>
+						Read_To_Acc <= '1';
+						IORQ <= '1';
+					when others =>
+					end case;
+				when "11" =>
+					-- LD A,(nn)
+					MCycles <= "100";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+					when 4 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- JP cc,nn
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					LDW <= '1';
+					Inc_PC <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Jump <= '1';
+					end if;
+				when others => null;
+				end case;
+			end if;
+		when "00011000" =>
+			if Mode /= 2 then
+				-- JR e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00111000" =>
+			if Mode /= 2 then
+				-- JR C,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00110000" =>
+			if Mode /= 2 then
+				-- JR NC,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_C) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00101000" =>
+			if Mode /= 2 then
+				-- JR Z,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '0' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "00100000" =>
+			if Mode /= 2 then
+				-- JR NZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					if F(Flag_Z) = '1' then
+						MCycles <= "010";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+		when "11101001" =>
+			-- JP (HL)
+			JumpXY <= '1';
+		when "00010000" =>
+			if Mode = 3 then
+				I_DJNZ <= '1';
+			elsif Mode < 2 then
+				-- DJNZ,e
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					I_DJNZ <= '1';
+					Set_BusB_To <= "1010";
+					Set_BusA_To(2 downto 0) <= "000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					I_DJNZ <= '1';
+					Inc_PC <= '1';
+				when 3 =>
+					NoRead <= '1';
+					JumpE <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end if;
+
+-- CALL AND RETURN GROUP
+		when "11001101" =>
+			-- CALL nn
+			MCycles <= "101";
+			case to_integer(unsigned(MCycle)) is
+			when 2 =>
+				Inc_PC <= '1';
+				LDZ <= '1';
+			when 3 =>
+				IncDec_16 <= "1111";
+				Inc_PC <= '1';
+				TStates <= "100";
+				Set_Addr_To <= aSP;
+				LDW <= '1';
+				Set_BusB_To <= "1101";
+			when 4 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 5 =>
+				Write <= '1';
+				Call <= '1';
+			when others => null;
+			end case;
+		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
+			if IR(5) = '0' or Mode /= 3 then
+				-- CALL cc,nn
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Inc_PC <= '1';
+					LDW <= '1';
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						IncDec_16 <= "1111";
+						Set_Addr_TO <= aSP;
+						TStates <= "100";
+						Set_BusB_To <= "1101";
+					else
+						MCycles <= "011";
+					end if;
+				when 4 =>
+					Write <= '1';
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					Set_BusB_To <= "1100";
+				when 5 =>
+					Write <= '1';
+					Call <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11001001" =>
+			-- RET
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				--TStates <= "101";
+				Set_Addr_TO <= aSP;
+			when 2 =>
+				IncDec_16 <= "0111";
+				Set_Addr_To <= aSP;
+				LDZ <= '1';
+			when 3 =>
+				Jump <= '1';
+				IncDec_16 <= "0111";
+			when others => null;
+			end case;
+		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
+			if IR(5) = '1' and Mode = 3 then
+				case IRB(4 downto 3) is
+				when "00" =>
+					-- LD ($FF00+nn),A
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+						Set_BusB_To	<= "0111";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				when "01" =>
+					-- ADD SP,n
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						ALU_Op <= "0000";
+						Inc_PC <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_BusA_To <= "1000";
+						Set_BusB_To <= "0110";
+					when 3 =>
+						NoRead <= '1';
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						ALU_Op <= "0001";
+						Set_BusA_To <= "1001";
+						Set_BusB_To <= "1110";	-- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					when others =>
+					end case;
+				when "10" =>
+					-- LD A,($FF00+nn)
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						Set_Addr_To <= aIOA;
+					when 3 =>
+						Read_To_Acc <= '1';
+					when others => null;
+					end case;
+				when "11" =>
+					-- LD HL,SP+n	-- Not correct !!!!!!!!!!!!!!!!!!!
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Inc_PC <= '1';
+						LDZ <= '1';
+					when 3 =>
+						Set_Addr_To <= aZI;
+						Inc_PC <= '1';
+						LDW <= '1';
+					when 4 =>
+						Set_BusA_To(2 downto 0) <= "101"; -- L
+						Read_To_Reg <= '1';
+						Inc_WZ <= '1';
+						Set_Addr_To <= aZI;
+					when 5 =>
+						Set_BusA_To(2 downto 0) <= "100"; -- H
+						Read_To_Reg <= '1';
+					when others => null;
+					end case;
+				end case;
+			else
+				-- RET cc
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+						Set_Addr_TO <= aSP;
+					else
+						MCycles <= "001";
+					end if;
+					TStates <= "101";
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
+			-- RST p
+			MCycles <= "011";
+			case to_integer(unsigned(MCycle)) is
+			when 1 =>
+				TStates <= "101";
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1101";
+			when 2 =>
+				Write <= '1';
+				IncDec_16 <= "1111";
+				Set_Addr_To <= aSP;
+				Set_BusB_To <= "1100";
+			when 3 =>
+				Write <= '1';
+				RstP <= '1';
+			when others => null;
+			end case;
+
+-- INPUT AND OUTPUT GROUP
+		when "11011011" =>
+			if Mode /= 3 then
+				-- IN A,(n)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+				when 3 =>
+					Read_To_Acc <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+		when "11010011" =>
+			if Mode /= 3 then
+				-- OUT (n),A
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					Set_Addr_To <= aIOA;
+					Set_BusB_To	<= "0111";
+				when 3 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others => null;
+				end case;
+			end if;
+
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+-- MULTIBYTE INSTRUCTIONS
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+		when "11001011" =>
+			if Mode /= 2 then
+				Prefix <= "01";
+			end if;
+
+		when "11101101" =>
+			if Mode < 2 then
+				Prefix <= "10";
+			end if;
+
+		when "11011101"|"11111101" =>
+			if Mode < 2 then
+				Prefix <= "11";
+			end if;
+
+		end case;
+
+		when "01" =>
+
+------------------------------------------------------------------------------
+--
+--	CB prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
+			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
+				-- RLC r
+				-- RL r
+				-- RRC r
+				-- RR r
+				-- SLA r
+				-- SRA r
+				-- SRL r
+				-- SLL r (Undocumented) / SWAP r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  ALU_Op <= "1000";
+					  Read_To_Reg <= '1';
+					  Save_ALU <= '1';
+					end if;
+				else
+				-- R/S (IX+d),Reg, undocumented
+					MCycles <= "011";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1000";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_Addr_To <= aXY;
+						TStates <= "100";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				end if;
+
+			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
+				-- RLC (HL)
+				-- RL (HL)
+				-- RRC (HL)
+				-- RR (HL)
+				-- SRA (HL)
+				-- SRL (HL)
+				-- SLA (HL)
+				-- SLL (HL) (Undocumented) / SWAP (HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
+				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
+				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
+				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
+				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
+				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
+				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
+				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
+				-- BIT b,r
+				if XY_State="00" then
+					if MCycle = "001" then
+					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
+					  ALU_Op <= "1001";
+					end if;
+				else
+				-- BIT b,(IX+d), undocumented
+					MCycles <= "010";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1001";
+						TStates <= "100";
+					when others => null;
+					end case;
+				end if;
+
+			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
+				-- BIT b,(HL)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1001";
+					TStates <= "100";
+				when others => null;
+				end case;
+			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
+				-- SET b,r
+				if XY_State="00" then
+					if MCycle = "001" then
+						ALU_Op <= "1010";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+					end if;
+				else
+				-- SET b,(IX+d),Reg, undocumented
+					MCycles <= "011";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1010";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_Addr_To <= aXY;
+						TStates <= "100";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				end if;
+
+			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
+				-- SET b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1010";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
+				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
+				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
+				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
+				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
+				-- RES b,r
+				if XY_State="00" then
+					if MCycle = "001" then
+						ALU_Op <= "1011";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+					end if;
+				else
+				-- RES b,(IX+d),Reg, undocumented
+					MCycles <= "011";
+					XYbit_undoc <= '1';
+					case to_integer(unsigned(MCycle)) is
+					when 1 | 7=>
+						Set_Addr_To <= aXY;
+					when 2 =>
+						ALU_Op <= "1011";
+						Read_To_Reg <= '1';
+						Save_ALU <= '1';
+						Set_Addr_To <= aXY;
+						TStates <= "100";
+					when 3 =>
+						Write <= '1';
+					when others => null;
+					end case;
+				end if;
+
+			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
+				-- RES b,(HL)
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 | 7 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					ALU_Op <= "1011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end case;
+
+		when others =>
+
+------------------------------------------------------------------------------
+--
+--	ED prefixed instructions
+--
+------------------------------------------------------------------------------
+
+			case IRB is
+			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
+				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
+				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
+				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
+				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
+				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
+				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
+				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
+
+
+				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
+				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
+				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
+				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
+				|                                            "10100100"|"10100101"|"10100110"|"10100111"
+				|                                            "10101100"|"10101101"|"10101110"|"10101111"
+				|                                            "10110100"|"10110101"|"10110110"|"10110111"
+				|                                            "10111100"|"10111101"|"10111110"|"10111111"
+				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
+				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
+				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
+				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
+				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
+				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
+				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
+				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
+				null; -- NOP, undocumented
+			when "01111110"|"01111111" =>
+				-- NOP, undocumented
+				null;
+-- 8 BIT LOAD GROUP
+			when "01010111" =>
+				-- LD A,I
+				Special_LD <= "100";
+				TStates <= "101";
+			when "01011111" =>
+				-- LD A,R
+				Special_LD <= "101";
+				TStates <= "101";
+			when "01000111" =>
+				-- LD I,A
+				Special_LD <= "110";
+				TStates <= "101";
+			when "01001111" =>
+				-- LD R,A
+				Special_LD <= "111";
+				TStates <= "101";
+-- 16 BIT LOAD GROUP
+			when "01001011"|"01011011"|"01101011"|"01111011" =>
+				-- LD dd,(nn)
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+				when 4 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1000";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '1';
+					end if;
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+				when 5 =>
+					Read_To_Reg <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusA_To <= "1001";
+					else
+						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusA_To(0) <= '0';
+					end if;
+				when others => null;
+				end case;
+			when "01000011"|"01010011"|"01100011"|"01110011" =>
+				-- LD (nn),dd
+				MCycles <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Inc_PC <= '1';
+					LDZ <= '1';
+				when 3 =>
+					Set_Addr_To <= aZI;
+					Inc_PC <= '1';
+					LDW <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1000";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 4 =>
+					Inc_WZ <= '1';
+					Set_Addr_To <= aZI;
+					Write <= '1';
+					if IR(5 downto 4) = "11" then
+						Set_BusB_To <= "1001";
+					else
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 5 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			when "10100000" | "10101000" | "10110000" | "10111000" =>
+				-- LDI, LDD, LDIR, LDDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0000";
+					Set_Addr_To <= aDE;
+					if IR(3) = '0' then
+						IncDec_16 <= "0110"; -- IX
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					I_BT <= '1';
+					TStates <= "101";
+					Write <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0101"; -- DE
+					else
+						IncDec_16 <= "1101";
+					end if;
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100001" | "10101001" | "10110001" | "10111001" =>
+				-- CPI, CPD, CPIR, CPDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+					IncDec_16 <= "1100"; -- BC
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "0111";
+					Save_ALU <= '1';
+					PreserveC <= '1';
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+				when 3 =>
+					NoRead <= '1';
+					I_BC <= '1';
+					TStates <= "101";
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
+				-- NEG
+				Alu_OP <= "0010";
+				Set_BusB_To <= "0111";
+				Set_BusA_To <= "1010";
+				Read_To_Acc <= '1';
+				Save_ALU <= '1';
+			when "01000110"|"01001110"|"01100110"|"01101110" =>
+				-- IM 0
+				IMode <= "00";
+			when "01010110"|"01110110" =>
+				-- IM 1
+				IMode <= "01";
+			when "01011110"|"01110111" =>
+				-- IM 2
+				IMode <= "10";
+-- 16 bit arithmetic
+			when "01001010"|"01011010"|"01101010"|"01111010" =>
+				-- ADC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0001";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+					SetWZ <= "11";
+				when 3 =>
+					NoRead <= '1';
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0001";
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '0';
+					when others =>
+						Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01000010"|"01010010"|"01100010"|"01110010" =>
+				-- SBC HL,ss
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "101";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+						Set_BusB_To(0) <= '1';
+					when others =>
+						Set_BusB_To <= "1000";
+					end case;
+					TStates <= "100";
+					SetWZ <= "11";
+				when 3 =>
+					NoRead <= '1';
+					ALU_Op <= "0011";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					Set_BusA_To(2 downto 0) <= "100";
+					case to_integer(unsigned(IR(5 downto 4))) is
+					when 0|1|2 =>
+						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
+					when others =>
+							Set_BusB_To <= "1001";
+					end case;
+				when others =>
+				end case;
+			when "01101111" =>
+				-- RLD -- Read in M2, not M3! fixed by Sorgelig
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1101";
+					Save_ALU <= '1';
+				when 3 =>
+					TStates <= "100";
+					I_RLD <= '1';
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 4 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01100111" =>
+				-- RRD -- Read in M2, not M3! fixed by Sorgelig
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aXY;
+				when 2 =>
+					Read_To_Reg <= '1';
+					Set_BusB_To(2 downto 0) <= "110";
+					Set_BusA_To(2 downto 0) <= "111";
+					ALU_Op <= "1110";
+					Save_ALU <= '1';
+				when 3 =>
+					TStates <= "100";
+					I_RRD <= '1';
+					NoRead <= '1';
+					Set_Addr_To <= aXY;
+				when 4 =>
+					Write <= '1';
+				when others =>
+				end case;
+			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
+				-- RETI/RETN
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+					LDW <= '1';
+					I_RETN <= '1';
+				when others => null;
+				end case;
+			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
+				-- IN r,(C)
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					SetWZ <= "01";
+				when 2 =>
+					IORQ <= '1';
+					if IR(5 downto 3) /= "110" then
+						Read_To_Reg <= '1';
+						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
+					end if;
+					I_INRC <= '1';
+				when others =>
+				end case;
+			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
+				-- OUT (C),r
+				-- OUT (C),0
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= aBC;
+					SetWZ <= "01";
+					Set_BusB_To(2 downto 0)	<= IR(5 downto 3);
+					if IR(5 downto 3) = "110" then
+						Set_BusB_To(3) <= '1';
+					end if;
+				when 2 =>
+					Write <= '1';
+					IORQ <= '1';
+				when others =>
+				end case;
+			when "10100010" | "10101010" | "10110010" | "10111010" =>
+				-- INI, IND, INIR, INDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aBC;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+					SetWZ <= "11";
+					IncDec_16(3) <= IR(3);
+				when 2 =>
+					IORQ <= '1';
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aXY;
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			when "10100011" | "10101011" | "10110011" | "10111011" =>
+				-- OUTI, OUTD, OTIR, OTDR
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					Set_Addr_To <= aXY;
+					Set_BusB_To <= "1010";
+					Set_BusA_To <= "0000";
+					Read_To_Reg <= '1';
+					Save_ALU <= '1';
+					ALU_Op <= "0010";
+				when 2 =>
+					Set_BusB_To <= "0110";
+					Set_Addr_To <= aBC;
+					SetWZ <= "11";
+					IncDec_16(3) <= IR(3);
+				when 3 =>
+					if IR(3) = '0' then
+						IncDec_16 <= "0110";
+					else
+						IncDec_16 <= "1110";
+					end if;
+					IORQ <= '1';
+					Write <= '1';
+					I_BTR <= '1';
+				when 4 =>
+					NoRead <= '1';
+					TStates <= "101";
+				when others => null;
+				end case;
+			end case;
+
+		end case;
+
+		if Mode = 1 then
+			if MCycle = "001" then
+--				TStates <= "100";
+			else
+				TStates <= "011";
+			end if;
+		end if;
+
+		if Mode = 3 then
+			if MCycle = "001" then
+--				TStates <= "100";
+			else
+				TStates <= "100";
+			end if;
+		end if;
+
+		if Mode < 2 then
+			if MCycle = "110" then
+				Inc_PC <= '1';
+				if Mode = 1 then
+					Set_Addr_To <= aXY;
+					TStates <= "100";
+					Set_BusB_To(2 downto 0) <= SSS;
+					Set_BusB_To(3) <= '0';
+				end if;
+				if IRB = "00110110" or IRB = "11001011" then
+					Set_Addr_To <= aNone;
+				end if;
+			end if;
+			if MCycle = "111" then
+				if Mode = 0 then
+					TStates <= "101";
+				end if;
+				if ISet /= "01" then
+					Set_Addr_To <= aXY;
+				end if;
+				Set_BusB_To(2 downto 0) <= SSS;
+				Set_BusB_To(3) <= '0';
+				if IRB = "00110110" or ISet = "01" then
+					-- LD (HL),n
+					Inc_PC <= '1';
+				else
+					NoRead <= '1';
+				end if;
+			end if;
+		end if;
+
+	end process;
+
+end;
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_Reg.vhd b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_Reg.vhd
new file mode 100644
index 00000000..ea526225
--- /dev/null
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80_Reg.vhd	
@@ -0,0 +1,152 @@
+--------------------------------------------------------------------------------
+-- ****
+-- T80(c) core. Attempt to finish all undocumented features and provide
+--              accurate timings.
+-- Version 350.
+-- Copyright (c) 2018 Sorgelig
+--  Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
+--  (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
+--      correct implementation is still unclear.
+--
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0242 : Initial release
+--
+--	0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk     : in  std_logic;
+		CEN     : in  std_logic;
+		WEH     : in  std_logic;
+		WEL     : in  std_logic;
+		AddrA   : in  std_logic_vector(2 downto 0);
+		AddrB   : in  std_logic_vector(2 downto 0);
+		AddrC   : in  std_logic_vector(2 downto 0);
+		DIH     : in  std_logic_vector(7 downto 0);
+		DIL     : in  std_logic_vector(7 downto 0);
+		DOAH    : out std_logic_vector(7 downto 0);
+		DOAL    : out std_logic_vector(7 downto 0);
+		DOBH    : out std_logic_vector(7 downto 0);
+		DOBL    : out std_logic_vector(7 downto 0);
+		DOCH    : out std_logic_vector(7 downto 0);
+		DOCL    : out std_logic_vector(7 downto 0);
+		DOR     : out std_logic_vector(127 downto 0);
+		DIRSet  : in  std_logic;
+		DIR     : in  std_logic_vector(127 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal RegsH : Register_Image(0 to 7);
+	signal RegsL : Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if rising_edge(Clk) then
+			if DIRSet = '1' then
+				RegsL(0) <= DIR(  7 downto   0);
+				RegsH(0) <= DIR( 15 downto   8);
+
+				RegsL(1) <= DIR( 23 downto  16);
+				RegsH(1) <= DIR( 31 downto  24);
+				
+				RegsL(2) <= DIR( 39 downto  32);
+				RegsH(2) <= DIR( 47 downto  40);
+
+				RegsL(3) <= DIR( 55 downto  48);
+				RegsH(3) <= DIR( 63 downto  56);
+
+				RegsL(4) <= DIR( 71 downto  64);
+				RegsH(4) <= DIR( 79 downto  72);
+
+				RegsL(5) <= DIR( 87 downto  80);
+				RegsH(5) <= DIR( 95 downto  88);
+
+				RegsL(6) <= DIR(103 downto  96);
+				RegsH(6) <= DIR(111 downto 104);
+
+				RegsL(7) <= DIR(119 downto 112);
+				RegsH(7) <= DIR(127 downto 120);
+			elsif CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+	DOR  <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0);
+
+end;
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80pa.vhd b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80pa.vhd
new file mode 100644
index 00000000..c09f15ae
--- /dev/null
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/T80pa.vhd	
@@ -0,0 +1,216 @@
+--
+-- Z80 compatible microprocessor core, preudo-asynchronous top level (by Sorgelig)
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- File history :
+--
+-- v1.0: convert to preudo-asynchronous model with original Z80 timings.
+--
+-- v2.0: rewritten for more precise timings.
+--       support for both CEN_n and CEN_p set to 1. Effective clock will be CLK/2.
+--
+-- v2.1: Output Address 0 during non-bus MCycle (fix ZX contention)
+--
+-- v2.2: Interrupt acknowledge cycle has been corrected
+--       WAIT_n is broken in T80.vhd. Simulate correct WAIT_n locally.
+--
+-- v2.3: Output last used Address during non-bus MCycle seems more correct.
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80pa is
+	generic(
+		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+	);
+	port(
+		RESET_n     : in  std_logic;
+		CLK	        : in  std_logic;
+		CEN_p       : in  std_logic := '1';
+		CEN_n       : in  std_logic := '1';
+		WAIT_n      : in  std_logic := '1';
+		INT_n       : in  std_logic := '1';
+		NMI_n       : in  std_logic := '1';
+		BUSRQ_n     : in  std_logic := '1';
+		M1_n        : out std_logic;
+		MREQ_n      : out std_logic;
+		IORQ_n      : out std_logic;
+		RD_n        : out std_logic;
+		WR_n        : out std_logic;
+		RFSH_n      : out std_logic;
+		HALT_n      : out std_logic;
+		BUSAK_n     : out std_logic;
+		OUT0        : in  std_logic := '0';  -- 0 => OUT(C),0, 1 => OUT(C),255
+		A           : out std_logic_vector(15 downto 0);
+		DI          : in  std_logic_vector(7 downto 0);
+		DO          : out std_logic_vector(7 downto 0);
+		REG         : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
+		DIRSet      : in  std_logic := '0';
+		DIR         : in  std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
+	);
+end T80pa;
+
+architecture rtl of T80pa is
+
+	signal IntCycle_n		: std_logic;
+	signal IntCycleD_n	: std_logic_vector(1 downto 0);
+	signal IORQ				: std_logic;
+	signal NoRead			: std_logic;
+	signal Write			: std_logic;
+	signal BUSAK			: std_logic;
+	signal DI_Reg			: std_logic_vector (7 downto 0);	-- Input synchroniser
+	signal MCycle			: std_logic_vector(2 downto 0);
+	signal TState			: std_logic_vector(2 downto 0);
+	signal CEN_pol			: std_logic;
+	signal A_int		   : std_logic_vector(15 downto 0);
+	signal A_last		   : std_logic_vector(15 downto 0);
+
+begin
+
+	A <= A_int when NoRead = '0' or Write = '1' else A_last;
+
+	BUSAK_n <= BUSAK;
+
+	u0 : work.T80
+		generic map(
+			Mode    => Mode,
+			IOWait  => 1
+		)
+		port map(
+			CEN     => CEN_p and not CEN_pol,
+			M1_n    => M1_n,
+			IORQ    => IORQ,
+			NoRead  => NoRead,
+			Write   => Write,
+			RFSH_n  => RFSH_n,
+			HALT_n  => HALT_n,
+			WAIT_n  => '1',
+			INT_n   => INT_n,
+			NMI_n   => NMI_n,
+			RESET_n => RESET_n,
+			BUSRQ_n => BUSRQ_n,
+			BUSAK_n => BUSAK,
+			CLK_n   => CLK,
+			A       => A_int,
+			DInst   => DI,     -- valid   at beginning of T3
+			DI      => DI_Reg, -- latched at middle    of T3
+			DO      => DO,
+			REG     => REG,
+			MC      => MCycle,
+			TS      => TState,
+			OUT0    => OUT0,
+			IntCycle_n => IntCycle_n,
+			DIRSet  => DIRSet,
+			DIR     => DIR
+		);
+
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			if RESET_n = '0' then
+				WR_n    <= '1';
+				RD_n    <= '1';
+				IORQ_n  <= '1';
+				MREQ_n  <= '1';
+				DI_Reg  <= "00000000";
+				CEN_pol <= '0';
+			elsif CEN_p = '1' and CEN_pol = '0' then
+				CEN_pol <= '1';
+				if MCycle = "001" then
+					if TState = "010" then
+						IORQ_n <= '1';
+						MREQ_n <= '1';
+						RD_n   <= '1';
+					end if;
+				else
+					if TState = "001" and IORQ = '1' then
+						WR_n   <= not Write;
+						RD_n   <= Write;
+						IORQ_n <= '0';
+					end if;
+				end if;
+			elsif CEN_n = '1' and CEN_pol = '1' then
+				if TState = "010" then
+					CEN_pol <= not WAIT_n;
+				else
+					CEN_pol <= '0';
+				end if;
+				if TState = "011" and BUSAK = '1' then
+					DI_Reg <= DI;
+				end if;
+				if MCycle = "001" then
+					if TState = "001" then
+						IntCycleD_n <= IntCycleD_n(0) & IntCycle_n;
+						RD_n   <= not IntCycle_n;
+						MREQ_n <= not IntCycle_n;
+						IORQ_n <= IntCycleD_n(1);
+						A_last <= A_int;
+					end if;
+					if TState = "011" then
+						IntCycleD_n <= "11";
+						RD_n   <= '1';
+						MREQ_n <= '0';
+					end if;
+					if TState = "100" then
+						MREQ_n <= '1';
+					end if;
+				else
+					if NoRead = '0' and IORQ = '0' then
+						if TState = "001" then
+							RD_n   <= Write;
+							MREQ_n <= '0';
+							A_last <= A_int;
+						end if;
+					end if;
+					if TState = "010" then
+						WR_n   <= not Write;
+					end if;
+					if TState = "011" then
+						WR_n   <= '1';
+						RD_n   <= '1';
+						IORQ_n <= '1';
+						MREQ_n <= '1';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+end;
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_alu.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_alu.v
deleted file mode 100644
index 2f015e21..00000000
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_alu.v	
+++ /dev/null
@@ -1,442 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-module tv80_alu (/*AUTOARG*/
-  // Outputs
-  Q, F_Out, 
-  // Inputs
-  Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
-  );
-
-  parameter		Mode   = 0;
-  parameter		Flag_C = 0;
-  parameter		Flag_N = 1;
-  parameter		Flag_P = 2;
-  parameter		Flag_X = 3;
-  parameter		Flag_H = 4;
-  parameter		Flag_Y = 5;
-  parameter		Flag_Z = 6;
-  parameter		Flag_S = 7;
-
-  input 		Arith16;
-  input 		Z16;
-  input [3:0]           ALU_Op ;
-  input [5:0]           IR;
-  input [1:0]           ISet;
-  input [7:0]           BusA;
-  input [7:0]           BusB;
-  input [7:0]           F_In;
-  output [7:0]          Q;
-  output [7:0]          F_Out;
-  reg [7:0]             Q;
-  reg [7:0]             F_Out;
-
-  function [4:0] AddSub4;
-    input [3:0] A;
-    input [3:0] B;
-    input Sub;
-    input Carry_In;
-    begin
-      AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
-    end
-  endfunction // AddSub4
-  
-  function [3:0] AddSub3;
-    input [2:0] A;
-    input [2:0] B;
-    input Sub;
-    input Carry_In;
-    begin
-      AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
-    end
-  endfunction // AddSub4
-
-  function [1:0] AddSub1;
-    input A;
-    input B;
-    input Sub;
-    input Carry_In;
-    begin
-      AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
-    end
-  endfunction // AddSub4
-
-  // AddSub variables (temporary signals)
-  reg UseCarry;
-  reg Carry7_v;
-  reg OverFlow_v;
-  reg HalfCarry_v;
-  reg Carry_v;
-  reg [7:0] Q_v;
-
-  reg [7:0] BitMask;
-
-
-  always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
-    begin
-      case (IR[5:3])
-        3'b000 : BitMask = 8'b00000001;
-        3'b001 : BitMask = 8'b00000010;
-        3'b010 : BitMask = 8'b00000100; 
-        3'b011 : BitMask = 8'b00001000; 
-        3'b100 : BitMask = 8'b00010000; 
-        3'b101 : BitMask = 8'b00100000; 
-        3'b110 : BitMask = 8'b01000000; 
-        default: BitMask = 8'b10000000; 
-      endcase // case(IR[5:3])
-      
-      UseCarry = ~ ALU_Op[2] && ALU_Op[0];
-      { HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
-      { Carry7_v, Q_v[6:4]  } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
-      { Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
-      OverFlow_v = Carry_v ^ Carry7_v;
-    end // always @ *
-  
-  reg [7:0] Q_t;
-  reg [8:0] DAA_Q;
-  
-  always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
-	    or Carry_v or F_In or HalfCarry_v or IR or ISet
-	    or OverFlow_v or Q_v or Z16)
-    begin
-      Q_t = 8'hxx;
-      DAA_Q = {9{1'bx}};
-      
-      F_Out = F_In;
-      case (ALU_Op)
-	4'b0000, 4'b0001,  4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
-          begin
-	    F_Out[Flag_N] = 1'b0;
-	    F_Out[Flag_C] = 1'b0;
-            
-	    case (ALU_Op[2:0])
-              
-	      3'b000, 3'b001 : // ADD, ADC
-                begin
-		  Q_t = Q_v;
-		  F_Out[Flag_C] = Carry_v;
-		  F_Out[Flag_H] = HalfCarry_v;
-		  F_Out[Flag_P] = OverFlow_v;
-                end
-              
-	      3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
-                begin
-		  Q_t = Q_v;
-		  F_Out[Flag_N] = 1'b1;
-		  F_Out[Flag_C] = ~ Carry_v;
-		  F_Out[Flag_H] = ~ HalfCarry_v;
-		  F_Out[Flag_P] = OverFlow_v;
-                end
-              
-	      3'b100 : // AND
-                begin
-		  Q_t[7:0] = BusA & BusB;
-		  F_Out[Flag_H] = 1'b1;
-                end
-              
-	      3'b101 : // XOR
-                begin
-		  Q_t[7:0] = BusA ^ BusB;
-		  F_Out[Flag_H] = 1'b0;
-                end
-              
-	      default : // OR 3'b110
-                begin
-		  Q_t[7:0] = BusA | BusB;
-		  F_Out[Flag_H] = 1'b0;
-                end
-              
-	    endcase // case(ALU_OP[2:0])
-            
-	    if (ALU_Op[2:0] == 3'b111 ) 
-              begin // CP
-		F_Out[Flag_X] = BusB[3];
-		F_Out[Flag_Y] = BusB[5];
-	      end 
-            else 
-              begin
-		F_Out[Flag_X] = Q_t[3];
-		F_Out[Flag_Y] = Q_t[5];
-	      end
-            
-	    if (Q_t[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-		if (Z16 == 1'b1 ) 
-                  begin
-		    F_Out[Flag_Z] = F_In[Flag_Z];	// 16 bit ADC,SBC
-		  end
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-	      end // else: !if(Q_t[7:0] == 8'b00000000 )
-            
-	    F_Out[Flag_S] = Q_t[7];
-	    case (ALU_Op[2:0])
-	      3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
-                ;
-              
-	      default :
-	        F_Out[Flag_P] = ~(^Q_t);                    
-	    endcase // case(ALU_Op[2:0])
-            
-	    if (Arith16 == 1'b1 ) 
-              begin
-		F_Out[Flag_S] = F_In[Flag_S];
-		F_Out[Flag_Z] = F_In[Flag_Z];
-		F_Out[Flag_P] = F_In[Flag_P];
-	      end
-          end // case: 4'b0000, 4'b0001,  4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
-        
-	4'b1100 :
-          begin
-	    // DAA
-	    F_Out[Flag_H] = F_In[Flag_H];
-	    F_Out[Flag_C] = F_In[Flag_C];
-	    DAA_Q[7:0] = BusA;
-	    DAA_Q[8] = 1'b0;
-	    if (F_In[Flag_N] == 1'b0 ) 
-              begin
-		// After addition
-		// Alow > 9 || H == 1
-		if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) 
-                  begin
-		    if ((DAA_Q[3:0] > 9) ) 
-                      begin
-			F_Out[Flag_H] = 1'b1;
-		      end 
-                    else 
-                      begin
-			F_Out[Flag_H] = 1'b0;
-		      end
-		    DAA_Q = DAA_Q + 6;
-		  end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
-                
-		// new Ahigh > 9 || C == 1
-		if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) 
-                  begin
-		    DAA_Q = DAA_Q + 96; // 0x60
-		  end
-	      end 
-            else 
-              begin
-		// After subtraction
-		if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) 
-                  begin
-		    if (DAA_Q[3:0] > 5 ) 
-                      begin
-			F_Out[Flag_H] = 1'b0;
-		      end
-		    DAA_Q[7:0] = DAA_Q[7:0] - 6;
-		  end
-		if (BusA > 153 || F_In[Flag_C] == 1'b1 ) 
-                  begin
-		    DAA_Q = DAA_Q - 352; // 0x160
-		  end
-	      end // else: !if(F_In[Flag_N] == 1'b0 )
-            
-	    F_Out[Flag_X] = DAA_Q[3];
-	    F_Out[Flag_Y] = DAA_Q[5];
-	    F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
-	    Q_t = DAA_Q[7:0];
-            
-	    if (DAA_Q[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-	      end
-            
-	    F_Out[Flag_S] = DAA_Q[7];
-	    F_Out[Flag_P] = ~ (^DAA_Q);
-          end // case: 4'b1100
-        
-	4'b1101, 4'b1110 :
-          begin
-	    // RLD, RRD
-	    Q_t[7:4] = BusA[7:4];
-	    if (ALU_Op[0] == 1'b1 ) 
-              begin
-		Q_t[3:0] = BusB[7:4];
-	      end 
-            else 
-              begin
-		Q_t[3:0] = BusB[3:0];
-	      end
-	    F_Out[Flag_H] = 1'b0;
-	    F_Out[Flag_N] = 1'b0;
-	    F_Out[Flag_X] = Q_t[3];
-	    F_Out[Flag_Y] = Q_t[5];
-	    if (Q_t[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-	      end
-	    F_Out[Flag_S] = Q_t[7];
-            F_Out[Flag_P] = ~(^Q_t);
-          end // case: when 4'b1101, 4'b1110
-        
-	4'b1001 :
-          begin
-	    // BIT
-	    Q_t[7:0] = BusB & BitMask;
-	    F_Out[Flag_S] = Q_t[7];
-	    if (Q_t[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-		F_Out[Flag_P] = 1'b1;
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-		F_Out[Flag_P] = 1'b0;
-	      end
-	    F_Out[Flag_H] = 1'b1;
-	    F_Out[Flag_N] = 1'b0;
-	    F_Out[Flag_X] = 1'b0;
-	    F_Out[Flag_Y] = 1'b0;
-	    if (IR[2:0] != 3'b110 ) 
-              begin
-		F_Out[Flag_X] = BusB[3];
-		F_Out[Flag_Y] = BusB[5];
-	      end
-          end // case: when 4'b1001
-        
-	4'b1010 :
-	  // SET
-	  Q_t[7:0] = BusB | BitMask;
-        
-	4'b1011 :
-	  // RES
-	  Q_t[7:0] = BusB & ~ BitMask;
-        
-	4'b1000 :
-          begin
-	    // ROT
-	    case (IR[5:3])
-	      3'b000 : // RLC
-                begin
-		  Q_t[7:1] = BusA[6:0];
-		  Q_t[0] = BusA[7];
-		  F_Out[Flag_C] = BusA[7];
-                end
-              
-	      3'b010 : // RL
-                begin
-		  Q_t[7:1] = BusA[6:0];
-		  Q_t[0] = F_In[Flag_C];
-		  F_Out[Flag_C] = BusA[7];
-                end
-              
-	      3'b001 : // RRC
-                begin
-		  Q_t[6:0] = BusA[7:1];
-		  Q_t[7] = BusA[0];
-		  F_Out[Flag_C] = BusA[0];
-                end
-              
-	      3'b011 : // RR
-                begin                        
-		  Q_t[6:0] = BusA[7:1];
-		  Q_t[7] = F_In[Flag_C];
-		  F_Out[Flag_C] = BusA[0];
-                end
-              
-	      3'b100 : // SLA
-                begin
-		  Q_t[7:1] = BusA[6:0];
-		  Q_t[0] = 1'b0;
-		  F_Out[Flag_C] = BusA[7];
-                end
-              
-	      3'b110 : // SLL (Undocumented) / SWAP
-                begin
-		  if (Mode == 3 ) 
-                    begin
-		      Q_t[7:4] = BusA[3:0];
-		      Q_t[3:0] = BusA[7:4];
-		      F_Out[Flag_C] = 1'b0;                            
-		    end 
-                  else 
-                    begin
-		      Q_t[7:1] = BusA[6:0];
-		      Q_t[0] = 1'b1;
-		      F_Out[Flag_C] = BusA[7];
-		    end // else: !if(Mode == 3 )
-                end // case: 3'b110
-              
-	      3'b101 : // SRA
-                begin
-		  Q_t[6:0] = BusA[7:1];
-		  Q_t[7] = BusA[7];
-		  F_Out[Flag_C] = BusA[0];
-                end
-              
-	      default : // SRL
-                begin
-		  Q_t[6:0] = BusA[7:1];
-		  Q_t[7] = 1'b0;
-		  F_Out[Flag_C] = BusA[0];
-                end
-	    endcase // case(IR[5:3])
-            
-	    F_Out[Flag_H] = 1'b0;
-	    F_Out[Flag_N] = 1'b0;
-	    F_Out[Flag_X] = Q_t[3];
-	    F_Out[Flag_Y] = Q_t[5];
-	    F_Out[Flag_S] = Q_t[7];
-	    if (Q_t[7:0] == 8'b00000000 ) 
-              begin
-		F_Out[Flag_Z] = 1'b1;
-	      end 
-            else 
-              begin
-		F_Out[Flag_Z] = 1'b0;
-	      end
-            F_Out[Flag_P] = ~(^Q_t);
-
-	    if (ISet == 2'b00 ) 
-              begin
-		F_Out[Flag_P] = F_In[Flag_P];
-		F_Out[Flag_S] = F_In[Flag_S];
-		F_Out[Flag_Z] = F_In[Flag_Z];
-	      end
-          end // case: 4'b1000
-        
-        
-	default :
-	  ;
-        
-      endcase // case(ALU_Op)
-      
-      Q = Q_t;
-    end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-  
-endmodule // T80_ALU
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_core.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_core.v
deleted file mode 100644
index af1483a1..00000000
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_core.v	
+++ /dev/null
@@ -1,1351 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-module tv80_core (/*AUTOARG*/
-  // Outputs
-  m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc, ts, 
-  intcycle_n, IntE, stop, 
-  // Inputs
-  reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
-  );
-  // Beginning of automatic inputs (from unused autoinst inputs)
-  // End of automatics
-  
-  parameter Mode = 1;   // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-  parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
-  parameter Flag_C = 0;
-  parameter Flag_N = 1;
-  parameter Flag_P = 2;
-  parameter Flag_X = 3;
-  parameter Flag_H = 4;
-  parameter Flag_Y = 5;
-  parameter Flag_Z = 6;
-  parameter Flag_S = 7;
-
-  input     reset_n;            
-  input     clk;                
-  input     cen;                
-  input     wait_n;             
-  input     int_n;              
-  input     nmi_n;              
-  input     busrq_n;            
-  output    m1_n;               
-  output    iorq;               
-  output    no_read;            
-  output    write;              
-  output    rfsh_n;             
-  output    halt_n;             
-  output    busak_n;            
-  output [15:0] A; 
-  input [7:0]   dinst;  
-  input [7:0]   di;     
-  output [7:0]  dout;     
-  output [6:0]  mc;     
-  output [6:0]  ts;     
-  output        intcycle_n;     
-  output        IntE;           
-  output        stop;           
-
-  reg    m1_n;          
-  reg    iorq;          
-  reg    rfsh_n;                
-  reg    halt_n;                
-  reg    busak_n;               
-  reg [15:0] A; 
-  reg [7:0]  dout;        
-  reg [6:0]  mc;        
-  reg [6:0]  ts;        
-  reg   intcycle_n;     
-  reg   IntE;           
-  reg   stop;           
-
-  parameter     aNone    = 3'b111;
-  parameter     aBC      = 3'b000;
-  parameter     aDE      = 3'b001;
-  parameter     aXY      = 3'b010;
-  parameter     aIOA     = 3'b100;
-  parameter     aSP      = 3'b101;
-  parameter     aZI      = 3'b110;
-
-  // Registers
-  reg [7:0]     ACC, F;
-  reg [7:0]     Ap, Fp;
-  reg [7:0]     I;
-  reg [7:0]     R;
-  reg [15:0]    SP, PC;
-  reg [7:0]     RegDIH;
-  reg [7:0]     RegDIL;
-  wire [15:0]   RegBusA;
-  wire [15:0]   RegBusB;
-  wire [15:0]   RegBusC;
-  reg [2:0]     RegAddrA_r;
-  reg [2:0]     RegAddrA;
-  reg [2:0]     RegAddrB_r;
-  reg [2:0]     RegAddrB;
-  reg [2:0]     RegAddrC;
-  reg           RegWEH;
-  reg           RegWEL;
-  reg           Alternate;
-
-  // Help Registers
-  reg [15:0]    TmpAddr;        // Temporary address register
-  reg [7:0]     IR;             // Instruction register
-  reg [1:0]     ISet;           // Instruction set selector
-  reg [15:0]    RegBusA_r;
-
-  reg [15:0]    ID16;
-  reg [7:0]     Save_Mux;
-
-  reg [6:0]     tstate;
-  reg [6:0]     mcycle;
-  reg           last_mcycle, last_tstate;
-  reg           IntE_FF1;
-  reg           IntE_FF2;
-  reg           Halt_FF;
-  reg           BusReq_s;
-  reg           BusAck;
-  reg           ClkEn;
-  reg           NMI_s;
-  reg           INT_s;
-  reg [1:0]     IStatus;
-
-  reg [7:0]     DI_Reg;
-  reg           T_Res;
-  reg [1:0]     XY_State;
-  reg [2:0]     Pre_XY_F_M;
-  reg           NextIs_XY_Fetch;
-  reg           XY_Ind;
-  reg           No_BTR;
-  reg           BTR_r;
-  reg           Auto_Wait;
-  reg           Auto_Wait_t1;
-  reg           Auto_Wait_t2;
-  reg           IncDecZ;
-
-  // ALU signals
-  reg [7:0]     BusB;
-  reg [7:0]     BusA;
-  wire [7:0]    ALU_Q;
-  wire [7:0]    F_Out;
-
-  // Registered micro code outputs
-  reg [4:0]     Read_To_Reg_r;
-  reg           Arith16_r;
-  reg           Z16_r;
-  reg [3:0]     ALU_Op_r;
-  reg           Save_ALU_r;
-  reg           PreserveC_r;
-  reg [2:0]     mcycles;
-
-  // Micro code outputs
-  wire [2:0]    mcycles_d;
-  wire [2:0]    tstates;
-  reg           IntCycle;
-  reg           NMICycle;
-  wire          Inc_PC;
-  wire          Inc_WZ;
-  wire [3:0]    IncDec_16;
-  wire [1:0]    Prefix;
-  wire          Read_To_Acc;
-  wire          Read_To_Reg;
-  wire [3:0]     Set_BusB_To;
-  wire [3:0]     Set_BusA_To;
-  wire [3:0]     ALU_Op;
-  wire           Save_ALU;
-  wire           PreserveC;
-  wire           Arith16;
-  wire [2:0]     Set_Addr_To;
-  wire           Jump;
-  wire           JumpE;
-  wire           JumpXY;
-  wire           Call;
-  wire           RstP;
-  wire           LDZ;
-  wire           LDW;
-  wire           LDSPHL;
-  wire           iorq_i;
-  wire [2:0]     Special_LD;
-  wire           ExchangeDH;
-  wire           ExchangeRp;
-  wire           ExchangeAF;
-  wire           ExchangeRS;
-  wire           I_DJNZ;
-  wire           I_CPL;
-  wire           I_CCF;
-  wire           I_SCF;
-  wire           I_RETN;
-  wire           I_BT;
-  wire           I_BC;
-  wire           I_BTR;
-  wire           I_RLD;
-  wire           I_RRD;
-  wire           I_INRC;
-  wire           SetDI;
-  wire           SetEI;
-  wire [1:0]     IMode;
-  wire           Halt;
-
-  reg [15:0]     PC16;
-  reg [15:0]     PC16_B;
-  reg [15:0]     SP16, SP16_A, SP16_B;
-  reg [15:0]     ID16_B;
-  reg            Oldnmi_n;
-  
-  tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode
-    (
-     .IR                   (IR),
-     .ISet                 (ISet),
-     .MCycle               (mcycle),
-     .F                    (F),
-     .NMICycle             (NMICycle),
-     .IntCycle             (IntCycle),
-     .MCycles              (mcycles_d),
-     .TStates              (tstates),
-     .Prefix               (Prefix),
-     .Inc_PC               (Inc_PC),
-     .Inc_WZ               (Inc_WZ),
-     .IncDec_16            (IncDec_16),
-     .Read_To_Acc          (Read_To_Acc),
-     .Read_To_Reg          (Read_To_Reg),
-     .Set_BusB_To          (Set_BusB_To),
-     .Set_BusA_To          (Set_BusA_To),
-     .ALU_Op               (ALU_Op),
-     .Save_ALU             (Save_ALU),
-     .PreserveC            (PreserveC),
-     .Arith16              (Arith16),
-     .Set_Addr_To          (Set_Addr_To),
-     .IORQ                 (iorq_i),
-     .Jump                 (Jump),
-     .JumpE                (JumpE),
-     .JumpXY               (JumpXY),
-     .Call                 (Call),
-     .RstP                 (RstP),
-     .LDZ                  (LDZ),
-     .LDW                  (LDW),
-     .LDSPHL               (LDSPHL),
-     .Special_LD           (Special_LD),
-     .ExchangeDH           (ExchangeDH),
-     .ExchangeRp           (ExchangeRp),
-     .ExchangeAF           (ExchangeAF),
-     .ExchangeRS           (ExchangeRS),
-     .I_DJNZ               (I_DJNZ),
-     .I_CPL                (I_CPL),
-     .I_CCF                (I_CCF),
-     .I_SCF                (I_SCF),
-     .I_RETN               (I_RETN),
-     .I_BT                 (I_BT),
-     .I_BC                 (I_BC),
-     .I_BTR                (I_BTR),
-     .I_RLD                (I_RLD),
-     .I_RRD                (I_RRD),
-     .I_INRC               (I_INRC),
-     .SetDI                (SetDI),
-     .SetEI                (SetEI),
-     .IMode                (IMode),
-     .Halt                 (Halt),
-     .NoRead               (no_read),
-     .Write                (write)
-     );
-
-  tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu
-    (
-     .Arith16              (Arith16_r),
-     .Z16                  (Z16_r),
-     .ALU_Op               (ALU_Op_r),
-     .IR                   (IR[5:0]),
-     .ISet                 (ISet),
-     .BusA                 (BusA),
-     .BusB                 (BusB),
-     .F_In                 (F),
-     .Q                    (ALU_Q),
-     .F_Out                (F_Out)
-     );
-
-  function [6:0] number_to_bitvec;
-    input [2:0] num;
-    begin
-      case (num)
-        1 : number_to_bitvec = 7'b0000001;
-        2 : number_to_bitvec = 7'b0000010;
-        3 : number_to_bitvec = 7'b0000100;
-        4 : number_to_bitvec = 7'b0001000;
-        5 : number_to_bitvec = 7'b0010000;
-        6 : number_to_bitvec = 7'b0100000;
-        7 : number_to_bitvec = 7'b1000000;
-        default : number_to_bitvec = 7'bx;
-      endcase // case(num)
-    end
-  endfunction // number_to_bitvec
-  
-  always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
-    begin
-      case (mcycles)
-        1 : last_mcycle = mcycle[0];
-        2 : last_mcycle = mcycle[1];
-        3 : last_mcycle = mcycle[2];
-        4 : last_mcycle = mcycle[3];
-        5 : last_mcycle = mcycle[4];
-        6 : last_mcycle = mcycle[5];
-        7 : last_mcycle = mcycle[6];
-        default : last_mcycle = 1'bx;
-      endcase // case(mcycles)
-
-      case (tstates)
-        0 : last_tstate = tstate[0];
-        1 : last_tstate = tstate[1];
-        2 : last_tstate = tstate[2];
-        3 : last_tstate = tstate[3];
-        4 : last_tstate = tstate[4];
-        5 : last_tstate = tstate[5];
-        6 : last_tstate = tstate[6];
-        default : last_tstate = 1'bx;
-      endcase
-    end // always @ (...
-  
-          
-  always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg
-           or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind
-           or XY_State or cen or last_tstate or mcycle)
-    begin
-      ClkEn = cen && ~ BusAck;
-
-      if (last_tstate)
-        T_Res = 1'b1;
-      else T_Res = 1'b0;
-      
-      if (XY_State != 2'b00 && XY_Ind == 1'b0 &&
-          ((Set_Addr_To == aXY) ||
-           (mcycle[0] && IR == 8'b11001011) ||
-           (mcycle[0] && IR == 8'b00110110)))
-        NextIs_XY_Fetch = 1'b1;
-      else 
-        NextIs_XY_Fetch = 1'b0;
-
-      if (ExchangeRp)
-        Save_Mux = BusB;
-      else if (!Save_ALU_r)
-        Save_Mux = DI_Reg;
-      else
-        Save_Mux = ALU_Q;
-    end // always @ *
-  
-  always @ (posedge clk)
-    begin
-      if (reset_n == 1'b0 ) 
-        begin
-          PC <= #1 0;  // Program Counter
-          A <= #1 0;
-          TmpAddr <= #1 0;
-          IR <= #1 8'b00000000;
-          ISet <= #1 2'b00;
-          XY_State <= #1 2'b00;
-          IStatus <= #1 2'b00;
-          mcycles <= #1 3'b000;
-          dout <= #1 8'b00000000;
-
-          ACC <= #1 8'hFF;
-          F <= #1 8'hFF;
-          Ap <= #1 8'hFF;
-          Fp <= #1 8'hFF;
-          I <= #1 0;
-          `ifdef TV80_REFRESH
-          R <= #1 0;
-          `endif
-          SP <= #1 16'hFFFF;
-          Alternate <= #1 1'b0;
-
-          Read_To_Reg_r <= #1 5'b00000;
-          Arith16_r <= #1 1'b0;
-          BTR_r <= #1 1'b0;
-          Z16_r <= #1 1'b0;
-          ALU_Op_r <= #1 4'b0000;
-          Save_ALU_r <= #1 1'b0;
-          PreserveC_r <= #1 1'b0;
-          XY_Ind <= #1 1'b0;
-        end 
-      else 
-        begin
-
-          if (ClkEn == 1'b1 ) 
-            begin
-
-              ALU_Op_r <= #1 4'b0000;
-              Save_ALU_r <= #1 1'b0;
-              Read_To_Reg_r <= #1 5'b00000;
-
-              mcycles <= #1 mcycles_d;
-
-              if (IMode != 2'b11 ) 
-                begin
-                  IStatus <= #1 IMode;
-                end
-
-              Arith16_r <= #1 Arith16;
-              PreserveC_r <= #1 PreserveC;
-              if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] ) 
-                begin
-                  Z16_r <= #1 1'b1;
-                end 
-              else 
-                begin
-                  Z16_r <= #1 1'b0;
-                end
-
-              if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] )) 
-                begin
-                  // mcycle == 1 && tstate == 1, 2, || 3
-                  if (tstate[2] && wait_n == 1'b1 ) 
-                    begin
-                      `ifdef TV80_REFRESH
-                      if (Mode < 2 ) 
-                        begin
-                          A[7:0] <= #1 R;
-                          A[15:8] <= #1 I;
-                          R[6:0] <= #1 R[6:0] + 1;
-                        end
-                      `endif
-                      if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) ) 
-                        begin
-                          PC <= #1 PC16;
-                        end
-
-                      if (IntCycle == 1'b1 && IStatus == 2'b01 ) 
-                        begin
-                          IR <= #1 8'b11111111;
-                        end 
-                      else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 ) 
-                        begin
-                          IR <= #1 8'b00000000;
-                        end 
-                      else 
-                        begin
-                          IR <= #1 dinst;
-                        end
-
-                      ISet <= #1 2'b00;
-                      if (Prefix != 2'b00 ) 
-                        begin
-                          if (Prefix == 2'b11 ) 
-                            begin
-                              if (IR[5] == 1'b1 ) 
-                                begin
-                                  XY_State <= #1 2'b10;
-                                end 
-                              else 
-                                begin
-                                  XY_State <= #1 2'b01;
-                                end
-                            end 
-                          else 
-                            begin
-                              if (Prefix == 2'b10 ) 
-                                begin
-                                  XY_State <= #1 2'b00;
-                                  XY_Ind <= #1 1'b0;
-                                end
-                              ISet <= #1 Prefix;
-                            end
-                        end 
-                      else 
-                        begin
-                          XY_State <= #1 2'b00;
-                          XY_Ind <= #1 1'b0;
-                        end
-                    end // if (tstate == 2 && wait_n == 1'b1 )
-                  
-
-                end 
-              else 
-                begin
-                  // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3)
-
-                  if (mcycle[5] ) 
-                    begin
-                      XY_Ind <= #1 1'b1;
-                      if (Prefix == 2'b01 ) 
-                        begin
-                          ISet <= #1 2'b01;
-                        end
-                    end
-                  
-                  if (T_Res == 1'b1 ) 
-                    begin
-                      BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR;
-                      if (Jump == 1'b1 ) 
-                        begin
-                          A[15:8] <= #1 DI_Reg;
-                          A[7:0] <= #1 TmpAddr[7:0];
-                          PC[15:8] <= #1 DI_Reg;
-                          PC[7:0] <= #1 TmpAddr[7:0];
-                        end 
-                      else if (JumpXY == 1'b1 ) 
-                        begin
-                          A <= #1 RegBusC;
-                          PC <= #1 RegBusC;
-                        end else if (Call == 1'b1 || RstP == 1'b1 ) 
-                          begin
-                            A <= #1 TmpAddr;
-                            PC <= #1 TmpAddr;
-                          end 
-                        else if (last_mcycle && NMICycle == 1'b1 ) 
-                          begin
-                            A <= #1 16'b0000000001100110;
-                            PC <= #1 16'b0000000001100110;
-                          end 
-                        else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 ) 
-                          begin
-                            A[15:8] <= #1 I;
-                            A[7:0] <= #1 TmpAddr[7:0];
-                            PC[15:8] <= #1 I;
-                            PC[7:0] <= #1 TmpAddr[7:0];
-                          end 
-                        else 
-                          begin
-                            case (Set_Addr_To)
-                              aXY :
-                                begin
-                                  if (XY_State == 2'b00 ) 
-                                    begin
-                                      A <= #1 RegBusC;
-                                    end 
-                                  else 
-                                    begin
-                                      if (NextIs_XY_Fetch == 1'b1 )
-                                        begin
-                                          A <= #1 PC;
-                                        end 
-                                      else 
-                                        begin
-                                          A <= #1 TmpAddr;
-                                        end
-                                    end // else: !if(XY_State == 2'b00 )
-                                end // case: aXY
-                              
-                              aIOA :
-                                begin
-                                  if (Mode == 3 ) 
-                                    begin
-                                      // Memory map I/O on GBZ80
-                                      A[15:8] <= #1 8'hFF;
-                                    end 
-                                  else if (Mode == 2 ) 
-                                    begin
-                                      // Duplicate I/O address on 8080
-                                      A[15:8] <= #1 DI_Reg;
-                                    end 
-                                  else 
-                                    begin
-                                      A[15:8] <= #1 ACC;
-                                    end
-                                  A[7:0] <= #1 DI_Reg;
-                                end // case: aIOA
-
-                              
-                              aSP :
-                                begin
-                                  A <= #1 SP;
-                                end
-                              
-                              aBC :
-                                begin
-                                  if (Mode == 3 && iorq_i == 1'b1 ) 
-                                    begin
-                                      // Memory map I/O on GBZ80
-                                      A[15:8] <= #1 8'hFF;
-                                      A[7:0] <= #1 RegBusC[7:0];
-                                    end 
-                                  else 
-                                    begin
-                                      A <= #1 RegBusC;
-                                    end
-                                end // case: aBC
-                              
-                              aDE :
-                                begin
-                                  A <= #1 RegBusC;
-                                end
-                              
-                              aZI :
-                                begin                                  
-                                  if (Inc_WZ == 1'b1 ) 
-                                    begin
-                                      A <= #1 TmpAddr + 1;
-                                    end 
-                                  else 
-                                    begin
-                                      A[15:8] <= #1 DI_Reg;
-                                      A[7:0] <= #1 TmpAddr[7:0];
-                                    end
-                                end // case: aZI
-                              
-                              default   :
-                                begin                                    
-                                  A <= #1 PC;
-                                end
-                            endcase // case(Set_Addr_To)
-                            
-                          end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
-                      
-
-                      Save_ALU_r <= #1 Save_ALU;
-                      ALU_Op_r <= #1 ALU_Op;
-                      
-                      if (I_CPL == 1'b1 ) 
-                        begin
-                          // CPL
-                          ACC <= #1 ~ ACC;
-                          F[Flag_Y] <= #1 ~ ACC[5];
-                          F[Flag_H] <= #1 1'b1;
-                          F[Flag_X] <= #1 ~ ACC[3];
-                          F[Flag_N] <= #1 1'b1;
-                        end
-                      if (I_CCF == 1'b1 ) 
-                        begin
-                          // CCF
-                          F[Flag_C] <= #1 ~ F[Flag_C];
-                          F[Flag_Y] <= #1 ACC[5];
-                          F[Flag_H] <= #1 F[Flag_C];
-                          F[Flag_X] <= #1 ACC[3];
-                          F[Flag_N] <= #1 1'b0;
-                        end
-                      if (I_SCF == 1'b1 ) 
-                        begin
-                          // SCF
-                          F[Flag_C] <= #1 1'b1;
-                          F[Flag_Y] <= #1 ACC[5];
-                          F[Flag_H] <= #1 1'b0;
-                          F[Flag_X] <= #1 ACC[3];
-                          F[Flag_N] <= #1 1'b0;
-                        end
-                    end // if (T_Res == 1'b1 )
-                  
-
-                  if (tstate[2] && wait_n == 1'b1 ) 
-                    begin
-                      if (ISet == 2'b01 && mcycle[6] ) 
-                        begin
-                          IR <= #1 dinst;
-                        end
-                      if (JumpE == 1'b1 ) 
-                        begin
-                          PC <= #1 PC16;
-                        end 
-                      else if (Inc_PC == 1'b1 ) 
-                        begin
-                          //PC <= #1 PC + 1;
-                          PC <= #1 PC16;
-                        end
-                      if (BTR_r == 1'b1 ) 
-                        begin
-                          //PC <= #1 PC - 2;
-                          PC <= #1 PC16;
-                        end
-                      if (RstP == 1'b1 ) 
-                        begin
-                          TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 };
-                          //TmpAddr <= #1 (others =>1'b0);
-                          //TmpAddr[5:3] <= #1 IR[5:3];
-                        end
-                    end
-                  if (tstate[3] && mcycle[5] ) 
-                    begin
-                      TmpAddr <= #1 SP16;
-                    end
-
-                  if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) ) 
-                    begin
-                      if (IncDec_16[2:0] == 3'b111 ) 
-                        begin
-                          SP <= #1 SP16;
-                        end
-                    end
-
-                  if (LDSPHL == 1'b1 ) 
-                    begin
-                      SP <= #1 RegBusC;
-                    end
-                  if (ExchangeAF == 1'b1 ) 
-                    begin
-                      Ap <= #1 ACC;
-                      ACC <= #1 Ap;
-                      Fp <= #1 F;
-                      F <= #1 Fp;
-                    end
-                  if (ExchangeRS == 1'b1 ) 
-                    begin
-                      Alternate <= #1 ~ Alternate;
-                    end
-                end // else: !if(mcycle  == 3'b001 && tstate(2) == 1'b0 )
-              
-
-              if (tstate[3] ) 
-                begin
-                  if (LDZ == 1'b1 ) 
-                    begin
-                      TmpAddr[7:0] <= #1 DI_Reg;
-                    end
-                  if (LDW == 1'b1 ) 
-                    begin
-                      TmpAddr[15:8] <= #1 DI_Reg;
-                    end
-
-                  if (Special_LD[2] == 1'b1 ) 
-                    begin
-                      case (Special_LD[1:0])
-                        2'b00 :
-                          begin
-                            ACC <= #1 I;
-                            F[Flag_P] <= #1 IntE_FF2;
-                          end
-                        
-                        2'b01 :
-                          begin
-                            ACC <= #1 R;
-                            F[Flag_P] <= #1 IntE_FF2;
-                          end
-                        
-                        2'b10 :
-                          I <= #1 ACC;
-
-                        `ifdef TV80_REFRESH                        
-                        default :
-                          R <= #1 ACC;
-                        `else
-                        default : ;
-                        `endif                        
-                      endcase
-                    end
-                end // if (tstate == 3 )
-              
-
-              if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 ) 
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      F[6] <= #1 F_Out[6];
-                      F[5] <= #1 F_Out[5];
-                      F[7] <= #1 F_Out[7];
-                      if (PreserveC_r == 1'b0 ) 
-                        begin
-                          F[4] <= #1 F_Out[4];
-                        end
-                    end 
-                  else 
-                    begin
-                      F[7:1] <= #1 F_Out[7:1];
-                      if (PreserveC_r == 1'b0 ) 
-                        begin
-                          F[Flag_C] <= #1 F_Out[0];
-                        end
-                    end
-                end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
-              
-              if (T_Res == 1'b1 && I_INRC == 1'b1 ) 
-                begin
-                  F[Flag_H] <= #1 1'b0;
-                  F[Flag_N] <= #1 1'b0;
-                  if (DI_Reg[7:0] == 8'b00000000 ) 
-                    begin
-                      F[Flag_Z] <= #1 1'b1;
-                    end 
-                  else 
-                    begin
-                      F[Flag_Z] <= #1 1'b0;
-                    end
-                  F[Flag_S] <= #1 DI_Reg[7];
-                  F[Flag_P] <= #1 ~ (^DI_Reg[7:0]);
-                end // if (T_Res == 1'b1 && I_INRC == 1'b1 )
-              
-
-              if (tstate[1] && Auto_Wait_t1 == 1'b0 ) 
-                begin
-                  dout <= #1 BusB;
-                  if (I_RLD == 1'b1 ) 
-                    begin
-                      dout[3:0] <= #1 BusA[3:0];
-                      dout[7:4] <= #1 BusB[3:0];
-                    end
-                  if (I_RRD == 1'b1 ) 
-                    begin
-                      dout[3:0] <= #1 BusB[7:4];
-                      dout[7:4] <= #1 BusA[3:0];
-                    end
-                end
-
-              if (T_Res == 1'b1 ) 
-                begin
-                  Read_To_Reg_r[3:0] <= #1 Set_BusA_To;
-                  Read_To_Reg_r[4] <= #1 Read_To_Reg;
-                  if (Read_To_Acc == 1'b1 ) 
-                    begin
-                      Read_To_Reg_r[3:0] <= #1 4'b0111;
-                      Read_To_Reg_r[4] <= #1 1'b1;
-                    end
-                end
-
-              if (tstate[1] && I_BT == 1'b1 ) 
-                begin
-                  F[Flag_X] <= #1 ALU_Q[3];
-                  F[Flag_Y] <= #1 ALU_Q[1];
-                  F[Flag_H] <= #1 1'b0;
-                  F[Flag_N] <= #1 1'b0;
-                end
-              if (I_BC == 1'b1 || I_BT == 1'b1 ) 
-                begin
-                  F[Flag_P] <= #1 IncDecZ;
-                end
-
-              if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
-                  (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) 
-                begin
-                  case (Read_To_Reg_r)
-                    5'b10111 :
-                      ACC <= #1 Save_Mux;
-                    5'b10110 :
-                      dout <= #1 Save_Mux;
-                    5'b11000 :
-                      SP[7:0] <= #1 Save_Mux;
-                    5'b11001 :
-                      SP[15:8] <= #1 Save_Mux;
-                    5'b11011 :
-                      F <= #1 Save_Mux;
-                  endcase
-                end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...              
-            end // if (ClkEn == 1'b1 )         
-        end // else: !if(reset_n == 1'b0 )
-    end
-  
-
-  //-------------------------------------------------------------------------
-  //
-  // BC('), DE('), HL('), IX && IY
-  //
-  //-------------------------------------------------------------------------
-  always @ (posedge clk)
-    begin
-      if (ClkEn == 1'b1 ) 
-        begin
-          // Bus A / Write
-          RegAddrA_r <= #1  { Alternate, Set_BusA_To[2:1] };
-          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 ) 
-            begin
-              RegAddrA_r <= #1 { XY_State[1],  2'b11 };
-            end
-
-          // Bus B
-          RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] };
-          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 ) 
-            begin
-              RegAddrB_r <= #1 { XY_State[1],  2'b11 };
-            end
-
-          // Address from register
-          RegAddrC <= #1 { Alternate,  Set_Addr_To[1:0] };
-          // Jump (HL), LD SP,HL
-          if ((JumpXY == 1'b1 || LDSPHL == 1'b1) ) 
-            begin
-              RegAddrC <= #1 { Alternate, 2'b10 };
-            end
-          if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) ) 
-            begin
-              RegAddrC <= #1 { XY_State[1],  2'b11 };
-            end
-
-          if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 ) 
-            begin
-              IncDecZ <= #1 F_Out[Flag_Z];
-            end
-          if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 ) 
-            begin
-              if (ID16 == 0 ) 
-                begin
-                  IncDecZ <= #1 1'b0;
-                end 
-              else 
-                begin
-                  IncDecZ <= #1 1'b1;
-                end
-            end
-          
-          RegBusA_r <= #1 RegBusA;
-        end
-      
-    end // always @ (posedge clk)
-  
-
-  always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16
-           or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate)
-    begin
-      if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00)
-        RegAddrA = { Alternate, IncDec_16[1:0] };
-      else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10)
-        RegAddrA = { XY_State[1], 2'b11 };
-      else if (ExchangeDH == 1'b1 && tstate[3])
-        RegAddrA = { Alternate, 2'b10 };
-      else if (ExchangeDH == 1'b1 && tstate[4])
-        RegAddrA = { Alternate, 2'b01 };
-      else
-        RegAddrA = RegAddrA_r;
-      
-      if (ExchangeDH == 1'b1 && tstate[3])
-        RegAddrB = { Alternate, 2'b01 };
-      else
-        RegAddrB = RegAddrB_r;
-    end // always @ *
-  
-
-  always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH
-           or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
-           or tstate or wait_n)
-    begin
-      RegWEH = 1'b0;
-      RegWEL = 1'b0;
-      if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
-          (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) ) 
-        begin
-          case (Read_To_Reg_r)
-            5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
-              begin
-                RegWEH = ~ Read_To_Reg_r[0];
-                RegWEL = Read_To_Reg_r[0];
-              end
-          endcase // case(Read_To_Reg_r)
-          
-        end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
-      
-
-      if (ExchangeDH == 1'b1 && (tstate[3] || tstate[4]) ) 
-        begin
-          RegWEH = 1'b1;
-          RegWEL = 1'b1;
-        end
-
-      if (IncDec_16[2] == 1'b1 && ((tstate[2] && wait_n == 1'b1 && mcycle != 3'b001) || (tstate[3] && mcycle[0])) ) 
-        begin
-          case (IncDec_16[1:0])
-            2'b00 , 2'b01 , 2'b10 :
-              begin
-                RegWEH = 1'b1;
-                RegWEL = 1'b1;
-              end
-          endcase
-        end
-    end // always @ *
-  
-
-  always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r
-           or RegBusB or Save_Mux or mcycle or tstate)
-    begin
-      RegDIH = Save_Mux;
-      RegDIL = Save_Mux;
-
-      if (ExchangeDH == 1'b1 && tstate[3] ) 
-        begin
-          RegDIH = RegBusB[15:8];
-          RegDIL = RegBusB[7:0];
-        end
-      else if (ExchangeDH == 1'b1 && tstate[4] ) 
-        begin
-          RegDIH = RegBusA_r[15:8];
-          RegDIL = RegBusA_r[7:0];
-        end
-      else if (IncDec_16[2] == 1'b1 && ((tstate[2] && mcycle != 3'b001) || (tstate[3] && mcycle[0])) ) 
-        begin
-          RegDIH = ID16[15:8];
-          RegDIL = ID16[7:0];
-        end
-    end
-
-  tv80_reg i_reg
-    (
-     .clk                  (clk),
-     .CEN                  (ClkEn),
-     .WEH                  (RegWEH),
-     .WEL                  (RegWEL),
-     .AddrA                (RegAddrA),
-     .AddrB                (RegAddrB),
-     .AddrC                (RegAddrC),
-     .DIH                  (RegDIH),
-     .DIL                  (RegDIL),
-     .DOAH                 (RegBusA[15:8]),
-     .DOAL                 (RegBusA[7:0]),
-     .DOBH                 (RegBusB[15:8]),
-     .DOBL                 (RegBusB[7:0]),
-     .DOCH                 (RegBusC[15:8]),
-     .DOCL                 (RegBusC[7:0])
-     );
-
-  //-------------------------------------------------------------------------
-  //
-  // Buses
-  //
-  //-------------------------------------------------------------------------
-
-  always @ (posedge clk)
-    begin
-      if (ClkEn == 1'b1 ) 
-        begin
-          case (Set_BusB_To)
-            4'b0111 :
-              BusB <= #1 ACC;
-            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
-              begin
-                if (Set_BusB_To[0] == 1'b1 ) 
-                  begin
-                    BusB <= #1 RegBusB[7:0];
-                  end 
-                else 
-                  begin
-                    BusB <= #1 RegBusB[15:8];
-                  end
-              end
-            4'b0110 :
-              BusB <= #1 DI_Reg;
-            4'b1000 :
-              BusB <= #1 SP[7:0];
-            4'b1001 :
-              BusB <= #1 SP[15:8];
-            4'b1010 :
-              BusB <= #1 8'b00000001;
-            4'b1011 :
-              BusB <= #1 F;
-            4'b1100 :
-              BusB <= #1 PC[7:0];
-            4'b1101 :
-              BusB <= #1 PC[15:8];
-            4'b1110 :
-              BusB <= #1 8'b00000000;
-            default :
-              BusB <= #1 8'hxx;
-          endcase
-
-          case (Set_BusA_To)
-            4'b0111 :
-              BusA <= #1 ACC;
-            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
-              begin
-                if (Set_BusA_To[0] == 1'b1 )
-                  begin
-                    BusA <= #1 RegBusA[7:0];
-                  end 
-                else 
-                  begin
-                    BusA <= #1 RegBusA[15:8];
-                  end
-              end
-            4'b0110 :
-              BusA <= #1 DI_Reg;
-            4'b1000 :
-              BusA <= #1 SP[7:0];
-            4'b1001 :
-              BusA <= #1 SP[15:8];
-            4'b1010 :
-              BusA <= #1 8'b00000000;
-            default :
-              BusB <= #1  8'hxx;
-          endcase
-        end
-    end
-
-  //-------------------------------------------------------------------------
-  //
-  // Generate external control signals
-  //
-  //-------------------------------------------------------------------------
-`ifdef TV80_REFRESH
-  always @ (posedge clk)
-    begin
-      if (reset_n == 1'b0 ) 
-        begin
-          rfsh_n <= #1 1'b1;
-        end 
-      else
-        begin
-          if (cen == 1'b1 ) 
-            begin
-              if (mcycle[0] && ((tstate[2]  && wait_n == 1'b1) || tstate[3]) ) 
-                begin
-                  rfsh_n <= #1 1'b0;
-                end 
-              else 
-                begin
-                  rfsh_n <= #1 1'b1;
-                end
-            end
-        end
-    end
-`endif  
-
-  always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle
-           or IntE_FF1 or di or iorq_i or mcycle or tstate)
-    begin
-      mc = mcycle;
-      ts = tstate;
-      DI_Reg = di;
-      halt_n = ~ Halt_FF;
-      busak_n = ~ BusAck;
-      intcycle_n = ~ IntCycle;
-      IntE = IntE_FF1;
-      iorq = iorq_i;
-      stop = I_DJNZ;
-    end
-
-  //-----------------------------------------------------------------------
-  //
-  // Syncronise inputs
-  //
-  //-----------------------------------------------------------------------
-
-  always @ (posedge clk)
-    begin : sync_inputs
-
-      if (reset_n == 1'b0 ) 
-        begin
-          BusReq_s <= #1 1'b0;
-          INT_s <= #1 1'b0;
-          NMI_s <= #1 1'b0;
-          Oldnmi_n <= #1 1'b0;
-        end 
-      else
-        begin
-          if (cen == 1'b1 ) 
-            begin
-              BusReq_s <= #1 ~ busrq_n;
-              INT_s <= #1 ~ int_n;
-              if (NMICycle == 1'b1 ) 
-                begin
-                  NMI_s <= #1 1'b0;
-                end 
-              else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 ) 
-                begin
-                  NMI_s <= #1 1'b1;
-                end
-              Oldnmi_n <= #1 nmi_n;
-            end
-        end
-    end
-
-  //-----------------------------------------------------------------------
-  //
-  // Main state machine
-  //
-  //-----------------------------------------------------------------------
-
-  always @ (posedge clk)
-    begin
-      if (reset_n == 1'b0 ) 
-        begin
-          mcycle <= #1 7'b0000001;
-          tstate <= #1 7'b0000001;
-          Pre_XY_F_M <= #1 3'b000;
-          Halt_FF <= #1 1'b0;
-          BusAck <= #1 1'b0;
-          NMICycle <= #1 1'b0;
-          IntCycle <= #1 1'b0;
-          IntE_FF1 <= #1 1'b0;
-          IntE_FF2 <= #1 1'b0;
-          No_BTR <= #1 1'b0;
-          Auto_Wait_t1 <= #1 1'b0;
-          Auto_Wait_t2 <= #1 1'b0;
-          m1_n <= #1 1'b1;
-        end 
-      else
-        begin
-          if (cen == 1'b1 ) 
-            begin
-              if (T_Res == 1'b1 ) 
-                begin
-                  Auto_Wait_t1 <= #1 1'b0;
-                end 
-              else 
-                begin
-                  Auto_Wait_t1 <= #1 Auto_Wait || iorq_i;
-                end
-              Auto_Wait_t2 <= #1 Auto_Wait_t1;
-              No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) ||
-                        (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) ||
-                        (I_BTR && (~ IR[4] || F[Flag_Z]));
-              if (tstate[2] ) 
-                begin
-                  if (SetEI == 1'b1 ) 
-                    begin
-                      IntE_FF1 <= #1 1'b1;
-                      IntE_FF2 <= #1 1'b1;
-                    end
-                  if (I_RETN == 1'b1 ) 
-                    begin
-                      IntE_FF1 <= #1 IntE_FF2;
-                    end
-                end
-              if (tstate[3] ) 
-                begin
-                  if (SetDI == 1'b1 ) 
-                    begin
-                      IntE_FF1 <= #1 1'b0;
-                      IntE_FF2 <= #1 1'b0;
-                    end
-                end
-              if (IntCycle == 1'b1 || NMICycle == 1'b1 ) 
-                begin
-                  Halt_FF <= #1 1'b0;
-                end
-              if (mcycle[0] && tstate[2] && wait_n == 1'b1 ) 
-                begin
-                  m1_n <= #1 1'b1;
-                end
-              if (BusReq_s == 1'b1 && BusAck == 1'b1 ) 
-                begin
-                end 
-              else 
-                begin
-                  BusAck <= #1 1'b0;
-                  if (tstate[2] && wait_n == 1'b0 ) 
-                    begin
-                    end 
-                  else if (T_Res == 1'b1 ) 
-                    begin
-                      if (Halt == 1'b1 ) 
-                        begin
-                          Halt_FF <= #1 1'b1;
-                        end
-                      if (BusReq_s == 1'b1 ) 
-                        begin
-                          BusAck <= #1 1'b1;
-                        end 
-                      else 
-                        begin
-                          tstate <= #1 7'b0000010;
-                          if (NextIs_XY_Fetch == 1'b1 ) 
-                            begin
-                              mcycle <= #1 7'b0100000;
-                              Pre_XY_F_M <= #1 mcycle;
-                              if (IR == 8'b00110110 && Mode == 0 ) 
-                                begin
-                                  Pre_XY_F_M <= #1 3'b010;
-                                end
-                            end 
-                          else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) ) 
-                            begin
-                              mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1);
-                            end 
-                          else if ((last_mcycle) ||
-                                   No_BTR == 1'b1 ||
-                                   (mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) ) 
-                            begin
-                              m1_n <= #1 1'b0;
-                              mcycle <= #1 7'b0000001;
-                              IntCycle <= #1 1'b0;
-                              NMICycle <= #1 1'b0;
-                              if (NMI_s == 1'b1 && Prefix == 2'b00 ) 
-                                begin
-                                  NMICycle <= #1 1'b1;
-                                  IntE_FF1 <= #1 1'b0;
-                                end 
-                              else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 ) 
-                                begin
-                                  IntCycle <= #1 1'b1;
-                                  IntE_FF1 <= #1 1'b0;
-                                  IntE_FF2 <= #1 1'b0;
-                                end
-                            end 
-                          else 
-                            begin
-                              mcycle <= #1 { mcycle[5:0], mcycle[6] };
-                            end
-                        end
-                    end 
-                  else 
-                    begin   // verilog has no "nor" operator
-                      if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) &&
-                           ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) ) 
-                        begin
-                          tstate <= #1 { tstate[5:0], tstate[6] };
-                        end
-                    end
-                end
-              if (tstate[0]) 
-                begin
-                  m1_n <= #1 1'b0;
-                end
-            end
-        end
-    end
-
-  always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
-           or RegBusA or RegBusC or SP or tstate)
-    begin
-      if (JumpE == 1'b1 ) 
-        begin
-          PC16_B = { {8{DI_Reg[7]}}, DI_Reg };
-        end 
-      else if (BTR_r == 1'b1 ) 
-        begin
-          PC16_B = -2;
-        end
-      else
-        begin
-          PC16_B = 1;
-        end
-
-      if (tstate[3])
-        begin
-          SP16_A = RegBusC;
-          SP16_B = { {8{DI_Reg[7]}}, DI_Reg };
-        end
-      else
-        begin
-          // suspect that ID16 and SP16 could be shared
-          SP16_A = SP;
-          
-          if (IncDec_16[3] == 1'b1)
-            SP16_B = -1;
-          else
-            SP16_B = 1;
-        end
-
-      if (IncDec_16[3])  
-        ID16_B = -1;
-      else
-        ID16_B = 1;
-
-      ID16 = RegBusA + ID16_B;
-      PC16 = PC + PC16_B;
-      SP16 = SP16_A + SP16_B;
-    end // always @ *
-  
-
-  always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle)
-    begin
-      Auto_Wait = 1'b0;
-      if (IntCycle == 1'b1 || NMICycle == 1'b1 ) 
-        begin
-          if (mcycle[0] ) 
-            begin
-              Auto_Wait = 1'b1;
-            end
-        end
-    end // always @ *
-  
-endmodule // T80
-
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_mcode.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_mcode.v
deleted file mode 100644
index 7d49cb51..00000000
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_mcode.v	
+++ /dev/null
@@ -1,2724 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-module tv80_mcode 
-  (/*AUTOARG*/
-   // Outputs
-   MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, 
-   Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, 
-   Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, 
-   LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, 
-   ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, 
-   I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, 
-   // Inputs
-   IR, ISet, MCycle, F, NMICycle, IntCycle
-   );
-  
-  parameter             Mode   = 0;
-  parameter             Flag_C = 0;
-  parameter             Flag_N = 1;
-  parameter             Flag_P = 2;
-  parameter             Flag_X = 3;
-  parameter             Flag_H = 4;
-  parameter             Flag_Y = 5;
-  parameter             Flag_Z = 6;
-  parameter             Flag_S = 7;
-
-  input [7:0]           IR;
-  input [1:0]           ISet                    ;
-  input [6:0]           MCycle                  ;
-  input [7:0]           F                       ;
-  input                 NMICycle                ;
-  input                 IntCycle                ;
-  output [2:0]          MCycles                 ;
-  output [2:0]          TStates                 ;
-  output [1:0]          Prefix                  ; // None,BC,ED,DD/FD
-  output                Inc_PC                  ;
-  output                Inc_WZ                  ;
-  output [3:0]          IncDec_16               ; // BC,DE,HL,SP   0 is inc
-  output                Read_To_Reg             ;
-  output                Read_To_Acc             ;
-  output [3:0]          Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-  output [3:0]          Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-  output [3:0]          ALU_Op                  ;
-  output                Save_ALU                ;
-  output                PreserveC               ;
-  output                Arith16                 ;
-  output [2:0]          Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-  output                IORQ                    ;
-  output                Jump                    ;
-  output                JumpE                   ;
-  output                JumpXY                  ;
-  output                Call                    ;
-  output                RstP                    ;
-  output                LDZ                     ;
-  output                LDW                     ;
-  output                LDSPHL                  ;
-  output [2:0]          Special_LD              ; // A,I;A,R;I,A;R,A;None
-  output                ExchangeDH              ;
-  output                ExchangeRp              ;
-  output                ExchangeAF              ;
-  output                ExchangeRS              ;
-  output                I_DJNZ                  ;
-  output                I_CPL                   ;
-  output                I_CCF                   ;
-  output                I_SCF                   ;
-  output                I_RETN                  ;
-  output                I_BT                    ;
-  output                I_BC                    ;
-  output                I_BTR                   ;
-  output                I_RLD                   ;
-  output                I_RRD                   ;
-  output                I_INRC                  ;
-  output                SetDI                   ;
-  output                SetEI                   ;
-  output [1:0]          IMode                   ;
-  output                Halt                    ;
-  output                NoRead                  ;
-  output                Write   ;                
-
-  // regs
-  reg [2:0]             MCycles                 ;
-  reg [2:0]             TStates                 ;
-  reg [1:0]             Prefix                  ; // None,BC,ED,DD/FD
-  reg                   Inc_PC                  ;
-  reg                   Inc_WZ                  ;
-  reg [3:0]             IncDec_16               ; // BC,DE,HL,SP   0 is inc
-  reg                   Read_To_Reg             ;
-  reg                   Read_To_Acc             ;
-  reg [3:0]             Set_BusA_To     ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-  reg [3:0]             Set_BusB_To     ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-  reg [3:0]             ALU_Op                  ;
-  reg                   Save_ALU                ;
-  reg                   PreserveC               ;
-  reg                   Arith16                 ;
-  reg [2:0]             Set_Addr_To             ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-  reg                   IORQ                    ;
-  reg                   Jump                    ;
-  reg                   JumpE                   ;
-  reg                   JumpXY                  ;
-  reg                   Call                    ;
-  reg                   RstP                    ;
-  reg                   LDZ                     ;
-  reg                   LDW                     ;
-  reg                   LDSPHL                  ;
-  reg [2:0]             Special_LD              ; // A,I;A,R;I,A;R,A;None
-  reg                   ExchangeDH              ;
-  reg                   ExchangeRp              ;
-  reg                   ExchangeAF              ;
-  reg                   ExchangeRS              ;
-  reg                   I_DJNZ                  ;
-  reg                   I_CPL                   ;
-  reg                   I_CCF                   ;
-  reg                   I_SCF                   ;
-  reg                   I_RETN                  ;
-  reg                   I_BT                    ;
-  reg                   I_BC                    ;
-  reg                   I_BTR                   ;
-  reg                   I_RLD                   ;
-  reg                   I_RRD                   ;
-  reg                   I_INRC                  ;
-  reg                   SetDI                   ;
-  reg                   SetEI                   ;
-  reg [1:0]             IMode                   ;
-  reg                   Halt                    ;
-  reg                   NoRead                  ;
-  reg                   Write   ;                
-
-  parameter             aNone   = 3'b111;
-  parameter             aBC     = 3'b000;
-  parameter             aDE     = 3'b001;
-  parameter             aXY     = 3'b010;
-  parameter             aIOA    = 3'b100;
-  parameter             aSP     = 3'b101;
-  parameter             aZI     = 3'b110;
-  //    constant aNone  : std_logic_vector[2:0] = 3'b000;
-  //    constant aXY    : std_logic_vector[2:0] = 3'b001;
-  //    constant aIOA   : std_logic_vector[2:0] = 3'b010;
-  //    constant aSP    : std_logic_vector[2:0] = 3'b011;
-  //    constant aBC    : std_logic_vector[2:0] = 3'b100;
-  //    constant aDE    : std_logic_vector[2:0] = 3'b101;
-  //    constant aZI    : std_logic_vector[2:0] = 3'b110;
-
-  function is_cc_true;
-    input [7:0] F;
-    input [2:0] cc;
-    begin
-      if (Mode == 3 ) 
-        begin
-          case (cc)
-            3'b000  : is_cc_true = F[7] == 1'b0; // NZ
-            3'b001  : is_cc_true = F[7] == 1'b1; // Z
-            3'b010  : is_cc_true = F[4] == 1'b0; // NC
-            3'b011  : is_cc_true = F[4] == 1'b1; // C
-            3'b100  : is_cc_true = 0;
-            3'b101  : is_cc_true = 0;
-            3'b110  : is_cc_true = 0;
-            3'b111  : is_cc_true = 0;
-          endcase
-        end 
-      else 
-        begin
-          case (cc)
-            3'b000  : is_cc_true = F[6] == 1'b0; // NZ
-            3'b001  : is_cc_true = F[6] == 1'b1; // Z
-            3'b010  : is_cc_true = F[0] == 1'b0; // NC
-            3'b011  : is_cc_true = F[0] == 1'b1; // C
-            3'b100  : is_cc_true = F[2] == 1'b0; // PO
-            3'b101  : is_cc_true = F[2] == 1'b1; // PE
-            3'b110  : is_cc_true = F[7] == 1'b0; // P
-            3'b111  : is_cc_true = F[7] == 1'b1; // M
-          endcase
-        end
-    end
-  endfunction // is_cc_true
-  
-
-  reg [2:0] DDD;
-  reg [2:0] SSS;
-  reg [1:0] DPAIR;
-  reg [7:0] IRB;
-  
-  always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle
-            or NMICycle)
-    begin
-      DDD = IR[5:3];
-      SSS = IR[2:0];
-      DPAIR = IR[5:4];
-      IRB = IR;
-
-      MCycles = 3'b001;
-      if (MCycle[0] ) 
-        begin
-          TStates = 3'b100;
-        end 
-      else 
-        begin
-          TStates = 3'b011;
-        end
-      Prefix = 2'b00;
-      Inc_PC = 1'b0;
-      Inc_WZ = 1'b0;
-      IncDec_16 = 4'b0000;
-      Read_To_Acc = 1'b0;
-      Read_To_Reg = 1'b0;
-      Set_BusB_To = 4'b0000;
-      Set_BusA_To = 4'b0000;
-      ALU_Op = { 1'b0, IR[5:3] };
-      Save_ALU = 1'b0;
-      PreserveC = 1'b0;
-      Arith16 = 1'b0;
-      IORQ = 1'b0;
-      Set_Addr_To = aNone;
-      Jump = 1'b0;
-      JumpE = 1'b0;
-      JumpXY = 1'b0;
-      Call = 1'b0;
-      RstP = 1'b0;
-      LDZ = 1'b0;
-      LDW = 1'b0;
-      LDSPHL = 1'b0;
-      Special_LD = 3'b000;
-      ExchangeDH = 1'b0;
-      ExchangeRp = 1'b0;
-      ExchangeAF = 1'b0;
-      ExchangeRS = 1'b0;
-      I_DJNZ = 1'b0;
-      I_CPL = 1'b0;
-      I_CCF = 1'b0;
-      I_SCF = 1'b0;
-      I_RETN = 1'b0;
-      I_BT = 1'b0;
-      I_BC = 1'b0;
-      I_BTR = 1'b0;
-      I_RLD = 1'b0;
-      I_RRD = 1'b0;
-      I_INRC = 1'b0;
-      SetDI = 1'b0;
-      SetEI = 1'b0;
-      IMode = 2'b11;
-      Halt = 1'b0;
-      NoRead = 1'b0;
-      Write = 1'b0;
-      
-      case (ISet)
-        2'b00  :
-          begin
-
-            //----------------------------------------------------------------------------
-            //
-            //  Unprefixed instructions
-            //
-            //----------------------------------------------------------------------------
-
-            casex (IRB)
-              // 8 BIT LOAD GROUP
-              8'b01xxxxxx :
-                begin
-                  if (IRB[5:0] == 6'b110110)
-                    Halt = 1'b1;
-                  else if (IRB[2:0] == 3'b110)
-                    begin
-                      // LD r,(HL)
-                      MCycles = 3'b010;
-                      if (MCycle[0])
-                        Set_Addr_To = aXY;
-                      if (MCycle[1])
-                        begin
-                          Set_BusA_To[2:0] = DDD;
-                          Read_To_Reg = 1'b1;
-                        end
-                    end // if (IRB[2:0] == 3'b110)
-                  else if (IRB[5:3] == 3'b110)
-                    begin
-                      // LD (HL),r
-                      MCycles = 3'b010;
-                      if (MCycle[0])
-                        begin
-                          Set_Addr_To = aXY;
-                          Set_BusB_To[2:0] = SSS;
-                          Set_BusB_To[3] = 1'b0;
-                        end
-                      if (MCycle[1])
-                        Write = 1'b1;
-                    end // if (IRB[5:3] == 3'b110)
-                  else
-                    begin
-                      Set_BusB_To[2:0] = SSS;
-                      ExchangeRp = 1'b1;
-                      Set_BusA_To[2:0] = DDD;
-                      Read_To_Reg = 1'b1;
-                    end // else: !if(IRB[5:3] == 3'b110)
-                end // case: 8'b01xxxxxx                                    
-
-              8'b00xxx110 :
-                begin
-                  if (IRB[5:3] == 3'b110)
-                    begin
-                      // LD (HL),n
-                      MCycles = 3'b011;
-                      if (MCycle[1])
-                        begin
-                          Inc_PC = 1'b1;
-                          Set_Addr_To = aXY;
-                          Set_BusB_To[2:0] = SSS;
-                          Set_BusB_To[3] = 1'b0;
-                        end
-                      if (MCycle[2])
-                        Write = 1'b1;
-                    end // if (IRB[5:3] == 3'b110)
-                  else
-                    begin
-                      // LD r,n
-                      MCycles = 3'b010;
-                      if (MCycle[1])
-                        begin
-                          Inc_PC = 1'b1;
-                          Set_BusA_To[2:0] = DDD;
-                          Read_To_Reg = 1'b1;
-                        end
-                    end
-                end
-              
-              8'b00001010  :
-                begin
-                  // LD A,(BC)
-                  MCycles = 3'b010;
-                  if (MCycle[0])
-                    Set_Addr_To = aBC;
-                  if (MCycle[1])
-                    Read_To_Acc = 1'b1;
-                end // case: 8'b00001010
-              
-              8'b00011010  :
-                begin
-                  // LD A,(DE)
-                  MCycles = 3'b010;
-                  if (MCycle[0])
-                    Set_Addr_To = aDE;
-                  if (MCycle[1])
-                    Read_To_Acc = 1'b1;
-                end // case: 8'b00011010
-              
-              8'b00111010  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LDD A,(HL)
-                      MCycles = 3'b010;
-                      if (MCycle[0])
-                        Set_Addr_To = aXY;
-                      if (MCycle[1])
-                        begin
-                          Read_To_Acc = 1'b1;
-                          IncDec_16 = 4'b1110;
-                        end
-                    end 
-                  else 
-                    begin
-                      // LD A,(nn)
-                      MCycles = 3'b100;
-                      if (MCycle[1])
-                        begin
-                          Inc_PC = 1'b1;
-                          LDZ = 1'b1;
-                        end
-                      if (MCycle[2])
-                        begin
-                          Set_Addr_To = aZI;
-                          Inc_PC = 1'b1;
-                        end
-                      if (MCycle[3])
-                        begin
-                          Read_To_Acc = 1'b1;
-                        end
-                    end // else: !if(Mode == 3 )
-                end // case: 8'b00111010
-              
-              8'b00000010  :
-                begin
-                  // LD (BC),A
-                  MCycles = 3'b010;
-                  if (MCycle[0])
-                    begin
-                      Set_Addr_To = aBC;
-                      Set_BusB_To = 4'b0111;
-                    end
-                  if (MCycle[1])
-                    begin
-                      Write = 1'b1;
-                    end
-                end // case: 8'b00000010
-              
-              8'b00010010  :
-                begin
-                  // LD (DE),A
-                  MCycles = 3'b010;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aDE;
-                        Set_BusB_To = 4'b0111;
-                      end
-                    MCycle[1] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b00010010
-              
-              8'b00110010  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LDD (HL),A
-                      MCycles = 3'b010;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            Set_Addr_To = aXY;
-                            Set_BusB_To = 4'b0111;
-                          end
-                        MCycle[1] :
-                          begin
-                            Write = 1'b1;
-                            IncDec_16 = 4'b1110;
-                          end
-                        default :;
-                      endcase // case(MCycle)
-                      
-                    end 
-                  else 
-                    begin
-                      // LD (nn),A
-                      MCycles = 3'b100;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Set_Addr_To = aZI;
-                            Inc_PC = 1'b1;
-                            Set_BusB_To = 4'b0111;
-                          end
-                        MCycle[3] :
-                          begin
-                            Write = 1'b1;
-                          end
-                        default :;
-                      endcase
-                    end // else: !if(Mode == 3 )
-                end // case: 8'b00110010
-              
-
-              // 16 BIT LOAD GROUP
-              8'b00000001,8'b00010001,8'b00100001,8'b00110001  :
-                begin
-                  // LD dd,nn
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        Inc_PC = 1'b1;
-                        Read_To_Reg = 1'b1;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusA_To[3:0] = 4'b1000;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = DPAIR;
-                            Set_BusA_To[0] = 1'b1;
-                          end
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        Inc_PC = 1'b1;
-                        Read_To_Reg = 1'b1;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusA_To[3:0] = 4'b1001;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = DPAIR;
-                            Set_BusA_To[0] = 1'b0;
-                          end
-                      end // case: 3
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001
-              
-              8'b00101010  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LDI A,(HL)
-                      MCycles = 3'b010;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aXY;
-                        MCycle[1] :
-                          begin
-                            Read_To_Acc = 1'b1;
-                            IncDec_16 = 4'b0110;
-                          end
-                        
-                        default :;
-                      endcase
-                    end 
-                  else 
-                    begin
-                      // LD HL,(nn)
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Set_Addr_To = aZI;
-                            Inc_PC = 1'b1;
-                            LDW = 1'b1;
-                          end
-                        MCycle[3] :
-                          begin
-                            Set_BusA_To[2:0] = 3'b101; // L
-                            Read_To_Reg = 1'b1;
-                            Inc_WZ = 1'b1;
-                            Set_Addr_To = aZI;
-                          end
-                        MCycle[4] :
-                          begin
-                            Set_BusA_To[2:0] = 3'b100; // H
-                            Read_To_Reg = 1'b1;
-                          end
-                        default :;
-                      endcase
-                    end // else: !if(Mode == 3 )
-                end // case: 8'b00101010
-              
-              8'b00100010  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LDI (HL),A
-                      MCycles = 3'b010;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            Set_Addr_To = aXY;
-                            Set_BusB_To = 4'b0111;
-                          end
-                        MCycle[1] :
-                          begin
-                            Write = 1'b1;
-                            IncDec_16 = 4'b0110;
-                          end
-                        default :;
-                      endcase
-                    end 
-                  else 
-                    begin
-                      // LD (nn),HL
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle                        
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Set_Addr_To = aZI;
-                            Inc_PC = 1'b1;
-                            LDW = 1'b1;
-                            Set_BusB_To = 4'b0101; // L
-                          end
-                        
-                        MCycle[3] :
-                          begin
-                            Inc_WZ = 1'b1;
-                            Set_Addr_To = aZI;
-                            Write = 1'b1;
-                            Set_BusB_To = 4'b0100; // H
-                          end
-                        MCycle[4] :                          
-                          Write = 1'b1;
-                        default :;
-                      endcase
-                    end // else: !if(Mode == 3 )
-                end // case: 8'b00100010
-              
-              8'b11111001  :
-                begin
-                  // LD SP,HL
-                  TStates = 3'b110;
-                  LDSPHL = 1'b1;
-                end
-              
-              8'b11xx0101 :
-                begin
-                  // PUSH qq
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle                    
-                    MCycle[0] :
-                      begin
-                        TStates = 3'b101;
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusB_To = 4'b0111;
-                          end 
-                        else
-                          begin
-                            Set_BusB_To[2:1] = DPAIR;
-                            Set_BusB_To[0] = 1'b0;
-                            Set_BusB_To[3] = 1'b0;
-                          end
-                      end // case: 1
-                    
-                    MCycle[1] :
-                      begin
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusB_To = 4'b1011;
-                          end 
-                        else 
-                          begin
-                            Set_BusB_To[2:1] = DPAIR;
-                            Set_BusB_To[0] = 1'b1;
-                            Set_BusB_To[3] = 1'b0;
-                          end
-                        Write = 1'b1;
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
-              
-              8'b11xx0001 :
-                begin
-                  // POP qq
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      Set_Addr_To = aSP;
-                    MCycle[1] :
-                      begin
-                        IncDec_16 = 4'b0111;
-                        Set_Addr_To = aSP;
-                        Read_To_Reg = 1'b1;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusA_To[3:0] = 4'b1011;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = DPAIR;
-                            Set_BusA_To[0] = 1'b1;
-                          end
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        IncDec_16 = 4'b0111;
-                        Read_To_Reg = 1'b1;
-                        if (DPAIR == 2'b11 ) 
-                          begin
-                            Set_BusA_To[3:0] = 4'b0111;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = DPAIR;
-                            Set_BusA_To[0] = 1'b0;
-                          end
-                      end // case: 3
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001
-              
-
-              // EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-              8'b11101011  :
-                begin
-                  if (Mode != 3 ) 
-                    begin
-                      // EX DE,HL
-                      ExchangeDH = 1'b1;
-                    end
-                end
-              
-              8'b00001000  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // LD (nn),SP
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Set_Addr_To = aZI;
-                            Inc_PC = 1'b1;
-                            LDW = 1'b1;
-                            Set_BusB_To = 4'b1000;
-                          end
-                        
-                        MCycle[3] :
-                          begin
-                            Inc_WZ = 1'b1;
-                            Set_Addr_To = aZI;
-                            Write = 1'b1;
-                            Set_BusB_To = 4'b1001;
-                          end
-                        
-                        MCycle[4] :
-                          Write = 1'b1;
-                        default :;
-                      endcase
-                    end 
-                  else if (Mode < 2 ) 
-                    begin
-                      // EX AF,AF'
-                      ExchangeAF = 1'b1;
-                    end
-                end // case: 8'b00001000
-              
-              8'b11011001  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      // RETI
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aSP;
-                        MCycle[1] :
-                          begin
-                            IncDec_16 = 4'b0111;
-                            Set_Addr_To = aSP;
-                            LDZ = 1'b1;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Jump = 1'b1;
-                            IncDec_16 = 4'b0111;
-                            I_RETN = 1'b1;
-                            SetEI = 1'b1;
-                          end
-                        default :;
-                      endcase
-                    end 
-                  else if (Mode < 2 ) 
-                    begin
-                      // EXX
-                      ExchangeRS = 1'b1;
-                    end
-                end // case: 8'b11011001
-              
-              8'b11100011  :
-                begin
-                  if (Mode != 3 ) 
-                    begin
-                      // EX (SP),HL
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aSP;
-                        MCycle[1] :
-                          begin
-                            Read_To_Reg = 1'b1;
-                            Set_BusA_To = 4'b0101;
-                            Set_BusB_To = 4'b0101;
-                            Set_Addr_To = aSP;
-                          end
-                        MCycle[2] :
-                          begin
-                            IncDec_16 = 4'b0111;
-                            Set_Addr_To = aSP;
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                          end
-                        MCycle[3] :
-                          begin
-                            Read_To_Reg = 1'b1;
-                            Set_BusA_To = 4'b0100;
-                            Set_BusB_To = 4'b0100;
-                            Set_Addr_To = aSP;
-                          end
-                        MCycle[4] :
-                          begin
-                            IncDec_16 = 4'b1111;
-                            TStates = 3'b101;
-                            Write = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase
-                    end // if (Mode != 3 )
-                end // case: 8'b11100011
-              
-
-              // 8 BIT ARITHMETIC AND LOGICAL GROUP
-              8'b10xxxxxx :
-                begin
-                  if (IR[2:0] == 3'b110)
-                    begin
-                      // ADD A,(HL)
-                      // ADC A,(HL)
-                      // SUB A,(HL)
-                      // SBC A,(HL)
-                      // AND A,(HL)
-                      // OR A,(HL)
-                      // XOR A,(HL)
-                      // CP A,(HL)
-                      MCycles = 3'b010;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aXY;
-                        MCycle[1] :
-                          begin
-                            Read_To_Reg = 1'b1;
-                            Save_ALU = 1'b1;
-                            Set_BusB_To[2:0] = SSS;
-                            Set_BusA_To[2:0] = 3'b111;
-                          end
-                        
-                        default :;
-                      endcase // case(MCycle)
-                    end // if (IR[2:0] == 3'b110)
-                  else
-                    begin
-                      // ADD A,r
-                      // ADC A,r
-                      // SUB A,r
-                      // SBC A,r
-                      // AND A,r
-                      // OR A,r
-                      // XOR A,r
-                      // CP A,r
-                      Set_BusB_To[2:0] = SSS;
-                      Set_BusA_To[2:0] = 3'b111;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                    end // else: !if(IR[2:0] == 3'b110)                  
-                end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
-              
-              8'b11xxx110 :
-                begin
-                  // ADD A,n
-                  // ADC A,n
-                  // SUB A,n
-                  // SBC A,n
-                  // AND A,n
-                  // OR A,n
-                  // XOR A,n
-                  // CP A,n
-                  MCycles = 3'b010;
-                  if (MCycle[1] ) 
-                    begin
-                      Inc_PC = 1'b1;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                      Set_BusB_To[2:0] = SSS;
-                      Set_BusA_To[2:0] = 3'b111;
-                    end
-                end
-              
-              8'b00xxx100 :
-                begin
-                  if (IRB[5:3] == 3'b110)
-                    begin
-                      // INC (HL)
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aXY;
-                        MCycle[1] :
-                          begin
-                            TStates = 3'b100;
-                            Set_Addr_To = aXY;
-                            Read_To_Reg = 1'b1;
-                            Save_ALU = 1'b1;
-                            PreserveC = 1'b1;
-                            ALU_Op = 4'b0000;
-                            Set_BusB_To = 4'b1010;
-                            Set_BusA_To[2:0] = DDD;
-                          end // case: 2
-                        
-                        MCycle[2] :
-                          Write = 1'b1;
-                        default :;
-                      endcase // case(MCycle)
-                    end // case: 8'b00110100
-                  else
-                    begin
-                      // INC r
-                      Set_BusB_To = 4'b1010;
-                      Set_BusA_To[2:0] = DDD;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                      PreserveC = 1'b1;
-                      ALU_Op = 4'b0000;
-                    end
-                end
-              
-              8'b00xxx101 :
-                begin               
-                  if (IRB[5:3] == 3'b110)
-                    begin
-                      // DEC (HL)
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          Set_Addr_To = aXY;
-                        MCycle[1] :
-                          begin
-                            TStates = 3'b100;
-                            Set_Addr_To = aXY;
-                            ALU_Op = 4'b0010;
-                            Read_To_Reg = 1'b1;
-                            Save_ALU = 1'b1;
-                            PreserveC = 1'b1;
-                            Set_BusB_To = 4'b1010;
-                            Set_BusA_To[2:0] = DDD;
-                          end // case: 2
-                        
-                        MCycle[2] :
-                          Write = 1'b1;
-                        default :;
-                      endcase // case(MCycle)
-                    end
-                  else
-                    begin
-                      // DEC r
-                      Set_BusB_To = 4'b1010;
-                      Set_BusA_To[2:0] = DDD;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                      PreserveC = 1'b1;
-                      ALU_Op = 4'b0010;
-                    end
-                end
-              
-              // GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-              8'b00100111  :
-                begin
-                  // DAA
-                  Set_BusA_To[2:0] = 3'b111;
-                  Read_To_Reg = 1'b1;
-                  ALU_Op = 4'b1100;
-                  Save_ALU = 1'b1;
-                end
-              
-              8'b00101111  :
-                // CPL
-                I_CPL = 1'b1;
-              
-              8'b00111111  :
-                // CCF
-                I_CCF = 1'b1;
-              
-              8'b00110111  :
-                // SCF
-                I_SCF = 1'b1;
-              
-              8'b00000000  :
-                begin
-                  if (NMICycle == 1'b1 ) 
-                    begin
-                      // NMI
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            TStates = 3'b101;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1101;
-                          end
-                        
-                        MCycle[1] :
-                          begin
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1100;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase // case(MCycle)
-                      
-                    end 
-                  else if (IntCycle == 1'b1 ) 
-                    begin
-                      // INT (IM 2)
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            LDZ = 1'b1;
-                            TStates = 3'b101;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1101;
-                          end
-                        
-                        MCycle[1] :
-                          begin
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1100;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            TStates = 3'b100;
-                            Write = 1'b1;
-                          end
-                        
-                        MCycle[3] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        
-                        MCycle[4] :
-                          Jump = 1'b1;
-                        default :;
-                      endcase
-                    end
-                end // case: 8'b00000000
-              
-              8'b11110011  :
-                // DI
-                SetDI = 1'b1;
-              
-              8'b11111011  :
-                // EI
-                SetEI = 1'b1;
-
-              // 16 BIT ARITHMETIC GROUP
-              8'b00001001,8'b00011001,8'b00101001,8'b00111001  :
-                begin
-                  // ADD HL,ss
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        NoRead = 1'b1;
-                        ALU_Op = 4'b0000;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_BusA_To[2:0] = 3'b101;
-                        case (IR[5:4])
-                          0,1,2  :
-                            begin
-                              Set_BusB_To[2:1] = IR[5:4];
-                              Set_BusB_To[0] = 1'b1;
-                            end
-                          
-                          default :
-                            Set_BusB_To = 4'b1000;
-                        endcase // case(IR[5:4])
-                        
-                        TStates = 3'b100;
-                        Arith16 = 1'b1;
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        NoRead = 1'b1;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        ALU_Op = 4'b0001;
-                        Set_BusA_To[2:0] = 3'b100;
-                        case (IR[5:4])
-                          0,1,2  :
-                            Set_BusB_To[2:1] = IR[5:4];
-                          default :
-                            Set_BusB_To = 4'b1001;
-                        endcase
-                        Arith16 = 1'b1;
-                      end // case: 3
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001              
-              
-              8'b00000011,8'b00010011,8'b00100011,8'b00110011  :
-                begin
-                  // INC ss
-                  TStates = 3'b110;
-                  IncDec_16[3:2] = 2'b01;
-                  IncDec_16[1:0] = DPAIR;
-                end
-              
-              8'b00001011,8'b00011011,8'b00101011,8'b00111011  :
-                begin
-                  // DEC ss
-                  TStates = 3'b110;
-                  IncDec_16[3:2] = 2'b11;
-                  IncDec_16[1:0] = DPAIR;
-                end
-
-              // ROTATE AND SHIFT GROUP
-              8'b00000111,
-                  // RLCA
-                  8'b00010111,
-                  // RLA
-                  8'b00001111,
-                  // RRCA
-                  8'b00011111 :
-                    // RRA
-                    begin
-                      Set_BusA_To[2:0] = 3'b111;
-                      ALU_Op = 4'b1000;
-                      Read_To_Reg = 1'b1;
-                      Save_ALU = 1'b1;
-                    end // case: 8'b00000111,...
-              
-
-              // JUMP GROUP
-              8'b11000011  :
-                begin
-                  // JP nn
-                  MCycles = 3'b011;
-                  if (MCycle[1])
-                    begin
-                      Inc_PC = 1'b1;
-                      LDZ = 1'b1;
-                    end
-                  
-                  if (MCycle[2])
-                    begin
-                      Inc_PC = 1'b1;
-                      Jump = 1'b1;
-                    end
-                  
-                end // case: 8'b11000011
-              
-              8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010  :
-                begin
-                  if (IR[5] == 1'b1 && Mode == 3 ) 
-                    begin
-                      case (IRB[4:3])
-                        2'b00  :
-                          begin
-                            // LD ($FF00+C),A
-                            MCycles = 3'b010;
-                            case (1'b1) // MCycle
-                              MCycle[0] :
-                                begin
-                                  Set_Addr_To = aBC;
-                                  Set_BusB_To   = 4'b0111;
-                                end
-                              MCycle[1] :
-                                begin
-                                  Write = 1'b1;
-                                  IORQ = 1'b1;
-                                end
-                              
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b00
-                        
-                        2'b01  :
-                          begin
-                            // LD (nn),A
-                            MCycles = 3'b100;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  LDZ = 1'b1;
-                                end
-                              
-                              MCycle[2] :
-                                begin
-                                  Set_Addr_To = aZI;
-                                  Inc_PC = 1'b1;
-                                  Set_BusB_To = 4'b0111;
-                                end
-                              
-                              MCycle[3] :
-                                Write = 1'b1;
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: default :...
-                        
-                        2'b10  :
-                          begin
-                            // LD A,($FF00+C)
-                            MCycles = 3'b010;
-                            case (1'b1) // MCycle
-                              MCycle[0] :
-                                Set_Addr_To = aBC;
-                              MCycle[1] :
-                                begin
-                                  Read_To_Acc = 1'b1;
-                                  IORQ = 1'b1;
-                                end
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b10
-                        
-                        2'b11  :
-                          begin
-                            // LD A,(nn)
-                            MCycles = 3'b100;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  LDZ = 1'b1;
-                                end
-                              MCycle[2] :
-                                begin
-                                  Set_Addr_To = aZI;
-                                  Inc_PC = 1'b1;
-                                end
-                              MCycle[3] :
-                                Read_To_Acc = 1'b1;
-                              default :;
-                            endcase // case(MCycle)
-                          end
-                      endcase
-                    end 
-                  else 
-                    begin
-                      // JP cc,nn
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Inc_PC = 1'b1;
-                            if (is_cc_true(F, IR[5:3]) ) 
-                              begin
-                                Jump = 1'b1;
-                              end
-                          end
-                        
-                        default :;
-                      endcase
-                    end // else: !if(DPAIR == 2'b11 )
-                end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010
-              
-              8'b00011000  :
-                begin
-                  if (Mode != 2 ) 
-                    begin
-                      // JR e
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          Inc_PC = 1'b1;
-                        MCycle[2] :
-                          begin
-                            NoRead = 1'b1;
-                            JumpE = 1'b1;
-                            TStates = 3'b101;
-                          end
-                        default :;
-                      endcase
-                    end // if (Mode != 2 )
-                end // case: 8'b00011000
-              
-              8'b00111000  :
-                begin
-                  if (Mode != 2 ) 
-                    begin
-                      // JR C,e
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            if (F[Flag_C] == 1'b0 ) 
-                              begin
-                                MCycles = 3'b010;
-                              end
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            NoRead = 1'b1;
-                            JumpE = 1'b1;
-                            TStates = 3'b101;
-                          end
-                        default :;
-                      endcase
-                    end // if (Mode != 2 )
-                end // case: 8'b00111000
-              
-              8'b00110000  :
-                begin
-                  if (Mode != 2 ) 
-                    begin
-                      // JR NC,e
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            if (F[Flag_C] == 1'b1 ) 
-                              begin
-                                MCycles = 3'b010;
-                              end
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            NoRead = 1'b1;
-                            JumpE = 1'b1;
-                            TStates = 3'b101;
-                          end
-                        default :;
-                      endcase
-                    end // if (Mode != 2 )
-                end // case: 8'b00110000
-              
-              8'b00101000  :
-                begin
-                  if (Mode != 2 ) 
-                    begin
-                      // JR Z,e
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            if (F[Flag_Z] == 1'b0 ) 
-                              begin
-                                MCycles = 3'b010;
-                              end
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            NoRead = 1'b1;
-                            JumpE = 1'b1;
-                            TStates = 3'b101;
-                          end
-                        
-                        default :;
-                      endcase
-                    end // if (Mode != 2 )
-                end // case: 8'b00101000
-              
-              8'b00100000  :
-                begin
-                  if (Mode != 2 ) 
-                    begin
-                      // JR NZ,e
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            if (F[Flag_Z] == 1'b1 ) 
-                              begin
-                                MCycles = 3'b010;
-                              end
-                          end
-                        MCycle[2] :
-                          begin                            
-                            NoRead = 1'b1;
-                            JumpE = 1'b1;
-                            TStates = 3'b101;
-                          end
-                        default :;
-                      endcase
-                    end // if (Mode != 2 )
-                end // case: 8'b00100000
-              
-              8'b11101001  :
-                // JP (HL)
-                JumpXY = 1'b1;
-              
-              8'b00010000  :
-                begin
-                  if (Mode == 3 ) 
-                    begin
-                      I_DJNZ = 1'b1;
-                    end 
-                  else if (Mode < 2 ) 
-                    begin
-                      // DJNZ,e
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            TStates = 3'b101;
-                            I_DJNZ = 1'b1;
-                            Set_BusB_To = 4'b1010;
-                            Set_BusA_To[2:0] = 3'b000;
-                            Read_To_Reg = 1'b1;
-                            Save_ALU = 1'b1;
-                            ALU_Op = 4'b0010;
-                          end
-                        MCycle[1] :
-                          begin
-                            I_DJNZ = 1'b1;
-                            Inc_PC = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            NoRead = 1'b1;
-                            JumpE = 1'b1;
-                            TStates = 3'b101;
-                          end
-                        default :;
-                      endcase
-                    end // if (Mode < 2 )
-                end // case: 8'b00010000
-              
-
-              // CALL AND RETURN GROUP
-              8'b11001101  :
-                begin
-                  // CALL nn
-                  MCycles = 3'b101;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        Inc_PC = 1'b1;
-                        LDZ = 1'b1;
-                      end
-                    MCycle[2] :
-                      begin
-                        IncDec_16 = 4'b1111;
-                        Inc_PC = 1'b1;
-                        TStates = 3'b100;
-                        Set_Addr_To = aSP;
-                        LDW = 1'b1;
-                        Set_BusB_To = 4'b1101;
-                      end
-                    MCycle[3] :
-                      begin
-                        Write = 1'b1;
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        Set_BusB_To = 4'b1100;
-                      end
-                    MCycle[4] :
-                      begin
-                        Write = 1'b1;
-                        Call = 1'b1;
-                      end
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11001101
-              
-              8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100  :
-                begin
-                  if (IR[5] == 1'b0 || Mode != 3 ) 
-                    begin
-                      // CALL cc,nn
-                      MCycles = 3'b101;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Inc_PC = 1'b1;
-                            LDW = 1'b1;
-                            if (is_cc_true(F, IR[5:3]) ) 
-                              begin
-                                IncDec_16 = 4'b1111;
-                                Set_Addr_To = aSP;
-                                TStates = 3'b100;
-                                Set_BusB_To = 4'b1101;
-                              end 
-                            else 
-                              begin
-                                MCycles = 3'b011;
-                              end // else: !if(is_cc_true(F, IR[5:3]) )
-                          end // case: 3
-                        
-                        MCycle[3] :
-                          begin
-                            Write = 1'b1;
-                            IncDec_16 = 4'b1111;
-                            Set_Addr_To = aSP;
-                            Set_BusB_To = 4'b1100;
-                          end
-                        
-                        MCycle[4] :
-                          begin
-                            Write = 1'b1;
-                            Call = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase
-                    end // if (IR[5] == 1'b0 || Mode != 3 )
-                end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100
-              
-              8'b11001001  :
-                begin
-                  // RET
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        TStates = 3'b101;
-                        Set_Addr_To = aSP;
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        IncDec_16 = 4'b0111;
-                        Set_Addr_To = aSP;
-                        LDZ = 1'b1;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Jump = 1'b1;
-                        IncDec_16 = 4'b0111;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11001001
-              
-              8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000  :
-                begin                  
-                  if (IR[5] == 1'b1 && Mode == 3 ) 
-                    begin
-                      case (IRB[4:3])
-                        2'b00  :
-                          begin
-                            // LD ($FF00+nn),A
-                            MCycles = 3'b011;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  Set_Addr_To = aIOA;
-                                  Set_BusB_To   = 4'b0111;
-                                end
-                              
-                              MCycle[2] :
-                                Write = 1'b1;
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b00
-                        
-                        2'b01  :
-                          begin
-                            // ADD SP,n
-                            MCycles = 3'b011;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  ALU_Op = 4'b0000;
-                                  Inc_PC = 1'b1;
-                                  Read_To_Reg = 1'b1;
-                                  Save_ALU = 1'b1;
-                                  Set_BusA_To = 4'b1000;
-                                  Set_BusB_To = 4'b0110;
-                                end
-                              
-                              MCycle[2] :
-                                begin
-                                  NoRead = 1'b1;
-                                  Read_To_Reg = 1'b1;
-                                  Save_ALU = 1'b1;
-                                  ALU_Op = 4'b0001;
-                                  Set_BusA_To = 4'b1001;
-                                  Set_BusB_To = 4'b1110;        // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-                                end
-                              
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b01
-                        
-                        2'b10  :
-                          begin
-                            // LD A,($FF00+nn)
-                            MCycles = 3'b011;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  Set_Addr_To = aIOA;
-                                end
-                              
-                              MCycle[2] :
-                                Read_To_Acc = 1'b1;
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b10
-                        
-                        2'b11  :
-                          begin
-                            // LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-                            MCycles = 3'b101;
-                            case (1'b1) // MCycle
-                              MCycle[1] :
-                                begin
-                                  Inc_PC = 1'b1;
-                                  LDZ = 1'b1;
-                                end
-                              
-                              MCycle[2] :
-                                begin
-                                  Set_Addr_To = aZI;
-                                  Inc_PC = 1'b1;
-                                  LDW = 1'b1;
-                                end
-                              
-                              MCycle[3] :
-                                begin
-                                  Set_BusA_To[2:0] = 3'b101; // L
-                                  Read_To_Reg = 1'b1;
-                                  Inc_WZ = 1'b1;
-                                  Set_Addr_To = aZI;
-                                end
-                              
-                              MCycle[4] :
-                                begin
-                                  Set_BusA_To[2:0] = 3'b100; // H
-                                  Read_To_Reg = 1'b1;
-                                end
-                              
-                              default :;
-                            endcase // case(MCycle)
-                          end // case: 2'b11
-                        
-                      endcase // case(IRB[4:3])
-                      
-                    end 
-                  else 
-                    begin
-                      // RET cc
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[0] :
-                          begin
-                            if (is_cc_true(F, IR[5:3]) )                              
-                              begin
-                                Set_Addr_To = aSP;
-                              end 
-                            else 
-                              begin
-                                MCycles = 3'b001;
-                              end
-                            TStates = 3'b101;
-                          end // case: 1
-                        
-                        MCycle[1] :
-                          begin
-                            IncDec_16 = 4'b0111;
-                            Set_Addr_To = aSP;
-                            LDZ = 1'b1;
-                          end
-                        MCycle[2] :
-                          begin
-                            Jump = 1'b1;
-                            IncDec_16 = 4'b0111;
-                          end
-                        default :;
-                      endcase
-                    end // else: !if(IR[5] == 1'b1 && Mode == 3 )
-                end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000
-              
-              8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111  :
-                begin
-                  // RST p
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        TStates = 3'b101;
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        Set_BusB_To = 4'b1101;
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Write = 1'b1;
-                        IncDec_16 = 4'b1111;
-                        Set_Addr_To = aSP;
-                        Set_BusB_To = 4'b1100;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Write = 1'b1;
-                        RstP = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111
-              
-              // INPUT AND OUTPUT GROUP
-              8'b11011011  :
-                begin
-                  if (Mode != 3 ) 
-                    begin
-                      // IN A,(n)
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            Set_Addr_To = aIOA;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Read_To_Acc = 1'b1;
-                            IORQ = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase
-                    end // if (Mode != 3 )
-                end // case: 8'b11011011
-              
-              8'b11010011  :
-                begin
-                  if (Mode != 3 ) 
-                    begin
-                      // OUT (n),A
-                      MCycles = 3'b011;
-                      case (1'b1) // MCycle
-                        MCycle[1] :
-                          begin
-                            Inc_PC = 1'b1;
-                            Set_Addr_To = aIOA;
-                            Set_BusB_To = 4'b0111;
-                          end
-                        
-                        MCycle[2] :
-                          begin
-                            Write = 1'b1;
-                            IORQ = 1'b1;
-                          end
-                        
-                        default :;
-                      endcase
-                    end // if (Mode != 3 )
-                end // case: 8'b11010011
-              
-
-              //----------------------------------------------------------------------------
-              //----------------------------------------------------------------------------
-              // MULTIBYTE INSTRUCTIONS
-              //----------------------------------------------------------------------------
-              //----------------------------------------------------------------------------
-
-              8'b11001011  :
-                begin
-                  if (Mode != 2 ) 
-                    begin
-                      Prefix = 2'b01;
-                    end
-                end              
-
-              8'b11101101  :
-                begin
-                  if (Mode < 2 ) 
-                    begin
-                      Prefix = 2'b10;
-                    end
-                end
-
-              8'b11011101,8'b11111101  :
-                begin
-                  if (Mode < 2 ) 
-                    begin
-                      Prefix = 2'b11;
-                    end
-                end
-              
-            endcase // case(IRB)
-          end // case: 2'b00
-        
-
-        2'b01  :
-          begin
-            
-
-            //----------------------------------------------------------------------------
-            //
-            //  CB prefixed instructions
-            //
-            //----------------------------------------------------------------------------
-            
-            Set_BusA_To[2:0] = IR[2:0];
-            Set_BusB_To[2:0] = IR[2:0];
-            
-            case (IRB)
-              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
-              8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
-              8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
-              8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
-              8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
-              8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111,
-              8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111,
-              8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 :
-                begin
-                  // RLC r
-                  // RL r
-                  // RRC r
-                  // RR r
-                  // SLA r
-                  // SRA r
-                  // SRL r
-                  // SLL r (Undocumented) / SWAP r
-                  if (MCycle[0] ) begin
-                    ALU_Op = 4'b1000;
-                    Read_To_Reg = 1'b1;
-                    Save_ALU = 1'b1;
-                  end
-                end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
-              
-              8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110  :
-                begin
-                  // RLC (HL)
-                  // RL (HL)
-                  // RRC (HL)
-                  // RR (HL)
-                  // SRA (HL)
-                  // SRL (HL)
-                  // SLA (HL)
-                  // SLL (HL) (Undocumented) / SWAP (HL)
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0], MCycle[6] :
-                      Set_Addr_To = aXY;
-                    MCycle[1] :
-                      begin
-                        ALU_Op = 4'b1000;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_Addr_To = aXY;
-                        TStates = 3'b100;
-                      end
-                    
-                    MCycle[2] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
-              
-              8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
-                  8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
-                  8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
-                  8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
-                  8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
-                  8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
-                  8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
-                  8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
-                    begin
-                      // BIT b,r
-                      if (MCycle[0] )
-                        begin
-                          Set_BusB_To[2:0] = IR[2:0];
-                          ALU_Op = 4'b1001;
-                        end
-                    end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
-              
-              8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110  :
-                begin
-                  // BIT b,(HL)
-                  MCycles = 3'b010;
-                  case (1'b1) // MCycle
-                    MCycle[0], MCycle[6] :
-                      Set_Addr_To = aXY;
-                    MCycle[1] :
-                      begin
-                        ALU_Op = 4'b1001;
-                        TStates = 3'b100;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110
-              
-              8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,
-                  8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111,
-                  8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111,
-                  8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111,
-                  8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111,
-                  8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
-                  8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
-                  8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
-                    begin
-                      // SET b,r
-                      if (MCycle[0] ) 
-                        begin
-                          ALU_Op = 4'b1010;
-                          Read_To_Reg = 1'b1;
-                          Save_ALU = 1'b1;
-                        end
-                    end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,...
-              
-              8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110  :
-                begin
-                  // SET b,(HL)
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0], MCycle[6] :
-                      Set_Addr_To = aXY;
-                    MCycle[1] :
-                      begin
-                        ALU_Op = 4'b1010;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_Addr_To = aXY;
-                        TStates = 3'b100;
-                      end
-                    MCycle[2] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
-              
-              8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
-                  8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
-                  8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
-                  8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
-                  8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
-                  8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
-                  8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
-                  8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
-                    begin
-                      // RES b,r
-                      if (MCycle[0] ) 
-                        begin
-                          ALU_Op = 4'b1011;
-                          Read_To_Reg = 1'b1;
-                          Save_ALU = 1'b1;
-                        end
-                    end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
-              
-              8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110  :
-                begin
-                  // RES b,(HL)
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0], MCycle[6] :
-                      Set_Addr_To = aXY;
-                    MCycle[1] :
-                      begin
-                        ALU_Op = 4'b1011;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_Addr_To = aXY;
-                        TStates = 3'b100;
-                      end
-                    
-                    MCycle[2] :
-                      Write = 1'b1;
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
-              
-            endcase // case(IRB)
-          end // case: 2'b01
-        
-        
-        default :
-          begin : default_ed_block
-            
-            //----------------------------------------------------------------------------
-            //
-            //  ED prefixed instructions
-            //
-            //----------------------------------------------------------------------------
-
-            case (IRB)
-              8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
-                ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
-                  ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111
-                    ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111
-                      ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111
-                        ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111
-                          ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111
-                            ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111
-                
-
-                              ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111
-                                ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111
-                                  ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111
-                                    ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111
-                                      ,                                            8'b10100100,8'b10100101,8'b10100110,8'b10100111
-                                        ,                                            8'b10101100,8'b10101101,8'b10101110,8'b10101111
-                                          ,                                            8'b10110100,8'b10110101,8'b10110110,8'b10110111
-                                            ,                                            8'b10111100,8'b10111101,8'b10111110,8'b10111111
-                                              ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111
-                                                ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111
-                                                  ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111
-                                                    ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111
-                                                      ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111
-                                                        ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111
-                                                          ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111
-                                                            ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 :
-                                                              ; // NOP, undocumented
-              
-              8'b01111110,8'b01111111  :
-                // NOP, undocumented
-                ;
-              // 8 BIT LOAD GROUP
-              8'b01010111  :
-                begin
-                  // LD A,I
-                  Special_LD = 3'b100;
-                  TStates = 3'b101;
-                end
-              
-              8'b01011111  :
-                begin
-                  // LD A,R
-                  Special_LD = 3'b101;
-                  TStates = 3'b101;
-                end
-              
-              8'b01000111  :
-                begin
-                  // LD I,A
-                  Special_LD = 3'b110;
-                  TStates = 3'b101;
-                end
-              
-              8'b01001111  :
-                begin
-                  // LD R,A
-                  Special_LD = 3'b111;
-                  TStates = 3'b101;
-                end
-              
-              // 16 BIT LOAD GROUP
-              8'b01001011,8'b01011011,8'b01101011,8'b01111011  :
-                begin
-                  // LD dd,(nn)
-                  MCycles = 3'b101;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        Inc_PC = 1'b1;
-                        LDZ = 1'b1;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Set_Addr_To = aZI;
-                        Inc_PC = 1'b1;
-                        LDW = 1'b1;
-                      end
-                    
-                    MCycle[3] :
-                      begin
-                        Read_To_Reg = 1'b1;
-                        if (IR[5:4] == 2'b11 ) 
-                          begin
-                            Set_BusA_To = 4'b1000;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = IR[5:4];
-                            Set_BusA_To[0] = 1'b1;
-                          end
-                        Inc_WZ = 1'b1;
-                        Set_Addr_To = aZI;
-                      end // case: 4
-                    
-                    MCycle[4] :
-                      begin
-                        Read_To_Reg = 1'b1;
-                        if (IR[5:4] == 2'b11 ) 
-                          begin
-                            Set_BusA_To = 4'b1001;
-                          end 
-                        else 
-                          begin
-                            Set_BusA_To[2:1] = IR[5:4];
-                            Set_BusA_To[0] = 1'b0;
-                          end
-                      end // case: 5
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011
-              
-              
-              8'b01000011,8'b01010011,8'b01100011,8'b01110011  :
-                begin
-                  // LD (nn),dd
-                  MCycles = 3'b101;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        Inc_PC = 1'b1;
-                        LDZ = 1'b1;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Set_Addr_To = aZI;
-                        Inc_PC = 1'b1;
-                        LDW = 1'b1;
-                        if (IR[5:4] == 2'b11 ) 
-                          begin
-                            Set_BusB_To = 4'b1000;
-                          end 
-                        else 
-                          begin
-                            Set_BusB_To[2:1] = IR[5:4];
-                            Set_BusB_To[0] = 1'b1;
-                            Set_BusB_To[3] = 1'b0;
-                          end
-                      end // case: 3
-                    
-                    MCycle[3] :
-                      begin
-                        Inc_WZ = 1'b1;
-                        Set_Addr_To = aZI;
-                        Write = 1'b1;
-                        if (IR[5:4] == 2'b11 ) 
-                          begin
-                            Set_BusB_To = 4'b1001;
-                          end 
-                        else 
-                          begin
-                            Set_BusB_To[2:1] = IR[5:4];
-                            Set_BusB_To[0] = 1'b0;
-                            Set_BusB_To[3] = 1'b0;
-                          end
-                      end // case: 4
-                    
-                    MCycle[4] :
-                      begin
-                        Write = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011
-              
-              8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000  :
-                begin
-                  // LDI, LDD, LDIR, LDDR
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aXY;
-                        IncDec_16 = 4'b1100; // BC
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Set_BusB_To = 4'b0110;
-                        Set_BusA_To[2:0] = 3'b111;
-                        ALU_Op = 4'b0000;
-                        Set_Addr_To = aDE;
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0110; // IX
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1110;
-                          end
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        I_BT = 1'b1;
-                        TStates = 3'b101;
-                        Write = 1'b1;
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0101; // DE
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1101;
-                          end
-                      end // case: 3
-                    
-                    MCycle[3] :
-                      begin
-                        NoRead = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000
-              
-              8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001  :
-                begin
-                  // CPI, CPD, CPIR, CPDR
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aXY;
-                        IncDec_16 = 4'b1100; // BC
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Set_BusB_To = 4'b0110;
-                        Set_BusA_To[2:0] = 3'b111;
-                        ALU_Op = 4'b0111;
-                        Save_ALU = 1'b1;
-                        PreserveC = 1'b1;
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0110;
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1110;
-                          end
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        NoRead = 1'b1;
-                        I_BC = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    MCycle[3] :
-                      begin
-                        NoRead = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001
-              
-              8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100  :
-                begin
-                  // NEG
-                  ALU_Op = 4'b0010;
-                  Set_BusB_To = 4'b0111;
-                  Set_BusA_To = 4'b1010;
-                  Read_To_Acc = 1'b1;
-                  Save_ALU = 1'b1;
-                end
-              
-              8'b01000110,8'b01001110,8'b01100110,8'b01101110  :
-                begin
-                  // IM 0
-                  IMode = 2'b00;
-                end
-              
-              8'b01010110,8'b01110110  :
-                // IM 1
-                IMode = 2'b01;
-              
-              8'b01011110,8'b01110111  :
-                // IM 2
-                IMode = 2'b10;
-              
-              // 16 bit arithmetic
-              8'b01001010,8'b01011010,8'b01101010,8'b01111010  :
-                begin
-                  // ADC HL,ss
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        NoRead = 1'b1;
-                        ALU_Op = 4'b0001;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_BusA_To[2:0] = 3'b101;
-                        case (IR[5:4])
-                          0,1,2  :
-                            begin
-                              Set_BusB_To[2:1] = IR[5:4];
-                              Set_BusB_To[0] = 1'b1;
-                            end
-                          default :
-                            Set_BusB_To = 4'b1000;
-                        endcase
-                        TStates = 3'b100;
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        NoRead = 1'b1;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        ALU_Op = 4'b0001;
-                        Set_BusA_To[2:0] = 3'b100;
-                        case (IR[5:4])
-                          0,1,2  :
-                            begin
-                              Set_BusB_To[2:1] = IR[5:4];
-                              Set_BusB_To[0] = 1'b0;
-                            end
-                          default :
-                            Set_BusB_To = 4'b1001;
-                        endcase // case(IR[5:4])
-                      end // case: 3
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010
-              
-              8'b01000010,8'b01010010,8'b01100010,8'b01110010  :
-                begin
-                  // SBC HL,ss
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        NoRead = 1'b1;
-                        ALU_Op = 4'b0011;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_BusA_To[2:0] = 3'b101;
-                        case (IR[5:4])
-                          0,1,2  :
-                            begin
-                              Set_BusB_To[2:1] = IR[5:4];
-                              Set_BusB_To[0] = 1'b1;
-                            end
-                          default :
-                            Set_BusB_To = 4'b1000;
-                        endcase
-                        TStates = 3'b100;
-                      end // case: 2
-                    
-                    MCycle[2] :
-                      begin
-                        NoRead = 1'b1;
-                        ALU_Op = 4'b0011;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        Set_BusA_To[2:0] = 3'b100;
-                        case (IR[5:4])
-                          0,1,2  :
-                            Set_BusB_To[2:1] = IR[5:4];
-                          default :
-                            Set_BusB_To = 4'b1001;
-                        endcase
-                      end // case: 3
-                    
-                    default :;
-                    
-                  endcase // case(MCycle)
-                end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010
-              
-              8'b01101111  :
-                begin
-                  // RLD
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      begin
-                        NoRead = 1'b1;
-                        Set_Addr_To = aXY;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Read_To_Reg = 1'b1;
-                        Set_BusB_To[2:0] = 3'b110;
-                        Set_BusA_To[2:0] = 3'b111;
-                        ALU_Op = 4'b1101;
-                        TStates = 3'b100;
-                        Set_Addr_To = aXY;
-                        Save_ALU = 1'b1;
-                      end
-                    
-                    MCycle[3] :
-                      begin
-                        I_RLD = 1'b1;
-                        Write = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01101111
-              
-              8'b01100111  :
-                begin
-                  // RRD
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[1] :
-                      Set_Addr_To = aXY;
-                    MCycle[2] :
-                      begin
-                        Read_To_Reg = 1'b1;
-                        Set_BusB_To[2:0] = 3'b110;
-                        Set_BusA_To[2:0] = 3'b111;
-                        ALU_Op = 4'b1110;
-                        TStates = 3'b100;
-                        Set_Addr_To = aXY;
-                        Save_ALU = 1'b1;
-                      end
-                    
-                    MCycle[3] :
-                      begin
-                        I_RRD = 1'b1;
-                        Write = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01100111
-              
-              8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101  :
-                begin
-                  // RETI, RETN
-                  MCycles = 3'b011;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      Set_Addr_To = aSP;
-                    
-                    MCycle[1] :
-                      begin
-                        IncDec_16 = 4'b0111;
-                        Set_Addr_To = aSP;
-                        LDZ = 1'b1;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        Jump = 1'b1;
-                        IncDec_16 = 4'b0111;
-                        I_RETN = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101
-              
-              8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000  :
-                begin
-                  // IN r,(C)
-                  MCycles = 3'b010;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      Set_Addr_To = aBC;
-                    
-                    MCycle[1] :
-                      begin
-                        IORQ = 1'b1;
-                        if (IR[5:3] != 3'b110 ) 
-                          begin
-                            Read_To_Reg = 1'b1;
-                            Set_BusA_To[2:0] = IR[5:3];
-                          end
-                        I_INRC = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000
-              
-              8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001  :
-                begin
-                  // OUT (C),r
-                  // OUT (C),0
-                  MCycles = 3'b010;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aBC;
-                        Set_BusB_To[2:0]        = IR[5:3];
-                        if (IR[5:3] == 3'b110 ) 
-                          begin
-                            Set_BusB_To[3] = 1'b1;
-                          end
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Write = 1'b1;
-                        IORQ = 1'b1;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001
-              
-              8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010  :
-                begin
-                  // INI, IND, INIR, INDR
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        Set_Addr_To = aBC;
-                        Set_BusB_To = 4'b1010;
-                        Set_BusA_To = 4'b0000;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        ALU_Op = 4'b0010;
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        IORQ = 1'b1;
-                        Set_BusB_To = 4'b0110;
-                        Set_Addr_To = aXY;
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        if (IR[3] == 1'b0 ) 
-                          begin
-			    IncDec_16 = 4'b0110;
-                          end 
-                        else 
-                          begin
-			    IncDec_16 = 4'b1110;
-                          end
-                        TStates = 3'b100;
-                        Write = 1'b1;
-                        I_BTR = 1'b1;
-                      end // case: 3
-                    
-                    MCycle[3] :
-                      begin
-                        NoRead = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010
-              
-              8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011  :
-                begin
-                  // OUTI, OUTD, OTIR, OTDR
-                  MCycles = 3'b100;
-                  case (1'b1) // MCycle
-                    MCycle[0] :
-                      begin
-                        TStates = 3'b101;
-                        Set_Addr_To = aXY;
-                        Set_BusB_To = 4'b1010;
-                        Set_BusA_To = 4'b0000;
-                        Read_To_Reg = 1'b1;
-                        Save_ALU = 1'b1;
-                        ALU_Op = 4'b0010;
-                      end
-                    
-                    MCycle[1] :
-                      begin
-                        Set_BusB_To = 4'b0110;
-                        Set_Addr_To = aBC;
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0110;
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1110;
-                          end
-                      end
-                    
-                    MCycle[2] :
-                      begin
-                        if (IR[3] == 1'b0 ) 
-                          begin
-                            IncDec_16 = 4'b0010;
-                          end 
-                        else 
-                          begin
-                            IncDec_16 = 4'b1010;
-                          end
-                        IORQ = 1'b1;
-                        Write = 1'b1;
-                        I_BTR = 1'b1;
-                      end // case: 3
-                    
-                    MCycle[3] :
-                      begin
-                        NoRead = 1'b1;
-                        TStates = 3'b101;
-                      end
-                    
-                    default :;
-                  endcase // case(MCycle)
-                end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
-              
-            endcase // case(IRB)                  
-          end // block: default_ed_block        
-      endcase // case(ISet)
-      
-      if (Mode == 1 ) 
-        begin
-          if (MCycle[0] ) 
-            begin
-              //TStates = 3'b100;
-            end 
-          else 
-            begin
-              TStates = 3'b011;
-            end
-        end
-
-      if (Mode == 3 ) 
-        begin
-          if (MCycle[0] ) 
-            begin
-              //TStates = 3'b100;
-            end 
-          else 
-            begin
-              TStates = 3'b100;
-            end
-        end
-
-      if (Mode < 2 ) 
-        begin
-          if (MCycle[5] ) 
-            begin
-              Inc_PC = 1'b1;
-              if (Mode == 1 ) 
-                begin
-                  Set_Addr_To = aXY;
-                  TStates = 3'b100;
-                  Set_BusB_To[2:0] = SSS;
-                  Set_BusB_To[3] = 1'b0;
-                end
-              if (IRB == 8'b00110110 || IRB == 8'b11001011 ) 
-                begin
-                  Set_Addr_To = aNone;
-                end
-            end
-          if (MCycle[6] ) 
-            begin
-              if (Mode == 0 ) 
-                begin
-                  TStates = 3'b101;
-                end
-              if (ISet != 2'b01 ) 
-                begin
-                  Set_Addr_To = aXY;
-                end
-              Set_BusB_To[2:0] = SSS;
-              Set_BusB_To[3] = 1'b0;
-              if (IRB == 8'b00110110 || ISet == 2'b01 ) 
-                begin
-                  // LD (HL),n
-                  Inc_PC = 1'b1;
-                end 
-              else 
-                begin
-                  NoRead = 1'b1;
-                end
-            end
-        end // if (Mode < 2 )      
-      
-    end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
-  
-endmodule // T80_MCode
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_reg.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_reg.v
deleted file mode 100644
index 9d378330..00000000
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80_reg.v	
+++ /dev/null
@@ -1,68 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-module tv80_reg (/*AUTOARG*/
-  // Outputs
-  DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, 
-  // Inputs
-  AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
-  );
-    input  [2:0] AddrC;
-    output [7:0] DOBH;
-    input  [2:0] AddrA;
-    input  [2:0] AddrB;
-    input  [7:0] DIH;
-    output [7:0] DOAL;
-    output [7:0] DOCL;
-    input  [7:0] DIL;
-    output [7:0] DOBL;
-    output [7:0] DOCH;
-    output [7:0] DOAH;
-    input  clk, CEN, WEH, WEL;
-
-  reg [7:0] RegsH [0:7];
-  reg [7:0] RegsL [0:7];
-
-  always @(posedge clk)
-    begin
-      if (CEN)
-        begin
-          if (WEH) RegsH[AddrA] <= DIH;
-          if (WEL) RegsL[AddrA] <= DIL;
-        end
-    end
-          
-  assign DOAH = RegsH[AddrA];
-  assign DOAL = RegsL[AddrA];
-  assign DOBH = RegsH[AddrB];
-  assign DOBL = RegsL[AddrB];
-  assign DOCH = RegsH[AddrC];
-  assign DOCL = RegsL[AddrC];
-
-  // break out ram bits for waveform debug
-  wire [7:0] H = RegsH[2];
-  wire [7:0] L = RegsL[2];
-  
-endmodule
-
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80n.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80n.v
deleted file mode 100644
index b7802e33..00000000
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/T80/tv80n.v	
+++ /dev/null
@@ -1,182 +0,0 @@
-//
-// TV80 8-Bit Microprocessor Core
-// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
-//
-// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a 
-// copy of this software and associated documentation files (the "Software"), 
-// to deal in the Software without restriction, including without limitation 
-// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-// and/or sell copies of the Software, and to permit persons to whom the 
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included 
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-// Negative-edge based wrapper allows memory wait_n signal to work
-// correctly without resorting to asynchronous logic.
-
-module tv80n (/*AUTOARG*/
-  // Outputs
-  m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout, 
-  // Inputs
-  reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
-  );
-
-  parameter Mode = 0;    // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-  parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
-  parameter IOWait  = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
-
-
-  input         reset_n; 
-  input         clk; 
-  input         wait_n; 
-  input         int_n; 
-  input         nmi_n; 
-  input         busrq_n; 
-  output        m1_n; 
-  output        mreq_n; 
-  output        iorq_n; 
-  output        rd_n; 
-  output        wr_n; 
-  output        rfsh_n; 
-  output        halt_n; 
-  output        busak_n; 
-  output [15:0] A;
-  input [7:0]   di;
-  output [7:0]  dout;
-
-  reg           mreq_n; 
-  reg           iorq_n; 
-  reg           rd_n; 
-  reg           wr_n; 
-  reg           nxt_mreq_n; 
-  reg           nxt_iorq_n; 
-  reg           nxt_rd_n; 
-  reg           nxt_wr_n; 
-  
-  wire          cen;
-  wire          intcycle_n;
-  wire          no_read;
-  wire          write;
-  wire          iorq;
-  reg [7:0]     di_reg;
-  wire [6:0]    mcycle;
-  wire [6:0]    tstate;
-
-  assign    cen = 1;
-
-  tv80_core #(Mode, IOWait) i_tv80_core
-    (
-     .cen (cen),
-     .m1_n (m1_n),
-     .iorq (iorq),
-     .no_read (no_read),
-     .write (write),
-     .rfsh_n (rfsh_n),
-     .halt_n (halt_n),
-     .wait_n (wait_n),
-     .int_n (int_n),
-     .nmi_n (nmi_n),
-     .reset_n (reset_n),
-     .busrq_n (busrq_n),
-     .busak_n (busak_n),
-     .clk (clk),
-     .IntE (),
-     .stop (),
-     .A (A),
-     .dinst (di),
-     .di (di_reg),
-     .dout (dout),
-     .mc (mcycle),
-     .ts (tstate),
-     .intcycle_n (intcycle_n)
-     );  
-
-  always @*
-    begin
-      nxt_mreq_n = 1;
-      nxt_rd_n   = 1;
-      nxt_iorq_n = 1;
-      nxt_wr_n   = 1;
-      
-      if (mcycle[0])
-        begin
-	  if (tstate[1] || tstate[2])
-            begin
-	      nxt_rd_n = ~ intcycle_n;
-	      nxt_mreq_n = ~ intcycle_n;
-	      nxt_iorq_n = intcycle_n;
-	    end
-        end // if (mcycle[0])          
-      else
-        begin
-	  if ((tstate[1] || tstate[2]) && !no_read && !write)
-            begin
-	      nxt_rd_n = 1'b0;
-	      nxt_iorq_n = ~ iorq;
-	      nxt_mreq_n = iorq;
-	    end
-	  if (T2Write == 0)
-            begin                          
-	      if (tstate[2] && write)
-                begin
-		  nxt_wr_n = 1'b0;
-		  nxt_iorq_n = ~ iorq;
-		  nxt_mreq_n = iorq;
-                end
-            end
-	  else
-            begin
-	      if ((tstate[1] || (tstate[2] && !wait_n)) && write)
-                begin
-		  nxt_wr_n = 1'b0;
-		  nxt_iorq_n = ~ iorq;
-		  nxt_mreq_n = iorq;
-		end
-	    end // else: !if(T2write == 0)          
-	end // else: !if(mcycle[0])
-    end // always @ *
-
-  always @(negedge clk)
-    begin
-      if (!reset_n)
-        begin
-	  rd_n   <= #1 1'b1;
-	  wr_n   <= #1 1'b1;
-	  iorq_n <= #1 1'b1;
-	  mreq_n <= #1 1'b1;
-        end
-      else
-        begin
-	  rd_n <= #1 nxt_rd_n;
-	  wr_n <= #1 nxt_wr_n;
-	  iorq_n <= #1 nxt_iorq_n;
-	  mreq_n <= #1 nxt_mreq_n;
-	end // else: !if(!reset_n)
-    end // always @ (posedge clk or negedge reset_n)
-
-  always @(posedge clk)
-    begin
-      if (!reset_n)
-        begin
-	  di_reg <= #1 0;
-        end
-      else
-        begin
-	  if (tstate[2] && wait_n == 1'b1)
-	    di_reg <= #1 di;
-	end // else: !if(!reset_n)
-    end // always @ (posedge clk)
-  
-endmodule // t80n
-
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.mif b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.mif
new file mode 100644
index 00000000..a62f3330
--- /dev/null
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace.mif	
@@ -0,0 +1,353 @@
+-- http://srecord.sourceforge.net/
+--
+-- Generated automatically by srec -o --mif
+--
+DEPTH = 8192;
+WIDTH = 8;
+ADDRESS_RADIX = HEX;
+DATA_RADIX = HEX;
+CONTENT BEGIN
+0000: F3 21 00 3C 3E FC 18 20 D9 DD CB 3E 5E C3 EE 03 2A 3B 3C 73 23 C3 5F 08;
+0018: 2A 3B 3C 2B 56 C3 59 08 E1 7E 32 3D 3C C3 AD 00 24 77 BE 28 FB A4 67 22;
+0030: 18 3C F9 21 0D 01 18 03 C3 3A 01 11 24 3C 01 2D 00 ED B0 DD 21 00 3C FD;
+0048: 21 C8 04 CD 24 0A AF 32 00 27 21 00 2C 7D E6 BF 0F 0F 0F 30 02 0F 0F 0F;
+0060: 47 9F CB 18 47 9F A8 E6 F0 A8 77 2C 20 E7 11 FF 2F 21 FB 1F 01 08 00 ED;
+0078: B8 EB 3E 5F 0E 07 CB 6F 28 03 70 2B 0D EB ED B8 EB 70 2B 3D 20 EE ED 56;
+0090: 18 09 51 55 49 D4 00 00 04 9B 00 ED 7B 18 3C FB C3 F2 04 41 42 4F 52 D4;
+00A8: 98 00 05 AD 00 FD E5 FD 21 B9 04 2A 37 3C 22 3B 3C 21 3E 3C 7E E6 B3 CB;
+00C0: 56 77 28 1A CD B9 04 90 04 B3 08 4B 10 05 D2 0D 6B 08 10 16 B5 15 11 10;
+00D8: 37 3C C1 08 0E 1A DD CB 3D 7E 20 1B CD 08 18 45 52 52 4F D2 CD B9 04 11;
+00F0: 10 3D 3C 96 08 B3 09 95 0A 0E 1A DD 36 3D FF 2A 37 3C 01 0C 00 09 22 3B;
+0108: 3C FD E1 18 8E E0 26 00 00 00 00 00 00 00 00 00 00 00 4C 3C 4C 3C 4F 3C;
+0120: 51 3C 45 3C 5D 3C FF 00 0A 46 4F 52 54 C8 00 00 FF 1F 05 B5 11 49 3C 00;
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+0150: 3C CB 46 28 21 A7 28 1E FE 20 38 14 CB 4E C4 07 08 CB 56 28 02 E6 9F CB;
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+0228: 23 22 20 3C CD 02 03 62 6B 1B 1A A7 C8 ED 53 20 3C 78 B1 28 02 ED B0 2B;
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+0898: DF 1A 5F 16 00 D7 FD E9 43 A1 95 08 02 A7 08 DF CD 4E 08 79 12 FD E9 C0;
+08B0: A4 08 01 B5 08 DF EB 5E 23 56 D7 FD E9 A1 B2 08 01 C3 08 DF CD 4E 08 EB;
+08C8: 71 23 70 FD E9 3E D2 C0 08 02 D4 08 DF C1 D5 C5 FD E9 52 BE D1 08 02 E1;
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+0958: 02 E7 07 2A 3B 3C ED 42 E5 5E 23 56 D7 E1 C9 54 59 50 C5 32 09 04 70 09;
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+0A00: 08 07 0A 5C 0A B6 04 09 0A DF 7B C6 30 FE 3A 38 02 C6 07 5F D7 FD E9 43;
+0A18: 4C D3 F6 09 03 1F 0A CD 24 0A FD E9 11 FF 26 2A 24 3C 01 20 00 09 2B ED;
+0A30: B8 ED 43 2F 3C 21 00 24 22 1C 3C 13 EB 22 24 3C C3 FA 07 53 49 47 CE 9B;
+0A48: 09 04 4C 0A DF CB 12 1E 2D 38 0C FD E9 48 4F 4C C4 1C 0A 04 5E 0A DF 2A;
+0A60: 1A 3C 2D 28 04 22 1A 3C 73 FD E9 53 50 41 43 C5 5B 0A 05 75 0A 3E 20 CF;
+0A78: FD E9 53 50 41 43 45 D3 72 0A 06 85 0A DF 1B CB 7A 20 ED 3E 20 CF 18 F6;
+0A90: 43 D2 82 0A 02 97 0A 3E 0D CF FD E9 45 4D 49 D4 94 0A 04 A5 0A DF 7B CF;
+0AA8: FD E9 46 AE A2 0A 02 B1 0A 2A 3B 3C 2B CB 7E CB BE 28 03 3E 2D CF 1E 00;
+0AC0: 7E 3D FE 49 30 04 FE 3C 30 04 36 41 3C 5F 3E 40 96 38 09 47 04 3E 2E CF;
+0AD8: 3E 30 10 FB 3E 40 BE 9F 2B B6 2B B6 2B B6 23 23 28 12 AF CD 32 07 C6 30;
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+0B08: 9F 67 3E 45 CF CD 0E 18 DF DF FD E9 41 D4 AE 0A 02 1B 0B DF CD 4E 08 79;
+0B20: CD 28 0B 22 1C 3C FD E9 C6 20 6F 26 01 29 29 29 29 29 16 00 7B E6 1F 5F;
+0B38: 19 ED 5B 24 3C ED 52 19 D8 E7 09 50 4C 4F D4 18 0B 04 4C 0B CD 4E 08 DF;
+0B50: DD 73 30 CB 3B CB 11 3E 16 93 DF DD 73 2F CB 3B CB 11 CD 28 0B 7E E6 78;
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+1DE0: 00 18 18 00 00 02 04 08 10 20 00 3C 46 4A 52 62 3C 00 18 28 08 08 08 3E;
+1DF8: 00 3C 42 02 3C 40 7E 00 3C 42 0C 02 42 3C 00 08 18 28 48 7E 08 00 7E 40;
+1E10: 7C 02 42 3C 00 3C 40 7C 42 42 3C 00 7E 02 04 08 10 10 00 3C 42 3C 42 42;
+1E28: 3C 00 3C 42 42 3E 02 3C 00 00 00 10 00 00 10 00 00 10 00 00 10 10 20 00;
+1E40: 04 08 10 08 04 00 00 00 3E 00 3E 00 00 00 10 08 04 08 10 00 3C 42 04 08;
+1E58: 00 08 3C 4A 56 5E 40 3C 3C 42 42 7E 42 42 7C 42 7C 42 42 7C 3C 42 40 40;
+1E70: 42 3C 78 44 42 42 44 78 7E 40 7C 40 40 7E 7E 40 7C 40 40 40 3C 42 40 4E;
+1E88: 42 3C 42 42 7E 42 42 42 3E 08 08 08 08 3E 02 02 02 42 42 3C 44 48 70 48;
+1EA0: 44 42 40 40 40 40 40 7E 42 66 5A 42 42 42 42 62 52 4A 46 42 3C 42 42 42;
+1EB8: 42 3C 7C 42 42 7C 40 40 3C 42 42 52 4A 3C 7C 42 42 7C 44 42 3C 40 3C 02;
+1ED0: 42 3C FE 10 10 10 10 10 42 42 42 42 42 3E 42 42 42 42 24 18 42 42 42 42;
+1EE8: 5A 24 42 24 18 18 24 42 82 44 28 10 10 10 7E 04 08 10 20 7E 0E 08 08 08;
+1F00: 08 0E 00 40 20 10 08 04 70 10 10 10 10 70 10 38 54 10 10 10 00 00 00 00;
+1F18: 00 00 FF 1C 22 78 20 20 7E 00 00 38 04 3C 44 3E 00 20 20 3C 22 22 3C 00;
+1F30: 00 1C 20 20 20 1C 00 04 04 3C 44 44 3E 00 00 38 44 78 40 3C 00 0C 10 18;
+1F48: 10 10 10 00 00 3C 44 44 3C 04 38 40 40 78 44 44 44 00 10 00 30 10 10 38;
+1F60: 00 04 00 04 04 04 24 18 20 28 30 30 28 24 00 10 10 10 10 10 0C 00 00 68;
+1F78: 54 54 54 54 00 00 78 44 44 44 44 00 00 38 44 44 44 38 00 00 78 44 44 78;
+1F90: 40 40 00 3C 44 44 3C 04 06 00 1C 20 20 20 20 00 00 38 40 38 04 78 00 10;
+1FA8: 38 10 10 10 0C 00 00 44 44 44 44 3C 00 00 44 44 28 28 10 00 00 44 54 54;
+1FC0: 54 28 00 00 44 28 10 28 44 00 00 44 44 44 3C 04 38 00 7C 08 10 20 7C 00;
+1FD8: 0E 08 30 30 08 0E 00 08 08 08 08 08 08 00 70 10 0C 0C 10 70 00 32 4C 00;
+1FF0: 00 00 00 00 3C 42 99 A1 A1 99 42 3C FF 58 1D 00;
+END;
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace_mist.sv b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace_mist.sv
index 2079be4a..8cfecfd1 100644
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace_mist.sv	
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/ace_mist.sv	
@@ -19,68 +19,44 @@ module ace_mist(
    input         SPI_SS2,
    input         SPI_SS3,
 	input         SPI_SS4,
-   input         CONF_DATA0,
-   output [12:0] SDRAM_A,
-   inout  [15:0] SDRAM_DQ,
-   output        SDRAM_DQML,
-   output        SDRAM_DQMH,
-   output        SDRAM_nWE,
-   output        SDRAM_nCAS,
-   output        SDRAM_nRAS,
-   output        SDRAM_nCS,
-   output  [1:0] SDRAM_BA,
-   output        SDRAM_CLK,
-   output        SDRAM_CKE
+   input         CONF_DATA0
     );
 	 
 `include "rtl\build_id.v" 
 	 
 localparam CONF_STR = {
 		  "Jupiter ACE;;",
+		  "F,ACE;",
 		  "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+		  "O67,CPU Speed,Normal,x2,x4;",
 		  "T5,Reset;",
-		  "V,v0.2.",`BUILD_DATE
+		  "V,v0.5.",`BUILD_DATE
 		};
 
 wire			clk_sys;
-wire 			clk_65;
-wire 			clk_cpu;
 wire        clk_sdram;
 wire 			locked;
 wire        scandoubler_disable;
 wire        ypbpr;
-wire        ps2_kbd_clk, ps2_kbd_data;
-
+wire [10:0] ps2_key;
+assign LED = ~ioctl_download;
 wire [31:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire 			audio;
-wire 			TapeIn;
-wire 			TapeOut;
-wire 			HSync, VSync;
+wire 			HSync, VSync, HBlank, VBlank;
+wire 			blankn = ~(HBlank | VBlank);
 wire 			video;
-wire 	[7:0] kbd_rows;
-wire 	[4:0] kbd_columns;
+wire        ioctl_download;
+wire        ioctl_wr;
+wire [24:0] ioctl_addr;
+wire  [7:0] ioctl_dout;
+reg         ioctl_wait = 0;
 	
 pll pll(
-	.areset(),
 	.inclk0(CLOCK_27),
-	.c0(clk_sys),//26.0Mhz
-	.c1(clk_65),//6.5Mhz
-	.c2(clk_cpu),//3.25Mhz
-	.c3(SDRAM_CLK),//100Mhz
-	.locked(locked)
+	.c0(clk_sys)
 	);
 
-reg [7:0] reset_cnt;
-always @(posedge clk_sys) begin
-	if(!locked || buttons[1] || status[0] || status[5])
-		reset_cnt <= 8'h0;
-	else if(reset_cnt != 8'd255)
-		reset_cnt <= reset_cnt + 8'd1;
-end 
-
-wire reset = (reset_cnt != 8'd255);
 
 mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 (
@@ -96,15 +72,19 @@ mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
 	.scandoubler_disable(scandoubler_disable),
 	.ypbpr(ypbpr),
 	.status(status),
-	.ps2_kbd_clk(ps2_kbd_clk),
-	.ps2_kbd_data(ps2_kbd_data)
+	.ps2_key(ps2_key),
+	.ioctl_download(ioctl_download),
+	.ioctl_wr(ioctl_wr),
+	.ioctl_addr(ioctl_addr),
+	.ioctl_dout(ioctl_dout),
+	.ioctl_wait(ioctl_wait)
 );
 
-video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(1)) video_mixer
+video_mixer #(.LINE_LENGTH(280), .HALF_DEPTH(1)) video_mixer
 (
 	.clk_sys(clk_sys),
-	.ce_pix(clk_65),
-	.ce_pix_actual(clk_65),
+	.ce_pix(ce_pix),
+	.ce_pix_actual(ce_pix),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
@@ -113,12 +93,12 @@ video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(1)) video_mixer
 	.hq2x(status[4:3]==1),
 	.ypbpr(ypbpr),
 	.ypbpr_full(1),
-	.R({video,video,1'b0}),
-	.G({video,video,1'b0}),
-	.B({video,video,1'b0}),
-	.mono(1),
-	.HSync(HSync),
-	.VSync(VSync),
+	.R(blankn ? {video,video,video} : "000"),
+	.G(blankn ? {video,video,video} : "000"),
+	.B(blankn ? {video,video,video} : "000"),
+	.mono(0),
+	.HSync(~HSync),
+	.VSync(~VSync),
 	.line_start(0),
 	.VGA_R(VGA_R),
 	.VGA_G(VGA_G),
@@ -127,79 +107,118 @@ video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(1)) video_mixer
 	.VGA_HS(VGA_HS)
 );
 
-wire [14:0]sd_addr;
-wire [7:0]sd_dout;
-wire [7:0]sd_din;
-wire sd_we;
-wire sd_rd;
-wire sd_ready;
+wire [1:0] turbo = status[7:6];
 
-sram sram(
-	.SDRAM_DQ(SDRAM_DQ),
-	.SDRAM_A(SDRAM_A),
-	.SDRAM_DQML(SDRAM_DQML),
-	.SDRAM_DQMH(SDRAM_DQMH),
-	.SDRAM_BA(SDRAM_BA),
-	.SDRAM_nCS(SDRAM_nCS),
-	.SDRAM_nWE(SDRAM_nWE),
-	.SDRAM_nRAS(SDRAM_nRAS),
-	.SDRAM_nCAS(SDRAM_nCAS),
-	.SDRAM_CKE(SDRAM_CKE),
-	.init(~locked),
-	.clk_sdram(SDRAM_CLK),			
-	.addr({10'b0000000000,sd_addr}),   // 25 bit address
-	.dout(sd_dout),	// data output to cpu
-	.din(sd_din),     // data input from cpu
-	.we(sd_we),       // cpu requests write
-	.rd(sd_rd),       // cpu requests read
-	.ready(sd_ready)
-);
+reg ce_pix;
+reg ce_cpu;
+always @(negedge clk_sys) begin
+	reg [2:0] div;
 
-
-jupiter_ace jupiter_ace
-(
-   .clk_65(clk_65),
-   .clk_cpu(clk_cpu),
-   .reset(~reset),
-   .filas(kbd_rows),
-   .columnas(kbd_columns),
-   .video(video),
-   .hsync(HSync),
+	div <= div + 1'd1;
+	ce_pix <= !div[1:0];
+	ce_cpu <= (!div[2:0] && !turbo) | (!div[1:0] && turbo[0]) | turbo[1];
+end
+wire reset = ~(buttons[1] || status[0] || status[5]);
+wire spk, mic;
+jupiter_ace jupiter_ace(
+	.clk(clk_sys),
+	.ce_pix(ce_pix),
+	.ce_cpu(ce_cpu),
+	.no_wait(|turbo),
+	.reset(reset|loader_reset),
+	.kbd_row(kbd_row),
+	.kbd_col(kbd_col),
+	.video_out(video),
+	.hsync(HSync),
 	.vsync(VSync),
-   .ear(UART_RX),//Play
-   .mic(UART_TX),//Record
-   .spk(audio),
-	.sd_addr(sd_addr),
-	.sd_dout(sd_dout),
-	.sd_din(sd_din),
-	.sd_we(sd_we),
-	.sd_rd(sd_rd),
-	.sd_ready(sd_ready)
+	.hblank(HBlank),
+	.vblank(VBlank),
+	.mic(mic),
+	.spk(spk),
+	.loader_en(loader_en),
+	.loader_addr(loader_addr),
+	.loader_data(loader_data),
+	.loader_wr(loader_wr)
 );
 
 sigma_delta_dac sigma_delta_dac
 (	
 	.DACout(AUDIO_L),
-	.DACin({audio}),
-	.CLK(clk_65),
-	.RESET(0)
+	.DACin({1'b0, spk, mic, 13'd0}),
+	.CLK(clk_sys),
+	.RESET(reset)
 );
 
 assign AUDIO_R = AUDIO_L;
-	
-keyboard keyboard
-(
-   .clk(clk_65),
-   .clkps2(ps2_kbd_clk),
-   .dataps2(ps2_kbd_data),
-   .rows(kbd_rows),
-   .columns(kbd_columns),
-   .kbd_reset(),
-   .kbd_nmi(),
-   .kbd_mreset()        
+wire [7:0] kbd_row;
+wire [4:0] kbd_col;
+
+keyboard keyboard(
+	.reset(reset),
+	.clk_sys(clk_sys),
+	.ps2_key(ps2_key),
+	.kbd_row(kbd_row),
+	.kbd_col(kbd_col)
 );
 
+reg [15:0] loader_addr;
+reg  [7:0] loader_data;
+reg        loader_wr;
+reg        loader_en;
+reg        loader_reset = 0;
 
+always @(posedge clk_sys) begin
+	reg [7:0] cnt = 0;
+	reg [1:0] status = 0;
+	reg       old_download;
+	integer   timeout = 0;
+
+	old_download <= ioctl_download;
+	
+	loader_reset <= 0;
+	if(~old_download && ioctl_download) begin
+		loader_addr <= 'h2000;
+		status <= 0;
+		loader_reset <=1;
+		ioctl_wait <= 1;
+		timeout <= 3000000;
+		cnt <= 0;
+	end
+	
+	loader_wr <= 0;
+	if(loader_wr) loader_addr <= loader_addr + 1'd1;
+
+	if(ioctl_wr) begin
+		loader_en <= 1;
+		case(status)
+			0: if(ioctl_dout == 'hED) status <= 1;
+				else begin
+					loader_wr <= 1;
+					loader_data <= ioctl_dout;
+				end
+			1: begin
+					cnt <= ioctl_dout;
+					status <= ioctl_dout ? 2'd2 : 2'd3; // cnt = 0 => stop
+				end
+			2: begin
+					loader_data <= ioctl_dout;
+					ioctl_wait <= 1;
+				end
+		endcase
+	end
+
+	if(ioctl_wait && !loader_wr) begin
+		if(cnt) begin
+			cnt <= cnt - 1'd1;
+			loader_wr <= 1;
+		end
+		else if(timeout) timeout <= timeout - 1;
+		else {status,ioctl_wait} <= 0;
+	end
+
+	if(old_download & ~ioctl_download) loader_en <= 0;
+	if(reset) ioctl_wait <= 0;
+end
 
 
 endmodule
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.v
index f10d751c..8318a533 100644
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.v	
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/build_id.v	
@@ -1,2 +1,2 @@
-`define BUILD_DATE "180723"
-`define BUILD_TIME "190837"
+`define BUILD_DATE "181231"
+`define BUILD_TIME "044701"
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/dpram.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/dpram.v
new file mode 100644
index 00000000..bba33894
--- /dev/null
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/dpram.v	
@@ -0,0 +1,80 @@
+
+module dpram #(parameter ADDRWIDTH=8, DATAWIDTH=8, NUMWORDS=1<<ADDRWIDTH, MEM_INIT_FILE="")
+(
+	input	                 clock,
+
+	input	 [ADDRWIDTH-1:0] address_a,
+	input	 [DATAWIDTH-1:0] data_a,
+	input	                 wren_a,
+	input                  oe_a_n,
+	output [DATAWIDTH-1:0] q_a,
+
+	input	 [ADDRWIDTH-1:0] address_b,
+	input	 [DATAWIDTH-1:0] data_b,
+	input	                 wren_b,
+	input                  oe_b_n,
+	output [DATAWIDTH-1:0] q_b
+);
+
+wire [DATAWIDTH-1:0] out_a;
+wire [DATAWIDTH-1:0] out_b;
+
+assign q_a = oe_a_n ? {DATAWIDTH{1'b1}} : out_a;
+assign q_b = oe_b_n ? {DATAWIDTH{1'b1}} : out_b;
+
+altsyncram	altsyncram_component (
+			.address_a (address_a),
+			.address_b (address_b),
+			.clock0 (clock),
+			.data_a (data_a),
+			.data_b (data_b),
+			.wren_a (wren_a),
+			.wren_b (wren_b),
+			.q_a (out_a),
+			.q_b (out_b),
+			.aclr0 (1'b0),
+			.aclr1 (1'b0),
+			.addressstall_a (1'b0),
+			.addressstall_b (1'b0),
+			.byteena_a (1'b1),
+			.byteena_b (1'b1),
+			.clock1 (1'b1),
+			.clocken0 (1'b1),
+			.clocken1 (1'b1),
+			.clocken2 (1'b1),
+			.clocken3 (1'b1),
+			.eccstatus (),
+			.rden_a (1'b1),
+			.rden_b (1'b1));
+defparam
+	altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
+	altsyncram_component.address_reg_b = "CLOCK0",
+	altsyncram_component.indata_reg_b = "CLOCK0",
+	altsyncram_component.numwords_a = NUMWORDS,
+	altsyncram_component.numwords_b = NUMWORDS,
+	altsyncram_component.widthad_a = ADDRWIDTH,
+	altsyncram_component.widthad_b = ADDRWIDTH,
+	altsyncram_component.width_a = DATAWIDTH,
+	altsyncram_component.width_b = DATAWIDTH,
+	altsyncram_component.width_byteena_a = 1,
+	altsyncram_component.width_byteena_b = 1,
+
+	altsyncram_component.init_file = MEM_INIT_FILE, 
+	altsyncram_component.clock_enable_input_a = "BYPASS",
+	altsyncram_component.clock_enable_input_b = "BYPASS",
+	altsyncram_component.clock_enable_output_a = "BYPASS",
+	altsyncram_component.clock_enable_output_b = "BYPASS",
+	altsyncram_component.intended_device_family = "Cyclone V",
+	altsyncram_component.lpm_type = "altsyncram",
+	altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+	altsyncram_component.outdata_aclr_a = "NONE",
+	altsyncram_component.outdata_aclr_b = "NONE",
+	altsyncram_component.outdata_reg_a = "UNREGISTERED",
+	altsyncram_component.outdata_reg_b = "UNREGISTERED",
+	altsyncram_component.power_up_uninitialized = "FALSE",
+	altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+	altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
+	altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ";
+
+
+endmodule
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/jupiter_ace.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/jupiter_ace.v
index 489f464b..80589310 100644
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/jupiter_ace.v	
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/jupiter_ace.v	
@@ -1,217 +1,230 @@
-`timescale 1ns / 1ps
-`default_nettype none
-
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    20:06:40 03/19/2011 
-// Design Name: 
-// Module Name:    jace_on_fpga 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
+//============================================================================
+//  Jupiter Ace main logic
+//  Copyright (C) 2018 Sorgelig
 //
-// Dependencies: 
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
 //
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
 //
-//////////////////////////////////////////////////////////////////////////////////
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
 
-module jupiter_ace (
-	input wire clk_65,
-   input wire clk_cpu,
-	input wire reset,
-	input wire ear,
-	output wire [7:0] filas,
-	input wire [4:0] columnas,
-	output wire video,
-	output wire hsync,
-	output wire vsync,
-   output wire mic,
-   output wire spk,
-   output wire [14:0] sd_addr,
-   input wire [7:0] sd_dout,
-   output wire [7:0] sd_din,
-   output wire sd_we,
-   output wire sd_rd,
-   input wire sd_ready
-	);
+module jupiter_ace
+(
+	input        clk,
+	input        ce_pix,
+	input        ce_cpu,
+	input        no_wait,
+	input        reset,
 
-	wire [7:0] DinZ80;
-	wire [7:0] DoutZ80;
-	wire [15:0] AZ80;
+	output [7:0] kbd_row,
+	input  [4:0] kbd_col,
+	output       video_out,
+	output       hsync,
+	output       vsync,
+	output       hblank,
+	output       vblank,
+	output reg   mic,
+	output reg   spk,
+
+	input        loader_en,
+	input [15:0] loader_addr,
+	input  [7:0] loader_data,
+	input        loader_wr
+);
+
+assign kbd_row = cpu_addr[15:8];
+
+wire [15:0]	addr   = loader_en ? loader_addr : cpu_addr;
+wire  [7:0] data   = loader_en ? loader_data : cpu_dout;
+wire        ram_we = loader_en ? loader_wr   : ~wr_n;
+
+wire rom_enable  = (~mreq_n | loader_en) && (addr[15:13] == 0);       // 0000 - 1FFF 8KB
+wire sram_enable = (~mreq_n | loader_en) && (addr[15:11] == 'b00100); // 2000 - 27FF 1KB * 2
+wire cram_enable = (~mreq_n | loader_en) && (addr[15:11] == 'b00101); // 2800 - 2FFF 1KB * 2
+wire uram_enable = (~mreq_n | loader_en) && (addr[15:12] == 'b0011);  // 3000 - 3FFF 1KB * 4
+wire xram_enable = (~mreq_n | loader_en) && (addr[15:14] == 'b01);    // 4000 - 7FFF 16KB
+wire eram_enable = (~mreq_n | loader_en) && (addr[15]);               // 8000 - FFFF 32KB
+
+wire wait_n = no_wait | ~(sram_enable | cram_enable) | hblank | vblank | ~addr[10]; // 2400 - 27FF, 2C00 - 2FFF
+
+always @(posedge clk) begin
+	if (~iorq_n & ~cpu_addr[0]) begin
+		if (~rd_n) spk <= 0;
+		if (~wr_n) {spk,mic} <= {1'b1,cpu_dout[3]};
+	end
+end
+
+wire [7:0] io_dout = {8{iorq_n|rd_n}} | (~cpu_addr[0] ? {3'b110, kbd_col} : (sram_data | cram_data));
+
+wire [9:0] sram_addr;
+wire [7:0] sram_data;
+wire [7:0] sram_dout;
+dpram #(10) sram
+(
+	.clock(clk),
+	.address_a(addr[9:0]),
+	.data_a(data),
+	.wren_a(ram_we & sram_enable),
+	.oe_a_n(~sram_enable),
+	.q_a(sram_dout),
+	.address_b(sram_addr),
+	.q_b(sram_data)
+);
+
+wire [9:0] cram_addr;
+wire [7:0] cram_data;
+dpram #(10) cram
+(
+	.clock(clk),
+	.address_a(addr[9:0]),
+	.data_a(data),
+	.wren_a(ram_we & cram_enable),
+	.address_b(cram_addr),
+	.q_b(cram_data)
+);
+
+wire [7:0] uram_dout;
+dpram #(10) uram
+(
+	.clock(clk),
+	.address_a(addr[9:0]),
+	.data_a(data),
+	.wren_a(ram_we & uram_enable),
+	.oe_a_n(~uram_enable),
+	.q_a(uram_dout)
+);
+
+wire [7:0] xram_dout;
+dpram #(14) xram
+(
+	.clock(clk),
+	.address_a(addr[13:0]),
+	.data_a(data),
+	.wren_a(ram_we & xram_enable),
+	.oe_a_n(~xram_enable),
+	.q_a(xram_dout)
+);
+
+wire [7:0] eram_dout;
+dpram #(14) eram//15
+(
+	.clock(clk),
+	.address_a(addr[13:0]),
+	.data_a(data),
+	.wren_a(ram_we & eram_enable),
+	.oe_a_n(~eram_enable),
+	.q_a(eram_dout)
+);
+
+wire [7:0] rom_dout;
+dpram #(.ADDRWIDTH(13), .MEM_INIT_FILE("ace.mif")) rom
+(
+	.clock(clk),
+	.address_a(cpu_addr[12:0]),
+	.oe_a_n(~rom_enable),
+	.q_a(rom_dout)
+);
+
+wire  [7:0] cpu_dout;
+wire [15:0] cpu_addr;
+wire        iorq_n, mreq_n, rd_n, wr_n, int_n;
+T80pa cpu
+(
+	.RESET_n(~(reset | loader_reset)),
+	.CLK(clk),
+	.CEN_p(ce_cpu),
+
+	.WAIT_n(wait_n),
+	.INT_n(vsync),
+	.MREQ_n(mreq_n),
+	.IORQ_n(iorq_n),
+	.RD_n(rd_n),
+	.WR_n(wr_n),
+	.A(cpu_addr),
+	.DI(rom_dout & sram_dout & uram_dout & xram_dout & eram_dout & io_dout),
+	.DO(cpu_dout),
+	.DIRSet(|regset),
+	.DIR(REG)
+);
+
+reg  [211:0] REG;  // IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
+reg    [1:0] regset = 0;
+reg          loader_reset;
+
+always @(posedge clk) begin
+	reg old_loader;
+	reg old_vsync;
 	
+	old_vsync <= vsync;
 
-	wire iorq_n, mreq_n, rd_n, wr_n, wait_n, int_n;
-   wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
-   wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
-   wire [7:0] sram_data, cram_data;
-   wire [9:0] sram_addr, cram_addr;
-    
-
-   wire enable_write_to_rom;
-   wire [7:0] dout_modulo_enable_write;
-   wire modulo_enable_write_oe;
-
-
-   assign filas = AZ80[15:8];
-
-   // Multiplexer
-   assign DinZ80 = (rom_enable == 1'b1)?        dout_rom :
-                   (sram_enable == 1'b1)?       dout_sram :
-                   (cram_enable == 1'b1)?       dout_cram :
-                   (uram_enable == 1'b1)?       dout_uram :
-                   (xram_enable == 1'b1)?       dout_xram :
-                   (eram_enable == 1'b1)?       dout_eram :
-                   (modulo_enable_write_oe == 1'b1)? dout_modulo_enable_write :
-                   (data_from_jace_oe == 1'b1)? data_from_jace :
-                                                sram_data | cram_data;  // By default, this is what the data bus sees
-
-	ram1k_dualport sram (
-       .clk(clk_65),
-       .ce(sram_enable),
-       .a1(AZ80[9:0]),
-	   .a2(sram_addr),
-	   .din(DoutZ80),
-	   .dout1(dout_sram),
-       .dout2(sram_data),
-	   .we(~wr_n)
-		);
-		
-	ram1k_dualport cram (
-       .clk(clk_65),
-       .ce(cram_enable),
-       .a1(AZ80[9:0]),
-	   .a2(cram_addr),
-	   .din(DoutZ80),
-	   .dout1(dout_cram),
-       .dout2(cram_data),
-	   .we(~wr_n)
-		);
-		
-	ram1k uram(
-		.clk(clk_65),
-        .ce(uram_enable),
-        .a(AZ80[9:0]),
-        .din(DoutZ80),
-        .dout(dout_uram),
-        .we(~wr_n)
-		);
-		
-	ram16k xram(
-		.clk(clk_65),
-        .ce(xram_enable),
-        .a(AZ80[13:0]),
-        .din(DoutZ80),
-        .dout(dout_xram),
-        .we(~wr_n)
-		);
-		
-assign sd_addr = AZ80[14:0];
-assign dout_eram = sd_dout;
-assign sd_din = DoutZ80;
-assign sd_we = ~wr_n;
-assign sd_rd = eram_enable;
-
-
-//	ram32k eram(//16k for now//todo 32k
-//		.clk(clk_65),
-//      .ce(eram_enable),
-//      .a(AZ80[13:0]),//14
-//      .din(DoutZ80),
-//      .dout(dout_eram),
-//      .we(~wr_n)
-//		);
-		
-//	rom the_rom(	
-//	   .clk(clk_65),
-//		.a(AZ80[12:0]),
-//		.dout(dout_rom)
-//		);
-		
-	rom2 the_rom(
-	   .clk(clk_65),
-      .ce(rom_enable),
-	   .a(AZ80[12:0]),
-      .din(DoutZ80),
-	   .dout(dout_rom),
-      .we(~wr_n & enable_write_to_rom)
-		);
-
-    io_write_to_rom modulo_habilitador_escrituras (
-       .clk(clk_65),
-        .a(AZ80),
-        .iorq_n(iorq_n),
-        .rd_n(rd_n),
-        .wr_n(wr_n),
-        .din(DoutZ80),
-        .dout(dout_modulo_enable_write),
-        .dout_oe(modulo_enable_write_oe),
-        .enable_write_to_rom(enable_write_to_rom)
-    );
-    
-	
-	tv80n cpu(
-		// Outputs
-		.m1_n(), 
-		.mreq_n(mreq_n), 
-		.iorq_n(iorq_n), 
-		.rd_n(rd_n), 
-		.wr_n(wr_n), 
-		.rfsh_n(), 
-		.halt_n(), 
-		.busak_n(), 
-		.A(AZ80), 
-		.dout(DoutZ80),
-		// Inputs
-		.di(DinZ80), 
-		.reset_n(reset), 
-		.clk(clk_cpu), 
-		.wait_n(wait_n), 
-		.int_n(int_n), 
-		.nmi_n(1'b1), 
-		.busrq_n(1'b1)
-        );
-        
-    glue glogic (
-        .clk(clk_65),
-        // CPU interface
-        .cpu_addr(AZ80),
-        .mreq_n(mreq_n),
-        .iorq_n(iorq_n),
-        .rd_n(rd_n),
-        .wr_n(wr_n),
-        .data_from_cpu(DoutZ80),
-        .data_to_cpu(data_from_jace),
-        .data_to_cpu_oe(data_from_jace_oe),
-        .wait_n(wait_n),
-        .int_n(int_n),
-        // CPU-RAM interface
-        .rom_enable(rom_enable),
-        .sram_enable(sram_enable),
-        .cram_enable(cram_enable),
-        .uram_enable(uram_enable),
-        .xram_enable(xram_enable),
-        .eram_enable(eram_enable),
-        // Screen RAM and Char RAM interface
-        .screen_addr(sram_addr),
-        .screen_data(sram_data),
-        .char_addr(cram_addr),
-        .char_data(cram_data),
-        // Devices
-        .kbdcols(columnas),
-        .ear(ear),
-        .spk(spk),
-        .mic(mic),
-        .video(video),
-        .hsync_pal(hsync),
-		  .vsync_pal(vsync)
-    );
-    
-
-endmodule
+	if(loader_en) begin
+		loader_reset <= 1;
+		regset <= 2'b11;
+		if(loader_wr && (loader_addr[15:8] == 8'h21) && !loader_addr[7]) begin
+			case(loader_addr[6:0])
+				'h00: REG[15:8]    <= loader_data; //f
+				'h01: REG[7:0]     <= loader_data; //a
+				'h04: REG[87:80]   <= loader_data; //c
+				'h05: REG[95:88]   <= loader_data; //b
+				'h08: REG[103:96]  <= loader_data; //e
+				'h09: REG[111:104] <= loader_data; //d
+				'h0C: REG[119:112] <= loader_data; //l
+				'h0D: REG[127:120] <= loader_data; //h
+				'h10: REG[135:128] <= loader_data; //xl
+				'h11: REG[143:136] <= loader_data; //xh
+				'h14: REG[199:192] <= loader_data; //yl
+				'h15: REG[207:200] <= loader_data; //yh
+				'h18: REG[55:48]   <= loader_data; //spl
+				'h19: REG[63:56]   <= loader_data; //sph
+				'h1C: REG[71:64]   <= loader_data; //pcl
+				'h1D: REG[79:72]   <= loader_data; //pch
+				'h20: REG[31:24]   <= loader_data; //f'
+				'h21: REG[23:16]   <= loader_data; //a'
+				'h24: REG[151:144] <= loader_data; //c'
+				'h25: REG[159:152] <= loader_data; //b' //EightyOne wrongly restores it to B register
+				'h28: REG[167:160] <= loader_data; //e'
+				'h29: REG[175:168] <= loader_data; //d'
+				'h2C: REG[183:176] <= loader_data; //l'
+				'h2D: REG[191:184] <= loader_data; //h'
+				'h30: REG[209:208] <= loader_data[1:0]; //im
+				'h34: REG[210]     <= loader_data[0];   //iff1
+				'h38: REG[211]     <= loader_data[0];   //iff2
+				'h3C: REG[39:32]   <= loader_data; //i
+				'h40: REG[47:40]   <= loader_data; //r
+			endcase
+		end
+	end
+	else begin
+		if(~old_vsync & vsync) loader_reset <= 0;
+		if(~loader_reset && regset) begin
+			regset <= regset - 1'd1;
+			if(REG[63:48] > loader_addr) begin
+				REG[63:48] <= 16'hFFFE; // bug in dump!
+			end
+		end
+	end
+end
 
+video video(
+	.clk(clk),
+	.ce_pix(ce_pix),
+	.sram_addr(sram_addr),
+	.sram_data(sram_data),
+	.cram_addr(cram_addr),
+	.cram_data(cram_data),
+	.video_out(video_out),
+	.hsync(hsync),
+	.vsync(vsync),
+	.hblank(hblank),
+	.vblank(vblank)
+);
+endmodule 
\ No newline at end of file
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/keyboard.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/keyboard.v
index e4f69fa6..ce47db4d 100644
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/keyboard.v	
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/keyboard.v	
@@ -1,632 +1,253 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    17:36:45 11/07/2015 
-// Design Name: 
-// Module Name:    keyboard
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
+//============================================================================
+//  Jupiter Ace keyboard
+//  Copyright (C) 2018 Sorgelig
 //
-// Dependencies: 
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
 //
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
 //
-//////////////////////////////////////////////////////////////////////////////////
-module keyboard(
-    input wire clk,
-    input wire clkps2,
-    input wire dataps2,
-    input wire [7:0] rows,
-    output wire [4:0] columns,
-    output reg kbd_reset,
-    output reg kbd_nmi,
-    output reg kbd_mreset
-    );
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
 
-    initial begin
-        kbd_reset = 1'b1;
-        kbd_nmi = 1'b1;
-        kbd_mreset = 1'b1;
-    end
+module keyboard
+(
+	input        reset,
+	input        clk_sys,
 
-   // Teclas no extendidas
-`define KEY_RELEASED 8'hf0
-`define KEY_EXTENDED 8'he0
-`define KEY_ESC 	8'h76
-`define KEY_F1 		8'h05
-`define KEY_F2 		8'h06
-`define KEY_F3 		8'h04
-`define KEY_F4 		8'h0C
-`define KEY_F5 		8'h03
-`define KEY_F6 		8'h0B
-`define KEY_F7 		8'h83
-`define KEY_F8 		8'h0A
-`define KEY_F9 		8'h01
-`define KEY_F10 	8'h09
-`define KEY_F11 	8'h78
-`define KEY_F12 	8'h07
+	input [10:0] ps2_key,
 
-`define KEY_BL 		8'h0E
-`define KEY_1 		8'h16
-`define KEY_2 		8'h1E
-`define KEY_3 		8'h26
-`define KEY_4 		8'h25
-`define KEY_5 		8'h2E
-`define KEY_6 		8'h36
-`define KEY_7 		8'h3D
-`define KEY_8 		8'h3E
-`define KEY_9 		8'h46
-`define KEY_0 		8'h45
-`define KEY_APOS 	8'h4E
-`define KEY_AEXC 	8'h55
-`define KEY_BKSP 	8'h66
+	input  [7:0] kbd_row,
+	output [4:0] kbd_col
+);
 
-`define KEY_TAB 	8'h0D
-`define KEY_Q 		8'h15
-`define KEY_W 		8'h1D
-`define KEY_E 		8'h24
-`define KEY_R 		8'h2D
-`define KEY_T 		8'h2C
-`define KEY_Y 		8'h35
-`define KEY_U 		8'h3C
-`define KEY_I 		8'h43
-`define KEY_O 		8'h44
-`define KEY_P 		8'h4D
-`define KEY_CORCHA 	8'h54
-`define KEY_CORCHC 	8'h5B
-`define KEY_ENTER 	8'h5A
+reg  [4:0] keys[7:0];
+wire       press_n = ~ps2_key[9];
 
-`define KEY_CPSLK 	8'h58
-`define KEY_A 		8'h1C
-`define KEY_S 		8'h1B
-`define KEY_D 		8'h23
-`define KEY_F 		8'h2B
-`define KEY_G 		8'h34
-`define KEY_H 		8'h33
-`define KEY_J 		8'h3B
-`define KEY_K 		8'h42
-`define KEY_L 		8'h4B
-`define KEY_NT 		8'h4C
-`define KEY_LLAVA 	8'h52
-`define KEY_LLAVC 	8'h5D
+// Output addressed row to ULA
+assign kbd_col = ({5{kbd_row[0]}} | keys[0])
+                &({5{kbd_row[1]}} | keys[1])
+                &({5{kbd_row[2]}} | keys[2])
+                &({5{kbd_row[3]}} | keys[3])
+                &({5{kbd_row[4]}} | keys[4])
+                &({5{kbd_row[5]}} | keys[5])
+                &({5{kbd_row[6]}} | keys[6])
+                &({5{kbd_row[7]}} | keys[7]);
 
-`define KEY_LSHIFT	8'h12
-`define KEY_LT 		8'h61
-`define KEY_Z 		8'h1A
-`define KEY_X 		8'h22
-`define KEY_C 		8'h21
-`define KEY_V 		8'h2A
-`define KEY_B 		8'h32
-`define KEY_N 		8'h31
-`define KEY_M 		8'h3A
-`define KEY_COMA 	8'h41
-`define KEY_PUNTO 	8'h49
-`define KEY_MENOS 	8'h4A
-`define KEY_RSHIFT	8'h59
+wire shift = ~keys[0][0];
 
-`define KEY_LCTRL 	8'h14
-`define KEY_LALT 	8'h11
-`define KEY_SPACE 	8'h29
+always @(posedge clk_sys) begin
+	reg old_reset = 0;
+	reg old_state;
 
-`define KEY_KP0 	8'h70
-`define KEY_KP1 	8'h69
-`define KEY_KP2 	8'h72
-`define KEY_KP3 	8'h7A
-`define KEY_KP4 	8'h6B
-`define KEY_KP5 	8'h73
-`define KEY_KP6 	8'h74
-`define KEY_KP7 	8'h6C
-`define KEY_KP8 	8'h75
-`define KEY_KP9 	8'h7D
-`define KEY_KPPUNTO 8'h71
-`define KEY_KPMAS 	8'h79
-`define KEY_KPMENOS 8'h7B
-`define KEY_KPASTER 8'h7C
+	old_state <= ps2_key[10];
 
-`define KEY_BLKNUM	8'h77
-`define KEY_BLKSCR 	8'h7E
+	old_reset <= reset;
+	if(~old_reset & reset)begin
+		keys[0] <= 5'b11111;
+		keys[1] <= 5'b11111;
+		keys[2] <= 5'b11111;
+		keys[3] <= 5'b11111;
+		keys[4] <= 5'b11111;
+		keys[5] <= 5'b11111;
+		keys[6] <= 5'b11111;
+		keys[7] <= 5'b11111;
+	end
 
-// Teclas extendidas (E0 + scancode)
-`define KEY_WAKEUP 	8'h5E
-`define KEY_SLEEP 	8'h3F
-`define KEY_POWER 	8'h37
-`define KEY_INS 	8'h70
-`define KEY_SUP 	8'h71
-`define KEY_HOME 	8'h6C
-`define KEY_END 	8'h69
-`define KEY_PGU 	8'h7D
-`define KEY_PGD 	8'h7A
-`define KEY_UP 		8'h75
-`define KEY_DOWN 	8'h72
-`define KEY_LEFT 	8'h6B
-`define KEY_RIGHT 	8'h74
-`define KEY_RCTRL 	8'h14
-`define KEY_ALTGR 	8'h11
-`define KEY_KPENTER 8'h5A
-`define KEY_KPSLASH 8'h4A
-`define KEY_PRTSCR 	8'h7C
+	if(old_state != ps2_key[10]) begin
+		case(ps2_key[7:0])
+			8'h12 : keys[0][0] <= press_n; // Left shift (CAPS SHIFT)
+			8'h59 : keys[0][0] <= press_n; // Right shift (CAPS SHIFT)
+			8'h14:  keys[0][1] <= press_n; // ctrl
+			8'h1a : keys[0][2] <= press_n; // Z
+			8'h22 : keys[0][3] <= press_n; // X
+			8'h21 : keys[0][4] <= press_n; // C
 
+			8'h1c : keys[1][0] <= press_n; // A
+			8'h1b : keys[1][1] <= press_n; // S
+			8'h23 : keys[1][2] <= press_n; // D
+			8'h2b : keys[1][3] <= press_n; // F
+			8'h34 : keys[1][4] <= press_n; // G
 
-    wire new_key_aval;
-    wire [7:0] scancode;
-    wire is_released;
-    wire is_extended;
+			8'h15 : keys[2][0] <= press_n; // Q
+			8'h1d : keys[2][1] <= press_n; // W
+			8'h24 : keys[2][2] <= press_n; // E
+			8'h2d : keys[2][3] <= press_n; // R
+			8'h2c : keys[2][4] <= press_n; // T
 
-    reg shift_pressed = 1'b0;
-    reg ctrl_pressed = 1'b0;
-    reg alt_pressed = 1'b0;
+			8'h16 : keys[3][0] <= press_n; // 1
+			8'h1e : keys[3][1] <= press_n; // 2
+			8'h26 : keys[3][2] <= press_n; // 3
+			8'h25 : keys[3][3] <= press_n; // 4
+			8'h2e : keys[3][4] <= press_n; // 5
 
-    ps2_port ps2_kbd (
-        .clk(clk),  // se recomienda 1 MHz <= clk <= 600 MHz
-        .enable_rcv(1'b1),  // habilitar la maquina de estados de recepcion
-        .ps2clk_ext(clkps2),
-        .ps2data_ext(dataps2),
-        .kb_interrupt(new_key_aval),  // a 1 durante 1 clk para indicar nueva tecla recibida
-        .scancode(scancode), // make o breakcode de la tecla
-        .released(is_released),  // soltada=1, pulsada=0
-        .extended(is_extended)  // extendida=1, no extendida=0
-    );
+			8'h45 : keys[4][0] <= press_n; // 0
+			8'h46 : keys[4][1] <= press_n; // 9
+			8'h3e : keys[4][2] <= press_n; // 8
+			8'h3d : keys[4][3] <= press_n; // 7
+			8'h36 : keys[4][4] <= press_n; // 6
 
-    reg [4:0] matrix[0:7];  // 40-key matrix keyboard
-    initial begin
-        matrix[0] = 5'b11111;  // C X Z SS CS
-        matrix[1] = 5'b11111;  // G F D S A
-        matrix[2] = 5'b11111;  // T R E W Q
-        matrix[3] = 5'b11111;  // 5 4 3 2 1
-        matrix[4] = 5'b11111;  // 6 7 8 9 0
-        matrix[5] = 5'b11111;  // Y U I O P
-        matrix[6] = 5'b11111;  // H J K L ENT
-        matrix[7] = 5'b11111;  // V B N M SP
-    end
+			8'h4d : keys[5][0] <= press_n; // P
+			8'h44 : keys[5][1] <= press_n; // O
+			8'h43 : keys[5][2] <= press_n; // I
+			8'h3c : keys[5][3] <= press_n; // U
+			8'h35 : keys[5][4] <= press_n; // Y
 
-    assign columns = (matrix[0] | { {8{rows[0]}} }) &
-                     (matrix[1] | { {8{rows[1]}} }) &
-                     (matrix[2] | { {8{rows[2]}} }) &
-                     (matrix[3] | { {8{rows[3]}} }) &
-                     (matrix[4] | { {8{rows[4]}} }) &
-                     (matrix[5] | { {8{rows[5]}} }) &
-                     (matrix[6] | { {8{rows[6]}} }) &
-                     (matrix[7] | { {8{rows[7]}} });
+			8'h5a : keys[6][0] <= press_n; // ENTER
+			8'h4b : keys[6][1] <= press_n; // L
+			8'h42 : keys[6][2] <= press_n; // K
+			8'h3b : keys[6][3] <= press_n; // J
+			8'h33 : keys[6][4] <= press_n; // H
+
+			8'h29 : keys[7][0] <= press_n; // SPACE
+			8'h3a : keys[7][1] <= press_n; // M
+			8'h31 : keys[7][2] <= press_n; // N
+			8'h32 : keys[7][3] <= press_n; // B
+			8'h2a : keys[7][4] <= press_n; // V
+
+			8'h6B : begin // Left (CAPS 5)
+					keys[0][0] <= press_n;
+					keys[3][4] <= press_n;
+				end
+			8'h72 : begin // Up (CAPS 6)
+					keys[0][0] <= press_n;
+					keys[4][3] <= press_n;
+				end
+			8'h75 : begin // Down (CAPS 7)
+					keys[0][0] <= press_n;
+					keys[4][4] <= press_n;
+				end
+			8'h74 : begin // Right (CAPS 8)
+					keys[0][0] <= press_n;
+					keys[4][2] <= press_n;
+				end
+
+			8'h66 : begin // Backspace (CAPS 0)
+					keys[0][0] <= press_n;
+					keys[4][0] <= press_n;
+				end
+			8'h76 : begin // Escape (CAPS SPACE)
+					keys[0][0] <= press_n;
+					keys[7][0] <= press_n;
+				end
+			8'h58 : begin // Caps Lock
+					keys[0][0] <= press_n;
+					keys[3][1] <= press_n;
+				end
+			8'h0D : begin // TAB
+					keys[0][0] <= press_n;
+					keys[3][0] <= press_n;
+				end
+
+			8'h41 : begin // , <
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[7][2] <= 1;
+						keys[2][3] <= 1;
+					end
+					else if(shift) keys[2][3] <= 0;
+					else keys[7][2] <= 0;
+				end
+			8'h49 : begin // . >
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[7][1] <= 1;
+						keys[2][4] <= 1;
+					end
+					else if(shift) keys[2][4] <= 0;
+					else keys[7][1] <= 0;
+				end
+			8'h4C : begin // ; :
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[5][1] <= 1;
+						keys[0][2] <= 1;
+					end
+					else if(shift) keys[0][2] <= 0;
+					else keys[5][1] <= 0;
+				end
+			8'h52 : begin // " '
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[5][0] <= 1;
+						keys[4][3] <= 1;
+					end
+					else if(shift) keys[4][3] <= 0;
+					else keys[5][0] <= 0;
+				end
+			8'h4A : begin // / ?
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[0][4] <= 1;
+						keys[7][4] <= 1;
+					end
+					else if(shift) keys[0][4] <= 0;
+					else keys[7][4] <= 0;
+				end
+			8'h4E : begin // - _
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[6][3] <= 1;
+						keys[4][0] <= 1;
+					end
+					else if(shift) keys[4][0] <= 0;
+					else keys[6][3] <= 0;
+				end
+			8'h55 : begin // = +
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[6][1] <= 1;
+						keys[6][2] <= 1;
+					end
+					else if(shift) keys[6][2] <= 0;
+					else keys[6][1] <= 0;
+				end
+			8'h54 : begin // [ {
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[5][4] <= 1;
+						keys[1][3] <= 1;
+					end
+					else if(shift) keys[1][3] <= 0;
+					else keys[5][4] <= 0;
+				end
+			8'h5B : begin // ] }
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[5][3] <= 1;
+						keys[1][4] <= 1;
+					end
+					else if(shift) keys[1][4] <= 0;
+					else keys[5][3] <= 0;
+				end
+			8'h5D : begin // \ |
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[1][2] <= 1;
+						keys[1][1] <= 1;
+					end
+					else if(shift) keys[1][1] <= 0;
+					else keys[1][2] <= 0;
+				end
+			8'h0E : begin // ~ *
+					keys[0][1] <= press_n;
+					if(press_n) begin
+						keys[1][0] <= 1;
+						keys[7][3] <= 1;
+					end
+					else if(shift) keys[7][3] <= 0;
+					else keys[1][0] <= 0;
+				end
+			default: ;
+		endcase
+	end
+end
 
-    always @(posedge clk) begin
-        if (new_key_aval == 1'b1) begin
-            case (scancode)
-                // Special and control keys
-                `KEY_LSHIFT,
-                `KEY_RSHIFT:
-                    shift_pressed <= ~is_released;
-                `KEY_LCTRL,
-                `KEY_RCTRL:
-                    begin
-                        ctrl_pressed <= ~is_released;
-                        if (is_extended)
-                            matrix[0][1] <= is_released;  // Right control = Symbol shift
-                        else
-                            matrix[0][0] <= is_released;  // Left control = Caps shift
-                    end
-                `KEY_LALT:
-                    alt_pressed <= ~is_released;
-                `KEY_KPPUNTO:
-                    if (ctrl_pressed && alt_pressed) begin
-                        kbd_reset <= is_released;
-                        if (is_released == 1'b0) begin
-                            matrix[0] <= 5'b11111;  // C X Z SS CS
-                            matrix[1] <= 5'b11111;  // G F D S A
-                            matrix[2] <= 5'b11111;  // T R E W Q
-                            matrix[3] <= 5'b11111;  // 5 4 3 2 1
-                            matrix[4] <= 5'b11111;  // 6 7 8 9 0
-                            matrix[5] <= 5'b11111;  // Y U I O P
-                            matrix[6] <= 5'b11111;  // H J K L ENT
-                            matrix[7] <= 5'b11111;  // V B N M SP
-                        end
-                    end                            
-                `KEY_F5:
-                    if (ctrl_pressed && alt_pressed)
-                        kbd_nmi <= is_released;
-                `KEY_ENTER:
-                    matrix[6][0] <= is_released;
-                `KEY_ESC:
-                    begin
-                        matrix[0][0] <= is_released;
-                        matrix[7][0] <= is_released;
-                    end
-                `KEY_BKSP:
-                    if (ctrl_pressed && alt_pressed) begin
-                        kbd_mreset <= is_released;                        
-                    end
-                    else begin
-                        matrix[0][0] <= is_released;
-                        matrix[4][0] <= is_released;
-                    end
-                `KEY_CPSLK:
-                    begin
-                        matrix[0][0] <= is_released;
-                        matrix[3][1] <= is_released;  // CAPS LOCK
-                    end
-                `KEY_F2:
-                    begin
-                        matrix[0][0] <= is_released;
-                        matrix[3][0] <= is_released;  // EDIT
-                    end
-                        
-                // Digits and puntuaction marks inside digits
-                `KEY_1:
-                    begin
-                        if (alt_pressed) begin
-                            matrix[0][1] <= is_released;
-                            matrix[1][1] <= is_released;  // |
-                        end
-                        else if (shift_pressed) begin
-                            matrix[0][1] <= is_released;
-                            matrix[3][0] <= is_released;  // !
-                        end
-                        else
-                            matrix[3][0] <= is_released;
-                        
-                    end
-                `KEY_2:
-                    begin
-                        if (alt_pressed) begin
-                            matrix[0][1] <= is_released;
-                            matrix[3][1] <= is_released;  // @
-                        end
-                        else if (shift_pressed) begin
-                            matrix[0][1] <= is_released;
-                            matrix[5][0] <= is_released;  // "
-                        end
-                        else
-                            matrix[3][1] <= is_released;
-                    end
-                `KEY_3:
-                    begin
-                        if (!shift_pressed)
-                            matrix[3][2] <= is_released;
-                        else begin
-                            matrix[0][1] <= is_released;
-                            matrix[3][2] <= is_released;  // #
-                        end
-                    end
-                `KEY_4:
-                    begin
-                        if (shift_pressed) begin
-                            matrix[0][1] <= is_released;
-                            matrix[3][3] <= is_released;  // $
-                        end
-                        else if (ctrl_pressed) begin
-                            matrix[0][0] <= is_released;
-                            matrix[3][3] <= is_released; // INV VIDEO
-                        end
-                        else
-                            matrix[3][3] <= is_released;                        
-                    end
-                `KEY_5:
-                    begin
-                        if (!shift_pressed)
-                            matrix[3][4] <= is_released;
-                        else begin
-                            matrix[0][1] <= is_released;
-                            matrix[3][4] <= is_released;  // %
-                        end
-                    end
-                `KEY_6:
-                    begin
-                        if (!shift_pressed)
-                            matrix[4][4] <= is_released;
-                        else begin
-                            matrix[0][1] <= is_released;
-                            matrix[4][4] <= is_released;  // &
-                        end
-                    end
-                `KEY_7:
-                    begin
-                        if (!shift_pressed)
-                            matrix[4][3] <= is_released;
-                        else begin
-                            matrix[0][1] <= is_released;
-                            matrix[7][4] <= is_released;  // /
-                        end
-                    end
-                `KEY_8:
-                    begin
-                        if (!shift_pressed)
-                            matrix[4][2] <= is_released;
-                        else begin
-                            matrix[0][1] <= is_released;
-                            matrix[4][2] <= is_released;  // (
-                        end
-                    end
-                `KEY_9:
-                    begin
-                        if (shift_pressed) begin
-                            matrix[0][1] <= is_released;
-                            matrix[4][1] <= is_released;  // )
-                        end
-                        else if (ctrl_pressed) begin
-                            matrix[0][0] <= is_released;
-                            matrix[4][1] <= is_released;
-                        end
-                        else
-                            matrix[4][1] <= is_released;
-                    end
-                `KEY_0:
-                    begin
-                        if (!shift_pressed)
-                            matrix[4][0] <= is_released;
-                        else begin
-                            matrix[0][1] <= is_released;
-                            matrix[6][1] <= is_released;  // =
-                        end
-                    end
-                    
-                // Alphabetic characters
-                `KEY_Z:
-                    begin
-                        matrix[0][2] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_X:
-                    begin
-                        matrix[0][3] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_C:
-                    begin
-                        matrix[0][4] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_A:
-                    begin
-                        matrix[1][0] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_S:
-                    begin
-                        matrix[1][1] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_D:
-                    begin
-                        matrix[1][2] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_F:
-                    begin
-                        matrix[1][3] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_G:
-                    begin
-                        matrix[1][4] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_Q:
-                    begin
-                        matrix[2][0] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_W:
-                    begin
-                        matrix[2][1] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_E:
-                    begin
-                        matrix[2][2] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_R:
-                    begin
-                        matrix[2][3] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_T:
-                    begin
-                        matrix[2][4] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_P:
-                    begin
-                        matrix[5][0] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_O:
-                    begin
-                        matrix[5][1] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_I:
-                    begin
-                        matrix[5][2] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_U:
-                    begin
-                        matrix[5][3] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_Y:
-                    begin
-                        matrix[5][4] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_L:
-                    begin
-                        matrix[6][1] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_K:
-                    begin
-                        matrix[6][2] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_J:
-                    begin
-                        matrix[6][3] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_H:
-                    begin
-                        matrix[6][4] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_M:
-                    begin
-                        matrix[7][1] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_N:
-                    begin
-                        matrix[7][2] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_B:
-                    begin
-                        matrix[7][3] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                `KEY_V:
-                    begin
-                        matrix[7][4] <= is_released;
-                        if (shift_pressed)
-                            matrix[0][0] <= is_released;
-                    end
-                    
-                // Symbols
-                `KEY_APOS:
-                    begin
-                        matrix[0][1] <= is_released;
-                        if (!shift_pressed)
-                            matrix[4][3] <= is_released;
-                        else
-                            matrix[0][4] <= is_released;  // ?
-                    end
-                `KEY_CORCHA:
-                    begin
-                        matrix[0][1] <= is_released;
-                        if (alt_pressed || shift_pressed)
-                            matrix[5][4] <= is_released;  // [
-                        else
-                            matrix[6][4] <= is_released;  // ^
-                    end
-                `KEY_CORCHC:
-                    begin
-                        matrix[0][1] <= is_released;
-                        if (shift_pressed)
-                            matrix[7][3] <= is_released;  // *
-                        else if (alt_pressed)
-                            matrix[5][3] <= is_released;  // ]
-                        else
-                            matrix[6][2] <= is_released;  // +
-                    end
-                `KEY_LLAVA:
-                    begin
-                        matrix[0][1] <= is_released;
-                        if (alt_pressed || shift_pressed)
-                            matrix[1][3] <= is_released;  // {
-                        else
-                            matrix[0][3] <= is_released; // pound
-                    end
-                `KEY_LLAVC:
-                    begin
-                        matrix[0][1] <= is_released;
-                        if (alt_pressed || shift_pressed)
-                            matrix[1][4] <= is_released;  // }
-                        else
-                            matrix[5][2] <= is_released;  // copyright
-                    end
-                `KEY_COMA:
-                    begin
-                        matrix[0][1] <= is_released;
-                        if (!shift_pressed)
-                            matrix[7][2] <= is_released;
-                        else
-                            matrix[5][1] <= is_released;  // ;
-                    end
-                `KEY_PUNTO:
-                    begin
-                        matrix[0][1] <= is_released;
-                        if (!shift_pressed)
-                            matrix[7][1] <= is_released;
-                        else
-                            matrix[0][2] <= is_released;  // :
-                    end
-                `KEY_MENOS:
-                    begin
-                        matrix[0][1] <= is_released;
-                        if (!shift_pressed)
-                            matrix[6][3] <= is_released;  //
-                        else
-                            matrix[4][0] <= is_released;  // _
-                    end
-                `KEY_LT:
-                    begin
-                        matrix[0][1] <= is_released;
-                        if (!shift_pressed)
-                            matrix[2][3] <= is_released;  // <
-                        else
-                            matrix[2][4] <= is_released;  // >
-                    end
-                `KEY_BL:
-                    begin
-                        matrix[0][1] <= is_released;
-                        matrix[1][2] <= is_released;  // \
-                    end       
-                `KEY_SPACE:
-                    matrix[7][0] <= is_released;
-                    
-                // Cursor keys
-                `KEY_UP:
-                    begin
-                        matrix[0][0] <= is_released;
-                        matrix[4][4] <= is_released;
-                    end
-                `KEY_DOWN:
-                    begin
-                        matrix[0][0] <= is_released;
-                        matrix[4][3] <= is_released;
-                    end
-                `KEY_LEFT:
-                    begin
-                        matrix[0][0] <= is_released;
-                        matrix[3][4] <= is_released;
-                    end
-                `KEY_RIGHT:
-                    begin
-                        matrix[0][0] <= is_released;
-                        matrix[4][2] <= is_released;
-                    end
-            endcase    
-        end
-    end
 endmodule
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v
index ab9ef8ad..40ced8f8 100644
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v	
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/mist_io.v	
@@ -5,6 +5,7 @@
 // http://code.google.com/p/mist-board/
 //
 // Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+// Copyright (c) 2015-2017 Sorgelig
 //
 // This source file is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published
@@ -61,13 +62,13 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
 	// SD config
 	input             sd_conf,
 	input             sd_sdhc,
-	output            img_mounted, // signaling that new image has been mounted
+	output      [1:0] img_mounted, // signaling that new image has been mounted
 	output reg [31:0] img_size,    // size of image in bytes
 
 	// SD block level access
 	input      [31:0] sd_lba,
-	input             sd_rd,
-	input             sd_wr,
+	input       [1:0] sd_rd,
+	input       [1:0] sd_wr,
 	output reg        sd_ack,
 	output reg        sd_ack_conf,
 
@@ -83,25 +84,27 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
 	output            ps2_mouse_clk,
 	output reg        ps2_mouse_data,
 
+	// ps2 alternative interface. 
+
+	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
+	output reg [10:0] ps2_key = 0,
+
+	// [24] - toggles with every event
+	output reg [24:0] ps2_mouse = 0,
+
 	// ARM -> FPGA download
-	input             ioctl_force_erase,
+	input             ioctl_ce,
 	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg        ioctl_erasing = 0,  // signal indicating an active erase
 	output reg  [7:0] ioctl_index,        // menu index used to upload the file
 	output reg        ioctl_wr = 0,
 	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
+	output reg  [7:0] ioctl_dout,
+	input             ioctl_wait
 );
 
-reg [7:0] b_data;
-reg [6:0] sbuf;
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [7:0] byte_cnt;   // counts bytes
 reg [7:0] but_sw;
 reg [2:0] stick_idx;
-
-reg    mount_strobe = 0;
+reg [1:0] mount_strobe = 0;
 assign img_mounted  = mount_strobe;
 
 assign buttons = but_sw[1:0];
@@ -109,160 +112,189 @@ assign switches = but_sw[3:2];
 assign scandoubler_disable = but_sw[4];
 assign ypbpr = but_sw[5];
 
-wire [7:0] spi_dout = { sbuf, SPI_DI};
-
 // this variant of user_io is for 8 bit cores (type == a4) only
 wire [7:0] core_type = 8'ha4;
 
 // command byte read by the io controller
-wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
+wire       drive_sel = sd_rd[1] | sd_wr[1];
+wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
+
+reg [7:0] cmd;
+reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
+reg [9:0] byte_cnt;   // counts bytes
 
 reg spi_do;
 assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
 
-// drive MISO only when transmitting core id
-always@(negedge SPI_SCK) begin
-	if(!CONF_DATA0) begin
-		// first byte returned is always core type, further bytes are 
-		// command dependent
-      if(byte_cnt == 0) begin
-		  spi_do <= core_type[~bit_cnt];
+reg [7:0] spi_data_out;
 
-		end else begin
-			case(cmd)
-				// reading config string
-				8'h14: begin
-					// returning a byte from string
-						if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
-							else spi_do <= 0;
-					end
+// SPI transmitter
+always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
 
-				// reading sd card status
-				8'h16: begin
-						if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
-						else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
-						else spi_do <= 0;
-					end
-
-				// reading sd card write data
-				8'h18:
-						spi_do <= b_data[~bit_cnt];
-
-				default:
-						spi_do <= 0;
-			endcase
-		end
-   end
-end
-
-reg b_wr2,b_wr3;
-always @(negedge clk_sys) begin
-	b_wr3      <= b_wr2;
-	sd_buff_wr <= b_wr3;
-end
+reg [7:0] spi_data_in;
+reg       spi_data_ready = 0;
 
 // SPI receiver
 always@(posedge SPI_SCK or posedge CONF_DATA0) begin
+	reg [6:0]  sbuf;
+	reg [31:0] sd_lba_r;
+	reg        drive_sel_r;
 
 	if(CONF_DATA0) begin
-		b_wr2 <= 0;
 	   bit_cnt <= 0;
 	   byte_cnt <= 0;
-		sd_ack <= 0;
-		sd_ack_conf <= 0;
-	end else begin
-		b_wr2 <= 0;
-
-		sbuf <= spi_dout[6:0];
+		spi_data_out <= core_type;
+	end
+	else
+	begin
 		bit_cnt <= bit_cnt + 1'd1;
-		if(bit_cnt == 5) begin
-			if (byte_cnt == 0) sd_buff_addr <= 0;
-			if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
-			if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
-		end
+		sbuf <= {sbuf[5:0], SPI_DI};
 
 		// finished reading command byte
       if(bit_cnt == 7) begin
+			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
+
+			spi_data_in <= {sbuf, SPI_DI};
+			spi_data_ready <= ~spi_data_ready;
 			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			if(byte_cnt == 0) begin
-				cmd <= spi_dout;
-
-				if(spi_dout == 8'h19) begin
-					sd_ack_conf  <= 1;
-					sd_buff_addr <= 0;
-				end
-				if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
-					sd_ack       <= 1;
-					sd_buff_addr <= 0;
-				end
-				if(spi_dout == 8'h18) b_data <= sd_buff_din;
-
-				mount_strobe <= 0;
-
-			end else begin
 			
-				case(cmd)
-					// buttons and switches
-					8'h01: but_sw <= spi_dout; 
-					8'h02: joystick_0 <= spi_dout;
-					8'h03: joystick_1 <= spi_dout;
+			spi_data_out <= 0;
+			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
+				// reading config string
+				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
 
-					// store incoming ps2 mouse bytes 
-					8'h04: begin
-							ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; 
-							ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-						end
+				// reading sd card status
+				8'h16: if(byte_cnt == 0) begin
+							spi_data_out <= sd_cmd;
+							sd_lba_r <= sd_lba;
+							drive_sel_r <= drive_sel;
+						 end else if (byte_cnt == 1) begin
+							spi_data_out <= drive_sel_r;
+						 end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
 
-					// store incoming ps2 keyboard bytes 
-					8'h05: begin
-							ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; 
-							ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-						end
-				
-					8'h15: status[7:0] <= spi_dout;
-				
-					// send SD config IO -> FPGA
-					// flag that download begins
-					// sd card knows data is config if sd_dout_strobe is asserted
-					// with sd_ack still being inactive (low)
-					8'h19,
-					// send sector IO -> FPGA
-					// flag that download begins
-					8'h17: begin
-							sd_buff_dout <= spi_dout;
-							b_wr2 <= 1;
-						end
+				// reading sd card write data
+				8'h18: spi_data_out <= sd_buff_din;
+			endcase
+		end
+	end
+end
 
-					8'h18: b_data <= sd_buff_din;
+reg [31:0] ps2_key_raw = 0;
+wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
+wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
 
-					// joystick analog
-					8'h1a: begin
-							// first byte is joystick index
-							if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
-							else if(byte_cnt == 2) begin
-								// second byte is x axis
-								if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
-									else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
-							end else if(byte_cnt == 3) begin
-								// third byte is y axis
-								if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
-									else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
-							end
-						end
+// transfer to clk_sys domain
+always@(posedge clk_sys) begin
+	reg old_ss1, old_ss2;
+	reg old_ready1, old_ready2;
+	reg [2:0] b_wr;
+	reg       got_ps2 = 0;
 
-					// notify image selection
-					8'h1c: mount_strobe <= 1;
+	old_ss1 <= CONF_DATA0;
+	old_ss2 <= old_ss1;
+	old_ready1 <= spi_data_ready;
+	old_ready2 <= old_ready1;
+	
+	sd_buff_wr <= b_wr[0];
+	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
+	b_wr <= (b_wr<<1);
 
-					// send image info
-					8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
-
-					// status, 32bit version
-					8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
-					default: ;
-				endcase
+	if(old_ss2) begin
+		got_ps2      <= 0;
+		sd_ack       <= 0;
+		sd_ack_conf  <= 0;
+		sd_buff_addr <= 0;
+		if(got_ps2) begin
+			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
+			if(cmd == 5) begin
+				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
+				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
+				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
+				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
 			end
 		end
 	end
+	else
+	if(old_ready2 ^ old_ready1) begin
+
+		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+
+		if(byte_cnt < 2) begin
+
+			if (cmd == 8'h19) sd_ack_conf  <= 1;
+			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
+			mount_strobe <= 0;
+
+			if(cmd == 5) ps2_key_raw <= 0;
+		end else begin
+		
+			case(cmd)
+				// buttons and switches
+				8'h01: but_sw <= spi_data_in; 
+				8'h02: joystick_0 <= spi_data_in;
+				8'h03: joystick_1 <= spi_data_in;
+
+				// store incoming ps2 mouse bytes 
+				8'h04: begin
+						got_ps2 <= 1;
+						case(byte_cnt)
+							2: ps2_mouse[7:0]   <= spi_data_in;
+							3: ps2_mouse[15:8]  <= spi_data_in;
+							4: ps2_mouse[23:16] <= spi_data_in;
+						endcase 
+						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
+						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
+					end
+
+				// store incoming ps2 keyboard bytes 
+				8'h05: begin
+						got_ps2 <= 1;
+						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
+						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
+						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
+					end
+			
+				8'h15: status[7:0] <= spi_data_in;
+			
+				// send SD config IO -> FPGA
+				// flag that download begins
+				// sd card knows data is config if sd_dout_strobe is asserted
+				// with sd_ack still being inactive (low)
+				8'h19,
+				// send sector IO -> FPGA
+				// flag that download begins
+				8'h17: begin
+						sd_buff_dout <= spi_data_in;
+						b_wr <= 1;
+					end
+
+				// joystick analog
+				8'h1a: begin
+						// first byte is joystick index
+						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
+						else if(byte_cnt == 3) begin
+							// second byte is x axis
+							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
+								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
+						end else if(byte_cnt == 4) begin
+							// third byte is y axis
+							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
+								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
+						end
+					end
+
+				// notify image selection
+				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
+
+				// send image info
+				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
+
+				// status, 32bit version
+				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
+				default: ;
+			endcase
+		end
+	end
 end
 
 
@@ -417,6 +449,8 @@ localparam UIO_FILE_TX      = 8'h53;
 localparam UIO_FILE_TX_DAT  = 8'h54;
 localparam UIO_FILE_INDEX   = 8'h55;
 
+reg        rdownload = 0;
+
 // data_io has its own SPI interface to the io controller
 always@(posedge SPI_SCK, posedge SPI_SS2) begin
 	reg  [6:0] sbuf;
@@ -426,15 +460,10 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
 
 	if(SPI_SS2) cnt <= 0;
 	else begin
-		rclk <= 0;
-
 		// don't shift in last bit. It is evaluated directly
 		// when writing to ram
 		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
 
-		// increase target address after write
-		if(rclk) addr <= addr + 1'd1;
-
 		// count 0-7 8-15 8-15 ... 
 		if(cnt < 15) cnt <= cnt + 1'd1;
 			else cnt <= 8;
@@ -446,18 +475,11 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
 		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
 			// prepare 
 			if(SPI_DI) begin
-				case(ioctl_index) 
-							0: addr <= 'h080000; // BOOT ROM
-						'h01: addr <= 'h000100; // ROM file
-						'h41: addr <= 'h000100; // COM file
-						'h81: addr <= 'h000000; // C00 file
-						'hC1: addr <= 'h010000; // EDD file
-					default: addr <= 'h100000; // FDD file
-				endcase
-				ioctl_download <= 1; 
+				addr <= 25'h080000;
+				rdownload <= 1; 
 			end else begin
 				addr_w <= addr;
-				ioctl_download <= 0;
+				rdownload <= 0;
 			end
 		end
 
@@ -465,7 +487,8 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
 		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
 			addr_w <= addr;
 			data_w <= {sbuf, SPI_DI};
-			rclk <= 1;
+			addr <= addr + 1'd1;
+			rclk <= ~rclk;
 		end
 
       // expose file (menu) index
@@ -473,60 +496,24 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
 	end
 end
 
-reg  [24:0] erase_mask;
-wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask;
-
+// transfer to ioctl_clk domain.
+// ioctl_index is set before ioctl_download, so it's stable already
 always@(posedge clk_sys) begin
 	reg        rclkD, rclkD2;
-	reg        old_force = 0;
-	reg  [5:0] erase_clk_div;
-	reg [24:0] end_addr;
-	reg        erase_trigger = 0;
 
-	rclkD    <= rclk;
-	rclkD2   <= rclkD;
-	ioctl_wr <= 0;
+	if(ioctl_ce& ~ioctl_wait) begin
+		ioctl_download <= rdownload;
 
-	if(rclkD & ~rclkD2) begin
-		ioctl_dout <= data_w;
-		ioctl_addr <= addr_w;
-		ioctl_wr   <= 1;
-	end
+		rclkD    <= rclk;
+		rclkD2   <= rclkD;
+		ioctl_wr <= 0;
 
-	if(ioctl_download) begin
-		old_force     <= 0;
-		ioctl_erasing <= 0;
-		erase_trigger <= (ioctl_index == 1);
-	end else begin
-
-		old_force <= ioctl_force_erase;
-
-		// start erasing
-		if(erase_trigger) begin
-			erase_trigger <= 0;
-			erase_mask    <= 'hFFFF;
-			end_addr      <= 'h0100;
-			erase_clk_div <= 1;
-			ioctl_erasing <= 1;
-		end else if((ioctl_force_erase & ~old_force)) begin
-			erase_trigger <= 0;
-			ioctl_addr    <= 'h1FFFFFF;
-			erase_mask    <= 'h1FFFFFF;
-			end_addr      <= 'h0050000;
-			erase_clk_div <= 1;
-			ioctl_erasing <= 1;
-		end else if(ioctl_erasing) begin
-			erase_clk_div <= erase_clk_div + 1'd1;
-			if(!erase_clk_div) begin
-				if(next_erase == end_addr) ioctl_erasing <= 0;
-				else begin
-					ioctl_addr <= next_erase;
-					ioctl_dout <= 0;
-					ioctl_wr   <= 1;
-				end
-			end
+		if(rclkD != rclkD2) begin
+			ioctl_dout <= data_w;
+			ioctl_addr <= addr_w;
+			ioctl_wr   <= 1;
 		end
 	end
 end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.qip b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.qip
index afd958be..aaef684a 100644
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.qip	
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.qip	
@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name IP_TOOL_VERSION "13.0"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.v b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.v
index 47bde791..0c5e50f4 100644
--- a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.v	
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/pll.v	
@@ -14,7 +14,7 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
 // ************************************************************
 
 
@@ -40,17 +40,11 @@ module pll (
 	areset,
 	inclk0,
 	c0,
-	c1,
-	c2,
-	c3,
 	locked);
 
 	input	  areset;
 	input	  inclk0;
 	output	  c0;
-	output	  c1;
-	output	  c2;
-	output	  c3;
 	output	  locked;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_off
@@ -60,26 +54,20 @@ module pll (
 // synopsys translate_on
 `endif
 
-	wire [4:0] sub_wire0;
-	wire  sub_wire3;
-	wire [0:0] sub_wire8 = 1'h0;
-	wire [2:2] sub_wire5 = sub_wire0[2:2];
-	wire [0:0] sub_wire4 = sub_wire0[0:0];
-	wire [3:3] sub_wire2 = sub_wire0[3:3];
-	wire [1:1] sub_wire1 = sub_wire0[1:1];
-	wire  c1 = sub_wire1;
-	wire  c3 = sub_wire2;
-	wire  locked = sub_wire3;
-	wire  c0 = sub_wire4;
-	wire  c2 = sub_wire5;
-	wire  sub_wire6 = inclk0;
-	wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
+	wire  sub_wire0;
+	wire [4:0] sub_wire1;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire  locked = sub_wire0;
+	wire [0:0] sub_wire2 = sub_wire1[0:0];
+	wire  c0 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
 
 	altpll	altpll_component (
 				.areset (areset),
-				.inclk (sub_wire7),
-				.clk (sub_wire0),
-				.locked (sub_wire3),
+				.inclk (sub_wire4),
+				.locked (sub_wire0),
+				.clk (sub_wire1),
 				.activeclock (),
 				.clkbad (),
 				.clkena ({6{1'b1}}),
@@ -119,18 +107,6 @@ module pll (
 		altpll_component.clk0_duty_cycle = 50,
 		altpll_component.clk0_multiply_by = 26,
 		altpll_component.clk0_phase_shift = "0",
-		altpll_component.clk1_divide_by = 54,
-		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.clk1_multiply_by = 13,
-		altpll_component.clk1_phase_shift = "0",
-		altpll_component.clk2_divide_by = 108,
-		altpll_component.clk2_duty_cycle = 50,
-		altpll_component.clk2_multiply_by = 13,
-		altpll_component.clk2_phase_shift = "0",
-		altpll_component.clk3_divide_by = 27,
-		altpll_component.clk3_duty_cycle = 50,
-		altpll_component.clk3_multiply_by = 104,
-		altpll_component.clk3_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 37037,
 		altpll_component.intended_device_family = "Cyclone III",
@@ -164,9 +140,9 @@ module pll (
 		altpll_component.port_scanread = "PORT_UNUSED",
 		altpll_component.port_scanwrite = "PORT_UNUSED",
 		altpll_component.port_clk0 = "PORT_USED",
-		altpll_component.port_clk1 = "PORT_USED",
-		altpll_component.port_clk2 = "PORT_USED",
-		altpll_component.port_clk3 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
 		altpll_component.port_clk4 = "PORT_UNUSED",
 		altpll_component.port_clk5 = "PORT_UNUSED",
 		altpll_component.port_clkena0 = "PORT_UNUSED",
@@ -205,17 +181,8 @@ endmodule
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "54"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "108"
-// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "26.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.500000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "3.250000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "104.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -236,42 +203,18 @@ endmodule
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "26"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "13"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "13"
-// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "104"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "26.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.50000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "3.25000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "104.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -294,20 +237,11 @@ endmodule
 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -316,18 +250,6 @@ endmodule
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "26"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "13"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "108"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "13"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27"
-// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "104"
-// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -360,9 +282,9 @@ endmodule
 // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
@@ -380,18 +302,12 @@ endmodule
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
 // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/sprom.vhd b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/video.sv b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/video.sv
new file mode 100644
index 00000000..e4b89236
--- /dev/null
+++ b/Computer_MiST/Jupiter Cantab - JupiterACE_MiST/rtl/video.sv	
@@ -0,0 +1,75 @@
+//============================================================================
+//  Jupiter Ace video
+//  Copyright (C) 2018 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+
+module video
+(
+	input         clk,
+	input         ce_pix,
+
+	output  [9:0] sram_addr,
+	input   [7:0] sram_data,
+	output  [9:0] cram_addr,
+	input   [7:0] cram_data,
+
+	output        video_out,
+	output reg    hsync,
+	output reg    vsync,
+	output reg    hblank,
+	output reg    vblank
+);
+
+assign sram_addr = {vcnt[7:3], hcnt[7:3]};
+assign cram_addr = {sram_data[6:0], vcnt[2:0]};
+assign video_out = pix[7] ^ inv;
+
+reg [8:0] hcnt;
+reg [8:0] vcnt;
+reg [7:0] pix;
+reg       inv;
+always @(posedge clk) begin
+	reg ven,hen;
+
+	if(ce_pix) begin
+		if (hcnt != 415) hcnt <= hcnt + 1'd1;
+		else begin
+			hcnt <= 0;
+			if (vcnt != 311) vcnt <= vcnt + 1'd1;
+			else vcnt <= 0;
+		end
+
+		if (hcnt == 308) hsync <= 0;
+		if (hcnt == 340) hsync <= 1;
+		if (hcnt == 000) hen = 1;
+		if (hcnt == 256) hen = 0;
+
+		if (vcnt == 248) vsync <= 0;
+		if (vcnt == 256) vsync <= 1;
+		if (vcnt == 000) ven = 1;
+		if (vcnt == 192) ven = 0;
+
+		hblank <= ~hen;
+		vblank <= ~ven;
+
+		pix <= {pix[6:0], 1'b0};
+		if (!hcnt[2:0] && ven && hen) pix <= cram_data;
+		if (!hcnt[2:0]) inv <= ven & hen & sram_data[7];
+	end
+end
+
+endmodule 
\ No newline at end of file
diff --git a/Computer_MiST/ORAO_MiST/db/Orao_MiST.db_info b/Computer_MiST/ORAO_MiST/db/Orao_MiST.db_info
new file mode 100644
index 00000000..cce0536c
--- /dev/null
+++ b/Computer_MiST/ORAO_MiST/db/Orao_MiST.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Mon Dec 31 01:30:50 2018
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/Release/mz80k_mist.rbf b/Computer_MiST/Sharp - MZ-80_MiST_New/Release/mz80k_mist.rbf
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/Release/mz80k_mist.rbf
rename to Computer_MiST/Sharp - MZ-80_MiST_New/Release/mz80k_mist.rbf
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/clean.bat b/Computer_MiST/Sharp - MZ-80_MiST_New/clean.bat
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/clean.bat
rename to Computer_MiST/Sharp - MZ-80_MiST_New/clean.bat
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.qpf b/Computer_MiST/Sharp - MZ-80_MiST_New/mz80k_mist.qpf
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.qpf
rename to Computer_MiST/Sharp - MZ-80_MiST_New/mz80k_mist.qpf
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.qsf b/Computer_MiST/Sharp - MZ-80_MiST_New/mz80k_mist.qsf
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.qsf
rename to Computer_MiST/Sharp - MZ-80_MiST_New/mz80k_mist.qsf
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.srf b/Computer_MiST/Sharp - MZ-80_MiST_New/mz80k_mist.srf
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.srf
rename to Computer_MiST/Sharp - MZ-80_MiST_New/mz80k_mist.srf
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/CPLD_74LS245.vhd b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/CPLD_74LS245.vhd
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/CPLD_74LS245.vhd
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/CPLD_74LS245.vhd
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/Color_Card.sv b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/Color_Card.sv
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/Color_Card.sv
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/Color_Card.sv
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/HighResCard.sv b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/HighResCard.sv
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/HighResCard.sv
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/HighResCard.sv
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS245.sv b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/TTL74LS245.sv
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS245.sv
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/TTL74LS245.sv
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS373.sv b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/TTL74LS373.sv
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS373.sv
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/TTL74LS373.sv
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/build_id.tcl b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/build_id.tcl
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/build_id.tcl
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/build_id.tcl
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/build_id.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/build_id.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/build_id.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/build_id.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/cg_rom.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/cg_rom.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/cg_rom.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/cg_rom.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/fz80.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/fz80.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/fz80.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/fz80.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/fz80c.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/fz80c.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/fz80c.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/fz80c.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/hq2x.sv b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/hq2x.sv
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/hq2x.sv
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/hq2x.sv
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/i8253.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/i8253.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/i8253.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/i8253.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/i8255.vhd b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/i8255.vhd
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/i8255.vhd
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/i8255.vhd
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/keymatrix.vhd b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/keymatrix.vhd
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/keymatrix.vhd
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/keymatrix.vhd
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/mist_io.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/mist_io.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/mist_io.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/mist_io.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/monrom.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/monrom.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/monrom.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/monrom.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/mz80k_mist.sv b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/mz80k_mist.sv
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/mz80k_mist.sv
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/mz80k_mist.sv
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/mz80k_top.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/mz80k_top.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/mz80k_top.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/mz80k_top.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/osd.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/osd.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/osd.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/osd.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/pll.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/pll.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/pll.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/pll.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/ram2.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/ram2.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/ram2.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/ram2.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/80ktc.zip b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/80ktc.zip
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/80ktc.zip
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/80ktc.zip
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/CG.ROM b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/CG.ROM
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/CG.ROM
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/CG.ROM
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E Jap CG b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/MZ80K2E Jap CG
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E Jap CG
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/MZ80K2E Jap CG
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E Jap CG.zip b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/MZ80K2E Jap CG.zip
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E Jap CG.zip
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/MZ80K2E Jap CG.zip
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E ROM b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/MZ80K2E ROM
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E ROM
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/MZ80K2E ROM
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E ROM.zip b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/MZ80K2E ROM.zip
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E ROM.zip
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/MZ80K2E ROM.zip
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/Mon.hex b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/Mon.hex
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/Mon.hex
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/Mon.hex
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/cg.hex b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/cg.hex
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/cg.hex
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/cg.hex
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/cg_jp.HEX b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/cg_jp.HEX
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/cg_jp.HEX
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/cg_jp.HEX
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/cg_jp_hex.hex b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/cg_jp_hex.hex
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/cg_jp_hex.hex
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/cg_jp_hex.hex
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/cgrom.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/cgrom.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/cgrom.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/cgrom.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/combined_keymap.mif b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/combined_keymap.mif
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/combined_keymap.mif
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/combined_keymap.mif
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/mon_jp.HEX b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/mon_jp.HEX
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/mon_jp.HEX
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/mon_jp.HEX
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/mon_rom_jp.hex.hex b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/mon_rom_jp.hex.hex
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/mon_rom_jp.hex.hex
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/mon_rom_jp.hex.hex
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/mram.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/mram.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/mram.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/mram.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/newMon.hex b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/newMon.hex
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/newMon.hex
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/newMon.hex
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/ram.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/ram.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/roms/ram.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/roms/ram.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/scandoubler.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/scandoubler.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/scandoubler.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/scandoubler.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/sigma_delta_dac.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/sigma_delta_dac.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/sigma_delta_dac.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/sigma_delta_dac.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/sound.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/sound.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/sound.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/sound.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/spram.vhd b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/spram.vhd
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/spram.vhd
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/spram.vhd
diff --git a/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/sprom.vhd b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/vga.v b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/vga.v
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/vga.v
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/vga.v
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/video_mixer.sv b/Computer_MiST/Sharp - MZ-80_MiST_New/rtl/video_mixer.sv
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/rtl/video_mixer.sv
rename to Computer_MiST/Sharp - MZ-80_MiST_New/rtl/video_mixer.sv
diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/suc_hires2.jpg b/Computer_MiST/Sharp - MZ-80_MiST_New/suc_hires2.jpg
similarity index 100%
rename from Computer_MiST/Sharp - MZ-80K_MiST/suc_hires2.jpg
rename to Computer_MiST/Sharp - MZ-80_MiST_New/suc_hires2.jpg