diff --git a/Arcade_MiST/Atari-Hardware/Centipede_MiST/Centipede.qsf b/Arcade_MiST/Atari-Hardware/Centipede_MiST/Centipede.qsf index 85e437f3..7c901b6e 100644 --- a/Arcade_MiST/Atari-Hardware/Centipede_MiST/Centipede.qsf +++ b/Arcade_MiST/Atari-Hardware/Centipede_MiST/Centipede.qsf @@ -148,7 +148,7 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # Incremental Compilation Assignments # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top @@ -157,4 +157,44 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end ENTITY(cent_top_mist) # ------------------------- +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CLOCK_27 +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0 +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DI +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_SCK +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_SS2 +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_SS3 +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to altera_reserved_tck +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to altera_reserved_tdi +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to altera_reserved_tdo +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to altera_reserved_tms +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to auto_stp_external_clock_0 +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp +set_global_assignment -name SLD_FILE "C:/Users/Harry Pothead/Desktop/Centipede_MiST/stp1_auto_stripped.stp" +set_global_assignment -name VHDL_FILE rtl/asteroids_pokey.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_space.sv set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Atari-Hardware/Centipede_MiST/Snapshot/Centipede(Sound needs some Resets).rbf b/Arcade_MiST/Atari-Hardware/Centipede_MiST/Snapshot/Centipede(Sound needs some Resets).rbf new file mode 100644 index 00000000..25c27580 Binary files /dev/null and b/Arcade_MiST/Atari-Hardware/Centipede_MiST/Snapshot/Centipede(Sound needs some Resets).rbf differ diff --git a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/asteroids_pokey.vhd b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/asteroids_pokey.vhd new file mode 100644 index 00000000..62475290 --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/asteroids_pokey.vhd @@ -0,0 +1,562 @@ +-- +-- A simulation model of Asteroids Deluxe hardware +-- Copyright (c) MikeJ - May 2004 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 002 return 00 on allpot when fast scan completed to fix self test +-- version 001 initial release (this version should be considered Beta +-- it seems to make all the right sort of sounds however ... ) +-- +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +--use work.pkg_asteroids.all; + +entity ASTEROIDS_POKEY is + port ( + ADDR : in std_logic_vector(3 downto 0); + DIN : in std_logic_vector(7 downto 0); + DOUT : out std_logic_vector(7 downto 0); + DOUT_OE_L : out std_logic; + RW_L : in std_logic; + CS : in std_logic; -- used as enable + CS_L : in std_logic; + -- + AUDIO_OUT : out std_logic_vector(7 downto 0); + -- + PIN : in std_logic_vector(7 downto 0); + ENA : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of ASTEROIDS_POKEY is + type array_8x8 is array (0 to 7) of std_logic_vector(7 downto 0); + type array_4x8 is array (1 to 4) of std_logic_vector(7 downto 0); + type array_4x4 is array (1 to 4) of std_logic_vector(3 downto 0); + type array_4x9 is array (1 to 4) of std_logic_vector(8 downto 0); + type array_2x17 is array (1 to 2) of std_logic_vector(16 downto 0); + type bool_4 is array (1 to 4) of boolean; + + signal we : std_logic; + signal oe : std_logic; + -- + signal ena_64k_15k : std_logic; + signal cnt_64k : std_logic_vector(4 downto 0) := (others => '0'); + signal ena_64k : std_logic; + signal cnt_15k : std_logic_vector(6 downto 0) := (others => '0'); + signal ena_15k : std_logic; + -- + signal poly4 : std_logic_vector(3 downto 0) := (others => '0'); + signal poly5 : std_logic_vector(4 downto 0) := (others => '0'); + signal poly9 : std_logic_vector(8 downto 0) := (others => '0'); + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + signal poly_17_9 : std_logic; + + -- registers + signal audf : array_4x8 := (x"00",x"00",x"00",x"00"); + signal audc : array_4x8 := (x"00",x"00",x"00",x"00"); + signal audctl : std_logic_vector(7 downto 0) := "00000000"; + signal stimer : std_logic_vector(7 downto 0); + signal skres : std_logic_vector(7 downto 0); + signal potgo : std_logic; + signal serout : std_logic_vector(7 downto 0); + signal irqen : std_logic_vector(7 downto 0); + signal skctls : std_logic_vector(7 downto 0); + signal reset : std_logic; + -- + signal kbcode : std_logic_vector(7 downto 0); + signal random : std_logic_vector(7 downto 0); + signal serin : std_logic_vector(7 downto 0); + signal irqst : std_logic_vector(7 downto 0); + signal skstat : std_logic_vector(7 downto 0); + -- + signal pot_fin : std_logic; + signal pot_cnt : std_logic_vector(7 downto 0); + signal pot_val : array_8x8; + signal pin_reg : std_logic_vector(7 downto 0); + signal pin_reg_gated : std_logic_vector(7 downto 0); + -- + signal chan_ena : std_logic_vector(4 downto 1); + signal tone_gen_div : std_logic_vector(4 downto 1); + signal tone_gen_cnt : array_4x8 := (others => (others => '0')); + signal tone_gen_div_mux : std_logic_vector(4 downto 1); + signal tone_gen_zero : std_logic_vector(4 downto 1); + signal tone_gen_zero_t : array_4x8 := (others => (others => '0')); + signal chan_done_load : std_logic_vector(4 downto 1) := (others => '0'); + -- + signal poly_sel : std_logic_vector(4 downto 1); + signal poly_sel_hp : std_logic_vector(4 downto 1); + signal poly_sel_hp_t1 : std_logic_vector(4 downto 1); + signal poly_sel_hp_reg : std_logic_vector(4 downto 1); + signal tone_gen_final : std_logic_vector(4 downto 1) := (others => '0'); +begin + + p_we : process(RW_L, CS_L, CS, ENA) + begin + we <= (not CS_L) and CS and (not RW_L) and ENA; + end process; + + p_oe : process(RW_L, CS_L, CS) + begin + oe <= (not CS_L) and CS and RW_L; + end process; + DOUT_OE_L <= not oe; + + p_ipreg : process + begin + wait until rising_edge(CLK); + -- in asteroids, these are dip switches + pin_reg <= PIN; + end process; + + p_dividers : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + ena_64k <= '0'; + if cnt_64k = "00000" then + cnt_64k <= "11011"; -- 28 - 1 + ena_64k <= '1'; + else + cnt_64k <= cnt_64k - "1"; + end if; + + ena_15k <= '0'; + if cnt_15k = "0000000" then + cnt_15k <= "1110001"; -- 114 - 1 + ena_15k <= '1'; + else + cnt_15k <= cnt_15k - "1"; + end if; + end if; + end process; + + p_ena_64k_15k : process(ena_64k, ena_15k, audctl) + begin + if (audctl(0) = '1') then + ena_64k_15k <= ena_15k; + else + ena_64k_15k <= ena_64k; + end if; + end process; + + p_poly : process + variable poly9_zero : std_logic; + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + if (ENA = '1') then + poly4 <= poly4(2 downto 0) & not (poly4(3) xor poly4(2)); + poly5 <= poly5(3 downto 0) & not (poly5(4) xor poly4(2)); -- used inverted + + -- not correct + poly9_zero := '0'; + if (poly9 = "000000000") then poly9_zero := '1'; end if; + poly9 <= poly9(7 downto 0) & (poly9(8) xor poly9(3) xor poly9_zero); + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + poly17 <= poly17(15 downto 0) & (poly17(16) xor poly17(2) xor poly17_zero); + + end if; + end process; + + p_random_mux : process(audctl, poly9, poly17) + begin + -- bit unnecessary this .... + for i in 0 to 7 loop + if (audctl(7) = '1') then -- 9 bit poly + random(i) <= poly9(8-i); + else + random(i) <= poly17(16-i); + end if; + end loop; + + if (audctl(7) = '1') then + poly_17_9 <= poly9(8); + else + poly_17_9 <= poly17(16); + end if; + end process; + + p_wdata : process + begin + wait until rising_edge(CLK); + potgo <= '0'; + + --if (reset = '1') then + -- no idea what the reset state is + --audf <= (others => (others => '0')); + --audc <= (others => (others => '0')); + --audctl <= x"00"; + --else + if (we = '1') then + case ADDR is + when x"0" => audf(1) <= DIN; + when x"1" => audc(1) <= DIN; + when x"2" => audf(2) <= DIN; + when x"3" => audc(2) <= DIN; + when x"4" => audf(3) <= DIN; + when x"5" => audc(3) <= DIN; + when x"6" => audf(4) <= DIN; + when x"7" => audc(4) <= DIN; + when x"8" => audctl <= DIN; + when x"9" => stimer <= DIN; + when x"A" => skres <= DIN; + when x"B" => potgo <= '1'; + --when x"C" => + when x"D" => serout <= DIN; + when x"E" => irqen <= DIN; + when x"F" => skctls <= DIN; + when others => null; + end case; + end if; + --end if; + end process; + + p_reset : process(skctls) + begin + -- chip in reset if bits 1..0 of skctls are both zero + reset <= '0'; + if (skctls(1 downto 0) = "00") then + reset <= '1'; + end if; + end process; + + p_rdata : process(oe, ADDR, pot_val, pin_reg_gated, kbcode, random, serin, irqst, skstat) + begin + DOUT <= x"00"; + if (oe = '1') then -- keep things quiet + case ADDR IS + when x"0" => DOUT <= pot_val(0); -- pot 0 + when x"1" => DOUT <= pot_val(1); -- pot 1 + when x"2" => DOUT <= pot_val(2); -- pot 2 + when x"3" => DOUT <= pot_val(3); -- pot 3 + when x"4" => DOUT <= pot_val(4); -- pot 4 + when x"5" => DOUT <= pot_val(5); -- pot 5 + when x"6" => DOUT <= pot_val(6); -- pot 6 + when x"7" => DOUT <= pot_val(7); -- pot 7 + when x"8" => DOUT <= pin_reg_gated;-- allpot + when x"9" => DOUT <= kbcode; + when x"A" => DOUT <= random; + when x"B" => DOUT <= x"FF"; + when x"C" => DOUT <= x"FF"; + when x"D" => DOUT <= serin; + when x"E" => DOUT <= irqst; + when x"F" => DOUT <= skstat; + when others => null; + end case; + end if; + end process; + + -- POT ANALOGUE IN UNTESTED !! + p_pot_cnt : process + begin + wait until rising_edge(CLK); + if (potgo = '1') then + pot_cnt <= x"00"; + elsif ((ena_15k = '1') or (skctls(2) = '1')) and (ENA = '1') then -- fast scan mode + pot_cnt <= pot_cnt + "1"; + end if; + end process; + + p_pot_comp : process + begin + wait until rising_edge(CLK); + if (reset = '1') then + pot_fin <= '1'; + else + if (potgo = '1') then + pot_fin <= '0'; + elsif (pot_cnt = x"E4") then -- 228 + pot_fin <= '1'; + end if; + end if; + end process; + + p_pot_val : process + begin + wait until rising_edge(CLK); + for i in 0 to 7 loop + if (pot_fin = '0') and (pin_reg(i) = '0') then + -- continue latching counter value until input reaches ViH threshold + pot_val(i) <= pot_cnt; + end if; + end loop; + end process; + + -- dump transistors + --PIN <= x"00" when (pot_fin = '1') else (others => 'Z'); + p_in_gate : process(pin_reg, reset) -- dump transistor fakeup + begin + pin_reg_gated <= pin_reg; + -- I think the datasheet lies about dump transistors being disabled + -- in fast scan mode, as the self test fails .... + if (reset = '1') or (pot_fin = '1') then --and (skctls(2) = '0')) + pin_reg_gated <= x"00"; + end if; + end process; + + p_tone_cnt_ena : process(audctl, ena_64k_15k, tone_gen_div) + variable chan_ena1, chan_ena3 : std_ulogic; + begin + + if (audctl(6) = '1') then + chan_ena1 := '1'; -- 1.5 MHz, + else + chan_ena1 := ena_64k_15k; + end if; + chan_ena(1) <= chan_ena1; + + if (audctl(4) = '1') then -- chan 1/2 joined + chan_ena(2) <= chan_ena1; + else + chan_ena(2) <= ena_64k_15k; + end if; + + if (audctl(5) = '1') then + chan_ena3 := '1'; -- 1.5 MHz, + else + chan_ena3 := ena_64k_15k; -- 64 KHz + end if; + chan_ena(3) <= chan_ena3; + + if (audctl(3) = '1') then -- chan 3/4 joined + chan_ena(4) <= chan_ena3; + else + chan_ena(4) <= ena_64k_15k; -- 64 KHz + end if; + end process; + + p_tone_generator_zero : process(tone_gen_cnt, chan_ena) + begin + for i in 1 to 4 loop + if (tone_gen_cnt(i) = "00000000") and (chan_ena(i) = '1') then + tone_gen_zero(i) <= '1'; + else + tone_gen_zero(i) <= '0'; + end if; + end loop; + end process; + + p_tone_generators : process + variable chan_load : std_logic_vector(4 downto 1); + variable chan_dec : std_logic_vector(4 downto 1); + begin + -- quite tricky this .. but I think it does the correct stuff + -- bet this is not how is was done originally ! + -- + -- nasty frig to easily get exact chip behaviour in high speed mode + -- fout = fin / 2(audf + n) when n=4 or 7 in 16 bit mode + wait until rising_edge(CLK); + if (ENA = '1') then + tone_gen_div <= "0000"; + + if (audctl(4) = '1') then -- chan 1/2 joined + chan_load(1) := '0'; + chan_load(2) := '0'; + if (tone_gen_zero_t(1)(5) = '1') and (tone_gen_zero_t(2)(5) = '1') and (chan_done_load(1) = '0') then + chan_load(1) := '1'; + chan_load(2) := '1'; + end if; + chan_dec(1) := '1'; + chan_dec(2) := tone_gen_zero(1); + else + chan_load(1) := tone_gen_zero_t(1)(2) and not chan_done_load(1); + chan_load(2) := tone_gen_zero_t(2)(2) and not chan_done_load(2); + + chan_dec(1) := '1'; + chan_dec(2) := '1'; + end if; + + if (audctl(3) = '1') then -- chan 1/2 joined + chan_load(3) := '0'; + chan_load(4) := '0'; + if (tone_gen_zero_t(3)(5) = '1') and (tone_gen_zero_t(4)(5) = '1') and (chan_done_load(3) = '0') then + chan_load(3) := '1'; + chan_load(4) := '1'; + end if; + chan_dec(3) := '1'; + chan_dec(4) := tone_gen_zero(3); + else + chan_load(3) := tone_gen_zero_t(3)(2) and not chan_done_load(3); + chan_load(4) := tone_gen_zero_t(4)(2) and not chan_done_load(4); + + chan_dec(3) := '1'; + chan_dec(4) := '1'; + end if; + + for i in 1 to 4 loop + + if (chan_load(i) = '1') then + chan_done_load(i) <= '1'; + tone_gen_div(i) <= '1'; + tone_gen_cnt(i) <= audf(i); + elsif (chan_dec(i) = '1') and (chan_ena(i) = '1') then + chan_done_load(i) <= '0'; + tone_gen_cnt(i) <= tone_gen_cnt(i) - "1"; + end if; + + tone_gen_div(i) <= chan_load(i); + tone_gen_zero_t(i)(7 downto 0) <= tone_gen_zero_t(i)(6 downto 0) & tone_gen_zero(i); + end loop; + + end if; + end process; + + p_tone_generator_mux : process(audctl, tone_gen_div) + begin + if (audctl(4) = '1') then -- chan 1/2 joined + tone_gen_div_mux(1) <= tone_gen_div(1); -- do they both waggle + tone_gen_div_mux(2) <= tone_gen_div(2); -- or do I mute chan 1? + else + tone_gen_div_mux(1) <= tone_gen_div(1); + tone_gen_div_mux(2) <= tone_gen_div(2); + end if; + + if (audctl(3) = '1') then -- chan 3/4 joined + tone_gen_div_mux(3) <= tone_gen_div(3); -- ditto + tone_gen_div_mux(4) <= tone_gen_div(4); + else + tone_gen_div_mux(3) <= tone_gen_div(3); + tone_gen_div_mux(4) <= tone_gen_div(4); + end if; + end process; + + p_poly_gating : process(audc, poly4, poly5, poly_17_9, tone_gen_div_mux) + variable filter_a : std_logic_vector(4 downto 1); + variable filter_b : std_logic_vector(4 downto 1); + begin + for i in 1 to 4 loop + if (audc(i)(7) = '0') then + filter_a(i) := poly5(4) and tone_gen_div_mux(i);-- 5 bit poly + else + filter_a(i) := tone_gen_div_mux(i); + end if; + + if (audc(i)(6) = '0') then + filter_b(i) := poly_17_9 and filter_a(i);-- 17 bit poly + else + filter_b(i) := poly4(3) and filter_a(i);-- 4 bit poly + end if; + + if (audc(i)(5) = '0') then + poly_sel(i) <= filter_b(i); + else + poly_sel(i) <= filter_a(i); + end if; + end loop; + end process; + + p_high_pass_filters : process(audctl, poly_sel, poly_sel_hp_reg) + begin + poly_sel_hp <= poly_sel; + + if (audctl(2) = '1') then + poly_sel_hp(1) <= poly_sel(1) xor poly_sel_hp_reg(1); + end if; + + if (audctl(1) = '1') then + poly_sel_hp(2) <= poly_sel(2) xor poly_sel_hp_reg(2); + end if; + end process; + + p_audio_out : process + begin + wait until rising_edge(CLK); + if (ENA = '1') then + for i in 1 to 4 loop + -- filter reg + if (tone_gen_div(3) = '1') then -- tone gen 1 clocked by gen 3 + poly_sel_hp_reg(1) <= poly_sel(1); + end if; + + if (tone_gen_div(4) = '1') then -- tone gen 2 clocked by gen 4 + poly_sel_hp_reg(2) <= poly_sel(2); + end if; + + poly_sel_hp_t1 <= poly_sel_hp; + + if (poly_sel_hp(i) = '1') and (poly_sel_hp_t1(i) = '0') then -- rising edge + tone_gen_final(i) <= not tone_gen_final(i); + end if; + end loop; + end if; + end process; + + p_op_mixer : process + variable vol : array_4x4; + variable sum12 : std_logic_vector(4 downto 0); + variable sum34 : std_logic_vector(4 downto 0); + variable sum : std_logic_vector(5 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + for i in 1 to 4 loop + if (audc(i)(4) = '1') then -- vol only + vol(i) := audc(i)(3 downto 0); + else + if (tone_gen_final(i) = '1') then + vol(i) := audc(i)(3 downto 0); + else + vol(i) := "0000"; + end if; + end if; + end loop; + + sum12 := ('0' & vol(1)) + ('0' & vol(2)); + sum34 := ('0' & vol(3)) + ('0' & vol(4)); + sum := ('0' & sum12) + ('0' & sum34); + + if (reset = '1') then + AUDIO_OUT <= "00000000"; + else + if (sum(5) = '0') then + AUDIO_OUT <= sum(4 downto 0) & "000"; + else -- clip + AUDIO_OUT <= "11111111"; + end if; + end if; + end if; + end process; + + -- keyboard / serial etc to do +end architecture RTL; diff --git a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/build_id.v b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/build_id.v index 772cae85..9106b2a5 100644 --- a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/build_id.v +++ b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/build_id.v @@ -1,2 +1,2 @@ `define BUILD_DATE "181123" -`define BUILD_TIME "201219" +`define BUILD_TIME "234234" diff --git a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/cent_top_mist.sv b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/cent_top_mist.sv index 216f40ad..93c22d84 100644 --- a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/cent_top_mist.sv +++ b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/cent_top_mist.sv @@ -33,13 +33,14 @@ localparam CONF_STR = { - wire clk24, clk12, clk6; +wire clk24, clk12, clk6, clk1p5; pll pll( .inclk0(CLOCK_27), .c0(clk24), .c1(clk12), - .c2(clk6) + .c2(clk6), + .c3(clk1p5) ); reg [3:0] reset_reg; @@ -144,7 +145,8 @@ sigma_delta_dac( //Note Cennected Joysticks breaks Controls centipede centipede( .clk_12mhz(clk12), - .reset(reset_reg[3] | status[0] | buttons[1] | status[6]), + .clk_1p5mhz(clk1p5), + .reset(/*reset_reg[3] |*/ status[0] | buttons[1] | status[6]), .playerinput_i(playerinput_i), .trakball_i(), // .joystick_i({joystick_0[1],joystick_0[0],joystick_0[3],joystick_0[2], joystick_1[1],joystick_1[0],joystick_1[3],joystick_1[2]}), diff --git a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/centipede.v b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/centipede.v index 1fdc330c..858ebc42 100644 --- a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/centipede.v +++ b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/centipede.v @@ -16,10 +16,11 @@ // //`define async_lr -//`define orig_phi0 +`define orig_phi0 module centipede( input clk_12mhz, + input clk_1p5mhz, input reset, input [9:0] playerinput_i, input [7:0] trakball_i, @@ -170,14 +171,14 @@ module centipede( wire [3:0] coloram_out; wire [3:0] coloram_rgbi; wire coloram_w_n; - reg coloren; + reg coloren; wire [1:0] rama_sel; wire [1:0] rama_hi; wire [1:0] rama_lo; wire [3:0] rama; - wire [5:0] audio; + wire [7:0] audio; // wire mob_n; @@ -960,7 +961,7 @@ hs_ram( // Audio output circuitry - +/* pokey_atosm pokey( .rst_i(mpu_reset), .clk_i(phi2), @@ -968,7 +969,7 @@ hs_ram( .dat_i(db_out[7:0]), .dat_o(pokey_out), .we_i(~rw_n), - .stb_i(~pokey_n), + .stb_i(1'b1 & ~pokey_n), .ack_o(), .irq(), .audout(audio), @@ -983,8 +984,22 @@ hs_ram( .serin(8'b0), .serin_rdy_i(1'b0), .serin_ack_o() - ); - + );*/ + +ASTEROIDS_POKEY ASTEROIDS_POKEY ( + .ADDR(ab[3:0]), + .DIN(db_out[7:0]), + .DOUT(pokey_out), + .DOUT_OE_L(), + .RW_L(rw_n), + .CS(~pokey_n), + .CS_L(1'b0), + .AUDIO_OUT(audio), + .PIN(8'b0), + .ENA(1'b1),//1.5m + .CLK(phi2)//6m + ); + // reg [7:0] last_pokey_rd; always @(posedge s_6mhz) @@ -1014,29 +1029,19 @@ hs_ram( wire gry0_or_1; assign gry0_or_1 = gry[1] | gry[0]; -// assign rama_sel = { coloram_n, gry0_or_1 }; -// -// assign rama = -// (rama_sel == 2'b00) ? { ab[3:0] } : -// (rama_sel == 2'b01) ? { ab[3:0] } : -// (rama_sel == 2'b10) ? { {gry0_or_1, 1'b1}, area[1:0] } : -// (rama_sel == 2'b11) ? { {gry0_or_1, 1'b1}, gry[1:0] } : -// 4'b0; + assign rama_sel = { coloram_n, gry0_or_1 }; + + assign rama = + (rama_sel == 2'b00) ? { ab[3:0] } : + (rama_sel == 2'b01) ? { ab[3:0] } : + (rama_sel == 2'b10) ? { {gry0_or_1, 1'b1}, area[1:0] } : + (rama_sel == 2'b11) ? { {gry0_or_1, 1'b1}, gry[1:0] } : + 4'b0; + + // assign rama = gry0_or_1 ? + // { {gry0_or_1, 1'b1}, gry[1:0] } : + // { {gry0_or_1, 1'b1}, area[1:0] }; - assign rama = gry0_or_1 ? - { {gry0_or_1, 1'b1}, gry[1:0] } : - { {gry0_or_1, 1'b1}, area[1:0] }; -/* -color_ram color_ram( - .clk_a(s_6mhz), - .clk_b(s_6mhz_n), - .reset(reset), - .addr_a(ab[3:0]), - .dout_a(coloram_out), - .din_a(db_out[3:0]), - .we_n_a(coloram_w_n), - .addr_b(rama), - .dout_b(coloram_rgbi));*/ dpram #( .addr_width_g(4), @@ -1067,7 +1072,8 @@ color_ram( assign sync_o = comp_sync; assign hsync_o = hsync; assign vsync_o = vsync; - assign audio_o = { 2'b0, audio }; + // assign audio_o = { 2'b0, audio };//original pokey + assign audio_o = { audio };//asteroids pokey assign hblank_o = hblank; assign vblank_o = vblank; diff --git a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/pll.v b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/pll.v index 683a7fcf..123a4f91 100644 --- a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/pll.v +++ b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/pll.v @@ -40,26 +40,30 @@ module pll ( inclk0, c0, c1, - c2); + c2, + c3); input inclk0; output c0; output c1; output c2; + output c3; wire [4:0] sub_wire0; - wire [0:0] sub_wire6 = 1'h0; - wire [2:2] sub_wire3 = sub_wire0[2:2]; - wire [0:0] sub_wire2 = sub_wire0[0:0]; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [3:3] sub_wire2 = sub_wire0[3:3]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; - wire c0 = sub_wire2; - wire c2 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + wire c3 = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; altpll altpll_component ( - .inclk (sub_wire5), + .inclk (sub_wire6), .clk (sub_wire0), .activeclock (), .areset (1'b0), @@ -110,6 +114,10 @@ module pll ( altpll_component.clk2_duty_cycle = 50, altpll_component.clk2_multiply_by = 2, altpll_component.clk2_phase_shift = "0", + altpll_component.clk3_divide_by = 18, + altpll_component.clk3_duty_cycle = 50, + altpll_component.clk3_multiply_by = 1, + altpll_component.clk3_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone IV E", @@ -145,7 +153,7 @@ module pll ( altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", altpll_component.port_clk2 = "PORT_USED", - altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_USED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", altpll_component.port_clkena0 = "PORT_UNUSED", @@ -185,12 +193,15 @@ endmodule // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "18" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "1.500000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -213,32 +224,40 @@ endmodule // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "1.50000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -263,15 +282,18 @@ endmodule // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -288,6 +310,10 @@ endmodule // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "18" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" @@ -322,7 +348,7 @@ endmodule // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -340,12 +366,14 @@ endmodule // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE diff --git a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/video_mixer.sv b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/video_mixer.sv index 22f27933..83da2ccd 100644 --- a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/video_mixer.sv +++ b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/video_mixer.sv @@ -181,11 +181,22 @@ osd osd .R_in(VGA_DE ? R_in[7:2] : 6'd0), .G_in(VGA_DE ? G_in[7:2] : 6'd0), .B_in(VGA_DE ? B_in[7:2] : 6'd0), - .R_out(VGA_R), - .G_out(VGA_G), - .B_out(VGA_B), +// .R_out(VGA_R), +// .G_out(VGA_G), +// .B_out(VGA_B), .HSync(hsync), .VSync(vsync) ); +vga_space vga_space +( + .*, + .ypbpr_full(1), + .ypbpr_en(ypbpr), + .red(R_out), + .green(G_out), + .blue(B_out) +); + + endmodule diff --git a/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/video_space.sv b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/video_space.sv new file mode 100644 index 00000000..bb70924e --- /dev/null +++ b/Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/video_space.sv @@ -0,0 +1,65 @@ + +module vga_space +( + input ypbpr_full, + input ypbpr_en, + + input [5:0] red, + input [5:0] green, + input [5:0] blue, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr_en ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr_en ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr_en ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; + + +endmodule