From 2c21f44565dbe75899d9e8a6ad450667d398c9e3 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Mon, 19 Apr 2021 15:12:44 +0200 Subject: [PATCH] Robotron: implement blitter slow mode --- .../rtl/robotron_cpu/robotron_cpu.vhd | 1 + .../Robotron Hardware/rtl/robotron_cpu/sc1.vhd | 14 +++++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/robotron_cpu.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/robotron_cpu.vhd index eaf101a9..e5b4d3ab 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/robotron_cpu.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/robotron_cpu.vhd @@ -808,6 +808,7 @@ begin port map( clk => clock, sc2 => blitter_sc2, + E_en => to_std_logic(clock_e_clear), reg_cs => blt_reg_cs, reg_data_in => blt_reg_data_in, diff --git a/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/sc1.vhd b/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/sc1.vhd index ce0f79eb..ea2e49cf 100644 --- a/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/sc1.vhd +++ b/Arcade_MiST/Williams 6809 rev.1 Hardware/Robotron Hardware/rtl/robotron_cpu/sc1.vhd @@ -35,6 +35,7 @@ entity sc1 is port( clk : in std_logic; sc2 : in std_logic; + E_en : in std_logic; reg_cs : in std_logic; reg_data_in : in std_logic_vector( 7 downto 0); @@ -99,6 +100,7 @@ architecture RTL of sc1 is signal y_count_next : std_logic_vector( 7 downto 0) := (others => '0'); signal xorval : std_logic_vector( 7 downto 0) := (others => '0'); + signal wait_slow : std_logic; begin -- SC1 had a bug so values had to be xored with 0X04, SC2 fixed the bug so no xor required @@ -124,7 +126,7 @@ begin ctrl_shift <= reg_ctrl(5); ctrl_solid <= reg_ctrl(4); ctrl_foreground <= reg_ctrl(3); - --ctrl_slow <= reg_ctrl(2); + ctrl_slow <= reg_ctrl(2); ctrl_span_dst <= reg_ctrl(1); ctrl_span_src <= reg_ctrl(0); @@ -161,6 +163,10 @@ begin process(clk) begin if rising_edge(clk) then + if E_en = '1' or ctrl_slow = '0' then + wait_slow <= '0'; + end if; + case state is when state_idle => if reg_cs = '1' and rs = "000" then @@ -180,7 +186,8 @@ begin end if; when state_src => - if blt_ack = '1' then + if blt_ack = '1' and wait_slow = '0' then + wait_slow <= '1'; if ctrl_shift = '0' then -- unshifted blt_src_data <= blt_data_in; @@ -193,7 +200,8 @@ begin end if; when state_dst => - if blt_ack = '1' then + if blt_ack = '1' and wait_slow = '0' then + wait_slow <= '1'; state <= state_src; if x_count_next < reg_width then