diff --git a/Arcade_MiST/Sega Zaxxon Hardware/README.txt b/Arcade_MiST/Sega Zaxxon Hardware/README.txt new file mode 100644 index 00000000..a5d13113 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/README.txt @@ -0,0 +1,300 @@ +-- Zaxxon port to MiST +-- no sound +-- need ZAXXON.ROM on the SD Card +-- +--------------------------------------------------------------------------------- +-- DE10_lite Top level for Zaxxon by Dar (darfpga@aol.fr) (23/11/2019) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Use zaxxon_de10_lite.sdc to compile (Timequest constraints) +-- /!\ +-- Don't forget to set device configuration mode with memory initialization +-- (Assignments/Device/Pin options/Configuration mode) +--------------------------------------------------------------------------------- +-- +-- release rev 00 : initial release +-- (23/11/2019) +--------------------------------------------------------------------------------- +-- +-- Main features : +-- PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection) +-- Audio pwm output @gpio pins 1/3 (beware voltage translation/protection) +-- +-- Video : TV 15kHz +-- Cocktail mode : Yes +-- Sound : No (atm) +-- +-- For hardware schematic see my other project : NES +-- +-- Uses 1 pll 24MHz from 50MHz +-- +-- Board key : +-- 0 : reset game +-- +-- Keyboard players inputs : +-- +-- F1 : Add coin +-- F2 : Start 1 player +-- F3 : Start 2 players + +-- SPACE : fire +-- RIGHT arrow : move right +-- LEFT arrow : move left +-- UP arrow : move up +-- DOWN arrow : move down +-- +-- F4 : flip screen (additional feature) +-- F5 : Service mode ?! (not tested) +-- F7 : uprigth/cocktail mode (required reset) + +-- +-- Other details : see zaxxon.vhd +-- For USB inputs and SGT5000 audio output see my other project: xevious_de10_lite +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +-- Zaxxon by Dar (darfpga@aol.fr) (23/11/2019) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- release rev 00 : initial release +-- (23/11/2019) +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 304 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- Video : TV 15kHz +-- Coctail mode : Yes +-- Sound : No (atm) + +-- Use with MAME roms from zaxxon.zip +-- +-- Use make_zaxxon_proms.bat to build vhd file from binaries +-- (CRC list included) + +-- Zaxxon (Gremlin/SEGA) Hardware caracteristics : +-- +-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram, +-- sprite data ram, I/O, sound board register and trigger. +-- 20Kx8bits program rom +-- +-- 3 graphic layers +-- +-- One char map 32x28 tiles +-- 2x2Kx8bits graphics rom 2bits/pixel +-- static layout color rom 16 color/tile +-- +-- One diagonal scrolling background map 8x8 tiles +-- 4x8Kx8bits tile map rom (10 bits code + 4bits color) +-- 3x8Kx8bits graphics rom 3bits/pixel +-- +-- 32 sprites, up to 8/scanline 32x32pixels with flip H/V +-- 6bits code + 2 bits flip h/v, 5 bits color +-- 3x8Kx8bits graphics rom 3bits/pixel +-- +-- general palette 256 colors 3red 3green 2blue +-- char 2bits/tile + 4bits color set/tile + 1bits global set +-- background 3bits/tile + 4 bits color set/tile + 1bits global set +-- sprites 3bits/sprite + 5 bits color set/sprite +-- +-- Working ram : 4Kx8bits +-- char ram : 1Kx8bits code, (+ static layout color rom) +-- sprites ram : 256x8bits + 32x9bits intermediate buffer + 256x8bits line buffer +-- + +-- SOUND : see zaxxon_sound_board.vhd + +--------------------------------------------------------------------------------- +-- Schematics remarks : IC board 834-0214 and 834-0257 or 834-0211 +-- some details are missing or seems to be wrong: +-- - sprite buffer addresses flip control seems to be incomplete +-- (fliping adresses both at read and write is useless !) +-- - diagonal scrolling seems to be incomplete (BCK on U52 pin 4 where from ?) +-- - 834-0211 sheet 6 of 9 : 74ls161 U26 at C-5 no ouput used ! +-- - 834-0211 sheet 7 of 9 : /128H, 128H and 256H dont agree with U21 Qc/Qd +-- output ! +-- +-- tips : +-- Background tiles scrolls over H (and V) but map rom output are latched +-- at fixed Hcnt position (4H^). Graphics rom ouput latch is scrolled over H. +-- +-- During visible area (hcnt(8) = 1) sprite data are transfered from sp_ram +-- to sp_online_ram. Only sprites visible on (next) line are transfered. So +-- 64 sprites are defined in sp_ram and only 8 can be transfered to +-- sp_online_ram. +-- +-- During line fly back (hcnt(8) = 0) sp_online_ram is read and sprite +-- graphics feed line buffer. Line buffer is then read starting from +-- visible line. +-- +-- Sprite data transfer is done at pixel rate : each sprite is 4 bytes data. +-- Visible area allows 64 sprites x 4 data (256 pixels) to be read, only 8 +-- sprites (the ones on next line) are transfered. +-- +-- Line buffer feed is done at twice pixel rate : 8 sprites x 32 pixels / 2 +-- (256/2 = 128 pixels = fly back area length). +-- +-- sp_online_ram is 9 bits wide. 9th bits is set during tranfer for actual +-- sprites data written. 9th bit is reset during fly back area after data +-- are read. So 9th bits are all set to 0s at start of next transfer. +-- +-- When feeding line buffer sprites graphic data are written only of no +-- graphics have been written previouly for that line. Line buffer pixels are +-- set to 0s after each pixel read during visible area. Thus line buffer is +-- fully cleared at start of next feeding. +-- +-- Global screen flip is fully managed at hardware level. This allow to +-- easily add an external flip screen feature. + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Fri Nov 29 21:07:56 2019 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ; +; Revision Name ; zaxxon_de10_lite ; +; Top-level Entity Name ; zaxxon_de10_lite ; +; Family ; MAX 10 ; +; Device ; 10M50DAF484C6GES ; +; Timing Models ; Preliminary ; +; Total logic elements ; 2,754 / 49,760 ( 6 % ) ; +; Total combinational functions ; 2,646 / 49,760 ( 5 % ) ; +; Dedicated logic registers ; 653 / 49,760 ( 1 % ) ; +; Total registers ; 653 ; +; Total pins ; 105 / 360 ( 29 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 867,616 / 1,677,312 ( 52 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + +--------------- +VHDL File list +--------------- + +de10_lite/max10_pll_24M.vhd Pll 24MHz from 50MHz altera mf + +rtl_dar/zaxxon_de10_lite.vhd Top level for de10_lite board +rtl_dar/zaxxon.vhd Main CPU and video boards logic + +rtl_T80_304/T80se.vhdT80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +rtl_T80_304/T80_Reg.vhd +rtl_T80_304/T80_Pack.vhd +rtl_T80_304/T80_MCode.vhd +rtl_T80_304/T80_ALU.vhd +rtl_T80_304/T80.vhd + +rtl_dar/kbd_joystick.vhd Keyboard key to player/coin input +rtl_dar/io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification) +rtl_dar/decodeur_7_seg.vhd 7 segments display decoder + +rtl_dar/proms/zaxxon_cpu.vhd CPU board PROMS +rtl_dar/proms/zaxxon_char_bits_2.vhd +rtl_dar/proms/zaxxon_char_bits_1.vhd +rtl_dar/proms/zaxxon_char_color.vhd +rtl_dar/proms/zaxxon_palette.vhd + +rtl_dar/proms/zaxxon_map_2.vhd Video board PROMS +rtl_dar/proms/zaxxon_map_1.vhd +rtl_dar/proms/zaxxon_sp_bits_3.vhd +rtl_dar/proms/zaxxon_sp_bits_2.vhd +rtl_dar/proms/zaxxon_sp_bits_1.vhd +rtl_dar/proms/zaxxon_bg_bits_3.vhd +rtl_dar/proms/zaxxon_bg_bits_2.vhd +rtl_dar/proms/zaxxon_bg_bits_1.vhd + +---------------------- +Quartus project files +---------------------- +de10_lite/zaxxon_de10_lite.sdc Timequest constraints file +de10_lite/zaxxon_de10_lite.qsf de10_lite settings (files,pins...) +de10_lite/zaxxon_de10_lite.qpf de10_lite project + +----------------------------- +Required ROMs (Not included) +----------------------------- +You need the following 17 ROMs binary files from zaxxon.zip (MAME) + +zaxxon_rom3d.u27 CRC 6e2b4a30 +zaxxon_rom2d.u28 CRC 1c9ea398 +zaxxon_rom1d.u29 CRC 1c123ef9 +zaxxon_rom14.u68 CRC 07bf8c52 +zaxxon_rom15.u69 CRC c215edcb +zaxxon_rom6.u113 CRC 6e07bb68 +zaxxon_rom5.u112 CRC 0a5bce6a +zaxxon_rom4.u111 CRC a5bf1465 +zaxxon_rom11.u77 CRC eaf0dd4b +zaxxon_rom12.u78 CRC 1c5369c7 +zaxxon_rom13.u79 CRC ab4e8a9a +zaxxon_rom8.u91 CRC 28d65063 +zaxxon_rom7.u90 CRC 6284c200 +zaxxon_rom10.u93 CRC a95e61fd +zaxxon_rom9.u92 CRC 7e42691f +mro16.u76 CRC 6cc6695b (or zaxxon.u98) +zaxxon.u72 CRC deaa21f7 + +------ +Tools +------ +You need to build vhdl files from the binary file : + - Unzip the roms file in the tools/zaxxon_unzip directory + - Double click (execute) the script tools/make_zaxxon_proms.bat to get the following 13 files + +zaxxon_cpu.vhd +zaxxon_char_bits_1.vhd +zaxxon_char_bits_2.vhd +zaxxon_bg_bits_1.vhd +zaxxon_bg_bits_2.vhd +zaxxon_bg_bits_3.vhd +zaxxon_sp_bits_1.vhd +zaxxon_sp_bits_2.vhd +zaxxon_sp_bits_3.vhd +zaxxon_map_1.vhd +zaxxon_map_2.vhd +zaxxon_palette.vhd +zaxxon_char_color.vhd + +*DO NOT REDISTRIBUTE THESE FILES* + +VHDL files are needed to compile and include roms into the project + +The script make_tron_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux. + +Source code of make_vhdl_prom.c is also delivered. + +--------------------------------- +Compiling for de10_lite +--------------------------------- +You can build the project with ROM image embeded in the sof file. +*DO NOT REDISTRIBUTE THESE FILES* + +3 steps + + - put the VHDL ROM files (.vhd) into the rtl_dar/proms directory + - build zaxxon_de10_lite + - program zaxxon_de10_lite.sof + +------------------------ +------------------------ +End of file +------------------------ diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qpf b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qpf new file mode 100644 index 00000000..1bd816c8 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 00:21:03 December 03, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "00:21:03 December 03, 2019" + +# Revisions + +PROJECT_REVISION = "Zaxxon" + diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf new file mode 100644 index 00000000..6106b3c3 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.qsf @@ -0,0 +1,227 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 13:14:18 November 17, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Timber_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY Zaxxon_MiST +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF + +# Power Estimation Assignments +# ============================ +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# Advanced I/O Timing Assignments +# =============================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ------------------------- +# start ENTITY(DoTron_MiST) + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(DoTron_MiST) +# ----------------------- +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp +set_global_assignment -name VERILOG_FILE rtl/pll_mist.v +set_global_assignment -name VHDL_FILE rtl/zaxxon.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv +set_global_assignment -name VHDL_FILE rtl/dpram.vhd +set_global_assignment -name SYSTEMVERILOG_FILE rtl/Zaxxon_MiST.sv +set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd +set_global_assignment -name QIP_FILE ../../common/mist/mist.qip +set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip +set_global_assignment -name SIGNALTAP_FILE output_files/zaxx.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.sdc b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.sdc new file mode 100644 index 00000000..33ffd42f --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/Zaxxon.sdc @@ -0,0 +1,134 @@ +## Generated SDC file "vectrex_MiST.out.sdc" + +## Copyright (C) 1991-2013 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition" + +## DATE "Sun Jun 24 12:53:00 2018" + +## +## DEVICE "EP3C25E144C8" +## + +# Clock constraints + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks -create_base_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# tsu/th constraints + +# tco constraints + +# tpd constraints + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]" +set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]" +#************************************************************** +# Create Generated Clock +#************************************************************** + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}] +set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}] + +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]] + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}] +set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}] + +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv b/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv new file mode 100644 index 00000000..5b38f7a8 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/Zaxxon_MiST.sv @@ -0,0 +1,292 @@ + +module Zaxxon_MiST( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27, + + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE +); + +`include "rtl/build_id.v" + +localparam CONF_STR = { + "ZAXXON;ROM;", + "O2,Rotate Controls,Off,On;", + "O34,Scanlines,Off,25%,50%,75%;", + "O5,Blend,Off,On;", + "O6,Flip,Off,On;", + "O7,Service,Off,On;", + "T0,Reset;", + "V,v1.0.",`BUILD_DATE +}; + +wire rotate = status[2]; +wire [1:0] scanlines = status[4:3]; +wire blend = status[5]; +wire flip = status[6]; +wire service = status[7]; + +assign LED = ~ioctl_downl; +assign SDRAM_CLK = clk_sd; +assign SDRAM_CKE = 1; +assign AUDIO_R = AUDIO_L; + +wire clk_sys, clk_sd; +wire pll_locked; +pll_mist pll( + .inclk0(CLOCK_27), + .c0(clk_sd),//36 + .c1(clk_sys),//24 + .locked(pll_locked) + ); + +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoublerD; +wire ypbpr; +wire [15:0] audio_r,audio_l; +wire hs, vs, cs, hb, vb; +wire blankn; +wire [2:0] g, r; +wire [1:0] b; +wire [14:0] rom_addr; +wire [15:0] rom_do; +wire [13:0] gfx_addr; +wire [15:0] gfx_do; +wire ioctl_downl; +wire [7:0] ioctl_index; +wire ioctl_wr; +wire [24:0] ioctl_addr; +wire [7:0] ioctl_dout; + +// ROM structure +// 00000-06FFF CPU ROM 28k u27-u28-u29-u29-u29 +// 07000-0EFFF Tiledata 32k u91-u90-u93-u92 +// 0FOOO-0F7FF char1 2k u68 +// 0F800-0FFFF char2 2k u69 +// 10000-05FFF bg 24k u113-u112-u111 +// 16000-1BFFF spr 24k u77-u78-u79 +// 1C000-1C0FF 256b u76 +// 1C100-1C1FF 256b u72 + +data_io data_io( + .clk_sys ( clk_sys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS2 ( SPI_SS2 ), + .SPI_DI ( SPI_DI ), + .ioctl_download( ioctl_downl ), + .ioctl_index ( ioctl_index ), + .ioctl_wr ( ioctl_wr ), + .ioctl_addr ( ioctl_addr ), + .ioctl_dout ( ioctl_dout ) +); + +wire [24:0] gfx_ioctl_addr = ioctl_addr - 16'h7000; + +reg port1_req, port2_req; +sdram sdram( + .*, + .init_n ( pll_locked ), + .clk ( clk_sd ), + + // port1 used for main CPU + .port1_req ( port1_req ), + .port1_ack ( ), + .port1_a ( ioctl_addr[23:1] ), + .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ), + .port1_we ( ioctl_downl ), + .port1_d ( {ioctl_dout, ioctl_dout} ), + .port1_q ( ), + + .cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]}), + .cpu1_q ( rom_do ), + + // port2 for gfx + .port2_req ( port2_req ), + .port2_ack ( ), + .port2_a ( {gfx_ioctl_addr[23:15], gfx_ioctl_addr[13:0]} ), + .port2_ds ( {gfx_ioctl_addr[14], ~gfx_ioctl_addr[14]} ), + .port2_we ( ioctl_downl ), + .port2_d ( {ioctl_dout, ioctl_dout} ), + .port2_q ( ), + + .gfx_addr ( gfx_addr ), + .gfx_q ( gfx_do ) +); + +always @(posedge clk_sys) begin + reg ioctl_wr_last = 0; + + ioctl_wr_last <= ioctl_wr; + if (ioctl_downl) begin + if (~ioctl_wr_last && ioctl_wr) begin + port1_req <= ~port1_req; + port2_req <= ~port2_req; + end + end +end + +reg reset = 1; +reg rom_loaded = 0; +always @(posedge clk_sd) begin + reg ioctl_downlD; + ioctl_downlD <= ioctl_downl; + + if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1; + reset <= status[0] | buttons[1] | ~rom_loaded; +end + +zaxxon zaxxon( + .clock_24(clk_sys), + .reset(reset), + + .video_r(r), + .video_g(g), + .video_b(b), + .video_blankn(blankn), + .video_hs(hs), + .video_vs(vs), + .video_csync(cs), + + .audio_out_r(audio_r), + .audio_out_l(audio_l), + + .coin1(btn_coin), + .coin2(btn_coin), + .start2(btn_two_players), + .start1(btn_one_player), + .left(m_left), + .right(m_right), + .up(m_up), + .down(m_down), + .fire(m_fire), + .service(service), + + .flip_screen(flip), + + .cpu_rom_addr ( rom_addr ), + .cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ), + .map_addr ( gfx_addr ), + .map_do ( gfx_do ), + + .dl_addr ( ioctl_addr[16:0] ), + .dl_data ( ioctl_dout ), + .dl_wr ( ioctl_wr ) +); + +mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video( + .clk_sys ( clk_sys ), + .SPI_SCK ( SPI_SCK ), + .SPI_SS3 ( SPI_SS3 ), + .SPI_DI ( SPI_DI ), + .R ( blankn ? r : 0 ), + .G ( blankn ? g : 0 ), + .B ( blankn ? {b,b[1]} : 0 ), + .HSync ( hs ), + .VSync ( vs ), + .VGA_R ( VGA_R ), + .VGA_G ( VGA_G ), + .VGA_B ( VGA_B ), + .VGA_VS ( VGA_VS ), + .VGA_HS ( VGA_HS ), + .ce_divider ( 1'b1 ), + .blend ( blend ), + .rotate ( {flip, rotate} ), + .scandoubler_disable(scandoublerD ), + .scanlines ( scanlines ), + .ypbpr ( ypbpr ) + ); + +user_io #( + .STRLEN(($size(CONF_STR)>>3))) +user_io( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_CLK (SPI_SCK ), + .SPI_SS_IO (CONF_DATA0 ), + .SPI_MISO (SPI_DO ), + .SPI_MOSI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable (scandoublerD ), + .ypbpr (ypbpr ), + .key_strobe (key_strobe ), + .key_pressed (key_pressed ), + .key_code (key_code ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #( + .C_bits(16)) +dac_l( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +wire m_up = ~rotate ? (flip ? btn_left | joystick_0[1] | joystick_1[1] : btn_right | joystick_0[0] | joystick_1[0]) : btn_up | joystick_0[3] | joystick_1[3]; +wire m_down = ~rotate ? (flip ? btn_right | joystick_0[0] | joystick_1[0] : btn_left | joystick_0[1] | joystick_1[1]) : btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = ~rotate ? (flip ? btn_down | joystick_0[2] | joystick_1[2] : btn_up | joystick_0[3] | joystick_1[3]) : btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = ~rotate ? (flip ? btn_up | joystick_0[3] | joystick_1[3] : btn_down | joystick_0[2] | joystick_1[2]) : btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +//reg btn_fire2 = 0; +//reg btn_fire3 = 0; +reg btn_coin = 0; +wire key_pressed; +wire [7:0] key_code; +wire key_strobe; + +always @(posedge clk_sys) begin + if(key_strobe) begin + case(key_code) + 'h75: btn_up <= key_pressed; // up + 'h72: btn_down <= key_pressed; // down + 'h6B: btn_left <= key_pressed; // left + 'h74: btn_right <= key_pressed; // right + 'h76: btn_coin <= key_pressed; // ESC + 'h05: btn_one_player <= key_pressed; // F1 + 'h06: btn_two_players <= key_pressed; // F2 +// 'h14: btn_fire3 <= key_pressed; // ctrl +// 'h11: btn_fire2 <= key_pressed; // alt + 'h29: btn_fire1 <= key_pressed; // Space + endcase + end +end + +endmodule diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/build_id.tcl b/Arcade_MiST/Sega Zaxxon Hardware/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/dpram.vhd b/Arcade_MiST/Sega Zaxxon Hardware/rtl/dpram.vhd new file mode 100644 index 00000000..284194c5 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/dpram.vhd @@ -0,0 +1,81 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- dpram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity dpram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk_a : in std_logic; + we_a : in std_logic := '0'; + addr_a : in std_logic_vector((aWidth-1) downto 0); + d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_a : out std_logic_vector((dWidth-1) downto 0); + + clk_b : in std_logic; + we_b : in std_logic := '0'; + addr_b : in std_logic_vector((aWidth-1) downto 0); + d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0'); + q_b : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of dpram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + signal addr_a_reg: std_logic_vector((aWidth-1) downto 0); + signal addr_b_reg: std_logic_vector((aWidth-1) downto 0); +begin + +-- ----------------------------------------------------------------------- + process(clk_a) + begin + if rising_edge(clk_a) then + if we_a = '1' then + ram(to_integer(unsigned(addr_a))) <= d_a; + end if; + q_a <= ram(to_integer(unsigned(addr_a))); + end if; + end process; + + process(clk_b) + begin + if rising_edge(clk_b) then + if we_b = '1' then + ram(to_integer(unsigned(addr_b))) <= d_b; + end if; + q_b <= ram(to_integer(unsigned(addr_b))); + end if; + end process; + +end architecture; + diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/gen_ram.vhd b/Arcade_MiST/Sega Zaxxon Hardware/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/pll_mist.v b/Arcade_MiST/Sega Zaxxon Hardware/rtl/pll_mist.v new file mode 100644 index 00000000..851e7663 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/pll_mist.v @@ -0,0 +1,337 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll_mist.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2014 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll_mist ( + inclk0, + c0, + c1, + locked); + + input inclk0; + output c0; + output c1; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 3, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 4, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 9, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 8, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/sdram.sv b/Arcade_MiST/Sega Zaxxon Hardware/rtl/sdram.sv new file mode 100644 index 00000000..2f65ee17 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/sdram.sv @@ -0,0 +1,323 @@ +// +// sdram.v +// +// sdram controller implementation for the MiST board +// https://github.com/mist-devel/mist-board +// +// Copyright (c) 2013 Till Harbaum +// Copyright (c) 2019 Gyorgy Szombathelyi +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module sdram ( + + // interface to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // two byte masks + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + + // cpu/chipset interface + input init_n, // init signal after FPGA config to initialize RAM + input clk, // sdram clock + + input port1_req, + output reg port1_ack, + input port1_we, + input [23:1] port1_a, + input [1:0] port1_ds, + input [15:0] port1_d, + output [15:0] port1_q, + + input [15:1] cpu1_addr, + output reg [15:0] cpu1_q, + + input port2_req, + output reg port2_ack, + input port2_we, + input [23:1] port2_a, + input [1:0] port2_ds, + input [15:0] port2_d, + output [15:0] port2_q, + + input [15:1] gfx_addr, + output reg [15:0] gfx_q +); + +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write + +localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz +localparam RFRSH_CYCLES = 10'd842; + +// --------------------------------------------------------------------- +// ------------------------ cycle state machine ------------------------ +// --------------------------------------------------------------------- + +/* + SDRAM state machine for 2 bank interleaved access + 1 word burst, CL2 +cmd issued registered + 0 RAS0 cas1 + 1 ras0 + 2 CAS0 data1 returned + 3 RAS1 cas0 + 4 ras1 + 5 CAS1 data0 returned +*/ + +localparam STATE_RAS0 = 3'd0; // first state in cycle +localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns) +localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3 +localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5 +localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7 +localparam STATE_READ1 = 3'd3; +localparam STATE_LAST = 3'd5; + +reg [2:0] t; + +always @(posedge clk) begin + t <= t + 1'd1; + if (t == STATE_LAST) t <= STATE_RAS0; +end + +// --------------------------------------------------------------------- +// --------------------------- startup/reset --------------------------- +// --------------------------------------------------------------------- + +// wait 1ms (32 8Mhz cycles) after FPGA config is done before going +// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) +reg [4:0] reset; +reg init = 1'b1; +always @(posedge clk, negedge init_n) begin + if(!init_n) begin + reset <= 5'h1f; + init <= 1'b1; + end else begin + if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; + init <= !(reset == 0); + end +end + +// --------------------------------------------------------------------- +// ------------------ generate ram control signals --------------------- +// --------------------------------------------------------------------- + +// all possible commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [3:0] sd_cmd; // current command sent to sd ram +reg [15:0] sd_din; +// drive control signals according to current command +assign SDRAM_nCS = sd_cmd[3]; +assign SDRAM_nRAS = sd_cmd[2]; +assign SDRAM_nCAS = sd_cmd[1]; +assign SDRAM_nWE = sd_cmd[0]; + +reg [24:1] addr_latch[2]; +reg [24:1] addr_latch_next[2]; +reg [15:1] addr_last[2]; +reg [15:1] addr_last2[2]; +reg [15:0] din_latch[2]; +reg [1:0] oe_latch; +reg [1:0] we_latch; +reg [1:0] ds[2]; + +localparam PORT_NONE = 2'd0; +localparam PORT_CPU1 = 2'd1; +localparam PORT_REQ = 2'd2; + +localparam PORT_GFX = 2'd1; + +reg [2:0] next_port[2]; +reg [2:0] port[2]; + +reg refresh; +reg [10:0] refresh_cnt; +wire need_refresh = (refresh_cnt >= RFRSH_CYCLES); + +// PORT1: bank 0,1 +always @(*) begin + if (refresh) begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end else if (port1_req ^ port1_ack) begin + next_port[0] = PORT_REQ; + addr_latch_next[0] = { 1'b0, port1_a }; + end else if (cpu1_addr != addr_last[PORT_CPU1]) begin + next_port[0] = PORT_CPU1; + addr_latch_next[0] = { 9'd0, cpu1_addr }; + end else begin + next_port[0] = PORT_NONE; + addr_latch_next[0] = addr_latch[0]; + end +end + +// PORT2: bank 2,3 +always @(*) begin + if (port2_req ^ port2_ack) begin + next_port[1] = PORT_REQ; + addr_latch_next[1] = { 1'b1, port2_a }; + end else if (gfx_addr != addr_last2[PORT_GFX]) begin + next_port[1] = PORT_GFX; + addr_latch_next[1] = { 1'b1, 8'd0, gfx_addr }; + end else begin + next_port[1] = PORT_NONE; + addr_latch_next[1] = addr_latch[1]; + end +end + +always @(posedge clk) begin + + // permanently latch ram data to reduce delays + sd_din <= SDRAM_DQ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + { SDRAM_DQMH, SDRAM_DQML } <= 2'b11; + sd_cmd <= CMD_NOP; // default: idle + refresh_cnt <= refresh_cnt + 1'd1; + + if(init) begin + // initialization takes place at the end of the reset phase + if(t == STATE_RAS0) begin + + if(reset == 15) begin + sd_cmd <= CMD_PRECHARGE; + SDRAM_A[10] <= 1'b1; // precharge all banks + end + + if(reset == 10 || reset == 8) begin + sd_cmd <= CMD_AUTO_REFRESH; + end + + if(reset == 2) begin + sd_cmd <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + SDRAM_BA <= 2'b00; + end + end + end else begin + // RAS phase + // bank 0,1 + if(t == STATE_RAS0) begin + addr_latch[0] <= addr_latch_next[0]; + port[0] <= next_port[0]; + { oe_latch[0], we_latch[0] } <= 2'b00; + + if (next_port[0] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[0][22:10]; + SDRAM_BA <= addr_latch_next[0][24:23]; + addr_last[next_port[0]] <= addr_latch_next[0][15:1]; + if (next_port[0] == PORT_REQ) begin + { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; + ds[0] <= port1_ds; + din_latch[0] <= port1_d; + end else begin + { oe_latch[0], we_latch[0] } <= 2'b10; + ds[0] <= 2'b11; + end + end + end + + // bank 2,3 + if(t == STATE_RAS1) begin + refresh <= 1'b0; + addr_latch[1] <= addr_latch_next[1]; + { oe_latch[1], we_latch[1] } <= 2'b00; + port[1] <= next_port[1]; + + if (next_port[1] != PORT_NONE) begin + sd_cmd <= CMD_ACTIVE; + SDRAM_A <= addr_latch_next[1][22:10]; + SDRAM_BA <= addr_latch_next[1][24:23]; + addr_last2[next_port[1]] <= addr_latch_next[1][15:1]; + if (next_port[1] == PORT_REQ) begin + { oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we }; + ds[1] <= port2_ds; + din_latch[1] <= port2_d; + end else begin + { oe_latch[1], we_latch[1] } <= 2'b10; + ds[1] <= 2'b11; + end + end + + if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin + refresh <= 1'b1; + refresh_cnt <= 0; + sd_cmd <= CMD_AUTO_REFRESH; + end + end + + // CAS phase + if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin + sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0]; + if (we_latch[0]) begin + SDRAM_DQ <= din_latch[0]; + port1_ack <= port1_req; + end + SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[0][24:23]; + end + + if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin + sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ; + { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1]; + if (we_latch[1]) begin + SDRAM_DQ <= din_latch[1]; + port2_ack <= port2_req; + end + SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge + SDRAM_BA <= addr_latch[1][24:23]; + end + + // Data returned + if(t == STATE_READ0 && oe_latch[0]) begin + case(port[0]) + PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end + PORT_CPU1: begin cpu1_q <= sd_din; end + default: ; + endcase; + end + if(t == STATE_READ1 && oe_latch[1]) begin + case(port[1]) + PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end + PORT_GFX: begin gfx_q <= sd_din; end + default: ; + endcase; + end + end +end + +endmodule diff --git a/Arcade_MiST/Sega Zaxxon Hardware/rtl/zaxxon.vhd b/Arcade_MiST/Sega Zaxxon Hardware/rtl/zaxxon.vhd new file mode 100644 index 00000000..73c43123 --- /dev/null +++ b/Arcade_MiST/Sega Zaxxon Hardware/rtl/zaxxon.vhd @@ -0,0 +1,1111 @@ +--------------------------------------------------------------------------------- +-- Zaxxon by Dar (darfpga@aol.fr) (23/11/2019) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- release rev 00 : initial release +-- (23/11/2019) +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 304 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Features : +-- Video : TV 15kHz +-- Coctail mode : Yes +-- Sound : No (atm) + +-- Use with MAME roms from zaxxon.zip +-- +-- Use make_zaxxon_proms.bat to build vhd file from binaries +-- (CRC list included) + +-- Zaxxon (Gremlin/SEGA) Hardware caracteristics : +-- +-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram, +-- sprite data ram, I/O, sound board register and trigger. +-- 20Kx8bits program rom +-- +-- 3 graphic layers +-- +-- One char map 32x28 tiles +-- 2x2Kx8bits graphics rom 2bits/pixel +-- static layout color rom 16 color/tile +-- +-- One diagonal scrolling background map 8x8 tiles +-- 4x8Kx8bits tile map rom (10 bits code + 4bits color) +-- 3x8Kx8bits graphics rom 3bits/pixel +-- +-- 32 sprites, up to 8/scanline 32x32pixels with flip H/V +-- 6bits code + 2 bits flip h/v, 5 bits color +-- 3x8Kx8bits graphics rom 3bits/pixel +-- +-- general palette 256 colors 3red 3green 2blue +-- char 2bits/tile + 4bits color set/tile + 1bits global set +-- background 3bits/tile + 4 bits color set/tile + 1bits global set +-- sprites 3bits/sprite + 5 bits color set/sprite +-- +-- Working ram : 4Kx8bits +-- char ram : 1Kx8bits code, (+ static layout color rom) +-- sprites ram : 256x8bits + 32x9bits intermediate buffer + 256x8bits line buffer +-- + +-- SOUND : see zaxxon_sound_board.vhd + +--------------------------------------------------------------------------------- +-- Schematics remarks : IC board 834-0214 and 834-0257 or 834-0211 +-- some details are missing or seems to be wrong: +-- - sprite buffer addresses flip control seems to be incomplete +-- (fliping adresses both at read and write is useless !) +-- - diagonal scrolling seems to be incomplete (BCK on U52 pin 4 where from ?) +-- - 834-0211 sheet 6 of 9 : 74ls161 U26 at C-5 no ouput used ! +-- - 834-0211 sheet 7 of 9 : /128H, 128H and 256H dont agree with U21 Qc/Qd +-- output ! +-- +-- tips : +-- Background tiles scrolls over H (and V) but map rom output are latched +-- at fixed Hcnt position (4H^). Graphics rom ouput latch is scrolled over H. +-- +-- During visible area (hcnt(8) = 1) sprite data are transfered from sp_ram +-- to sp_online_ram. Only sprites visible on (next) line are transfered. So +-- 64 sprites are defined in sp_ram and only 8 can be transfered to +-- sp_online_ram. +-- +-- During line fly back (hcnt(8) = 0) sp_online_ram is read and sprite +-- graphics feed line buffer. Line buffer is then read starting from +-- visible line. +-- +-- Sprite data transfer is done at pixel rate : each sprite is 4 bytes data. +-- Visible area allows 64 sprites x 4 data (256 pixels) to be read, only 8 +-- sprites (the ones on next line) are transfered. +-- +-- Line buffer feed is done at twice pixel rate : 8 sprites x 32 pixels / 2 +-- (256/2 = 128 pixels = fly back area length). +-- +-- sp_online_ram is 9 bits wide. 9th bits is set during tranfer for actual +-- sprites data written. 9th bit is reset during fly back area after data +-- are read. So 9th bits are all set to 0s at start of next transfer. +-- +-- When feeding line buffer sprites graphic data are written only of no +-- graphics have been written previouly for that line. Line buffer pixels are +-- set to 0s after each pixel read during visible area. Thus line buffer is +-- fully cleared at start of next feeding. +-- +-- Global screen flip is fully managed at hardware level. This allow to +-- easily add an external flip screen feature. +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity zaxxon is +port( + clock_24 : in std_logic; + reset : in std_logic; +-- tv15Khz_mode : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + video_clk : out std_logic; + video_csync : out std_logic; + video_blankn : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + + audio_out_l : out std_logic_vector(15 downto 0); + audio_out_r : out std_logic_vector(15 downto 0); + + coin1 : in std_logic; + coin2 : in std_logic; + start1 : in std_logic; + start2 : in std_logic; + + left : in std_logic; + right : in std_logic; + up : in std_logic; + down : in std_logic; + fire : in std_logic; + + left_c : in std_logic; + right_c : in std_logic; + up_c : in std_logic; + down_c : in std_logic; + fire_c : in std_logic; + + cocktail : in std_logic; + service : in std_logic; + flip_screen : in std_logic; + + cpu_rom_addr : out std_logic_vector(14 downto 0); + cpu_rom_do : in std_logic_vector(7 downto 0); + map_addr : out std_logic_vector(13 downto 0); + map_do : in std_logic_vector(15 downto 0); + + dl_addr : in std_logic_vector(16 downto 0); + dl_data : in std_logic_vector(7 downto 0); + dl_wr : in std_logic; + + dbg_cpu_addr : out std_logic_vector(15 downto 0) + ); +end zaxxon; + +architecture struct of zaxxon is + + signal reset_n : std_logic; + signal clock_vid : std_logic; + signal clock_vidn: std_logic; + signal clock_cnt : std_logic_vector(3 downto 0) := "0000"; + + signal hcnt : std_logic_vector(8 downto 0) := (others=>'0'); -- horizontal counter + signal vcnt : std_logic_vector(8 downto 0) := (others=>'0'); -- vertical counter + signal hflip : std_logic_vector(8 downto 0) := (others=>'0'); -- horizontal counter flip + signal vflip : std_logic_vector(8 downto 0) := (others=>'0'); -- vertical counter flip + signal hflip2 : std_logic_vector(8 downto 0) := (others=>'0'); -- horizontal counter flip + + signal hs_cnt, vs_cnt :std_logic_vector(9 downto 0) ; + signal hsync0, hsync1, hsync2, hsync3, hsync4 : std_logic; + signal top_frame : std_logic := '0'; + + signal pix_ena : std_logic; + signal cpu_ena : std_logic; + + signal cpu_addr : std_logic_vector(15 downto 0); + signal cpu_di : std_logic_vector( 7 downto 0); + signal cpu_do : std_logic_vector( 7 downto 0); + signal cpu_wr_n : std_logic; + signal cpu_rd_n : std_logic; + signal cpu_mreq_n : std_logic; + signal cpu_ioreq_n : std_logic; + signal cpu_irq_n : std_logic; + signal cpu_m1_n : std_logic; + +-- signal cpu_rom_do : std_logic_vector(7 downto 0); + + signal wram_we : std_logic; + signal wram_do : std_logic_vector(7 downto 0); + + signal ch_ram_addr: std_logic_vector(9 downto 0); + signal ch_ram_we : std_logic; + signal ch_ram_do : std_logic_vector(7 downto 0); + signal ch_ram_do_to_cpu: std_logic_vector(7 downto 0); -- registred ram data for cpu + + signal ch_code : std_logic_vector(7 downto 0); + signal ch_code_r : std_logic_vector(7 downto 0); + signal ch_attr : std_logic_vector(7 downto 0); + + signal ch_code_line : std_logic_vector(10 downto 0); + signal ch_bit_nb : integer range 0 to 7; + signal ch_graphx1_do : std_logic_vector( 7 downto 0); + signal ch_graphx2_do : std_logic_vector( 7 downto 0); + signal ch_vid : std_logic_vector( 1 downto 0); + + signal ch_color_addr : std_logic_vector(7 downto 0); + signal ch_color_do : std_logic_vector(7 downto 0); -- 4 bits only used + signal palette_addr : std_logic_vector(7 downto 0); + signal palette_do : std_logic_vector(7 downto 0); + + signal map_offset_h : std_logic_vector(11 downto 0); + signal map_offset_l1 : std_logic_vector( 7 downto 0); + signal map_offset_l2 : std_logic_vector( 7 downto 0); + +-- signal map_addr : std_logic_vector(13 downto 0); + signal map1_do : std_logic_vector( 7 downto 0); + signal map2_do : std_logic_vector( 7 downto 0); + + signal bg_graphics_addr : std_logic_vector(12 downto 0); + signal bg_graphics1_do : std_logic_vector( 7 downto 0); + signal bg_graphics2_do : std_logic_vector( 7 downto 0); + signal bg_graphics3_do : std_logic_vector( 7 downto 0); + signal bg_bit_nb : integer range 0 to 7; + signal bg_color_a : std_logic_vector(3 downto 0); + signal bg_color : std_logic_vector(3 downto 0); + signal bg_vid : std_logic_vector(2 downto 0); + signal bg_code_line : std_logic_vector(9 downto 0); + + signal sp_ram_addr : std_logic_vector(7 downto 0); + signal sp_ram_we : std_logic; + signal sp_ram_do : std_logic_vector(7 downto 0); + signal sp_ram_do_to_cpu : std_logic_vector(7 downto 0); + signal sp_ram_do_to_sp_machine : std_logic_vector(7 downto 0); + + signal sp_vcnt : std_logic_vector(7 downto 0); + signal sp_on_line : std_logic; + + signal sp_online_ram_we : std_logic; + signal sp_online_ram_addr : std_logic_vector(4 downto 0); + signal sp_online_ram_di : std_logic_vector(8 downto 0); + signal sp_online_ram_do : std_logic_vector(8 downto 0); + + signal vflip_r : std_logic_vector(8 downto 0); + signal sp_online_vcnt : std_logic_vector(7 downto 0); + signal sp_line : std_logic_vector(7 downto 0); + signal sp_code : std_logic_vector(7 downto 0); + signal sp_color : std_logic_vector(4 downto 0); + signal sp_color_r : std_logic_vector(4 downto 0); + + signal sp_code_line : std_logic_vector(12 downto 0); + signal sp_hflip : std_logic; + signal sp_vflip : std_logic; + + signal sp_graphics_addr : std_logic_vector(12 downto 0); + signal sp_graphics1_do : std_logic_vector( 7 downto 0); + signal sp_graphics2_do : std_logic_vector( 7 downto 0); + signal sp_graphics3_do : std_logic_vector( 7 downto 0); + + signal sp_ok : std_logic; + signal sp_bit_hpos : std_logic_vector(7 downto 0); + signal sp_bit_nb : integer range 0 to 7; + + signal sp_buffer_ram_addr : std_logic_vector(7 downto 0); + signal sp_buffer_ram_we : std_logic; + signal sp_buffer_ram_di : std_logic_vector(7 downto 0); + signal sp_buffer_ram_do : std_logic_vector(7 downto 0); + + signal sp_vid : std_logic_vector(7 downto 0); + + signal vblkn, vblkn_r : std_logic; + signal int_on : std_logic := '0'; + + signal flip_cpu : std_logic := '0'; + signal flip : std_logic := '0'; + signal ch_color_ref : std_logic := '0'; + signal bg_position : std_logic_vector(10 downto 0) := (others => '0'); + signal bg_color_ref : std_logic := '0'; + signal bg_enable : std_logic := '0'; + + signal p1_input : std_logic_vector(7 downto 0); + signal p2_input : std_logic_vector(7 downto 0); + signal sw1_input : std_logic_vector(7 downto 0); + signal sw2_input : std_logic_vector(7 downto 0); + signal gen_input : std_logic_vector(7 downto 0); + + signal coin1_r, coin1_mem, coin1_ena : std_logic := '0'; + signal coin2_r, coin2_mem, coin2_ena : std_logic := '0'; + + signal bg_graphics_1_we : std_logic; + signal bg_graphics_2_we : std_logic; + signal bg_graphics_bits_1_we : std_logic; + signal bg_graphics_bits_2_we : std_logic; + signal bg_graphics_bits_3_we : std_logic; + signal sp_graphics_bits_1_we : std_logic; + signal sp_graphics_bits_2_we : std_logic; + signal sp_graphics_bits_3_we : std_logic; + signal char_color_we : std_logic; + signal palette_we : std_logic; + +begin + +clock_vid <= clock_24; +clock_vidn <= not clock_24; +reset_n <= not reset; + +-- debug +process (reset, clock_vid) +begin +-- if rising_edge(clock_vid) and cpu_ena ='1' and cpu_mreq_n ='0' then + --dbg_cpu_addr <= cpu_addr; + if rising_edge(clock_vid) then + dbg_cpu_addr <= sp_buffer_ram_do & sp_graphics1_do; + end if; +end process; + +-- make enables clock from clock_vid +process (clock_vid, reset) +begin + if reset='1' then + clock_cnt <= (others=>'0'); + else + if rising_edge(clock_vid) then + if clock_cnt = "1111" then -- divide by 16 + clock_cnt <= (others=>'0'); + else + clock_cnt <= clock_cnt + 1; + end if; + end if; + end if; +end process; +-- _ _ _ _ _ _ _ _ _ _ _ +-- |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| | clock_vid 24MHz +-- ___ ___ ___ ___ ___ +-- ___| |___| |___| |___| |___| |__ clock_cnt(0) 12MHz +-- _______ _______ __ +-- _______| |_______| |_______| clock_cnt(1) 6MHz +-- ___ ___ ___ +-- ___| |___________| |___________| |__ pix_ena 6MHz +-- +-- _______ _______________ _______________ __ +-- _______|_______________|_______________|__ video +-- + +pix_ena <= '1' when clock_cnt(1 downto 0) = "01" else '0'; -- (6MHz) +cpu_ena <= '1' when hcnt(0) = '0' and pix_ena = '1' else '0'; -- (3MHz) + +--------------------------------------- +-- Video scanner 384x264 @6.083 MHz -- +-- display 256x224 -- +-- -- +-- line : 63.13us -> 15.84kHz -- +-- frame : 16.67ms -> 60.00Hz -- +--------------------------------------- +video_hs <= hsync0; + +process (reset, clock_vid) +begin + if reset='1' then + hcnt <= (others=>'0'); + vcnt <= (others=>'0'); + top_frame <= '0'; + else + if rising_edge(clock_vid) then + if pix_ena = '1' then + + -- main horizontal / vertical counters + hcnt <= hcnt + 1; + if hcnt = 511 then + hcnt <= std_logic_vector(to_unsigned(128,9)); + end if; + + if hcnt = 128+8+8 then + vcnt <= vcnt + 1; + if vcnt = 263 then + vcnt <= (others=>'0'); + top_frame <= not top_frame; + end if; + end if; + + -- set syncs position + if hcnt = 170 then -- tune screen H position here + hs_cnt <= (others => '0'); + if vcnt = 0 then video_vs <= '0'; end if; + if vcnt = 3 then video_vs <= '1'; end if; + if (vcnt = 248) then -- tune screen V position here + vs_cnt <= (others => '0'); + else + vs_cnt <= vs_cnt +1; + end if; + + else + hs_cnt <= hs_cnt + 1; + end if; + + -- blanking + video_blankn <= '0'; + if (hcnt >= 256+9-5 or hcnt < 128+9-5) and + vcnt >= 17 and vcnt < 240 then video_blankn <= '1';end if; + + -- build syncs pattern (composite) + if hs_cnt = 0 then hsync0 <= '0'; + elsif hs_cnt = 29 then hsync0 <= '1'; + end if; + + if hs_cnt = 0 then hsync1 <= '0'; + elsif hs_cnt = 14 then hsync1 <= '1'; + elsif hs_cnt = 192+ 0 then hsync1 <= '0'; + elsif hs_cnt = 192+14 then hsync1 <= '1'; + end if; + + if hs_cnt = 0 then hsync2 <= '0'; + elsif hs_cnt = 192-29 then hsync2 <= '1'; + elsif hs_cnt = 192 then hsync2 <= '0'; + elsif hs_cnt = 384-29 then hsync2 <= '1'; + end if; + + if hs_cnt = 0 then hsync3 <= '0'; + elsif hs_cnt = 14 then hsync3 <= '1'; + elsif hs_cnt = 192 then hsync3 <= '0'; + elsif hs_cnt = 384-29 then hsync3 <= '1'; + end if; + + if hs_cnt = 0 then hsync4 <= '0'; + elsif hs_cnt = 192-29 then hsync4 <= '1'; + elsif hs_cnt = 192 then hsync4 <= '0'; + elsif hs_cnt = 192+14 then hsync4 <= '1'; + end if; + + if vs_cnt = 1 then video_csync <= hsync1; + elsif vs_cnt = 2 then video_csync <= hsync1; + elsif vs_cnt = 3 then video_csync <= hsync1; + elsif vs_cnt = 4 and top_frame = '1' then video_csync <= hsync3; + elsif vs_cnt = 4 and top_frame = '0' then video_csync <= hsync1; + elsif vs_cnt = 5 then video_csync <= hsync2; + elsif vs_cnt = 6 then video_csync <= hsync2; + elsif vs_cnt = 7 and top_frame = '1' then video_csync <= hsync4; + elsif vs_cnt = 7 and top_frame = '0' then video_csync <= hsync2; + elsif vs_cnt = 8 then video_csync <= hsync1; + elsif vs_cnt = 9 then video_csync <= hsync1; + elsif vs_cnt = 10 then video_csync <= hsync1; + elsif vs_cnt = 11 then video_csync <= hsync0; + else video_csync <= hsync0; + end if; + + end if; + end if; + end if; +end process; + +--------------------------------- +-- players/dip switches inputs -- +--------------------------------- +p1_input <= "000" & fire & down & up & left & right ; +p2_input <= "000" & fire_c & down_c & up_c & left_c & right_c; +sw1_input <= cocktail&"111"&x"f"; -- cocktail->FF upright->7F +sw2_input <= x"33"; -- coin a/b 1c_1c +gen_input <= service & coin2_mem & coin1_mem & '0' & start2 & start1 & "00"; + +------------------------------------------ +-- cpu data input with address decoding -- +------------------------------------------ +cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"6" else -- 0000-5FFF + wram_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = x"6" else -- 6000-6FFF + ch_ram_do_to_cpu when cpu_mreq_n = '0' and (cpu_addr and x"E000") = x"8000" else -- video ram 8000-83FF + mirroring 1C00 + sp_ram_do_to_cpu when cpu_mreq_n = '0' and (cpu_addr and x"E000") = x"A000" else -- sprite ram A000-A0FF + mirroring 1F00 + p1_input when cpu_mreq_n = '0' and (cpu_addr and x"E703") = x"C000" else -- player 1 C000 + mirroring 18FC + p2_input when cpu_mreq_n = '0' and (cpu_addr and x"E703") = x"C001" else -- player 2 C001 + mirroring 18FC + sw1_input when cpu_mreq_n = '0' and (cpu_addr and x"E703") = x"C002" else -- switch 1 C002 + mirroring 18FC + sw2_input when cpu_mreq_n = '0' and (cpu_addr and x"E703") = x"C003" else -- switch 2 C003 + mirroring 18FC + gen_input when cpu_mreq_n = '0' and (cpu_addr and x"E700") = x"C100" else -- general C100 + mirroring 18FF + X"FF"; + +------------------------------------------------------------------------ +-- Coin registers +------------------------------------------------------------------------ +process (clock_vid, coin1_ena, coin2_ena) +begin + if coin1_ena = '0' then + coin1_mem <= '0'; + else + if rising_edge(clock_vid) then + coin1_r <= coin1; + if coin1 = '1' and coin1_r = '0' then coin1_mem <= coin1_ena; end if; + end if; + end if; + if coin2_ena = '0' then + coin2_mem <= '0'; + else + if rising_edge(clock_vid) then + coin2_r <= coin2; + if coin2 = '1' and coin2_r = '0' then coin2_mem <= coin2_ena; end if; + end if; + end if; +end process; + +------------------------------------------------------------------------ +-- Misc registers - interrupt set/enable +------------------------------------------------------------------------ +vblkn <= '0' when vcnt < 256 else '1'; + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + vblkn_r <= vblkn; + + if cpu_mreq_n = '0' and cpu_wr_n = '0' then + + if (cpu_addr and x"E707") = x"C000" then coin1_ena <= cpu_do(0); end if; -- C000 + mirroring 18F8 + if (cpu_addr and x"E707") = x"C001" then coin2_ena <= cpu_do(0); end if; -- C001 + mirroring 18F8 + if (cpu_addr and x"E707") = x"C006" then flip_cpu <= cpu_do(0); end if; -- C006 + mirroring 18F8 + + if (cpu_addr and x"E0FF") = x"E0F0" then int_on <= cpu_do(0); end if; -- E0F0 + mirroring 1F00 + if (cpu_addr and x"E0FF") = x"E0F1" then ch_color_ref <= cpu_do(0); end if; -- E0F1 + mirroring 1F00 + if (cpu_addr and x"E0FF") = x"E0F8" then bg_position( 7 downto 0) <= not cpu_do ; end if; -- E0F8 + mirroring 1F00 + if (cpu_addr and x"E0FF") = x"E0F9" then bg_position(10 downto 8) <= not cpu_do(2 downto 0); end if; -- E0F9 + mirroring 1F00 + if (cpu_addr and x"E0FF") = x"E0FA" then bg_color_ref <= cpu_do(0); end if; -- E0FA + mirroring 1F00 + if (cpu_addr and x"E0FF") = x"E0FB" then bg_enable <= cpu_do(0); end if; -- E0FB + mirroring 1F00 + + end if; + + if int_on = '0' then + cpu_irq_n <= '1'; + else + if vblkn_r = '1' and vblkn = '0' then cpu_irq_n <= '0'; end if; + end if; + + end if; +end process; + +------------------------------------------ +-- write enable / ram access from CPU -- +-- mux ch_ram and sp ram addresses -- +-- dmux ch_ram and sp_ram data out -- +------------------------------------------ +wram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 12 ) = x"6" else '0'; +ch_ram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"E000") = x"8000" and hcnt(0) = '1' else '0'; +sp_ram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"E000") = x"A000" and hcnt(0) = '1' else '0'; + +flip <= flip_cpu xor flip_screen; +hflip <= hcnt when flip = '0' else not hcnt; +vflip <= vcnt when flip = '0' else not vcnt; + +ch_ram_addr <= cpu_addr(9 downto 0) when hcnt(0) = '1' else vflip(7 downto 3) & hflip(7 downto 3); +sp_ram_addr <= cpu_addr(7 downto 0) when hcnt(0) = '1' else '0'& hcnt(7 downto 1); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + if hcnt(0) = '1' then + ch_ram_do_to_cpu <= ch_ram_do; + sp_ram_do_to_cpu <= sp_ram_do; + else + sp_ram_do_to_sp_machine <= sp_ram_do; + end if; + end if; +end process; + +---------------------- +--- sprite machine --- +---------------------- +-- +-- transfert sprites data from sp_ram to sp_online_ram +-- +sp_vcnt <= sp_ram_do_to_sp_machine + ("111" & not(flip) & flip & flip & flip & '1') + vflip(7 downto 0) + 1; + +sp_online_ram_we <= '1' when hcnt(8) = '1' and sp_on_line = '1' and hcnt(0) ='0' and sp_online_ram_addr < "11111" else + '1' when hcnt(8) = '0' and hcnt(3) = '1' else '0'; + +sp_online_ram_di <= '1' & sp_ram_do_to_sp_machine when hcnt(8) = '1' else '0'&x"00"; + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if hcnt(8) = '1' then + if hcnt(2 downto 0) = "000" then + if sp_vcnt(7 downto 5) = "111" then + sp_on_line <= '1'; + else + sp_on_line <= '0'; + end if; + end if; + else + sp_on_line <= '0'; + end if; + + if hcnt(8) = '1' then + + -- during line display seek for sprite on line and transfert them to sp_online_ram + if hcnt = 256 then sp_online_ram_addr <= (others => '0'); end if; + + if pix_ena = '1' and sp_on_line = '1' and hcnt(0) = '0' and sp_online_ram_addr < "11111" then + + sp_online_ram_addr <= sp_online_ram_addr + 1; + + end if; + + -- during line fly back read sp_online_ram + else + sp_online_ram_addr <= hcnt(6 downto 4) & hcnt(2 downto 1); + end if; + + end if; +end process; + +-- +-- read sprite data from sp_online_ram and feed sprite line buffer with sprite graphics data +-- + +sp_online_vcnt <= sp_online_ram_do(7 downto 0) + ("111" & not(flip) & flip & flip & flip & '1') + vflip_r(7 downto 0) + 1; + +sp_code_line <= (sp_code(5 downto 0)) & + (sp_line(4 downto 3) xor (sp_code(7) & sp_code(7))) & + ("00" xor (sp_code(6) & sp_code(6))) & + (sp_line(2 downto 0) xor (sp_code(7) & sp_code(7) & sp_code(7))); + +sp_buffer_ram_addr <= sp_bit_hpos when flip = '1' and hcnt(8) = '1' else not sp_bit_hpos; + +sp_buffer_ram_di <= x"00" when hcnt(8) = '1' else + sp_color_r & sp_graphics3_do(sp_bit_nb) & + sp_graphics2_do(sp_bit_nb) & sp_graphics1_do(sp_bit_nb); + +sp_buffer_ram_we <= pix_ena when hcnt(8) = '1' else + sp_ok and clock_cnt(0) when sp_buffer_ram_do(2 downto 0) = "000" else '0'; + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '0' then + sp_vid <= sp_buffer_ram_do; + end if; + + if hcnt = 128 then vflip_r <= vflip; end if; + + if hcnt(8)='0' then + + if clock_cnt(0) = '1' then + if sp_hflip = '1' then sp_bit_nb <= sp_bit_nb + 1; end if; + if sp_hflip = '0' then sp_bit_nb <= sp_bit_nb - 1; end if; + + sp_bit_hpos <= sp_bit_hpos + 1; + end if; + + if pix_ena = '1' then + + if hcnt(3 downto 0) = "0000" then sp_line <= sp_online_vcnt; end if; + if hcnt(3 downto 0) = "0010" then sp_code <= sp_online_ram_do(7 downto 0); end if; + if hcnt(3 downto 0) = "0100" then sp_color <= sp_online_ram_do(4 downto 0); end if; + if hcnt(3 downto 0) = "0110" then sp_bit_hpos <= sp_online_ram_do(7 downto 0) + ("111" & not(flip) & flip & flip & flip & '1') +1; end if; + + if hcnt(3 downto 0) = "0110" then + sp_graphics_addr <= sp_code_line; + sp_ok <= sp_online_ram_do(8); + sp_hflip <= sp_code(6); + sp_vflip <= sp_code(7); + if sp_code(6) = '1' then sp_bit_nb <= 0; else sp_bit_nb <= 7; end if; + sp_color_r <= sp_color; + end if; + if hcnt(3 downto 0) = "1010" then + sp_graphics_addr(4 downto 3) <= "01" xor (sp_hflip & sp_hflip); + end if; + if hcnt(3 downto 0) = "1110" then + sp_graphics_addr(4 downto 3) <= "10" xor (sp_hflip & sp_hflip); + end if; + if hcnt(3 downto 0) = "0010" then + sp_graphics_addr(4 downto 3) <= "11" xor (sp_hflip & sp_hflip); + end if; + + end if; + + else + + if flip = '1' then + sp_bit_hpos <= hcnt(7 downto 0) - 5; -- tune sprite position w.r.t. background + else + sp_bit_hpos <= hcnt(7 downto 0) - 2; -- tune sprite position w.r.t. background + end if; + + end if; + + end if; +end process; + +-------------------- +--- char machine --- +-------------------- +ch_code_line <= ch_code & vflip(2 downto 0); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '1' then + + if hcnt(2 downto 0) = "010" then + ch_code <= ch_ram_do; + ch_color_addr <= vflip(7 downto 5) & hflip(7 downto 3); + + if flip = '1' then ch_bit_nb <= 0; else ch_bit_nb <= 7; end if; + else + + if flip = '1' then + ch_bit_nb <= ch_bit_nb + 1; + else + ch_bit_nb <= ch_bit_nb - 1; + end if; + + end if; + + end if; + + end if; +end process; + +ch_vid <= ch_graphx2_do(ch_bit_nb) & ch_graphx1_do(ch_bit_nb); + +-------------------------- +--- background machine --- +-------------------------- +map_offset_h <= (bg_position & '1') + (x"0" & vflip(7 downto 0)) + 1; + +-- count from "00"->"FF" and then continue with "00"->"7F" instead of "80"->"FF" +hflip2 <= hflip xor (not(hcnt(8)) & "0000000") when flip = '1' else hflip; + +map_offset_l1 <= not('0' & vflip(7 downto 1)) + (hflip2(7 downto 3) & "111") + 1; +map_offset_l2 <= map_offset_l1 + ('0' & not(flip) & flip & flip & flip & "000"); + +map_addr <= map_offset_h(11 downto 3) & map_offset_l2(7 downto 3); + +bg_graphics_addr(2 downto 0) <= map_offset_h(2 downto 0); + +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '1' then + + if hcnt(2 downto 0) = "011" then -- 4H^ + bg_code_line(9 downto 0) <= map2_do(1 downto 0) & map1_do; + bg_color_a <= map2_do(7 downto 4); + end if; + + if (not(vflip(3 downto 1)) + hflip(2 downto 0)) = "011" then + bg_graphics_addr(12 downto 3) <= bg_code_line; + bg_color <= bg_color_a; + + if flip = '1' then bg_bit_nb <= 0; else bg_bit_nb <= 7; end if; + else + if flip = '1' then + bg_bit_nb <= bg_bit_nb + 1; + else + bg_bit_nb <= bg_bit_nb - 1; + end if; + end if; + + end if; + + end if; +end process; + +bg_vid <= bg_graphics3_do(bg_bit_nb) & bg_graphics2_do(bg_bit_nb) & bg_graphics1_do(bg_bit_nb) + when bg_enable = '1' else "000"; + +-------------------------------------- +-- mux char/background/sprite video -- +-------------------------------------- +process (clock_vid) +begin + if rising_edge(clock_vid) then + + if pix_ena = '1' then + + palette_addr <= bg_color_ref & bg_color & bg_vid; + + if sp_vid(2 downto 0) /= "000" then + palette_addr <= sp_vid; + end if; + + if ch_vid /= "00" then + palette_addr <= ch_color_ref & ch_color_do(3 downto 0) & '0' & ch_vid; + end if; + + video_r <= palette_do(2 downto 0); + video_g <= palette_do(5 downto 3); + video_b <= palette_do(7 downto 6); + + end if; + + end if; +end process; + +------------------------------ +-- components & sound board -- +------------------------------ + +-- microprocessor Z80 +cpu : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => clock_vid, + CLKEN => cpu_ena, + WAIT_n => '1', + INT_n => cpu_irq_n, + NMI_n => '1', --cpu_nmi_n, + BUSRQ_n => '1', + M1_n => cpu_m1_n, + MREQ_n => cpu_mreq_n, + IORQ_n => cpu_ioreq_n, + RD_n => cpu_rd_n, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + +-- cpu program ROM 0x0000-0x5FFF +--rom_cpu : entity work.zaxxon_cpu +--port map( +-- clk => clock_vidn, +-- addr => cpu_addr(14 downto 0), +-- data => cpu_rom_do +--); +cpu_rom_addr <= cpu_addr(14 downto 0); + +-- working RAM 0x6000-0x6FFF +wram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 12) +port map( + clk => clock_vidn, + we => wram_we, + addr => cpu_addr(11 downto 0), + d => cpu_do, + q => wram_do +); + +-- video RAM 0x8000-0x83FF + mirroring adresses +video_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_vidn, + we => ch_ram_we, + addr => ch_ram_addr, + d => cpu_do, + q => ch_ram_do +); + +-- sprite RAM 0xA000-0xA0FF + mirroring adresses +sprites_ram : entity work.gen_ram +--sprites_ram_test : entity work.sp_ram_test +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_vidn, + we => sp_ram_we, +-- we => '0', + addr => sp_ram_addr, + d => cpu_do, + q => sp_ram_do +); + +-- sprite online RAM +sprites_online_ram : entity work.gen_ram +generic map( dWidth => 9, aWidth => 5) +port map( + clk => clock_vidn, + we => sp_online_ram_we, + addr => sp_online_ram_addr, + d => sp_online_ram_di, + q => sp_online_ram_do +); + +-- sprite line buffer +sprlinebuf : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_vidn, + we => sp_buffer_ram_we, + addr => sp_buffer_ram_addr, + d => sp_buffer_ram_di, + q => sp_buffer_ram_do +); + +-- char graphics ROM 1 +bg_graphics_1 : entity work.dpram +generic map( + dWidth => 8, + aWidth => 11 +) +port map( + clk_a => clock_vidn, + addr_a => ch_code_line, + q_a => ch_graphx1_do, + clk_b => clock_vid, + addr_b => dl_addr(10 downto 0), + we_b => bg_graphics_1_we, + d_b => dl_data +); +bg_graphics_1_we <= '1' when dl_wr = '1' and dl_addr(16 downto 11) = "011110" else '0'; + +-- char graphics ROM 2 +bg_graphics_2 : entity work.dpram +generic map( + dWidth => 8, + aWidth => 11 +) +port map( + clk_a => clock_vidn, + addr_a => ch_code_line, + q_a => ch_graphx2_do, + clk_b => clock_vid, + addr_b => dl_addr(10 downto 0), + we_b => bg_graphics_2_we, + d_b => dl_data +); +bg_graphics_2_we <= '1' when dl_wr = '1' and dl_addr(16 downto 11) = "011111" else '0'; + + +-- map tile ROM 1 +--map_tile_1 : entity work.zaxxon_map_1 +--port map( +-- clk => clock_vidn, +-- addr => map_addr, +-- data => map1_do +--); +map1_do <= map_do(7 downto 0); + +-- map tile ROM 2 +--map_tile_2 : entity work.zaxxon_map_2 +--port map( +-- clk => clock_vidn, +-- addr => map_addr, +-- data => map2_do +--); +map2_do <= map_do(15 downto 8); + +-- background graphics ROM 1 +bg_graphics_bits_1 : entity work.dpram +generic map( + dWidth => 8, + aWidth => 13 +) +port map( + clk_a => clock_vidn, + addr_a => bg_graphics_addr, + q_a => bg_graphics1_do, + clk_b => clock_vid, + addr_b => dl_addr(12 downto 0), + we_b => bg_graphics_bits_1_we, + d_b => dl_data +); +bg_graphics_bits_1_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1000" else '0'; --10000-11fff + +-- background graphics ROM 2 +bg_graphics_bits_2 : entity work.dpram +generic map( + dWidth => 8, + aWidth => 13 +) +port map( + clk_a => clock_vidn, + addr_a => bg_graphics_addr, + q_a => bg_graphics2_do, + clk_b => clock_vid, + addr_b => dl_addr(12 downto 0), + we_b => bg_graphics_bits_2_we, + d_b => dl_data +); +bg_graphics_bits_2_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1001" else '0'; --12000-13fff + +-- background graphics ROM 3 +bg_graphics_bits_3 : entity work.dpram +generic map( + dWidth => 8, + aWidth => 13 +) +port map( + clk_a => clock_vidn, + addr_a => bg_graphics_addr, + q_a => bg_graphics3_do, + clk_b => clock_vid, + addr_b => dl_addr(12 downto 0), + we_b => bg_graphics_bits_3_we, + d_b => dl_data +); +bg_graphics_bits_3_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1010" else '0'; --14000-15fff + +-- sprite graphics ROM 1 +sp_graphics_bits_1 : entity work.dpram +generic map( + dWidth => 8, + aWidth => 13 +) +port map( + clk_a => clock_vidn, + addr_a => sp_graphics_addr, + q_a => sp_graphics1_do, + clk_b => clock_vid, + addr_b => dl_addr(12 downto 0), + we_b => sp_graphics_bits_1_we, + d_b => dl_data +); +sp_graphics_bits_1_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1011" else '0'; --16000-17fff + +-- sprite graphics ROM 2 +sp_graphics_bits_2 : entity work.dpram +generic map( + dWidth => 8, + aWidth => 13 +) +port map( + clk_a => clock_vidn, + addr_a => sp_graphics_addr, + q_a => sp_graphics2_do, + clk_b => clock_vid, + addr_b => dl_addr(12 downto 0), + we_b => sp_graphics_bits_2_we, + d_b => dl_data +); +sp_graphics_bits_2_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1100" else '0'; --18000-19fff + +-- sprite graphics ROM 3 +sp_graphics_bits_3 : entity work.dpram +generic map( + dWidth => 8, + aWidth => 13 +) +port map( + clk_a => clock_vidn, + addr_a => sp_graphics_addr, + q_a => sp_graphics3_do, + clk_b => clock_vid, + addr_b => dl_addr(12 downto 0), + we_b => sp_graphics_bits_3_we, + d_b => dl_data +); +sp_graphics_bits_3_we <= '1' when dl_wr = '1' and dl_addr(16 downto 13) = "1101" else '0'; --1a000-1bfff + +-- char color +char_color : entity work.dpram +generic map( + dWidth => 8, + aWidth => 8 +) +port map( + clk_a => clock_vidn, + addr_a => ch_color_addr, + q_a => ch_color_do, + clk_b => clock_vid, + addr_b => dl_addr(7 downto 0), + we_b => char_color_we, + d_b => dl_data +); +char_color_we <= '1' when dl_wr = '1' and dl_addr(16 downto 8) = "111000001" else '0'; --1C100-1C1FF + +-- palette +palette : entity work.dpram +generic map( + dWidth => 8, + aWidth => 8 +) +port map( + clk_a => clock_vidn, + addr_a => palette_addr, + q_a => palette_do, + clk_b => clock_vid, + addr_b => dl_addr(7 downto 0), + we_b => palette_we, + d_b => dl_data +); +palette_we <= '1' when dl_wr = '1' and dl_addr(16 downto 8) = "111000000" else '0'; --1C000-1C0FF + +--zaxxon_sound_board +--sound_board : entity work.tron_sound_board +--port map( +-- clock_40 => clock_40, +-- reset => reset, +-- +-- main_cpu_addr => cpu_addr(7 downto 0), +-- +-- ssio_iowe => ssio_iowe, +-- ssio_di => cpu_do, +-- ssio_do => ssio_do, +-- +-- input_0 => input_0, +-- input_1 => input_1, +-- input_2 => input_2, +-- input_3 => input_3, +-- input_4 => input_4, +-- +-- separate_audio => separate_audio, +-- audio_out_l => audio_out_l, +-- audio_out_r => audio_out_r, +-- +-- dbg_cpu_addr => open --dbg_cpu_addr +--); +end struct; \ No newline at end of file