diff --git a/Arcade_MiST/Custom Hardware/Crazy Kong.jpg b/Arcade_MiST/Crazy Climber Hardware/Crazy Kong.jpg
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Crazy Kong.jpg
rename to Arcade_MiST/Crazy Climber Hardware/Crazy Kong.jpg
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/CrazyKong.qpf b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.qpf
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/CrazyKong.qpf
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.qpf
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/CrazyKong.qsf b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.qsf
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/CrazyKong.qsf
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/CrazyKong.qsf
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/README.txt b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/README.txt
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/README.txt
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/Release/CrazyKong.rbf b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/Release/CrazyKong.rbf
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/Release/CrazyKong.rbf
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/Release/CrazyKong.rbf
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/clean.bat b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/clean.bat
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/clean.bat
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80_ALU.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80_MCode.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80_Pack.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80_Reg.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80s.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/T80/T80s.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/T80/T80s.vhd
diff --git a/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/build_id.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/build_id.sv
new file mode 100644
index 00000000..b0202b40
--- /dev/null
+++ b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/build_id.sv
@@ -0,0 +1,2 @@
+`define BUILD_DATE "190715"
+`define BUILD_TIME "162500"
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/build_id.tcl b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_palette.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_palette.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_palette.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit0.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit0.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit0.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit0.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit1.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit1.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit1.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_big_sprite_tile_bit1.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_mist.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_mist.sv
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_mist.sv
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_mist.sv
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_palette.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_palette.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_palette.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_palette.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_program.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_program.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_program.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_program.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_samples.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_samples.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_samples.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_samples.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_sound.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_sound.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_sound.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_sound.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_tile_bit0.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_tile_bit0.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_tile_bit0.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_tile_bit0.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_tile_bit1.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_tile_bit1.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ckong_tile_bit1.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ckong_tile_bit1.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/dac.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/dac.sv
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/dac.sv
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/dac.sv
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/gen_ram.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/gen_ram.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/gen_ram.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/hq2x.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/hq2x.sv
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/hq2x.sv
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/hq2x.sv
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/line_doubler.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/line_doubler.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/line_doubler.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/line_doubler.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/mist_io.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/mist_io.sv
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/mist_io.sv
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/mist_io.sv
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/osd.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/osd.sv
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/osd.sv
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/osd.sv
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/pll.qip b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/pll.qip
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/pll.v b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/pll.v
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/scandoubler.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/scandoubler.sv
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/scandoubler.sv
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/scandoubler.sv
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/video_gen.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/video_gen.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/video_gen.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/video_gen.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/video_mixer.sv b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/video_mixer.sv
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/video_mixer.sv
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/video_mixer.sv
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ym_2149_linmix.vhd b/Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ym_2149_linmix.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/ym_2149_linmix.vhd
rename to Arcade_MiST/Crazy Climber Hardware/CrazyKong_MiST/rtl/ym_2149_linmix.vhd
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.db_info b/Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.db_info
deleted file mode 100644
index d4da0ec1..00000000
--- a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-Version_Index = 318813696
-Creation_Time = Sun Mar 10 14:00:42 2019
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.ipinfo b/Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.ipinfo
deleted file mode 100644
index 85a7d32e..00000000
Binary files a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.ipinfo and /dev/null differ
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.sld_design_entry.sci b/Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.sld_design_entry.sci
deleted file mode 100644
index 8cbf58a9..00000000
Binary files a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/db/CrazyKong.sld_design_entry.sci and /dev/null differ
diff --git a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/build_id.sv b/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/build_id.sv
deleted file mode 100644
index bbe6acae..00000000
--- a/Arcade_MiST/Custom Hardware/CrazyKong_MiST/rtl/build_id.sv
+++ /dev/null
@@ -1,2 +0,0 @@
-`define BUILD_DATE "190308"
-`define BUILD_TIME "223352"
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.ppf b/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.ppf
deleted file mode 100644
index 547d702c..00000000
--- a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.ppf
+++ /dev/null
@@ -1,10 +0,0 @@
-
-
-
-
-
-
-
-
-
-
diff --git a/Arcade_MiST/Custom Hardware/Galaga.jpg b/Arcade_MiST/Galaga Hardware/Galaga.jpg
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga.jpg
rename to Arcade_MiST/Galaga Hardware/Galaga.jpg
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/Galaga_MiST.qpf b/Arcade_MiST/Galaga Hardware/Galaga_MiST/Galaga_MiST.qpf
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/Galaga_MiST.qpf
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/Galaga_MiST.qpf
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/Galaga_MiST.qsf b/Arcade_MiST/Galaga Hardware/Galaga_MiST/Galaga_MiST.qsf
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/Galaga_MiST.qsf
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/Galaga_MiST.qsf
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/Galaga_MiST.sdc b/Arcade_MiST/Galaga Hardware/Galaga_MiST/Galaga_MiST.sdc
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/Galaga_MiST.sdc
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/Galaga_MiST.sdc
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/README.txt b/Arcade_MiST/Galaga Hardware/Galaga_MiST/README.txt
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/README.txt
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/README.txt
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/Release/galaga_mist.rbf b/Arcade_MiST/Galaga Hardware/Galaga_MiST/Release/galaga_mist.rbf
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/Release/galaga_mist.rbf
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/Release/galaga_mist.rbf
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/clean.bat b/Arcade_MiST/Galaga Hardware/Galaga_MiST/clean.bat
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/clean.bat
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/clean.bat
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80_ALU.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80_ALU.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80_ALU.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80_MCode.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80_MCode.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80_MCode.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80_Pack.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80_Pack.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80_Pack.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80_Reg.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80_Reg.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80_Reg.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80se.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80se.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/T80/T80se.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/T80/T80se.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/build_id.tcl
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/build_id.tcl
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/build_id.tcl
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/galaga.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/galaga.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_mist.sv b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/galaga_mist.sv
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_mist.sv
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/galaga_mist.sv
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_video.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/galaga_video.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/galaga_video.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/galaga_video.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/gen_ram.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/gen_ram.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/gen_ram.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/gen_video.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/gen_video.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/gen_video.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/gen_video.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/mb88.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/mb88.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/mb88.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/mb88.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.qip b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/pll.qip
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.qip
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/pll.qip
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.v b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/pll.v
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/pll.v
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/pll.v
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/bg_graphx.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/bg_graphx.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/bg_graphx.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/bg_graphx.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/bg_palette.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/bg_palette.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/bg_palette.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/bg_palette.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/cs54xx_prog.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/cs54xx_prog.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/cs54xx_prog.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/cs54xx_prog.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu1.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/galaga_cpu1.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu1.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/galaga_cpu1.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu2.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/galaga_cpu2.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu2.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/galaga_cpu2.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu3.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/galaga_cpu3.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/galaga_cpu3.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/galaga_cpu3.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/rgb.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/rgb.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/rgb.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/rgb.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sound_samples.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/sound_samples.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sound_samples.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/sound_samples.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sound_seq.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/sound_seq.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sound_seq.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/sound_seq.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sp_graphx.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/sp_graphx.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sp_graphx.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/sp_graphx.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sp_palette.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/sp_palette.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/roms/sp_palette.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/roms/sp_palette.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/sound_machine.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/sound_machine.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/sound_machine.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/sound_machine.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/stars.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/stars.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/stars.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/stars.vhd
diff --git a/Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/stars_machine.vhd b/Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/stars_machine.vhd
similarity index 100%
rename from Arcade_MiST/Custom Hardware/Galaga_MiST/rtl/stars_machine.vhd
rename to Arcade_MiST/Galaga Hardware/Galaga_MiST/rtl/stars_machine.vhd
diff --git a/Arcade_MiST/Galaga Hardware/ReadMe.txt b/Arcade_MiST/Galaga Hardware/ReadMe.txt
new file mode 100644
index 00000000..8c5b4745
--- /dev/null
+++ b/Arcade_MiST/Galaga Hardware/ReadMe.txt
@@ -0,0 +1,5 @@
+Games that should work on this Hardware
+
+Bosconian
+Dig Dug
+Xevious
\ No newline at end of file
diff --git a/Arcade_MiST/README.txt b/Arcade_MiST/README.txt
index 50382284..1e614115 100644
--- a/Arcade_MiST/README.txt
+++ b/Arcade_MiST/README.txt
@@ -24,12 +24,9 @@ Aviable Arcade Cores
Berzerk
Frenzy
-#Custom Hardware
- Crazy Kong
- Galaga
-
#Crazy Climber Hardware
Crazy Climber
+ Crazy Kong
River Patrol
Silver Land
@@ -40,6 +37,9 @@ Aviable Arcade Cores
#Dottori-Kun Hardware
Dottori Kun / Dottori-Man Jr / Mine Sweeper (3in1Game)
+#Galaga Hardware
+ Galaga
+
#Galaxian Hardware
Azurian Attack
Black Hole
diff --git a/Computer_MiST/Commodore - MAX_MiST/MAX.qpf b/Computer_MiST/Commodore - MAX_MiST/MAX.qpf
deleted file mode 100644
index dc3a3a2c..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/MAX.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 16:51:32 December 14, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "16:51:32 December 14, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "MAX"
diff --git a/Computer_MiST/Commodore - MAX_MiST/MAX.qsf b/Computer_MiST/Commodore - MAX_MiST/MAX.qsf
deleted file mode 100644
index 828985b1..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/MAX.qsf
+++ /dev/null
@@ -1,172 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 16:51:32 December 14, 2017
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# MAX_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_90 -to SPI_SS4
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PIN_49 -to SDRAM_A[0]
-set_location_assignment PIN_44 -to SDRAM_A[1]
-set_location_assignment PIN_42 -to SDRAM_A[2]
-set_location_assignment PIN_39 -to SDRAM_A[3]
-set_location_assignment PIN_4 -to SDRAM_A[4]
-set_location_assignment PIN_6 -to SDRAM_A[5]
-set_location_assignment PIN_8 -to SDRAM_A[6]
-set_location_assignment PIN_10 -to SDRAM_A[7]
-set_location_assignment PIN_11 -to SDRAM_A[8]
-set_location_assignment PIN_28 -to SDRAM_A[9]
-set_location_assignment PIN_50 -to SDRAM_A[10]
-set_location_assignment PIN_30 -to SDRAM_A[11]
-set_location_assignment PIN_32 -to SDRAM_A[12]
-set_location_assignment PIN_83 -to SDRAM_DQ[0]
-set_location_assignment PIN_79 -to SDRAM_DQ[1]
-set_location_assignment PIN_77 -to SDRAM_DQ[2]
-set_location_assignment PIN_76 -to SDRAM_DQ[3]
-set_location_assignment PIN_72 -to SDRAM_DQ[4]
-set_location_assignment PIN_71 -to SDRAM_DQ[5]
-set_location_assignment PIN_69 -to SDRAM_DQ[6]
-set_location_assignment PIN_68 -to SDRAM_DQ[7]
-set_location_assignment PIN_86 -to SDRAM_DQ[8]
-set_location_assignment PIN_87 -to SDRAM_DQ[9]
-set_location_assignment PIN_98 -to SDRAM_DQ[10]
-set_location_assignment PIN_99 -to SDRAM_DQ[11]
-set_location_assignment PIN_100 -to SDRAM_DQ[12]
-set_location_assignment PIN_101 -to SDRAM_DQ[13]
-set_location_assignment PIN_103 -to SDRAM_DQ[14]
-set_location_assignment PIN_104 -to SDRAM_DQ[15]
-set_location_assignment PIN_58 -to SDRAM_BA[0]
-set_location_assignment PIN_51 -to SDRAM_BA[1]
-set_location_assignment PIN_85 -to SDRAM_DQMH
-set_location_assignment PIN_67 -to SDRAM_DQML
-set_location_assignment PIN_60 -to SDRAM_nRAS
-set_location_assignment PIN_64 -to SDRAM_nCAS
-set_location_assignment PIN_66 -to SDRAM_nWE
-set_location_assignment PIN_59 -to SDRAM_nCS
-set_location_assignment PIN_33 -to SDRAM_CKE
-set_location_assignment PIN_43 -to SDRAM_CLK
-set_location_assignment PIN_31 -to UART_RX
-set_location_assignment PIN_46 -to UART_TX
-
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name TOP_LEVEL_ENTITY MAX
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:51:32 DECEMBER 14, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name VHDL_FILE rtl/sid_voice.vhd
-set_global_assignment -name VHDL_FILE rtl/sid_components.vhd
-set_global_assignment -name VHDL_FILE rtl/sid_6581.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/MAX.sv
-set_global_assignment -name QIP_FILE rtl/pll.qip
-set_global_assignment -name QIP_FILE rtl/COLRAM.qip
-set_global_assignment -name QIP_FILE rtl/MAINRAM.qip
-set_global_assignment -name VHDL_FILE rtl/cpu_6510.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu65xx_e.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu65xx_fast.vhd
-set_global_assignment -name VHDL_FILE rtl/fpga64_rgbcolor.vhd
-set_global_assignment -name VERILOG_FILE rtl/user_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name VERILOG_FILE rtl/data_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VHDL_FILE rtl/cia_6526.vhd
-set_global_assignment -name VERILOG_FILE rtl/pla_6703.v
-set_global_assignment -name VHDL_FILE rtl/vic_656x_a.vhd
-set_global_assignment -name VHDL_FILE rtl/vic_656x_e.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/cart.sv
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Computer_MiST/Commodore - MAX_MiST/Schematic/326100.bmp b/Computer_MiST/Commodore - MAX_MiST/Schematic/326100.bmp
deleted file mode 100644
index 816401da..00000000
Binary files a/Computer_MiST/Commodore - MAX_MiST/Schematic/326100.bmp and /dev/null differ
diff --git a/Computer_MiST/Commodore - MAX_MiST/Schematic/326100.png b/Computer_MiST/Commodore - MAX_MiST/Schematic/326100.png
deleted file mode 100644
index 8987c18b..00000000
Binary files a/Computer_MiST/Commodore - MAX_MiST/Schematic/326100.png and /dev/null differ
diff --git a/Computer_MiST/Commodore - MAX_MiST/Schematic/Max_schematic.jpg b/Computer_MiST/Commodore - MAX_MiST/Schematic/Max_schematic.jpg
deleted file mode 100644
index b23f2e97..00000000
Binary files a/Computer_MiST/Commodore - MAX_MiST/Schematic/Max_schematic.jpg and /dev/null differ
diff --git a/Computer_MiST/Commodore - MAX_MiST/Schematic/scematic.pdf b/Computer_MiST/Commodore - MAX_MiST/Schematic/scematic.pdf
deleted file mode 100644
index 15505744..00000000
Binary files a/Computer_MiST/Commodore - MAX_MiST/Schematic/scematic.pdf and /dev/null differ
diff --git a/Computer_MiST/Commodore - MAX_MiST/Schematic/ultimaxSchematic.gif b/Computer_MiST/Commodore - MAX_MiST/Schematic/ultimaxSchematic.gif
deleted file mode 100644
index 119f1498..00000000
Binary files a/Computer_MiST/Commodore - MAX_MiST/Schematic/ultimaxSchematic.gif and /dev/null differ
diff --git a/Computer_MiST/Commodore - MAX_MiST/clean.bat b/Computer_MiST/Commodore - MAX_MiST/clean.bat
deleted file mode 100644
index d76d65c1..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/clean.bat
+++ /dev/null
@@ -1,13 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-del PLLJ_PLLSPE_INFO.txt
-del *.qws
-del *.ppf
-del *.qip
-pause
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/COLRAM.qip b/Computer_MiST/Commodore - MAX_MiST/rtl/COLRAM.qip
deleted file mode 100644
index 25074317..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/COLRAM.qip
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "COLRAM.v"]
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/COLRAM.v b/Computer_MiST/Commodore - MAX_MiST/rtl/COLRAM.v
deleted file mode 100644
index 989754a8..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/COLRAM.v
+++ /dev/null
@@ -1,177 +0,0 @@
-// megafunction wizard: %RAM: 1-PORT%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram
-
-// ============================================================
-// File Name: COLRAM.v
-// Megafunction Name(s):
-// altsyncram
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 13.1.0 Build 162 10/23/2013 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2013 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module COLRAM (
- address,
- clock,
- data,
- rden,
- wren,
- q);
-
- input [9:0] address;
- input clock;
- input [3:0] data;
- input rden;
- input wren;
- output [3:0] q;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri1 clock;
- tri1 rden;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
- wire [3:0] sub_wire0;
- wire [3:0] q = sub_wire0[3:0];
-
- altsyncram altsyncram_component (
- .address_a (address),
- .clock0 (clock),
- .data_a (data),
- .wren_a (wren),
- .rden_a (rden),
- .q_a (sub_wire0),
- .aclr0 (1'b0),
- .aclr1 (1'b0),
- .address_b (1'b1),
- .addressstall_a (1'b0),
- .addressstall_b (1'b0),
- .byteena_a (1'b1),
- .byteena_b (1'b1),
- .clock1 (1'b1),
- .clocken0 (1'b1),
- .clocken1 (1'b1),
- .clocken2 (1'b1),
- .clocken3 (1'b1),
- .data_b (1'b1),
- .eccstatus (),
- .q_b (),
- .rden_b (1'b1),
- .wren_b (1'b0));
- defparam
- altsyncram_component.clock_enable_input_a = "BYPASS",
- altsyncram_component.clock_enable_output_a = "BYPASS",
- altsyncram_component.intended_device_family = "Cyclone III",
- altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.numwords_a = 1024,
- altsyncram_component.operation_mode = "SINGLE_PORT",
- altsyncram_component.outdata_aclr_a = "NONE",
- altsyncram_component.outdata_reg_a = "CLOCK0",
- altsyncram_component.power_up_uninitialized = "FALSE",
- altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
- altsyncram_component.widthad_a = 10,
- altsyncram_component.width_a = 4,
- altsyncram_component.width_byteena_a = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-// Retrieval info: PRIVATE: AclrData NUMERIC "0"
-// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clken NUMERIC "0"
-// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING ""
-// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-// Retrieval info: PRIVATE: RegData NUMERIC "1"
-// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
-// Retrieval info: PRIVATE: WidthData NUMERIC "4"
-// Retrieval info: PRIVATE: rden NUMERIC "1"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
-// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
-// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL COLRAM_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/MAINRAM.qip b/Computer_MiST/Commodore - MAX_MiST/rtl/MAINRAM.qip
deleted file mode 100644
index 91977785..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/MAINRAM.qip
+++ /dev/null
@@ -1,3 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "MAINRAM.v"]
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/MAINRAM.v b/Computer_MiST/Commodore - MAX_MiST/rtl/MAINRAM.v
deleted file mode 100644
index 878b2d98..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/MAINRAM.v
+++ /dev/null
@@ -1,177 +0,0 @@
-// megafunction wizard: %RAM: 1-PORT%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram
-
-// ============================================================
-// File Name: MAINRAM.v
-// Megafunction Name(s):
-// altsyncram
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 13.1.0 Build 162 10/23/2013 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2013 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module MAINRAM (
- address,
- clock,
- data,
- rden,
- wren,
- q);
-
- input [10:0] address;
- input clock;
- input [7:0] data;
- input rden;
- input wren;
- output [7:0] q;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri1 clock;
- tri1 rden;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
- wire [7:0] sub_wire0;
- wire [7:0] q = sub_wire0[7:0];
-
- altsyncram altsyncram_component (
- .address_a (address),
- .clock0 (clock),
- .data_a (data),
- .wren_a (wren),
- .rden_a (rden),
- .q_a (sub_wire0),
- .aclr0 (1'b0),
- .aclr1 (1'b0),
- .address_b (1'b1),
- .addressstall_a (1'b0),
- .addressstall_b (1'b0),
- .byteena_a (1'b1),
- .byteena_b (1'b1),
- .clock1 (1'b1),
- .clocken0 (1'b1),
- .clocken1 (1'b1),
- .clocken2 (1'b1),
- .clocken3 (1'b1),
- .data_b (1'b1),
- .eccstatus (),
- .q_b (),
- .rden_b (1'b1),
- .wren_b (1'b0));
- defparam
- altsyncram_component.clock_enable_input_a = "BYPASS",
- altsyncram_component.clock_enable_output_a = "BYPASS",
- altsyncram_component.intended_device_family = "Cyclone III",
- altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.numwords_a = 2048,
- altsyncram_component.operation_mode = "SINGLE_PORT",
- altsyncram_component.outdata_aclr_a = "NONE",
- altsyncram_component.outdata_reg_a = "CLOCK0",
- altsyncram_component.power_up_uninitialized = "FALSE",
- altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
- altsyncram_component.widthad_a = 11,
- altsyncram_component.width_a = 8,
- altsyncram_component.width_byteena_a = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-// Retrieval info: PRIVATE: AclrData NUMERIC "0"
-// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clken NUMERIC "0"
-// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING ""
-// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-// Retrieval info: PRIVATE: RegData NUMERIC "1"
-// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-// Retrieval info: PRIVATE: WidthData NUMERIC "8"
-// Retrieval info: PRIVATE: rden NUMERIC "1"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL MAINRAM_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/MAX.sv b/Computer_MiST/Commodore - MAX_MiST/rtl/MAX.sv
deleted file mode 100644
index 98e34e63..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/MAX.sv
+++ /dev/null
@@ -1,331 +0,0 @@
-module MAX(
- input CLOCK_27,
- output [5:0] VGA_R,
- output [5:0] VGA_G,
- output [5:0] VGA_B,
- output VGA_HS,
- output VGA_VS,
- output LED,
- output AUDIO_L,
- output AUDIO_R,
- input SPI_SCK,
- output SPI_DO,
- input SPI_DI,
- input SPI_SS2,
- input SPI_SS3,
- input SPI_SS4,
- input CONF_DATA0
-
- );
-
-`include "build_id.sv"
-
-localparam CONF_STR = {
- "Commodore MAX;e0;",
- "O2,SID Filter,On,Off;",
- "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
- "T5,Reset;",
- "V,v0.0.",`BUILD_DATE
- };
-
-wire clk_cpu, clk_sid, clk_ce, phi0_cpu;
-wire locked;
-wire scandoubler_disable;
-wire ypbpr;
-wire ps2_kbd_clk, ps2_kbd_data;
-wire [31:0] status;
-wire [1:0] buttons;
-wire [1:0] switches;
-assign LED = 1;
-
-reg [7:0] reset_cnt;
-always @(posedge clk_cpu) begin
- if(!locked || buttons[1] || status[0] || status[5])// | dio_download)
- reset_cnt <= 8'h0;
- else if(reset_cnt != 8'd255)
- reset_cnt <= reset_cnt + 8'd1;
-end
-
-wire reset = (reset_cnt != 8'd255);
-
-wire [15:0]ADDR_BUS;
-wire [15:0]VIC_ADDR_BUS;
-tri [7:0]DATA_BUS;
-wire BA;
-wire RW;
-wire nRW_PLA;
-wire nRAM;
-wire nEXTRAM;
-wire nVIC;
-wire nSID;
-wire nCIA_PLA;
-wire nCIA;
-wire nROML;
-wire nROMH;
-wire nCOLRAM;
-wire nIRQ;
-wire nNMI;
-wire BUF;
-wire AEC;
-
-// Video
-wire hs, vs;
-wire [5:0]r, g, b;
-wire [17:0]audio;
-//EXPANSIONS PORT
-wire SP;
-wire CNT;
-//Joystick
-wire [7:0]JoyA,JoyB;
-
-
-wire [7:0]CPU_DI;
-wire [7:0]CPU_DO;
-wire [7:0]cpuIO;
-//CIA
-wire [7:0]CIA_DO;
-//VIC
-wire [7:0]VIC_DO;
-wire [3:0]VIC_ColIndex;
-//Main RAM
-wire [7:0]RAM_DO;
-//Color RAM
-wire [3:0]COL_DI;
-wire [3:0]COL_DO;
-//SID
-wire [7:0]SID_DO;
-//CARD
-wire [7:0]CART_DO;
-wire [7:0]cia_pai;
-wire [7:0]cia_pao;
-wire [7:0]cia_pbi;
-wire [7:0]cia_pbo;
-
-wire enableCPU, enableCIA, enableVIC = 1;
-wire enablePixel = 1;
-wire pulseRd;
-
-pll pll(
- .inclk0(CLOCK_27),
- .areset(0),
- .c0(clk_cpu),//32
- .c1(clk_sid),//1
- .c2(clk_ce),//8
- .c3(phi0_cpu),//todo
- .locked(locked)
- );
-
-mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
-(
- .conf_str(CONF_STR),
- .clk_sys(clk_cpu),
- .SPI_SCK(SPI_SCK),
- .CONF_DATA0(CONF_DATA0),
- .SPI_SS2(SPI_SS2),
- .SPI_DO(SPI_DO),
- .SPI_DI(SPI_DI),
- .buttons(buttons),
- .switches(switches),
- .scandoubler_disable(scandoubler_disable),
- .ypbpr(ypbpr),
- .status(status),
- .ps2_kbd_clk(ps2_kbd_clk),
- .ps2_kbd_data(ps2_kbd_data),
- .joystick_0(JoyA),
- .joystick_1(JoyB)
-);
-
-video_mixer #(.LINE_LENGTH(600), .HALF_DEPTH(0)) video_mixer
-(
- .clk_sys(clk_cpu),
- .ce_pix(clk_ce),
- .ce_pix_actual(clk_ce),
- .SPI_SCK(SPI_SCK),
- .SPI_SS3(SPI_SS3),
- .SPI_DI(SPI_DI),
- .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
- .scandoubler_disable(scandoubler_disable),
- .hq2x(status[4:3]==1),
- .ypbpr(ypbpr),
- .ypbpr_full(1),
- .R(r),
- .G(g),
- .B(b),
- .mono(0),
- .HSync(hs),
- .VSync(vs),
- .line_start(0),
- .VGA_R(VGA_R),
- .VGA_G(VGA_G),
- .VGA_B(VGA_B),
- .VGA_VS(VGA_VS),
- .VGA_HS(VGA_HS)
-);
-
-sigma_delta_dac sigma_delta_dac
-(
- .DACout(AUDIO_L),
- .DACin(audio),
- .CLK(clk_cpu),
- .RESET(0)
-);
-
-assign AUDIO_R = AUDIO_L;
-
-//CPU MOS6510
-cpu_6510 U5 (
- .clk(phi0_cpu),
- .reset(reset),
- .enable(enableCPU),
- .nmi_n(nNMI),
- .nmi_ack(),
- .irq_n(nIRQ),
- .CPUdi(CPU_DI),
- .CPUdo(CPU_DO),
- .addr(ADDR_BUS),
- .we(RW),
- .doIO(cpuIO),
- .diIO("00010111")
- );
-
-//PLA MOS6703
-pla_6703 pla_6703 (
- .A(ADDR_BUS[15:10]),
- .DI(CPU_DO),// Color Data
- .DO(),//CPU_DI),// DataBUS
- .CLK(clk_cpu),
- .BA(BA),
- .RW_IN(RW),
- .RAM(nRAM), //invert
- .EXRAM(nEXTRAM), //invert
- .VIC(nVIC), //invert
- .SID(nSID), //invert
- .CIA(nCIA_PLA), //invert
- .COLRAM(nCOLRAM), //invert
- .ROML(nROML), //invert
- .ROMH(nROMH), //invert
- .BUF(BUF), //not invert
- .RW_OUT(nRW_PLA) //invert
- );
-
-
-
-//COLRAM 1024x4
-COLRAM U11 (
- .address(ADDR_BUS[9:0]),
- .clock(clk_cpu),
- .data(CPU_DO),
- .rden(~nCOLRAM),
- .wren(~nRW_PLA),
- .q(COL_DO)
- );
-
-//MAINRAM 2048x8
-MAINRAM U6 (
- .address(ADDR_BUS[10:0]),
- .clock(clk_cpu),
- .data(CPU_DO),
- .rden(~nRAM),
- .wren(~nRW_PLA),
- .q(CPU_DI)
- );
-
-
-//VIC MOS6566
-vic_656x vic_656x (
- .clk(clk_cpu),
- .phi(phi0_cpu),// phi = 0 is VIC cycle-- phi = 1 is CPU cycle (only used by VIC when BA is low)
- .enaData(enablePixel),
- .enaPixel(enableVIC),
- .baSync(0),
- .ba(BA),
- .mode6569(0),// PAL 63 cycles and 312 lines
- .mode6567old(1),// old NTSC 64 cycles and 262 line
- .mode6567R8(0),// new NTSC 65 cycles and 263 line
- .mode6572(0),// PAL-N 65 cycles and 312 lines
- .reset(reset),
- .cs(~nVIC),
- .we(~nRW_PLA),
- .rd(pulseRd),
- .lp_n(),
- .aRegisters(DATA_BUS[5:0]),
- .diRegisters(CPU_DO),
- .datai(CPU_DO),
- .diColor(COL_DO),
- .datao(VIC_DO),
- .vicAddr(VIC_ADDR_BUS[13:0]),
- .irq_n(nIRQ),
- .hSync(hs),
- .vSync(vs),
- .colorIndex(VIC_ColIndex),
- .debugX(),
- .debugY(),
- .vicRefresh(),
- .addrValid()
- );
-
-fpga64_rgbcolor fpga64_rgbcolor (
- .index(VIC_ColIndex),
- .r(r[5:0]),
- .g(g[5:0]),
- .b(b[5:0])
- );
-
-//CIA MOS6526
-cia_6526 cia_6526 (
- .clk(clk_cpu),
- .todClk(vs),
- .reset(reset),
- .enable(enableCIA),
- .cs(~nCIA),
- .we(~RW),
- .rd(pulseRd),
- .addr(ADDR_BUS[3:0]),
- .CIAdi(CPU_DO),
- .CIAdo(CIA_DO),
- .ppai(cia_pai),//Keyboard
- .ppao(cia_pao),//Keyboard
- .ppbi(cia_pbi),//Keyboard
- .ppbo(cia_pbo),//Keyboard
- .flag_n(1),
- .sp(SP),
- .cnt(CNT),
- .irq_n(~nIRQ)
- );
-
-//SID MOS6581
-sid_6581 sid_6581 (
- .clk32(clk_cpu),
- .clk_1MHz(clk_sid),
- .reset(reset),
- .cs(~nSID),
- .we(~RW),
- .addr(ADDR_BUS[3:0]),
- .data_i(CPU_DO),
- .data_o(SID_DO),
- .poti_x(~(cia_pao[7] & JoyA[5]) | (cia_pao[6] & JoyB[5])),//todo
- .poti_y(~(cia_pao[7] & JoyA[6]) | (cia_pao[6] & JoyB[6])),//todo
- .audio_data(audio)
- );
-
-cart cart(
- .clk0(clk_cpu),
- .addr(ADDR_BUS),
- .data_i(CPU_DO),
- .data_o(CART_DO),
- .nmi(nNMI),
- .reset(reset),
- .romL(nROML),
- .romH(nROMH),
- .rw_pla_n(nRW_PLA),
- .ba(BA),
- .cia_pla_n(nCIA_PLA),
- .cia_n(nCIA),
- .cnt(CNT),
- .exram_n(nEXTRAM),
- .sp(SP),
- .rw_n(RW),
- .irq_n(nIRQ)
- );
-
-endmodule
\ No newline at end of file
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/build_id.sv b/Computer_MiST/Commodore - MAX_MiST/rtl/build_id.sv
deleted file mode 100644
index 7d0ba7de..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/build_id.sv
+++ /dev/null
@@ -1,2 +0,0 @@
-`define BUILD_DATE "180103"
-`define BUILD_TIME "021747"
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/cart.sv b/Computer_MiST/Commodore - MAX_MiST/rtl/cart.sv
deleted file mode 100644
index 83235c84..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/cart.sv
+++ /dev/null
@@ -1,21 +0,0 @@
-module cart(
- input clk0,
- input [15:0] addr,
- input [7:0] data_i,
- output [7:0] data_o,
- output reg nmi,
- input reset,
- input romL, // romL signal in
- input romH,
- input rw_pla_n,
- input ba,
- input cia_pla_n,
- input cia_n,
- input cnt,
- input exram_n,
- input sp,
- input rw_n,
- input irq_n
-);
-
-endmodule
\ No newline at end of file
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/cia_6526.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/cia_6526.vhd
deleted file mode 100644
index a9766508..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/cia_6526.vhd
+++ /dev/null
@@ -1,783 +0,0 @@
--- -----------------------------------------------------------------------
---
--- FPGA 64
---
--- A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- 6526 Complex Interface Adapter
---
--- rev 1 - june17 / TOD alarms
--- -----------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity cia_6526 is
- generic (
- todEnabled : std_logic := '0'
- );
- port (
- clk: in std_logic;
- todClk: in std_logic;
- reset: in std_logic;
- enable: in std_logic;
- cs: in std_logic;
- we: in std_logic; -- Write strobe
- rd: in std_logic; -- Read strobe
-
- addr: in unsigned(3 downto 0);
- CIAdi: in unsigned(7 downto 0);
- CIAdo: out unsigned(7 downto 0);
-
- ppai: in unsigned(7 downto 0);
- ppao: out unsigned(7 downto 0);
- ppad: out unsigned(7 downto 0);
-
- ppbi: in unsigned(7 downto 0);
- ppbo: out unsigned(7 downto 0);
- ppbd: out unsigned(7 downto 0);
-
- flag_n: in std_logic;
- sp: out std_logic;
- cnt: out std_logic;
- irq_n: out std_logic
- );
-end cia_6526;
-
--- -----------------------------------------------------------------------
-
-architecture Behavioral of cia_6526 is
- -- IO ports
- signal pra: unsigned(7 downto 0);
- signal prb: unsigned(7 downto 0);
- signal ddra: unsigned(7 downto 0);
- signal ddrb: unsigned(7 downto 0);
-
- -- Timer to IO ports
- signal timerAPulse : std_logic;
- signal timerAToggle : std_logic;
- signal timerBPulse : std_logic;
- signal timerBToggle : std_logic;
-
- -- Timer A reload registers
- signal talo: unsigned(7 downto 0) := (others => '1');
- signal tahi: unsigned(7 downto 0) := (others => '1');
-
- -- Timer B reload registers
- signal tblo: unsigned(7 downto 0) := (others => '1');
- signal tbhi: unsigned(7 downto 0) := (others => '1');
-
- -- Timer A and B internal registers
- signal timerA : unsigned(15 downto 0);
- signal forceTimerA : std_logic;
- signal loadTimerA : std_logic;
- signal clkTimerA : std_logic; -- internal timer clock
-
- signal timerB: unsigned(15 downto 0);
- signal forceTimerB : std_logic;
- signal loadTimerB : std_logic;
- signal clkTimerB : std_logic; -- internal timer clock
-
- signal WR_Delay_offset : std_logic; -- adjustable WR signal delay - LCA jun17
-
- -- Config register A
- signal cra_start : std_logic;
- signal cra_pbon : std_logic;
- signal cra_outmode : std_logic;
- signal cra_runmode : std_logic;
- signal cra_runmode_reg : std_logic;
- signal cra_inmode : std_logic;
- signal cra_spmode : std_logic;
- signal cra_todin : std_logic;
-
- -- Config register B
- signal crb_start : std_logic;
- signal crb_pbon : std_logic;
- signal crb_outmode : std_logic;
- signal crb_runmode : std_logic;
- signal crb_runmode_reg : std_logic;
- signal crb_inmode5 : std_logic;
- signal crb_inmode6 : std_logic;
- signal crb_alarm : std_logic;
-
- -- TOD 50/60 hz clock
- signal todTick : std_logic;
- signal oldTodClk : std_logic;
- signal tod_clkcnt: unsigned(2 downto 0);
-
- -- TOD counters
- signal tod_running: std_logic;
- signal tod_10ths: unsigned(3 downto 0);
- signal tod_secs: unsigned(6 downto 0);
- signal tod_mins: unsigned(6 downto 0);
- signal tod_hrs: unsigned(7 downto 0);
- signal tod_pm: std_logic;
-
- -- TOD latches
- signal tod_latched: std_logic;
- signal tod_latch_10ths: unsigned(3 downto 0);
- signal tod_latch_secs: unsigned(6 downto 0);
- signal tod_latch_mins: unsigned(6 downto 0);
- signal tod_latch_hrs: unsigned(7 downto 0);
- constant tod_latch_pm: std_logic := '0';
-
- -- TOD alarms - LCA
- signal tod_10ths_alarm: unsigned(3 downto 0);
- signal tod_secs_alarm: unsigned(6 downto 0);
- signal tod_mins_alarm: unsigned(6 downto 0);
- signal tod_hrs_alarm: unsigned(7 downto 0);
- signal tod_pm_alarm: std_logic;
-
- -- Interrupt processing
- signal resetIrq : boolean;
- signal intr_flagn : std_logic;
- signal intr_serial : std_logic;
- signal intr_alarm : std_logic; -- LCA
- signal intr_timerA : std_logic;
- signal intr_timerB : std_logic;
- signal mask_timerA : std_logic;
- signal mask_timerB : std_logic;
- signal mask_alarm : std_logic; -- LCA
- signal mask_serial : std_logic;
- signal mask_flagn : std_logic;
- signal ir: std_logic;
-
- signal prevFlag_n: std_logic;
-
- signal myWr : std_logic;
- signal myRd : std_logic;
-begin
--- -----------------------------------------------------------------------
--- chip-select signals
--- -----------------------------------------------------------------------
- myWr <= cs and we;
- myRd <= cs and rd;
-
--- -----------------------------------------------------------------------
--- I/O ports
--- -----------------------------------------------------------------------
- -- Port A
- process(pra, ddra)
- begin
- ppad <= ddra;
- ppao <= pra or (not ddra);
- end process;
-
- -- Port B
- process(prb, ddrb, cra_pbon, cra_outmode, crb_pbon, crb_outmode, timerAPulse, timerAToggle, timerBPulse, timerBToggle)
- begin
- ppbd <= ddrb;
- ppbo <= prb or (not ddrb);
- if cra_pbon = '1' then
- ppbo(6) <= timerAPulse or (not ddrb(6));
- if cra_outmode = '1' then
- ppbo(6) <= timerAToggle or (not ddrb(6));
- end if;
- end if;
- if crb_pbon = '1' then
- ppbo(7) <= timerBPulse or (not ddrb(7));
- if crb_outmode = '1' then
- ppbo(7) <= timerBToggle or (not ddrb(7));
- end if;
- end if;
- end process;
-
- -- I/O port registers
- process(clk)
- begin
- if rising_edge(clk) then
- if myWr = '1' then
- case addr is
- when X"0" => pra <= CIAdi;
- when X"1" => prb <= CIAdi;
- when X"2" => ddra <= CIAdi;
- when X"3" => ddrb <= CIAdi;
- when others => null;
- end case;
- end if;
- if reset = '1' then
- pra <= (others => '0');
- prb <= (others => '0');
- ddra <= (others => '0');
- ddrb <= (others => '0');
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- TOD - time of day
--- -----------------------------------------------------------------------
- process(clk)
- begin
- -- Process rising edge on the todClk.
- -- There is a prescaler of 5 or 6 to get 10ths of seconds from
- -- 50 Hz or 60 Hz line frequency.
- --
- -- Output is a 'todTick' signal synchronished with enable signal (@ 1Mhz).
- if rising_edge(clk) then
- if todEnabled = '1' then
- if enable = '1' then
- todTick <= '0';
- end if;
-
- if todClk = '1' and oldTodClk = '0' then
- -- Divide by 5 or 6 dependng on 50/60 Hz flag.
- if tod_clkcnt /= "000" then
- tod_clkcnt <= tod_clkcnt - 1;
- else
- todTick <= tod_running;
- tod_clkcnt <= "101"; -- 60 Hz
- if cra_todin = '1' then
- tod_clkcnt <= "100"; -- 50 Hz
- end if;
- end if;
- end if;
- oldTodClk <= todClk;
- else
- todTick <= '0';
- end if;
- end if;
- end process;
-
- process(clk)
- variable new_10ths : unsigned(3 downto 0);
- variable new_secsL : unsigned(3 downto 0);
- variable new_secsH : unsigned(2 downto 0);
- variable new_minsL : unsigned(3 downto 0);
- variable new_minsH : unsigned(2 downto 0);
- variable new_hrsL : unsigned(3 downto 0);
- variable new_hrsH : std_logic;
- variable new_hrs_byte : unsigned(7 downto 0); -- LCA am/pm and hours
- begin
- if rising_edge(clk) then
- new_10ths := tod_10ths;
- new_secsL := tod_secs(3 downto 0);
- new_secsH := tod_secs(6 downto 4);
- new_minsL := tod_mins(3 downto 0);
- new_minsH := tod_mins(6 downto 4);
--- new_hrsL := tod_hrs(3 downto 0);
--- new_hrsH := tod_hrs(4);
- new_hrs_byte := tod_hrs (7 downto 0); -- LCA am/pm and hours
--- new_hrs_byte := new_hrsH & new_hrsL;
-
- if enable = '1'
- and todTick = '1' then
- if new_10ths /= "1001" then
- new_10ths := new_10ths + 1;
- else
- new_10ths := "0000";
- if new_secsL /= "1001" then
- new_secsL := new_secsL + 1;
- else
- new_secsL := "0000";
- if new_secsH /= "101" then
- new_secsH := new_secsH + 1;
- else
- new_secsH := "000";
- if new_minsL /= "1001" then
- new_minsL := new_minsL + 1;
- else
- new_minsL := "0000";
- if new_minsH /= "101" then
- new_minsH := new_minsH + 1;
- else
- new_minsH := "000";
- -- hrs were missing jun17 LCA
- -- I mean completely absent from code :) !!!!!!
- -- case to lookup then handles oddities in others
- -- retarded am/pm flag flip madness handled at register load below (REG B)
-
- case tod_hrs is -- case state to set hours and am/pm
- when "00010010" =>
- new_hrs_byte := "00000001"; -- 1 am set
- when "00000001" =>
- new_hrs_byte := "00000010";
- when "00000010" =>
- new_hrs_byte := "00000011";
- when "00000011" =>
- new_hrs_byte := "00000100";
- when "00000100" =>
- new_hrs_byte := "00000101";
- when "00000101" =>
- new_hrs_byte := "00000110";
- when "00000110" =>
- new_hrs_byte := "00000111";
- when "00000111" =>
- new_hrs_byte := "00001000";
- when "00001000" =>
- new_hrs_byte := "00001001";
- when "00001001" =>
- new_hrs_byte := "00010000";
- when "00010000" =>
- new_hrs_byte := "00010001"; -- 11am set
- when "00010001" =>
- new_hrs_byte := "10010010"; -- 12pm set
- when "10010010" =>
- new_hrs_byte := "10000001"; -- 1 pm set
-
- when "10000001" =>
- new_hrs_byte := "10000010";
- when "10000010" =>
- new_hrs_byte := "10000011";
- when "10000011" =>
- new_hrs_byte := "10000100";
- when "10000100" =>
- new_hrs_byte := "10000101";
- when "10000101" =>
- new_hrs_byte := "10000110";
- when "10000110" =>
- new_hrs_byte := "10000111";
- when "10000111" =>
- new_hrs_byte := "10001000";
- when "10001000" =>
- new_hrs_byte := "10001001";
- when "10001001" =>
- new_hrs_byte := "10010000"; -- 10pm set
- when "10010000" =>
- new_hrs_byte := "10010001"; -- 11pm set
- when "10010001" =>
- new_hrs_byte := "00010010"; -- 12am set (midnight)
- when others =>
- new_hrs_byte (3 downto 0) := new_hrs_byte (3 downto 0) + 1;
- --null;
- end case;
-
- end if;
- end if;
- end if;
- end if;
- end if;
- end if;
-
- if myWr = '1' then
- if crb_alarm = '0' then
- case addr is
- when X"8" =>
- new_10ths := CIAdi(3 downto 0);
- tod_running <= '1';
- when X"9" =>
- new_secsL := CIAdi(3 downto 0);
- new_secsH := CIAdi(6 downto 4);
- when X"A" =>
- new_minsL := CIAdi(3 downto 0);
- new_minsH := CIAdi(6 downto 4);
- when X"B" =>
- new_hrs_byte := CIAdi(7) & "00" & CIAdi(4 downto 0); -- LCA
- tod_running <= '0';
- if CIAdi(7 downto 0) = "10010010" or CIAdi(7 downto 0) = "00010010" then -- super bodge because cbm flips am/pm flag at 12 am or pm (its retarded!!!!!)
- new_hrs_byte(7) := not new_hrs_byte(7); -- This P.O.S. now mimics real commodore 64 !!!!! LCA
- end if;
- when others =>
- null;
- end case;
- else -- TOD ALARM UPDATE
- case addr is
- when X"8" =>
- tod_10ths_alarm <= CIAdi(3 downto 0);
- when X"9" =>
- tod_secs_alarm <= CIAdi(6 downto 0);
- when X"A" =>
- tod_mins_alarm <= CIAdi(6 downto 0);
- when X"B" =>
--- tod_hrs_alarm <= CIAdi(4 downto 0);
--- tod_pm_alarm <= CIAdi(7);
- tod_hrs_alarm <= CIAdi(7) & "00" & CIAdi(4 downto 0); -- LCA
- if CIAdi(7 downto 0) = "10010010" or CIAdi(7 downto 0) = "00010010" then -- super bodge because cbm flips am/pm flag at 12 am or pm (its retarded!!!!!)
- tod_hrs_alarm(7) <= not tod_hrs_alarm(7); -- This P.O.S. now mimics real commodore 64 !!!!! LCA
- end if;
- when others =>
- null;
- end case;
- end if;
- end if;
-
- -- Update state
- tod_10ths <= new_10ths;
- tod_secs <= new_secsH & new_secsL;
- tod_mins <= new_minsH & new_minsL;
- tod_hrs <= new_hrs_byte; -- LCA
-
- if tod_latched = '0' then
- tod_latch_10ths <= new_10ths;
- tod_latch_secs <= new_secsH & new_secsL;
- tod_latch_mins <= new_minsH & new_minsL;
- tod_latch_hrs <= new_hrs_byte; -- LCA
- end if;
-
- -- TOD ALARM test for match - LCA
- if (tod_10ths = tod_10ths_alarm) and
- (tod_secs = tod_secs_alarm) and
- (tod_mins = tod_mins_alarm) and
- (tod_hrs = tod_hrs_alarm) and
- (crb_alarm = '1') then
- intr_alarm <= '1' ;
- end if;
-
- if reset = '1' then
- tod_running <= '0';
- tod_10ths_alarm <= "0000" ;
- tod_secs_alarm <= "0000000" ;
- tod_mins_alarm <= "0000000" ;
- tod_hrs_alarm <= "00000000" ;
- tod_pm_alarm <= '0' ;
- end if;
-
- if resetIrq then
- intr_alarm <= '0' ;
- end if;
- end if;
- end process;
-
- -- Control TOD output latch
- -- Reading the hours latches the output until
- -- the 10ths of seconds are read. While latched the
- -- clock continues to run in the bankground.
- process(clk)
- begin
- if rising_edge(clk) then
- if myRd = '1' then
- case addr is
- when X"8" => tod_latched <= '0';
- when X"B" => tod_latched <= '1';
- when others => null;
- end case;
- end if;
- end if;
- end process;
-
-
--- -----------------------------------------------------------------------
--- Timer A and B
--- -----------------------------------------------------------------------
-
-
--- adjustable time delay jun17 - LCA
-
--- -----------------------------------------------------------------------
--- -----------------------------------------------------------------------
-
- process(clk)
- variable WR_delay : unsigned(15 downto 0);
- begin
- if rising_edge(clk) then
- if (myWr = '0' or reset = '1') then
- WR_delay := "0000000000000000";
- WR_Delay_offset <= '0';
--- end if;
- elsif (myWr = '1' and (WR_delay < 31)) then
- WR_delay := WR_delay + 1;
--- end if;
- elsif (WR_delay > 8) then -- adds a (1/32mhz * value) qualifier to WR signal in timers - LCA jun17
- WR_Delay_offset <= '1';
- else
- WR_Delay_offset <= '0';
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
-
- process(clk)
- variable newTimerA : unsigned(15 downto 0);
- variable nextClkTimerA : std_logic;
- variable timerBInput : std_logic;
- variable newTimerB : unsigned(15 downto 0);
- variable nextClkTimerB : std_logic;
- variable new_cra_runmode : std_logic;
- variable new_crb_runmode : std_logic;
- begin
- if rising_edge(clk) then
- loadTimerA <= '0';
- loadTimerB <= '0';
- new_cra_runmode := cra_runmode;
- new_crb_runmode := crb_runmode;
-
- if resetIrq then
- intr_timerA <= '0';
- intr_timerB <= '0';
- end if;
-
- if myWr = '1' then
--- if (myWr = '1' and WR_Delay_offset = '1') then -- x/32mhz offset to qualify WR signal LCA jun17
- case addr is
- when X"4" =>
- talo <= CIAdi;
- when X"5" =>
- tahi <= CIAdi;
- if cra_start = '0' then
- loadTimerA <= '1';
- end if;
- when X"6" =>
- tblo <= CIAdi;
- when X"7" =>
- tbhi <= CIAdi;
- if crb_start = '0' then
- loadTimerB <= '1';
- end if;
- when X"E" =>
- if cra_start = '0' then
- -- Only set on rising edge
- timerAToggle <= timerAToggle or CIAdi(0);
- end if;
- cra_start <= CIAdi(0);
- new_cra_runmode := CIAdi(3);
- when X"F" =>
- if crb_start = '0' then
- -- Only set on rising edge
- timerBToggle <= timerBToggle or CIAdi(0);
- end if;
- crb_start <= CIAdi(0);
- new_crb_runmode := CIAdi(3);
- when others => null;
- end case;
- end if;
-
- if reset = '1' then
- new_cra_runmode := '0';
- new_crb_runmode := '0';
- end if;
-
- cra_runmode <= new_cra_runmode;
- crb_runmode <= new_crb_runmode;
-
- if enable = '1' then
- --
- -- process timer A
- --
- timerAPulse <= '0';
- newTimerA := timerA;
-
- -- CNT is not emulated so don't count when inmode = 1
- nextClkTimerA := cra_start and (not cra_inmode);
- if clkTimerA = '1' then
- newTimerA := newTimerA - 1;
- end if;
- if nextClkTimerA = '1'
- and newTimerA = 0 then
- intr_timerA <= '1';
- loadTimerA <= '1';
- timerAPulse <= '1';
- timerAToggle <= not timerAToggle;
- if (new_cra_runmode or cra_runmode) = '1' then
- cra_start <= '0';
- end if;
- end if;
- if forceTimerA = '1' then
- loadTimerA <= '1';
- end if;
- clkTimerA <= nextClkTimerA;
- timerA <= newTimerA;
-
- --
- -- process timer B
- --
- timerBPulse <= '0';
- newTimerB := timerB;
-
- if crb_inmode6 = '1' then
- -- count timerA underflows
- timerBInput := timerAPulse;
- elsif crb_inmode5 = '0' then
- -- count clock pulses
- timerBInput := '1';
- else
- -- CNT is not emulated so don't count
- timerBInput := '0';
- end if;
- nextClkTimerB := timerBInput and crb_start;
- if clkTimerB = '1' then
- newTimerB := newTimerB - 1;
- end if;
- if nextClkTimerB = '1'
- and newTimerB = 0 then
- intr_timerB <= '1';
- loadTimerB <= '1';
- timerBPulse <= '1';
- timerBToggle <= not timerBToggle;
- if (new_crb_runmode or crb_runmode) = '1' then
- crb_start <= '0';
- end if;
- end if;
- if forceTimerB = '1' then
- loadTimerB <= '1';
- end if;
- clkTimerB <= nextClkTimerB;
- timerB <= newTimerB;
- end if;
-
- if loadTimerA = '1' then
- timerA <= tahi & talo;
- clkTimerA <= '0';
- end if;
-
- if loadTimerB = '1' then
- timerB <= tbhi & tblo;
- clkTimerB <= '0';
- end if;
- end if;
- end process;
-
-
--- -----------------------------------------------------------------------
--- Interrupts
--- -----------------------------------------------------------------------
- resetIrq <= ((myRd = '1') and (addr = X"D")) or (reset = '1');
- irq_n <= not(ir);
- intr_serial <= '0';
-
- process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- ir <= ir
- or (intr_timerA and mask_timerA)
- or (intr_timerB and mask_timerB)
- or (intr_alarm and mask_alarm)
- or (intr_serial and mask_serial)
- or (intr_flagn and mask_flagn);
- end if;
-
- if myWr = '1' then
- case addr is
- when X"D" =>
- if CIAdi(7) ='0' then
- mask_timerA <= mask_timerA and (not CIAdi(0));
- mask_timerB <= mask_timerB and (not CIAdi(1));
- mask_alarm <= mask_alarm and (not CIAdi(2)); -- LCA
- mask_serial <= mask_serial and (not CIAdi(3));
- mask_flagn <= mask_flagn and (not CIAdi(4));
- else
- mask_timerA <= mask_timerA or CIAdi(0);
- mask_timerB <= mask_timerB or CIAdi(1);
- mask_alarm <= mask_alarm or CIAdi(2); -- LCA
- mask_serial <= mask_serial or CIAdi(3);
- mask_flagn <= mask_flagn or CIAdi(4);
- end if;
- when others =>
- null;
- end case;
- end if;
-
- if resetIrq then
- ir <= '0';
- end if;
-
- if reset = '1' then
- mask_timerA <= '0';
- mask_timerB <= '0';
- mask_alarm <= '0' ;
- mask_serial <= '0';
- mask_flagn <= '0';
- end if;
- end if;
- end process;
-
-
-
-
--- -----------------------------------------------------------------------
--- FLAG_N input
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- prevFlag_n <= flag_n;
- if (flag_n = '0') and (prevFlag_n = '1') then
- intr_flagn <= '1';
- end if;
- if resetIrq then
- intr_flagn <= '0';
- end if;
- end if;
- end process;
-
-
--- -----------------------------------------------------------------------
--- Write registers
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
--- resetIrq <= '0';
- if enable = '1' then
- forceTimerA <= '0';
- forceTimerB <= '0';
--- cra_runmode_reg <= cra_runmode;
--- crb_runmode_reg <= crb_runmode;
- end if;
- if myWr = '1' then
- case addr is
- when X"E" =>
- cra_pbon <= CIAdi(1);
- cra_outmode <= CIAdi(2);
--- cra_runmode <= CIAdi(3);
- forceTimerA <= CIAdi(4);
- cra_inmode <= CIAdi(5);
- cra_spmode <= CIAdi(6);
- cra_todin <= CIAdi(7);
- when X"F" =>
- crb_pbon <= CIAdi(1);
- crb_outmode <= CIAdi(2);
--- crb_runmode <= CIAdi(3);
- forceTimerB <= CIAdi(4);
- crb_inmode5 <= CIAdi(5);
- crb_inmode6 <= CIAdi(6);
- crb_alarm <= CIAdi(7);
- when others => null;
- end case;
- end if;
- if reset = '1' then
- cra_pbon <= '0';
- cra_outmode <= '0';
--- cra_runmode <= '0';
- cra_inmode <= '0';
- cra_spmode <= '0';
- cra_todin <= '0';
- crb_pbon <= '0';
- crb_outmode <= '0';
--- crb_runmode <= '0';
- crb_inmode5 <= '0';
- crb_inmode6 <= '0';
- crb_alarm <= '0';
- end if;
- end if;
- end process;
-
-
--- -----------------------------------------------------------------------
--- Read registers
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- case addr is
- when X"0" => CIAdo <= ppai;
- when X"1" => CIAdo <= ppbi;
- when X"2" => CIAdo <= DDRA;
- when X"3" => CIAdo <= DDRB;
- when X"4" => CIAdo <= timera(7 downto 0);
- when X"5" => CIAdo <= timera(15 downto 8);
- when X"6" => CIAdo <= timerb(7 downto 0);
- when X"7" => CIAdo <= timerb(15 downto 8);
- when X"8" => CIAdo <= "0000" & tod_latch_10ths;
- when X"9" => CIAdo <= "0" & tod_latch_secs;
- when X"A" => CIAdo <= "0" & tod_latch_mins;
--- when X"B" => CIAdo <= tod_latch_pm & "00" & tod_latch_hrs;
- when X"B" => CIAdo <= tod_latch_hrs; -- LCA
- when X"C" => CIAdo <= (others => '0');
- when X"D" => CIAdo <= ir & "00" & intr_flagn & intr_serial & intr_alarm & intr_timerB & intr_timerA;
- when X"E" => CIAdo <= cra_todin & cra_spmode & cra_inmode & '0' & cra_runmode & cra_outmode & cra_pbon & cra_start;
- when X"F" => CIAdo <= crb_alarm & crb_inmode6 & crb_inmode5 & '0' & crb_runmode & crb_outmode & crb_pbon & crb_start;
- when others => CIAdo <= (others => '-');
- end case;
- end if;
- end process;
-end Behavioral;
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/cpu65xx_e.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/cpu65xx_e.vhd
deleted file mode 100644
index 27166e7a..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/cpu65xx_e.vhd
+++ /dev/null
@@ -1,49 +0,0 @@
--- -----------------------------------------------------------------------
---
--- FPGA 64
---
--- A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- Interface to 6502/6510 core
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use ieee.std_logic_1164.ALL;
-use ieee.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity cpu65xx is
- generic (
- pipelineOpcode : boolean;
- pipelineAluMux : boolean;
- pipelineAluOut : boolean
- );
- port (
- clk : in std_logic;
- enable : in std_logic;
- reset : in std_logic;
- nmi_n : in std_logic;
- nmi_ack : out std_logic;
- irq_n : in std_logic;
- so_n : in std_logic := '1';
-
- di : in unsigned(7 downto 0);
- do : out unsigned(7 downto 0);
- addr : out unsigned(15 downto 0);
- we : out std_logic;
-
- debugOpcode : out unsigned(7 downto 0);
- debugPc : out unsigned(15 downto 0);
- debugA : out unsigned(7 downto 0);
- debugX : out unsigned(7 downto 0);
- debugY : out unsigned(7 downto 0);
- debugS : out unsigned(7 downto 0)
- );
-end cpu65xx;
\ No newline at end of file
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/cpu65xx_fast.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/cpu65xx_fast.vhd
deleted file mode 100644
index a387b37d..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/cpu65xx_fast.vhd
+++ /dev/null
@@ -1,1565 +0,0 @@
--- -----------------------------------------------------------------------
---
--- FPGA 64
---
--- A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- Table driven, cycle exact 6502/6510 core
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use ieee.std_logic_1164.ALL;
-use ieee.std_logic_unsigned.ALL;
-use ieee.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
--- Store Zp (3) => fetch, cycle2, cycleEnd
--- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
--- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
--- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
--- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
--- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
--- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
--- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
--- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
--- Jmp abs (-) => fetch, cycle2, .., cycleJump
--- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
--- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
--- -----------------------------------------------------------------------
-
-architecture fast of cpu65xx is
--- Statemachine
- type cpuCycles is (
- opcodeFetch, -- New opcode is read and registers updated
- cycle2,
- cycle3,
- cyclePreIndirect,
- cycleIndirect,
- cycleBranchTaken,
- cycleBranchPage,
- cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
- cycleRead, -- Read cycle
- cycleRead2, -- Second read cycle after page-boundary crossing.
- cycleRmw, -- Calculate ALU output for read-modify-write instr.
- cyclePreWrite, -- Cycle before write when doing indexed addressing.
- cycleWrite, -- Write cycle for zeropage or absolute addressing.
- cycleStack1,
- cycleStack2,
- cycleStack3,
- cycleStack4,
- cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
- cycleEnd
- );
- signal theCpuCycle : cpuCycles;
- signal nextCpuCycle : cpuCycles;
- signal updateRegisters : boolean;
- signal processIrq : std_logic;
- signal nmiReg: std_logic;
- signal nmiEdge: std_logic;
- signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
- signal soReg : std_logic; -- SO pin edge detection
-
--- Opcode decoding
- constant opcUpdateA : integer := 0;
- constant opcUpdateX : integer := 1;
- constant opcUpdateY : integer := 2;
- constant opcUpdateS : integer := 3;
- constant opcUpdateN : integer := 4;
- constant opcUpdateV : integer := 5;
- constant opcUpdateD : integer := 6;
- constant opcUpdateI : integer := 7;
- constant opcUpdateZ : integer := 8;
- constant opcUpdateC : integer := 9;
-
- constant opcSecondByte : integer := 10;
- constant opcAbsolute : integer := 11;
- constant opcZeroPage : integer := 12;
- constant opcIndirect : integer := 13;
- constant opcStackAddr : integer := 14; -- Push/Pop address
- constant opcStackData : integer := 15; -- Push/Pop status/data
- constant opcJump : integer := 16;
- constant opcBranch : integer := 17;
- constant indexX : integer := 18;
- constant indexY : integer := 19;
- constant opcStackUp : integer := 20;
- constant opcWrite : integer := 21;
- constant opcRmw : integer := 22;
- constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
- constant opcRti : integer := 24;
- constant opcIRQ : integer := 25;
-
- constant opcInA : integer := 26;
- constant opcInE : integer := 27;
- constant opcInX : integer := 28;
- constant opcInY : integer := 29;
- constant opcInS : integer := 30;
- constant opcInT : integer := 31;
- constant opcInH : integer := 32;
- constant opcInClear : integer := 33;
- constant aluMode1From : integer := 34;
- --
- constant aluMode1To : integer := 37;
- constant aluMode2From : integer := 38;
- --
- constant aluMode2To : integer := 40;
- --
- constant opcInCmp : integer := 41;
- constant opcInCpx : integer := 42;
- constant opcInCpy : integer := 43;
-
-
- subtype addrDef is unsigned(0 to 15);
- --
- -- is Interrupt -----------------+
- -- instruction is RTI ----------------+|
- -- PC++ on last cycle (RTS) ---------------+||
- -- RMW --------------+|||
- -- Write -------------+||||
- -- Pop/Stack up -------------+|||||
- -- Branch ---------+ ||||||
- -- Jump ----------+| ||||||
- -- Push or Pop data -------+|| ||||||
- -- Push or Pop addr ------+||| ||||||
- -- Indirect -----+|||| ||||||
- -- ZeroPage ----+||||| ||||||
- -- Absolute ---+|||||| ||||||
- -- PC++ on cycle2 --+||||||| ||||||
- -- |AZI||JBXY|WM|||
- constant immediate : addrDef := "1000000000000000";
- constant implied : addrDef := "0000000000000000";
- -- Zero page
- constant readZp : addrDef := "1010000000000000";
- constant writeZp : addrDef := "1010000000010000";
- constant rmwZp : addrDef := "1010000000001000";
- -- Zero page indexed
- constant readZpX : addrDef := "1010000010000000";
- constant writeZpX : addrDef := "1010000010010000";
- constant rmwZpX : addrDef := "1010000010001000";
- constant readZpY : addrDef := "1010000001000000";
- constant writeZpY : addrDef := "1010000001010000";
- constant rmwZpY : addrDef := "1010000001001000";
- -- Zero page indirect
- constant readIndX : addrDef := "1001000010000000";
- constant writeIndX : addrDef := "1001000010010000";
- constant rmwIndX : addrDef := "1001000010001000";
- constant readIndY : addrDef := "1001000001000000";
- constant writeIndY : addrDef := "1001000001010000";
- constant rmwIndY : addrDef := "1001000001001000";
- -- |AZI||JBXY|WM||
- -- Absolute
- constant readAbs : addrDef := "1100000000000000";
- constant writeAbs : addrDef := "1100000000010000";
- constant rmwAbs : addrDef := "1100000000001000";
- constant readAbsX : addrDef := "1100000010000000";
- constant writeAbsX : addrDef := "1100000010010000";
- constant rmwAbsX : addrDef := "1100000010001000";
- constant readAbsY : addrDef := "1100000001000000";
- constant writeAbsY : addrDef := "1100000001010000";
- constant rmwAbsY : addrDef := "1100000001001000";
- -- PHA PHP
- constant push : addrDef := "0000010000000000";
- -- PLA PLP
- constant pop : addrDef := "0000010000100000";
- -- Jumps
- constant jsr : addrDef := "1000101000000000";
- constant jumpAbs : addrDef := "1000001000000000";
- constant jumpInd : addrDef := "1100001000000000";
- constant relative : addrDef := "1000000100000000";
- -- Specials
- constant rts : addrDef := "0000101000100100";
- constant rti : addrDef := "0000111000100010";
- constant brk : addrDef := "1000111000000001";
--- constant : unsigned(0 to 0) := "0";
- constant xxxxxxxx : addrDef := "----------0---00";
-
- -- A = accu
- -- E = Accu | 0xEE (for ANE, LXA)
- -- X = index X
- -- Y = index Y
- -- S = Stack pointer
- -- H = indexH
- --
- -- AEXYSTHc
- constant aluInA : unsigned(0 to 7) := "10000000";
- constant aluInE : unsigned(0 to 7) := "01000000";
- constant aluInEXT : unsigned(0 to 7) := "01100100";
- constant aluInET : unsigned(0 to 7) := "01000100";
- constant aluInX : unsigned(0 to 7) := "00100000";
- constant aluInXH : unsigned(0 to 7) := "00100010";
- constant aluInY : unsigned(0 to 7) := "00010000";
- constant aluInYH : unsigned(0 to 7) := "00010010";
- constant aluInS : unsigned(0 to 7) := "00001000";
- constant aluInT : unsigned(0 to 7) := "00000100";
- constant aluInAX : unsigned(0 to 7) := "10100000";
- constant aluInAXH : unsigned(0 to 7) := "10100010";
- constant aluInAT : unsigned(0 to 7) := "10000100";
- constant aluInXT : unsigned(0 to 7) := "00100100";
- constant aluInST : unsigned(0 to 7) := "00001100";
- constant aluInSet : unsigned(0 to 7) := "00000000";
- constant aluInClr : unsigned(0 to 7) := "00000001";
- constant aluInXXX : unsigned(0 to 7) := "--------";
-
- -- Most of the aluModes are just like the opcodes.
- -- aluModeInp -> input is output. calculate N and Z
- -- aluModeCmp -> Compare for CMP, CPX, CPY
- -- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
- -- aluModeInc -> for INC but also INX, INY
- -- aluModeDec -> for DEC but also DEX, DEY
-
- subtype aluMode1 is unsigned(0 to 3);
- subtype aluMode2 is unsigned(0 to 2);
- subtype aluMode is unsigned(0 to 9);
-
- -- Logic/Shift ALU
- constant aluModeInp : aluMode1 := "0000";
- constant aluModeP : aluMode1 := "0001";
- constant aluModeInc : aluMode1 := "0010";
- constant aluModeDec : aluMode1 := "0011";
- constant aluModeFlg : aluMode1 := "0100";
- constant aluModeBit : aluMode1 := "0101";
- -- 0110
- -- 0111
- constant aluModeLsr : aluMode1 := "1000";
- constant aluModeRor : aluMode1 := "1001";
- constant aluModeAsl : aluMode1 := "1010";
- constant aluModeRol : aluMode1 := "1011";
- -- 1100
- -- 1101
- -- 1110
- constant aluModeAnc : aluMode1 := "1111";
-
- -- Arithmetic ALU
- constant aluModePss : aluMode2 := "000";
- constant aluModeCmp : aluMode2 := "001";
- constant aluModeAdc : aluMode2 := "010";
- constant aluModeSbc : aluMode2 := "011";
- constant aluModeAnd : aluMode2 := "100";
- constant aluModeOra : aluMode2 := "101";
- constant aluModeEor : aluMode2 := "110";
- constant aluModeArr : aluMode2 := "111";
-
-
- constant aluInp : aluMode := aluModeInp & aluModePss & "---";
- constant aluP : aluMode := aluModeP & aluModePss & "---";
- constant aluInc : aluMode := aluModeInc & aluModePss & "---";
- constant aluDec : aluMode := aluModeDec & aluModePss & "---";
- constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
- constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
- constant aluRor : aluMode := aluModeRor & aluModePss & "---";
- constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
- constant aluRol : aluMode := aluModeRol & aluModePss & "---";
- constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
-
- constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
- constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
- constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
- constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
- constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
- constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
- constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
- constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
-
- constant aluSlo : aluMode := aluModeAsl & aluModeOra & "---";
- constant aluSre : aluMode := aluModeLsr & aluModeEor & "---";
- constant aluRra : aluMode := aluModeRor & aluModeAdc & "---";
- constant aluRla : aluMode := aluModeRol & aluModeAnd & "---";
- constant aluDcp : aluMode := aluModeDec & aluModeCmp & "100";
- constant aluIsc : aluMode := aluModeInc & aluModeSbc & "---";
- constant aluAnc : aluMode := aluModeAnc & aluModeAnd & "---";
- constant aluArr : aluMode := aluModeRor & aluModeArr & "---";
- constant aluSbx : aluMode := aluModeInp & aluModeCmp & "110";
-
- constant aluXXX : aluMode := (others => '-');
-
-
- -- Stack operations. Push/Pop/None
- constant stackInc : unsigned(0 to 0) := "0";
- constant stackDec : unsigned(0 to 0) := "1";
- constant stackXXX : unsigned(0 to 0) := "-";
-
- subtype decodedBitsDef is unsigned(0 to 43);
- type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
- constant opcodeInfoTable : opcodeInfoTableDef := (
- -- +------- Update register A
- -- |+------ Update register X
- -- ||+----- Update register Y
- -- |||+---- Update register S
- -- |||| +-- Update Flags
- -- |||| |
- -- |||| _|__
- -- |||| / \
- -- AXYS NVDIZC addressing aluInput aluMode
- "0000" & "000100" & brk & aluInXXX & aluP, -- 00 BRK
- "1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 02 *** JAM ***
- "1000" & "100011" & rmwIndX & aluInT & aluSlo, -- 03 iSLO (zp,x)
- "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 04 iNOP zp
- "1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
- "0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
- "1000" & "100011" & rmwZp & aluInT & aluSlo, -- 07 iSLO zp
- "0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
- "1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
- "1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
- "1000" & "100011" & immediate & aluInT & aluAnc, -- 0B iANC imm
- "0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 0C iNOP abs
- "1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
- "0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
- "1000" & "100011" & rmwAbs & aluInT & aluSlo, -- 0F iSLO abs
- "0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
- "1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 12 *** JAM ***
- "1000" & "100011" & rmwIndY & aluInT & aluSlo, -- 13 iSLO (zp),y
- "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 14 iNOP zp,x
- "1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
- "0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
- "1000" & "100011" & rmwZpX & aluInT & aluSlo, -- 17 iSLO zp,x
- "0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
- "1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
- "0000" & "000000" & implied & aluInXXX & aluXXX, -- 1A iNOP implied
- "1000" & "100011" & rmwAbsY & aluInT & aluSlo, -- 1B iSLO abs,y
- "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 1C iNOP abs,x
- "1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
- "0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
- "1000" & "100011" & rmwAbsX & aluInT & aluSlo, -- 1F iSLO abs,x
- -- AXYS NVDIZC addressing aluInput aluMode
- "0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
- "1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 22 *** JAM ***
- "1000" & "100011" & rmwIndX & aluInT & aluRla, -- 23 iRLA (zp,x)
- "0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
- "1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
- "0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
- "1000" & "100011" & rmwZp & aluInT & aluRla, -- 27 iRLA zp
- "0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
- "1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
- "1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
- "1000" & "100011" & immediate & aluInT & aluAnc, -- 2B iANC imm
- "0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
- "1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
- "0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
- "1000" & "100011" & rmwAbs & aluInT & aluRla, -- 2F iRLA abs
- "0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
- "1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 32 *** JAM ***
- "1000" & "100011" & rmwIndY & aluInT & aluRla, -- 33 iRLA (zp),y
- "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 34 iNOP zp,x
- "1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
- "0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
- "1000" & "100011" & rmwZpX & aluInT & aluRla, -- 37 iRLA zp,x
- "0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
- "1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
- "0000" & "000000" & implied & aluInXXX & aluXXX, -- 3A iNOP implied
- "1000" & "100011" & rmwAbsY & aluInT & aluRla, -- 3B iRLA abs,y
- "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 3C iNOP abs,x
- "1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
- "0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
- "1000" & "100011" & rmwAbsX & aluInT & aluRla, -- 3F iRLA abs,x
- -- AXYS NVDIZC addressing aluInput aluMode
- "0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
- "1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 42 *** JAM ***
- "1000" & "100011" & rmwIndX & aluInT & aluSre, -- 43 iSRE (zp,x)
- "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 44 iNOP zp
- "1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
- "0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
- "1000" & "100011" & rmwZp & aluInT & aluSre, -- 47 iSRE zp
- "0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
- "1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
- "1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu
- "1000" & "100011" & immediate & aluInAT & aluLsr, -- 4B iALR imm
- "0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
- "1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
- "0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
- "1000" & "100011" & rmwAbs & aluInT & aluSre, -- 4F iSRE abs
- "0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
- "1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 52 *** JAM ***
- "1000" & "100011" & rmwIndY & aluInT & aluSre, -- 53 iSRE (zp),y
- "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 54 iNOP zp,x
- "1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
- "0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
- "1000" & "100011" & rmwZpX & aluInT & aluSre, -- 57 SRE zp,x
- "0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
- "1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
- "0000" & "000000" & implied & aluInXXX & aluXXX, -- 5A iNOP implied
- "1000" & "100011" & rmwAbsY & aluInT & aluSre, -- 5B iSRE abs,y
- "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 5C iNOP abs,x
- "1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
- "0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
- "1000" & "100011" & rmwAbsX & aluInT & aluSre, -- 5F SRE abs,x
- -- AXYS NVDIZC addressing aluInput aluMode
- "0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
- "1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 62 *** JAM ***
- "1000" & "110011" & rmwIndX & aluInT & aluRra, -- 63 iRRA (zp,x)
- "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 64 iNOP zp
- "1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
- "0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
- "1000" & "110011" & rmwZp & aluInT & aluRra, -- 67 iRRA zp
- "1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
- "1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
- "1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
- "1000" & "110011" & immediate & aluInAT & aluArr, -- 6B iARR imm
- "0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
- "1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
- "0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
- "1000" & "110011" & rmwAbs & aluInT & aluRra, -- 6F iRRA abs
- "0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
- "1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 72 *** JAM ***
- "1000" & "110011" & rmwIndY & aluInT & aluRra, -- 73 iRRA (zp),y
- "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 74 iNOP zp,x
- "1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
- "0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
- "1000" & "110011" & rmwZpX & aluInT & aluRra, -- 77 iRRA zp,x
- "0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
- "1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
- "0000" & "000000" & implied & aluInXXX & aluXXX, -- 7A iNOP implied
- "1000" & "110011" & rmwAbsY & aluInT & aluRra, -- 7B iRRA abs,y
- "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 7C iNOP abs,x
- "1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
- "0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
- "1000" & "110011" & rmwAbsX & aluInT & aluRra, -- 7F iRRA abs,x
- -- AXYS NVDIZC addressing aluInput aluMode
- "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
- "0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
- "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
- "0000" & "000000" & writeIndX & aluInAX & aluInp, -- 83 iSAX (zp,x)
- "0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
- "0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
- "0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
- "0000" & "000000" & writeZp & aluInAX & aluInp, -- 87 iSAX zp
- "0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
- "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
- "1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
- "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
- "0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs
- "0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
- "0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
- "0000" & "000000" & writeAbs & aluInAX & aluInp, -- 8F iSAX abs
- "0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
- "0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 92 *** JAM ***
- "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
- "0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
- "0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
- "0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
- "0000" & "000000" & writeZpY & aluInAX & aluInp, -- 97 iSAX zp,y
- "1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
- "0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
- "0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
- "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
- "0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x
- "0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
- "0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y
- "0000" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9F iAHX abs,y
- -- AXYS NVDIZC addressing aluInput aluMode
- "0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
- "1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
- "0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
- "1100" & "100010" & readIndX & aluInT & aluInp, -- A3 LAX (zp,x)
- "0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
- "1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
- "0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
- "1100" & "100010" & readZp & aluInT & aluInp, -- A7 iLAX zp
- "0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
- "1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
- "0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
- "1100" & "100010" & immediate & aluInET & aluInp, -- AB iLXA imm
- "0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
- "1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
- "0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
- "1100" & "100010" & readAbs & aluInT & aluInp, -- AF iLAX abs
- "0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
- "1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- B2 *** JAM ***
- "1100" & "100010" & readIndY & aluInT & aluInp, -- B3 iLAX (zp),y
- "0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
- "1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
- "0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
- "1100" & "100010" & readZpY & aluInT & aluInp, -- B7 iLAX zp,y
- "0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
- "1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
- "0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
- "1101" & "100010" & readAbsY & aluInST & aluInp, -- BB iLAS abs,y
- "0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
- "1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
- "0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
- "1100" & "100010" & readAbsY & aluInT & aluInp, -- BF iLAX abs,y
- -- AXYS NVDIZC addressing aluInput aluMode
- "0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
- "0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
- "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
- "0000" & "100011" & rmwIndX & aluInT & aluDcp, -- C3 iDCP (zp,x)
- "0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
- "0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
- "0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
- "0000" & "100011" & rmwZp & aluInT & aluDcp, -- C7 iDCP zp
- "0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
- "0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
- "0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
- "0100" & "100011" & immediate & aluInT & aluSbx, -- CB SBX imm
- "0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
- "0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
- "0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
- "0000" & "100011" & rmwAbs & aluInT & aluDcp, -- CF iDCP abs
- "0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
- "0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- D2 *** JAM ***
- "0000" & "100011" & rmwIndY & aluInT & aluDcp, -- D3 iDCP (zp),y
- "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- D4 iNOP zp,x
- "0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
- "0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
- "0000" & "100011" & rmwZpX & aluInT & aluDcp, -- D7 iDCP zp,x
- "0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
- "0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
- "0000" & "000000" & implied & aluInXXX & aluXXX, -- DA iNOP implied
- "0000" & "100011" & rmwAbsY & aluInT & aluDcp, -- DB iDCP abs,y
- "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- DC iNOP abs,x
- "0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
- "0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
- "0000" & "100011" & rmwAbsX & aluInT & aluDcp, -- DF iDCP abs,x
- -- AXYS NVDIZC addressing aluInput aluMode
- "0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
- "1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
- "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
- "1000" & "110011" & rmwIndX & aluInT & aluIsc, -- E3 iISC (zp,x)
- "0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
- "1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
- "0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
- "1000" & "110011" & rmwZp & aluInT & aluIsc, -- E7 iISC zp
- "0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
- "1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
- "0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
- "1000" & "110011" & immediate & aluInT & aluSbc, -- EB SBC imm (illegal opc)
- "0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
- "1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
- "0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
- "1000" & "110011" & rmwAbs & aluInT & aluIsc, -- EF iISC abs
- "0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
- "1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
- "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- F2 *** JAM ***
- "1000" & "110011" & rmwIndY & aluInT & aluIsc, -- F3 iISC (zp),y
- "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- F4 iNOP zp,x
- "1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
- "0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
- "1000" & "110011" & rmwZpX & aluInT & aluIsc, -- F7 iISC zp,x
- "0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
- "1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
- "0000" & "000000" & implied & aluInXXX & aluXXX, -- FA iNOP implied
- "1000" & "110011" & rmwAbsY & aluInT & aluIsc, -- FB iISC abs,y
- "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- FC iNOP abs,x
- "1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
- "0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
- "1000" & "110011" & rmwAbsX & aluInT & aluIsc -- FF iISC abs,x
- );
- signal opcInfo : decodedBitsDef;
- signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
- signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined
- signal theOpcode : unsigned(7 downto 0);
- signal nextOpcode : unsigned(7 downto 0);
-
--- Program counter
- signal PC : unsigned(15 downto 0); -- Program counter
-
--- Address generation
- type nextAddrDef is (
- nextAddrHold,
- nextAddrIncr,
- nextAddrIncrL, -- Increment low bits only (zeropage accesses)
- nextAddrIncrH, -- Increment high bits only (page-boundary)
- nextAddrDecrH, -- Decrement high bits (branch backwards)
- nextAddrPc,
- nextAddrIrq,
- nextAddrReset,
- nextAddrAbs,
- nextAddrAbsIndexed,
- nextAddrZeroPage,
- nextAddrZPIndexed,
- nextAddrStack,
- nextAddrRelative
- );
- signal nextAddr : nextAddrDef;
- signal myAddr : unsigned(15 downto 0);
- signal myAddrIncr : unsigned(15 downto 0);
- signal myAddrIncrH : unsigned(7 downto 0);
- signal myAddrDecrH : unsigned(7 downto 0);
- signal theWe : std_logic;
-
- signal irqActive : std_logic;
-
--- Output register
- signal doReg : unsigned(7 downto 0);
-
--- Buffer register
- signal T : unsigned(7 downto 0);
-
--- General registers
- signal A: unsigned(7 downto 0); -- Accumulator
- signal X: unsigned(7 downto 0); -- Index X
- signal Y: unsigned(7 downto 0); -- Index Y
- signal S: unsigned(7 downto 0); -- stack pointer
-
--- Status register
- signal C: std_logic; -- Carry
- signal Z: std_logic; -- Zero flag
- signal I: std_logic; -- Interrupt flag
- signal D: std_logic; -- Decimal mode
- signal V: std_logic; -- Overflow
- signal N: std_logic; -- Negative
-
--- ALU
- -- ALU input
- signal aluInput : unsigned(7 downto 0);
- signal aluCmpInput : unsigned(7 downto 0);
- -- ALU output
- signal aluRegisterOut : unsigned(7 downto 0);
- signal aluRmwOut : unsigned(7 downto 0);
- signal aluC : std_logic;
- signal aluZ : std_logic;
- signal aluV : std_logic;
- signal aluN : std_logic;
- -- Pipeline registers
- signal aluInputReg : unsigned(7 downto 0);
- signal aluCmpInputReg : unsigned(7 downto 0);
- signal aluRmwReg : unsigned(7 downto 0);
- signal aluNineReg : unsigned(7 downto 0);
- signal aluCReg : std_logic;
- signal aluZReg : std_logic;
- signal aluVReg : std_logic;
- signal aluNReg : std_logic;
-
--- Indexing
- signal indexOut : unsigned(8 downto 0);
-
-begin
-processAluInput: process(clk, opcInfo, A, X, Y, T, S)
- variable temp : unsigned(7 downto 0);
- begin
- temp := (others => '1');
- if opcInfo(opcInA) = '1' then
- temp := temp and A;
- end if;
- if opcInfo(opcInE) = '1' then
- temp := temp and (A or X"EE");
- end if;
- if opcInfo(opcInX) = '1' then
- temp := temp and X;
- end if;
- if opcInfo(opcInY) = '1' then
- temp := temp and Y;
- end if;
- if opcInfo(opcInS) = '1' then
- temp := temp and S;
- end if;
- if opcInfo(opcInT) = '1' then
- temp := temp and T;
- end if;
- if opcInfo(opcInClear) = '1' then
- temp := (others => '0');
- end if;
- if rising_edge(clk) then
- aluInputReg <= temp;
- end if;
-
- aluInput <= temp;
- if pipelineAluMux then
- aluInput <= aluInputReg;
- end if;
- end process;
-
-processCmpInput: process(clk, opcInfo, A, X, Y)
- variable temp : unsigned(7 downto 0);
- begin
- temp := (others => '1');
- if opcInfo(opcInCmp) = '1' then
- temp := temp and A;
- end if;
- if opcInfo(opcInCpx) = '1' then
- temp := temp and X;
- end if;
- if opcInfo(opcInCpy) = '1' then
- temp := temp and Y;
- end if;
- if rising_edge(clk) then
- aluCmpInputReg <= temp;
- end if;
-
- aluCmpInput <= temp;
- if pipelineAluMux then
- aluCmpInput <= aluCmpInputReg;
- end if;
- end process;
-
- -- ALU consists of two parts
- -- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
- -- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
- -- Some instructions are both RMW and accumulator so for most
- -- instructions the rmw results are routed through accu alu too.
-processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C)
- variable lowBits: unsigned(5 downto 0);
- variable nineBits: unsigned(8 downto 0);
- variable rmwBits: unsigned(8 downto 0);
-
- variable varC : std_logic;
- variable varZ : std_logic;
- variable varV : std_logic;
- variable varN : std_logic;
- begin
- lowBits := (others => '-');
- nineBits := (others => '-');
- rmwBits := (others => '-');
- varV := aluInput(6); -- Default for BIT / PLP / RTI
-
- -- Shift unit
- case opcInfo(aluMode1From to aluMode1To) is
- when aluModeInp =>
- rmwBits := C & aluInput;
- when aluModeP =>
- rmwBits := C & N & V & '1' & (not irqActive) & D & I & Z & C;
- when aluModeInc =>
- rmwBits := C & (aluInput + 1);
- when aluModeDec =>
- rmwBits := C & (aluInput - 1);
- when aluModeAsl =>
- rmwBits := aluInput & "0";
- when aluModeFlg =>
- rmwBits := aluInput(0) & aluInput;
- when aluModeLsr =>
- rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
- when aluModeRol =>
- rmwBits := aluInput & C;
- when aluModeRoR =>
- rmwBits := aluInput(0) & C & aluInput(7 downto 1);
- when aluModeAnc =>
- rmwBits := (aluInput(7) and A(7)) & aluInput;
- when others =>
- rmwBits := C & aluInput;
- end case;
-
- -- ALU
- case opcInfo(aluMode2From to aluMode2To) is
- when aluModeAdc =>
- lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
- ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
- when aluModeSbc =>
- lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
- ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
- when aluModeCmp =>
- ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
- when aluModeAnd =>
- ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
- when aluModeEor =>
- ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
- when aluModeOra =>
- ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
- when others =>
- ninebits := rmwBits;
- end case;
-
- if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
- varZ := rmwBits(1);
- elsif ninebits(7 downto 0) = X"00" then
- varZ := '1';
- else
- varZ := '0';
- end if;
-
- case opcInfo(aluMode2From to aluMode2To) is
- when aluModeAdc =>
- -- decimal mode low bits correction, is done after setting Z flag.
- if D = '1' then
- if lowBits(5 downto 1) > 9 then
- ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
- if lowBits(5) = '0' then
- ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
- end if;
- end if;
- end if;
- when others =>
- null;
- end case;
-
- if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
- or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
- varN := rmwBits(7);
- else
- varN := nineBits(7);
- end if;
- varC := ninebits(8);
- if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
- varC := aluInput(7);
- varV := aluInput(7) xor aluInput(6);
- end if;
-
- case opcInfo(aluMode2From to aluMode2To) is
- when aluModeAdc =>
- -- decimal mode high bits correction, is done after setting Z and N flags
- varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
- if D = '1' then
- if ninebits(8 downto 4) > 9 then
- ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
- varC := '1';
- end if;
- end if;
- when aluModeSbc =>
- varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
- if D = '1' then
- -- Check for borrow (lower 4 bits)
- if lowBits(5) = '0' then
- ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
- end if;
- -- Check for borrow (upper 4 bits)
- if ninebits(8) = '0' then
- ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
- end if;
- end if;
- when aluModeArr =>
- if D = '1' then
- if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
- ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
- end if;
- if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
- ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
- varC := '1';
- else
- varC := '0';
- end if;
- end if;
- when others =>
- null;
- end case;
-
- if rising_edge(clk) then
- aluRmwReg <= rmwBits(7 downto 0);
- aluNineReg <= ninebits(7 downto 0);
- aluCReg <= varC;
- aluZReg <= varZ;
- aluVReg <= varV;
- aluNReg <= varN;
- end if;
-
- aluRmwOut <= rmwBits(7 downto 0);
- aluRegisterOut <= ninebits(7 downto 0);
- aluC <= varC;
- aluZ <= varZ;
- aluV <= varV;
- aluN <= varN;
- if pipelineAluOut then
- aluRmwOut <= aluRmwReg;
- aluRegisterOut <= aluNineReg;
- aluC <= aluCReg;
- aluZ <= aluZReg;
- aluV <= aluVReg;
- aluN <= aluNReg;
- end if;
- end process;
-
-calcInterrupt: process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- if theCpuCycle = cycleStack4
- or reset = '1' then
- nmiReg <= '1';
- end if;
-
- if nextCpuCycle /= cycleBranchTaken
- and nextCpuCycle /= opcodeFetch then
- irqReg <= irq_n;
- nmiEdge <= nmi_n;
- if (nmiEdge = '1') and (nmi_n = '0') then
- nmiReg <= '0';
- end if;
- end if;
- -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
- -- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
- processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
- end if;
- end if;
- end process;
-
-calcNextOpcode: process(clk, di, reset, processIrq)
- variable myNextOpcode : unsigned(7 downto 0);
- begin
- -- Next opcode is read from input unless a reset or IRQ is pending.
- myNextOpcode := di;
- if reset = '1' then
- myNextOpcode := X"4C";
- elsif processIrq = '1' then
- myNextOpcode := X"00";
- end if;
-
- nextOpcode <= myNextOpcode;
- end process;
-
- nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
- process(clk)
- begin
- if rising_edge(clk) then
- nextOpcInfoReg <= nextOpcInfo;
- end if;
- end process;
-
- -- Read bits and flags from opcodeInfoTable and store in opcInfo.
- -- This info is used to control the execution of the opcode.
-calcOpcInfo: process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- if (reset = '1') or (theCpuCycle = opcodeFetch) then
- opcInfo <= nextOpcInfo;
- if pipelineOpcode then
- opcInfo <= nextOpcInfoReg;
- end if;
- end if;
- end if;
- end if;
- end process;
-
-calcTheOpcode: process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- if theCpuCycle = opcodeFetch then
- irqActive <= '0';
- if processIrq = '1' then
- irqActive <= '1';
- end if;
- -- Fetch opcode
- theOpcode <= nextOpcode;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- State machine
--- -----------------------------------------------------------------------
- process(enable, theCpuCycle, opcInfo)
- begin
- updateRegisters <= false;
- if enable = '1' then
- if opcInfo(opcRti) = '1' then
- if theCpuCycle = cycleRead then
- updateRegisters <= true;
- end if;
- elsif theCpuCycle = opcodeFetch then
- updateRegisters <= true;
- end if;
- end if;
- end process;
-
- debugOpcode <= theOpcode;
- process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- theCpuCycle <= nextCpuCycle;
- end if;
- if reset = '1' then
- theCpuCycle <= cycle2;
- end if;
- end if;
- end process;
-
- -- Determine the next cpu cycle. After the last cycle we always
- -- go to opcodeFetch to get the next opcode.
-calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z)
- begin
- nextCpuCycle <= opcodeFetch;
-
- case theCpuCycle is
- when opcodeFetch =>
- nextCpuCycle <= cycle2;
- when cycle2 =>
- if opcInfo(opcBranch) = '1' then
- if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
- or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
- or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
- or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11") then
- -- Branch condition is true
- nextCpuCycle <= cycleBranchTaken;
- end if;
- elsif (opcInfo(opcStackUp) = '1') then
- nextCpuCycle <= cycleStack1;
- elsif opcInfo(opcStackAddr) = '1'
- and opcInfo(opcStackData) = '1' then
- nextCpuCycle <= cycleStack2;
- elsif opcInfo(opcStackAddr) = '1' then
- nextCpuCycle <= cycleStack1;
- elsif opcInfo(opcStackData) = '1' then
- nextCpuCycle <= cycleWrite;
- elsif opcInfo(opcAbsolute) = '1' then
- nextCpuCycle <= cycle3;
- elsif opcInfo(opcIndirect) = '1' then
- if opcInfo(indexX) = '1' then
- nextCpuCycle <= cyclePreIndirect;
- else
- nextCpuCycle <= cycleIndirect;
- end if;
- elsif opcInfo(opcZeroPage) = '1' then
- if opcInfo(opcWrite) = '1' then
- if (opcInfo(indexX) = '1')
- or (opcInfo(indexY) = '1') then
- nextCpuCycle <= cyclePreWrite;
- else
- nextCpuCycle <= cycleWrite;
- end if;
- else
- if (opcInfo(indexX) = '1')
- or (opcInfo(indexY) = '1') then
- nextCpuCycle <= cyclePreRead;
- else
- nextCpuCycle <= cycleRead2;
- end if;
- end if;
- elsif opcInfo(opcJump) = '1' then
- nextCpuCycle <= cycleJump;
- end if;
- when cycle3 =>
- nextCpuCycle <= cycleRead;
- if opcInfo(opcWrite) = '1' then
- if (opcInfo(indexX) = '1')
- or (opcInfo(indexY) = '1') then
- nextCpuCycle <= cyclePreWrite;
- else
- nextCpuCycle <= cycleWrite;
- end if;
- end if;
- if (opcInfo(opcIndirect) = '1')
- and (opcInfo(indexX) = '1') then
- if opcInfo(opcWrite) = '1' then
- nextCpuCycle <= cycleWrite;
- else
- nextCpuCycle <= cycleRead2;
- end if;
- end if;
- when cyclePreIndirect =>
- nextCpuCycle <= cycleIndirect;
- when cycleIndirect =>
- nextCpuCycle <= cycle3;
- when cycleBranchTaken =>
- if indexOut(8) /= T(7) then
- -- Page boundary crossing during branch.
- nextCpuCycle <= cycleBranchPage;
- end if;
- when cyclePreRead =>
- if opcInfo(opcZeroPage) = '1' then
- nextCpuCycle <= cycleRead2;
- end if;
- when cycleRead =>
- if opcInfo(opcJump) = '1' then
- nextCpuCycle <= cycleJump;
- elsif indexOut(8) = '1' then
- -- Page boundary crossing while indexed addressing.
- nextCpuCycle <= cycleRead2;
- elsif opcInfo(opcRmw) = '1' then
- nextCpuCycle <= cycleRmw;
- if opcInfo(indexX) = '1'
- or opcInfo(indexY) = '1' then
- -- 6510 needs extra cycle for indexed addressing
- -- combined with RMW indexing
- nextCpuCycle <= cycleRead2;
- end if;
- end if;
- when cycleRead2 =>
- if opcInfo(opcRmw) = '1' then
- nextCpuCycle <= cycleRmw;
- end if;
- when cycleRmw =>
- nextCpuCycle <= cycleWrite;
- when cyclePreWrite =>
- nextCpuCycle <= cycleWrite;
- when cycleStack1 =>
- nextCpuCycle <= cycleRead;
- if opcInfo(opcStackAddr) = '1' then
- nextCpuCycle <= cycleStack2;
- end if;
- when cycleStack2 =>
- nextCpuCycle <= cycleStack3;
- if opcInfo(opcRti) = '1' then
- nextCpuCycle <= cycleRead;
- end if;
- if opcInfo(opcStackData) = '0'
- and opcInfo(opcStackUp) = '1' then
- nextCpuCycle <= cycleJump;
- end if;
- when cycleStack3 =>
- nextCpuCycle <= cycleRead;
- if opcInfo(opcStackData) = '0'
- or opcInfo(opcStackUp) = '1' then
- nextCpuCycle <= cycleJump;
- elsif opcInfo(opcStackAddr) = '1' then
- nextCpuCycle <= cycleStack4;
- end if;
- when cycleStack4 =>
- nextCpuCycle <= cycleRead;
- when cycleJump =>
- if opcInfo(opcIncrAfter) = '1' then
- -- Insert extra cycle
- nextCpuCycle <= cycleEnd;
- end if;
- when others =>
- null;
- end case;
- end process;
-
--- -----------------------------------------------------------------------
--- T register
--- -----------------------------------------------------------------------
-calcT: process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- case theCpuCycle is
- when cycle2 =>
- T <= di;
- when cycleStack1 | cycleStack2 =>
- if opcInfo(opcStackUp) = '1' then
- -- Read from stack
- T <= di;
- end if;
- when cycleIndirect | cycleRead | cycleRead2 =>
- T <= di;
- when others =>
- null;
- end case;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- A register
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if updateRegisters then
- if opcInfo(opcUpdateA) = '1' then
- A <= aluRegisterOut;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- X register
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if updateRegisters then
- if opcInfo(opcUpdateX) = '1' then
- X <= aluRegisterOut;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Y register
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if updateRegisters then
- if opcInfo(opcUpdateY) = '1' then
- Y <= aluRegisterOut;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- C flag
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if updateRegisters then
- if opcInfo(opcUpdateC) = '1' then
- C <= aluC;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Z flag
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if updateRegisters then
- if opcInfo(opcUpdateZ) = '1' then
- Z <= aluZ;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- I flag
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if updateRegisters then
- if opcInfo(opcUpdateI) = '1' then
- I <= aluInput(2);
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- D flag
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if updateRegisters then
- if opcInfo(opcUpdateD) = '1' then
- D <= aluInput(3);
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- V flag
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if updateRegisters then
- if opcInfo(opcUpdateV) = '1' then
- V <= aluV;
- end if;
- end if;
- if enable = '1' then
- if soReg = '1' and so_n = '0' then
- V <= '1';
- end if;
- soReg <= so_n;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- N flag
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if updateRegisters then
- if opcInfo(opcUpdateN) = '1' then
- N <= aluN;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Stack pointer
--- -----------------------------------------------------------------------
- process(clk)
- variable sIncDec : unsigned(7 downto 0);
- variable updateFlag : boolean;
- begin
- if rising_edge(clk) then
-
- if opcInfo(opcStackUp) = '1' then
- sIncDec := S + 1;
- else
- sIncDec := S - 1;
- end if;
-
- if enable = '1' then
- updateFlag := false;
- case nextCpuCycle is
- when cycleStack1 =>
- if (opcInfo(opcStackUp) = '1')
- or (opcInfo(opcStackData) = '1') then
- updateFlag := true;
- end if;
- when cycleStack2 =>
- updateFlag := true;
- when cycleStack3 =>
- updateFlag := true;
- when cycleStack4 =>
- updateFlag := true;
- when cycleRead =>
- if opcInfo(opcRti) = '1' then
- updateFlag := true;
- end if;
- when cycleWrite =>
- if opcInfo(opcStackData) = '1' then
- updateFlag := true;
- end if;
- when others =>
- null;
- end case;
- if updateFlag then
- S <= sIncDec;
- end if;
- end if;
- if updateRegisters then
- if opcInfo(opcUpdateS) = '1' then
- S <= aluRegisterOut;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Data out
--- -----------------------------------------------------------------------
---calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
-calcDo: process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- doReg <= aluRmwOut;
- if opcInfo(opcInH) = '1' then
- -- For illegal opcodes SHA, SHX, SHY, SHS
- doReg <= aluRmwOut and myAddrIncrH;
- end if;
-
- case nextCpuCycle is
- when cycleStack2 =>
- if opcInfo(opcIRQ) = '1'
- and irqActive = '0' then
- doReg <= myAddrIncr(15 downto 8);
- else
- doReg <= PC(15 downto 8);
- end if;
- when cycleStack3 =>
- doReg <= PC(7 downto 0);
- when cycleRmw =>
--- do <= T; -- Read-modify-write write old value first.
- doReg <= di; -- Read-modify-write write old value first.
- when others => null;
- end case;
- end if;
- end if;
- end process;
- do <= doReg;
-
-
-
--- -----------------------------------------------------------------------
--- Write enable
--- -----------------------------------------------------------------------
-calcWe: process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- theWe <= '0';
- case nextCpuCycle is
- when cycleStack1 =>
- if opcInfo(opcStackUp) = '0'
- and ((opcInfo(opcStackAddr) = '0')
- or (opcInfo(opcStackData) = '1')) then
- theWe <= '1';
- end if;
- when cycleStack2 | cycleStack3 | cycleStack4 =>
- if opcInfo(opcStackUp) = '0' then
- theWe <= '1';
- end if;
- when cycleRmw =>
- theWe <= '1';
- when cycleWrite =>
- theWe <= '1';
- when others =>
- null;
- end case;
- end if;
- end if;
- end process;
- we <= theWe;
-
--- -----------------------------------------------------------------------
--- Program counter
--- -----------------------------------------------------------------------
-calcPC: process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- case theCpuCycle is
- when opcodeFetch =>
- PC <= myAddr;
- when cycle2 =>
- if irqActive = '0' then
- if opcInfo(opcSecondByte) = '1' then
- PC <= myAddrIncr;
- else
- PC <= myAddr;
- end if;
- end if;
- when cycle3 =>
- if opcInfo(opcAbsolute) = '1' then
- PC <= myAddrIncr;
- end if;
- when others =>
- null;
- end case;
- end if;
- end if;
- end process;
- debugPc <= PC;
-
--- -----------------------------------------------------------------------
--- Address generation
--- -----------------------------------------------------------------------
-calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
- begin
- nextAddr <= nextAddrIncr;
- case theCpuCycle is
- when cycle2 =>
- if opcInfo(opcStackAddr) = '1'
- or opcInfo(opcStackData) = '1' then
- nextAddr <= nextAddrStack;
- elsif opcInfo(opcAbsolute) = '1' then
- nextAddr <= nextAddrIncr;
- elsif opcInfo(opcZeroPage) = '1' then
- nextAddr <= nextAddrZeroPage;
- elsif opcInfo(opcIndirect) = '1' then
- nextAddr <= nextAddrZeroPage;
- elsif opcInfo(opcSecondByte) = '1' then
- nextAddr <= nextAddrIncr;
- else
- nextAddr <= nextAddrHold;
- end if;
- when cycle3 =>
- if (opcInfo(opcIndirect) = '1')
- and (opcInfo(indexX) = '1') then
- nextAddr <= nextAddrAbs;
- else
- nextAddr <= nextAddrAbsIndexed;
- end if;
- when cyclePreIndirect =>
- nextAddr <= nextAddrZPIndexed;
- when cycleIndirect =>
- nextAddr <= nextAddrIncrL;
- when cycleBranchTaken =>
- nextAddr <= nextAddrRelative;
- when cycleBranchPage =>
- if T(7) = '0' then
- nextAddr <= nextAddrIncrH;
- else
- nextAddr <= nextAddrDecrH;
- end if;
- when cyclePreRead =>
- nextAddr <= nextAddrZPIndexed;
- when cycleRead =>
- nextAddr <= nextAddrPc;
- if opcInfo(opcJump) = '1' then
- -- Emulate 6510 bug, jmp(xxFF) fetches from same page.
- -- Replace with nextAddrIncr if emulating 65C02 or later cpu.
- nextAddr <= nextAddrIncrL;
- elsif indexOut(8) = '1' then
- nextAddr <= nextAddrIncrH;
- elsif opcInfo(opcRmw) = '1' then
- nextAddr <= nextAddrHold;
- end if;
- when cycleRead2 =>
- nextAddr <= nextAddrPc;
- if opcInfo(opcRmw) = '1' then
- nextAddr <= nextAddrHold;
- end if;
- when cycleRmw =>
- nextAddr <= nextAddrHold;
- when cyclePreWrite =>
- nextAddr <= nextAddrHold;
- if opcInfo(opcZeroPage) = '1' then
- nextAddr <= nextAddrZPIndexed;
- elsif indexOut(8) = '1' then
- nextAddr <= nextAddrIncrH;
- end if;
- when cycleWrite =>
- nextAddr <= nextAddrPc;
- when cycleStack1 =>
- nextAddr <= nextAddrStack;
- when cycleStack2 =>
- nextAddr <= nextAddrStack;
- when cycleStack3 =>
- nextAddr <= nextAddrStack;
- if opcInfo(opcStackData) = '0' then
- nextAddr <= nextAddrPc;
- end if;
- when cycleStack4 =>
- nextAddr <= nextAddrIrq;
- when cycleJump =>
- nextAddr <= nextAddrAbs;
- when others =>
- null;
- end case;
- if reset = '1' then
- nextAddr <= nextAddrReset;
- end if;
- end process;
-
-indexAlu: process(opcInfo, myAddr, T, X, Y)
- begin
- if opcInfo(indexX) = '1' then
- indexOut <= (B"0" & T) + (B"0" & X);
- elsif opcInfo(indexY) = '1' then
- indexOut <= (B"0" & T) + (B"0" & Y);
- elsif opcInfo(opcBranch) = '1' then
- indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
- else
- indexOut <= B"0" & T;
- end if;
- end process;
-
-calcAddr: process(clk)
- begin
- if rising_edge(clk) then
- if enable = '1' then
- case nextAddr is
- when nextAddrIncr => myAddr <= myAddrIncr;
- when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
- when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
- when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
- when nextAddrPc => myAddr <= PC;
- when nextAddrIrq =>
- myAddr <= X"FFFE";
- if nmiReg = '0' then
- myAddr <= X"FFFA";
- end if;
- when nextAddrReset => myAddr <= X"FFFC";
- when nextAddrAbs => myAddr <= di & T;
- when nextAddrAbsIndexed => myAddr <= di & indexOut(7 downto 0);
- when nextAddrZeroPage => myAddr <= "00000000" & di;
- when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
- when nextAddrStack => myAddr <= "00000001" & S;
- when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
- when others => null;
- end case;
- end if;
- end if;
- end process;
-
- myAddrIncr <= myAddr + 1;
- myAddrIncrH <= myAddr(15 downto 8) + 1;
- myAddrDecrH <= myAddr(15 downto 8) - 1;
-
- addr <= myAddr;
-
- debugA <= A;
- debugX <= X;
- debugY <= Y;
- debugS <= S;
-
-end architecture;
-
-
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/cpu_6510.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/cpu_6510.vhd
deleted file mode 100644
index 8ae35705..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/cpu_6510.vhd
+++ /dev/null
@@ -1,150 +0,0 @@
--- -----------------------------------------------------------------------
---
--- FPGA 64
---
--- A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- 6510 wrapper for 65xx core
--- Adds 8 bit I/O port mapped at addresses $0000 to $0001
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use ieee.std_logic_1164.ALL;
-use ieee.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity cpu_6510 is
- generic (
- pipelineOpcode : boolean:= false;
- pipelineAluMux : boolean:= false;
- pipelineAluOut : boolean:= false
- );
- port (
- clk : in std_logic;
- enable : in std_logic;
- reset : in std_logic;
- nmi_n : in std_logic;
- nmi_ack : out std_logic;
- irq_n : in std_logic;
-
- CPUdi : in unsigned(7 downto 0);
- CPUdo : out unsigned(7 downto 0);
- addr : out unsigned(15 downto 0);
- we : out std_logic;
-
- diIO : in unsigned(7 downto 0);
- doIO : out unsigned(7 downto 0);
-
- debugOpcode : out unsigned(7 downto 0);
- debugPc : out unsigned(15 downto 0);
- debugA : out unsigned(7 downto 0);
- debugX : out unsigned(7 downto 0);
- debugY : out unsigned(7 downto 0);
- debugS : out unsigned(7 downto 0)
- );
-end cpu_6510;
-
--- -----------------------------------------------------------------------
-
-architecture rtl of cpu_6510 is
- signal localA : unsigned(15 downto 0);
- signal localDi : unsigned(7 downto 0);
- signal localDo : unsigned(7 downto 0);
- signal localWe : std_logic;
-
- signal currentIO : unsigned(7 downto 0);
- signal ioDir : unsigned(7 downto 0);
- signal ioData : unsigned(7 downto 0);
-
- signal accessIO : std_logic;
-begin
- cpuInstance: entity work.cpu65xx(fast)
- generic map (
- pipelineOpcode => pipelineOpcode,
- pipelineAluMux => pipelineAluMux,
- pipelineAluOut => pipelineAluOut
- )
- port map (
- clk => clk,
- enable => enable,
- reset => reset,
- nmi_n => nmi_n,
- nmi_ack => nmi_ack,
- irq_n => irq_n,
-
- di => localDi,
- do => localDo,
- addr => localA,
- we => localWe,
-
- debugOpcode => debugOpcode,
- debugPc => debugPc,
- debugA => debugA,
- debugX => debugX,
- debugY => debugY,
- debugS => debugS
- );
-
- process(localA)
- begin
- accessIO <= '0';
- if localA(15 downto 1) = 0 then
- accessIO <= '1';
- end if;
- end process;
-
- process(CPUdi, localA, ioDir, currentIO, accessIO)
- begin
- localDi <= CPUdi;
- if accessIO = '1' then
- if localA(0) = '0' then
- localDi <= ioDir;
- else
- localDi <= currentIO;
- end if;
- end if;
- end process;
-
- process(clk)
- begin
- if rising_edge(clk) then
- if accessIO = '1' then
- if localWe = '1'
- and enable = '1' then
- if localA(0) = '0' then
- ioDir <= localDo;
- else
- ioData <= localDo;
- end if;
- end if;
- end if;
- if reset = '1' then
- ioDir <= (others => '0');
- end if;
- end if;
- end process;
-
- process(ioDir, ioData, diIO)
- begin
- for i in 0 to 7 loop
- if ioDir(i) = '0' then
- currentIO(i) <= diIO(i);
- else
- currentIO(i) <= ioData(i);
- end if;
- end loop;
- end process;
-
- -- Cunnect zee wires
- addr <= localA;
- CPUdo <= localDo;
- we <= localWe;
- doIO <= currentIO;
-end architecture;
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/data_io.v b/Computer_MiST/Commodore - MAX_MiST/rtl/data_io.v
deleted file mode 100644
index 4629033b..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/data_io.v
+++ /dev/null
@@ -1,126 +0,0 @@
-//
-// data_io.v
-//
-// io controller writable ram for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// ZX Spectrum adapted version
-//
-// Copyright (c) 2015 Till Harbaum
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see .
-//
-
-module data_io (
- // io controller spi interface
- input sck,
- input ss,
- input sdi,
-
- output downloading, // signal indicating an active download
- output reg [4:0] index, // menu index used to upload the file
-
- // external ram interface
- input clk,
- output reg wr,
- output reg [24:0] addr,
- output reg [7:0] data
-);
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// filter spi clock. the 8 bit gate delay is ~2.5ns in total
-wire [7:0] spi_sck_D = { spi_sck_D[6:0], sck } /* synthesis keep */;
-wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg [6:0] sbuf;
-reg [7:0] cmd;
-reg [4:0] cnt;
-reg rclk;
-
-reg [24:0] laddr;
-reg [7:0] ldata;
-
-localparam UIO_FILE_TX = 8'h53;
-localparam UIO_FILE_TX_DAT = 8'h54;
-localparam UIO_FILE_INDEX = 8'h55;
-
-assign downloading = downloading_reg;
-reg downloading_reg = 1'b0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge spi_sck, posedge ss) begin
- if(ss == 1'b1)
- cnt <= 5'd0;
- else begin
- rclk <= 1'b0;
-
- // don't shift in last bit. It is evaluated directly
- // when writing to ram
- if(cnt != 15)
- sbuf <= { sbuf[5:0], sdi};
-
- // increase target address after write
- if(rclk)
- laddr <= laddr + 1;
-
- // count 0-7 8-15 8-15 ...
- if(cnt < 15) cnt <= cnt + 4'd1;
- else cnt <= 4'd8;
-
- // finished command byte
- if(cnt == 7)
- cmd <= {sbuf, sdi};
-
- // prepare/end transmission
- if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
- // prepare
- if(sdi) begin
- laddr <= 25'd0;
- downloading_reg <= 1'b1;
- end else
- downloading_reg <= 1'b0;
- end
-
- // command 0x54: UIO_FILE_TX
- if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
- ldata <= {sbuf, sdi};
- rclk <= 1'b1;
- end
-
- // expose file (menu) index
- if((cmd == UIO_FILE_INDEX) && (cnt == 15))
- index <= {sbuf[3:0], sdi};
- end
-end
-
-reg rclkD, rclkD2;
-always@(posedge clk) begin
- // bring all signals from spi clock domain into local clock domain
- rclkD <= rclk;
- rclkD2 <= rclkD;
- wr <= 1'b0;
-
- if(rclkD && !rclkD2) begin
- addr <= laddr;
- data <= ldata;
- wr <= 1'b1;
- end
-end
-
-endmodule
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/fpga64_rgbcolor.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/fpga64_rgbcolor.vhd
deleted file mode 100644
index 1fc4eb9a..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/fpga64_rgbcolor.vhd
+++ /dev/null
@@ -1,56 +0,0 @@
--- -----------------------------------------------------------------------
---
--- FPGA 64
---
--- A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- C64 palette index to 24 bit RGB color
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.all;
-
--- -----------------------------------------------------------------------
-
-entity fpga64_rgbcolor is
- port (
- index: in unsigned(3 downto 0);
- r: out unsigned(7 downto 0);
- g: out unsigned(7 downto 0);
- b: out unsigned(7 downto 0)
- );
-end fpga64_rgbcolor;
-
--- -----------------------------------------------------------------------
-
-architecture Behavioral of fpga64_rgbcolor is
-begin
- process(index)
- begin
- case index is
- when X"0" => r <= X"00"; g <= X"00"; b <= X"00";
- when X"1" => r <= X"FF"; g <= X"FF"; b <= X"FF";
- when X"2" => r <= X"68"; g <= X"37"; b <= X"2B";
- when X"3" => r <= X"70"; g <= X"A4"; b <= X"B2";
- when X"4" => r <= X"6F"; g <= X"3D"; b <= X"86";
- when X"5" => r <= X"58"; g <= X"8D"; b <= X"43";
- when X"6" => r <= X"35"; g <= X"28"; b <= X"79";
- when X"7" => r <= X"B8"; g <= X"C7"; b <= X"6F";
- when X"8" => r <= X"6F"; g <= X"4F"; b <= X"25";
- when X"9" => r <= X"43"; g <= X"39"; b <= X"00";
- when X"A" => r <= X"9A"; g <= X"67"; b <= X"59";
- when X"B" => r <= X"44"; g <= X"44"; b <= X"44";
- when X"C" => r <= X"6C"; g <= X"6C"; b <= X"6C";
- when X"D" => r <= X"9A"; g <= X"D2"; b <= X"84";
- when X"E" => r <= X"6C"; g <= X"5E"; b <= X"B5";
- when X"F" => r <= X"95"; g <= X"95"; b <= X"95";
- end case;
- end process;
-end Behavioral;
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/hq2x.sv b/Computer_MiST/Commodore - MAX_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/hq2x.sv
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
- N <= 2 ? 0 : \
- N <= 4 ? 1 : \
- N <= 8 ? 2 : \
- N <= 16 ? 3 : \
- N <= 32 ? 4 : \
- N <= 64 ? 5 : \
- N <= 128 ? 6 : \
- N <= 256 ? 7 : \
- N <= 512 ? 8 : \
- N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
- input clk,
-
- input [AWIDTH:0] rdaddr,
- input rdbuf,
- output[DWIDTH:0] q,
-
- input [AWIDTH:0] wraddr,
- input wrbuf,
- input [DWIDTH:0] data,
- input wren
-);
-
- localparam AWIDTH = `BITS_TO_FIT(LENGTH);
- wire [DWIDTH:0] out[2];
- assign q = out[rdbuf];
-
- hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
- hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
- input clk,
-
- input [AWIDTH:0] rdaddr,
- input [1:0] rdbuf,
- output[DWIDTH:0] q,
-
- input [AWIDTH:0] wraddr,
- input [1:0] wrbuf,
- input [DWIDTH:0] data,
- input wren
-);
-
- localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
- wire [DWIDTH:0] out[4];
- assign q = out[rdbuf];
-
- hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
- hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
- hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
- hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
- input clock,
- input [DWIDTH:0] data,
- input [AWIDTH:0] rdaddress,
- input [AWIDTH:0] wraddress,
- input wren,
- output [DWIDTH:0] q
-);
-
- altsyncram altsyncram_component (
- .address_a (wraddress),
- .clock0 (clock),
- .data_a (data),
- .wren_a (wren),
- .address_b (rdaddress),
- .q_b(q),
- .aclr0 (1'b0),
- .aclr1 (1'b0),
- .addressstall_a (1'b0),
- .addressstall_b (1'b0),
- .byteena_a (1'b1),
- .byteena_b (1'b1),
- .clock1 (1'b1),
- .clocken0 (1'b1),
- .clocken1 (1'b1),
- .clocken2 (1'b1),
- .clocken3 (1'b1),
- .data_b ({(DWIDTH+1){1'b1}}),
- .eccstatus (),
- .q_a (),
- .rden_a (1'b1),
- .rden_b (1'b1),
- .wren_b (1'b0));
- defparam
- altsyncram_component.address_aclr_b = "NONE",
- altsyncram_component.address_reg_b = "CLOCK0",
- altsyncram_component.clock_enable_input_a = "BYPASS",
- altsyncram_component.clock_enable_input_b = "BYPASS",
- altsyncram_component.clock_enable_output_b = "BYPASS",
- altsyncram_component.intended_device_family = "Cyclone III",
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.numwords_a = NUMWORDS,
- altsyncram_component.numwords_b = NUMWORDS,
- altsyncram_component.operation_mode = "DUAL_PORT",
- altsyncram_component.outdata_aclr_b = "NONE",
- altsyncram_component.outdata_reg_b = "UNREGISTERED",
- altsyncram_component.power_up_uninitialized = "FALSE",
- altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
- altsyncram_component.widthad_a = AWIDTH+1,
- altsyncram_component.widthad_b = AWIDTH+1,
- altsyncram_component.width_a = DWIDTH+1,
- altsyncram_component.width_b = DWIDTH+1,
- altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
- input [17:0] rgb1,
- input [17:0] rgb2,
- output result
-);
-
- wire [5:0] r = rgb1[5:1] - rgb2[5:1];
- wire [5:0] g = rgb1[11:7] - rgb2[11:7];
- wire [5:0] b = rgb1[17:13] - rgb2[17:13];
- wire [6:0] t = $signed(r) + $signed(b);
- wire [6:0] gx = {g[5], g};
- wire [7:0] y = $signed(t) + $signed(gx);
- wire [6:0] u = $signed(r) - $signed(b);
- wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
- // if y is inside (-24..24)
- wire y_inside = (y < 8'h18 || y >= 8'he8);
-
- // if u is inside (-4, 4)
- wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
- // if v is inside (-6, 6)
- wire v_inside = (v < 8'h6 || v >= 8'hfA);
- assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
- input [8:0] Op,
- input [5:0] A,
- input [5:0] B,
- input [5:0] C,
- output [5:0] O
-);
-
- function [8:0] mul6x3;
- input [5:0] op1;
- input [2:0] op2;
- begin
- mul6x3 = 9'd0;
- if(op2[0]) mul6x3 = mul6x3 + op1;
- if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
- if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
- end
- endfunction
-
- wire OpOnes = Op[4];
- wire [8:0] Amul = mul6x3(A, Op[7:5]);
- wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
- wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
- wire [8:0] At = Amul;
- wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
- wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
- wire [9:0] Res = {At, 1'b0} + Bt + Ct;
- assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
- input [5:0] rule,
- input disable_hq2x,
- input [17:0] E,
- input [17:0] A,
- input [17:0] B,
- input [17:0] D,
- input [17:0] F,
- input [17:0] H,
- output [17:0] Result
-);
-
- reg [1:0] input_ctrl;
- reg [8:0] op;
- localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
- localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
- localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
- localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
- localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
- localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
- localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
- localparam AB = 2'b00;
- localparam AD = 2'b01;
- localparam DB = 2'b10;
- localparam BD = 2'b11;
- wire is_diff;
- DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
- always @* begin
- case({!is_diff, rule[5:2]})
- 1,17: {op, input_ctrl} = {BLEND1, AB};
- 2,18: {op, input_ctrl} = {BLEND1, DB};
- 3,19: {op, input_ctrl} = {BLEND1, BD};
- 4,20: {op, input_ctrl} = {BLEND2, DB};
- 5,21: {op, input_ctrl} = {BLEND2, AB};
- 6,22: {op, input_ctrl} = {BLEND2, AD};
-
- 8: {op, input_ctrl} = {BLEND0, 2'bxx};
- 9: {op, input_ctrl} = {BLEND0, 2'bxx};
- 10: {op, input_ctrl} = {BLEND0, 2'bxx};
- 11: {op, input_ctrl} = {BLEND1, AB};
- 12: {op, input_ctrl} = {BLEND1, AB};
- 13: {op, input_ctrl} = {BLEND1, AB};
- 14: {op, input_ctrl} = {BLEND1, DB};
- 15: {op, input_ctrl} = {BLEND1, BD};
-
- 24: {op, input_ctrl} = {BLEND2, DB};
- 25: {op, input_ctrl} = {BLEND5, DB};
- 26: {op, input_ctrl} = {BLEND6, DB};
- 27: {op, input_ctrl} = {BLEND2, DB};
- 28: {op, input_ctrl} = {BLEND4, DB};
- 29: {op, input_ctrl} = {BLEND5, DB};
- 30: {op, input_ctrl} = {BLEND3, BD};
- 31: {op, input_ctrl} = {BLEND3, DB};
- default: {op, input_ctrl} = 11'bx;
- endcase
-
- // Setting op[8] effectively disables HQ2X because blend will always return E.
- if (disable_hq2x) op[8] = 1;
- end
-
- // Generate inputs to the inner blender. Valid combinations.
- // 00: E A B
- // 01: E A D
- // 10: E D B
- // 11: E B D
- wire [17:0] Input1 = E;
- wire [17:0] Input2 = !input_ctrl[1] ? A :
- !input_ctrl[0] ? D : B;
-
- wire [17:0] Input3 = !input_ctrl[0] ? B : D;
- InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
- InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
- InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
- input clk,
- input ce_x4,
- input [DWIDTH:0] inputpixel,
- input mono,
- input disable_hq2x,
- input reset_frame,
- input reset_line,
- input [1:0] read_y,
- input [AWIDTH+1:0] read_x,
- output [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
- 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
- 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
- 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
- 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg [7:0] pattern, nextpatt;
-reg [1:0] i;
-reg [7:0] y;
-
-wire curbuf = y[0];
-reg prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg Curr2_addr1;
-reg [AWIDTH:0] Curr2_addr2;
-wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg [AWIDTH:0] wrin_addr2;
-reg [DWIDTH:0] wrpix;
-reg wrin_en;
-
-function [17:0] h2rgb;
- input [8:0] v;
-begin
- h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function [8:0] rgb2h;
- input [17:0] v;
-begin
- rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
- .clk(clk),
-
- .rdaddr(Curr2_addr2),
- .rdbuf(Curr2_addr1),
- .q(Curr2tmp),
-
- .wraddr(wrin_addr2),
- .wrbuf(iobuf),
- .data(wrpix),
- .wren(wrin_en)
-);
-
-reg [1:0] wrout_addr1;
-reg [AWIDTH+1:0] wrout_addr2;
-reg wrout_en;
-reg [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
- .clk(clk),
-
- .rdaddr(read_x),
- .rdbuf(read_y),
- .q(outpixel),
-
- .wraddr(wrout_addr2),
- .wrbuf(wrout_addr1),
- .data(wrdata),
- .wren(wrout_en)
-);
-
-always @(posedge clk) begin
- reg [AWIDTH:0] offs;
- reg old_reset_line;
- reg old_reset_frame;
-
- wrout_en <= 0;
- wrin_en <= 0;
-
- if(ce_x4) begin
-
- pattern <= new_pattern;
-
- if(~&offs) begin
- if (i == 0) begin
- Curr2_addr1 <= prevbuf;
- Curr2_addr2 <= offs;
- end
- if (i == 1) begin
- Prev2 <= Curr2;
- Curr2_addr1 <= curbuf;
- Curr2_addr2 <= offs;
- end
- if (i == 2) begin
- Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
- wrpix <= inputpixel;
- wrin_addr2 <= offs;
- wrin_en <= 1;
- end
- if (i == 3) begin
- offs <= offs + 1'd1;
- end
-
- if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
- else wrdata <= blend_result;
-
- wrout_addr1 <= {curbuf, i[1]};
- wrout_addr2 <= {offs, i[1]^i[0]};
- wrout_en <= 1;
- end
-
- if(i==3) begin
- nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
- {A, G} <= {Prev0, Next0};
- {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
- {Prev0, Prev1} <= {Prev1, Prev2};
- {Curr0, Curr1} <= {Curr1, Curr2};
- {Next0, Next1} <= {Next1, Next2};
- end else begin
- nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
- {B, F, H, D} <= {F, H, D, B};
- end
-
- i <= i + 1'b1;
- if(old_reset_line && ~reset_line) begin
- old_reset_frame <= reset_frame;
- offs <= 0;
- i <= 0;
- y <= y + 1'd1;
- prevbuf <= curbuf;
- if(old_reset_frame & ~reset_frame) begin
- y <= 0;
- prevbuf <= 0;
- end
- end
-
- old_reset_line <= reset_line;
- end
-end
-
-endmodule // Hq2x
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/mist_io.v b/Computer_MiST/Commodore - MAX_MiST/rtl/mist_io.v
deleted file mode 100644
index ab9ef8ad..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/mist_io.v
+++ /dev/null
@@ -1,532 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see .
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-// (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
- // parameter STRLEN and the actual length of conf_str have to match
- input [(8*STRLEN)-1:0] conf_str,
-
- // Global clock. It should be around 100MHz (higher is better).
- input clk_sys,
-
- // Global SPI clock from ARM. 24MHz
- input SPI_SCK,
-
- input CONF_DATA0,
- input SPI_SS2,
- output SPI_DO,
- input SPI_DI,
-
- output reg [7:0] joystick_0,
- output reg [7:0] joystick_1,
- output reg [15:0] joystick_analog_0,
- output reg [15:0] joystick_analog_1,
- output [1:0] buttons,
- output [1:0] switches,
- output scandoubler_disable,
- output ypbpr,
-
- output reg [31:0] status,
-
- // SD config
- input sd_conf,
- input sd_sdhc,
- output img_mounted, // signaling that new image has been mounted
- output reg [31:0] img_size, // size of image in bytes
-
- // SD block level access
- input [31:0] sd_lba,
- input sd_rd,
- input sd_wr,
- output reg sd_ack,
- output reg sd_ack_conf,
-
- // SD byte level access. Signals for 2-PORT altsyncram.
- output reg [8:0] sd_buff_addr,
- output reg [7:0] sd_buff_dout,
- input [7:0] sd_buff_din,
- output reg sd_buff_wr,
-
- // ps2 keyboard emulation
- output ps2_kbd_clk,
- output reg ps2_kbd_data,
- output ps2_mouse_clk,
- output reg ps2_mouse_data,
-
- // ARM -> FPGA download
- input ioctl_force_erase,
- output reg ioctl_download = 0, // signal indicating an active download
- output reg ioctl_erasing = 0, // signal indicating an active erase
- output reg [7:0] ioctl_index, // menu index used to upload the file
- output reg ioctl_wr = 0,
- output reg [24:0] ioctl_addr,
- output reg [7:0] ioctl_dout
-);
-
-reg [7:0] b_data;
-reg [6:0] sbuf;
-reg [7:0] cmd;
-reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
-reg [7:0] byte_cnt; // counts bytes
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg mount_strobe = 0;
-assign img_mounted = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoubler_disable = but_sw[4];
-assign ypbpr = but_sw[5];
-
-wire [7:0] spi_dout = { sbuf, SPI_DI};
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-// drive MISO only when transmitting core id
-always@(negedge SPI_SCK) begin
- if(!CONF_DATA0) begin
- // first byte returned is always core type, further bytes are
- // command dependent
- if(byte_cnt == 0) begin
- spi_do <= core_type[~bit_cnt];
-
- end else begin
- case(cmd)
- // reading config string
- 8'h14: begin
- // returning a byte from string
- if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
- else spi_do <= 0;
- end
-
- // reading sd card status
- 8'h16: begin
- if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
- else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
- else spi_do <= 0;
- end
-
- // reading sd card write data
- 8'h18:
- spi_do <= b_data[~bit_cnt];
-
- default:
- spi_do <= 0;
- endcase
- end
- end
-end
-
-reg b_wr2,b_wr3;
-always @(negedge clk_sys) begin
- b_wr3 <= b_wr2;
- sd_buff_wr <= b_wr3;
-end
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-
- if(CONF_DATA0) begin
- b_wr2 <= 0;
- bit_cnt <= 0;
- byte_cnt <= 0;
- sd_ack <= 0;
- sd_ack_conf <= 0;
- end else begin
- b_wr2 <= 0;
-
- sbuf <= spi_dout[6:0];
- bit_cnt <= bit_cnt + 1'd1;
- if(bit_cnt == 5) begin
- if (byte_cnt == 0) sd_buff_addr <= 0;
- if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
- if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
- end
-
- // finished reading command byte
- if(bit_cnt == 7) begin
- if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
- if(byte_cnt == 0) begin
- cmd <= spi_dout;
-
- if(spi_dout == 8'h19) begin
- sd_ack_conf <= 1;
- sd_buff_addr <= 0;
- end
- if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
- sd_ack <= 1;
- sd_buff_addr <= 0;
- end
- if(spi_dout == 8'h18) b_data <= sd_buff_din;
-
- mount_strobe <= 0;
-
- end else begin
-
- case(cmd)
- // buttons and switches
- 8'h01: but_sw <= spi_dout;
- 8'h02: joystick_0 <= spi_dout;
- 8'h03: joystick_1 <= spi_dout;
-
- // store incoming ps2 mouse bytes
- 8'h04: begin
- ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout;
- ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
- end
-
- // store incoming ps2 keyboard bytes
- 8'h05: begin
- ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout;
- ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
- end
-
- 8'h15: status[7:0] <= spi_dout;
-
- // send SD config IO -> FPGA
- // flag that download begins
- // sd card knows data is config if sd_dout_strobe is asserted
- // with sd_ack still being inactive (low)
- 8'h19,
- // send sector IO -> FPGA
- // flag that download begins
- 8'h17: begin
- sd_buff_dout <= spi_dout;
- b_wr2 <= 1;
- end
-
- 8'h18: b_data <= sd_buff_din;
-
- // joystick analog
- 8'h1a: begin
- // first byte is joystick index
- if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
- else if(byte_cnt == 2) begin
- // second byte is x axis
- if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
- else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
- end else if(byte_cnt == 3) begin
- // third byte is y axis
- if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
- else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
- end
- end
-
- // notify image selection
- 8'h1c: mount_strobe <= 1;
-
- // send image info
- 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
-
- // status, 32bit version
- 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
- default: ;
- endcase
- end
- end
- end
-end
-
-
-/////////////////////////////// PS2 ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
- integer cnt;
- cnt <= cnt + 1'd1;
- if(cnt == PS2DIV) begin
- clk_ps2 <= ~clk_ps2;
- cnt <= 0;
- end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin
- ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
- ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
- if(ps2_kbd_tx_byte[0])
- ps2_kbd_parity <= !ps2_kbd_parity;
- end
-
- // transmission of parity
- if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
- // transmission of stop bit
- if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
-
- // advance state machine
- if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
- else ps2_kbd_tx_state <= 0;
- end
- end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin
- ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
- ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
- if(ps2_mouse_tx_byte[0])
- ps2_mouse_parity <= !ps2_mouse_parity;
- end
-
- // transmission of parity
- if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
- // transmission of stop bit
- if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
-
- // advance state machine
- if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
- else ps2_mouse_tx_state <= 0;
- end
- end
-end
-
-
-/////////////////////////////// DOWNLOADING ///////////////////////////////
-
-reg [7:0] data_w;
-reg [24:0] addr_w;
-reg rclk = 0;
-
-localparam UIO_FILE_TX = 8'h53;
-localparam UIO_FILE_TX_DAT = 8'h54;
-localparam UIO_FILE_INDEX = 8'h55;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
- reg [6:0] sbuf;
- reg [7:0] cmd;
- reg [4:0] cnt;
- reg [24:0] addr;
-
- if(SPI_SS2) cnt <= 0;
- else begin
- rclk <= 0;
-
- // don't shift in last bit. It is evaluated directly
- // when writing to ram
- if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
- // increase target address after write
- if(rclk) addr <= addr + 1'd1;
-
- // count 0-7 8-15 8-15 ...
- if(cnt < 15) cnt <= cnt + 1'd1;
- else cnt <= 8;
-
- // finished command byte
- if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
- // prepare/end transmission
- if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
- // prepare
- if(SPI_DI) begin
- case(ioctl_index)
- 0: addr <= 'h080000; // BOOT ROM
- 'h01: addr <= 'h000100; // ROM file
- 'h41: addr <= 'h000100; // COM file
- 'h81: addr <= 'h000000; // C00 file
- 'hC1: addr <= 'h010000; // EDD file
- default: addr <= 'h100000; // FDD file
- endcase
- ioctl_download <= 1;
- end else begin
- addr_w <= addr;
- ioctl_download <= 0;
- end
- end
-
- // command 0x54: UIO_FILE_TX
- if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
- addr_w <= addr;
- data_w <= {sbuf, SPI_DI};
- rclk <= 1;
- end
-
- // expose file (menu) index
- if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
- end
-end
-
-reg [24:0] erase_mask;
-wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask;
-
-always@(posedge clk_sys) begin
- reg rclkD, rclkD2;
- reg old_force = 0;
- reg [5:0] erase_clk_div;
- reg [24:0] end_addr;
- reg erase_trigger = 0;
-
- rclkD <= rclk;
- rclkD2 <= rclkD;
- ioctl_wr <= 0;
-
- if(rclkD & ~rclkD2) begin
- ioctl_dout <= data_w;
- ioctl_addr <= addr_w;
- ioctl_wr <= 1;
- end
-
- if(ioctl_download) begin
- old_force <= 0;
- ioctl_erasing <= 0;
- erase_trigger <= (ioctl_index == 1);
- end else begin
-
- old_force <= ioctl_force_erase;
-
- // start erasing
- if(erase_trigger) begin
- erase_trigger <= 0;
- erase_mask <= 'hFFFF;
- end_addr <= 'h0100;
- erase_clk_div <= 1;
- ioctl_erasing <= 1;
- end else if((ioctl_force_erase & ~old_force)) begin
- erase_trigger <= 0;
- ioctl_addr <= 'h1FFFFFF;
- erase_mask <= 'h1FFFFFF;
- end_addr <= 'h0050000;
- erase_clk_div <= 1;
- ioctl_erasing <= 1;
- end else if(ioctl_erasing) begin
- erase_clk_div <= erase_clk_div + 1'd1;
- if(!erase_clk_div) begin
- if(next_erase == end_addr) ioctl_erasing <= 0;
- else begin
- ioctl_addr <= next_erase;
- ioctl_dout <= 0;
- ioctl_wr <= 1;
- end
- end
- end
- end
-end
-
-endmodule
\ No newline at end of file
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/osd.v b/Computer_MiST/Commodore - MAX_MiST/rtl/osd.v
deleted file mode 100644
index c62c10af..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/osd.v
+++ /dev/null
@@ -1,179 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
- // OSDs pixel clock, should be synchronous to cores pixel clock to
- // avoid jitter.
- input clk_sys,
-
- // SPI interface
- input SPI_SCK,
- input SPI_SS3,
- input SPI_DI,
-
- // VGA signals coming from core
- input [5:0] R_in,
- input [5:0] G_in,
- input [5:0] B_in,
- input HSync,
- input VSync,
-
- // VGA signals going to video connector
- output [5:0] R_out,
- output [5:0] G_out,
- output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR = 3'd0;
-
-localparam OSD_WIDTH = 10'd256;
-localparam OSD_HEIGHT = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg osd_enable;
-(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
- reg [4:0] cnt;
- reg [10:0] bcnt;
- reg [7:0] sbuf;
- reg [7:0] cmd;
-
- if(SPI_SS3) begin
- cnt <= 0;
- bcnt <= 0;
- end else begin
- sbuf <= {sbuf[6:0], SPI_DI};
-
- // 0:7 is command, rest payload
- if(cnt < 15) cnt <= cnt + 1'd1;
- else cnt <= 8;
-
- if(cnt == 7) begin
- cmd <= {sbuf[6:0], SPI_DI};
-
- // lower three command bits are line address
- bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
- // command 0x40: OSDCMDENABLE, OSDCMDDISABLE
- if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
- end
-
- // command 0x20: OSDCMDWRITE
- if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
- osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
- bcnt <= bcnt + 1'd1;
- end
- end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg [9:0] h_cnt;
-reg [9:0] hs_low, hs_high;
-wire hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg [9:0] v_cnt;
-reg [9:0] vs_low, vs_high;
-wire vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
- integer cnt = 0;
- integer pixsz, pixcnt;
- reg hs;
-
- cnt <= cnt + 1;
- hs <= HSync;
-
- pixcnt <= pixcnt + 1;
- if(pixcnt == pixsz) pixcnt <= 0;
- ce_pix <= !pixcnt;
-
- if(hs && ~HSync) begin
- cnt <= 0;
- pixsz <= (cnt >> 9) - 1;
- pixcnt <= 0;
- ce_pix <= 1;
- end
-end
-
-always @(posedge clk_sys) begin
- reg hsD, hsD2;
- reg vsD, vsD2;
-
- if(ce_pix) begin
- // bring hsync into local clock domain
- hsD <= HSync;
- hsD2 <= hsD;
-
- // falling edge of HSync
- if(!hsD && hsD2) begin
- h_cnt <= 0;
- hs_high <= h_cnt;
- end
-
- // rising edge of HSync
- else if(hsD && !hsD2) begin
- h_cnt <= 0;
- hs_low <= h_cnt;
- v_cnt <= v_cnt + 1'd1;
- end else begin
- h_cnt <= h_cnt + 1'd1;
- end
-
- vsD <= VSync;
- vsD2 <= vsD;
-
- // falling edge of VSync
- if(!vsD && vsD2) begin
- v_cnt <= 0;
- vs_high <= v_cnt;
- end
-
- // rising edge of VSync
- else if(vsD && !vsD2) begin
- v_cnt <= 0;
- vs_low <= v_cnt;
- end
- end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) &&
- (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [7:0] osd_byte;
-always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
-
-wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/pla_6703.v b/Computer_MiST/Commodore - MAX_MiST/rtl/pla_6703.v
deleted file mode 100644
index f31bd0f4..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/pla_6703.v
+++ /dev/null
@@ -1,59 +0,0 @@
-module pla_6703(
-
-input [15:10]A,
-input [3:0]DI,
-output [11:8]DO,
-input CLK,//CLK
-input BA,//BA
-input RW_IN,// RW
-
-output reg RAM,//RAM invert
-output reg EXRAM,//EXRAM invert
-output reg VIC,//VIC invert
-output reg SID,//SID invert
-output reg CIA,//CIA_PLA invert
-output reg COLRAM,//COLRAM invert
-output reg ROML,//ROML invert
-output reg ROMH,//ROMH invert
-output reg BUF,//to the 4066 COLOR Ram DATA
-output reg RW_OUT//RW_PLA invert
-
-);
-
-
-always @ (posedge CLK)
-begin
- RAM = ~(~A[11] & ~A[12] & ~A[13] & ~A[14] & ~A[15] & CLK & BA);
- EXRAM = ~(A[11] & ~A[12] & ~A[13] & ~A[14] & ~A[15] & CLK & BA);
- ROML = ~(~A[13] & ~A[14] & A[15] & CLK & BA);
- ROMH = ~(A[13] & A[14] & A[15] & CLK & BA);
- SID = ~(A[10] & ~A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
- VIC = ~(~A[10] & ~A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
- COLRAM = ~(~A[10] & A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
- BUF = (~A[10] & A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
- CIA = ~(A[10] & A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
- RW_OUT = ~(CLK & ~RW_IN);
-end
-
-
-
-//GAL Code
-/*!
-RAM = !A11 & !A12 & !A13 & !A14 & !A15 & CLK & BA
-!EXRAM = A11 & !A12 & !A13 & !A14 & !A15 & CLK & BA
-# A11 & !A12 & !A13 & !CLK
-# A11 & !A12 & !A13 & !BA;
-!ROML = !A13 & !A14 & A15 & CLK & BA;
-!ROMH = A13 & A14 & A15 & CLK & BA
-# A12 & A13 & !CLK
-# A12 & A13 & !BA;
-!SID = A10 & !A11 & A12 & !A13 & A14 & A15 & CLK & BA;
-!VIC = !A10 & !A11 & A12 & !A13 & A14 & A15 & CLK & BA;
-!COLRAM = !A10 & A11 & A12 & !A13 & A14 & A15 & CLK & BA
-# !CLK
-# !BA;
-BUF = !A10 & A11 & A12 & !A13 & A14 & A15 & CLK & BA;
-!CIA = A10 & A11 & A12 & !A13 & A14 & A15 & CLK & BA;
-!RW_OUT = CLK & !RW_IN;*/
-
-endmodule
\ No newline at end of file
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/pll.qip b/Computer_MiST/Commodore - MAX_MiST/rtl/pll.qip
deleted file mode 100644
index afd958be..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/pll.qip
+++ /dev/null
@@ -1,4 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/pll.v b/Computer_MiST/Commodore - MAX_MiST/rtl/pll.v
deleted file mode 100644
index 0adb538f..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/pll.v
+++ /dev/null
@@ -1,404 +0,0 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: pll.v
-// Megafunction Name(s):
-// altpll
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 13.1.0 Build 162 10/23/2013 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2013 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll (
- areset,
- inclk0,
- c0,
- c1,
- c2,
- c3,
- locked);
-
- input areset;
- input inclk0;
- output c0;
- output c1;
- output c2;
- output c3;
- output locked;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
- tri0 areset;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
- wire [4:0] sub_wire0;
- wire sub_wire3;
- wire [0:0] sub_wire8 = 1'h0;
- wire [2:2] sub_wire5 = sub_wire0[2:2];
- wire [0:0] sub_wire4 = sub_wire0[0:0];
- wire [3:3] sub_wire2 = sub_wire0[3:3];
- wire [1:1] sub_wire1 = sub_wire0[1:1];
- wire c1 = sub_wire1;
- wire c3 = sub_wire2;
- wire locked = sub_wire3;
- wire c0 = sub_wire4;
- wire c2 = sub_wire5;
- wire sub_wire6 = inclk0;
- wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
-
- altpll altpll_component (
- .areset (areset),
- .inclk (sub_wire7),
- .clk (sub_wire0),
- .locked (sub_wire3),
- .activeclock (),
- .clkbad (),
- .clkena ({6{1'b1}}),
- .clkloss (),
- .clkswitch (1'b0),
- .configupdate (1'b0),
- .enable0 (),
- .enable1 (),
- .extclk (),
- .extclkena ({4{1'b1}}),
- .fbin (1'b1),
- .fbmimicbidir (),
- .fbout (),
- .fref (),
- .icdrclk (),
- .pfdena (1'b1),
- .phasecounterselect ({4{1'b1}}),
- .phasedone (),
- .phasestep (1'b1),
- .phaseupdown (1'b1),
- .pllena (1'b1),
- .scanaclr (1'b0),
- .scanclk (1'b0),
- .scanclkena (1'b1),
- .scandata (1'b0),
- .scandataout (),
- .scandone (),
- .scanread (1'b0),
- .scanwrite (1'b0),
- .sclkout0 (),
- .sclkout1 (),
- .vcooverrange (),
- .vcounderrange ());
- defparam
- altpll_component.bandwidth_type = "AUTO",
- altpll_component.clk0_divide_by = 27,
- altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 32,
- altpll_component.clk0_phase_shift = "0",
- altpll_component.clk1_divide_by = 27,
- altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 1,
- altpll_component.clk1_phase_shift = "0",
- altpll_component.clk2_divide_by = 27,
- altpll_component.clk2_duty_cycle = 50,
- altpll_component.clk2_multiply_by = 8,
- altpll_component.clk2_phase_shift = "0",
- altpll_component.clk3_divide_by = 2240,
- altpll_component.clk3_duty_cycle = 50,
- altpll_component.clk3_multiply_by = 83,
- altpll_component.clk3_phase_shift = "0",
- altpll_component.compensate_clock = "CLK0",
- altpll_component.inclk0_input_frequency = 37037,
- altpll_component.intended_device_family = "Cyclone III",
- altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
- altpll_component.lpm_type = "altpll",
- altpll_component.operation_mode = "NORMAL",
- altpll_component.pll_type = "AUTO",
- altpll_component.port_activeclock = "PORT_UNUSED",
- altpll_component.port_areset = "PORT_USED",
- altpll_component.port_clkbad0 = "PORT_UNUSED",
- altpll_component.port_clkbad1 = "PORT_UNUSED",
- altpll_component.port_clkloss = "PORT_UNUSED",
- altpll_component.port_clkswitch = "PORT_UNUSED",
- altpll_component.port_configupdate = "PORT_UNUSED",
- altpll_component.port_fbin = "PORT_UNUSED",
- altpll_component.port_inclk0 = "PORT_USED",
- altpll_component.port_inclk1 = "PORT_UNUSED",
- altpll_component.port_locked = "PORT_USED",
- altpll_component.port_pfdena = "PORT_UNUSED",
- altpll_component.port_phasecounterselect = "PORT_UNUSED",
- altpll_component.port_phasedone = "PORT_UNUSED",
- altpll_component.port_phasestep = "PORT_UNUSED",
- altpll_component.port_phaseupdown = "PORT_UNUSED",
- altpll_component.port_pllena = "PORT_UNUSED",
- altpll_component.port_scanaclr = "PORT_UNUSED",
- altpll_component.port_scanclk = "PORT_UNUSED",
- altpll_component.port_scanclkena = "PORT_UNUSED",
- altpll_component.port_scandata = "PORT_UNUSED",
- altpll_component.port_scandataout = "PORT_UNUSED",
- altpll_component.port_scandone = "PORT_UNUSED",
- altpll_component.port_scanread = "PORT_UNUSED",
- altpll_component.port_scanwrite = "PORT_UNUSED",
- altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_USED",
- altpll_component.port_clk2 = "PORT_USED",
- altpll_component.port_clk3 = "PORT_USED",
- altpll_component.port_clk4 = "PORT_UNUSED",
- altpll_component.port_clk5 = "PORT_UNUSED",
- altpll_component.port_clkena0 = "PORT_UNUSED",
- altpll_component.port_clkena1 = "PORT_UNUSED",
- altpll_component.port_clkena2 = "PORT_UNUSED",
- altpll_component.port_clkena3 = "PORT_UNUSED",
- altpll_component.port_clkena4 = "PORT_UNUSED",
- altpll_component.port_clkena5 = "PORT_UNUSED",
- altpll_component.port_extclk0 = "PORT_UNUSED",
- altpll_component.port_extclk1 = "PORT_UNUSED",
- altpll_component.port_extclk2 = "PORT_UNUSED",
- altpll_component.port_extclk3 = "PORT_UNUSED",
- altpll_component.self_reset_on_loss_lock = "OFF",
- altpll_component.width_clock = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
-// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "2240"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "1.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "8.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "1.000446"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "32"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "8"
-// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "83"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "1.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "8.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "1.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2240"
-// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "83"
-// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
-// Retrieval info: LIB_FILE: altera_mf
-// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/scandoubler.v b/Computer_MiST/Commodore - MAX_MiST/rtl/scandoubler.v
deleted file mode 100644
index 5a3ccd17..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/scandoubler.v
+++ /dev/null
@@ -1,195 +0,0 @@
-//
-// scandoubler.v
-//
-// Copyright (c) 2015 Till Harbaum
-// Copyright (c) 2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see .
-
-// TODO: Delay vsync one line
-
-`define BITS_TO_FIT(N) ( \
- N <= 2 ? 0 : \
- N <= 4 ? 1 : \
- N <= 8 ? 2 : \
- N <= 16 ? 3 : \
- N <= 32 ? 4 : \
- N <= 64 ? 5 : \
- N <= 128 ? 6 : \
- N <= 256 ? 7 : \
- N <= 512 ? 8 : \
- N <=1024 ? 9 : 10 )
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
- // system interface
- input clk_sys,
- input ce_pix,
- input ce_pix_actual,
-
- input hq2x,
-
- // shifter video interface
- input hs_in,
- input vs_in,
- input line_start,
-
- input [DWIDTH:0] r_in,
- input [DWIDTH:0] g_in,
- input [DWIDTH:0] b_in,
- input mono,
-
- // output interface
- output reg hs_out,
- output vs_out,
- output [DWIDTH:0] r_out,
- output [DWIDTH:0] g_out,
- output [DWIDTH:0] b_out
-);
-
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg [2:0] phase;
-reg [2:0] ce_div;
-reg [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
- reg old_ce;
- reg [2:0] ce_cnt;
-
- reg [7:0] pixsz2, pixsz4 = 0;
-
- old_ce <= ce_pix;
- if(~&pix_len) pix_len <= pix_len + 1'd1;
-
- ce_x4 <= 0;
- ce_x1 <= 0;
-
- // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
- if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
- phase <= phase + 1'd1;
- ce_x4 <= 1;
- end
-
- if(~old_ce & ce_pix) begin
- pixsz2 <= {1'b0, pl[7:1]};
- pixsz4 <= {2'b00, pl[7:2]};
- ce_x1 <= 1;
- ce_x4 <= 1;
- pix_len <= 0;
- phase <= phase + 1'd1;
-
- ce_cnt <= ce_cnt + 1'd1;
- if(ce_pix_actual) begin
- phase <= 0;
- ce_div <= ce_cnt + 1'd1;
- ce_cnt <= 0;
- req_line_reset <= 0;
- end
-
- if(ls_in) req_line_reset <= 1;
- end
-end
-
-reg ce_sd;
-always @(*) begin
- case(ce_div)
- 2: ce_sd = !phase[0];
- 4: ce_sd = !phase[1:0];
- default: ce_sd <= 1;
- endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
- .clk(clk_sys),
- .ce_x4(ce_x4 & ce_sd),
- .inputpixel({b_in,g_in,r_in}),
- .mono(mono),
- .disable_hq2x(~hq2x),
- .reset_frame(vs_in),
- .reset_line(req_line_reset),
- .read_y(sd_line),
- .read_x(sd_h_actual),
- .outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
- case(ce_div)
- 2: sd_h_actual = sd_h[10:1];
- 4: sd_h_actual = sd_h[10:2];
- default: sd_h_actual = sd_h;
- endcase
-end
-
-reg [10:0] sd_h;
-reg [1:0] sd_line;
-always @(posedge clk_sys) begin
-
- reg [11:0] hs_max,hs_rise,hs_ls;
- reg [10:0] hcnt;
- reg [11:0] sd_hcnt;
-
- reg hs, hs2, vs, ls;
-
- if(ce_x1) begin
- hs <= hs_in;
- ls <= ls_in;
-
- if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
- // falling edge of hsync indicates start of line
- if(hs && !hs_in) begin
- hs_max <= {hcnt,1'b1};
- hcnt <= 0;
- if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
- end else begin
- hcnt <= hcnt + 1'd1;
- end
-
- // save position of rising edge
- if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
- vs <= vs_in;
- if(vs && ~vs_in) sd_line <= 0;
- end
-
- if(ce_x4) begin
- hs2 <= hs_in;
-
- // output counter synchronous to input and at twice the rate
- sd_hcnt <= sd_hcnt + 1'd1;
- sd_h <= sd_h + 1'd1;
- if(hs2 && !hs_in) sd_hcnt <= hs_max;
- if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
- // replicate horizontal sync at twice the speed
- if(sd_hcnt == hs_max) hs_out <= 0;
- if(sd_hcnt == hs_rise) hs_out <= 1;
-
- if(sd_hcnt == hs_ls) sd_h <= 0;
- if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
- end
-end
-
-endmodule
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/sid_6581.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/sid_6581.vhd
deleted file mode 100644
index 920c6f1b..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/sid_6581.vhd
+++ /dev/null
@@ -1,348 +0,0 @@
--------------------------------------------------------------------------------
---
--- SID 6581
---
--- A fully functional SID chip implementation in VHDL
---
--------------------------------------------------------------------------------
--- to do: - filter
--- - smaller implementation, use multiplexed channels
---
---
--- "The Filter was a classic multi-mode (state variable) VCF design. There was
--- no way to create a variable transconductance amplifier in our NMOS process,
--- so I simply used FETs as voltage-controlled resistors to control the cutoff
--- frequency. An 11-bit D/A converter generates the control voltage for the
--- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
--- disconnected it!)."
--- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
--- bit would turn on one of the weighted resistors and allow a portion of the
--- output to feed back to the input. The state-variable design provided
--- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
--- selected which combination of outputs were sent to the final amplifier (a
--- notch filter was created by enabling both the high and low-pass outputs
--- simultaneously)."
--- "The filter is the worst part of SID because I could not create high-gain
--- op-amps in NMOS, which were essential to a resonant filter. In addition,
--- the resistance of the FETs varied considerably with processing, so different
--- lots of SID chips had different cutoff frequency characteristics. I knew it
--- wouldn't work very well, but it was better than nothing and I didn't have
--- time to make it better."
---
--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.numeric_std.all;
-
--------------------------------------------------------------------------------
-
-entity sid_6581 is
- port (
- clk_1MHz : in std_logic; -- main SID clock signal
- clk32 : in std_logic; -- main clock signal
- reset : in std_logic; -- high active signal (reset when reset = '1')
- cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
- we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
-
- addr : in std_logic_vector(4 downto 0); -- address lines
- data_i : in std_logic_vector(7 downto 0); -- data in (to chip)
- data_o : out std_logic_vector(7 downto 0); -- data out (from chip)
-
- poti_x : in std_logic; -- paddle input-X
- poti_y : in std_logic; -- paddle input-Y
- audio_data : out std_logic_vector(17 downto 0)
- );
-end sid_6581;
-
-architecture Behavioral of sid_6581 is
-
- component pwm_sdadc is
- port (
- clk : in std_logic; -- main clock signal (actually the higher the better)
- reset : in std_logic; --
- ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
- ADC_in : in std_logic -- "analog" paddle input pin
- );
- end component;
-
- -- Implementation of the SID voices (sound channels)
- component sid_voice is
- port (
- clk_1MHz : in std_logic; -- this line drives the oscilator
- reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
- Freq_lo : in std_logic_vector(7 downto 0); --
- Freq_hi : in std_logic_vector(7 downto 0); --
- Pw_lo : in std_logic_vector(7 downto 0); --
- Pw_hi : in std_logic_vector(3 downto 0); --
- Control : in std_logic_vector(7 downto 0); --
- Att_dec : in std_logic_vector(7 downto 0); --
- Sus_Rel : in std_logic_vector(7 downto 0); --
- PA_MSB_in : in std_logic; --
- PA_MSB_out : out std_logic; --
- Osc : out std_logic_vector(7 downto 0); --
- Env : out std_logic_vector(7 downto 0); --
- voice : out std_logic_vector(11 downto 0) --
- );
- end component;
-
--------------------------------------------------------------------------------
---constant : := ;
--- DC offset required to play samples, this is actually a bug of the real 6581,
--- that was converted into an advantage to play samples
-constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
--------------------------------------------------------------------------------
-
-signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
-signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
-
-signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
-signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
-
-signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
-signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
-signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
-
-signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
-signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
-signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
-signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
-
-signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
-signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
-signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
-signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
-
-signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
-
-signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
-signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
-signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
-signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
-
-signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
-signal voice_1_PA_MSB : std_logic := '0';
-signal voice_2_PA_MSB : std_logic := '0';
-signal voice_3_PA_MSB : std_logic := '0';
-
--------------------------------------------------------------------------------
-
-begin
-
- paddle_x: pwm_sdadc
- port map (
- clk => clk_1MHz,
- reset => reset,
- ADC_out => Misc_PotX,
- ADC_in => poti_x
- );
-
- paddle_y: pwm_sdadc
- port map (
- clk => clk_1MHz,
- reset => reset,
- ADC_out => Misc_PotY,
- ADC_in => poti_y
- );
-
- sid_voice_1: sid_voice
- port map(
- clk_1MHz => clk_1MHz,
- reset => reset,
- Freq_lo => Voice_1_Freq_lo,
- Freq_hi => Voice_1_Freq_hi,
- Pw_lo => Voice_1_Pw_lo,
- Pw_hi => Voice_1_Pw_hi,
- Control => Voice_1_Control,
- Att_dec => Voice_1_Att_dec,
- Sus_Rel => Voice_1_Sus_Rel,
- PA_MSB_in => voice_3_PA_MSB,
- PA_MSB_out => voice_1_PA_MSB,
- Osc => Voice_1_Osc,
- Env => Voice_1_Env,
- voice => voice_1
- );
-
- sid_voice_2: sid_voice
- port map(
- clk_1MHz => clk_1MHz,
- reset => reset,
- Freq_lo => Voice_2_Freq_lo,
- Freq_hi => Voice_2_Freq_hi,
- Pw_lo => Voice_2_Pw_lo,
- Pw_hi => Voice_2_Pw_hi,
- Control => Voice_2_Control,
- Att_dec => Voice_2_Att_dec,
- Sus_Rel => Voice_2_Sus_Rel,
- PA_MSB_in => voice_1_PA_MSB,
- PA_MSB_out => voice_2_PA_MSB,
- Osc => Voice_2_Osc,
- Env => Voice_2_Env,
- voice => voice_2
- );
-
- sid_voice_3: sid_voice
- port map(
- clk_1MHz => clk_1MHz,
- reset => reset,
- Freq_lo => Voice_3_Freq_lo,
- Freq_hi => Voice_3_Freq_hi,
- Pw_lo => Voice_3_Pw_lo,
- Pw_hi => Voice_3_Pw_hi,
- Control => Voice_3_Control,
- Att_dec => Voice_3_Att_dec,
- Sus_Rel => Voice_3_Sus_Rel,
- PA_MSB_in => voice_2_PA_MSB,
- PA_MSB_out => voice_3_PA_MSB,
- Osc => Misc_Osc3_Random,
- Env => Misc_Env3,
- voice => voice_3
- );
-
--------------------------------------------------------------------------------------
-data_o <= do_buf;
-
--- add voice 1+2 and 3, we must do this in this way to create the shortest
--- timing path (keep in mind that a basic adder can only add two variables)
-voice_mixed <= (("00" & voice_1) + ("00" & voice_2)) + (voice_3 + DC_offset);
--- multiply the volume register with the voices
-audio_data <= (voice_mixed * Filter_Mode_Vol(3 downto 0));
-
--- Register decoding
-register_decoder:process(clk32)
-begin
- if rising_edge(clk32) then
- if (reset = '1') then
- --------------------------------------- Voice-1
- Voice_1_Freq_lo <= (others => '0');
- Voice_1_Freq_hi <= (others => '0');
- Voice_1_Pw_lo <= (others => '0');
- Voice_1_Pw_hi <= (others => '0');
- Voice_1_Control <= (others => '0');
- Voice_1_Att_dec <= (others => '0');
- Voice_1_Sus_Rel <= (others => '0');
- --------------------------------------- Voice-2
- Voice_2_Freq_lo <= (others => '0');
- Voice_2_Freq_hi <= (others => '0');
- Voice_2_Pw_lo <= (others => '0');
- Voice_2_Pw_hi <= (others => '0');
- Voice_2_Control <= (others => '0');
- Voice_2_Att_dec <= (others => '0');
- Voice_2_Sus_Rel <= (others => '0');
- --------------------------------------- Voice-3
- Voice_3_Freq_lo <= (others => '0');
- Voice_3_Freq_hi <= (others => '0');
- Voice_3_Pw_lo <= (others => '0');
- Voice_3_Pw_hi <= (others => '0');
- Voice_3_Control <= (others => '0');
- Voice_3_Att_dec <= (others => '0');
- Voice_3_Sus_Rel <= (others => '0');
- --------------------------------------- Filter & volume
- Filter_Fc_lo <= (others => '0');
- Filter_Fc_hi <= (others => '0');
- Filter_Res_Filt <= (others => '0');
- Filter_Mode_Vol <= (others => '0');
- else
- Voice_1_Freq_lo <= Voice_1_Freq_lo;
- Voice_1_Freq_hi <= Voice_1_Freq_hi;
- Voice_1_Pw_lo <= Voice_1_Pw_lo;
- Voice_1_Pw_hi <= Voice_1_Pw_hi;
- Voice_1_Control <= Voice_1_Control;
- Voice_1_Att_dec <= Voice_1_Att_dec;
- Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
- Voice_2_Freq_lo <= Voice_2_Freq_lo;
- Voice_2_Freq_hi <= Voice_2_Freq_hi;
- Voice_2_Pw_lo <= Voice_2_Pw_lo;
- Voice_2_Pw_hi <= Voice_2_Pw_hi;
- Voice_2_Control <= Voice_2_Control;
- Voice_2_Att_dec <= Voice_2_Att_dec;
- Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
- Voice_3_Freq_lo <= Voice_3_Freq_lo;
- Voice_3_Freq_hi <= Voice_3_Freq_hi;
- Voice_3_Pw_lo <= Voice_3_Pw_lo;
- Voice_3_Pw_hi <= Voice_3_Pw_hi;
- Voice_3_Control <= Voice_3_Control;
- Voice_3_Att_dec <= Voice_3_Att_dec;
- Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
- Filter_Fc_lo <= Filter_Fc_lo;
- Filter_Fc_hi <= Filter_Fc_hi;
- Filter_Res_Filt <= Filter_Res_Filt;
- Filter_Mode_Vol <= Filter_Mode_Vol;
- do_buf <= (others => '0');
-
- if (cs='1') then
- if (we='1') then -- Write to SID-register
- ------------------------
- case addr is
- -------------------------------------- Voice-1
- when "00000" => Voice_1_Freq_lo <= data_i;
- when "00001" => Voice_1_Freq_hi <= data_i;
- when "00010" => Voice_1_Pw_lo <= data_i;
- when "00011" => Voice_1_Pw_hi <= data_i(3 downto 0);
- when "00100" => Voice_1_Control <= data_i;
- when "00101" => Voice_1_Att_dec <= data_i;
- when "00110" => Voice_1_Sus_Rel <= data_i;
- --------------------------------------- Voice-2
- when "00111" => Voice_2_Freq_lo <= data_i;
- when "01000" => Voice_2_Freq_hi <= data_i;
- when "01001" => Voice_2_Pw_lo <= data_i;
- when "01010" => Voice_2_Pw_hi <= data_i(3 downto 0);
- when "01011" => Voice_2_Control <= data_i;
- when "01100" => Voice_2_Att_dec <= data_i;
- when "01101" => Voice_2_Sus_Rel <= data_i;
- --------------------------------------- Voice-3
- when "01110" => Voice_3_Freq_lo <= data_i;
- when "01111" => Voice_3_Freq_hi <= data_i;
- when "10000" => Voice_3_Pw_lo <= data_i;
- when "10001" => Voice_3_Pw_hi <= data_i(3 downto 0);
- when "10010" => Voice_3_Control <= data_i;
- when "10011" => Voice_3_Att_dec <= data_i;
- when "10100" => Voice_3_Sus_Rel <= data_i;
- --------------------------------------- Filter & volume
- when "10101" => Filter_Fc_lo <= data_i;
- when "10110" => Filter_Fc_hi <= data_i;
- when "10111" => Filter_Res_Filt <= data_i;
- when "11000" => Filter_Mode_Vol <= data_i;
- --------------------------------------
- when others => null;
- end case;
-
- else -- Read from SID-register
- -------------------------
- --case CONV_INTEGER(addr) is
- case addr is
- -------------------------------------- Misc
- when "11001" => do_buf <= Misc_PotX;
- when "11010" => do_buf <= Misc_PotY;
- when "11011" => do_buf <= Misc_Osc3_Random;
- when "11100" => do_buf <= Misc_Env3;
- --------------------------------------
--- when others => null;
- when others => do_buf <= (others => '0');
- end case;
- end if;
- end if;
- end if;
- end if;
-end process;
-
-end Behavioral;
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/sid_components.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/sid_components.vhd
deleted file mode 100644
index 6f2e1ed7..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/sid_components.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------------
---
--- SID 6581 (voice)
---
--- This piece of VHDL code describes a single SID voice (sound channel)
---
--------------------------------------------------------------------------------
--- to do: - better resolution of result signal voice, this is now only 12bits,
--- but it could be 20 !! Problem, it does not fit the PWM-dac
--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.numeric_std.all;
-
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
--- dac_o 0---XXXXX---+---0 analog audio
--- 3k3 |
--- === 4n7
--- |
--- GND
---
--------------------------------------------------------------------------------
---Implementation Digital to Analog converter
-entity pwm_sddac is
- generic (
- msbi_g : integer := 9
- );
- port (
- clk_i : in std_logic;
- reset : in std_logic;
- dac_i : in std_logic_vector(msbi_g downto 0);
- dac_o : out std_logic
- );
-end pwm_sddac;
-
-architecture rtl of pwm_sddac is
- signal sig_in : unsigned(msbi_g+2 downto 0) := (others => '0');
-
-begin
- seq: process (clk_i, reset)
- begin
- if reset = '1' then
- sig_in <= to_unsigned(2**(msbi_g+1), sig_in'length);
- dac_o <= '0';
- elsif rising_edge(clk_i) then
- sig_in <= sig_in + unsigned(sig_in(msbi_g+2) & sig_in(msbi_g+2) & dac_i);
- dac_o <= sig_in(msbi_g+2);
- end if;
- end process seq;
-end rtl;
-
--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.numeric_std.all;
-
-entity pwm_sdadc is
- port (
- clk : in std_logic; -- main clock signal (the higher the better)
- reset : in std_logic; --
- ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
- ADC_in : in std_logic -- "analog" paddle input pin
- );
-end pwm_sdadc;
-
--- Dummy implementation (no real A/D conversion performed)
-architecture rtl of pwm_sdadc is
-begin
- process (clk, ADC_in)
- begin
- if ADC_in = '1' then
- ADC_out <= (others => '1');
- else
- ADC_out <= (others => '0');
- end if;
- end process;
-end rtl;
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/sid_voice.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/sid_voice.vhd
deleted file mode 100644
index 69fa50f1..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/sid_voice.vhd
+++ /dev/null
@@ -1,656 +0,0 @@
--------------------------------------------------------------------------------
---
--- SID 6581 (voice)
---
--- This piece of VHDL code describes a single SID voice (sound channel)
---
--------------------------------------------------------------------------------
--- to do: - better resolution of result signal voice, this is now only 12bits
--- but it could be 20 !! Problem, it does not fit the PWM-dac
--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
---use IEEE.std_logic_arith.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.numeric_std.all;
-
--------------------------------------------------------------------------------
-
-entity sid_voice is
- port (
- clk_1MHz : in std_logic; -- this line drives the oscilator
- reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
- Freq_lo : in std_logic_vector(7 downto 0); -- low-byte of frequency register
- Freq_hi : in std_logic_vector(7 downto 0); -- high-byte of frequency register
- Pw_lo : in std_logic_vector(7 downto 0); -- low-byte of PuleWidth register
- Pw_hi : in std_logic_vector(3 downto 0); -- high-nibble of PuleWidth register
- Control : in std_logic_vector(7 downto 0); -- control register
- Att_dec : in std_logic_vector(7 downto 0); -- attack-deccay register
- Sus_Rel : in std_logic_vector(7 downto 0); -- sustain-release register
- PA_MSB_in : in std_logic; -- Phase Accumulator MSB input
- PA_MSB_out : out std_logic; -- Phase Accumulator MSB output
- Osc : out std_logic_vector(7 downto 0); -- Voice waveform register
- Env : out std_logic_vector(7 downto 0); -- Voice envelope register
- voice : out std_logic_vector(11 downto 0) -- Voice waveform, this is the actual audio signal
- );
-end sid_voice;
-
-architecture Behavioral of sid_voice is
-
--------------------------------------------------------------------------------
--- Altera multiplier
--- COMPONENT lpm_mult
--- GENERIC
--- (
--- lpm_hint : STRING;
--- lpm_representation : STRING;
--- lpm_type : STRING;
--- lpm_widtha : NATURAL;
--- lpm_widthb : NATURAL;
--- lpm_widthp : NATURAL;
--- lpm_widths : NATURAL
--- );
--- PORT
--- (
--- dataa : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
--- datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--- result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
--- );
--- END COMPONENT;
-
--------------------------------------------------------------------------------
-
-signal accumulator : std_logic_vector(23 downto 0) := (others => '0');
-signal accu_bit_prev : std_logic := '0';
-signal PA_MSB_in_prev : std_logic := '0';
-
--- this type of signal has only two states 0 or 1 (so no more bits are required)
-signal pulse : std_logic := '0';
-signal sawtooth : std_logic_vector(11 downto 0) := (others => '0');
-signal triangle : std_logic_vector(11 downto 0) := (others => '0');
-signal noise : std_logic_vector(11 downto 0) := (others => '0');
-signal LFSR : std_logic_vector(22 downto 0) := (others => '0');
-
-signal frequency : std_logic_vector(15 downto 0) := (others => '0');
-signal pulsewidth : std_logic_vector(11 downto 0) := (others => '0');
-
--- Envelope Generator
-type envelope_state_types is (idle, attack, attack_lp, decay, decay_lp, sustain, releases, release_lp);
-signal cur_state, next_state : envelope_state_types;
-signal divider_value : integer range 0 to 2**15 - 1 :=0;
-signal divider_attack : integer range 0 to 2**15 - 1 :=0;
-signal divider_dec_rel : integer range 0 to 2**15 - 1 :=0;
-signal divider_counter : integer range 0 to 2**18 - 1 :=0;
-signal exp_table_value : integer range 0 to 2**18 - 1 :=0;
-signal exp_table_active : std_logic := '0';
-signal divider_rst : std_logic := '0';
-signal Dec_rel : std_logic_vector(3 downto 0) := (others => '0');
-signal Dec_rel_sel : std_logic := '0';
-
-signal env_counter : std_logic_vector(17 downto 0) := (others => '0');
-signal env_count_hold_A : std_logic := '0';
-signal env_count_hold_B : std_logic := '0';
-signal env_cnt_up : std_logic := '0';
-signal env_cnt_clear : std_logic := '0';
-
-signal signal_mux : std_logic_vector(17 downto 0) := (others => '0');
-signal signal_vol : std_logic_vector(35 downto 0) := (others => '0');
-
--------------------------------------------------------------------------------------
-
--- stop the oscillator when test = '1'
-alias test : std_logic is Control(3);
--- Ring Modulation was accomplished by substituting the accumulator MSB of an
--- oscillator in the EXOR function of the triangle waveform generator with the
--- accumulator MSB of the previous oscillator. That is why the triangle waveform
--- must be selected to use Ring Modulation.
-alias ringmod : std_logic is Control(2);
--- Hard Sync was accomplished by clearing the accumulator of an Oscillator
--- based on the accumulator MSB of the previous oscillator.
-alias sync : std_logic is Control(1);
---
-alias gate : std_logic is Control(0);
-
--------------------------------------------------------------------------------------
-
-begin
-
--- output the Phase accumulator's MSB for sync and ringmod purposes
-PA_MSB_out <= accumulator(23);
--- output the upper 8-bits of the waveform.
--- Useful for random numbers (noise must be selected)
-Osc <= signal_mux(11 downto 4);
--- output the envelope register, for special sound effects when connecting this
--- signal to the input of other channels/voices
-Env <= env_counter(7 downto 0);
--- use the register value to fill the variable
-frequency(15 downto 8) <= Freq_hi(7 downto 0);
---
-frequency(7 downto 0) <= Freq_lo(7 downto 0);
--- use the register value to fill the variable
-pulsewidth(11 downto 8) <= Pw_hi(3 downto 0);
---
-pulsewidth(7 downto 0) <= Pw_lo(7 downto 0);
---
-voice <= signal_vol(19 downto 8);
-
--- Phase accumulator :
--- "As I recall, the Oscillator is a 24-bit phase-accumulating design of which
--- the lower 16-bits are programmable for pitch control. The output of the
--- accumulator goes directly to a D/A converter through a waveform selector.
--- Normally, the output of a phase-accumulating oscillator would be used as an
--- address into memory which contained a wavetable, but SID had to be entirely
--- self-contained and there was no room at all for a wavetable on the chip."
--- "Hard Sync was accomplished by clearing the accumulator of an Oscillator
--- based on the accumulator MSB of the previous oscillator."
-PhaseAcc:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- PA_MSB_in_prev <= PA_MSB_in;
- -- the reset and test signal can stop the oscillator,
- -- stopping the oscillator is very useful when you want to play "samples"
- if ((reset = '1') or (test = '1') or ((sync = '1') and (PA_MSB_in_prev /= PA_MSB_in) and (PA_MSB_in = '0'))) then
- accumulator <= (others => '0');
- else
- -- accumulate the new phase (i.o.w. increment env_counter with the freq. value)
- accumulator <= accumulator + ("0" & frequency(15 downto 0));
- end if;
- end if;
-end process;
-
--- Sawtooth waveform :
--- "The Sawtooth waveform was created by sending the upper 12-bits of the
--- accumulator to the 12-bit Waveform D/A."
-Snd_Sawtooth:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- sawtooth <= accumulator(23 downto 12);
- end if;
-end process;
-
---Pulse waveform :
--- "The Pulse waveform was created by sending the upper 12-bits of the
--- accumulator to a 12-bit digital comparator. The output of the comparator was
--- either a one or a zero. This single output was then sent to all 12 bits of
--- the Waveform D/A. "
-Snd_pulse:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- if ((accumulator(23 downto 12)) >= (pulsewidth(11 downto 0))) then
- pulse <= '1';
- else
- pulse <= '0';
- end if;
- end if;
-end process;
-
---Triangle waveform :
--- "The Triangle waveform was created by using the MSB of the accumulator to
--- invert the remaining upper 11 accumulator bits using EXOR gates. These 11
--- bits were then left-shifted (throwing away the MSB) and sent to the Waveform
--- D/A (so the resolution of the triangle waveform was half that of the sawtooth,
--- but the amplitude and frequency were the same). "
--- "Ring Modulation was accomplished by substituting the accumulator MSB of an
--- oscillator in the EXOR function of the triangle waveform generator with the
--- accumulator MSB of the previous oscillator. That is why the triangle waveform
--- must be selected to use Ring Modulation."
-Snd_triangle:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- if ringmod = '0' then
- -- no ringmodulation
- triangle(11)<= accumulator(23) xor accumulator(22);
- triangle(10)<= accumulator(23) xor accumulator(21);
- triangle(9) <= accumulator(23) xor accumulator(20);
- triangle(8) <= accumulator(23) xor accumulator(19);
- triangle(7) <= accumulator(23) xor accumulator(18);
- triangle(6) <= accumulator(23) xor accumulator(17);
- triangle(5) <= accumulator(23) xor accumulator(16);
- triangle(4) <= accumulator(23) xor accumulator(15);
- triangle(3) <= accumulator(23) xor accumulator(14);
- triangle(2) <= accumulator(23) xor accumulator(13);
- triangle(1) <= accumulator(23) xor accumulator(12);
- triangle(0) <= accumulator(23) xor accumulator(11);
- else
- -- ringmodulation by the other voice (previous voice)
- triangle(11)<= PA_MSB_in xor accumulator(22);
- triangle(10)<= PA_MSB_in xor accumulator(21);
- triangle(9) <= PA_MSB_in xor accumulator(20);
- triangle(8) <= PA_MSB_in xor accumulator(19);
- triangle(7) <= PA_MSB_in xor accumulator(18);
- triangle(6) <= PA_MSB_in xor accumulator(17);
- triangle(5) <= PA_MSB_in xor accumulator(16);
- triangle(4) <= PA_MSB_in xor accumulator(15);
- triangle(3) <= PA_MSB_in xor accumulator(14);
- triangle(2) <= PA_MSB_in xor accumulator(13);
- triangle(1) <= PA_MSB_in xor accumulator(12);
- triangle(0) <= PA_MSB_in xor accumulator(11);
- end if;
- end if;
-end process;
-
---Noise (23-bit Linear Feedback Shift Register, max combinations = 8388607) :
--- "The Noise waveform was created using a 23-bit pseudo-random sequence
--- generator (i.e., a shift register with specific outputs fed back to the input
--- through combinatorial logic). The shift register was clocked by one of the
--- intermediate bits of the accumulator to keep the frequency content of the
--- noise waveform relatively the same as the pitched waveforms.
--- The upper 12-bits of the shift register were sent to the Waveform D/A."
-noise <= LFSR(22 downto 11);
-
-Snd_noise:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- -- the test signal can stop the oscillator,
- -- stopping the oscillator is very useful when you want to play "samples"
- if ((reset = '1') or (test = '1')) then
- accu_bit_prev <= '0';
- -- the "seed" value (the value that eventually determines the output
- -- pattern) may never be '0' otherwise the generator "locks up"
- LFSR <= "00000000000000000000001";
- else
- accu_bit_prev <= accumulator(22);
- -- when not equal to ...
- if (accu_bit_prev /= accumulator(22)) then
- LFSR(22 downto 1) <= LFSR(21 downto 0);
- LFSR(0) <= LFSR(17) xor LFSR(22); -- see Xilinx XAPP052 for maximal LFSR taps
- else
- LFSR <= LFSR;
- end if;
- end if;
- end if;
-end process;
-
--- Waveform Output selector (MUX):
--- "Since all of the waveforms were just digital bits, the Waveform Selector
--- consisted of multiplexers that selected which waveform bits would be sent
--- to the Waveform D/A. The multiplexers were single transistors and did not
--- provide a "lock-out", allowing combinations of the waveforms to be selected.
--- The combination was actually a logical ANDing of the bits of each waveform,
--- which produced unpredictable results, so I didn't encourage this, especially
--- since it could lock up the pseudo-random sequence generator by filling it
--- with zeroes."
-Snd_select:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- signal_mux(11) <= (triangle(11) and Control(4)) or (sawtooth(11) and Control(5)) or (pulse and Control(6)) or (noise(11) and Control(7));
- signal_mux(10) <= (triangle(10) and Control(4)) or (sawtooth(10) and Control(5)) or (pulse and Control(6)) or (noise(10) and Control(7));
- signal_mux(9) <= (triangle(9) and Control(4)) or (sawtooth(9) and Control(5)) or (pulse and Control(6)) or (noise(9) and Control(7));
- signal_mux(8) <= (triangle(8) and Control(4)) or (sawtooth(8) and Control(5)) or (pulse and Control(6)) or (noise(8) and Control(7));
- signal_mux(7) <= (triangle(7) and Control(4)) or (sawtooth(7) and Control(5)) or (pulse and Control(6)) or (noise(7) and Control(7));
- signal_mux(6) <= (triangle(6) and Control(4)) or (sawtooth(6) and Control(5)) or (pulse and Control(6)) or (noise(6) and Control(7));
- signal_mux(5) <= (triangle(5) and Control(4)) or (sawtooth(5) and Control(5)) or (pulse and Control(6)) or (noise(5) and Control(7));
- signal_mux(4) <= (triangle(4) and Control(4)) or (sawtooth(4) and Control(5)) or (pulse and Control(6)) or (noise(4) and Control(7));
- signal_mux(3) <= (triangle(3) and Control(4)) or (sawtooth(3) and Control(5)) or (pulse and Control(6)) or (noise(3) and Control(7));
- signal_mux(2) <= (triangle(2) and Control(4)) or (sawtooth(2) and Control(5)) or (pulse and Control(6)) or (noise(2) and Control(7));
- signal_mux(1) <= (triangle(1) and Control(4)) or (sawtooth(1) and Control(5)) or (pulse and Control(6)) or (noise(1) and Control(7));
- signal_mux(0) <= (triangle(0) and Control(4)) or (sawtooth(0) and Control(5)) or (pulse and Control(6)) or (noise(0) and Control(7));
- end if;
-end process;
-
--- Waveform envelope (volume) control :
--- "The output of the Waveform D/A (which was an analog voltage at this point)
--- was fed into the reference input of an 8-bit multiplying D/A, creating a DCA
--- (digitally-controlled-amplifier). The digital control word which modulated
--- the amplitude of the waveform came from the Envelope Generator."
--- "The 8-bit output of the Envelope Generator was then sent to the Multiplying
--- D/A converter to modulate the amplitude of the selected Oscillator Waveform
--- (to be technically accurate, actually the waveform was modulating the output
--- of the Envelope Generator, but the result is the same)."
- Envelope_multiplier:process(clk_1MHz)
- begin
- if (rising_edge(clk_1MHz)) then
- --calculate the resulting volume (due to the envelope generator) of the
- --voice, signal_mux(12bit) * env_counter(8bit), so the result will
- --require 20 bits !!
- signal_vol <= signal_mux * env_counter;
- end if;
-end process;
-
--- Altera multiplier
--- lpm_mult_component : lpm_mult
--- GENERIC MAP
--- (
--- lpm_hint => "MAXIMIZE_SPEED=5",
--- lpm_representation => "UNSIGNED",
--- lpm_type => "LPM_MULT",
--- lpm_widtha => 12,
--- lpm_widthb => 8,
--- lpm_widthp => 20,
--- lpm_widths => 1
--- )
--- PORT MAP
--- (
--- dataa(11 downto 0) => signal_mux,
--- datab(7 downto 0) => env_counter,
--- result => signal_vol
--- );
-
--- Envelope generator :
--- "The Envelope Generator was simply an 8-bit up/down counter which, when
--- triggered by the Gate bit, counted from 0 to 255 at the Attack rate, from
--- 255 down to the programmed Sustain value at the Decay rate, remained at the
--- Sustain value until the Gate bit was cleared then counted down from the
--- Sustain value to 0 at the Release rate."
---
--- /\
--- / \
--- / | \________
--- / | | \
--- / | | |\
--- / | | | \
--- attack|dec|sustain|rel
-
--- this process controls the state machine "current-state"-value
-Envelope_SM_advance: process (reset, clk_1MHz)
-begin
- if (reset = '1') then
- cur_state <= idle;
- else
- if (rising_edge(clk_1MHz)) then
- cur_state <= next_state;
- end if;
- end if;
-end process;
-
-
--- this process controls the envelope (in other words, the volume control)
-Envelope_SM: process (reset, cur_state, gate, divider_attack, divider_dec_rel, Att_dec, Sus_Rel, env_counter)
-begin
- if (reset = '1') then
- next_state <= idle;
- env_cnt_clear <='1';
- env_cnt_up <='1';
- env_count_hold_B <='1';
- divider_rst <='1';
- divider_value <= 0;
- exp_table_active <='0';
- Dec_rel_sel <='0'; -- select decay as input for decay/release table
- else
- env_cnt_clear <='0'; -- use this statement unless stated otherwise
- env_cnt_up <='1'; -- use this statement unless stated otherwise
- env_count_hold_B <='1'; -- use this statement unless stated otherwise
- divider_rst <='0'; -- use this statement unless stated otherwise
- divider_value <= 0; -- use this statement unless stated otherwise
- exp_table_active <='0'; -- use this statement unless stated otherwise
- case cur_state is
-
- -- IDLE
- when idle =>
- env_cnt_clear <= '1'; -- clear envelope env_counter
- divider_rst <= '1';
- Dec_rel_sel <= '0'; -- select decay as input for decay/release table
- if gate = '1' then
- next_state <= attack;
- else
- next_state <= idle;
- end if;
-
- when attack =>
- env_cnt_clear <= '1'; -- clear envelope env_counter
- divider_rst <= '1';
- divider_value <= divider_attack;
- next_state <= attack_lp;
- Dec_rel_sel <= '0'; -- select decay as input for decay/release table
-
- when attack_lp =>
- env_count_hold_B <= '0'; -- enable envelope env_counter
- env_cnt_up <= '1'; -- envelope env_counter must count up (increment)
- divider_value <= divider_attack;
- Dec_rel_sel <= '0'; -- select decay as input for decay/release table
- if env_counter = "11111111" then
- next_state <= decay;
- else
- if gate = '0' then
- next_state <= releases;
- else
- next_state <= attack_lp;
- end if;
- end if;
-
- when decay =>
- divider_rst <= '1';
- exp_table_active <= '1'; -- activate exponential look-up table
- env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
- divider_value <= divider_dec_rel;
- next_state <= decay_lp;
- Dec_rel_sel <= '0'; -- select decay as input for decay/release table
-
- when decay_lp =>
- exp_table_active <= '1'; -- activate exponential look-up table
- env_count_hold_B <= '0'; -- enable envelope env_counter
- env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
- divider_value <= divider_dec_rel;
- Dec_rel_sel <= '0'; -- select decay as input for decay/release table
- if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
- next_state <= sustain;
- else
- if gate = '0' then
- next_state <= releases;
- else
- next_state <= decay_lp;
- end if;
- end if;
-
- -- "A digital comparator was used for the Sustain function. The upper
- -- four bits of the Up/Down counter were compared to the programmed
- -- Sustain value and would stop the clock to the Envelope Generator when
- -- the counter counted down to the Sustain value. This created 16 linearly
- -- spaced sustain levels without havingto go through a look-up table
- -- translation between the 4-bit register value and the 8-bit Envelope
- -- Generator output. It also meant that sustain levels were adjustable
- -- in steps of 16. Again, more register bits would have provided higher
- -- resolution."
- -- "When the Gate bit was cleared, the clock would again be enabled,
- -- allowing the counter to count down to zero. Like an analog envelope
- -- generator, the SID Envelope Generator would track the Sustain level
- -- if it was changed to a lower value during the Sustain portion of the
- -- envelope, however, it would not count UP if the Sustain level were set
- -- higher." Instead it would count down to '0'.
- when sustain =>
- divider_value <= 0;
- Dec_rel_sel <='1'; -- select release as input for decay/release table
- if gate = '0' then
- next_state <= releases;
- else
- if (env_counter(7 downto 4) = Sus_Rel(7 downto 4)) then
- next_state <= sustain;
- else
- next_state <= decay;
- end if;
- end if;
-
- when releases =>
- divider_rst <= '1';
- exp_table_active <= '1'; -- activate exponential look-up table
- env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
- divider_value <= divider_dec_rel;
- Dec_rel_sel <= '1'; -- select release as input for decay/release table
- next_state <= release_lp;
-
- when release_lp =>
- exp_table_active <= '1'; -- activate exponential look-up table
- env_count_hold_B <= '0'; -- enable envelope env_counter
- env_cnt_up <= '0'; -- envelope env_counter must count down (decrement)
- divider_value <= divider_dec_rel;
- Dec_rel_sel <= '1'; -- select release as input for decay/release table
- if env_counter = "00000000" then
- next_state <= idle;
- else
- if gate = '1' then
- next_state <= idle;
- else
- next_state <= release_lp;
- end if;
- end if;
-
- when others =>
- divider_value <= 0;
- Dec_rel_sel <= '0'; -- select decay as input for decay/release table
- next_state <= idle;
- end case;
- end if;
-end process;
-
--- 8 bit up/down env_counter
-Envelope_counter:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- if ((reset = '1') or (env_cnt_clear = '1')) then
- env_counter <= (others => '0');
- else
- if ((env_count_hold_A = '1') or (env_count_hold_B = '1'))then
- env_counter <= env_counter;
- else
- if (env_cnt_up = '1') then
- env_counter <= env_counter + 1;
- else
- env_counter <= env_counter - 1;
- end if;
- end if;
- end if;
- end if;
-end process;
-
--- Divider :
--- "A programmable frequency divider was used to set the various rates
--- (unfortunately I don't remember how many bits the divider was, either 12
--- or 16 bits). A small look-up table translated the 16 register-programmable
--- values to the appropriate number to load into the frequency divider.
--- Depending on what state the Envelope Generator was in (i.e. ADS or R), the
--- appropriate register would be selected and that number would be translated
--- and loaded into the divider. Obviously it would have been better to have
--- individual bit control of the divider which would have provided great
--- resolution for each rate, however I did not have enough silicon area for a
--- lot of register bits. Using this approach, I was able to cram a wide range
--- of rates into 4 bits, allowing the ADSR to be defined in two bytes instead
--- of eight. The actual numbers in the look-up table were arrived at
--- subjectively by setting up typical patches on a Sequential Circuits Pro-1
--- and measuring the envelope times by ear (which is why the available rates
--- seem strange)!"
-prog_freq_div:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- if ((reset = '1') or (divider_rst = '1')) then
- env_count_hold_A <= '1';
- divider_counter <= 0;
- else
- if (divider_counter = 0) then
- env_count_hold_A <= '0';
- if (exp_table_active = '1') then
- divider_counter <= exp_table_value;
- else
- divider_counter <= divider_value;
- end if;
- else
- env_count_hold_A <= '1';
- divider_counter <= divider_counter - 1;
- end if;
- end if;
- end if;
-end process;
-
--- Piese-wise linear approximation of an exponential :
--- "In order to more closely model the exponential decay of sounds, another
--- look-up table on the output of the Envelope Generator would sequentially
--- divide the clock to the Envelope Generator by two at specific counts in the
--- Decay and Release cycles. This created a piece-wise linear approximation of
--- an exponential. I was particularly happy how well this worked considering
--- the simplicity of the circuitry. The Attack, however, was linear, but this
--- sounded fine."
--- The clock is divided by two at specifiek values of the envelope generator to
--- create an exponential.
-Exponential_table:process(clk_1MHz)
-BEGIN
- if (rising_edge(clk_1MHz)) then
- if (reset = '1') then
- exp_table_value <= 0;
- else
- case CONV_INTEGER(env_counter) is
- when 0 to 51 => exp_table_value <= divider_value * 16;
- when 52 to 101 => exp_table_value <= divider_value * 8;
- when 102 to 152 => exp_table_value <= divider_value * 4;
- when 153 to 203 => exp_table_value <= divider_value * 2;
- when 204 to 255 => exp_table_value <= divider_value;
- when others => exp_table_value <= divider_value;
- end case;
- end if;
- end if;
-end process;
-
--- Attack Lookup table :
--- It takes 255 clock cycles from zero to peak value. Therefore the divider
--- equals (attack rate / clockcycletime of 1MHz clock) / 254;
-Attack_table:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- if (reset = '1') then
- divider_attack <= 0;
- else
- case Att_dec(7 downto 4) is
- when "0000" => divider_attack <= 8; --attack rate: ( 2mS / 1uS per clockcycle) /254 steps
- when "0001" => divider_attack <= 31; --attack rate: ( 8mS / 1uS per clockcycle) /254 steps
- when "0010" => divider_attack <= 63; --attack rate: ( 16mS / 1uS per clockcycle) /254 steps
- when "0011" => divider_attack <= 94; --attack rate: ( 24mS / 1uS per clockcycle) /254 steps
- when "0100" => divider_attack <= 150; --attack rate: ( 38mS / 1uS per clockcycle) /254 steps
- when "0101" => divider_attack <= 220; --attack rate: ( 56mS / 1uS per clockcycle) /254 steps
- when "0110" => divider_attack <= 268; --attack rate: ( 68mS / 1uS per clockcycle) /254 steps
- when "0111" => divider_attack <= 315; --attack rate: ( 80mS / 1uS per clockcycle) /254 steps
- when "1000" => divider_attack <= 394; --attack rate: ( 100mS / 1uS per clockcycle) /254 steps
- when "1001" => divider_attack <= 984; --attack rate: ( 250mS / 1uS per clockcycle) /254 steps
- when "1010" => divider_attack <= 1968; --attack rate: ( 500mS / 1uS per clockcycle) /254 steps
- when "1011" => divider_attack <= 3150; --attack rate: ( 800mS / 1uS per clockcycle) /254 steps
- when "1100" => divider_attack <= 3937; --attack rate: (1000mS / 1uS per clockcycle) /254 steps
- when "1101" => divider_attack <= 11811; --attack rate: (3000mS / 1uS per clockcycle) /254 steps
- when "1110" => divider_attack <= 19685; --attack rate: (5000mS / 1uS per clockcycle) /254 steps
- when "1111" => divider_attack <= 31496; --attack rate: (8000mS / 1uS per clockcycle) /254 steps
- when others => divider_attack <= 0; --
- end case;
- end if;
- end if;
-end process;
-
-Decay_Release_input_select:process(Dec_rel_sel, Att_dec, Sus_Rel)
-begin
- if (Dec_rel_sel = '0') then
- Dec_rel(3 downto 0) <= Att_dec(3 downto 0);
- else
- Dec_rel(3 downto 0) <= Sus_rel(3 downto 0);
- end if;
-end process;
-
--- Decay Lookup table :
--- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
--- Release Lookup table :
--- It takes 32 * 51 = 1632 clock cycles to fall from peak level to zero.
-Decay_Release_table:process(clk_1MHz)
-begin
- if (rising_edge(clk_1MHz)) then
- if reset = '1' then
- divider_dec_rel <= 0;
- else
- case Dec_rel(3 downto 0) is
- when "0000" => divider_dec_rel <= 3; --release rate: ( 6mS / 1uS per clockcycle) / 1632
- when "0001" => divider_dec_rel <= 15; --release rate: ( 24mS / 1uS per clockcycle) / 1632
- when "0010" => divider_dec_rel <= 29; --release rate: ( 48mS / 1uS per clockcycle) / 1632
- when "0011" => divider_dec_rel <= 44; --release rate: ( 72mS / 1uS per clockcycle) / 1632
- when "0100" => divider_dec_rel <= 70; --release rate: ( 114mS / 1uS per clockcycle) / 1632
- when "0101" => divider_dec_rel <= 103; --release rate: ( 168mS / 1uS per clockcycle) / 1632
- when "0110" => divider_dec_rel <= 125; --release rate: ( 204mS / 1uS per clockcycle) / 1632
- when "0111" => divider_dec_rel <= 147; --release rate: ( 240mS / 1uS per clockcycle) / 1632
- when "1000" => divider_dec_rel <= 184; --release rate: ( 300mS / 1uS per clockcycle) / 1632
- when "1001" => divider_dec_rel <= 459; --release rate: ( 750mS / 1uS per clockcycle) / 1632
- when "1010" => divider_dec_rel <= 919; --release rate: ( 1500mS / 1uS per clockcycle) / 1632
- when "1011" => divider_dec_rel <= 1471; --release rate: ( 2400mS / 1uS per clockcycle) / 1632
- when "1100" => divider_dec_rel <= 1838; --release rate: ( 3000mS / 1uS per clockcycle) / 1632
- when "1101" => divider_dec_rel <= 5515; --release rate: ( 9000mS / 1uS per clockcycle) / 1632
- when "1110" => divider_dec_rel <= 9191; --release rate: (15000mS / 1uS per clockcycle) / 1632
- when "1111" => divider_dec_rel <= 14706; --release rate: (24000mS / 1uS per clockcycle) / 1632
- when others => divider_dec_rel <= 0; --
- end case;
- end if;
- end if;
-end process;
-
-end Behavioral;
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/sigma_delta_dac.v b/Computer_MiST/Commodore - MAX_MiST/rtl/sigma_delta_dac.v
deleted file mode 100644
index 34cfd312..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/sigma_delta_dac.v
+++ /dev/null
@@ -1,33 +0,0 @@
-//
-// PWM DAC
-//
-// MSBI is the highest bit number. NOT amount of bits!
-//
-module sigma_delta_dac #(parameter MSBI=18)
-(
- output reg DACout, //Average Output feeding analog lowpass
- input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
- input CLK,
- input RESET
-);
-
-reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
-reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
-reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
-reg [MSBI+2:0] DeltaB; //B input of Delta Adder
-
-always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
-always @(*) DeltaAdder = DACin + DeltaB;
-always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
-
-always @(posedge CLK or posedge RESET) begin
- if(RESET) begin
- SigmaLatch <= 1'b1 << (MSBI+1);
- DACout <= 1;
- end else begin
- SigmaLatch <= SigmaAdder;
- DACout <= ~SigmaLatch[MSBI+2];
- end
-end
-
-endmodule
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/user_io.v b/Computer_MiST/Commodore - MAX_MiST/rtl/user_io.v
deleted file mode 100644
index c66c515f..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/user_io.v
+++ /dev/null
@@ -1,411 +0,0 @@
-//
-// user_io.v
-//
-// user_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see .
-//
-
-// parameter STRLEN and the actual length of conf_str have to match
-
-module user_io #(parameter STRLEN=0) (
- input [(8*STRLEN)-1:0] conf_str,
-
- input SPI_CLK,
- input SPI_SS_IO,
- output reg SPI_MISO,
- input SPI_MOSI,
-
- output reg [7:0] joystick_0,
- output reg [7:0] joystick_1,
- output reg [15:0] joystick_analog_0,
- output reg [15:0] joystick_analog_1,
- output [1:0] buttons,
- output [1:0] switches,
- output scandoubler_disable,
-
- output reg [7:0] status,
-
- // connection to sd card emulation
- input [31:0] sd_lba,
- input sd_rd,
- input sd_wr,
- output reg sd_ack,
- input sd_conf,
- input sd_sdhc,
- output reg [7:0] sd_dout,
- output reg sd_dout_strobe,
- input [7:0] sd_din,
- output reg sd_din_strobe,
-
-
- // ps2 keyboard emulation
- input ps2_clk, // 12-16khz provided by core
- output ps2_kbd_clk,
- output reg ps2_kbd_data,
- output ps2_mouse_clk,
- output reg ps2_mouse_data,
-
- // serial com port
- input [7:0] serial_data,
- input serial_strobe
-);
-
-reg [6:0] sbuf;
-reg [7:0] cmd;
-reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
-reg [7:0] byte_cnt; // counts bytes
-reg [7:0] joystick0;
-reg [7:0] joystick1;
-reg [4:0] but_sw;
-reg [2:0] stick_idx;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoubler_disable = but_sw[4];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
-
-// filter spi clock. the 8 bit gate delay is ~2.5ns in total
-wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
-wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
-
-// drive MISO only when transmitting core id
-always@(negedge spi_sck or posedge SPI_SS_IO) begin
- if(SPI_SS_IO == 1) begin
- SPI_MISO <= 1'bZ;
- end else begin
-
- // first byte returned is always core type, further bytes are
- // command dependent
- if(byte_cnt == 0) begin
- SPI_MISO <= core_type[~bit_cnt];
-
- end else begin
- // reading serial fifo
- if(cmd == 8'h1b) begin
- // send alternating flag byte and data
- if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt];
- else SPI_MISO <= serial_out_byte[~bit_cnt];
- end
-
- // reading config string
- else if(cmd == 8'h14) begin
- // returning a byte from string
- if(byte_cnt < STRLEN + 1)
- SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
- else
- SPI_MISO <= 1'b0;
- end
-
- // reading sd card status
- else if(cmd == 8'h16) begin
- if(byte_cnt == 1)
- SPI_MISO <= sd_cmd[~bit_cnt];
- else if((byte_cnt >= 2) && (byte_cnt < 6))
- SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
- else
- SPI_MISO <= 1'b0;
- end
-
- // reading sd card write data
- else if(cmd == 8'h18)
- SPI_MISO <= sd_din[~bit_cnt];
-
- else
- SPI_MISO <= 1'b0;
- end
- end
-end
-
-// ---------------- PS2 ---------------------
-
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-// keyboard
-reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge ps2_clk) begin
- ps2_kbd_r_inc <= 1'b0;
-
- if(ps2_kbd_r_inc)
- ps2_kbd_rptr <= ps2_kbd_rptr + 1;
-
- // transmitter is idle?
- if(ps2_kbd_tx_state == 0) begin
- // data in fifo present?
- if(ps2_kbd_wptr != ps2_kbd_rptr) begin
- // load tx register from fifo
- ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
- ps2_kbd_r_inc <= 1'b1;
-
- // reset parity
- ps2_kbd_parity <= 1'b1;
-
- // start transmitter
- ps2_kbd_tx_state <= 4'd1;
-
- // put start bit on data line
- ps2_kbd_data <= 1'b0; // start bit is 0
- end
- end else begin
-
- // transmission of 8 data bits
- if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
- ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
- ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
- if(ps2_kbd_tx_byte[0])
- ps2_kbd_parity <= !ps2_kbd_parity;
- end
-
- // transmission of parity
- if(ps2_kbd_tx_state == 9)
- ps2_kbd_data <= ps2_kbd_parity;
-
- // transmission of stop bit
- if(ps2_kbd_tx_state == 10)
- ps2_kbd_data <= 1'b1; // stop bit is 1
-
- // advance state machine
- if(ps2_kbd_tx_state < 11)
- ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
- else
- ps2_kbd_tx_state <= 4'd0;
-
- end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge ps2_clk) begin
- ps2_mouse_r_inc <= 1'b0;
-
- if(ps2_mouse_r_inc)
- ps2_mouse_rptr <= ps2_mouse_rptr + 1;
-
- // transmitter is idle?
- if(ps2_mouse_tx_state == 0) begin
- // data in fifo present?
- if(ps2_mouse_wptr != ps2_mouse_rptr) begin
- // load tx register from fifo
- ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
- ps2_mouse_r_inc <= 1'b1;
-
- // reset parity
- ps2_mouse_parity <= 1'b1;
-
- // start transmitter
- ps2_mouse_tx_state <= 4'd1;
-
- // put start bit on data line
- ps2_mouse_data <= 1'b0; // start bit is 0
- end
- end else begin
-
- // transmission of 8 data bits
- if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
- ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
- ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
- if(ps2_mouse_tx_byte[0])
- ps2_mouse_parity <= !ps2_mouse_parity;
- end
-
- // transmission of parity
- if(ps2_mouse_tx_state == 9)
- ps2_mouse_data <= ps2_mouse_parity;
-
- // transmission of stop bit
- if(ps2_mouse_tx_state == 10)
- ps2_mouse_data <= 1'b1; // stop bit is 1
-
- // advance state machine
- if(ps2_mouse_tx_state < 11)
- ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
- else
- ps2_mouse_tx_state <= 4'd0;
-
- end
-end
-
-// fifo to receive serial data from core to be forwarded to io controller
-
-// 16 byte fifo to store serial bytes
-localparam SERIAL_OUT_FIFO_BITS = 6;
-reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
-reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
-reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
-
-wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
-wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
-wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
-
-// status[0] is reset signal from io controller and is thus used to flush
-// the fifo
-always @(posedge serial_strobe or posedge status[0]) begin
- if(status[0] == 1) begin
- serial_out_wptr <= 0;
- end else begin
- serial_out_fifo[serial_out_wptr] <= serial_data;
- serial_out_wptr <= serial_out_wptr + 1;
- end
-end
-
-always@(negedge spi_sck or posedge status[0]) begin
- if(status[0] == 1) begin
- serial_out_rptr <= 0;
- end else begin
- if((byte_cnt != 0) && (cmd == 8'h1b)) begin
- // read last bit -> advance read pointer
- if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
- serial_out_rptr <= serial_out_rptr + 1;
- end
- end
-end
-
-// SPI receiver
-always@(posedge spi_sck or posedge SPI_SS_IO) begin
-
- if(SPI_SS_IO == 1) begin
- bit_cnt <= 3'd0;
- byte_cnt <= 8'd0;
- sd_ack <= 1'b0;
- sd_dout_strobe <= 1'b0;
- sd_din_strobe <= 1'b0;
- end else begin
- sd_dout_strobe <= 1'b0;
- sd_din_strobe <= 1'b0;
-
- sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
- bit_cnt <= bit_cnt + 3'd1;
- if((bit_cnt == 7)&&(byte_cnt != 8'd255))
- byte_cnt <= byte_cnt + 8'd1;
-
- // finished reading command byte
- if(bit_cnt == 7) begin
- if(byte_cnt == 0) begin
- cmd <= { sbuf, SPI_MOSI};
-
- // fetch first byte when sectore FPGA->IO command has been seen
- if({ sbuf, SPI_MOSI} == 8'h18)
- sd_din_strobe <= 1'b1;
-
- if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
- sd_ack <= 1'b1;
-
- end else begin
-
- // buttons and switches
- if(cmd == 8'h01)
- but_sw <= { sbuf[3:0], SPI_MOSI };
-
- if(cmd == 8'h02)
- joystick_0 <= { sbuf, SPI_MOSI };
-
- if(cmd == 8'h03)
- joystick_1 <= { sbuf, SPI_MOSI };
-
- if(cmd == 8'h04) begin
- // store incoming ps2 mouse bytes
- ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI };
- ps2_mouse_wptr <= ps2_mouse_wptr + 1;
- end
-
- if(cmd == 8'h05) begin
- // store incoming ps2 keyboard bytes
- ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI };
- ps2_kbd_wptr <= ps2_kbd_wptr + 1;
- end
-
- if(cmd == 8'h15)
- status <= { sbuf[6:0], SPI_MOSI };
-
- // send sector IO -> FPGA
- if(cmd == 8'h17) begin
- // flag that download begins
- sd_dout <= { sbuf, SPI_MOSI};
- sd_dout_strobe <= 1'b1;
- end
-
- // send sector FPGA -> IO
- if(cmd == 8'h18)
- sd_din_strobe <= 1'b1;
-
- // send SD config IO -> FPGA
- if(cmd == 8'h19) begin
- // flag that download begins
- sd_dout <= { sbuf, SPI_MOSI};
- // sd card knows data is config if sd_dout_strobe is asserted
- // with sd_ack still being inactive (low)
- sd_dout_strobe <= 1'b1;
- end
-
- // joystick analog
- if(cmd == 8'h1a) begin
- // first byte is joystick indes
- if(byte_cnt == 1)
- stick_idx <= { sbuf[1:0], SPI_MOSI };
- else if(byte_cnt == 2) begin
- // second byte is x axis
- if(stick_idx == 0)
- joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
- else if(stick_idx == 1)
- joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
- end else if(byte_cnt == 3) begin
- // third byte is y axis
- if(stick_idx == 0)
- joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
- else if(stick_idx == 1)
- joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
- end
- end
-
- end
- end
- end
-end
-
-endmodule
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/vic_656x_a.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/vic_656x_a.vhd
deleted file mode 100644
index 7333518f..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/vic_656x_a.vhd
+++ /dev/null
@@ -1,1447 +0,0 @@
--- -----------------------------------------------------------------------
---
--- FPGA 64
---
--- A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- VIC-II - Video Interface Chip no 2
---
--- -----------------------------------------------------------------------
--- Dar 08/03/2014 : shift hsync to sprite #3
--- -----------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-architecture rtl of vic_656x is
- type vicCycles is (
- cycleRefresh1, cycleRefresh2, cycleRefresh3, cycleRefresh4, cycleRefresh5,
- cycleIdle1,
- cycleChar,
- cycleCalcSprites, cycleSpriteBa1, cycleSpriteBa2, cycleSpriteBa3,
- cycleSpriteA, cycleSpriteB
- );
- subtype ColorDef is unsigned(3 downto 0);
- type MFlags is array(0 to 7) of boolean;
- type MXdef is array(0 to 7) of unsigned(8 downto 0);
- type MYdef is array(0 to 7) of unsigned(7 downto 0);
- type MCntDef is array(0 to 7) of unsigned(5 downto 0);
- type MPixelsDef is array(0 to 7) of unsigned(23 downto 0);
- type MCurrentPixelDef is array(0 to 7) of unsigned(1 downto 0);
- type charStoreDef is array(38 downto 0) of unsigned(11 downto 0);
- type spriteColorsDef is array(7 downto 0) of unsigned(3 downto 0);
- type pixelColorStoreDef is array(7 downto 0) of unsigned(3 downto 0);
-
--- State machine
- signal lastLineFlag : boolean; -- True for on last line of the frame.
- signal beyondFrameFlag : boolean; -- Y>frame lines
- signal vicCycle : vicCycles := cycleRefresh1;
- signal sprite : unsigned(2 downto 0) := "000";
- signal shiftChars : boolean;
- signal idle: std_logic := '1';
- signal rasterIrqDone : std_logic; -- Only one interrupt each rasterLine
- signal rasterEnable: std_logic;
-
--- BA signal
- signal badLine : boolean; -- true if we have a badline condition
- signal baLoc : std_logic;
- signal baCnt : unsigned(2 downto 0);
-
- signal baChars : std_logic;
- signal baSprite04 : std_logic;
- signal baSprite15 : std_logic;
- signal baSprite26 : std_logic;
- signal baSprite37 : std_logic;
-
--- Memory refresh cycles
- signal refreshCounter : unsigned(7 downto 0);
-
--- User registers
- signal MX : MXdef; -- Sprite X
- signal MY : MYdef; -- Sprite Y
- signal ME : unsigned(7 downto 0); -- Sprite enable
- signal MXE : unsigned(7 downto 0); -- Sprite X expansion
- signal MYE : unsigned(7 downto 0); -- Sprite Y expansion
- signal MPRIO : unsigned(7 downto 0); -- Sprite priority
- signal MC : unsigned(7 downto 0); -- sprite multi color
-
- -- !!! Krestage 3 hacks
- signal MCDelay : unsigned(7 downto 0); -- sprite multi color
-
- -- mode
- signal BMM: std_logic; -- Bitmap mode
- signal ECM: std_logic; -- Extended color mode
- signal MCM: std_logic; -- Multi color mode
- signal DEN: std_logic; -- DMA enable
- signal RSEL: std_logic; -- Visible rows selection (24/25)
- signal CSEL: std_logic; -- Visible columns selection (38/40)
-
- signal RES: std_logic;
-
- signal VM: unsigned(13 downto 10);
- signal CB: unsigned(13 downto 11);
-
- signal EC : ColorDef; -- border color
- signal B0C : ColorDef; -- background color 0
- signal B1C : ColorDef; -- background color 1
- signal B2C : ColorDef; -- background color 2
- signal B3C : ColorDef; -- background color 3
- signal MM0 : ColorDef; -- sprite multicolor 0
- signal MM1 : ColorDef; -- sprite multicolor 1
- signal spriteColors: spriteColorsDef;
-
--- borders and blanking
- signal LRBorder: std_logic;
- signal TBBorder: std_logic;
- signal hBlack: std_logic;
- signal vBlanking : std_logic;
- signal hBlanking : std_logic;
- signal xscroll: unsigned(2 downto 0);
- signal yscroll: unsigned(2 downto 0);
- signal rasterCmp : unsigned(8 downto 0);
-
--- Address generator
- signal vicAddrReg : unsigned(13 downto 0);
- signal vicAddrLoc : unsigned(13 downto 0);
-
--- Address counters
- signal ColCounter: unsigned(9 downto 0) := (others => '0');
- signal ColRestart: unsigned(9 downto 0) := (others => '0');
- signal RowCounter: unsigned(2 downto 0) := (others => '0');
-
--- IRQ Registers
- signal IRST: std_logic := '0';
- signal ERST: std_logic := '0';
- signal IMBC: std_logic := '0';
- signal EMBC: std_logic := '0';
- signal IMMC: std_logic := '0';
- signal EMMC: std_logic := '0';
- signal ILP: std_logic := '0';
- signal ELP: std_logic := '0';
- signal IRQ: std_logic;
-
--- Collision detection registers
- signal M2M: unsigned(7 downto 0); -- Sprite to sprite collision
- signal M2D: unsigned(7 downto 0); -- Sprite to character collision
- signal M2Mhit : std_logic;
- signal M2Dhit : std_logic;
-
--- Raster counters
- signal rasterX : unsigned(9 downto 0) := (others => '0');
- signal rasterY : unsigned(8 downto 0) := (others => '0');
-
--- Light pen
- signal lightPenHit: std_logic;
- signal lpX : unsigned(7 downto 0);
- signal lpY : unsigned(7 downto 0);
-
--- IRQ Resets
- signal resetLightPenIrq: std_logic;
- signal resetIMMC : std_logic;
- signal resetIMBC : std_logic;
- signal resetRasterIrq : std_logic;
-
--- Character generation
- signal charStore: charStoreDef;
- signal nextChar : unsigned(11 downto 0);
- -- Char/Pixels just coming from memory
- signal readChar : unsigned(11 downto 0);
- signal readPixels : unsigned(7 downto 0);
- -- Char/Pixels pair waiting to be shifted
- signal waitingChar : unsigned(11 downto 0);
- signal waitingPixels : unsigned(7 downto 0);
- -- Stores colorinfo and the Pixels that are currently in shift register
- signal shiftingChar : unsigned(11 downto 0);
- signal shiftingPixels : unsigned(7 downto 0);
- signal shifting_ff : std_logic; -- Multicolor shift-regiter status bit.
-
--- Sprite work registers
- signal MPtr : unsigned(7 downto 0); -- sprite base pointer
- signal MPixels : MPixelsDef; -- Sprite 24 bit shift register
- signal MActive : MFlags; -- Sprite is active (derived from MCnt)
- signal MCnt : MCntDef;
- signal MXE_ff : unsigned(7 downto 0); -- Sprite X expansion flipflop
- signal MYE_ff : unsigned(7 downto 0); -- Sprite Y expansion flipflop
- signal MC_ff : unsigned(7 downto 0); -- controls sprite shift-register in multicolor
- signal MShift : MFlags; -- Sprite is shifting
- signal MCurrentPixel : MCurrentPixelDef;
-
--- Current colors and pixels
- signal pixelColor: ColorDef;
- signal pixelBgFlag: std_logic; -- For collision detection
- signal pixelDelay: pixelColorStoreDef;
-
--- Read/Write lines
- signal myWr : std_logic;
- signal myRd : std_logic;
-
-begin
--- -----------------------------------------------------------------------
--- Ouput signals
--- -----------------------------------------------------------------------
- ba <= baLoc;
- vicAddr <= vicAddrReg when registeredAddress else vicAddrLoc;
- hSync <= hBlanking;
- vSync <= vBlanking;
- irq_n <= not IRQ;
-
--- -----------------------------------------------------------------------
--- chip-select signals
--- -----------------------------------------------------------------------
- myWr <= cs and we;
- myRd <= cs and rd;
-
--- -----------------------------------------------------------------------
--- debug signals
--- -----------------------------------------------------------------------
- debugX <= rasterX;
- debugY <= rasterY;
-
--- -----------------------------------------------------------------------
--- Badline condition
--- -----------------------------------------------------------------------
- process(rasterY, yscroll, rasterEnable)
- begin
- badLine <= false;
- if (rasterY(2 downto 0) = yscroll)
- and (rasterEnable = '1') then
- badLine <= true;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- BA=low counter
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if baLoc = '0' then
- if phi = '0'
- and enaData = '1'
- and baCnt(2) = '0' then
- baCnt <= baCnt + 1;
- end if;
- else
- baCnt <= (others => '0');
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Calculate lastLineFlag
--- -----------------------------------------------------------------------
- process(clk)
- variable rasterLines : integer range 0 to 312;
- begin
- if rising_edge(clk) then
- lastLineFlag <= false;
-
- rasterLines := 311; -- PAL
- if mode6567old = '1' then
- rasterLines := 261; -- NTSC (R7 and earlier have 262 lines)
- end if;
- if mode6567R8 = '1' then
- rasterLines := 262; -- NTSC (R8 and newer have 263 lines)
- end if;
- if rasterY = rasterLines then
- lastLineFlag <= true;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- State machine
--- -----------------------------------------------------------------------
-vicStateMachine: process(clk)
- begin
- if rising_edge(clk) then
- if enaData = '1'
- and baSync = '0' then
- if phi = '0' then
- case vicCycle is
- when cycleRefresh1 =>
- vicCycle <= cycleRefresh2;
- if ((mode6567old or mode6567R8) = '1') then
- vicCycle <= cycleIdle1;
- end if;
- when cycleIdle1 => vicCycle <= cycleRefresh2;
- when cycleRefresh2 => vicCycle <= cycleRefresh3;
- when cycleRefresh3 => vicCycle <= cycleRefresh4;
- when cycleRefresh4 => vicCycle <= cycleRefresh5; -- X=0..7 on this cycle
- when cycleRefresh5 => vicCycle <= cycleChar;
- when cycleChar =>
- if ((mode6569 = '1') and rasterX(9 downto 3) = "0100111") -- PAL
- or ((mode6567old = '1') and rasterX(9 downto 3) = "0100111") -- Old NTSC
- or ((mode6567R8 = '1') and rasterX(9 downto 3) = "0101000") -- New NTSC
- or ((mode6572 = '1') and rasterX(9 downto 3) = "0101000") then -- PAL-N
- vicCycle <= cycleCalcSprites;
- end if;
- when cycleCalcSprites => vicCycle <= cycleSpriteBa1;
- when cycleSpriteBa1 => vicCycle <= cycleSpriteBa2;
- when cycleSpriteBa2 => vicCycle <= cycleSpriteBa3;
- when others =>
- null;
- end case;
- else
- case vicCycle is
- when cycleSpriteBa3 => vicCycle <= cycleSpriteA;
- when cycleSpriteA =>
- vicCycle <= cycleSpriteB;
- when cycleSpriteB =>
- vicCycle <= cycleSpriteA;
- if sprite = 7 then
- vicCycle <= cycleRefresh1;
- end if;
- when others =>
- null;
- end case;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Iterate through all sprites.
--- Only used when state-machine above is in any sprite cycles.
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if phi = '1'
- and enaData = '1'
- and vicCycle = cycleSpriteB
- and baSync = '0' then
- sprite <= sprite + 1;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Address generator
--- -----------------------------------------------------------------------
- process(phi, vicCycle, sprite, shiftChars, idle,
- VM, CB, ECM, BMM, nextChar, colCounter, rowCounter, MPtr, MCnt)
- begin
- --
- -- Default case ($3FFF fetches)
- vicAddrLoc <= (others => '1');
- if (idle = '0')
- and shiftChars then
- if BMM = '1' then
- vicAddrLoc <= CB(13) & colCounter & rowCounter;
- else
- vicAddrLoc <= CB & nextChar(7 downto 0) & rowCounter;
- end if;
- end if;
- if ECM = '1' then
- vicAddrLoc(10 downto 9) <= "00";
- end if;
-
- case vicCycle is
- when cycleRefresh1 | cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 =>
- if emulateRefresh then
- vicAddrLoc <= "111111" & refreshCounter;
- else
- vicAddrLoc <= (others => '-');
- end if;
- when cycleSpriteBa1 | cycleSpriteBa2 | cycleSpriteBa3 =>
- vicAddrLoc <= (others => '1');
- when cycleSpriteA =>
- vicAddrLoc <= VM & "1111111" & sprite;
- if phi = '1' then
- vicAddrLoc <= MPtr & MCnt(to_integer(sprite));
- end if;
- when cycleSpriteB =>
- vicAddrLoc <= MPtr & MCnt(to_integer(sprite));
- when others =>
- if phi = '1' then
- vicAddrLoc <= VM & colCounter;
- end if;
- end case;
- end process;
-
- -- Registered address
- process(clk)
- begin
- if rising_edge(clk) then
- vicAddrReg <= vicAddrLoc;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Character storage
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if enaData = '1'
- and shiftChars
- and phi = '1' then
- if badLine then
- nextChar(7 downto 0) <= datai;
- nextChar(11 downto 8) <= diColor;
- else
- nextChar <= charStore(38);
- end if;
- charStore <= charStore(37 downto 0) & nextChar;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Sprite base pointer (MPtr)
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if phi = '0'
- and enaData = '1'
- and vicCycle = cycleSpriteA then
- MPtr <= (others => '1');
- if MActive(to_integer(sprite)) then
- MPtr <= datai;
- end if;
-
- -- If refresh counter is not emulated we don't care about
- -- MPtr having the correct value in idle state.
- if not emulateRefresh then
- MPtr <= datai;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Refresh counter
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- vicRefresh <= '0';
- case vicCycle is
- when cycleRefresh1 | cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 =>
- vicRefresh <= '1';
- if phi = '0'
- and enaData = '1'
- and baSync = '0' then
- refreshCounter <= refreshCounter - 1;
- end if;
- when others =>
- null;
- end case;
- if lastLineFlag then
- refreshCounter <= (others => '1');
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Generate Raster Enable
--- -----------------------------------------------------------------------
- process(clk)
- begin
- -- Enable screen and character display.
- -- This is only possible in line 48 on the VIC-II.
- -- On other lines any DEN changes are ignored.
- if rising_edge(clk) then
- if (rasterY = 48) and (DEN = '1') then
- rasterEnable <= '1';
- end if;
- if (rasterY = 248) then
- rasterEnable <= '0';
- end if;
- end if;
- end process;
-
-
--- -----------------------------------------------------------------------
--- BA generator (Text/Bitmap)
--- -----------------------------------------------------------------------
---
--- For Text/Bitmap BA goes low 3 cycles before real access. So BA starts
--- going low during refresh2 state. See diagram below for timing:
---
--- X 0 0 0 0 0
--- 0 0 0 0 1
--- 0 4 8 C 0
---
--- phi ___ ___ ___ ___ ___ ___ ___ ___...
--- ___ ___ ___ ___ ___ ___ ___ ...
---
--- | | | | | | |...
--- rfr2 rfr3 rfr4 rfr5 char1 char2 char3
---
--- BA _______
--- \\\_______________________________________
--- | 1 | 2 | 3 |
---
--- BACnt 000 001 | 010 | 011 | 100 100 100 ...
---
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if phi = '0' then
- baChars <= '1';
- case vicCycle is
- when cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 =>
- if badLine then
- baChars <= '0';
- end if;
- when others =>
- if rasterX(9 downto 3) < "0101000"
- and badLine then
- baChars <= '0';
- end if;
- end case;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- BA generator (Sprites)
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if phi = '0' then
- if sprite = 1 then
- baSprite04 <= '1';
- end if;
- if sprite = 2 then
- baSprite15 <= '1';
- end if;
- if sprite = 3 then
- baSprite26 <= '1';
- end if;
- if sprite = 4 then
- baSprite37 <= '1';
- end if;
- if sprite = 5 then
- baSprite04 <= '1';
- end if;
- if sprite = 6 then
- baSprite15 <= '1';
- end if;
- if sprite = 7 then
- baSprite26 <= '1';
- end if;
- if vicCycle = cycleRefresh1 then
- baSprite37 <= '1';
- end if;
-
- if MActive(0) and (vicCycle = cycleCalcSprites) then
- baSprite04 <= '0';
- end if;
- if MActive(1) and (vicCycle = cycleSpriteBa2) then
- baSprite15 <= '0';
- end if;
- if MActive(2) and (vicCycle = cycleSpriteB) and (sprite = 0) then
- baSprite26 <= '0';
- end if;
- if MActive(3) and (vicCycle = cycleSpriteB) and (sprite = 1) then
- baSprite37 <= '0';
- end if;
- if MActive(4) and (vicCycle = cycleSpriteB) and (sprite = 2) then
- baSprite04 <= '0';
- end if;
- if MActive(5) and (vicCycle = cycleSpriteB) and (sprite = 3) then
- baSprite15 <= '0';
- end if;
- if MActive(6) and (vicCycle = cycleSpriteB) and (sprite = 4) then
- baSprite26 <= '0';
- end if;
- if MActive(7) and (vicCycle = cycleSpriteB) and (sprite = 5) then
- baSprite37 <= '0';
- end if;
- end if;
- end if;
- end process;
- baLoc <= baChars and baSprite04 and baSprite15 and baSprite26 and baSprite37;
-
--- -----------------------------------------------------------------------
--- Address valid?
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- addrValid <= '0';
- if phi = '0'
- or baCnt(2) = '1' then
- addrValid <= '1';
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Generate ShiftChars flag
--- -----------------------------------------------------------------------
- process(rasterX)
- begin
- shiftChars <= false;
- if rasterX(9 downto 3) > "0000000"
- and rasterX(9 downto 3) < "0101001" then
- shiftChars <= true;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- RowCounter and ColCounter
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if phi = '0'
- and enaData = '1'
- and baSync = '0' then
- if shiftChars
- and idle = '0' then
- colCounter <= colCounter + 1;
- end if;
- case vicCycle is
- when cycleRefresh4 =>
- colCounter <= colRestart;
- if badline then
- rowCounter <= (others => '0');
- end if;
- when cycleSpriteA =>
- if sprite = "000" then
- if rowCounter = 7 then
- colRestart <= colCounter;
- idle <= '1';
- else
- rowCounter <= rowCounter + 1;
- end if;
- if badline then
- rowCounter <= rowCounter + 1;
- end if;
- end if;
- when others =>
- null;
- end case;
- if lastLineFlag then
- -- Reset column counter outside visible range.
- colRestart <= (others => '0');
- end if;
-
- -- Set display mode (leave idle-mode) as soon as
- -- there is a badline condition.
- if badline then
- idle <= '0';
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- X/Y Raster counter
--- -----------------------------------------------------------------------
-rasterCounters: process(clk)
- begin
- if rising_edge(clk) then
- if enaPixel = '1' then
- rasterX(2 downto 0) <= rasterX(2 downto 0) + 1;
- end if;
- if phi = '0'
- and enaData = '1'
- and baSync = '0' then
- rasterX(9 downto 3) <= rasterX(9 downto 3) + 1;
- rasterX(2 downto 0) <= (others => '0');
- if vicCycle = cycleRefresh4 then
- rasterX <= (others => '0');
- end if;
- end if;
- if phi = '1'
- and enaData = '1'
- and baSync = '0' then
- beyondFrameFlag <= false;
- if (vicCycle = cycleSpriteB)
- and (sprite = 2) then
- rasterY <= rasterY + 1;
- beyondFrameFlag <= lastLineFlag;
- end if;
- if beyondFrameFlag then
- rasterY <= (others => '0');
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Raster IRQ
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if phi = '1'
- and enaData = '1'
- and baSync = '0'
- and (vicCycle = cycleSpriteB)
- and (sprite = 2) then
- rasterIrqDone <= '0';
- end if;
- if resetRasterIrq = '1' then
- IRST <= '0';
- end if;
- if (rasterIrqDone = '0')
- and (rasterY = rasterCmp) then
- rasterIrqDone <= '1';
- IRST <= '1';
- end if;
- end if;
- end process;
-
-
--- -----------------------------------------------------------------------
--- Light pen
--- -----------------------------------------------------------------------
--- On a negative edge on the LP input, the current position of the raster beam
--- is latched in the registers LPX ($d013) and LPY ($d014). LPX contains the
--- upper 8 bits (of 9) of the X position and LPY the lower 8 bits (likewise of
--- 9) of the Y position. So the horizontal resolution of the light pen is
--- limited to 2 pixels.
-
--- Only one negative edge on LP is recognized per frame. If multiple edges
--- occur on LP, all following ones are ignored. The trigger is not released
--- until the next vertical blanking interval.
--- -----------------------------------------------------------------------
-lightPen: process(clk)
- begin
- if rising_edge(clk) then
- if emulateLightpen then
- if resetLightPenIrq = '1' then
- -- Reset light pen interrupt
- ILP <= '0';
- end if;
- if lastLineFlag then
- -- Reset lightpen state at beginning of frame
- lightPenHit <= '0';
- elsif (lightPenHit = '0') and (lp_n = '0') then
- -- One hit/frame
- lightPenHit <= '1';
- -- Toggle Interrupt
- ILP <= '1';
- -- Store position of beam
- lpx <= rasterX(8 downto 1);
- lpy <= rasterY(7 downto 0);
- end if;
- else
- ILP <= '0';
- lpx <= (others => '1');
- lpy <= (others => '1');
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- VSync
--- -----------------------------------------------------------------------
-doVBlanking: process(clk, mode6569, mode6567old, mode6567R8)
- variable rasterBlank : integer range 0 to 300;
- begin
- rasterBlank := 300;
- if (mode6567old or mode6567R8) = '1' then
- rasterBlank := 12;
- end if;
- if rising_edge(clk) then
- vBlanking <= '0';
- if rasterY = rasterBlank then
- vBlanking <= '1';
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- HSync
--- -----------------------------------------------------------------------
-doHBlanking: process(clk)
- begin
- if rising_edge(clk) then
- if sprite = 3 then
- hBlack <= '1';
- end if;
- if vicCycle = cycleRefresh1 then
- hBlack <= '0';
- end if;
- if sprite = 3 then -- dar 5 then
- hBlanking <= '1';
- else
- hBlanking <= '0';
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Borders
--- -----------------------------------------------------------------------
-calcBorders: process(clk)
- variable newTBBorder: std_logic;
- begin
- if rising_edge(clk) then
- if enaPixel = '1' then
- --
- -- Calc top/bottom border
- newTBBorder := TBBorder;
--- if (rasterY = 55) and (RSEL = '0') and (rasterEnable = '1') then
- if (rasterY = 55) and (rasterEnable = '1') then
- newTBBorder := '0';
- end if;
- if (rasterY = 51) and (RSEL = '1') and (rasterEnable = '1') then
- newTBBorder := '0';
- end if;
- if (rasterY = 247) and (RSEL = '0') then
- newTBBorder := '1';
- end if;
- if (rasterY = 251) and (RSEL = '1') then
- newTBBorder := '1';
- end if;
-
- --
- -- Calc left/right border
- if (rasterX = (31+1)) and (CSEL = '0') then
- LRBorder <= newTBBorder;
- TBBorder <= newTBBorder;
- end if;
- if (rasterX = (24+1)) and (CSEL = '1') then
- LRBorder <= newTBBorder;
- TBBorder <= newTBBorder;
- end if;
- if (rasterX = (335+1)) and (CSEL = '0') then
- LRBorder <= '1';
- end if;
- if (rasterX = (344+1)) and (CSEL = '1') then
- LRBorder <= '1';
- end if;
- end if;
- end if;
- end process;
-
-
--- -----------------------------------------------------------------------
--- Pixel generator for Text/Bitmap screen
--- -----------------------------------------------------------------------
-calcBitmap: process(clk)
- variable multiColor : std_logic;
- begin
- if rising_edge(clk) then
- if enaPixel = '1' then
- --
- -- Toggle flipflop for multicolor 2-bits shift.
- shifting_ff <= not shifting_ff;
-
- --
- -- Multicolor mode is active with MCM, but for character
- -- mode it depends on bit3 of color ram too.
- multiColor := MCM and (BMM or ECM or shiftingChar(11));
-
- --
- -- Reload shift register when xscroll=rasterX
- -- otherwise shift pixels
- if xscroll = rasterX(2 downto 0) then
- shifting_ff <= '0';
- shiftingChar <= waitingChar;
- shiftingPixels <= waitingPixels;
- elsif multiColor = '0' then
- shiftingPixels <= shiftingPixels(6 downto 0) & '0';
- elsif shifting_ff = '1' then
- shiftingPixels <= shiftingPixels(5 downto 0) & "00";
- end if;
-
- --
- -- Calculate if pixel is in foreground or background
- pixelBgFlag <= shiftingPixels(7);
-
- --
- -- Calculate color of next pixel
- pixelColor <= B0C;
- if (BMM = '0') and (ECM='0') then
- if (multiColor = '0') then
- -- normal character mode
- if shiftingPixels(7) = '1' then
- pixelColor <= shiftingChar(11 downto 8);
- end if;
- else
- -- multi-color character mode
- case shiftingPixels(7 downto 6) is
- when "01" => pixelColor <= B1C;
- when "10" => pixelColor <= B2C;
- when "11" => pixelColor <= '0' & shiftingChar(10 downto 8);
- when others => null;
- end case;
- end if;
- elsif (MCM = '0') and (BMM = '0') and (ECM='1') then
- -- extended-color character mode
- -- multiple background colors but only 64 characters
- if shiftingPixels(7) = '1' then
- pixelColor <= shiftingChar(11 downto 8);
- else
- case shiftingChar(7 downto 6) is
- when "01" => pixelColor <= B1C;
- when "10" => pixelColor <= B2C;
- when "11" => pixelColor <= B3C;
- when others => null;
- end case;
- end if;
- elsif emulateGraphics and (MCM = '0') and (BMM = '1') and (ECM='0') then
- -- highres bitmap mode
- if shiftingPixels(7) = '1' then
- pixelColor <= shiftingChar(7 downto 4);
- else
- pixelColor <= shiftingChar(3 downto 0);
- end if;
- elsif emulateGraphics and (MCM = '1') and (BMM = '1') and (ECM='0') then
- -- Multi-color bitmap mode
- case shiftingPixels(7 downto 6) is
- when "01" => pixelColor <= shiftingChar(7 downto 4);
- when "10" => pixelColor <= shiftingChar(3 downto 0);
- when "11" => pixelColor <= shiftingChar(11 downto 8);
- when others => null;
- end case;
- else
- -- illegal display mode, the output is black
- pixelColor <= "0000";
- end if;
- end if;
-
- --
- -- Store fetched pixels, until current pixels are displayed
- -- and shift-register is empty.
- if enaData = '1'
- and phi = '0' then
- readPixels <= (others => '0');
- if shiftChars then
- readPixels <= datai;
- readChar <= (others => '0');
- if idle = '0' then
- readChar <= nextChar;
- end if;
- end if;
- -- Store the characters until shiftregister is empty
- waitingPixels <= readPixels;
- waitingChar <= readChar;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Which sprites are active?
--- -----------------------------------------------------------------------
- process(MCnt)
- begin
- for i in 0 to 7 loop
- MActive(i) <= false;
- if MCnt(i) /= 63 then
- MActive(i) <= true;
- end if;
- end loop;
- end process;
-
--- -----------------------------------------------------------------------
--- Sprite byte counter
--- Y expansion flipflop
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if phi = '0'
- and enaData = '1' then
- case vicCycle is
- when cycleRefresh5 =>
- for i in 0 to 7 loop
- MYE_ff(i) <= not MYE_ff(i);
- if MActive(i) then
- if MYE_ff(i) = MYE(i) then
- MCnt(i) <= MCnt(i) + 1;
- else
- MCnt(i) <= MCnt(i) - 2;
- end if;
- end if;
- end loop;
- when others =>
- null;
- end case;
- end if;
- for i in 0 to 7 loop
- if MYE(i) = '0'
- or not MActive(i) then
- MYE_ff(i) <= '0';
- end if;
- end loop;
-
- --
- -- On cycleCalcSprite check for each inactive sprite if
- -- there is a Y match. Reset MCnt if this is so.
- --
- -- The RasterX counter is used here to multiplex the compare logic.
- -- This saves a few logic cells in the FPGA.
- if vicCycle = cycleCalcSprites then
- if (not MActive(to_integer(RasterX(2 downto 0))))
- and (ME(to_integer(RasterX(2 downto 0))) = '1')
- and (rasterY(7 downto 0) = MY(to_integer(RasterX(2 downto 0)))) then
- MCnt(to_integer(RasterX(2 downto 0))) <= (others => '0');
- end if;
- end if;
- --
- -- Original non-multiplexed version
--- if vicCycle = cycleCalcSprites then
--- for i in 0 to 7 loop
--- if (not MActive(i))
--- and (ME(i) = '1')
--- and (rasterY(7 downto 0) = MY(i)) then
--- MCnt(i) <= (others => '0');
--- end if;
--- end loop;
--- end if;
-
- --
- -- Increment MCnt after fetching data.
- if enaData = '1' then
- if (vicCycle = cycleSpriteA and phi = '1')
- or (vicCycle = cycleSpriteB and phi = '0') then
- if MActive(to_integer(sprite)) then
- MCnt(to_integer(sprite)) <= MCnt(to_integer(sprite)) + 1;
- end if;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Sprite pixel Shift register
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if enaPixel = '1' then
- -- Enable sprites on the correct X position
- for i in 0 to 7 loop
- if rasterX = MX(i) then
- MShift(i) <= true;
- end if;
- end loop;
-
- -- Shift one pixel of the sprite from the shift register.
- for i in 0 to 7 loop
- if MShift(i) then
- MXE_ff(i) <= (not MXE_ff(i)) and MXE(i);
- if MXE_ff(i) = '0' then
- MC_ff(i) <= (not MC_ff(i)) and MC(i);
- if MC_ff(i) = '0' then
- MCurrentPixel(i) <= MPixels(i)(23 downto 22);
- end if;
- MPixels(i) <= MPixels(i)(22 downto 0) & '0';
- end if;
- else
- MXE_ff(i) <= '0';
- MC_ff(i) <= '0';
- MCurrentPixel(i) <= "00";
- end if;
- end loop;
- end if;
-
- --
- -- Fill Sprite shift-register with new data.
- if enaData = '1' then
- if phi = '0'
- and vicCycle = cycleSpriteA then
- MShift(to_integer(sprite)) <= false;
- end if;
-
- if Mactive(to_integer(sprite)) then
- if phi = '0' then
- case vicCycle is
- when cycleSpriteB =>
- MPixels(to_integer(sprite)) <= MPixels(to_integer(sprite))(15 downto 0) & datai;
- when others => null;
- end case;
- else
- case vicCycle is
- when cycleSpriteA | cycleSpriteB =>
- MPixels(to_integer(sprite)) <= MPixels(to_integer(sprite))(15 downto 0) & datai;
- when others => null;
- end case;
- end if;
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Video output
--- -----------------------------------------------------------------------
- process(clk)
- variable myColor: unsigned(3 downto 0);
- variable muxSprite : unsigned(2 downto 0);
- variable muxColor : unsigned(1 downto 0);
- -- 00 = pixels
- -- 01 = MM0
- -- 10 = Sprite
- -- 11 = MM1
- begin
- if rising_edge(clk) then
- muxColor := "00";
- muxSprite := (others => '-');
- for i in 7 downto 0 loop
- if (MPRIO(i) = '0') or (pixelBgFlag = '0') then
- if MC(i) = '1' then
- if MCurrentPixel(i) /= "00" then
- muxColor := MCurrentPixel(i);
- muxSprite := to_unsigned(i, 3);
- end if;
- elsif MCurrentPixel(i)(1) = '1' then
- muxColor := "10";
- muxSprite := to_unsigned(i, 3);
- end if;
- end if;
- end loop;
-
- myColor := pixelColor;
- case muxColor is
- when "01" => myColor := MM0;
- when "10" => myColor := spriteColors(to_integer(muxSprite));
- when "11" => myColor := MM1;
- when others =>
- null;
- end case;
-
-
--- myColor := pixelColor;
--- for i in 7 downto 0 loop
--- if (MPRIO(i) = '0') or (pixelBgFlag = '0') then
--- if MC(i) = '1' then
--- case MCurrentPixel(i) is
--- when "01" => myColor := MM0;
--- when "10" => myColor := spriteColors(i);
--- when "11" => myColor := MM1;
--- when others => null;
--- end case;
--- elsif MCurrentPixel(i)(1) = '1' then
--- myColor := spriteColors(i);
--- end if;
--- end if;
--- end loop;
-
- if enaPixel = '1' then
- colorIndex <= myColor;
-
--- Krestage 3 debugging routine
--- if (cs = '1' and aRegisters = "011100") then
--- colorIndex <= "1111";
--- end if;
- if (LRBorder = '1') or (TBBorder = '1') then
- colorIndex <= EC;
- end if;
- if (hBlack = '1') then
- colorIndex <= (others => '0');
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Sprite to sprite collision
--- -----------------------------------------------------------------------
-spriteSpriteCollision: process(clk)
- variable collision : unsigned(7 downto 0);
- begin
- if rising_edge(clk) then
- if resetIMMC = '1' then
- IMMC <= '0';
- end if;
-
- if (myRd = '1')
- and (aRegisters = "011110") then
- M2M <= (others => '0');
- M2Mhit <= '0';
- end if;
-
- for i in 0 to 7 loop
- collision(i) := MCurrentPixel(i)(1);
- end loop;
- if (collision /= "00000000")
- and (collision /= "00000001")
- and (collision /= "00000010")
- and (collision /= "00000100")
- and (collision /= "00001000")
- and (collision /= "00010000")
- and (collision /= "00100000")
- and (collision /= "01000000")
- and (collision /= "10000000")
- and (TBBorder = '0') then
- M2M <= M2M or collision;
-
- -- Give collision interrupt but only once until clear of register
- if M2Mhit = '0' then
- IMMC <= '1';
- M2Mhit <= '1';
- end if;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Sprite to background collision
--- -----------------------------------------------------------------------
-spriteBackgroundCollision: process(clk)
- begin
- if rising_edge(clk) then
- if resetIMBC = '1' then
- IMBC <= '0';
- end if;
-
- if (myRd = '1')
- and (aRegisters = "011111") then
- M2D <= (others => '0');
- M2Dhit <= '0';
- end if;
-
- for i in 0 to 7 loop
- if MCurrentPixel(i)(1) = '1'
- and pixelBgFlag = '1'
- and (TBBorder = '0') then
- M2D(i) <= '1';
-
- -- Give collision interrupt but only once until clear of register
- if M2Dhit = '0' then
- IMBC <= '1';
- M2Dhit <= '1';
- end if;
- end if;
- end loop;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Generate IRQ signal
--- -----------------------------------------------------------------------
- IRQ <= (ILP and ELP) or (IMMC and EMMC) or (IMBC and EMBC) or (IRST and ERST);
-
--- -----------------------------------------------------------------------
--- Krestage 3 hack
--- -----------------------------------------------------------------------
- process(clk)
- begin
- if rising_edge(clk) then
- if phi = '1'
- and enaData = '1' then
- MC <= MCDelay;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Write registers
--- -----------------------------------------------------------------------
-writeRegisters: process(clk)
- begin
- if rising_edge(clk) then
- resetLightPenIrq <= '0';
- resetIMMC <= '0';
- resetIMBC <= '0';
- resetRasterIrq <= '0';
-
- --
- -- write to registers
- if(reset = '1') then
- MX(0) <= (others => '0');
- MX(1) <= (others => '0');
- MX(2) <= (others => '0');
- MX(3) <= (others => '0');
- MX(4) <= (others => '0');
- MX(5) <= (others => '0');
- MX(6) <= (others => '0');
- MX(7) <= (others => '0');
- rasterCmp <= (others => '0');
- ECM <= '0';
- BMM <= '0';
- DEN <= '0';
- RSEL <= '0';
- yscroll <= (others => '0');
- ME <= (others => '0');
- RES <= '0';
- MCM <= '0';
- CSEL <= '0';
- xscroll <= (others => '0');
- MYE <= (others => '0');
- VM <= (others => '0');
- CB <= (others => '0');
- resetLightPenIrq <= '0';
- resetIMMC <= '0';
- resetIMBC <= '0';
- resetRasterIrq <= '0';
- ELP <= '0';
- EMMC <= '0';
- EMBC <= '0';
- ERST <= '0';
- MPRIO <= (others => '0');
- MCDelay <= (others => '0');
- MXE <= (others => '0');
- EC <= (others => '0');
- B0C <= (others => '0');
- B1C <= (others => '0');
- B2C <=(others => '0');
- B3C <= (others => '0');
- MM0 <= (others => '0');
- MM1 <= (others => '0');
- spriteColors(0) <= (others => '0');
- spriteColors(1) <= (others => '0');
- spriteColors(2) <= (others => '0');
- spriteColors(3) <= (others => '0');
- spriteColors(4) <= (others => '0');
- spriteColors(5) <= (others => '0');
- spriteColors(6) <= (others => '0');
- spriteColors(7) <= (others => '0');
-
- elsif (myWr = '1') then
- case aRegisters is
- when "000000" => MX(0)(7 downto 0) <= diRegisters;
- when "000001" => MY(0) <= diRegisters;
- when "000010" => MX(1)(7 downto 0) <= diRegisters;
- when "000011" => MY(1) <= diRegisters;
- when "000100" => MX(2)(7 downto 0) <= diRegisters;
- when "000101" => MY(2) <= diRegisters;
- when "000110" => MX(3)(7 downto 0) <= diRegisters;
- when "000111" => MY(3) <= diRegisters;
- when "001000" => MX(4)(7 downto 0) <= diRegisters;
- when "001001" => MY(4) <= diRegisters;
- when "001010" => MX(5)(7 downto 0) <= diRegisters;
- when "001011" => MY(5) <= diRegisters;
- when "001100" => MX(6)(7 downto 0) <= diRegisters;
- when "001101" => MY(6) <= diRegisters;
- when "001110" => MX(7)(7 downto 0) <= diRegisters;
- when "001111" => MY(7) <= diRegisters;
- when "010000" =>
- MX(0)(8) <= diRegisters(0);
- MX(1)(8) <= diRegisters(1);
- MX(2)(8) <= diRegisters(2);
- MX(3)(8) <= diRegisters(3);
- MX(4)(8) <= diRegisters(4);
- MX(5)(8) <= diRegisters(5);
- MX(6)(8) <= diRegisters(6);
- MX(7)(8) <= diRegisters(7);
- when "010001" =>
- rasterCmp(8) <= diRegisters(7);
- ECM <= diRegisters(6);
- BMM <= diRegisters(5);
- DEN <= diRegisters(4);
- RSEL <= diRegisters(3);
- yscroll <= diRegisters(2 downto 0);
- when "010010" =>
- rasterCmp(7 downto 0) <= diRegisters;
- when "010101" =>
- ME <= diRegisters;
- when "010110" =>
- RES <= diRegisters(5);
- MCM <= diRegisters(4);
- CSEL <= diRegisters(3);
- xscroll <= diRegisters(2 downto 0);
-
- when "010111" => MYE <= diRegisters;
- when "011000" =>
- VM <= diRegisters(7 downto 4);
- CB <= diRegisters(3 downto 1);
- when "011001" =>
- resetLightPenIrq <= diRegisters(3);
- resetIMMC <= diRegisters(2);
- resetIMBC <= diRegisters(1);
- resetRasterIrq <= diRegisters(0);
- when "011010" =>
- ELP <= diRegisters(3);
- EMMC <= diRegisters(2);
- EMBC <= diRegisters(1);
- ERST <= diRegisters(0);
- when "011011" => MPRIO <= diRegisters;
- when "011100" =>
- -- MC <= diRegisters;
- MCDelay <= diRegisters; -- !!! Krestage 3 hack
- when "011101" => MXE <= diRegisters;
- when "100000" => EC <= diRegisters(3 downto 0);
- when "100001" => B0C <= diRegisters(3 downto 0);
- when "100010" => B1C <= diRegisters(3 downto 0);
- when "100011" => B2C <= diRegisters(3 downto 0);
- when "100100" => B3C <= diRegisters(3 downto 0);
- when "100101" => MM0 <= diRegisters(3 downto 0);
- when "100110" => MM1 <= diRegisters(3 downto 0);
- when "100111" => spriteColors(0) <= diRegisters(3 downto 0);
- when "101000" => spriteColors(1) <= diRegisters(3 downto 0);
- when "101001" => spriteColors(2) <= diRegisters(3 downto 0);
- when "101010" => spriteColors(3) <= diRegisters(3 downto 0);
- when "101011" => spriteColors(4) <= diRegisters(3 downto 0);
- when "101100" => spriteColors(5) <= diRegisters(3 downto 0);
- when "101101" => spriteColors(6) <= diRegisters(3 downto 0);
- when "101110" => spriteColors(7) <= diRegisters(3 downto 0);
- when others => null;
- end case;
- end if;
- end if;
- end process;
-
--- -----------------------------------------------------------------------
--- Read registers
--- -----------------------------------------------------------------------
-readRegisters: process(clk)
- begin
- if rising_edge(clk) then
- case aRegisters is
- when "000000" => datao <= MX(0)(7 downto 0);
- when "000001" => datao <= MY(0);
- when "000010" => datao <= MX(1)(7 downto 0);
- when "000011" => datao <= MY(1);
- when "000100" => datao <= MX(2)(7 downto 0);
- when "000101" => datao <= MY(2);
- when "000110" => datao <= MX(3)(7 downto 0);
- when "000111" => datao <= MY(3);
- when "001000" => datao <= MX(4)(7 downto 0);
- when "001001" => datao <= MY(4);
- when "001010" => datao <= MX(5)(7 downto 0);
- when "001011" => datao <= MY(5);
- when "001100" => datao <= MX(6)(7 downto 0);
- when "001101" => datao <= MY(6);
- when "001110" => datao <= MX(7)(7 downto 0);
- when "001111" => datao <= MY(7);
- when "010000" =>
- datao <= MX(7)(8) & MX(6)(8) & MX(5)(8) & MX(4)(8)
- & MX(3)(8) & MX(2)(8) & MX(1)(8) & MX(0)(8);
- when "010001" => datao <= rasterY(8) & ECM & BMM & DEN & RSEL & yscroll;
- when "010010" => datao <= rasterY(7 downto 0);
- when "010011" => datao <= lpX;
- when "010100" => datao <= lpY;
- when "010101" => datao <= ME;
- when "010110" => datao <= "11" & RES & MCM & CSEL & xscroll;
- when "010111" => datao <= MYE;
- when "011000" => datao <= VM & CB & '1';
- when "011001" => datao <= IRQ & "111" & ILP & IMMC & IMBC & IRST;
- when "011010" => datao <= "1111" & ELP & EMMC & EMBC & ERST;
- when "011011" => datao <= MPRIO;
- when "011100" => datao <= MC;
- when "011101" => datao <= MXE;
- when "011110" => datao <= M2M;
- when "011111" => datao <= M2D;
- when "100000" => datao <= "1111" & EC;
- when "100001" => datao <= "1111" & B0C;
- when "100010" => datao <= "1111" & B1C;
- when "100011" => datao <= "1111" & B2C;
- when "100100" => datao <= "1111" & B3C;
- when "100101" => datao <= "1111" & MM0;
- when "100110" => datao <= "1111" & MM1;
- when "100111" => datao <= "1111" & spriteColors(0);
- when "101000" => datao <= "1111" & spriteColors(1);
- when "101001" => datao <= "1111" & spriteColors(2);
- when "101010" => datao <= "1111" & spriteColors(3);
- when "101011" => datao <= "1111" & spriteColors(4);
- when "101100" => datao <= "1111" & spriteColors(5);
- when "101101" => datao <= "1111" & spriteColors(6);
- when "101110" => datao <= "1111" & spriteColors(7);
- when others => datao <= (others => '1');
- end case;
- end if;
- end process;
-end architecture;
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/vic_656x_e.vhd b/Computer_MiST/Commodore - MAX_MiST/rtl/vic_656x_e.vhd
deleted file mode 100644
index 7e42eacc..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/vic_656x_e.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
--- -----------------------------------------------------------------------
---
--- FPGA 64
---
--- A fully functional commodore 64 implementation in a single FPGA
---
--- -----------------------------------------------------------------------
--- Peter Wendrich (pwsoft@syntiac.com)
--- http://www.syntiac.com/fpga64.html
--- -----------------------------------------------------------------------
---
--- VIC-II - Video Interface Chip no 2
---
--- -----------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
--- -----------------------------------------------------------------------
-
-entity vic_656x is
- generic (
- registeredAddress : boolean := false;
- emulateRefresh : boolean := false;
- emulateLightpen : boolean := false;
- emulateGraphics : boolean := true
- );
- port (
- clk: in std_logic;
- -- phi = 0 is VIC cycle
- -- phi = 1 is CPU cycle (only used by VIC when BA is low)
- phi : in std_logic;
- enaData : in std_logic;
- enaPixel : in std_logic;
-
- baSync : in std_logic;
- ba: out std_logic;
-
- mode6569 : in std_logic; -- PAL 63 cycles and 312 lines
- mode6567old : in std_logic; -- old NTSC 64 cycles and 262 line
- mode6567R8 : in std_logic; -- new NTSC 65 cycles and 263 line
- mode6572 : in std_logic; -- PAL-N 65 cycles and 312 lines
-
- reset : in std_logic;
- cs : in std_logic;
- we : in std_logic;
- rd : in std_logic;
- lp_n : in std_logic;
-
- aRegisters: in unsigned(5 downto 0);
- diRegisters: in unsigned(7 downto 0);
-
- datai: in unsigned(7 downto 0);
- diColor: in unsigned(3 downto 0);
- datao: out unsigned(7 downto 0);
-
- vicAddr: out unsigned(13 downto 0);
- irq_n: out std_logic;
-
- -- Video output
- hSync : out std_logic;
- vSync : out std_logic;
- colorIndex : out unsigned(3 downto 0);
-
- -- Debug outputs
- debugX : out unsigned(9 downto 0);
- debugY : out unsigned(8 downto 0);
- vicRefresh : out std_logic;
- addrValid : out std_logic
- );
-end entity;
-
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/video_mixer.sv b/Computer_MiST/Commodore - MAX_MiST/rtl/video_mixer.sv
deleted file mode 100644
index ec953e53..00000000
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/video_mixer.sv
+++ /dev/null
@@ -1,242 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of display line in pixels
-// Usually it's length from HSync to HSync.
-// May be less if line_start is used.
-//
-// HALF_DEPTH: If =1 then color dept is 3 bits per component
-// For half depth 6 bits monochrome is available with
-// mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
- parameter LINE_LENGTH = 768,
- parameter HALF_DEPTH = 0,
-
- parameter OSD_COLOR = 3'd7,
- parameter OSD_X_OFFSET = 10'd0,
- parameter OSD_Y_OFFSET = 10'd0
-)
-(
- // master clock
- // it should be multiple by (ce_pix*4).
- input clk_sys,
-
- // Pixel clock or clock_enable (both are accepted).
- input ce_pix,
-
- // Some systems have multiple resolutions.
- // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
- // thus half or qurter resolutions can be used without brake video sync while switching resolutions.
- // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
- input ce_pix_actual,
-
- // OSD SPI interface
- input SPI_SCK,
- input SPI_SS3,
- input SPI_DI,
-
- // scanlines (00-none 01-25% 10-50% 11-75%)
- input [1:0] scanlines,
-
- // 0 = HVSync 31KHz, 1 = CSync 15KHz
- input scandoubler_disable,
-
- // High quality 2x scaling
- input hq2x,
-
- // YPbPr always uses composite sync
- input ypbpr,
-
- // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
- input ypbpr_full,
-
- // color
- input [DWIDTH:0] R,
- input [DWIDTH:0] G,
- input [DWIDTH:0] B,
-
- // Monochrome mode (for HALF_DEPTH only)
- input mono,
-
- // interlace sync. Positive pulses.
- input HSync,
- input VSync,
-
- // Falling of this signal means start of informative part of line.
- // It can be horizontal blank signal.
- // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
- // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
- // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
- // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
- // before first informative pixel.
- input line_start,
-
- // MiST video output signals
- output [5:0] VGA_R,
- output [5:0] VGA_G,
- output [5:0] VGA_B,
- output VGA_VS,
- output VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
- .*,
- .hs_in(HSync),
- .vs_in(VSync),
- .r_in(R),
- .g_in(G),
- .b_in(B),
-
- .hs_out(hs_sd),
- .vs_out(vs_sd),
- .r_out(R_sd),
- .g_out(G_sd),
- .b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd);
-wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd);
-wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd);
-
-generate
- if(HALF_DEPTH) begin
- wire [5:0] r = mono ? {gt,rt} : {rt,rt};
- wire [5:0] g = mono ? {gt,rt} : {gt,gt};
- wire [5:0] b = mono ? {gt,rt} : {bt,bt};
- end else begin
- wire [5:0] r = rt;
- wire [5:0] g = gt;
- wire [5:0] b = bt;
- end
-endgenerate
-
-wire hs = (scandoubler_disable ? HSync : hs_sd);
-wire vs = (scandoubler_disable ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
- reg old_hs, old_vs;
-
- old_hs <= hs;
- old_vs <= vs;
-
- if(old_hs && ~hs) scanline <= ~scanline;
- if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
- case(scanlines & {scanline, scanline})
- 1: begin // reduce 25% = 1/2 + 1/4
- r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
- g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
- b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
- end
-
- 2: begin // reduce 50% = 1/2
- r_out = {1'b0, r[5:1]};
- g_out = {1'b0, g[5:1]};
- b_out = {1'b0, b[5:1]};
- end
-
- 3: begin // reduce 75% = 1/4
- r_out = {2'b00, r[5:2]};
- g_out = {2'b00, g[5:2]};
- b_out = {2'b00, b[5:2]};
- end
-
- default: begin
- r_out = r;
- g_out = g;
- b_out = b;
- end
- endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
- .*,
-
- .R_in(r_out),
- .G_in(g_out),
- .B_in(b_out),
- .HSync(hs),
- .VSync(vs),
-
- .R_out(red),
- .G_out(green),
- .B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
- 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
- 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
- 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
- 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
- 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
- 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
- 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
- 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
- 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
- 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
- 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
- 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
- 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
- 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
- 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
- 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
- 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
- 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
- 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
- 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
- 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
- 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
- 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
- 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
- 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
- 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
- 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
- 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
- 6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
-assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
-assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
-assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf
index 7ec0d75d..bdbd29e9 100644
--- a/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf
+++ b/Computer_MiST/Galaksija_MiST/Galaksija_Mist.qsf
@@ -57,7 +57,6 @@ set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
# Pin & Location Assignments
# ==========================
@@ -213,6 +212,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end ENTITY(Galaksija_MiST)
# --------------------------
-set_global_assignment -name QIP_FILE ../../Mist_FPGA/common/mist/mist.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/galaksija_keyboard.sv
+set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Computer_MiST/Galaksija_MiST/Galaksija_Mist_assignment_defaults.qdf b/Computer_MiST/Galaksija_MiST/Galaksija_Mist_assignment_defaults.qdf
deleted file mode 100644
index fbb4920a..00000000
--- a/Computer_MiST/Galaksija_MiST/Galaksija_Mist_assignment_defaults.qdf
+++ /dev/null
@@ -1,692 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 21:09:05 March 28, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Note:
-#
-# 1) Do not modify this file. This file was generated
-# automatically by the Quartus II software and is used
-# to preserve global assignments across Quartus II versions.
-#
-# -------------------------------------------------------------------------- #
-
-set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
-set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
-set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
-set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
-set_global_assignment -name SMART_RECOMPILE Off
-set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
-set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
-set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
-set_global_assignment -name HC_OUTPUT_DIR hc_output
-set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
-set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
-set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
-set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
-set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
-set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
-set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
-set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
-set_global_assignment -name REVISION_TYPE Base
-set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
-set_global_assignment -name DO_COMBINED_ANALYSIS Off
-set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT On
-set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
-set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
-set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
-set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
-set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
-set_global_assignment -name MUX_RESTRUCTURE Auto
-set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
-set_global_assignment -name ENABLE_IP_DEBUG Off
-set_global_assignment -name SAVE_DISK_SPACE On
-set_global_assignment -name DISABLE_OCP_HW_EVAL Off
-set_global_assignment -name DEVICE_FILTER_PACKAGE Any
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ""
-set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
-set_global_assignment -name FAMILY "Cyclone IV GX"
-set_global_assignment -name TRUE_WYSIWYG_FLOW Off
-set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
-set_global_assignment -name STATE_MACHINE_PROCESSING Auto
-set_global_assignment -name SAFE_STATE_MACHINE Off
-set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
-set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
-set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
-set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
-set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
-set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
-set_global_assignment -name PARALLEL_SYNTHESIS On
-set_global_assignment -name DSP_BLOCK_BALANCING Auto
-set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
-set_global_assignment -name NOT_GATE_PUSH_BACK On
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
-set_global_assignment -name IGNORE_CARRY_BUFFERS Off
-set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
-set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
-set_global_assignment -name IGNORE_LCELL_BUFFERS Off
-set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
-set_global_assignment -name IGNORE_SOFT_BUFFERS On
-set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
-set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
-set_global_assignment -name AUTO_GLOBAL_OE_MAX On
-set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
-set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
-set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
-set_global_assignment -name ALLOW_XOR_GATE_USAGE On
-set_global_assignment -name AUTO_LCELL_INSERTION On
-set_global_assignment -name CARRY_CHAIN_LENGTH 48
-set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
-set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
-set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
-set_global_assignment -name CASCADE_CHAIN_LENGTH 2
-set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
-set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
-set_global_assignment -name AUTO_CARRY_CHAINS On
-set_global_assignment -name AUTO_CASCADE_CHAINS On
-set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
-set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
-set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
-set_global_assignment -name AUTO_ROM_RECOGNITION On
-set_global_assignment -name AUTO_RAM_RECOGNITION On
-set_global_assignment -name AUTO_DSP_RECOGNITION On
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
-set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
-set_global_assignment -name STRICT_RAM_RECOGNITION Off
-set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
-set_global_assignment -name FORCE_SYNCH_CLEAR Off
-set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
-set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
-set_global_assignment -name AUTO_RESOURCE_SHARING Off
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
-set_global_assignment -name MAX7000_FANIN_PER_CELL 100
-set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
-set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
-set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
-set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
-set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
-set_global_assignment -name REPORT_PARAMETER_SETTINGS On
-set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
-set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
-set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
-set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
-set_global_assignment -name HDL_MESSAGE_LEVEL Level2
-set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
-set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
-set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
-set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
-set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
-set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
-set_global_assignment -name BLOCK_DESIGN_NAMING Auto
-set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
-set_global_assignment -name SYNTHESIS_EFFORT Auto
-set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
-set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
-set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
-set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
-set_global_assignment -name MAX_LABS "-1 (Unlimited)"
-set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
-set_global_assignment -name SYNTHESIS_SEED 1
-set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
-set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
-set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
-set_global_assignment -name AUTO_MERGE_PLLS On
-set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
-set_global_assignment -name TXPMA_SLEW_RATE Low
-set_global_assignment -name ADCE_ENABLED Auto
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
-set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
-set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
-set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
-set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
-set_global_assignment -name ENABLE_NCEO_OUTPUT Off
-set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
-set_global_assignment -name STRATIX_UPDATE_MODE Standard
-set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standard
-set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
-set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
-set_global_assignment -name CVP_MODE Off
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
-set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
-set_global_assignment -name USER_START_UP_CLOCK Off
-set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
-set_global_assignment -name ENABLE_VREFA_PIN Off
-set_global_assignment -name ENABLE_VREFB_PIN Off
-set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
-set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
-set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
-set_global_assignment -name INIT_DONE_OPEN_DRAIN On
-set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
-set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
-set_global_assignment -name ENABLE_CONFIGURATION_PINS On
-set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
-set_global_assignment -name ENABLE_NCE_PIN On
-set_global_assignment -name ENABLE_BOOT_SEL_PIN On
-set_global_assignment -name CRC_ERROR_CHECKING Off
-set_global_assignment -name INTERNAL_SCRUBBING Off
-set_global_assignment -name PR_ERROR_OPEN_DRAIN On
-set_global_assignment -name PR_READY_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CVP_CONFDONE Off
-set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
-set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
-set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
-set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
-set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
-set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
-set_global_assignment -name OPTIMIZE_SSN Off
-set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
-set_global_assignment -name ECO_OPTIMIZE_TIMING Off
-set_global_assignment -name ECO_REGENERATE_REPORT Off
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
-set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
-set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
-set_global_assignment -name SEED 1
-set_global_assignment -name SLOW_SLEW_RATE Off
-set_global_assignment -name PCI_IO Off
-set_global_assignment -name VREF_MODE EXTERNAL
-set_global_assignment -name TURBO_BIT On
-set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
-set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
-set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
-set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
-set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
-set_global_assignment -name AUTO_PACKED_REGISTERS Off
-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
-set_global_assignment -name NORMAL_LCELL_INSERT On
-set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
-set_global_assignment -name AUTO_DELAY_CHAINS On
-set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
-set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
-set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
-set_global_assignment -name AUTO_TURBO_BIT ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
-set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
-set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
-set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
-set_global_assignment -name FITTER_EFFORT "Auto Fit"
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
-set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
-set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
-set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
-set_global_assignment -name AUTO_GLOBAL_CLOCK On
-set_global_assignment -name AUTO_GLOBAL_OE On
-set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
-set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
-set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
-set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
-set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
-set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
-set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
-set_global_assignment -name ENABLE_HOLD_BACK_OFF On
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
-set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
-set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
-set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
-set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
-set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
-set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
-set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
-set_global_assignment -name PR_DONE_OPEN_DRAIN On
-set_global_assignment -name NCEO_OPEN_DRAIN On
-set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
-set_global_assignment -name ENABLE_PR_PINS Off
-set_global_assignment -name PR_PINS_OPEN_DRAIN Off
-set_global_assignment -name CLAMPING_DIODE Off
-set_global_assignment -name TRI_STATE_SPI_PINS Off
-set_global_assignment -name UNUSED_TSD_PINS_GND Off
-set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
-set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
-set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
-set_global_assignment -name EDA_SIMULATION_TOOL ""
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL ""
-set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL ""
-set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL ""
-set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ""
-set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL ""
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL ""
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL ""
-set_global_assignment -name EDA_RESYNTHESIS_TOOL ""
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
-set_global_assignment -name COMPRESSION_MODE Off
-set_global_assignment -name CLOCK_SOURCE Internal
-set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
-set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
-set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
-set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
-set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
-set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
-set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
-set_global_assignment -name SECURITY_BIT Off
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
-set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
-set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
-set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
-set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
-set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
-set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
-set_global_assignment -name GENERATE_TTF_FILE Off
-set_global_assignment -name GENERATE_RBF_FILE Off
-set_global_assignment -name GENERATE_HEX_FILE Off
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
-set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
-set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
-set_global_assignment -name AUTO_RESTART_CONFIGURATION On
-set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
-set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
-set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
-set_global_assignment -name ENABLE_OCT_DONE Off
-set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
-set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
-set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
-set_global_assignment -name START_TIME 0ns
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
-set_global_assignment -name SETUP_HOLD_DETECTION Off
-set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
-set_global_assignment -name CHECK_OUTPUTS Off
-set_global_assignment -name SIMULATION_COVERAGE On
-set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
-set_global_assignment -name GLITCH_DETECTION Off
-set_global_assignment -name GLITCH_INTERVAL 1ns
-set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
-set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
-set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
-set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
-set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
-set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
-set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
-set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
-set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
-set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
-set_global_assignment -name DRC_TOP_FANOUT 50
-set_global_assignment -name DRC_FANOUT_EXCEEDING 30
-set_global_assignment -name DRC_GATED_CLOCK_FEED 30
-set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
-set_global_assignment -name ENABLE_DRC_SETTINGS Off
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
-set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
-set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
-set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
-set_global_assignment -name MERGE_HEX_FILE Off
-set_global_assignment -name GENERATE_SVF_FILE Off
-set_global_assignment -name GENERATE_ISC_FILE Off
-set_global_assignment -name GENERATE_JAM_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE Off
-set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
-set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
-set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
-set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
-set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
-set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
-set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
-set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
-set_global_assignment -name POWER_USE_PVA On
-set_global_assignment -name POWER_USE_INPUT_FILE "No File"
-set_global_assignment -name POWER_USE_INPUT_FILES Off
-set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
-set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
-set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
-set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
-set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
-set_global_assignment -name POWER_TJ_VALUE 25
-set_global_assignment -name POWER_USE_TA_VALUE 25
-set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
-set_global_assignment -name POWER_BOARD_TEMPERATURE 25
-set_global_assignment -name POWER_HPS_ENABLE Off
-set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
-set_global_assignment -name IGNORE_PARTITIONS Off
-set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
-set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
-set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
-set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
-set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
-set_global_assignment -name RTLV_GROUP_RELATED_NODES On
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
-set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
-set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
-set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
-set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
-set_global_assignment -name EQC_BBOX_MERGE On
-set_global_assignment -name EQC_LVDS_MERGE On
-set_global_assignment -name EQC_RAM_UNMERGING On
-set_global_assignment -name EQC_DFF_SS_EMULATION On
-set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
-set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
-set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
-set_global_assignment -name EQC_STRUCTURE_MATCHING On
-set_global_assignment -name EQC_AUTO_BREAK_CONE On
-set_global_assignment -name EQC_POWER_UP_COMPARE Off
-set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
-set_global_assignment -name EQC_AUTO_INVERSION On
-set_global_assignment -name EQC_AUTO_TERMINATE On
-set_global_assignment -name EQC_SUB_CONE_REPORT Off
-set_global_assignment -name EQC_RENAMING_RULES On
-set_global_assignment -name EQC_PARAMETER_CHECK On
-set_global_assignment -name EQC_AUTO_PORTSWAP On
-set_global_assignment -name EQC_DETECT_DONT_CARES On
-set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
-set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
-set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
-set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
-set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
-set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
-set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
-set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
-set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
-set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
-set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ?
-set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
-set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
-set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
-set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
-set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
-set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
-set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
-set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
-set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
-set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
-set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
-set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
-set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
-set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
-set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
-set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
-set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
-set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
-set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
-set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
-set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
-set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
-set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
-set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
-set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
-set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
-set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
-set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
-set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
-set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
-set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
-set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
-set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
-set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
-set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
-set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
-set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
-set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
-set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
-set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv b/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv
index ec5c169f..44ca17ff 100644
--- a/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv
+++ b/Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv
@@ -106,7 +106,7 @@ user_io(
);
dac #(
- .msbi_g(7))
+ .C_bits(7))
dac (
.clk_i(clk_25),
.res_n_i(1'b1),
diff --git a/Computer_MiST/ORAO_MiST/db/Orao_MiST.db_info b/Computer_MiST/ORAO_MiST/db/Orao_MiST.db_info
deleted file mode 100644
index cce0536c..00000000
--- a/Computer_MiST/ORAO_MiST/db/Orao_MiST.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
-Version_Index = 302049280
-Creation_Time = Mon Dec 31 01:30:50 2018
diff --git a/Computer_MiST/Robotron - KC87_MiST/kc87.qsf b/Computer_MiST/Robotron - KC87_MiST/kc87.qsf
index 0d09c74c..e796bbb2 100644
--- a/Computer_MiST/Robotron - KC87_MiST/kc87.qsf
+++ b/Computer_MiST/Robotron - KC87_MiST/kc87.qsf
@@ -43,7 +43,7 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:04:18 MAY 11, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
diff --git a/Computer_MiST/Robotron - Z1013_MiST/Z1013_Mist.qsf b/Computer_MiST/Robotron - Z1013_MiST/Z1013_Mist.qsf
index d11fc2e5..2ec2dab4 100644
--- a/Computer_MiST/Robotron - Z1013_MiST/Z1013_Mist.qsf
+++ b/Computer_MiST/Robotron - Z1013_MiST/Z1013_Mist.qsf
@@ -1,6 +1,6 @@
# -------------------------------------------------------------------------- #
#
-# Copyright (C) 1991-2013 Altera Corporation
+# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
@@ -17,15 +17,15 @@
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 20:08:26 November 23, 2017
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 00:27:10 July 08, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
-# mz80k_assignment_defaults.qdf
+# Z1013_Mist_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -34,6 +34,57 @@
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:08:26 NOVEMBER 23, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
+set_global_assignment -name VHDL_FILE rtl/video_ram_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/video_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/video.vhd
+set_global_assignment -name VHDL_FILE rtl/vga_controller_800_600.vhd
+set_global_assignment -name VHDL_FILE rtl/top_mist.vhd
+set_global_assignment -name VHDL_FILE rtl/text.vhd
+set_global_assignment -name VERILOG_FILE rtl/sdram.v
+set_global_assignment -name VHDL_FILE rtl/scanline.vhd
+set_global_assignment -name VHDL_FILE rtl/scancode_ascii.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM.vhd
+set_global_assignment -name VHDL_FILE rtl/redz0mb1e_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/redz0mb1e.vhd
+set_global_assignment -name VHDL_FILE rtl/ps2_scancode.vhd
+set_global_assignment -name VHDL_FILE rtl/PIO.vhd
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VHDL_FILE rtl/online_help.vhd
+set_global_assignment -name VHDL_FILE rtl/mist_components.vhd
+set_global_assignment -name VHDL_FILE rtl/keyboard_matrix.vhd
+set_global_assignment -name VHDL_FILE rtl/joystick_emu.vhd
+set_global_assignment -name VHDL_FILE rtl/init_message_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/headersave_decode.vhd
+set_global_assignment -name VHDL_FILE rtl/clock_blink.vhd
+set_global_assignment -name VHDL_FILE rtl/chars.vhd
+set_global_assignment -name VHDL_FILE rtl/charrom.vhd
+set_global_assignment -name VHDL_FILE rtl/bm204_202_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/bm100_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/auto_start.vhd
+set_global_assignment -name VHDL_FILE rtl/altpll0.vhd
+set_global_assignment -name QIP_FILE rtl/altpll0.qip
+set_global_assignment -name VHDL_FILE rtl/addr_decode.vhd
+set_global_assignment -name VHDL_FILE rtl/data_io.vhd
+set_global_assignment -name VHDL_FILE rtl/user_io.vhd
+
+# Pin & Location Assignments
+# ==========================
set_location_assignment PIN_65 -to audiol
set_location_assignment PIN_80 -to audior
set_location_assignment PIN_55 -to clk_27[1]
@@ -101,88 +152,89 @@ set_location_assignment PIN_135 -to vga_red[0]
set_location_assignment PIN_136 -to vga_vsync
set_location_assignment PIN_89 -to reset_n
set_location_assignment PIN_33 -to test_point_tp1
-set_location_assignment PIN_105 -to spi_do
-set_location_assignment PIN_88 -to spi_di
-set_location_assignment PIN_126 -to spi_sck
-set_location_assignment PIN_127 -to spi_ss2
-set_location_assignment PIN_91 -to spi_ss3
-set_location_assignment PIN_90 -to spi_ss4
-set_location_assignment PIN_13 -to conf_data0
+set_location_assignment PIN_105 -to spi_do
+set_location_assignment PIN_88 -to spi_di
+set_location_assignment PIN_126 -to spi_sck
+set_location_assignment PIN_127 -to spi_ss2
+set_location_assignment PIN_91 -to spi_ss3
+set_location_assignment PIN_90 -to spi_ss4
+set_location_assignment PIN_13 -to conf_data0
-
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name TOP_LEVEL_ENTITY top_mist
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:08:26 NOVEMBER 23, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+# Classic Timing Assignments
+# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY top_mist
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/video_ram_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/video_ram.vhd
-set_global_assignment -name VHDL_FILE rtl/video.vhd
-set_global_assignment -name VHDL_FILE rtl/vga_controller_800_600.vhd
-set_global_assignment -name VHDL_FILE rtl/top_mist.vhd
-set_global_assignment -name VHDL_FILE rtl/text.vhd
-set_global_assignment -name VERILOG_FILE rtl/sdram.v
-set_global_assignment -name VHDL_FILE rtl/scanline.vhd
-set_global_assignment -name VHDL_FILE rtl/scancode_ascii.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM.vhd
-set_global_assignment -name VHDL_FILE rtl/redz0mb1e_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/redz0mb1e.vhd
-set_global_assignment -name VHDL_FILE rtl/ps2_scancode.vhd
-set_global_assignment -name VHDL_FILE rtl/PIO.vhd
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VHDL_FILE rtl/online_help.vhd
-set_global_assignment -name VHDL_FILE rtl/mist_components.vhd
-set_global_assignment -name VHDL_FILE rtl/keyboard_matrix.vhd
-set_global_assignment -name VHDL_FILE rtl/joystick_emu.vhd
-set_global_assignment -name VHDL_FILE rtl/init_message_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/headersave_decode.vhd
-set_global_assignment -name VHDL_FILE rtl/clock_blink.vhd
-set_global_assignment -name VHDL_FILE rtl/chars.vhd
-set_global_assignment -name VHDL_FILE rtl/charrom.vhd
-set_global_assignment -name VHDL_FILE rtl/bm204_202_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/bm100_pkg.vhd
-set_global_assignment -name VHDL_FILE rtl/auto_start.vhd
-set_global_assignment -name VHDL_FILE rtl/altpll0.vhd
-set_global_assignment -name QIP_FILE rtl/altpll0.qip
-set_global_assignment -name VHDL_FILE rtl/addr_decode.vhd
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name VHDL_FILE rtl/data_io.vhd
-set_global_assignment -name VHDL_FILE rtl/user_io.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+ # EDA Netlist Writer Assignments
+ # ==============================
+ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ----------------------
+# start ENTITY(top_mist)
+
+ # start DESIGN_PARTITION(Top)
+ # ---------------------------
+
+ # Incremental Compilation Assignments
+ # ===================================
+ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+ # end DESIGN_PARTITION(Top)
+ # -------------------------
+
+# end ENTITY(top_mist)
+# --------------------
\ No newline at end of file
diff --git a/Computer_MiST/Commodore - MAX_MiST/rtl/build_id.tcl b/Computer_MiST/Robotron - Z1013_MiST/rtl/build_id.tcl
similarity index 95%
rename from Computer_MiST/Commodore - MAX_MiST/rtl/build_id.tcl
rename to Computer_MiST/Robotron - Z1013_MiST/rtl/build_id.tcl
index be673dac..938515d8 100644
--- a/Computer_MiST/Commodore - MAX_MiST/rtl/build_id.tcl
+++ b/Computer_MiST/Robotron - Z1013_MiST/rtl/build_id.tcl
@@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
- set outputFileName "rtl/build_id.sv"
+ set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source