commit 320d8a7b546010f5a6b73b3db7e1cd89b981293e Author: Gehstock Date: Mon Jan 22 11:32:25 2018 +0100 Initial commit diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 00000000..dfe07704 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,2 @@ +# Auto detect text files and perform LF normalization +* text=auto diff --git a/Sharp -MZ-80K_MiST/clean.bat b/Sharp -MZ-80K_MiST/clean.bat new file mode 100644 index 00000000..b3b7c3b5 --- /dev/null +++ b/Sharp -MZ-80K_MiST/clean.bat @@ -0,0 +1,37 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/Sharp -MZ-80K_MiST/mz80k.qpf b/Sharp -MZ-80K_MiST/mz80k.qpf new file mode 100644 index 00000000..609aba22 --- /dev/null +++ b/Sharp -MZ-80K_MiST/mz80k.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:08:26 November 23, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "20:08:26 November 23, 2017" + +# Revisions + +PROJECT_REVISION = "mz80k" diff --git a/Sharp -MZ-80K_MiST/mz80k.qsf b/Sharp -MZ-80K_MiST/mz80k.qsf new file mode 100644 index 00000000..65cc6ac8 --- /dev/null +++ b/Sharp -MZ-80K_MiST/mz80k.qsf @@ -0,0 +1,123 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition +# Date created = 20:08:26 November 23, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# mz80k_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_54 -to CLOCK_27 +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_13 -to CONF_DATA0 +set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl" +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name TOP_LEVEL_ENTITY mz80k +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:08:26 NOVEMBER 23, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name SYSTEMVERILOG_FILE rtl/mz80k.sv +set_global_assignment -name VERILOG_FILE rtl/mycom.v +set_global_assignment -name QIP_FILE rtl/vram.qip +set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv +set_global_assignment -name VERILOG_FILE rtl/vga.v +set_global_assignment -name VERILOG_FILE rtl/sound.v +set_global_assignment -name VERILOG_FILE rtl/scandoubler.v +set_global_assignment -name VERILOG_FILE rtl/ps2.v +set_global_assignment -name QIP_FILE rtl/pll.qip +set_global_assignment -name VERILOG_FILE rtl/osd.v +set_global_assignment -name QIP_FILE rtl/monrom.qip +set_global_assignment -name VERILOG_FILE rtl/mist_io.v +set_global_assignment -name VERILOG_FILE rtl/keyboard.v +set_global_assignment -name VERILOG_FILE rtl/i8253.v +set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv +set_global_assignment -name VERILOG_FILE rtl/fz80.v +set_global_assignment -name VHDL_FILE rtl/dac.vhd +set_global_assignment -name QIP_FILE rtl/cgrom.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Sharp -MZ-80K_MiST/rtl/80KCG.hex b/Sharp -MZ-80K_MiST/rtl/80KCG.hex new file mode 100644 index 00000000..884b9f47 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/80KCG.hex @@ -0,0 +1,129 @@ +:1000000000000000000000001824427E424242002E +:100010007C22223C22227C001C22404040221C00E8 +:1000200078242222222478007E40407840407E00BE +:100030007E404078404040001C22404E42221C003E +:100040004242427E424242001C08080808081C0046 +:100050000E040404044438004244487048444200FA +:100060004040404040407E0042665A5A4242420070 +:100070004262524A46424200182442424224180038 +:100080007C42427C40404000182442424A241A00EC +:100090007C42427C484442003C42403C02423C009C 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+:100FB0000E2A7111C5D5E5C111280021D8CF190518 +:100FC000F2BE0F060009D1C1C92103E0368A3607F7 +:100FD00036053E013203E0C9AF772310FCC9E1D1E9 +:100FE000C1F1C9F53A9D11B72808F1F5CDCE0BCD69 +:100FF000B500F1C93A9D11B7C83E0DCDB500AFC9D6 +:00000001FF diff --git a/Sharp -MZ-80K_MiST/rtl/build_id.tcl b/Sharp -MZ-80K_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..938515d8 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Sharp -MZ-80K_MiST/rtl/build_id.v b/Sharp -MZ-80K_MiST/rtl/build_id.v new file mode 100644 index 00000000..9d95a4f0 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/build_id.v @@ -0,0 +1,2 @@ +`define BUILD_DATE "171123" +`define BUILD_TIME "223444" diff --git a/Sharp -MZ-80K_MiST/rtl/cgrom.qip b/Sharp -MZ-80K_MiST/rtl/cgrom.qip new file mode 100644 index 00000000..d16c4c00 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/cgrom.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cgrom.v"] diff --git a/Sharp -MZ-80K_MiST/rtl/cgrom.v b/Sharp -MZ-80K_MiST/rtl/cgrom.v new file mode 100644 index 00000000..02de61de --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/cgrom.v @@ -0,0 +1,169 @@ +// megafunction wizard: %ROM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: cgrom.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module cgrom ( + address, + clock, + rden, + q); + + input [10:0] address; + input clock; + input rden; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri1 rden; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .rden_a (rden), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({8{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", +`ifdef NO_PLI + altsyncram_component.init_file = "../rtl/80KCG.rif" +`else + altsyncram_component.init_file = "../rtl/80KCG.hex" +`endif +, + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 2048, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.widthad_a = 11, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "../rtl/80KCG.hex" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "11" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "../rtl/80KCG.hex" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" +// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Sharp -MZ-80K_MiST/rtl/dac.vhd b/Sharp -MZ-80K_MiST/rtl/dac.vhd new file mode 100644 index 00000000..db58d70b --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/dac.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- +-- Delta-Sigma DAC +-- +-- Refer to Xilinx Application Note XAPP154. +-- +-- This DAC requires an external RC low-pass filter: +-- +-- dac_o 0---XXXXX---+---0 analog audio +-- 3k3 | +-- === 4n7 +-- | +-- GND +-- +------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity dac is + generic ( + C_bits : integer := 8 + ); + port ( + clk_i : in std_logic; + res_n_i : in std_logic; + dac_i : in std_logic_vector(C_bits-1 downto 0); + dac_o : out std_logic + ); +end dac; + +architecture rtl of dac is + signal sig_in: unsigned(C_bits downto 0); +begin + seq: process(clk_i, res_n_i) + begin + if res_n_i = '0' then + sig_in <= to_unsigned(2**C_bits, sig_in'length); + dac_o <= '0'; + elsif rising_edge(clk_i) then + -- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i + --sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0)); + sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i); + dac_o <= sig_in(C_bits); + end if; + end process seq; +end rtl; diff --git a/Sharp -MZ-80K_MiST/rtl/fz80.v b/Sharp -MZ-80K_MiST/rtl/fz80.v new file mode 100644 index 00000000..96014f60 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/fz80.v @@ -0,0 +1,1456 @@ +// Z80 CPU binary compatible soft core +// Copyright (C) 2004,2005 by Yasuo Kuwahara +// version 1.04 + +// This software is provided "AS IS", with NO WARRANTY. +// NON-COMMERCIAL USE ONLY + +//`define DEBUG +//`define ICE +//`define M1 + +module fz80(data_in, reset_in, clk, adr, intreq, nmireq, busreq, start, +mreq, iorq, rd, wr, data_out, busack_out, intack_out, mr, +`ifdef M1 + m1, radr, nmiack_out, +`endif +`ifdef ICE + ice_enable, sclk, sdata, +`endif + waitreq +); +`ifdef M1 + output m1, nmiack_out; + output [15:0] radr; +`endif +`ifdef ICE + input sclk, ice_enable; + output sdata; +`endif + input [7:0] data_in; + input reset_in, clk, intreq, nmireq, busreq, waitreq; + output start, mreq, iorq, rd, wr, busack_out, intack_out, mr; + output [7:0] data_out; + output [15:0] adr; + wire [7:0] q_f; + wire [7:0] q_a, q_b, q_c, q_d, q_e, q_h, q_l, q_sph, q_spl, q_pch, q_pcl, q_adrh, q_adrl, q_r, q_i, q_data; + reg sel_af, sel_exx; + wire g_if, g_imm2, g_mr1, g_mr2, g_disp, g_mw1, g_mw2, g_in, g_out; + wire sgate; + wire s_if, s_if2, s_imm1, s_imm2, s_mr1, s_mr2, s_disp, s_iack, s_mw1, s_mw2, s_in, s_out; + wire [1:0] intmode; + wire eschalt; + wire icb, idd, ied, ifd; + wire [7:0] inst_reg; + wire [7:0] q_f_out; + wire [7:0] d_f; + wire cond, cond2; +`ifdef M1 + wire [15:0] radr = { q_i, q_r }; +`endif +// + function [3:0] decode2; + input [1:0] a; + begin + case (a) + 2'h0: decode2 = 4'b0001; + 2'h1: decode2 = 4'b0010; + 2'h2: decode2 = 4'b0100; + 2'h3: decode2 = 4'b1000; + endcase + end + endfunction + function [7:0] decode3; + input [2:0] a; + begin + case (a) + 3'h0: decode3 = 8'b00000001; + 3'h1: decode3 = 8'b00000010; + 3'h2: decode3 = 8'b00000100; + 3'h3: decode3 = 8'b00001000; + 3'h4: decode3 = 8'b00010000; + 3'h5: decode3 = 8'b00100000; + 3'h6: decode3 = 8'b01000000; + 3'h7: decode3 = 8'b10000000; + endcase + end + endfunction + function [7:0] select0; + input [1:0] sel; + input [15:0] a; + begin + case (sel) + 3'h1: select0 = a[15:8]; + 3'h2: select0 = a[7:0]; + default: select0 = 8'b00000000; + endcase + end + endfunction + function [3:0] select1h; + input [3:0] sel; + input [59:0] a; + begin + case (sel) + default: select1h = a[59:56]; + 4'h1: select1h = a[55:52]; + 4'h2: select1h = a[51:48]; + 4'h3: select1h = a[47:44]; + 4'h4: select1h = a[43:40]; + 4'h5: select1h = a[39:36]; + 4'h6: select1h = a[35:32]; + 4'h7: select1h = a[31:28]; + 4'h8: select1h = a[27:24]; + 4'h9: select1h = a[23:20]; + 4'ha: select1h = a[19:16]; + 4'hb: select1h = a[15:12]; + 4'hc: select1h = a[11:8]; + 4'hd: select1h = a[7:4]; + 4'hf: select1h = a[3:0]; + endcase + end + endfunction + function [3:0] select1l; + input [3:0] sel; + input [63:0] a; + begin + case (sel) + 4'h0: select1l = a[63:60]; + 4'h1: select1l = a[59:56]; + 4'h2: select1l = a[55:52]; + 4'h3: select1l = a[51:48]; + 4'h4: select1l = a[47:44]; + 4'h5: select1l = a[43:40]; + 4'h6: select1l = a[39:36]; + 4'h7: select1l = a[35:32]; + 4'h8: select1l = a[31:28]; + 4'h9: select1l = a[27:24]; + 4'ha: select1l = a[23:20]; + 4'hb: select1l = a[19:16]; + 4'hc: select1l = a[15:12]; + 4'hd: select1l = a[11:8]; + 4'he: select1l = a[7:4]; + 4'hf: select1l = a[3:0]; + endcase + end + endfunction + function [15:0] select2; + input [2:0] sel; + input [95:0] a; + begin + case (sel) + 3'h0: select2 = a[95:80]; + 3'h1: select2 = a[79:64]; + 3'h2: select2 = a[63:48]; + 3'h4: select2 = a[47:32]; + 3'h5: select2 = a[31:16]; + default: select2 = a[15:0]; + endcase + end + endfunction + function [7:0] select3; + input [1:0] sel; + input [15:0] a; + begin + case (sel) + 2'h1: select3 = a[15:8]; + 2'h2: select3 = a[7:0]; + default: select3 = 8'b00000000; + endcase + end + endfunction + function [7:0] selectah; + input [2:0] sel; + input [63:0] a; + begin + case (sel) + 3'h1: selectah = a[63:56]; + 3'h2: selectah = a[55:48]; + 3'h3: selectah = a[47:40]; + 3'h4: selectah = a[39:32]; + 3'h5: selectah = a[31:24]; + 3'h6: selectah = a[23:16]; + 3'h7: selectah = a[15:8]; + default: selectah = a[7:0]; + endcase + end + endfunction + function [7:0] selectal; + input [2:0] sel; + input [47:0] a; + begin + case (sel) + 3'h1: selectal = a[47:40]; + 3'h4: selectal = a[39:32]; + 3'h5: selectal = a[31:24]; + 3'h6: selectal = a[23:16]; + 3'h7: selectal = a[15:8]; + default: selectal = a[7:0]; + endcase + end + endfunction + function [7:0] selectf; + input [1:0] sel; + input [31:0] a; + begin + case (sel) + 2'h0: selectf = a[31:24]; + 2'h1: selectf = a[23:16]; + 2'h2: selectf = a[15:8]; + 2'h3: selectf = a[7:0]; + endcase + end + endfunction +`ifdef ICE + parameter INST_COUNT_TARGET = 0; + reg [6:0] rs_count = 0; + reg [5:0] rs_timing = 0; + reg ice_wait = 0, sclk1 = 0, sclk2 = 0; + reg [7:0] inst_count = 0; + wire [7:0] ice_data_tmp; + assign ice_data_tmp = rd ? data_in : data_out; + wire [111:0] sdata_sel = { 2'b00, g_if, mr, mreq, iorq, rd, wr, ice_data_tmp, adr, q_f_out, q_a, q_h, q_l, q_d, q_e, q_b, q_c, q_pch, q_pcl }; + wire sdata = sdata_sel[rs_count]; + wire waitreq1 = waitreq | start | ice_wait & inst_count == INST_COUNT_TARGET; + always @(posedge clk) begin + sclk1 <= sclk; + sclk2 <= sclk1; + if (sclk1 ^ sclk2) begin + if (rs_count == 111) ice_wait <= 0; + rs_count <= rs_count + 1; + end + else if (sclk2) begin + rs_timing <= rs_timing + 1; + if (rs_timing == 31) rs_count <= 0; + end + else rs_timing <= 0; + if (start & ice_enable) ice_wait <= 1; + if (s_if & ~s_if2 & inst_count != INST_COUNT_TARGET) + inst_count <= inst_count + 1; + end +`else + wire waitreq1 = waitreq; +`endif +// instruction decoder + wire intack; + wire int1 = intmode == 2'b10 & intack; + wire [7:0] data = data_in | { 8 { int1 } }; + wire [7:0] i = g_if ? data : inst_reg; + wire i0 = ~icb & ~ied; + wire [3:0] ih = decode2(i[7:6]); + wire [7:0] im = decode3(i[5:3]); + wire [7:0] il = decode3(i[2:0]); + // 8-bit load group + wire i_ldrr = i0 & ih[1] & ~im[6] & ~il[6]; + wire i_ldrn = i0 & ih[0] & ~im[6] & il[6]; + wire i_ldrhl = i0 & ih[1] & ~im[6] & il[6]; + wire i_ldhlr = i0 & ih[1] & im[6] & ~il[6]; + wire i_ldhln = i0 & ih[0] & im[6] & il[6]; + wire i_ldabc = i0 & ih[0] & im[1] & il[2]; + wire i_ldade = i0 & ih[0] & im[3] & il[2]; + wire i_ldann = i0 & ih[0] & im[7] & il[2]; + wire i_ldbca = i0 & ih[0] & im[0] & il[2]; + wire i_lddea = i0 & ih[0] & im[2] & il[2]; + wire i_ldnna = i0 & ih[0] & im[6] & il[2]; + wire i_ldai = ied & ih[1] & im[2] & il[7]; + wire i_ldar = ied & ih[1] & im[3] & il[7]; + wire i_ldia = ied & ih[1] & im[0] & il[7]; + wire i_ldra = ied & ih[1] & im[1] & il[7]; + wire ldair = i_ldai | i_ldar; + // 16-bit load group + wire i_ldddnn = i0 & ih[0] & ~i[3] & il[1]; + wire i_ldhl_nn = i0 & ih[0] & im[5] & il[2]; + wire i_lddd_nn = ied & ih[1] & i[3] & il[3]; + wire i_ldnnhl = i0 & ih[0] & im[4] & il[2]; + wire i_ldnndd = ied & ih[1] & ~i[3] & il[3]; + wire i_ldsphl = i0 & ih[3] & im[7] & il[1]; + wire i_push = i0 & ih[3] & ~i[3] & il[5]; + wire i_pop = i0 & ih[3] & ~i[3] & il[1]; + // exchange, block + wire i_exdehl = i0 & ih[3] & im[5] & il[3]; + wire i_exafaf = i0 & ih[0] & im[1] & il[0]; + wire i_exx = i0 & ih[3] & im[3] & il[1]; + wire i_exsphl = i0 & ih[3] & im[4] & il[3]; + wire i_ldblock = ied & ih[2] & i[5] & il[0]; + wire i_cpblock = ied & ih[2] & i[5] & il[1]; + // 8-bit arithmetic & logical + wire al = i0 & (ih[2] | ih[3] & il[6]); + wire al_r = i0 & ih[2] & ~il[6]; + wire al_n = i0 & ih[3] & il[6]; + wire al_hl = i0 & ih[2] & il[6]; + wire al_r_notcp = al_r & ~im[7]; + wire al_n_notcp = al_n & ~im[7]; + wire al_hl_notcp = al_hl & ~im[7]; + wire arith8_notcp = al & ~i[5]; + wire i_cp = al & im[7]; + wire arith8 = arith8_notcp | i_cp; + wire logica = al & i[5] & (~i[4] | ~i[3]); + wire i_and = logica & im[4]; + wire i_xor = logica & im[5]; + wire i_or = logica & im[6]; + wire incdec8 = i0 & ih[0] & i[2] & ~i[1]; + wire dec8 = incdec8 & i[0]; + wire incdec_hl = incdec8 & im[6]; + // gen. arithmetic & CPU control + wire i_daa = i0 & ih[0] & im[4] & il[7]; + wire i_cpl = i0 & ih[0] & im[5] & il[7]; + wire i_neg = ied & ih[1] & im[0] & il[4]; + wire i_ccf = i0 & ih[0] & im[7] & il[7]; + wire i_scf = i0 & ih[0] & im[6] & il[7]; + wire i_halt = i0 & ih[1] & im[6] & il[6]; + wire i_eidi = i0 & ih[3] & i[5] & i[4] & il[3]; + wire i_im = ied & ih[1] & ~i[5] & il[6]; + // 16-bit arithmetic + wire add16 = i0 & ih[0] & i[3] & il[1]; + wire arith16 = ied & ih[1] & il[2]; + wire i_c16 = add16 | arith16; + wire i_incdec16 = i0 & ih[0] & il[3]; + // rotate & shift + wire i_rotate1 = i0 & ih[0] & ~i[5] & il[7]; + wire i_rs_r = icb & ih[0] & ~il[6]; + wire i_rs_hl = icb & ih[0] & il[6]; + wire i_rotate2 = icb & ih[0] & ~i[5]; + wire rotate = i_rotate1 | i_rotate2; + wire shift = icb & ih[0] & i[5]; + wire rs = rotate | shift; + wire i_rd = ied & ih[1] & i[5] & ~i[4] & il[7]; + wire i_rld = i_rd & i[3]; + wire i_rrd = i_rd & ~i[3]; + wire l = rs & ~i[3]; + wire r = rs & i[3]; + // bit/set/res + wire i_bit_r = icb & ih[1] & ~il[6]; + wire i_bit_hl = icb & ih[1] & il[6]; + wire i_setres_r = icb & i[7] & ~il[6]; + wire i_setres_hl = icb & i[7] & il[6]; + wire ibit = icb & ih[1]; + wire set = icb & ih[3]; + wire res = icb & ih[2]; + // jump + wire i_jpnn = i0 & ih[3] & im[0] & il[3]; + wire i_jpccnn = i0 & ih[3] & il[2]; + wire i_jr = i0 & ih[0] & im[3] & il[0]; + wire i_jrcc = i0 & ih[0] & i[5] & il[0]; + wire i_jphl = i0 & ih[3] & im[5] & il[1]; + wire i_djnz = i0 & ih[0] & im[2] & il[0]; + // call/return + wire i_call = i0 & ih[3] & im[1] & il[5]; + wire i_callcc = i0 & ih[3] & il[4]; + wire i_ret = i0 & ih[3] & im[1] & il[1]; + wire i_retcc = i0 & ih[3] & il[0]; + wire retin = ied & ih[1] & (im[1] | im[0]) & il[5]; + wire i_rst = i0 & ih[3] & il[7]; + // I/O + wire i_inan = i0 & ih[3] & im[3] & il[3]; + wire i_inrc = ied & ih[1] & il[0]; + wire i_outna = ih[3] & im[2] & il[3]; + wire i_outcr = ied & ih[1] & il[1]; + wire i_ioblock = ied & ih[2] & i[5] & ~i[2] & i[1]; + wire i_inblock = i_ioblock & ~i[0]; + wire i_outblock = i_ioblock & i[0]; + // bus cycle decoder + wire nmiack, g_iack; + wire imm1 = i_ldrn | i_ldhln | al_n | i_inan | i_outna | i_jr | i_jrcc | i_djnz; + wire imm2 = i_ldddnn | i_ldann | i_ldnna | i_ldhl_nn | i_ldnnhl | i_ldnndd | i_lddd_nn + | i_jpnn | i_jpccnn | i_call | i_callcc; + wire mr1 = i_ldrhl | i_ldabc | i_ldade | i_ldann | i_ldblock | i_cpblock | al_hl | incdec_hl + | i_rs_hl | i_rd | i_bit_hl | i_setres_hl | i_outblock; + wire mr2 = i_ldhl_nn | i_lddd_nn | i_pop | i_exsphl + | i_ret | i_retcc & cond | retin + | intmode == 2'b11 & intack; + wire mw1 = i_ldhlr | i_ldbca | i_lddea | i_ldnna | i_ldhln | i_ldblock | incdec_hl + | i_rs_hl | i_rd | i_setres_hl | i_inblock; + wire mw2 = i_ldnnhl | i_ldnndd | i_exsphl | i_push | i_call | i_callcc & cond | i_rst + | intmode == 2'b11 & intack | nmiack; + wire disp = (idd | ifd) & (mr1 | mw1); + wire i_in = i_inan | i_inrc | i_inblock; + wire i_out = i_outna | i_outcr | i_outblock; + // + wire mr = g_mr1 | g_mr2; // for debug + wire intack_out = (g_if | g_iack) & intack; + wire nmiack_out = g_iack & nmiack; + // load + wire tmp0 = s_if & (i_rs_r | i_setres_r); + wire tmp1 = s_if & (i_ldrr | incdec8) | s_imm1 & i_ldrn | s_mr1 & i_ldrhl | s_in & i_inrc; + wire load_a = tmp1 & im[7] + | tmp0 & il[7] + | s_mr1 & (i_ldabc | i_ldade | i_ldann | al_hl_notcp) + | s_mr2 & i_pop & im[6] + | s_if & (ldair | al_r_notcp | i_daa | i_cpl | i_neg | i_rotate1) + | s_imm1 & al_n_notcp + | s_mw1 & i_rd + | s_in & i_inan; + wire load_f = s_mr1 & i_pop & im[6]; + wire load_b = tmp1 & im[0] + | tmp0 & il[0] + | s_imm2 & i_ldddnn & im[0] + | s_mr2 & i_lddd_nn & im[1] + | s_mr2 & i_pop & im[0] + | s_imm1 & i_djnz; + wire load_c = tmp1 & im[1] + | tmp0 & il[1] + | s_imm1 & i_ldddnn & im[0] + | s_mr1 & i_lddd_nn & im[1] + | s_mr1 & i_pop & im[0]; + wire load_d = tmp1 & im[2] + | tmp0 & il[2] + | s_imm2 & i_ldddnn & im[2] + | s_mr2 & i_lddd_nn & im[3] + | s_mr2 & i_pop & im[2]; + wire load_e = tmp1 & im[3] + | tmp0 & il[3] + | s_imm1 & i_ldddnn & im[2] + | s_mr1 & i_lddd_nn & im[3] + | s_mr1 & i_pop & im[2]; + wire load_h = tmp1 & im[4] + | tmp0 & il[4] + | s_imm2 & i_ldddnn & im[4] + | s_mr2 & i_ldhl_nn + | s_mr2 & i_lddd_nn & im[5] + | s_mr2 & i_pop & im[4] + | s_if & i_c16; + wire load_l = tmp1 & im[5] + | tmp0 & il[5] + | s_imm1 & i_ldddnn & im[4] + | s_mr1 & i_ldhl_nn + | s_mr1 & i_lddd_nn & im[5] + | s_mr1 & i_pop & im[4]; + wire tmp_adr = i_ldann | i_ldnna | i_ldhl_nn | i_lddd_nn | i_ldnnhl | i_ldnndd | i_call | i_callcc | i_inan | i_outna; + wire load_adrh = s_mr2 & i_exsphl | s_imm2 & tmp_adr; + wire load_adrl = s_mr1 & i_exsphl | s_imm1 & tmp_adr | s_iack; + wire load_r = s_if & i_ldra; + wire load_i = s_if & i_ldia; + wire loadex = s_if & i_exdehl; + wire tmp2 = s_imm2 & (i_jpnn | i_jpccnn & cond); + wire load_pch = tmp2 + | s_mr2 & (i_ret | i_retcc | retin | intack); + wire load_pcl = tmp2 + | s_mr1 & (i_ret | i_retcc | retin | intack); + wire load_sph = s_imm2 & i_ldddnn & im[6] + | s_mr2 & i_lddd_nn & im[7]; + wire load_spl = s_imm1 & i_ldddnn & im[6] + | s_mr1 & i_lddd_nn & im[7]; + wire load_data = s_if & (i_rst | i_outcr) + | s_mr1 & (i_ldblock | incdec_hl | i_rd | i_rs_hl | i_setres_hl | i_outblock) + | s_imm1 & (i_ldhln | i_jpnn | i_jpccnn) + | s_in & i_inblock; + wire loada_bc = s_if & (i_ldblock | i_cpblock | i_incdec16 & ~i[5] & ~i[4]) + | s_in & i_inblock | s_mr1 & i_outblock; + wire loada_de = s_if & (i_exdehl | (i_incdec16 & ~i[5] & i[4])) + | s_mw1 & i_ldblock; + wire loada_l = s_if & i_c16; + wire loada_hl = s_if & i_incdec16 & i[5] & ~i[4] + | s_mr1 & (i_ldblock | i_cpblock) + | s_out & i_outblock + | s_mw1 & i_inblock + | s_mw2 & i_exsphl; + wire loada_sp = s_if & (i_push | i_ldsphl | i_incdec16 & i[5] & i[4] | i_call | i_callcc & cond | i_rst | intack | nmiack) + | s_mw1 & (i_push | i_exsphl | i_call | i_callcc | i_rst | intack | nmiack) + | s_mr1 & (i_pop | i_exsphl | i_ret | i_retcc | retin) + | s_mr2 & (i_pop | i_ret | i_retcc | retin) + | s_iack; + wire alu_zero; + wire loada_pc = s_if & i_jphl + | s_imm1 & (i_jr | i_jrcc & cond2 | i_djnz & ~alu_zero) + | s_mw2 & (i_call | i_callcc); + wire loada_adr = s_disp + | s_mr1 & (i_ldhl_nn | i_lddd_nn | intack) + | s_mw1 & (i_ldnnhl | i_ldnndd); + wire load3_pc = s_mw2 & i_rst; + wire load66_pc = s_mw2 & nmiack; + wire clr_pch = s_mw2 & (i_rst | nmiack); + wire count_pc = (s_if | s_imm1 | s_imm2) & ~(i_halt | intack | nmiack) & ~(s_if2 & (i_ldblock | i_cpblock | i_ioblock)) + | s_disp + | s_mr1 & (i_ldblock | i_cpblock) + | s_in & i_inblock + | s_out & i_outblock + | eschalt; + wire asu_zero; + reg q_asu_zero; + wire dec_pc = (i_ldblock | i_cpblock) & i[4] & ~q_asu_zero & ~(i_cpblock & alu_zero) + | i_inblock & i[4] & ~asu_zero + | i_outblock & i[4] & ~q_f[6]; + wire count_r = s_if; + // + // ALU block + // + // selector 0 (for alu-input a) + wire sel0_a = i_cpblock | al | i_daa; + wire sel0_h = i_c16; + wire [1:0] sel0 = { sel0_h, sel0_a }; + // selector 1 (for alu-input b) + wire sel1_tmp = i_ldrr | i_ldrhl | i_ldhlr | al_r | i_rs_r | i_bit_r | i_setres_r; + wire sel1_b = sel1_tmp & il[0] + | incdec8 & im[0] + | g_mw2 & i_ldnndd & im[0] + | g_mw1 & i_push & im[0] + | i_c16 & (im[0] | im[1]) + | i_djnz + | i_outcr & im[0]; + wire sel1_c = sel1_tmp & il[1] + | incdec8 & im[1] + | g_mw1 & i_ldnndd & im[0] + | g_mw2 & i_push & im[0] + | i_outcr & im[1]; + wire sel1_d = sel1_tmp & il[2] + | incdec8 & im[2] + | g_mw2 & i_ldnndd & im[2] + | g_mw1 & i_push & im[2] + | i_c16 & (im[2] | im[3]) + | i_outcr & im[2]; + wire sel1_e = sel1_tmp & il[3] + | incdec8 & im[3] + | g_mw1 & i_ldnndd & im[2] + | g_mw2 & i_push & im[2] + | i_outcr & im[3]; + wire sel1_h = sel1_tmp & il[4] + | incdec8 & im[4] + | g_mw2 & (i_ldnnhl | i_ldnndd & im[4]) + | g_mw1 & (i_push & im[4] | i_exsphl) + | i_c16 & (im[4] | im[5]) + | i_outcr & im[4]; + wire sel1_l = sel1_tmp & il[5] + | incdec8 & im[5] + | g_mw1 & (i_ldnnhl | i_ldnndd & im[4]) + | g_mw2 & (i_push & im[4] | i_exsphl) + | i_outcr & im[5]; + wire sel1_a = sel1_tmp & il[7] | i_ldbca | i_lddea + | incdec8 & im[7] + | i_cpl | i_neg + | g_mw1 & (i_ldnna | i_push & im[6]) + | i_rotate1 + | i_outna + | i_outcr & im[7]; + wire sel1_data = g_mw1 & (i_ldhln | i_ldblock | incdec_hl | i_rs_hl | i_setres_hl | i_inblock) + | g_imm2 & (i_jpnn | i_jpccnn) + | g_out & (i_outcr & im[6] | i_outblock); + wire sel1_sph = g_mw2 & i_ldnndd & im[6] + | i_c16 & (im[6] | im[7]); + wire sel1_spl = g_mw1 & i_ldnndd & im[6]; + wire sel1_pch = g_mw1 & (i_call | i_callcc | i_rst | intack | nmiack); + wire sel1_pcl = g_mw2 & (i_call | i_callcc | i_rst | intack | nmiack); + wire sel1_i = i_ldai; + wire sel1_r = i_ldar; + wire [3:0] sel1 = { + sel1_b | sel1_c | sel1_d | sel1_e | sel1_h | sel1_l | sel1_a, + sel1_h | sel1_l | sel1_a | sel1_pch | sel1_pcl | sel1_i | sel1_r, + sel1_sph | sel1_spl | sel1_d | sel1_e | sel1_a | sel1_pch | sel1_pcl, + sel1_data | sel1_spl | sel1_c | sel1_e | sel1_l | sel1_a | sel1_pcl | sel1_r + }; + wire sel_rld = g_mw1 & i_rld; + wire sel_rrd = g_mw1 & i_rrd; + wire [3:0] sel1h = { + sel1[3] | sel_rld | sel_rrd, + sel1[2] | sel_rld | sel_rrd, + sel1[1] | sel_rld | sel_rrd, + sel1[0] | sel_rld | sel_rrd + }; + wire [3:0] sel1l = { + sel1[3] | sel_rld, + sel1[2] | sel_rld, + sel1[1] | sel_rld, + sel1[0] | sel_rrd + }; + //initial $monitor($stime,, sel1_b, sel1_c, sel1_d, sel1_e, sel1_h, sel1_l, sel1_a, sel1_data, sel1_sph, sel1_spl, sel1_pch, sel1_pcl); + // + wire [7:0] alu_z, alu_c; + assign alu_zero = ~| alu_z; + wire inva = dec8 | i_djnz; + wire sub = i_cpblock | arith8 & i[4] | i_daa & q_f[1] | i_cpl | i_neg | arith16 & ~i[3]; + wire asu_co; + wire ci = q_f[0] & arith8 & ~i[5] & i[3] | (add16 | arith16) & asu_co | incdec8 & ~i[0]; + wire s_and = i_and; + wire s_xor = i_cpblock | i_cpl | arith8 | i_xor | incdec8 | i_c16 | i_daa | i_neg | i_djnz; + wire s_or = ~s_and & ~s_xor & ~rs & ~i_outcr; + wire ec = i_cpblock | arith8 & (~i[5] | i[3]) | incdec8 | i_c16 | i_daa | i_neg | i_djnz; + wire [7:0] alu_a = select0(sel0, { q_a, q_h }); + wire [3:0] alu_bh = select1h(sel1h, { data[7:4], q_data[7:4], q_sph[7:4], q_spl[7:4], q_i[7:4], q_r[7:4], q_pch[7:4], q_pcl[7:4], q_b[7:4], q_c[7:4], q_d[7:4], q_e[7:4], q_h[7:4], q_l[7:4], q_a[7:4] }); + wire [3:0] alu_bl = select1l(sel1l, { data[3:0], q_data[3:0], q_sph[3:0], q_spl[3:0], q_i[3:0], q_r[3:0], q_pch[3:0], q_pcl[3:0], q_b[3:0], q_c[3:0], q_d[3:0], q_e[3:0], q_h[3:0], q_l[3:0], q_data[7:4], q_a[3:0] }); + wire [7:0] alu_b = { alu_bh, alu_bl }; + alu alu(.c_in(ci), .im(im), .a(alu_a), .b(alu_b), .inva(inva), .invb(sub), + .reg_q_c(q_f[0]), .reg_q_h(q_f[4]), + .s_and(s_and), .s_or(s_or), .s_xor(s_xor), .ec(ec), + .i_daa(i_daa), .set(set), .res(res), .l(l), .r(r), + .z(alu_z), .co(alu_c)); + // + // ASU block + // + // selector 2 (for asu-input a) + wire sel2_bc = g_if & (i_ldblock | i_cpblock | (i_c16 | i_incdec16) & ~i[5] & ~i[4]) + | g_in & i_inblock + | g_mr1 & i_outblock; + wire sel2_de = g_mw1 & i_ldblock + | (i_c16 | i_incdec16) & ~i[5] & i[4]; + wire sel2_hl = g_disp + | i_ldsphl | i_exdehl | (i_c16 | i_incdec16) & i[5] & ~i[4] | i_jphl + | g_mr1 & (i_ldblock | i_cpblock) + | g_out & i_outblock + | g_mw1 & i_inblock; + wire sel2_pc = i_jr | i_jrcc | i_djnz; + wire sel2_adr = i_ldhl_nn | i_lddd_nn | i_ldnnhl | i_ldnndd + | g_mr1 & intack + | g_mw2 & (i_exsphl | i_call | i_callcc); + wire [2:0] sel2 = { + sel2_bc | sel2_de | sel2_hl, + sel2_adr | sel2_hl, + sel2_pc | sel2_de + }; + // selector 3 (for asu-input b) + wire sel3_l = i_c16; + wire sel3_data_in = g_disp | i_jr | i_jrcc | i_djnz; + wire [1:0] sel3 = { + sel3_data_in, + sel3_l + }; + // + wire [15:0] asu_z; + assign asu_zero = ~| asu_z[15:8] & (i_ioblock | ~| asu_z[7:0]); + wire asu_ci = i_ldhl_nn | i_lddd_nn | i_ldnnhl | i_ldnndd | i_pop + | s_mr1 & (i_exsphl | intack) + | (s_mr1 | s_mw1) & (i_ldblock | i_cpblock) & ~i[3] + | (s_out | s_mw1) & i_ioblock & ~i[3] + | q_f[0] & arith16 | i_incdec16 & ~i[3] | i_jr | i_jrcc | i_djnz | i_ret | i_retcc | retin; + wire [2:0] asu_i = { + s_in & i_inblock | s_mr1 & i_outblock, + s_in & i_inblock | s_mr1 & i_outblock + | s_if & (i_push | i_ldblock | i_cpblock | i_incdec16 & i[3] | i_call | i_callcc | i_rst | intack | nmiack) + | s_mw1 & (i_push | i_exsphl | (i_ldblock | i_inblock) & i[3] | i_call | i_callcc | i_rst | intack | nmiack) + | s_mr1 & (i_ldblock | i_cpblock) & i[3] + | s_out & i_outblock & i[3] + | s_iack, + s_if & i_c16 & ~i[3] + }; + wire [15:0] asu_a = select2(sel2, { q_sph, q_spl, q_pch, q_pcl, q_adrh, q_adrl, q_b, q_c, q_d, q_e, q_h, q_l }); + wire [7:0] asu_b = select3(sel3, { q_l, data_in }); + asu asu(.a(asu_a), .b(asu_b), .ci(asu_ci), .i(asu_i), .z(asu_z), .co(asu_co)); + always @(posedge clk) + if (s_if | s_in) q_asu_zero <= asu_zero; + // + // address selector + // + wire sela_tmp = g_mr1 | g_mr2 | g_mw1 | g_mw2 | g_in | g_out; + wire sela_tmp2 = i_ldann | i_ldnna | i_ldhl_nn | i_lddd_nn | i_ldnnhl | i_ldnndd; + wire sela_tmp3 = (idd | ifd) & (g_mr1 | g_mw1); + wire selah_a = sela_tmp & (i_inan | i_outna); + wire sela_bc = sela_tmp & (i_ldabc | i_ldbca | i_inrc | i_outcr) + | g_in & i_inblock | g_out & i_outblock; + wire sela_de = g_mr1 & i_ldade | g_mw1 & (i_lddea | i_ldblock); + wire sela_hl = ~sela_tmp3 & (sela_tmp & (i_ldrhl | i_ldhlr | i_ldhln | i_cpblock | al_hl | incdec_hl | i_rs_hl | i_rd | i_bit_hl | i_setres_hl) + | g_mw1 & i_inblock + | g_mr1 & (i_ldblock | i_outblock)); + wire selah_adr = sela_tmp3 | sela_tmp & sela_tmp2; + wire selal_adr = sela_tmp3 + | sela_tmp & (sela_tmp2 | i_inan | i_outna) + | (g_mr1 | g_mr2) & intack; + wire sela_sp = sela_tmp & (i_push | i_pop | i_exsphl | i_call | i_callcc | i_ret | i_retcc | retin | i_rst) + | (g_mw1 | g_mw2) & (intack | nmiack); + wire selah_i = (g_mr1 | g_mr2) & intack; + wire [2:0] selah = { + sela_bc | sela_de | sela_hl | sela_sp, + selah_a | selah_i | sela_hl | sela_sp, + selah_adr | selah_i | sela_de | sela_sp + }; + wire [2:0] selal = { + sela_bc | sela_de | sela_hl | sela_sp, + sela_hl | sela_sp, + selal_adr | sela_de | sela_sp + }; + //initial $monitor($stime,, selal,, selah); + // final selector + wire sel_fr = g_mw2 & i_push & im[6]; + wire [1:0] self = { + sel_rld | sel_rrd, + sel_fr | sel_rrd + }; + //initial $monitor($stime,, self); + // sequencer + seq seq(.data_in(data), .busreq(busreq), .waitreq(waitreq1), .intreq(intreq), .nmireq(nmireq), .reset_in(reset_in), .clk(clk), + .intack(intack), .nmiack(nmiack), .busack(busack_out), .iff2(iff2), .start(start), + .icb(icb), .idd(idd), .ied(ied), .ifd(ifd), .inst_reg(inst_reg), + .mreq(mreq), .iorq(iorq), .rd(rd), .wr(wr), + .imm1(imm1), .imm2(imm2), .mr1(mr1), .mr2(mr2), .mw1(mw1), .mw2(mw2), .disp(disp), .i_in(i_in), .i_out(i_out), .i_eidi(i_eidi), .i_im(i_im), .retin(retin), .i43(i[4:3]), + .g_if(g_if), .g_imm2(g_imm2), .g_mr1(g_mr1), .g_mr2(g_mr2), .g_mw1(g_mw1), .g_mw2(g_mw2), .g_disp(g_disp), .g_in(g_in), .g_out(g_out), .g_iack(g_iack), + .sgate(sgate), + .s_if(s_if), .s_if2(s_if2), .s_imm1(s_imm1), .s_imm2(s_imm2), + .s_mr1(s_mr1), .s_mr2(s_mr2), .s_mw1(s_mw1), .s_mw2(s_mw2), + .s_disp(s_disp), .s_in(s_in), .s_out(s_out), .s_iack(s_iack), +`ifdef M1 + .m1(m1), +`endif + .intmode(intmode), .i_halt(i_halt), .eschalt(eschalt)); +// exchange register + always @(posedge clk) begin + if (reset_in) begin + sel_af <= 1'b0; + sel_exx <= 1'b0; + end + else begin + if (s_if & i_exafaf) sel_af <= ~sel_af; + if (s_if & i_exx) sel_exx <= ~sel_exx; + end + end +//// F register + wire sel = alu_z[i[5:3]]; + wire subf = incdec8 ? i[0] : sub; + wire cv0 = arith8 | arith16 | i_daa | i_neg | add16; + wire cv1 = i_ccf; + wire cv2 = i_scf; + wire cv3 = l; + wire cv4 = r; + wire cv5 = logica; + assign d_f[0] = data_in[0] & load_f + | (alu_c[7] ^ sub) & cv0 + | ~q_f[0] & cv1 + | cv2 + | alu_b[7] & cv3 + | alu_b[0] & cv4 + | q_f[0] & ~(load_f | cv0 | cv1 | cv2 | cv3 | cv4 | cv5); + wire nv0 = i_ioblock; + wire nv1 = (arith8 | incdec8 | arith16) & subf | i_cpblock | i_cpl | i_neg; + wire nv2 = (arith8 | incdec8 | add16 | arith16) & ~subf | ldair | i_inrc | i_rd | i_ccf | i_scf | i_ldblock | logica | rs | ibit; + assign d_f[1] = data_in[1] & load_f + | alu_b[7] & nv0 + | nv1 + | q_f[1] & ~(load_f | nv0 | nv1 | nv2); + wire pv0 = ldair; + wire pv1 = i_ldblock | i_cpblock; + wire pv2 = arith8 | arith16 | i_neg | incdec8; + wire pv3 = logica | i_daa | i_rotate2 | shift | i_rd | i_inrc; + wire pv4 = ibit; + assign d_f[2] = data_in[2] & load_f + | iff2 & pv0 + | ~q_asu_zero & pv1 + | (alu_c[7] ^ alu_c[6]) & pv2 + | ~^alu_z[7:0] & pv3 + |~sel & pv4 + | q_f[2] & ~(load_f | pv0 | pv1 | pv2 | pv3 | pv4); + wire xy0 = arith8_notcp | incdec8 | i_daa | i_cpl | i_neg | i_ccf | i_scf | add16 | arith16 | rs | i_rd | i_inrc; + wire xy1 = i_cp; + wire xy2 = ibit; + wire xy3 = i_ioblock; + assign d_f[3] = data_in[3] & load_f + | alu_z[3] & (xy0 | i_ldblock) + | alu_b[3] & xy1 + | ~i[5] & i[4] & i[3] & sel & xy2 + | q_b[3] & xy3 + | q_f[3] & ~(load_f | xy0 | xy1 | xy2 | xy3); + wire hv0 = arith8 | arith16 | i_neg | i_cpblock | incdec8 | add16; + wire hv1 = i_and | i_cpl | ibit; + wire hv2 = i_ccf; + wire hv3 = ldair | i_inrc | i_rd | i_ldblock | i_or | i_xor | i_scf | rs; + assign d_f[4] = data_in[4] & load_f + | (alu_c[3] ^ subf) & hv0 + | hv1 + | q_f[0] & hv2 + | (q_f[1] ? ~alu_b[3] & (~alu_b[2] | ~alu_b[1]) : alu_b[3] & (alu_b[2] | alu_b[1])) & i_daa + | q_f[4] & ~(load_f | hv0 | hv1 | hv2 | hv3 | i_daa); + assign d_f[5] = data_in[5] & load_f + | alu_z[5] & xy0 + | alu_b[5] & xy1 + | i[5] & ~i[4] & i[3] & sel & xy2 + | q_b[5] & xy3 + | alu_z[1] & i_ldblock + | q_f[5] & ~(load_f | xy0 | xy1 | xy2 | xy3 | i_ldblock); + wire zs0 = arith8 | arith16 | i_daa | i_neg | i_cpblock | incdec8 | ldair | i_inrc | i_rd | i_rotate2 | shift | logica; + wire zs1 = ibit; + wire zl = ~| alu_z[7:0]; + wire zu = ~| asu_z[7:0]; + assign d_f[6] = data_in[6] & load_f + | zl & zs0 & (~arith16 | zu) + | ~sel & zs1 + | q_asu_zero & i_inblock + | asu_zero & i_outblock + | q_f[6] & ~(load_f | zs0 | zs1 | i_ioblock); + assign d_f[7] = data_in[7] & load_f + | alu_z[7] & zs0 + | i[5] & i[4] & i[3] & sel & zs1 + | q_b[7] & i_ioblock + | q_f[7] & ~(load_f | zs0 | zs1 | i_ioblock); +// assign q_f_out = q_f; + assign q_f_out = { q_f[7:6], 1'b0, q_f[4], 1'b0, q_f[2:0] }; + wire [7:0] cond3_sel = { q_f[7], ~q_f[7], q_f[2], ~q_f[2], q_f[0], ~q_f[0], q_f[6], ~q_f[6] }; + assign cond = cond3_sel[i[5:3]]; + wire [3:0] cond2_sel = { q_f[0], ~q_f[0], q_f[6], ~q_f[6] }; + assign cond2 = cond2_sel[i[4:3]]; +// + wire [15:0] adr = { + selectah(selah, { q_adrh, q_a, q_i, q_b, q_d, q_h, q_sph, q_pch }), + selectal(selal, { q_adrl, q_c, q_e, q_l, q_spl, q_pcl }) + }; + wire [7:0] data_out = selectf(self, { alu_b, q_f_out, q_data[3:0], q_a[3:0], q_a[3:0], q_data[7:4] }); + wire loadal = loada_hl | loada_l; + wire clr_pch1 = reset_in | clr_pch; + wire reg_load_f = sgate & ~((g_if | g_mw1) & (al_n | al_hl | incdec_hl | i_rs_hl)) & ~g_out & ~g_disp; + reg_a reg_a(.a(alu_z), + .load(load_a), + .set(reset_in), .regsel(sel_af), .clk(clk), .q(q_a)); + reg_f reg_f(.a(d_f), + .load(reg_load_f), + .set(reset_in), .regsel(sel_af), .clk(clk), .q(q_f)); + reg_dual2 reg_b(.a(alu_z), .a2(asu_z[15:8]), + .load(load_b), .load2(loada_bc), + .regsel(sel_exx), .clk(clk), .q(q_b)); + reg_dual2 reg_c(.a(alu_z), .a2(asu_z[7:0]), + .load(load_c), .load2(loada_bc), + .regsel(sel_exx), + .clk(clk), .q(q_c)); + reg_dual2 reg_d(.a(alu_z), .a2(asu_z[15:8]), + .load(load_d), .load2(loada_de), + .regsel(sel_exx), + .clk(clk), .q(q_d)); + reg_dual2 reg_e(.a(alu_z), .a2(asu_z[7:0]), + .load(load_e), .load2(loada_de), + .regsel(sel_exx), + .clk(clk), .q(q_e)); + wire indexvalid = ~(g_mr1 & i_ldrhl | g_mw1 & i_ldhlr); + reg_quad3 reg_h(.a(alu_z), .a2(asu_z[15:8]), .a3(q_d), + .load(load_h), .load2(loada_hl), .load3(loadex), + .regsel(sel_exx), + .i_dd(idd & indexvalid), .i_fd(ifd & indexvalid), + .clk(clk), .q(q_h)); + reg_quad3 reg_l(.a(alu_z), .a2(asu_z[7:0]), .a3(q_e), + .load(load_l), .load2(loadal), .load3(loadex), + .regsel(sel_exx), + .i_dd(idd & indexvalid), .i_fd(ifd & indexvalid), + .clk(clk), .q(q_l)); + reg_2s reg_sph(.a(data_in), .a2(asu_z[15:8]), + .load(load_sph), .load2(loada_sp), + .set(reset_in), + .clk(clk), .q(q_sph)); + reg_2s reg_spl(.a(data_in), .a2(asu_z[7:0]), + .load(load_spl), .load2(loada_sp), + .set(reset_in), + .clk(clk), + .q(q_spl)); + reg_pch reg_pch(.a(data_in), .a2(asu_z[15:8]), + .load(load_pch), .load2(loada_pc), .count(co_pc), .dec(dec_pc), + .clr(clr_pch1), + .clk(clk), + .q(q_pch)); + reg_pcl reg_pcl(.a(alu_z), .a2(asu_z[7:0]), .a3(q_data[5:3]), + .load(load_pcl), .load2(loada_pc), .load3(load3_pc), .load66(load66_pc), .count(count_pc), .dec(dec_pc), + .clr(reset_in), + .clk(clk), + .q(q_pcl), .co(co_pc)); + reg_2 reg_adrh(.a(data_in), .a2(asu_z[15:8]), + .load(load_adrh), .load2(loada_adr), + .clk(clk), + .q(q_adrh)); + reg_2 reg_adrl(.a(data_in), .a2(asu_z[7:0]), + .load(load_adrl), .load2(loada_adr), + .clk(clk), + .q(q_adrl)); + reg_r reg_r(.a(q_a), + .load(load_r), + .count(count_r), + .clr(reset_in), + .clk(clk), + .q(q_r)); + reg_simplec reg_i(.a(q_a), + .load(load_i), + .clr(reset_in), + .clk(clk), + .q(q_i)); + reg_simple reg_data(.a(alu_z), + .load(load_data), + .clk(clk), + .q(q_data)); +`ifdef DEBUG + wire [15:0] debug_pc, debug_sp, debug_bc, debug_de, debug_hl; + assign debug_pc = { q_pch, q_pcl }; + assign debug_sp = { q_sph, q_spl }; + assign debug_bc = { q_b, q_c }; + assign debug_de = { q_d, q_e }; + assign debug_hl = { q_h, q_l }; + initial $monitor($stime, " %x %x %x %x %x %x %x %x", seq.state, debug_pc, debug_sp, debug_bc, debug_de, debug_hl, q_a, q_f_out); +`endif +endmodule + +module seq(data_in, busreq, waitreq, intreq, nmireq, reset_in, clk, + intack, nmiack, busack, iff2, icb, idd, ied, ifd, inst_reg, start, + mreq, iorq, rd, wr, + imm1, imm2, mr1, mr2, mw1, mw2, disp, i_in, i_out, i_eidi, i_im, retin, i43, + g_if, g_imm2, g_mr1, g_mr2, g_mw1, g_mw2, g_disp, g_in, g_out, g_iack, + sgate, + s_if, s_if2, s_imm1, s_imm2, s_mr1, s_mr2, s_mw1, s_mw2, s_disp, s_in, s_out, s_iack, +`ifdef M1 + m1, +`endif + intmode, i_halt, eschalt); + input [7:0] data_in; + input [1:0] i43; + input busreq, waitreq, intreq, nmireq, reset_in, clk; + input imm1, imm2, mr1, mr2, mw1, mw2, disp, i_in, i_out, i_eidi, i_im, retin; + input i_halt; + output mreq, iorq, rd, wr; + output intack, nmiack, busack, iff2, icb, idd, ied, ifd, start; + output [7:0] inst_reg; + output g_if, g_imm2, g_mr1, g_mr2, g_mw1, g_mw2, g_disp, g_in, g_out, g_iack; + output sgate; + output s_if, s_if2, s_imm1, s_imm2, s_mr1, s_mr2, s_mw1, s_mw2, s_disp, s_in, s_out, s_iack; + output [1:0] intmode; + output eschalt; +`ifdef M1 + output m1; +`endif + parameter S_IF1 = 4'b0000; + parameter S_IF2 = 4'b0001; + parameter S_IMM1 = 4'b0010; + parameter S_IMM2 = 4'b0011; + parameter S_MR1 = 4'b0100; + parameter S_MR2 = 4'b0101; + parameter S_DISP = 4'b0110; + parameter S_IN = 4'b0111; + parameter S_IACK = 4'b1000; + parameter S_MW1 = 4'b1100; + parameter S_MW2 = 4'b1101; + parameter S_OUT = 4'b1111; + reg [3:0] state; + reg [7:0] inst_reg; + reg icb, ied, idd, ifd, iff1, iff2, intack, nmiack, busack, eschalt; + reg [1:0] intmode; + reg start; + wire g_if = state[3:1] == 3'b000; + wire g_if1 = state == S_IF1; + wire g_if2 = state == S_IF2; + wire g_imm1 = state == S_IMM1; + wire g_imm2 = state == S_IMM2; + wire g_mr1 = state == S_MR1; + wire g_mr2 = state == S_MR2; + wire g_disp = state == S_DISP; + wire g_in = state == S_IN; + wire g_iack = state == S_IACK; // IM2 | NMI only + wire g_mw1 = state == S_MW1; + wire g_mw2 = state == S_MW2; + wire g_out = state == S_OUT; + wire sgate = ~reset_in & ~busack & ~waitreq; + wire s_if = sgate & g_if; + wire s_if2 = sgate & g_if2; + wire s_imm1 = sgate & g_imm1; + wire s_imm2 = sgate & g_imm2; + wire s_mr1 = sgate & g_mr1; + wire s_mr2 = sgate & g_mr2; + wire s_disp = sgate & g_disp; + wire s_in = sgate & g_in; + wire s_iack = sgate & g_iack; + wire s_mw1 = sgate & g_mw1; + wire s_mw2 = sgate & g_mw2; + wire s_out = sgate & g_out; + wire nextcycle = g_if1 & data_in != 8'hcb & data_in != 8'hdd & data_in != 8'hed & data_in != 8'hfd & ~intack & ~disp & ~imm1 & ~imm2 & ~mr1 & ~mr2 & ~mw1 & ~mw2 & ~i_in + | g_if2 & ~imm1 & ~imm2 & ~mr1 & ~mr2 & ~i_in & ~i_out + | g_imm1 & ~imm2 & ~mw1 & ~i_in & ~i_out + | g_imm2 & ~mr1 & ~mr2 & ~mw1 & ~mw2 + | g_mr1 & ~mr2 & ~mw1 & ~mw2 & ~i_out + | g_mr2 & ~intack & ~mw1 & ~mw2 + | g_mw1 & ~mw2 + | g_mw2 & ~intack + | g_in & ~mw1 + | g_out; + wire next_if2 = (g_if1 & (data_in == 8'hcb & ~idd & ~ifd | data_in == 8'hed) + | g_disp & icb); + wire next_imm1 = (g_if1 & ~disp & (imm1 | imm2) + | g_disp & ~icb & imm1 + | g_if2 & (imm1 | imm2)); + wire next_imm2 = g_imm1 & imm2; + wire next_mr1 = (g_if1 & ~disp & ~imm1 & ~imm2 & (mr1 | mr2) + | g_disp & ~icb & ~imm1 & mr1 + | g_if2 & ~imm1 & ~imm2 & (mr1 | mr2) + | g_imm2 & (mr1 | mr2) + | g_mw2 & intack & intmode == 2'b11); + wire next_mr2 = g_mr1 & mr2; + wire next_disp = g_if1 & (data_in == 8'hcb & (idd | ifd) | disp); + wire next_in = i_in & (g_if1 & ~imm1 & ~mw1 + | g_if2 + | g_imm1); + wire next_iack = (nextcycle & (nmireq | intreq & iff1 & intmode == 2'b11)); + wire next_mw1 = (g_if1 & ~disp & ~imm1 & ~imm2 & ~mr1 & ~mr2 & (mw1 | mw2) + | g_disp & ~icb & ~imm1 & ~mr1 + | g_imm1 & ~imm2 & mw1 + | g_imm2 & ~mr1 & ~mr2 & (mw1 | mw2) + | g_mr1 & ~mr2 & (mw1 | mw2) + | g_mr2 & ~intack & (mw1 | mw2) + | g_in & mw1 + | g_iack); + wire next_mw2 = g_mw1 & mw2; + wire next_out = i_out & (g_if2 & ~imm1 & ~mr1 + | g_imm1 + | g_mr1); + always @(posedge clk) begin + if (reset_in) begin + state <= S_IF1; + start <= 1'b1; + icb <= 1'b0; + ied <= 1'b0; + idd <= 1'b0; + ifd <= 1'b0; + iff1 <= 1'b0; + iff2 <= 1'b0; + intmode <= 2'b00; + intack <= 1'b0; + nmiack <= 1'b0; + busack <= 1'b0; + eschalt <= 1'b0; + end + else if (busack) begin + if (~busreq) busack <= 1'b0; + end + else if (waitreq) start <= 1'b0; + else begin + state <= { + next_iack | next_mw1 | next_mw2 | next_out, + next_mr1 | next_mr2 | next_disp | next_in | next_mw1 | next_mw2 | next_out, + next_imm1 | next_imm2 | next_disp | next_in | next_out, + next_if2 | next_imm2 | next_mr2 | next_in | next_mw2 | next_out + }; + start <= 1'b1; + if (g_if1) begin + inst_reg <= data_in; + intack <= 1'b0; // when IM0 | IM1 + eschalt <= 1'b0; + if (data_in == 8'hcb) icb <= 1'b1; + if (data_in == 8'hed) ied <= 1'b1; + if (data_in == 8'hdd) begin + idd <= 1'b1; + ifd <= 1'b0; + end + if (data_in == 8'hfd) begin + ifd <= 1'b1; + idd <= 1'b0; + end + end + else if (g_if2) inst_reg <= data_in; + else if (g_mr2) intack <= 1'b0; // IM2 + else if (g_mw2) begin + if (intack & intmode != 2'b11) intack <= 1'b0; + nmiack <= 1'b0; + end + else if (g_iack) eschalt <= 1'b0; + if (i_eidi) begin + iff1 <= i43[0]; + iff2 <= i43[0]; + end + if (retin) iff1 <= iff2; + if (i_im) intmode <= i43[1:0]; + if (nextcycle) begin + icb <= 1'b0; + ied <= 1'b0; + idd <= 1'b0; + ifd <= 1'b0; + if (nmireq) begin + nmiack <= 1'b1; + iff1 <= 1'b0; + eschalt <= i_halt; + inst_reg <= 8'b00000000; + end + else if (intreq & iff1) begin + intack <= 1'b1; + iff1 <= 1'b0; + iff2 <= 1'b0; + eschalt <= i_halt; + inst_reg <= 8'b00000000; + end + end + if (busreq) busack <= 1'b1; + end + end + wire intack_r = (g_if | g_iack) & intack; + wire iorq_t = state[2:0] == 3'b111 | intack_r; + wire iorq = ~busack & iorq_t; + wire mreq = ~busack & ~iorq_t & ~intack_r; + wire rd = ~busack & (~state[3] | g_iack) & ~intack_r; + wire wr = ~busack & state[3] & ~g_iack; +`ifdef M1 + wire m1 = g_if | g_iack; +`endif +endmodule + +// ASU +// z,co = a + b + ci 8bit/16bit i = 3'b000 for lower 8bit of 16bit arithmetic / 16bit increment +// z,co = b - a - ci 8bit i = 3'b001 for lower 8bit of 16bit arithmetic +// z = a - ~ci 16bit i = 3'b010 16bit decrement +// z = a - 0x100 16bit i = 3'b110 upper 8bit decrement + +module asu(a, b, ci, i, z, co); + input [15:0] a; + input [7:0] b; + input ci; + input [2:0] i; + output [15:0] z; + output co; + wire [14:0] c; + wire [14:0] tand, tor; + wire [7:0] a1 = a ^ { 8 { i[0] } }; + wire [7:0] b1 = b | { 8 { i[1] } }; + wire c1 = ci ^ (i[2] | i[0]); + assign tand[7:0] = a1[7:0] & b1[7:0]; + assign tor[7:0] = a1[7:0] | b1[7:0]; + assign c[0] = tand[0] | tor[0] & c1; + assign c[1] = tand[1] | tor[1] & tand[0] + | &tor[1:0] & c1; + assign c[2] = tand[2] | tor[2] & tand[1] + | &tor[2:1] & tand[0] + | &tor[2:0] & c1; + assign c[3] = tand[3] | tor[3] & tand[2] + | &tor[3:2] & tand[1] + | &tor[3:1] & tand[0] + | &tor[3:0] & c1; + assign c[4] = tand[4] | tor[4] & tand[3] + | &tor[4:3] & tand[2] + | &tor[4:2] & tand[1] + | &tor[4:1] & tand[0] + | &tor[4:0] & c1; + assign c[5] = tand[5] | tor[5] & tand[4] + | &tor[5:4] & tand[3] + | &tor[5:3] & tand[2] + | &tor[5:2] & tand[1] + | &tor[5:1] & tand[0] + | &tor[5:0] & c1; + assign c[6] = tand[6] | tor[6] & tand[5] + | &tor[6:5] & tand[4] + | &tor[6:4] & tand[3] + | &tor[6:3] & tand[2] + | &tor[6:2] & tand[1] + | &tor[6:1] & tand[0] + | &tor[6:0] & c1; + assign c[7] = tand[7] | tor[7] & tand[6] + | &tor[7:6] & tand[5] + | &tor[7:5] & tand[4] + | &tor[7:4] & tand[3] + | &tor[7:3] & tand[2] + | &tor[7:2] & tand[1] + | &tor[7:1] & tand[0] + | &tor[7:0] & c1; + assign z[7:0] = a1[7:0] ^ b1[7:0] ^ { c[6:0], c1 }; + wire co = c[7] ^ (i[2] | i[0]); + assign tand[14:8] = a[14:8] & { 8 { b1[7] } }; + assign tor[14:8] = a[14:8] | { 8 { b1[7] } }; + assign c[8] = tand[8] | tor[8] & co; + assign c[9] = tand[9] | tor[9] & tand[8] + | &tor[9:8] & co; + assign c[10] = tand[10] | tor[10] & tand[9] + | &tor[10:9] & tand[8] + | &tor[10:8] & co; + assign c[11] = tand[11] | tor[11] & tand[10] + | &tor[11:10] & tand[9] + | &tor[11:9] & tand[8] + | &tor[11:8] & co; + assign c[12] = tand[12] | tor[12] & tand[11] + | &tor[12:11] & tand[10] + | &tor[12:10] & tand[9] + | &tor[12:9] & tand[8] + | &tor[12:8] & co; + assign c[13] = tand[13] | tor[13] & tand[12] + | &tor[13:12] & tand[11] + | &tor[13:11] & tand[10] + | &tor[13:10] & tand[9] + | &tor[13:9] & tand[8] + | &tor[13:8] & co; + assign c[14] = tand[14] | tor[14] & tand[13] + | &tor[14:13] & tand[12] + | &tor[14:12] & tand[11] + | &tor[14:11] & tand[10] + | &tor[14:10] & tand[9] + | &tor[14:9] & tand[8] + | &tor[14:8] & co; + assign z[15:8] = a[15:8] ^ { 8 { b1[7] } } ^ { c[14:8], co }; + //initial $monitor($stime,, a,, b,, ci,, i,, c,, z,, co); +endmodule + +// ALU for general 8-bit arithmetic/logical + +module alu(c_in, im, a, b, inva, invb, reg_q_c, reg_q_h, s_and, s_or, s_xor, ec, i_daa, set, res, l, r, z, co); + input [7:0] im, a, b; + input inva, invb, c_in, reg_q_c, reg_q_h, s_and, s_or, s_xor, ec; + input i_daa, set, res, l, r; + output [7:0] z, co; + wire [7:0] b1, c; + wire [7:0] a1 = a ^ { 8 { inva } }; + wire daah = a1[3] & (a1[2] | a1[1]); + wire daac = a1[7] & (a1[6] | a1[5]) | a1[7] & a1[4] & daah; + wire daa0 = i_daa & (reg_q_h | daah); + wire daa1 = i_daa & (reg_q_c | daac); + wire [7:0] b0 = b & { 8 { ~i_daa } }; + assign b1[0] = (b0[0] ^ invb | set & im[0]) & ~(res & im[0]); + assign b1[1] = ((b0[1] | daa0) ^ invb | set & im[1]) & ~(res & im[1]); + assign b1[2] = ((b0[2] | daa0) ^ invb | set & im[2]) & ~(res & im[2]); + assign b1[3] = (b0[3] ^ invb | set & im[3]) & ~(res & im[3]); + assign b1[4] = (b0[4] ^ invb | set & im[4]) & ~(res & im[4]); + assign b1[5] = ((b0[5] | daa1) ^ invb | set & im[5]) & ~(res & im[5]); + assign b1[6] = ((b0[6] | daa1) ^ invb | set & im[6]) & ~(res & im[6]); + assign b1[7] = (b0[7] ^ invb | set & im[7]) & ~(res & im[7]); + wire [7:0] tand = a1 & b1; + wire [7:0] tor = a1 | b1; + wire rlc = l & im[0]; + wire rrc = r & im[1]; + wire rl = l & im[2]; + wire rr = r & im[3]; + wire sra = r & im[5]; + wire ci = c_in ^ invb; + assign z[0] = s_and & tand[0] | s_or & tor[0] | s_xor & (a1[0] ^ b1[0] ^ ci & ec) + | rlc & b1[7] | rl & reg_q_c | r & b1[1]; + assign c[0] = tand[0] | tor[0] & ci; + assign z[1] = s_and & tand[1] | s_or & tor[1] | s_xor & (a1[1] ^ b1[1] ^ c[0] & ec) + | l & b1[0] | r & b1[2]; + assign c[1] = tand[1] | tor[1] & tand[0] + | &tor[1:0] & ci; + assign z[2] = s_and & tand[2] | s_or & tor[2] | s_xor & (a1[2] ^ b1[2] ^ c[1] & ec) + | l & b1[1] | r & b1[3]; + assign c[2] = tand[2] | tor[2] & tand[1] + | &tor[2:1] & tand[0] + | &tor[2:0] & ci; + assign z[3] = s_and & tand[3] | s_or & tor[3] | s_xor & (a1[3] ^ b1[3] ^ c[2] & ec) + | l & b1[2] | r & b1[4]; + assign c[3] = tand[3] | tor[3] & tand[2] + | &tor[3:2] & tand[1] + | &tor[3:1] & tand[0] + | &tor[3:0] & ci; + assign z[4] = s_and & tand[4] | s_or & tor[4] | s_xor & (a1[4] ^ b1[4] ^ c[3] & ec) + | l & b1[3] | r & b1[5]; + assign c[4] = tand[4] | tor[4] & tand[3] + | &tor[4:3] & tand[2] + | &tor[4:2] & tand[1] + | &tor[4:1] & tand[0] + | &tor[4:0] & ci; + assign z[5] = s_and & tand[5] | s_or & tor[5] | s_xor & (a1[5] ^ b1[5] ^ c[4] & ec) + | l & b1[4] | r & b1[6]; + assign c[5] = tand[5] | tor[5] & tand[4] + | &tor[5:4] & tand[3] + | &tor[5:3] & tand[2] + | &tor[5:2] & tand[1] + | &tor[5:1] & tand[0] + | &tor[5:0] & ci; + assign z[6] = s_and & tand[6] | s_or & tor[6] | s_xor & (a1[6] ^ b1[6] ^ c[5] & ec) + | l & b1[5] | r & b1[7]; + assign c[6] = tand[6] | tor[6] & tand[5] + | &tor[6:5] & tand[4] + | &tor[6:4] & tand[3] + | &tor[6:3] & tand[2] + | &tor[6:2] & tand[1] + | &tor[6:1] & tand[0] + | &tor[6:0] & ci; + assign z[7] = s_and & tand[7] | s_or & tor[7] | s_xor & (a1[7] ^ b1[7] ^ c[6] & ec) + | l & b1[6] | rrc & b1[0] | rr & reg_q_c | sra & b1[7]; + assign c[7] = tand[7] | tor[7] & tand[6] + | &tor[7:6] & tand[5] + | &tor[7:5] & tand[4] + | &tor[7:4] & tand[3] + | &tor[7:3] & tand[2] + | &tor[7:2] & tand[1] + | &tor[7:1] & tand[0] + | &tor[7:0] & ci; + assign co = { i_daa ? daa1 ^ invb : c[7], c[6:0] }; + //initial $monitor($stime,, c_in, a1,, b1,, inva, invb, reg_q_c, reg_q_h, s_and, s_or, s_xor, ec, i_daa, set, res, l, r, z, co); +endmodule + +// A register: dual register + +module reg_a(a, load, set, regsel, clk, q); + input [7:0] a; + input load, set, regsel, clk; + output [7:0] q; + reg [7:0] q0, q1; + always @(posedge clk) begin + if (set) begin + q0 <= 8'b11111111; + q1 <= 8'b11111111; + end + else if (load) + if (regsel) q1 <= a; + else q0 <= a; + end + assign q = regsel ? q1 : q0; +endmodule + +// F register: dual register + +module reg_f(a, load, set, regsel, clk, q); + input [7:0] a; + input load, set, regsel, clk; + output [7:0] q; + reg [7:0] q0, q1; + always @(posedge clk) begin + if (set) begin + q0 <= 8'b11111111; + q1 <= 8'b11111111; + end + else if (load) + if (regsel) q1 <= a; + else q0 <= a; + end + assign q = regsel ? q1 : q0; +endmodule + +// simple register + +module reg_simple(a, load, clk, q); + input [7:0] a; + input load, clk; + output [7:0] q; + reg [7:0] q; + always @(posedge clk) begin + if (load) q <= a; + end +endmodule + +// simple register w/clear + +module reg_simplec(a, load, clr, clk, q); + input [7:0] a; + input load, clr, clk; + output [7:0] q; + reg [7:0] q; + always @(posedge clk) begin + if (clr) q <= 8'b00000000; + else if (load) q <= a; + end +endmodule + +// 2 input dual register + +module reg_dual2(a, a2, load, load2, regsel, clk, q); + input [7:0] a, a2; + input load, load2, regsel, clk; + output [7:0] q; + reg [7:0] q0 = 8'b00000000, q1 = 8'b00000000; + always @(posedge clk) begin + if (load) + if (regsel) q1 <= a; + else q0 <= a; + else if (load2) + if (regsel) q1 <= a2; + else q0 <= a2; + end + assign q = regsel ? q1 : q0; +endmodule + +// 2 input register + +module reg_2(a, a2, load, load2, clk, q); + input [7:0] a, a2; + input load, load2, clk; + output [7:0] q; + reg [7:0] q; + always @(posedge clk) begin + if (load) q <= a; + else if (load2) q <= a2; + end +endmodule + +// 2 input register w/ set + +module reg_2s(a, a2, load, load2, set, clk, q); + input [7:0] a, a2; + input load, load2, set, clk; + output [7:0] q; + reg [7:0] q; + always @(posedge clk) begin + if (set) q <= 8'b11111111; + else if (load) q <= a; + else if (load2) q <= a2; + end +endmodule + +// 3 input quad register + +module reg_quad3(a, a2, a3, load, load2, load3, regsel, i_dd, i_fd, clk, q); + input [7:0] a, a2, a3; + input load, load2, load3, regsel, i_dd, i_fd, clk; + output [7:0] q; + reg [7:0] q0 = 8'b00000000, q1 = 8'b00000000, qx = 8'b00000000, qy = 8'b00000000; + function [7:0] select; + input [1:0] sel; + input [31:0] a; + begin + case (sel) + 2'h0: select = a[31:24]; + 2'h1: select = a[23:16]; + 2'h2: select = a[15:8]; + 2'h3: select = a[7:0]; + endcase + end + endfunction + always @(posedge clk) begin + if (load) + if (i_dd) qx <= a; + else if (i_fd) qy <= a; + else if (regsel) q1 <= a; + else q0 <= a; + else if (load2) + if (i_dd) qx <= a2; + else if (i_fd) qy <= a2; + else if (regsel) q1 <= a2; + else q0 <= a2; + else if (load3) + if (i_dd) qx <= a3; + else if (i_fd) qy <= a3; + else if (regsel) q1 <= a3; + else q0 <= a3; + end + assign q = select({ i_dd | i_fd, ~i_dd & regsel | i_fd }, { q0, q1, qx, qy }); +endmodule + +// PCH register: 2 input register w/ increment, decrement, clear + +module reg_pch(a, a2, load, load2, count, dec, clr, clk, q); + input [7:0] a, a2; + input load, load2, count, dec, clr, clk; + output [7:0] q; + wire [6:0] c, qa; + reg [7:0] q; + wire notload = ~load & ~load2 & ~clr; + assign qa = q[6:0] ^ { 7 { dec } }; + assign c[0] = qa[0] & count; + assign c[1] = &qa[1:0] & count; + assign c[2] = &qa[2:0] & count; + assign c[3] = &qa[3:0] & count; + assign c[4] = &qa[4:0] & count; + assign c[5] = &qa[5:0] & count; + assign c[6] = &qa[6:0] & count; + wire [7:0] d = { 8 { load } } & a | { 8 { load2 } } & a2 | { 8 { notload } } & (q ^ { c, count }); + always @(posedge clk) q <= d; +endmodule + +// PCL register: 3 input register w/ increment, decrement, clear, load 66 + +module reg_pcl(a, a2, a3, load, load2, load3, count, dec, clr, load66, clk, q, co); + input [7:0] a, a2; + input [2:0] a3; + input load, load2, load3, count, dec, clr, load66, clk; + output [7:0] q; + output co; + wire [6:0] c; + wire [7:0] d, qa; + reg [7:0] q; + wire notload = ~load & ~load2 & ~load3 & ~load66 & ~clr; + assign qa = q ^ { 8 { dec } }; + assign c[0] = qa[0] & count; + assign c[1] = &qa[1:0] & count; + assign c[2] = &qa[2:0] & count; + assign c[3] = &qa[3:0] & count; + assign c[4] = &qa[4:0] & count; + assign c[5] = &qa[5:0] & count; + assign c[6] = &qa[6:0] & count; + assign co = &qa[7:0] & count; + assign d[0] = load & a[0] | load2 & a2[0] | notload & (q[0] ^ count); + assign d[1] = load & a[1] | load2 & a2[1] | notload & (q[1] ^ c[0]) | load66; + assign d[2] = load & a[2] | load2 & a2[2] | notload & (q[2] ^ c[1]) | load66; + assign d[3] = load & a[3] | load2 & a2[3] | notload & (q[3] ^ c[2]) | load3 & a3[0]; + assign d[4] = load & a[4] | load2 & a2[4] | notload & (q[4] ^ c[3]) | load3 & a3[1]; + assign d[5] = load & a[5] | load2 & a2[5] | notload & (q[5] ^ c[4]) | load3 & a3[2] | load66; + assign d[6] = load & a[6] | load2 & a2[6] | notload & (q[6] ^ c[5]) | load66; + assign d[7] = load & a[7] | load2 & a2[7] | notload & (q[7] ^ c[6]); + always @(posedge clk) q <= d; +endmodule + +// R register: up counter + +module reg_r(a, load, count, clr, clk, q); + input [7:0] a; + input load, count, clr, clk; + output [7:0] q; + reg [7:0] q; + always @(posedge clk) + if (clr) q <= 8'b00000000; + else if (load) q <= a; + else if (count) q[6:0] <= q[6:0] + 1; +endmodule + diff --git a/Sharp -MZ-80K_MiST/rtl/hq2x.sv b/Sharp -MZ-80K_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Sharp -MZ-80K_MiST/rtl/i8253.v b/Sharp -MZ-80K_MiST/rtl/i8253.v new file mode 100644 index 00000000..72e2b77d --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/i8253.v @@ -0,0 +1,158 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 09:58:45 02/25/2008 +// Design Name: +// Module Name: i8253 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module i8253(reset, clk, addr, data_out, data_in, cs, rd, wr, clk0, clk1, clk2, out0, out1, out2); + input reset; + input clk; + input [1:0] addr; + output[7:0] data_out; + input [7:0] data_in; + input cs, rd, wr; + input clk0, clk1, clk2; + output out0, out1, out2; + wire [1:0] addr; + wire [7:0] data_out, data_in; + wire cs, rd, wr; + wire clk0, clk1, clk2; + wire out0, out1, out2; + + reg [7:0] mode0, mode1, mode2; + reg [15:0] max0, max1, max2; + reg [15:0] count0 = 0, count1 = 0, count2 = 0; + reg signal0 = 0, signal1 = 0, signal2 = 0; + reg read_hl0, read_hl1, read_hl2; + reg write_hl0, write_hl1, write_hl2; + reg [7:0] data; + + always @(posedge clk or posedge reset) begin + if ( reset ) begin + mode0 <= 8'h00; + mode1 <= 8'h00; + mode2 <= 8'h00; + max0 <= 16'd1; + max1 <= 16'd1; + max2 <= 16'd1; + write_hl0 <= 1'b0; + write_hl1 <= 1'b0; + write_hl2 <= 1'b0; + read_hl0 <= 1'b0; + read_hl1 <= 1'b0; + read_hl2 <= 1'b0; + end else if ( cs ) begin + if ( addr == 2'd0 & wr ) begin + write_hl0 <= ( mode0[5:4] == 2'b00 | mode0[5:4] == 2'b11 ) ? ~write_hl0: write_hl0; + if ( ((mode0[5:4] == 2'b00 | mode0[5:4] == 2'b11) & write_hl0) | mode0[5:4] == 2'b10 ) + max0[15:8] <= data_in; + else + max0[7:0] <= data_in; + end else if ( addr == 2'd1 & wr ) begin + write_hl1 <= ( mode1[5:4] == 2'b00 | mode1[5:4] == 2'b11 ) ? ~write_hl1: write_hl1; + if ( ((mode1[5:4] == 2'b00 | mode1[5:4] == 2'b11) & write_hl1) | mode1[5:4] == 2'b10 ) + max1[15:8] <= data_in; + else + max1[7:0] <= data_in; + end else if ( addr == 2'd2 & wr ) begin + write_hl2 <= ( mode2[5:4] == 2'b00 | mode2[5:4] == 2'b11 ) ? ~write_hl2: write_hl2; + if ( ((mode2[5:4] == 2'b00 | mode2[5:4] == 2'b11) & write_hl2) | mode2[5:4] == 2'b10 ) + max2[15:8] <= data_in; + else + max2[7:0] <= data_in; + end else if ( addr == 2'd3 & wr ) begin + if ( data_in[7:6] == 2'd0 ) begin + mode0 <= data_in; + read_hl0 <= data_in[5:4] == 2'b10 ? 1 : 0; + write_hl0 <= data_in[5:4] == 2'b10 ? 1 : 0; + end else if ( data_in[7:6] == 2'd1 ) begin + mode1 <= data_in; + read_hl1 <= data_in[5:4] == 2'b10 ? 1 : 0; + write_hl1 <= data_in[5:4] == 2'b10 ? 1 : 0; + end else if ( data_in[7:6] == 2'd2 ) begin + mode2 <= data_in; + read_hl2 <= data_in[5:4] == 2'b10 ? 1 : 0; + write_hl2 <= data_in[5:4] == 2'b10 ? 1 : 0; + end + end else if ( addr == 2'd0 & rd ) begin + read_hl0 <= ( mode0[5:4] == 2'b00 | mode0[5:4] == 2'b11 ) ? ~read_hl0: read_hl0; + data <= ~( ((mode0[5:4] == 2'b00 | mode0[5:4] == 2'b11 ) & read_hl0) | mode0[5:4] == 2'b10 ) ? count0[15:8] : count0[7:0]; + end else if ( addr == 2'd1 & rd ) begin + read_hl1 <= ( mode1[5:4] == 2'b00 | mode1[5:4] == 2'b11 ) ? ~read_hl1: read_hl1; + data <= ~( ((mode1[5:4] == 2'b00 | mode1[5:4] == 2'b11 ) & read_hl1) | mode1[5:4] == 2'b10 ) ? count1[15:8] : count1[7:0]; + end else if ( addr == 2'd2 & rd ) begin + read_hl2 <= ( mode2[5:4] == 2'b00 | mode2[5:4] == 2'b11 ) ? ~read_hl2: read_hl2; + data <= ~( ((mode2[5:4] == 2'b00 | mode2[5:4] == 2'b11 ) & read_hl2) | mode2[5:4] == 2'b10 ) ? count2[15:8] : count2[7:0]; + end + end + end + + always @(posedge clk0) begin + if ( count0 != 0 ) begin + count0 <= ( count0 <= max0 ) ? count0 - 1: max0; + if ( mode0[3:1] == 3'b000 | mode0[3:1] == 3'b001 ) // MODE0 + signal0 <= 0; + end else begin + if ( mode0[3:1] == 3'b000 | mode0[3:1] == 3'b001 ) begin // MODE0 + count0 <= max0; + signal0 <= 1; + end else begin + count0 <= max0; + signal0 <= ~signal0; + end + end + end + + always @(posedge clk1) begin + if ( count1 != 0 ) begin + count1 <= ( count1 <= max1 ) ? count1 - 1: max1; + if ( mode1[3:1] == 3'b000 | mode1[3:1] == 3'b001 ) // MODE0/1 + signal1 <= 0; + end else begin + if ( mode1[3:1] == 3'b000 | mode1[3:1] == 3'b001 ) begin // MODE0/1 + count1 <= max1; + signal1 <= 1; + end else begin + count1 <= max1; + signal1 <= ~signal1; + end + end + end + + always @(posedge clk2) begin + if ( count2 != 0 ) begin + count2 <= ( count2 <= max2 ) ? count2 - 1: max2; + if ( mode2[3:1] == 3'b000 | mode2[3:1] == 3'b001 ) // MODE0/1 + signal2 <= 0; + end else begin + if ( mode2[3:1] == 3'b000 | mode2[3:1] == 3'b001 ) begin // MODE0/1 + count2 <= max2; + signal2 <= 1; + end else begin + count2 <= max2; + signal2 <= ~signal2; + end + end + end + + assign out0 = signal0; + assign out1 = signal1; + assign out2 = signal2; + + assign data_out = data; + +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/keyboard.v b/Sharp -MZ-80K_MiST/rtl/keyboard.v new file mode 100644 index 00000000..ba7038b6 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/keyboard.v @@ -0,0 +1,82 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output reg[7:0] joystick +); + +reg [11:0] shift_reg = 12'hFFF; +wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]}; +wire [7:0] kcode = kdata[9:2]; +reg release_btn = 0; + +reg [7:0] code; +reg input_strobe = 0; + +always @(negedge clk) begin + reg old_reset = 0; + + old_reset <= reset; + + if(~old_reset & reset)begin + joystick <= 0; + end + + if(input_strobe) begin + case(code) + 'h16: joystick[1] <= ~release_btn; // 1 + 'h1E: joystick[2] <= ~release_btn; // 2 + + 'h75: joystick[4] <= ~release_btn; // arrow up + 'h72: joystick[5] <= ~release_btn; // arrow down + 'h6B: joystick[6] <= ~release_btn; // arrow left + 'h74: joystick[7] <= ~release_btn; // arrow right + + 'h29: joystick[0] <= ~release_btn; // Space +// 'h11: joystick[1] <= ~release_btn; // Left Alt +// 'h0d: joystick[2] <= ~release_btn; // Tab + 'h76: joystick[3] <= ~release_btn; // Escape + endcase + end +end + +always @(posedge clk) begin + reg [3:0] prev_clk = 0; + reg old_reset = 0; + reg action = 0; + + old_reset <= reset; + input_strobe <= 0; + + if(~old_reset & reset)begin + prev_clk <= 0; + shift_reg <= 12'hFFF; + end else begin + prev_clk <= {ps2_kbd_clk,prev_clk[3:1]}; + if(prev_clk == 1) begin + if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin + shift_reg <= 12'hFFF; + if (kcode == 8'he0) ; + // Extended key code follows + else if (kcode == 8'hf0) + // Release code follows + action <= 1; + else begin + // Cancel extended/release flags for next time + action <= 0; + release_btn <= action; + code <= kcode; + input_strobe <= 1; + end + end else begin + shift_reg <= kdata; + end + end + end +end +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/mist_io.v b/Sharp -MZ-80K_MiST/rtl/mist_io.v new file mode 100644 index 00000000..ad233a3b --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/mist_io.v @@ -0,0 +1,491 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + input ps2_caps_led, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output ioctl_wr, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] b_data; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; +assign ypbpr = but_sw[5]; + +wire [7:0] spi_dout = { sbuf, SPI_DI}; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1}; + +// drive MISO only when transmitting core id +always@(negedge SPI_SCK) begin + if(!CONF_DATA0) begin + // first byte returned is always core type, further bytes are + // command dependent + if(byte_cnt == 0) begin + spi_do <= core_type[~bit_cnt]; + + end else begin + case(cmd) + // reading config string + 8'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card status + 8'h16: begin + if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else spi_do <= 0; + end + + // reading sd card write data + 8'h18: + spi_do <= b_data[~bit_cnt]; + + // reading keyboard LED status + 8'h1f: + spi_do <= kbd_led[~bit_cnt]; + + default: + spi_do <= 0; + endcase + end + end +end + +reg b_wr2,b_wr3; +always @(negedge clk_sys) begin + b_wr3 <= b_wr2; + sd_buff_wr <= b_wr3; +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0) begin + b_wr2 <= 0; + bit_cnt <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + end else begin + b_wr2 <= 0; + + sbuf <= spi_dout[6:0]; + bit_cnt <= bit_cnt + 1'd1; + if(bit_cnt == 5) begin + if (byte_cnt == 0) sd_buff_addr <= 0; + if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1; + if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0; + end + + // finished reading command byte + if(bit_cnt == 7) begin + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= spi_dout; + + if(spi_dout == 8'h19) begin + sd_ack_conf <= 1; + sd_buff_addr <= 0; + end + if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin + sd_ack <= 1; + sd_buff_addr <= 0; + end + if(spi_dout == 8'h18) b_data <= sd_buff_din; + + mount_strobe <= 0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_dout; + 8'h02: joystick_0 <= spi_dout; + 8'h03: joystick_1 <= spi_dout; + + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_dout; + b_wr2 <= 1; + end + + 8'h18: b_data <= sd_buff_din; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= spi_dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1; + + // send image info + 8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout; + + // status, 32bit version + 8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout; + default: ; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + rclk <= 0; + + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // increase target address after write + if(rclk) addr <= addr + 1'd1; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + addr <= 0; + ioctl_download <= 1; + end else begin + addr_w <= addr; + ioctl_download <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + rclk <= 1; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +assign ioctl_wr = |ioctl_wrd; +reg [1:0] ioctl_wrd; + +always@(negedge clk_sys) begin + reg rclkD, rclkD2; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wrd<= {ioctl_wrd[0],1'b0}; + + if(rclkD & ~rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wrd <= 2'b11; + end +end + +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/monrom.qip b/Sharp -MZ-80K_MiST/rtl/monrom.qip new file mode 100644 index 00000000..381bc68d --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/monrom.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "monrom.v"] diff --git a/Sharp -MZ-80K_MiST/rtl/monrom.v b/Sharp -MZ-80K_MiST/rtl/monrom.v new file mode 100644 index 00000000..e1ff0617 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/monrom.v @@ -0,0 +1,184 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: monrom.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module monrom ( + address, + clock, + data, + rden, + wren, + q); + + input [14:0] address; + input clock; + input [7:0] data; + input rden; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri1 rden; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .rden_a (rden), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", +`ifdef NO_PLI + altsyncram_component.init_file = "80ktc.rif" +`else + altsyncram_component.init_file = "80ktc.hex" +`endif +, + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 32768, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 15, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "80ktc.hex" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "15" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "80ktc.hex" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL monrom.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL monrom.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL monrom.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL monrom.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL monrom_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL monrom_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Sharp -MZ-80K_MiST/rtl/mycom.v b/Sharp -MZ-80K_MiST/rtl/mycom.v new file mode 100644 index 00000000..7aed02a4 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/mycom.v @@ -0,0 +1,139 @@ + + +module mycom(CLK_50MHZ, BTN_NORTH,BTN_EAST,BTN_SOUTH, BTN_WEST, + VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC, Pix_ce, + PS2_CLK, PS2_DATA, Turbo, + SW,LED,TP1); + input CLK_50MHZ; + input BTN_NORTH,BTN_EAST,BTN_SOUTH,BTN_WEST; + input PS2_CLK, PS2_DATA; + input Turbo; + output VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC; + output Pix_ce; + input [3:0] SW; + output [7:0] LED; + output TP1; +// �N���b�N�̐��� + wire CLK_CPU; + reg CLK_2M = 0, CLK_31250 = 0; + reg [4:0] count_2M = 0; + reg [10:0] count_31250 = 0; + reg [32:0] clk_count = 0; + always @(posedge CLK_50MHZ) begin + clk_count <= clk_count + 1; + end + always @(posedge CLK_50MHZ) begin + count_2M <= count_2M >= 13 ? 0 : count_2M + 1; + count_31250 <= count_31250 >= 800 ? 0 : count_31250 + 1; + CLK_2M <= count_2M == 0 ? ~CLK_2M : CLK_2M; + CLK_31250 <= count_31250 == 0 ? ~CLK_31250 : CLK_31250; + end + assign CLK_CPU = Turbo ? clk_count[2] : clk_count[3]; +// assign CLK_CPU = clk_count[2]; // 6MHZ +// assign CLK_CPU = clk_count[3]; // 3MHZ + +// reset���H + wire reset; + reg reset1 = 1, reset2 = 1; + always @( posedge CLK_CPU ) begin + reset1 <= BTN_EAST; + reset2 <= reset1; + end + assign reset = reset1 | reset2; + +// Z80��WIRE���` + wire [15:0] cpu_addr; + wire [7:0] cpu_data_in, cpu_data_out; + wire mreq, iorq, rd, wr, busreq, busack, intack; + wire start, waitreq; + +// I/O�̎�� +wire [15:0]io_led,io_e000,io_e001,io_e002,io_8253,io_e008; + assign io_led = (cpu_addr[15:0] == 16'he300) & mreq; + assign io_e000 = (cpu_addr[15:0] == 16'he000) & mreq; + assign io_e001 = (cpu_addr[15:0] == 16'he001) & mreq; + assign io_e002 = (cpu_addr[15:0] == 16'he002) & mreq; + assign io_8253 = (cpu_addr[15:2] == 14'b11100000000001) & mreq; + assign io_e008 = (cpu_addr[15:0] == 16'he008) & mreq; + wire [7:0] io_switch = {BTN_NORTH,BTN_EAST,BTN_SOUTH, + BTN_WEST,SW[3:0]}; + reg [7:0] led_buf; + reg [7:0] sound_buf; + reg [3:0] key_no; + reg speaker_enable; + always @(posedge CLK_CPU or posedge reset) begin + if (reset) begin + led_buf <= 0; + sound_buf <= 0; + key_no <= 0; + speaker_enable <= 0; + end else begin + if ( io_led & wr ) begin + led_buf <= cpu_data_out; + end else if (io_e000 & wr ) begin + key_no <= cpu_data_out[3:0]; + end else if (io_e008 & wr ) begin + speaker_enable <= cpu_data_out[0]; + end + end + end + assign LED = led_buf; + +// Z80�̎�� + assign waitreq = start; + wire out0, out1, out2; + fz80 z80(.data_in(cpu_data_in), .data_out(cpu_data_out), + .reset_in(reset), .clk(CLK_CPU), + .mreq(mreq), .iorq(iorq), .rd(rd), .wr(wr), + .adr(cpu_addr), .waitreq(waitreq), + .nmireq(0), .intreq(out2 & 0), .busreq(busreq), .busack_out(busack), + .start(start)); +// 8253�̎�� (CLK0=2M CLK1=31.25K CLK2=OUT1) + wire [7:0] i8253_data_out; + i8253 i8253_1(.reset(reset), .clk(CLK_CPU), .addr(cpu_addr[1:0]), .data_out(i8253_data_out), .data_in(cpu_data_out), + .cs(io_8253 & ~start), .rd(rd), .wr(wr), + .clk0(CLK_2M), .clk1(CLK_31250), .clk2(out1), + .out0(out0), .out1(out1), .out2(out2) ); + +// KEYBOARD�̎�� + wire [7:0] ps2_data; + ps2 ps2_1(.clk(CLK_50MHZ), .reset(reset), .ps2_clk(PS2_CLK), .ps2_data(PS2_DATA), .cs(io_e001 & rd), .rd(rd), .addr(key_no), .data(ps2_data)); + +// MAIN RAM�̎�� + wire ram_select = (( cpu_addr[15:15] == 1'b0 || cpu_addr[15:12] == 4'b1000) & mreq) & ~busack; + wire ram_en, ram_we; + wire [7:0] ram_data_out, ram_data_in; + + monrom monrom(.address(cpu_addr),.clock(CLK_50MHZ),.data(ram_data_in), + .q(ram_data_out),.rden(ram_en),.wren(ram_we)); + assign ram_en = ram_select; + assign ram_we = wr; + assign ram_data_in = cpu_data_out; + +// VRAM�̎�� + wire vram_select = ((cpu_addr[15:11] == 5'b11010) & mreq) | busack; + wire [11:0] vram_addr; + wire vram_rd, vram_wr; + wire [7:0] vram_data, vram_data_in; + vram vram(.address(vram_addr),.clock(CLK_50MHZ), + .data(vram_data_in),.q(vram_data),.rden(vram_select),.wren(vram_wr)); + assign vram_data_in = (vram_select & wr) ? cpu_data_out : 8'hzz; + +// VGA�̎�� + wire [11:0] vga_addr; + vga vga1(.CLK_50MHZ(CLK_50MHZ), .VGA_RED(VGA_RED), .VGA_GREEN(VGA_GREEN), .VGA_BLUE(VGA_BLUE), + .VGA_HSYNC(VGA_HSYNC), .VGA_VSYNC(VGA_VSYNC), .Pix_ce(Pix_ce), + .VGA_ADDR(vga_addr), .VGA_DATA(vram_data), .BUS_REQ(busreq), .BUS_ACK(busack)); + assign vram_addr[11:0] = busack ? vga_addr[11:0] : cpu_addr[11:0]; + assign vram_rd = busack | rd; + assign vram_wr = busack ? 1'b0 : wr; +// Memory�A�N�Z�X + assign cpu_data_in = ( io_led & rd ) ? io_switch : + ( io_e001 & rd ) ? ps2_data : + ( io_e002 & rd ) ? {VGA_VSYNC, clk_count[24], 6'b0000000} : + ( io_8253 & rd ) ? i8253_data_out : + ( io_e008 & rd ) ? {7'b0000000, clk_count[19]} : // MUSIC���Ȃǂ�WAIT�ŏd�v + (vram_select & rd) ? vram_data : + (ram_select & rd) ? ram_data_out: 8'hzz; + assign TP1 = speaker_enable & out0; +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/mz80k.sv b/Sharp -MZ-80K_MiST/rtl/mz80k.sv new file mode 100644 index 00000000..d99dec2e --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/mz80k.sv @@ -0,0 +1,136 @@ +module mz80k +( + output LED, + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + output AUDIO_L, + output AUDIO_R, + input SPI_SCK, + output SPI_DO, + input SPI_DI, + input SPI_SS2, + input SPI_SS3, + input CONF_DATA0, + input CLOCK_27 +); + +`include "rtl\build_id.v" + +localparam CONF_STR = { + "MZ80K;;", + "O2,CPU CLOCK ,6MHZ,3MHZ;", + "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", + "T6,Reset;", + "V,v1.00.",`BUILD_DATE +}; + + +wire clk_sys; +wire [31:0] status; +wire [1:0] buttons; +wire [1:0] switches; +wire [7:0] kbjoy; +wire [7:0] joystick_0; +wire [7:0] joystick_1; +wire scandoubler_disable; +wire ypbpr; +wire ps2_kbd_clk, ps2_kbd_data; +wire [7:0] audio; +//assign LED = 1; + +wire hblank, vblank; +wire ce_vid; +wire hs, vs; +wire r,g,b; + + +pll pll +( + .inclk0(CLOCK_27), + .c0(clk_sys) + ); + +video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer +( + .clk_sys(clk_sys), + .ce_pix(ce_vid), + .ce_pix_actual(ce_vid), + .SPI_SCK(SPI_SCK), + .SPI_SS3(SPI_SS3), + .SPI_DI(SPI_DI), + .R({r,r,r}), + .G({g,g,g}), + .B({b,b,b}), + .HSync(hs), + .VSync(vs), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .scandoubler_disable(1),//scandoubler_disable), + .scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}), + .hq2x(status[4:3]==1), + .ypbpr_full(1), + .line_start(0), + .mono(0) +); + + +mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io +( + .clk_sys (clk_sys ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoubler_disable(scandoubler_disable), + .ypbpr (ypbpr ), + .ps2_kbd_clk (ps2_kbd_clk ), + .ps2_kbd_data (ps2_kbd_data ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) +); + +mycom mycom +( + .CLK_50MHZ(clk_sys), + .BTN_NORTH(), + .BTN_EAST((status[0] | status[6] | buttons[1])),//reset + .BTN_SOUTH(), + .BTN_WEST(), + .VGA_RED(r), + .VGA_GREEN(g), + .VGA_BLUE(b), + .VGA_HSYNC(hs), + .VGA_VSYNC(vs), + .Turbo(status[2]), + .Pix_ce(ce_vid), + .PS2_CLK(ps2_kbd_clk), + .PS2_DATA(ps2_kbd_data), + .SW(), + .LED(LED), + .TP1(audio) + ); + + + +dac dac +( + .clk_i(clk_sys), + .res_n_i(1), + .dac_i(audio), + .dac_o(AUDIO_L) + ); + +assign AUDIO_R = AUDIO_L; + +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/osd.v b/Sharp -MZ-80K_MiST/rtl/osd.v new file mode 100644 index 00000000..c62c10af --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/osd.v @@ -0,0 +1,179 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [7:0] osd_byte; +always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; + +wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/pll.qip b/Sharp -MZ-80K_MiST/rtl/pll.qip new file mode 100644 index 00000000..48665362 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Sharp -MZ-80K_MiST/rtl/pll.vhd b/Sharp -MZ-80K_MiST/rtl/pll.vhd new file mode 100644 index 00000000..73463402 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/pll.vhd @@ -0,0 +1,350 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.0 Build 162 10/23/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire4_bv(0 DOWNTO 0) <= "0"; + sub_wire4 <= To_stdlogicvector(sub_wire4_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + sub_wire2 <= inclk0; + sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 27, + clk0_duty_cycle => 50, + clk0_multiply_by => 50, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 37037, + intended_device_family => "Cyclone III", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire3, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Sharp -MZ-80K_MiST/rtl/ps2.v b/Sharp -MZ-80K_MiST/rtl/ps2.v new file mode 100644 index 00000000..a61eee0c --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/ps2.v @@ -0,0 +1,283 @@ +module ps2(clk, reset, + ps2_clk, ps2_data, + cs, rd, addr, data); + + input clk,reset; + input ps2_clk, ps2_data; + input cs, rd; + input [7:0] addr; + output [7:0] data; + + wire clk, reset; + wire ps2_clk, ps2_data; + wire cs, rd; + wire [7:0] addr; + reg [7:0] data; + + reg [7:0]key_tbl0 = 8'b11111111, + key_tbl1 = 8'b11111111, + key_tbl2 = 8'b11111111, + key_tbl3 = 8'b11111111, + key_tbl4 = 8'b11111111, + key_tbl5 = 8'b11111111, + key_tbl6 = 8'b11111111, + key_tbl7 = 8'b11111111, + key_tbl8 = 8'b11111111, + key_tbl9 = 8'b11111111, + key_tbla = 8'b11111111, + key_tblb = 8'b11111111, + key_tblc = 8'b11111111, + key_tbld = 8'b11111111, + key_tble = 8'b11111111; + reg key_f0 = 1'b0; + reg key_e0 = 1'b0; + + // + // I/O(0-9) read + // + always @(posedge clk ) begin + if ( cs & rd ) begin + begin + case (addr[3:0]) + 4'h0: data <= key_tbl0; + 4'h1: data <= key_tbl1; + 4'h2: data <= key_tbl2; + 4'h3: data <= key_tbl3; + 4'h4: data <= key_tbl4; + 4'h5: data <= key_tbl5; + 4'h6: data <= key_tbl6; + 4'h7: data <= key_tbl7; + 4'h8: data <= key_tbl8; + 4'h9: data <= key_tbl9; + 4'ha: data <= key_tbla; + 4'hb: data <= key_tblb; + 4'hc: data <= key_tblc; + 4'hd: data <= key_tbld; + 4'he: data <= key_tble; + default: data <= 8'hzz; + endcase + end + end + end + + // + // PS/2���͏������ + // + wire dten; + wire [7:0] kdata; + ps2_recieve ps2_recieve1(.clk(clk), .reset(reset), + .ps2_clk(ps2_clk), .ps2_data(ps2_data), + .dten(dten), .kdata(kdata)); + + + // + // + // + always @(posedge clk or posedge reset) begin + if( reset ) begin + key_e0 <= 1'b0; + key_f0 <= 1'b0; + key_tbl0 <= 8'b11111111; + key_tbl1 <= 8'b11111111; + key_tbl2 <= 8'b11111111; + key_tbl3 <= 8'b11111111; + key_tbl4 <= 8'b11111111; + key_tbl5 <= 8'b11111111; + key_tbl6 <= 8'b11111111; + key_tbl7 <= 8'b11111111; + key_tbl8 <= 8'b11111111; + key_tbl9 <= 8'b11111111; + end else if ( dten ) begin + case ( kdata ) + 8'h70: begin + if ( key_e0 ) begin + key_tbl8[1] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // INS (E0) + end else begin + key_tbl1[4] <= key_f0; key_f0 <= 1'b0; // 0 + end + end + 8'h69: begin + if ( key_e0 ) begin + key_f0 <= 1'b0; key_e0 <= 1'b0; // END (E0) + end else begin + key_tbl0[0] <= key_f0; key_f0 <= 1'b0; // 1 + end + end + 8'h72: begin + if ( key_e0 ) begin + key_tbl9[2] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // DOWN (E0) + end else begin + key_tbl1[0] <= key_f0; key_f0 <= 1'b0; // 2 + end + end + 8'h7A: begin + if ( key_e0 ) begin + key_tble[0] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // PGDN (E0) + end else begin + key_tbl0[1] <= key_f0; key_f0 <= 1'b0; // 3 + end + end + 8'h6B: begin + if ( key_e0 ) begin + key_tbl8[3] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // LEFT (E0) + end else begin + key_tbl1[1] <= key_f0; key_f0 <= 1'b0; // 4 + end + end + 8'h73: begin key_tbl0[2] <= key_f0; key_f0 <= 1'b0; end // 5 + 8'h74: begin + if ( key_e0 ) begin + key_tbl8[3] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // RIGHT (E0) + end else begin + key_tbl1[2] <= key_f0; key_f0 <= 1'b0; // 6 + end + end + 8'h6C: begin + if ( key_e0 ) begin + key_tbl8[0] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // HOME (E0) + end else begin + key_tbl0[3] <= key_f0; key_f0 <= 1'b0; // 7 + end + end + 8'h75: begin + if ( key_e0 ) begin + key_tbl9[2] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // UP (E0) + end else begin + key_tbl1[3] <= key_f0; key_f0 <= 1'b0; // 8 + end + end + 8'h7D: begin + if ( key_e0 ) begin + key_tble[0] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // PGUP (E0) + end else begin + key_tbl0[4] <= key_f0; key_f0 <= 1'b0; // 9 + end + end + 8'h7C: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // * + 8'h79: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // + + 8'h7B: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // = + 8'h7C: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // , + 8'h71: begin + if ( key_e0 ) begin + key_tbl8[1] <= key_f0; key_tblc[7] <= key_f0; key_f0 <= 1'b0; key_e0 <= 1'b0; // DEL (E0) + end else begin + key_tble[0] <= key_f0; key_f0 <= 1'b0; // . + end + end + 8'h71: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // . + 8'h5A: begin key_tbl8[4] <= key_f0; key_f0 <= 1'b0; end // RET E0 + 8'h54: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // @ + 8'h1C: begin key_tbl4[0] <= key_f0; key_f0 <= 1'b0; end // A + 8'h32: begin key_tbl6[2] <= key_f0; key_f0 <= 1'b0; end // B + 8'h21: begin key_tbl6[1] <= key_f0; key_f0 <= 1'b0; end // C + 8'h23: begin key_tbl4[1] <= key_f0; key_f0 <= 1'b0; end // D + 8'h24: begin key_tbl2[1] <= key_f0; key_f0 <= 1'b0; end // E + 8'h2B: begin key_tbl5[1] <= key_f0; key_f0 <= 1'b0; end // F + 8'h34: begin key_tbl4[2] <= key_f0; key_f0 <= 1'b0; end // G + 8'h33: begin key_tbl5[2] <= key_f0; key_f0 <= 1'b0; end // H + 8'h43: begin key_tbl3[3] <= key_f0; key_f0 <= 1'b0; end // I + 8'h3B: begin key_tbl4[3] <= key_f0; key_f0 <= 1'b0; end // J + 8'h42: begin key_tbl5[3] <= key_f0; key_f0 <= 1'b0; end // K + 8'h4B: begin key_tbl4[4] <= key_f0; key_f0 <= 1'b0; end // L + 8'h3A: begin key_tbl6[3] <= key_f0; key_f0 <= 1'b0; end // M + 8'h31: begin key_tbl7[2] <= key_f0; key_f0 <= 1'b0; end // N + 8'h44: begin key_tbl2[4] <= key_f0; key_f0 <= 1'b0; end // O + 8'h4D: begin key_tbl3[4] <= key_f0; key_f0 <= 1'b0; end // P + 8'h15: begin key_tbl2[0] <= key_f0; key_f0 <= 1'b0; end // Q + 8'h2D: begin key_tbl3[1] <= key_f0; key_f0 <= 1'b0; end // R + 8'h1B: begin key_tbl5[0] <= key_f0; key_f0 <= 1'b0; end // S + 8'h2C: begin key_tbl2[2] <= key_f0; key_f0 <= 1'b0; end // T + 8'h3C: begin key_tbl2[3] <= key_f0; key_f0 <= 1'b0; end // U + 8'h2A: begin key_tbl7[1] <= key_f0; key_f0 <= 1'b0; end // V + 8'h1D: begin key_tbl3[0] <= key_f0; key_f0 <= 1'b0; end // W + 8'h22: begin key_tbl7[0] <= key_f0; key_f0 <= 1'b0; end // X + 8'h35: begin key_tbl3[2] <= key_f0; key_f0 <= 1'b0; end // Y + 8'h1A: begin key_tbl6[0] <= key_f0; key_f0 <= 1'b0; end // Z + 8'h5B: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // [ + 8'h6A: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // \ + 8'h5D: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // ] + 8'h55: begin key_tbl5[5] <= key_f0; key_f0 <= 1'b0; end // ^ + 8'h4E: begin key_tbl2[5] <= key_f0; key_f0 <= 1'b0; end // = + 8'h45: begin key_tbl1[4] <= key_f0; key_f0 <= 1'b0; end // 0 + 8'h16: begin key_tbl0[0] <= key_f0; key_f0 <= 1'b0; end // 1 + 8'h1E: begin key_tbl1[0] <= key_f0; key_f0 <= 1'b0; end // 2 + 8'h26: begin key_tbl0[1] <= key_f0; key_f0 <= 1'b0; end // 3 + 8'h25: begin key_tbl1[1] <= key_f0; key_f0 <= 1'b0; end // 4 + 8'h2E: begin key_tbl0[2] <= key_f0; key_f0 <= 1'b0; end // 5 + 8'h36: begin key_tbl1[2] <= key_f0; key_f0 <= 1'b0; end // 6 + 8'h3D: begin key_tbl0[3] <= key_f0; key_f0 <= 1'b0; end // 7 + 8'h3E: begin key_tbl1[3] <= key_f0; key_f0 <= 1'b0; end // 8 + 8'h46: begin key_tbl0[4] <= key_f0; key_f0 <= 1'b0; end // 9 + 8'h52: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // : + 8'h4C: begin key_tbl5[4] <= key_f0; key_f0 <= 1'b0; end // ; + 8'h41: begin key_tbl7[3] <= key_f0; key_f0 <= 1'b0; end // < , + 8'h49: begin key_tbl6[4] <= key_f0; key_f0 <= 1'b0; end // > . + 8'h4A: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // ? + 8'h51: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // _ + 8'h11: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // GRPH + 8'h13: begin key_tbl6[5] <= key_f0; key_f0 <= 1'b0; end // �J�i + 8'h12: begin key_tbl8[0] <= ( key_f0 | key_e0 ) & (key_tbl8[0] | ~key_e0 ); key_f0 <= 1'b0; key_e0 <= 1'b0; end // SHIFT + 8'h59: begin key_tbl8[5] <= ( key_f0 | key_e0 ) & (key_tbl8[5] | ~key_e0 ); key_f0 <= 1'b0; key_e0 <= 1'b0; end // SHIFT + 8'h14: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // CTRL + 8'h77: begin key_tbl9[3] <= key_f0; key_f0 <= 1'b0; end // STOP (E1) + 8'h7E: begin key_tbl9[3] <= key_f0; key_f0 <= 1'b0; end // STOP (SCROLL KEY) + 8'h05: begin key_tble[0] <= key_f0; key_tblc[0] <= key_f0; key_f0 <= 1'b0; end // F1 + 8'h06: begin key_tble[0] <= key_f0; key_tblc[1] <= key_f0; key_f0 <= 1'b0; end // F2 + 8'h04: begin key_tble[0] <= key_f0; key_tblc[2] <= key_f0; key_f0 <= 1'b0; end // F3 + 8'h0C: begin key_tble[0] <= key_f0; key_tblc[3] <= key_f0; key_f0 <= 1'b0; end // F4 + 8'h03: begin key_tble[0] <= key_f0; key_tblc[4] <= key_f0; key_f0 <= 1'b0; end // F5 + 8'h29: begin key_tbl9[1] <= key_f0; key_tbld[7] <= key_f0; key_f0 <= 1'b0; end // SPACE + 8'h76: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // ESC + 8'h0d: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // TAB + 8'h58: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // CAPS + 8'h66: begin key_tbl8[1] <= key_f0; key_f0 <= 1'b0; end // BS + 8'h0b: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F6 + 8'h83: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F7 + 8'h0a: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F8 + 8'h01: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F9 + 8'h09: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // F10 + 8'he0: key_e0 <= 1'b1; + 8'hf0: key_f0 <= 1'b1; + default: begin key_e0 <= 1'b0; key_f0 <= 1'b0; end + endcase + end + end + +endmodule + +module ps2_recieve(clk, reset, + ps2_clk, ps2_data, + dten, kdata); + + input clk,reset; + input ps2_clk, ps2_data; + output dten; + output [7:0] kdata; + + wire clk, reset; + wire ps2_clk, ps2_data; + reg dten; + reg [7:0] kdata; + + reg [10:0] key_data; + reg [3:0] clk_data; + + always @(posedge clk or posedge reset) begin + if( reset ) begin + key_data <= 11'b11111111111; + dten <= 1'b0; + end else begin + clk_data <= {clk_data[2:0], ps2_clk}; + if ( clk_data == 4'b0011 ) + key_data <= {ps2_data, key_data[10:1]}; + if ( !key_data[0] & key_data[10] ) begin + dten <= 1'b1; + kdata <= key_data[8:1]; + key_data <= 11'b11111111111; + end else + dten <= 1'b0; + end + + end + +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/rom/80KCG.ROM b/Sharp -MZ-80K_MiST/rtl/rom/80KCG.ROM new file mode 100644 index 00000000..6598e217 Binary files /dev/null and b/Sharp -MZ-80K_MiST/rtl/rom/80KCG.ROM differ diff --git a/Sharp -MZ-80K_MiST/rtl/rom/80ktc.rom b/Sharp -MZ-80K_MiST/rtl/rom/80ktc.rom new file mode 100644 index 00000000..c9c38c2c Binary files /dev/null and b/Sharp -MZ-80K_MiST/rtl/rom/80ktc.rom differ diff --git a/Sharp -MZ-80K_MiST/rtl/scandoubler.v b/Sharp -MZ-80K_MiST/rtl/scandoubler.v new file mode 100644 index 00000000..e85cba43 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/scandoubler.v @@ -0,0 +1,183 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/sound.v b/Sharp -MZ-80K_MiST/rtl/sound.v new file mode 100644 index 00000000..921ad339 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/sound.v @@ -0,0 +1,49 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 08:54:34 02/19/2008 +// Design Name: +// Module Name: clock_gen +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module sound(CLK_50MHZ, SW, TP1); + input CLK_50MHZ; + input [7:0] SW; + output TP1; + reg [14:0] count = 0; + reg [14:0] count2 = 1; + reg CLK = 0; + wire TP1; + + always @(posedge CLK_50MHZ) + begin + count <= count + 1; + end + + always @(posedge count[12]) + begin + if ( count2 >= SW ) + begin + CLK <= SW != 0 ? ~CLK: CLK; + count2 <= 1; + end else + begin + count2 <= count2 + 1; + end + end + + assign TP1 = CLK; + +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/vga.v b/Sharp -MZ-80K_MiST/rtl/vga.v new file mode 100644 index 00000000..38e585a1 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/vga.v @@ -0,0 +1,72 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:27:35 02/19/2008 +// Design Name: +// Module Name: vga +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module vga(CLK_50MHZ, VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC, Pix_ce, + VGA_ADDR, VGA_DATA, BUS_REQ, BUS_ACK); + input CLK_50MHZ; + output VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC; + output Pix_ce; + output [11:0] VGA_ADDR; + input [7:0] VGA_DATA; + output BUS_REQ; + input BUS_ACK; + reg [9:0] x = 0; + reg [9:0] y = 0; + reg [1:0] counter = 0; + wire display; + wire [9:0] gx, gy; // �O���t�B�b�N��W(0,0)-(639,399) + + always @(posedge CLK_50MHZ) begin + counter <= counter + 1; + end + assign Pix_ce = counter[0]; + assign gx = x - 144; // (96+48) + assign gy = y - 71; // (2+29+40) + always @(posedge counter[0]) begin + if ( x < 800 ) + begin + x <= x + 1; + end else begin + x <= 0; + if ( y < 521 ) + y <= y + 1; + else + y <= 0; + end + end +// CGROM�̎�� + wire [7:0] cgrom_data; + wire [11:0] cgrom_addr; +cgrom cgrom(.address(cgrom_addr), .clock(CLK_50MHZ), .q(cgrom_data), .rden(1'b1)); + wire [5:0] cx, cy; // �L�����N�^�[��W�֕ϊ�(0,0)-(79,24) + assign cx = gx >> 4; // �P�U�Ŋ��� + assign cy = gy >> 4; // �P�U�Ŋ��� + assign VGA_ADDR = (cy * 40) + cx; + assign cgrom_addr = {VGA_DATA, gy[3:1]}; + +// assign BUS_REQ = ( (96+48-8) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400)); + assign BUS_REQ = ( (96+48-16) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400)); + assign display =( (96+48) <= x & x < (96+48+640) ) & ( ( 2+29+40) <= y & y < (2+29+40+400)); + assign VGA_RED = 0; //display ? (cgrom_data[7-((gx>>1) & 7)]) : 0; + assign VGA_GREEN = display & (y[0] & 1) ? cgrom_data[7-(((gx+15)>>1) & 7)] : 0; + assign VGA_BLUE = 0; //display ? (cgrom_data[7-((gx>>1) & 7)]) : 0; + assign VGA_HSYNC = x < 96 ? 0 : 1; + assign VGA_VSYNC = y < 2 ? 0 : 1; +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/video_mixer.sv b/Sharp -MZ-80K_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..04cfd4ba --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/video_mixer.sv @@ -0,0 +1,242 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoubler_disable, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); +wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); +wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoubler_disable ? HSync : hs_sd); +wire vs = (scandoubler_disable ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Sharp -MZ-80K_MiST/rtl/vram.qip b/Sharp -MZ-80K_MiST/rtl/vram.qip new file mode 100644 index 00000000..c2a4bc54 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/vram.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "vram.v"] diff --git a/Sharp -MZ-80K_MiST/rtl/vram.v b/Sharp -MZ-80K_MiST/rtl/vram.v new file mode 100644 index 00000000..54555898 --- /dev/null +++ b/Sharp -MZ-80K_MiST/rtl/vram.v @@ -0,0 +1,177 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: vram.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.1.0 Build 162 10/23/2013 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module vram ( + address, + clock, + data, + rden, + wren, + q); + + input [11:0] address; + input clock; + input [7:0] data; + input rden; + input wren; + output [7:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri1 rden; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .rden_a (rden), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 4096, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 12, + altsyncram_component.width_a = 8, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "12" +// Retrieval info: PRIVATE: WidthData NUMERIC "8" +// Retrieval info: PRIVATE: rden NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL vram.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL vram_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/Sharp -MZ-80K_MiST/snapshot/mz80k.rbf b/Sharp -MZ-80K_MiST/snapshot/mz80k.rbf new file mode 100644 index 00000000..629f2f13 Binary files /dev/null and b/Sharp -MZ-80K_MiST/snapshot/mz80k.rbf differ