diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/SuperBreakout.qsf b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/SuperBreakout.qsf
index 3bca0b06..ff0af0f9 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/SuperBreakout.qsf	
+++ b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/SuperBreakout.qsf	
@@ -44,30 +44,6 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16  OCTOBER 10, 20
 set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/super_breakout_mist.sv
-set_global_assignment -name VHDL_FILE rtl/super_breakout.vhd
-set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
-set_global_assignment -name VHDL_FILE rtl/sync.vhd
-set_global_assignment -name VHDL_FILE rtl/playfield.vhd
-set_global_assignment -name VHDL_FILE rtl/motion.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv
-set_global_assignment -name VERILOG_FILE rtl/pll.v
-set_global_assignment -name VHDL_FILE rtl/audio.vhd
-set_global_assignment -name VHDL_FILE rtl/paddle.vhd
-set_global_assignment -name VHDL_FILE rtl/IO.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/joy2quad.sv
-set_global_assignment -name VHDL_FILE rtl/quadrature_decoder.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -171,4 +147,20 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(super_breakout_mist)
 # -------------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/super_breakout_mist.sv
+set_global_assignment -name VHDL_FILE rtl/super_breakout.vhd
+set_global_assignment -name VHDL_FILE rtl/sync.vhd
+set_global_assignment -name VHDL_FILE rtl/playfield.vhd
+set_global_assignment -name VHDL_FILE rtl/motion.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VHDL_FILE rtl/audio.vhd
+set_global_assignment -name VHDL_FILE rtl/paddle.vhd
+set_global_assignment -name VHDL_FILE rtl/IO.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/joy2quad.sv
+set_global_assignment -name VHDL_FILE rtl/quadrature_decoder.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/Char_LSB.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/Char_LSB.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/Char_MSB.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/Char_MSB.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65.vhd b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65.vhd
deleted file mode 100644
index 161debea..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65.vhd	
+++ /dev/null
@@ -1,551 +0,0 @@
--- ****
--- T65(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 more merging
--- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 65xx compatible microprocessor core
---
--- Version : 0246
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t65/
---
--- Limitations :
---
--- 65C02 and 65C816 modes are incomplete
--- Undocumented instructions are not supported
--- Some interface signals behaves incorrect
---
--- File history :
---
---      0246 : First release
---
-
-library IEEE;
-  use IEEE.std_logic_1164.all;
-  use IEEE.numeric_std.all;
-  use work.T65_Pack.all;
-
--- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
--- the ready signal to limit the CPU.
-entity T65 is
-	port(
-		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
-		Res_n   : in  std_logic;
-		Enable  : in  std_logic;
-		Clk     : in  std_logic;
-		Rdy     : in  std_logic;
-		Abort_n : in  std_logic;
-		IRQ_n   : in  std_logic;
-		NMI_n   : in  std_logic;
-		SO_n    : in  std_logic;
-		R_W_n   : out std_logic;
-		Sync    : out std_logic;
-		EF      : out std_logic;
-		MF      : out std_logic;
-		XF      : out std_logic;
-		ML_n    : out std_logic;
-		VP_n    : out std_logic;
-		VDA     : out std_logic;
-		VPA     : out std_logic;
-		A       : out std_logic_vector(23 downto 0);
-		DI      : in  std_logic_vector(7 downto 0);
-		DO      : out std_logic_vector(7 downto 0)
-	);
-end T65;
-
-architecture rtl of T65 is
-
-	-- Registers
-	signal ABC, X, Y, D       : std_logic_vector(15 downto 0);
-	signal P, AD, DL          : std_logic_vector(7 downto 0) :=  x"00";
-	signal BAH                : std_logic_vector(7 downto 0);
-	signal BAL                : std_logic_vector(8 downto 0);
-	signal PBR                : std_logic_vector(7 downto 0);
-	signal DBR                : std_logic_vector(7 downto 0);
-	signal PC                 : unsigned(15 downto 0);
-	signal S                  : unsigned(15 downto 0);
-	signal EF_i               : std_logic;
-	signal MF_i               : std_logic;
-	signal XF_i               : std_logic;
-
-	signal IR                 : std_logic_vector(7 downto 0);
-	signal MCycle             : std_logic_vector(2 downto 0);
-
-	signal Mode_r             : std_logic_vector(1 downto 0);
-	signal ALU_Op_r           : std_logic_vector(3 downto 0);
-	signal Write_Data_r       : std_logic_vector(2 downto 0);
-	signal Set_Addr_To_r      : std_logic_vector(1 downto 0);
-	signal PCAdder            : unsigned(8 downto 0);
-
-	signal RstCycle           : std_logic;
-	signal IRQCycle           : std_logic;
-	signal NMICycle           : std_logic;
-
-	signal B_o                : std_logic;
-	signal SO_n_o             : std_logic;
-	signal IRQ_n_o            : std_logic;
-	signal NMI_n_o            : std_logic;
-	signal NMIAct             : std_logic;
-
-	signal Break              : std_logic;
-
-	-- ALU signals
-	signal BusA               : std_logic_vector(7 downto 0);
-	signal BusA_r             : std_logic_vector(7 downto 0);
-	signal BusB               : std_logic_vector(7 downto 0);
-	signal ALU_Q              : std_logic_vector(7 downto 0);
-	signal P_Out              : std_logic_vector(7 downto 0);
-
-	-- Micro code outputs
-	signal LCycle             : std_logic_vector(2 downto 0);
-	signal ALU_Op             : std_logic_vector(3 downto 0);
-	signal Set_BusA_To        : std_logic_vector(2 downto 0);
-	signal Set_Addr_To        : std_logic_vector(1 downto 0);
-	signal Write_Data         : std_logic_vector(2 downto 0);
-	signal Jump               : std_logic_vector(1 downto 0);
-	signal BAAdd              : std_logic_vector(1 downto 0);
-	signal BreakAtNA          : std_logic;
-	signal ADAdd              : std_logic;
-	signal AddY               : std_logic;
-	signal PCAdd              : std_logic;
-	signal Inc_S              : std_logic;
-	signal Dec_S              : std_logic;
-	signal LDA                : std_logic;
-	signal LDP                : std_logic;
-	signal LDX                : std_logic;
-	signal LDY                : std_logic;
-	signal LDS                : std_logic;
-	signal LDDI               : std_logic;
-	signal LDALU              : std_logic;
-	signal LDAD               : std_logic;
-	signal LDBAL              : std_logic;
-	signal LDBAH              : std_logic;
-	signal SaveP              : std_logic;
-	signal Write              : std_logic;
-
-	signal really_rdy         : std_logic;
-	signal R_W_n_i            : std_logic;
-
-begin
-	-- ehenciak : gate Rdy with read/write to make an "OK, it's
-	--            really OK to stop the processor now if Rdy is
-	--            deasserted" signal
-	really_rdy <= Rdy or not(R_W_n_i);
-
-	-- ehenciak : Drive R_W_n_i off chip.
-	R_W_n      <= R_W_n_i;
-
-	Sync <= '1' when MCycle = "000" else '0';
-	EF <= EF_i;
-	MF <= MF_i;
-	XF <= XF_i;
-	ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
-	VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
-	VDA <= '1' when Set_Addr_To_r /= "000" else '0';            -- Incorrect !!!!!!!!!!!!
-	VPA <= '1' when Jump(1) = '0' else '0';                     -- Incorrect !!!!!!!!!!!!
-
-	mcode : T65_MCode
-		port map(
-			Mode        => Mode_r,
-			IR          => IR,
-			MCycle      => MCycle,
-			P           => P,
-			LCycle      => LCycle,
-			ALU_Op      => ALU_Op,
-			Set_BusA_To => Set_BusA_To,
-			Set_Addr_To => Set_Addr_To,
-			Write_Data  => Write_Data,
-			Jump        => Jump,
-			BAAdd       => BAAdd,
-			BreakAtNA   => BreakAtNA,
-			ADAdd       => ADAdd,
-			AddY        => AddY,
-			PCAdd       => PCAdd,
-			Inc_S       => Inc_S,
-			Dec_S       => Dec_S,
-			LDA         => LDA,
-			LDP         => LDP,
-			LDX         => LDX,
-			LDY         => LDY,
-			LDS         => LDS,
-			LDDI        => LDDI,
-			LDALU       => LDALU,
-			LDAD        => LDAD,
-			LDBAL       => LDBAL,
-			LDBAH       => LDBAH,
-			SaveP       => SaveP,
-			Write       => Write
-			);
-
-	alu : T65_ALU
-		port map(
-			Mode => Mode_r,
-			Op => ALU_Op_r,
-			BusA => BusA_r,
-			BusB => BusB,
-			P_In => P,
-			P_Out => P_Out,
-			Q => ALU_Q
-			);
-
-	process (Res_n, Clk)
-	begin
-		if Res_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			IR <= "00000000";
-			S <= (others => '0');       -- Dummy !!!!!!!!!!!!!!!!!!!!!
-			D <= (others => '0');
-			PBR <= (others => '0');
-			DBR <= (others => '0');
-
-			Mode_r <= (others => '0');
-			ALU_Op_r <= "1100";
-			Write_Data_r <= "000";
-			Set_Addr_To_r <= "00";
-
-			R_W_n_i <= '1';
-			EF_i <= '1';
-			MF_i <= '1';
-			XF_i <= '1';
-
-		elsif Clk'event and Clk = '1' then
-		  if (Enable = '1') then
-			if (really_rdy = '1') then
-				R_W_n_i <= not Write or RstCycle;
-
-				D <= (others => '1');   -- Dummy
-				PBR <= (others => '1'); -- Dummy
-				DBR <= (others => '1'); -- Dummy
-				EF_i <= '0';    -- Dummy
-				MF_i <= '0';    -- Dummy
-				XF_i <= '0';    -- Dummy
-
-				if MCycle  = "000" then
-					Mode_r <= Mode;
-
-					if IRQCycle = '0' and NMICycle = '0' then
-						PC <= PC + 1;
-					end if;
-
-					if IRQCycle = '1' or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DI;
-					end if;
-				end if;
-
-				ALU_Op_r <= ALU_Op;
-				Write_Data_r <= Write_Data;
-				if Break = '1' then
-					Set_Addr_To_r <= "00";
-				else
-					Set_Addr_To_r <= Set_Addr_To;
-				end if;
-
-				if Inc_S = '1' then
-					S <= S + 1;
-				end if;
-				if Dec_S = '1' and RstCycle = '0' then
-					S <= S - 1;
-				end if;
-				if LDS = '1' then
-					S(7 downto 0) <= unsigned(ALU_Q);
-				end if;
-
-				if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
-					PC <= PC + 1;
-				end if;
-				--
-				-- jump control logic
-				--
-				case Jump is
-				  when "01" =>
-					  PC <= PC + 1;
-
-				  when "10" =>
-					  PC <= unsigned(DI & DL);
-
-				  when "11" =>
-					  if PCAdder(8) = '1' then
-						  if DL(7) = '0' then
-							  PC(15 downto 8) <= PC(15 downto 8) + 1;
-						  else
-							  PC(15 downto 8) <= PC(15 downto 8) - 1;
-						  end if;
-					  end if;
-					  PC(7 downto 0) <= PCAdder(7 downto 0);
-
-				  when others => null;
-				end case;
-			end if;
-		  end if;
-		end if;
-	end process;
-
-	PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
-			   else "0" & PC(7 downto 0);
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-		  if (Enable = '1') then
-			if (really_rdy = '1') then
-				if MCycle = "000" then
-					if LDA = '1' then
-						ABC(7 downto 0) <= ALU_Q;
-					end if;
-					if LDX = '1' then
-						X(7 downto 0) <= ALU_Q;
-					end if;
-					if LDY = '1' then
-						Y(7 downto 0) <= ALU_Q;
-					end if;
-					if (LDA or LDX or LDY) = '1' then
-						P <= P_Out;
-					end if;
-				end if;
-				if SaveP = '1' then
-					P <= P_Out;
-				end if;
-				if LDP = '1' then
-					P <= ALU_Q;
-				end if;
-				if IR(4 downto 0) = "11000" then
-					case IR(7 downto 5) is
-					when "000" =>
-						P(Flag_C) <= '0';
-					when "001" =>
-						P(Flag_C) <= '1';
-					when "010" =>
-						P(Flag_I) <= '0';
-					when "011" =>
-						P(Flag_I) <= '1';
-					when "101" =>
-						P(Flag_V) <= '0';
-					when "110" =>
-						P(Flag_D) <= '0';
-					when "111" =>
-						P(Flag_D) <= '1';
-					when others =>
-					end case;
-				end if;
-				if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
-					P(Flag_B) <= '1';
-				end if;
-				if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1')  then
-					P(Flag_I) <= '1';
-					P(Flag_B) <= B_o;
-				end if;
-				if SO_n_o = '1' and SO_n = '0' then
-					P(Flag_V) <= '1';
-				end if;
-				if RstCycle = '1' and Mode_r /= "00" then
-					P(Flag_1) <= '1';
-					P(Flag_D) <= '0';
-					P(Flag_I) <= '1';
-				end if;
-				P(Flag_1) <= '1';
-
-				B_o     <= P(Flag_B);
-				SO_n_o <= SO_n;
-				IRQ_n_o <= IRQ_n;
-				NMI_n_o <= NMI_n;
-			end if;
-		  end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-
-	process (Res_n, Clk)
-	begin
-		if Res_n = '0' then
-			BusA_r <= (others => '0');
-			BusB <= (others => '0');
-			AD <= (others => '0');
-			BAL <= (others => '0');
-			BAH <= (others => '0');
-			DL <= (others => '0');
-		elsif Clk'event and Clk = '1' then
-		  if (Enable = '1') then
-			if (Rdy = '1') then
-				BusA_r <= BusA;
-				BusB <= DI;
-
-				case BAAdd is
-				when "01" =>
-					-- BA Inc
-					AD <= std_logic_vector(unsigned(AD) + 1);
-					BAL <= std_logic_vector(unsigned(BAL) + 1);
-				when "10" =>
-					-- BA Add
-					BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
-				when "11" =>
-					-- BA Adj
-					if BAL(8) = '1' then
-						BAH <= std_logic_vector(unsigned(BAH) + 1);
-					end if;
-				when others =>
-				end case;
-
-				-- ehenciak : modified to use Y register as well (bugfix)
-				if ADAdd = '1' then
-				  if (AddY = '1') then
-					AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
-				  else
-					AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
-				  end if;
-				end if;
-
-				if IR = "00000000" then
-					BAL <= (others => '1');
-					BAH <= (others => '1');
-					if RstCycle = '1' then
-						BAL(2 downto 0) <= "100";
-					elsif NMICycle = '1' then
-						BAL(2 downto 0) <= "010";
-					else
-						BAL(2 downto 0) <= "110";
-					end if;
-					if Set_addr_To_r = "11" then
-						BAL(0) <= '1';
-					end if;
-				end if;
-
-
-				if LDDI = '1' then
-					DL <= DI;
-				end if;
-				if LDALU = '1' then
-					DL <= ALU_Q;
-				end if;
-				if LDAD = '1' then
-					AD <= DI;
-				end if;
-				if LDBAL = '1' then
-					BAL(7 downto 0) <= DI;
-				end if;
-				if LDBAH = '1' then
-					BAH <= DI;
-				end if;
-			end if;
-		end if;
-	  end if;
-	end process;
-
-	Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
-
-
-	with Set_BusA_To select
-		BusA <= DI when "000",
-			ABC(7 downto 0) when "001",
-			X(7 downto 0) when "010",
-			Y(7 downto 0) when "011",
-			std_logic_vector(S(7 downto 0)) when "100",
-			P when "101",
-			(others => '-') when others;
-
-	with Set_Addr_To_r select
-		A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
-			DBR & "00000000" & AD when "10",
-			"00000000" & BAH & BAL(7 downto 0) when "11",
-			PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
-
-	with Write_Data_r select
-		DO <= DL when "000",
-			ABC(7 downto 0) when "001",
-			X(7 downto 0) when "010",
-			Y(7 downto 0) when "011",
-			std_logic_vector(S(7 downto 0)) when "100",
-			P when "101",
-			std_logic_vector(PC(7 downto 0)) when "110",
-			std_logic_vector(PC(15 downto 8)) when others;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-
-	process (Res_n, Clk)
-	begin
-		if Res_n = '0' then
-			MCycle <= "001";
-			RstCycle <= '1';
-			IRQCycle <= '0';
-			NMICycle <= '0';
-			NMIAct <= '0';
-		elsif Clk'event and Clk = '1' then
-		  if (Enable = '1') then
-			if (really_rdy = '1') then
-				if MCycle = LCycle or Break = '1' then
-					MCycle <= "000";
-					RstCycle <= '0';
-					IRQCycle <= '0';
-					NMICycle <= '0';
-					if NMIAct = '1' then
-						NMICycle <= '1';
-					elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
-						IRQCycle <= '1';
-					end if;
-				else
-					MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-				end if;
-
-				if NMICycle = '1' then
-					NMIAct <= '0';
-				end if;
-				if NMI_n_o = '1' and NMI_n = '0' then
-					NMIAct <= '1';
-				end if;
-			end if;
-		  end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65_ALU.vhd
deleted file mode 100644
index b1f6d632..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65_ALU.vhd	
+++ /dev/null
@@ -1,260 +0,0 @@
--- ****
--- T65(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 Bugfixes by ehenciak added
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 6502 compatible microprocessor core
---
--- Version : 0245
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t65/
---
--- Limitations :
---
--- File history :
---
---      0245 : First version
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T65_Pack.all;
-
-entity T65_ALU is
-	port(
-		Mode    : in std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
-		Op      : in std_logic_vector(3 downto 0);
-		BusA    : in std_logic_vector(7 downto 0);
-		BusB    : in std_logic_vector(7 downto 0);
-		P_In    : in std_logic_vector(7 downto 0);
-		P_Out   : out std_logic_vector(7 downto 0);
-		Q       : out std_logic_vector(7 downto 0)
-	);
-end T65_ALU;
-
-architecture rtl of T65_ALU is
-
-	-- AddSub variables (temporary signals)
-	signal      ADC_Z           : std_logic;
-	signal      ADC_C           : std_logic;
-	signal      ADC_V           : std_logic;
-	signal      ADC_N           : std_logic;
-	signal      ADC_Q           : std_logic_vector(7 downto 0);
-	signal      SBC_Z           : std_logic;
-	signal      SBC_C           : std_logic;
-	signal      SBC_V           : std_logic;
-	signal      SBC_N           : std_logic;
-	signal      SBC_Q           : std_logic_vector(7 downto 0);
-
-begin
-
-	process (P_In, BusA, BusB)
-		variable AL : unsigned(6 downto 0);
-		variable AH : unsigned(6 downto 0);
-		variable C : std_logic;
-	begin
-		AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
-		AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-
--- pragma translate_off
-			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
-			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
--- pragma translate_on
-
-		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
-			ADC_Z <= '1';
-		else
-			ADC_Z <= '0';
-		end if;
-
-		if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
-			AL(6 downto 1) := AL(6 downto 1) + 6;
-		end if;
-
-		C := AL(6) or AL(5);
-		AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-
-		ADC_N <= AH(4);
-		ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-
--- pragma translate_off
-			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
--- pragma translate_on
-
-		if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
-			AH(6 downto 1) := AH(6 downto 1) + 6;
-		end if;
-
-		ADC_C <= AH(6) or AH(5);
-
-		ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
-	end process;
-
-	process (Op, P_In, BusA, BusB)
-		variable AL : unsigned(6 downto 0);
-		variable AH : unsigned(5 downto 0);
-		variable C : std_logic;
-	begin
-		C := P_In(Flag_C) or not Op(0);
-		AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
-		AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-
--- pragma translate_off
-			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
-			if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
--- pragma translate_on
-
-		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
-			SBC_Z <= '1';
-		else
-			SBC_Z <= '0';
-		end if;
-
-		SBC_C <= not AH(5);
-		SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
-		SBC_N <= AH(4);
-
-		if P_In(Flag_D) = '1' then
-			if AL(5) = '1' then
-				AL(5 downto 1) := AL(5 downto 1) - 6;
-			end if;
-			AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
-			if AH(5) = '1' then
-				AH(5 downto 1) := AH(5 downto 1) - 6;
-			end if;
-		end if;
-
-		SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
-	end process;
-
-	process (Op, P_In, BusA, BusB,
-			ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
-			SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
-		variable Q_t : std_logic_vector(7 downto 0);
-	begin
-		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
-		P_Out <= P_In;
-		Q_t := BusA;
-		case Op(3 downto 0) is
-		when "0000" =>
-			-- ORA
-			Q_t := BusA or BusB;
-		when "0001" =>
-			-- AND
-			Q_t := BusA and BusB;
-		when "0010" =>
-			-- EOR
-			Q_t := BusA xor BusB;
-		when "0011" =>
-			-- ADC
-			P_Out(Flag_V) <= ADC_V;
-			P_Out(Flag_C) <= ADC_C;
-			Q_t := ADC_Q;
-		when "0101" | "1101" =>
-			-- LDA
-		when "0110" =>
-			-- CMP
-			P_Out(Flag_C) <= SBC_C;
-		when "0111" =>
-			-- SBC
-			P_Out(Flag_V) <= SBC_V;
-			P_Out(Flag_C) <= SBC_C;
-			Q_t := SBC_Q;
-		when "1000" =>
-			-- ASL
-			Q_t := BusA(6 downto 0) & "0";
-			P_Out(Flag_C) <= BusA(7);
-		when "1001" =>
-			-- ROL
-			Q_t := BusA(6 downto 0) & P_In(Flag_C);
-			P_Out(Flag_C) <= BusA(7);
-		when "1010" =>
-			-- LSR
-			Q_t := "0" & BusA(7 downto 1);
-			P_Out(Flag_C) <= BusA(0);
-		when "1011" =>
-			-- ROR
-			Q_t := P_In(Flag_C) & BusA(7 downto 1);
-			P_Out(Flag_C) <= BusA(0);
-		when "1100" =>
-			-- BIT
-			P_Out(Flag_V) <= BusB(6);
-		when "1110" =>
-			-- DEC
-			Q_t := std_logic_vector(unsigned(BusA) - 1);
-		when "1111" =>
-			-- INC
-			Q_t := std_logic_vector(unsigned(BusA) + 1);
-		when others =>
-		end case;
-
-		case Op(3 downto 0) is
-		when "0011" =>
-			P_Out(Flag_N) <= ADC_N;
-			P_Out(Flag_Z) <= ADC_Z;
-		when "0110" | "0111" =>
-			P_Out(Flag_N) <= SBC_N;
-			P_Out(Flag_Z) <= SBC_Z;
-		when "0100" =>
-		when "1100" =>
-			P_Out(Flag_N) <= BusB(7);
-			if (BusA and BusB) = "00000000" then
-				P_Out(Flag_Z) <= '1';
-			else
-				P_Out(Flag_Z) <= '0';
-			end if;
-		when others =>
-			P_Out(Flag_N) <= Q_t(7);
-			if Q_t = "00000000" then
-				P_Out(Flag_Z) <= '1';
-			else
-				P_Out(Flag_Z) <= '0';
-			end if;
-		end case;
-
-		Q <= Q_t;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65_MCode.vhd
deleted file mode 100644
index 06229751..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65_MCode.vhd	
+++ /dev/null
@@ -1,1050 +0,0 @@
--- ****
--- T65(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 Jump timing fixed
--- Ver 300 Bugfixes by ehenciak added
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 65xx compatible microprocessor core
---
--- Version : 0246 + fix
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t65/
---
--- Limitations :
---
--- 65C02
--- supported : inc, dec, phx, plx, phy, ply
--- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
---
--- File history :
---
---      0246 : First release
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T65_Pack.all;
-
-entity T65_MCode is
-	port(
-		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
-		IR                      : in  std_logic_vector(7 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		P                       : in  std_logic_vector(7 downto 0);
-		LCycle                  : out std_logic_vector(2 downto 0);
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
-		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
-		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
-		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
-		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
-		BreakAtNA               : out std_logic;
-		ADAdd                   : out std_logic;
-		AddY                    : out std_logic;
-		PCAdd                   : out std_logic;
-		Inc_S                   : out std_logic;
-		Dec_S                   : out std_logic;
-		LDA                     : out std_logic;
-		LDP                     : out std_logic;
-		LDX                     : out std_logic;
-		LDY                     : out std_logic;
-		LDS                     : out std_logic;
-		LDDI                    : out std_logic;
-		LDALU                   : out std_logic;
-		LDAD                    : out std_logic;
-		LDBAL                   : out std_logic;
-		LDBAH                   : out std_logic;
-		SaveP                   : out std_logic;
-		Write                   : out std_logic
-	);
-end T65_MCode;
-
-architecture rtl of T65_MCode is
-
-	signal Branch : std_logic;
-
-begin
-
-	with IR(7 downto 5) select
-		Branch <= not P(Flag_N) when "000",
-					  P(Flag_N) when "001",
-				  not P(Flag_V) when "010",
-					  P(Flag_V) when "011",
-				  not P(Flag_C) when "100",
-					  P(Flag_C) when "101",
-				  not P(Flag_Z) when "110",
-					  P(Flag_Z) when others;
-
-	process (IR, MCycle, P, Branch, Mode)
-	begin
-		LCycle      <= "001";
-		Set_BusA_To <= "001"; -- A
-		Set_Addr_To <= (others => '0');
-		Write_Data  <= (others => '0');
-		Jump        <= (others => '0');
-		BAAdd       <= "00";
-		BreakAtNA   <= '0';
-		ADAdd       <= '0';
-		PCAdd       <= '0';
-		Inc_S       <= '0';
-		Dec_S       <= '0';
-		LDA         <= '0';
-		LDP         <= '0';
-		LDX         <= '0';
-		LDY         <= '0';
-		LDS         <= '0';
-		LDDI        <= '0';
-		LDALU       <= '0';
-		LDAD        <= '0';
-		LDBAL       <= '0';
-		LDBAH       <= '0';
-		SaveP       <= '0';
-		Write       <= '0';
-		AddY        <= '0';
-
-		case IR(7 downto 5) is
-		when "100" =>
-		--{{{
-			case IR(1 downto 0) is
-			when "00" =>
-				Set_BusA_To <= "011"; -- Y
-				Write_Data <= "011"; -- Y
-			when "10" =>
-				Set_BusA_To <= "010"; -- X
-				Write_Data <= "010"; -- X
-			when others =>
-				Write_Data <= "001"; -- A
-			end case;
-		--}}}
-		when "101" =>
-		--{{{
-			case IR(1 downto 0) is
-			when "00" =>
-				if IR(4) /= '1' or IR(2) /= '0' then
-					LDY <= '1';
-				end if;
-			when "10" =>
-				LDX <= '1';
-			when others =>
-				LDA <= '1';
-			end case;
-			Set_BusA_To <= "000"; -- DI
-		--}}}
-		when "110" =>
-		--{{{
-			case IR(1 downto 0) is
-			when "00" =>
-				if IR(4) = '0' then
-					LDY <= '1';
-				end if;
-				Set_BusA_To <= "011"; -- Y
-			when others =>
-				Set_BusA_To <= "001"; -- A
-			end case;
-		--}}}
-		when "111" =>
-		--{{{
-			case IR(1 downto 0) is
-			when "00" =>
-				if IR(4) = '0' then
-					LDX <= '1';
-				end if;
-				Set_BusA_To <= "010"; -- X
-			when others =>
-				Set_BusA_To <= "001"; -- A
-			end case;
-		--}}}
-		when others =>
-		end case;
-
-		if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-			Set_BusA_To <= "000"; -- DI
-		end if;
-
-		case IR(4 downto 0) is
-		when "00000" | "01000" | "01010" | "11000" | "11010" =>
-		--{{{
-			-- Implied
-			case IR is
-			when "00000000" =>
-				-- BRK
-				LCycle <= "110";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= "01"; -- S
-					Write_Data <= "111"; -- PCH
-					Write <= '1';
-				when 2 =>
-					Dec_S <= '1';
-					Set_Addr_To <= "01"; -- S
-					Write_Data <= "110"; -- PCL
-					Write <= '1';
-				when 3 =>
-					Dec_S <= '1';
-					Set_Addr_To <= "01"; -- S
-					Write_Data <= "101"; -- P
-					Write <= '1';
-				when 4 =>
-					Dec_S <= '1';
-					Set_Addr_To <= "11"; -- BA
-				when 5 =>
-					LDDI <= '1';
-					Set_Addr_To <= "11"; -- BA
-				when 6 =>
-					Jump <= "10"; -- DIDL
-				when others =>
-				end case;
-			when "00100000" =>
-				-- JSR
-				LCycle <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Jump <= "01";
-					LDDI <= '1';
-					Set_Addr_To <= "01"; -- S
-				when 2 =>
-					Set_Addr_To <= "01"; -- S
-					Write_Data <= "111"; -- PCH
-					Write <= '1';
-				when 3 =>
-					Dec_S <= '1';
-					Set_Addr_To <= "01"; -- S
-					Write_Data <= "110"; -- PCL
-					Write <= '1';
-				when 4 =>
-					Dec_S <= '1';
-				when 5 =>
-					Jump <= "10"; -- DIDL
-				when others =>
-				end case;
-			when "01000000" =>
-				-- RTI
-				LCycle <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= "01"; -- S
-				when 2 =>
-					Inc_S <= '1';
-					Set_Addr_To <= "01"; -- S
-				when 3 =>
-					Inc_S <= '1';
-					Set_Addr_To <= "01"; -- S
-					Set_BusA_To <= "000"; -- DI
-				when 4 =>
-					LDP <= '1';
-					Inc_S <= '1';
-					LDDI <= '1';
-					Set_Addr_To <= "01"; -- S
-				when 5 =>
-					Jump <= "10"; -- DIDL
-				when others =>
-				end case;
-			when "01100000" =>
-				-- RTS
-				LCycle <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= "01"; -- S
-				when 2 =>
-					Inc_S <= '1';
-					Set_Addr_To <= "01"; -- S
-				when 3 =>
-					Inc_S <= '1';
-					LDDI <= '1';
-					Set_Addr_To <= "01"; -- S
-				when 4 =>
-					Jump <= "10"; -- DIDL
-				when 5 =>
-					Jump <= "01";
-				when others =>
-				end case;
-			when "00001000" | "01001000" | "01011010" | "11011010" =>
-				-- PHP, PHA, PHY*, PHX*
-				LCycle <= "010";
-				if Mode = "00" and IR(1) = '1' then
-					LCycle <= "001";
-				end if;
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					case IR(7 downto 4) is
-					when "0000" =>
-						Write_Data <= "101"; -- P
-					when "0100" =>
-						Write_Data <= "001"; -- A
-					when "0101" =>
-						Write_Data <= "011"; -- Y
-					when "1101" =>
-						Write_Data <= "010"; -- X
-					when others =>
-					end case;
-					Write <= '1';
-					Set_Addr_To <= "01"; -- S
-				when 2 =>
-					Dec_S <= '1';
-				when others =>
-				end case;
-			when "00101000" | "01101000" | "01111010" | "11111010" =>
-				-- PLP, PLA, PLY*, PLX*
-				LCycle <= "011";
-				if Mode = "00" and IR(1) = '1' then
-					LCycle <= "001";
-				end if;
-				case IR(7 downto 4) is
-				when "0010" =>
-					LDP <= '1';
-				when "0110" =>
-					LDA <= '1';
-				when "0111" =>
-					if Mode /= "00" then
-						LDY <= '1';
-					end if;
-				when "1111" =>
-					if Mode /= "00" then
-						LDX <= '1';
-					end if;
-				when others =>
-				end case;
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-					SaveP <= '1';
-				when 1 =>
-					Set_Addr_To <= "01"; -- S
-				when 2 =>
-					Inc_S <= '1';
-					Set_Addr_To <= "01"; -- S
-				when 3 =>
-					Set_BusA_To <= "000"; -- DI
-				when others =>
-				end case;
-			when "10100000" | "11000000" | "11100000" =>
-				-- LDY, CPY, CPX
-				-- Immediate
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Jump <= "01";
-				when others =>
-				end case;
-			when "10001000" =>
-				-- DEY
-				LDY <= '1';
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Set_BusA_To <= "011"; -- Y
-				when others =>
-				end case;
-			when "11001010" =>
-				-- DEX
-				LDX <= '1';
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Set_BusA_To <= "010"; -- X
-				when others =>
-				end case;
-			when "00011010" | "00111010" =>
-				-- INC*, DEC*
-				if Mode /= "00" then
-					LDA <= '1'; -- A
-				end if;
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Set_BusA_To <= "100"; -- S
-				when others =>
-				end case;
-			when "00001010" | "00101010" | "01001010" | "01101010" =>
-				-- ASL, ROL, LSR, ROR
-				LDA <= '1'; -- A
-				Set_BusA_To <= "001"; -- A
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-				when others =>
-				end case;
-			when "10001010" | "10011000" =>
-				-- TYA, TXA
-				LDA <= '1'; -- A
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-				when others =>
-				end case;
-			when "10101010" | "10101000" =>
-				-- TAX, TAY
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Set_BusA_To <= "001"; -- A
-				when others =>
-				end case;
-			when "10011010" =>
-				-- TXS
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-					LDS <= '1';
-				when 1 =>
-				when others =>
-				end case;
-			when "10111010" =>
-				-- TSX
-				LDX <= '1';
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Set_BusA_To <= "100"; -- S
-				when others =>
-				end case;
-
-		--                      when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" =>
-		--                              -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX
-		--                              case to_integer(unsigned(MCycle)) is
-		--                              when 1 =>
-		--                              when others =>
-		--                              end case;
-			when others =>
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when others =>
-				end case;
-			end case;
-		--}}}
-
-		when "00001" | "00011" =>
-		--{{{
-			-- Zero Page Indexed Indirect (d,x)
-			LCycle <= "101";
-			if IR(7 downto 6) /= "10" then
-				LDA <= '1';
-			end if;
-			case to_integer(unsigned(MCycle)) is
-			when 0 =>
-			when 1 =>
-				Jump <= "01";
-				LDAD <= '1';
-				Set_Addr_To <= "10"; -- AD
-			when 2 =>
-				ADAdd <= '1';
-				Set_Addr_To <= "10"; -- AD
-			when 3 =>
-				BAAdd <= "01";  -- DB Inc
-				LDBAL <= '1';
-				Set_Addr_To <= "10"; -- AD
-			when 4 =>
-				LDBAH <= '1';
-				if IR(7 downto 5) = "100" then
-					Write <= '1';
-				end if;
-				Set_Addr_To <= "11"; -- BA
-			when 5 =>
-			when others =>
-			end case;
-		--}}}
-
-		when "01001" | "01011" =>
-		--{{{
-			-- Immediate
-			LDA <= '1';
-			case to_integer(unsigned(MCycle)) is
-			when 0 =>
-			when 1 =>
-				Jump <= "01";
-			when others =>
-			end case;
-
-		--}}}
-
-		when "00010" | "10010" =>
-		--{{{
-			-- Immediate, KIL
-			LDX <= '1';
-			case to_integer(unsigned(MCycle)) is
-			when 0 =>
-			when 1 =>
-				if IR = "10100010" then
-					-- LDX
-					Jump <= "01";
-				else
-					-- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-				end if;
-			when others =>
-			end case;
-		--}}}
-
-		when "00100" =>
-		--{{{
-			-- Zero Page
-			LCycle <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 0 =>
-				if IR(7 downto 5) = "001" then
-					SaveP <= '1';
-				end if;
-			when 1 =>
-				Jump <= "01";
-				LDAD <= '1';
-				if IR(7 downto 5) = "100" then
-					Write <= '1';
-				end if;
-				Set_Addr_To <= "10"; -- AD
-			when 2 =>
-			when others =>
-			end case;
-		--}}}
-
-		when "00101" | "00110" | "00111" =>
-		--{{{
-			-- Zero Page
-			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-				-- Read-Modify-Write
-				LCycle <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Jump <= "01";
-					LDAD <= '1';
-					Set_Addr_To <= "10"; -- AD
-				when 2 =>
-					LDDI <= '1';
-					Write <= '1';
-					Set_Addr_To <= "10"; -- AD
-				when 3 =>
-					LDALU <= '1';
-					SaveP <= '1';
-					Write <= '1';
-					Set_Addr_To <= "10"; -- AD
-				when 4 =>
-				when others =>
-				end case;
-			else
-				LCycle <= "010";
-				if IR(7 downto 6) /= "10" then
-					LDA <= '1';
-				end if;
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Jump <= "01";
-					LDAD <= '1';
-					if IR(7 downto 5) = "100" then
-						Write <= '1';
-					end if;
-					Set_Addr_To <= "10"; -- AD
-				when 2 =>
-				when others =>
-				end case;
-			end if;
-		--}}}
-
-		when "01100" =>
-		--{{{
-			-- Absolute
-			if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then
-				-- JMP
-				if IR(5) = '0' then
-					--LCycle <= "011";
-					LCycle <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Jump <= "01";
-						LDDI <= '1';
-					when 2 =>
-						Jump <= "10"; -- DIDL
-					when others =>
-					end case;
-				else
-					LCycle <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Jump <= "01";
-						LDDI <= '1';
-						LDBAL <= '1';
-					when 3 =>
-						LDBAH <= '1';
-						if Mode /= "00" then
-							Jump <= "10"; -- DIDL
-						end if;
-						if Mode = "00" then
-							Set_Addr_To <= "11"; -- BA
-						end if;
-					when 4 =>
-						LDDI <= '1';
-						if Mode = "00" then
-							Set_Addr_To <= "11"; -- BA
-							BAAdd <= "01";      -- DB Inc
-						else
-							Jump <= "01";
-						end if;
-					when 5 =>
-						Jump <= "10"; -- DIDL
-					when others =>
-					end case;
-				end if;
-			else
-				LCycle <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-					if IR(7 downto 5) = "001" then
-						SaveP <= '1';
-					end if;
-				when 1 =>
-					Jump <= "01";
-					LDBAL <= '1';
-				when 2 =>
-					Jump <= "01";
-					LDBAH <= '1';
-					if IR(7 downto 5) = "100" then
-						Write <= '1';
-					end if;
-					Set_Addr_To <= "11"; -- BA
-				when 3 =>
-				when others =>
-				end case;
-			end if;
-		--}}}
-
-		when "01101" | "01110" | "01111" =>
-		--{{{
-			-- Absolute
-			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-				-- Read-Modify-Write
-				LCycle <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Jump <= "01";
-					LDBAL <= '1';
-				when 2 =>
-					Jump <= "01";
-					LDBAH <= '1';
-					Set_Addr_To <= "11"; -- BA
-				when 3 =>
-					LDDI <= '1';
-					Write <= '1';
-					Set_Addr_To <= "11"; -- BA
-				when 4 =>
-					Write <= '1';
-					LDALU <= '1';
-					SaveP <= '1';
-					Set_Addr_To <= "11"; -- BA
-				when 5 =>
-					SaveP <= '0'; -- MIKEJ was 1
-				when others =>
-				end case;
-			else
-				LCycle <= "011";
-				if IR(7 downto 6) /= "10" then
-					LDA <= '1';
-				end if;
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Jump <= "01";
-					LDBAL <= '1';
-				when 2 =>
-					Jump <= "01";
-					LDBAH <= '1';
-					if IR(7 downto 5) = "100" then
-						Write <= '1';
-					end if;
-					Set_Addr_To <= "11"; -- BA
-				when 3 =>
-				when others =>
-				end case;
-			end if;
-		--}}}
-
-		when "10000" =>
-		--{{{
-			-- Relative
-
-						-- This circuit dictates when the last
-						-- microcycle occurs for the branch depending on
-						-- whether or not the branch is taken and if a page
-						-- is crossed...
-			if (Branch = '1') then
-
-							 LCycle <= "011"; -- We're done @ T3 if branching...upper
-											  -- level logic will stop at T2 if no page cross
-											  -- (See the Break signal)
-			else
-
-							 LCycle <= "001";
-
-			end if;
-
-						-- This decodes the current microcycle and takes the
-						-- proper course of action...
-			case to_integer(unsigned(MCycle)) is
-
-							-- On the T1 microcycle, increment the program counter
-							-- and instruct the upper level logic to fetch the offset
-							-- from the Din bus and store it in the data latches. This
-							-- will be the last microcycle if the branch isn't taken.
-				when 1 =>
-
-					Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-											  -- from microcycle T0.
-
-				LDDI <= '1';  -- Tells logic in top level (T65.vhd) to route
-											  -- the Din bus to the memory data latch (DL)
-											  -- so that the branch offset is fetched.
-
-							-- In microcycle T2, tell the logic in the top level to
-							-- add the offset.  If the most significant byte of the
-							-- program counter (i.e. the current "page") does not need
-							-- updating, we are done here...the Break signal at the
-							-- T65.vhd level takes care of that...
-				when 2 =>
-
-				Jump    <= "11"; -- Tell the PC Jump logic to use relative mode.
-
-				PCAdd   <= '1';  -- This tells the PC adder to update itself with
-												 -- the current offset recently fetched from
-												 -- memory.
-
-							-- The following is microcycle T3 :
-							-- The program counter should be completely updated
-							-- on this cycle after the page cross is detected.
-							-- We don't need to do anything here...
-				when 3 =>
-
-
-				when others => null; -- Do nothing.
-
-			end case;
-		--}}}
-
-		when "10001" | "10011" =>
-		--{{{
-			-- Zero Page Indirect Indexed (d),y
-			LCycle <= "101";
-			if IR(7 downto 6) /= "10" then
-				LDA <= '1';
-			end if;
-			case to_integer(unsigned(MCycle)) is
-			when 0 =>
-			when 1 =>
-				Jump <= "01";
-				LDAD <= '1';
-				Set_Addr_To <= "10"; -- AD
-			when 2 =>
-				LDBAL <= '1';
-				BAAdd <= "01";  -- DB Inc
-				Set_Addr_To <= "10"; -- AD
-			when 3 =>
-				Set_BusA_To <= "011"; -- Y
-				BAAdd <= "10";  -- BA Add
-				LDBAH <= '1';
-				Set_Addr_To <= "11"; -- BA
-			when 4 =>
-				BAAdd <= "11";  -- BA Adj
-				if IR(7 downto 5) = "100" then
-					Write <= '1';
-				else
-					BreakAtNA <= '1';
-				end if;
-				Set_Addr_To <= "11"; -- BA
-			when 5 =>
-			when others =>
-			end case;
-		--}}}
-
-		when "10100" | "10101" | "10110" | "10111" =>
-		--{{{
-			-- Zero Page, X
-			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-				-- Read-Modify-Write
-				LCycle <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Jump <= "01";
-					LDAD <= '1';
-					Set_Addr_To <= "10"; -- AD
-				when 2 =>
-					ADAdd <= '1';
-					Set_Addr_To <= "10"; -- AD
-				when 3 =>
-					LDDI <= '1';
-					Write <= '1';
-					Set_Addr_To <= "10"; -- AD
-				when 4 =>
-					LDALU <= '1';
-					SaveP <= '1';
-					Write <= '1';
-					Set_Addr_To <= "10"; -- AD
-				when 5 =>
-				when others =>
-				end case;
-			else
-				LCycle <= "011";
-				if IR(7 downto 6) /= "10" then
-					LDA <= '1';
-				end if;
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Jump <= "01";
-					LDAD <= '1';
-					Set_Addr_To <= "10"; -- AD
-				when 2 =>
-					ADAdd <= '1';
-					-- Added this check for Y reg. use...
-					if (IR(3 downto 0) = "0110") then
-					  AddY <= '1';
-					end if;
-
-					if IR(7 downto 5) = "100" then
-						Write <= '1';
-					end if;
-					Set_Addr_To <= "10"; -- AD
-				when 3 => null;
-				when others =>
-				end case;
-			end if;
-		--}}}
-
-		when "11001" | "11011" =>
-		--{{{
-			-- Absolute Y
-			LCycle <= "100";
-			if IR(7 downto 6) /= "10" then
-				LDA <= '1';
-			end if;
-			case to_integer(unsigned(MCycle)) is
-			when 0 =>
-			when 1 =>
-				Jump <= "01";
-				LDBAL <= '1';
-			when 2 =>
-				Jump <= "01";
-				Set_BusA_To <= "011"; -- Y
-				BAAdd <= "10";  -- BA Add
-				LDBAH <= '1';
-				Set_Addr_To <= "11"; -- BA
-			when 3 =>
-				BAAdd <= "11";  -- BA adj
-				if IR(7 downto 5) = "100" then
-					Write <= '1';
-				else
-					BreakAtNA <= '1';
-				end if;
-				Set_Addr_To <= "11"; -- BA
-			when 4 =>
-			when others =>
-			end case;
-		--}}}
-
-		when "11100" | "11101" | "11110" | "11111" =>
-		--{{{
-			-- Absolute X
-
-			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
-				-- Read-Modify-Write
-				LCycle <= "110";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Jump <= "01";
-					LDBAL <= '1';
-				when 2 =>
-					Jump <= "01";
-					Set_BusA_To <= "010"; -- X
-					BAAdd <= "10";      -- BA Add
-					LDBAH <= '1';
-					Set_Addr_To <= "11"; -- BA
-				when 3 =>
-					BAAdd <= "11";      -- BA adj
-					Set_Addr_To <= "11"; -- BA
-				when 4 =>
-					LDDI <= '1';
-					Write <= '1';
-					Set_Addr_To <= "11"; -- BA
-				when 5 =>
-					LDALU <= '1';
-					SaveP <= '1';
-					Write <= '1';
-					Set_Addr_To <= "11"; -- BA
-				when 6 =>
-				when others =>
-				end case;
-			else
-				LCycle <= "100";
-				if IR(7 downto 6) /= "10" then
-					LDA <= '1';
-				end if;
-				case to_integer(unsigned(MCycle)) is
-				when 0 =>
-				when 1 =>
-					Jump <= "01";
-					LDBAL <= '1';
-				when 2 =>
-					Jump <= "01";
-					-- mikej
-					-- special case 0xBE which uses Y reg as index!!
-					if (IR = "10111110") then
-					  Set_BusA_To <= "011"; -- Y
-					else
-					  Set_BusA_To <= "010"; -- X
-					end if;
-					BAAdd <= "10";      -- BA Add
-					LDBAH <= '1';
-					Set_Addr_To <= "11"; -- BA
-				when 3 =>
-					BAAdd <= "11";      -- BA adj
-					if IR(7 downto 5) = "100" then
-						Write <= '1';
-					else
-						BreakAtNA <= '1';
-					end if;
-					Set_Addr_To <= "11"; -- BA
-				when 4 =>
-				when others =>
-				end case;
-			end if;
-		--}}}
-		when others =>
-		end case;
-	end process;
-
-	process (IR, MCycle)
-	begin
-		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
-		case IR(1 downto 0) is
-		when "00" =>
-		--{{{
-			case IR(4 downto 2) is
-			when "000" | "001" | "011" =>
-				case IR(7 downto 5) is
-				when "110" | "111" =>
-					-- CP
-					ALU_Op <= "0110";
-				when "101" =>
-					-- LD
-					ALU_Op <= "0101";
-				when "001" =>
-					-- BIT
-					ALU_Op <= "1100";
-				when others =>
-					-- NOP/ST
-					ALU_Op <= "0100";
-				end case;
-			when "010" =>
-				case IR(7 downto 5) is
-				when "111" | "110" =>
-					-- IN
-					ALU_Op <= "1111";
-				when "100" =>
-					-- DEY
-					ALU_Op <= "1110";
-				when others =>
-					-- LD
-					ALU_Op <= "1101";
-				end case;
-			when "110" =>
-				case IR(7 downto 5) is
-				when "100" =>
-					-- TYA
-					ALU_Op <= "1101";
-				when others =>
-					ALU_Op <= "----";
-				end case;
-			when others =>
-				case IR(7 downto 5) is
-				when "101" =>
-					-- LD
-					ALU_Op <= "1101";
-				when others =>
-					ALU_Op <= "0100";
-				end case;
-			end case;
-		--}}}
-		when "01" => -- OR
-		--{{{
-			ALU_Op(3) <= '0';
-			ALU_Op(2 downto 0) <= IR(7 downto 5);
-		--}}}
-		when "10" =>
-		--{{{
-			ALU_Op(3) <= '1';
-			ALU_Op(2 downto 0) <= IR(7 downto 5);
-			case IR(7 downto 5) is
-			when "000" =>
-				if IR(4 downto 2) = "110" then
-					-- INC
-					ALU_Op <= "1111";
-				end if;
-			when "001" =>
-				if IR(4 downto 2) = "110" then
-					-- DEC
-					ALU_Op <= "1110";
-				end if;
-			when "100" =>
-				if IR(4 downto 2) = "010" then
-					-- TXA
-					ALU_Op <= "0101";
-				else
-					ALU_Op <= "0100";
-				end if;
-			when others =>
-			end case;
-		--}}}
-		when others =>
-		--{{{
-			case IR(7 downto 5) is
-			when "100" =>
-				ALU_Op <= "0100";
-			when others =>
-				if MCycle = "000" then
-					ALU_Op(3) <= '0';
-					ALU_Op(2 downto 0) <= IR(7 downto 5);
-				else
-					ALU_Op(3) <= '1';
-					ALU_Op(2 downto 0) <= IR(7 downto 5);
-				end if;
-			end case;
-		--}}}
-		end case;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65_Pack.vhd
deleted file mode 100644
index e025e1bf..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/T65_Pack.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
--- ****
--- T65(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 Bugfixes by ehenciak added
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- 65xx compatible microprocessor core
---
--- Version : 0246
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t65/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T65_Pack is
-
-	constant Flag_C : integer := 0;
-	constant Flag_Z : integer := 1;
-	constant Flag_I : integer := 2;
-	constant Flag_D : integer := 3;
-	constant Flag_B : integer := 4;
-	constant Flag_1 : integer := 5;
-	constant Flag_V : integer := 6;
-	constant Flag_N : integer := 7;
-
-	component T65_MCode
-	port(
-		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
-		IR                      : in  std_logic_vector(7 downto 0);
-		MCycle                  : in  std_logic_vector(2 downto 0);
-		P                       : in  std_logic_vector(7 downto 0);
-		LCycle                  : out std_logic_vector(2 downto 0);
-		ALU_Op                  : out std_logic_vector(3 downto 0);
-		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
-		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
-		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
-		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
-		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
-		BreakAtNA               : out std_logic;
-		ADAdd                   : out std_logic;
-		AddY                    : out std_logic;
-		PCAdd                   : out std_logic;
-		Inc_S                   : out std_logic;
-		Dec_S                   : out std_logic;
-		LDA                     : out std_logic;
-		LDP                     : out std_logic;
-		LDX                     : out std_logic;
-		LDY                     : out std_logic;
-		LDS                     : out std_logic;
-		LDDI                    : out std_logic;
-		LDALU                   : out std_logic;
-		LDAD                    : out std_logic;
-		LDBAL                   : out std_logic;
-		LDBAH                   : out std_logic;
-		SaveP                   : out std_logic;
-		Write                   : out std_logic
-	);
-	end component;
-
-	component T65_ALU
-	port(
-		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
-		Op      : in  std_logic_vector(3 downto 0);
-		BusA    : in  std_logic_vector(7 downto 0);
-		BusB    : in  std_logic_vector(7 downto 0);
-		P_In    : in  std_logic_vector(7 downto 0);
-		P_Out   : out std_logic_vector(7 downto 0);
-		Q       : out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/addec_prom.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/addec_prom.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/greybox_tmp/cbx_args.txt b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/greybox_tmp/cbx_args.txt
deleted file mode 100644
index deea9283..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/greybox_tmp/cbx_args.txt	
+++ /dev/null
@@ -1,16 +0,0 @@
-ADDRESS_ACLR_A=NONE
-CLOCK_ENABLE_INPUT_A=BYPASS
-CLOCK_ENABLE_OUTPUT_A=BYPASS
-INIT_FILE=../roms/6400-01m2.hex
-INTENDED_DEVICE_FAMILY="Cyclone III"
-NUMWORDS_A=256
-OPERATION_MODE=ROM
-OUTDATA_ACLR_A=NONE
-OUTDATA_REG_A=UNREGISTERED
-WIDTHAD_A=8
-WIDTH_A=4
-WIDTH_BYTEENA_A=1
-DEVICE_FAMILY="Cyclone III"
-address_a
-clock0
-q_a
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/j6_prom.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/j6_prom.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/k6_prom.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/k6_prom.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/prog_rom1.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/prog_rom1.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/prog_rom2.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/prog_rom2.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/prog_rom3.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/prog_rom3.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/prog_rom4.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/prog_rom4.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/ram1k_dp.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/ram1k_dp.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/sync_prom.qip b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/T65/sync_prom.qip
deleted file mode 100644
index e69de29b..00000000
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/build_id.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/build_id.sv
index d1fe1923..a4e69e93 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/build_id.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/build_id.sv	
@@ -1,2 +1,2 @@
-`define BUILD_DATE "190421"
-`define BUILD_TIME "114651"
+`define BUILD_DATE "210524"
+`define BUILD_TIME "140250"
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/dac.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/dac.sv
deleted file mode 100644
index 25899384..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/dac.sv	
+++ /dev/null
@@ -1,33 +0,0 @@
-//
-// PWM DAC
-//
-// MSBI is the highest bit number. NOT amount of bits!
-//
-module dac #(parameter MSBI=7, parameter INV=1'b1)
-(
-   output reg      DACout, //Average Output feeding analog lowpass
-   input  [MSBI:0] DACin,  //DAC input (excess 2**MSBI)
-   input           CLK,
-   input           RESET
-);
-
-reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
-reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
-reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
-reg [MSBI+2:0] DeltaB;     //B input of Delta Adder
-
-always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
-always @(*) DeltaAdder = DACin + DeltaB;
-always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
-
-always @(posedge CLK or posedge RESET) begin
-   if(RESET) begin
-      SigmaLatch <= 1'b1 << (MSBI+1);
-      DACout <= INV;
-   end else begin
-      SigmaLatch <= SigmaAdder;
-      DACout <= SigmaLatch[MSBI+2] ^ INV;
-   end
-end
-
-endmodule
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/hq2x.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/joy2quad.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/joy2quad.sv
index dae1fa5f..cd439ebb 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/joy2quad.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/joy2quad.sv	
@@ -97,4 +97,4 @@ always @(posedge CLK) begin
  end
 end
 
-endmodule
\ No newline at end of file
+endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/mist_io.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/mist_io.sv
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/mist_io.sv	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/osd.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/osd.sv
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/osd.sv	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/scandoubler.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/scandoubler.sv
deleted file mode 100644
index 0213d20c..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/scandoubler.sv	
+++ /dev/null
@@ -1,195 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv
index 4a119212..dd698a91 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv	
@@ -1,3 +1,4 @@
+//FPGA implementation of Super Breakout arcade game released by Atari in 1978
 module super_breakout_mist(
 	output        LED,
 	output  [5:0] VGA_R,
@@ -24,8 +25,8 @@ localparam CONF_STR = {
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
 	"O5,Color,On,Off;",
-	"T6,Reset;",
-	"V,v1.25.",`BUILD_DATE
+	"T0,Reset;",
+	"V,v1.30.",`BUILD_DATE
 	};
     
 assign AUDIO_R = AUDIO_L;
@@ -36,18 +37,20 @@ pll pll(
 	.inclk0(CLOCK_27),
 	.c0(clk_24),//24.192
 	.c1(clk_12),//12.096
-	.c2(clk_6),//6.048
 	.locked(locked)
 	);
 
 	
-wire [31:0] status;
+wire [63:0] status;
 wire  [1:0] buttons;
 wire  [1:0] switches;
-wire  [7:0] joystick_0, joystick_1;
+wire [31:0] joystick_0, joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire        no_csync;
 wire  [7:0] audio;
 wire			video;
 wire  [2:0] r,g;
@@ -56,23 +59,23 @@ wire 			hs, vs;
 
 super_breakout super_breakout(
 	.clk_12(clk_12),
-	.Reset_n(~(status[0] | status[6] | buttons[1])),			
+	.Reset_n(~(status[0] | buttons[1])),			
 	.HS(hs),
 	.VS(vs),
 	.Video_O(video),
 	.Video_RGB({r,g,b}),
 	.Audio_O(audio),
-	.Coin1_I(~btn_coin),
-	.Coin2_I(1'b1),
-	.Start1_I(~btn_one_player),
-	.Start2_I(1'b1),
-	.Select1_I(),
-	.Select2_I(),
+	.Coin1_I(~m_coin1),
+	.Coin2_I(~m_coin2),
+	.Start1_I(~m_one_player),
+	.Start2_I(~m_two_players),
+	.Select1_I(~m_fireB),
+	.Select2_I(~m_fire2B),
 	.Enc_A(steer[1]),
 	.Enc_B(steer[0]),
 	.Pot_Comp1_I(),
-	.Slam_I(1'b1),
-	.Serve_I(~(btn_fire2 | joystick_0[4] | joystick_1[4])),
+	.Slam_I(~m_tilt),
+	.Serve_I(~(m_fireA | m_fire2A)),
 	.Test_I(~status[1]),	
 	.Lamp1_O(),
 	.Lamp2_O(),
@@ -81,101 +84,91 @@ super_breakout super_breakout(
 	);
 	
 dac #(
-	.MSBI(7))
-dac(
-	.CLK(clk_24),
-	.RESET(1'b0),
-	.DACin(audio),
-	.DACout(AUDIO_L)
+	.C_bits(8))
+dac_l(
+	.clk_i(clk_24),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
 	);
 
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
+mist_video #(
+	.COLOR_DEPTH(3), 
+	.SD_HCNT_WIDTH(9)) 
+mist_video(
+	.clk_sys        ( clk_24           ),
+	.SPI_SCK        ( SPI_SCK          ),
+	.SPI_SS3        ( SPI_SS3          ),
+	.SPI_DI         ( SPI_DI           ),
 	.R(~status[5] ? r : {video,video,video}),
 	.G(~status[5] ? g : {video,video,video}),
 	.B(~status[5] ? {b,1'b0} : {video,video,video}),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),//(left/right,on/off)
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3))) 
-mist_io(
-	.clk_sys        (clk_24   	     ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0	  ),
-	.joystick_1     (joystick_1	  ),
-	.status         (status         )
+	.HSync          ( hs               ),
+	.VSync          ( vs               ),
+	.VGA_R          ( VGA_R            ),
+	.VGA_G          ( VGA_G            ),
+	.VGA_B          ( VGA_B            ),
+	.VGA_VS         ( VGA_VS           ),
+	.VGA_HS         ( VGA_HS           ),
+	.scanlines      (scandoublerD ? 2'b00 : status[4:3]),
+//	.rotate         ( { 1'b1, rotate } ),
+//	.ce_divider     ( 1'b1             ),
+	.blend          ( status[6]        ),
+	.scandoubler_disable(scandoublerD  ),
+	.no_csync       ( no_csync         ),
+	.ypbpr          ( ypbpr            )
 	);
 	
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire1 			<= pressed; // ctrl
-			'h11: btn_fire1 			<= pressed; // alt
-			'h29: btn_fire2   		<= pressed; // Space
-		endcase
-	end
-end
-
-wire m_left   = ~status[2] ? (btn_up | joystick_0[3] | joystick_1[3]) : (btn_left | joystick_0[1] | joystick_1[1]);
-wire m_right  = ~status[2] ? (btn_down | joystick_0[2] | joystick_1[2]) : (btn_right | joystick_0[0] | joystick_1[0]);
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_24         ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
 
 wire [1:0] steer;
 joy2quad steer1(
 	.CLK(clk_24),
 	.clkdiv('d22500),	
-	.right(m_right),
-	.left(m_left),	
+	.right(m_right | m_right2),
+	.left(m_left | m_left2),	
 	.steer(steer)
 	);
+	
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+	.clk         ( clk_24      ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+//	.rotate      ( rotate      ),
+//	.orientation ( 2'b11       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b0        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
+	
 
 endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/video_mixer.sv b/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/video_mixer.sv
deleted file mode 100644
index af9b2c56..00000000
--- a/Arcade_MiST/Atari BW Raster Hardware/SuperBreakout_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,244 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/ultratank_mist.sv b/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/ultratank_mist.sv
index e74bf7b5..b26a3099 100644
--- a/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/ultratank_mist.sv	
+++ b/Arcade_MiST/Atari BW Raster Hardware/UltraTank_MiST/rtl/ultratank_mist.sv	
@@ -29,9 +29,9 @@ localparam CONF_STR = {
 	"O2,Invisible,Off,On;",
 	"O5,Rebound,Off,On;",
 	"O7,Barrier,Off,On;",
-// mn	"O6,Blend,Off,On;",
+// 	"O6,Blend,Off,On;",
 	"OC,Color,Off,On;",
-	"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+	"O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
 	"T0,Reset;",
 	"V,v1.10.",`BUILD_DATE
 };
@@ -166,9 +166,9 @@ mist_video(
 	.SPI_SCK        ( SPI_SCK          ),
 	.SPI_SS3        ( SPI_SS3          ),
 	.SPI_DI         ( SPI_DI           ),
-	.R					 (blankn ? r : 0	  ),
-	.G					 (blankn ? g : 0	  ),
-	.B					 (blankn ? b : 0	  ),
+	.R			(blankn ? r : 0	   ),
+	.G			(blankn ? g : 0	   ),
+	.B			(blankn ? b : 0	   ),
 	.HSync          ( hs               ),
 	.VSync          ( vs               ),
 	.VGA_R          ( VGA_R            ),
@@ -181,7 +181,7 @@ mist_video(
 //	.ce_divider     ( 1'b1             ),
 	.blend          ( status[6]        ),
 	.scandoubler_disable(scandoublerD  ),
-	.no_csync       ( 1'b1             ),
+	.no_csync       ( no_csync         ),
 	.ypbpr          ( ypbpr            )
 	);