From 3581b3ef24ac9702182d2463cde4ef323ad72d6e Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sat, 7 Dec 2019 23:14:28 +0100 Subject: [PATCH] Fix a possible bug in the SDRAM controller - current cores are not affected --- .../Midway MCR 3/Demolition Derby_MiST/rtl/sdram.sv | 9 +++++++-- Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/rtl/sdram.sv | 9 +++++++-- Arcade_MiST/Midway MCR 3/Tapper_MiST/rtl/sdram.sv | 9 +++++++-- Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/sdram.sv | 9 +++++++-- .../Tehkan Bombjack Hardware/Bomb Jack/rtl/sdram.sv | 9 +++++++-- 5 files changed, 35 insertions(+), 10 deletions(-) diff --git a/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/rtl/sdram.sv b/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/rtl/sdram.sv index 49ea563d..41f5b7a8 100644 --- a/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/rtl/sdram.sv +++ b/Arcade_MiST/Midway MCR 3/Demolition Derby_MiST/rtl/sdram.sv @@ -159,6 +159,9 @@ reg [1:0] oe_latch; reg [1:0] we_latch; reg [1:0] ds[2]; +reg port1_state; +reg port2_state; + localparam PORT_NONE = 2'd0; localparam PORT_CPU1 = 2'd1; localparam PORT_CPU2 = 2'd2; @@ -177,7 +180,7 @@ always @(*) begin if (refresh) begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; - end else if (port1_req ^ port1_ack) begin + end else if (port1_req ^ port1_state) begin next_port[0] = PORT_REQ; addr_latch_next[0] = { 1'b0, port1_a }; end else if (cpu1_addr != addr_last[PORT_CPU1]) begin @@ -194,7 +197,7 @@ end // PORT1: bank 2,3 always @(*) begin - if (port2_req ^ port2_ack) begin + if (port2_req ^ port2_state) begin next_port[1] = PORT_REQ; addr_latch_next[1] = { 1'b1, port2_a }; end else if (sp_addr != addr_last2[PORT_SP]) begin @@ -251,6 +254,7 @@ always @(posedge clk) begin { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; ds[0] <= port1_ds; din_latch[0] <= port1_d; + port1_state <= port1_req; end else begin { oe_latch[0], we_latch[0] } <= 2'b10; ds[0] <= 2'b11; @@ -274,6 +278,7 @@ always @(posedge clk) begin { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; ds[1] <= port2_ds; din_latch[1] <= port2_d; + port2_state <= port2_req; end else begin { oe_latch[1], we_latch[1] } <= 2'b10; ds[1] <= 2'b11; diff --git a/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/rtl/sdram.sv b/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/rtl/sdram.sv index 49ea563d..41f5b7a8 100644 --- a/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/rtl/sdram.sv +++ b/Arcade_MiST/Midway MCR 3/Discs of Tron_MiST/rtl/sdram.sv @@ -159,6 +159,9 @@ reg [1:0] oe_latch; reg [1:0] we_latch; reg [1:0] ds[2]; +reg port1_state; +reg port2_state; + localparam PORT_NONE = 2'd0; localparam PORT_CPU1 = 2'd1; localparam PORT_CPU2 = 2'd2; @@ -177,7 +180,7 @@ always @(*) begin if (refresh) begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; - end else if (port1_req ^ port1_ack) begin + end else if (port1_req ^ port1_state) begin next_port[0] = PORT_REQ; addr_latch_next[0] = { 1'b0, port1_a }; end else if (cpu1_addr != addr_last[PORT_CPU1]) begin @@ -194,7 +197,7 @@ end // PORT1: bank 2,3 always @(*) begin - if (port2_req ^ port2_ack) begin + if (port2_req ^ port2_state) begin next_port[1] = PORT_REQ; addr_latch_next[1] = { 1'b1, port2_a }; end else if (sp_addr != addr_last2[PORT_SP]) begin @@ -251,6 +254,7 @@ always @(posedge clk) begin { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; ds[0] <= port1_ds; din_latch[0] <= port1_d; + port1_state <= port1_req; end else begin { oe_latch[0], we_latch[0] } <= 2'b10; ds[0] <= 2'b11; @@ -274,6 +278,7 @@ always @(posedge clk) begin { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; ds[1] <= port2_ds; din_latch[1] <= port2_d; + port2_state <= port2_req; end else begin { oe_latch[1], we_latch[1] } <= 2'b10; ds[1] <= 2'b11; diff --git a/Arcade_MiST/Midway MCR 3/Tapper_MiST/rtl/sdram.sv b/Arcade_MiST/Midway MCR 3/Tapper_MiST/rtl/sdram.sv index 49ea563d..41f5b7a8 100644 --- a/Arcade_MiST/Midway MCR 3/Tapper_MiST/rtl/sdram.sv +++ b/Arcade_MiST/Midway MCR 3/Tapper_MiST/rtl/sdram.sv @@ -159,6 +159,9 @@ reg [1:0] oe_latch; reg [1:0] we_latch; reg [1:0] ds[2]; +reg port1_state; +reg port2_state; + localparam PORT_NONE = 2'd0; localparam PORT_CPU1 = 2'd1; localparam PORT_CPU2 = 2'd2; @@ -177,7 +180,7 @@ always @(*) begin if (refresh) begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; - end else if (port1_req ^ port1_ack) begin + end else if (port1_req ^ port1_state) begin next_port[0] = PORT_REQ; addr_latch_next[0] = { 1'b0, port1_a }; end else if (cpu1_addr != addr_last[PORT_CPU1]) begin @@ -194,7 +197,7 @@ end // PORT1: bank 2,3 always @(*) begin - if (port2_req ^ port2_ack) begin + if (port2_req ^ port2_state) begin next_port[1] = PORT_REQ; addr_latch_next[1] = { 1'b1, port2_a }; end else if (sp_addr != addr_last2[PORT_SP]) begin @@ -251,6 +254,7 @@ always @(posedge clk) begin { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; ds[0] <= port1_ds; din_latch[0] <= port1_d; + port1_state <= port1_req; end else begin { oe_latch[0], we_latch[0] } <= 2'b10; ds[0] <= 2'b11; @@ -274,6 +278,7 @@ always @(posedge clk) begin { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; ds[1] <= port2_ds; din_latch[1] <= port2_d; + port2_state <= port2_req; end else begin { oe_latch[1], we_latch[1] } <= 2'b10; ds[1] <= 2'b11; diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/sdram.sv b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/sdram.sv index 49ea563d..41f5b7a8 100644 --- a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/sdram.sv +++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/sdram.sv @@ -159,6 +159,9 @@ reg [1:0] oe_latch; reg [1:0] we_latch; reg [1:0] ds[2]; +reg port1_state; +reg port2_state; + localparam PORT_NONE = 2'd0; localparam PORT_CPU1 = 2'd1; localparam PORT_CPU2 = 2'd2; @@ -177,7 +180,7 @@ always @(*) begin if (refresh) begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; - end else if (port1_req ^ port1_ack) begin + end else if (port1_req ^ port1_state) begin next_port[0] = PORT_REQ; addr_latch_next[0] = { 1'b0, port1_a }; end else if (cpu1_addr != addr_last[PORT_CPU1]) begin @@ -194,7 +197,7 @@ end // PORT1: bank 2,3 always @(*) begin - if (port2_req ^ port2_ack) begin + if (port2_req ^ port2_state) begin next_port[1] = PORT_REQ; addr_latch_next[1] = { 1'b1, port2_a }; end else if (sp_addr != addr_last2[PORT_SP]) begin @@ -251,6 +254,7 @@ always @(posedge clk) begin { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; ds[0] <= port1_ds; din_latch[0] <= port1_d; + port1_state <= port1_req; end else begin { oe_latch[0], we_latch[0] } <= 2'b10; ds[0] <= 2'b11; @@ -274,6 +278,7 @@ always @(posedge clk) begin { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; ds[1] <= port2_ds; din_latch[1] <= port2_d; + port2_state <= port2_req; end else begin { oe_latch[1], we_latch[1] } <= 2'b10; ds[1] <= 2'b11; diff --git a/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/rtl/sdram.sv b/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/rtl/sdram.sv index 49ea563d..41f5b7a8 100644 --- a/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/rtl/sdram.sv +++ b/Arcade_MiST/Tehkan Bombjack Hardware/Bomb Jack/rtl/sdram.sv @@ -159,6 +159,9 @@ reg [1:0] oe_latch; reg [1:0] we_latch; reg [1:0] ds[2]; +reg port1_state; +reg port2_state; + localparam PORT_NONE = 2'd0; localparam PORT_CPU1 = 2'd1; localparam PORT_CPU2 = 2'd2; @@ -177,7 +180,7 @@ always @(*) begin if (refresh) begin next_port[0] = PORT_NONE; addr_latch_next[0] = addr_latch[0]; - end else if (port1_req ^ port1_ack) begin + end else if (port1_req ^ port1_state) begin next_port[0] = PORT_REQ; addr_latch_next[0] = { 1'b0, port1_a }; end else if (cpu1_addr != addr_last[PORT_CPU1]) begin @@ -194,7 +197,7 @@ end // PORT1: bank 2,3 always @(*) begin - if (port2_req ^ port2_ack) begin + if (port2_req ^ port2_state) begin next_port[1] = PORT_REQ; addr_latch_next[1] = { 1'b1, port2_a }; end else if (sp_addr != addr_last2[PORT_SP]) begin @@ -251,6 +254,7 @@ always @(posedge clk) begin { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we }; ds[0] <= port1_ds; din_latch[0] <= port1_d; + port1_state <= port1_req; end else begin { oe_latch[0], we_latch[0] } <= 2'b10; ds[0] <= 2'b11; @@ -274,6 +278,7 @@ always @(posedge clk) begin { oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we }; ds[1] <= port2_ds; din_latch[1] <= port2_d; + port2_state <= port2_req; end else begin { oe_latch[1], we_latch[1] } <= 2'b10; ds[1] <= 2'b11;