diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/README.txt b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/README.txt
new file mode 100644
index 00000000..b6a5db53
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/README.txt
@@ -0,0 +1,308 @@
+-- Super Zaxxon port to MiST
+--
+-- Usage:
+-- Create SZAXXON.ROM from MAME ROM zaxxon.zip file using the mra utility and the SZaxxon.mra file.
+-- Example: mra -A -z /path/to/mame/roms SZaxxon.mra
+
+-- Copy the SZAXXON.ROM file to the root of the SD Card.
+--
+-- Sound is optional, if you created the ROM with the samples, then enable sound in the OSD menu!
+--
+-- MRA utilty: https://github.com/sebdel/mra-tools-c
+--
+---------------------------------------------------------------------------------
+-- DE10_lite Top level for Zaxxon by Dar (darfpga@aol.fr) (23/11/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+-- Use zaxxon_de10_lite.sdc to compile (Timequest constraints)
+-- /!\
+-- Don't forget to set device configuration mode with memory initialization
+-- (Assignments/Device/Pin options/Configuration mode)
+---------------------------------------------------------------------------------
+--
+-- release rev 00 : initial release
+-- (23/11/2019)
+---------------------------------------------------------------------------------
+--
+-- Main features :
+-- PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection)
+-- Audio pwm output @gpio pins 1/3 (beware voltage translation/protection)
+--
+-- Video : TV 15kHz
+-- Cocktail mode : Yes
+-- Sound : No (atm)
+--
+-- For hardware schematic see my other project : NES
+--
+-- Uses 1 pll 24MHz from 50MHz
+--
+-- Board key :
+-- 0 : reset game
+--
+-- Keyboard players inputs :
+--
+-- F1 : Add coin
+-- F2 : Start 1 player
+-- F3 : Start 2 players
+
+-- SPACE : fire
+-- RIGHT arrow : move right
+-- LEFT arrow : move left
+-- UP arrow : move up
+-- DOWN arrow : move down
+--
+-- F4 : flip screen (additional feature)
+-- F5 : Service mode ?! (not tested)
+-- F7 : uprigth/cocktail mode (required reset)
+
+--
+-- Other details : see zaxxon.vhd
+-- For USB inputs and SGT5000 audio output see my other project: xevious_de10_lite
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+-- Zaxxon by Dar (darfpga@aol.fr) (23/11/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+--
+-- release rev 00 : initial release
+-- (23/11/2019)
+---------------------------------------------------------------------------------
+-- gen_ram.vhd & io_ps2_keyboard
+--------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- T80/T80se - Version : 304
+-----------------------------
+-- Z80 compatible microprocessor core
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+
+-- Features :
+-- Video : TV 15kHz
+-- Coctail mode : Yes
+-- Sound : No (atm)
+
+-- Use with MAME roms from zaxxon.zip
+--
+-- Use make_zaxxon_proms.bat to build vhd file from binaries
+-- (CRC list included)
+
+-- Zaxxon (Gremlin/SEGA) Hardware caracteristics :
+--
+-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram,
+-- sprite data ram, I/O, sound board register and trigger.
+-- 20Kx8bits program rom
+--
+-- 3 graphic layers
+--
+-- One char map 32x28 tiles
+-- 2x2Kx8bits graphics rom 2bits/pixel
+-- static layout color rom 16 color/tile
+--
+-- One diagonal scrolling background map 8x8 tiles
+-- 4x8Kx8bits tile map rom (10 bits code + 4bits color)
+-- 3x8Kx8bits graphics rom 3bits/pixel
+--
+-- 32 sprites, up to 8/scanline 32x32pixels with flip H/V
+-- 6bits code + 2 bits flip h/v, 5 bits color
+-- 3x8Kx8bits graphics rom 3bits/pixel
+--
+-- general palette 256 colors 3red 3green 2blue
+-- char 2bits/tile + 4bits color set/tile + 1bits global set
+-- background 3bits/tile + 4 bits color set/tile + 1bits global set
+-- sprites 3bits/sprite + 5 bits color set/sprite
+--
+-- Working ram : 4Kx8bits
+-- char ram : 1Kx8bits code, (+ static layout color rom)
+-- sprites ram : 256x8bits + 32x9bits intermediate buffer + 256x8bits line buffer
+--
+
+-- SOUND : see zaxxon_sound_board.vhd
+
+---------------------------------------------------------------------------------
+-- Schematics remarks : IC board 834-0214 and 834-0257 or 834-0211
+-- some details are missing or seems to be wrong:
+-- - sprite buffer addresses flip control seems to be incomplete
+-- (fliping adresses both at read and write is useless !)
+-- - diagonal scrolling seems to be incomplete (BCK on U52 pin 4 where from ?)
+-- - 834-0211 sheet 6 of 9 : 74ls161 U26 at C-5 no ouput used !
+-- - 834-0211 sheet 7 of 9 : /128H, 128H and 256H dont agree with U21 Qc/Qd
+-- output !
+--
+-- tips :
+-- Background tiles scrolls over H (and V) but map rom output are latched
+-- at fixed Hcnt position (4H^). Graphics rom ouput latch is scrolled over H.
+--
+-- During visible area (hcnt(8) = 1) sprite data are transfered from sp_ram
+-- to sp_online_ram. Only sprites visible on (next) line are transfered. So
+-- 64 sprites are defined in sp_ram and only 8 can be transfered to
+-- sp_online_ram.
+--
+-- During line fly back (hcnt(8) = 0) sp_online_ram is read and sprite
+-- graphics feed line buffer. Line buffer is then read starting from
+-- visible line.
+--
+-- Sprite data transfer is done at pixel rate : each sprite is 4 bytes data.
+-- Visible area allows 64 sprites x 4 data (256 pixels) to be read, only 8
+-- sprites (the ones on next line) are transfered.
+--
+-- Line buffer feed is done at twice pixel rate : 8 sprites x 32 pixels / 2
+-- (256/2 = 128 pixels = fly back area length).
+--
+-- sp_online_ram is 9 bits wide. 9th bits is set during tranfer for actual
+-- sprites data written. 9th bit is reset during fly back area after data
+-- are read. So 9th bits are all set to 0s at start of next transfer.
+--
+-- When feeding line buffer sprites graphic data are written only of no
+-- graphics have been written previouly for that line. Line buffer pixels are
+-- set to 0s after each pixel read during visible area. Thus line buffer is
+-- fully cleared at start of next feeding.
+--
+-- Global screen flip is fully managed at hardware level. This allow to
+-- easily add an external flip screen feature.
+
++----------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+---------------------------------------------+
+; Fitter Status ; Successful - Fri Nov 29 21:07:56 2019 ;
+; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
+; Revision Name ; zaxxon_de10_lite ;
+; Top-level Entity Name ; zaxxon_de10_lite ;
+; Family ; MAX 10 ;
+; Device ; 10M50DAF484C6GES ;
+; Timing Models ; Preliminary ;
+; Total logic elements ; 2,754 / 49,760 ( 6 % ) ;
+; Total combinational functions ; 2,646 / 49,760 ( 5 % ) ;
+; Dedicated logic registers ; 653 / 49,760 ( 1 % ) ;
+; Total registers ; 653 ;
+; Total pins ; 105 / 360 ( 29 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 867,616 / 1,677,312 ( 52 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
+; Total PLLs ; 1 / 4 ( 25 % ) ;
+; UFM blocks ; 0 / 1 ( 0 % ) ;
+; ADC blocks ; 0 / 2 ( 0 % ) ;
++------------------------------------+---------------------------------------------+
+
+---------------
+VHDL File list
+---------------
+
+de10_lite/max10_pll_24M.vhd Pll 24MHz from 50MHz altera mf
+
+rtl_dar/zaxxon_de10_lite.vhd Top level for de10_lite board
+rtl_dar/zaxxon.vhd Main CPU and video boards logic
+
+rtl_T80_304/T80se.vhdT80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+rtl_T80_304/T80_Reg.vhd
+rtl_T80_304/T80_Pack.vhd
+rtl_T80_304/T80_MCode.vhd
+rtl_T80_304/T80_ALU.vhd
+rtl_T80_304/T80.vhd
+
+rtl_dar/kbd_joystick.vhd Keyboard key to player/coin input
+rtl_dar/io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+rtl_dar/gen_ram.vhd Generic RAM (Peter Wendrich + DAR Modification)
+rtl_dar/decodeur_7_seg.vhd 7 segments display decoder
+
+rtl_dar/proms/zaxxon_cpu.vhd CPU board PROMS
+rtl_dar/proms/zaxxon_char_bits_2.vhd
+rtl_dar/proms/zaxxon_char_bits_1.vhd
+rtl_dar/proms/zaxxon_char_color.vhd
+rtl_dar/proms/zaxxon_palette.vhd
+
+rtl_dar/proms/zaxxon_map_2.vhd Video board PROMS
+rtl_dar/proms/zaxxon_map_1.vhd
+rtl_dar/proms/zaxxon_sp_bits_3.vhd
+rtl_dar/proms/zaxxon_sp_bits_2.vhd
+rtl_dar/proms/zaxxon_sp_bits_1.vhd
+rtl_dar/proms/zaxxon_bg_bits_3.vhd
+rtl_dar/proms/zaxxon_bg_bits_2.vhd
+rtl_dar/proms/zaxxon_bg_bits_1.vhd
+
+----------------------
+Quartus project files
+----------------------
+de10_lite/zaxxon_de10_lite.sdc Timequest constraints file
+de10_lite/zaxxon_de10_lite.qsf de10_lite settings (files,pins...)
+de10_lite/zaxxon_de10_lite.qpf de10_lite project
+
+-----------------------------
+Required ROMs (Not included)
+-----------------------------
+You need the following 17 ROMs binary files from zaxxon.zip (MAME)
+
+zaxxon_rom3d.u27 CRC 6e2b4a30
+zaxxon_rom2d.u28 CRC 1c9ea398
+zaxxon_rom1d.u29 CRC 1c123ef9
+zaxxon_rom14.u68 CRC 07bf8c52
+zaxxon_rom15.u69 CRC c215edcb
+zaxxon_rom6.u113 CRC 6e07bb68
+zaxxon_rom5.u112 CRC 0a5bce6a
+zaxxon_rom4.u111 CRC a5bf1465
+zaxxon_rom11.u77 CRC eaf0dd4b
+zaxxon_rom12.u78 CRC 1c5369c7
+zaxxon_rom13.u79 CRC ab4e8a9a
+zaxxon_rom8.u91 CRC 28d65063
+zaxxon_rom7.u90 CRC 6284c200
+zaxxon_rom10.u93 CRC a95e61fd
+zaxxon_rom9.u92 CRC 7e42691f
+mro16.u76 CRC 6cc6695b (or zaxxon.u98)
+zaxxon.u72 CRC deaa21f7
+
+------
+Tools
+------
+You need to build vhdl files from the binary file :
+ - Unzip the roms file in the tools/zaxxon_unzip directory
+ - Double click (execute) the script tools/make_zaxxon_proms.bat to get the following 13 files
+
+zaxxon_cpu.vhd
+zaxxon_char_bits_1.vhd
+zaxxon_char_bits_2.vhd
+zaxxon_bg_bits_1.vhd
+zaxxon_bg_bits_2.vhd
+zaxxon_bg_bits_3.vhd
+zaxxon_sp_bits_1.vhd
+zaxxon_sp_bits_2.vhd
+zaxxon_sp_bits_3.vhd
+zaxxon_map_1.vhd
+zaxxon_map_2.vhd
+zaxxon_palette.vhd
+zaxxon_char_color.vhd
+
+*DO NOT REDISTRIBUTE THESE FILES*
+
+VHDL files are needed to compile and include roms into the project
+
+The script make_tron_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux.
+
+Source code of make_vhdl_prom.c is also delivered.
+
+---------------------------------
+Compiling for de10_lite
+---------------------------------
+You can build the project with ROM image embeded in the sof file.
+*DO NOT REDISTRIBUTE THESE FILES*
+
+3 steps
+
+ - put the VHDL ROM files (.vhd) into the rtl_dar/proms directory
+ - build zaxxon_de10_lite
+ - program zaxxon_de10_lite.sof
+
+------------------------
+------------------------
+End of file
+------------------------
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/SuperZaxxon.qpf b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/SuperZaxxon.qpf
new file mode 100644
index 00000000..86dbfc67
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/SuperZaxxon.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 00:21:03 December 03, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "00:21:03 December 03, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "SuperZaxxon"
+
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/SuperZaxxon.qsf b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/SuperZaxxon.qsf
new file mode 100644
index 00000000..68bae1c2
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/SuperZaxxon.qsf
@@ -0,0 +1,229 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 13:14:18 November 17, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# Timber_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY SuperZaxxon_MiST
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# -------------------------
+# start ENTITY(DoTron_MiST)
+
+ # start DESIGN_PARTITION(Top)
+ # ---------------------------
+
+ # Incremental Compilation Assignments
+ # ===================================
+
+ # end DESIGN_PARTITION(Top)
+ # -------------------------
+
+# end ENTITY(DoTron_MiST)
+# -----------------------
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/zaxx.stp
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SuperZaxxon_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/zaxxon.vhd
+set_global_assignment -name VHDL_FILE rtl/zaxxon_sound.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/dec_315_5013.vhd
+set_global_assignment -name VERILOG_FILE rtl/Sega_Crypt.v
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/SuperZaxxon.sdc b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/SuperZaxxon.sdc
new file mode 100644
index 00000000..33ffd42f
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/SuperZaxxon.sdc
@@ -0,0 +1,134 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions
+## and other software and tools, and its AMPP partner logic
+## functions, and any output files from any of the foregoing
+## (including device programming or simulation files), and any
+## associated documentation or information are expressly subject
+## to the terms and conditions of the Altera Program License
+## Subscription Agreement, Altera MegaCore Function License
+## Agreement, or other applicable license agreement, including,
+## without limitation, that your use is for the sole purpose of
+## programming logic devices manufactured by Altera and sold by
+## Altera or its authorized distributors. Please refer to the
+## applicable agreement for further details.
+
+
+## VENDOR "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
+
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
+set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/clean.bat b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/clean.bat
new file mode 100644
index 00000000..b3b7c3b5
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/clean.bat
@@ -0,0 +1,37 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+
+pause
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/meta/SZaxxon.mra b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/meta/SZaxxon.mra
new file mode 100644
index 00000000..80b385e2
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/meta/SZaxxon.mra
@@ -0,0 +1,36 @@
+
+ SZaxxon
+ 0193
+ 202003290000
+ 1982
+ Sega/Gremlin
+ Isometric Shoot'em up
+ Space
+ szaxxon
+ szaxxon
+
+
+
+
+ FF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/Sega_Crypt.v b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/Sega_Crypt.v
new file mode 100644
index 00000000..7228a870
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/Sega_Crypt.v
@@ -0,0 +1,39 @@
+module Sega_Crypt
+(
+ input clk,
+
+ input mrom_m1,
+ input [14:0] mrom_ad,
+ output reg [7:0] mrom_dt,
+ output [14:0] cpu_rom_addr,
+ input [7:0] cpu_rom_do
+);
+
+reg [15:0] madr;
+wire [7:0] mdat;
+
+wire f = mdat[7];
+wire [7:0] xorv = { f, 1'b0, f, 1'b0, f, 3'b000 };
+wire [7:0] andv = ~(8'hA8);
+wire [1:0] decidx0 = { mdat[5], mdat[3] } ^ { f, f };
+wire [6:0] decidx = { madr[12], madr[8], madr[4], madr[0], ~madr[15], decidx0 };
+wire [7:0] dectbl;
+wire [7:0] mdec = ( mdat & andv ) | ( dectbl ^ xorv );
+
+dec_315_5013 dec_315_5013(
+ .clk(clk),
+ .addr(decidx),
+ .data(dectbl)
+);
+
+assign cpu_rom_addr = madr[14:0];
+assign mdat = cpu_rom_do;
+
+reg phase = 1'b0;
+always @( negedge clk ) begin
+ if ( phase ) mrom_dt <= mdec;
+ else madr <= { mrom_m1, mrom_ad };
+ phase <= ~phase;
+end
+
+endmodule
\ No newline at end of file
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/SuperZaxxon_MiST.sv b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/SuperZaxxon_MiST.sv
new file mode 100644
index 00000000..aee188d1
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/SuperZaxxon_MiST.sv
@@ -0,0 +1,298 @@
+
+module SuperZaxxon_MiST(
+ output LED,
+ output [5:0] VGA_R,
+ output [5:0] VGA_G,
+ output [5:0] VGA_B,
+ output VGA_HS,
+ output VGA_VS,
+ output AUDIO_L,
+ output AUDIO_R,
+ input SPI_SCK,
+ output SPI_DO,
+ input SPI_DI,
+ input SPI_SS2,
+ input SPI_SS3,
+ input CONF_DATA0,
+ input CLOCK_27,
+
+ output [12:0] SDRAM_A,
+ inout [15:0] SDRAM_DQ,
+ output SDRAM_DQML,
+ output SDRAM_DQMH,
+ output SDRAM_nWE,
+ output SDRAM_nCAS,
+ output SDRAM_nRAS,
+ output SDRAM_nCS,
+ output [1:0] SDRAM_BA,
+ output SDRAM_CLK,
+ output SDRAM_CKE
+);
+
+`include "rtl/build_id.v"
+
+localparam CONF_STR = {
+ "SZAXXON;ROM;",
+ "O2,Rotate Controls,Off,On;",
+ "O34,Scanlines,Off,25%,50%,75%;",
+ "O5,Blend,Off,On;",
+ "O6,Flip,Off,On;",
+ "O8,Sound,Off,On;",
+ "O9A,Lives,3,5,4,Free ships;",
+ "OBC,Extra ship,40k,20k,30k,10k;",
+ "T0,Reset;",
+ "V,v2.0.",`BUILD_DATE
+};
+
+wire rotate = status[2];
+wire [1:0] scanlines = status[4:3];
+wire blend = status[5];
+wire flip = status[6];
+wire service = status[7];
+wire sound = status[8];// deactivated for Now,
+wire [1:0] ships = ~status[10:9];
+wire [1:0] extraship = status[12:11];
+
+wire [7:0] sw1 = {1'b0, sound, ships, 2'b11, extraship }; // cocktail(1) / sound(1) / ships(2) / N.U.(2) / extra ship (2)
+
+assign LED = ~ioctl_downl;
+assign SDRAM_CLK = clk_sd;
+assign SDRAM_CKE = 1;
+assign AUDIO_R = AUDIO_L;
+
+wire clk_sys, clk_sd;
+wire pll_locked;
+pll_mist pll(
+ .inclk0(CLOCK_27),
+ .c0(clk_sd),//36
+ .c1(clk_sys),//24
+ .locked(pll_locked)
+ );
+
+wire [31:0] status;
+wire [1:0] buttons;
+wire [1:0] switches;
+wire [7:0] joystick_0;
+wire [7:0] joystick_1;
+wire key_pressed;
+wire key_strobe;
+wire [7:0] key_code;
+wire scandoublerD;
+wire ypbpr;
+wire no_csync;
+
+user_io #(
+ .STRLEN(($size(CONF_STR)>>3)))
+user_io(
+ .clk_sys (clk_sys ),
+ .conf_str (CONF_STR ),
+ .SPI_CLK (SPI_SCK ),
+ .SPI_SS_IO (CONF_DATA0 ),
+ .SPI_MISO (SPI_DO ),
+ .SPI_MOSI (SPI_DI ),
+ .buttons (buttons ),
+ .switches (switches ),
+ .scandoubler_disable (scandoublerD ),
+ .ypbpr (ypbpr ),
+ .no_csync (no_csync ),
+ .key_strobe (key_strobe ),
+ .key_pressed (key_pressed ),
+ .key_code (key_code ),
+ .joystick_0 (joystick_0 ),
+ .joystick_1 (joystick_1 ),
+ .status (status )
+ );
+
+wire [15:0] audio_l;
+wire hs, vs, cs, hb, vb;
+wire blankn;
+wire [2:0] g, r;
+wire [1:0] b;
+wire [14:0] rom_addr;
+wire [15:0] rom_do;
+wire [13:0] gfx_addr;
+wire [15:0] gfx_do;
+wire [19:0] wave_addr;
+wire [15:0] wave_do;
+wire ioctl_downl;
+wire [7:0] ioctl_index;
+wire ioctl_wr;
+wire [24:0] ioctl_addr;
+wire [7:0] ioctl_dout;
+
+// ROM structure
+// 00000-06FFF CPU ROM 28k u27-u28-u29-u29-u29
+// 07000-0EFFF Tiledata 32k u91-u90-u93-u92
+// 0F000-0F7FF char1 2k u68
+// 0F800-0FFFF char2 2k u69
+// 10000-05FFF bg 24k u113-u112-u111
+// 16000-1BFFF spr 24k u77-u78-u79
+// 1C000-1C0FF 256b u76
+// 1C100-1C1FF 256b u98
+
+data_io data_io(
+ .clk_sys ( clk_sys ),
+ .SPI_SCK ( SPI_SCK ),
+ .SPI_SS2 ( SPI_SS2 ),
+ .SPI_DI ( SPI_DI ),
+ .ioctl_download( ioctl_downl ),
+ .ioctl_index ( ioctl_index ),
+ .ioctl_wr ( ioctl_wr ),
+ .ioctl_addr ( ioctl_addr ),
+ .ioctl_dout ( ioctl_dout )
+);
+
+wire [24:0] gfx_ioctl_addr = ioctl_addr - 16'h7000;
+
+reg port1_req, port2_req;
+sdram #(36) sdram(
+ .*,
+ .init_n ( pll_locked ),
+ .clk ( clk_sd ),
+
+ // port1 used for main CPU
+ .port1_req ( port1_req ),
+ .port1_ack ( ),
+ .port1_a ( ioctl_addr[23:1] ),
+ .port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
+ .port1_we ( ioctl_downl ),
+ .port1_d ( {ioctl_dout, ioctl_dout} ),
+ .port1_q ( ),
+
+ .cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]}),
+ .cpu1_q ( rom_do ),
+ .snd_addr ( wave_addr[19:1] + 16'he100 ),
+ .snd_q ( wave_do ),
+
+ // port2 for gfx
+ .port2_req ( port2_req ),
+ .port2_ack ( ),
+ .port2_a ( {gfx_ioctl_addr[23:15], gfx_ioctl_addr[13:0]} ),
+ .port2_ds ( {gfx_ioctl_addr[14], ~gfx_ioctl_addr[14]} ),
+ .port2_we ( ioctl_downl ),
+ .port2_d ( {ioctl_dout, ioctl_dout} ),
+ .port2_q ( ),
+
+ .gfx_addr ( gfx_addr ),
+ .gfx_q ( gfx_do )
+);
+
+always @(posedge clk_sys) begin
+ reg ioctl_wr_last = 0;
+
+ ioctl_wr_last <= ioctl_wr;
+ if (ioctl_downl) begin
+ if (~ioctl_wr_last && ioctl_wr) begin
+ port1_req <= ~port1_req;
+ port2_req <= ~port2_req;
+ end
+ end
+end
+
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge clk_sd) begin
+ reg ioctl_downlD;
+ ioctl_downlD <= ioctl_downl;
+
+ if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+ reset <= status[0] | buttons[1] | ~rom_loaded;
+end
+
+wire dl_wr = ioctl_wr && ioctl_addr < 17'h1c200;
+
+zaxxon zaxxon(
+ .clock_24(clk_sys),
+ .reset(reset),
+
+ .video_r(r),
+ .video_g(g),
+ .video_b(b),
+ .video_blankn(blankn),
+ .video_hs(hs),
+ .video_vs(vs),
+ .video_csync(cs),
+
+ .audio_out_l(audio_l),
+
+ .coin1(m_coin1),
+ .coin2(m_coin2),
+ .start2(m_two_players),
+ .start1(m_one_player),
+ .left(m_left),
+ .right(m_right),
+ .up(m_up),
+ .down(m_down),
+ .fire(m_fireA),
+
+ .sw1_input(sw1), // cocktail(1) / sound(1) / ships(2) / N.U.(2) / extra ship (2)
+ .sw2_input(8'h33), // coin b(4) / coin a(4) -- "3" => 1c_1c
+
+ .flip_screen(flip),
+
+ .cpu_rom_addr ( rom_addr ),
+ .cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
+ .map_addr ( gfx_addr ),
+ .map_do ( gfx_do ),
+ .wave_addr ( wave_addr ),
+ .wave_data ( wave_do ),
+
+ .dl_addr ( ioctl_addr[16:0] ),
+ .dl_data ( ioctl_dout ),
+ .dl_wr ( dl_wr )
+);
+
+mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
+ .clk_sys ( clk_sys ),
+ .SPI_SCK ( SPI_SCK ),
+ .SPI_SS3 ( SPI_SS3 ),
+ .SPI_DI ( SPI_DI ),
+ .R ( blankn ? r : 0 ),
+ .G ( blankn ? g : 0 ),
+ .B ( blankn ? {b,b[1]} : 0 ),
+ .HSync ( hs ),
+ .VSync ( vs ),
+ .VGA_R ( VGA_R ),
+ .VGA_G ( VGA_G ),
+ .VGA_B ( VGA_B ),
+ .VGA_VS ( VGA_VS ),
+ .VGA_HS ( VGA_HS ),
+ .ce_divider ( 1'b1 ),
+ .blend ( blend ),
+ .rotate ( {flip, rotate} ),
+ .scandoubler_disable(scandoublerD ),
+ .scanlines ( scanlines ),
+ .ypbpr ( ypbpr ),
+ .no_csync ( no_csync )
+ );
+
+dac #(
+ .C_bits(16))
+dac(
+ .clk_i(clk_sys),
+ .res_n_i(status[8]),
+ .dac_i(audio_l),
+ .dac_o(AUDIO_L)
+ );
+
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+ .clk ( clk_sys ),
+ .key_strobe ( key_strobe ),
+ .key_pressed ( key_pressed ),
+ .key_code ( key_code ),
+ .joystick_0 ( joystick_0 ),
+ .joystick_1 ( joystick_1 ),
+ .rotate ( rotate ),
+ .orientation ( {flip, 1'b1} ),
+ .joyswap ( 1'b0 ),
+ .oneplayer ( 1'b1 ),
+ .controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+ .player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+ .player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
+
+endmodule
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/build_id.tcl b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/build_id.tcl
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+ # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+ set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+ set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+ # Create a Verilog file for output
+ set outputFileName "rtl/build_id.v"
+ set outputFile [open $outputFileName "w"]
+
+ # Output the Verilog source
+ puts $outputFile "`define BUILD_DATE \"$buildDate\""
+ puts $outputFile "`define BUILD_TIME \"$buildTime\""
+ close $outputFile
+
+ # Send confirmation message to the Messages window
+ post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+ post_message "Date: $buildDate"
+ post_message "Time: $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/dpram.vhd b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..284194c5
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/dpram.vhd
@@ -0,0 +1,81 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr)
+-- http://darfpga.blogspot.fr
+-- Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- dpram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity dpram is
+ generic (
+ dWidth : integer := 8;
+ aWidth : integer := 10
+ );
+ port (
+ clk_a : in std_logic;
+ we_a : in std_logic := '0';
+ addr_a : in std_logic_vector((aWidth-1) downto 0);
+ d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
+ q_a : out std_logic_vector((dWidth-1) downto 0);
+
+ clk_b : in std_logic;
+ we_b : in std_logic := '0';
+ addr_b : in std_logic_vector((aWidth-1) downto 0);
+ d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
+ q_b : out std_logic_vector((dWidth-1) downto 0)
+ );
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of dpram is
+ subtype addressRange is integer range 0 to ((2**aWidth)-1);
+ type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+ signal ram: ramDef;
+ signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
+ signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
+begin
+
+-- -----------------------------------------------------------------------
+ process(clk_a)
+ begin
+ if rising_edge(clk_a) then
+ if we_a = '1' then
+ ram(to_integer(unsigned(addr_a))) <= d_a;
+ end if;
+ q_a <= ram(to_integer(unsigned(addr_a)));
+ end if;
+ end process;
+
+ process(clk_b)
+ begin
+ if rising_edge(clk_b) then
+ if we_b = '1' then
+ ram(to_integer(unsigned(addr_b))) <= d_b;
+ end if;
+ q_b <= ram(to_integer(unsigned(addr_b)));
+ end if;
+ end process;
+
+end architecture;
+
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/gen_ram.vhd
new file mode 100644
index 00000000..f1a95608
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/gen_ram.vhd
@@ -0,0 +1,84 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr)
+-- http://darfpga.blogspot.fr
+-- Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- gen_rwram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity gen_ram is
+ generic (
+ dWidth : integer := 8;
+ aWidth : integer := 10
+ );
+ port (
+ clk : in std_logic;
+ we : in std_logic;
+ addr : in std_logic_vector((aWidth-1) downto 0);
+ d : in std_logic_vector((dWidth-1) downto 0);
+ q : out std_logic_vector((dWidth-1) downto 0)
+ );
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of gen_ram is
+ subtype addressRange is integer range 0 to ((2**aWidth)-1);
+ type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+ signal ram: ramDef;
+
+ signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
+ signal qReg : std_logic_vector((dWidth-1) downto 0);
+begin
+-- -----------------------------------------------------------------------
+-- Signals to entity interface
+-- -----------------------------------------------------------------------
+-- q <= qReg;
+
+-- -----------------------------------------------------------------------
+-- Memory write
+-- -----------------------------------------------------------------------
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ if we = '1' then
+ ram(to_integer(unsigned(addr))) <= d;
+ end if;
+ end if;
+ end process;
+
+-- -----------------------------------------------------------------------
+-- Memory read
+-- -----------------------------------------------------------------------
+process(clk)
+ begin
+ if rising_edge(clk) then
+-- qReg <= ram(to_integer(unsigned(rAddrReg)));
+-- rAddrReg <= addr;
+---- qReg <= ram(to_integer(unsigned(addr)));
+ q <= ram(to_integer(unsigned(addr)));
+ end if;
+ end process;
+--q <= ram(to_integer(unsigned(addr)));
+end architecture;
+
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/pll_mist.v b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/pll_mist.v
new file mode 100644
index 00000000..851e7663
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/pll_mist.v
@@ -0,0 +1,337 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll_mist.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll_mist (
+ inclk0,
+ c0,
+ c1,
+ locked);
+
+ input inclk0;
+ output c0;
+ output c1;
+ output locked;
+
+ wire [4:0] sub_wire0;
+ wire sub_wire2;
+ wire [0:0] sub_wire6 = 1'h0;
+ wire [0:0] sub_wire3 = sub_wire0[0:0];
+ wire [1:1] sub_wire1 = sub_wire0[1:1];
+ wire c1 = sub_wire1;
+ wire locked = sub_wire2;
+ wire c0 = sub_wire3;
+ wire sub_wire4 = inclk0;
+ wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+ altpll altpll_component (
+ .inclk (sub_wire5),
+ .clk (sub_wire0),
+ .locked (sub_wire2),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = 3,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 4,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 9,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 8,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 37037,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_mist",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "AUTO",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.self_reset_on_loss_lock = "OFF",
+ altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/rom/char_col.vhd b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/rom/char_col.vhd
new file mode 100644
index 00000000..e94c1f8c
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/rom/char_col.vhd
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity char_col is
+port (
+ clk : in std_logic;
+ addr : in std_logic_vector(7 downto 0);
+ data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of char_col is
+ type rom is array(0 to 255) of std_logic_vector(7 downto 0);
+ signal rom_data: rom := (
+ X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"00",X"04",X"00",X"03",X"03",X"02",X"01",
+ X"04",X"01",X"04",X"01",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"06",X"06",X"06",X"01",
+ X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"00",X"04",X"00",X"03",X"03",X"02",X"01",
+ X"04",X"01",X"04",X"01",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"06",X"06",X"06",X"01",
+ X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"00",X"04",X"00",X"03",X"03",X"02",X"01",
+ X"04",X"01",X"04",X"01",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"03",X"06",X"06",X"06",X"01",
+ X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"00",X"04",X"00",X"03",X"03",X"02",X"01",
+ X"04",X"01",X"04",X"01",X"04",X"01",X"01",X"01",X"02",X"02",X"02",X"02",X"05",X"05",X"06",X"01",
+ X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"00",X"04",X"00",X"03",X"03",X"02",X"01",
+ X"04",X"01",X"04",X"01",X"04",X"01",X"01",X"01",X"02",X"02",X"02",X"02",X"05",X"05",X"06",X"01",
+ X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"00",X"04",X"00",X"03",X"03",X"02",X"01",
+ X"04",X"01",X"04",X"01",X"04",X"01",X"01",X"01",X"02",X"02",X"02",X"02",X"05",X"05",X"06",X"01",
+ X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"00",X"04",X"00",X"03",X"03",X"02",X"01",
+ X"04",X"01",X"04",X"01",X"04",X"01",X"01",X"01",X"02",X"02",X"02",X"02",X"05",X"05",X"04",X"01",
+ X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"02",X"03",X"00",X"04",X"00",X"03",X"03",X"02",X"01",
+ X"04",X"01",X"04",X"01",X"04",X"01",X"01",X"01",X"02",X"02",X"02",X"02",X"05",X"05",X"04",X"01");
+begin
+process(clk)
+begin
+ if rising_edge(clk) then
+ data <= rom_data(to_integer(unsigned(addr)));
+ end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/rom/dec_315_5013.vhd b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/rom/dec_315_5013.vhd
new file mode 100644
index 00000000..1005daba
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/rom/dec_315_5013.vhd
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity dec_315_5013 is
+port (
+ clk : in std_logic;
+ addr : in std_logic_vector(6 downto 0);
+ data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of dec_315_5013 is
+ type rom is array(0 to 127) of std_logic_vector(7 downto 0);
+ signal rom_data: rom := (
+ X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0",X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00",
+ X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80",X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0",
+ X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00",X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0",
+ X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80",X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00",
+ X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00",X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0",
+ X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0",X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80",
+ X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80",X"A8",X"28",X"A0",X"20",X"20",X"A0",X"00",X"80",
+ X"08",X"28",X"88",X"A8",X"88",X"80",X"08",X"00",X"88",X"A8",X"80",X"A0",X"28",X"20",X"A8",X"A0");
+begin
+process(clk)
+begin
+ if rising_edge(clk) then
+ data <= rom_data(to_integer(unsigned(addr)));
+ end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/rom/palette.vhd b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/rom/palette.vhd
new file mode 100644
index 00000000..1480b764
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/rom/palette.vhd
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity palette is
+port (
+ clk : in std_logic;
+ addr : in std_logic_vector(7 downto 0);
+ data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of palette is
+ type rom is array(0 to 255) of std_logic_vector(7 downto 0);
+ signal rom_data: rom := (
+ X"00",X"00",X"F0",X"F0",X"36",X"26",X"00",X"FF",X"00",X"00",X"F0",X"F6",X"26",X"36",X"00",X"FF",
+ X"00",X"00",X"F0",X"36",X"00",X"06",X"00",X"FF",X"00",X"00",X"F0",X"06",X"06",X"00",X"00",X"00",
+ X"00",X"00",X"F0",X"38",X"06",X"06",X"00",X"00",X"00",X"00",X"36",X"C6",X"46",X"85",X"00",X"FF",
+ X"00",X"00",X"36",X"06",X"06",X"06",X"06",X"00",X"00",X"C0",X"DB",X"F6",X"F0",X"E0",X"80",X"06",
+ X"00",X"04",X"02",X"F0",X"06",X"06",X"04",X"02",X"00",X"00",X"9B",X"A3",X"A4",X"EC",X"A3",X"A4",
+ X"00",X"F0",X"E0",X"36",X"26",X"06",X"FF",X"00",X"00",X"18",X"85",X"B4",X"AC",X"14",X"84",X"E0",
+ X"00",X"24",X"1B",X"82",X"E0",X"36",X"12",X"80",X"00",X"00",X"F6",X"18",X"40",X"B4",X"AC",X"A4",
+ X"00",X"B4",X"AC",X"E0",X"18",X"40",X"A4",X"00",X"00",X"AC",X"B4",X"36",X"F6",X"A4",X"00",X"18",
+ X"00",X"C6",X"06",X"F0",X"36",X"26",X"04",X"34",X"00",X"F6",X"DB",X"E0",X"06",X"26",X"03",X"00",
+ X"00",X"00",X"20",X"06",X"26",X"34",X"32",X"30",X"00",X"F6",X"00",X"B4",X"AC",X"52",X"A5",X"06",
+ X"00",X"A4",X"00",X"05",X"04",X"16",X"26",X"F6",X"00",X"A3",X"36",X"34",X"30",X"A4",X"16",X"20",
+ X"00",X"26",X"85",X"F6",X"D2",X"C0",X"80",X"82",X"00",X"26",X"85",X"F6",X"30",X"28",X"20",X"18",
+ X"00",X"26",X"85",X"F6",X"07",X"06",X"05",X"04",X"00",X"A3",X"26",X"06",X"04",X"A4",X"16",X"5D",
+ X"00",X"F6",X"36",X"06",X"04",X"26",X"03",X"00",X"00",X"16",X"00",X"EE",X"E6",X"C6",X"5D",X"00",
+ X"00",X"07",X"06",X"04",X"C4",X"85",X"05",X"05",X"00",X"00",X"36",X"16",X"05",X"EE",X"E6",X"C6",
+ X"00",X"EE",X"E6",X"C4",X"16",X"05",X"C6",X"00",X"00",X"E6",X"EE",X"85",X"36",X"C6",X"00",X"16");
+begin
+process(clk)
+begin
+ if rising_edge(clk) then
+ data <= rom_data(to_integer(unsigned(addr)));
+ end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/sdram.sv b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..728abae6
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/sdram.sv
@@ -0,0 +1,337 @@
+//
+// sdram.v
+//
+// sdram controller implementation for the MiST board
+// https://github.com/mist-devel/mist-board
+//
+// Copyright (c) 2013 Till Harbaum
+// Copyright (c) 2019 Gyorgy Szombathelyi
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+
+module sdram (
+
+ // interface to the MT48LC16M16 chip
+ inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
+ output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
+ output reg SDRAM_DQML, // two byte masks
+ output reg SDRAM_DQMH, // two byte masks
+ output reg [1:0] SDRAM_BA, // two banks
+ output SDRAM_nCS, // a single chip select
+ output SDRAM_nWE, // write enable
+ output SDRAM_nRAS, // row address select
+ output SDRAM_nCAS, // columns address select
+
+ // cpu/chipset interface
+ input init_n, // init signal after FPGA config to initialize RAM
+ input clk, // sdram clock
+
+ input port1_req,
+ output reg port1_ack,
+ input port1_we,
+ input [23:1] port1_a,
+ input [1:0] port1_ds,
+ input [15:0] port1_d,
+ output [15:0] port1_q,
+
+ input [15:1] cpu1_addr,
+ output reg [15:0] cpu1_q,
+ input [19:1] snd_addr,
+ output reg [15:0] snd_q,
+
+ input port2_req,
+ output reg port2_ack,
+ input port2_we,
+ input [23:1] port2_a,
+ input [1:0] port2_ds,
+ input [15:0] port2_d,
+ output [15:0] port2_q,
+
+ input [15:1] gfx_addr,
+ output reg [15:0] gfx_q
+);
+
+parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
+
+localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
+localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
+localparam CAS_LATENCY = 3'd2; // 2/3 allowed
+localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
+
+localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
+
+// 64ms/8192 rows = 7.8us
+localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
+
+// ---------------------------------------------------------------------
+// ------------------------ cycle state machine ------------------------
+// ---------------------------------------------------------------------
+
+/*
+ SDRAM state machine for 2 bank interleaved access
+ 1 word burst, CL2
+cmd issued registered
+ 0 RAS0 cas1
+ 1 ras0
+ 2 CAS0 data1 returned
+ 3 RAS1 cas0
+ 4 ras1
+ 5 CAS1 data0 returned
+*/
+
+localparam STATE_RAS0 = 3'd0; // first state in cycle
+localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3
+localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
+localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7
+localparam STATE_READ1 = 3'd3;
+localparam STATE_LAST = 3'd5;
+
+reg [2:0] t;
+
+always @(posedge clk) begin
+ t <= t + 1'd1;
+ if (t == STATE_LAST) t <= STATE_RAS0;
+end
+
+// ---------------------------------------------------------------------
+// --------------------------- startup/reset ---------------------------
+// ---------------------------------------------------------------------
+
+// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
+// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
+reg [4:0] reset;
+reg init = 1'b1;
+always @(posedge clk, negedge init_n) begin
+ if(!init_n) begin
+ reset <= 5'h1f;
+ init <= 1'b1;
+ end else begin
+ if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
+ init <= !(reset == 0);
+ end
+end
+
+// ---------------------------------------------------------------------
+// ------------------ generate ram control signals ---------------------
+// ---------------------------------------------------------------------
+
+// all possible commands
+localparam CMD_INHIBIT = 4'b1111;
+localparam CMD_NOP = 4'b0111;
+localparam CMD_ACTIVE = 4'b0011;
+localparam CMD_READ = 4'b0101;
+localparam CMD_WRITE = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE = 4'b0010;
+localparam CMD_AUTO_REFRESH = 4'b0001;
+localparam CMD_LOAD_MODE = 4'b0000;
+
+reg [3:0] sd_cmd; // current command sent to sd ram
+reg [15:0] sd_din;
+// drive control signals according to current command
+assign SDRAM_nCS = sd_cmd[3];
+assign SDRAM_nRAS = sd_cmd[2];
+assign SDRAM_nCAS = sd_cmd[1];
+assign SDRAM_nWE = sd_cmd[0];
+
+reg [24:1] addr_latch[2];
+reg [24:1] addr_latch_next[2];
+reg [19:1] addr_last[2];
+reg [15:1] addr_last2[2];
+reg [15:0] din_latch[2];
+reg [1:0] oe_latch;
+reg [1:0] we_latch;
+reg [1:0] ds[2];
+
+reg port1_state;
+reg port2_state;
+
+localparam PORT_NONE = 2'd0;
+localparam PORT_CPU1 = 2'd1;
+localparam PORT_SND = 2'd2;
+localparam PORT_REQ = 2'd3;
+
+localparam PORT_GFX = 2'd1;
+
+reg [2:0] next_port[2];
+reg [2:0] port[2];
+
+reg refresh;
+reg [10:0] refresh_cnt;
+wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
+
+// PORT1: bank 0,1
+always @(*) begin
+ if (refresh) begin
+ next_port[0] = PORT_NONE;
+ addr_latch_next[0] = addr_latch[0];
+ end else if (port1_req ^ port1_state) begin
+ next_port[0] = PORT_REQ;
+ addr_latch_next[0] = { 1'b0, port1_a };
+ end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
+ next_port[0] = PORT_CPU1;
+ addr_latch_next[0] = { 9'd0, cpu1_addr };
+ end else if (snd_addr != addr_last[PORT_SND]) begin
+ next_port[0] = PORT_SND;
+ addr_latch_next[0] = { 5'd0, snd_addr };
+ end else begin
+ next_port[0] = PORT_NONE;
+ addr_latch_next[0] = addr_latch[0];
+ end
+end
+
+// PORT2: bank 2,3
+always @(*) begin
+ if (port2_req ^ port2_state) begin
+ next_port[1] = PORT_REQ;
+ addr_latch_next[1] = { 1'b1, port2_a };
+ end else if (gfx_addr != addr_last2[PORT_GFX]) begin
+ next_port[1] = PORT_GFX;
+ addr_latch_next[1] = { 1'b1, 8'd0, gfx_addr };
+ end else begin
+ next_port[1] = PORT_NONE;
+ addr_latch_next[1] = addr_latch[1];
+ end
+end
+
+always @(posedge clk) begin
+
+ // permanently latch ram data to reduce delays
+ sd_din <= SDRAM_DQ;
+ SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+ { SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
+ sd_cmd <= CMD_NOP; // default: idle
+ refresh_cnt <= refresh_cnt + 1'd1;
+
+ if(init) begin
+ // initialization takes place at the end of the reset phase
+ if(t == STATE_RAS0) begin
+
+ if(reset == 15) begin
+ sd_cmd <= CMD_PRECHARGE;
+ SDRAM_A[10] <= 1'b1; // precharge all banks
+ end
+
+ if(reset == 10 || reset == 8) begin
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+
+ if(reset == 2) begin
+ sd_cmd <= CMD_LOAD_MODE;
+ SDRAM_A <= MODE;
+ SDRAM_BA <= 2'b00;
+ end
+ end
+ end else begin
+ // RAS phase
+ // bank 0,1
+ if(t == STATE_RAS0) begin
+ addr_latch[0] <= addr_latch_next[0];
+ port[0] <= next_port[0];
+ { oe_latch[0], we_latch[0] } <= 2'b00;
+
+ if (next_port[0] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[0][22:10];
+ SDRAM_BA <= addr_latch_next[0][24:23];
+ addr_last[next_port[0]] <= addr_latch_next[0][19:1];
+ if (next_port[0] == PORT_REQ) begin
+ { oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
+ ds[0] <= port1_ds;
+ din_latch[0] <= port1_d;
+ port1_state <= port1_req;
+ end else begin
+ { oe_latch[0], we_latch[0] } <= 2'b10;
+ ds[0] <= 2'b11;
+ end
+ end
+ end
+
+ // bank 2,3
+ if(t == STATE_RAS1) begin
+ refresh <= 1'b0;
+ addr_latch[1] <= addr_latch_next[1];
+ { oe_latch[1], we_latch[1] } <= 2'b00;
+ port[1] <= next_port[1];
+
+ if (next_port[1] != PORT_NONE) begin
+ sd_cmd <= CMD_ACTIVE;
+ SDRAM_A <= addr_latch_next[1][22:10];
+ SDRAM_BA <= addr_latch_next[1][24:23];
+ addr_last2[next_port[1]] <= addr_latch_next[1][15:1];
+ if (next_port[1] == PORT_REQ) begin
+ { oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
+ ds[1] <= port2_ds;
+ din_latch[1] <= port2_d;
+ port2_state <= port2_req;
+ end else begin
+ { oe_latch[1], we_latch[1] } <= 2'b10;
+ ds[1] <= 2'b11;
+ end
+ end
+
+ if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
+ refresh <= 1'b1;
+ refresh_cnt <= 0;
+ sd_cmd <= CMD_AUTO_REFRESH;
+ end
+ end
+
+ // CAS phase
+ if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
+ sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
+ if (we_latch[0]) begin
+ SDRAM_DQ <= din_latch[0];
+ port1_ack <= port1_req;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[0][24:23];
+ end
+
+ if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
+ sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
+ { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+ if (we_latch[1]) begin
+ SDRAM_DQ <= din_latch[1];
+ port2_ack <= port2_req;
+ end
+ SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
+ SDRAM_BA <= addr_latch[1][24:23];
+ end
+
+ // Data returned
+ if(t == STATE_READ0 && oe_latch[0]) begin
+ case(port[0])
+ PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
+ PORT_CPU1: begin cpu1_q <= sd_din; end
+ PORT_SND: begin snd_q <= sd_din; end
+ default: ;
+ endcase;
+ end
+ if(t == STATE_READ1 && oe_latch[1]) begin
+ case(port[1])
+ PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end
+ PORT_GFX: begin gfx_q <= sd_din; end
+ default: ;
+ endcase;
+ end
+ end
+end
+
+endmodule
diff --git a/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/zaxxon_sound.vhd b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/zaxxon_sound.vhd
new file mode 100644
index 00000000..b812e008
--- /dev/null
+++ b/Arcade_MiST/Sega Zaxxon Hardware/SuperZaxxon_MiST/rtl/zaxxon_sound.vhd
@@ -0,0 +1,237 @@
+----------------
+-- Wave player --
+-----------------
+
+-- Zaxxon sample wav files info header - start/stop addresses as loaded in SDRAM
+
+--00.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg: 29970 start: 44 (x0002C) stop: 30014 (x0753E)
+--01.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg: 17798 start: 30058 (x0756A) stop: 47856 (x0BAF0)
+--02.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg: 63596 start: 47900 (x0BB1C) stop:111496 (x1B388)
+--03.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg: 40420 start:111540 (x1B3B4) stop:151960 (x25198)
+--04.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg: 66294 start:152004 (x251C4) stop:218298 (x354BA)
+--05.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg: 56038 start:218342 (x354E6) stop:274380 (x42FCC)
+--08.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg:104692 start:274424 (x42FF8) stop:379116 (x5C8EC)
+--10.wav e:RIFF n:1 sr:22050 br:44100 al:2 bps:16 lg:168970 start:379160 (x5C918) stop:548130 (x85D22)
+--11.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg:154144 start:548174 (x85D4E) stop:702318 (xAB76E)
+--20.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg: 4128 start:702362 (xAB79A) stop:706490 (xAC7BA)
+--21.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg: 6854 start:706534 (xAC7E6) stop:713388 (xAE2AC)
+--23.wav e:RIFF n:1 sr:44100 br:88200 al:2 bps:16 lg: 86978 start:713432 (xAE2D8) stop:800410 (xC369A)
+
+-- 8255 PIA port A B C
+
+-- PA1/PA0 PLAYER SHIP A/B - Volume 04/05.wav
+--
+--#0 - PA7 loop BATTLESHIP 00.wav - boss
+--#1 - PA6 loop LASER 01.wav - electric field
+--#2 - PA5 retrig BASE MISSILE 02.wav - missile engine
+--#3 - PA4 loop HOMING MISSILE 03.wav - homing missile
+--#4 - PA3 loop PLAYER SHIP D 04.wav - shuttle engine
+--#5 - PA2 loop PLAYER SHIP C 05.wav - within space
+--#6 - PB7 retrig CANNON 08.wav - player shot
+--#7 - PB5 no retrig M-EXP 10.wav - final explode
+--#8 - PB4 retrig S-EXP 11.wav - explode
+--#9 - PC3 no retrig ALARM3 20.wav - low fuel
+--#10 - PC2 retrig ALARM2 21.wav - enemy locked
+--#11 - PC0 retrig SHOT 23.wav - coin / tourelle shot
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity zaxxon_sound is
+port(
+ clock_24 : in std_logic;
+ reset : in std_logic;
+
+ port_a : in std_logic_vector(7 downto 0);
+ port_a_r : in std_logic_vector(7 downto 0); -- i8255 ports
+ port_b : in std_logic_vector(7 downto 0);
+ port_b_r : in std_logic_vector(7 downto 0);
+ port_c : in std_logic_vector(7 downto 0);
+ port_c_r : in std_logic_vector(7 downto 0);
+
+ audio_out_l : out std_logic_vector(15 downto 0);
+ audio_out_r : out std_logic_vector(15 downto 0);
+
+ wave_addr : buffer std_logic_vector(19 downto 0);
+ wave_rd : out std_logic;
+ wave_data : in std_logic_vector(15 downto 0)
+ );
+end zaxxon_sound;
+
+architecture struct of zaxxon_sound is
+
+ signal wav_clk_cnt : std_logic_vector(11 downto 0); -- 44kHz divider / sound# counter
+
+ subtype snd_id_t is integer range 0 to 11;
+ signal snd_id : snd_id_t;
+
+ type snd_addr_t is array(snd_id_t) of std_logic_vector(19 downto 0);
+
+ -- wave current addresses in sdram
+ signal snd_addrs : snd_addr_t;
+
+ -- wave start addresses in sdram
+ signal snd_starts : snd_addr_t := (
+ x"0002C",x"0756A",x"0BB1C",x"1B3B4",x"251C4",x"354E6",
+ x"42FF8",x"5C918",x"85D4E",x"AB79A",x"AC7E6",x"AE2D8");
+
+ -- wave end addresses in sdram
+ signal snd_stops : snd_addr_t := (
+ x"0753E",x"0BAF0",x"1B388",x"25198",x"354BA",x"42FCC",
+ x"5C8EC",x"85D22",x"AB76E",x"AC7BA",x"AE2AC",x"C369A");
+
+ type snd_flag_t is array(snd_id_t) of std_logic;
+
+ -- sound playing (once)
+ signal snd_starteds : snd_flag_t := (
+ '0','0','0','0','0','0','0','0','0','0','0','0');
+ -- sound to be restarted
+ signal snd_restarts : snd_flag_t := (
+ '0','0','0','0','0','0','0','0','0','0','0','0');
+ -- sound playing (loop)
+ signal snd_continus : snd_flag_t := (
+ '0','0','0','0','0','0','0','0','0','0','0','0');
+ -- sound sample rate 44/22kHz
+ signal snd_44k : snd_flag_t := (
+ '1','1','1','1','1','1','1','0','1','1','1','1');
+
+ -- divide 44kHz flag
+ signal snd_22k_flag : std_logic := '0';
+
+ -- sum all sound
+ signal audio_r, audio_sum : signed(19 downto 0);
+ signal ship_vol, volume : signed( 7 downto 0);
+ signal audio_vol : signed(23 downto 0);
+
+
+begin
+
+-- scan sound# from 0-11
+snd_id <= to_integer(unsigned(wav_clk_cnt(8 downto 5)));
+
+-- apply volume to sdram (wav file) data w.r.t port_a and snd_id
+with port_a(1 downto 0) select
+ship_vol <= x"10" when "00",
+ x"20" when "01",
+ x"30" when "10",
+ x"40" when others;
+
+with snd_id select
+volume <= ship_vol when 4,
+ ship_vol when 5,
+ x"7F" when others;
+
+audio_vol <= (signed(wave_data) * volume) / 128;
+
+-- wave player
+process (clock_24, reset)
+begin
+ if reset='1' then
+ wav_clk_cnt <= (others=>'0');
+ else
+ if rising_edge(clock_24) then
+
+ -- sound triggers
+ snd_continus( 0) <= not port_a(7); -- boss
+ snd_continus( 1) <= not port_a(6); -- electric field
+
+ snd_starteds( 2) <= snd_starteds( 2) or (not(port_a(5)) and port_a_r(5)); -- missile engine
+ snd_restarts( 2) <= snd_restarts( 2) or (not(port_a(5)) and port_a_r(5));
+
+ snd_continus( 3) <= not port_a(4); -- homing missile
+ snd_continus( 4) <= not port_a(3); -- shuttle engine
+ snd_continus( 5) <= not port_a(2); -- within space
+
+ snd_starteds( 6) <= snd_starteds( 6) or (not(port_b(7)) and port_b_r(7)); -- player shot
+ snd_restarts( 6) <= snd_restarts( 6) or (not(port_b(7)) and port_b_r(7));
+
+ snd_starteds( 7) <= snd_starteds( 7) or (not(port_b(5)) and port_b_r(5)); -- final explode
+
+ snd_starteds( 8) <= snd_starteds( 8) or (not(port_b(4)) and port_b_r(4)); -- explode
+ snd_restarts( 8) <= snd_restarts( 8) or (not(port_b(4)) and port_b_r(4));
+
+ snd_starteds( 9) <= snd_starteds( 9) or (not(port_c(3)) and port_c_r(3)); -- low fuel
+
+ snd_starteds(10) <= snd_starteds(10) or (not(port_c(2)) and port_c_r(2)); -- enemy locked
+ snd_restarts(10) <= snd_restarts(10) or (not(port_c(2)) and port_c_r(2));
+
+ snd_starteds(11) <= snd_starteds(11) or (not(port_c(0)) and port_c_r(0)); -- coin / tourelle shot
+ snd_restarts(11) <= snd_restarts(11) or (not(port_c(0)) and port_c_r(0));
+
+ -- 44.1kHz base tempo / high bits for scanning sound#
+ if wav_clk_cnt = x"21F" then -- divide 24MHz by 544 => 44.117kHz
+ wav_clk_cnt <= (others=>'0');
+ snd_22k_flag <= not snd_22k_flag; -- divide by 2 => 22.05kHz
+
+ -- latch final audio / reset sum
+ audio_r <= audio_sum;
+ audio_sum <= (others => '0');
+ else
+ wav_clk_cnt <= wav_clk_cnt + 1;
+ end if;
+
+ -- clip audio
+ if audio_r(19 downto 2) > 32767 then
+ audio_out_l <= x"7FFF";
+ elsif audio_r(19 downto 2) < -32768 then
+ audio_out_l <= x"8000";
+ else
+ audio_out_l <= std_logic_vector(audio_r(17 downto 2));
+ end if;
+
+ -- sdram read trigger (and auto refresh period)
+ if wav_clk_cnt(4 downto 0) = "00000" then wave_rd <= '1';end if;
+ if wav_clk_cnt(4 downto 0) = "00010" then wave_rd <= '0';end if;
+
+ -- select only useful cycles (0-11)
+ -- remaing cycles unsued
+ if wav_clk_cnt(11 downto 5) <= 11 then
+
+ -- set sdram addr at begining of cycle
+ if wav_clk_cnt(4 downto 0) = "00000" then
+ wave_addr <= snd_addrs(snd_id);
+ end if;
+
+ -- sound# currently playing
+ if (snd_starteds(snd_id) = '1' or snd_continus(snd_id) = '1' ) then
+
+ -- get sound# sample and update next sound# address
+ -- (next / restart)
+ if wav_clk_cnt(4 downto 0) = "10000" then
+
+ audio_sum <= audio_sum + audio_vol(15 downto 0);
+
+ if snd_restarts(snd_id) = '1' then
+ snd_addrs(snd_id) <= snd_starts(snd_id);
+ snd_restarts(snd_id) <= '0';
+ else
+ if (snd_44k(snd_id) = '1' or snd_22k_flag = '1') then
+ snd_addrs(snd_id) <= snd_addrs(snd_id) + 2;
+ end if;
+ end if;
+ end if;
+
+ -- update next sound# address
+ -- (stop / loop)
+ if snd_addrs(snd_id) >= snd_stops(snd_id) then
+ if snd_continus(snd_id) = '1' then
+ snd_addrs(snd_id) <= snd_starts(snd_id);
+ else
+ snd_starteds(snd_id) <= '0';
+ end if;
+ end if;
+
+ else
+ -- sound# stopped set begin address
+ snd_addrs(snd_id) <= snd_starts(snd_id);
+ end if;
+
+ end if;
+
+ end if;
+ end if;
+end process;
+
+end struct;
\ No newline at end of file