From 36e390aa9a5c5707a32687868fd892af2a0232b5 Mon Sep 17 00:00:00 2001
From: Gehstock <marceljenke@gmail.com>
Date: Sun, 8 Mar 2020 22:45:59 +0100
Subject: [PATCH] add SonSon Project Files

---
 .../DigDug_MiST/DigDug_MiST.srf               |   14 -
 .../Kung_MiST/LodeRunner_MiST.qpf             |   30 +
 .../Kung_MiST/LodeRunner_MiST.qsf             |  275 +
 .../IremM62 Hardware/Kung_MiST/clean.bat      |   15 +
 .../Kung_MiST/rtl/Graphics.VHD                |  272 +
 .../IremM62 Hardware/Kung_MiST/rtl/Inputs.VHD |   51 +
 .../Kung_MiST/rtl/LodeRunner_MiST.sv          |  285 +
 .../Kung_MiST/rtl/Sound_Board.vhd             |  423 ++
 .../IremM62 Hardware/Kung_MiST/rtl/YM2149.sv  |  329 +
 .../Kung_MiST/rtl/bitmapctl_e.vhd             |   30 +
 .../Kung_MiST/rtl/build_id.tcl                |   35 +
 .../Kung_MiST/rtl/clk_div.vhd                 |   39 +
 .../IremM62 Hardware/Kung_MiST/rtl/cpu68.vhd  | 3963 ++++++++++++
 .../IremM62 Hardware/Kung_MiST/rtl/dpram.vhd  |  131 +
 .../Kung_MiST/rtl/dprom_2r.vhd                |  135 +
 .../Kung_MiST/rtl/input_mapper.vhd            |   99 +
 .../IremM62 Hardware/Kung_MiST/rtl/pace.vhd   |  146 +
 .../Kung_MiST/rtl/pace_pkg.vhd                |  280 +
 .../Kung_MiST/rtl/pace_pkg_body.vhd           |   50 +
 .../Kung_MiST/rtl/platform.vhd                |  477 ++
 .../Kung_MiST/rtl/platform_pkg.vhd            |   55 +
 .../Kung_MiST/rtl/platform_variant_pkg.vhd    |  524 ++
 .../Kung_MiST/rtl/pll_mist.qip                |    4 +
 .../Kung_MiST/rtl/pll_mist.vhd                |  461 ++
 .../Kung_MiST/rtl/roms/Roms.txt               |   37 +
 .../Kung_MiST/rtl/roms/a-3e-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/a-3f-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/a-3h-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/a-4d-c.bin.hex         | 1025 +++
 .../Kung_MiST/rtl/roms/a-4e-c.bin.hex         | 1025 +++
 .../Kung_MiST/rtl/roms/b-3m-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-3n-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4a-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4c-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4d-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4e-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4f-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4h-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4k-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4l-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4m-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/b-4n-.bin.hex          |  513 ++
 .../Kung_MiST/rtl/roms/battroad.zip           |  Bin 0 -> 68780 bytes
 .../Kung_MiST/rtl/roms/g-4c-a.hex             |  258 +
 .../Kung_MiST/rtl/roms/g-4d-a.hex             |  258 +
 .../Kung_MiST/rtl/roms/g-4e-a.hex             |  258 +
 .../Kung_MiST/rtl/roms/kungfum.zip            |  Bin 0 -> 92575 bytes
 .../Kung_MiST/rtl/roms/kungfum/a-3e-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/a-3f-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/a-3h-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/a-4d-c.bin     |  Bin 0 -> 16384 bytes
 .../Kung_MiST/rtl/roms/kungfum/a-4e-c.bin     |  Bin 0 -> 16384 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-1l-.bin      |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-1m-.bin      |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-1n-.bin      |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-3m-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-3n-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4a-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4c-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4d-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4e-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4f-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4h-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4k-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4l-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4m-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-4n-.bin      |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-5f-.bin      |  Bin 0 -> 32 bytes
 .../Kung_MiST/rtl/roms/kungfum/b-6f-.bin      |    1 +
 .../Kung_MiST/rtl/roms/kungfum/g-1f-.bin      |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/kungfum/g-1h-.bin      |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/kungfum/g-1j-.bin      |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/kungfum/g-4c-a.bin     |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/g-4d-a.bin     |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/g-4e-a.bin     |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/kungfum/make_proms.bat |   15 +
 .../rtl/roms/kungfum/make_vhdl_prom.exe       |  Bin 0 -> 119861 bytes
 .../Kung_MiST/rtl/roms/kungfum/prog.bin       |  Bin 0 -> 32768 bytes
 .../Kung_MiST/rtl/roms/kungfum/prog.vhd       | 2070 ++++++
 .../Kung_MiST/rtl/roms/kungfum/snd.bin        |  Bin 0 -> 24576 bytes
 .../Kung_MiST/rtl/roms/kungfum/snd_prg.vhd    | 1558 +++++
 .../Kung_MiST/rtl/roms/kungfum/spr1.bin       |  Bin 0 -> 32768 bytes
 .../Kung_MiST/rtl/roms/kungfum/spr2.bin       |  Bin 0 -> 32768 bytes
 .../Kung_MiST/rtl/roms/kungfum/spr3.bin       |  Bin 0 -> 32768 bytes
 .../Kung_MiST/rtl/roms/ldrun.zip              |  Bin 0 -> 47197 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-a-3f          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-a-3h          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-a-4a          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-a-4b          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-a-4d          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-a-4e          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-b-1l          |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-b-1m          |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-b-1n          |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-b-3n          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-b-4c          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-b-4k          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-b-5p          |  Bin 0 -> 32 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-b-6f          |    1 +
 .../Kung_MiST/rtl/roms/ldrun/lr-e-2d          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-e-2f          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-e-2j          |  Bin 0 -> 8192 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-e-3l          |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-e-3m          |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/ldrun/lr-e-3n          |  Bin 0 -> 256 bytes
 .../Kung_MiST/rtl/roms/ldrun/make_proms.bat   |   11 +
 .../rtl/roms/ldrun/make_vhdl_prom.exe         |  Bin 0 -> 119861 bytes
 .../Kung_MiST/rtl/roms/ldrun/prog.bin         |  Bin 0 -> 32768 bytes
 .../Kung_MiST/rtl/roms/ldrun/prog.vhd         | 2070 ++++++
 .../rtl/roms/ldrun/rom_sprite_high.vhd        |   24 +
 .../rtl/roms/ldrun/rom_sprite_high_new.vhd    |   24 +
 .../Kung_MiST/rtl/roms/ldrun/snd.bin          |  Bin 0 -> 16384 bytes
 .../Kung_MiST/rtl/roms/ldrun/snd_prg.vhd      | 1046 +++
 .../Kung_MiST/rtl/roms/lotlot.zip             |  Bin 0 -> 38811 bytes
 .../Kung_MiST/rtl/roms/nu/lr-a-4a.hex         |  513 ++
 .../Kung_MiST/rtl/roms/nu/lr-a-4b.hex         |  513 ++
 .../Kung_MiST/rtl/roms/nu/lr-a-4d.hex         |  513 ++
 .../Kung_MiST/rtl/roms/nu/lr-a-4e.hex         |  513 ++
 .../Kung_MiST/rtl/roms/nu/lr-b-3n.hex         |  513 ++
 .../Kung_MiST/rtl/roms/nu/lr-b-4c.hex         |  513 ++
 .../Kung_MiST/rtl/roms/nu/lr-b-4k.hex         |  513 ++
 .../Kung_MiST/rtl/roms/nu/lr-e-2d.hex         |  513 ++
 .../Kung_MiST/rtl/roms/nu/lr-e-2f.hex         |  513 ++
 .../Kung_MiST/rtl/roms/nu/lr-e-2j.hex         |  513 ++
 .../IremM62 Hardware/Kung_MiST/rtl/sdram.sv   |  348 +
 .../IremM62 Hardware/Kung_MiST/rtl/spram.vhd  |   91 +
 .../Kung_MiST/rtl/sprite_array.vhd            |  164 +
 .../Kung_MiST/rtl/sprite_pkg.vhd              |   97 +
 .../Kung_MiST/rtl/sprite_pkg_body.vhd         |   62 +
 .../Kung_MiST/rtl/spritectl.vhd               |  202 +
 .../Kung_MiST/rtl/spritereg.vhd               |   68 +
 .../IremM62 Hardware/Kung_MiST/rtl/sprom.vhd  |   83 +
 .../Kung_MiST/rtl/target_top.vhd              |  145 +
 .../Kung_MiST/rtl/tilemapctl.vhd              |  106 +
 .../Kung_MiST/rtl/tilemapctl_e.vhd            |   29 +
 .../Kung_MiST/rtl/video_controller.vhd        |  465 ++
 .../Kung_MiST/rtl/video_controller_pkg.vhd    |  230 +
 .../rtl/video_controller_pkg_body.vhd         |   29 +
 .../Kung_MiST/rtl/video_mixer.vhd             |   66 +
 .../LodeRunner_MiST/LodeRunner_MiST.qsf       |    4 +-
 .../LodeRunner_MiST/rtl/Graphics.VHD          |    1 -
 .../LodeRunner_MiST/rtl/LodeRunner_MiST.sv    |   94 +-
 .../LodeRunner_MiST/rtl/Sound_Board.vhd       |   11 +-
 .../LodeRunner_MiST/rtl/platform_pkg.vhd      |   77 +-
 .../LodeRunner_MiST/rtl/pll_mist.vhd          |   58 +-
 .../LodeRunner_MiST/rtl/target_top.vhd        |   66 +-
 .../LodeRunner_MiST/rtl/video_controller.vhd  |   10 +
 .../rtl/video_controller_pkg.vhd              |    3 +-
 .../Sonson_MiST/Sonson_MiST.qpf               |   30 +
 .../Sonson_MiST/Sonson_MiST.qsf               |  269 +
 .../SonSon Hardware/Sonson_MiST/clean.bat     |   15 +
 .../Sonson_MiST/rtl/Graphics.VHD              |  270 +
 .../Sonson_MiST/rtl/SonSon_MiST.sv            |  281 +
 .../SonSon Hardware/Sonson_MiST/rtl/YM2149.sv |  329 +
 .../Sonson_MiST/rtl/bitmapctl_e.vhd           |   29 +
 .../Sonson_MiST/rtl/build_id.tcl              |   35 +
 .../Sonson_MiST/rtl/cpu09s.vhd                | 5679 +++++++++++++++++
 .../SonSon Hardware/Sonson_MiST/rtl/dpram.vhd |  131 +
 .../Sonson_MiST/rtl/dprom_2r.vhd              |  135 +
 .../Sonson_MiST/rtl/mc6809-master/README.md   |  109 +
 .../Sonson_MiST/rtl/mc6809-master/mc6809.v    |   80 +
 .../Sonson_MiST/rtl/mc6809-master/mc6809e.v   |   48 +
 .../Sonson_MiST/rtl/mc6809-master/mc6809i.v   | 4156 ++++++++++++
 .../Sonson_MiST/rtl/mc6809-master/mc6809s.v   |   82 +
 .../SonSon Hardware/Sonson_MiST/rtl/pace.vhd  |  160 +
 .../Sonson_MiST/rtl/pace_pkg.vhd              |  147 +
 .../Sonson_MiST/rtl/pace_pkg_body.vhd         |   17 +
 .../Sonson_MiST/rtl/platform.vhd              |  567 ++
 .../Sonson_MiST/rtl/platform_pkg.vhd          |  212 +
 .../Sonson_MiST/rtl/pll_mist.qip              |    4 +
 .../Sonson_MiST/rtl/pll_mist.vhd              |  429 ++
 .../Sonson_MiST/rtl/roms/cram.hex             |   65 +
 .../Sonson_MiST/rtl/roms/sonson.zip           |  Bin 0 -> 64728 bytes
 .../Sonson_MiST/rtl/roms/sonson/make.bat      |    7 +
 .../Sonson_MiST/rtl/roms/sonson/ss.01e        |  Bin 0 -> 16384 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss.02e        |  Bin 0 -> 16384 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss.03e        |  Bin 0 -> 16384 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss_10.m6      |  Bin 0 -> 8192 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss_11.m3      |  Bin 0 -> 8192 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss_12.m4      |  Bin 0 -> 8192 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss_13.m1      |  Bin 0 -> 8192 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss_14.m2      |  Bin 0 -> 8192 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss_6.c11      |  Bin 0 -> 8192 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss_7.b6       |  Bin 0 -> 8192 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss_8.b5       |  Bin 0 -> 8192 bytes
 .../Sonson_MiST/rtl/roms/sonson/ss_9.m5       |  Bin 0 -> 8192 bytes
 .../Sonson_MiST/rtl/roms/sonson/ssb1.k11      |  Bin 0 -> 256 bytes
 .../Sonson_MiST/rtl/roms/sonson/ssb2.c4       |  Bin 0 -> 256 bytes
 .../Sonson_MiST/rtl/roms/sonson/ssb3.h7       |  Bin 0 -> 256 bytes
 .../Sonson_MiST/rtl/roms/sonson/ssb4.b2       |  Bin 0 -> 32 bytes
 .../Sonson_MiST/rtl/roms/sonson/ssb5.b1       |  Bin 0 -> 32 bytes
 .../Sonson_MiST/rtl/roms/ss_01e.hex           | 1025 +++
 .../Sonson_MiST/rtl/roms/ss_02e.hex           | 1025 +++
 .../Sonson_MiST/rtl/roms/ss_03e.hex           | 1025 +++
 .../Sonson_MiST/rtl/roms/ss_10_m6.hex         |  513 ++
 .../Sonson_MiST/rtl/roms/ss_11_m3.hex         |  513 ++
 .../Sonson_MiST/rtl/roms/ss_12_m4.hex         |  513 ++
 .../Sonson_MiST/rtl/roms/ss_13_m1.hex         |  513 ++
 .../Sonson_MiST/rtl/roms/ss_14_m2.hex         |  513 ++
 .../Sonson_MiST/rtl/roms/ss_7_b6.hex          |  513 ++
 .../Sonson_MiST/rtl/roms/ss_8_b5.hex          |  513 ++
 .../Sonson_MiST/rtl/roms/ss_9_m5.hex          |  513 ++
 .../Sonson_MiST/rtl/roms/vram.hex             |   65 +
 .../SonSon Hardware/Sonson_MiST/rtl/sdram.sv  |  348 +
 .../SonSon Hardware/Sonson_MiST/rtl/sound.vhd |   46 +
 .../SonSon Hardware/Sonson_MiST/rtl/spram.vhd |   91 +
 .../Sonson_MiST/rtl/sprite_array.vhd          |  164 +
 .../Sonson_MiST/rtl/sprite_pkg.vhd            |   97 +
 .../Sonson_MiST/rtl/sprite_pkg_body.vhd       |   62 +
 .../Sonson_MiST/rtl/spritectl.vhd             |  160 +
 .../Sonson_MiST/rtl/spritereg.vhd             |   62 +
 .../SonSon Hardware/Sonson_MiST/rtl/sprom.vhd |   83 +
 .../Sonson_MiST/rtl/target_top.vhd            |  107 +
 .../Sonson_MiST/rtl/tilemapctl.vhd            |  111 +
 .../Sonson_MiST/rtl/tilemapctl_e.vhd          |   28 +
 .../Sonson_MiST/rtl/video_controller.vhd      |  455 ++
 .../Sonson_MiST/rtl/video_controller_pkg.vhd  |  229 +
 .../rtl/video_controller_pkg_body.vhd         |   29 +
 .../Sonson_MiST/rtl/video_mixer.vhd           |   66 +
 219 files changed, 55624 insertions(+), 182 deletions(-)
 delete mode 100644 Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.srf
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qpf
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qsf
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/clean.bat
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Graphics.VHD
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Inputs.VHD
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/LodeRunner_MiST.sv
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Sound_Board.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/YM2149.sv
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/bitmapctl_e.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/clk_div.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/cpu68.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/dpram.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/dprom_2r.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/input_mapper.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace_pkg.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace_pkg_body.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform_pkg.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform_variant_pkg.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.qip
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.vhd
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/Roms.txt
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3e-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3f-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3h-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-4d-c.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-4e-c.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-3m-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-3n-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4a-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4c-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4d-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4e-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4f-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4h-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4k-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4l-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4m-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4n-.bin.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/battroad.zip
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4c-a.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4d-a.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4e-a.hex
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum.zip
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/a-3e-.bin
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/a-3f-.bin
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/a-3h-.bin
 create mode 100644 Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/a-4d-c.bin
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diff --git a/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.srf b/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.srf
deleted file mode 100644
index 9dc57685..00000000
--- a/Arcade_MiST/Galaga Hardware/DigDug_MiST/DigDug_MiST.srf	
+++ /dev/null
@@ -1,14 +0,0 @@
-{ "" "" "" "Verilog HDL Declaration warning at tv80s.v(55): \"do\" is SystemVerilog-2005 keyword" {  } {  } 0 10463 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Unrecognized synthesis attribute \"dc_script_begin\" at rtl/TV80/tv80_reg.v(67)" {  } {  } 0 10335 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"R\" at tv80_core.v(97) has no driver or initial value, using a default initial value '0'" {  } {  } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL warning at tv80_core.v(97): object R used but never assigned" {  } {  } 0 10858 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Output port \"rfsh_n\" at tv80_core.v(59) has no driver" {  } {  } 0 10034 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10335 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10463 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10270 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 14284 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qpf b/Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qpf
new file mode 100644
index 00000000..dbbbab92
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
+# Date created = 23:49:02  July 13, 2012
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "10.1"
+DATE = "23:49:02  July 13, 2012"
+
+# Revisions
+
+PROJECT_REVISION = "LodeRunner_MiST"
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qsf b/Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qsf
new file mode 100644
index 00000000..7e0b14c7
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/LodeRunner_MiST.qsf	
@@ -0,0 +1,275 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:06:00  February 29, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		LodeRunner_MiST_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/LodeRunner_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/target_top.vhd
+set_global_assignment -name VHDL_FILE rtl/platform_variant_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/platform.vhd
+set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd
+set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/pace.vhd
+set_global_assignment -name VHDL_FILE rtl/Graphics.VHD
+set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd
+set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd
+set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/video_controller.vhd
+set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
+set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
+set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
+set_global_assignment -name VHDL_FILE rtl/spritereg.vhd
+set_global_assignment -name VHDL_FILE rtl/spritectl.vhd
+set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd
+set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd
+set_global_assignment -name VHDL_FILE rtl/Inputs.VHD
+set_global_assignment -name VHDL_FILE rtl/input_mapper.vhd
+set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/clk_div.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
+set_global_assignment -name VHDL_FILE rtl/Sound_Board.vhd
+set_global_assignment -name VHDL_FILE rtl/roms/ldrun/snd_prg.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name VHDL_FILE ../../../common/CPU/T80/Z80.vhd
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY LodeRunner_MiST
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SEARCH_PATH common/CPU/T80/ -tag from_archive
+set_global_assignment -name SEARCH_PATH common/mist/ -tag from_archive
+set_global_assignment -name SEARCH_PATH rtl/ -tag from_archive
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/mcr3.stp
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# -----------------------------
+# start ENTITY(LodeRunner_MiST)
+
+	# Pin & Location Assignments
+	# ==========================
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+	set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+
+	# Fitter Assignments
+	# ==================
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+	set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(LodeRunner_MiST)
+# ---------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/clean.bat b/Arcade_MiST/IremM62 Hardware/Kung_MiST/clean.bat
new file mode 100644
index 00000000..c9a2cb06
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Graphics.VHD b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Graphics.VHD
new file mode 100644
index 00000000..dc3fb666
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Graphics.VHD	
@@ -0,0 +1,272 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+--use work.project_pkg.all;
+use work.platform_pkg.all;
+
+entity Graphics is
+  port
+  (
+    bitmap_ctl_i    : in to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    bitmap_ctl_o    : out from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    tilemap_ctl_i   : in to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+    tilemap_ctl_o   : out from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+
+    sprite_reg_i    : in to_SPRITE_REG_t;
+    sprite_ctl_i    : in to_SPRITE_CTL_t;
+    sprite_ctl_o    : out from_SPRITE_CTL_t;
+		spr0_hit				: out std_logic;
+    
+    graphics_i      : in to_GRAPHICS_t;
+    graphics_o      : out from_GRAPHICS_t;
+
+		video_i					: in from_VIDEO_t;
+		video_o					: out to_VIDEO_t
+  );
+
+end Graphics;
+
+architecture SYN of Graphics is
+
+	alias clk 					    : std_logic is video_i.clk;
+
+  signal from_video_ctl   : from_VIDEO_CTL_t;
+  signal bitmap_ctl_o_s   : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+  signal tilemap_ctl_o_s  : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+  signal sprite_ctl_o_s   : from_SPRITE_CTL_t;
+  signal sprite_pri       : std_logic;
+
+
+	signal rgb_data			    : RGB_t;
+  -- before OSD is mixed in
+  signal video_o_s        : to_VIDEO_t;
+  
+begin
+
+  -- dodgy OSD transparency...
+	video_o.clk <= video_o_s.clk;
+  video_o.rgb.r <= 	video_o_s.rgb.r;
+  video_o.rgb.g <=  video_o_s.rgb.g;
+  video_o.rgb.b <= 	video_o_s.rgb.b;
+	video_o.hsync <= video_o_s.hsync;
+	video_o.vsync <= video_o_s.vsync;
+	video_o.hblank <= video_o_s.hblank;
+	video_o.vblank <= video_o_s.vblank;
+
+  graphics_o.y <= from_video_ctl.y;
+  -- should this be the 'real' vblank or the 'active' vblank?
+  -- - use the real for now
+  graphics_o.hblank <= video_o_s.hblank;
+  graphics_o.vblank <= video_o_s.vblank;
+  --graphics_o.vblank <= from_video_ctl.vblank;
+    
+  pace_video_controller_inst : entity work.pace_video_controller
+    generic map
+    (
+      CONFIG		  => PACE_VIDEO_CONTROLLER_TYPE,
+      DELAY       => PACE_VIDEO_PIPELINE_DELAY,
+      H_SIZE      => PACE_VIDEO_H_SIZE,
+      V_SIZE      => PACE_VIDEO_V_SIZE,
+      L_CROP      => PACE_VIDEO_L_CROP,
+      R_CROP      => PACE_VIDEO_R_CROP,
+      H_SCALE     => PACE_VIDEO_H_SCALE,
+      V_SCALE     => PACE_VIDEO_V_SCALE,
+      H_SYNC_POL  => PACE_VIDEO_H_SYNC_POLARITY,
+      V_SYNC_POL  => PACE_VIDEO_V_SYNC_POLARITY,
+      BORDER_RGB  => PACE_VIDEO_BORDER_RGB
+    )
+    port map
+    (
+      -- clocking etc
+      video_i         => video_i,
+      
+			-- register interface
+			reg_i.h_scale	=> "000",
+			reg_i.v_scale 	=> "000",
+      -- video data signals (in)
+      rgb_i		    		=> rgb_data,
+
+      -- video control signals (out)
+      video_ctl_o     => from_video_ctl,
+
+      -- VGA signals (out)
+      video_o     		=> video_o_s
+    );
+
+  pace_video_mixer_inst : entity work.pace_video_mixer
+    port map
+    (
+        bitmap_ctl_o  => bitmap_ctl_o_s,
+        tilemap_ctl_o => tilemap_ctl_o_s,
+        sprite_rgb    => sprite_ctl_o_s.rgb,
+        sprite_set    => sprite_ctl_o_s.set,
+        sprite_pri    => sprite_pri,
+        
+        video_ctl_i   => from_video_ctl,
+        graphics_i    => graphics_i,
+        rgb_o         => rgb_data
+    );
+    
+	GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate
+    --bitmap_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
+	end generate GEN_NO_BITMAPS;
+	
+	GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate
+	
+	  forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+	      ctl_i         => bitmap_ctl_i(1),
+	      ctl_o         => bitmap_ctl_o_s(1),
+
+        graphics_i    => graphics_i
+	    );
+		end generate GEN_BITMAP_1;
+
+	GEN_BITMAP_2 : if PACE_VIDEO_NUM_BITMAPS > 1 generate
+
+	  forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_2)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+	      ctl_i         => bitmap_ctl_i(2),
+	      ctl_o         => bitmap_ctl_o_s(2),
+
+        graphics_i    => graphics_i
+	    );
+      
+  end generate GEN_BITMAP_2;
+
+	GEN_BITMAP_3 : if PACE_VIDEO_NUM_BITMAPS > 2 generate
+
+	  forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_3)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+	      ctl_i         => bitmap_ctl_i(3),
+	      ctl_o         => bitmap_ctl_o_s(3),
+
+        graphics_i    => graphics_i
+	    );
+      
+  end generate GEN_BITMAP_3;
+  
+  bitmap_ctl_o <= bitmap_ctl_o_s;
+  
+	GEN_NO_TILEMAPS : if PACE_VIDEO_NUM_TILEMAPS = 0 generate
+    --tilemap_ctl_o_s(1) <= ((others => '0'), (others => '0'), (others => '0'), 
+    --                      (others => (others => '0')), '0');
+	end generate GEN_NO_TILEMAPS;
+	
+	GEN_TILEMAP_1 : if PACE_VIDEO_NUM_TILEMAPS > 0 generate
+	
+	  foreground_mapctl_inst : entity work.tilemapCtl(TILEMAP_1)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+				ctl_i         => tilemap_ctl_i(1),
+				ctl_o         => tilemap_ctl_o_s(1),
+
+        graphics_i    => graphics_i
+	    );
+
+		end generate GEN_TILEMAP_1;
+
+	GEN_TILEMAP_2 : if PACE_VIDEO_NUM_TILEMAPS > 1 generate
+	
+	  background_mapctl_inst : entity work.tilemapCtl(TILEMAP_2)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+				ctl_i         => tilemap_ctl_i(2),
+				ctl_o         => tilemap_ctl_o_s(2),
+
+        graphics_i    => graphics_i
+	    );
+
+		end generate GEN_TILEMAP_2;
+    
+  tilemap_ctl_o <= tilemap_ctl_o_s;
+
+	GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate
+    sprite_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
+    sprite_pri <= '0';
+    spr0_hit <= '0';
+	end generate GEN_NO_SPRITES;
+	
+	GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate
+	
+		sprites_inst : sprite_array
+      generic map
+      (
+        N_SPRITES     => PACE_VIDEO_NUM_SPRITES,
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+			port map
+			(
+				reset				  => video_i.reset,
+  
+        -- register interface
+        reg_i         => sprite_reg_i,
+
+        -- video control signals
+        video_ctl     => from_video_ctl,
+
+        graphics_i    => graphics_i,
+
+				row_a         => sprite_ctl_o_s.a,
+				row_d         => sprite_ctl_i.d,
+				
+				rgb					  => sprite_ctl_o_s.rgb,
+				set           => sprite_ctl_o_s.set,
+				pri           => sprite_pri,
+				spr0_set	    => spr0_hit
+			);
+
+	end generate GEN_SPRITES;
+
+  sprite_ctl_o <= sprite_ctl_o_s;
+
+end SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Inputs.VHD b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Inputs.VHD
new file mode 100644
index 00000000..6551aeaf
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Inputs.VHD	
@@ -0,0 +1,51 @@
+Library IEEE;
+Use     IEEE.std_logic_1164.all;
+
+library work;
+use work.pace_pkg.all;
+
+entity inputs is
+	generic
+	(
+    NUM_DIPS        : integer := 8;
+		NUM_INPUTS 			: integer := 2;
+		CLK_1US_DIV			: natural := 30
+	);
+  port
+  (
+    clk             : in std_logic;                               
+    reset           : in std_logic;                                                          
+		jamma		        : in from_JAMMA_t;
+		
+		dips		        : in std_logic_vector(NUM_DIPS-1 downto 0);
+		inputs	        : out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
+  );
+end entity inputs;
+
+architecture SYN of inputs is
+
+  signal reset_n        : std_logic;
+
+    
+begin
+
+  reset_n <= not reset;
+
+
+  inputmapper_inst : entity work.inputmapper
+		generic map
+		(
+      NUM_DIPS    => NUM_DIPS,
+			NUM_INPUTS	=> NUM_INPUTS
+		)
+    port map
+    (
+      clk       => clk,
+      rst_n     => reset_n,
+		jamma		  => jamma,
+		dips		  => dips,
+      inputs	  => inputs
+    );
+
+    
+end architecture SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/LodeRunner_MiST.sv b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/LodeRunner_MiST.sv
new file mode 100644
index 00000000..d5564488
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/LodeRunner_MiST.sv	
@@ -0,0 +1,285 @@
+module LodeRunner_MiST(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27,
+
+	output [12:0] SDRAM_A,
+	inout  [15:0] SDRAM_DQ,
+	output        SDRAM_DQML,
+	output        SDRAM_DQMH,
+	output        SDRAM_nWE,
+	output        SDRAM_nCAS,
+	output        SDRAM_nRAS,
+	output        SDRAM_nCS,
+	output  [1:0] SDRAM_BA,
+	output        SDRAM_CLK,
+	output        SDRAM_CKE
+);
+
+`include "rtl/build_id.v" 
+
+localparam CONF_STR = {      
+	"KUNGFUM;ROM;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Blending,Off,On;",
+	"O6,Service,Off,On;",
+	"T0,Reset;",
+	"V,v1.0.",`BUILD_DATE
+};
+
+wire       rotate    = status[2];
+wire [1:0] scanlines = status[4:3];
+wire       blend     = status[5];
+wire       service   = status[6];
+
+assign LED = ~ioctl_downl;
+assign SDRAM_CLK = clk_sd;
+assign SDRAM_CKE = 1; 
+
+wire clk_sys, clk_aud, clk_sd, clk_vid;
+wire pll_locked;
+pll_mist pll(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clk_sys),
+	.c1(clk_vid),
+	.c2(clk_sd),
+	.c3(clk_aud),
+	.locked(pll_locked)
+	);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+wire [14:0] rom_addr;
+wire [15:0] rom_do;
+
+wire [13:0] snd_addr;
+wire [15:0] snd_do;
+
+wire [14:0] sp_addr;
+wire [31:0] sp_do;
+
+wire        ioctl_downl;
+wire  [7:0] ioctl_index;
+wire        ioctl_wr;
+wire [24:0] ioctl_addr;
+wire  [7:0] ioctl_dout;
+
+data_io data_io(
+	.clk_sys       ( clk_sd       ),
+	.SPI_SCK       ( SPI_SCK      ),
+	.SPI_SS2       ( SPI_SS2      ),
+	.SPI_DI        ( SPI_DI       ),
+	.ioctl_download( ioctl_downl  ),
+	.ioctl_index   ( ioctl_index  ),
+	.ioctl_wr      ( ioctl_wr     ),
+	.ioctl_addr    ( ioctl_addr   ),
+	.ioctl_dout    ( ioctl_dout   )
+);
+
+wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h10000; //todo
+
+reg port1_req, port2_req;
+sdram sdram(
+	.*,
+	.init_n        ( pll_locked   ),
+	.clk           ( clk_sd      ),
+
+	// port1 used for main + sound CPU
+	.port1_req     ( port1_req    ),
+	.port1_ack     ( ),
+	.port1_a       ( ioctl_addr[23:1] ),
+	.port1_ds      ( {ioctl_addr[0], ~ioctl_addr[0]} ),
+	.port1_we      ( ioctl_downl ),
+	.port1_d       ( {ioctl_dout, ioctl_dout} ),
+	.port1_q       ( ),
+
+	.cpu1_addr     ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]} ),
+	.cpu1_q        ( rom_do ),
+	.cpu2_addr     ( ioctl_downl ? 16'hffff : (16'h4000 + snd_addr[13:1]) ),
+	.cpu2_q        ( snd_do ),
+
+	// port2 for sprite graphics
+	.port2_req     ( port2_req ),
+	.port2_ack     ( ),
+	.port2_a       ( {sp_ioctl_addr[23:16], sp_ioctl_addr[13:0], sp_ioctl_addr[15]} ), // merge sprite roms to 32-bit wide words
+	.port2_ds      ( {sp_ioctl_addr[14], ~sp_ioctl_addr[14]} ),
+	.port2_we      ( ioctl_downl ),
+	.port2_d       ( {ioctl_dout, ioctl_dout} ),
+	.port2_q       ( ),
+
+	.sp_addr       ( ioctl_downl ? 15'h7fff : sp_addr ),
+	.sp_q          ( sp_do )
+);
+
+// ROM download controller
+always @(posedge clk_sd) begin
+	reg        ioctl_wr_last = 0;
+
+	ioctl_wr_last <= ioctl_wr;
+	if (ioctl_downl) begin
+		if (~ioctl_wr_last && ioctl_wr) begin
+			port1_req <= ~port1_req;
+			port2_req <= ~port2_req;
+		end
+	end
+end
+
+// reset signal generation
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge clk_sys) begin
+	reg ioctl_downlD;
+	reg [15:0] reset_count;
+	ioctl_downlD <= ioctl_downl;
+
+	if (status[0] | buttons[1] | ~rom_loaded) reset_count <= 16'hffff;
+	else if (reset_count != 0) reset_count <= reset_count - 1'd1;
+
+	if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+	reset <= reset_count != 16'h0000;
+
+end
+
+wire [11:0] audio;
+wire        hs, vs;
+wire        blankn = 1'b1;//todo
+wire  [3:0] g,b,r;
+
+target_top target_top(
+	.clock_sys(clk_sys),//4xclk_vid
+	.clock_vid(clk_vid),//11MHz
+	.clk_aud(clk_aud),//0.895MHz
+	.reset_in(reset),
+	.audio_out(audio),
+	.usr_coin1(m_coin1),
+	.usr_coin2(m_coin2),
+	.usr_service(service),
+	.usr_start1(m_one_player),
+	.usr_start2(m_two_players),
+	.p1_up(m_up),
+	.p1_dw(m_down),
+	.p1_lt(m_left),
+	.p1_rt(m_right),
+	.p1_f1(m_fireA),
+	.p1_f2(m_fireB),
+	.p2_up(m_up2),
+	.p2_dw(m_down2),
+	.p2_lt(m_left2),
+	.p2_rt(m_right2),
+	.p2_f1(m_fire2A),
+	.p2_f2(m_fire2B),
+	.VGA_VS(vs),
+	.VGA_HS(hs),
+	.VGA_R(r),
+	.VGA_G(g),
+	.VGA_B(b),
+	.cpu_rom_addr(rom_addr),
+	.cpu_rom_do( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
+	.snd_rom_addr(snd_addr),
+	.snd_rom_do(snd_addr[0] ? snd_do[15:8] : snd_do[7:0])
+  ); 
+
+mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
+	.clk_sys        ( clk_sys          ),
+	.SPI_SCK        ( SPI_SCK          ),
+	.SPI_SS3        ( SPI_SS3          ),
+	.SPI_DI         ( SPI_DI           ),
+	.R              ( blankn ? r : 0   ),
+	.G              ( blankn ? g : 0   ),
+	.B              ( blankn ? b : 0   ),
+	.HSync          ( hs               ),
+	.VSync          ( vs               ),
+	.VGA_R          ( VGA_R            ),
+	.VGA_G          ( VGA_G            ),
+	.VGA_B          ( VGA_B            ),
+	.VGA_VS         ( VGA_VS           ),
+	.VGA_HS         ( VGA_HS           ),
+	.rotate         ( { 1'b1, rotate } ),
+	.ce_divider     ( 1'b0             ),
+	.scandoubler_disable( scandoublerD ),
+	.scanlines      ( scanlines        ),
+	.blend          ( blend            ),
+	.ypbpr          ( ypbpr            ),
+	.no_csync       ( no_csync         )
+	);
+
+wire dac_o;
+assign AUDIO_L = dac_o;
+assign AUDIO_R = dac_o;
+
+dac #(
+	.C_bits(12))
+dac(
+	.clk_i(clk_aud),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(dac_o)
+	);
+	
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b10       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
+
+endmodule 
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Sound_Board.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Sound_Board.vhd
new file mode 100644
index 00000000..abcb4631
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/Sound_Board.vhd	
@@ -0,0 +1,423 @@
+---------------------------------------------------------------------------------
+-- Moon patrol sound board by Dar (darfpga@aol.fr)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- gen_ram.vhd  
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- cpu68 - Version 9th Jan 2004 0.8
+-- 6800/01 compatible CPU core 
+-- GNU public license - December 2002 : John E. Kent
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+-- Version 0.0 -- 24/11/2017 -- 
+--		    initial version
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity Sound_Board is
+port(
+ clock_E      : in std_logic; -- 3.58 Mhz/4
+ areset       : in std_logic;
+
+ select_sound : in std_logic_vector(7 downto 0);
+ audio_out    : out std_logic_vector(11 downto 0);
+ snd_rom_addr      : out std_logic_vector(13 downto 0);
+ snd_rom_do        : in std_logic_vector(7 downto 0);
+
+ dbg_cpu_addr : out std_logic_vector(15 downto 0)
+);
+end Sound_Board;
+
+architecture struct of Sound_Board is
+  component YM2149
+  port (
+    CLK         : in  std_logic;
+    CE          : in  std_logic;
+    RESET       : in  std_logic;
+    A8          : in  std_logic := '1';
+    A9_L        : in  std_logic := '0';
+    BDIR        : in  std_logic; -- Bus Direction (0 - read , 1 - write)
+    BC          : in  std_logic; -- Bus control
+    DI          : in  std_logic_vector(7 downto 0);
+    DO          : out std_logic_vector(7 downto 0);
+    CHANNEL_A   : out std_logic_vector(7 downto 0);
+    CHANNEL_B   : out std_logic_vector(7 downto 0);
+    CHANNEL_C   : out std_logic_vector(7 downto 0);
+
+    SEL         : in  std_logic;
+    MODE        : in  std_logic;
+
+    ACTIVE      : out std_logic_vector(5 downto 0);
+
+    IOA_in      : in  std_logic_vector(7 downto 0);
+    IOA_out     : out std_logic_vector(7 downto 0);
+
+    IOB_in      : in  std_logic_vector(7 downto 0);
+    IOB_out     : out std_logic_vector(7 downto 0)
+    );
+  end component;
+
+ signal reset      : std_logic := '1';
+ signal reset_cnt  : integer range 0 to 1000000 := 1000000;
+
+ signal cpu_addr   : std_logic_vector(15 downto 0);
+ signal cpu_di     : std_logic_vector( 7 downto 0);
+ signal cpu_do     : std_logic_vector( 7 downto 0);
+ signal cpu_rw     : std_logic;
+ signal cpu_irq    : std_logic;
+ signal cpu_nmi    : std_logic;
+ 
+ signal irqraz_cs : std_logic;
+ signal irqraz_we : std_logic;
+ 
+ signal wram_cs   : std_logic;
+ signal wram_we   : std_logic;
+ signal wram_do   : std_logic_vector( 7 downto 0);
+ 
+ signal rom_cs    : std_logic;
+ signal rom_do    : std_logic_vector( 7 downto 0);
+
+ signal ay1_chan_a    : std_logic_vector(7 downto 0);
+ signal ay1_chan_b    : std_logic_vector(7 downto 0);
+ signal ay1_chan_c    : std_logic_vector(7 downto 0);
+ signal ay1_do        : std_logic_vector(7 downto 0);
+ signal ay1_audio     : std_logic_vector(9 downto 0);
+ signal ay1_port_b_do : std_logic_vector(7 downto 0);
+ 
+ signal ay2_chan_a    : std_logic_vector(7 downto 0);
+ signal ay2_chan_b    : std_logic_vector(7 downto 0);
+ signal ay2_chan_c    : std_logic_vector(7 downto 0);
+ signal ay2_do        : std_logic_vector(7 downto 0);
+ signal ay2_audio     : std_logic_vector(9 downto 0);
+
+ signal ports_cs    : std_logic;
+ signal ports_we    : std_logic;
+  
+ signal port1_bus   : std_logic_vector(7 downto 0);  
+ signal port1_data  : std_logic_vector(7 downto 0);
+ signal port1_ddr   : std_logic_vector(7 downto 0);
+ signal port1_in    : std_logic_vector(7 downto 0);
+ 
+ signal port2_bus   : std_logic_vector(7 downto 0);  
+ signal port2_data  : std_logic_vector(7 downto 0);
+ signal port2_ddr   : std_logic_vector(7 downto 0);
+ signal port2_in    : std_logic_vector(7 downto 0);
+ 
+ signal adpcm_cs    : std_logic;
+ signal adpcm_we    : std_logic;
+ signal adpcm_0_di  : std_logic_vector(3 downto 0);
+
+ signal select_sound_r : std_logic_vector(7 downto 0);
+
+ signal audio : std_logic_vector(12 downto 0);
+
+ type t_step_size is array(0 to 48) of integer range 0 to 1552;
+ constant step_size : t_step_size := (
+    16,   17,   19,   21,   23,   25,   28,   31,
+    34,   37,   41,   45,   50,   55,   60,   66,
+    73,   80,   88,   97,  107,  118,  130,  143,
+	157,  173,  190,  209,  230,  253,  279,  307,
+	337,  371,  408,  449,  494,  544,  598,  658,
+	724,  796,  876,  963, 1060, 1166, 1282, 1411, 1552);
+	
+ type t_delta_step is array(0 to 7) of integer range -1 to 8;	
+ constant delta_step : t_delta_step := (-1,-1,-1,-1,2,4,6,8);
+
+ signal adpcm_vclk  : std_logic := '0';
+ signal adpcm_signal : integer range -16384 to 16383 := 0; 
+
+-- adpcm algorithm (4bits) [no pcm here]
+--
+--   val    : input value 3bits (0 - 7 : b2b1b0)
+--   sign   : input value sign  (4th bit : 0=>sign=1 ,1=>sign=-1)
+--
+--   step   : internal data, init = 0
+--   signal : output value, init = 0;
+--
+--   for each new val (and sign) :
+--   |
+--   | step_size = 16*1.1^(step)
+--   | delta     = sign * (step_size/8 + step_size/4*b0 + step_size/2*b1 + step_size*b2)
+--   | signal    = signal + delta
+--   | step      = step + delta_step(val)
+--   |
+--   | signal is then limited between -2048..2047
+--   | step   is then limited between     0..48
+ 
+begin
+
+dbg_cpu_addr <= cpu_addr;
+
+-- cs
+wram_cs   <= '1' when cpu_addr(15 downto  7) = X"00"&'1' else '0'; -- 0080-00FF
+ports_cs  <= '1' when cpu_addr(15 downto  4) = X"000"    else '0'; -- 0000-000F
+adpcm_cs  <= '1' when cpu_addr(14 downto 11) = "0001"    else '0'; -- 0800-0FFF / 8800-8FFF
+irqraz_cs <= '1' when cpu_addr(14 downto 12) = "001"     else '0'; -- 1000-1FFF / 9000-9FFF
+rom_cs    <= '1' when cpu_addr(14 downto 12) = "111"     else '0'; -- 7000-7FFF / F000-FFFF
+	
+-- write enables
+wram_we <=   '1' when cpu_rw = '0' and wram_cs =   '1' else '0';
+ports_we <=  '1' when cpu_rw = '0' and ports_cs =  '1' else '0';
+adpcm_we <=  '1' when cpu_rw = '0' and adpcm_cs =  '1' else '0';
+irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';
+
+-- mux cpu in data between roms/io/wram
+cpu_di <=
+	wram_do when wram_cs = '1' else
+	port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
+	port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
+	port1_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
+	port2_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
+	snd_rom_do when rom_cs = '1' else X"55";
+
+process (clock_E)
+begin
+	if rising_edge(clock_E) then
+		reset <= '0';
+		if reset_cnt /= 0 then
+			reset_cnt <= reset_cnt - 1;
+			reset <= '1';
+		end if;
+		if areset = '1' then
+		   reset_cnt <= 1000000;
+		end if;
+	end if;
+end process;
+
+-- irq to cpu
+process (reset, clock_E)
+begin
+	if reset='1' then
+		cpu_irq <= '0';
+		select_sound_r(7) <= '1';
+	elsif rising_edge(clock_E) then
+		select_sound_r <= select_sound;
+		if select_sound_r(7) = '0' then
+			cpu_irq  <= '1';
+		end if;
+		if irqraz_we = '1' then
+			cpu_irq  <= '0';
+		end if;
+	end if;
+end process;
+
+-- cpu nmi
+cpu_nmi <= adpcm_vclk;
+
+-- 6803 ports 1 and 2 (only)
+process (reset, clock_E)
+begin
+	if reset='1' then
+		port1_ddr  <= (others=>'0');  -- port1 set as input
+		port1_data <= (others=>'0');  -- port1 data set to 0
+		port2_ddr  <= ("11100000");   -- port2 bit 7 to 5 should always remain output to simulate mode data
+		port2_data <= ("01000000");   -- port2 data bit 7 to 5 set to 2 (for mode 2 at start up)
+	elsif rising_edge(clock_E) then
+			if ports_cs = '1' and ports_we = '1' then
+				if cpu_addr(3 downto 0) = X"0" then port1_ddr  <= cpu_do; end if;
+				if cpu_addr(3 downto 0) = X"1" then port2_ddr  <= cpu_do and "11100000"; end if;
+				if cpu_addr(3 downto 0) = X"2" then port1_data <= cpu_do; end if; 
+				if cpu_addr(3 downto 0) = X"3" then port2_data <= cpu_do; end if;
+			end if;
+	end if;
+end process;
+
+port1_in <= (port1_bus and not(port1_ddr)) or (port1_data and port1_ddr);
+port2_in <= (port2_bus and not(port2_ddr)) or (port2_data and port2_ddr);
+
+-- port1 bus mux
+port1_bus <= ay1_do when port2_data(4) = '0' else 
+				 ay2_do when port2_data(3) = '0' else X"FF";
+
+-- port2 bus
+port2_bus <= X"FF";
+
+
+-- latch adpcm (msm5205) data in
+process (reset, clock_E)
+begin
+	if reset='1' then
+		adpcm_0_di <= (others=>'0');
+	elsif rising_edge(clock_E) then
+			if adpcm_cs = '1' and adpcm_we = '1' then
+				if cpu_addr(1) = '0' then adpcm_0_di  <= cpu_do(3 downto 0); end if;
+			end if;
+	end if;
+end process;
+
+-- adcpm clocks and computation -- make 24kHz and vclk 8/6/4kHz
+adpcm_clocks : process(clock_E, ay1_port_b_do)
+	variable clock_div_a : integer range 0 to 148 := 0;
+	variable clock_div_b : integer range 0 to 5 := 0;
+	variable step   : integer range  0 to 48;
+	variable step_n : integer range -1 to 48+8;
+   variable sz : integer range 0 to 1552;
+	variable dn : integer range -32768 to 32767;
+	variable adpcm_signal_n : integer range -32768 to 32767;
+begin
+	if rising_edge(clock_E) then
+		if clock_div_a = 37 then   -- 24kHz
+			clock_div_a := 0;
+			
+			case ay1_port_b_do(3 downto 2) is				
+			when "00" => if clock_div_b = 5 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if;  -- 4kHz
+			when "01" => if clock_div_b = 2 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if;  -- 8kHz
+			when "10" => if clock_div_b = 3 then clock_div_b := 0; else clock_div_b := clock_div_b +1; end if;  -- 6kHz
+			when others => null;
+			end case;
+							
+			if clock_div_b = 0 then adpcm_vclk <= '1'; else adpcm_vclk <= '0'; end if;
+		else
+			clock_div_a := clock_div_a + 1;			
+		end if;
+			
+		if ay1_port_b_do(0) = '1' then
+			step := 0;
+			adpcm_signal <= 0;
+		else
+		
+			if clock_div_b = 0 then
+			case clock_div_a is
+			
+			when 0 => -- it's time to get new nibble (adpcm_0_di)
+							
+				sz := step_size(step);
+				dn := sz/8;
+				if adpcm_0_di(0) = '1' then dn := dn + sz/4; end if;
+				if adpcm_0_di(1) = '1' then dn := dn + sz/2; end if;
+				if adpcm_0_di(2) = '1' then dn := dn + sz  ; end if;
+				
+				if adpcm_0_di(3) = '1' then
+					dn := -dn;	
+				end if;
+								
+				step_n := step + delta_step(to_integer(unsigned(adpcm_0_di(2 downto 0))));
+			
+			when 4 => 
+			
+				adpcm_signal_n := adpcm_signal + dn;
+			
+				if step_n > 48 then step := 48; else step := step_n; end if;
+				if step_n < 0  then step := 0;  else step := step_n; end if;
+				
+			when 8 =>
+			
+				if adpcm_signal_n >  2040 then adpcm_signal <=  2040; else adpcm_signal <= adpcm_signal_n; end if;
+				if adpcm_signal_n < -2040 then adpcm_signal <= -2040; else adpcm_signal <= adpcm_signal_n; end if;
+			
+			when others => null;
+			
+			end case;
+			end if;
+			
+		end if;
+	end if;
+end process;
+
+-- audio mux
+audio <= ("000"&ay1_audio) + ("000"&ay2_audio) + ('0'&std_logic_vector(to_unsigned((adpcm_signal)+2048,12)));
+audio_out <= audio(12 downto 1);
+				 
+-- microprocessor 6800/01/03
+main_cpu : entity work.cpu68
+port map(	
+	clk      => clock_E,   -- E clock input (falling edge)
+	rst      => reset,    -- reset input (active high)
+	rw       => cpu_rw,   -- read not write output
+	vma      => open,     -- valid memory address (active high)
+	address  => cpu_addr, -- address bus output
+	data_in  => cpu_di,   -- data bus input
+	data_out => cpu_do,   -- data bus output
+	hold     => '0',      -- hold input (active high) extend bus cycle
+	halt     => '0',      -- halt input (active high) grants DMA
+	irq      => cpu_irq,  -- interrupt request input (active high)
+	nmi      => cpu_nmi,  -- non maskable interrupt request input (active high)
+	test_alu => open,
+	test_cc  => open
+);
+
+
+
+ snd_rom_addr <= cpu_addr(13 downto 0);
+
+ 
+-- cpu wram
+cpu_ram : entity work.spram
+generic map( widthad_a => 7)
+port map(
+ clock  => clock_E,
+ wren   => wram_we,
+ address => cpu_addr(6 downto 0),
+ data    => cpu_do,
+ q    => wram_do
+);
+
+  ay83910_inst1: YM2149
+  port map (
+    CLK         => clock_E,
+    CE          => '1',
+    RESET       => reset,
+    A8          => '1',
+    A9_L        => port2_data(4),
+    BDIR        => port2_data(0),
+    BC          => port2_data(2),
+    DI          => port1_data,
+    DO          => ay1_do,
+    CHANNEL_A   => ay1_chan_a,
+    CHANNEL_B   => ay1_chan_b,
+    CHANNEL_C   => ay1_chan_c,
+
+    SEL         => '0',
+    MODE        => '1',
+
+    ACTIVE      => open,
+
+    IOA_in      => select_sound_r,
+    IOA_out     => open,
+
+    IOB_in      => (others => '0'),
+    IOB_out     => ay1_port_b_do
+    );
+
+  ay1_audio <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c;
+
+  ay83910_inst2: YM2149
+  port map (
+    CLK         => clock_E,
+    CE          => '1',
+    RESET       => reset,
+    A8          => '1',
+    A9_L        => port2_data(3),
+    BDIR        => port2_data(0),
+    BC          => port2_data(2),
+    DI          => port1_data,
+    DO          => ay2_do,
+    CHANNEL_A   => ay2_chan_a,
+    CHANNEL_B   => ay2_chan_b,
+    CHANNEL_C   => ay2_chan_c,
+
+    SEL         => '0',
+    MODE        => '1',
+
+    ACTIVE      => open,
+
+    IOA_in      => (others => '0'),
+    IOA_out     => open,
+
+    IOB_in      => (others => '0'),
+    IOB_out     => open
+    );
+
+  ay2_audio <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c;
+
+end struct;
\ No newline at end of file
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/YM2149.sv b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/YM2149.sv
new file mode 100644
index 00000000..eae73bb3
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/YM2149.sv	
@@ -0,0 +1,329 @@
+//
+// Copyright (c) MikeJ - Jan 2005
+// Copyright (c) 2016-2018 Sorgelig
+//
+// All rights reserved
+//
+// Redistribution and use in source and synthezised forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in synthesized form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// Neither the name of the author nor the names of other contributors may
+// be used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+
+// BDIR  BC  MODE
+//   0   0   inactive
+//   0   1   read value
+//   1   0   write value
+//   1   1   set address
+//
+
+module YM2149
+(
+	input        CLK,       // Global clock
+	input        CE,        // PSG Clock enable
+	input        RESET,     // Chip RESET (set all Registers to '0', active hi)
+	input        BDIR,      // Bus Direction (0 - read , 1 - write)
+	input        BC,        // Bus control
+	input        A8,
+	input        A9_L,
+	input  [7:0] DI,        // Data In
+	output [7:0] DO,        // Data Out
+	output [7:0] CHANNEL_A, // PSG Output channel A
+	output [7:0] CHANNEL_B, // PSG Output channel B
+	output [7:0] CHANNEL_C, // PSG Output channel C
+
+	input        SEL,
+	input        MODE,
+	
+	output [5:0] ACTIVE,
+
+	input  [7:0] IOA_in,
+	output [7:0] IOA_out,
+
+	input  [7:0] IOB_in,
+	output [7:0] IOB_out
+);
+
+assign ACTIVE  = ~ymreg[7][5:0];
+assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff;
+assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff;
+
+reg [7:0] addr;
+reg [7:0] ymreg[16];
+wire      cs = !A9_L & A8;
+
+// Write to PSG
+reg env_reset;
+always @(posedge CLK) begin
+	if(RESET) begin
+		ymreg     <= '{default:0};
+		ymreg[7]  <= '1;
+		addr      <= '0;
+		env_reset <= 0;
+	end else begin
+		env_reset <= 0;
+		if(cs & BDIR) begin
+			if(BC) addr <= DI;
+			else if(!addr[7:4]) begin
+				ymreg[addr[3:0]] <= DI;
+				env_reset <= (addr == 13);
+			end
+		end
+	end
+end
+
+// Read from PSG
+assign DO = dout;
+reg [7:0] dout;
+always_comb begin
+	dout = 8'hFF;
+	if(cs & ~BDIR & BC & !addr[7:4]) begin
+		case(addr[3:0])
+			 0: dout = ymreg[0];
+			 1: dout = ymreg[1][3:0];
+			 2: dout = ymreg[2];
+			 3: dout = ymreg[3][3:0];
+			 4: dout = ymreg[4];
+			 5: dout = ymreg[5][3:0];
+			 6: dout = ymreg[6][4:0];
+			 7: dout = ymreg[7];
+			 8: dout = ymreg[8][4:0];
+			 9: dout = ymreg[9][4:0];
+			10: dout = ymreg[10][4:0];
+			11: dout = ymreg[11];
+			12: dout = ymreg[12];
+			13: dout = ymreg[13][3:0];
+			14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
+			15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
+		endcase
+	end
+end
+
+reg ena_div;
+reg ena_div_noise;
+
+//  p_divider
+always @(posedge CLK) begin
+	reg [3:0]  cnt_div;
+	reg        noise_div;
+
+	if(CE) begin
+		ena_div <= 0;
+		ena_div_noise <= 0;
+		if(!cnt_div) begin
+			cnt_div <= {SEL, 3'b111};
+			ena_div <= 1;
+            
+			noise_div <= (~noise_div);
+			if (noise_div) ena_div_noise <= 1;
+		end else begin
+			cnt_div <= cnt_div - 1'b1;
+		end
+	end
+end
+
+
+reg [2:0] noise_gen_op;
+
+//  p_noise_gen
+always @(posedge CLK) begin
+	reg [16:0] poly17;
+	reg [4:0]  noise_gen_cnt;
+
+	if(CE) begin
+		if (ena_div_noise) begin
+			if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
+				noise_gen_cnt <= 0;
+				poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
+			end else begin
+				noise_gen_cnt <= noise_gen_cnt + 1'd1;
+			end
+			noise_gen_op <= {3{poly17[0]}};
+		end
+	end
+end
+
+wire [11:0] tone_gen_freq[1:3];
+assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
+assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
+assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
+
+reg [3:1] tone_gen_op;
+
+//p_tone_gens
+always @(posedge CLK) begin
+	integer i;
+	reg [11:0] tone_gen_cnt[1:3];
+
+	if(CE) begin
+		// looks like real chips count up - we need to get the Exact behaviour ..
+	
+		for (i = 1; i <= 3; i = i + 1) begin
+			if(ena_div) begin
+				if (tone_gen_freq[i]) begin
+					if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
+						tone_gen_cnt[i] <= 0;
+						tone_gen_op[i]  <= ~tone_gen_op[i];
+					end else begin
+						tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
+					end
+				end else begin
+					tone_gen_op[i] <= ymreg[7][i];
+					tone_gen_cnt[i] <= 0;
+				end
+			end
+		end
+	end
+end
+
+reg env_ena;
+wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
+
+//p_envelope_freq
+always @(posedge CLK) begin
+	reg [15:0] env_gen_cnt;
+
+	if(CE) begin
+		env_ena <= 0;
+		if(ena_div) begin
+			if (env_gen_cnt >= env_gen_comp) begin
+				env_gen_cnt <= 0;
+				env_ena <= 1;
+			end else begin
+				env_gen_cnt <= (env_gen_cnt + 1'd1);
+			end
+		end
+	end
+end
+
+reg [4:0] env_vol;
+
+wire is_bot    = (env_vol == 5'b00000);
+wire is_bot_p1 = (env_vol == 5'b00001);
+wire is_top_m1 = (env_vol == 5'b11110);
+wire is_top    = (env_vol == 5'b11111);
+
+always @(posedge CLK) begin
+	reg env_hold;
+	reg env_inc;
+
+	// envelope shapes
+	// C AtAlH
+	// 0 0 x x  \___
+	//
+	// 0 1 x x  /___
+	//
+	// 1 0 0 0  \\\\
+	//
+	// 1 0 0 1  \___
+	//
+	// 1 0 1 0  \/\/
+	//           ___
+	// 1 0 1 1  \
+	//
+	// 1 1 0 0  ////
+	//           ___
+	// 1 1 0 1  /
+	//
+	// 1 1 1 0  /\/\
+	//
+	// 1 1 1 1  /___
+
+	if(env_reset | RESET) begin
+		// load initial state
+		if(!ymreg[13][2]) begin		// attack
+			env_vol <= 5'b11111;
+			env_inc <= 0;		// -1
+		end else begin
+			env_vol <= 5'b00000;
+			env_inc <= 1;		// +1
+		end
+		env_hold <= 0;
+	end
+	else if(CE) begin
+		if (env_ena) begin
+			if (!env_hold) begin
+				if (env_inc) env_vol <= (env_vol + 5'b00001);
+					else env_vol <= (env_vol + 5'b11111);
+			end
+
+			// envelope shape control.
+			if(!ymreg[13][3]) begin
+				if(!env_inc) begin	// down
+					if(is_bot_p1) env_hold <= 1;
+				end else if (is_top) env_hold <= 1;
+			end else if(ymreg[13][0]) begin		// hold = 1
+				if(!env_inc) begin	// down
+					if(ymreg[13][1]) begin		// alt
+						if(is_bot) env_hold <= 1;
+					end else if(is_bot_p1) env_hold <= 1;
+				end else if(ymreg[13][1]) begin	// alt
+					if(is_top) env_hold <= 1;
+				end else if(is_top_m1) env_hold <= 1;
+			end else if(ymreg[13][1]) begin		// alternate
+				if(env_inc == 1'b0) begin		// down
+					if(is_bot_p1) env_hold <= 1;
+					if(is_bot) begin
+						env_hold <= 0;
+						env_inc  <= 1;
+					end
+				end else begin
+					if(is_top_m1) env_hold <= 1;
+					if(is_top) begin
+						env_hold <= 0;
+						env_inc  <= 0;
+					end
+				end
+			end
+		end
+	end
+end
+
+reg [5:0] A,B,C;
+always @(posedge CLK) begin
+	A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4]  ? env_vol[4:0] : { ymreg[8][3:0],  ymreg[8][3]}};
+	B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4]  ? env_vol[4:0] : { ymreg[9][3:0],  ymreg[9][3]}};
+	C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}};
+end
+
+wire [7:0] volTable[64] = '{
+	//YM2149
+	8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, 
+	8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, 
+	8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, 
+	8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff,
+
+	//AY8910
+	8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, 
+	8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, 
+	8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, 
+	8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff 
+};
+
+assign CHANNEL_A = volTable[A];
+assign CHANNEL_B = volTable[B];
+assign CHANNEL_C = volTable[C];
+
+endmodule
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/bitmapctl_e.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/bitmapctl_e.vhd
new file mode 100644
index 00000000..be8471e3
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/bitmapctl_e.vhd	
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.platform_pkg.all;
+--use work.project_pkg.all;
+
+entity bitmapCtl is
+  generic
+  (
+    DELAY         : integer
+  );
+  port               
+  (
+    reset					: in std_logic;
+
+    -- video control signals		
+    video_ctl     : in from_VIDEO_CTL_t;
+
+    -- bitmap controller signals
+    ctl_i         : in to_BITMAP_CTL_t;
+    ctl_o         : out from_BITMAP_CTL_t;
+
+    graphics_i    : in to_GRAPHICS_t
+  );
+end entity bitmapCtl;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/build_id.tcl b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/clk_div.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/clk_div.vhd
new file mode 100644
index 00000000..020d6ae6
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/clk_div.vhd	
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clk_div is
+	generic
+	(
+		DIVISOR   : natural
+	);
+  port
+  (
+    clk       : in std_logic;
+    reset     : in std_logic;
+
+		clk_en    : out std_logic
+  );
+end clk_div;
+
+architecture SYN of clk_div is
+
+begin
+
+	process (clk, reset)
+		variable count : integer range 0 to DIVISOR-1;
+	begin
+		if reset = '1' then
+			count := 0;
+			clk_en <= '0';
+		elsif rising_edge(clk) then
+			clk_en <= '0';
+			if count = DIVISOR-1 then
+				clk_en <= '1';
+				count := 0;
+			else
+				count := count + 1;
+			end if;
+		end if;
+	end process;
+
+end SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/cpu68.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/cpu68.vhd
new file mode 100644
index 00000000..016bd9a9
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/cpu68.vhd	
@@ -0,0 +1,3963 @@
+--===========================================================================--
+--
+--  S Y N T H E Z I A B L E    CPU68   C O R E
+--
+--  www.OpenCores.Org - December 2002
+--  This core adheres to the GNU public license  
+--
+-- File name      : cpu68.vhd
+--
+-- Purpose        : Implements a 6800 compatible CPU core with some
+--                  additional instructions found in the 6801
+--                  
+-- Dependencies   : ieee.Std_Logic_1164
+--                  ieee.std_logic_unsigned
+--
+-- Author         : John E. Kent      
+--
+--===========================================================================----
+--
+-- Revision History:
+--
+-- Date:          Revision         Author
+-- 22 Sep 2002    0.1              John Kent
+--
+-- 30 Oct 2002    0.2              John Kent
+-- made NMI edge triggered
+--
+-- 30 Oct 2002    0.3              John Kent
+-- more corrections to NMI
+-- added wai_wait_state to prevent stack overflow on wai.
+--
+--  1 Nov 2002    0.4              John Kent
+-- removed WAI states and integrated WAI with the interrupt service routine
+-- replace Data out (do) and Data in (di) register with a single Memory Data (md) reg.
+-- Added Multiply instruction states.
+-- run ALU and CC out of CPU module for timing measurements.
+-- 
+--  3 Nov 2002    0.5              John Kent
+-- Memory Data Register was not loaded on Store instructions
+-- SEV and CLV were not defined in the ALU
+-- Overflow Flag on NEG was incorrect
+--
+-- 16th Feb 2003  0.6              John Kent
+-- Rearranged the execution cycle for dual operand instructions
+-- so that occurs during the following fetch cycle.
+-- This allows the reduction of one clock cycle from dual operand
+-- instruction. Note that this also necessitated re-arranging the
+-- program counter so that it is no longer incremented in the ALU.
+-- The effective address has also been re-arranged to include a 
+-- separate added. The STD (store accd) now sets the condition codes.
+--
+-- 28th Jun 2003 0.7               John Kent
+-- Added Hold and Halt signals. Hold is used to steal cycles from the
+-- CPU or add wait states. Halt puts the CPU in the inactive state
+-- and is only honoured in the fetch cycle. Both signals are active high.
+--
+-- 9th Jan 2004 0.8						John Kent
+-- Clear instruction did an alu_ld8 rather than an alu_clr, so
+-- the carry bit was not cleared correctly.
+-- This error was picked up by Michael Hassenfratz.
+--
+
+library ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity cpu68 is
+	port (	
+		clk:	    in  std_logic;
+		rst:	    in  std_logic;
+		rw:	    out std_logic;
+		vma:	    out std_logic;
+		address:	 out std_logic_vector(15 downto 0);
+	   data_in:	 in  std_logic_vector(7 downto 0);
+	   data_out: out std_logic_vector(7 downto 0);
+		hold:     in  std_logic;
+		halt:     in  std_logic;
+		irq:      in  std_logic;
+		nmi:      in  std_logic;
+		test_alu: out std_logic_vector(15 downto 0);
+		test_cc:  out std_logic_vector(7 downto 0)
+		);
+end;
+
+architecture CPU_ARCH of cpu68 is
+
+  constant SBIT : integer := 7;
+  constant XBIT : integer := 6;
+  constant HBIT : integer := 5;
+  constant IBIT : integer := 4;
+  constant NBIT : integer := 3;
+  constant ZBIT : integer := 2;
+  constant VBIT : integer := 1;
+  constant CBIT : integer := 0;
+
+	type state_type is (reset_state, fetch_state, decode_state,
+                       extended_state, indexed_state, read8_state, read16_state, immediate16_state,
+	                    write8_state, write16_state,
+						     execute_state, halt_state, error_state,
+						     mul_state, mulea_state, muld_state,
+						     mul0_state, mul1_state, mul2_state, mul3_state,
+						     mul4_state, mul5_state, mul6_state, mul7_state,
+							  jmp_state, jsr_state, jsr1_state,
+						     branch_state, bsr_state, bsr1_state, 
+							  rts_hi_state, rts_lo_state,
+							  int_pcl_state, int_pch_state,
+						     int_ixl_state, int_ixh_state,
+						     int_cc_state, int_acca_state, int_accb_state,
+						     int_wai_state, int_mask_state,
+						     rti_state, rti_cc_state, rti_acca_state, rti_accb_state,
+						     rti_ixl_state, rti_ixh_state,
+						     rti_pcl_state, rti_pch_state,
+							  pula_state, psha_state, pulb_state, pshb_state,
+						     pulx_lo_state, pulx_hi_state, pshx_lo_state, pshx_hi_state,
+							  vect_lo_state, vect_hi_state );
+	type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad );
+	type dout_type is (md_lo_dout, md_hi_dout, acca_dout, accb_dout, ix_lo_dout, ix_hi_dout, cc_dout, pc_lo_dout, pc_hi_dout );
+   type op_type is (reset_op, fetch_op, latch_op );
+   type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
+   type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
+   type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
+	type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
+	type sp_type is (reset_sp, latch_sp, load_sp );
+	type pc_type is (reset_pc, latch_pc, load_ea_pc, add_ea_pc, pull_lo_pc, pull_hi_pc, inc_pc );
+   type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
+   type ea_type is (reset_ea, latch_ea, add_ix_ea, load_accb_ea, inc_ea, fetch_first_ea, fetch_next_ea );
+	type iv_type is (reset_iv, latch_iv, swi_iv, nmi_iv, irq_iv );
+	type nmi_type is (reset_nmi, set_nmi, latch_nmi );
+	type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, sp_left );
+	type right_type is (md_right, zero_right, plus_one_right, accb_right );
+   type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc, 
+                       alu_and, alu_ora, alu_eor,
+                       alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
+							  alu_inx, alu_dex, alu_cpx,
+						     alu_lsr16, alu_lsl16,
+						     alu_ror8, alu_rol8,
+						     alu_asr8, alu_asl8, alu_lsr8,
+						     alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv, alu_tpa, alu_tap,
+						     alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa );
+
+	signal op_code:     std_logic_vector(7 downto 0);
+  	signal acca:        std_logic_vector(7 downto 0);
+  	signal accb:        std_logic_vector(7 downto 0);
+   signal cc:          std_logic_vector(7 downto 0);
+	signal cc_out:      std_logic_vector(7 downto 0);
+	signal xreg:        std_logic_vector(15 downto 0);
+	signal sp:          std_logic_vector(15 downto 0);
+	signal ea:          std_logic_vector(15 downto 0);
+	signal pc:	        std_logic_vector(15 downto 0);
+	signal md:          std_logic_vector(15 downto 0);
+   signal left:        std_logic_vector(15 downto 0);
+   signal right:       std_logic_vector(15 downto 0);
+	signal out_alu:     std_logic_vector(15 downto 0);
+	signal iv:          std_logic_vector(1 downto 0);
+	signal nmi_req:     std_logic;
+	signal nmi_ack:     std_logic;
+
+	signal state:       state_type;
+	signal next_state:  state_type;
+   signal pc_ctrl:     pc_type;
+   signal ea_ctrl:     ea_type; 
+   signal op_ctrl:     op_type;
+	signal md_ctrl:     md_type;
+	signal acca_ctrl:   acca_type;
+	signal accb_ctrl:   accb_type;
+	signal ix_ctrl:     ix_type;
+	signal cc_ctrl:     cc_type;
+	signal sp_ctrl:     sp_type;
+	signal iv_ctrl:     iv_type;
+	signal left_ctrl:   left_type;
+	signal right_ctrl:  right_type;
+   signal alu_ctrl:    alu_type;
+   signal addr_ctrl:   addr_type;
+   signal dout_ctrl:   dout_type;
+   signal nmi_ctrl:    nmi_type;
+
+
+begin
+
+----------------------------------
+--
+-- Address bus multiplexer
+--
+----------------------------------
+
+addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv )
+begin
+  case addr_ctrl is
+    when idle_ad =>
+	   address <= "1111111111111111";
+		vma     <= '0';
+		rw      <= '1';
+    when fetch_ad =>
+	   address <= pc;
+		vma     <= '1';
+		rw      <= '1';
+	 when read_ad =>
+	   address <= ea;
+		vma     <= '1';
+		rw      <= '1';
+    when write_ad =>
+	   address <= ea;
+		vma     <= '1';
+		rw      <= '0';
+	 when push_ad =>
+	   address <= sp;
+		vma     <= '1';
+		rw      <= '0';
+    when pull_ad =>
+	   address <= sp;
+		vma     <= '1';
+		rw      <= '1';
+	 when int_hi_ad =>
+	   address <= "1111111111111" & iv & "0";
+		vma     <= '1';
+		rw      <= '1';
+    when int_lo_ad =>
+	   address <= "1111111111111" & iv & "1";
+		vma     <= '1';
+		rw      <= '1';
+	 when others =>
+	   address <= "1111111111111111";
+		vma     <= '0';
+		rw      <= '1';
+  end case;
+end process;
+
+--------------------------------
+--
+-- Data Bus output
+--
+--------------------------------
+dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, pc, cc )
+begin
+    case dout_ctrl is
+	 when md_hi_dout => -- alu output
+	   data_out <= md(15 downto 8);
+	 when md_lo_dout =>
+	   data_out <= md(7 downto 0);
+	 when acca_dout => -- accumulator a
+	   data_out <= acca;
+	 when accb_dout => -- accumulator b
+	   data_out <= accb;
+	 when ix_lo_dout => -- index reg
+	   data_out <= xreg(7 downto 0);
+	 when ix_hi_dout => -- index reg
+	   data_out <= xreg(15 downto 8);
+	 when cc_dout => -- condition codes
+	   data_out <= cc;
+	 when pc_lo_dout => -- low order pc
+	   data_out <= pc(7 downto 0);
+	 when pc_hi_dout => -- high order pc
+	   data_out <= pc(15 downto 8);
+	 when others =>
+	   data_out <= "00000000";
+    end case;
+end process;
+
+
+----------------------------------
+--
+-- Program Counter Control
+--
+----------------------------------
+
+pc_mux: process( clk, pc_ctrl, pc, out_alu, data_in, ea, hold )
+variable tempof : std_logic_vector(15 downto 0);
+variable temppc : std_logic_vector(15 downto 0);
+begin
+  case pc_ctrl is
+  when add_ea_pc =>
+	 if ea(7) = '0' then
+	   tempof := "00000000" & ea(7 downto 0);
+    else
+		tempof := "11111111" & ea(7 downto 0);
+    end if;
+  when inc_pc =>
+	 tempof := "0000000000000001";
+  when others =>
+    tempof := "0000000000000000";
+  end case;
+
+  case pc_ctrl is
+  when reset_pc =>
+	 temppc := "1111111111111110";
+  when load_ea_pc =>
+	 temppc := ea;
+  when pull_lo_pc =>
+	 temppc(7 downto 0) := data_in;
+	 temppc(15 downto 8) := pc(15 downto 8);
+  when pull_hi_pc =>
+	 temppc(7 downto 0) := pc(7 downto 0);
+	 temppc(15 downto 8) := data_in;
+  when others =>
+    temppc := pc;
+  end case;
+
+  if clk'event and clk = '0' then
+    if hold = '1' then
+      pc <= pc;
+    else
+      pc <= temppc + tempof;
+	 end if;
+  end if;
+end process;
+
+----------------------------------
+--
+-- Effective Address  Control
+--
+----------------------------------
+
+ea_mux: process( clk, ea_ctrl, ea, out_alu, data_in, accb, xreg, hold )
+variable tempind : std_logic_vector(15 downto 0);
+variable tempea  : std_logic_vector(15 downto 0);
+begin
+  case ea_ctrl is
+  when add_ix_ea =>
+	 tempind := "00000000" & ea(7 downto 0);
+  when inc_ea =>
+	 tempind := "0000000000000001";
+  when others =>
+    tempind := "0000000000000000";
+  end case;
+
+  case ea_ctrl is
+  when reset_ea =>
+	 tempea := "0000000000000000";
+  when load_accb_ea =>
+	 tempea := "00000000" & accb(7 downto 0);
+  when add_ix_ea =>
+	 tempea := xreg;
+  when fetch_first_ea =>
+	 tempea(7 downto 0) := data_in;
+	 tempea(15 downto 8) := "00000000";
+  when fetch_next_ea =>
+	 tempea(7 downto 0) := data_in;
+	 tempea(15 downto 8) := ea(7 downto 0);
+  when others =>
+    tempea := ea;
+  end case;
+
+  if clk'event and clk = '0' then
+    if hold = '1' then
+      ea <= ea;
+    else
+      ea <= tempea + tempind;
+	 end if;
+  end if;
+end process;
+
+--------------------------------
+--
+-- Accumulator A
+--
+--------------------------------
+acca_mux : process( clk, acca_ctrl, out_alu, acca, data_in, hold )
+begin
+  if clk'event and clk = '0' then
+    if hold = '1' then
+	   acca <= acca;
+	 else
+    case acca_ctrl is
+    when reset_acca =>
+	   acca <= "00000000";
+	 when load_acca =>
+	   acca <= out_alu(7 downto 0);
+	 when load_hi_acca =>
+	   acca <= out_alu(15 downto 8);
+	 when pull_acca =>
+	   acca <= data_in;
+	 when others =>
+--	 when latch_acca =>
+	   acca <= acca;
+    end case;
+	 end if;
+  end if;
+end process;
+
+--------------------------------
+--
+-- Accumulator B
+--
+--------------------------------
+accb_mux : process( clk, accb_ctrl, out_alu, accb, data_in, hold )
+begin
+  if clk'event and clk = '0' then
+    if hold = '1' then
+	   accb <= accb;
+	 else
+    case accb_ctrl is
+    when reset_accb =>
+	   accb <= "00000000";
+	 when load_accb =>
+	   accb <= out_alu(7 downto 0);
+	 when pull_accb =>
+	   accb <= data_in;
+	 when others =>
+--	 when latch_accb =>
+	   accb <= accb;
+    end case;
+	 end if;
+  end if;
+end process;
+
+--------------------------------
+--
+-- X Index register
+--
+--------------------------------
+ix_mux : process( clk, ix_ctrl, out_alu, xreg, data_in, hold )
+begin
+  if clk'event and clk = '0' then
+    if hold = '1' then
+	   xreg <= xreg;
+	 else
+    case ix_ctrl is
+    when reset_ix =>
+	   xreg <= "0000000000000000";
+	 when load_ix =>
+	   xreg <= out_alu(15 downto 0);
+	 when pull_hi_ix =>
+	   xreg(15 downto 8) <= data_in;
+	 when pull_lo_ix =>
+	   xreg(7 downto 0) <= data_in;
+	 when others =>
+--	 when latch_ix =>
+	   xreg <= xreg;
+    end case;
+	 end if;
+  end if;
+end process;
+
+--------------------------------
+--
+-- stack pointer
+--
+--------------------------------
+sp_mux : process( clk, sp_ctrl, out_alu, hold )
+begin
+  if clk'event and clk = '0' then
+    if hold = '1' then
+	   sp <= sp;
+	 else
+    case sp_ctrl is
+    when reset_sp =>
+	   sp <= "0000000000000000";
+	 when load_sp =>
+	   sp <= out_alu(15 downto 0);
+	 when others =>
+--	 when latch_sp =>
+	   sp <= sp;
+    end case;
+	 end if;
+  end if;
+end process;
+
+--------------------------------
+--
+-- Memory Data
+--
+--------------------------------
+md_mux : process( clk, md_ctrl, out_alu, data_in, md, hold )
+begin
+  if clk'event and clk = '0' then
+    if hold = '1' then
+	   md <= md;
+	 else
+    case md_ctrl is
+    when reset_md =>
+	   md <= "0000000000000000";
+	 when load_md =>
+	   md <= out_alu(15 downto 0);
+	 when fetch_first_md =>
+	   md(15 downto 8) <= "00000000";
+	   md(7 downto 0) <= data_in;
+	 when fetch_next_md =>
+	   md(15 downto 8) <= md(7 downto 0);
+		md(7 downto 0) <= data_in;
+	 when shiftl_md =>
+	   md(15 downto 1) <= md(14 downto 0);
+		md(0) <= '0';
+	 when others =>
+--	 when latch_md =>
+	   md <= md;
+    end case;
+	 end if;
+  end if;
+end process;
+
+
+----------------------------------
+--
+-- Condition Codes
+--
+----------------------------------
+
+cc_mux: process( clk, cc_ctrl, cc_out, cc, data_in, hold )
+begin
+  if clk'event and clk = '0' then
+    if hold = '1' then
+	   cc <= cc;
+	 else
+    case cc_ctrl is
+	 when reset_cc =>
+	   cc <= "11000000";
+	 when load_cc =>
+	   cc <= cc_out;
+  	 when pull_cc =>
+      cc <= data_in;
+	 when others =>
+--  when latch_cc =>
+      cc <= cc;
+    end case;
+	 end if;
+  end if;
+end process;
+
+----------------------------------
+--
+-- interrupt vector
+--
+----------------------------------
+
+iv_mux: process( clk, iv_ctrl, hold )
+begin
+  if clk'event and clk = '0' then
+    if hold = '1' then
+	   iv <= iv;
+	 else
+    case iv_ctrl is
+	 when reset_iv =>
+	   iv <= "11";
+	 when nmi_iv =>
+      iv <= "10";
+  	 when swi_iv =>
+      iv <= "01";
+	 when irq_iv =>
+      iv <= "00";
+	 when others =>
+	   iv <= iv;
+    end case;
+	 end if;
+  end if;
+end process;
+
+----------------------------------
+--
+-- op code fetch
+--
+----------------------------------
+
+op_fetch: process( clk, data_in, op_ctrl, op_code, hold )
+begin
+  if clk'event and clk = '0' then
+    if hold = '1' then
+	   op_code <= op_code;
+	 else
+    case op_ctrl is
+	 when reset_op =>
+	   op_code <= "00000001"; -- nop
+  	 when fetch_op =>
+      op_code <= data_in;
+	 when others =>
+--	 when latch_op =>
+	   op_code <= op_code;
+    end case;
+	 end if;
+  end if;
+end process;
+
+----------------------------------
+--
+-- Left Mux
+--
+----------------------------------
+
+left_mux: process( left_ctrl, acca, accb, xreg, sp, pc, ea, md )
+begin
+  case left_ctrl is
+	 when acca_left =>
+	   left(15 downto 8) <= "00000000";
+		left(7 downto 0)  <= acca;
+	 when accb_left =>
+	   left(15 downto 8) <= "00000000";
+		left(7 downto 0)  <= accb;
+	 when accd_left =>
+	   left(15 downto 8) <= acca;
+		left(7 downto 0)  <= accb;
+	 when ix_left =>
+	   left <= xreg;
+	 when sp_left =>
+	   left <= sp;
+	 when others =>
+--	 when md_left =>
+	   left <= md;
+    end case;
+end process;
+----------------------------------
+--
+-- Right Mux
+--
+----------------------------------
+
+right_mux: process( right_ctrl, data_in, md, accb, ea )
+begin
+  case right_ctrl is
+	 when zero_right =>
+	   right <= "0000000000000000";
+	 when plus_one_right =>
+	   right <= "0000000000000001";
+	 when accb_right =>
+	   right <= "00000000" & accb;
+	 when others =>
+--	 when md_right =>
+	   right <= md;
+    end case;
+end process;
+
+----------------------------------
+--
+-- Arithmetic Logic Unit
+--
+----------------------------------
+
+mux_alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
+variable valid_lo, valid_hi : boolean;
+variable carry_in : std_logic;
+variable daa_reg : std_logic_vector(7 downto 0);
+begin
+
+  case alu_ctrl is
+  	 when alu_adc | alu_sbc |
+  	      alu_rol8 | alu_ror8 =>
+	   carry_in := cc(CBIT);
+  	 when others =>
+	   carry_in := '0';
+  end case;
+
+  valid_lo := left(3 downto 0) <= 9;
+  valid_hi := left(7 downto 4) <= 9;
+
+  if (cc(CBIT) = '0') then
+    if( cc(HBIT) = '1' ) then
+		if valid_hi then
+		  daa_reg := "00000110";
+		else
+		  daa_reg := "01100110";
+	   end if;
+    else
+		if valid_lo then
+		  if valid_hi then
+		    daa_reg := "00000000";
+		  else
+		    daa_reg := "01100000";
+		  end if;
+		else
+	     if( left(7 downto 4) <= 8 ) then
+		    daa_reg := "00000110";
+		  else
+			 daa_reg := "01100110";
+		  end if;
+		end if;
+	 end if;
+  else
+    if ( cc(HBIT) = '1' )then
+		daa_reg := "01100110";
+ 	 else
+		if valid_lo then
+		  daa_reg := "01100000";
+	   else
+		  daa_reg := "01100110";
+		end if;
+	 end if;
+  end if;
+
+  case alu_ctrl is
+  	 when alu_add8 | alu_inc |
+  	      alu_add16 | alu_inx |
+  	      alu_adc =>
+		out_alu <= left + right + ("000000000000000" & carry_in);
+  	 when alu_sub8 | alu_dec |
+  	      alu_sub16 | alu_dex |
+  	      alu_sbc | alu_cpx =>
+	   out_alu <= left - right - ("000000000000000" & carry_in);
+  	 when alu_and =>
+	   out_alu   <= left and right; 	-- and/bit
+  	 when alu_ora =>
+	   out_alu   <= left or right; 	-- or
+  	 when alu_eor =>
+	   out_alu   <= left xor right; 	-- eor/xor
+  	 when alu_lsl16 | alu_asl8 | alu_rol8 =>
+	   out_alu   <= left(14 downto 0) & carry_in; 	-- rol8/asl8/lsl16
+  	 when alu_lsr16 | alu_lsr8 =>
+	   out_alu   <= carry_in & left(15 downto 1); 	-- lsr
+  	 when alu_ror8 =>
+	   out_alu   <= "00000000" & carry_in & left(7 downto 1); 	-- ror
+  	 when alu_asr8 =>
+	   out_alu   <= "00000000" & left(7) & left(7 downto 1); 	-- asr
+  	 when alu_neg =>
+	   out_alu   <= right - left; 	-- neg (right=0)
+  	 when alu_com =>
+	   out_alu   <= not left;
+  	 when alu_clr | alu_ld8 | alu_ld16 =>
+	   out_alu   <= right; 	         -- clr, ld
+	 when alu_st8 | alu_st16 =>
+	   out_alu   <= left;
+	 when alu_daa =>
+	   out_alu   <= left + ("00000000" & daa_reg);
+	 when alu_tpa =>
+	   out_alu <= "00000000" & cc;
+  	 when others =>
+	   out_alu   <= left; -- nop
+    end case;
+
+	 --
+	 -- carry bit
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_adc  =>
+      cc_out(CBIT) <= (left(7) and right(7)) or
+		                (left(7) and not out_alu(7)) or
+						   (right(7) and not out_alu(7));
+  	 when alu_sub8 | alu_sbc =>
+      cc_out(CBIT) <= ((not left(7)) and right(7)) or
+		                ((not left(7)) and out_alu(7)) or
+						         (right(7) and out_alu(7));
+  	 when alu_add16  =>
+      cc_out(CBIT) <= (left(15) and right(15)) or
+		                (left(15) and not out_alu(15)) or
+						   (right(15) and not out_alu(15));
+  	 when alu_sub16 =>
+      cc_out(CBIT) <= ((not left(15)) and right(15)) or
+		                ((not left(15)) and out_alu(15)) or
+						         (right(15) and out_alu(15));
+	 when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
+	   cc_out(CBIT) <= left(0);
+	 when alu_rol8 | alu_asl8 =>
+	   cc_out(CBIT) <= left(7);
+	 when alu_lsl16 =>
+	   cc_out(CBIT) <= left(15);
+	 when alu_com =>
+	   cc_out(CBIT) <= '1';
+	 when alu_neg | alu_clr =>
+	   cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
+		                out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0); 
+    when alu_daa =>
+	   if ( daa_reg(7 downto 4) = "0110" ) then
+		  cc_out(CBIT) <= '1';
+		else
+		  cc_out(CBIT) <= '0';
+	   end if;
+  	 when alu_sec =>
+      cc_out(CBIT) <= '1';
+  	 when alu_clc =>
+      cc_out(CBIT) <= '0';
+    when alu_tap =>
+      cc_out(CBIT) <= left(CBIT);
+  	 when others => -- carry is not affected by cpx
+      cc_out(CBIT) <= cc(CBIT);
+    end case;
+	 --
+	 -- Zero flag
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_sub8 |
+	      alu_adc | alu_sbc |
+  	      alu_and | alu_ora | alu_eor |
+  	      alu_inc | alu_dec | 
+			alu_neg | alu_com | alu_clr |
+			alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
+		   alu_ld8  | alu_st8 =>
+      cc_out(ZBIT) <= not( out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
+	                        out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
+  	 when alu_add16 | alu_sub16 |
+  	      alu_lsl16 | alu_lsr16 |
+  	      alu_inx | alu_dex |
+		   alu_ld16  | alu_st16 | alu_cpx =>
+      cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
+	                        out_alu(11) or out_alu(10) or out_alu(9)  or out_alu(8)  or
+  	                        out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
+	                        out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
+    when alu_tap =>
+      cc_out(ZBIT) <= left(ZBIT);
+  	 when others =>
+      cc_out(ZBIT) <= cc(ZBIT);
+    end case;
+
+    --
+	 -- negative flag
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_sub8 |
+	      alu_adc | alu_sbc |
+	      alu_and | alu_ora | alu_eor |
+  	      alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
+  	      alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
+			alu_ld8  | alu_st8 =>
+      cc_out(NBIT) <= out_alu(7);
+	 when alu_add16 | alu_sub16 |
+	      alu_lsl16 | alu_lsr16 |
+			alu_ld16 | alu_st16 | alu_cpx =>
+		cc_out(NBIT) <= out_alu(15);
+    when alu_tap =>
+      cc_out(NBIT) <= left(NBIT);
+  	 when others =>
+      cc_out(NBIT) <= cc(NBIT);
+    end case;
+
+    --
+	 -- Interrupt mask flag
+    --
+    case alu_ctrl is
+  	 when alu_sei =>
+		cc_out(IBIT) <= '1';               -- set interrupt mask
+  	 when alu_cli =>
+		cc_out(IBIT) <= '0';               -- clear interrupt mask
+	 when alu_tap =>
+      cc_out(IBIT) <= left(IBIT);
+  	 when others =>
+		cc_out(IBIT) <= cc(IBIT);             -- interrupt mask
+    end case;
+
+    --
+    -- Half Carry flag
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_adc =>
+      cc_out(HBIT) <= (left(3) and right(3)) or
+                     (right(3) and not out_alu(3)) or 
+                      (left(3) and not out_alu(3));
+    when alu_tap =>
+      cc_out(HBIT) <= left(HBIT);
+  	 when others =>
+		cc_out(HBIT) <= cc(HBIT);
+    end case;
+
+    --
+    -- Overflow flag
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_adc =>
+      cc_out(VBIT) <= (left(7)  and      right(7)  and (not out_alu(7))) or
+                 ((not left(7)) and (not right(7)) and      out_alu(7));
+	 when alu_sub8 | alu_sbc =>
+      cc_out(VBIT) <= (left(7)  and (not right(7)) and (not out_alu(7))) or
+                 ((not left(7)) and      right(7)  and      out_alu(7));
+  	 when alu_add16 =>
+      cc_out(VBIT) <= (left(15)  and      right(15)  and (not out_alu(15))) or
+                 ((not left(15)) and (not right(15)) and      out_alu(15));
+	 when alu_sub16 | alu_cpx =>
+      cc_out(VBIT) <= (left(15)  and (not right(15)) and (not out_alu(15))) or
+                 ((not left(15)) and      right(15) and       out_alu(15));
+	 when alu_inc =>
+	   cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
+		                      left(3)  and left(2) and left(1) and left(0));
+	 when alu_dec | alu_neg =>
+	   cc_out(VBIT) <= (left(7)  and (not left(6)) and (not left(5)) and (not left(4)) and
+		            (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
+	 when alu_asr8 =>
+	   cc_out(VBIT) <= left(0) xor left(7);
+	 when alu_lsr8 | alu_lsr16 =>
+	   cc_out(VBIT) <= left(0);
+	 when alu_ror8 =>
+      cc_out(VBIT) <= left(0) xor cc(CBIT);
+    when alu_lsl16 =>
+      cc_out(VBIT) <= left(15) xor left(14);
+	 when alu_rol8 | alu_asl8  =>
+      cc_out(VBIT) <= left(7) xor left(6);
+    when alu_tap =>
+      cc_out(VBIT) <= left(VBIT);
+	 when alu_and | alu_ora | alu_eor | alu_com |
+	      alu_st8 | alu_st16 | alu_ld8 | alu_ld16 |
+		   alu_clv =>
+      cc_out(VBIT) <= '0';
+    when alu_sev =>
+	   cc_out(VBIT) <= '1';
+  	 when others =>
+		cc_out(VBIT) <= cc(VBIT);
+    end case;
+
+	 case alu_ctrl is
+	 when alu_tap =>
+      cc_out(XBIT) <= cc(XBIT) and left(XBIT);
+      cc_out(SBIT) <= left(SBIT);
+	 when others =>
+      cc_out(XBIT) <= cc(XBIT) and left(XBIT);
+	   cc_out(SBIT) <= cc(SBIT);
+	 end case;
+
+	 test_alu <= out_alu;
+	 test_cc  <= cc_out;
+end process;
+
+------------------------------------
+--
+-- Detect Edge of NMI interrupt
+--
+------------------------------------
+
+nmi_handler : process( clk, rst, nmi, nmi_ack )
+begin
+  if clk'event and clk='0' then
+    if hold = '1' then
+	   nmi_req <= nmi_req;
+	 else
+    if rst='1' then
+	   nmi_req <= '0';
+    else
+	   if (nmi='1') and (nmi_ack='0') then
+	     nmi_req <= '1';
+	   else
+		  if (nmi='0') and (nmi_ack='1') then
+	       nmi_req <= '0';
+	     else
+	       nmi_req <= nmi_req;
+		  end if;
+		end if;
+	 end if;
+	 end if;
+  end if;
+end process;
+
+------------------------------------
+--
+-- Nmi mux
+--
+------------------------------------
+
+nmi_mux: process( clk, nmi_ctrl, nmi_ack, hold )
+begin
+  if clk'event and clk='0' then
+    if hold = '1' then
+	   nmi_ack <= nmi_ack;
+	 else
+    case nmi_ctrl is
+	 when set_nmi =>
+      nmi_ack <= '1';
+	 when reset_nmi =>
+	   nmi_ack <= '0';
+	 when others =>
+--  when latch_nmi =>
+	   nmi_ack <= nmi_ack;
+	 end case;
+	 end if;
+  end if;
+end process;
+
+------------------------------------
+--
+-- state sequencer
+--
+------------------------------------
+process( state, op_code, cc, ea, irq, nmi_req, nmi_ack, hold, halt )
+  	begin
+		  case state is
+          when reset_state =>        --  released from reset
+			    -- reset the registers
+             op_ctrl    <= reset_op;
+				 acca_ctrl  <= reset_acca;
+				 accb_ctrl  <= reset_accb;
+				 ix_ctrl    <= reset_ix;
+		       sp_ctrl    <= reset_sp;
+		       pc_ctrl    <= reset_pc;
+	 		    ea_ctrl    <= reset_ea;
+				 md_ctrl    <= reset_md;
+				 iv_ctrl    <= reset_iv;
+				 nmi_ctrl   <= reset_nmi;
+				 -- idle the ALU
+             left_ctrl  <= acca_left;
+				 right_ctrl <= zero_right;
+				 alu_ctrl   <= alu_nop;
+             cc_ctrl    <= reset_cc;
+				 -- idle the bus
+				 dout_ctrl  <= md_lo_dout;
+             addr_ctrl  <= idle_ad;
+	 	       next_state <= vect_hi_state;
+
+			 --
+			 -- Jump via interrupt vector
+			 -- iv holds interrupt type
+			 -- fetch PC hi from vector location
+			 --
+          when vect_hi_state =>
+			    -- default the registers
+             op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             sp_ctrl    <= latch_sp;
+             md_ctrl    <= latch_md;
+             ea_ctrl    <= latch_ea;
+             iv_ctrl    <= latch_iv;
+				 -- idle the ALU
+             left_ctrl  <= acca_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+				 -- fetch pc low interrupt vector
+		       pc_ctrl    <= pull_hi_pc;
+             addr_ctrl  <= int_hi_ad;
+             dout_ctrl  <= pc_hi_dout;
+	 	       next_state <= vect_lo_state;
+			 --
+			 -- jump via interrupt vector
+			 -- iv holds vector type
+			 -- fetch PC lo from vector location
+			 --
+          when vect_lo_state =>
+			    -- default the registers
+             op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             sp_ctrl    <= latch_sp;
+             md_ctrl    <= latch_md;
+             ea_ctrl    <= latch_ea;
+             iv_ctrl    <= latch_iv;
+				 -- idle the ALU
+             left_ctrl  <= acca_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+				 -- fetch the vector low byte
+		       pc_ctrl    <= pull_lo_pc;
+             addr_ctrl  <= int_lo_ad;
+             dout_ctrl  <= pc_lo_dout;
+	 	       next_state <= fetch_state;
+
+			 --
+			 -- Here to fetch an instruction
+			 -- PC points to opcode
+			 -- Should service interrupt requests at this point
+			 -- either from the timer
+			 -- or from the external input.
+			 --
+          when fetch_state =>
+			      case op_code(7 downto 4) is
+				   when "0000" |
+	                 "0001" |
+	                 "0010" |  -- branch conditional
+	                 "0011" |
+	                 "0100" |  -- acca single op
+	                 "0101" |  -- accb single op
+	                 "0110" |  -- indexed single op
+	                 "0111" => -- extended single op
+					  -- idle ALU
+                 left_ctrl  <= acca_left;
+					  right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  cc_ctrl    <= latch_cc;
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+
+	            when "1000" | -- acca immediate
+	                 "1001" | -- acca direct
+	                 "1010" | -- acca indexed
+                    "1011" => -- acca extended
+				     case op_code(3 downto 0) is
+					  when "0000" => -- suba
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sub8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0001" => -- cmpa
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sub8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0010" => -- sbca
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sbc;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0011" => -- subd
+					    left_ctrl   <= accd_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sub16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_hi_acca;
+						 accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0100" => -- anda
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_and;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0101" => -- bita
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_and;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0110" => -- ldaa
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ld8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0111" => -- staa
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_st8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1000" => -- eora
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_eor;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1001" => -- adca
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_adc;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1010" => -- oraa
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ora;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1011" => -- adda
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_add8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1100" => -- cpx
+					    left_ctrl   <= ix_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_cpx;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1101" => -- bsr / jsr
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_nop;
+						 cc_ctrl     <= latch_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1110" => -- lds
+					    left_ctrl   <= sp_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ld16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+						 sp_ctrl     <= load_sp;
+					  when "1111" => -- sts
+					    left_ctrl   <= sp_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_st16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when others =>
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_nop;
+						 cc_ctrl     <= latch_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  end case;
+	            when "1100" | -- accb immediate
+	                 "1101" | -- accb direct
+	                 "1110" | -- accb indexed
+                    "1111" => -- accb extended
+				     case op_code(3 downto 0) is
+					  when "0000" => -- subb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sub8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0001" => -- cmpb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sub8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0010" => -- sbcb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sbc;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0011" => -- addd
+					    left_ctrl   <= accd_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_add16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_hi_acca;
+						 accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0100" => -- andb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_and;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0101" => -- bitb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_and;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0110" => -- ldab
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ld8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "0111" => -- stab
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_st8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1000" => -- eorb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_eor;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1001" => -- adcb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_adc;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1010" => -- orab
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ora;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1011" => -- addb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_add8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1100" => -- ldd
+					    left_ctrl   <= accd_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ld16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_hi_acca;
+                   accb_ctrl   <= load_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1101" => -- std
+					    left_ctrl   <= accd_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_st16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when "1110" => -- ldx
+					    left_ctrl   <= ix_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ld16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= load_ix;
+						 sp_ctrl     <= latch_sp;
+					  when "1111" => -- stx
+					    left_ctrl   <= ix_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_st16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  when others =>
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_nop;
+						 cc_ctrl     <= latch_cc;
+					    acca_ctrl   <= latch_acca;
+                   accb_ctrl   <= latch_accb;
+                   ix_ctrl     <= latch_ix;
+                   sp_ctrl     <= latch_sp;
+					  end case;
+	            when others =>
+					  left_ctrl   <= accd_left;
+					  right_ctrl  <= md_right;
+					  alu_ctrl    <= alu_nop;
+					  cc_ctrl     <= latch_cc;
+					  acca_ctrl   <= latch_acca;
+                 accb_ctrl   <= latch_accb;
+                 ix_ctrl     <= latch_ix;
+                 sp_ctrl     <= latch_sp;
+              end case;
+             md_ctrl    <= latch_md;
+				 -- fetch the op code
+			    op_ctrl    <= fetch_op;
+             ea_ctrl    <= reset_ea;
+             addr_ctrl  <= fetch_ad;
+             dout_ctrl  <= md_lo_dout;
+		  	    iv_ctrl    <= latch_iv;
+				 if halt = '1' then
+               pc_ctrl    <= latch_pc;
+				   nmi_ctrl   <= latch_nmi;
+			      next_state <= halt_state;
+				 -- service non maskable interrupts
+			    elsif (nmi_req = '1') and (nmi_ack = '0') then
+               pc_ctrl    <= latch_pc;
+				   nmi_ctrl   <= set_nmi;
+			      next_state <= int_pcl_state;
+				 -- service maskable interrupts
+			    else
+				   --
+					-- nmi request is not cleared until nmi input goes low
+					--
+				   if(nmi_req = '0') and (nmi_ack='1') then
+				     nmi_ctrl <= reset_nmi;
+					else
+					  nmi_ctrl <= latch_nmi;
+					end if;
+					--
+					-- IRQ is level sensitive
+					--
+				   if (irq = '1') and (cc(IBIT) = '0') then
+                 pc_ctrl    <= latch_pc;
+			        next_state <= int_pcl_state;
+               else
+				   -- Advance the PC to fetch next instruction byte
+                 pc_ctrl    <= inc_pc;
+			        next_state <= decode_state;
+               end if;
+				 end if;
+			 --
+			 -- Here to decode instruction
+			 -- and fetch next byte of intruction
+			 -- whether it be necessary or not
+			 --
+          when decode_state =>
+				 -- fetch first byte of address or immediate data
+             ea_ctrl    <= fetch_first_ea;
+             addr_ctrl  <= fetch_ad;
+             dout_ctrl  <= md_lo_dout;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             iv_ctrl    <= latch_iv;
+			    case op_code(7 downto 4) is
+				 when "0000" =>
+				   md_ctrl    <= fetch_first_md;
+               sp_ctrl    <= latch_sp;
+               pc_ctrl    <= latch_pc;
+  	            case op_code(3 downto 0) is
+		         when "0001" => -- nop
+					  left_ctrl  <= accd_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "0100" => -- lsrd
+					  left_ctrl  <= accd_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_lsr16;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= load_hi_acca;
+					  accb_ctrl  <= load_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "0101" => -- lsld
+					  left_ctrl  <= accd_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_lsl16;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= load_hi_acca;
+					  accb_ctrl  <= load_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "0110" => -- tap
+					  left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_tap;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "0111" => -- tpa
+					  left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_tpa;
+                 cc_ctrl    <= latch_cc;
+					  acca_ctrl  <= load_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "1000" => -- inx
+					  left_ctrl  <= ix_left;
+	              right_ctrl <= plus_one_right;
+					  alu_ctrl   <= alu_inx;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= load_ix;
+		         when "1001" => -- dex
+					  left_ctrl  <= ix_left;
+	              right_ctrl <= plus_one_right;
+					  alu_ctrl   <= alu_dex;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= load_ix;
+		         when "1010" => -- clv
+					  left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_clv;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "1011" => -- sev
+					  left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_sev;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "1100" => -- clc
+					  left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_clc;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "1101" => -- sec
+					  left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_sec;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "1110" => -- cli
+					  left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_cli;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+		         when "1111" => -- sei
+					  left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_sei;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+               when others =>
+					  left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= latch_accb;
+					  ix_ctrl    <= latch_ix;
+		         end case;
+					next_state <= fetch_state;
+				 -- acca / accb inherent instructions
+	          when "0001" =>
+				   md_ctrl    <= fetch_first_md;
+               ix_ctrl    <= latch_ix;
+               sp_ctrl    <= latch_sp;
+               pc_ctrl    <= latch_pc;
+					left_ctrl  <= acca_left;
+	            right_ctrl <= accb_right;
+	            case op_code(3 downto 0) is
+		         when "0000" => -- sba
+					  alu_ctrl   <= alu_sub8;
+					  cc_ctrl    <= load_cc;
+					  acca_ctrl  <= load_acca;
+                 accb_ctrl  <= latch_accb;
+		         when "0001" => -- cba
+					  alu_ctrl   <= alu_sub8;
+					  cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+		         when "0110" => -- tab
+					  alu_ctrl   <= alu_st8;
+					  cc_ctrl    <= load_cc;
+					  acca_ctrl  <= latch_acca;
+					  accb_ctrl  <= load_accb;
+		         when "0111" => -- tba
+					  alu_ctrl   <= alu_ld8;
+					  cc_ctrl    <= load_cc;
+					  acca_ctrl  <= load_acca;
+                 accb_ctrl  <= latch_accb;
+		         when "1001" => -- daa
+					  alu_ctrl   <= alu_daa;
+					  cc_ctrl    <= load_cc;
+					  acca_ctrl  <= load_acca;
+                 accb_ctrl  <= latch_accb;
+		         when "1011" => -- aba
+					  alu_ctrl   <= alu_add8;
+					  cc_ctrl    <= load_cc;
+					  acca_ctrl  <= load_acca;
+                 accb_ctrl  <= latch_accb;
+		         when others =>
+					  alu_ctrl   <= alu_nop;
+					  cc_ctrl    <= latch_cc;
+					  acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+		         end case;
+					next_state <= fetch_state;
+	          when "0010" => -- branch conditional
+				   md_ctrl    <= fetch_first_md;
+					acca_ctrl  <= latch_acca;
+               accb_ctrl  <= latch_accb;
+               ix_ctrl    <= latch_ix;
+               sp_ctrl    <= latch_sp;
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+					cc_ctrl    <= latch_cc;
+					-- increment the pc
+               pc_ctrl    <= inc_pc;
+               case op_code(3 downto 0) is
+		         when "0000" => -- bra
+                 next_state <= branch_state;
+		         when "0001" => -- brn
+					  next_state <= fetch_state;
+		         when "0010" => -- bhi
+					  if (cc(CBIT) or cc(ZBIT)) = '0' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "0011" => -- bls
+					  if (cc(CBIT) or cc(ZBIT)) = '1' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "0100" => -- bcc/bhs
+					  if cc(CBIT) = '0' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "0101" => -- bcs/blo
+					  if cc(CBIT) = '1' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "0110" => -- bne
+					  if cc(ZBIT) = '0' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "0111" => -- beq
+					  if cc(ZBIT) = '1' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "1000" => -- bvc
+					  if cc(VBIT) = '0' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "1001" => -- bvs
+					  if cc(VBIT) = '1' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "1010" => -- bpl
+					  if cc(NBIT) = '0' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "1011" => -- bmi
+					  if cc(NBIT) = '1' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "1100" => -- bge
+					  if (cc(NBIT) xor cc(VBIT)) = '0' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "1101" => -- blt
+					  if (cc(NBIT) xor cc(VBIT)) = '1' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "1110" => -- bgt
+					  if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when "1111" => -- ble
+					  if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then
+					    next_state <= branch_state;
+					  else
+					    next_state <= fetch_state;
+					  end if;
+		         when others =>
+					  next_state <= fetch_state;
+		         end case;
+				 --
+				 -- Single byte stack operators
+				 -- Do not advance PC
+				 --
+	          when "0011" =>
+				   md_ctrl    <= fetch_first_md;
+					acca_ctrl  <= latch_acca;
+               accb_ctrl  <= latch_accb;
+               pc_ctrl    <= latch_pc;
+	            case op_code(3 downto 0) is
+		         when "0000" => -- tsx
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= plus_one_right;
+						alu_ctrl   <= alu_add16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= load_ix;
+                  sp_ctrl    <= latch_sp;
+						next_state <= fetch_state;
+		         when "0001" => -- ins
+                  left_ctrl  <= sp_left;
+                  right_ctrl <= plus_one_right;
+                  alu_ctrl   <= alu_add16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+                  sp_ctrl    <= load_sp;
+						next_state <= fetch_state;
+		         when "0010" => -- pula
+                  left_ctrl  <= sp_left;
+                  right_ctrl <= plus_one_right;
+                  alu_ctrl   <= alu_add16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+                  sp_ctrl    <= load_sp;
+						next_state <= pula_state;
+		         when "0011" => -- pulb
+                  left_ctrl  <= sp_left;
+                  right_ctrl <= plus_one_right;
+                  alu_ctrl   <= alu_add16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+                  sp_ctrl    <= load_sp;
+						next_state <= pulb_state;
+		         when "0100" => -- des
+                  -- decrement sp
+                  left_ctrl  <= sp_left;
+                  right_ctrl <= plus_one_right;
+                  alu_ctrl   <= alu_sub16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+                  sp_ctrl    <= load_sp;
+						next_state <= fetch_state;
+		         when "0101" => -- txs
+		            left_ctrl  <= ix_left;
+		            right_ctrl <= plus_one_right;
+						alu_ctrl   <= alu_sub16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+						sp_ctrl    <= load_sp;
+						next_state <= fetch_state;
+		         when "0110" => -- psha
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= zero_right;
+						alu_ctrl   <= alu_nop;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+						sp_ctrl    <= latch_sp;
+						next_state <= psha_state;
+		         when "0111" => -- pshb
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= zero_right;
+						alu_ctrl   <= alu_nop;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+						sp_ctrl    <= latch_sp;
+						next_state <= pshb_state;
+		         when "1000" => -- pulx
+                  left_ctrl  <= sp_left;
+                  right_ctrl <= plus_one_right;
+                  alu_ctrl   <= alu_add16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+                  sp_ctrl    <= load_sp;
+						next_state <= pulx_hi_state;
+		         when "1001" => -- rts
+                  left_ctrl  <= sp_left;
+                  right_ctrl <= plus_one_right;
+                  alu_ctrl   <= alu_add16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+                  sp_ctrl    <= load_sp;
+						next_state <= rts_hi_state;
+		         when "1010" => -- abx
+		            left_ctrl  <= ix_left;
+		            right_ctrl <= accb_right;
+						alu_ctrl   <= alu_add16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= load_ix;
+                  sp_ctrl    <= latch_sp;
+						next_state <= fetch_state;
+		         when "1011" => -- rti
+                  left_ctrl  <= sp_left;
+                  right_ctrl <= plus_one_right;
+                  alu_ctrl   <= alu_add16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+                  sp_ctrl    <= load_sp;
+						next_state <= rti_cc_state;
+		         when "1100" => -- pshx
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= zero_right;
+						alu_ctrl   <= alu_nop;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+						sp_ctrl    <= latch_sp;
+						next_state <= pshx_lo_state;
+		         when "1101" => -- mul
+		            left_ctrl  <= acca_left;
+		            right_ctrl <= accb_right;
+						alu_ctrl   <= alu_add16;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+						sp_ctrl    <= latch_sp;
+						next_state <= mul_state;
+		         when "1110" => -- wai
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= zero_right;
+						alu_ctrl   <= alu_nop;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+						sp_ctrl    <= latch_sp;
+						next_state <= int_pcl_state;
+		         when "1111" => -- swi
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= zero_right;
+						alu_ctrl   <= alu_nop;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+						sp_ctrl    <= latch_sp;
+						next_state <= int_pcl_state;
+		         when others =>
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= zero_right;
+						alu_ctrl   <= alu_nop;
+					   cc_ctrl    <= latch_cc;
+						ix_ctrl    <= latch_ix;
+						sp_ctrl    <= latch_sp;
+						next_state <= fetch_state;
+		         end case;
+				 --
+				 -- Accumulator A Single operand
+				 -- source = Acc A dest = Acc A
+				 -- Do not advance PC
+				 --
+	          when "0100" => -- acca single op
+				   md_ctrl    <= fetch_first_md;
+               accb_ctrl  <= latch_accb;
+               pc_ctrl    <= latch_pc;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+		         left_ctrl  <= acca_left;
+	            case op_code(3 downto 0) is
+		         when "0000" => -- neg
+					  right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_neg;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+ 	            when "0011" => -- com
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_com;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "0100" => -- lsr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_lsr8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "0110" => -- ror
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_ror8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "0111" => -- asr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_asr8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1000" => -- asl
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_asl8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1001" => -- rol
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_rol8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1010" => -- dec
+		           right_ctrl <= plus_one_right;
+					  alu_ctrl   <= alu_dec;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1011" => -- undefined
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  acca_ctrl  <= latch_acca;
+					  cc_ctrl    <= latch_cc;
+		         when "1100" => -- inc
+		           right_ctrl <= plus_one_right;
+					  alu_ctrl   <= alu_inc;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1101" => -- tst
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_st8;
+					  acca_ctrl  <= latch_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1110" => -- jmp
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  acca_ctrl  <= latch_acca;
+					  cc_ctrl    <= latch_cc;
+		         when "1111" => -- clr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_clr;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when others =>
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  acca_ctrl  <= latch_acca;
+					  cc_ctrl    <= latch_cc;
+		         end case;
+				   next_state <= fetch_state;
+				 --
+				 -- single operand acc b
+				 -- Do not advance PC
+				 --
+	          when "0101" =>
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+               pc_ctrl    <= latch_pc;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+		         left_ctrl  <= accb_left;
+	            case op_code(3 downto 0) is
+		         when "0000" => -- neg
+					  right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_neg;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+ 	            when "0011" => -- com
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_com;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "0100" => -- lsr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_lsr8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "0110" => -- ror
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_ror8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "0111" => -- asr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_asr8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1000" => -- asl
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_asl8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1001" => -- rol
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_rol8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1010" => -- dec
+		           right_ctrl <= plus_one_right;
+					  alu_ctrl   <= alu_dec;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1011" => -- undefined
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  accb_ctrl  <= latch_accb;
+					  cc_ctrl    <= latch_cc;
+		         when "1100" => -- inc
+		           right_ctrl <= plus_one_right;
+					  alu_ctrl   <= alu_inc;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1101" => -- tst
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_st8;
+					  accb_ctrl  <= latch_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1110" => -- jmp
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  accb_ctrl  <= latch_accb;
+					  cc_ctrl    <= latch_cc;
+		         when "1111" => -- clr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_clr;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when others =>
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  accb_ctrl  <= latch_accb;
+					  cc_ctrl    <= latch_cc;
+		         end case;
+				   next_state <= fetch_state;
+				 --
+				 -- Single operand indexed
+				 -- Two byte instruction so advance PC
+				 -- EA should hold index offset
+				 --
+	          when "0110" => -- indexed single op
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- increment the pc 
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+					cc_ctrl    <= latch_cc;
+               pc_ctrl    <= inc_pc;
+				   next_state <= indexed_state;
+             --
+				 -- Single operand extended addressing
+				 -- three byte instruction so advance the PC
+				 -- Low order EA holds high order address
+				 --
+	          when "0111" => -- extended single op
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- increment the pc
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+					cc_ctrl    <= latch_cc;
+               pc_ctrl    <= inc_pc;
+				   next_state <= extended_state;
+
+	          when "1000" => -- acca immediate
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+				   -- increment the pc
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+					cc_ctrl    <= latch_cc;
+               pc_ctrl    <= inc_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- subdd #
+					     "1100" | -- cpx #
+					     "1110" => -- lds #
+					  next_state <= immediate16_state;
+					when "1101" => -- bsr
+					  next_state <= bsr_state;
+					when others =>
+				     next_state <= fetch_state;
+               end case;
+
+	          when "1001" => -- acca direct
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- increment the pc
+               pc_ctrl    <= inc_pc;
+					case op_code(3 downto 0) is
+					when "0111" =>  -- staa direct
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_st8;
+					  cc_ctrl    <= latch_cc;
+				     md_ctrl    <= load_md;
+				     next_state <= write8_state;
+					when "1111" => -- sts direct
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_st16;
+					  cc_ctrl    <= latch_cc;
+				     md_ctrl    <= load_md;
+				     next_state <= write16_state;
+					when "1101" => -- jsr direct
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_nop;
+					  cc_ctrl    <= latch_cc;
+				     md_ctrl    <= fetch_first_md;
+					  next_state <= jsr_state;
+					when others =>
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_nop;
+					  cc_ctrl    <= latch_cc;
+				     md_ctrl    <= fetch_first_md;
+				     next_state <= read8_state;
+               end case;
+
+	          when "1010" => -- acca indexed
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- increment the pc
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+					cc_ctrl    <= latch_cc;
+               pc_ctrl    <= inc_pc;
+				   next_state <= indexed_state;
+
+             when "1011" => -- acca extended
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- increment the pc
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+					cc_ctrl    <= latch_cc;
+               pc_ctrl    <= inc_pc;
+				   next_state <= extended_state;
+
+	          when "1100" => -- accb immediate
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- increment the pc
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+					cc_ctrl    <= latch_cc;
+               pc_ctrl    <= inc_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- addd #
+					     "1100" | -- ldd #
+					     "1110" => -- ldx #
+					  next_state <= immediate16_state;
+					when others =>
+				     next_state <= fetch_state;
+               end case;
+
+	          when "1101" => -- accb direct
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- increment the pc
+               pc_ctrl    <= inc_pc;
+					case op_code(3 downto 0) is
+					when "0111" =>  -- stab direct
+                 left_ctrl  <= accb_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_st8;
+					  cc_ctrl    <= latch_cc;
+				     md_ctrl    <= load_md;
+				     next_state <= write8_state;
+					when "1101" => -- std direct
+                 left_ctrl  <= accd_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_st16;
+					  cc_ctrl    <= latch_cc;
+				     md_ctrl    <= load_md;
+					  next_state <= write16_state;
+					when "1111" => -- stx direct
+                 left_ctrl  <= ix_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_st16;
+					  cc_ctrl    <= latch_cc;
+				     md_ctrl    <= load_md;
+				     next_state <= write16_state;
+					when others =>
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_nop;
+					  cc_ctrl    <= latch_cc;
+				     md_ctrl    <= fetch_first_md;
+				     next_state <= read8_state;
+               end case;
+
+	          when "1110" => -- accb indexed
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- increment the pc
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+					cc_ctrl    <= latch_cc;
+               pc_ctrl    <= inc_pc;
+				   next_state <= indexed_state;
+
+             when "1111" => -- accb extended
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- increment the pc
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+					cc_ctrl    <= latch_cc;
+               pc_ctrl    <= inc_pc;
+				   next_state <= extended_state;
+
+	          when others =>
+				   md_ctrl    <= fetch_first_md;
+               acca_ctrl  <= latch_acca;
+					accb_ctrl  <= latch_accb;
+				   ix_ctrl    <= latch_ix;
+				   sp_ctrl    <= latch_sp;
+					-- idle the pc
+               left_ctrl  <= acca_left;
+               right_ctrl <= zero_right;
+               alu_ctrl   <= alu_nop;
+  					cc_ctrl    <= latch_cc;
+               pc_ctrl    <= latch_pc;
+ 		         next_state <= fetch_state;
+             end case;
+
+			  when immediate16_state =>
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             sp_ctrl    <= latch_sp;
+			    op_ctrl    <= latch_op;
+             iv_ctrl    <= latch_iv;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- increment pc
+             left_ctrl  <= acca_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+             pc_ctrl    <= inc_pc;
+				 -- fetch next immediate byte
+			    md_ctrl    <= fetch_next_md;
+             addr_ctrl  <= fetch_ad;
+             dout_ctrl  <= md_lo_dout;
+				 next_state <= fetch_state;
+           --
+			  -- ea holds 8 bit index offet
+			  -- calculate the effective memory address
+			  -- using the alu
+			  --
+           when indexed_state =>
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             sp_ctrl    <= latch_sp;
+             pc_ctrl    <= latch_pc;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+				 -- calculate effective address from index reg
+             -- index offest is not sign extended
+             ea_ctrl    <= add_ix_ea;
+				 -- idle the bus
+             addr_ctrl  <= idle_ad;
+             dout_ctrl  <= md_lo_dout;
+				 -- work out next state
+				 case op_code(7 downto 4) is
+				 when "0110" => -- single op indexed
+               md_ctrl    <= latch_md;
+			      left_ctrl  <= acca_left;
+				   right_ctrl <= zero_right;
+				   alu_ctrl   <= alu_nop;
+               cc_ctrl    <= latch_cc;
+	            case op_code(3 downto 0) is
+		         when "1011" => -- undefined
+					  next_state <= fetch_state;
+		         when "1110" => -- jmp
+					  next_state <= jmp_state;
+		         when others =>
+					  next_state <= read8_state;
+		         end case;
+	          when "1010" => -- acca indexed
+				   case op_code(3 downto 0) is
+					when "0111" =>  -- staa
+			        left_ctrl  <= acca_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st8;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+				     next_state <= write8_state;
+					when "1101" => -- jsr
+			        left_ctrl  <= acca_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= latch_md;
+					  next_state <= jsr_state;
+					when "1111" => -- sts
+			        left_ctrl  <= sp_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st16;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+				     next_state <= write16_state;
+					when others =>
+			        left_ctrl  <= acca_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= latch_md;
+					  next_state <= read8_state;
+					end case;
+	          when "1110" => -- accb indexed
+				   case op_code(3 downto 0) is
+					when "0111" =>  -- stab direct
+			        left_ctrl  <= accb_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st8;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+				     next_state <= write8_state;
+					when "1101" => -- std direct
+			        left_ctrl  <= accd_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st16;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+					  next_state <= write16_state;
+					when "1111" => -- stx direct
+			        left_ctrl  <= ix_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st16;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+				     next_state <= write16_state;
+					when others =>
+			        left_ctrl  <= acca_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= latch_md;
+					  next_state <= read8_state;
+					end case;
+			    when others =>
+               md_ctrl    <= latch_md;
+			      left_ctrl  <= acca_left;
+				   right_ctrl <= zero_right;
+				   alu_ctrl   <= alu_nop;
+               cc_ctrl    <= latch_cc;
+					next_state <= fetch_state;
+			    end case;
+           --
+			  -- ea holds the low byte of the absolute address
+			  -- Move ea low byte into ea high byte
+			  -- load new ea low byte to for absolute 16 bit address
+			  -- advance the program counter
+			  --
+			  when extended_state => -- fetch ea low byte
+               acca_ctrl  <= latch_acca;
+               accb_ctrl  <= latch_accb;
+               ix_ctrl    <= latch_ix;
+               sp_ctrl    <= latch_sp;
+               iv_ctrl    <= latch_iv;
+			      op_ctrl    <= latch_op;
+				   nmi_ctrl   <= latch_nmi;
+					-- increment pc
+               pc_ctrl    <= inc_pc;
+					-- fetch next effective address bytes
+					ea_ctrl    <= fetch_next_ea;
+               addr_ctrl  <= fetch_ad;
+					dout_ctrl  <= md_lo_dout;
+					-- work out the next state
+				 case op_code(7 downto 4) is
+				 when "0111" => -- single op extended
+               md_ctrl    <= latch_md;
+			      left_ctrl  <= acca_left;
+				   right_ctrl <= zero_right;
+				   alu_ctrl   <= alu_nop;
+               cc_ctrl    <= latch_cc;
+	            case op_code(3 downto 0) is
+		         when "1011" => -- undefined
+					  next_state <= fetch_state;
+		         when "1110" => -- jmp
+					  next_state <= jmp_state;
+		         when others =>
+					  next_state <= read8_state;
+		         end case;
+	          when "1011" => -- acca extended
+				   case op_code(3 downto 0) is
+					when "0111" =>  -- staa
+			        left_ctrl  <= acca_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st8;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+				     next_state <= write8_state;
+					when "1101" => -- jsr
+			        left_ctrl  <= acca_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= latch_md;
+					  next_state <= jsr_state;
+					when "1111" => -- sts
+			        left_ctrl  <= sp_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st16;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+				     next_state <= write16_state;
+					when others =>
+			        left_ctrl  <= acca_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= latch_md;
+					  next_state <= read8_state;
+					end case;
+	          when "1111" => -- accb extended
+				   case op_code(3 downto 0) is
+					when "0111" =>  -- stab
+			        left_ctrl  <= accb_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st8;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+				     next_state <= write8_state;
+					when "1101" => -- std
+			        left_ctrl  <= accd_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st16;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+					  next_state <= write16_state;
+					when "1111" => -- stx
+			        left_ctrl  <= ix_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_st16;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+				     next_state <= write16_state;
+					when others =>
+			        left_ctrl  <= acca_left;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= latch_md;
+					  next_state <= read8_state;
+					end case;
+			    when others =>
+               md_ctrl    <= latch_md;
+			      left_ctrl  <= acca_left;
+				   right_ctrl <= zero_right;
+				   alu_ctrl   <= alu_nop;
+               cc_ctrl    <= latch_cc;
+					next_state <= fetch_state;
+			    end case;
+           --
+			  -- here if ea holds low byte (direct page)
+			  -- can enter here from extended addressing
+			  -- read memory location
+			  -- note that reads may be 8 or 16 bits
+			  --
+			  when read8_state => -- read data
+               acca_ctrl  <= latch_acca;
+               accb_ctrl  <= latch_accb;
+               ix_ctrl    <= latch_ix;
+               sp_ctrl    <= latch_sp;
+               pc_ctrl    <= latch_pc;
+               iv_ctrl    <= latch_iv;
+			      op_ctrl    <= latch_op;
+				   nmi_ctrl   <= latch_nmi;
+					--
+               addr_ctrl  <= read_ad;
+					dout_ctrl  <= md_lo_dout;
+					case op_code(7 downto 4) is
+					  when "0110" | "0111" => -- single operand
+ 					      left_ctrl  <= acca_left;
+					      right_ctrl <= zero_right;
+					      alu_ctrl   <= alu_nop;
+                     cc_ctrl    <= latch_cc;
+				         md_ctrl    <= fetch_first_md;
+					      ea_ctrl    <= latch_ea;
+					      next_state <= execute_state;
+
+	              when "1001" | "1010" | "1011" => -- acca
+				       case op_code(3 downto 0) is
+					    when "0011" |  -- subd
+					         "1110" |  -- lds
+					         "1100" => -- cpx
+ 					      left_ctrl  <= acca_left;
+					      right_ctrl <= zero_right;
+					      alu_ctrl   <= alu_nop;
+                     cc_ctrl    <= latch_cc;
+				         md_ctrl    <= fetch_first_md;
+				         -- increment the effective address in case of 16 bit load
+					      ea_ctrl    <= inc_ea;
+					      next_state <= read16_state;
+--					    when "0111" =>   -- staa
+-- 					      left_ctrl  <= acca_left;
+--					      right_ctrl <= zero_right;
+--					      alu_ctrl   <= alu_st8;
+--                     cc_ctrl    <= latch_cc;
+--				         md_ctrl    <= load_md;
+-- 					      ea_ctrl    <= latch_ea;
+--					      next_state <= write8_state;
+--					    when "1101" => -- jsr
+--			            left_ctrl  <= acca_left;
+--				         right_ctrl <= zero_right;
+--				         alu_ctrl   <= alu_nop;
+--                     cc_ctrl    <= latch_cc;
+--                     md_ctrl    <= latch_md;
+-- 					      ea_ctrl    <= latch_ea;
+--					      next_state <= jsr_state;
+--					    when "1111" =>  -- sts
+-- 					      left_ctrl  <= sp_left;
+--					      right_ctrl <= zero_right;
+--					      alu_ctrl   <= alu_st16;
+--                     cc_ctrl    <= latch_cc;
+--				         md_ctrl    <= load_md;
+--					      ea_ctrl    <= latch_ea;
+--					      next_state <= write16_state;
+					    when others =>
+ 					      left_ctrl  <= acca_left;
+					      right_ctrl <= zero_right;
+					      alu_ctrl   <= alu_nop;
+                     cc_ctrl    <= latch_cc;
+				         md_ctrl    <= fetch_first_md;
+ 					      ea_ctrl    <= latch_ea;
+					      next_state <= fetch_state;
+					    end case;
+
+	              when "1101" | "1110" | "1111" => -- accb
+				       case op_code(3 downto 0) is
+					    when "0011" |  -- addd
+					         "1100" |  -- ldd
+					         "1110" => -- ldx
+ 					      left_ctrl  <= acca_left;
+					      right_ctrl <= zero_right;
+					      alu_ctrl   <= alu_nop;
+                     cc_ctrl    <= latch_cc;
+				         md_ctrl    <= fetch_first_md;
+				         -- increment the effective address in case of 16 bit load
+					      ea_ctrl    <= inc_ea;
+					      next_state <= read16_state;
+--					    when "0111" =>   -- stab
+-- 					      left_ctrl  <= accb_left;
+--					      right_ctrl <= zero_right;
+--					      alu_ctrl   <= alu_st8;
+--                     cc_ctrl    <= latch_cc;
+--				         md_ctrl    <= load_md;
+--					      ea_ctrl    <= latch_ea;
+--					      next_state <= write8_state;
+--					    when "1101" => -- std
+--			            left_ctrl  <= accd_left;
+--				         right_ctrl <= zero_right;
+--				         alu_ctrl   <= alu_st16;
+--                     cc_ctrl    <= latch_cc;
+--                     md_ctrl    <= load_md;
+-- 					      ea_ctrl    <= latch_ea;
+--					      next_state <= write16_state;
+--					    when "1111" =>  -- stx
+-- 					      left_ctrl  <= ix_left;
+--					      right_ctrl <= zero_right;
+--					      alu_ctrl   <= alu_st16;
+--                     cc_ctrl    <= latch_cc;
+--				         md_ctrl    <= load_md;
+--					      ea_ctrl    <= latch_ea;
+--					      next_state <= write16_state;
+					    when others =>
+ 					      left_ctrl  <= acca_left;
+					      right_ctrl <= zero_right;
+					      alu_ctrl   <= alu_nop;
+                     cc_ctrl    <= latch_cc;
+				         md_ctrl    <= fetch_first_md;
+					      ea_ctrl    <= latch_ea;
+					      next_state <= execute_state;
+					    end case;
+					  when others =>
+ 					    left_ctrl  <= acca_left;
+					    right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_nop;
+                   cc_ctrl    <= latch_cc;
+				       md_ctrl    <= fetch_first_md;
+					    ea_ctrl    <= latch_ea;
+					    next_state <= fetch_state;
+					  end case;
+
+			   when read16_state => -- read second data byte from ea
+                 -- default
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+					  -- idle the effective address
+                 ea_ctrl    <= latch_ea;
+					  -- read the low byte of the 16 bit data
+				     md_ctrl    <= fetch_next_md;
+                 addr_ctrl  <= read_ad;
+                 dout_ctrl  <= md_lo_dout;
+					  next_state <= fetch_state;
+           --
+			  -- 16 bit Write state
+			  -- write high byte of ALU output.
+			  -- EA hold address of memory to write to
+			  -- Advance the effective address in ALU
+			  --
+			  when write16_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             sp_ctrl    <= latch_sp;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+				 -- increment the effective address
+				 left_ctrl  <= acca_left;
+				 right_ctrl <= zero_right;
+				 alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+			    ea_ctrl    <= inc_ea;
+ 				 -- write the ALU hi byte to ea
+             addr_ctrl  <= write_ad;
+             dout_ctrl  <= md_hi_dout;
+				 next_state <= write8_state;
+           --
+			  -- 8 bit write
+			  -- Write low 8 bits of ALU output
+			  --
+			  when write8_state =>
+				 -- default registers
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             sp_ctrl    <= latch_sp;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- idle the ALU
+             left_ctrl  <= acca_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+				 -- write ALU low byte output
+             addr_ctrl  <= write_ad;
+             dout_ctrl  <= md_lo_dout;
+				 next_state <= fetch_state;
+
+				when jmp_state =>
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 md_ctrl    <= latch_md;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- load PC with effective address
+                 left_ctrl  <= acca_left;
+					  right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+					  pc_ctrl    <= load_ea_pc;
+					  -- idle the bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+                 next_state <= fetch_state;
+
+				when jsr_state => -- JSR
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 md_ctrl    <= latch_md;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+                 -- decrement sp
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= plus_one_right;
+                 alu_ctrl   <= alu_sub16;
+                 cc_ctrl    <= latch_cc;
+                 sp_ctrl    <= load_sp;
+					  -- write pc low
+                 addr_ctrl  <= push_ad;
+					  dout_ctrl  <= pc_lo_dout; 
+                 next_state <= jsr1_state;
+
+				when jsr1_state => -- JSR
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 pc_ctrl    <= latch_pc;
+                 md_ctrl    <= latch_md;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+                 -- decrement sp
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= plus_one_right;
+                 alu_ctrl   <= alu_sub16;
+                 cc_ctrl    <= latch_cc;
+                 sp_ctrl    <= load_sp;
+					  -- write pc hi
+                 addr_ctrl  <= push_ad;
+					  dout_ctrl  <= pc_hi_dout; 
+                 next_state <= jmp_state;
+
+				when branch_state => -- Bcc
+				     -- default registers
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 md_ctrl    <= latch_md;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- calculate signed branch
+					  left_ctrl  <= acca_left;
+					  right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+					  pc_ctrl    <= add_ea_pc;
+					  -- idle the bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+                 next_state <= fetch_state;
+
+				when bsr_state => -- BSR
+				     -- default
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 pc_ctrl    <= latch_pc;
+                 md_ctrl    <= latch_md;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+                 -- decrement sp
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= plus_one_right;
+                 alu_ctrl   <= alu_sub16;
+                 cc_ctrl    <= latch_cc;
+                 sp_ctrl    <= load_sp;
+					  -- write pc low
+                 addr_ctrl  <= push_ad;
+					  dout_ctrl  <= pc_lo_dout; 
+                 next_state <= bsr1_state;
+
+				when bsr1_state => -- BSR
+				     -- default registers
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 pc_ctrl    <= latch_pc;
+                 md_ctrl    <= latch_md;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+                 -- decrement sp
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= plus_one_right;
+                 alu_ctrl   <= alu_sub16;
+                 cc_ctrl    <= latch_cc;
+                 sp_ctrl    <= load_sp;
+					  -- write pc hi
+                 addr_ctrl  <= push_ad;
+					  dout_ctrl  <= pc_hi_dout; 
+                 next_state <= branch_state;
+
+				 when rts_hi_state => -- RTS
+				     -- default
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 pc_ctrl    <= latch_pc;
+                 md_ctrl    <= latch_md;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- increment the sp
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= plus_one_right;
+                 alu_ctrl   <= alu_add16;
+                 cc_ctrl    <= latch_cc;
+                 sp_ctrl    <= load_sp;
+                 -- read pc hi
+					  pc_ctrl    <= pull_hi_pc;
+                 addr_ctrl  <= pull_ad;
+                 dout_ctrl  <= pc_hi_dout;
+                 next_state <= rts_lo_state;
+
+				when rts_lo_state => -- RTS1
+				     -- default
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 md_ctrl    <= latch_md;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- idle the ALU
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+					  -- read pc low
+					  pc_ctrl    <= pull_lo_pc;
+                 addr_ctrl  <= pull_ad;
+                 dout_ctrl  <= pc_lo_dout;
+                 next_state <= fetch_state;
+
+				 when mul_state =>
+				     -- default
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- move acca to md
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_st16;
+                 cc_ctrl    <= latch_cc;
+                 md_ctrl    <= load_md;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= mulea_state;
+
+				 when mulea_state =>
+				     -- default
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 md_ctrl    <= latch_md;
+					  -- idle ALU
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_nop;
+                 cc_ctrl    <= latch_cc;
+					  -- move accb to ea
+                 ea_ctrl    <= load_accb_ea;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= muld_state;
+
+				 when muld_state =>
+				     -- default
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+                 md_ctrl    <= latch_md;
+					  -- clear accd
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_ld8;
+                 cc_ctrl    <= latch_cc;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= mul0_state;
+
+				 when mul0_state =>
+				     -- default
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- if bit 0 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+                 right_ctrl <= md_right;
+                 alu_ctrl   <= alu_add16;
+					  if ea(0) = '1' then
+                   cc_ctrl    <= load_cc;
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  else
+                   cc_ctrl    <= latch_cc;
+                   acca_ctrl  <= latch_acca;
+                   accb_ctrl  <= latch_accb;
+					  end if;
+                 md_ctrl    <= shiftl_md;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= mul1_state;
+
+				 when mul1_state =>
+				     -- default
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- if bit 1 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+                 right_ctrl <= md_right;
+                 alu_ctrl   <= alu_add16;
+					  if ea(1) = '1' then
+                   cc_ctrl    <= load_cc;
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  else
+                   cc_ctrl    <= latch_cc;
+                   acca_ctrl  <= latch_acca;
+                   accb_ctrl  <= latch_accb;
+					  end if;
+                 md_ctrl    <= shiftl_md;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= mul2_state;
+
+				 when mul2_state =>
+				     -- default
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- if bit 2 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+                 right_ctrl <= md_right;
+                 alu_ctrl   <= alu_add16;
+					  if ea(2) = '1' then
+                   cc_ctrl    <= load_cc;
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  else
+                   cc_ctrl    <= latch_cc;
+                   acca_ctrl  <= latch_acca;
+                   accb_ctrl  <= latch_accb;
+					  end if;
+                 md_ctrl    <= shiftl_md;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= mul3_state;
+
+				 when mul3_state =>
+				     -- default
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- if bit 3 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+                 right_ctrl <= md_right;
+                 alu_ctrl   <= alu_add16;
+					  if ea(3) = '1' then
+                   cc_ctrl    <= load_cc;
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  else
+                   cc_ctrl    <= latch_cc;
+                   acca_ctrl  <= latch_acca;
+                   accb_ctrl  <= latch_accb;
+					  end if;
+                 md_ctrl    <= shiftl_md;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= mul4_state;
+
+				 when mul4_state =>
+				     -- default
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- if bit 4 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+                 right_ctrl <= md_right;
+                 alu_ctrl   <= alu_add16;
+					  if ea(4) = '1' then
+                   cc_ctrl    <= load_cc;
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  else
+                   cc_ctrl    <= latch_cc;
+                   acca_ctrl  <= latch_acca;
+                   accb_ctrl  <= latch_accb;
+					  end if;
+                 md_ctrl    <= shiftl_md;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= mul5_state;
+
+				 when mul5_state =>
+				     -- default
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- if bit 5 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+                 right_ctrl <= md_right;
+                 alu_ctrl   <= alu_add16;
+					  if ea(5) = '1' then
+                   cc_ctrl    <= load_cc;
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  else
+                   cc_ctrl    <= latch_cc;
+                   acca_ctrl  <= latch_acca;
+                   accb_ctrl  <= latch_accb;
+					  end if;
+                 md_ctrl    <= shiftl_md;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= mul6_state;
+
+				 when mul6_state =>
+				     -- default
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- if bit 6 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+                 right_ctrl <= md_right;
+                 alu_ctrl   <= alu_add16;
+					  if ea(6) = '1' then
+                   cc_ctrl    <= load_cc;
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  else
+                   cc_ctrl    <= latch_cc;
+                   acca_ctrl  <= latch_acca;
+                   accb_ctrl  <= latch_accb;
+					  end if;
+                 md_ctrl    <= shiftl_md;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= mul7_state;
+
+				 when mul7_state =>
+				     -- default
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+			        op_ctrl    <= latch_op;
+				     nmi_ctrl   <= latch_nmi;
+                 ea_ctrl    <= latch_ea;
+					  -- if bit 7 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+                 right_ctrl <= md_right;
+                 alu_ctrl   <= alu_add16;
+					  if ea(7) = '1' then
+                   cc_ctrl    <= load_cc;
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  else
+                   cc_ctrl    <= latch_cc;
+                   acca_ctrl  <= latch_acca;
+                   accb_ctrl  <= latch_accb;
+					  end if;
+                 md_ctrl    <= shiftl_md;
+					  -- idle bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+				     next_state <= fetch_state;
+
+			    when execute_state => -- execute single operand instruction
+				   -- default
+			      op_ctrl    <= latch_op;
+				   nmi_ctrl   <= latch_nmi;
+			      case op_code(7 downto 4) is
+	            when "0110" | -- indexed single op
+	                 "0111" => -- extended single op
+                 acca_ctrl  <= latch_acca;
+                 accb_ctrl  <= latch_accb;
+                 ix_ctrl    <= latch_ix;
+                 sp_ctrl    <= latch_sp;
+                 pc_ctrl    <= latch_pc;
+                 iv_ctrl    <= latch_iv;
+                 ea_ctrl    <= latch_ea;
+					  -- idle the bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+                 left_ctrl  <= md_left;
+	              case op_code(3 downto 0) is
+		           when "0000" => -- neg
+					    right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_neg;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+ 	              when "0011" => -- com
+		             right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_com;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+		           when "0100" => -- lsr
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_lsr8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+		           when "0110" => -- ror
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_ror8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+		           when "0111" => -- asr
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_asr8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+		           when "1000" => -- asl
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_asl8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+		           when "1001" => -- rol
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_rol8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+		           when "1010" => -- dec
+		             right_ctrl <= plus_one_right;
+					    alu_ctrl   <= alu_dec;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+		           when "1011" => -- undefined
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_nop;
+					    cc_ctrl    <= latch_cc;
+				       md_ctrl    <= latch_md;
+				       next_state <= fetch_state;
+		           when "1100" => -- inc
+		             right_ctrl <= plus_one_right;
+					    alu_ctrl   <= alu_inc;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+		           when "1101" => -- tst
+		             right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_st8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= latch_md;
+				       next_state <= fetch_state;
+		           when "1110" => -- jmp
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_nop;
+					    cc_ctrl    <= latch_cc;
+				       md_ctrl    <= latch_md;
+				       next_state <= fetch_state;
+		           when "1111" => -- clr
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_clr;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= write8_state;
+		           when others =>
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_nop;
+					    cc_ctrl    <= latch_cc;
+				       md_ctrl    <= latch_md;
+				       next_state <= fetch_state;
+		           end case;
+
+	            when others =>
+					  left_ctrl   <= accd_left;
+					  right_ctrl  <= md_right;
+					  alu_ctrl    <= alu_nop;
+					  cc_ctrl     <= latch_cc;
+					  acca_ctrl   <= latch_acca;
+                 accb_ctrl   <= latch_accb;
+                 ix_ctrl     <= latch_ix;
+                 sp_ctrl     <= latch_sp;
+                 pc_ctrl     <= latch_pc;
+                 md_ctrl     <= latch_md;
+                 iv_ctrl     <= latch_iv;
+                 ea_ctrl     <= latch_ea;
+					  -- idle the bus
+                 addr_ctrl  <= idle_ad;
+                 dout_ctrl  <= md_lo_dout;
+		           next_state <= fetch_state;
+              end case;
+
+			  when psha_state =>
+				 -- default registers
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write acca
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= acca_dout; 
+             next_state <= fetch_state;
+
+			  when pula_state =>
+				 -- default registers
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- idle sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= latch_sp;
+				 -- read acca
+				 acca_ctrl  <= pull_acca;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= acca_dout;
+             next_state <= fetch_state;
+
+			  when pshb_state =>
+				 -- default registers
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write accb
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= accb_dout; 
+             next_state <= fetch_state;
+
+			  when pulb_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- idle sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= latch_sp;
+				 -- read accb
+				 accb_ctrl  <= pull_accb;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= accb_dout;
+             next_state <= fetch_state;
+
+			  when pshx_lo_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             sp_ctrl    <= latch_sp;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write ix low
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= ix_lo_dout; 
+             next_state <= pshx_hi_state;
+
+			  when pshx_hi_state =>
+				 -- default registers
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write ix hi
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= ix_hi_dout; 
+             next_state <= fetch_state;
+
+		  	  when pulx_hi_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_add16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- pull ix hi
+				 ix_ctrl    <= pull_hi_ix;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= ix_hi_dout;
+             next_state <= pulx_lo_state;
+
+		  	  when pulx_lo_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- idle sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= latch_sp;
+				 -- read ix low
+				 ix_ctrl    <= pull_lo_ix;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= ix_lo_dout;
+             next_state <= fetch_state;
+
+           --
+			  -- return from interrupt
+			  -- enter here from bogus interrupts
+			  --
+			  when rti_state =>
+				 -- default registers
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- idle address bus
+             cc_ctrl    <= latch_cc;
+             addr_ctrl  <= idle_ad;
+             dout_ctrl  <= cc_dout;
+             next_state <= rti_cc_state;
+
+			  when rti_cc_state =>
+				 -- default registers
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read cc
+             cc_ctrl    <= pull_cc;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= cc_dout;
+             next_state <= rti_accb_state;
+
+			  when rti_accb_state =>
+				 -- default registers
+             acca_ctrl  <= latch_acca;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_add16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- read accb
+				 accb_ctrl  <= pull_accb;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= accb_dout;
+             next_state <= rti_acca_state;
+
+			  when rti_acca_state =>
+				 -- default registers
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_add16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- read acca
+				 acca_ctrl  <= pull_acca;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= acca_dout;
+             next_state <= rti_ixh_state;
+
+			  when rti_ixh_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_add16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- read ix hi
+				 ix_ctrl    <= pull_hi_ix;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= ix_hi_dout;
+             next_state <= rti_ixl_state;
+
+			  when rti_ixl_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_add16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- read ix low
+				 ix_ctrl    <= pull_lo_ix;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= ix_lo_dout;
+             next_state <= rti_pch_state;
+
+			  when rti_pch_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+	          -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_add16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- pull pc hi
+				 pc_ctrl    <= pull_hi_pc;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= pc_hi_dout;
+             next_state <= rti_pcl_state;
+
+			  when rti_pcl_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- idle sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= latch_sp;
+	          -- pull pc low
+				 pc_ctrl    <= pull_lo_pc;
+             addr_ctrl  <= pull_ad;
+             dout_ctrl  <= pc_lo_dout;
+             next_state <= fetch_state;
+
+			  --
+			  -- here on interrupt
+			  -- iv register hold interrupt type
+			  --
+			  when int_pcl_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write pc low
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= pc_lo_dout; 
+             next_state <= int_pch_state;
+
+			  when int_pch_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write pc hi
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= pc_hi_dout; 
+             next_state <= int_ixl_state;
+
+			  when int_ixl_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write ix low
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= ix_lo_dout; 
+             next_state <= int_ixh_state;
+
+			  when int_ixh_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write ix hi
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= ix_hi_dout; 
+             next_state <= int_acca_state;
+
+			  when int_acca_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write acca
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= acca_dout; 
+             next_state <= int_accb_state;
+
+
+			  when int_accb_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write accb
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= accb_dout; 
+             next_state <= int_cc_state;
+
+			  when int_cc_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_sub16;
+             cc_ctrl    <= latch_cc;
+             sp_ctrl    <= load_sp;
+				 -- write cc
+             addr_ctrl  <= push_ad;
+			    dout_ctrl  <= cc_dout;
+				 nmi_ctrl   <= latch_nmi;
+				 --
+				 -- nmi is edge triggered
+				 -- nmi_req is cleared when nmi goes low.
+				 --
+			    if nmi_req = '1' then
+		  			iv_ctrl    <= nmi_iv;
+			      next_state <= vect_hi_state;
+			    else
+					--
+					-- IRQ is level sensitive
+					--
+				   if (irq = '1') and (cc(IBIT) = '0') then
+		  			  iv_ctrl    <= irq_iv;
+			        next_state <= int_mask_state;
+               else
+					  case op_code is
+					  when "00111110" => -- WAI (wait for interrupt)
+                   iv_ctrl    <= latch_iv;
+	                next_state <= int_wai_state;
+					  when "00111111" => -- SWI (Software interrupt)
+                   iv_ctrl    <= swi_iv;
+	                next_state <= vect_hi_state;
+					  when others => -- bogus interrupt (return)
+                   iv_ctrl    <= latch_iv;
+	                next_state <= rti_state;
+					  end case;
+					end if;
+				 end if;
+
+			  when int_wai_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+			    op_ctrl    <= latch_op;
+             ea_ctrl    <= latch_ea;
+             -- enable interrupts
+             left_ctrl  <= sp_left;
+             right_ctrl <= plus_one_right;
+             alu_ctrl   <= alu_cli;
+             cc_ctrl    <= load_cc;
+             sp_ctrl    <= latch_sp;
+				 -- idle bus
+             addr_ctrl  <= idle_ad;
+			    dout_ctrl  <= cc_dout; 
+			    if (nmi_req = '1') and (nmi_ack='0') then
+		  			iv_ctrl    <= nmi_iv;
+				   nmi_ctrl   <= set_nmi;
+			      next_state <= vect_hi_state;
+			    else
+				   --
+					-- nmi request is not cleared until nmi input goes low
+					--
+				   if (nmi_req = '0') and (nmi_ack='1') then
+				     nmi_ctrl <= reset_nmi;
+					else
+					  nmi_ctrl <= latch_nmi;
+					end if;
+					--
+					-- IRQ is level sensitive
+					--
+				   if (irq = '1') and (cc(IBIT) = '0') then
+		  			  iv_ctrl    <= irq_iv;
+			        next_state <= int_mask_state;
+               else
+                 iv_ctrl    <= latch_iv;
+	              next_state <= int_wai_state;
+					end if;
+				 end if;
+
+			  when int_mask_state =>
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- Mask IRQ
+             left_ctrl  <= sp_left;
+             right_ctrl <= zero_right;
+			    alu_ctrl   <= alu_sei;
+				 cc_ctrl    <= load_cc;
+             sp_ctrl    <= latch_sp;
+				 -- idle bus cycle
+             addr_ctrl  <= idle_ad;
+             dout_ctrl  <= md_lo_dout;
+             next_state <= vect_hi_state;
+
+			  when halt_state => -- halt CPU.
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             sp_ctrl    <= latch_sp;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- do nothing in ALU
+             left_ctrl  <= acca_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+				 -- idle bus cycle
+             addr_ctrl  <= idle_ad;
+             dout_ctrl  <= md_lo_dout;
+				 if halt = '1' then
+			      next_state <= halt_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when others => -- error state halt on undefine states
+				 -- default
+             acca_ctrl  <= latch_acca;
+             accb_ctrl  <= latch_accb;
+             ix_ctrl    <= latch_ix;
+             sp_ctrl    <= latch_sp;
+             pc_ctrl    <= latch_pc;
+             md_ctrl    <= latch_md;
+             iv_ctrl    <= latch_iv;
+			    op_ctrl    <= latch_op;
+				 nmi_ctrl   <= latch_nmi;
+             ea_ctrl    <= latch_ea;
+				 -- do nothing in ALU
+             left_ctrl  <= acca_left;
+             right_ctrl <= zero_right;
+             alu_ctrl   <= alu_nop;
+             cc_ctrl    <= latch_cc;
+				 -- idle bus cycle
+             addr_ctrl  <= idle_ad;
+             dout_ctrl  <= md_lo_dout;
+				 next_state <= error_state;
+		  end case;
+end process;
+
+--------------------------------
+--
+-- state machine
+--
+--------------------------------
+
+change_state: process( clk, rst, state, hold )
+begin
+  if clk'event and clk = '0' then
+    if rst = '1' then
+ 	   state <= reset_state;
+    elsif hold = '1' then
+	   state <= state;
+	 else
+      state <= next_state;
+	 end if;
+  end if;
+end process;
+	-- output
+	
+end CPU_ARCH;
+	
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/dpram.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..672d33d3
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/dpram.vhd	
@@ -0,0 +1,131 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram IS
+	GENERIC
+	(
+		init_file			: string := "";
+		--numwords_a		: natural;
+		widthad_a			: natural;
+		width_a				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED";
+    outdata_reg_b : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(width_a-1 DOWNTO 0);
+	q_b    <= sub_wire1(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		numwords_b => 2**widthad_a,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		outdata_reg_b => outdata_reg_a,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => widthad_a,
+		widthad_b => widthad_a,
+		width_a => width_a,
+		width_b => width_a,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/dprom_2r.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/dprom_2r.vhd
new file mode 100644
index 00000000..a17e0e58
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/dprom_2r.vhd	
@@ -0,0 +1,135 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dprom_2r IS
+	GENERIC
+	(
+		INIT_FILE			: string := "";
+		--NUMWORDS_A		: natural;
+		WIDTHAD_A			: natural;
+		WIDTH_A				: natural := 8;
+		--NUMWORDS_B		: natural;
+		WIDTHAD_B			: natural;
+		WIDTH_B				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED";
+    outdata_reg_b : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address_a		: in std_logic_vector (WIDTHAD_A-1 downto 0);
+		address_b		: in std_logic_vector (WIDTHAD_B-1 downto 0);
+		clock				: in std_logic ;
+		q_a					: out std_logic_vector (WIDTH_A-1 downto 0);
+		q_b					: out std_logic_vector (WIDTH_B-1 downto 0)
+	);
+END dprom_2r;
+
+
+ARCHITECTURE SYN OF dprom_2r IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3_bv	: BIT_VECTOR (WIDTH_A-1 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (WIDTH_B-1 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		init_file_layout		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		ram_block_type		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (WIDTHAD_A-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (WIDTHAD_B-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire2    <= '0';
+	sub_wire3_bv(WIDTH_A-1 DOWNTO 0) <= (others => '0');
+	sub_wire3    <= To_stdlogicvector(sub_wire3_bv);
+	sub_wire4_bv(WIDTH_B-1 DOWNTO 0) <= (others => '0');
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	q_a    <= sub_wire0(WIDTH_A-1 DOWNTO 0);
+	q_b    <= sub_wire1(WIDTH_B-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK0",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK0",
+		init_file => INIT_FILE,
+		init_file_layout => "PORT_A",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2**WIDTHAD_A,
+		numwords_b => 2**WIDTHAD_B,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		outdata_reg_b => outdata_reg_b,
+		power_up_uninitialized => "FALSE",
+		ram_block_type => "M9K",
+		widthad_a => WIDTHAD_A,
+		widthad_b => WIDTHAD_B,
+		width_a => WIDTH_A,
+		width_b => WIDTH_B,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK0"
+	)
+	PORT MAP (
+		wren_a => sub_wire2,
+		wren_b => sub_wire2,
+		clock0 => clock,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => sub_wire3,
+		data_b => sub_wire4,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+END SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/input_mapper.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/input_mapper.vhd
new file mode 100644
index 00000000..8fc031ba
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/input_mapper.vhd	
@@ -0,0 +1,99 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+
+entity inputmapper is
+	generic
+	(
+    NUM_DIPS    : integer := 8;
+		NUM_INPUTS  : integer := 2
+	);
+	port
+	(
+    clk       : in std_logic;
+    rst_n     : in std_logic;
+    jamma			: in from_JAMMA_t;
+
+    -- user outputs
+    dips			: in	std_logic_vector(NUM_DIPS-1 downto 0);
+    inputs		: out from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1)
+	);
+end inputmapper;
+
+architecture SYN of inputmapper is
+
+begin
+
+  process (clk, rst_n)
+    variable jamma_v	: from_MAPPED_INPUTS_t(0 to NUM_INPUTS-1);
+  begin
+
+       -- note: all inputs are active LOW
+
+      if rst_n = '0' then
+        for i in 0 to NUM_INPUTS-1 loop
+          jamma_v(i).d := (others =>'1');
+        end loop;
+        
+      elsif rising_edge (clk) then
+
+        -- handle JAMMA inputs
+        jamma_v(0).d(0) := jamma.p(1).start;
+        jamma_v(0).d(1) := jamma.p(2).start;
+        jamma_v(0).d(2) := '1';--jamma.service;
+        jamma_v(0).d(3) := jamma.coin(1);
+		  --unused
+		  --unused
+		  --unused
+		  --unused
+		  
+        jamma_v(1).d(0) := jamma.p(1).right;
+        jamma_v(1).d(1) := jamma.p(1).left;
+        jamma_v(1).d(2) := jamma.p(1).down;
+        jamma_v(1).d(3) := jamma.p(1).up;
+		  --unused
+        jamma_v(1).d(5) := jamma.p(1).button(2);
+		  --unused
+        jamma_v(1).d(7) := jamma.p(1).button(1);
+		  
+		  jamma_v(2).d(0) := jamma.p(2).right;
+        jamma_v(2).d(1) := jamma.p(2).left;
+        jamma_v(2).d(2) := jamma.p(2).down;
+        jamma_v(2).d(3) := jamma.p(2).up;
+		  jamma_v(2).d(4) := jamma.coin(2);
+        jamma_v(2).d(5) := jamma.p(2).button(2);
+		  --unused
+        jamma_v(2).d(7) := jamma.p(2).button(1);
+      end if; -- rising_edge (clk)
+
+      -- assign outputs
+      inputs(0).d <= jamma_v(0).d;
+      inputs(1).d <= jamma_v(1).d;
+      inputs(2).d <= jamma_v(2).d;
+      inputs(3).d <= "11111110";  -- 1C/1C, 10/30/50K, 3 lives
+      inputs(4).d <= jamma.service & "1111100";
+--	PORT_START("DSW2")
+--	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW2:1")
+--	PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
+--	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+--	PORT_DIPNAME( 0x02, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:2")
+--	PORT_DIPSETTING(    0x00, DEF_STR( Upright ) )
+--	PORT_DIPSETTING(    0x02, DEF_STR( Cocktail ) )
+--	PORT_DIPNAME( 0x04, 0x04, "Coin Mode" ) PORT_DIPLOCATION("SW2:3")
+--	PORT_DIPSETTING(    0x04, "Mode 1" )
+--	PORT_DIPSETTING(    0x00, "Mode 2" )
+--	/* Bits 4,5,6 are different in each game, see below */
+--	PORT_DIPUNUSED_DIPLOC( 0x38, 0x38, "SW2:4,5,6" )
+--	PORT_DIPNAME( 0x40, 0x40, "Invulnerability (Cheat)" ) PORT_DIPLOCATION("SW2:7")
+--	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
+--	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+--	PORT_SERVICE_DIPLOC( 0x80, IP_ACTIVE_LOW, "SW2:8" )
+
+  end process;
+
+end architecture SYN;
+
+
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace.vhd
new file mode 100644
index 00000000..112c724a
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace.vhd	
@@ -0,0 +1,146 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+--use work.project_pkg.all;
+
+entity PACE is
+  port
+  (
+  	-- clocks and resets
+    clkrst_i        : in from_CLKRST_t;
+
+    -- misc I/O
+    buttons_i       : in from_BUTTONS_t;
+    switches_i      : in from_SWITCHES_t;
+    leds_o          : out to_LEDS_t;
+
+    -- controller inputs
+    inputs_i        : in from_INPUTS_t;
+
+    -- video
+    video_i         : in from_VIDEO_t;
+    video_o         : out to_VIDEO_t;
+	 sound_data_o    : out std_logic_vector(7 downto 0);
+
+    -- custom i/o
+ --   project_i       : in from_PROJECT_IO_t;
+ --   project_o       : out to_PROJECT_IO_t;
+    platform_i      : in from_PLATFORM_IO_t;
+    platform_o      : out to_PLATFORM_IO_t;
+	 cpu_rom_addr          : out std_logic_vector(14 downto 0);
+	 cpu_rom_do          : in std_logic_vector(7 downto 0)
+  );
+end entity PACE;
+
+architecture SYN of PACE is
+
+	constant CLK_1US_COUNTS : integer := 
+    integer(27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY);
+
+	signal mapped_inputs		: from_MAPPED_INPUTS_t(0 to PACE_INPUTS_NUM_BYTES-1);
+
+  signal to_tilemap_ctl   : to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+  signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+
+  signal to_bitmap_ctl    : to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+  signal from_bitmap_ctl  : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+
+  signal to_sprite_reg    : to_SPRITE_REG_t;
+  signal to_sprite_ctl    : to_SPRITE_CTL_t;
+  signal from_sprite_ctl  : from_SPRITE_CTL_t;
+	signal spr0_hit					: std_logic;
+
+  signal to_graphics      : to_GRAPHICS_t;
+	signal from_graphics    : from_GRAPHICS_t;
+
+begin
+
+	inputs_inst : entity work.inputs
+		generic map
+		(
+      NUM_DIPS        => PACE_NUM_SWITCHES,
+			NUM_INPUTS	    => PACE_INPUTS_NUM_BYTES,
+			CLK_1US_DIV	    => CLK_1US_COUNTS
+		)
+	  port map
+	  (
+	    clk     	      => clkrst_i.clk(0),
+	    reset   	      => clkrst_i.rst(0),
+			jamma			      => inputs_i.jamma_n,
+	
+	    dips     	      => switches_i,
+	    inputs		      => mapped_inputs
+	  );
+
+  platform_inst : entity work.platform
+    generic map
+    (
+      NUM_INPUT_BYTES => PACE_INPUTS_NUM_BYTES
+    )
+    port map
+    (
+      -- clocking and reset
+      clkrst_i        => clkrst_i,
+      
+      -- misc inputs and outputs
+      buttons_i       => buttons_i,
+      switches_i      => switches_i,
+      leds_o          => leds_o,
+      sound_data_o    => sound_data_o,
+      -- controller inputs
+      inputs_i        => mapped_inputs,
+
+      -- graphics
+      bitmap_i        => from_bitmap_ctl,
+      bitmap_o        => to_bitmap_ctl,
+      
+      tilemap_i       => from_tilemap_ctl,
+      tilemap_o       => to_tilemap_ctl,
+      
+      sprite_reg_o    => to_sprite_reg,
+      sprite_i        => from_sprite_ctl,
+      sprite_o        => to_sprite_ctl,
+			spr0_hit				=> spr0_hit,
+      
+      graphics_i      => from_graphics,
+      graphics_o      => to_graphics,
+
+      -- custom i/o
+--      project_i       => project_i,
+--      project_o       => project_o,
+      platform_i      => platform_i,
+      platform_o      => platform_o,
+		
+		cpu_rom_addr    => cpu_rom_addr,
+	   cpu_rom_do      => cpu_rom_do
+    );
+
+  graphics_inst : entity work.Graphics                                    
+    Port Map
+    (
+      bitmap_ctl_i    => to_bitmap_ctl,
+      bitmap_ctl_o    => from_bitmap_ctl,
+
+      tilemap_ctl_i   => to_tilemap_ctl,
+      tilemap_ctl_o   => from_tilemap_ctl,
+
+      sprite_reg_i    => to_sprite_reg,
+      sprite_ctl_i    => to_sprite_ctl,
+      sprite_ctl_o    => from_sprite_ctl,
+      spr0_hit				=> spr0_hit,
+      
+      graphics_i      => to_graphics,
+      graphics_o      => from_graphics,
+      
+			-- video (incl. clk)
+			video_i					=> video_i,
+			video_o					=> video_o
+    );
+	
+end SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace_pkg.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace_pkg.vhd
new file mode 100644
index 00000000..d2dd0c07
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace_pkg.vhd	
@@ -0,0 +1,280 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+package pace_pkg is
+
+	--  
+	-- PACE constants which *MUST* be defined
+	--
+
+  type PACETargetType is
+  (
+    PACE_TARGET_NANOBOARD_NB1,
+    PACE_TARGET_DE0,
+    PACE_TARGET_DE0_CV,		-- 5CEBA4
+    PACE_TARGET_DE0_NANO,	-- EP4CE22
+    PACE_TARGET_DE1,
+    PACE_TARGET_DE2,
+    PACE_TARGET_DE2_70,		-- EP2C70
+    PACE_TARGET_DE2_115,	-- EP4CE115
+    PACE_TARGET_P2,		-- A02 build
+    PACE_TARGET_P2A,		-- A04/A build (SRAM byte selects)
+    PACE_TARGET_P3M,
+    PACE_TARGET_S3A_700,	-- Spartan 3A/N Starter Kit
+    PACE_TARGET_RC10,
+    PACE_TARGET_NX2_12,
+    PACE_TARGET_NEXYS_3,	-- Digilent S6 board
+    PACE_TARGET_CYC3DEV,
+    PACE_TARGET_CYC5GXDEV,
+    PACE_TARGET_COCO3PLUS,
+    PACE_TARGET_S5A,
+    PACE_TARGET_CARTEBLANCHE_250,
+    PACE_TARGET_CARTEBLANCHE_500,
+    PACE_TARGET_BEMICRO,
+    PACE_TARGET_OPENEP3C16,
+    PACE_TARGET_MIST,
+    PACE_TARGET_CHAMELEON64,
+    PACE_TARGET_RETRORAMBLINGS_CYC3,  -- Generic EP3C25 board with custom io boards
+    PACE_TARGET_S5A_R2_EP4C,
+    PACE_TARGET_S5A_R2_EP3SL,
+    PACE_TARGET_S5A_R2B0_EP4C,
+    PACE_TARGET_S5A_R2B0_EP3SL,
+    PACE_TARGET_S5A_R2C0_EP4C,
+    PACE_TARGET_S5A_R2C0_EP3SL,
+    PACE_TARGET_S5L_A0_EP4C,
+    PACE_TARGET_S5L_A0_EP3SL,
+    PACE_TARGET_NAVICO_ROCKY,
+    PACE_TARGET_NGPACE,
+    PACE_TARGET_S6M_A0
+  );
+
+	type PACEFpgaVendor_t is
+	(
+		PACE_FPGA_VENDOR_ALTERA,
+		PACE_FPGA_VENDOR_XILINX,
+		PACE_FPGA_VENDOR_LATTICE
+	);
+
+	type PACEFpgaFamily_t is
+	(
+		PACE_FPGA_FAMILY_CYCLONE1,
+		PACE_FPGA_FAMILY_CYCLONE2,
+		PACE_FPGA_FAMILY_CYCLONE3,
+		PACE_FPGA_FAMILY_CYCLONE4,
+		PACE_FPGA_FAMILY_CYCLONE5,
+		PACE_FPGA_FAMILY_CYCLONE6,
+		PACE_FPGA_FAMILY_STRATIX_III,
+		PACE_FPGA_FAMILY_SPARTAN3,
+		PACE_FPGA_FAMILY_SPARTAN3A,
+		PACE_FPGA_FAMILY_SPARTAN3E
+	);
+
+  type PACEJamma_t is
+  (
+    PACE_JAMMA_NONE,
+    PACE_JAMMA_MAPLE,
+    PACE_JAMMA_NGC,
+    PACE_JAMMA_PS2
+  );
+
+  -- Types
+
+	type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
+
+  type from_CLKRST_t is record
+    arst      : std_logic;
+    arst_n    : std_logic;
+    rst       : std_logic_vector(0 to 3);
+    clk_ref   : std_logic;                  --reference clock
+    clk       : std_logic_vector(0 to 3);
+  end record;
+  
+  -- maximums from the DE2 target
+
+  constant PACE_NUM_SWITCHES  : natural := 18;
+  subtype from_SWITCHES_t is std_logic_vector(PACE_NUM_SWITCHES-1 downto 0);
+  
+  constant PACE_NUM_BUTTONS   : natural := 4;
+  subtype from_BUTTONS_t is std_logic_vector(PACE_NUM_BUTTONS-1 downto 0);
+  
+  constant PACE_NUM_LEDS      : natural := 18;
+  subtype to_LEDS_t is std_logic_vector(PACE_NUM_LEDS-1 downto 0);
+  
+	--
+	-- JAMMA interface data structures
+	-- - note: all signals are active LOW
+	--
+
+	type from_JAMMA_player_t is record
+		start			: std_logic;
+		up				: std_logic;
+		down			: std_logic;
+		left			: std_logic;
+		right			: std_logic;
+		button		: std_logic_vector(1 to 5);
+	end record;
+
+	type from_JAMMA_player_a is array (natural range <>) of from_JAMMA_player_t;
+	
+	type from_JAMMA_t is record
+		coin_cnt	: std_logic_vector(1 to 2);
+		service		: std_logic;
+		tilt			: std_logic;
+		test			: std_logic;
+		coin			: std_logic_vector(1 to 2);
+		p					: from_JAMMA_player_a(1 to 2);
+	end record;
+
+  --
+  -- INPUTS
+  --
+  subtype analogue_in_t is std_logic_vector(9 downto 0);
+  type analogue_in_a is array (natural range <>) of analogue_in_t;
+  
+	type from_INPUTS_t is record
+    ps2_kclk  : std_logic;
+    ps2_kdat  : std_logic;
+    ps2_mclk  : std_logic;
+    ps2_mdat  : std_logic;
+    jamma_n   : from_JAMMA_t;
+    -- up to 4 10-bit analgue inputs
+    analogue  : analogue_in_a(1 to 4);
+  end record;
+
+  type in8_t is record
+    d         : std_logic_vector(7 downto 0);
+  end record;
+  
+  type from_MAPPED_INPUTS_t is array (natural range <>) of in8_t;
+  
+	--
+	-- SRAM interface data structure
+	--
+	type from_SRAM_t is record
+		d					: std_logic_vector(31 downto 0);
+	end record;
+	
+	type to_SRAM_t is record
+		a					: std_logic_vector(23 downto 0);
+		d					: std_logic_vector(31 downto 0);
+		be				: std_logic_vector(3 downto 0);
+		cs				: std_logic;
+		oe				: std_logic;
+		we				: std_logic;
+	end record;
+
+  function NULL_TO_SRAM return to_SRAM_t;
+	
+	--
+	-- FLASH interface data structure
+	--
+	type from_FLASH_t is record
+		d					: std_logic_vector(15 downto 0);
+	end record;
+	
+	type to_FLASH_t is record
+		a					: std_logic_vector(21 downto 0);
+		d					: std_logic_vector(15 downto 0);
+		we				: std_logic;
+		cs				: std_logic;
+		oe				: std_logic;
+	end record;
+
+  function NULL_TO_FLASH return to_FLASH_t;
+
+  type from_AUDIO_t is record
+    clk       : std_logic;
+  end record;
+  
+  type to_AUDIO_t is record
+    clk       : std_logic;
+    ldata     : std_logic_vector(15 downto 0);
+    rdata     : std_logic_vector(15 downto 0);
+  end record;
+  
+  function NULL_TO_AUDIO return to_AUDIO_t;
+
+  type from_SPI_t is record
+    din       : std_logic;
+  end record;
+  
+  type to_SPI_t is record
+    clk       : std_logic;
+    mode      : std_logic;
+    sel       : std_logic;
+    ena       : std_logic;
+    dout      : std_logic;
+  end record;
+  
+  function NULL_TO_SPI return to_SPI_t;
+
+  type to_SERIAL_t is record
+    txd       : std_logic;
+    rts       : std_logic;
+  end record;
+  
+  function NULL_TO_SERIAL return to_SERIAL_t;
+
+  type from_SERIAL_t is record
+    dcd       : std_logic;
+    rxd       : std_logic;
+    cts       : std_logic;
+  end record;
+  
+  constant PACE_NUM_GPI : natural := 72;
+  subtype from_GP_t is std_logic_vector(PACE_NUM_GPI-1 downto 0);
+  constant PACE_NUM_GPO : natural := PACE_NUM_GPI;
+  type to_GP_t is record
+    d         : std_logic_vector(PACE_NUM_GPO-1 downto 0);
+    oe        : std_logic_vector(PACE_NUM_GPO-1 downto 0);
+  end record;
+
+  function NULL_TO_GP return to_GP_t;
+  
+  subtype SND_A_t is std_logic_vector(7 downto 0);
+  subtype SND_D_t is std_logic_vector(7 downto 0);
+  
+  type to_SOUND_t is record
+    a         : SND_A_t;
+    d         : SND_D_t;
+    rd        : std_logic;
+    wr        : std_logic;
+  end record;
+  
+  type from_SOUND_t is record
+    d         : SND_D_t;
+  end record;
+
+  function NULL_TO_SOUND return to_SOUND_t;
+  
+ 	--
+  -- OSD interface data structure
+  --
+  type from_OSD_t is record
+    d         : std_logic_vector(7 downto 0);
+  end record;
+
+  function NULL_FROM_OSD return from_OSD_t;
+
+  type to_OSD_t is record
+    en        : std_logic;
+    a         : std_logic_vector(7 downto 0);
+    d         : std_logic_vector(7 downto 0);
+    we        : std_logic;
+  end record;
+
+  function NULL_TO_OSD return to_OSD_t;
+
+	-- create a constant that automatically determines 
+	-- whether this is simulation or synthesis
+	constant IN_SIMULATION : BOOLEAN := false
+	-- synthesis translate_off
+	or true
+	-- synthesis translate_on
+	;
+	constant IN_SYNTHESIS : boolean := not IN_SIMULATION;
+	
+end;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace_pkg_body.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace_pkg_body.vhd
new file mode 100644
index 00000000..e1cedf87
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pace_pkg_body.vhd	
@@ -0,0 +1,50 @@
+library work;
+
+package body pace_pkg is
+
+  function NULL_TO_FLASH return to_FLASH_t is
+  begin
+    return ((others => '0'), (others => '0'), '0', '0', '0');
+  end NULL_TO_FLASH;
+  
+  function NULL_TO_SRAM return to_SRAM_t is
+  begin
+    return ((others => '0'), (others => '0'), (others => '0'), '0', '0', '0');
+  end NULL_TO_SRAM;
+
+  function NULL_TO_AUDIO return to_AUDIO_t is
+  begin
+    return ('0', (others => '0'), (others => '0'));
+  end NULL_TO_AUDIO;
+
+  function NULL_TO_SPI return to_SPI_t is
+  begin
+    return (others => '0');
+  end NULL_TO_SPI;
+
+  function NULL_TO_SERIAL return to_SERIAL_t is
+  begin
+    return (others => '0');
+  end NULL_TO_SERIAL;
+
+  function NULL_TO_SOUND return to_SOUND_t is
+  begin
+    return ((others => '0'), (others => '0'), '0', '0');
+  end NULL_TO_SOUND;
+  
+  function NULL_FROM_OSD return from_OSD_t is
+  begin
+    return (others => (others => '0'));
+  end NULL_FROM_OSD;
+
+  function NULL_TO_OSD return to_OSD_t is
+  begin
+    return ('0', (others => '0'), (others => '0'), '0');
+  end NULL_TO_OSD;
+
+  function NULL_TO_GP return to_GP_t is
+  begin
+    return ((others => '0'), (others => '0'));
+  end NULL_TO_GP;
+
+end package body pace_pkg;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform.vhd
new file mode 100644
index 00000000..2ad4f64f
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform.vhd	
@@ -0,0 +1,477 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+use work.platform_variant_pkg.all;
+--use work.project_pkg.all;
+
+entity platform is
+  generic
+  (
+    NUM_INPUT_BYTES   : integer
+  );
+  port
+  (
+    -- clocking and reset
+    clkrst_i        : in from_CLKRST_t;
+
+    -- misc I/O
+    buttons_i       : in from_BUTTONS_t;
+    switches_i      : in from_SWITCHES_t;
+    leds_o          : out to_LEDS_t;
+
+    -- controller inputs
+    inputs_i        : in from_MAPPED_INPUTS_t(0 to NUM_INPUT_BYTES-1);
+
+    -- graphics
+    
+    bitmap_i        : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    bitmap_o        : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    
+    tilemap_i       : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+    tilemap_o       : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+
+    sprite_reg_o    : out to_SPRITE_REG_t;
+    sprite_i        : in from_SPRITE_CTL_t;
+    sprite_o        : out to_SPRITE_CTL_t;
+		spr0_hit				: in std_logic;
+
+    -- various graphics information
+    graphics_i      : in from_GRAPHICS_t;
+    graphics_o      : out to_GRAPHICS_t;
+	 sound_data_o    : out std_logic_vector(7 downto 0);
+
+    -- custom i/o
+--    project_i       : in from_PROJECT_IO_t;
+--    project_o       : out to_PROJECT_IO_t;
+    platform_i      : in from_PLATFORM_IO_t;
+    platform_o      : out to_PLATFORM_IO_t;
+	 cpu_rom_addr          : out std_logic_vector(14 downto 0);
+	 cpu_rom_do          : in std_logic_vector(7 downto 0)
+  );
+
+end platform;
+
+architecture SYN of platform is
+
+	alias clk_sys				  : std_logic is clkrst_i.clk(0);
+	alias rst_sys				  : std_logic is clkrst_i.rst(0);
+	alias clk_video       : std_logic is clkrst_i.clk(1);
+	
+  -- cpu signals  
+  signal clk_3M072_en		: std_logic;
+  signal cpu_clk_en     : std_logic;
+  signal cpu_a          : std_logic_vector(15 downto 0);
+  signal cpu_d_i        : std_logic_vector(7 downto 0);
+  signal cpu_d_o        : std_logic_vector(7 downto 0);
+  signal cpu_mem_wr     : std_logic;
+  signal cpu_io_rd      : std_logic;
+  signal cpu_io_wr      : std_logic;
+  signal cpu_irq        : std_logic;
+
+  -- ROM signals        
+	signal rom_cs					: std_logic;
+--  signal rom_d_o        : std_logic_vector(7 downto 0);
+  
+  -- keyboard signals
+	                        
+  -- VRAM signals       
+	signal vram_cs				: std_logic;
+	signal vram_wr				: std_logic;
+   signal vram_d_o       : std_logic_vector(7 downto 0);
+
+   signal snd_cs              : std_logic;
+
+  
+  -- RAM signals        
+  signal wram_cs        : std_logic;
+  signal wram_wr        : std_logic;
+  signal wram_d_o       : std_logic_vector(7 downto 0);
+
+  -- CRAM/SPRITE signals        
+  signal cram_cs        : std_logic;
+  signal cram_wr        : std_logic;
+	signal cram_d_o		    : std_logic_vector(7 downto 0);
+	signal sprite_cs      : std_logic;
+  
+  -- misc signals      
+  signal in_cs          : std_logic;
+  signal in_d_o         : std_logic_vector(7 downto 0);
+  
+  -- other signals
+  signal rst_platform   : std_logic;
+  signal pause          : std_logic;
+  signal rot_en         : std_logic;
+
+begin
+
+  -- handle special keys
+  process (clk_sys, rst_sys)
+    variable spec_keys_r  : std_logic_vector(7 downto 0);
+    alias spec_keys       : std_logic_vector(7 downto 0) is inputs_i(PACE_INPUTS_NUM_BYTES-1).d;
+    variable layer_en     : std_logic_vector(4 downto 0);
+  begin
+    if rst_sys = '1' then
+      rst_platform <= '0';
+      pause <= '0';
+      rot_en <= '0';  -- to default later
+      spec_keys_r := (others => '0');
+      layer_en := "11111";
+    elsif rising_edge(clk_sys) then
+      rst_platform <= spec_keys(0);
+      if spec_keys_r(1) = '0' and spec_keys(1) = '1' then
+        pause <= not pause;
+      end if;
+      if spec_keys_r(2) = '0' and spec_keys(2) = '1' then
+        rot_en <= not rot_en;
+        if layer_en = "11111" then
+          layer_en := "00001";
+        elsif layer_en = "10000" then
+          layer_en := "11111";
+        else
+          layer_en := layer_en(3 downto 0) & layer_en(4);
+        end if;
+      end if;
+      spec_keys_r := spec_keys;
+    end if;
+    graphics_o.bit8(0)(4 downto 0) <= layer_en;
+  end process;
+  
+  --graphics_o.bit8(0)(0) <= rot_en;
+  
+  -- chip select logic
+  -- ROM $0000-$7FFF
+  rom_cs <=     '1' when STD_MATCH(cpu_a,  "0---------------") else '0';
+  -- SPRITE $C000-$C0FF
+  sprite_cs <=  '1' when STD_MATCH(cpu_a, X"C0"&   "--------") else '0';
+  -- VRAM/CRAM $D000-$DFFF
+  vram_cs <=    '1' when PLATFORM_VARIANT = "kungfum" and
+                          STD_MATCH(cpu_a, X"D"&"0-----------") else 
+                '1' when PLATFORM_VARIANT /= "kungfum" and
+                          STD_MATCH(cpu_a, X"D"&"-----------0") else 
+                '0';
+  cram_cs <=    '1' when PLATFORM_VARIANT = "kungfum" and
+                          STD_MATCH(cpu_a, X"D"&"1-----------") else 
+                '1' when PLATFORM_VARIANT /= "kungfum" and
+                          STD_MATCH(cpu_a, X"D"&"-----------1") else 
+                '0';
+  -- RAM $E000-$EFFF
+  wram_cs <=    '1' when STD_MATCH(cpu_a, X"E"&"------------") else '0';
+
+  -- OUTPUT $DXX0
+  snd_cs <=      '1' when STD_MATCH(cpu_a(7 downto 0), X"D") else '0';
+
+  -- INPUTS (I/O) $00-$04
+  in_cs <=      '1' when STD_MATCH(cpu_a(7 downto 0), X"0"&"00--") else 
+                '1' when STD_MATCH(cpu_a(7 downto 0), X"04") else
+                '0';
+					 
+process (clk_sys, rst_sys) begin
+	if rst_sys = '1' then
+		sound_data_o <= X"00";
+	elsif rising_edge(clk_sys) then
+      if cpu_clk_en = '1' and cpu_mem_wr = '1' and snd_cs = '1' then
+			sound_data_o <= cpu_d_o;
+		end if;
+	end if; 
+  end process;
+
+  
+	-- memory read mux
+	cpu_d_i <=  in_d_o when (cpu_io_rd = '1' and in_cs = '1') else
+					cpu_rom_do when rom_cs = '1' else
+					vram_d_o when vram_cs = '1' else
+					cram_d_o when cram_cs = '1' else
+					wram_d_o when wram_cs = '1' else
+					(others => '1');
+              
+  -- memory block write signals 
+	vram_wr <= vram_cs and cpu_mem_wr;
+	cram_wr <= cram_cs and cpu_mem_wr;
+	wram_wr <= wram_cs and cpu_mem_wr;
+
+  -- sprite registers
+  sprite_reg_o.clk <= clk_sys;
+  sprite_reg_o.clk_ena <= clk_3M072_en;
+  sprite_reg_o.a <= cpu_a(7 downto 0);
+  sprite_reg_o.d <= cpu_d_o;
+  sprite_reg_o.wr <= sprite_cs and cpu_mem_wr;
+
+  --
+  -- COMPONENT INSTANTIATION
+  --
+
+  BLK_CPU : block
+    signal cpu_rst        : std_logic;
+  begin
+    -- generate CPU enable clock (3MHz from 27/30MHz)
+    clk_en_inst : entity work.clk_div
+      generic map
+      (
+        DIVISOR		=> M62_CPU_CLK_ENA_DIVIDE_BY
+      )
+      port map
+      (
+        clk				=> clk_sys,
+        reset			=> rst_sys,
+        clk_en		=> clk_3M072_en
+      );
+    
+    -- gated CPU signals
+    cpu_clk_en <= clk_3M072_en and not pause;
+    cpu_rst <= rst_sys or rst_platform;
+    
+    cpu_inst : entity work.Z80                                                
+      port map
+      (
+        clk 		=> clk_sys,                                   
+        clk_en	=> cpu_clk_en,
+        reset  	=> cpu_rst,
+
+        addr   	=> cpu_a,
+        datai  	=> cpu_d_i,
+        datao  	=> cpu_d_o,
+
+        mem_rd 	=> open,
+        mem_wr 	=> cpu_mem_wr,
+        io_rd  	=> cpu_io_rd,
+        io_wr  	=> cpu_io_wr,
+
+        intreq 	=> cpu_irq,
+        intvec 	=> cpu_d_i,
+        intack 	=> open,
+        nmi    	=> '0'
+      );
+
+  end block BLK_CPU;
+  
+  BLK_INTERRUPTS : block
+  
+    signal vblank_int     : std_logic;
+
+  begin
+  
+		process (clk_sys, rst_sys)
+			variable vblank_r : std_logic_vector(3 downto 0);
+			alias vblank_prev : std_logic is vblank_r(vblank_r'left);
+			alias vblank_um   : std_logic is vblank_r(vblank_r'left-1);
+      -- 1us duty for VBLANK_INT
+      variable count    : integer range 0 to CLK0_FREQ_MHz * 100;
+		begin
+			if rst_sys = '1' then
+				vblank_int <= '0';
+				vblank_r := (others => '0');
+        count := count'high;
+			elsif rising_edge(clk_sys) then
+        -- rising edge vblank only
+        if vblank_prev = '0' and vblank_um = '1' then
+          count := 0;
+        end if;
+        if count /= count'high then
+          vblank_int <= '1';
+          count := count + 1;
+        else
+          vblank_int <= '0';
+        end if;
+        vblank_r := vblank_r(vblank_r'left-1 downto 0) & graphics_i.vblank;
+			end if; -- rising_edge(clk_sys)
+		end process;
+
+    -- generate INT
+    cpu_irq <= vblank_int;
+    
+  end block BLK_INTERRUPTS;
+  
+  BLK_INPUTS : block
+  begin
+    in_d_o <= inputs_i(0).d when cpu_a(2 downto 0) = "000" else
+              inputs_i(1).d when cpu_a(2 downto 0) = "001" else
+              inputs_i(2).d when cpu_a(2 downto 0) = "010" else
+              inputs_i(3).d when cpu_a(2 downto 0) = "011" else
+              inputs_i(4).d;
+  end block BLK_INPUTS;
+  
+  BLK_SCROLL : block
+    signal m62_hscroll  : std_logic_vector(15 downto 0);
+  begin
+    process (clk_sys, rst_sys)
+    begin
+      if rst_sys = '1' then
+        m62_hscroll <= (others => '0');
+      elsif rising_edge(clk_sys) then
+        if cpu_clk_en = '1' and cpu_mem_wr = '1' then
+          case cpu_a is
+            when X"A000" =>
+              if PLATFORM_VARIANT = "kungfum" then
+                m62_hscroll(7 downto 0) <= cpu_d_o;
+              end if;
+            when X"B000" =>
+              if PLATFORM_VARIANT = "kungfum" then
+                m62_hscroll(15 downto 8) <= cpu_d_o;
+              end if;
+            when others =>
+              null;
+          end case;
+        end if; -- cpu_wr
+      end if; -- rising_edge(clk_sys)
+    end process;
+    graphics_o.bit16(0) <= m62_hscroll;
+  end block BLK_SCROLL;
+  
+cpu_rom_addr <= cpu_a(14 downto 0);
+
+  BLK_GFX_ROMS : block
+  
+    type gfx_rom_d_a is array(M62_CHAR_ROM'range) of std_logic_vector(7 downto 0);
+    signal chr_rom_d      : gfx_rom_d_a;
+    type spr_rom_d_a is array(0 to 11) of std_logic_vector(7 downto 0);
+    signal spr_rom_left   : spr_rom_d_a;
+    signal spr_rom_right  : spr_rom_d_a;
+    
+  begin
+  
+    GEN_CHAR_ROMS : for i in M62_CHAR_ROM'range generate
+      char_rom_inst : entity work.sprom
+        generic map
+        (
+          init_file		=> "./roms/" &
+                          M62_CHAR_ROM(i) & ".hex",
+          widthad_a		=> 13
+        )
+        port map
+        (
+          clock			=> clk_video,
+          address		=> tilemap_i(1).tile_a(12 downto 0),
+          q					=> chr_rom_d(i)
+        );
+    end generate GEN_CHAR_ROMS;
+
+    tilemap_o(1).tile_d(23 downto 0) <= chr_rom_d(0) & chr_rom_d(1) & chr_rom_d(2);
+
+    GEN_SPRITE_ROMS : for i in M62_SPRITE_ROM'range generate
+      sprite_rom_inst : entity work.dprom_2r
+        generic map
+        (
+          init_file		=> "./roms/" &
+                          M62_SPRITE_ROM(i) & ".hex",
+          widthad_a		=> 13,
+          widthad_b		=> 13
+        )
+        port map
+        (
+          clock			              => clk_video,
+          address_a(12 downto 5)  => sprite_i.a(12 downto 5),
+          address_a(4)            => '0',
+          address_a(3 downto 0)   => sprite_i.a(3 downto 0),
+          q_a 			              => spr_rom_left(i),
+          address_b(12 downto 5)  => sprite_i.a(12 downto 5),
+          address_b(4)            => '1',
+          address_b(3 downto 0)   => sprite_i.a(3 downto 0),
+          q_b                     => spr_rom_right(i)
+        );
+    end generate GEN_SPRITE_ROMS;
+
+    sprite_o.d(sprite_o.d'left downto 48) <= (others => '0');
+    sprite_o.d(47 downto 0) <=  spr_rom_left(0) & spr_rom_right(0) & 
+                                spr_rom_left(1) & spr_rom_right(1) &
+                                spr_rom_left(2) & spr_rom_right(2)
+                                  when sprite_i.a(14 downto 13) = "00" else
+                                spr_rom_left(3) & spr_rom_right(3) &
+                                spr_rom_left(4) & spr_rom_right(4) &
+                                spr_rom_left(5) & spr_rom_right(5) 
+                                  when sprite_i.a(14 downto 13) = "01" else
+                                spr_rom_left(6) & spr_rom_right(6) &
+                                spr_rom_left(7) & spr_rom_right(7) &
+                                spr_rom_left(8) & spr_rom_right(8) 
+                                  when sprite_i.a(14 downto 13) = "10" else
+                                spr_rom_left(9) & spr_rom_right(9) &
+                                spr_rom_left(10) & spr_rom_right(10) &
+                                spr_rom_left(11) & spr_rom_right(11);
+
+  end block BLK_GFX_ROMS;
+
+
+
+  BLK_VRAM : block
+    signal vram_a   : std_logic_vector(10 downto 0);
+    alias cram_a    : std_logic_vector(10 downto 0) is vram_a;
+  begin
+  
+    vram_a <= cpu_a(10 downto 0) when PLATFORM_VARIANT = "kungfum" else
+              cpu_a(11 downto 1);
+              
+    vram_inst : entity work.dpram
+      generic map
+      (
+        init_file		=> "",
+        widthad_a		=> 11
+      )
+      port map
+      (
+        clock_b			=> clk_sys,
+        address_b		=> vram_a,
+        wren_b			=> vram_wr,
+        data_b			=> cpu_d_o,
+        q_b					=> vram_d_o,
+
+        clock_a			=> clk_video,
+        address_a		=> tilemap_i(1).map_a(10 downto 0),
+        wren_a			=> '0',
+        data_a			=> (others => 'X'),
+        q_a					=> tilemap_o(1).map_d(7 downto 0)
+      );
+    tilemap_o(1).map_d(15 downto 8) <= (others => '0');
+
+    cram_inst : entity work.dpram
+      generic map
+      (
+        init_file		=> "",
+        widthad_a		=> 11
+      )
+      port map
+      (
+        clock_b			=> clk_sys,
+        address_b		=> cram_a,
+        wren_b			=> cram_wr,
+        data_b			=> cpu_d_o,
+        q_b					=> cram_d_o,
+
+        clock_a			=> clk_video,
+        address_a		=> tilemap_i(1).attr_a(10 downto 0),
+        wren_a			=> '0',
+        data_a			=> (others => 'X'),
+        q_a					=> tilemap_o(1).attr_d(7 downto 0)
+      );
+    tilemap_o(1).attr_d(15 downto 8) <= (others => '0');
+    
+  end block BLK_VRAM;
+ 
+  
+    wram_inst : entity work.spram
+      generic map
+      (
+      	widthad_a => 12
+      )
+      port map
+      (
+        clock				=> clk_sys,
+        address			=> cpu_a(11 downto 0),
+        data				=> cpu_d_o,
+        wren				=> wram_wr,
+        q						=> wram_d_o
+      );
+
+		
+  -- unused outputs
+
+  sprite_o.ld <= '0';
+  --graphics_o <= NULL_TO_GRAPHICS;
+  leds_o <= (others => '0');
+  
+end SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform_pkg.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform_pkg.vhd
new file mode 100644
index 00000000..355d009a
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform_pkg.vhd	
@@ -0,0 +1,55 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+
+use work.platform_variant_pkg.all;
+use work.video_controller_pkg.all;
+package platform_pkg is
+
+
+	constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_PAL_576x288_50Hz;
+	constant PACE_CLK0_DIVIDE_BY              : natural := 27;
+	constant PACE_CLK0_MULTIPLY_BY            : natural := 44;   -- 27*44/27 = 44MHz
+	constant PACE_CLK1_DIVIDE_BY              : natural := 27;
+	constant PACE_CLK1_MULTIPLY_BY            : natural := 11;   -- 27*11/27 = 11MHz
+	constant PACE_VIDEO_H_SCALE               : integer := 1;
+	constant PACE_VIDEO_V_SCALE               : integer := 1;
+	constant PACE_ENABLE_ADV724					: std_logic := '1';
+	constant USE_VIDEO_VBLANK_INTERRUPT 		: boolean := false;
+	constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '1';
+	constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '1';
+
+	constant PACE_VIDEO_BORDER_RGB            : RGB_t := RGB_BLACK;
+
+	constant M62_VIDEO_H_SIZE				      : integer := 256;
+	constant M62_VIDEO_H_OFFSET           		: integer := (512-M62_VIDEO_H_SIZE)/2;
+	constant M62_VIDEO_V_SIZE				      : integer := 256;
+
+	constant PACE_VIDEO_NUM_BITMAPS		    	: natural := 0;
+	constant PACE_VIDEO_NUM_TILEMAPS	    		: natural := 1;
+	constant PACE_VIDEO_NUM_SPRITES 	    		: natural := 32;
+	constant PACE_VIDEO_H_SIZE				    	: integer := M62_VIDEO_H_SIZE;
+	constant PACE_VIDEO_V_SIZE				    	: integer := M62_VIDEO_V_SIZE;
+	constant PACE_VIDEO_L_CROP            		: integer := 0;
+	constant PACE_VIDEO_R_CROP            		: integer := PACE_VIDEO_L_CROP;
+	constant PACE_VIDEO_PIPELINE_DELAY    		: integer := 5;
+
+	constant PACE_INPUTS_NUM_BYTES        		: integer := 6;
+
+	constant CLK0_FREQ_MHz		            	: natural := 
+    27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY;
+	constant CPU_FREQ_MHz                 		: natural := 3;
+
+	constant M62_CPU_CLK_ENA_DIVIDE_BY    		: natural := CLK0_FREQ_MHz / CPU_FREQ_MHz;
+
+  type from_PLATFORM_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_PLATFORM_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+end;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform_variant_pkg.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform_variant_pkg.vhd
new file mode 100644
index 00000000..c4995415
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/platform_variant_pkg.vhd	
@@ -0,0 +1,524 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+
+use work.platform_pkg.all;
+
+package platform_variant_pkg is
+
+
+  constant PLATFORM_VARIANT             : string := "kungfum";
+  
+  type rom_a is array (natural range <>) of string;
+  
+--  constant M62_ROM                      : rom_a(0 to 3) := 
+--                                          (
+--                                            0 => "lr-a-4e", 
+--                                            1 => "lr-a-4d",
+ --                                           2 => "lr-a-4b",
+ --                                           3 => "lr-a-4a"
+ --                                         );
+ -- constant M62_ROM_WIDTHAD              : natural := 13;
+
+  constant M62_CHAR_ROM                 : rom_a(0 to 2) := 
+                                          (
+                                            0 => "g-4c-a", 
+                                            1 => "g-4d-a",
+                                            2 => "g-4e-a"
+                                          );
+
+  constant M62_SPRITE_ROM               : rom_a(0 to 11) := 
+                                          (
+                                            0 => "b-4k-.bin", 
+                                            3 => "b-4f-.bin",
+                                            6 => "b-4l-.bin",
+                                            9 => "b-4h-.bin",
+                                            1 => "b-3n-.bin",
+                                            4 => "b-4n-.bin",
+                                            7 => "b-4m-.bin",
+                                            10 => "b-3m-.bin",
+                                            2 => "b-4c-.bin",
+                                            5 => "b-4e-.bin",
+                                            8 => "b-4d-.bin",
+                                            11 => "b-4a-.bin"
+                                          );
+
+
+type pal_rgb_t is array (0 to 2) of std_logic_vector(7 downto 0);
+	type pal_a is array (natural range <>) of pal_rgb_t;
+
+	constant tile_pal : pal_a(0 to 255) :=
+	(
+    0 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    1 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    2 => (0=>"00000011", 1=>"11111111", 2=>"00000011"),  -- 03FF03
+    3 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    4 => (0=>"00000011", 1=>"00000011", 2=>"11111111"),  -- 0303FF
+    5 => (0=>"11111111", 1=>"00000011", 2=>"11111111"),  -- FF03FF
+    6 => (0=>"00000011", 1=>"11111111", 2=>"11111111"),  -- 03FFFF
+    8 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    9 => (0=>"11110000", 1=>"10110111", 2=>"10000100"),  -- F0B784
+    10 => (0=>"11011100", 1=>"10100110", 2=>"01110000"),  -- DCA670
+    11 => (0=>"11111111", 1=>"00000011", 2=>"00110001"),  -- FF0331
+    12 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    13 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    14 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    15 => (0=>"11110000", 1=>"11110000", 2=>"11110000"),  -- F0F0F0
+    16 => (0=>"10110111", 1=>"10110111", 2=>"10110111"),  -- B7B7B7
+    18 => (0=>"10000100", 1=>"11001100", 2=>"10000100"),  -- 84CC84
+    19 => (0=>"11001100", 1=>"11110000", 2=>"11001100"),  -- CCF0CC
+    20 => (0=>"01100010", 1=>"01100010", 2=>"01100010"),  -- 626262
+    21 => (0=>"11011100", 1=>"10010100", 2=>"01010000"),  -- DC9450
+    22 => (0=>"10110111", 1=>"10010100", 2=>"01010000"),  -- B79450
+    23 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    24 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    25 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    26 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    27 => (0=>"10100110", 1=>"11001100", 2=>"11111111"),  -- A6CCFF
+    29 => (0=>"11001100", 1=>"10010100", 2=>"10000100"),  -- CC9484
+    30 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    31 => (0=>"11111111", 1=>"11110000", 2=>"11001100"),  -- FFF0CC
+    32 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    33 => (0=>"11001100", 1=>"00110001", 2=>"01000001"),  -- CC3141
+    34 => (0=>"11111111", 1=>"10000100", 2=>"10000100"),  -- FF8484
+    35 => (0=>"11111111", 1=>"10110111", 2=>"10110111"),  -- FFB7B7
+    36 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    37 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    38 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    39 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    40 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    41 => (0=>"00000011", 1=>"11001100", 2=>"11001100"),  -- 03CCCC
+    42 => (0=>"11011100", 1=>"11111111", 2=>"11111111"),  -- DCFFFF
+    43 => (0=>"11011100", 1=>"10010100", 2=>"01110000"),  -- DC9470
+    44 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    45 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    46 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    47 => (0=>"11111111", 1=>"11001100", 2=>"01110000"),  -- FFCC70
+    48 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    49 => (0=>"11011100", 1=>"11111111", 2=>"11111111"),  -- DCFFFF
+    50 => (0=>"00000011", 1=>"11110000", 2=>"11110000"),  -- 03F0F0
+    51 => (0=>"11011100", 1=>"10010100", 2=>"01110000"),  -- DC9470
+    52 => (0=>"11111111", 1=>"11001100", 2=>"01110000"),  -- FFCC70
+    53 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    54 => (0=>"01110000", 1=>"01110000", 2=>"01110000"),  -- 707070
+    55 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    56 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    57 => (0=>"00000011", 1=>"11111111", 2=>"00000011"),  -- 03FF03
+    58 => (0=>"11111111", 1=>"11001100", 2=>"00000011"),  -- FFCC03
+    59 => (0=>"11111111", 1=>"11011100", 2=>"00000011"),  -- FFDC03
+    60 => (0=>"00000011", 1=>"11111111", 2=>"11111111"),  -- 03FFFF
+    61 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    62 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    63 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    64 => (0=>"11111111", 1=>"00000011", 2=>"00110001"),  -- FF0331
+    65 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    66 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    67 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    68 => (0=>"11011100", 1=>"10010100", 2=>"01110000"),  -- DC9470
+    69 => (0=>"11111111", 1=>"11001100", 2=>"01110000"),  -- FFCC70
+    70 => (0=>"00000011", 1=>"11110000", 2=>"11110000"),  -- 03F0F0
+    71 => (0=>"11011100", 1=>"11111111", 2=>"11111111"),  -- DCFFFF
+    72 => (0=>"10100110", 1=>"11001100", 2=>"11111111"),  -- A6CCFF
+    73 => (0=>"11111111", 1=>"11001100", 2=>"01110000"),  -- FFCC70
+    74 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    75 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    76 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    77 => (0=>"11110000", 1=>"11011100", 2=>"10100110"),  -- F0DCA6
+    78 => (0=>"11110000", 1=>"11110000", 2=>"11110000"),  -- F0F0F0
+    80 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    81 => (0=>"11111111", 1=>"11001100", 2=>"01110000"),  -- FFCC70
+    82 => (0=>"11011100", 1=>"10010100", 2=>"01110000"),  -- DC9470
+    83 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    84 => (0=>"11011100", 1=>"11111111", 2=>"11111111"),  -- DCFFFF
+    85 => (0=>"00000011", 1=>"11110000", 2=>"11110000"),  -- 03F0F0
+    86 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    87 => (0=>"01110000", 1=>"01110000", 2=>"01110000"),  -- 707070
+    88 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    91 => (0=>"11111111", 1=>"00000011", 2=>"00110001"),  -- FF0331
+    92 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    93 => (0=>"11001100", 1=>"00000011", 2=>"10000100"),  -- CC0384
+    94 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    96 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    97 => (0=>"00000011", 1=>"10110111", 2=>"11001100"),  -- 03B7CC
+    98 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    99 => (0=>"11111111", 1=>"11001100", 2=>"01110000"),  -- FFCC70
+    100 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    101 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    102 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    103 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    105 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    106 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    107 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    108 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    109 => (0=>"10100110", 1=>"11001100", 2=>"11111111"),  -- A6CCFF
+    110 => (0=>"00000011", 1=>"11011100", 2=>"00000011"),  -- 03DC03
+    111 => (0=>"10110111", 1=>"11111111", 2=>"10110111"),  -- B7FFB7
+    112 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    113 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    114 => (0=>"00000011", 1=>"11110000", 2=>"10100110"),  -- 03F0A6
+    115 => (0=>"11111111", 1=>"11011100", 2=>"10010100"),  -- FFDC94
+    116 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    117 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    118 => (0=>"00000011", 1=>"11011100", 2=>"00000011"),  -- 03DC03
+    119 => (0=>"10110111", 1=>"11111111", 2=>"10110111"),  -- B7FFB7
+    120 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    121 => (0=>"11111111", 1=>"10110111", 2=>"10110111"),  -- FFB7B7
+    122 => (0=>"00000011", 1=>"11110000", 2=>"10100110"),  -- 03F0A6
+    123 => (0=>"11111111", 1=>"11011100", 2=>"10010100"),  -- FFDC94
+    125 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    126 => (0=>"11011100", 1=>"11011100", 2=>"11011100"),  -- DCDCDC
+    127 => (0=>"10110111", 1=>"10110111", 2=>"10110111"),  -- B7B7B7
+    128 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    129 => (0=>"11111111", 1=>"10110111", 2=>"10110111"),  -- FFB7B7
+    130 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    131 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    132 => (0=>"00000011", 1=>"11011100", 2=>"00000011"),  -- 03DC03
+    133 => (0=>"11011100", 1=>"11011100", 2=>"11011100"),  -- DCDCDC
+    134 => (0=>"10110111", 1=>"11111111", 2=>"10110111"),  -- B7FFB7
+    135 => (0=>"10110111", 1=>"10110111", 2=>"10110111"),  -- B7B7B7
+    136 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    137 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    138 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    139 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    140 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    141 => (0=>"11111111", 1=>"11001100", 2=>"10110111"),  -- FFCCB7
+    142 => (0=>"00000011", 1=>"11011100", 2=>"11011100"),  -- 03DCDC
+    143 => (0=>"10110111", 1=>"10100110", 2=>"10000100"),  -- B7A684
+    144 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    145 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    146 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    147 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    148 => (0=>"11001100", 1=>"10010100", 2=>"10000100"),  -- CC9484
+    149 => (0=>"11111111", 1=>"11001100", 2=>"10110111"),  -- FFCCB7
+    150 => (0=>"10100110", 1=>"11001100", 2=>"11111111"),  -- A6CCFF
+    151 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    152 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    153 => (0=>"10100110", 1=>"10000100", 2=>"00000011"),  -- A68403
+    154 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    155 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    156 => (0=>"11001100", 1=>"10010100", 2=>"10000100"),  -- CC9484
+    157 => (0=>"11111111", 1=>"11001100", 2=>"10110111"),  -- FFCCB7
+    158 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    159 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    160 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    162 => (0=>"11111111", 1=>"10010100", 2=>"01110000"),  -- FF9470
+    163 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    164 => (0=>"11111111", 1=>"11111111", 2=>"11001100"),  -- FFFFCC
+    165 => (0=>"11111111", 1=>"11111111", 2=>"10110111"),  -- FFFFB7
+    166 => (0=>"11001100", 1=>"11001100", 2=>"00000011"),  -- CCCC03
+    167 => (0=>"11110000", 1=>"11110000", 2=>"00000011"),  -- F0F003
+    168 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    169 => (0=>"00000011", 1=>"11111111", 2=>"11111111"),  -- 03FFFF
+    170 => (0=>"11111111", 1=>"00000011", 2=>"11111111"),  -- FF03FF
+    171 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    173 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    174 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    175 => (0=>"10110111", 1=>"10110111", 2=>"10110111"),  -- B7B7B7
+    176 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    177 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    178 => (0=>"11001100", 1=>"11111111", 2=>"11001100"),  -- CCFFCC
+    179 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    180 => (0=>"00000011", 1=>"00000011", 2=>"11111111"),  -- 0303FF
+    181 => (0=>"11110000", 1=>"10110111", 2=>"10010100"),  -- F0B794
+    182 => (0=>"10110111", 1=>"11110000", 2=>"11110000"),  -- B7F0F0
+    183 => (0=>"11001100", 1=>"10100110", 2=>"10000100"),  -- CCA684
+    186 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    188 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    194 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    196 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    200 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    201 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    202 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    203 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    204 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    205 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    206 => (0=>"00000011", 1=>"00000011", 2=>"10100110"),  -- 0303A6
+    208 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    209 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    210 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    212 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    213 => (0=>"11111111", 1=>"10010100", 2=>"10010100"),  -- FF9494
+    214 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    216 => (0=>"11111111", 1=>"11110000", 2=>"11011100"),  -- FFF0DC
+    217 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    218 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    219 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    220 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    221 => (0=>"11111111", 1=>"11001100", 2=>"10110111"),  -- FFCCB7
+    222 => (0=>"11011100", 1=>"10110111", 2=>"10010100"),  -- DCB794
+    223 => (0=>"11110000", 1=>"11001100", 2=>"10100110"),  -- F0CCA6
+    224 => (0=>"01100010", 1=>"01100010", 2=>"01100010"),  -- 626262
+    225 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    226 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    227 => (0=>"11011100", 1=>"00100010", 2=>"11001100"),  -- DC22CC
+    228 => (0=>"11001100", 1=>"11110000", 2=>"11001100"),  -- CCF0CC
+    229 => (0=>"10000100", 1=>"11001100", 2=>"10000100"),  -- 84CC84
+    231 => (0=>"11110000", 1=>"11011100", 2=>"10100110"),  -- F0DCA6
+    232 => (0=>"10100110", 1=>"10000100", 2=>"11011100"),  -- A684DC
+    233 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    234 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    235 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+    236 => (0=>"01100010", 1=>"01100010", 2=>"01100010"),  -- 626262
+    237 => (0=>"11110000", 1=>"11011100", 2=>"10100110"),  -- F0DCA6
+    238 => (0=>"11011100", 1=>"00100010", 2=>"11001100"),  -- DC22CC
+    239 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    240 => (0=>"01100010", 1=>"01100010", 2=>"01100010"),  -- 626262
+    241 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    242 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    243 => (0=>"11011100", 1=>"00100010", 2=>"11001100"),  -- DC22CC
+    244 => (0=>"00000011", 1=>"10110111", 2=>"00000011"),  -- 03B703
+    245 => (0=>"11110000", 1=>"11011100", 2=>"10100110"),  -- F0DCA6
+    246 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    248 => (0=>"11111111", 1=>"11110000", 2=>"11011100"),  -- FFF0DC
+    249 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    250 => (0=>"10010100", 1=>"10000100", 2=>"10110111"),  -- 9484B7
+    251 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    252 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    253 => (0=>"10000100", 1=>"11001100", 2=>"10000100"),  -- 84CC84
+    254 => (0=>"11011100", 1=>"11001100", 2=>"10110111"),  -- DCCCB7
+    255 => (0=>"11110000", 1=>"11110000", 2=>"11001100"),  -- F0F0CC
+		others => (others => (others => '1'))
+  );
+                                          
+	constant sprite_pal : pal_a(0 to 255) :=
+	(
+    0 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    1 => (0=>"10100110", 1=>"01110000", 2=>"00000011"),  -- A67003
+    2 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    3 => (0=>"11111111", 1=>"10110111", 2=>"10010100"),  -- FFB794
+    4 => (0=>"11111111", 1=>"11001100", 2=>"10100110"),  -- FFCCA6
+    5 => (0=>"11001100", 1=>"11111111", 2=>"11111111"),  -- CCFFFF
+    6 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    8 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    9 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    10 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    11 => (0=>"11111111", 1=>"10110111", 2=>"10010100"),  -- FFB794
+    12 => (0=>"11111111", 1=>"11001100", 2=>"10100110"),  -- FFCCA6
+    13 => (0=>"10100110", 1=>"11011100", 2=>"11110000"),  -- A6DCF0
+    14 => (0=>"11001100", 1=>"11111111", 2=>"11111111"),  -- CCFFFF
+    16 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    17 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    18 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    19 => (0=>"11111111", 1=>"10110111", 2=>"10010100"),  -- FFB794
+    20 => (0=>"11111111", 1=>"11001100", 2=>"10100110"),  -- FFCCA6
+    21 => (0=>"10100110", 1=>"11011100", 2=>"11110000"),  -- A6DCF0
+    22 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    24 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    25 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    26 => (0=>"11001100", 1=>"11111111", 2=>"11111111"),  -- CCFFFF
+    27 => (0=>"11111111", 1=>"11001100", 2=>"10100110"),  -- FFCCA6
+    28 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    29 => (0=>"10100110", 1=>"01110000", 2=>"00000011"),  -- A67003
+    30 => (0=>"10110111", 1=>"10010100", 2=>"01110000"),  -- B79470
+    31 => (0=>"11111111", 1=>"10110111", 2=>"10010100"),  -- FFB794
+    32 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    33 => (0=>"10010100", 1=>"10010100", 2=>"11001100"),  -- 9494CC
+    34 => (0=>"10110111", 1=>"10110111", 2=>"11011100"),  -- B7B7DC
+    35 => (0=>"11001100", 1=>"11011100", 2=>"11111111"),  -- CCDCFF
+    36 => (0=>"11011100", 1=>"00000011", 2=>"11011100"),  -- DC03DC
+    37 => (0=>"11110000", 1=>"10100110", 2=>"11011100"),  -- F0A6DC
+    38 => (0=>"11111111", 1=>"10110111", 2=>"10010100"),  -- FFB794
+    39 => (0=>"11111111", 1=>"11001100", 2=>"10100110"),  -- FFCCA6
+    40 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    41 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    42 => (0=>"10110111", 1=>"10110111", 2=>"11011100"),  -- B7B7DC
+    43 => (0=>"11001100", 1=>"11011100", 2=>"11111111"),  -- CCDCFF
+    44 => (0=>"11011100", 1=>"00000011", 2=>"11011100"),  -- DC03DC
+    45 => (0=>"11110000", 1=>"10100110", 2=>"11011100"),  -- F0A6DC
+    46 => (0=>"11111111", 1=>"10110111", 2=>"10010100"),  -- FFB794
+    47 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    48 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    49 => (0=>"11001100", 1=>"11011100", 2=>"11111111"),  -- CCDCFF
+    50 => (0=>"10100110", 1=>"10110111", 2=>"11001100"),  -- A6B7CC
+    51 => (0=>"11110000", 1=>"11110000", 2=>"11110000"),  -- F0F0F0
+    52 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    53 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    54 => (0=>"11111111", 1=>"11011100", 2=>"10110111"),  -- FFDCB7
+    56 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    57 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    59 => (0=>"11110000", 1=>"10100110", 2=>"00000011"),  -- F0A603
+    60 => (0=>"11111111", 1=>"11011100", 2=>"10110111"),  -- FFDCB7
+    61 => (0=>"11110000", 1=>"11001100", 2=>"10100110"),  -- F0CCA6
+    62 => (0=>"10100110", 1=>"10000100", 2=>"00000011"),  -- A68403
+    63 => (0=>"10110111", 1=>"11111111", 2=>"10110111"),  -- B7FFB7
+    64 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    65 => (0=>"11111111", 1=>"10110111", 2=>"10010100"),  -- FFB794
+    66 => (0=>"11111111", 1=>"11001100", 2=>"10100110"),  -- FFCCA6
+    67 => (0=>"11011100", 1=>"11110000", 2=>"11110000"),  -- DCF0F0
+    68 => (0=>"11001100", 1=>"11011100", 2=>"11111111"),  -- CCDCFF
+    69 => (0=>"10100110", 1=>"10010100", 2=>"01110000"),  -- A69470
+    70 => (0=>"10000100", 1=>"10000100", 2=>"10000100"),  -- 848484
+    71 => (0=>"10110111", 1=>"10110111", 2=>"11011100"),  -- B7B7DC
+    72 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    73 => (0=>"11110000", 1=>"11110000", 2=>"10000100"),  -- F0F084
+    74 => (0=>"11111111", 1=>"11001100", 2=>"10100110"),  -- FFCCA6
+    75 => (0=>"11011100", 1=>"11110000", 2=>"11110000"),  -- DCF0F0
+    76 => (0=>"11001100", 1=>"11011100", 2=>"11111111"),  -- CCDCFF
+    77 => (0=>"10100110", 1=>"10010100", 2=>"01110000"),  -- A69470
+    78 => (0=>"10000100", 1=>"10000100", 2=>"10000100"),  -- 848484
+    80 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    81 => (0=>"11011100", 1=>"11001100", 2=>"10010100"),  -- DCCC94
+    82 => (0=>"01110000", 1=>"10110111", 2=>"01110000"),  -- 70B770
+    83 => (0=>"11110000", 1=>"11011100", 2=>"10010100"),  -- F0DC94
+    84 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    86 => (0=>"01110000", 1=>"10010100", 2=>"01110000"),  -- 709470
+    88 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    89 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    90 => (0=>"10000100", 1=>"11111111", 2=>"10000100"),  -- 84FF84
+    91 => (0=>"11111111", 1=>"10110111", 2=>"01110000"),  -- FFB770
+    92 => (0=>"01110000", 1=>"01110000", 2=>"10110111"),  -- 7070B7
+    94 => (0=>"11001100", 1=>"10100110", 2=>"11111111"),  -- CCA6FF
+    96 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    97 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    98 => (0=>"01110000", 1=>"11001100", 2=>"01110000"),  -- 70CC70
+    99 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    100 => (0=>"01110000", 1=>"10100110", 2=>"01110000"),  -- 70A670
+    101 => (0=>"11111111", 1=>"11001100", 2=>"01110000"),  -- FFCC70
+    102 => (0=>"10110111", 1=>"11110000", 2=>"11110000"),  -- B7F0F0
+    104 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    105 => (0=>"11011100", 1=>"00000011", 2=>"00000011"),  -- DC0303
+    107 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    108 => (0=>"00000011", 1=>"00000011", 2=>"10110111"),  -- 0303B7
+    109 => (0=>"11110000", 1=>"10100110", 2=>"01110000"),  -- F0A670
+    110 => (0=>"10000100", 1=>"10000100", 2=>"11111111"),  -- 8484FF
+    111 => (0=>"11111111", 1=>"11001100", 2=>"01110000"),  -- FFCC70
+    112 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    113 => (0=>"11111111", 1=>"11001100", 2=>"00000011"),  -- FFCC03
+    114 => (0=>"10110111", 1=>"10010100", 2=>"10000100"),  -- B79484
+    115 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    116 => (0=>"10000100", 1=>"10000100", 2=>"10110111"),  -- 8484B7
+    117 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    118 => (0=>"11011100", 1=>"10110111", 2=>"10010100"),  -- DCB794
+    120 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    121 => (0=>"11111111", 1=>"11001100", 2=>"00000011"),  -- FFCC03
+    122 => (0=>"10110111", 1=>"10010100", 2=>"10000100"),  -- B79484
+    123 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    124 => (0=>"11111111", 1=>"10100110", 2=>"00000011"),  -- FFA603
+    125 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    126 => (0=>"11011100", 1=>"10110111", 2=>"10010100"),  -- DCB794
+    128 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    129 => (0=>"11111111", 1=>"11001100", 2=>"00000011"),  -- FFCC03
+    130 => (0=>"10110111", 1=>"10010100", 2=>"10000100"),  -- B79484
+    131 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    132 => (0=>"10000100", 1=>"10000100", 2=>"10110111"),  -- 8484B7
+    133 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    134 => (0=>"11011100", 1=>"10110111", 2=>"10010100"),  -- DCB794
+    136 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    137 => (0=>"11011100", 1=>"00000011", 2=>"00000011"),  -- DC0303
+    138 => (0=>"10010100", 1=>"11111111", 2=>"10010100"),  -- 94FF94
+    139 => (0=>"10110111", 1=>"10110111", 2=>"10110111"),  -- B7B7B7
+    140 => (0=>"00000011", 1=>"11011100", 2=>"00000011"),  -- 03DC03
+    141 => (0=>"11110000", 1=>"10010100", 2=>"10010100"),  -- F09494
+    142 => (0=>"10110111", 1=>"10000100", 2=>"00000011"),  -- B78403
+    143 => (0=>"11111111", 1=>"11001100", 2=>"10100110"),  -- FFCCA6
+    144 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    145 => (0=>"11011100", 1=>"00000011", 2=>"00000011"),  -- DC0303
+    146 => (0=>"10110111", 1=>"10110111", 2=>"10110111"),  -- B7B7B7
+    148 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    149 => (0=>"11110000", 1=>"10010100", 2=>"10010100"),  -- F09494
+    150 => (0=>"11011100", 1=>"11011100", 2=>"11011100"),  -- DCDCDC
+    151 => (0=>"11111111", 1=>"11001100", 2=>"10100110"),  -- FFCCA6
+    152 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    153 => (0=>"11011100", 1=>"10000100", 2=>"00000011"),  -- DC8403
+    154 => (0=>"11111111", 1=>"11011100", 2=>"10110111"),  -- FFDCB7
+    155 => (0=>"11110000", 1=>"11110000", 2=>"00000011"),  -- F0F003
+    156 => (0=>"10100110", 1=>"11110000", 2=>"10100110"),  -- A6F0A6
+    157 => (0=>"10110111", 1=>"10110111", 2=>"10110111"),  -- B7B7B7
+    158 => (0=>"10110111", 1=>"11111111", 2=>"10110111"),  -- B7FFB7
+    159 => (0=>"11110000", 1=>"11110000", 2=>"11110000"),  -- F0F0F0
+    160 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    161 => (0=>"11011100", 1=>"10000100", 2=>"00000011"),  -- DC8403
+    162 => (0=>"10000100", 1=>"11001100", 2=>"10000100"),  -- 84CC84
+    163 => (0=>"11001100", 1=>"01110000", 2=>"00000011"),  -- CC7003
+    164 => (0=>"10100110", 1=>"11110000", 2=>"10100110"),  -- A6F0A6
+    165 => (0=>"10110111", 1=>"10110111", 2=>"10110111"),  -- B7B7B7
+    166 => (0=>"10110111", 1=>"11111111", 2=>"10110111"),  -- B7FFB7
+    167 => (0=>"11110000", 1=>"11110000", 2=>"11110000"),  -- F0F0F0
+    168 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    169 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    170 => (0=>"01110000", 1=>"01110000", 2=>"01110000"),  -- 707070
+    171 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    172 => (0=>"00000011", 1=>"00000011", 2=>"11110000"),  -- 0303F0
+    174 => (0=>"11001100", 1=>"10010100", 2=>"11001100"),  -- CC94CC
+    176 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    177 => (0=>"10100110", 1=>"10010100", 2=>"01110000"),  -- A69470
+    178 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    179 => (0=>"11011100", 1=>"11001100", 2=>"10010100"),  -- DCCC94
+    180 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    182 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    183 => (0=>"11110000", 1=>"11011100", 2=>"10100110"),  -- F0DCA6
+    184 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    185 => (0=>"11011100", 1=>"10110111", 2=>"11001100"),  -- DCB7CC
+    186 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    188 => (0=>"10010100", 1=>"10010100", 2=>"10010100"),  -- 949494
+    189 => (0=>"11111111", 1=>"11011100", 2=>"11011100"),  -- FFDCDC
+    190 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    191 => (0=>"11110000", 1=>"11011100", 2=>"10100110"),  -- F0DCA6
+    192 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    193 => (0=>"11111111", 1=>"00000011", 2=>"00000011"),  -- FF0303
+    194 => (0=>"11011100", 1=>"11011100", 2=>"11011100"),  -- DCDCDC
+    195 => (0=>"11111111", 1=>"11111111", 2=>"00000011"),  -- FFFF03
+    196 => (0=>"10110111", 1=>"10100110", 2=>"10000100"),  -- B7A684
+    198 => (0=>"11011100", 1=>"10110111", 2=>"10010100"),  -- DCB794
+    199 => (0=>"11110000", 1=>"11110000", 2=>"11110000"),  -- F0F0F0
+    200 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    201 => (0=>"11111111", 1=>"10000100", 2=>"10000100"),  -- FF8484
+    202 => (0=>"11001100", 1=>"10110111", 2=>"10000100"),  -- CCB784
+    203 => (0=>"11111111", 1=>"11111111", 2=>"10010100"),  -- FFFF94
+    204 => (0=>"10110111", 1=>"01110000", 2=>"10000100"),  -- B77084
+    205 => (0=>"11110000", 1=>"10110111", 2=>"10010100"),  -- F0B794
+    206 => (0=>"11110000", 1=>"11011100", 2=>"10110111"),  -- F0DCB7
+    207 => (0=>"11011100", 1=>"11011100", 2=>"11011100"),  -- DCDCDC
+    208 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    209 => (0=>"11111111", 1=>"10000100", 2=>"10000100"),  -- FF8484
+    210 => (0=>"10100110", 1=>"10100110", 2=>"10100110"),  -- A6A6A6
+    211 => (0=>"11111111", 1=>"11111111", 2=>"10010100"),  -- FFFF94
+    212 => (0=>"10110111", 1=>"01110000", 2=>"10000100"),  -- B77084
+    213 => (0=>"11110000", 1=>"10110111", 2=>"10010100"),  -- F0B794
+    214 => (0=>"10110111", 1=>"10110111", 2=>"10110111"),  -- B7B7B7
+    215 => (0=>"11011100", 1=>"11011100", 2=>"11011100"),  -- DCDCDC
+    216 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    217 => (0=>"11111111", 1=>"00000011", 2=>"10010100"),  -- FF0394
+    218 => (0=>"11011100", 1=>"11001100", 2=>"10010100"),  -- DCCC94
+    219 => (0=>"11110000", 1=>"11011100", 2=>"10110111"),  -- F0DCB7
+    220 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    221 => (0=>"11111111", 1=>"10010100", 2=>"00000011"),  -- FF9403
+    222 => (0=>"10100110", 1=>"01110000", 2=>"10000100"),  -- A67084
+    224 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    225 => (0=>"11111111", 1=>"00000011", 2=>"10010100"),  -- FF0394
+    226 => (0=>"11011100", 1=>"11001100", 2=>"10010100"),  -- DCCC94
+    227 => (0=>"11110000", 1=>"11011100", 2=>"10110111"),  -- F0DCB7
+    228 => (0=>"11011100", 1=>"00000011", 2=>"00000011"),  -- DC0303
+    229 => (0=>"11111111", 1=>"10010100", 2=>"00000011"),  -- FF9403
+    230 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    232 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    234 => (0=>"11001100", 1=>"11001100", 2=>"00000011"),  -- CCCC03
+    235 => (0=>"11011100", 1=>"11111111", 2=>"00000011"),  -- DCFF03
+    236 => (0=>"11001100", 1=>"11001100", 2=>"11001100"),  -- CCCCCC
+    240 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+    248 => (0=>"00000011", 1=>"00000011", 2=>"00000011"),  -- 030303
+		others => (others => (others => '1'))
+	);
+
+  -- table of sprite heights
+  type prom_a is array (natural range <>) of integer range 0 to 3;
+  constant sprite_prom : prom_a(0 to 31) :=
+  (
+    0 => 0,
+    1 => 0,
+    8 => 0,
+    9 => 0,
+    12 => 2,
+    13 => 2,
+    14 => 2,
+    15 => 2,
+    16 => 0,
+    23 => 0,
+    24 => 0,
+    27 => 0,
+    others => 1
+  );
+  
+end package platform_variant_pkg;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.qip b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.qip
new file mode 100644
index 00000000..d4720390
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.vhd
new file mode 100644
index 00000000..ebe4c7e7
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/pll_mist.vhd	
@@ -0,0 +1,461 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_mist.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_mist IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_mist;
+
+
+ARCHITECTURE SYN OF pll_mist IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(2);
+	sub_wire4    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	locked    <= sub_wire3;
+	c0    <= sub_wire4;
+	c2    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 44,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 11,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 27,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 88,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 9000,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 299,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire7,
+		clk => sub_wire0,
+		locked => sub_wire3
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "44.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "11.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "88.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.897000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "44"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "11"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "88"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "44.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "11.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "88.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89700000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "44"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "88"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9000"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "299"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/Roms.txt b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/Roms.txt
new file mode 100644
index 00000000..c6db1e07
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/Roms.txt	
@@ -0,0 +1,37 @@
+ROM_START( ldrun )
+	ROM_REGION( 0x10000, "maincpu", 0 )
+	ROM_LOAD( "lr-a-4e",      0x0000, 0x2000, CRC(5d7e2a4d) SHA1(fe8aeff360f6c3a8606d67a8b95148c3c2ef7267) )
+	ROM_LOAD( "lr-a-4d",      0x2000, 0x2000, CRC(96f20473) SHA1(e400c43f3f32e12f68ca204c60bcebdb2b3da55d) )
+	ROM_LOAD( "lr-a-4b",      0x4000, 0x2000, CRC(b041c4a9) SHA1(77768b03ea2497e25c3e47b68a0eb2fe3e9aea35) )
+	ROM_LOAD( "lr-a-4a",      0x6000, 0x2000, CRC(645e42aa) SHA1(c806ffce7ece418bad86854c987f78c70c13e492) )
+
+	ROM_REGION( 0x10000, "irem_audio:iremsound", 0 )   /* 64k for the audio CPU (6803) */
+	ROM_LOAD( "lr-a-3f",      0xc000, 0x2000, CRC(7a96accd) SHA1(e94815dbfaabbb562df8f3298060aa6bd7825904) )
+	ROM_LOAD( "lr-a-3h",      0xe000, 0x2000, CRC(3f7f3939) SHA1(7ee25a21e74995bfb36ac11b45d384b33a6d8515) )
+
+	ROM_REGION( 0x6000, "gfx1", 0 )
+	ROM_LOAD( "lr-e-2d",      0x0000, 0x2000, CRC(24f9b58d) SHA1(e33224b910d37aaa85713b954c8dd50996245a8c) )    /* characters */
+	ROM_LOAD( "lr-e-2j",      0x2000, 0x2000, CRC(43175e08) SHA1(9dbafb27d46cf7df35f343a8753e8d91ea706993) )
+	ROM_LOAD( "lr-e-2f",      0x4000, 0x2000, CRC(e0317124) SHA1(b766bd21e2da1673d2054148f62d61c33c95d38e) )
+
+	ROM_REGION( 0x6000, "gfx2", 0 )
+	ROM_LOAD( "lr-b-4k",      0x0000, 0x2000, CRC(8141403e) SHA1(65fa6bc872fb07c71aacbbcc35cee766b2877896) )    /* sprites */
+	ROM_LOAD( "lr-b-3n",      0x2000, 0x2000, CRC(55154154) SHA1(35304676e1ab55adccdabdc766a4e0e0901d3cd0) )
+	ROM_LOAD( "lr-b-4c",      0x4000, 0x2000, CRC(924e34d0) SHA1(6a841419797a129235fc7d0405a5be55e8d703da) )
+
+	ROM_REGION( 0x20, "spr_height_prom", 0 )
+	ROM_LOAD( "lr-b-5p",      0x00, 0x20, CRC(e01f69e2) SHA1(0d00ef348025ea4a9c274a7e3dbb006217d8449d) )    /* sprite height, one entry per 32 */
+
+	ROM_REGION( 0x300, "spr_color_proms", 0 )
+	ROM_LOAD( "lr-b-1m",      0x0000, 0x0100, CRC(4bae1c25) SHA1(17a9e2567d9d648dca69510bb201f8af0738b068) )    /* sprite palette red component */
+	ROM_LOAD( "lr-b-1n",      0x0100, 0x0100, CRC(9cd3db94) SHA1(bff95965f946df0e4af1f99db5b2468bf1d4403f) )    /* sprite palette green component */
+	ROM_LOAD( "lr-b-1l",      0x0200, 0x0100, CRC(08d8cf9a) SHA1(a46213e0dc04e44b0544401eb341fd49eef331dd) )    /* sprite palette blue component */
+
+	ROM_REGION( 0x300, "chr_color_proms", 0 )
+	ROM_LOAD( "lr-e-3m",      0x0000, 0x0100, CRC(53040416) SHA1(2c6915164d1c31afc60a21b557abdf023d5b3f46) )    /* character palette red component */
+	ROM_LOAD( "lr-e-3l",      0x0100, 0x0100, CRC(67786037) SHA1(cd40dfd94295afe57139733752643cf48b8566b1) )    /* character palette green component */
+	ROM_LOAD( "lr-e-3n",      0x0200, 0x0100, CRC(5b716837) SHA1(e3ea250891fec43a97e92ac1c3a4fbb5ee2d4a4d) )    /* character palette blue component */
+
+	ROM_REGION( 0x100, "timing", 0 )
+	ROM_LOAD( "lr-b-6f",      0x000, 0x100, CRC(34d88d3c) SHA1(727f4c5cfff33538886fa0a29fd119aa085d7008) )    /* video timing - common to the other games */
+ROM_END
\ No newline at end of file
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3e-.bin.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3e-.bin.hex
new file mode 100644
index 00000000..2f175a44
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3e-.bin.hex	
@@ -0,0 +1,513 @@
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3f-.bin.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3f-.bin.hex
new file mode 100644
index 00000000..5ef7e119
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3f-.bin.hex	
@@ -0,0 +1,513 @@
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3h-.bin.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3h-.bin.hex
new file mode 100644
index 00000000..e5840791
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-3h-.bin.hex	
@@ -0,0 +1,513 @@
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-4d-c.bin.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-4d-c.bin.hex
new file mode 100644
index 00000000..3d9223bc
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-4d-c.bin.hex	
@@ -0,0 +1,1025 @@
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-4e-c.bin.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-4e-c.bin.hex
new file mode 100644
index 00000000..c97273bc
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/a-4e-c.bin.hex	
@@ -0,0 +1,1025 @@
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-3m-.bin.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-3m-.bin.hex
new file mode 100644
index 00000000..e1058caf
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-3m-.bin.hex	
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new file mode 100644
index 00000000..425c676a
--- /dev/null
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new file mode 100644
index 00000000..91d24ab9
--- /dev/null
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new file mode 100644
index 00000000..cdee4044
--- /dev/null
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new file mode 100644
index 00000000..d5f6935c
--- /dev/null
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new file mode 100644
index 00000000..577402e3
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4e-.bin.hex	
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4f-.bin.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4f-.bin.hex
new file mode 100644
index 00000000..1cc6cd57
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/b-4f-.bin.hex	
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new file mode 100644
index 00000000..d3010c60
--- /dev/null
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new file mode 100644
index 00000000..8d5ee2a8
--- /dev/null
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new file mode 100644
index 00000000..1119f163
--- /dev/null
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new file mode 100644
index 00000000..b9e915b4
--- /dev/null
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new file mode 100644
index 00000000..4b8f2dec
--- /dev/null
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4c-a.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4c-a.hex
new file mode 100644
index 00000000..e25956f5
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4c-a.hex	
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4d-a.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4d-a.hex
new file mode 100644
index 00000000..c57078fd
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4d-a.hex	
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4e-a.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4e-a.hex
new file mode 100644
index 00000000..19086346
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/g-4e-a.hex	
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum.zip b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum.zip
new file mode 100644
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new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-1l-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-1l-.bin
new file mode 100644
index 0000000000000000000000000000000000000000..922551d251f217082012a03bdc020edcecd4e0ef
GIT binary patch
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-1m-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-1m-.bin
new file mode 100644
index 0000000000000000000000000000000000000000..e982e9d42a3336fa5e8a2bde422d7e0c4a62cd56
GIT binary patch
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literal 0
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-1n-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-1n-.bin
new file mode 100644
index 0000000000000000000000000000000000000000..0d0c36823e0d9c1fe6434998cc3c29f2037a2c02
GIT binary patch
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HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-3m-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-3m-.bin
new file mode 100644
index 0000000000000000000000000000000000000000..eede9a79c05b648cc9644784442366adcfb7b7a3
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-3n-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-3n-.bin
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-5f-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-5f-.bin
new file mode 100644
index 0000000000000000000000000000000000000000..9998b1851c2f799d68b021d47c31d6a79d23e96a
GIT binary patch
literal 32
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-6f-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-6f-.bin
new file mode 100644
index 00000000..9b9dcba0
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/b-6f-.bin	
@@ -0,0 +1 @@
+























\ No newline at end of file
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-1f-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-1f-.bin
new file mode 100644
index 0000000000000000000000000000000000000000..06590b345d51c0998eb700e9106141e564e4b943
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-1h-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-1h-.bin
new file mode 100644
index 0000000000000000000000000000000000000000..39abc7d50b857bce1589dc3c0df506792f786cfa
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-1j-.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-1j-.bin
new file mode 100644
index 0000000000000000000000000000000000000000..7f7e332ce4f63a80fbc247ef2bdec3c16cab2c97
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-4c-a.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-4c-a.bin
new file mode 100644
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new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-4e-a.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/g-4e-a.bin
new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/make_proms.bat b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/make_proms.bat
new file mode 100644
index 00000000..d22c0b3d
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/make_proms.bat	
@@ -0,0 +1,15 @@
+copy /b a-4e-c.bin + a-4d-c.bin prog.bin
+make_vhdl_prom.exe prog.bin prog.vhd
+
+
+copy /b a-3e-.bin + a-3f-.bin + a-3h-.bin snd.bin
+make_vhdl_prom.exe snd.bin snd_prg.vhd
+
+copy /b prog.bin + snd.bin KUNGFUM.ROM
+
+
+
+copy /b b-4k-.bin + b-4f-.bin + b-4l-.bin + b-4h-.bin spr1.bin
+copy /b b-3n-.bin + b-4n-.bin + b-4m-.bin + b-3m-.bin spr2.bin
+copy /b b-4c-.bin + b-4e-.bin + b-4d-.bin + b-4a-.bin spr3.bin
+pause
\ No newline at end of file
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/make_vhdl_prom.exe b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/make_vhdl_prom.exe
new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/prog.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/prog.bin
new file mode 100644
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D7nvmt

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/prog.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/prog.vhd
new file mode 100644
index 00000000..f95fd9cf
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/prog.vhd	
@@ -0,0 +1,2070 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity prog is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(14 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of prog is
+	type rom is array(0 to  32767) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"F3",X"ED",X"56",X"31",X"00",X"F0",X"21",X"00",X"E0",X"11",X"01",X"E0",X"01",X"FF",X"0F",X"36",
+		X"00",X"ED",X"B0",X"21",X"25",X"EB",X"22",X"03",X"EB",X"DB",X"04",X"CB",X"7F",X"CA",X"66",X"76",
+		X"CD",X"8F",X"05",X"21",X"CC",X"05",X"11",X"06",X"EA",X"01",X"78",X"00",X"ED",X"B0",X"2A",X"3F",
+		X"06",X"7D",X"6C",X"67",X"18",X"4C",X"C7",X"C7",X"08",X"D9",X"2A",X"03",X"EB",X"11",X"20",X"C0",
+		X"01",X"C0",X"00",X"ED",X"B0",X"3A",X"02",X"E9",X"32",X"00",X"A0",X"3A",X"03",X"E9",X"32",X"00",
+		X"B0",X"FD",X"E5",X"DD",X"E5",X"C3",X"8D",X"00",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"ED",X"45",X"63",X"AD",X"9C",X"52",X"72",X"CF",X"87",X"41",
+		X"54",X"37",X"A7",X"43",X"91",X"51",X"A7",X"43",X"91",X"51",X"9F",X"B8",X"E5",X"D6",X"85",X"56",
+		X"35",X"23",X"22",X"80",X"E9",X"21",X"17",X"E9",X"34",X"FB",X"C3",X"7E",X"48",X"3A",X"00",X"E0",
+		X"A7",X"FA",X"F8",X"01",X"DB",X"04",X"CB",X"67",X"20",X"1D",X"21",X"05",X"E0",X"CB",X"7E",X"20",
+		X"16",X"CB",X"46",X"DB",X"00",X"20",X"09",X"E6",X"02",X"20",X"0C",X"CB",X"C6",X"C3",X"F0",X"01",
+		X"E6",X"01",X"C2",X"F0",X"01",X"CB",X"86",X"DB",X"04",X"CB",X"5F",X"20",X"10",X"21",X"04",X"E9",
+		X"CB",X"4E",X"28",X"09",X"21",X"0E",X"E8",X"35",X"F2",X"F0",X"01",X"36",X"08",X"3A",X"00",X"E0",
+		X"FE",X"06",X"3E",X"47",X"28",X"02",X"ED",X"5F",X"21",X"10",X"E0",X"86",X"77",X"23",X"86",X"77",
+		X"21",X"14",X"E0",X"34",X"7E",X"E6",X"03",X"16",X"00",X"5F",X"3A",X"00",X"E0",X"21",X"7E",X"00",
+		X"FE",X"06",X"28",X"13",X"21",X"6E",X"00",X"3A",X"80",X"E0",X"E6",X"38",X"FE",X"20",X"38",X"02",
+		X"3E",X"18",X"0F",X"4F",X"06",X"00",X"09",X"19",X"7E",X"21",X"15",X"E0",X"86",X"77",X"23",X"86",
+		X"77",X"23",X"86",X"77",X"CD",X"05",X"0D",X"CD",X"48",X"0D",X"CD",X"2F",X"48",X"CD",X"E5",X"0D",
+		X"3A",X"01",X"E0",X"A7",X"20",X"07",X"3A",X"13",X"E9",X"A7",X"C2",X"17",X"02",X"CD",X"F8",X"03",
+		X"3A",X"00",X"E0",X"FE",X"0B",X"D2",X"DD",X"01",X"3E",X"18",X"32",X"00",X"EB",X"21",X"25",X"EB",
+		X"22",X"03",X"EB",X"22",X"01",X"EB",X"3A",X"00",X"E0",X"87",X"5F",X"16",X"00",X"21",X"56",X"01",
+		X"19",X"5E",X"23",X"56",X"EB",X"E9",X"C4",X"01",X"C4",X"01",X"BE",X"01",X"68",X"01",X"68",X"01",
+		X"B4",X"01",X"68",X"01",X"B9",X"01",X"BE",X"01",X"CD",X"3F",X"41",X"CD",X"2C",X"40",X"3A",X"80",
+		X"E0",X"E6",X"07",X"FE",X"04",X"28",X"08",X"CD",X"E5",X"40",X"CD",X"B3",X"1C",X"18",X"06",X"CD",
+		X"B3",X"1C",X"CD",X"E5",X"40",X"CD",X"B6",X"47",X"3A",X"00",X"E1",X"A7",X"28",X"0E",X"FE",X"0A",
+		X"38",X"05",X"CD",X"DE",X"37",X"18",X"08",X"CD",X"95",X"35",X"18",X"03",X"CD",X"AC",X"12",X"CD",
+		X"C7",X"2F",X"3A",X"3F",X"E3",X"A7",X"C4",X"C1",X"2E",X"CD",X"C0",X"39",X"CD",X"72",X"2D",X"CD",
+		X"06",X"2F",X"18",X"10",X"CD",X"24",X"4D",X"18",X"0B",X"CD",X"36",X"54",X"18",X"06",X"CD",X"00",
+		X"40",X"CD",X"E5",X"40",X"3A",X"00",X"EB",X"A7",X"28",X"13",X"47",X"FD",X"2A",X"01",X"EB",X"AF",
+		X"11",X"08",X"00",X"FD",X"77",X"04",X"FD",X"77",X"05",X"FD",X"19",X"10",X"F6",X"3A",X"00",X"E0",
+		X"FE",X"06",X"3E",X"37",X"28",X"02",X"ED",X"5F",X"21",X"12",X"E0",X"86",X"77",X"23",X"86",X"77",
+		X"DD",X"E1",X"FD",X"E1",X"D9",X"08",X"FB",X"C9",X"F5",X"3E",X"18",X"32",X"00",X"EB",X"21",X"25",
+		X"EB",X"22",X"03",X"EB",X"22",X"01",X"EB",X"F1",X"3C",X"C4",X"AE",X"7A",X"CD",X"F8",X"03",X"CD",
+		X"05",X"0D",X"CD",X"E5",X"0D",X"18",X"AD",X"31",X"00",X"F0",X"3E",X"01",X"32",X"01",X"E0",X"AF",
+		X"32",X"00",X"E0",X"FB",X"CD",X"78",X"51",X"3E",X"FF",X"32",X"06",X"E0",X"21",X"80",X"E0",X"11",
+		X"81",X"E0",X"01",X"1F",X"00",X"36",X"00",X"ED",X"B0",X"DB",X"03",X"E6",X"01",X"20",X"08",X"3E",
+		X"08",X"32",X"80",X"E0",X"32",X"90",X"E0",X"CD",X"6F",X"05",X"32",X"84",X"E0",X"32",X"94",X"E0",
+		X"21",X"05",X"E0",X"CB",X"BE",X"AF",X"32",X"00",X"E0",X"DB",X"04",X"E6",X"02",X"21",X"10",X"E9",
+		X"28",X"0B",X"3A",X"02",X"E0",X"E6",X"01",X"28",X"04",X"CB",X"C6",X"18",X"02",X"CB",X"86",X"21",
+		X"85",X"E0",X"CB",X"4E",X"20",X"0F",X"CB",X"CE",X"CD",X"0D",X"52",X"3E",X"E1",X"CD",X"0F",X"57",
+		X"3E",X"70",X"CD",X"0F",X"57",X"CD",X"57",X"11",X"AF",X"32",X"07",X"E0",X"32",X"08",X"E0",X"CD",
+		X"49",X"04",X"3E",X"04",X"32",X"00",X"E0",X"3E",X"24",X"CD",X"FE",X"0D",X"DB",X"04",X"CB",X"67",
+		X"28",X"0C",X"CB",X"6F",X"20",X"08",X"21",X"04",X"E9",X"CB",X"46",X"C2",X"9C",X"03",X"3A",X"00",
+		X"E0",X"FE",X"0B",X"CA",X"3A",X"03",X"FE",X"0C",X"CA",X"C0",X"02",X"CD",X"B8",X"0F",X"18",X"DC",
+		X"3E",X"00",X"CD",X"FE",X"0D",X"3E",X"22",X"CD",X"FE",X"0D",X"3E",X"E1",X"CD",X"82",X"05",X"3E",
+		X"38",X"CD",X"82",X"05",X"3E",X"01",X"CD",X"82",X"05",X"21",X"09",X"E7",X"7E",X"A7",X"FA",X"EA",
+		X"02",X"35",X"CD",X"97",X"2F",X"CD",X"5F",X"05",X"18",X"EA",X"11",X"00",X"00",X"D5",X"3E",X"03",
+		X"CD",X"82",X"05",X"D1",X"2A",X"03",X"E0",X"7D",X"B4",X"28",X"22",X"7B",X"C6",X"01",X"27",X"5F",
+		X"ED",X"52",X"19",X"30",X"02",X"5D",X"54",X"7D",X"93",X"27",X"6F",X"7C",X"9A",X"27",X"67",X"22",
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+		X"D4",X"46",X"49",X"47",X"48",X"54",X"45",X"52",X"53",X"FD",X"90",X"D2",X"43",X"4F",X"49",X"4E",
+		X"20",X"4D",X"4F",X"44",X"45",X"FF",X"54",X"41",X"42",X"4C",X"45",X"20",X"20",X"FF",X"55",X"50",
+		X"52",X"49",X"47",X"48",X"54",X"FF",X"45",X"41",X"53",X"59",X"20",X"20",X"20",X"20",X"20",X"FF",
+		X"44",X"49",X"46",X"46",X"49",X"43",X"55",X"4C",X"54",X"FF",X"53",X"4C",X"4F",X"57",X"FF",X"46",
+		X"41",X"53",X"54",X"FF",X"20",X"20",X"20",X"20",X"20",X"46",X"52",X"45",X"45",X"20",X"20",X"20",
+		X"50",X"4C",X"41",X"59",X"20",X"20",X"20",X"FF",X"49",X"4E",X"54",X"45",X"52",X"46",X"41",X"43",
+		X"45",X"FF",X"52",X"45",X"41",X"44",X"20",X"44",X"41",X"54",X"41",X"FF",X"FD",X"57",X"D5",X"54",
+		X"49",X"4D",X"4D",X"49",X"4E",X"47",X"FF",X"FE",X"14",X"FD",X"50",X"D1",X"30",X"31",X"20",X"44",
+		X"49",X"50",X"20",X"53",X"57",X"49",X"54",X"43",X"48",X"FD",X"90",X"D1",X"30",X"32",X"20",X"49",
+		X"2F",X"4F",X"20",X"50",X"4F",X"52",X"54",X"FD",X"D0",X"D1",X"30",X"33",X"20",X"53",X"4F",X"55",
+		X"4E",X"44",X"FD",X"10",X"D2",X"30",X"34",X"20",X"43",X"48",X"41",X"52",X"41",X"43",X"54",X"45",
+		X"52",X"FD",X"50",X"D2",X"30",X"35",X"20",X"43",X"4F",X"4C",X"4F",X"52",X"FD",X"90",X"D2",X"30",
+		X"36",X"20",X"43",X"52",X"4F",X"53",X"53",X"20",X"48",X"41",X"54",X"43",X"48",X"20",X"50",X"41",
+		X"54",X"54",X"45",X"52",X"4E",X"FF",X"FE",X"14",X"FD",X"15",X"D1",X"53",X"4F",X"55",X"4E",X"44",
+		X"FD",X"50",X"D1",X"30",X"31",X"20",X"59",X"45",X"4C",X"4C",X"20",X"4F",X"46",X"20",X"50",X"4C",
+		X"41",X"59",X"45",X"52",X"28",X"4A",X"55",X"4D",X"50",X"2D",X"4B",X"49",X"43",X"4B",X"53",X"29",
+		X"FD",X"93",X"D1",X"43",X"52",X"45",X"44",X"49",X"54",X"20",X"41",X"44",X"44",X"49",X"4E",X"47",
+		X"20",X"53",X"4F",X"55",X"4E",X"44",X"FD",X"D0",X"D1",X"30",X"32",X"20",X"59",X"45",X"4C",X"4C",
+		X"20",X"4F",X"46",X"20",X"50",X"4C",X"41",X"59",X"45",X"52",X"28",X"50",X"55",X"4E",X"43",X"48",
+		X"45",X"53",X"2C",X"4B",X"49",X"43",X"4B",X"53",X"29",X"FD",X"10",X"D2",X"30",X"33",X"20",X"47",
+		X"52",X"4F",X"41",X"4E",X"20",X"4F",X"46",X"20",X"50",X"4C",X"41",X"59",X"45",X"52",X"20",X"4F",
+		X"52",X"20",X"45",X"4E",X"45",X"4D",X"59",X"FD",X"50",X"D2",X"30",X"34",X"20",X"4C",X"41",X"55",
+		X"47",X"48",X"49",X"4E",X"47",X"20",X"56",X"4F",X"49",X"43",X"45",X"20",X"4F",X"46",X"20",X"45",
+		X"4E",X"45",X"4D",X"49",X"45",X"53",X"2D",X"31",X"FD",X"90",X"D2",X"30",X"35",X"20",X"4C",X"41",
+		X"55",X"47",X"48",X"49",X"4E",X"47",X"20",X"56",X"4F",X"49",X"43",X"45",X"20",X"4F",X"46",X"20",
+		X"45",X"4E",X"45",X"4D",X"49",X"45",X"53",X"2D",X"32",X"FD",X"D0",X"D2",X"30",X"36",X"20",X"42",
+		X"55",X"52",X"53",X"54",X"49",X"4E",X"47",X"20",X"4F",X"46",X"20",X"50",X"41",X"50",X"45",X"52",
+		X"20",X"42",X"41",X"4C",X"4C",X"FD",X"13",X"D3",X"42",X"55",X"52",X"53",X"54",X"49",X"4E",X"47",
+		X"20",X"4F",X"46",X"20",X"44",X"52",X"41",X"47",X"4F",X"4E",X"27",X"53",X"20",X"45",X"47",X"47",
+		X"FD",X"50",X"D3",X"30",X"37",X"20",X"53",X"48",X"52",X"49",X"45",X"4B",X"20",X"4F",X"46",X"20",
+		X"50",X"4C",X"41",X"59",X"45",X"52",X"FD",X"90",X"D3",X"30",X"38",X"20",X"50",X"4C",X"41",X"59",
+		X"45",X"52",X"20",X"52",X"55",X"4E",X"4E",X"49",X"4E",X"47",X"FD",X"D0",X"D3",X"30",X"39",X"20",
+		X"48",X"49",X"54",X"54",X"49",X"4E",X"47",X"20",X"53",X"4F",X"55",X"4E",X"44",X"FD",X"10",X"D4",
+		X"31",X"30",X"20",X"53",X"57",X"49",X"53",X"48",X"49",X"4E",X"47",X"20",X"53",X"4F",X"55",X"4E",
+		X"44",X"FD",X"50",X"D4",X"31",X"31",X"20",X"42",X"55",X"52",X"53",X"54",X"49",X"4E",X"47",X"20",
+		X"4F",X"46",X"20",X"53",X"4E",X"41",X"4B",X"45",X"20",X"50",X"4F",X"54",X"FD",X"90",X"D4",X"31",
+		X"32",X"20",X"42",X"49",X"54",X"49",X"4E",X"47",X"20",X"53",X"4F",X"55",X"4E",X"44",X"FD",X"D0",
+		X"D4",X"31",X"33",X"20",X"53",X"4F",X"55",X"4E",X"44",X"20",X"4F",X"46",X"20",X"4B",X"4E",X"49",
+		X"56",X"45",X"53",X"2C",X"42",X"4F",X"4F",X"4D",X"45",X"52",X"41",X"4E",X"47",X"53",X"FD",X"10",
+		X"D5",X"31",X"34",X"20",X"43",X"4F",X"55",X"4E",X"54",X"49",X"4E",X"47",X"20",X"50",X"4F",X"49",
+		X"4E",X"54",X"53",X"FD",X"50",X"D5",X"31",X"35",X"20",X"47",X"41",X"4D",X"45",X"20",X"53",X"54",
+		X"41",X"52",X"54",X"FD",X"90",X"D5",X"31",X"36",X"20",X"42",X"47",X"4D",X"FD",X"D0",X"D5",X"31",
+		X"37",X"20",X"43",X"4F",X"4D",X"50",X"4C",X"45",X"54",X"49",X"4F",X"4E",X"20",X"4F",X"46",X"20",
+		X"45",X"41",X"43",X"48",X"20",X"50",X"41",X"54",X"54",X"45",X"52",X"4E",X"FD",X"10",X"D6",X"31",
+		X"38",X"20",X"43",X"4F",X"4D",X"50",X"4C",X"45",X"54",X"49",X"4F",X"4E",X"20",X"4F",X"46",X"20",
+		X"47",X"41",X"4D",X"45",X"FD",X"50",X"D6",X"31",X"39",X"20",X"47",X"41",X"4D",X"45",X"20",X"4F",
+		X"56",X"45",X"52",X"FD",X"90",X"D6",X"32",X"30",X"20",X"54",X"49",X"4D",X"45",X"20",X"55",X"50",
+		X"20",X"57",X"41",X"52",X"4E",X"49",X"4E",X"47",X"FD",X"D0",X"D6",X"32",X"31",X"20",X"41",X"44",
+		X"44",X"49",X"54",X"49",X"4F",X"4E",X"41",X"4C",X"20",X"46",X"49",X"47",X"48",X"54",X"45",X"52",
+		X"FD",X"16",X"D7",X"4D",X"55",X"53",X"49",X"43",X"20",X"45",X"4E",X"44",X"FF",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/snd.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/snd.bin
new file mode 100644
index 0000000000000000000000000000000000000000..2bca293054d2562f68ae1940847100f0227edfdc
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/snd_prg.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/snd_prg.vhd
new file mode 100644
index 00000000..c3748bca
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/snd_prg.vhd	
@@ -0,0 +1,1558 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity snd_prg is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(14 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of snd_prg is
+	type rom is array(0 to  24575) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"00",X"00",X"01",X"80",X"40",X"02",X"B0",X"82",X"F0",X"01",X"B0",X"84",X"A0",X"01",X"50",
+		X"85",X"F0",X"10",X"00",X"95",X"F0",X"18",X"80",X"AE",X"70",X"03",X"A0",X"B2",X"10",X"08",X"00",
+		X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"01",
+		X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"01",
+		X"AA",X"98",X"26",X"10",X"80",X"28",X"8B",X"BA",X"10",X"0A",X"8B",X"AA",X"22",X"71",X"19",X"10",
+		X"10",X"AC",X"B1",X"00",X"CB",X"E9",X"25",X"31",X"80",X"01",X"0A",X"C8",X"00",X"AD",X"DA",X"04",
+		X"42",X"18",X"00",X"08",X"D9",X"88",X"9E",X"A8",X"17",X"21",X"98",X"11",X"0B",X"C8",X"AB",X"E9",
+		X"14",X"71",X"89",X"81",X"19",X"B9",X"9B",X"E9",X"25",X"51",X"99",X"82",X"0B",X"BC",X"AB",X"25",
+		X"53",X"09",X"98",X"0A",X"CB",X"AD",X"05",X"53",X"8A",X"A0",X"19",X"CA",X"BB",X"37",X"61",X"99",
+		X"A1",X"09",X"AB",X"C2",X"73",X"08",X"AA",X"88",X"89",X"CA",X"47",X"20",X"AA",X"89",X"98",X"AA",
+		X"37",X"78",X"99",X"89",X"80",X"A8",X"46",X"19",X"A9",X"89",X"88",X"A2",X"73",X"9A",X"99",X"A1",
+		X"2E",X"06",X"29",X"99",X"99",X"11",X"D0",X"71",X"99",X"89",X"81",X"0C",X"17",X"0A",X"88",X"98",
+		X"49",X"B3",X"69",X"A0",X"0B",X"14",X"C8",X"50",X"A8",X"0A",X"84",X"8B",X"62",X"C9",X"18",X"A3",
+		X"1E",X"25",X"AA",X"10",X"B2",X"3E",X"05",X"8C",X"10",X"A1",X"2B",X"87",X"8B",X"11",X"B0",X"3C",
+		X"06",X"8B",X"10",X"A1",X"1C",X"35",X"C9",X"39",X"A3",X"AB",X"72",X"D0",X"2A",X"03",X"F0",X"58",
+		X"C2",X"8A",X"48",X"D4",X"2D",X"03",X"C0",X"3E",X"05",X"9B",X"49",X"96",X"CB",X"51",X"C3",X"A9",
+		X"7B",X"C4",X"1B",X"3C",X"96",X"8D",X"11",X"12",X"DB",X"51",X"B8",X"02",X"00",X"F0",X"48",X"B0",
+		X"18",X"5B",X"B6",X"8B",X"03",X"A3",X"9F",X"31",X"B8",X"4A",X"11",X"E1",X"2A",X"81",X"09",X"4D",
+		X"03",X"A9",X"84",X"80",X"9B",X"58",X"A8",X"59",X"81",X"D2",X"1A",X"A7",X"A0",X"0A",X"20",X"9C",
+		X"7A",X"82",X"B2",X"92",X"D5",X"A8",X"3C",X"19",X"2B",X"31",X"C5",X"C2",X"A2",X"90",X"2C",X"5C",
+		X"3C",X"3A",X"3A",X"83",X"D4",X"C2",X"93",X"B1",X"1B",X"3B",X"3C",X"2A",X"31",X"C1",X"A6",X"C2",
+		X"A3",X"89",X"89",X"4A",X"81",X"4C",X"1B",X"86",X"98",X"3C",X"2C",X"01",X"39",X"9C",X"3B",X"26",
+		X"A1",X"D1",X"95",X"88",X"A8",X"11",X"82",X"A0",X"E1",X"A7",X"91",X"B2",X"A8",X"97",X"91",X"D3",
+		X"90",X"87",X"C0",X"A1",X"88",X"41",X"BA",X"18",X"2C",X"7B",X"3D",X"39",X"09",X"7D",X"18",X"82",
+		X"B5",X"88",X"D4",X"A2",X"C5",X"B1",X"99",X"2C",X"7A",X"1E",X"4A",X"3C",X"5B",X"91",X"A4",X"C2",
+		X"2A",X"A2",X"01",X"C2",X"3B",X"B1",X"22",X"F4",X"B3",X"D3",X"A2",X"D5",X"B1",X"A2",X"08",X"A7",
+		X"9B",X"3A",X"4E",X"49",X"2D",X"4B",X"3E",X"5A",X"2C",X"20",X"99",X"6B",X"80",X"04",X"C9",X"59",
+		X"99",X"13",X"C8",X"30",X"C2",X"A4",X"D1",X"28",X"B3",X"92",X"F0",X"30",X"C1",X"01",X"D2",X"01",
+		X"C2",X"81",X"BA",X"78",X"A0",X"12",X"C8",X"15",X"BA",X"6B",X"1D",X"33",X"9C",X"28",X"1E",X"15",
+		X"AA",X"01",X"2D",X"85",X"89",X"C4",X"88",X"B0",X"7A",X"9A",X"51",X"D0",X"06",X"D8",X"06",X"BB",
+		X"21",X"6D",X"94",X"0D",X"84",X"3C",X"C3",X"5B",X"D2",X"25",X"DA",X"34",X"CB",X"48",X"5D",X"82",
+		X"3F",X"85",X"B5",X"D1",X"28",X"F2",X"5D",X"4D",X"5A",X"0C",X"40",X"C1",X"10",X"A0",X"A7",X"B8",
+		X"97",X"AA",X"05",X"AA",X"04",X"B5",X"D2",X"81",X"98",X"1C",X"7A",X"98",X"39",X"B2",X"0A",X"7D",
+		X"4A",X"2B",X"3A",X"12",X"9D",X"22",X"9C",X"13",X"D5",X"B0",X"02",X"B8",X"12",X"AE",X"7C",X"01",
+		X"19",X"A2",X"09",X"95",X"B3",X"A8",X"81",X"3F",X"A7",X"99",X"11",X"A8",X"3B",X"A0",X"7E",X"32",
+		X"8D",X"15",X"D0",X"2A",X"5D",X"48",X"A8",X"21",X"D1",X"19",X"00",X"B3",X"80",X"A2",X"2C",X"A5",
+		X"9D",X"7B",X"02",X"90",X"B7",X"A8",X"01",X"B2",X"2F",X"39",X"09",X"12",X"F2",X"09",X"84",X"D3",
+		X"88",X"91",X"3E",X"10",X"89",X"10",X"2E",X"12",X"C1",X"01",X"A9",X"5A",X"08",X"08",X"4C",X"95",
+		X"A0",X"82",X"8C",X"38",X"90",X"83",X"9F",X"5A",X"93",X"90",X"A2",X"0A",X"03",X"AA",X"23",X"F2",
+		X"0B",X"20",X"8A",X"25",X"E0",X"29",X"80",X"97",X"D2",X"1B",X"10",X"88",X"83",X"C8",X"5A",X"92",
+		X"83",X"F1",X"3E",X"12",X"A0",X"82",X"B0",X"3B",X"02",X"C1",X"2A",X"93",X"9A",X"4A",X"18",X"81",
+		X"99",X"49",X"A3",X"A1",X"99",X"2B",X"7F",X"32",X"E0",X"28",X"A2",X"90",X"09",X"18",X"1A",X"89",
+		X"7B",X"B7",X"A1",X"1B",X"49",X"81",X"A2",X"90",X"00",X"A1",X"80",X"0A",X"42",X"F6",X"AA",X"4A",
+		X"00",X"91",X"08",X"92",X"A1",X"80",X"91",X"93",X"D3",X"B9",X"7F",X"41",X"F2",X"0A",X"10",X"88",
+		X"00",X"91",X"09",X"81",X"88",X"82",X"A8",X"6B",X"97",X"B8",X"39",X"90",X"2A",X"00",X"09",X"18",
+		X"00",X"B3",X"91",X"99",X"7B",X"81",X"87",X"F4",X"0E",X"38",X"A1",X"08",X"88",X"29",X"92",X"89",
+		X"10",X"99",X"38",X"C4",X"90",X"89",X"16",X"F1",X"3E",X"11",X"A1",X"09",X"18",X"80",X"80",X"80",
+		X"E7",X"F0",X"79",X"F3",X"1B",X"18",X"83",X"AA",X"39",X"82",X"93",X"F0",X"5B",X"93",X"91",X"9A",
+		X"48",X"98",X"7A",X"D5",X"8A",X"18",X"10",X"B1",X"2A",X"97",X"AB",X"68",X"A1",X"81",X"8A",X"49",
+		X"A3",X"4F",X"03",X"B0",X"80",X"2C",X"11",X"B5",X"8E",X"38",X"80",X"A3",X"99",X"2A",X"59",X"F4",
+		X"89",X"1A",X"28",X"A3",X"82",X"F0",X"28",X"8A",X"22",X"D1",X"4E",X"11",X"91",X"C3",X"0B",X"22",
+		X"E1",X"00",X"0C",X"38",X"92",X"9B",X"40",X"8A",X"97",X"A8",X"4D",X"28",X"00",X"B4",X"91",X"9C",
+		X"59",X"1A",X"01",X"82",X"E2",X"92",X"99",X"3A",X"88",X"12",X"D1",X"01",X"0E",X"29",X"3B",X"82",
+		X"2C",X"81",X"82",X"E2",X"02",X"E1",X"93",X"99",X"11",X"98",X"93",X"A0",X"1B",X"3A",X"4B",X"95",
+		X"0D",X"95",X"88",X"A2",X"2A",X"8A",X"22",X"AA",X"24",X"B9",X"03",X"B0",X"91",X"7A",X"92",X"89",
+		X"D4",X"19",X"A0",X"49",X"8C",X"22",X"8C",X"22",X"8B",X"81",X"08",X"A1",X"27",X"BC",X"34",X"CA",
+		X"15",X"98",X"90",X"20",X"BD",X"41",X"8B",X"13",X"AB",X"28",X"29",X"18",X"2B",X"A1",X"5E",X"08",
+		X"78",X"A9",X"14",X"BA",X"38",X"5D",X"01",X"80",X"A1",X"03",X"BE",X"58",X"8D",X"59",X"1B",X"10",
+		X"2B",X"01",X"0B",X"A1",X"79",X"00",X"A9",X"A5",X"7C",X"2B",X"2B",X"17",X"8A",X"90",X"1A",X"70",
+		X"B9",X"03",X"B3",X"6E",X"09",X"4A",X"21",X"E0",X"02",X"B2",X"2C",X"88",X"3A",X"05",X"B9",X"85",
+		X"A8",X"5C",X"1A",X"39",X"83",X"9C",X"85",X"99",X"39",X"B1",X"38",X"AC",X"7B",X"19",X"6B",X"02",
+		X"C2",X"80",X"A0",X"7C",X"A4",X"1B",X"97",X"C0",X"84",X"A9",X"23",X"F0",X"38",X"E5",X"A1",X"A0",
+		X"2A",X"5B",X"B7",X"8B",X"06",X"AB",X"05",X"AA",X"6D",X"20",X"8A",X"25",X"D9",X"58",X"A8",X"30",
+		X"E3",X"89",X"96",X"8D",X"31",X"AB",X"44",X"D9",X"5A",X"94",X"8D",X"30",X"0D",X"5B",X"A6",X"9A",
+		X"32",X"F3",X"8A",X"01",X"7D",X"95",X"AB",X"69",X"D5",X"98",X"97",X"AD",X"42",X"CA",X"50",X"D1",
+		X"39",X"E5",X"1D",X"38",X"9B",X"7A",X"B4",X"3D",X"A5",X"2D",X"95",X"A9",X"5D",X"5D",X"29",X"69",
+		X"D2",X"5D",X"B5",X"0C",X"85",X"8D",X"59",X"89",X"39",X"A7",X"D3",X"81",X"F5",X"3D",X"A5",X"8D",
+		X"41",X"D1",X"18",X"B4",X"2F",X"12",X"0E",X"5A",X"80",X"08",X"97",X"BA",X"33",X"DA",X"5A",X"0A",
+		X"7B",X"B6",X"8A",X"94",X"0B",X"4D",X"4A",X"3E",X"42",X"D8",X"23",X"F3",X"1C",X"81",X"3E",X"13",
+		X"C0",X"02",X"D4",X"9A",X"03",X"8E",X"59",X"A8",X"20",X"C7",X"B9",X"84",X"A9",X"59",X"A1",X"19",
+		X"A7",X"A9",X"83",X"9A",X"7B",X"08",X"2A",X"87",X"B0",X"92",X"98",X"5C",X"00",X"1A",X"03",X"B1",
+		X"A2",X"A1",X"4E",X"28",X"0A",X"11",X"A2",X"89",X"95",X"9B",X"30",X"8C",X"59",X"93",X"99",X"96",
+		X"A9",X"38",X"99",X"4B",X"84",X"8B",X"05",X"A9",X"11",X"A0",X"3D",X"02",X"0A",X"A4",X"88",X"08",
+		X"01",X"9D",X"31",X"8D",X"12",X"A1",X"80",X"A4",X"0C",X"18",X"3B",X"8B",X"63",X"CC",X"41",X"C1",
+		X"81",X"91",X"80",X"91",X"91",X"80",X"00",X"81",X"80",X"81",X"90",X"80",X"80",X"81",X"80",X"08",
+		X"A9",X"2A",X"57",X"CD",X"5A",X"94",X"92",X"2F",X"00",X"B2",X"28",X"4C",X"93",X"D0",X"39",X"21",
+		X"F2",X"AA",X"50",X"83",X"F0",X"1B",X"13",X"A4",X"8E",X"29",X"A3",X"00",X"6A",X"B3",X"BB",X"58",
+		X"16",X"AA",X"2B",X"A2",X"83",X"78",X"A0",X"A9",X"98",X"25",X"40",X"B8",X"AC",X"98",X"15",X"51",
+		X"99",X"9D",X"89",X"93",X"43",X"5A",X"88",X"DA",X"89",X"03",X"44",X"3B",X"88",X"EA",X"90",X"91",
+		X"62",X"20",X"A0",X"BD",X"A8",X"88",X"36",X"22",X"89",X"8C",X"BA",X"A0",X"12",X"74",X"00",X"0A",
+		X"AB",X"C9",X"91",X"03",X"72",X"00",X"8B",X"AB",X"BA",X"82",X"25",X"72",X"01",X"0B",X"BB",X"CA",
+		X"91",X"22",X"65",X"18",X"09",X"CA",X"B9",X"98",X"24",X"35",X"30",X"A9",X"AD",X"BA",X"99",X"14",
+		X"34",X"35",X"89",X"9A",X"CB",X"A8",X"90",X"33",X"36",X"48",X"90",X"9A",X"C9",X"89",X"14",X"32",
+		X"46",X"89",X"89",X"BC",X"B9",X"98",X"13",X"33",X"73",X"88",X"89",X"CB",X"A9",X"B1",X"33",X"46",
+		X"40",X"08",X"AB",X"BC",X"C9",X"81",X"22",X"44",X"31",X"88",X"BC",X"BC",X"A9",X"91",X"42",X"34",
+		X"41",X"88",X"9C",X"C8",X"BB",X"08",X"13",X"43",X"43",X"30",X"9A",X"CC",X"CA",X"A8",X"09",X"25",
+		X"21",X"44",X"18",X"08",X"BD",X"99",X"BA",X"00",X"04",X"42",X"24",X"28",X"99",X"BD",X"B9",X"9A",
+		X"02",X"0A",X"43",X"19",X"43",X"9B",X"89",X"FB",X"18",X"D2",X"2A",X"14",X"01",X"42",X"12",X"18",
+		X"9C",X"BC",X"B9",X"BA",X"89",X"B9",X"9A",X"A2",X"51",X"55",X"34",X"22",X"41",X"11",X"19",X"9C",
+		X"CB",X"CB",X"AA",X"99",X"01",X"11",X"12",X"1B",X"98",X"9A",X"82",X"26",X"23",X"42",X"20",X"1A",
+		X"CA",X"CB",X"B1",X"13",X"53",X"43",X"10",X"9A",X"BB",X"BA",X"92",X"23",X"34",X"11",X"9A",X"CC",
+		X"BB",X"AA",X"03",X"31",X"43",X"18",X"18",X"9A",X"9A",X"8A",X"98",X"08",X"08",X"08",X"19",X"00",
+		X"10",X"08",X"18",X"8A",X"08",X"89",X"08",X"08",X"10",X"80",X"08",X"8A",X"88",X"00",X"11",X"11",
+		X"08",X"09",X"9A",X"89",X"00",X"00",X"30",X"20",X"18",X"0A",X"8A",X"8A",X"08",X"02",X"10",X"30",
+		X"19",X"89",X"9A",X"89",X"80",X"00",X"11",X"18",X"08",X"09",X"88",X"09",X"08",X"89",X"18",X"08",
+		X"98",X"91",X"91",X"88",X"10",X"08",X"80",X"90",X"00",X"01",X"01",X"00",X"B8",X"A9",X"90",X"A0",
+		X"89",X"80",X"81",X"72",X"48",X"8D",X"0C",X"88",X"29",X"50",X"08",X"0C",X"89",X"88",X"40",X"22",
+		X"3D",X"1B",X"B9",X"1B",X"10",X"E9",X"99",X"76",X"12",X"0B",X"AB",X"C9",X"20",X"34",X"29",X"1C",
+		X"BB",X"8B",X"44",X"41",X"29",X"CC",X"BC",X"8A",X"16",X"70",X"38",X"AB",X"9C",X"80",X"11",X"51",
+		X"88",X"8D",X"98",X"81",X"52",X"81",X"AD",X"AA",X"B1",X"27",X"34",X"09",X"B9",X"E8",X"81",X"14",
+		X"10",X"98",X"C9",X"98",X"32",X"31",X"0F",X"BB",X"99",X"73",X"31",X"1D",X"8B",X"AA",X"20",X"43",
+		X"28",X"8B",X"E9",X"00",X"14",X"89",X"BC",X"B4",X"23",X"72",X"A9",X"9C",X"A1",X"81",X"25",X"81",
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+		X"00",X"FF",X"00",X"FF",X"40",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",
+		X"FF",X"40",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"BF",X"00",X"FF",X"00",X"FF",X"00",
+		X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",
+		X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"02",X"00",
+		X"09",X"0A",X"0C",X"0D",X"0F",X"10",X"12",X"13",X"15",X"16",X"18",X"19",X"1B",X"1C",X"1E",X"1F",
+		X"23",X"24",X"26",X"27",X"29",X"2A",X"2C",X"2D",X"2F",X"30",X"32",X"33",X"35",X"36",X"38",X"39",
+		X"22",X"5A",X"38",X"30",X"22",X"3B",X"3B",X"20",X"20",X"64",X"65",X"74",X"61",X"20",X"69",X"73",
+		X"20",X"20",X"2D",X"2D",X"2D",X"2D",X"48",X"20",X"74",X"6F",X"20",X"2D",X"2D",X"2D",X"2D",X"48",
+		X"45",X"4E",X"44",X"48",X"45",X"58",X"3E",X"3E",X"20",X"50",X"61",X"72",X"61",X"6D",X"74",X"65",
+		X"72",X"20",X"65",X"72",X"72",X"6F",X"72",X"20",X"3C",X"3C",X"0D",X"00",X"44",X"55",X"4D",X"50",
+		X"20",X"4C",X"49",X"53",X"54",X"20",X"50",X"41",X"47",X"45",X"20",X"3D",X"20",X"FF",X"00",X"0D",
+		X"0D",X"00",X"FF",X"00",X"FF",X"00",X"FE",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",
+		X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",
+		X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",
+		X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",
+		X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",
+		X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",X"00",X"FF",
+		X"FF",X"00",X"D1",X"AE",X"02",X"00",X"4D",X"00",X"FF",X"00",X"FF",X"00",X"00",X"00",X"FF",X"00",
+		X"FE",X"FF",X"00",X"00",X"00",X"00",X"35",X"00",X"FE",X"FF",X"08",X"2E",X"E4",X"41",X"0C",X"00",
+		X"F9",X"00",X"F9",X"00",X"F9",X"00",X"F9",X"00",X"FA",X"86",X"F9",X"00",X"F9",X"D4",X"F9",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/spr1.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/spr1.bin
new file mode 100644
index 0000000000000000000000000000000000000000..bbf5c1fb4c461f4a35c9be01e990f1da62249db2
GIT binary patch
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/spr2.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/spr2.bin
new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/spr3.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/kungfum/spr3.bin
new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun.zip b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun.zip
new file mode 100644
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new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-a-3h b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-a-3h
new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-a-4a b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-a-4a
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-a-4e b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-a-4e
new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-1l b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-1l
new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-1m b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-1m
new file mode 100644
index 0000000000000000000000000000000000000000..413cad4dfe09660d3ab17a1b5909008d50386b0c
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-1n b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-1n
new file mode 100644
index 0000000000000000000000000000000000000000..23910f5ada4e8f5614d155d52c90927089733079
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-3n b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-3n
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-5p b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-5p
new file mode 100644
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GIT binary patch
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-6f b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-b-6f
new file mode 100644
index 00000000..bc766564
--- /dev/null
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-2f b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-2f
new file mode 100644
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GIT binary patch
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-2j b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-2j
new file mode 100644
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-3l b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-3l
new file mode 100644
index 0000000000000000000000000000000000000000..00fe489fdf8f3de35c017a53cec6efc968f2d559
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-3m b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-3m
new file mode 100644
index 0000000000000000000000000000000000000000..5ecfd4ae1b4c33c5f9a4b9627ec48cc62fc4cafc
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literal 0
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-3n b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/lr-e-3n
new file mode 100644
index 0000000000000000000000000000000000000000..3abc5d5eb82998a0df6e1060215978584613ab2d
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literal 0
HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/make_proms.bat b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/make_proms.bat
new file mode 100644
index 00000000..54526f8c
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/make_proms.bat	
@@ -0,0 +1,11 @@
+copy /b lr-a-4e + lr-a-4d + lr-a-4b + lr-a-4a prog.bin
+make_vhdl_prom.exe prog.bin prog.vhd
+
+make_vhdl_prom.exe lr-b-5p rom_sprite_high_new.vhd
+
+
+copy /b lr-a-3f + lr-a-3h snd.bin
+make_vhdl_prom.exe snd.bin snd_prg.vhd
+
+copy /b prog.bin + snd.bin LDRUNNER.ROM
+pause
\ No newline at end of file
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/make_vhdl_prom.exe b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/make_vhdl_prom.exe
new file mode 100644
index 0000000000000000000000000000000000000000..1e5618bf9417eaeb90556e3021a78e9860a815e8
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/prog.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/prog.bin
new file mode 100644
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zmdO<n%E5-%xcCHy9hN-&&JlMJ?TFgyo5SRwZfBz%n4=SwV|otEB7Au>3mTLls>iGu
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N_CG&;@&B3P{{q01>{kE)

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/prog.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/prog.vhd
new file mode 100644
index 00000000..fb5ff9f0
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/prog.vhd	
@@ -0,0 +1,2070 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity prog is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(14 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of prog is
+	type rom is array(0 to  32767) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"F3",X"31",X"00",X"E8",X"01",X"00",X"00",X"FD",X"21",X"00",X"00",X"10",X"FA",X"0D",X"20",X"F7",
+		X"ED",X"56",X"21",X"B3",X"E6",X"36",X"01",X"DB",X"04",X"CB",X"7F",X"CA",X"41",X"6F",X"35",X"CD",
+		X"7A",X"00",X"00",X"00",X"00",X"FB",X"C3",X"CF",X"25",X"CD",X"00",X"1D",X"CD",X"4C",X"04",X"CD",
+		X"2C",X"07",X"18",X"F5",X"C7",X"C7",X"C7",X"C7",X"08",X"D9",X"DD",X"E5",X"FD",X"E5",X"CD",X"28",
+		X"01",X"CD",X"A2",X"00",X"CD",X"68",X"31",X"3A",X"6A",X"E5",X"B7",X"C4",X"4B",X"2A",X"3A",X"9D",
+		X"E5",X"FE",X"02",X"CC",X"41",X"01",X"CD",X"90",X"01",X"FD",X"E1",X"DD",X"E1",X"D9",X"08",X"FB",
+		X"C9",X"C7",X"C7",X"C7",X"C7",X"C7",X"FB",X"ED",X"45",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"93",X"24",X"6C",X"DB",X"7A",X"FB",X"85",X"91",X"A3",X"80",X"AF",X"32",X"9D",X"E5",X"D3",X"01",
+		X"21",X"00",X"D0",X"36",X"00",X"54",X"5D",X"13",X"01",X"F0",X"17",X"ED",X"B0",X"CD",X"28",X"01",
+		X"CD",X"F4",X"08",X"CD",X"D6",X"08",X"CD",X"A6",X"6D",X"3E",X"00",X"D3",X"00",X"F6",X"80",X"D3",
+		X"00",X"C9",X"21",X"B5",X"E5",X"35",X"23",X"35",X"21",X"B5",X"E6",X"35",X"3A",X"B9",X"E5",X"B7",
+		X"20",X"04",X"DB",X"01",X"18",X"02",X"DB",X"02",X"2F",X"32",X"4D",X"E4",X"21",X"CF",X"E5",X"07",
+		X"CB",X"16",X"07",X"07",X"CB",X"16",X"3A",X"4D",X"E4",X"21",X"D0",X"E5",X"0F",X"CB",X"16",X"0F",
+		X"CB",X"16",X"DB",X"00",X"2F",X"21",X"AA",X"E5",X"1F",X"CB",X"16",X"1F",X"CB",X"16",X"DB",X"04",
+		X"CB",X"67",X"20",X"29",X"21",X"B4",X"E5",X"7E",X"B7",X"20",X"11",X"3A",X"AA",X"E5",X"E6",X"05",
+		X"FE",X"05",X"20",X"06",X"36",X"01",X"F1",X"C3",X"59",X"00",X"18",X"11",X"3A",X"AA",X"E5",X"E6",
+		X"0A",X"FE",X"0A",X"20",X"04",X"36",X"00",X"18",X"04",X"F1",X"C3",X"59",X"00",X"CD",X"23",X"09",
+		X"3A",X"AF",X"E5",X"B7",X"20",X"05",X"3E",X"02",X"32",X"B2",X"E5",X"3A",X"A7",X"E5",X"B7",X"C8",
+		X"3A",X"B2",X"E5",X"B7",X"C8",X"C3",X"A0",X"68",X"3A",X"B3",X"E6",X"B7",X"28",X"07",X"CD",X"39",
+		X"7C",X"F1",X"C3",X"59",X"00",X"01",X"00",X"01",X"11",X"00",X"C0",X"21",X"00",X"E3",X"ED",X"B0",
+		X"C9",X"CD",X"E6",X"03",X"CD",X"00",X"0B",X"CD",X"00",X"13",X"CD",X"00",X"24",X"C9",X"FD",X"E5",
+		X"3A",X"E9",X"E4",X"32",X"88",X"E5",X"FD",X"21",X"58",X"E4",X"11",X"18",X"00",X"DD",X"7E",X"06",
+		X"FD",X"BE",X"06",X"20",X"20",X"DD",X"7E",X"07",X"FD",X"96",X"07",X"30",X"02",X"ED",X"44",X"FE",
+		X"04",X"30",X"12",X"FD",X"7E",X"0D",X"B7",X"28",X"0C",X"FD",X"7E",X"08",X"FE",X"09",X"30",X"02",
+		X"0E",X"FF",X"FD",X"E1",X"C9",X"FD",X"19",X"21",X"88",X"E5",X"35",X"20",X"D0",X"FD",X"E1",X"C9",
+		X"3A",X"9D",X"E5",X"B7",X"C8",X"3A",X"6A",X"E5",X"B7",X"CC",X"03",X"32",X"DD",X"21",X"40",X"E4",
+		X"FD",X"21",X"B0",X"E3",X"3A",X"6A",X"E5",X"FE",X"02",X"20",X"04",X"FD",X"21",X"F0",X"E3",X"AF",
+		X"32",X"E8",X"E4",X"DD",X"4E",X"0A",X"3A",X"E8",X"E4",X"B7",X"28",X"17",X"DD",X"7E",X"0D",X"B7",
+		X"28",X"0E",X"DD",X"34",X"08",X"DD",X"7E",X"08",X"FE",X"18",X"38",X"04",X"DD",X"36",X"08",X"00",
+		X"CD",X"4E",X"01",X"79",X"FE",X"FF",X"20",X"0B",X"FD",X"36",X"04",X"00",X"FD",X"36",X"0C",X"00",
+		X"C3",X"11",X"03",X"06",X"00",X"2A",X"F6",X"E4",X"3A",X"E8",X"E4",X"B7",X"20",X"05",X"21",X"00",
+		X"00",X"18",X"19",X"57",X"3A",X"02",X"E5",X"B7",X"28",X"12",X"3A",X"E9",X"E4",X"BA",X"20",X"0C",
+		X"11",X"30",X"00",X"19",X"3A",X"CD",X"E5",X"FE",X"08",X"20",X"01",X"EB",X"09",X"22",X"F9",X"E4",
+		X"01",X"60",X"45",X"09",X"46",X"DD",X"6E",X"00",X"DD",X"7E",X"01",X"C6",X"04",X"67",X"29",X"29",
+		X"29",X"0E",X"00",X"CB",X"28",X"CB",X"19",X"DD",X"7E",X"0B",X"B7",X"20",X"04",X"ED",X"42",X"18",
+		X"01",X"09",X"29",X"FD",X"74",X"06",X"3E",X"00",X"17",X"FD",X"77",X"07",X"3A",X"F8",X"E4",X"4F",
+		X"DD",X"CB",X"17",X"66",X"28",X"01",X"0C",X"3A",X"E8",X"E4",X"B7",X"20",X"04",X"0E",X"03",X"18",
+		X"11",X"47",X"3A",X"02",X"E5",X"B7",X"28",X"0A",X"3A",X"E9",X"E4",X"B8",X"20",X"04",X"3A",X"6E",
+		X"E5",X"4F",X"CB",X"E1",X"FD",X"71",X"00",X"11",X"B0",X"43",X"2A",X"F9",X"E4",X"19",X"56",X"DD",
+		X"7E",X"0B",X"B7",X"20",X"04",X"3E",X"40",X"AA",X"57",X"7A",X"E6",X"C0",X"FD",X"77",X"05",X"2A",
+		X"F9",X"E4",X"7A",X"11",X"00",X"42",X"19",X"57",X"5E",X"D5",X"FD",X"73",X"04",X"11",X"C0",X"48",
+		X"2A",X"F9",X"E4",X"19",X"AF",X"57",X"5E",X"CB",X"7B",X"28",X"01",X"15",X"DD",X"6E",X"02",X"DD",
+		X"66",X"03",X"29",X"29",X"29",X"17",X"6C",X"67",X"19",X"EB",X"21",X"E9",X"00",X"B7",X"ED",X"52",
+		X"ED",X"5B",X"E3",X"E5",X"19",X"FD",X"75",X"02",X"FD",X"74",X"03",X"D1",X"CB",X"42",X"28",X"4D",
+		X"1C",X"FD",X"73",X"0C",X"FD",X"71",X"08",X"E5",X"01",X"70",X"4A",X"2A",X"F9",X"E4",X"09",X"7E",
+		X"06",X"00",X"ED",X"44",X"4F",X"CB",X"79",X"28",X"01",X"05",X"E1",X"09",X"FD",X"75",X"0A",X"FD",
+		X"74",X"0B",X"7A",X"E6",X"C0",X"FD",X"77",X"0D",X"01",X"10",X"47",X"2A",X"F9",X"E4",X"09",X"7E",
+		X"CB",X"72",X"28",X"02",X"ED",X"44",X"4F",X"06",X"00",X"CB",X"79",X"28",X"01",X"05",X"FD",X"66",
+		X"07",X"FD",X"6E",X"06",X"09",X"FD",X"75",X"0E",X"FD",X"74",X"0F",X"18",X"04",X"FD",X"36",X"0C",
+		X"00",X"11",X"F0",X"FF",X"FD",X"19",X"01",X"18",X"00",X"DD",X"09",X"21",X"E8",X"E4",X"34",X"3A",
+		X"E9",X"E4",X"BE",X"D2",X"B3",X"01",X"3A",X"6A",X"E5",X"FE",X"02",X"C8",X"FD",X"21",X"00",X"E3",
+		X"3A",X"17",X"E5",X"87",X"87",X"87",X"21",X"12",X"E5",X"86",X"ED",X"44",X"3C",X"4F",X"06",X"00",
+		X"2A",X"E3",X"E5",X"09",X"FD",X"75",X"02",X"FD",X"74",X"03",X"FD",X"36",X"00",X"12",X"3A",X"16",
+		X"E5",X"C6",X"04",X"87",X"87",X"87",X"6F",X"26",X"00",X"29",X"FD",X"75",X"06",X"FD",X"74",X"07",
+		X"3A",X"10",X"E5",X"FD",X"77",X"04",X"FD",X"21",X"08",X"E3",X"FD",X"36",X"04",X"00",X"FD",X"36",
+		X"0C",X"00",X"16",X"14",X"1E",X"02",X"DD",X"21",X"18",X"E5",X"DD",X"7E",X"01",X"FE",X"00",X"28",
+		X"3A",X"DD",X"7E",X"03",X"87",X"87",X"87",X"47",X"3E",X"F1",X"90",X"4F",X"06",X"00",X"2A",X"E3",
+		X"E5",X"09",X"FD",X"75",X"02",X"FD",X"74",X"03",X"DD",X"7E",X"02",X"C6",X"04",X"87",X"87",X"87",
+		X"6F",X"26",X"00",X"29",X"FD",X"75",X"06",X"FD",X"74",X"07",X"FD",X"36",X"00",X"12",X"DD",X"7E",
+		X"01",X"FD",X"77",X"04",X"01",X"08",X"00",X"FD",X"09",X"1D",X"C8",X"01",X"04",X"00",X"DD",X"09",
+		X"15",X"20",X"B7",X"21",X"9E",X"E5",X"06",X"00",X"7E",X"B7",X"28",X"12",X"35",X"20",X"0F",X"E5",
+		X"78",X"87",X"87",X"87",X"5F",X"16",X"00",X"21",X"C4",X"E3",X"19",X"36",X"00",X"E1",X"23",X"04",
+		X"78",X"FE",X"08",X"38",X"E3",X"C9",X"21",X"8A",X"E5",X"7E",X"23",X"B6",X"23",X"47",X"7E",X"E6",
+		X"F0",X"B0",X"20",X"0B",X"AF",X"77",X"3E",X"01",X"32",X"CE",X"E5",X"CD",X"03",X"32",X"C9",X"0E",
+		X"00",X"21",X"B1",X"E6",X"3A",X"8B",X"E5",X"BE",X"20",X"01",X"0C",X"ED",X"5B",X"E1",X"E5",X"21",
+		X"8D",X"E5",X"7E",X"93",X"27",X"77",X"2B",X"7E",X"9A",X"27",X"77",X"06",X"02",X"2B",X"7E",X"DE",
+		X"00",X"27",X"77",X"10",X"F8",X"CB",X"41",X"C8",X"3A",X"8B",X"E5",X"21",X"B1",X"E6",X"BE",X"C8",
+		X"7E",X"FE",X"15",X"20",X"04",X"3E",X"1C",X"18",X"0A",X"FE",X"10",X"20",X"04",X"3E",X"1D",X"18",
+		X"02",X"3E",X"1E",X"CD",X"42",X"31",X"7E",X"D6",X"05",X"27",X"77",X"C9",X"3A",X"FC",X"E4",X"B7",
+		X"C0",X"21",X"B6",X"E5",X"3A",X"04",X"E5",X"B7",X"20",X"02",X"36",X"FF",X"7E",X"FE",X"80",X"38",
+		X"02",X"36",X"18",X"7E",X"21",X"04",X"E5",X"FE",X"09",X"30",X"0D",X"7E",X"FE",X"01",X"28",X"06",
+		X"3E",X"01",X"77",X"CD",X"89",X"63",X"18",X"0B",X"7E",X"FE",X"02",X"28",X"06",X"3E",X"02",X"77",
+		X"CD",X"89",X"63",X"3A",X"41",X"E4",X"21",X"7B",X"E5",X"BE",X"20",X"0C",X"3A",X"43",X"E4",X"23",
+		X"BE",X"20",X"05",X"3E",X"01",X"32",X"AF",X"E6",X"3A",X"AF",X"E6",X"B7",X"C8",X"3A",X"46",X"E4",
+		X"FE",X"08",X"C0",X"AF",X"CD",X"89",X"63",X"F1",X"3E",X"00",X"32",X"9D",X"E5",X"3E",X"00",X"CD",
+		X"42",X"31",X"3E",X"23",X"CD",X"42",X"31",X"3E",X"54",X"CD",X"3E",X"30",X"CD",X"8D",X"32",X"3A",
+		X"00",X"E5",X"B7",X"20",X"47",X"21",X"21",X"D7",X"36",X"05",X"2B",X"36",X"00",X"11",X"22",X"D7",
+		X"01",X"3E",X"00",X"ED",X"B0",X"21",X"A1",X"D7",X"36",X"05",X"2B",X"36",X"00",X"11",X"A2",X"D7",
+		X"01",X"3E",X"00",X"ED",X"B0",X"21",X"21",X"D8",X"36",X"05",X"2B",X"36",X"00",X"11",X"22",X"D8",
+		X"01",X"3E",X"00",X"ED",X"B0",X"0E",X"47",X"21",X"A2",X"D7",X"11",X"F8",X"06",X"CD",X"2D",X"30",
+		X"3E",X"1F",X"CD",X"42",X"31",X"0E",X"02",X"CD",X"CF",X"2F",X"18",X"4C",X"3A",X"FF",X"E4",X"B7",
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+		X"01",X"00",X"08",X"AF",X"77",X"23",X"0B",X"78",X"B1",X"20",X"F8",X"C9",X"72",X"23",X"0B",X"78",
+		X"B1",X"20",X"F9",X"C9",X"72",X"23",X"23",X"0B",X"78",X"B1",X"20",X"F8",X"C9",X"08",X"D9",X"C3",
+		X"39",X"7C",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"21",X"09",X"E0",X"34",X"CD",X"52",X"7C",
+		X"3A",X"02",X"E3",X"0F",X"38",X"07",X"21",X"06",X"E3",X"3E",X"80",X"86",X"77",X"C9",X"D9",X"08",
+		X"FB",X"C9",X"21",X"00",X"E1",X"11",X"00",X"C0",X"01",X"00",X"01",X"ED",X"B0",X"C9",X"CD",X"B6",
+		X"77",X"21",X"B9",X"7D",X"CD",X"D5",X"77",X"2A",X"9C",X"7D",X"22",X"06",X"E7",X"DD",X"21",X"08",
+		X"E7",X"FD",X"21",X"A0",X"7D",X"CD",X"95",X"79",X"CD",X"95",X"79",X"CD",X"95",X"79",X"CD",X"8B",
+		X"7C",X"DB",X"00",X"2F",X"0F",X"0F",X"DA",X"33",X"70",X"18",X"D3",X"FD",X"22",X"0B",X"E7",X"3E",
+		X"01",X"32",X"05",X"E7",X"06",X"06",X"CD",X"50",X"7D",X"CD",X"E5",X"7C",X"CD",X"CF",X"7C",X"01",
+		X"00",X"00",X"ED",X"43",X"13",X"E3",X"DB",X"00",X"2F",X"0F",X"0F",X"30",X"04",X"C1",X"C3",X"33",
+		X"70",X"DB",X"00",X"2F",X"0F",X"DC",X"CF",X"7C",X"DB",X"01",X"2F",X"0F",X"38",X"34",X"0F",X"38",
+		X"5D",X"ED",X"4B",X"13",X"E3",X"0B",X"78",X"B1",X"20",X"D8",X"CD",X"E5",X"7C",X"18",X"4F",X"3A",
+		X"05",X"E7",X"4F",X"06",X"00",X"FD",X"2A",X"0B",X"E7",X"FD",X"09",X"FD",X"7E",X"00",X"D3",X"00",
+		X"F6",X"80",X"D3",X"00",X"C9",X"3E",X"00",X"D3",X"00",X"3E",X"80",X"D3",X"00",X"06",X"00",X"10",
+		X"FE",X"C9",X"CD",X"E5",X"7C",X"CD",X"95",X"79",X"CD",X"95",X"79",X"CD",X"95",X"79",X"3A",X"07",
+		X"E7",X"5F",X"3A",X"05",X"E7",X"BB",X"C8",X"06",X"04",X"CD",X"50",X"7D",X"3D",X"32",X"05",X"E7",
+		X"06",X"06",X"CD",X"50",X"7D",X"CD",X"CF",X"7C",X"01",X"00",X"00",X"C3",X"A2",X"7C",X"CD",X"E5",
+		X"7C",X"CD",X"95",X"79",X"CD",X"95",X"79",X"CD",X"95",X"79",X"3A",X"06",X"E7",X"5F",X"3A",X"05",
+		X"E7",X"BB",X"C8",X"06",X"04",X"CD",X"50",X"7D",X"3C",X"32",X"05",X"E7",X"06",X"06",X"CD",X"50",
+		X"7D",X"CD",X"CF",X"7C",X"01",X"00",X"00",X"C3",X"A2",X"7C",X"4F",X"D6",X"03",X"3C",X"18",X"17",
+		X"4F",X"C5",X"21",X"20",X"D1",X"11",X"80",X"00",X"47",X"05",X"28",X"03",X"19",X"18",X"FA",X"C1",
+		X"23",X"70",X"23",X"23",X"70",X"79",X"C9",X"C5",X"21",X"20",X"D1",X"11",X"80",X"00",X"47",X"FE",
+		X"01",X"28",X"04",X"05",X"19",X"10",X"FD",X"C1",X"23",X"70",X"23",X"23",X"70",X"79",X"C9",X"C5",
+		X"0E",X"00",X"06",X"00",X"10",X"FE",X"F5",X"3A",X"00",X"D0",X"CB",X"4F",X"28",X"09",X"F1",X"0D",
+		X"20",X"F0",X"3D",X"20",X"EB",X"C1",X"C9",X"F1",X"C1",X"06",X"01",X"C9",X"15",X"01",X"00",X"00",
+		X"00",X"01",X"02",X"03",X"04",X"05",X"06",X"1C",X"11",X"12",X"13",X"14",X"15",X"20",X"21",X"22",
+		X"23",X"24",X"25",X"26",X"27",X"00",X"00",X"00",X"00",X"0B",X"A0",X"D0",X"53",X"20",X"4F",X"20",
+		X"55",X"20",X"4E",X"20",X"44",X"20",X"53",X"0F",X"20",X"D1",X"30",X"31",X"20",X"48",X"4F",X"4C",
+		X"45",X"20",X"44",X"49",X"47",X"47",X"49",X"4E",X"47",X"15",X"A0",X"D1",X"30",X"32",X"20",X"50",
+		X"49",X"43",X"4B",X"49",X"4E",X"47",X"20",X"55",X"50",X"20",X"46",X"4F",X"52",X"54",X"49",X"4E",
+		X"45",X"0F",X"20",X"D2",X"30",X"33",X"20",X"44",X"4F",X"4F",X"52",X"20",X"4F",X"50",X"45",X"4E",
+		X"49",X"4E",X"47",X"13",X"A0",X"D2",X"30",X"34",X"20",X"42",X"55",X"52",X"49",X"45",X"44",X"20",
+		X"49",X"4E",X"54",X"4F",X"20",X"48",X"4F",X"4C",X"45",X"14",X"20",X"D3",X"30",X"35",X"20",X"46",
+		X"41",X"4C",X"4C",X"49",X"4E",X"47",X"20",X"49",X"4E",X"54",X"4F",X"20",X"48",X"4F",X"4C",X"45",
+		X"10",X"A0",X"D3",X"30",X"36",X"20",X"50",X"4C",X"41",X"59",X"45",X"52",X"20",X"4B",X"49",X"4C",
+		X"4C",X"45",X"44",X"12",X"20",X"D4",X"30",X"37",X"20",X"54",X"49",X"4D",X"45",X"20",X"55",X"50",
+		X"20",X"57",X"41",X"52",X"4E",X"49",X"4E",X"47",X"16",X"A0",X"D4",X"30",X"38",X"20",X"54",X"49",
+		X"4D",X"45",X"20",X"53",X"43",X"4F",X"52",X"45",X"20",X"43",X"4F",X"55",X"4E",X"54",X"49",X"4E",
+		X"47",X"11",X"20",X"D5",X"30",X"39",X"20",X"43",X"4F",X"49",X"4E",X"20",X"49",X"4E",X"53",X"45",
+		X"52",X"54",X"49",X"4E",X"47",X"0F",X"A0",X"D5",X"31",X"30",X"20",X"5A",X"4F",X"4F",X"4D",X"20",
+		X"49",X"4E",X"20",X"20",X"20",X"20",X"20",X"0F",X"20",X"D6",X"31",X"31",X"20",X"5A",X"4F",X"4F",
+		X"4D",X"20",X"4F",X"55",X"54",X"20",X"20",X"20",X"20",X"16",X"A0",X"D6",X"31",X"32",X"20",X"50",
+		X"4C",X"41",X"59",X"45",X"52",X"20",X"46",X"41",X"4C",X"4C",X"49",X"4E",X"47",X"20",X"20",X"20",
+		X"20",X"20",X"0D",X"20",X"D7",X"31",X"33",X"20",X"47",X"41",X"4D",X"45",X"20",X"53",X"54",X"41",
+		X"52",X"54",X"0C",X"A0",X"D7",X"31",X"34",X"20",X"47",X"41",X"4D",X"45",X"20",X"4F",X"56",X"45",
+		X"52",X"1B",X"20",X"D8",X"31",X"35",X"20",X"42",X"47",X"4D",X"20",X"28",X"43",X"4F",X"4E",X"54",
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+		X"A0",X"D8",X"31",X"36",X"20",X"52",X"4F",X"55",X"4E",X"44",X"20",X"43",X"4C",X"45",X"41",X"52",
+		X"0E",X"20",X"D9",X"31",X"37",X"20",X"42",X"4C",X"4F",X"43",X"4B",X"20",X"43",X"4C",X"45",X"41",
+		X"52",X"0D",X"A0",X"D9",X"31",X"38",X"20",X"54",X"49",X"4D",X"45",X"20",X"55",X"50",X"20",X"20",
+		X"20",X"12",X"20",X"DA",X"31",X"39",X"20",X"42",X"47",X"4D",X"20",X"28",X"47",X"41",X"4D",X"45",
+		X"20",X"50",X"4C",X"41",X"59",X"29",X"12",X"A0",X"DA",X"32",X"30",X"20",X"47",X"41",X"4D",X"45",
+		X"20",X"43",X"4F",X"4D",X"50",X"4C",X"45",X"54",X"49",X"4E",X"47",X"0C",X"20",X"DB",X"20",X"20",
+		X"4D",X"55",X"53",X"49",X"43",X"20",X"45",X"4E",X"44",X"20",X"00",X"00",X"00",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",
+		X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7",X"C7");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/rom_sprite_high.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/rom_sprite_high.vhd
new file mode 100644
index 00000000..8c30be36
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/rom_sprite_high.vhd	
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity rom_sprite_high is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(4 downto 0);
+	data : out std_logic_vector(3 downto 0)
+);
+end entity;
+
+architecture prom of rom_sprite_high is
+	type rom is array(0 to  31) of std_logic_vector(3 downto 0);
+	signal rom_data: rom := (
+		"0001","0001","0001","0001","0000","0000","0000","0000","0001","0001","0001","0001","0000","0000","0000","0000",
+		"0001","0001","0001","0001","0000","0000","0000","0000","0001","0001","0001","0001","0000","0000","0000","0000");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/rom_sprite_high_new.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/rom_sprite_high_new.vhd
new file mode 100644
index 00000000..bf9564e1
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/rom_sprite_high_new.vhd	
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity rom_sprite_high_new is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(4 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of rom_sprite_high_new is
+	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",
+		X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/snd.bin b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/snd.bin
new file mode 100644
index 0000000000000000000000000000000000000000..e483d90d58718fbd8906218ad44752532abd0822
GIT binary patch
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KWw0Lq75P6t&XG3&

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/snd_prg.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/snd_prg.vhd
new file mode 100644
index 00000000..d96f47a1
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/ldrun/snd_prg.vhd	
@@ -0,0 +1,1046 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity snd_prg is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(13 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of snd_prg is
+	type rom is array(0 to  16383) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"81",X"C7",X"0F",X"BC",X"77",X"F3",X"2F",X"23",X"E8",X"5D",X"85",X"A9",X"87",X"D8",X"40",X"D3",
+		X"0B",X"49",X"8C",X"52",X"D1",X"88",X"1E",X"5A",X"A5",X"8D",X"5A",X"3E",X"05",X"8D",X"22",X"9C",
+		X"43",X"D8",X"5D",X"14",X"D2",X"B6",X"D9",X"5B",X"22",X"D1",X"80",X"1E",X"5B",X"96",X"B8",X"6D",
+		X"49",X"C4",X"8C",X"58",X"D4",X"3D",X"18",X"D5",X"C1",X"5D",X"31",X"E4",X"9D",X"48",X"81",X"8D",
+		X"49",X"82",X"E5",X"B3",X"C2",X"1E",X"5A",X"82",X"D5",X"D8",X"5A",X"A6",X"C4",X"0D",X"23",X"E2",
+		X"8A",X"7D",X"19",X"42",X"D9",X"5D",X"85",X"C9",X"58",X"C5",X"8D",X"59",X"A3",X"8E",X"59",X"81",
+		X"98",X"10",X"93",X"F2",X"2E",X"3A",X"85",X"BB",X"69",X"B6",X"C2",X"2E",X"5B",X"01",X"89",X"C7",
+		X"1D",X"13",X"E0",X"5C",X"10",X"1F",X"35",X"D0",X"3E",X"05",X"AC",X"49",X"94",X"A8",X"82",X"1C",
+		X"97",X"D0",X"5C",X"20",X"B1",X"10",X"B9",X"61",X"F4",X"2D",X"21",X"D0",X"39",X"C5",X"0D",X"40",
+		X"D2",X"3E",X"12",X"B3",X"C1",X"83",X"E3",X"0B",X"10",X"5D",X"95",X"C8",X"5C",X"95",X"2D",X"05",
+		X"CA",X"35",X"DA",X"5B",X"A6",X"9B",X"6B",X"86",X"D2",X"3D",X"82",X"1E",X"13",X"1F",X"85",X"9B",
+		X"5A",X"82",X"88",X"B7",X"BA",X"68",X"C3",X"1C",X"00",X"39",X"F5",X"8C",X"48",X"A0",X"28",X"B4",
+		X"3F",X"85",X"C9",X"30",X"C5",X"BA",X"68",X"D4",X"2D",X"85",X"9D",X"15",X"D8",X"5A",X"09",X"4A",
+		X"91",X"83",X"BA",X"7C",X"30",X"B2",X"A5",X"9A",X"87",X"AC",X"41",X"D0",X"5D",X"05",X"AC",X"25",
+		X"BC",X"25",X"D9",X"5C",X"85",X"9C",X"34",X"D0",X"4B",X"A5",X"8D",X"50",X"D4",X"1D",X"14",X"D9",
+		X"5A",X"94",X"A8",X"49",X"C3",X"1C",X"03",X"AB",X"42",X"BA",X"36",X"D8",X"31",X"CA",X"42",X"9C",
+		X"38",X"C4",X"8A",X"29",X"08",X"97",X"9D",X"33",X"BC",X"34",X"CA",X"50",X"A0",X"92",X"0C",X"2A",
+		X"23",X"D0",X"2A",X"B7",X"8B",X"14",X"AA",X"58",X"C1",X"4A",X"C3",X"3D",X"A5",X"8B",X"59",X"90",
+		X"19",X"1C",X"23",X"D9",X"50",X"D1",X"5C",X"A5",X"9B",X"5A",X"01",X"90",X"89",X"38",X"A2",X"C2",
+		X"4A",X"B9",X"71",X"F0",X"59",X"C2",X"2A",X"80",X"18",X"92",X"99",X"82",X"3C",X"B7",X"B5",X"A9",
+		X"13",X"BB",X"51",X"C8",X"4A",X"80",X"81",X"00",X"C3",X"2D",X"82",X"2A",X"D2",X"5C",X"82",X"89",
+		X"3B",X"B7",X"0C",X"28",X"92",X"08",X"A3",X"8F",X"32",X"CA",X"40",X"A8",X"4A",X"92",X"2E",X"05",
+		X"CA",X"58",X"A0",X"29",X"B5",X"1D",X"95",X"1D",X"04",X"9D",X"25",X"C8",X"11",X"A1",X"89",X"3B",
+		X"02",X"9A",X"20",X"05",X"F0",X"4B",X"92",X"1B",X"39",X"90",X"23",X"F9",X"69",X"B1",X"3A",X"95",
+		X"A9",X"22",X"BD",X"50",X"B0",X"5C",X"95",X"A9",X"39",X"90",X"29",X"1B",X"97",X"1F",X"05",X"8C",
+		X"01",X"1A",X"83",X"A8",X"18",X"95",X"C2",X"8A",X"4A",X"92",X"2B",X"93",X"3D",X"C4",X"2E",X"12",
+		X"C0",X"28",X"A1",X"1B",X"69",X"B2",X"3B",X"A4",X"90",X"88",X"3B",X"C7",X"8B",X"16",X"BA",X"40",
+		X"B0",X"39",X"B5",X"9A",X"30",X"D1",X"4B",X"93",X"0C",X"13",X"C8",X"48",X"C1",X"28",X"C1",X"4A",
+		X"C4",X"2D",X"83",X"8A",X"84",X"8B",X"04",X"8C",X"12",X"98",X"A2",X"4C",X"95",X"9A",X"10",X"80",
+		X"2B",X"02",X"98",X"08",X"99",X"58",X"E4",X"0B",X"06",X"BB",X"78",X"A9",X"50",X"C0",X"20",X"B1",
+		X"00",X"99",X"79",X"C2",X"4C",X"83",X"9A",X"11",X"0C",X"12",X"9A",X"31",X"D1",X"2A",X"A2",X"1A",
+		X"3B",X"96",X"8A",X"12",X"D8",X"24",X"D9",X"15",X"AB",X"48",X"92",X"9A",X"48",X"90",X"94",X"AA",
+		X"59",X"90",X"10",X"A0",X"28",X"A8",X"68",X"F1",X"3B",X"A4",X"2B",X"93",X"98",X"8A",X"79",X"A2",
+		X"00",X"AB",X"70",X"9A",X"32",X"F0",X"28",X"A2",X"0C",X"15",X"AB",X"40",X"A0",X"18",X"A1",X"3B",
+		X"C3",X"5A",X"E3",X"19",X"B3",X"88",X"82",X"89",X"B3",X"7B",X"B4",X"18",X"D2",X"4C",X"94",X"0B",
+		X"02",X"98",X"81",X"92",X"B8",X"7A",X"92",X"1E",X"23",X"E8",X"30",X"AA",X"33",X"CB",X"41",X"B0",
+		X"18",X"2A",X"A2",X"18",X"B0",X"4A",X"85",X"AF",X"58",X"A1",X"2B",X"A4",X"2B",X"B4",X"19",X"A0",
+		X"4A",X"A3",X"3F",X"03",X"AC",X"33",X"BC",X"32",X"BA",X"15",X"9B",X"28",X"21",X"F0",X"38",X"C1",
+		X"28",X"B2",X"88",X"01",X"AB",X"72",X"E0",X"29",X"90",X"28",X"A8",X"20",X"9A",X"50",X"E2",X"1A",
+		X"80",X"49",X"D1",X"49",X"D1",X"5A",X"B4",X"1B",X"83",X"8A",X"94",X"0A",X"92",X"19",X"B4",X"1C",
+		X"82",X"3F",X"84",X"9A",X"12",X"8B",X"85",X"0C",X"03",X"9B",X"30",X"8B",X"03",X"08",X"C4",X"8B",
+		X"15",X"BB",X"24",X"8C",X"20",X"01",X"C8",X"38",X"BB",X"72",X"F0",X"39",X"A0",X"20",X"99",X"28",
+		X"92",X"9A",X"05",X"9A",X"28",X"09",X"C3",X"7D",X"03",X"A9",X"12",X"9C",X"20",X"09",X"18",X"D5",
+		X"1A",X"C1",X"31",X"D8",X"10",X"39",X"F1",X"3A",X"A1",X"12",X"D8",X"48",X"C0",X"69",X"B1",X"39",
+		X"B0",X"69",X"A1",X"08",X"08",X"19",X"A3",X"09",X"91",X"5D",X"95",X"0B",X"83",X"98",X"2B",X"83",
+		X"A9",X"12",X"3D",X"C5",X"1B",X"A1",X"58",X"D1",X"20",X"A9",X"13",X"C9",X"6A",X"A3",X"1B",X"02",
+		X"9B",X"52",X"F1",X"29",X"A0",X"29",X"80",X"A5",X"0D",X"11",X"0E",X"15",X"AB",X"40",X"A8",X"28",
+		X"A4",X"8A",X"84",X"9C",X"24",X"AB",X"22",X"8E",X"13",X"AA",X"24",X"C9",X"59",X"B3",X"2B",X"94",
+		X"8A",X"01",X"0A",X"94",X"8C",X"22",X"9B",X"22",X"8C",X"03",X"99",X"91",X"69",X"C1",X"3B",X"00",
+		X"92",X"9B",X"27",X"8D",X"04",X"A9",X"39",X"99",X"26",X"BC",X"51",X"C8",X"30",X"D0",X"38",X"B0",
+		X"31",X"AE",X"23",X"9D",X"13",X"9B",X"06",X"9A",X"12",X"B9",X"38",X"A2",X"5D",X"83",X"9B",X"23",
+		X"AB",X"31",X"B1",X"19",X"4B",X"D3",X"4B",X"C3",X"29",X"B1",X"5A",X"A3",X"0A",X"10",X"B0",X"68",
+		X"F0",X"49",X"A2",X"2C",X"08",X"11",X"9B",X"50",X"C1",X"10",X"C2",X"00",X"A0",X"12",X"E8",X"7B",
+		X"00",X"00",X"A1",X"3E",X"03",X"8D",X"04",X"9A",X"12",X"98",X"09",X"03",X"C9",X"40",X"D2",X"3B",
+		X"B5",X"8B",X"12",X"1D",X"02",X"89",X"89",X"58",X"A8",X"25",X"E8",X"38",X"A8",X"49",X"98",X"21",
+		X"D0",X"39",X"98",X"12",X"AA",X"A7",X"99",X"38",X"B1",X"40",X"C9",X"22",X"9A",X"B3",X"7A",X"B3",
+		X"39",X"D1",X"39",X"9D",X"41",X"B9",X"25",X"C0",X"01",X"98",X"08",X"29",X"B3",X"01",X"BE",X"42",
+		X"D0",X"3A",X"B5",X"8A",X"13",X"BC",X"60",X"AA",X"40",X"C1",X"29",X"A3",X"0E",X"22",X"9B",X"84",
+		X"2D",X"93",X"0A",X"02",X"8C",X"14",X"9D",X"13",X"0D",X"02",X"08",X"A9",X"48",X"8B",X"14",X"0C",
+		X"84",X"99",X"00",X"0A",X"03",X"B3",X"A8",X"2F",X"06",X"8B",X"82",X"2B",X"A3",X"2A",X"C1",X"40",
+		X"AE",X"34",X"BB",X"33",X"B9",X"82",X"8A",X"58",X"B8",X"41",X"C0",X"10",X"B2",X"4D",X"B7",X"0A",
+		X"81",X"2C",X"00",X"18",X"92",X"B9",X"68",X"A8",X"22",X"E0",X"10",X"80",X"B1",X"69",X"C2",X"19",
+		X"09",X"A5",X"0B",X"10",X"93",X"0B",X"E2",X"6A",X"A1",X"21",X"AD",X"33",X"CA",X"31",X"B8",X"28",
+		X"2B",X"B6",X"18",X"D8",X"48",X"90",X"91",X"3D",X"01",X"0A",X"A2",X"59",X"F2",X"3A",X"C2",X"29",
+		X"19",X"0B",X"47",X"F7",X"AF",X"7E",X"4B",X"28",X"80",X"80",X"0A",X"4C",X"3C",X"5C",X"5D",X"5D",
+		X"5D",X"4A",X"A6",X"D5",X"C8",X"5D",X"40",X"D5",X"8D",X"58",X"D3",X"3E",X"85",X"AD",X"52",X"DA",
+		X"51",X"CA",X"51",X"AD",X"42",X"9A",X"B6",X"09",X"8B",X"42",X"A0",X"AA",X"42",X"B1",X"0D",X"04",
+		X"8A",X"21",X"D8",X"22",X"A9",X"22",X"E8",X"11",X"0A",X"81",X"29",X"E1",X"00",X"2A",X"80",X"04",
+		X"E9",X"6A",X"00",X"08",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"88",X"08",X"08",
+		X"00",X"88",X"08",X"81",X"92",X"A3",X"B3",X"C3",X"0C",X"5A",X"94",X"0B",X"B3",X"78",X"AB",X"81",
+		X"24",X"20",X"10",X"9A",X"FA",X"D9",X"16",X"30",X"DB",X"16",X"0C",X"84",X"8C",X"22",X"E2",X"1D",
+		X"39",X"95",X"D3",X"A1",X"8A",X"5C",X"5C",X"3B",X"4B",X"29",X"94",X"E5",X"D4",X"A8",X"4D",X"5A",
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+		X"5A",X"26",X"FA",X"86",X"13",X"97",X"D8",X"39",X"BD",X"FB",X"C0",X"86",X"BF",X"97",X"BB",X"C6",
+		X"FF",X"D7",X"82",X"D7",X"83",X"D7",X"B1",X"D7",X"B2",X"D7",X"B3",X"C6",X"17",X"7E",X"FB",X"DB",
+		X"86",X"BF",X"97",X"BA",X"C6",X"FF",X"D7",X"80",X"D7",X"81",X"D7",X"AE",X"D7",X"AF",X"D7",X"B0",
+		X"C6",X"07",X"7E",X"FB",X"DB",X"7C",X"00",X"BD",X"20",X"04",X"0F",X"7F",X"00",X"BD",X"37",X"36",
+		X"C1",X"10",X"2A",X"19",X"86",X"0D",X"97",X"03",X"D7",X"02",X"C6",X"08",X"D7",X"03",X"5C",X"32",
+		X"97",X"02",X"96",X"BD",X"27",X"FC",X"D7",X"03",X"5A",X"D7",X"03",X"33",X"39",X"86",X"15",X"97",
+		X"03",X"C4",X"0F",X"D7",X"02",X"C6",X"10",X"20",X"E3",X"37",X"20",X"E4",X"37",X"86",X"15",X"97",
+		X"03",X"C4",X"0F",X"D7",X"02",X"C6",X"14",X"20",X"0D",X"C1",X"10",X"2A",X"EF",X"37",X"86",X"0D",
+		X"97",X"03",X"D7",X"02",X"C6",X"0C",X"4F",X"97",X"03",X"97",X"00",X"D7",X"03",X"96",X"02",X"5F",
+		X"D7",X"03",X"5A",X"D7",X"00",X"33",X"39",X"0F",X"BD",X"FC",X"1D",X"C6",X"09",X"7F",X"00",X"BD",
+		X"84",X"1F",X"81",X"10",X"2A",X"08",X"4A",X"81",X"07",X"2B",X"03",X"BD",X"FC",X"09",X"0E",X"39",
+		X"0F",X"BD",X"FC",X"0C",X"C6",X"11",X"20",X"E5",X"17",X"84",X"0F",X"81",X"08",X"2A",X"08",X"A6",
+		X"94",X"AB",X"98",X"A7",X"94",X"20",X"67",X"CB",X"38",X"DE",X"CD",X"A6",X"05",X"36",X"DE",X"D1",
+		X"AB",X"94",X"A7",X"94",X"32",X"2B",X"0C",X"24",X"02",X"6C",X"98",X"BD",X"FB",X"DA",X"5C",X"A6",
+		X"94",X"20",X"4B",X"25",X"F6",X"6A",X"98",X"20",X"F2",X"6F",X"8C",X"DE",X"CD",X"C1",X"A0",X"2B",
+		X"02",X"08",X"08",X"08",X"08",X"08",X"C1",X"C0",X"2B",X"08",X"17",X"84",X"0F",X"81",X"08",X"2B",
+		X"01",X"08",X"86",X"01",X"39",X"DF",X"CD",X"DE",X"D1",X"6A",X"90",X"27",X"DC",X"C1",X"A0",X"2A",
+		X"10",X"C4",X"1F",X"A6",X"94",X"36",X"DE",X"CD",X"A6",X"03",X"BD",X"FB",X"DA",X"0E",X"32",X"08",
+		X"39",X"C1",X"C0",X"2A",X"93",X"A6",X"90",X"44",X"A6",X"94",X"25",X"02",X"A6",X"98",X"C4",X"1F",
+		X"BD",X"FB",X"DA",X"0E",X"DE",X"CD",X"A6",X"04",X"39",X"26",X"CA",X"DF",X"CD",X"E6",X"00",X"2A",
+		X"03",X"7E",X"FD",X"90",X"C4",X"3F",X"C1",X"20",X"2A",X"11",X"A6",X"01",X"BD",X"FB",X"DA",X"0E",
+		X"E6",X"00",X"08",X"08",X"58",X"2B",X"E4",X"A6",X"00",X"08",X"39",X"C4",X"1F",X"17",X"84",X"0F",
+		X"26",X"31",X"A6",X"01",X"97",X"CE",X"A6",X"02",X"97",X"CD",X"BD",X"FD",X"D1",X"DC",X"CD",X"04",
+		X"DD",X"CD",X"E6",X"00",X"C4",X"1F",X"5C",X"5C",X"BD",X"FD",X"D1",X"7C",X"00",X"CE",X"26",X"03",
+		X"7C",X"00",X"CD",X"BD",X"FD",X"D1",X"CB",X"07",X"86",X"09",X"BD",X"FB",X"DB",X"0E",X"E6",X"00",
+		X"08",X"20",X"BF",X"80",X"08",X"2B",X"29",X"DD",X"CF",X"84",X"03",X"C1",X"10",X"2B",X"02",X"8B",
+		X"03",X"16",X"A6",X"01",X"CE",X"00",X"00",X"3A",X"D6",X"CF",X"C1",X"04",X"2A",X"0B",X"A6",X"B4",
+		X"A7",X"AE",X"DE",X"CD",X"D6",X"D0",X"7E",X"FC",X"EA",X"A7",X"B4",X"DE",X"CD",X"7E",X"FC",X"F0",
+		X"4C",X"27",X"17",X"5C",X"C1",X"10",X"2A",X"09",X"96",X"BA",X"A4",X"01",X"97",X"BA",X"7E",X"FC",
+		X"EC",X"96",X"BB",X"A4",X"01",X"97",X"BB",X"7E",X"FC",X"EC",X"C1",X"10",X"2A",X"09",X"96",X"BA",
+		X"AA",X"01",X"97",X"BA",X"7E",X"FC",X"EC",X"96",X"BB",X"AA",X"01",X"97",X"BB",X"7E",X"FC",X"EC",
+		X"C1",X"F0",X"2A",X"17",X"A6",X"01",X"EE",X"02",X"3C",X"DE",X"D1",X"E7",X"8C",X"4C",X"A7",X"90",
+		X"32",X"A7",X"94",X"32",X"A7",X"98",X"DE",X"CD",X"86",X"01",X"39",X"5C",X"27",X"12",X"DE",X"D1",
+		X"5C",X"26",X"10",X"DC",X"CD",X"A7",X"9C",X"E7",X"A0",X"DE",X"CD",X"EE",X"01",X"86",X"01",X"39",
+		X"86",X"FF",X"39",X"A6",X"9C",X"E6",X"A0",X"DD",X"CD",X"DE",X"CD",X"08",X"08",X"08",X"86",X"01",
+		X"39",X"96",X"CE",X"BD",X"FB",X"DA",X"5C",X"96",X"CD",X"BD",X"FB",X"DB",X"5C",X"39",X"26",X"06",
+		X"BD",X"FB",X"93",X"7E",X"FB",X"A8",X"81",X"10",X"2B",X"03",X"7E",X"FE",X"5B",X"81",X"07",X"2A",
+		X"35",X"97",X"CB",X"96",X"D8",X"8A",X"01",X"16",X"C4",X"FE",X"D7",X"D8",X"C6",X"0F",X"BD",X"FB",
+		X"DB",X"86",X"05",X"7F",X"00",X"BD",X"D6",X"BD",X"27",X"FC",X"4A",X"26",X"F6",X"D6",X"CB",X"58",
+		X"58",X"CE",X"EA",X"00",X"3A",X"3C",X"EE",X"00",X"DF",X"C7",X"38",X"EE",X"02",X"DF",X"C3",X"96",
+		X"BE",X"84",X"02",X"97",X"BE",X"39",X"97",X"CC",X"96",X"D8",X"8A",X"02",X"16",X"C4",X"FD",X"D7",
+		X"D8",X"C6",X"0F",X"BD",X"FB",X"DB",X"86",X"05",X"7F",X"00",X"BD",X"D6",X"BD",X"27",X"FC",X"4A",
+		X"26",X"F6",X"D6",X"CC",X"58",X"58",X"CE",X"EA",X"00",X"3A",X"3C",X"EE",X"00",X"DF",X"C9",X"38",
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+		X"3A",X"EE",X"00",X"81",X"20",X"2B",X"22",X"7E",X"FE",X"6E",X"81",X"15",X"2A",X"34",X"3C",X"36",
+		X"BD",X"FB",X"93",X"BD",X"FB",X"A8",X"32",X"38",X"97",X"A4",X"DF",X"84",X"7F",X"00",X"80",X"7F",
+		X"00",X"8C",X"C6",X"B8",X"DA",X"BA",X"D7",X"BA",X"39",X"81",X"13",X"2A",X"DD",X"81",X"1F",X"27",
+		X"DD",X"DF",X"88",X"97",X"A6",X"7F",X"00",X"82",X"7F",X"00",X"8E",X"86",X"78",X"9A",X"BB",X"97",
+		X"BB",X"39",X"81",X"18",X"2A",X"E7",X"DF",X"8A",X"97",X"A7",X"7F",X"00",X"83",X"7F",X"00",X"8F",
+		X"86",X"78",X"9A",X"BB",X"97",X"BB",X"39",X"81",X"15",X"2A",X"E7",X"DF",X"86",X"7F",X"00",X"8D",
+		X"7F",X"00",X"81",X"86",X"B8",X"9A",X"BA",X"97",X"BA",X"39",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"00",X"00",X"00",
+		X"09",X"0A",X"0C",X"0D",X"0F",X"10",X"12",X"13",X"15",X"16",X"18",X"19",X"1B",X"1C",X"1E",X"1F",
+		X"23",X"24",X"26",X"27",X"29",X"2A",X"2C",X"2D",X"2F",X"30",X"32",X"33",X"35",X"36",X"38",X"39",
+		X"22",X"5A",X"38",X"30",X"22",X"3B",X"3B",X"20",X"20",X"64",X"65",X"74",X"61",X"20",X"69",X"73",
+		X"20",X"20",X"2D",X"2D",X"2D",X"2D",X"48",X"20",X"74",X"6F",X"20",X"2D",X"2D",X"2D",X"2D",X"48",
+		X"45",X"4E",X"44",X"48",X"45",X"58",X"3E",X"3E",X"20",X"50",X"61",X"72",X"61",X"6D",X"74",X"65",
+		X"72",X"20",X"65",X"72",X"72",X"6F",X"72",X"20",X"3C",X"3C",X"0D",X"00",X"44",X"55",X"4D",X"50",
+		X"20",X"4C",X"49",X"53",X"54",X"20",X"50",X"41",X"47",X"45",X"20",X"3D",X"20",X"F6",X"06",X"0D",
+		X"0D",X"00",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"68",X"F6",X"00",X"00",X"00",X"00",X"06",X"91",X"68",X"F6",X"06",X"91",X"68",X"F6",X"06",X"91",
+		X"FA",X"00",X"FA",X"00",X"FA",X"00",X"FA",X"00",X"FB",X"86",X"FA",X"00",X"FA",X"D4",X"FA",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/lotlot.zip b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/lotlot.zip
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HcmV?d00001

diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4a.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4a.hex
new file mode 100644
index 00000000..0e16cf8b
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4a.hex	
@@ -0,0 +1,513 @@
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4b.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4b.hex
new file mode 100644
index 00000000..534377e2
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4b.hex	
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4d.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4d.hex
new file mode 100644
index 00000000..89abed9d
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4d.hex	
@@ -0,0 +1,513 @@
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4e.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4e.hex
new file mode 100644
index 00000000..d12ef3bf
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-a-4e.hex	
@@ -0,0 +1,513 @@
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-b-3n.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-b-3n.hex
new file mode 100644
index 00000000..b7ef7de1
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-b-3n.hex	
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-b-4c.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-b-4c.hex
new file mode 100644
index 00000000..1c61bb52
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-b-4c.hex	
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new file mode 100644
index 00000000..02cf2779
--- /dev/null
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-e-2d.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-e-2d.hex
new file mode 100644
index 00000000..4814deca
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-e-2d.hex	
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-e-2f.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-e-2f.hex
new file mode 100644
index 00000000..105c8ccc
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-e-2f.hex	
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-e-2j.hex b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-e-2j.hex
new file mode 100644
index 00000000..a06e2825
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/roms/nu/lr-e-2j.hex	
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diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sdram.sv b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..41f5b7a8
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sdram.sv	
@@ -0,0 +1,348 @@
+//
+// sdram.v
+//
+// sdram controller implementation for the MiST board
+// https://github.com/mist-devel/mist-board
+// 
+// Copyright (c) 2013 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2019 Gyorgy Szombathelyi
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+
+module sdram (
+
+	// interface to the MT48LC16M16 chip
+	inout  reg [15:0] SDRAM_DQ,   // 16 bit bidirectional data bus
+	output reg [12:0] SDRAM_A,    // 13 bit multiplexed address bus
+	output reg        SDRAM_DQML, // two byte masks
+	output reg        SDRAM_DQMH, // two byte masks
+	output reg [1:0]  SDRAM_BA,   // two banks
+	output            SDRAM_nCS,  // a single chip select
+	output            SDRAM_nWE,  // write enable
+	output            SDRAM_nRAS, // row address select
+	output            SDRAM_nCAS, // columns address select
+
+	// cpu/chipset interface
+	input             init_n,     // init signal after FPGA config to initialize RAM
+	input             clk,        // sdram clock
+
+	input             port1_req,
+	output reg        port1_ack,
+	input             port1_we,
+	input      [23:1] port1_a,
+	input       [1:0] port1_ds,
+	input      [15:0] port1_d,
+	output reg [15:0] port1_q,
+
+	input      [16:1] cpu1_addr,
+	output reg [15:0] cpu1_q,
+	input      [16:1] cpu2_addr,
+	output reg [15:0] cpu2_q,
+
+	input             port2_req,
+	output reg        port2_ack,
+	input             port2_we,
+	input      [23:1] port2_a,
+	input       [1:0] port2_ds,
+	input      [15:0] port2_d,
+	output reg [31:0] port2_q,
+	
+	input      [16:2] sp_addr,
+	output reg [31:0] sp_q
+);
+
+localparam RASCAS_DELAY   = 3'd2;   // tRCD=20ns -> 2 cycles@<100MHz
+localparam BURST_LENGTH   = 3'b001; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE    = 1'b0;   // 0=sequential, 1=interleaved
+localparam CAS_LATENCY    = 3'd2;   // 2/3 allowed
+localparam OP_MODE        = 2'b00;  // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1;   // 0= write burst enabled, 1=only single access write
+
+localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 
+
+// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
+localparam RFRSH_CYCLES = 10'd842;
+
+// ---------------------------------------------------------------------
+// ------------------------ cycle state machine ------------------------
+// ---------------------------------------------------------------------
+
+/*
+ SDRAM state machine for 2 bank interleaved access
+ 1 word burst, CL2
+cmd issued  registered
+ 0 RAS0     cas1 - data0 read burst terminated
+ 1          ras0
+ 2          data1 returned
+ 3 CAS0     data1 returned
+ 4 RAS1     cas0
+ 5          ras1
+ 6 CAS1     data0 returned
+*/
+
+localparam STATE_RAS0      = 3'd0;   // first state in cycle
+localparam STATE_RAS1      = 3'd4;   // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_CAS0      = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
+localparam STATE_CAS1      = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
+localparam STATE_READ0     = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
+localparam STATE_READ1     = 3'd3;
+localparam STATE_DS1b      = 3'd0;
+localparam STATE_READ1b    = 3'd4;
+localparam STATE_LAST      = 3'd6;
+
+reg [2:0] t;
+
+always @(posedge clk) begin
+	t <= t + 1'd1;
+	if (t == STATE_LAST) t <= STATE_RAS0;
+end
+
+// ---------------------------------------------------------------------
+// --------------------------- startup/reset ---------------------------
+// ---------------------------------------------------------------------
+
+// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
+// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
+reg [4:0]  reset;
+reg        init = 1'b1;
+always @(posedge clk, negedge init_n) begin
+	if(!init_n) begin
+		reset <= 5'h1f;
+		init <= 1'b1;
+	end else begin
+		if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
+		init <= !(reset == 0);
+	end
+end
+
+// ---------------------------------------------------------------------
+// ------------------ generate ram control signals ---------------------
+// ---------------------------------------------------------------------
+
+// all possible commands
+localparam CMD_INHIBIT         = 4'b1111;
+localparam CMD_NOP             = 4'b0111;
+localparam CMD_ACTIVE          = 4'b0011;
+localparam CMD_READ            = 4'b0101;
+localparam CMD_WRITE           = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE       = 4'b0010;
+localparam CMD_AUTO_REFRESH    = 4'b0001;
+localparam CMD_LOAD_MODE       = 4'b0000;
+
+reg [3:0]  sd_cmd;   // current command sent to sd ram
+reg [15:0] sd_din;
+// drive control signals according to current command
+assign SDRAM_nCS  = sd_cmd[3];
+assign SDRAM_nRAS = sd_cmd[2];
+assign SDRAM_nCAS = sd_cmd[1];
+assign SDRAM_nWE  = sd_cmd[0];
+
+reg [24:1] addr_latch[2];
+reg [24:1] addr_latch_next[2];
+reg [16:1] addr_last[2];
+reg [16:2] addr_last2[2];
+reg [15:0] din_latch[2];
+reg  [1:0] oe_latch;
+reg  [1:0] we_latch;
+reg  [1:0] ds[2];
+
+reg        port1_state;
+reg        port2_state;
+
+localparam PORT_NONE  = 2'd0;
+localparam PORT_CPU1  = 2'd1;
+localparam PORT_CPU2  = 2'd2;
+localparam PORT_SP    = 2'd1;
+localparam PORT_REQ   = 2'd3;
+
+reg  [1:0] next_port[2];
+reg  [1:0] port[2];
+
+reg        refresh;
+reg [10:0] refresh_cnt;
+wire       need_refresh = (refresh_cnt >= RFRSH_CYCLES);
+
+// PORT1: bank 0,1
+always @(*) begin
+	if (refresh) begin
+		next_port[0] = PORT_NONE;
+		addr_latch_next[0] = addr_latch[0];
+	end else if (port1_req ^ port1_state) begin
+		next_port[0] = PORT_REQ;
+		addr_latch_next[0] = { 1'b0, port1_a };
+	end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
+		next_port[0] = PORT_CPU1;
+		addr_latch_next[0] = { 8'd0, cpu1_addr };
+	end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
+		next_port[0] = PORT_CPU2;
+		addr_latch_next[0] = { 8'd0, cpu2_addr };
+	end else begin
+		next_port[0] = PORT_NONE;
+		addr_latch_next[0] = addr_latch[0];
+	end
+end
+
+// PORT1: bank 2,3
+always @(*) begin
+	if (port2_req ^ port2_state) begin
+		next_port[1] = PORT_REQ;
+		addr_latch_next[1] = { 1'b1, port2_a };
+	end else if (sp_addr != addr_last2[PORT_SP]) begin
+		next_port[1] = PORT_SP;
+		addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
+	end else begin
+		next_port[1] = PORT_NONE;
+		addr_latch_next[1] = addr_latch[1];
+	end
+end
+
+always @(posedge clk) begin
+
+	// permanently latch ram data to reduce delays
+	sd_din <= SDRAM_DQ;
+	SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+	{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
+	sd_cmd <= CMD_NOP;  // default: idle
+	refresh_cnt <= refresh_cnt + 1'd1;
+
+	if(init) begin
+		// initialization takes place at the end of the reset phase
+		if(t == STATE_RAS0) begin
+
+			if(reset == 15) begin
+				sd_cmd <= CMD_PRECHARGE;
+				SDRAM_A[10] <= 1'b1;      // precharge all banks
+			end
+
+			if(reset == 10 || reset == 8) begin
+				sd_cmd <= CMD_AUTO_REFRESH;
+			end
+
+			if(reset == 2) begin
+				sd_cmd <= CMD_LOAD_MODE;
+				SDRAM_A <= MODE;
+				SDRAM_BA <= 2'b00;
+			end
+		end
+	end else begin
+		// RAS phase
+		// bank 0,1
+		if(t == STATE_RAS0) begin
+			addr_latch[0] <= addr_latch_next[0];
+			port[0] <= next_port[0];
+			{ oe_latch[0], we_latch[0] } <= 2'b00;
+
+			if (next_port[0] != PORT_NONE) begin
+				sd_cmd <= CMD_ACTIVE;
+				SDRAM_A <= addr_latch_next[0][22:10];
+				SDRAM_BA <= addr_latch_next[0][24:23];
+				addr_last[next_port[0]] <= addr_latch_next[0][16:1];
+				if (next_port[0] == PORT_REQ) begin
+					{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
+					ds[0] <= port1_ds;
+					din_latch[0] <= port1_d;
+					port1_state <= port1_req;
+				end else begin
+					{ oe_latch[0], we_latch[0] } <= 2'b10;
+					ds[0] <= 2'b11;
+				end
+			end
+		end
+
+		// bank 2,3
+		if(t == STATE_RAS1) begin
+			refresh <= 1'b0;
+			addr_latch[1] <= addr_latch_next[1];
+			{ oe_latch[1], we_latch[1] } <= 2'b00;
+			port[1] <= next_port[1];
+
+			if (next_port[1] != PORT_NONE) begin
+				sd_cmd <= CMD_ACTIVE;
+				SDRAM_A <= addr_latch_next[1][22:10];
+				SDRAM_BA <= addr_latch_next[1][24:23];
+				addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
+				if (next_port[1] == PORT_REQ) begin
+					{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
+					ds[1] <= port2_ds;
+					din_latch[1] <= port2_d;
+					port2_state <= port2_req;
+				end else begin
+					{ oe_latch[1], we_latch[1] } <= 2'b10;
+					ds[1] <= 2'b11;
+				end
+			end
+
+			if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
+				refresh <= 1'b1;
+				refresh_cnt <= 0;
+				sd_cmd <= CMD_AUTO_REFRESH;
+			end
+		end
+
+		// CAS phase
+		if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
+			sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
+			{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
+			if (we_latch[0]) begin
+				SDRAM_DQ <= din_latch[0];
+				port1_ack <= port1_req;
+			end
+			SDRAM_A <= { 4'b0010, addr_latch[0][9:1] };  // auto precharge
+			SDRAM_BA <= addr_latch[0][24:23];
+		end
+
+		if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
+			sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
+			{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+			if (we_latch[1]) begin
+				SDRAM_DQ <= din_latch[1];
+				port2_ack <= port2_req;
+			end
+			SDRAM_A <= { 4'b0010, addr_latch[1][9:1] };  // auto precharge
+			SDRAM_BA <= addr_latch[1][24:23];
+		end
+
+		// Data returned
+		if(t == STATE_READ0 && oe_latch[0]) begin
+			case(port[0])
+				PORT_REQ:  begin port1_q <= sd_din; port1_ack <= port1_req; end
+				PORT_CPU1: begin cpu1_q  <= sd_din; end
+				PORT_CPU2: begin cpu2_q  <= sd_din; end
+				default: ;
+			endcase;
+		end
+
+		if(t == STATE_READ1 && oe_latch[1]) begin
+			case(port[1])
+				PORT_REQ:	port2_q[15:0] <= sd_din;
+				PORT_SP :    sp_q[15:0] <= sd_din;
+				default: ;
+			endcase;
+		end
+
+		if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+
+		if(t == STATE_READ1b && oe_latch[1]) begin
+			case(port[1])
+				PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
+				PORT_SP : begin    sp_q[31:16] <= sd_din; end
+				default: ;
+			endcase;
+		end
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/spram.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d86010fc
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/spram.vhd	
@@ -0,0 +1,91 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY spram IS
+	GENERIC
+	(
+		init_file			: string := "";
+		--numwords_a		: natural;
+		widthad_a			: natural;
+		width_a				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		wren_a => wren,
+		clock0 => clock,
+		address_a => address,
+		data_a => data,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprite_array.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprite_array.vhd
new file mode 100644
index 00000000..880f09f2
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprite_array.vhd	
@@ -0,0 +1,164 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+--use ieee.std_logic_arith.all;
+--use IEEE.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+
+entity sprite_array is
+  generic
+  (
+    N_SPRITES   : integer;
+    DELAY       : integer
+  );
+	port
+	(
+		reset				: in std_logic;
+
+    -- register interface
+    reg_i       : in to_SPRITE_REG_t;
+
+    -- video control signals
+    video_ctl   : in from_VIDEO_CTL_t;
+
+    -- extra data
+    graphics_i  : in to_GRAPHICS_t;
+
+		-- sprite data
+    row_a       : out SPRITE_ROW_A_t;
+    row_d       : in SPRITE_ROW_D_t;
+
+    -- video data
+    rgb         : out RGB_t;
+    set         : out std_logic;
+    pri         : out std_logic;
+    spr0_set    : out std_logic
+	);
+end entity sprite_array;
+
+architecture SYN of sprite_array is
+
+	type reg_a_t is array (natural range <>) of from_SPRITE_REG_t;
+  type ctl_i_a_t is array (natural range <>) of to_SPRITE_CTL_t;
+  type ctl_o_a_t is array (natural range <>) of from_SPRITE_CTL_t;
+  
+	alias clk       : std_logic is video_ctl.clk;
+	alias clk_ena   : std_logic is video_ctl.clk_ena;
+	
+	signal reg_o    : reg_a_t(0 to N_SPRITES-1);
+  signal ctl_i    : ctl_i_a_t(0 to N_SPRITES-1);
+  signal ctl_o    : ctl_o_a_t(0 to N_SPRITES-1);
+	
+	signal ld_r     : std_logic_vector(N_SPRITES-1 downto 0);
+	
+begin
+
+	-- Sprite Data Load Arbiter
+	-- - enables each sprite controller during hblank
+	--   to allow loading of sprite row data into row buffer
+	process (clk, clk_ena, reset)
+		variable i : integer range 0 to N_SPRITES-1;
+	begin
+		if reset = '1' then
+			-- enable must be 1 clock behind address to latch data after fetch
+			--ld_r <= (N_SPRITES-1 => '1', others => '0');
+      -- make ISE 9.2.03i happy...
+			ld_r(ld_r'left) <= '1';
+			ld_r(ld_r'left-1 downto 0) <= (others => '0');
+			i := 0;
+		elsif rising_edge(clk) and clk_ena = '1' then
+			ld_r <= ld_r(ld_r'left-1 downto 0) & ld_r(ld_r'left);
+			if i = N_SPRITES-1 then
+			  i := 0;
+			else
+			  i := i + 1;
+			end if;
+      row_a <= ctl_o(i).a;
+		end if;
+	end process;
+
+  -- sprite row data fan-out
+  GEN_ROW_D : for i in 0 to N_SPRITES-1 generate
+    ctl_i(i).ld <= ld_r(i);
+    ctl_i(i).d <= row_d;
+  end generate GEN_ROW_D;
+  
+	-- Sprite Priority Encoder
+	-- - determines which sprite pixel (if any) is to be displayed
+	-- We can use a clocked process here because the tilemap
+	-- output is 1 clock behind at this point
+	process (clk, clk_ena)
+		variable spr_on_v 	: std_logic := '0';
+		variable spr_pri_v 	: std_logic := '0';
+	begin
+		if rising_edge(clk) and clk_ena = '1' then
+			spr_on_v := '0';
+			spr_pri_v := '0';
+			for i in 0 to N_SPRITES-1 loop
+				-- if highest priority = 0 and pixel on
+				if spr_pri_v = '0' and ctl_o(i).set = '1' then
+					-- if no sprite on or this priority = 1
+					if spr_on_v = '0' or reg_o(i).pri = '1' then
+						rgb <= ctl_o(i).rgb;
+						spr_on_v := '1';					    -- flag as sprite on
+						spr_pri_v := reg_o(i).pri;		-- store priority
+					end if;
+				end if;
+			end loop;
+		end if;
+		set <= spr_on_v;
+		pri <= spr_pri_v;
+	end process;
+
+	-- for NES, and perhaps others
+	-- it's actually more complicated than this
+	-- but it'll do for now...
+	spr0_set <= ctl_o(0).set;
+		
+	--
+	-- Component Instantiation
+	--
+	
+	GEN_REGS : for i in 0 to N_SPRITES-1 generate
+	
+		sptReg_inst : entity work.sptReg
+			generic map
+			(
+				INDEX			=> i
+			)
+			port map
+			(
+        reg_i           => reg_i,
+				reg_o           => reg_o(i)
+			);
+
+		sptCtl_inst : entity work.spritectl
+			generic map
+			(
+				INDEX			=> i,
+				DELAY     => DELAY
+			)
+			port map
+			(
+        -- sprite registers
+        reg_i       => reg_o(i),
+        
+        -- video control signals
+        video_ctl   => video_ctl,
+
+        -- sprite control signals
+        ctl_i       => ctl_i(i),
+        ctl_o       => ctl_o(i),
+
+        graphics_i  => graphics_i
+      );
+				
+	end generate GEN_REGS;
+	
+end SYN;
+
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprite_pkg.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprite_pkg.vhd
new file mode 100644
index 00000000..ee5cf179
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprite_pkg.vhd	
@@ -0,0 +1,97 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+--use IEEE.numeric_std.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.video_controller_pkg.all;
+
+package sprite_pkg is
+
+  subtype SPRITE_N_t is std_logic_vector(11 downto 0);
+  subtype SPRITE_A_t is std_logic_vector(7 downto 0);
+  subtype SPRITE_D_t is std_logic_vector(7 downto 0);
+  
+  type from_SPRITE_REG_t is record
+    n         : SPRITE_N_t;
+    x         : std_logic_vector(10 downto 0);
+    y         : std_logic_vector(10 downto 0);
+    xflip     : std_logic;
+    yflip     : std_logic;
+    colour    : std_logic_vector(7 downto 0);
+    pri       : std_logic;
+  end record;
+  
+  type to_SPRITE_REG_t is record
+    clk       : std_logic;
+    clk_ena   : std_logic;
+    wr        : std_logic;
+    a         : SPRITE_A_t;
+    d         : SPRITE_D_t;
+  end record;
+
+  function NULL_TO_SPRITE_REG return to_SPRITE_REG_t;
+  
+  subtype SPRITE_ROW_D_t is std_logic_vector(63 downto 0);
+  subtype SPRITE_ROW_A_t is std_logic_vector(15 downto 0);
+  
+  type to_SPRITE_CTL_t is record
+    ld        : std_logic;
+    d         : SPRITE_ROW_D_t;
+  end record;
+  
+  type from_SPRITE_CTL_t is record
+    a         : SPRITE_ROW_A_t;
+    rgb       : RGB_t;
+    set       : std_logic;
+  end record;
+
+  function NULL_TO_SPRITE_CTL return to_SPRITE_CTL_t;
+
+  component sprite_array is
+    generic
+    (
+      N_SPRITES   : integer;
+      DELAY       : integer
+    );
+    port
+    (
+      reset				: in std_logic;
+
+      -- register interface
+      reg_i       : in to_SPRITE_REG_t;
+
+      -- video control signals
+      video_ctl   : in from_VIDEO_CTL_t;
+
+      -- extra data
+      graphics_i  : in to_GRAPHICS_t;
+
+      -- sprite data
+      row_a       : out SPRITE_ROW_A_t;
+      row_d       : in SPRITE_ROW_D_t;
+
+      -- video data
+      rgb         : out RGB_t;
+      set         : out std_logic;
+      pri         : out std_logic;
+      spr0_set    : out std_logic
+    );
+  end component sprite_array;
+
+  function flip_row
+  (
+    row_in      : std_logic_vector;
+    flip        : std_logic
+  )
+  return SPRITE_ROW_D_t;
+
+  function flip_1
+  (
+    d_i         : std_logic_vector;
+    flip        : std_logic
+  )
+  return std_logic_vector;
+
+end package sprite_pkg;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprite_pkg_body.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprite_pkg_body.vhd
new file mode 100644
index 00000000..551261b2
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprite_pkg_body.vhd	
@@ -0,0 +1,62 @@
+library work;
+use work.pace_pkg.all;
+--use work.sprite_pkg.all;
+
+package body sprite_pkg is
+
+  function NULL_TO_SPRITE_REG return to_SPRITE_REG_t is
+  begin
+    return ('0', '0', '0', (others => '0'), (others => '0'));
+  end function NULL_TO_SPRITE_REG;
+
+  function NULL_TO_SPRITE_CTL return to_SPRITE_CTL_t is
+  begin
+    return ('0', (others => '0'));
+  end function NULL_TO_SPRITE_CTL;
+
+  function flip_row
+  (
+    row_in      : std_logic_vector;
+    flip        : std_logic
+  )
+  return std_logic_vector is
+  
+    constant HALF	    : natural := (row_in'length / 2) - 1;
+
+    alias row_in_0    : std_logic_vector(row_in'length-1 downto 0)
+                          is row_in;
+    variable row_out  : std_logic_vector(row_in_0'range);
+    
+  begin
+
+    if flip = '0' then
+      return row_in;
+    else
+      for i in 0 to HALF loop
+        row_out ((HALF-i)*2+1 downto (HALF-i)*2) := row_in_0(i*2+1 downto i*2);
+      end loop;
+      return row_out;
+    end if;
+  
+  end flip_row;
+
+  function flip_1
+  (
+    d_i   : std_logic_vector;
+    flip  : std_logic
+   )
+   return std_logic_vector is
+    alias d_i_0   : std_logic_vector(d_i'length-1 downto 0) is d_i;
+    variable d_o  : std_logic_vector(d_i_0'range);
+   begin
+    if flip = '0' then
+      return d_i;
+    else
+      for i in d_i_0'range loop
+        d_o(i) := d_i_0(d_i_0'high-i);
+      end loop;
+      return d_o;
+    end if;
+   end function flip_1;
+    
+end package body sprite_pkg;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/spritectl.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/spritectl.vhd
new file mode 100644
index 00000000..dc91db61
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/spritectl.vhd	
@@ -0,0 +1,202 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+--use work.project_pkg.all;
+use work.platform_pkg.all;    
+use work.platform_variant_pkg.all;
+
+entity spritectl is
+	generic
+	(
+		INDEX		: natural;
+		DELAY   : integer
+	);
+	port               
+	(
+    -- sprite registers
+    reg_i       : in from_SPRITE_REG_t;
+    
+    -- video control signals
+    video_ctl   : in from_VIDEO_CTL_t;
+
+    -- sprite control signals
+    ctl_i       : in to_SPRITE_CTL_t;
+    ctl_o       : out from_SPRITE_CTL_t;
+    
+		graphics_i  : in to_GRAPHICS_t
+	);
+end entity spritectl;
+
+architecture SYN of spritectl is
+
+  alias clk       : std_logic is video_ctl.clk;
+  alias clk_ena   : std_logic is video_ctl.clk_ena;
+  
+  signal flipData : std_logic_vector(47 downto 0);   -- flipped row data
+   
+  alias rgb       : RGB_t is ctl_o.rgb;
+  
+begin
+
+  flipData(47 downto 32) <= flip_1 (ctl_i.d(47 downto 32), reg_i.xflip);
+  flipData(31 downto 16) <= flip_1 (ctl_i.d(31 downto 16), reg_i.xflip);
+  flipData(15 downto 0) <= flip_1 (ctl_i.d(15 downto 0), reg_i.xflip);
+  
+	process (clk, clk_ena)
+
+   	variable rowStore : std_logic_vector(47 downto 0);  -- saved row of spt to show during visibile period
+		variable pel      : std_logic_vector(2 downto 0);
+    variable x        : unsigned(video_ctl.x'range);
+    variable y        : unsigned(video_ctl.y'range);
+    variable yMat     : boolean;      -- raster is between first and last line of sprite
+    variable xMat     : boolean;      -- raster in between left edge and end of line
+
+    variable height     : unsigned(6 downto 0);
+		-- the width of rowCount determines the scanline multipler
+		-- - eg.	(4 downto 0) is 1:1
+		-- 				(5 downto 0) is 2:1 (scan-doubling)
+--  	variable rowCount : unsigned(3+PACE_VIDEO_V_SCALE downto 0);
+--    alias row         : unsigned(4 downto 0) is 
+--                          rowCount(rowCount'left downto rowCount'left-4);
+    variable rowCount   : unsigned(height'range);
+    alias row           : unsigned(rowCount'range) is rowCount;
+    -- which part of the sprite is being drawn
+    alias segment       : unsigned(1 downto 0) is rowCount(5 downto 4);
+    
+    variable prom_i     : integer range sprite_prom'range;
+    variable code       : std_logic_vector(9 downto 0);
+    variable pal_i      : std_logic_vector(7 downto 0);
+		variable pal_rgb    : pal_rgb_t;
+    
+  begin
+
+		if rising_edge(clk) then
+      if clk_ena = '1' then
+        if video_ctl.hblank = '1' then
+
+          x := unsigned(reg_i.x) - M62_VIDEO_H_OFFSET + PACE_VIDEO_PIPELINE_DELAY - 3;
+          y := 256 + 128 - 15 - unsigned(reg_i.y);
+
+          -- hande sprite height, placement
+          prom_i := to_integer(unsigned(reg_i.n(9 downto 5)));
+          code := reg_i.n(9 downto 0); -- default
+          case sprite_prom(prom_i) is
+            when 1 =>
+              -- double height
+              height := to_unsigned(2*16,height'length);
+              y := y - 16;
+            when 2 =>
+              -- quadruple height
+              height := to_unsigned(4*16,height'length);
+              y := y - 3*16;
+            when others =>
+              height := to_unsigned(16,height'length);
+          end case;
+          
+          -- do this 1st because we don't have many clocks
+          if y = unsigned(video_ctl.y) then
+            -- start counting sprite row
+            rowCount := (others => '0');
+            yMat := true;
+          elsif row = height then
+            yMat := false;				
+          end if;
+
+          case sprite_prom(prom_i) is
+            when 1 =>
+              -- double height
+              if reg_i.yflip = '1' then
+                code(0) := not segment(0);
+              else
+                code(0) := segment(0);
+              end if;
+            when 2 =>
+              -- quadruple height
+              if reg_i.yflip = '1' then
+                code(1 downto 0) := not std_logic_vector(segment);
+              else
+                code(1 downto 0) := std_logic_vector(segment);
+              end if;
+            when others =>
+              null;
+          end case;
+
+          xMat := false;
+          -- stop sprites wrapping from bottom of screen
+          if y = 0 then
+            yMat := false;
+          end if;
+          
+          -- sprites not visible before row 16				
+          if ctl_i.ld = '1' then
+            if yMat then
+              rowStore := flipData;			-- load sprite data
+            else
+              rowStore := (others => '0');
+            end if;
+          end if;
+              
+        end if; -- hblank='1'
+        
+        if video_ctl.stb = '1' then
+      
+          if x = unsigned(video_ctl.x) then
+            -- count up at left edge of sprite
+            rowCount := rowCount + 1;
+            -- start of sprite
+            --if unsigned(x) /= 0 and unsigned(x) < 240 then
+              xMat := true;
+            --end if;
+          end if;
+          
+          if xMat then
+            -- shift in next pixel
+            pel := rowStore(rowStore'left-32) & rowStore(rowStore'left-16) & rowStore(rowStore'left);
+            rowStore(47 downto 32) := rowStore(46 downto 32) & '0';
+            rowStore(31 downto 16) := rowStore(30 downto 16) & '0';
+            rowStore(15 downto 0) := rowStore(14 downto 0) & '0';
+          end if;
+
+        end if;
+
+        if PLATFORM_VARIANT = "ldrun" or
+            PLATFORM_VARIANT = "battroad" then
+          pal_i := '0' & reg_i.colour(3 downto 0) & pel;
+        else
+          pal_i := reg_i.colour(4 downto 0) & pel;
+        end if;
+        --pal_i := "000" & std_logic_vector(to_unsigned(INDEX,5));
+        pal_rgb := sprite_pal(to_integer(unsigned(pal_i)));
+        rgb.r <= pal_rgb(0) & "00";
+        rgb.g <= pal_rgb(1) & "00";
+        rgb.b <= pal_rgb(2) & "00";
+
+        -- set pixel transparency based on match
+        ctl_o.set <= '0';
+        if xMat and pel /= "000" then
+          if graphics_i.bit8(0)(4) = '1' then
+            ctl_o.set <= '1';
+          end if;
+        end if;
+
+      end if; -- clk_ena='1'
+    end if; -- rising_edge(clk)
+    
+    -- generate sprite data address
+    ctl_o.a(15) <= '0'; -- unused
+    ctl_o.a(14 downto 5) <= code;
+    ctl_o.a(4) <= '0'; -- dual-port RAM
+    if reg_i.yflip = '0' then
+      ctl_o.a(3 downto 0) <= std_logic_vector(row(3 downto 0));
+    else
+      ctl_o.a(3 downto 0) <=  not std_logic_vector(row(3 downto 0));
+    end if;
+
+  end process;
+
+end architecture SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/spritereg.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/spritereg.vhd
new file mode 100644
index 00000000..107edb1c
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/spritereg.vhd	
@@ -0,0 +1,68 @@
+Library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.sprite_pkg.all;
+
+entity sptReg is
+
+	generic
+	(
+		INDEX			: natural
+	);
+	port
+	(
+    reg_i     : in to_SPRITE_REG_t;
+    reg_o     : out from_SPRITE_REG_t
+	);
+
+end sptReg;
+
+architecture SYN of sptReg is
+
+  alias clk       : std_logic is reg_i.clk;
+  alias clk_ena   : std_logic is reg_i.clk_ena;
+
+begin
+
+  process (clk, clk_ena)
+  begin
+    if rising_edge(clk) then
+      if clk_ena = '1' then
+        if reg_i.a(7 downto 3) = std_logic_vector(to_unsigned(INDEX, 5)) then
+          if reg_i.wr = '1' then
+            case reg_i.a(2 downto 0) is
+              when "000" =>
+                reg_o.colour(4 downto 0) <= reg_i.d(4 downto 0);
+              when "010" =>
+                reg_o.y(7 downto 0) <= reg_i.d;
+              when "011" =>
+                reg_o.y(8) <= reg_i.d(0);
+              when "100" =>
+                reg_o.n(7 downto 0) <= reg_i.d(7 downto 0);
+              when "101" =>
+                reg_o.yflip <= reg_i.d(7);
+                reg_o.xflip <= reg_i.d(6);
+                reg_o.n(10 downto 8) <= reg_i.d(2 downto 0);
+              when "110" =>
+                reg_o.x(7 downto 0) <= reg_i.d;
+              when "111" =>
+                reg_o.x(8) <= reg_i.d(0);
+              when others =>
+                null;
+            end case;
+          end if; -- reg_i.wr='1'
+        end if; -- reg_i.a()=INDEX
+      end if; -- clk_ena='1'
+    end if; -- rising_edge(clk)
+  end process;
+
+  reg_o.x(reg_o.x'left downto 9) <= (others => '0');
+  reg_o.y(reg_o.y'left downto 9) <= (others => '0');
+  reg_o.n(reg_o.n'left downto 11) <= (others => '0');
+  reg_o.colour(reg_o.colour'left downto 5) <= (others => '0');
+  reg_o.pri <= '1';
+
+end SYN;
+
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprom.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..292a214f
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/sprom.vhd	
@@ -0,0 +1,83 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		--numwords_a	  : natural;
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/target_top.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/target_top.vhd
new file mode 100644
index 00000000..4064a09c
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/target_top.vhd	
@@ -0,0 +1,145 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.platform_pkg.all;
+
+entity target_top is port(
+		clock_sys       : in std_logic;
+		clock_vid      	: in std_logic;
+		clk_aud      		: in std_logic;
+		reset_in        : in std_logic;
+		audio_out       : out std_logic_vector(11 downto 0);
+		usr_coin1      	: in std_logic;
+		usr_coin2       : in std_logic;
+		usr_service     : in std_logic;
+		usr_start1      : in std_logic;
+		usr_start2      : in std_logic;
+		p1_up           : in std_logic;
+		p1_dw           : in std_logic;
+		p1_lt           : in std_logic;
+		p1_rt           : in std_logic;
+		p1_f1           : in std_logic;
+		p1_f2           : in std_logic;
+		
+		p2_up           : in std_logic;
+		p2_dw           : in std_logic;
+		p2_lt           : in std_logic;
+		p2_rt           : in std_logic;
+		p2_f1           : in std_logic;
+		p2_f2           : in std_logic;
+
+		VGA_VS          : out std_logic;
+		VGA_HS          : out std_logic;
+		VGA_R           : out std_logic_vector(3 downto 0);
+		VGA_G           : out std_logic_vector(3 downto 0);
+		VGA_B           : out std_logic_vector(3 downto 0);
+		cpu_rom_addr    : out std_logic_vector(14 downto 0);
+		cpu_rom_do      : in std_logic_vector(7 downto 0);
+		snd_rom_addr    : out std_logic_vector(13 downto 0);
+		snd_rom_do      : in std_logic_vector(7 downto 0)
+  );
+end target_top;
+
+architecture SYN of target_top is 
+  
+  signal clkrst_i       : from_CLKRST_t;
+  signal buttons_i      : from_BUTTONS_t;
+  signal switches_i     : from_SWITCHES_t;
+  signal leds_o         : to_LEDS_t;
+  signal inputs_i       : from_INPUTS_t;
+  signal video_i        : from_VIDEO_t;
+  signal video_o        : to_VIDEO_t;
+  signal platform_i     : from_PLATFORM_IO_t;
+  signal platform_o     : to_PLATFORM_IO_t;
+  signal sound_data     : std_logic_vector(7 downto 0);
+
+begin
+	clkrst_i.clk(0) <= clock_sys;
+	clkrst_i.clk(1) <= clock_vid;		
+	clkrst_i.arst <= reset_in;
+	clkrst_i.arst_n <= not clkrst_i.arst;
+
+GEN_RESETS : for i in 0 to 3 generate
+	process (clkrst_i.clk(i), clkrst_i.arst)
+		variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
+			begin
+				if clkrst_i.arst = '1' then
+					rst_r := (others => '1');
+				elsif rising_edge(clkrst_i.clk(i)) then
+					rst_r := rst_r(rst_r'left-1 downto 0) & '0';
+				end if;
+				clkrst_i.rst(i) <= rst_r(rst_r'left);
+    end process;
+end generate GEN_RESETS;
+
+ video_i.clk <= clkrst_i.clk(1);
+ video_i.clk_ena <= '1';
+ video_i.reset <= clkrst_i.rst(1);
+ VGA_R <= video_o.rgb.r(9 downto 6);
+ VGA_G <= video_o.rgb.g(9 downto 6);
+ VGA_B <= video_o.rgb.b(9 downto 6);
+ VGA_HS <= video_o.hsync;
+ VGA_VS <= video_o.vsync;
+
+--Sound_Board : entity work.Sound_Board
+--	port map(
+--		clock_E    		=> clk_aud,
+--		areset     		=> clkrst_i.rst(1),
+--		select_sound  	=> sound_data,
+--		audio_out     	=> audio_out,
+--		snd_rom_addr   => snd_rom_addr,
+ --     snd_rom_do     => snd_rom_do,
+--		dbg_cpu_addr  	=> open
+--	);
+ 
+pace_inst : entity work.pace                                            
+	port map(
+		clkrst_i				=> clkrst_i,
+		buttons_i         => buttons_i,
+		switches_i        => switches_i,
+		inputs_i          => inputs_i,
+		video_i           => video_i,
+		video_o           => video_o,
+		sound_data_o 		=> sound_data,
+      platform_i        => platform_i,
+      platform_o        => platform_o,
+		cpu_rom_addr      => cpu_rom_addr,
+	   cpu_rom_do        => cpu_rom_do
+    );
+
+		inputs_i.jamma_n.coin(1) <= not usr_coin1;
+		inputs_i.jamma_n.coin(2) <= not usr_coin2;
+		inputs_i.jamma_n.service <= not usr_service;
+		inputs_i.jamma_n.p(1).start <= not usr_start1;
+		inputs_i.jamma_n.p(2).start <= not usr_start2;
+		
+		inputs_i.jamma_n.p(1).up <= not p1_up;
+		inputs_i.jamma_n.p(1).down <= not p1_dw;
+		inputs_i.jamma_n.p(1).left <= not p1_lt;
+		inputs_i.jamma_n.p(1).right <= not p1_rt;
+		inputs_i.jamma_n.p(1).button(1) <= not p1_f1; 
+		inputs_i.jamma_n.p(1).button(2) <= not p1_f2; 
+		inputs_i.jamma_n.p(1).button(3) <= '1';
+		inputs_i.jamma_n.p(1).button(4) <= '1';
+		inputs_i.jamma_n.p(1).button(5) <= '1';
+
+		inputs_i.jamma_n.p(2).up <= not p2_up;
+		inputs_i.jamma_n.p(2).down <= not p2_dw;
+		inputs_i.jamma_n.p(2).left <= not p2_lt;
+		inputs_i.jamma_n.p(2).right <= not p2_rt;		
+		inputs_i.jamma_n.p(2).button(1) <= not p2_f1; 
+		inputs_i.jamma_n.p(2).button(2) <= not p2_f2; 
+		inputs_i.jamma_n.p(2).button(3) <= '1';
+		inputs_i.jamma_n.p(2).button(4) <= '1';
+		inputs_i.jamma_n.p(2).button(5) <= '1';
+ 
+	-- not currently wired to any inputs
+	inputs_i.jamma_n.coin_cnt <= (others => '1');
+	inputs_i.jamma_n.tilt <= '1';
+	inputs_i.jamma_n.test <= '1';
+end SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/tilemapctl.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/tilemapctl.vhd
new file mode 100644
index 00000000..9ccad9f8
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/tilemapctl.vhd	
@@ -0,0 +1,106 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+--use work.project_pkg.all;
+use work.platform_pkg.all;
+use work.platform_variant_pkg.all;
+use work.video_controller_pkg.all;
+
+--
+--	Irem M62 Tilemap Controller
+--
+--	Tile data is 2 BPP.
+--
+
+architecture TILEMAP_1 of tilemapCtl is
+
+  alias clk       : std_logic is video_ctl.clk;
+  alias clk_ena   : std_logic is video_ctl.clk_ena;
+  alias stb       : std_logic is video_ctl.stb;
+  alias hblank    : std_logic is video_ctl.hblank;
+  alias vblank    : std_logic is video_ctl.vblank;
+  
+  signal x        : std_logic_vector(video_ctl.x'range);
+  signal y        : std_logic_vector(video_ctl.y'range);
+  
+  alias rot_en    : std_logic is graphics_i.bit8(0)(0);
+  alias hscroll   : std_logic_vector(15 downto 0) is graphics_i.bit16(0);
+  
+begin
+
+  -- not used
+	ctl_o.map_a(ctl_o.map_a'left downto 11) <= (others => '0');
+  ctl_o.attr_a(ctl_o.attr_a'left downto 11) <= (others => '0');
+  ctl_o.tile_a(ctl_o.tile_a'left downto 13) <= (others => '0');
+
+  -- screen rotation
+  x <=  std_logic_vector(M62_VIDEO_H_OFFSET + unsigned(video_ctl.x)) when unsigned(y) < 6*8 else
+        std_logic_vector(M62_VIDEO_H_OFFSET + unsigned(video_ctl.x) + unsigned(hscroll(8 downto 0))); 
+        -- when rot_en = '0' else not video_ctl.y;
+  --y <= not video_ctl.y when rot_en = '0' else 32 + video_ctl.x;
+  y <= video_ctl.y; -- when rot_en = '0' else video_ctl.x;
+  
+  -- generate pixel
+  process (clk, clk_ena)
+
+    variable tile_d_r   : std_logic_vector(23 downto 0);
+    variable attr_d_r   : std_logic_vector(7 downto 0);
+		variable pel        : std_logic_vector(2 downto 0);
+    variable pal_i      : std_logic_vector(7 downto 0);
+		variable pal_rgb    : pal_rgb_t;
+
+  begin
+  
+  	if rising_edge(clk) then
+      if clk_ena = '1' then
+
+        -- 1st stage of pipeline
+        -- - set tilemap, attribute address
+        ctl_o.map_a(10 downto 6) <= y(7 downto 3);
+        ctl_o.map_a(5 downto 0) <= x(8 downto 3);
+        ctl_o.attr_a(10 downto 6) <= y(7 downto 3);
+        ctl_o.attr_a(5 downto 0) <= x(8 downto 3);
+
+        -- 2nd stage of pipeline
+        -- - set tile address
+        if x(2 downto 0) = "010" then
+          ctl_o.tile_a(12 downto 11) <= ctl_i.attr_d(7 downto 6);
+          ctl_o.tile_a(10 downto 3) <= ctl_i.map_d(7 downto 0);
+          ctl_o.tile_a(2 downto 0) <= y(2 downto 0);
+        end if;
+        
+        -- 3rd stage of pipeline
+        -- - read tile, attribute data from ROM
+        if x(2 downto 0) = "100" then
+          tile_d_r := ctl_i.tile_d(tile_d_r'range);
+          attr_d_r := ctl_i.attr_d(7 downto 0);
+        elsif stb = '1' then
+          tile_d_r := tile_d_r(tile_d_r'left-1 downto 0) & '0';
+        end if;
+
+        -- extract R,G,B from colour palette
+        pel := tile_d_r(tile_d_r'left-16) & tile_d_r(tile_d_r'left-8) & tile_d_r(tile_d_r'left);
+        pal_i := attr_d_r(4 downto 0) & pel;
+        pal_rgb := tile_pal(to_integer(unsigned(pal_i)));
+        ctl_o.rgb.r <= pal_rgb(0) & "00";
+        ctl_o.rgb.g <= pal_rgb(1) & "00";
+        ctl_o.rgb.b <= pal_rgb(2) & "00";
+        ctl_o.set <= '0'; -- default
+--        if pel /= "000" then
+--            pal_rgb(0)(7 downto 5) /= "000" or
+--            pal_rgb(1)(7 downto 5) /= "000" or
+--            pal_rgb(2)(7 downto 5) /= "000" then
+          if graphics_i.bit8(0)(3) = '1' then
+            ctl_o.set <= '1';
+          end if;
+--        end if;
+
+      end if; -- clk_ena
+		end if; -- rising_edge_clk
+
+  end process;
+
+end architecture TILEMAP_1;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/tilemapctl_e.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/tilemapctl_e.vhd
new file mode 100644
index 00000000..8d93334b
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/tilemapctl_e.vhd	
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+--use work.project_pkg.all;
+use work.platform_pkg.all;
+use work.video_controller_pkg.all;
+
+entity tilemapCtl is          
+  generic
+  (
+    DELAY       : integer
+  );
+  port               
+  (
+    reset				: in std_logic;
+
+    -- video control signals		
+    video_ctl   : in from_VIDEO_CTL_t;
+
+    -- tilemap controller signals
+    ctl_i       : in to_TILEMAP_CTL_t;
+    ctl_o       : out from_TILEMAP_CTL_t;
+
+    graphics_i  : in to_GRAPHICS_t
+  );
+end entity tilemapCtl;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_controller.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_controller.vhd
new file mode 100644
index 00000000..9372578d
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_controller.vhd	
@@ -0,0 +1,465 @@
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.video_controller_pkg.all;
+
+entity pace_video_controller is
+  generic
+  (
+		CONFIG		  : PACEVideoController_t := PACE_VIDEO_NONE;
+		DELAY       : integer := 1;
+		H_SIZE      : integer;
+		V_SIZE      : integer;
+    L_CROP      : integer range 0 to 255;
+    R_CROP      : integer range 0 to 255;
+		H_SCALE     : integer;
+		V_SCALE     : integer;
+    H_SYNC_POL  : std_logic := '1';
+    V_SYNC_POL  : std_logic := '1';
+		BORDER_RGB  : RGB_t := RGB_BLACK
+  );
+  port
+  (
+    -- clocking etc
+    video_i       : in from_VIDEO_t;
+
+		-- register interface
+		reg_i			    : in VIDEO_REG_t;
+    
+    -- video input data
+    rgb_i         : in RGB_t;
+
+		-- control signals (out)
+		video_ctl_o   : out from_VIDEO_CTL_t;
+
+    -- video output control & data
+    video_o       : out to_VIDEO_t
+  );
+end pace_video_controller;
+
+architecture SYN of pace_video_controller is
+
+  constant SIM_DELAY          : time := 2 ns;
+
+	constant VIDEO_H_SIZE				: integer := H_SIZE * H_SCALE;
+	constant VIDEO_V_SIZE				: integer := V_SIZE * V_SCALE;
+
+  subtype reg_t is integer range 0 to 2047;
+
+  alias clk       : std_logic is video_i.clk;
+  alias clk_ena   : std_logic is video_i.clk_ena;
+  alias reset     : std_logic is video_i.reset;
+  
+  -- registers
+  signal h_front_porch_r        : reg_t := 0;
+  signal h_sync_r               : reg_t := 0;
+  signal h_back_porch_r         : reg_t := 0;
+  signal h_border_r             : reg_t := 0;
+  signal h_video_r              : reg_t := 0;
+  signal v_front_porch_r        : reg_t := 0;
+  signal v_sync_r               : reg_t := 0;
+  signal v_back_porch_r         : reg_t := 0;
+  signal v_border_r             : reg_t := 0;
+  signal v_video_r              : reg_t := 0;
+
+  signal border_rgb_r           : RGB_t := ((others=>'0'), (others=>'0'), (others=>'0'));
+  
+  -- derived values
+  signal h_sync_start           : reg_t := 0;
+  signal h_back_porch_start     : reg_t := 0;
+  signal h_left_border_start    : reg_t := 0;
+  signal h_video_start          : reg_t := 0;
+  signal h_right_border_start   : reg_t := 0;
+  signal h_line_end             : reg_t := 0;
+  signal v_sync_start           : reg_t := 0;
+  signal v_back_porch_start     : reg_t := 0;
+  signal v_top_border_start     : reg_t := 0;
+  signal v_video_start          : reg_t := 0;
+  signal v_bottom_border_start  : reg_t := 0;
+  signal v_screen_end           : reg_t := 0;
+
+  signal hsync_s                : std_logic := '0';
+  signal vsync_s                : std_logic := '0';
+  signal hactive_s              : std_logic := '0';
+  signal vactive_s              : std_logic := '0';
+  signal hblank_s               : std_logic := '0';
+  signal vblank_s               : std_logic := '0';
+  
+  subtype count_t is integer range 0 to 2047;
+  signal x_count                : count_t := 0;
+  signal y_count                : count_t := 0;
+  
+  signal x_s                    : unsigned(10 downto 0) := (others => '0');
+  signal y_s                    : unsigned(10 downto 0) := (others => '0');
+  
+  --signal extended_reset         : std_logic := '1';
+  alias extended_reset          : std_logic is video_i.reset;
+  
+begin
+
+  -- registers
+	reg_proc: process (reset, clk)
+
+	begin
+		--if reset = '1' then
+			case CONFIG is
+
+        when PACE_VIDEO_VGA_240x320_60Hz =>
+          -- P3M, clk=11.136MHz, clk_ena=5.568MHz
+          h_front_porch_r <= 272-240;
+          h_sync_r <= 5;
+          h_back_porch_r <= 22;
+          h_border_r <= (240-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 326-320;
+          v_sync_r <= 1;
+          v_back_porch_r <= 5;
+          v_border_r <= (320-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_320x480_60Hz =>
+          -- VGA, clk=12.588MHz
+          --# 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio
+          --Modeline "320x240"    12.588    320  336  384  400    240  245  246  262 Doublescan
+          h_front_porch_r <= 16;
+          h_sync_r <= 48;
+          h_back_porch_r <= 16;
+          h_border_r <= (320-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= (5*2);
+          v_sync_r <= (1*2);
+          v_back_porch_r <= (16*2);
+          v_border_r <= (480-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_640x480_60Hz =>
+          -- VGA, clk=25.175MHz
+          h_front_porch_r <= 16;
+          h_sync_r <= 96;
+          h_back_porch_r <= 48;
+          h_border_r <= (640-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 10;
+          v_sync_r <= 2;
+          v_back_porch_r <= 33;
+          v_border_r <= (480-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_800x600_60Hz =>
+          -- SVGA, clk=40MHz
+          h_front_porch_r <= 40;
+          h_sync_r <= 128;
+          h_back_porch_r <= 88;
+          h_border_r <= (800-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 1;
+          v_sync_r <= 4;
+          v_back_porch_r <= 23;
+          v_border_r <= (600-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1024x768_60Hz =>
+          -- XVGA, clk=65MHz
+          h_front_porch_r <= 24;
+          h_sync_r <= 136;
+          h_back_porch_r <= 160;
+          h_border_r <= (1024-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 3;
+          v_sync_r <= 6;
+          v_back_porch_r <= 29;
+          v_border_r <= (768-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1366x768_60Hz =>
+          -- XVGA(NAVICO ROCKY), clk=72MHz
+          h_front_porch_r <= 88; --64;
+          h_sync_r <= 44; --112;
+          h_back_porch_r <= 148; --248;
+          h_border_r <= (1366-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 4; --3;
+          v_sync_r <= 5; --6;
+          v_back_porch_r <= 36; --18;
+          v_border_r <= (768-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1280x800_60Hz =>
+          -- Sentinel Mode 36, clk=103.2MHz
+          h_front_porch_r <= 64;
+          h_sync_r <= 32;
+          h_back_porch_r <= 362-32-64;
+          h_border_r <= (1280-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 3;
+          v_sync_r <= 4;
+          v_back_porch_r <= 38-4-3;
+          v_border_r <= (800-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1280x1024_60Hz =>
+          -- SXGA, clk=108MHz
+          h_front_porch_r <= 48;
+          h_sync_r <= 112;
+          h_back_porch_r <= 248;
+          h_border_r <= (1280-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 1;
+          v_sync_r <= 3;
+          v_back_porch_r <= 38;
+          v_border_r <= (1024-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1680x1050_60Hz =>
+          -- WSXGA+, clk=147.14MHz
+          h_front_porch_r <= 104;
+          h_sync_r <= 184;
+          h_back_porch_r <= 288;
+          v_front_porch_r <= 1;
+          v_sync_r <= 3;
+          v_back_porch_r <= 33;
+          -- WSXGA+, clk=118MHz
+          --h_front_porch_r <= 48;
+          --h_sync_r <= 32;
+          --h_back_porch_r <= 80;
+          --v_front_porch_r <= 3;
+          --v_sync_r <= 6;
+          --v_back_porch_r <= 21;
+          h_border_r <= (1680-VIDEO_H_SIZE)/2;
+          v_border_r <= (1050-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_ARCADE_STD_336x240_60Hz =>
+          -- arcade standard resolution, clk=7.16MHz
+          h_front_porch_r <= 34;
+          h_sync_r <= 34;
+          h_back_porch_r <= 51;
+          h_border_r <= (336-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 3;
+          v_sync_r <= 3;
+          v_back_porch_r <= 16;
+          v_border_r <= (240-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64 =>
+          -- arcade standard resolution, clk=28.64MHz
+          h_front_porch_r <= 4*34;
+          h_sync_r <= 4*34;
+          h_back_porch_r <= 4*51;
+          h_border_r <= 4*(336-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 3;
+          v_sync_r <= 3;
+          v_back_porch_r <= 16;
+          v_border_r <= (240-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_CVBS_720x288p_50Hz =>
+          -- generic composite, clk=13.5MHz
+          h_front_porch_r <= (8+12);
+          h_sync_r <= 64;
+          h_back_porch_r <= (144-64-(8+12));
+          h_border_r <= (720-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 1;
+          v_sync_r <= 3;
+          v_back_porch_r <= 20;
+          v_border_r <= (288-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_LCM_320x240_60Hz =>
+          -- DE1/2, clk=18MHz
+          h_front_porch_r <= 59;
+          h_sync_r <= 1;
+          h_back_porch_r <= 151;
+          h_border_r <= (320-VIDEO_H_SIZE)*3/2;
+          v_front_porch_r <= 8;
+          v_sync_r <= 1;
+          v_back_porch_r <= 13;
+          v_border_r <= (240-VIDEO_V_SIZE)/2;
+
+				when PACE_VIDEO_PAL_576x288_50Hz =>
+					-- pixclk=11 MHz
+					h_front_porch_r <= 2*6;
+					h_sync_r <= 2*28;
+					h_back_porch_r <= 2*30;
+					h_border_r <= (576-VIDEO_H_SIZE)/2;
+					v_front_porch_r <= 8;
+					v_sync_r <= 3;
+					v_back_porch_r <= 13;
+					v_border_r <= (288-VIDEO_V_SIZE)/2;
+				when others =>
+					null;
+			end case;
+
+      h_video_r <= VIDEO_H_SIZE;
+      v_video_r <= VIDEO_V_SIZE;
+      border_rgb_r <= BORDER_RGB;
+      
+		--end if;
+	end process reg_proc;
+
+  -- register some arithmetic
+  init_proc: process (reset, clk, clk_ena)
+  begin
+    if reset = '1' then
+      null;
+    elsif rising_edge(clk) then
+      h_sync_start <= h_front_porch_r - 1;
+      h_back_porch_start <= h_sync_start + h_sync_r;
+      h_left_border_start <= h_back_porch_start + h_back_porch_r;
+      h_video_start <= h_left_border_start + h_border_r;
+      h_right_border_start <= h_video_start + h_video_r;
+      h_line_end <= h_right_border_start + h_border_r;
+      v_sync_start <= v_front_porch_r - 1;
+      v_back_porch_start <= v_sync_start + v_sync_r;
+      v_top_border_start <= v_back_porch_start + v_back_porch_r;
+      v_video_start <= v_top_border_start + v_border_r;
+      v_bottom_border_start <= v_video_start + v_video_r;
+      v_screen_end <= v_bottom_border_start + v_border_r;
+    end if;
+  end process init_proc;
+  
+  reset_proc: process (reset, clk)
+    variable count_v : integer;
+  begin
+    if reset = '1' then
+      --extended_reset <= '1';
+      count_v := 7;
+    elsif rising_edge(clk) then
+      if count_v = 0 then
+        --extended_reset <= '0';
+      else
+        count_v := count_v - 1;
+      end if;
+    end if;
+  end process reset_proc;
+
+  -- video control outputs
+  timer_proc: process (extended_reset, clk, clk_ena)
+  begin
+    if extended_reset = '1' then
+      hblank_s <= '1';
+      vblank_s <= '1';
+      hactive_s <= '0';
+      vactive_s <= '0';
+      hsync_s <= not H_SYNC_POL;
+      x_count <= 0;
+      y_count <= 0;
+    elsif rising_edge(clk) and clk_ena = '1' then
+      if x_count = h_line_end then
+        hblank_s <= '1';
+        hactive_s <= '0';     -- for 0 borders
+        if y_count = v_screen_end then
+          vblank_s <= '1';
+          vactive_s <= '0';   -- for 0 borders
+          y_count <= 0;
+        else
+          y_s <= y_s + 1;
+          if y_count = v_sync_start then
+            vsync_s <= V_SYNC_POL;
+          elsif y_count = v_back_porch_start then
+            vsync_s <= not V_SYNC_POL;
+          elsif y_count = v_video_start then
+            vblank_s <= '0';  -- for 0 borders
+            vactive_s <= '1';
+            y_s <= (others => '0');
+          -- check the borders last in case they're 0
+          elsif y_count = v_top_border_start then
+            vblank_s <= '0';
+          elsif y_count = v_bottom_border_start then
+            vactive_s <= '0';
+          end if;
+          y_count <= y_count + 1;
+        end if;
+        x_count <= 0;
+      else
+        x_s <= x_s + 1;
+        if x_count = h_sync_start then
+          hsync_s <= H_SYNC_POL;
+        elsif x_count = h_back_porch_start then
+          hsync_s <= not H_SYNC_POL;
+        elsif x_count = h_video_start then
+          hblank_s <= '0'; -- for 0 borders
+          hactive_s <= '1';
+          x_s <= (others => '0');
+          -- check the borders last in case they're 0
+        elsif x_count = h_left_border_start then
+          hblank_s <= '0';
+        elsif x_count = h_right_border_start then
+          hactive_s <= '0';
+        end if;
+        x_count <= x_count + 1;
+      end if;
+    end if; -- rising_edge(clk) and clk_ena = '1'
+  end process timer_proc;
+
+  -- pass-through for tile/bitmap & sprite controllers
+  video_ctl_o.clk <= clk;
+  video_ctl_o.clk_ena <= clk_ena;
+  
+  -- for video DACs and TFT output
+  video_o.clk <= clk;
+
+  BLK_VIDEO_O : block
+
+    constant PIPELINE_DELAY : natural := DELAY+1;
+
+    -- won't synthesize correctly under ISE if these are variables
+    signal hactive_v_r  : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+    signal vactive_v_r  : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+
+  begin
+  
+    video_o_proc: process (extended_reset, clk, clk_ena)
+      variable hsync_v_r    : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      variable vsync_v_r    : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      --variable hactive_v_r  : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      --variable vactive_v_r  : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      variable hblank_v_r   : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      variable vblank_v_r   : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      alias hsync_v         : std_logic is hsync_v_r(hsync_v_r'left);
+      alias vsync_v         : std_logic is vsync_v_r(vsync_v_r'left);
+      alias hactive_v       : std_logic is hactive_v_r(hactive_v_r'left);
+      alias vactive_v       : std_logic is vactive_v_r(vactive_v_r'left);
+      alias hblank_v        : std_logic is hblank_v_r(hblank_v_r'left);
+      alias vblank_v        : std_logic is vblank_v_r(vblank_v_r'left);
+      variable stb_cnt_v    : unsigned(3 downto 0); -- up to 16x scaling
+    begin
+      if extended_reset = '1' then
+        hsync_v_r := (others => not H_SYNC_POL);
+        vsync_v_r := (others => not V_SYNC_POL);
+        hactive_v_r <= (others => '0');
+        vactive_v_r <= (others => '0');
+        hblank_v_r := (others => '0');
+        vblank_v_r := (others => '0');
+        stb_cnt_v := (others => '1');
+      elsif rising_edge(clk) and clk_ena = '1' then
+  
+        -- register control signals and handle scaling
+        video_ctl_o.hblank <= not hactive_s after SIM_DELAY;	-- used only by the bitmap/tilemap/sprite controllers
+        video_ctl_o.vblank <= not vactive_s after SIM_DELAY;	-- used only by the bitmap/tilemap/sprite controllers
+        -- handle scaling
+        video_ctl_o.stb <= stb_cnt_v(H_SCALE-1) after SIM_DELAY;
+        if hactive_s = '1' and vactive_s = '1' then
+          stb_cnt_v := stb_cnt_v + 2;
+        elsif hblank_s = '0' and vblank_s = '0' then    
+          stb_cnt_v := (others => '1');
+        end if;
+        video_ctl_o.x <= std_logic_vector(resize(x_s(x_s'left downto H_SCALE-1), video_ctl_o.x'length)) after SIM_DELAY;
+        video_ctl_o.y <= std_logic_vector(resize(y_s(y_s'left downto V_SCALE-1), video_ctl_o.y'length)) after SIM_DELAY;
+  
+        -- register video outputs
+        if hactive_v = '1' and vactive_v = '1' then
+          -- active video
+          if  x_s(x_s'left downto H_SCALE-1) < (L_CROP + PIPELINE_DELAY) or 
+              x_s(x_s'left downto H_SCALE-1) >= (H_SIZE - R_CROP + PIPELINE_DELAY) then
+            video_o.rgb <= RGB_BLACK after SIM_DELAY;
+          else
+            video_o.rgb <= rgb_i after SIM_DELAY;
+          end if;
+        elsif hblank_v = '0' and vblank_v = '0' then
+          -- border
+          video_o.rgb <= border_rgb_r after SIM_DELAY;
+        else
+          video_o.rgb.r <= (others => '0') after SIM_DELAY;
+          video_o.rgb.g <= (others => '0') after SIM_DELAY;
+          video_o.rgb.b <= (others => '0') after SIM_DELAY;
+        end if;
+        video_o.hsync <= hsync_v after SIM_DELAY;
+        video_o.vsync <= vsync_v after SIM_DELAY;
+        video_o.hblank <= hblank_v after SIM_DELAY;
+        video_o.vblank <= vblank_v after SIM_DELAY;
+        -- pipelined signals
+        hsync_v_r := hsync_v_r(hsync_v_r'left-1 downto 0) & hsync_s;
+        vsync_v_r := vsync_v_r(vsync_v_r'left-1 downto 0) & vsync_s;
+        hactive_v_r <= hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s;
+        vactive_v_r <= vactive_v_r(vactive_v_r'left-1 downto 0) & vactive_s;
+        hblank_v_r := hblank_v_r(hblank_v_r'left-1 downto 0) & hblank_s;
+        vblank_v_r := vblank_v_r(vblank_v_r'left-1 downto 0) & vblank_s;
+      end if;
+    end process video_o_proc;
+
+  end block BLK_VIDEO_O;
+  
+end SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_controller_pkg.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_controller_pkg.vhd
new file mode 100644
index 00000000..526be3c8
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_controller_pkg.vhd	
@@ -0,0 +1,230 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+--use IEEE.numeric_std.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+package video_controller_pkg is
+
+  type PACEVideoController_t is
+  (
+    PACE_VIDEO_NONE,                      -- PACE video controller not used
+    PACE_VIDEO_VGA_240x320_60Hz,          -- P3M video
+    PACE_VIDEO_VGA_320x480_60Hz,          -- for 320x200 (12.588MHz)
+    PACE_VIDEO_VGA_640x480_60Hz,          -- generic VGA (25.175MHz)
+    PACE_VIDEO_VGA_800x600_60Hz,          -- generic VGA (40MHz)
+    PACE_VIDEO_VGA_1024x768_60Hz,         -- XVGA (65MHz)
+    PACE_VIDEO_VGA_1366x768_60Hz,         -- (NAVICO ROCKY) (72MHz)
+    PACE_VIDEO_VGA_1280x800_60Hz,         -- Sentinel Mode 36
+    PACE_VIDEO_VGA_1280x1024_60Hz,        -- SXGA (108MHz)
+    PACE_VIDEO_VGA_1680x1050_60Hz,        -- WSXGA+ (147MHz)
+    PACE_VIDEO_ARCADE_STD_336x240_60Hz,   -- arcade std resolution (7.16MHz)
+    PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64,   -- arcade std resolution (28.64MHz)
+    PACE_VIDEO_CVBS_720x288p_50Hz,        -- generic composite
+    PACE_VIDEO_LCM_320x240_60Hz,          -- DE2 LCD
+    PACE_VIDEO_PAL_576x288_50Hz
+  );
+
+  type PACEVideoDisplay_t is
+  (
+    PACE_DISPLAY_NONE,
+    PACE_DISPLAY_VGA,
+    PACE_DISPLAY_CVBS,
+    PACE_DISPLAY_TFT
+  );
+
+  type RGB_t is record
+    r : std_logic_vector(9 downto 0);
+    g : std_logic_vector(9 downto 0);
+    b : std_logic_vector(9 downto 0);
+  end record;
+
+  type RGB_a is array (natural range <>) of RGB_t;
+  
+  function NULL_RGB return RGB_t;
+
+  constant RGB_BLACK    : RGB_t := ((others=>'0'),(others=>'0'),(others=>'0'));
+  constant RGB_RED      : RGB_t := ((others=>'1'),(others=>'0'),(others=>'0'));
+  constant RGB_GREEN    : RGB_t := ((others=>'0'),(others=>'1'),(others=>'0'));
+  constant RGB_YELLOW   : RGB_t := ((others=>'1'),(others=>'1'),(others=>'0'));
+  constant RGB_BLUE     : RGB_t := ((others=>'0'),(others=>'0'),(others=>'1'));
+  constant RGB_MAGENTA  : RGB_t := ((others=>'1'),(others=>'0'),(others=>'1'));
+  constant RGB_CYAN     : RGB_t := ((others=>'0'),(others=>'1'),(others=>'1'));
+  constant RGB_WHITE    : RGB_t := ((others=>'1'),(others=>'1'),(others=>'1'));
+  
+	type VIDEO_REG_t is record
+		h_scale		: std_logic_vector(2 downto 0);
+		v_scale		: std_logic_vector(2 downto 0);
+	end record;
+
+  type from_VIDEO_t is record
+    clk       : std_logic;
+    clk_ena   : std_logic;
+    reset     : std_logic;
+  end record;
+  
+  type to_VIDEO_t is record
+    clk       : std_logic;
+    rgb       : rgb_t;
+    hsync     : std_logic;
+    vsync     : std_logic;
+    hblank    : std_logic;
+    vblank    : std_logic;
+    de        : std_logic;
+  end record;
+
+  type from_VIDEO_CTL_t is record
+    clk       : std_logic;
+    clk_ena   : std_logic;
+    stb       : std_logic;
+    hblank    : std_logic;
+    vblank    : std_logic;
+    x         : std_logic_vector(10 downto 0);
+    y         : std_logic_vector(10 downto 0);
+  end record;
+  
+  subtype BITMAP_D_t is std_logic_vector(23 downto 0);
+  subtype BITMAP_A_t is std_logic_vector(15 downto 0);
+  
+  type to_BITMAP_CTL_t is record
+    d         : BITMAP_D_t;
+  end record;
+  
+  type to_BITMAP_CTL_a is array (natural range <>) of to_BITMAP_CTL_t;
+
+  function NULL_TO_BITMAP_CTL return to_BITMAP_CTL_t;
+
+  type from_BITMAP_CTL_t is record
+    a         : BITMAP_A_t;
+    rgb       : RGB_t;
+    set       : std_logic;
+  end record;
+
+  type from_BITMAP_CTL_a is array (natural range <>) of from_BITMAP_CTL_t;
+
+  subtype TILEMAP_D_t is std_logic_vector(15 downto 0);
+  subtype TILEMAP_A_t is std_logic_vector(15 downto 0);
+  subtype TILE_A_t is std_logic_vector(16 downto 0);
+  subtype TILE_D_t is std_logic_vector(23 downto 0);
+  subtype ATTR_A_t is std_logic_vector(15 downto 0);
+  subtype ATTR_D_t is std_logic_vector(15 downto 0);
+  
+  type to_TILEMAP_CTL_t is record
+    map_d     : TILEMAP_D_t;
+    tile_d    : TILE_D_t;
+    attr_d    : ATTR_D_t;
+  end record;
+
+  type to_TILEMAP_CTL_a is array (natural range <>) of to_TILEMAP_CTL_t;
+  
+  function NULL_TO_TILEMAP_CTL return to_TILEMAP_CTL_t;
+
+  type from_TILEMAP_CTL_t is record
+    map_a     : TILEMAP_A_t;
+    tile_a    : TILE_A_t;
+    attr_a    : ATTR_A_t;
+    rgb       : RGB_t;
+    set       : std_logic;
+  end record;
+
+  type from_TILEMAP_CTL_a is array (natural range <>) of from_TILEMAP_CTL_t;
+  
+  subtype PAL_ENTRY_t is std_logic_vector(15 downto 0);
+  type PAL_A_t is array (natural range <>) of PAL_ENTRY_t;
+  
+  subtype BYTE_t is std_logic_vector(7 downto 0);
+  type BYTE_A_t is array (natural range <>) of BYTE_t;
+  
+  subtype WORD_t is std_logic_vector(15 downto 0);
+  type WORD_A_t is array (natural range <>) of WORD_t;
+  
+  type to_GRAPHICS_t is record
+    pal       : PAL_A_t(0 to 15);
+    -- for various uses
+    bit8      : BYTE_A_t(0 to 7);
+    bit16     : WORD_A_t(0 to 3);
+    -- 'native' graphics stream
+    hsync     : std_logic;
+    vsync     : std_logic;
+    rgb       : RGB_t;
+  end record;
+
+  function NULL_TO_GRAPHICS return to_GRAPHICS_t;
+
+  type from_GRAPHICS_t is record
+    y         : std_logic_vector(10 downto 0);
+    hblank    : std_logic;
+    vblank    : std_logic;
+  end record;
+
+  component pace_video_controller is
+    generic
+    (
+      CONFIG		  : PACEVideoController_t := PACE_VIDEO_NONE;
+      DELAY       : integer := 1;
+      H_SIZE      : integer;
+      V_SIZE      : integer;
+      --H_SCALE     : integer;
+      --V_SCALE     : integer;
+      BORDER_RGB  : RGB_t := RGB_BLACK
+    );
+    port
+    (
+      -- clocking etc
+      video_i       : in from_VIDEO_t;
+      
+      -- register interface
+      reg_i			    : in VIDEO_REG_t;
+      
+      -- video input data
+      rgb_i         : in RGB_t;
+
+      -- control signals (out)
+      video_ctl_o   : from_VIDEO_CTL_t;
+      
+      -- Outputs to video
+      video_o       : out to_VIDEO_t
+    );
+  end component pace_video_controller;
+
+	component tilemapCtl is          
+	  generic
+	  (
+	    DELAY       : integer
+	  );
+	  port               
+	  (
+	    reset				: in std_logic;
+	
+	    -- video control signals		
+	    video_ctl   : in from_VIDEO_CTL_t;
+	
+	    -- tilemap controller signals
+	    ctl_i       : in to_TILEMAP_CTL_t;
+	    ctl_o       : out from_TILEMAP_CTL_t;
+	
+	    graphics_i  : in to_GRAPHICS_t
+	  );
+	end component tilemapCtl;
+
+  component bitmapCtl is
+    generic
+    (
+      DELAY         : integer
+    );
+    port               
+    (
+      reset					: in std_logic;
+
+      -- video control signals		
+      video_ctl     : in from_VIDEO_CTL_t;
+
+      -- bitmap controller signals
+      ctl_i         : in to_BITMAP_CTL_t;
+      ctl_o         : out from_BITMAP_CTL_t;
+
+      graphics_i    : in to_GRAPHICS_t
+    );
+  end component bitmapCtl;
+
+end package video_controller_pkg;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_controller_pkg_body.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_controller_pkg_body.vhd
new file mode 100644
index 00000000..996e5867
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_controller_pkg_body.vhd	
@@ -0,0 +1,29 @@
+library work;
+--use work.pace_pkg.all;
+
+package body video_controller_pkg is
+
+  function NULL_RGB return RGB_t is
+  begin
+    return (others => (others => '0'));
+  end NULL_RGB;
+
+  function NULL_TO_BITMAP_CTL return to_BITMAP_CTL_t is
+  begin
+    return (others => (others => '0'));
+  end NULL_TO_BITMAP_CTL;
+
+  function NULL_TO_TILEMAP_CTL return to_TILEMAP_CTL_t is
+  begin
+    return ((others => '0'), (others => '0'), (others => '0'));
+  end NULL_TO_TILEMAP_CTL;
+  
+  function NULL_TO_GRAPHICS return to_GRAPHICS_t is
+  begin
+    return ((others => (others => '0')), 
+            (others => (others => '0')), 
+            (others => (others => '0')),
+            '0', '0', NULL_RGB);
+  end NULL_TO_GRAPHICS;
+
+end package body video_controller_pkg;
diff --git a/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_mixer.vhd b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_mixer.vhd
new file mode 100644
index 00000000..fb4b4aa4
--- /dev/null
+++ b/Arcade_MiST/IremM62 Hardware/Kung_MiST/rtl/video_mixer.vhd	
@@ -0,0 +1,66 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+
+entity pace_video_mixer is
+  port
+  (
+      --bitmap_rgb    : in RGB_t;
+      --bitmap_set    : in std_logic;
+      bitmap_ctl_o  : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+      tilemap_ctl_o : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+      sprite_rgb    : in RGB_t;
+      sprite_set    : in std_logic;
+      sprite_pri    : in std_logic;
+      
+      video_ctl_i   : in from_VIDEO_CTL_t;
+      graphics_i    : in to_GRAPHICS_t;
+      rgb_o         : out RGB_t
+  );
+end entity pace_video_mixer;
+  
+architecture SYN of pace_video_mixer is
+  signal bg_rgb : RGB_t;
+begin
+
+  GEN_BITMAPS : 
+    if PACE_VIDEO_NUM_BITMAPS = 1 generate
+      bg_rgb <= bitmap_ctl_o(1).rgb;
+    elsif PACE_VIDEO_NUM_BITMAPS = 2 generate
+      bg_rgb <= bitmap_ctl_o(1).rgb when bitmap_ctl_o(1).set = '1' else
+                bitmap_ctl_o(2).rgb;
+    elsif PACE_VIDEO_NUM_BITMAPS = 3 generate
+      bg_rgb <= bitmap_ctl_o(1).rgb when bitmap_ctl_o(1).set = '1' else
+                bitmap_ctl_o(2).rgb when bitmap_ctl_o(2).set = '1' else
+                bitmap_ctl_o(3).rgb when bitmap_ctl_o(3).set = '1' else
+                (others => (others => '0'));
+    else generate
+      bg_rgb <= (others => (others => '0'));
+  end generate GEN_BITMAPS;
+    
+  GEN_TILEMAPS : 
+    if PACE_VIDEO_NUM_TILEMAPS = 1 generate
+      rgb_o <=  sprite_rgb when sprite_set = '1' and sprite_pri = '1' else
+                tilemap_ctl_o(1).rgb when tilemap_ctl_o(1).set = '1' else
+                sprite_rgb when sprite_set = '1' else
+                bg_rgb;
+    elsif PACE_VIDEO_NUM_TILEMAPS = 2 generate
+      rgb_o <=  sprite_rgb when sprite_set = '1' and sprite_pri = '1' else
+                tilemap_ctl_o(1).rgb when tilemap_ctl_o(1).set = '1' else
+                tilemap_ctl_o(2).rgb when tilemap_ctl_o(2).set = '1' else
+                sprite_rgb when sprite_set = '1' else
+                bg_rgb;
+    else generate
+      rgb_o <=  sprite_rgb when sprite_set = '1' and sprite_pri = '1' else
+                sprite_rgb when sprite_set = '1' else
+                bg_rgb;
+  end generate GEN_TILEMAPS;
+  
+end architecture SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/LodeRunner_MiST.qsf b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/LodeRunner_MiST.qsf
index 317e418d..7e0b14c7 100644
--- a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/LodeRunner_MiST.qsf	
+++ b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/LodeRunner_MiST.qsf	
@@ -266,10 +266,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(LodeRunner_MiST)
-# ---------------------------
\ No newline at end of file
+# ---------------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Graphics.VHD b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Graphics.VHD
index 8dc75400..dc3fb666 100644
--- a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Graphics.VHD	
+++ b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Graphics.VHD	
@@ -269,5 +269,4 @@ begin
 
   sprite_ctl_o <= sprite_ctl_o_s;
 
-
 end SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/LodeRunner_MiST.sv b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/LodeRunner_MiST.sv
index bbc4ef58..a244cfc1 100644
--- a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/LodeRunner_MiST.sv	
+++ b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/LodeRunner_MiST.sv	
@@ -40,7 +40,10 @@ localparam CONF_STR = {
 	"V,v1.0.",`BUILD_DATE
 };
 
-
+wire       rotate    = status[2];
+wire [1:0] scanlines = status[4:3];
+wire       blend     = status[5];
+wire       service   = status[6];
 
 assign LED = ~ioctl_downl;
 assign SDRAM_CLK = clk_sd;
@@ -65,21 +68,39 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [11:0] audio;
-wire        hs, vs;
-wire        blankn = 1'b1;//todo
-wire  [3:0] g,b,r;
+wire        no_csync;
 wire        key_pressed;
 wire  [7:0] key_code;
 wire        key_strobe;
 
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
 wire [14:0] rom_addr;
 wire [15:0] rom_do;
 
 wire [13:0] snd_addr;
 wire [15:0] snd_do;
 
-
 wire [14:0] sp_addr;
 wire [31:0] sp_do;
 
@@ -165,15 +186,20 @@ always @(posedge clk_sys) begin
 
 end
 
+wire [11:0] audio;
+wire        hs, vs;
+wire        blankn = 1'b1;//todo
+wire  [3:0] g,b,r;
+
 target_top target_top(
-   .clock_50(clk_sys),//40MHz
-	.clock_vid(clk_vid),//25.263158MHz
+	.clock_sys(clk_sys),//4xclk_vid
+	.clock_vid(clk_vid),//11MHz
 	.clk_aud(clk_aud),//0.895MHz
 	.reset_in(reset),
 	.audio_out(audio),
 	.usr_coin1(m_coin1),
 	.usr_coin2(m_coin2),
-	.usr_service(status[6]),
+	.usr_service(service),
 	.usr_start1(m_one_player),
 	.usr_start2(m_two_players),
 	.p1_up(m_up),
@@ -188,18 +214,18 @@ target_top target_top(
 	.p2_rt(m_right2),
 	.p2_f1(m_fire2A),
 	.p2_f2(m_fire2B),
-   .VGA_VS(hs),
-   .VGA_HS(vs),
-   .VGA_R(r),
-   .VGA_G(g),
-   .VGA_B(b),
+	.VGA_VS(vs),
+	.VGA_HS(hs),
+	.VGA_R(r),
+	.VGA_G(g),
+	.VGA_B(b),
 	.cpu_rom_addr(rom_addr),
 	.cpu_rom_do( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
 	.snd_rom_addr(snd_addr),
-   .snd_rom_do(snd_addr[0] ? snd_do[15:8] : snd_do[7:0])
+	.snd_rom_do(snd_addr[0] ? snd_do[15:8] : snd_do[7:0])
   ); 
 
-mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(9)) mist_video(
+mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
 	.clk_sys        ( clk_sys          ),
 	.SPI_SCK        ( SPI_SCK          ),
 	.SPI_SS3        ( SPI_SS3          ),
@@ -214,33 +240,13 @@ mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(9)) mist_video(
 	.VGA_B          ( VGA_B            ),
 	.VGA_VS         ( VGA_VS           ),
 	.VGA_HS         ( VGA_HS           ),
-	.rotate         ( { 1'b1, status[2] } ),
-	.ce_divider     ( 1'b1                ),
-	.scandoubler_disable( 1),//scandoublerD ),
-	.scanlines      ( status[4:3]        ),
-	.blend          ( status[5]            ),
-	.ypbpr          ( ypbpr            )
-	);
-
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-user_io(
-	.clk_sys        (clk_sys        ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
+	.rotate         ( { 1'b1, rotate } ),
+	.ce_divider     ( 1'b0             ),
+	.scandoubler_disable( scandoublerD ),
+	.scanlines      ( scanlines        ),
+	.blend          ( blend            ),
+	.ypbpr          ( ypbpr            ),
+	.no_csync       ( no_csync         )
 	);
 
 wire dac_o;
@@ -267,7 +273,7 @@ arcade_inputs inputs (
 	.key_code    ( key_code    ),
 	.joystick_0  ( joystick_0  ),
 	.joystick_1  ( joystick_1  ),
-	.rotate      ( status[2]   ),
+	.rotate      ( rotate      ),
 	.orientation ( 2'b10       ),
 	.joyswap     ( 1'b0        ),
 	.oneplayer   ( 1'b1        ),
diff --git a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Sound_Board.vhd b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Sound_Board.vhd
index 2ba93794..abcb4631 100644
--- a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Sound_Board.vhd	
+++ b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/Sound_Board.vhd	
@@ -178,7 +178,7 @@ cpu_di <=
 	port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
 	port1_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
 	port2_in  when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
-	rom_do when rom_cs = '1' else X"55";
+	snd_rom_do when rom_cs = '1' else X"55";
 
 process (clock_E)
 begin
@@ -346,14 +346,9 @@ port map(
 	test_cc  => open
 );
 
-rom_cpu : entity work.snd_prg
-port map(
-	clk   => clock_E,   -- E clock input (falling edge)
-	addr  => cpu_addr(13 downto 0),
-	data  => rom_do
-);
 
--- snd_rom_addr <= cpu_addr(13 downto 0);
+
+ snd_rom_addr <= cpu_addr(13 downto 0);
 
  
 -- cpu wram
diff --git a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/platform_pkg.vhd b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/platform_pkg.vhd
index cc47e1a0..7e2c8831 100644
--- a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/platform_pkg.vhd	
+++ b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/platform_pkg.vhd	
@@ -8,62 +8,41 @@ use work.platform_variant_pkg.all;
 use work.video_controller_pkg.all;
 package platform_pkg is
 
-	constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_VGA_640x480_60Hz;
-	constant PACE_CLK0_DIVIDE_BY              : natural := 3;
-	constant PACE_CLK0_MULTIPLY_BY            : natural := 5;   -- 24*5/3 = 40MHz
-	constant PACE_CLK1_DIVIDE_BY              : natural := 19;
-	constant PACE_CLK1_MULTIPLY_BY            : natural := 20; 	-- 24*20/19 = 25.263158MHz
-	constant PACE_VIDEO_H_SCALE       	      : integer := 1;
-	constant PACE_VIDEO_V_SCALE       	      : integer := 1;
-	constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '0';
-	constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '0';
 
---  constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_ARCADE_STD_336x240_60Hz;
---  constant PACE_CLK0_DIVIDE_BY              : natural := 1;
---  constant PACE_CLK0_MULTIPLY_BY            : natural := 1;   	-- 24*1/1 = 24MHz
---  constant PACE_CLK1_DIVIDE_BY              : natural := 57;
---  constant PACE_CLK1_MULTIPLY_BY            : natural := 17;  	-- 24*17/57 = 7.157895MHz
---  constant PACE_VIDEO_H_SCALE       	      : integer := 1;
---  constant PACE_VIDEO_V_SCALE       	      : integer := 1;
---  constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '0';
---  constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '0';
-  
-  --constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_CVBS_720x288p_50Hz;
-  --constant PACE_CLK0_DIVIDE_BY              : natural := 8;
-  --constant PACE_CLK0_MULTIPLY_BY            : natural := 9;   -- 24*9/8 = 27MHz
-  --constant PACE_CLK1_DIVIDE_BY              : natural := 16;
-  --constant PACE_CLK1_MULTIPLY_BY            : natural := 9;		-- 24*9/16 = 13.5MHz
-	--constant PACE_VIDEO_H_SCALE               : integer := 2;
-	--constant PACE_VIDEO_V_SCALE               : integer := 1;
-	--constant PACE_ENABLE_ADV724					      : std_logic := '1';
-	--constant USE_VIDEO_VBLANK_INTERRUPT 		  : boolean := false;
+	constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_PAL_576x288_50Hz;
+	constant PACE_CLK0_DIVIDE_BY              : natural := 27;
+	constant PACE_CLK0_MULTIPLY_BY            : natural := 44;   -- 27*44/27 = 44MHz
+	constant PACE_CLK1_DIVIDE_BY              : natural := 27;
+	constant PACE_CLK1_MULTIPLY_BY            : natural := 11;   -- 27*11/27 = 11MHz
+	constant PACE_VIDEO_H_SCALE               : integer := 1;
+	constant PACE_VIDEO_V_SCALE               : integer := 1;
+	constant PACE_ENABLE_ADV724					: std_logic := '1';
+	constant USE_VIDEO_VBLANK_INTERRUPT 		: boolean := false;
+	constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '1';
+	constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '1';
 
 	constant PACE_VIDEO_BORDER_RGB            : RGB_t := RGB_BLACK;
 
 	constant M62_VIDEO_H_SIZE				      : integer := 384;
-	constant M62_VIDEO_H_OFFSET           : integer := (512-M62_VIDEO_H_SIZE)/2;
+	constant M62_VIDEO_H_OFFSET           		: integer := (512-M62_VIDEO_H_SIZE)/2;
 	constant M62_VIDEO_V_SIZE				      : integer := 256;
-	
-	constant PACE_VIDEO_NUM_BITMAPS		    : natural := 0;
-	constant PACE_VIDEO_NUM_TILEMAPS	    : natural := 1;
-	constant PACE_VIDEO_NUM_SPRITES 	    : natural := 32;
-	constant PACE_VIDEO_H_SIZE				    : integer := M62_VIDEO_H_SIZE;
-	constant PACE_VIDEO_V_SIZE				    : integer := M62_VIDEO_V_SIZE;
-	constant PACE_VIDEO_L_CROP            : integer := 0;
-	constant PACE_VIDEO_R_CROP            : integer := PACE_VIDEO_L_CROP;
-	constant PACE_VIDEO_PIPELINE_DELAY    : integer := 5;
-	
-	constant PACE_INPUTS_NUM_BYTES        : integer := 6;
-	
-	constant CLK0_FREQ_MHz		            : natural := 
-    27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY;
-	constant CPU_FREQ_MHz                 : natural := 3;
-  
-	constant M62_CPU_CLK_ENA_DIVIDE_BY    : natural := CLK0_FREQ_MHz / CPU_FREQ_MHz;
-	
 
-  
-  
+	constant PACE_VIDEO_NUM_BITMAPS		    	: natural := 0;
+	constant PACE_VIDEO_NUM_TILEMAPS	    		: natural := 1;
+	constant PACE_VIDEO_NUM_SPRITES 	    		: natural := 32;
+	constant PACE_VIDEO_H_SIZE				    	: integer := M62_VIDEO_H_SIZE;
+	constant PACE_VIDEO_V_SIZE				    	: integer := M62_VIDEO_V_SIZE;
+	constant PACE_VIDEO_L_CROP            		: integer := 0;
+	constant PACE_VIDEO_R_CROP            		: integer := PACE_VIDEO_L_CROP;
+	constant PACE_VIDEO_PIPELINE_DELAY    		: integer := 5;
+
+	constant PACE_INPUTS_NUM_BYTES        		: integer := 6;
+
+	constant CLK0_FREQ_MHz		            	: natural := 
+    27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY;
+	constant CPU_FREQ_MHz                 		: natural := 3;
+
+	constant M62_CPU_CLK_ENA_DIVIDE_BY    		: natural := CLK0_FREQ_MHz / CPU_FREQ_MHz;
 
   type from_PLATFORM_IO_t is record
     not_used  : std_logic;
diff --git a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/pll_mist.vhd b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/pll_mist.vhd
index 8e360627..ebe4c7e7 100644
--- a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/pll_mist.vhd	
+++ b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/pll_mist.vhd	
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2013 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -166,19 +166,19 @@ BEGIN
 		bandwidth_type => "AUTO",
 		clk0_divide_by => 27,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 40,
+		clk0_multiply_by => 44,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 43,
+		clk1_divide_by => 27,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 40,
+		clk1_multiply_by => 11,
 		clk1_phase_shift => "0",
-		clk2_divide_by => 3,
+		clk2_divide_by => 27,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 8,
+		clk2_multiply_by => 88,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 5400,
+		clk3_divide_by => 9000,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 179,
+		clk3_multiply_by => 299,
 		clk3_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 37037,
@@ -262,17 +262,17 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "43"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "3"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
 -- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.116280"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "72.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.895000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "44.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "11.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "88.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.897000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -301,15 +301,15 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "40"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "44"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "11"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "88"
 -- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.26315800"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "72.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89500000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "44.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "11.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "88.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89700000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
@@ -371,19 +371,19 @@ END SYN;
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "44"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "43"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "88"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5400"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9000"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "179"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "299"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
diff --git a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/target_top.vhd b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/target_top.vhd
index a4bbbccb..4064a09c 100644
--- a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/target_top.vhd	
+++ b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/target_top.vhd	
@@ -9,40 +9,40 @@ use work.video_controller_pkg.all;
 use work.platform_pkg.all;
 
 entity target_top is port(
-      clock_50      		: in std_logic;
+		clock_sys       : in std_logic;
 		clock_vid      	: in std_logic;
 		clk_aud      		: in std_logic;
-		reset_in      		: in std_logic;
-      audio_out         : out std_logic_vector(11 downto 0);
+		reset_in        : in std_logic;
+		audio_out       : out std_logic_vector(11 downto 0);
 		usr_coin1      	: in std_logic;
-		usr_coin2     		: in std_logic;
-		usr_service     	: in std_logic;
-	   usr_start1      	: in std_logic;
-		usr_start2      	: in std_logic;
-	   p1_up      			: in std_logic;
-	   p1_dw      			: in std_logic;
-	   p1_lt      			: in std_logic;
-	   p1_rt      			: in std_logic;
-		p1_f1      			: in std_logic;
-		p1_f2      			: in std_logic;
+		usr_coin2       : in std_logic;
+		usr_service     : in std_logic;
+		usr_start1      : in std_logic;
+		usr_start2      : in std_logic;
+		p1_up           : in std_logic;
+		p1_dw           : in std_logic;
+		p1_lt           : in std_logic;
+		p1_rt           : in std_logic;
+		p1_f1           : in std_logic;
+		p1_f2           : in std_logic;
 		
-	   p2_up      			: in std_logic;
-	   p2_dw      			: in std_logic;
-	   p2_lt      			: in std_logic;
-	   p2_rt      			: in std_logic;
-		p2_f1      			: in std_logic;
-		p2_f2      			: in std_logic;
-		
-      VGA_VS        		: out std_logic;
-      VGA_HS        		: out std_logic;
-      VGA_R         		: out std_logic_vector(3 downto 0);
-      VGA_G         		: out std_logic_vector(3 downto 0);
-      VGA_B         		: out std_logic_vector(3 downto 0);
-	   cpu_rom_addr      : out std_logic_vector(14 downto 0);
-	   cpu_rom_do        : in std_logic_vector(7 downto 0);
-		snd_rom_addr      : out std_logic_vector(13 downto 0);
-      snd_rom_do        : in std_logic_vector(7 downto 0)
-  );    
+		p2_up           : in std_logic;
+		p2_dw           : in std_logic;
+		p2_lt           : in std_logic;
+		p2_rt           : in std_logic;
+		p2_f1           : in std_logic;
+		p2_f2           : in std_logic;
+
+		VGA_VS          : out std_logic;
+		VGA_HS          : out std_logic;
+		VGA_R           : out std_logic_vector(3 downto 0);
+		VGA_G           : out std_logic_vector(3 downto 0);
+		VGA_B           : out std_logic_vector(3 downto 0);
+		cpu_rom_addr    : out std_logic_vector(14 downto 0);
+		cpu_rom_do      : in std_logic_vector(7 downto 0);
+		snd_rom_addr    : out std_logic_vector(13 downto 0);
+		snd_rom_do      : in std_logic_vector(7 downto 0)
+  );
 end target_top;
 
 architecture SYN of target_top is 
@@ -59,7 +59,7 @@ architecture SYN of target_top is
   signal sound_data     : std_logic_vector(7 downto 0);
 
 begin
-	clkrst_i.clk(0) <= clock_50;
+	clkrst_i.clk(0) <= clock_sys;
 	clkrst_i.clk(1) <= clock_vid;		
 	clkrst_i.arst <= reset_in;
 	clkrst_i.arst_n <= not clkrst_i.arst;
@@ -93,7 +93,7 @@ end generate GEN_RESETS;
 --		select_sound  	=> sound_data,
 --		audio_out     	=> audio_out,
 --		snd_rom_addr   => snd_rom_addr,
---      snd_rom_do     => snd_rom_do,
+ --     snd_rom_do     => snd_rom_do,
 --		dbg_cpu_addr  	=> open
 --	);
  
@@ -140,8 +140,6 @@ pace_inst : entity work.pace
  
 	-- not currently wired to any inputs
 	inputs_i.jamma_n.coin_cnt <= (others => '1');
---	inputs_i.jamma_n.coin(2) <= '1';
---	inputs_i.jamma_n.service <= '1';
 	inputs_i.jamma_n.tilt <= '1';
 	inputs_i.jamma_n.test <= '1';
 end SYN;
diff --git a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller.vhd b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller.vhd
index 14da0c20..9372578d 100644
--- a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller.vhd	
+++ b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller.vhd	
@@ -258,6 +258,16 @@ begin
           v_back_porch_r <= 13;
           v_border_r <= (240-VIDEO_V_SIZE)/2;
 
+				when PACE_VIDEO_PAL_576x288_50Hz =>
+					-- pixclk=11 MHz
+					h_front_porch_r <= 2*6;
+					h_sync_r <= 2*28;
+					h_back_porch_r <= 2*30;
+					h_border_r <= (576-VIDEO_H_SIZE)/2;
+					v_front_porch_r <= 8;
+					v_sync_r <= 3;
+					v_back_porch_r <= 13;
+					v_border_r <= (288-VIDEO_V_SIZE)/2;
 				when others =>
 					null;
 			end case;
diff --git a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller_pkg.vhd b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller_pkg.vhd
index 183bfe23..526be3c8 100644
--- a/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller_pkg.vhd	
+++ b/Arcade_MiST/IremM62 Hardware/LodeRunner_MiST/rtl/video_controller_pkg.vhd	
@@ -21,7 +21,8 @@ package video_controller_pkg is
     PACE_VIDEO_ARCADE_STD_336x240_60Hz,   -- arcade std resolution (7.16MHz)
     PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64,   -- arcade std resolution (28.64MHz)
     PACE_VIDEO_CVBS_720x288p_50Hz,        -- generic composite
-    PACE_VIDEO_LCM_320x240_60Hz           -- DE2 LCD
+    PACE_VIDEO_LCM_320x240_60Hz,          -- DE2 LCD
+    PACE_VIDEO_PAL_576x288_50Hz
   );
 
   type PACEVideoDisplay_t is
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qpf b/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qpf
new file mode 100644
index 00000000..bd3ad814
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version
+# Date created = 11:47:13  October 18, 2011
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "10.1"
+DATE = "11:47:13  October 18, 2011"
+
+# Revisions
+
+PROJECT_REVISION = "Sonson_MiST"
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf b/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf
new file mode 100644
index 00000000..7c7f9830
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/Sonson_MiST.qsf	
@@ -0,0 +1,269 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 21:06:00  February 29, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Sonson_MiST_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SMART_RECOMPILE ON
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY SonSon_MiST
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SEARCH_PATH common/CPU/T80/ -tag from_archive
+set_global_assignment -name SEARCH_PATH common/mist/ -tag from_archive
+set_global_assignment -name SEARCH_PATH rtl/ -tag from_archive
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/mcr3.stp
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# -----------------------------
+# start ENTITY(LodeRunner_MiST)
+
+	# Pin & Location Assignments
+	# ==========================
+
+	# Fitter Assignments
+	# ==================
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(LodeRunner_MiST)
+# ---------------------------
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/SonSon_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/target_top.vhd
+set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/platform.vhd
+set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd
+set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/pace.vhd
+set_global_assignment -name VHDL_FILE rtl/Graphics.VHD
+set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd
+set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd
+set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/video_controller.vhd
+set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
+set_global_assignment -name VHDL_FILE rtl/tilemapctl.vhd
+set_global_assignment -name VHDL_FILE rtl/spritereg.vhd
+set_global_assignment -name VHDL_FILE rtl/spritectl.vhd
+set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd
+set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd
+set_global_assignment -name VHDL_FILE rtl/sprite_array.vhd
+set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu09s.vhd
+set_global_assignment -name VHDL_FILE rtl/sound.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
+set_global_assignment -name VHDL_FILE rtl/dprom_2r.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+set_global_assignment -name VERILOG_FILE "rtl/mc6809-master/mc6809i.v"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/clean.bat b/Arcade_MiST/SonSon Hardware/Sonson_MiST/clean.bat
new file mode 100644
index 00000000..c9a2cb06
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/clean.bat	
@@ -0,0 +1,15 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/Graphics.VHD b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/Graphics.VHD
new file mode 100644
index 00000000..9b3d355e
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/Graphics.VHD	
@@ -0,0 +1,270 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+
+entity Graphics is
+  port
+  (
+    bitmap_ctl_i    : in to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    bitmap_ctl_o    : out from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    tilemap_ctl_i   : in to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+    tilemap_ctl_o   : out from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+
+    sprite_reg_i    : in to_SPRITE_REG_t;
+    sprite_ctl_i    : in to_SPRITE_CTL_t;
+    sprite_ctl_o    : out from_SPRITE_CTL_t;
+		spr0_hit				: out std_logic;
+    
+    graphics_i      : in to_GRAPHICS_t;
+    graphics_o      : out from_GRAPHICS_t;
+
+		video_i					: in from_VIDEO_t;
+		video_o					: out to_VIDEO_t
+  );
+
+end Graphics;
+
+architecture SYN of Graphics is
+
+	alias clk 					    : std_logic is video_i.clk;
+
+  signal from_video_ctl   : from_VIDEO_CTL_t;
+  signal bitmap_ctl_o_s   : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+  signal tilemap_ctl_o_s  : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+  signal sprite_ctl_o_s   : from_SPRITE_CTL_t;
+  signal sprite_pri       : std_logic;
+
+	signal rgb_data			    : RGB_t;
+  -- before OSD is mixed in
+  signal video_o_s        : to_VIDEO_t;
+  
+begin
+
+  -- dodgy OSD transparency...
+	video_o.clk <= video_o_s.clk;
+  video_o.rgb.r <= 	video_o_s.rgb.r;
+  video_o.rgb.g <=  video_o_s.rgb.g;
+  video_o.rgb.b <= 	video_o_s.rgb.b;
+	video_o.hsync <= video_o_s.hsync;
+	video_o.vsync <= video_o_s.vsync;
+	video_o.hblank <= video_o_s.hblank;
+	video_o.vblank <= video_o_s.vblank;
+
+  graphics_o.y <= from_video_ctl.y;
+  -- should this be the 'real' vblank or the 'active' vblank?
+  -- - use the real for now
+  graphics_o.hblank <= video_o_s.hblank;
+  graphics_o.vblank <= video_o_s.vblank;
+  --graphics_o.vblank <= from_video_ctl.vblank;
+    
+  pace_video_controller_inst : entity work.pace_video_controller
+    generic map
+    (
+      CONFIG		  => PACE_VIDEO_CONTROLLER_TYPE,
+      DELAY       => PACE_VIDEO_PIPELINE_DELAY,
+      H_SIZE      => PACE_VIDEO_H_SIZE,
+      V_SIZE      => PACE_VIDEO_V_SIZE,
+      L_CROP      => PACE_VIDEO_L_CROP,
+      R_CROP      => PACE_VIDEO_R_CROP,
+      H_SCALE     => PACE_VIDEO_H_SCALE,
+      V_SCALE     => PACE_VIDEO_V_SCALE,
+      H_SYNC_POL  => PACE_VIDEO_H_SYNC_POLARITY,
+      V_SYNC_POL  => PACE_VIDEO_V_SYNC_POLARITY,
+      BORDER_RGB  => PACE_VIDEO_BORDER_RGB
+    )
+    port map
+    (
+      -- clocking etc
+      video_i         => video_i,
+      
+			-- register interface
+			reg_i.h_scale	=> "000",
+			reg_i.v_scale 	=> "000",
+      -- video data signals (in)
+      rgb_i		    		=> rgb_data,
+
+      -- video control signals (out)
+      video_ctl_o     => from_video_ctl,
+
+      -- VGA signals (out)
+      video_o     		=> video_o_s
+    );
+
+  pace_video_mixer_inst : entity work.pace_video_mixer
+    port map
+    (
+        bitmap_ctl_o  => bitmap_ctl_o_s,
+        tilemap_ctl_o => tilemap_ctl_o_s,
+        sprite_rgb    => sprite_ctl_o_s.rgb,
+        sprite_set    => sprite_ctl_o_s.set,
+        sprite_pri    => sprite_pri,
+        
+        video_ctl_i   => from_video_ctl,
+        graphics_i    => graphics_i,
+        rgb_o         => rgb_data
+    );
+    
+	GEN_NO_BITMAPS : if PACE_VIDEO_NUM_BITMAPS = 0 generate
+    --bitmap_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
+	end generate GEN_NO_BITMAPS;
+	
+	GEN_BITMAP_1 : if PACE_VIDEO_NUM_BITMAPS > 0 generate
+	
+	  forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_1)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+	      ctl_i         => bitmap_ctl_i(1),
+	      ctl_o         => bitmap_ctl_o_s(1),
+
+        graphics_i    => graphics_i
+	    );
+		end generate GEN_BITMAP_1;
+
+	GEN_BITMAP_2 : if PACE_VIDEO_NUM_BITMAPS > 1 generate
+
+	  forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_2)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+	      ctl_i         => bitmap_ctl_i(2),
+	      ctl_o         => bitmap_ctl_o_s(2),
+
+        graphics_i    => graphics_i
+	    );
+      
+  end generate GEN_BITMAP_2;
+
+	GEN_BITMAP_3 : if PACE_VIDEO_NUM_BITMAPS > 2 generate
+
+	  forground_bitmapctl_inst : entity work.bitmapCtl(BITMAP_3)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+	      ctl_i         => bitmap_ctl_i(3),
+	      ctl_o         => bitmap_ctl_o_s(3),
+
+        graphics_i    => graphics_i
+	    );
+      
+  end generate GEN_BITMAP_3;
+  
+  bitmap_ctl_o <= bitmap_ctl_o_s;
+  
+	GEN_NO_TILEMAPS : if PACE_VIDEO_NUM_TILEMAPS = 0 generate
+    --tilemap_ctl_o_s(1) <= ((others => '0'), (others => '0'), (others => '0'), 
+    --                      (others => (others => '0')), '0');
+	end generate GEN_NO_TILEMAPS;
+	
+	GEN_TILEMAP_1 : if PACE_VIDEO_NUM_TILEMAPS > 0 generate
+	
+	  foreground_mapctl_inst : entity work.tilemapCtl(TILEMAP_1)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+				ctl_i         => tilemap_ctl_i(1),
+				ctl_o         => tilemap_ctl_o_s(1),
+
+        graphics_i    => graphics_i
+	    );
+
+		end generate GEN_TILEMAP_1;
+
+	GEN_TILEMAP_2 : if PACE_VIDEO_NUM_TILEMAPS > 1 generate
+	
+	  background_mapctl_inst : entity work.tilemapCtl(TILEMAP_2)
+      generic map
+      (
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+	    port map
+	    (
+				reset					=> video_i.reset,
+				
+				video_ctl     => from_video_ctl,
+
+				ctl_i         => tilemap_ctl_i(2),
+				ctl_o         => tilemap_ctl_o_s(2),
+
+        graphics_i    => graphics_i
+	    );
+
+		end generate GEN_TILEMAP_2;
+    
+  tilemap_ctl_o <= tilemap_ctl_o_s;
+
+	GEN_NO_SPRITES : if PACE_VIDEO_NUM_SPRITES = 0 generate
+    sprite_ctl_o_s <= ((others => '0'), (others => (others => '0')), '0');
+    sprite_pri <= '0';
+    spr0_hit <= '0';
+	end generate GEN_NO_SPRITES;
+	
+	GEN_SPRITES : if PACE_VIDEO_NUM_SPRITES > 0 generate
+	
+		sprites_inst : sprite_array
+      generic map
+      (
+        N_SPRITES     => PACE_VIDEO_NUM_SPRITES,
+        DELAY         => PACE_VIDEO_PIPELINE_DELAY
+      )
+			port map
+			(
+				reset				  => video_i.reset,
+  
+        -- register interface
+        reg_i         => sprite_reg_i,
+
+        -- video control signals
+        video_ctl     => from_video_ctl,
+
+        graphics_i    => graphics_i,
+
+				row_a         => sprite_ctl_o_s.a,
+				row_d         => sprite_ctl_i.d,
+				
+				rgb					  => sprite_ctl_o_s.rgb,
+				set           => sprite_ctl_o_s.set,
+				pri           => sprite_pri,
+				spr0_set	    => spr0_hit
+			);
+
+	end generate GEN_SPRITES;
+
+  sprite_ctl_o <= sprite_ctl_o_s;
+
+end SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv
new file mode 100644
index 00000000..51c1cb8f
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/SonSon_MiST.sv	
@@ -0,0 +1,281 @@
+module SonSon_MiST(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27,
+
+	output [12:0] SDRAM_A,
+	inout  [15:0] SDRAM_DQ,
+	output        SDRAM_DQML,
+	output        SDRAM_DQMH,
+	output        SDRAM_nWE,
+	output        SDRAM_nCAS,
+	output        SDRAM_nRAS,
+	output        SDRAM_nCS,
+	output  [1:0] SDRAM_BA,
+	output        SDRAM_CLK,
+	output        SDRAM_CKE
+);
+
+`include "rtl/build_id.v" 
+
+localparam CONF_STR = {      
+	"SONSON;ROM;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Blending,Off,On;",
+	"O6,Freeze,Off,On;",
+	"O7,Flip,Off,On;",
+	"O8,Test,Off,On;",
+	"T0,Reset;",
+	"V,v1.0.",`BUILD_DATE
+};
+
+wire       rotate    = status[2];
+wire [1:0] scanlines = status[4:3];
+wire       blend     = status[5];
+wire       freeze   = status[6];
+wire       flip   = status[7];
+wire       test   = status[8];
+
+assign LED = ~ioctl_downl;
+assign SDRAM_CKE = 1; 
+
+wire clk_sys, clk_vid;
+wire pll_locked;
+pll_mist pll(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clk_sys),//20
+	.c1(clk_vid),//40
+	.c2(SDRAM_CLK),
+	.locked(pll_locked)
+	);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+	);
+
+wire [15:0] cpu_rom_addr;	
+//wire [15:0] rom_addr;
+wire [15:0] rom_do;
+
+wire [12:0] tile_rom_addr;	
+//wire [12:0] tile_addr;
+wire [15:0] tile_do;
+
+wire [14:0] sp_addr; //todo
+wire [31:0] sp_do; //todo
+
+wire        ioctl_downl;
+wire  [7:0] ioctl_index;
+wire        ioctl_wr;
+wire [24:0] ioctl_addr;
+wire  [7:0] ioctl_dout;
+
+data_io data_io(
+	.clk_sys       ( clk_sys      ),
+	.SPI_SCK       ( SPI_SCK      ),
+	.SPI_SS2       ( SPI_SS2      ),
+	.SPI_DI        ( SPI_DI       ),
+	.ioctl_download( ioctl_downl  ),
+	.ioctl_index   ( ioctl_index  ),
+	.ioctl_wr      ( ioctl_wr     ),
+	.ioctl_addr    ( ioctl_addr   ),
+	.ioctl_dout    ( ioctl_dout   )
+);
+
+wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h10000; //todo
+
+reg port1_req, port2_req;
+sdram sdram(
+	.*,
+	.init_n        ( pll_locked   ),
+	.clk           ( SDRAM_CLK      ),
+
+	// port1 used for main + sound CPU
+	.port1_req     ( port1_req    ),
+	.port1_ack     ( ),
+	.port1_a       ( ioctl_addr[23:1] ),
+	.port1_ds      ( {ioctl_addr[0], ~ioctl_addr[0]} ),
+	.port1_we      ( ioctl_downl ),
+	.port1_d       ( {ioctl_dout, ioctl_dout} ),
+	.port1_q       ( ),
+
+	.cpu1_addr     ( ioctl_downl ? 16'hffff : {1'b0, cpu_rom_addr[15:1]} ),
+	.cpu1_q        ( rom_do ),
+	.cpu2_addr     ( ioctl_downl ? 16'hffff : (16'h6000 + tile_rom_addr[12:1]) ),
+	.cpu2_q        ( tile_do ),
+
+	// port2 for sprite graphics
+	.port2_req     ( port2_req ),
+	.port2_ack     ( ),
+	.port2_a       ( {sp_ioctl_addr[23:1]} ),
+	.port2_ds      ( {sp_ioctl_addr[0], ~sp_ioctl_addr[0]} ),
+	.port2_we      ( ioctl_downl ),
+	.port2_d       ( {ioctl_dout, ioctl_dout} ),
+	.port2_q       ( ),
+
+	.sp_addr       ( ioctl_downl ? 15'h7fff : sp_addr ),
+	.sp_q          ( sp_do )
+);
+
+// ROM download controller
+always @(posedge clk_sys) begin
+	reg        ioctl_wr_last = 0;
+	ioctl_wr_last <= ioctl_wr;
+	if (ioctl_downl) begin
+		if (~ioctl_wr_last && ioctl_wr) begin
+			port1_req <= ~port1_req;
+			port2_req <= ~port2_req;
+		end
+	end
+	// async clock domain crossing here (clk_snd -> clk_sys)	
+end
+
+// reset signal generation
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge clk_sys) begin
+	reg ioctl_downlD;
+	reg [15:0] reset_count;
+	ioctl_downlD <= ioctl_downl;
+
+	if (status[0] | buttons[1] | ~rom_loaded) reset_count <= 16'hffff;
+	else if (reset_count != 0) reset_count <= reset_count - 1'd1;
+
+	if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+	reset <= reset_count != 16'h0000;
+
+end
+
+wire [11:0] audio;
+wire        hs, vs, hb, vb;
+wire        blankn = ~(hb | vb);
+wire  [3:0] g,b,r;
+wire			vma;
+target_top target_top(
+	.clk_sys(clk_sys),
+	.clk_vid(clk_vid),
+	.reset_in(reset),
+	.vma(vma),
+	.snd_l(),
+	.snd_r(),
+	.vid_hs(hs),
+	.vid_vs(vs),
+	.vid_hb(hb),
+	.vid_vb(vb),
+	.vid_r(r),
+	.vid_g(g),
+	.vid_b(b),
+		
+	.inputs_p1(~{2'b00,m_down,m_up,m_right,m_left,1'b0,m_fireC}),
+   .inputs_p2(~{2'b00,m_down2,m_up2,m_right2,m_left2,1'b0,m_fire2C}),
+   .inputs_sys(~{2'b00,m_coin2,m_coin1,2'b00,m_two_players,m_one_player}),
+   .inputs_dip1(~{flip,test,"011111"}),
+   .inputs_dip2(~{freeze,"1111111"}),
+	.cpu_rom_addr(cpu_rom_addr),
+	.cpu_rom_do(cpu_rom_addr[0] ? rom_do[15:8] : rom_do[7:0]),
+	.tile_rom_addr(tile_rom_addr),
+	.tile_rom_do(tile_do)
+  ); 
+
+mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
+	.clk_sys        ( clk_sys          ),
+	.SPI_SCK        ( SPI_SCK          ),
+	.SPI_SS3        ( SPI_SS3          ),
+	.SPI_DI         ( SPI_DI           ),
+	.R              ( blankn ? r : 0   ),
+	.G              ( blankn ? g : 0   ),
+	.B              ( blankn ? b : 0   ),
+	.HSync          ( hs               ),
+	.VSync          ( vs               ),
+	.VGA_R          ( VGA_R            ),
+	.VGA_G          ( VGA_G            ),
+	.VGA_B          ( VGA_B            ),
+	.VGA_VS         ( VGA_VS           ),
+	.VGA_HS         ( VGA_HS           ),
+	.rotate         ( { 1'b1, rotate } ),
+	.ce_divider     ( 1'b0             ),
+	.scandoubler_disable( 1),//                             scandoublerD ),
+	.scanlines      ( scanlines        ),
+	.blend          ( blend            ),
+	.ypbpr          ( ypbpr            ),
+	.no_csync       ( no_csync         )
+	);
+
+wire dac_o;
+assign AUDIO_L = dac_o;
+assign AUDIO_R = dac_o;
+
+dac #(
+	.C_bits(12))
+dac(
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(dac_o)
+	);
+	
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+	.clk         ( clk_sys     ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.rotate      ( rotate      ),
+	.orientation ( 2'b10       ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b1        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
+);
+
+endmodule 
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/YM2149.sv b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/YM2149.sv
new file mode 100644
index 00000000..eae73bb3
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/YM2149.sv	
@@ -0,0 +1,329 @@
+//
+// Copyright (c) MikeJ - Jan 2005
+// Copyright (c) 2016-2018 Sorgelig
+//
+// All rights reserved
+//
+// Redistribution and use in source and synthezised forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in synthesized form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// Neither the name of the author nor the names of other contributors may
+// be used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+
+// BDIR  BC  MODE
+//   0   0   inactive
+//   0   1   read value
+//   1   0   write value
+//   1   1   set address
+//
+
+module YM2149
+(
+	input        CLK,       // Global clock
+	input        CE,        // PSG Clock enable
+	input        RESET,     // Chip RESET (set all Registers to '0', active hi)
+	input        BDIR,      // Bus Direction (0 - read , 1 - write)
+	input        BC,        // Bus control
+	input        A8,
+	input        A9_L,
+	input  [7:0] DI,        // Data In
+	output [7:0] DO,        // Data Out
+	output [7:0] CHANNEL_A, // PSG Output channel A
+	output [7:0] CHANNEL_B, // PSG Output channel B
+	output [7:0] CHANNEL_C, // PSG Output channel C
+
+	input        SEL,
+	input        MODE,
+	
+	output [5:0] ACTIVE,
+
+	input  [7:0] IOA_in,
+	output [7:0] IOA_out,
+
+	input  [7:0] IOB_in,
+	output [7:0] IOB_out
+);
+
+assign ACTIVE  = ~ymreg[7][5:0];
+assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff;
+assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff;
+
+reg [7:0] addr;
+reg [7:0] ymreg[16];
+wire      cs = !A9_L & A8;
+
+// Write to PSG
+reg env_reset;
+always @(posedge CLK) begin
+	if(RESET) begin
+		ymreg     <= '{default:0};
+		ymreg[7]  <= '1;
+		addr      <= '0;
+		env_reset <= 0;
+	end else begin
+		env_reset <= 0;
+		if(cs & BDIR) begin
+			if(BC) addr <= DI;
+			else if(!addr[7:4]) begin
+				ymreg[addr[3:0]] <= DI;
+				env_reset <= (addr == 13);
+			end
+		end
+	end
+end
+
+// Read from PSG
+assign DO = dout;
+reg [7:0] dout;
+always_comb begin
+	dout = 8'hFF;
+	if(cs & ~BDIR & BC & !addr[7:4]) begin
+		case(addr[3:0])
+			 0: dout = ymreg[0];
+			 1: dout = ymreg[1][3:0];
+			 2: dout = ymreg[2];
+			 3: dout = ymreg[3][3:0];
+			 4: dout = ymreg[4];
+			 5: dout = ymreg[5][3:0];
+			 6: dout = ymreg[6][4:0];
+			 7: dout = ymreg[7];
+			 8: dout = ymreg[8][4:0];
+			 9: dout = ymreg[9][4:0];
+			10: dout = ymreg[10][4:0];
+			11: dout = ymreg[11];
+			12: dout = ymreg[12];
+			13: dout = ymreg[13][3:0];
+			14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
+			15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
+		endcase
+	end
+end
+
+reg ena_div;
+reg ena_div_noise;
+
+//  p_divider
+always @(posedge CLK) begin
+	reg [3:0]  cnt_div;
+	reg        noise_div;
+
+	if(CE) begin
+		ena_div <= 0;
+		ena_div_noise <= 0;
+		if(!cnt_div) begin
+			cnt_div <= {SEL, 3'b111};
+			ena_div <= 1;
+            
+			noise_div <= (~noise_div);
+			if (noise_div) ena_div_noise <= 1;
+		end else begin
+			cnt_div <= cnt_div - 1'b1;
+		end
+	end
+end
+
+
+reg [2:0] noise_gen_op;
+
+//  p_noise_gen
+always @(posedge CLK) begin
+	reg [16:0] poly17;
+	reg [4:0]  noise_gen_cnt;
+
+	if(CE) begin
+		if (ena_div_noise) begin
+			if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
+				noise_gen_cnt <= 0;
+				poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
+			end else begin
+				noise_gen_cnt <= noise_gen_cnt + 1'd1;
+			end
+			noise_gen_op <= {3{poly17[0]}};
+		end
+	end
+end
+
+wire [11:0] tone_gen_freq[1:3];
+assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
+assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
+assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
+
+reg [3:1] tone_gen_op;
+
+//p_tone_gens
+always @(posedge CLK) begin
+	integer i;
+	reg [11:0] tone_gen_cnt[1:3];
+
+	if(CE) begin
+		// looks like real chips count up - we need to get the Exact behaviour ..
+	
+		for (i = 1; i <= 3; i = i + 1) begin
+			if(ena_div) begin
+				if (tone_gen_freq[i]) begin
+					if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
+						tone_gen_cnt[i] <= 0;
+						tone_gen_op[i]  <= ~tone_gen_op[i];
+					end else begin
+						tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
+					end
+				end else begin
+					tone_gen_op[i] <= ymreg[7][i];
+					tone_gen_cnt[i] <= 0;
+				end
+			end
+		end
+	end
+end
+
+reg env_ena;
+wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
+
+//p_envelope_freq
+always @(posedge CLK) begin
+	reg [15:0] env_gen_cnt;
+
+	if(CE) begin
+		env_ena <= 0;
+		if(ena_div) begin
+			if (env_gen_cnt >= env_gen_comp) begin
+				env_gen_cnt <= 0;
+				env_ena <= 1;
+			end else begin
+				env_gen_cnt <= (env_gen_cnt + 1'd1);
+			end
+		end
+	end
+end
+
+reg [4:0] env_vol;
+
+wire is_bot    = (env_vol == 5'b00000);
+wire is_bot_p1 = (env_vol == 5'b00001);
+wire is_top_m1 = (env_vol == 5'b11110);
+wire is_top    = (env_vol == 5'b11111);
+
+always @(posedge CLK) begin
+	reg env_hold;
+	reg env_inc;
+
+	// envelope shapes
+	// C AtAlH
+	// 0 0 x x  \___
+	//
+	// 0 1 x x  /___
+	//
+	// 1 0 0 0  \\\\
+	//
+	// 1 0 0 1  \___
+	//
+	// 1 0 1 0  \/\/
+	//           ___
+	// 1 0 1 1  \
+	//
+	// 1 1 0 0  ////
+	//           ___
+	// 1 1 0 1  /
+	//
+	// 1 1 1 0  /\/\
+	//
+	// 1 1 1 1  /___
+
+	if(env_reset | RESET) begin
+		// load initial state
+		if(!ymreg[13][2]) begin		// attack
+			env_vol <= 5'b11111;
+			env_inc <= 0;		// -1
+		end else begin
+			env_vol <= 5'b00000;
+			env_inc <= 1;		// +1
+		end
+		env_hold <= 0;
+	end
+	else if(CE) begin
+		if (env_ena) begin
+			if (!env_hold) begin
+				if (env_inc) env_vol <= (env_vol + 5'b00001);
+					else env_vol <= (env_vol + 5'b11111);
+			end
+
+			// envelope shape control.
+			if(!ymreg[13][3]) begin
+				if(!env_inc) begin	// down
+					if(is_bot_p1) env_hold <= 1;
+				end else if (is_top) env_hold <= 1;
+			end else if(ymreg[13][0]) begin		// hold = 1
+				if(!env_inc) begin	// down
+					if(ymreg[13][1]) begin		// alt
+						if(is_bot) env_hold <= 1;
+					end else if(is_bot_p1) env_hold <= 1;
+				end else if(ymreg[13][1]) begin	// alt
+					if(is_top) env_hold <= 1;
+				end else if(is_top_m1) env_hold <= 1;
+			end else if(ymreg[13][1]) begin		// alternate
+				if(env_inc == 1'b0) begin		// down
+					if(is_bot_p1) env_hold <= 1;
+					if(is_bot) begin
+						env_hold <= 0;
+						env_inc  <= 1;
+					end
+				end else begin
+					if(is_top_m1) env_hold <= 1;
+					if(is_top) begin
+						env_hold <= 0;
+						env_inc  <= 0;
+					end
+				end
+			end
+		end
+	end
+end
+
+reg [5:0] A,B,C;
+always @(posedge CLK) begin
+	A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4]  ? env_vol[4:0] : { ymreg[8][3:0],  ymreg[8][3]}};
+	B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4]  ? env_vol[4:0] : { ymreg[9][3:0],  ymreg[9][3]}};
+	C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}};
+end
+
+wire [7:0] volTable[64] = '{
+	//YM2149
+	8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, 
+	8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, 
+	8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, 
+	8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff,
+
+	//AY8910
+	8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, 
+	8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, 
+	8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, 
+	8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff 
+};
+
+assign CHANNEL_A = volTable[A];
+assign CHANNEL_B = volTable[B];
+assign CHANNEL_C = volTable[C];
+
+endmodule
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/bitmapctl_e.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/bitmapctl_e.vhd
new file mode 100644
index 00000000..8d309476
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/bitmapctl_e.vhd	
@@ -0,0 +1,29 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.platform_pkg.all;
+
+entity bitmapCtl is
+  generic
+  (
+    DELAY         : integer
+  );
+  port               
+  (
+    reset					: in std_logic;
+
+    -- video control signals		
+    video_ctl     : in from_VIDEO_CTL_t;
+
+    -- bitmap controller signals
+    ctl_i         : in to_BITMAP_CTL_t;
+    ctl_o         : out from_BITMAP_CTL_t;
+
+    graphics_i    : in to_GRAPHICS_t
+  );
+end entity bitmapCtl;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/build_id.tcl b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/cpu09s.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/cpu09s.vhd
new file mode 100644
index 00000000..e404bbdf
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/cpu09s.vhd	
@@ -0,0 +1,5679 @@
+--===========================================================================--
+--                                                                           --
+--        Synthesizable 6809 instruction compatible VHDL CPU core            --
+--                                                                           --
+--===========================================================================--
+--
+-- File name      : cpu09.vhd
+--
+-- Entity name    : cpu09
+--
+-- Purpose        : 6809 instruction compatible CPU core written in VHDL
+--                  Not cycle compatible with the original 6809 CPU
+--
+-- Dependencies   : ieee.std_logic_1164
+--                  ieee.std_logic_unsigned
+--
+-- Author         : John E. Kent
+--
+-- Email          : dilbert57@opencores.org      
+--
+-- Web            : http://opencores.org/project,system09
+--
+-- 
+--  Copyright (C) 2003 - 2010 John Kent
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--===========================================================================--
+--                                                                           --
+--                                Revision History                           --
+--                                                                           --
+--===========================================================================--
+--
+-- Version 0.1 - 26 June 2003 - John Kent
+-- Added extra level in state stack
+-- fixed some calls to the extended addressing state
+--
+-- Version 0.2 - 5 Sept 2003 - John Kent
+-- Fixed 16 bit indexed offset (was doing read rather than fetch)
+-- Added/Fixed STY and STS instructions.
+-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
+-- CMPX Loaded ACCA and ACCB - Now fixed 
+--
+-- Version 1.0 - 6 Sep 2003 - John Kent 
+-- Initial release to Open Cores
+-- reversed clock edge
+--
+-- Version 1.1 - 29 November 2003 John kent
+--	ACCA and ACCB indexed offsets are 2's complement.
+-- ALU Right Mux now sign extends ACCA & ACCB offsets
+-- Absolute Indirect addressing performed a read on the
+-- second byte of the address rather than a fetch
+-- so it formed an incorrect address. Now fixed. 
+--
+-- Version 1.2 - 29 November 2003 John Kent
+-- LEAX and LEAY affect the Z bit only
+--	LEAS and LEAU do not affect any condition codes
+-- added an extra ALU control for LEA.
+--
+-- Version 1.3 - 12 December 2003 John Kent
+-- CWAI did not work, was missed a PUSH_ST on calling
+-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
+-- finding this fault.
+--
+-- Version 1.4 - 12 December 2003 John Kent
+-- Missing cc_ctrl assignment in otherwise case of 
+-- lea_state resulted in cc_ctrl being latched in
+-- that state.	
+-- The otherwise statement should never be reached,
+-- and has been fixed simply to resolve synthesis warnings.
+--
+-- Version 1.5 - 17 january 2004 John kent
+-- The clear instruction used "alu_ld8" to control the ALU
+-- rather than "alu_clr". This mean the Carry was not being
+-- cleared correctly.
+--
+-- Version 1.6 - 24 January 2004 John Kent
+-- Fixed problems in PSHU instruction
+--
+-- Version 1.7 - 25 January 2004 John Kent
+-- removed redundant "alu_inx" and "alu_dex'
+-- Removed "test_alu" and "test_cc"
+-- STD instruction did not set condition codes
+-- JMP direct was not decoded properly
+-- CLR direct performed an unwanted read cycle
+-- Bogus "latch_md" in Page2 indexed addressing
+--
+-- Version 1.8 - 27 January 2004 John Kent
+-- CWAI in decode1_state should increment the PC.
+-- ABX is supposed to be an unsigned addition.
+-- Added extra ALU function
+-- ASR8 slightly changed in the ALU.
+--
+--	Version 1.9 - 20 August 2005
+-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
+-- rather than LSR16. There was a problem with single 
+-- operand instructions using the MD register which is
+-- sign extended on the first 8 bit fetch.
+--
+-- Version 1.10 - 13 September 2005
+-- TFR & EXG instructions did not work for the Condition Code Register
+-- An extra case has been added to the ALU for the alu_tfr control 
+-- to assign the left ALU input (alu_left) to the condition code
+-- outputs (cc_out). 
+--
+-- Version 1.11 - 16 September 2005
+-- JSR ,X should not predecrement S before calculating the jump address.
+-- The reason is that JSR [0,S] needs S to point to the top of the stack
+-- to fetch a valid vector address. The solution is to have the addressing
+-- mode microcode called before decrementing S and then decrementing S in
+-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
+-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
+-- pushed on the stack. This adds one extra bus cycle, but resolves the
+-- addressing conflict. I've also removed the pre-decement S in 
+-- JSR EXTENDED as it also calls JSR_STATE.
+--
+-- Version 1.12 - 6th June 2006
+-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
+-- This is different to the 6800. CLR should reset the V bit.
+--
+-- Version 1.13 - 7th July 2006
+-- Disable NMI on reset until S Stack pointer has been loaded.
+-- Added nmi_enable signal in sp_reg process and nmi_handler process.
+--
+-- Version 1.14 - 11th July 2006
+-- 1. Added new state to RTI called rti_entire_state.
+-- This state tests the CC register after it has been loaded
+-- from the stack. Previously the current CC was tested which
+-- was incorrect. The Entire Flag should be set before the
+-- interrupt stacks the CC.
+-- 2. On bogus Interrupts, int_cc_state went to rti_state,
+-- which was an enumerated state, but not defined anywhere.
+-- rti_state has been changed to rti_cc_state so that bogus interrupt
+-- will perform an RTI after entering that state.
+-- 3. Sync should generate an interrupt if the interrupt masks
+-- are cleared. If the interrupt masks are set, then an interrupt
+-- will cause the the PC to advance to the next instruction.
+-- Note that I don't wait for an interrupt to be asserted for
+-- three clock cycles.
+-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
+-- the Multiply instruction replacing "alu_add16". This is similar 
+-- to "alu_add16" except it sets the Carry bit to B7 of the result
+-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
+-- does not affect The Half carry (H), Negative (N) or Overflow (V)
+-- flags. The logic was re-arranged so that it adds md or zero so 
+-- that the Carry condition code is set on zero multiplicands.
+-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
+-- and Zero Flags. It will also affect the Overflow (V) flag although
+-- the operation is undefined. It's anyones guess what DAA does to V.
+--
+-- Version 1.15 - 25th Feb 2007 - John Kent
+-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
+-- Changed sensitivity lists.
+--
+-- Version 1.16 - 5th February 2008 - John Kent
+-- FIRQ interrupts should take priority over IRQ Interrupts.
+-- This presumably means they should be tested for before IRQ
+-- when they happen concurrently.
+--
+-- Version 1.17 - 18th February 2008 - John Kent
+-- NMI in CWAI should mask IRQ and FIRQ interrupts
+--
+-- Version 1.18 - 21st February 2008 - John Kent
+-- Removed default register settings in each case statement
+-- and placed them at the beginning of the state sequencer.
+-- Modified the SYNC instruction so that the interrupt vector(iv)
+-- is not set unless an unmasked FIRQ or IRQ is received.
+--
+-- Version 1.19 - 25th February 2008 - John Kent
+-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
+-- Enumerated separate states for MASKI and MASKIF states
+-- Removed code on BSR/JSR in fetch cycle
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity cpu09 is
+  generic (
+    CLK_POL   : std_logic := '0'
+  );
+	port (	
+		clk       :	in std_logic;
+    clk_en    : in std_logic := '1';
+		rst       :  in std_logic;
+		vma       : out std_logic;
+		addr      : out std_logic_vector(15 downto 0);
+		rw        : out std_logic;
+	  data_out  : out std_logic_vector(7 downto 0);
+	  data_in   :  in std_logic_vector(7 downto 0);
+		irq       :  in std_logic;
+		firq      :  in std_logic;
+		nmi       :  in std_logic;
+		halt      :  in std_logic;
+		hold      :  in std_logic
+		);
+end cpu09;
+
+architecture rtl of cpu09 is
+
+  constant EBIT : integer := 7;
+  constant FBIT : integer := 6;
+  constant HBIT : integer := 5;
+  constant IBIT : integer := 4;
+  constant NBIT : integer := 3;
+  constant ZBIT : integer := 2;
+  constant VBIT : integer := 1;
+  constant CBIT : integer := 0;
+
+  --
+  -- Interrupt vector modifiers
+  --
+  constant RST_VEC  : std_logic_vector(2 downto 0) := "111";
+  constant NMI_VEC  : std_logic_vector(2 downto 0) := "110";
+  constant SWI_VEC  : std_logic_vector(2 downto 0) := "101";
+  constant IRQ_VEC  : std_logic_vector(2 downto 0) := "100";
+  constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
+  constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
+  constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
+  constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
+
+	type state_type is (-- Start off in Reset
+	                    reset_state,
+							  -- Fetch Interrupt Vectors (including reset)
+							  vect_lo_state, vect_hi_state,
+                       -- Fetch Instruction Cycle
+                       fetch_state,
+							  -- Decode Instruction Cycles
+                       decode1_state, decode2_state, decode3_state,
+							  -- Calculate Effective Address
+						     imm16_state,
+		                 indexed_state, index8_state, index16_state, index16_2_state,
+							  pcrel8_state, pcrel16_state, pcrel16_2_state,
+							  indexaddr_state, indexaddr2_state,
+						     postincr1_state, postincr2_state,
+							  indirect_state, indirect2_state, indirect3_state,
+                       extended_state,
+							  -- single ops
+							  single_op_read_state,
+						     single_op_exec_state,
+	                    single_op_write_state,
+							  -- Dual op states
+							  dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
+						     dual_op_write8_state, dual_op_write16_state,
+                       -- 
+						     sync_state, halt_state, error_state,
+							  --
+							  andcc_state, orcc_state,
+							  tfr_state, exg_state, exg1_state,
+							  lea_state,
+							  -- Multiplication
+						     mul_state, mulea_state, muld_state,
+						     mul0_state, mul1_state, mul2_state, mul3_state,
+						     mul4_state, mul5_state, mul6_state, mul7_state,
+							  --  Branches
+							  lbranch_state, sbranch_state,
+							  -- Jumps, Subroutine Calls and Returns
+                       jsr_state, jmp_state,
+                       push_return_hi_state, push_return_lo_state,
+                       pull_return_hi_state, pull_return_lo_state,
+							  -- Interrupt cycles
+							  int_nmiirq_state, int_firq_state,
+							  int_entire_state, int_fast_state,
+							  int_pcl_state,  int_pch_state,
+						     int_upl_state,  int_uph_state,
+						     int_iyl_state,  int_iyh_state,
+						     int_ixl_state,  int_ixh_state,
+						     int_dp_state,
+				           int_accb_state, int_acca_state,
+						     int_cc_state,
+						     int_cwai_state, 
+							  int_maski_state, int_maskif_state,
+							  -- Return From Interrupt
+						     rti_cc_state,   rti_entire_state,
+							  rti_acca_state, rti_accb_state,
+						     rti_dp_state,
+						     rti_ixl_state,  rti_ixh_state,
+						     rti_iyl_state,  rti_iyh_state,
+						     rti_upl_state,  rti_uph_state,
+						     rti_pcl_state,  rti_pch_state,
+							  -- Push Registers using SP
+							  pshs_state,
+						     pshs_pcl_state,  pshs_pch_state,
+						     pshs_upl_state,  pshs_uph_state,
+						     pshs_iyl_state,  pshs_iyh_state,
+						     pshs_ixl_state,  pshs_ixh_state,
+						     pshs_dp_state,
+						     pshs_acca_state, pshs_accb_state,
+						     pshs_cc_state,
+							  -- Pull Registers using SP
+							  puls_state,
+							  puls_cc_state,
+							  puls_acca_state, puls_accb_state,
+							  puls_dp_state,
+						     puls_ixl_state,  puls_ixh_state,
+						     puls_iyl_state,  puls_iyh_state,
+						     puls_upl_state,  puls_uph_state,
+						     puls_pcl_state,  puls_pch_state,
+							  -- Push Registers using UP
+							  pshu_state,
+						     pshu_pcl_state,  pshu_pch_state,
+						     pshu_spl_state,  pshu_sph_state,
+						     pshu_iyl_state,  pshu_iyh_state,
+						     pshu_ixl_state,  pshu_ixh_state,
+						     pshu_dp_state,
+						     pshu_acca_state, pshu_accb_state,
+						     pshu_cc_state,
+							  -- Pull Registers using UP
+							  pulu_state,
+							  pulu_cc_state,
+							  pulu_acca_state, pulu_accb_state,
+							  pulu_dp_state,
+						     pulu_ixl_state,  pulu_ixh_state,
+						     pulu_iyl_state,  pulu_iyh_state,
+						     pulu_spl_state,  pulu_sph_state,
+						     pulu_pcl_state,  pulu_pch_state );
+
+	type stack_type is array(2 downto 0) of state_type;
+	type st_type    is (idle_st, push_st, pull_st );
+	type addr_type  is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
+	type dout_type  is (cc_dout, acca_dout, accb_dout, dp_dout,
+                       ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
+                       up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
+                       pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
+   type op_type    is (reset_op, fetch_op, latch_op );
+   type pre_type   is (reset_pre, fetch_pre, latch_pre );
+   type cc_type    is (reset_cc, load_cc, pull_cc, latch_cc );
+   type acca_type  is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
+   type accb_type  is (reset_accb, load_accb, pull_accb, latch_accb );
+   type dp_type    is (reset_dp, load_dp, pull_dp, latch_dp );
+	type ix_type    is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
+	type iy_type    is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
+	type sp_type    is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
+	type up_type    is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
+	type pc_type    is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
+   type md_type    is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
+   type ea_type    is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
+	type iv_type    is (latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
+	type nmi_type   is (reset_nmi, set_nmi, latch_nmi );
+	type left_type  is (cc_left, acca_left, accb_left, dp_left,
+							  ix_left, iy_left, up_left, sp_left,
+                       accd_left, md_left, pc_left, ea_left );
+	type right_type is (ea_right, zero_right, one_right, two_right,
+                       acca_right, accb_right, accd_right,
+							  md_right, md_sign5_right, md_sign8_right );
+   type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc, 
+                       alu_and, alu_ora, alu_eor,
+                       alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
+						     alu_lsr16, alu_lsl16,
+						     alu_ror8, alu_rol8, alu_mul,
+						     alu_asr8, alu_asl8, alu_lsr8,
+						     alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
+							  alu_seif, alu_sei, alu_see, alu_cle,
+						     alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
+
+	signal op_code:     std_logic_vector(7 downto 0);
+	signal pre_code:    std_logic_vector(7 downto 0);
+  	signal acca:        std_logic_vector(7 downto 0);
+  	signal accb:        std_logic_vector(7 downto 0);
+   signal cc:          std_logic_vector(7 downto 0);
+	signal cc_out:      std_logic_vector(7 downto 0);
+	signal dp:          std_logic_vector(7 downto 0);
+	signal xreg:        std_logic_vector(15 downto 0);
+	signal yreg:        std_logic_vector(15 downto 0);
+	signal sp:          std_logic_vector(15 downto 0);
+	signal up:          std_logic_vector(15 downto 0);
+	signal ea:          std_logic_vector(15 downto 0);
+	signal pc:	        std_logic_vector(15 downto 0);
+	signal md:          std_logic_vector(15 downto 0);
+   signal left:        std_logic_vector(15 downto 0);
+   signal right:       std_logic_vector(15 downto 0);
+	signal out_alu:     std_logic_vector(15 downto 0);
+	signal iv:          std_logic_vector(2 downto 0);
+	signal nmi_req:     std_logic;
+	signal nmi_ack:     std_logic;
+	signal nmi_enable:  std_logic;
+
+	signal state:        state_type;
+	signal next_state:   state_type;
+	signal saved_state:  state_type;
+	signal return_state: state_type;
+	signal state_stack:  stack_type;
+	signal st_ctrl:      st_type;
+   signal pc_ctrl:      pc_type;
+   signal ea_ctrl:      ea_type; 
+   signal op_ctrl:      op_type;
+	signal pre_ctrl:     pre_type;
+	signal md_ctrl:      md_type;
+	signal acca_ctrl:    acca_type;
+	signal accb_ctrl:    accb_type;
+	signal ix_ctrl:      ix_type;
+	signal iy_ctrl:      iy_type;
+	signal cc_ctrl:      cc_type;
+	signal dp_ctrl:      dp_type;
+	signal sp_ctrl:      sp_type;
+	signal up_ctrl:      up_type;
+	signal iv_ctrl:      iv_type;
+	signal left_ctrl:    left_type;
+	signal right_ctrl:   right_type;
+   signal alu_ctrl:     alu_type;
+   signal addr_ctrl:    addr_type;
+   signal dout_ctrl:    dout_type;
+   signal nmi_ctrl:     nmi_type;
+
+
+begin
+
+----------------------------------
+--
+-- State machine stack
+--
+----------------------------------
+--state_stack_proc: process( clk, hold, state_stack, st_ctrl, 
+--                           return_state, fetch_state  )
+state_stack_proc: process( clk, state_stack )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       state_stack(0) <= state_stack(0); 
+       state_stack(1) <= state_stack(1); 
+       state_stack(2) <= state_stack(2); 
+     else
+       case st_ctrl is
+      when idle_st =>
+        state_stack(0) <= state_stack(0); 
+         state_stack(1) <= state_stack(1); 
+         state_stack(2) <= state_stack(2); 
+        when push_st =>
+        state_stack(0) <= return_state; 
+         state_stack(1) <= state_stack(0); 
+         state_stack(2) <= state_stack(1); 
+        when pull_st =>
+        state_stack(0) <= state_stack(1); 
+         state_stack(1) <= state_stack(2); 
+         state_stack(2) <= fetch_state;
+      when others =>
+        state_stack(0) <= state_stack(0); 
+         state_stack(1) <= state_stack(1); 
+         state_stack(2) <= state_stack(2); 
+       end case;
+      end if;
+    end if; -- clk_en
+  end if; -- clk'event
+  saved_state <= state_stack(0);
+end process;
+
+----------------------------------
+--
+-- Program Counter Control
+--
+----------------------------------
+
+--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
+pc_reg: process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       pc <= pc;
+     else
+      case pc_ctrl is
+     when reset_pc =>
+       pc <= "0000000000000000";
+     when load_pc =>
+       pc <= out_alu(15 downto 0);
+     when pull_lo_pc =>
+       pc(7 downto 0) <= data_in;
+     when pull_hi_pc =>
+       pc(15 downto 8) <= data_in;
+     when incr_pc =>
+       pc <= pc + 1;
+     when others =>
+  --	 when latch_pc =>
+        pc <= pc;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+----------------------------------
+--
+-- Effective Address  Control
+--
+----------------------------------
+
+--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
+ea_reg: process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       ea <= ea;
+     else
+      case ea_ctrl is
+     when reset_ea =>
+       ea <= "0000000000000000";
+     when fetch_first_ea =>
+       ea(7 downto 0) <= data_in;
+        ea(15 downto 8) <= dp;
+       when fetch_next_ea =>
+       ea(15 downto 8) <= ea(7 downto 0);
+        ea(7 downto 0)  <= data_in;
+     when load_ea =>
+       ea <= out_alu(15 downto 0);
+     when others =>
+  --  	 when latch_ea =>
+        ea <= ea;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+--------------------------------
+--
+-- Accumulator A
+--
+--------------------------------
+--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
+acca_reg : process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       acca <= acca;
+     else
+      case acca_ctrl is
+      when reset_acca =>
+       acca <= "00000000";
+     when load_acca =>
+       acca <= out_alu(7 downto 0);
+     when load_hi_acca =>
+       acca <= out_alu(15 downto 8);
+     when pull_acca =>
+       acca <= data_in;
+     when others =>
+  --	 when latch_acca =>
+       acca <= acca;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+--------------------------------
+--
+-- Accumulator B
+--
+--------------------------------
+--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
+accb_reg : process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       accb <= accb;
+     else
+      case accb_ctrl is
+      when reset_accb =>
+       accb <= "00000000";
+     when load_accb =>
+       accb <= out_alu(7 downto 0);
+     when pull_accb =>
+       accb <= data_in;
+     when others =>
+  --	 when latch_accb =>
+       accb <= accb;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+--------------------------------
+--
+-- X Index register
+--
+--------------------------------
+--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
+ix_reg : process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       xreg <= xreg;
+     else
+      case ix_ctrl is
+      when reset_ix =>
+       xreg <= "0000000000000000";
+     when load_ix =>
+       xreg <= out_alu(15 downto 0);
+     when pull_hi_ix =>
+       xreg(15 downto 8) <= data_in;
+     when pull_lo_ix =>
+       xreg(7 downto 0) <= data_in;
+     when others =>
+  --	 when latch_ix =>
+       xreg <= xreg;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+--------------------------------
+--
+-- Y Index register
+--
+--------------------------------
+--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
+iy_reg : process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       yreg <= yreg;
+     else
+      case iy_ctrl is
+      when reset_iy =>
+       yreg <= "0000000000000000";
+     when load_iy =>
+       yreg <= out_alu(15 downto 0);
+     when pull_hi_iy =>
+       yreg(15 downto 8) <= data_in;
+     when pull_lo_iy =>
+       yreg(7 downto 0) <= data_in;
+     when others =>
+  --	 when latch_iy =>
+       yreg <= yreg;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+--------------------------------
+--
+-- S stack pointer
+--
+--------------------------------
+--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
+sp_reg : process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       sp <= sp;
+      nmi_enable <= nmi_enable;
+     else
+      case sp_ctrl is
+      when reset_sp =>
+       sp <= "0000000000000000";
+      nmi_enable <= '0';
+     when load_sp =>
+       sp <= out_alu(15 downto 0);
+      nmi_enable <= '1';
+     when pull_hi_sp =>
+       sp(15 downto 8) <= data_in;
+      nmi_enable <= nmi_enable;
+     when pull_lo_sp =>
+       sp(7 downto 0) <= data_in;
+      nmi_enable <= '1';
+     when others =>
+  --	 when latch_sp =>
+       sp <= sp;
+      nmi_enable <= nmi_enable;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+--------------------------------
+--
+-- U stack pointer
+--
+--------------------------------
+--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
+up_reg : process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       up <= up;
+     else
+      case up_ctrl is
+      when reset_up =>
+       up <= "0000000000000000";
+     when load_up =>
+       up <= out_alu(15 downto 0);
+     when pull_hi_up =>
+       up(15 downto 8) <= data_in;
+     when pull_lo_up =>
+       up(7 downto 0) <= data_in;
+     when others =>
+  --	 when latch_up =>
+       up <= up;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+--------------------------------
+--
+-- Memory Data
+--
+--------------------------------
+--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
+md_reg : process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       md <= md;
+     else
+      case md_ctrl is
+      when reset_md =>
+       md <= "0000000000000000";
+     when load_md =>
+       md <= out_alu(15 downto 0);
+     when fetch_first_md => -- sign extend md for branches
+       md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
+                          data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
+       md(7 downto 0) <= data_in;
+     when fetch_next_md =>
+       md(15 downto 8) <= md(7 downto 0);
+      md(7 downto 0) <= data_in;
+     when shiftl_md =>
+       md(15 downto 1) <= md(14 downto 0);
+      md(0) <= '0';
+     when others =>
+  --	 when latch_md =>
+       md <= md;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+
+----------------------------------
+--
+-- Condition Codes
+--
+----------------------------------
+
+--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
+cc_reg: process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       cc <= cc;
+     else
+      case cc_ctrl is
+     when reset_cc =>
+       cc <= "11010000"; -- set EBIT, FBIT & IBIT
+     when load_cc =>
+       cc <= cc_out;
+       when pull_cc =>
+        cc <= data_in;
+     when others =>
+  --  when latch_cc =>
+        cc <= cc;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+----------------------------------
+--
+-- Direct Page register
+--
+----------------------------------
+
+--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
+dp_reg: process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       dp <= dp;
+     else
+      case dp_ctrl is
+     when reset_dp =>
+       dp <= "00000000";
+     when load_dp =>
+       dp <= out_alu(7 downto 0);
+       when pull_dp =>
+        dp <= data_in;
+     when others =>
+  --  when latch_dp =>
+        dp <= dp;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+----------------------------------
+--
+-- interrupt vector
+--
+----------------------------------
+
+--iv_mux: process( clk, iv_ctrl, hold, iv )
+iv_mux: process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       iv <= iv;
+     else
+      case iv_ctrl is
+     when reset_iv =>
+       iv <= RST_VEC;
+     when nmi_iv =>
+        iv <= NMI_VEC;
+       when swi_iv =>
+        iv <= SWI_VEC;
+     when irq_iv =>
+        iv <= IRQ_VEC;
+     when firq_iv =>
+       iv <= FIRQ_VEC;
+     when swi2_iv =>
+        iv <= SWI2_VEC;
+       when swi3_iv =>
+        iv <= SWI3_VEC;
+     when resv_iv =>
+        iv <= RESV_VEC;
+     when others =>
+       iv <= iv;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+
+----------------------------------
+--
+-- op code register
+--
+----------------------------------
+
+--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
+op_reg: process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       op_code <= op_code;
+     else
+      case op_ctrl is
+     when reset_op =>
+       op_code <= "00010010";
+       when fetch_op =>
+        op_code <= data_in;
+     when others =>
+  --	 when latch_op =>
+       op_code <= op_code;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+
+----------------------------------
+--
+-- pre byte op code register
+--
+----------------------------------
+
+--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
+pre_reg: process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold= '1' then
+       pre_code <= pre_code;
+     else
+      case pre_ctrl is
+     when reset_pre =>
+       pre_code <= "00000000";
+       when fetch_pre =>
+        pre_code <= data_in;
+     when others =>
+  --	 when latch_pre =>
+       pre_code <= pre_code;
+      end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+--------------------------------
+--
+-- state machine
+--
+--------------------------------
+
+--change_state: process( clk, rst, state, hold, next_state )
+change_state: process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if rst = '1' then
+       state <= reset_state;
+      else
+       if hold = '1' then
+        state <= state;
+      else
+          state <= next_state;
+      end if;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+	-- output
+	
+------------------------------------
+--
+-- Nmi register
+--
+------------------------------------
+
+--nmi_reg: process( clk, nmi_ctrl, hold, nmi_ack )
+nmi_reg: process( clk )
+begin
+  if clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+      if hold = '1' then
+        nmi_ack <= nmi_ack;
+      else
+      case nmi_ctrl is
+     when set_nmi =>
+        nmi_ack <= '1';
+     when reset_nmi =>
+       nmi_ack <= '0';
+     when others =>
+  --  when latch_nmi =>
+       nmi_ack <= nmi_ack;
+     end case;
+     end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+------------------------------------
+--
+-- Detect Edge of NMI interrupt
+--
+------------------------------------
+
+--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
+nmi_handler : process( rst, clk )
+begin
+  if rst='1' then
+	 nmi_req <= '0';
+  elsif clk'event and clk = CLK_POL then
+    if clk_en = '1' then
+       if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
+         nmi_req <= '1';
+       else
+        if (nmi='0') and (nmi_ack='1') then
+           nmi_req <= '0';
+        end if;
+      end if;
+    end if; -- clk_en
+  end if; -- clk'event
+end process;
+
+
+----------------------------------
+--
+-- Address output multiplexer
+--
+----------------------------------
+
+addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
+begin
+  case addr_ctrl is
+    when idle_ad =>
+		vma  <= '0';
+	   addr <= "1111111111111111";
+		rw   <= '1';
+    when fetch_ad =>
+		vma  <= '1';
+	   addr <= pc;
+		rw   <= '1';
+	 when read_ad =>
+		vma  <= '1';
+	   addr <= ea;
+		rw   <= '1';
+    when write_ad =>
+		vma  <= '1';
+	   addr <= ea;
+		rw   <= '0';
+	 when pushs_ad =>
+		vma  <= '1';
+	   addr <= sp;
+		rw   <= '0';
+    when pulls_ad =>
+		vma  <= '1';
+	   addr <= sp;
+		rw   <= '1';
+	 when pushu_ad =>
+		vma  <= '1';
+	   addr <= up;
+		rw   <= '0';
+    when pullu_ad =>
+		vma  <= '1';
+	   addr <= up;
+		rw   <= '1';
+	 when int_hi_ad =>
+		vma  <= '1';
+	   addr <= "111111111111" & iv & "0";
+		rw   <= '1';
+    when int_lo_ad =>
+		vma  <= '1';
+	   addr <= "111111111111" & iv & "1";
+		rw   <= '1';
+	 when others =>
+		vma  <= '0';
+	   addr <= "1111111111111111";
+		rw   <= '1';
+  end case;
+end process;
+
+--------------------------------
+--
+-- Data Bus output
+--
+--------------------------------
+dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
+begin
+    case dout_ctrl is
+	 when cc_dout => -- condition code register
+	   data_out <= cc;
+	 when acca_dout => -- accumulator a
+	   data_out <= acca;
+	 when accb_dout => -- accumulator b
+	   data_out <= accb;
+	 when dp_dout => -- direct page register
+	   data_out <= dp;
+	 when ix_lo_dout => -- X index reg
+	   data_out <= xreg(7 downto 0);
+	 when ix_hi_dout => -- X index reg
+	   data_out <= xreg(15 downto 8);
+	 when iy_lo_dout => -- Y index reg
+	   data_out <= yreg(7 downto 0);
+	 when iy_hi_dout => -- Y index reg
+	   data_out <= yreg(15 downto 8);
+	 when up_lo_dout => -- U stack pointer
+	   data_out <= up(7 downto 0);
+	 when up_hi_dout => -- U stack pointer
+	   data_out <= up(15 downto 8);
+	 when sp_lo_dout => -- S stack pointer
+	   data_out <= sp(7 downto 0);
+	 when sp_hi_dout => -- S stack pointer
+	   data_out <= sp(15 downto 8);
+	 when md_lo_dout => -- alu output
+	   data_out <= md(7 downto 0);
+	 when md_hi_dout => -- alu output
+	   data_out <= md(15 downto 8);
+	 when pc_lo_dout => -- low order pc
+	   data_out <= pc(7 downto 0);
+	 when pc_hi_dout => -- high order pc
+	   data_out <= pc(15 downto 8);
+	 when others =>
+	   data_out <= "00000000";
+    end case;
+end process;
+
+----------------------------------
+--
+-- Left Mux
+--
+----------------------------------
+
+left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
+begin
+  case left_ctrl is
+	 when cc_left =>
+	   left(15 downto 8) <= "00000000";
+		left(7 downto 0)  <= cc;
+	 when acca_left =>
+	   left(15 downto 8) <= "00000000";
+		left(7 downto 0)  <= acca;
+	 when accb_left =>
+	   left(15 downto 8) <= "00000000";
+		left(7 downto 0)  <= accb;
+	 when dp_left =>
+	   left(15 downto 8) <= "00000000";
+		left(7 downto 0)  <= dp;
+	 when accd_left =>
+	   left(15 downto 8) <= acca;
+		left(7 downto 0)  <= accb;
+	 when md_left =>
+	   left <= md;
+	 when ix_left =>
+	   left <= xreg;
+	 when iy_left =>
+	   left <= yreg;
+	 when sp_left =>
+	   left <= sp;
+	 when up_left =>
+	   left <= up;
+	 when pc_left =>
+	   left <= pc;
+	 when others =>
+--	 when ea_left =>
+	   left <= ea;
+    end case;
+end process;
+
+----------------------------------
+--
+-- Right Mux
+--
+----------------------------------
+
+right_mux: process( right_ctrl, md, acca, accb, ea )
+begin
+  case right_ctrl is
+	 when ea_right =>
+	   right <= ea;
+	 when zero_right =>
+	   right <= "0000000000000000";
+	 when one_right =>
+	   right <= "0000000000000001";
+	 when two_right =>
+	   right <= "0000000000000010";
+	 when acca_right =>
+	   if acca(7) = '0' then
+	     right <= "00000000" & acca(7 downto 0);
+		else
+		  right <= "11111111" & acca(7 downto 0);
+		end if;
+	 when accb_right =>
+	   if accb(7) = '0' then
+	     right <= "00000000" & accb(7 downto 0);
+		else
+		  right <= "11111111" & accb(7 downto 0);
+		end if;
+	 when accd_right =>
+	   right <= acca & accb;
+	 when md_sign5_right =>
+	   if md(4) = '0' then
+	     right <= "00000000000" & md(4 downto 0);
+		else
+		  right <= "11111111111" & md(4 downto 0);
+		end if;
+	 when md_sign8_right =>
+	   if md(7) = '0' then
+	     right <= "00000000" & md(7 downto 0);
+		else
+		  right <= "11111111" & md(7 downto 0);
+		end if;
+	 when others =>
+--	 when md_right =>
+	   right <= md;
+    end case;
+end process;
+
+----------------------------------
+--
+-- Arithmetic Logic Unit
+--
+----------------------------------
+
+alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
+variable valid_lo, valid_hi : boolean;
+variable carry_in : std_logic;
+variable daa_reg : std_logic_vector(7 downto 0);
+begin
+
+  case alu_ctrl is
+  	 when alu_adc | alu_sbc |
+  	      alu_rol8 | alu_ror8 =>
+	   carry_in := cc(CBIT);
+    when alu_asr8 =>
+	   carry_in := left(7);
+  	 when others =>
+	   carry_in := '0';
+  end case;
+
+  valid_lo := left(3 downto 0) <= 9;
+  valid_hi := left(7 downto 4) <= 9;
+
+  if (cc(CBIT) = '0') then
+    if( cc(HBIT) = '1' ) then
+		if valid_hi then
+		  daa_reg := "00000110";
+		else
+		  daa_reg := "01100110";
+	   end if;
+    else
+		if valid_lo then
+		  if valid_hi then
+		    daa_reg := "00000000";
+		  else
+		    daa_reg := "01100000";
+		  end if;
+		else
+	     if( left(7 downto 4) <= 8 ) then
+		    daa_reg := "00000110";
+		  else
+			 daa_reg := "01100110";
+		  end if;
+		end if;
+	 end if;
+  else
+    if ( cc(HBIT) = '1' )then
+		daa_reg := "01100110";
+ 	 else
+		if valid_lo then
+		  daa_reg := "01100000";
+	   else
+		  daa_reg := "01100110";
+		end if;
+	 end if;
+  end if;
+
+  case alu_ctrl is
+  	 when alu_add8 | alu_inc |
+  	      alu_add16 | alu_adc | alu_mul =>
+		out_alu <= left + right + ("000000000000000" & carry_in);
+  	 when alu_sub8 | alu_dec |
+  	      alu_sub16 | alu_sbc =>
+	   out_alu <= left - right - ("000000000000000" & carry_in);
+    when alu_abx =>
+	   out_alu <= left + ("00000000" & right(7 downto 0)) ;
+  	 when alu_and =>
+	   out_alu   <= left and right; 	-- and/bit
+  	 when alu_ora =>
+	   out_alu   <= left or right; 	-- or
+  	 when alu_eor =>
+	   out_alu   <= left xor right; 	-- eor/xor
+  	 when alu_lsl16 | alu_asl8 | alu_rol8 =>
+	   out_alu   <= left(14 downto 0) & carry_in; 	-- rol8/asl8/lsl16
+  	 when alu_lsr16 =>
+	   out_alu   <= carry_in & left(15 downto 1); 	-- lsr16
+  	 when alu_lsr8 | alu_asr8 | alu_ror8 =>
+	   out_alu   <= "00000000" & carry_in & left(7 downto 1); 	-- ror8/asr8/lsr8
+  	 when alu_neg =>
+	   out_alu   <= right - left; 	-- neg (right=0)
+  	 when alu_com =>
+	   out_alu   <= not left;
+  	 when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
+	   out_alu   <= right; 	         -- clr, ld
+	 when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
+	   out_alu   <= left;
+	 when alu_daa =>
+	   out_alu   <= left + ("00000000" & daa_reg);
+	 when alu_sex =>
+	   if left(7) = '0' then
+	      out_alu <= "00000000" & left(7 downto 0);
+		else
+		   out_alu <= "11111111" & left(7 downto 0);
+		end if;
+  	 when others =>
+	   out_alu   <= left; -- nop
+    end case;
+
+	 --
+	 -- carry bit
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_adc  =>
+      cc_out(CBIT) <= (left(7) and right(7)) or
+		                (left(7) and not out_alu(7)) or
+						   (right(7) and not out_alu(7));
+  	 when alu_sub8 | alu_sbc =>
+      cc_out(CBIT) <= ((not left(7)) and right(7)) or
+		                ((not left(7)) and out_alu(7)) or
+						         (right(7) and out_alu(7));
+  	 when alu_add16  =>
+      cc_out(CBIT) <= (left(15) and right(15)) or
+		                (left(15) and not out_alu(15)) or
+						   (right(15) and not out_alu(15));
+  	 when alu_sub16 =>
+      cc_out(CBIT) <= ((not left(15)) and right(15)) or
+		                ((not left(15)) and out_alu(15)) or
+						         (right(15) and out_alu(15));
+	 when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
+	   cc_out(CBIT) <= left(0);
+	 when alu_rol8 | alu_asl8 =>
+	   cc_out(CBIT) <= left(7);
+	 when alu_lsl16 =>
+	   cc_out(CBIT) <= left(15);
+	 when alu_com =>
+	   cc_out(CBIT) <= '1';
+	 when alu_neg | alu_clr =>
+	   cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
+		                out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
+    when alu_mul =>
+		cc_out(CBIT) <= out_alu(7);
+    when alu_daa =>
+	   if ( daa_reg(7 downto 4) = "0110" ) then
+		  cc_out(CBIT) <= '1';
+		else
+		  cc_out(CBIT) <= '0';
+	   end if;
+  	 when alu_andcc =>
+      cc_out(CBIT) <= left(CBIT) and cc(CBIT);
+  	 when alu_orcc =>
+      cc_out(CBIT) <= left(CBIT) or cc(CBIT);
+  	 when alu_tfr =>
+      cc_out(CBIT) <= left(CBIT);
+  	 when others =>
+      cc_out(CBIT) <= cc(CBIT);
+    end case;
+	 --
+	 -- Zero flag
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_sub8 |
+	      alu_adc | alu_sbc |
+  	      alu_and | alu_ora | alu_eor |
+  	      alu_inc | alu_dec | 
+			alu_neg | alu_com | alu_clr |
+			alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
+		   alu_ld8  | alu_st8 | alu_sex | alu_daa =>
+      cc_out(ZBIT) <= not( out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
+	                        out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
+  	 when alu_add16 | alu_sub16 | alu_mul |
+  	      alu_lsl16 | alu_lsr16 |
+		   alu_ld16  | alu_st16 | alu_lea =>
+      cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
+	                        out_alu(11) or out_alu(10) or out_alu(9)  or out_alu(8)  or
+  	                        out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
+	                        out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
+  	 when alu_andcc =>
+      cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
+  	 when alu_orcc =>
+      cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
+  	 when alu_tfr =>
+      cc_out(ZBIT) <= left(ZBIT);
+  	 when others =>
+      cc_out(ZBIT) <= cc(ZBIT);
+    end case;
+
+    --
+	 -- negative flag
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_sub8 |
+	      alu_adc | alu_sbc |
+	      alu_and | alu_ora | alu_eor |
+  	      alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
+  	      alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
+			alu_ld8  | alu_st8 | alu_sex | alu_daa =>
+      cc_out(NBIT) <= out_alu(7);
+	 when alu_add16 | alu_sub16 |
+	      alu_lsl16 | alu_lsr16 |
+			alu_ld16 | alu_st16 =>
+		cc_out(NBIT) <= out_alu(15);
+  	 when alu_andcc =>
+      cc_out(NBIT) <= left(NBIT) and cc(NBIT);
+  	 when alu_orcc =>
+      cc_out(NBIT) <= left(NBIT) or cc(NBIT);
+  	 when alu_tfr =>
+      cc_out(NBIT) <= left(NBIT);
+  	 when others =>
+      cc_out(NBIT) <= cc(NBIT);
+    end case;
+
+    --
+	 -- Interrupt mask flag
+    --
+    case alu_ctrl is
+  	 when alu_andcc =>
+      cc_out(IBIT) <= left(IBIT) and cc(IBIT);
+  	 when alu_orcc =>
+      cc_out(IBIT) <= left(IBIT) or cc(IBIT);
+  	 when alu_tfr =>
+      cc_out(IBIT) <= left(IBIT);
+    when alu_seif | alu_sei =>
+	   cc_out(IBIT) <= '1';
+  	 when others =>
+		cc_out(IBIT) <= cc(IBIT);             -- interrupt mask
+    end case;
+
+    --
+    -- Half Carry flag
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_adc =>
+      cc_out(HBIT) <= (left(3) and right(3)) or
+                     (right(3) and not out_alu(3)) or 
+                      (left(3) and not out_alu(3));
+  	 when alu_andcc =>
+      cc_out(HBIT) <= left(HBIT) and cc(HBIT);
+  	 when alu_orcc =>
+      cc_out(HBIT) <= left(HBIT) or cc(HBIT);
+  	 when alu_tfr =>
+      cc_out(HBIT) <= left(HBIT);
+  	 when others =>
+		cc_out(HBIT) <= cc(HBIT);
+    end case;
+
+    --
+    -- Overflow flag
+	 --
+    case alu_ctrl is
+  	 when alu_add8 | alu_adc =>
+      cc_out(VBIT) <= (left(7)  and      right(7)  and (not out_alu(7))) or
+                 ((not left(7)) and (not right(7)) and      out_alu(7));
+	 when alu_sub8 | alu_sbc =>
+      cc_out(VBIT) <= (left(7)  and (not right(7)) and (not out_alu(7))) or
+                 ((not left(7)) and      right(7)  and      out_alu(7));
+  	 when alu_add16 =>
+      cc_out(VBIT) <= (left(15)  and      right(15)  and (not out_alu(15))) or
+                 ((not left(15)) and (not right(15)) and      out_alu(15));
+	 when alu_sub16 =>
+      cc_out(VBIT) <= (left(15)  and (not right(15)) and (not out_alu(15))) or
+                 ((not left(15)) and      right(15) and       out_alu(15));
+	 when alu_inc =>
+	   cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
+		                      left(3)  and left(2) and left(1) and left(0));
+	 when alu_dec | alu_neg =>
+	   cc_out(VBIT) <= (left(7)  and (not left(6)) and (not left(5)) and (not left(4)) and
+		            (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
+-- 6809 Programming reference manual says
+-- V not affected by ASR, LSR and ROR
+-- This is different to the 6800
+-- John Kent 6th June 2006
+--	 when alu_asr8 =>
+--	   cc_out(VBIT) <= left(0) xor left(7);
+--	 when alu_lsr8 | alu_lsr16 =>
+--	   cc_out(VBIT) <= left(0);
+--	 when alu_ror8 =>
+--      cc_out(VBIT) <= left(0) xor cc(CBIT);
+    when alu_lsl16 =>
+      cc_out(VBIT) <= left(15) xor left(14);
+	 when alu_rol8 | alu_asl8 =>
+      cc_out(VBIT) <= left(7) xor left(6);
+--
+-- 11th July 2006 - John Kent
+-- What DAA does with V is anyones guess
+-- It is undefined in the 6809 programming manual
+--
+	 when alu_daa =>
+      cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
+-- CLR resets V Bit
+-- John Kent 6th June 2006
+	 when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
+	      alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
+      cc_out(VBIT) <= '0';
+  	 when alu_andcc =>
+      cc_out(VBIT) <= left(VBIT) and cc(VBIT);
+  	 when alu_orcc =>
+      cc_out(VBIT) <= left(VBIT) or cc(VBIT);
+  	 when alu_tfr =>
+      cc_out(VBIT) <= left(VBIT);
+  	 when others =>
+		cc_out(VBIT) <= cc(VBIT);
+    end case;
+
+	 case alu_ctrl is
+  	 when alu_andcc =>
+      cc_out(FBIT) <= left(FBIT) and cc(FBIT);
+  	 when alu_orcc =>
+      cc_out(FBIT) <= left(FBIT) or cc(FBIT);
+  	 when alu_tfr =>
+      cc_out(FBIT) <= left(FBIT);
+    when alu_seif =>
+	   cc_out(FBIT) <= '1';
+	 when others =>
+      cc_out(FBIT) <= cc(FBIT);
+	 end case;
+
+	 case alu_ctrl is
+  	 when alu_andcc =>
+      cc_out(EBIT) <= left(EBIT) and cc(EBIT);
+  	 when alu_orcc =>
+      cc_out(EBIT) <= left(EBIT) or cc(EBIT);
+  	 when alu_tfr =>
+      cc_out(EBIT) <= left(EBIT);
+    when alu_see =>
+	   cc_out(EBIT) <= '1';
+    when alu_cle =>
+	   cc_out(EBIT) <= '0';
+	 when others =>
+	   cc_out(EBIT) <= cc(EBIT);
+	 end case;
+end process;
+
+------------------------------------
+--
+-- state sequencer
+--
+------------------------------------
+process( state, saved_state, 
+         op_code, pre_code, 
+			cc, ea, md, iv,
+			irq, firq, nmi_req, nmi_ack, halt )
+variable cond_true : boolean;  -- variable used to evaluate coditional branches
+begin
+        -- Registers preserved
+        cc_ctrl    <= latch_cc;
+        acca_ctrl  <= latch_acca;
+        accb_ctrl  <= latch_accb;
+        dp_ctrl    <= latch_dp;
+        ix_ctrl    <= latch_ix;
+        iy_ctrl    <= latch_iy;
+        up_ctrl    <= latch_up;
+        sp_ctrl    <= latch_sp;
+        pc_ctrl    <= latch_pc;
+        md_ctrl    <= latch_md;
+        ea_ctrl    <= latch_ea;
+        iv_ctrl    <= latch_iv;
+        op_ctrl    <= latch_op;
+        pre_ctrl   <= latch_pre;
+        nmi_ctrl   <= latch_nmi;
+		  -- ALU Idle
+        left_ctrl  <= pc_left;
+        right_ctrl <= zero_right;
+        alu_ctrl   <= alu_nop;
+		  -- Bus idle
+        addr_ctrl  <= idle_ad;
+        dout_ctrl  <= cc_dout;
+		  -- Next State Fetch
+        st_ctrl      <= idle_st;
+        return_state <= fetch_state;
+        next_state   <= fetch_state;
+
+		    case state is
+          when reset_state =>        --  released from reset
+			    -- reset the registers
+             op_ctrl    <= reset_op;
+             pre_ctrl   <= reset_pre;
+             cc_ctrl    <= reset_cc;
+				 acca_ctrl  <= reset_acca;
+				 accb_ctrl  <= reset_accb;
+             dp_ctrl    <= reset_dp;
+				 ix_ctrl    <= reset_ix;
+				 iy_ctrl    <= reset_iy;
+		       up_ctrl    <= reset_up;
+		       sp_ctrl    <= reset_sp;
+		       pc_ctrl    <= reset_pc;
+	 		    ea_ctrl    <= reset_ea;
+				 md_ctrl    <= reset_md;
+				 iv_ctrl    <= reset_iv;
+				 nmi_ctrl   <= reset_nmi;
+	 	       next_state <= vect_hi_state;
+
+			 --
+			 -- Jump via interrupt vector
+			 -- iv holds interrupt type
+			 -- fetch PC hi from vector location
+			 --
+          when vect_hi_state =>
+				 -- fetch pc low interrupt vector
+		       pc_ctrl    <= pull_hi_pc;
+             addr_ctrl  <= int_hi_ad;
+	 	       next_state <= vect_lo_state;
+			 --
+			 -- jump via interrupt vector
+			 -- iv holds vector type
+			 -- fetch PC lo from vector location
+			 --
+          when vect_lo_state =>
+				 -- fetch the vector low byte
+		       pc_ctrl    <= pull_lo_pc;
+             addr_ctrl  <= int_lo_ad;
+	 	       next_state <= fetch_state;
+			 --
+			 -- Here to fetch an instruction
+			 -- PC points to opcode
+			 -- Should service interrupt requests at this point
+			 -- either from the timer
+			 -- or from the external input.
+			 --
+          when fetch_state =>
+				   -- fetch the op code
+			      op_ctrl    <= fetch_op;
+               pre_ctrl   <= fetch_pre;
+               ea_ctrl    <= reset_ea;
+				   -- Fetch op code
+               addr_ctrl  <= fetch_ad;
+				   --
+					case op_code(7 downto 6) is
+					when "10" => -- acca
+				     case op_code(3 downto 0) is
+					  when "0000" => -- suba
+					    left_ctrl  <= acca_left;
+					    right_ctrl <= md_right;
+					    alu_ctrl   <= alu_sub8;
+						 cc_ctrl    <= load_cc;
+					    acca_ctrl  <= load_acca;
+					  when "0001" => -- cmpa
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sub8;
+						 cc_ctrl     <= load_cc;
+					  when "0010" => -- sbca
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sbc;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+					  when "0011" =>
+					    case pre_code is
+						 when "00010000" => -- page 2 -- cmpd
+					      left_ctrl   <= accd_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_sub16;
+						   cc_ctrl     <= load_cc;
+						 when "00010001" => -- page 3 -- cmpu
+					      left_ctrl   <= up_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_sub16;
+						   cc_ctrl     <= load_cc;
+						 when others => -- page 1 -- subd
+					      left_ctrl   <= accd_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_sub16;
+						   cc_ctrl     <= load_cc;
+					      acca_ctrl   <= load_hi_acca;
+						   accb_ctrl   <= load_accb;
+						 end case;
+					  when "0100" => -- anda
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_and;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+					  when "0101" => -- bita
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_and;
+						 cc_ctrl     <= load_cc;
+					  when "0110" => -- ldaa
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ld8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+					  when "0111" => -- staa
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_st8;
+						 cc_ctrl     <= load_cc;
+					  when "1000" => -- eora
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_eor;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+					  when "1001" => -- adca
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_adc;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+					  when "1010" => -- oraa
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ora;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+					  when "1011" => -- adda
+					    left_ctrl   <= acca_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_add8;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_acca;
+					  when "1100" =>
+					    case pre_code is
+						 when "00010000" => -- page 2 -- cmpy
+					      left_ctrl   <= iy_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_sub16;
+						   cc_ctrl     <= load_cc;
+						 when "00010001" => -- page 3 -- cmps
+					      left_ctrl   <= sp_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_sub16;
+						   cc_ctrl     <= load_cc;
+						 when others => -- page 1 -- cmpx
+					      left_ctrl   <= ix_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_sub16;
+						   cc_ctrl     <= load_cc;
+						 end case;
+					  when "1101" => -- bsr / jsr
+					    null;
+					  when "1110" => -- ldx
+					    case pre_code is
+						 when "00010000" => -- page 2 -- ldy
+					      left_ctrl   <= iy_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_ld16;
+						   cc_ctrl     <= load_cc;
+                     iy_ctrl     <= load_iy;
+						 when others =>   -- page 1 -- ldx
+					      left_ctrl   <= ix_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_ld16;
+						   cc_ctrl     <= load_cc;
+                     ix_ctrl     <= load_ix;
+						 end case;
+					  when "1111" => -- stx
+					    case pre_code is
+						 when "00010000" => -- page 2 -- sty
+					      left_ctrl   <= iy_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_st16;
+						   cc_ctrl     <= load_cc;
+						 when others =>     -- page 1 -- stx
+					      left_ctrl   <= ix_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_st16;
+						   cc_ctrl     <= load_cc;
+						 end case;
+					  when others =>
+					    null;
+					  end case;
+					when "11" => -- accb dual op
+				     case op_code(3 downto 0) is
+					  when "0000" => -- subb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sub8;
+						 cc_ctrl     <= load_cc;
+                   accb_ctrl   <= load_accb;
+					  when "0001" => -- cmpb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sub8;
+						 cc_ctrl     <= load_cc;
+					  when "0010" => -- sbcb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_sbc;
+						 cc_ctrl     <= load_cc;
+                   accb_ctrl   <= load_accb;
+					  when "0011" => -- addd
+					    left_ctrl   <= accd_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_add16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_hi_acca;
+						 accb_ctrl   <= load_accb;
+					  when "0100" => -- andb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_and;
+						 cc_ctrl     <= load_cc;
+                   accb_ctrl   <= load_accb;
+					  when "0101" => -- bitb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_and;
+						 cc_ctrl     <= load_cc;
+					  when "0110" => -- ldab
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ld8;
+						 cc_ctrl     <= load_cc;
+                   accb_ctrl   <= load_accb;
+					  when "0111" => -- stab
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_st8;
+						 cc_ctrl     <= load_cc;
+					  when "1000" => -- eorb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_eor;
+						 cc_ctrl     <= load_cc;
+                   accb_ctrl   <= load_accb;
+					  when "1001" => -- adcb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_adc;
+						 cc_ctrl     <= load_cc;
+                   accb_ctrl   <= load_accb;
+					  when "1010" => -- orab
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ora;
+						 cc_ctrl     <= load_cc;
+                   accb_ctrl   <= load_accb;
+					  when "1011" => -- addb
+					    left_ctrl   <= accb_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_add8;
+						 cc_ctrl     <= load_cc;
+                   accb_ctrl   <= load_accb;
+					  when "1100" => -- ldd
+					    left_ctrl   <= accd_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_ld16;
+						 cc_ctrl     <= load_cc;
+					    acca_ctrl   <= load_hi_acca;
+                   accb_ctrl   <= load_accb;
+					  when "1101" => -- std
+					    left_ctrl   <= accd_left;
+					    right_ctrl  <= md_right;
+					    alu_ctrl    <= alu_st16;
+						 cc_ctrl     <= load_cc;
+					  when "1110" => -- ldu
+					    case pre_code is
+						 when "00010000" => -- page 2 -- lds
+					      left_ctrl   <= sp_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_ld16;
+						   cc_ctrl     <= load_cc;
+						   sp_ctrl     <= load_sp;
+						 when others => -- page 1 -- ldu
+					      left_ctrl   <= up_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_ld16;
+						   cc_ctrl     <= load_cc;
+                     up_ctrl     <= load_up;
+						 end case;
+					  when "1111" =>
+					    case pre_code is
+						 when "00010000" => -- page 2 -- sts
+					      left_ctrl   <= sp_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_st16;
+						   cc_ctrl     <= load_cc;
+						 when others =>     -- page 1 -- stu
+					      left_ctrl   <= up_left;
+					      right_ctrl  <= md_right;
+					      alu_ctrl    <= alu_st16;
+						   cc_ctrl     <= load_cc;
+						 end case;
+					  when others =>
+					    null;
+					  end case;
+					when others =>
+					  null;
+					end case;
+				 if halt = '1' then
+		  	      iv_ctrl    <= reset_iv;
+			      next_state <= halt_state;
+				 -- service non maskable interrupts
+			    elsif (nmi_req = '1') and (nmi_ack = '0') then
+		  	      iv_ctrl    <= nmi_iv;
+				   nmi_ctrl   <= set_nmi;
+			      next_state <= int_nmiirq_state;
+				 -- service maskable interrupts
+			    else
+				   --
+					-- nmi request is not cleared until nmi input goes low
+					--
+				   if(nmi_req = '0') and (nmi_ack='1') then
+				     nmi_ctrl <= reset_nmi;
+					end if;
+					--
+					-- FIRQ & IRQ are level sensitive
+					--
+               if (firq = '1') and (cc(FBIT) = '0') then
+		  	        iv_ctrl    <= firq_iv;
+			        next_state <= int_firq_state;
+				   elsif (irq = '1') and (cc(IBIT) = '0') then
+		  	        iv_ctrl    <= irq_iv;
+			        next_state <= int_nmiirq_state;
+               else
+				     -- Advance the PC to fetch next instruction byte
+		  	        iv_ctrl    <= reset_iv; -- default to reset
+                 pc_ctrl    <= incr_pc;
+			        next_state <= decode1_state;
+               end if;
+				 end if;
+			  --
+			  -- Here to decode instruction
+			  -- and fetch next byte of intruction
+			  -- whether it be necessary or not
+			  --
+           when decode1_state =>
+				 -- fetch first byte of address or immediate data
+             ea_ctrl    <= fetch_first_ea;
+				 md_ctrl    <= fetch_first_md;
+             addr_ctrl  <= fetch_ad;
+			    case op_code(7 downto 4) is
+				 --
+				 -- direct single op (2 bytes)
+				 -- 6809 => 6 cycles
+				 -- cpu09 => 5 cycles
+			    -- 1 op=(pc) / pc=pc+1
+				 -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
+				 -- 3 md_lo=(ea) / pc=pc
+				 -- 4 alu_left=md / md=alu_out / pc=pc
+				 -- 5 (ea)=md_lo / pc=pc
+				 --
+				 -- Exception is JMP
+			    -- 6809 => 3 cycles
+				 -- cpu09 => 3 cycles
+				 -- 1 op=(pc) / pc=pc+1
+				 -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
+				 -- 3 pc=ea
+				 --
+	          when "0000" => 
+					-- advance the PC
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+ 				   when "1110" => -- jmp
+				     next_state <= jmp_state;
+					when "1111" => -- clr
+				     next_state <= single_op_exec_state;
+					when others =>
+				     next_state <= single_op_read_state;
+					end case;
+
+				 -- acca / accb inherent instructions
+	          when "0001" =>
+	            case op_code(3 downto 0) is
+					--
+					-- Page2 pre byte
+					-- pre=(pc) / pc=pc+1
+					-- op=(pc) / pc=pc+1
+					--
+		         when "0000" => -- page2
+			        op_ctrl    <= fetch_op;
+					  -- advance pc
+                 pc_ctrl    <= incr_pc;
+					  next_state <= decode2_state;
+
+					--
+					-- Page3 pre byte
+					-- pre=(pc) / pc=pc+1
+					-- op=(pc) / pc=pc+1
+					--
+		         when "0001" => -- page3
+			        op_ctrl    <= fetch_op;
+					  -- advance pc
+                 pc_ctrl    <= incr_pc;
+					  next_state <= decode3_state;
+
+					--
+					-- nop - No operation ( 1 byte )
+					-- 6809 => 2 cycles
+					-- cpu09 => 2 cycles
+					-- 1 op=(pc) / pc=pc+1
+					-- 2 decode
+					-- 
+		         when "0010" => -- nop
+					  next_state   <= fetch_state;
+
+					--
+					-- sync - halt execution until an interrupt is received
+					-- interrupt may be NMI, IRQ or FIRQ
+					-- program execution continues if the 
+					-- interrupt is asserted for 3 clock cycles
+					-- note that registers are not pushed onto the stack
+					-- CPU09 => Interrupts need only be asserted for one clock cycle
+					--
+		         when "0011" => -- sync
+					  next_state   <= sync_state;
+
+					--
+					-- lbra -- long branch (3 bytes)
+					-- 6809 => 5 cycles
+					-- cpu09 => 4 cycles
+					-- 1 op=(pc) / pc=pc+1
+					-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
+					-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
+					-- 4 pc=pc+md
+					--
+		         when "0110" =>
+					  -- increment the pc
+                 pc_ctrl    <= incr_pc;
+					  next_state <= lbranch_state;
+
+					--
+					-- lbsr - long branch to subroutine (3 bytes)
+					-- 6809 => 9 cycles
+					-- cpu09 => 6 cycles
+					-- 1 op=(pc) /pc=pc+1
+					-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
+					-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
+					-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
+					-- 5 (sp)=pc_hi / pc=pc
+					-- 6 pc=pc+md
+					--
+		         when "0111" =>
+					  -- pre decrement sp
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= one_right;
+                 alu_ctrl   <= alu_sub16;
+                 sp_ctrl    <= load_sp;
+					  -- increment the pc
+                 pc_ctrl    <= incr_pc;
+					  next_state <= lbranch_state;
+
+		         when "1001" => -- daa
+					  left_ctrl  <= acca_left;
+	              right_ctrl <= accb_right;
+					  alu_ctrl   <= alu_daa;
+                 cc_ctrl    <= load_cc;
+					  acca_ctrl  <= load_acca;
+					  next_state <= fetch_state;
+
+		         when "1010" => -- orcc
+					  -- increment the pc
+                 pc_ctrl      <= incr_pc;
+				     st_ctrl      <= push_st;
+				     return_state <= fetch_state;
+					  next_state   <= orcc_state;
+
+		         when "1100" => -- andcc
+					  -- increment the pc
+                 pc_ctrl      <= incr_pc;
+				     st_ctrl      <= push_st;
+				     return_state <= fetch_state;
+					  next_state   <= andcc_state;
+
+		         when "1101" => -- sex
+					  -- have sex
+                 left_ctrl  <= accb_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_sex;
+					  cc_ctrl    <= load_cc;
+					  acca_ctrl  <= load_hi_acca;
+					  next_state <= fetch_state;
+
+		         when "1110" => -- exg
+					  -- increment the pc
+                 pc_ctrl    <= incr_pc;
+					  next_state <= exg_state;
+
+		         when "1111" => -- tfr
+					  -- increment the pc
+                 pc_ctrl      <= incr_pc;
+					  -- call transfer as a subroutine
+				     st_ctrl      <= push_st;
+				     return_state <= fetch_state;
+					  next_state   <= tfr_state;
+
+		         when others =>
+					  -- increment the pc
+                 pc_ctrl    <= incr_pc;
+					  next_state <= fetch_state;
+		         end case;
+             --
+				 -- Short branch conditional
+				 -- 6809 => always 3 cycles
+				 -- cpu09 => always = 3 cycles
+				 -- 1 op=(pc) / pc=pc+1
+				 -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
+				 -- 3 if cc tru pc=pc+md else pc=pc
+				 --
+	          when "0010" => -- branch conditional
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+               next_state <= sbranch_state;
+				 --
+				 -- Single byte stack operators
+				 -- Do not advance PC
+				 --
+	          when "0011" =>
+					--
+					-- lea - load effective address (2+ bytes)
+					-- 6809 => 4 cycles + addressing mode
+					-- cpu09 => 4 cycles + addressing mode
+					-- 1 op=(pc) / pc=pc+1
+					-- 2 md_lo=(pc) / pc=pc+1
+					-- 3 calculate ea
+					-- 4 ix/iy/sp/up = ea
+					--
+	            case op_code(3 downto 0) is
+		         when "0000" |  -- leax
+		              "0001" |  -- leay
+		              "0010" |  -- leas
+		              "0011" => -- leau
+						-- advance PC
+                  pc_ctrl      <= incr_pc;
+				      st_ctrl      <= push_st;
+				      return_state <= lea_state;
+						next_state   <= indexed_state;
+
+					--
+					-- pshs - push registers onto sp stack
+					-- 6809 => 5 cycles + registers
+					-- cpu09 => 3 cycles + registers
+					--  1 op=(pc) / pc=pc+1
+					--  2 ea_lo=(pc) / pc=pc+1 
+					--  3 if ea(7 downto 0) != "00000000" then sp=sp-1
+					--  4 if ea(7) = 1 (sp)=pcl, sp=sp-1
+					--  5 if ea(7) = 1 (sp)=pch
+					--    if ea(6 downto 0) != "0000000" then sp=sp-1
+					--  6 if ea(6) = 1 (sp)=upl, sp=sp-1
+					--  7 if ea(6) = 1 (sp)=uph
+					--    if ea(5 downto 0) != "000000" then sp=sp-1
+					--  8 if ea(5) = 1 (sp)=iyl, sp=sp-1
+					--  9 if ea(5) = 1 (sp)=iyh
+					--    if ea(4 downto 0) != "00000" then sp=sp-1
+					-- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
+					-- 11 if ea(4) = 1 (sp)=ixh
+					--    if ea(3 downto 0) != "0000" then sp=sp-1
+					-- 12 if ea(3) = 1 (sp)=dp
+					--    if ea(2 downto 0) != "000" then sp=sp-1
+					-- 13 if ea(2) = 1 (sp)=accb
+					--    if ea(1 downto 0) != "00" then sp=sp-1
+					-- 14 if ea(1) = 1 (sp)=acca
+					--    if ea(0 downto 0) != "0" then sp=sp-1
+					-- 15 if ea(0) = 1 (sp)=cc
+					--
+		         when "0100" => -- pshs
+						-- advance PC
+                  pc_ctrl    <= incr_pc;
+						next_state <= pshs_state;
+
+					--
+					-- puls - pull registers of sp stack
+					-- 6809 => 5 cycles + registers
+					-- cpu09 => 3 cycles + registers
+					--
+		         when "0101" => -- puls
+						-- advance PC
+                  pc_ctrl    <= incr_pc;
+						next_state <= puls_state;
+
+					--
+					-- pshu - push registers onto up stack
+					-- 6809 => 5 cycles + registers
+					-- cpu09 => 3 cycles + registers
+					--
+		         when "0110" => -- pshu
+						-- advance PC
+                  pc_ctrl    <= incr_pc;
+						next_state <= pshu_state;
+
+					--
+					-- pulu - pull registers of up stack
+					-- 6809 => 5 cycles + registers
+					-- cpu09 => 3 cycles + registers
+					--
+		         when "0111" => -- pulu
+						-- advance PC
+                  pc_ctrl    <= incr_pc;
+						next_state <= pulu_state;
+
+					--
+					-- rts - return from subroutine
+					-- 6809 => 5 cycles
+					-- cpu09 => 4 cycles 
+					-- 1 op=(pc) / pc=pc+1
+					-- 2 decode op
+					-- 3 pc_hi = (sp) / sp=sp+1
+					-- 4 pc_lo = (sp) / sp=sp+1
+					--
+		         when "1001" =>
+				      st_ctrl      <= push_st;
+				      return_state <= fetch_state;
+						next_state   <= pull_return_hi_state;
+
+					--
+					-- add accb to index register
+					-- *** Note: this is an unsigned addition.
+					--           does not affect any condition codes
+					-- 6809 => 3 cycles
+					-- cpu09 => 2 cycles
+					-- 1 op=(pc) / pc=pc+1
+					-- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
+					--
+		         when "1010" => -- abx
+		            left_ctrl  <= ix_left;
+		            right_ctrl <= accb_right;
+						alu_ctrl   <= alu_abx;
+						ix_ctrl    <= load_ix;
+						next_state <= fetch_state;
+
+		         when "1011" => -- rti
+						next_state <= rti_cc_state;
+
+		         when "1100" => -- cwai #$<cc_mask>
+					   -- pre decrement sp
+		            left_ctrl    <= sp_left;
+		            right_ctrl   <= one_right;
+						alu_ctrl     <= alu_sub16;
+						sp_ctrl      <= load_sp;
+                  iv_ctrl      <= reset_iv;
+						--	increment pc
+                  pc_ctrl      <= incr_pc;
+				      st_ctrl      <= push_st;
+				      return_state <= int_entire_state; -- set entire flag
+						next_state   <= andcc_state;
+
+		         when "1101" => -- mul
+						next_state <= mul_state;
+
+		         when "1111" => -- swi
+					   -- predecrement SP
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= one_right;
+						alu_ctrl   <= alu_sub16;
+						sp_ctrl    <= load_sp;
+                  iv_ctrl    <= swi_iv;
+						next_state <= int_entire_state;
+
+		         when others =>
+						next_state <= fetch_state;
+
+		         end case;
+				 --
+				 -- Accumulator A Single operand
+				 -- source = acca, dest = acca
+				 -- Do not advance PC
+				 -- Typically 2 cycles 1 bytes
+				 -- 1 opcode fetch
+				 -- 2 post byte fetch / instruction decode
+				 -- Note that there is no post byte
+				 -- so do not advance PC in decode cycle
+				 -- Re-run opcode fetch cycle after decode
+				 -- 
+	          when "0100" => -- acca single op
+		         left_ctrl  <= acca_left;
+	            case op_code(3 downto 0) is
+		         when "0000" => -- neg
+					  right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_neg;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+ 	            when "0011" => -- com
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_com;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "0100" => -- lsr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_lsr8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "0110" => -- ror
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_ror8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "0111" => -- asr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_asr8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1000" => -- asl
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_asl8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1001" => -- rol
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_rol8;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1010" => -- dec
+		           right_ctrl <= one_right;
+					  alu_ctrl   <= alu_dec;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1011" => -- undefined
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  acca_ctrl  <= latch_acca;
+					  cc_ctrl    <= latch_cc;
+		         when "1100" => -- inc
+		           right_ctrl <= one_right;
+					  alu_ctrl   <= alu_inc;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1101" => -- tst
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_st8;
+					  acca_ctrl  <= latch_acca;
+					  cc_ctrl    <= load_cc;
+		         when "1110" => -- jmp (not defined)
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  acca_ctrl  <= latch_acca;
+					  cc_ctrl    <= latch_cc;
+		         when "1111" => -- clr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_clr;
+					  acca_ctrl  <= load_acca;
+					  cc_ctrl    <= load_cc;
+		         when others =>
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  acca_ctrl  <= latch_acca;
+					  cc_ctrl    <= latch_cc;
+		         end case;
+				   next_state <= fetch_state;
+				 --
+				 -- Single Operand accb
+				 -- source = accb, dest = accb
+				 -- Typically 2 cycles 1 bytes
+				 -- 1 opcode fetch
+				 -- 2 post byte fetch / instruction decode
+				 -- Note that there is no post byte
+				 -- so do not advance PC in decode cycle
+				 -- Re-run opcode fetch cycle after decode
+				 --
+	          when "0101" =>
+		         left_ctrl  <= accb_left;
+	            case op_code(3 downto 0) is
+		         when "0000" => -- neg
+					  right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_neg;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+ 	            when "0011" => -- com
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_com;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "0100" => -- lsr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_lsr8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "0110" => -- ror
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_ror8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "0111" => -- asr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_asr8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1000" => -- asl
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_asl8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1001" => -- rol
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_rol8;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1010" => -- dec
+		           right_ctrl <= one_right;
+					  alu_ctrl   <= alu_dec;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1011" => -- undefined
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  accb_ctrl  <= latch_accb;
+					  cc_ctrl    <= latch_cc;
+		         when "1100" => -- inc
+		           right_ctrl <= one_right;
+					  alu_ctrl   <= alu_inc;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1101" => -- tst
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_st8;
+					  accb_ctrl  <= latch_accb;
+					  cc_ctrl    <= load_cc;
+		         when "1110" => -- jmp (undefined)
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  accb_ctrl  <= latch_accb;
+					  cc_ctrl    <= latch_cc;
+		         when "1111" => -- clr
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_clr;
+					  accb_ctrl  <= load_accb;
+					  cc_ctrl    <= load_cc;
+		         when others =>
+		           right_ctrl <= zero_right;
+					  alu_ctrl   <= alu_nop;
+					  accb_ctrl  <= latch_accb;
+					  cc_ctrl    <= latch_cc;
+		         end case;
+				   next_state   <= fetch_state;
+				 --
+				 -- Single operand indexed
+				 -- Two byte instruction so advance PC
+				 -- EA should hold index offset
+				 --
+	          when "0110" => -- indexed single op
+					-- increment the pc 
+               pc_ctrl    <= incr_pc;
+				   st_ctrl    <= push_st;
+					case op_code(3 downto 0) is
+ 				   when "1110" => -- jmp
+				     return_state <= jmp_state;
+					when "1111" => -- clr
+				     return_state <= single_op_exec_state;
+					when others =>
+				     return_state <= single_op_read_state;
+					end case;
+				   next_state <= indexed_state;
+             --
+				 -- Single operand extended addressing
+				 -- three byte instruction so advance the PC
+				 -- Low order EA holds high order address
+				 --
+	          when "0111" => -- extended single op
+					-- increment PC
+               pc_ctrl    <= incr_pc;
+				   st_ctrl    <= push_st;
+					case op_code(3 downto 0) is
+ 				   when "1110" => -- jmp
+				     return_state <= jmp_state;
+					when "1111" => -- clr
+				     return_state <= single_op_exec_state;
+					when others =>
+				     return_state <= single_op_read_state;
+					end case;
+				   next_state <= extended_state;
+
+	          when "1000" => -- acca immediate
+				   -- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- subd #
+					     "1100" | -- cmpx #
+					     "1110" => -- ldx #
+				     st_ctrl      <= push_st;
+				     return_state <= fetch_state;
+					  next_state   <= imm16_state;
+
+					--
+					-- bsr offset - Branch to subroutine (2 bytes)
+					-- 6809 => 7 cycles
+					-- cpu09 => 5 cycles
+					-- 1 op=(pc) / pc=pc+1
+ 				   -- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
+					-- 3 (sp)=pc_lo / sp=sp-1
+					-- 4 (sp)=pc_hi
+					-- 5 pc=pc+md
+					--
+					when "1101" => -- bsr
+					  -- pre decrement SP
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= one_right;
+                 alu_ctrl   <= alu_sub16;
+				     sp_ctrl    <= load_sp;
+					  --
+				     st_ctrl      <= push_st;
+				     return_state <= sbranch_state;
+					  next_state   <= push_return_lo_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+               end case;
+
+	          when "1001" => -- acca direct
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- subd
+					     "1100" | -- cmpx
+					     "1110" => -- ldx
+				     next_state   <= dual_op_read16_state;
+
+					when "0111" =>  -- sta direct
+				     next_state <= dual_op_write8_state;
+
+					when "1111" => -- stx direct
+					  -- idle ALU
+                 left_ctrl  <= ix_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_nop;
+					  cc_ctrl    <= latch_cc;
+				     sp_ctrl    <= latch_sp;
+				     next_state <= dual_op_write16_state;
+
+					--
+					-- jsr direct - Jump to subroutine in direct page (2 bytes)
+					-- 6809 => 7 cycles
+					-- cpu09 => 5 cycles
+					-- 1 op=(pc) / pc=pc+1
+ 				   -- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
+					-- 3 (sp)=pc_lo / sp=sp-1
+					-- 4 (sp)=pc_hi
+					-- 5 pc=ea
+					--
+					when "1101" => -- jsr direct
+					  -- pre decrement sp
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= one_right;
+                 alu_ctrl   <= alu_sub16;
+				     sp_ctrl    <= load_sp;
+					  --
+				     st_ctrl      <= push_st;
+				     return_state <= jmp_state;
+					  next_state   <= push_return_lo_state;
+
+					when others =>
+				     next_state   <= dual_op_read8_state;
+               end case;
+
+	          when "1010" => -- acca indexed
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- subd
+					     "1100" | -- cmpx
+					     "1110" => -- ldx
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+				     next_state   <= indexed_state;
+
+					when "0111" =>  -- staa ,x
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write8_state;
+				     next_state   <= indexed_state;
+
+					when "1111" => -- stx ,x
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= indexed_state;
+
+					when "1101" => -- jsr ,x
+					  -- DO NOT pre decrement SP
+				     st_ctrl      <= push_st;
+				     return_state <= jsr_state;
+					  next_state   <= indexed_state;
+
+					when others =>
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read8_state;
+				     next_state   <= indexed_state;
+               end case;
+
+             when "1011" => -- acca extended
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- subd
+					     "1100" | -- cmpx
+					     "1110" => -- ldx
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+				     next_state   <= extended_state;
+
+					when "0111" =>  -- staa >
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write8_state;
+				     next_state   <= extended_state;
+
+					when "1111" => -- stx >
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= extended_state;
+
+					when "1101" => -- jsr >extended
+					  -- DO NOT pre decrement sp
+				     st_ctrl      <= push_st;
+				     return_state <= jsr_state;
+					  next_state   <= extended_state;
+
+					when others =>
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read8_state;
+				     next_state   <= extended_state;
+               end case;
+
+	          when "1100" => -- accb immediate
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- addd #
+					     "1100" | -- ldd #
+					     "1110" => -- ldu #
+				     st_ctrl      <= push_st;
+				     return_state <= fetch_state;
+					  next_state   <= imm16_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+
+               end case;
+
+
+	          when "1101" => -- accb direct
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- addd
+					     "1100" | -- ldd
+					     "1110" => -- ldu
+				     next_state   <= dual_op_read16_state;
+
+					when "0111" =>  -- stab direct
+				     next_state   <= dual_op_write8_state;
+
+					when "1101" =>  -- std direct
+				     next_state   <= dual_op_write16_state;
+
+					when "1111" => -- stu direct
+				     next_state   <= dual_op_write16_state;
+
+					when others =>
+				     next_state   <= dual_op_read8_state;
+               end case;
+
+	          when "1110" => -- accb indexed
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- addd
+					     "1100" | -- ldd
+					     "1110" => -- ldu
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+				     next_state   <= indexed_state;
+
+					when "0111" =>  -- stab indexed
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write8_state;
+				     next_state   <= indexed_state;
+
+					when "1101" =>  -- std indexed
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= indexed_state;
+
+					when "1111" => -- stu indexed
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= indexed_state;
+
+					when others =>
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read8_state;
+				     next_state   <= indexed_state;
+               end case;
+
+             when "1111" => -- accb extended
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- addd
+					     "1100" | -- ldd
+					     "1110" => -- ldu
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+				     next_state   <= extended_state;
+
+					when "0111" =>  -- stab extended
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write8_state;
+				     next_state   <= extended_state;
+
+					when "1101" =>  -- std extended
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= extended_state;
+
+					when "1111" => -- stu  extended
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= extended_state;
+
+					when others =>
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read8_state;
+				     next_state   <= extended_state;
+               end case;
+
+	          when others =>
+				   null;
+             end case;
+
+			 --
+			 -- Here to decode prefix 2 instruction
+			 -- and fetch next byte of intruction
+			 -- whether it be necessary or not
+			 --
+          when decode2_state =>
+				 -- fetch first byte of address or immediate data
+             ea_ctrl    <= fetch_first_ea;
+				 md_ctrl    <= fetch_first_md;
+             addr_ctrl  <= fetch_ad;
+			    case op_code(7 downto 4) is
+				 --
+				 -- lbcc -- long branch conditional
+				 -- 6809 => branch 6 cycles, no branch 5 cycles
+				 -- cpu09 => always 5 cycles
+				 -- 1 pre=(pc) / pc=pc+1
+				 -- 2 op=(pc) / pc=pc+1
+				 -- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
+             -- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
+				 -- 5 if cond pc=pc+md else pc=pc
+				 --
+	          when "0010" => 
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					next_state <= lbranch_state;
+
+				 --
+				 -- Single byte stack operators
+				 -- Do not advance PC
+				 --
+	          when "0011" =>
+	            case op_code(3 downto 0) is
+		         when "1111" => -- swi 2
+					   -- predecrement sp
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= one_right;
+						alu_ctrl   <= alu_sub16;
+						sp_ctrl    <= load_sp;
+                  iv_ctrl    <= swi2_iv;
+						next_state <= int_entire_state;
+
+		         when others =>
+						next_state   <= fetch_state;
+		         end case;
+
+	          when "1000" => -- acca immediate
+				   -- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- cmpd #
+					     "1100" | -- cmpy #
+					     "1110" => -- ldy #
+				     st_ctrl      <= push_st;
+				     return_state <= fetch_state;
+					  next_state   <= imm16_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+
+               end case;
+
+	          when "1001" => -- acca direct
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- cmpd <
+					     "1100" | -- cmpy <
+					     "1110" => -- ldy <
+					  next_state   <= dual_op_read16_state;
+
+					when "1111" => -- sty <
+				     next_state   <= dual_op_write16_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+
+               end case;
+
+	          when "1010" => -- acca indexed
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- cmpd ,ind
+					     "1100" | -- cmpy ,ind
+					     "1110" => -- ldy ,ind
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+					  next_state   <= indexed_state;
+
+					when "1111" => -- sty ,ind
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= indexed_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+               end case;
+
+             when "1011" => -- acca extended
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- cmpd <
+					     "1100" | -- cmpy <
+					     "1110" => -- ldy <
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+					  next_state   <= extended_state;
+
+					when "1111" => -- sty >
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= extended_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+
+               end case;
+
+	          when "1100" => -- accb immediate
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- undef #
+					     "1100" | -- undef #
+					     "1110" => -- lds #
+				     st_ctrl      <= push_st;
+				     return_state <= fetch_state;
+					  next_state   <= imm16_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+
+               end case;
+
+	          when "1101" => -- accb direct
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- undef <
+					     "1100" | -- undef <
+					     "1110" => -- lds <
+					  next_state   <= dual_op_read16_state;
+
+					when "1111" => -- sts <
+				     next_state   <= dual_op_write16_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+
+               end case;
+
+	          when "1110" => -- accb indexed
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- undef ,ind
+					     "1100" | -- undef ,ind
+					     "1110" => -- lds ,ind
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+					  next_state   <= indexed_state;
+
+					when "1111" => -- sts ,ind
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= indexed_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+
+               end case;
+
+             when "1111" => -- accb extended
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- undef >
+					     "1100" | -- undef >
+					     "1110" => -- lds >
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+					  next_state   <= extended_state;
+
+					when "1111" => -- sts >
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_write16_state;
+				     next_state   <= extended_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+               end case;
+
+	          when others =>
+ 		         next_state   <= fetch_state;
+             end case;
+			 --
+			 -- Here to decode instruction
+			 -- and fetch next byte of intruction
+			 -- whether it be necessary or not
+			 --
+          when decode3_state =>
+             ea_ctrl    <= fetch_first_ea;
+				 md_ctrl    <= fetch_first_md;
+             addr_ctrl  <= fetch_ad;
+             dout_ctrl  <= md_lo_dout;
+			    case op_code(7 downto 4) is
+				 --
+				 -- Single byte stack operators
+				 -- Do not advance PC
+				 --
+	          when "0011" =>
+	            case op_code(3 downto 0) is
+		         when "1111" => -- swi3
+					   -- predecrement sp
+		            left_ctrl  <= sp_left;
+		            right_ctrl <= one_right;
+						alu_ctrl   <= alu_sub16;
+						sp_ctrl    <= load_sp;
+                  iv_ctrl    <= swi3_iv;
+						next_state <= int_entire_state;
+		         when others =>
+						next_state   <= fetch_state;
+		         end case;
+
+	          when "1000" => -- acca immediate
+				   -- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- cmpu #
+					     "1100" | -- cmps #
+					     "1110" => -- undef #
+				     st_ctrl      <= push_st;
+				     return_state <= fetch_state;
+					  next_state   <= imm16_state;
+					when others =>
+				     next_state   <= fetch_state;
+               end case;
+
+	          when "1001" => -- acca direct
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- cmpu <
+					     "1100" | -- cmps <
+					     "1110" => -- undef <
+				     st_ctrl      <= idle_st;
+				     return_state <= fetch_state;
+					  next_state   <= dual_op_read16_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+
+               end case;
+
+	          when "1010" => -- acca indexed
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- cmpu ,X
+					     "1100" | -- cmps ,X
+					     "1110" => -- undef ,X
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+					  next_state   <= indexed_state;
+
+					when others =>
+				     next_state   <= fetch_state;
+
+               end case;
+
+             when "1011" => -- acca extended
+					-- increment the pc
+               pc_ctrl    <= incr_pc;
+					case op_code(3 downto 0) is
+               when "0011" | -- cmpu >
+					     "1100" | -- cmps >
+					     "1110" => -- undef >
+				     st_ctrl      <= push_st;
+				     return_state <= dual_op_read16_state;
+					  next_state   <= extended_state;
+					when others =>
+				     next_state   <= fetch_state;
+               end case;
+
+	          when others =>
+ 		         next_state   <= fetch_state;
+             end case;
+
+           --
+			  -- here if ea holds low byte
+			  -- Direct
+			  -- Extended
+			  -- Indexed
+			  -- read memory location
+			  --
+			  when single_op_read_state =>
+					-- read memory into md
+				   md_ctrl    <= fetch_first_md;
+               addr_ctrl  <= read_ad;
+					dout_ctrl  <= md_lo_dout;
+					next_state <= single_op_exec_state;
+
+	        when single_op_exec_state =>
+	            case op_code(3 downto 0) is
+		         when "0000" => -- neg
+                   left_ctrl  <= md_left;
+					    right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_neg;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+ 	            when "0011" => -- com
+                   left_ctrl  <= md_left;
+		             right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_com;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+		         when "0100" => -- lsr
+                   left_ctrl  <= md_left;
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_lsr8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+		         when "0110" => -- ror
+                   left_ctrl  <= md_left;
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_ror8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+		         when "0111" => -- asr
+                   left_ctrl  <= md_left;
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_asr8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+		         when "1000" => -- asl
+                   left_ctrl  <= md_left;
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_asl8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+		         when "1001" => -- rol
+                   left_ctrl  <= md_left;
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_rol8;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+		         when "1010" => -- dec
+                   left_ctrl  <= md_left;
+		             right_ctrl <= one_right;
+					    alu_ctrl   <= alu_dec;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+		         when "1011" => -- undefined
+				       next_state <= fetch_state;
+		         when "1100" => -- inc
+                   left_ctrl  <= md_left;
+		             right_ctrl <= one_right;
+					    alu_ctrl   <= alu_inc;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+		         when "1101" => -- tst
+                   left_ctrl  <= md_left;
+		             right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_st8;
+					    cc_ctrl    <= load_cc;
+				       next_state <= fetch_state;
+		         when "1110" => -- jmp
+                   left_ctrl  <= md_left;
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_ld16;
+                   pc_ctrl    <= load_pc;
+				       next_state <= fetch_state;
+		         when "1111" => -- clr
+                   left_ctrl  <= md_left;
+						 right_ctrl <= zero_right;
+					    alu_ctrl   <= alu_clr;
+					    cc_ctrl    <= load_cc;
+				       md_ctrl    <= load_md;
+				       next_state <= single_op_write_state;
+		         when others =>
+				       next_state <= fetch_state;
+		         end case;
+           --
+			  -- single operand 8 bit write
+			  -- Write low 8 bits of ALU output
+			  -- EA holds address
+			  -- MD holds data
+			  --
+			  when single_op_write_state =>
+				 -- write ALU low byte output
+             addr_ctrl  <= write_ad;
+             dout_ctrl  <= md_lo_dout;
+				 next_state <= fetch_state;
+
+           --
+			  -- here if ea holds address of low byte
+			  -- read memory location
+			  --
+			  when dual_op_read8_state =>
+				   -- read first data byte from ea
+				   md_ctrl    <= fetch_first_md;
+               addr_ctrl  <= read_ad;
+					next_state <= fetch_state;
+
+				--
+				-- Here to read a 16 bit value into MD
+				-- pointed to by the EA register
+				-- The first byte is read
+				-- and the EA is incremented
+				--
+			   when dual_op_read16_state =>
+					-- increment the effective address
+               left_ctrl  <= ea_left;
+               right_ctrl <= one_right;
+               alu_ctrl   <= alu_add16;
+               ea_ctrl    <= load_ea;
+					-- read the high byte of the 16 bit data
+				   md_ctrl    <= fetch_first_md;
+               addr_ctrl  <= read_ad;
+					next_state <= dual_op_read16_2_state;
+
+				--
+				-- here to read the second byte
+			   -- pointed to by EA into MD
+				--
+			   when dual_op_read16_2_state =>
+					-- read the low byte of the 16 bit data
+				   md_ctrl    <= fetch_next_md;
+               addr_ctrl  <= read_ad;
+					next_state <= fetch_state;
+
+           --
+			  -- 16 bit Write state
+			  -- EA hold address of memory to write to
+			  -- Advance the effective address in ALU
+			  -- decode op_code to determine which
+			  -- register to write
+			  --
+			  when dual_op_write16_state =>
+				 -- increment the effective address
+				 left_ctrl  <= ea_left;
+				 right_ctrl <= one_right;
+				 alu_ctrl   <= alu_add16;
+			    ea_ctrl    <= load_ea;
+ 				 -- write the ALU hi byte at ea
+             addr_ctrl  <= write_ad;
+				 if op_code(6) = '0' then
+				   case op_code(3 downto 0) is
+			      when "1111" => -- stx / sty
+					  case pre_code is
+					  when "00010000" => -- page 2 -- sty
+	                dout_ctrl  <= iy_hi_dout;
+				     when others =>     -- page 1 -- stx
+                   dout_ctrl  <= ix_hi_dout;
+					  end case;
+				   when others =>
+                 dout_ctrl  <= md_hi_dout;
+				   end case;
+             else
+				   case op_code(3 downto 0) is
+			      when "1101" => -- std
+                 dout_ctrl  <= acca_dout; -- acca is high byte of ACCD
+			      when "1111" => -- stu / sts
+					  case pre_code is
+					  when "00010000" => -- page 2 -- sts
+	                dout_ctrl  <= sp_hi_dout;
+					  when others =>     -- page 1 -- stu
+	                dout_ctrl  <= up_hi_dout;
+					  end case;
+				   when others =>
+                 dout_ctrl  <= md_hi_dout;
+				   end case;
+             end if;
+				 next_state   <= dual_op_write8_state;
+
+           --
+			  -- Dual operand 8 bit write
+           -- Write 8 bit accumulator
+			  -- or low byte of 16 bit register
+			  -- EA holds address
+			  -- decode opcode to determine
+			  -- which register to apply to the bus
+			  -- Also set the condition codes here
+			  --
+			  when dual_op_write8_state =>
+			    if op_code(6) = '0' then
+				   case op_code(3 downto 0) is
+					when "0111" => -- sta
+                 dout_ctrl  <= acca_dout;
+					when "1111" => -- stx / sty
+					  case pre_code is
+					  when "00010000" => -- page 2 -- sty
+	                dout_ctrl  <= iy_lo_dout;
+				     when others =>     -- page 1 -- stx
+                   dout_ctrl  <= ix_lo_dout;
+					  end case;
+					when others =>
+                 dout_ctrl  <= md_lo_dout;
+					end case;
+             else               
+				   case op_code(3 downto 0) is
+					when "0111" => -- stb
+                 dout_ctrl  <= accb_dout;
+					when "1101" => -- std
+                 dout_ctrl  <= accb_dout; -- accb is low byte of accd
+					when "1111" => -- stu / sts
+					  case pre_code is
+					  when "00010000" => -- page 2 -- sts
+	                dout_ctrl  <= sp_lo_dout;
+					  when others =>     -- page 1 -- stu
+	                dout_ctrl  <= up_lo_dout;
+					  end case;
+					when others =>
+                 dout_ctrl  <= md_lo_dout;
+					end case;
+             end if;
+				 -- write ALU low byte output
+             addr_ctrl    <= write_ad;
+				 next_state   <= fetch_state;
+
+			  --
+			  -- 16 bit immediate addressing mode
+			  --
+			  when imm16_state =>
+				   -- increment pc
+               pc_ctrl    <= incr_pc;
+				   -- fetch next immediate byte
+			      md_ctrl    <= fetch_next_md;
+               addr_ctrl  <= fetch_ad;
+					st_ctrl    <= pull_st;
+					next_state <= saved_state;
+
+           --
+			  -- md & ea holds 8 bit index offset
+			  -- calculate the effective memory address
+			  -- using the alu
+			  --
+           when indexed_state =>
+				 --
+				 -- decode indexing mode
+				 --
+				 if md(7) = '0' then
+				   case md(6 downto 5) is
+					when "00" =>
+			        left_ctrl  <= ix_left;
+					when "01" =>
+			        left_ctrl  <= iy_left;
+					when "10" =>
+			        left_ctrl  <= up_left;
+					when others =>
+					-- when "11" =>
+			        left_ctrl  <= sp_left;
+					end case;
+				   right_ctrl   <= md_sign5_right;
+				   alu_ctrl     <= alu_add16;
+               ea_ctrl      <= load_ea;
+					st_ctrl      <= pull_st;
+					next_state   <= saved_state;
+
+				 else
+				   case md(3 downto 0) is
+					when "0000" =>     -- ,R+
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+					  when others =>
+			          left_ctrl  <= sp_left;
+					  end case;
+					  --
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_add16;
+                 ea_ctrl    <= load_ea;
+                 next_state <= postincr1_state;
+
+					when "0001" =>     -- ,R++
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+					  end case;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_add16;
+                 ea_ctrl    <= load_ea;
+                 next_state <= postincr2_state;
+
+					when "0010" =>     -- ,-R
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+                   ix_ctrl    <= load_ix;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+                   iy_ctrl    <= load_iy;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+                   up_ctrl    <= load_up;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+                   sp_ctrl    <= load_sp;
+					  end case;
+				     right_ctrl   <= one_right;
+				     alu_ctrl     <= alu_sub16;
+                 ea_ctrl      <= load_ea;
+					  st_ctrl      <= pull_st;
+					  next_state   <= saved_state;
+
+					when "0011" =>     -- ,--R
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+                   ix_ctrl    <= load_ix;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+                   iy_ctrl    <= load_iy;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+                   up_ctrl    <= load_up;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+                   sp_ctrl    <= load_sp;
+					  end case;
+				     right_ctrl <= two_right;
+				     alu_ctrl   <= alu_sub16;
+                 ea_ctrl    <= load_ea;
+					  if md(4) = '0' then
+					    st_ctrl      <= pull_st;
+					    next_state   <= saved_state;
+					  else
+					    next_state   <= indirect_state;
+					  end if;
+
+					when "0100" =>     -- ,R (zero offset)
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+					  end case;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_add16;
+                 ea_ctrl    <= load_ea;
+					  if md(4) = '0' then
+					    st_ctrl      <= pull_st;
+					    next_state   <= saved_state;
+					  else
+					    next_state   <= indirect_state;
+					  end if;
+
+					when "0101" =>     -- ACCB,R
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+					  end case;
+				     right_ctrl <= accb_right;
+				     alu_ctrl   <= alu_add16;
+                 ea_ctrl    <= load_ea;
+					  if md(4) = '0' then
+					    st_ctrl      <= pull_st;
+					    next_state   <= saved_state;
+					  else
+					    next_state   <= indirect_state;
+					  end if;
+
+					when "0110" =>     -- ACCA,R
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+					  end case;
+				     right_ctrl <= acca_right;
+				     alu_ctrl   <= alu_add16;
+                 ea_ctrl    <= load_ea;
+					  if md(4) = '0' then
+					    st_ctrl      <= pull_st;
+					    next_state   <= saved_state;
+					  else
+					    next_state   <= indirect_state;
+					  end if;
+
+					when "0111" =>     -- undefined
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+					  end case;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_add16;
+                 ea_ctrl    <= load_ea;
+					  if md(4) = '0' then
+					    st_ctrl      <= pull_st;
+					    next_state   <= saved_state;
+					  else
+					    next_state   <= indirect_state;
+					  end if;
+
+					when "1000" =>     -- offset8,R
+                 md_ctrl    <= fetch_first_md; -- pick up 8 bit offset
+                 addr_ctrl  <= fetch_ad;
+                 pc_ctrl    <= incr_pc;
+                 next_state <= index8_state;
+
+					when "1001" =>     -- offset16,R
+                 md_ctrl    <= fetch_first_md; -- pick up first byte of 16 bit offset
+                 addr_ctrl  <= fetch_ad;
+                 pc_ctrl    <= incr_pc;
+                 next_state <= index16_state;
+
+					when "1010" =>     -- undefined
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+					  end case;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_add16;
+                 ea_ctrl    <= load_ea;
+					  --
+					  if md(4) = '0' then
+					    st_ctrl      <= pull_st;
+					    next_state   <= saved_state;
+					  else
+					    next_state   <= indirect_state;
+					  end if;
+
+					when "1011" =>     -- ACCD,R
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+					  end case;
+				     right_ctrl <= accd_right;
+				     alu_ctrl   <= alu_add16;
+                 ea_ctrl    <= load_ea;
+					  if md(4) = '0' then
+					    st_ctrl      <= pull_st;
+					    next_state   <= saved_state;
+					  else
+					    next_state   <= indirect_state;
+					  end if;
+
+					when "1100" =>     -- offset8,PC
+					  -- fetch 8 bit offset
+                 md_ctrl    <= fetch_first_md;
+                 addr_ctrl  <= fetch_ad;
+                 pc_ctrl    <= incr_pc;
+                 next_state <= pcrel8_state;
+
+					when "1101" =>     -- offset16,PC
+					  -- fetch offset
+                 md_ctrl    <= fetch_first_md;
+                 addr_ctrl  <= fetch_ad;
+                 pc_ctrl    <= incr_pc;
+                 next_state <= pcrel16_state;
+
+					when "1110" =>     -- undefined
+				     case md(6 downto 5) is
+					  when "00" =>
+			          left_ctrl  <= ix_left;
+					  when "01" =>
+			          left_ctrl  <= iy_left;
+					  when "10" =>
+			          left_ctrl  <= up_left;
+					  when others =>
+					  -- when "11" =>
+			          left_ctrl  <= sp_left;
+					  end case;
+				     right_ctrl <= zero_right;
+				     alu_ctrl   <= alu_add16;
+                 ea_ctrl    <= load_ea;
+					  if md(4) = '0' then
+					    st_ctrl      <= pull_st;
+					    next_state   <= saved_state;
+					  else
+					    next_state   <= indirect_state;
+					  end if;
+
+               when others =>
+--    			when "1111" =>     -- [,address]
+					  -- advance PC to pick up address
+                 md_ctrl    <= fetch_first_md;
+                 addr_ctrl  <= fetch_ad;
+					  pc_ctrl    <= incr_pc;
+                 next_state <= indexaddr_state;
+					end case;
+				 end if;
+
+			  -- load index register with ea plus one
+			  when postincr1_state =>
+			    left_ctrl  <= ea_left;
+			    right_ctrl <= one_right;
+			    alu_ctrl   <= alu_add16;
+				 case md(6 downto 5) is
+			    when "00" =>
+               ix_ctrl    <= load_ix;
+				 when "01" =>
+               iy_ctrl    <= load_iy;
+				 when "10" =>
+               up_ctrl    <= load_up;
+				 when others =>
+				 -- when "11" =>
+               sp_ctrl    <= load_sp;
+			    end case;
+				 -- return to previous state
+			    if md(4) = '0' then
+					 st_ctrl      <= pull_st;
+					 next_state   <= saved_state;
+				 else
+					 next_state   <= indirect_state;
+				 end if;
+
+			  -- load index register with ea plus two
+			  when postincr2_state =>
+				 -- increment register by two (address)
+			    left_ctrl  <= ea_left;
+			    right_ctrl <= two_right;
+			    alu_ctrl   <= alu_add16;
+				 case md(6 downto 5) is
+			    when "00" =>
+               ix_ctrl    <= load_ix;
+				 when "01" =>
+               iy_ctrl    <= load_iy;
+				 when "10" =>
+               up_ctrl    <= load_up;
+				 when others =>
+				 -- when "11" =>
+               sp_ctrl    <= load_sp;
+			    end case;
+				 -- return to previous state
+			    if md(4) = '0' then
+					 st_ctrl      <= pull_st;
+					 next_state   <= saved_state;
+				 else
+					 next_state   <= indirect_state;
+				 end if;
+           --
+			  -- ea = index register + md (8 bit signed offset)
+			  -- ea holds post byte
+			  --
+			  when index8_state =>
+				 case ea(6 downto 5) is
+			    when "00" =>
+			      left_ctrl  <= ix_left;
+			    when "01" =>
+			      left_ctrl  <= iy_left;
+				 when "10" =>
+			      left_ctrl  <= up_left;
+				 when others =>
+				 -- when "11" =>
+			      left_ctrl  <= sp_left;
+				 end case;
+				 -- ea = index reg + md
+			    right_ctrl <= md_sign8_right;
+			    alu_ctrl   <= alu_add16;
+             ea_ctrl    <= load_ea;
+				 -- return to previous state
+			    if ea(4) = '0' then
+					 st_ctrl      <= pull_st;
+					 next_state   <= saved_state;
+				 else
+					 next_state   <= indirect_state;
+				 end if;
+
+			  -- fetch low byte of 16 bit indexed offset
+			  when index16_state =>
+				 -- advance pc
+             pc_ctrl    <= incr_pc;
+				 -- fetch low byte
+             md_ctrl    <= fetch_next_md;
+             addr_ctrl  <= fetch_ad;
+				 next_state <= index16_2_state;
+
+			  -- ea = index register + md (16 bit offset)
+			  -- ea holds post byte
+			  when index16_2_state =>
+				 case ea(6 downto 5) is
+			    when "00" =>
+			      left_ctrl  <= ix_left;
+			    when "01" =>
+			      left_ctrl  <= iy_left;
+				 when "10" =>
+			      left_ctrl  <= up_left;
+				 when others =>
+				 -- when "11" =>
+			      left_ctrl  <= sp_left;
+				 end case;
+				 -- ea = index reg + md
+			    right_ctrl <= md_right;
+			    alu_ctrl   <= alu_add16;
+             ea_ctrl    <= load_ea;
+				 -- return to previous state
+			    if ea(4) = '0' then
+					 st_ctrl      <= pull_st;
+					 next_state   <= saved_state;
+				 else
+					 next_state   <= indirect_state;
+				 end if;
+           --
+			  -- pc relative with 8 bit signed offest
+			  -- md holds signed offset
+			  --
+			  when pcrel8_state =>
+				 -- ea = pc + signed md
+			    left_ctrl  <= pc_left;
+			    right_ctrl <= md_sign8_right;
+			    alu_ctrl   <= alu_add16;
+             ea_ctrl    <= load_ea;
+				 -- return to previous state
+			    if ea(4) = '0' then
+					 st_ctrl      <= pull_st;
+					 next_state   <= saved_state;
+				 else
+					 next_state   <= indirect_state;
+				 end if;
+
+			  -- pc relative addressing with 16 bit offset
+			  -- pick up the low byte of the offset in md
+			  -- advance the pc
+			  when pcrel16_state =>
+				 -- advance pc
+             pc_ctrl    <= incr_pc;
+				 -- fetch low byte
+             md_ctrl    <= fetch_next_md;
+             addr_ctrl  <= fetch_ad;
+				 next_state <= pcrel16_2_state;
+
+			  -- pc relative with16 bit signed offest
+			  -- md holds signed offset
+			  when pcrel16_2_state =>
+				 -- ea = pc +  md
+			    left_ctrl  <= pc_left;
+			    right_ctrl <= md_right;
+			    alu_ctrl   <= alu_add16;
+             ea_ctrl    <= load_ea;
+				 -- return to previous state
+			    if ea(4) = '0' then
+					 st_ctrl      <= pull_st;
+					 next_state   <= saved_state;
+				 else
+					 next_state   <= indirect_state;
+				 end if;
+
+			  -- indexed to address
+			  -- pick up the low byte of the address
+			  -- advance the pc
+			  when indexaddr_state =>
+				 -- advance pc
+             pc_ctrl    <= incr_pc;
+				 -- fetch low byte
+             md_ctrl    <= fetch_next_md;
+             addr_ctrl  <= fetch_ad;
+				 next_state <= indexaddr2_state;
+
+			  -- indexed to absolute address
+			  -- md holds address
+			  -- ea hold indexing mode byte
+			  when indexaddr2_state =>
+				 -- ea = md
+			    left_ctrl  <= pc_left;
+			    right_ctrl <= md_right;
+			    alu_ctrl   <= alu_ld16;
+             ea_ctrl    <= load_ea;
+				 -- return to previous state
+			    if ea(4) = '0' then
+					 st_ctrl      <= pull_st;
+					 next_state   <= saved_state;
+				 else
+					 next_state   <= indirect_state;
+				 end if;
+
+           --
+			  -- load md with high byte of indirect address
+			  -- pointed to by ea
+			  -- increment ea
+			  --
+			  when indirect_state =>
+				 -- increment ea
+			    left_ctrl  <= ea_left;
+			    right_ctrl <= one_right;
+			    alu_ctrl   <= alu_add16;
+             ea_ctrl    <= load_ea;
+				 -- fetch high byte
+             md_ctrl    <= fetch_first_md;
+             addr_ctrl  <= read_ad;
+				 next_state <= indirect2_state;
+           --
+			  -- load md with low byte of indirect address
+			  -- pointed to by ea
+			  -- ea has previously been incremented
+			  --
+			  when indirect2_state =>
+				 -- fetch high byte
+             md_ctrl    <= fetch_next_md;
+             addr_ctrl  <= read_ad;
+             dout_ctrl  <= md_lo_dout;
+				 next_state <= indirect3_state;
+			  --
+			  -- complete idirect addressing
+			  -- by loading ea with md
+			  --
+			  when indirect3_state =>
+				 -- load ea with md
+			    left_ctrl  <= ea_left;
+			    right_ctrl <= md_right;
+			    alu_ctrl   <= alu_ld16;
+             ea_ctrl    <= load_ea;
+				 -- return to previous state
+				 st_ctrl      <= pull_st;
+				 next_state   <= saved_state;
+
+           --
+			  -- ea holds the low byte of the absolute address
+			  -- Move ea low byte into ea high byte
+			  -- load new ea low byte to for absolute 16 bit address
+			  -- advance the program counter
+			  --
+			  when extended_state => -- fetch ea low byte
+					-- increment pc
+               pc_ctrl      <= incr_pc;
+					-- fetch next effective address bytes
+					ea_ctrl      <= fetch_next_ea;
+               addr_ctrl    <= fetch_ad;
+				   -- return to previous state
+				   st_ctrl      <= pull_st;
+				   next_state   <= saved_state;
+
+				when lea_state => -- here on load effective address
+					-- load index register with effective address
+               left_ctrl  <= pc_left;
+					right_ctrl <= ea_right;
+				   alu_ctrl   <= alu_lea;
+					case op_code(3 downto 0) is
+					when "0000" => -- leax
+                   cc_ctrl    <= load_cc;
+                   ix_ctrl    <= load_ix;
+					when "0001" => -- leay
+                   cc_ctrl    <= load_cc;
+                   iy_ctrl    <= load_iy;
+					when "0010" => -- leas
+                   sp_ctrl    <= load_sp;
+					when "0011" => -- leau
+                   up_ctrl    <= load_up;
+					when others =>
+					    null;
+					end case;
+               next_state   <= fetch_state;
+
+				--
+				-- jump to subroutine
+				-- sp=sp-1
+				-- call push_return_lo_state to save pc
+				-- return to jmp_state
+				--
+				when jsr_state =>
+					-- decrement sp
+               left_ctrl    <= sp_left;
+					right_ctrl   <= one_right;
+				   alu_ctrl     <= alu_sub16;
+               sp_ctrl      <= load_sp;
+					-- call push_return_state
+					st_ctrl      <= push_st;
+					return_state <= jmp_state;
+               next_state   <= push_return_lo_state;
+
+				--
+				-- Load pc with ea
+				-- (JMP)
+				--
+				when jmp_state =>
+					-- load PC with effective address
+               left_ctrl  <= pc_left;
+					right_ctrl <= ea_right;
+				   alu_ctrl   <= alu_ld16;
+					pc_ctrl    <= load_pc;
+               next_state <= fetch_state;
+
+				--
+				-- long branch or branch to subroutine
+				-- pick up next md byte
+				-- md_hi = md_lo
+				-- md_lo = (pc)
+				-- pc=pc+1
+				-- if a lbsr push return address
+				-- continue to sbranch_state
+				-- to evaluate conditional branches
+				--
+				when lbranch_state =>
+					pc_ctrl    <= incr_pc;
+					-- fetch the next byte into md_lo
+               md_ctrl    <= fetch_next_md;
+               addr_ctrl  <= fetch_ad;
+					-- if lbsr - push return address
+					-- then continue on to short branch
+					if op_code = "00010111" then
+					  st_ctrl      <= push_st;
+					  return_state <= sbranch_state;
+                 next_state   <= push_return_lo_state;
+					else
+                 next_state   <= sbranch_state;
+					end if;
+
+				 --
+				 -- here to execute conditional branch
+				 -- short conditional branch md = signed 8 bit offset
+				 -- long branch md = 16 bit offset
+				 -- 
+	          when sbranch_state =>
+               left_ctrl  <= pc_left;
+					right_ctrl <= md_right;
+				   alu_ctrl   <= alu_add16;
+					-- Test condition for branch
+			      if op_code(7 downto 4) = "0010" then -- conditional branch
+                 case op_code(3 downto 0) is
+		           when "0000" => -- bra
+					    cond_true := (1 = 1);
+		           when "0001" => -- brn
+					    cond_true := (1 = 0);
+		           when "0010" => -- bhi
+					    cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
+		           when "0011" => -- bls
+					    cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
+		           when "0100" => -- bcc/bhs
+					    cond_true := (cc(CBIT) = '0');
+		           when "0101" => -- bcs/blo
+					    cond_true := (cc(CBIT) = '1');
+		           when "0110" => -- bne
+		             cond_true := (cc(ZBIT) = '0');
+		           when "0111" => -- beq
+					    cond_true := (cc(ZBIT) = '1');
+		           when "1000" => -- bvc
+					    cond_true := (cc(VBIT) = '0');
+		           when "1001" => -- bvs
+					    cond_true := (cc(VBIT) = '1');
+		           when "1010" => -- bpl
+					    cond_true := (cc(NBIT) = '0');
+		           when "1011" => -- bmi
+					    cond_true := (cc(NBIT) = '1');
+		           when "1100" => -- bge
+					    cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
+		           when "1101" => -- blt
+					    cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
+		           when "1110" => -- bgt
+					    cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
+		           when "1111" => -- ble
+					    cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
+		           when others =>
+					    null;
+		           end case;
+					else
+					  cond_true := (1 = 1); -- lbra, lbsr, bsr
+				   end if;
+					if cond_true then
+					  pc_ctrl    <= load_pc;
+               end if;
+					next_state   <= fetch_state;
+
+				 --
+				 -- push return address onto the S stack
+				 --
+				 -- (sp) = pc_lo
+				 -- sp = sp - 1
+				 --
+				 when push_return_lo_state =>
+					  -- decrement the sp
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= one_right;
+                 alu_ctrl   <= alu_sub16;
+                 sp_ctrl    <= load_sp;
+                 -- write PC low
+                 addr_ctrl  <= pushs_ad;
+                 dout_ctrl  <= pc_lo_dout;
+                 next_state <= push_return_hi_state;
+
+				--
+				-- push program counter hi byte onto the stack
+				-- (sp) = pc_hi
+				-- sp = sp
+				-- return to originating state
+				--
+				when push_return_hi_state =>
+					  -- write pc hi bytes
+                 addr_ctrl    <= pushs_ad;
+                 dout_ctrl    <= pc_hi_dout;
+ 					  st_ctrl      <= pull_st;
+                 next_state   <= saved_state;
+
+				 when pull_return_hi_state =>
+					  -- increment the sp
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= one_right;
+                 alu_ctrl   <= alu_add16;
+                 sp_ctrl    <= load_sp;
+                 -- read pc hi
+					  pc_ctrl    <= pull_hi_pc;
+                 addr_ctrl  <= pulls_ad;
+                 next_state <= pull_return_lo_state;
+
+				when pull_return_lo_state =>
+					  -- increment the SP
+                 left_ctrl  <= sp_left;
+                 right_ctrl <= one_right;
+                 alu_ctrl   <= alu_add16;
+                 sp_ctrl    <= load_sp;
+					  -- read pc low
+					  pc_ctrl    <= pull_lo_pc;
+                 addr_ctrl  <= pulls_ad;
+                 dout_ctrl  <= pc_lo_dout;
+ 					  --
+					  st_ctrl      <= pull_st;
+                 next_state   <= saved_state;
+
+				 when andcc_state =>
+					  -- AND CC with md
+                 left_ctrl  <= md_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_andcc;
+                 cc_ctrl    <= load_cc;
+ 					  --
+					  st_ctrl    <= pull_st;
+				     next_state <= saved_state;
+
+				 when orcc_state =>
+					  -- OR CC with md
+                 left_ctrl  <= md_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_orcc;
+                 cc_ctrl    <= load_cc;
+ 					  --
+					  st_ctrl    <= pull_st;
+				     next_state <= saved_state;
+
+				 when tfr_state =>
+					  -- select source register
+					  case md(7 downto 4) is
+					  when "0000" =>
+					    left_ctrl <= accd_left;
+					  when "0001" =>
+					    left_ctrl <= ix_left;
+					  when "0010" =>
+					    left_ctrl <= iy_left;
+					  when "0011" =>
+					    left_ctrl <= up_left;
+					  when "0100" =>
+					    left_ctrl <= sp_left;
+					  when "0101" =>
+					    left_ctrl <= pc_left;
+					  when "1000" =>
+					    left_ctrl <= acca_left;
+					  when "1001" =>
+					    left_ctrl <= accb_left;
+					  when "1010" =>
+					    left_ctrl <= cc_left;
+					  when "1011" =>
+					    left_ctrl <= dp_left;
+					  when others =>
+                   left_ctrl  <= md_left;
+					  end case;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_tfr;
+					  -- select destination register
+					  case md(3 downto 0) is
+					  when "0000" => -- accd
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  when "0001" => -- ix
+                   ix_ctrl    <= load_ix;
+					  when "0010" => -- iy
+                   iy_ctrl    <= load_iy;
+					  when "0011" => -- up
+                   up_ctrl    <= load_up;
+					  when "0100" => -- sp
+                   sp_ctrl    <= load_sp;
+					  when "0101" => -- pc
+                   pc_ctrl    <= load_pc;
+					  when "1000" => -- acca
+                   acca_ctrl  <= load_acca;
+					  when "1001" => -- accb
+                   accb_ctrl  <= load_accb;
+					  when "1010" => -- cc
+                   cc_ctrl    <= load_cc;
+					  when "1011" => --dp
+                   dp_ctrl    <= load_dp;
+					  when others =>
+					    null;
+					  end case;
+ 					  --
+					  st_ctrl      <= pull_st;
+				     next_state   <= saved_state;
+
+				 when exg_state =>
+					  -- save destination register
+					  case md(3 downto 0) is
+					  when "0000" =>
+					    left_ctrl <= accd_left;
+					  when "0001" =>
+					    left_ctrl <= ix_left;
+					  when "0010" =>
+					    left_ctrl <= iy_left;
+					  when "0011" =>
+					    left_ctrl <= up_left;
+					  when "0100" =>
+					    left_ctrl <= sp_left;
+					  when "0101" =>
+					    left_ctrl <= pc_left;
+					  when "1000" =>
+					    left_ctrl <= acca_left;
+					  when "1001" =>
+					    left_ctrl <= accb_left;
+					  when "1010" =>
+					    left_ctrl <= cc_left;
+					  when "1011" =>
+					    left_ctrl <= dp_left;
+					  when others =>
+                   left_ctrl  <= md_left;
+					  end case;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_tfr;
+                 ea_ctrl    <= load_ea;
+ 					  -- call tranfer microcode
+					  st_ctrl      <= push_st;
+					  return_state <= exg1_state;
+				     next_state   <= tfr_state;
+
+				 when exg1_state =>
+					  -- restore destination
+                 left_ctrl  <= ea_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_tfr;
+					  -- save as source register
+					  case md(7 downto 4) is
+					  when "0000" => -- accd
+                   acca_ctrl  <= load_hi_acca;
+                   accb_ctrl  <= load_accb;
+					  when "0001" => -- ix
+                   ix_ctrl    <= load_ix;
+					  when "0010" => -- iy
+                   iy_ctrl    <= load_iy;
+					  when "0011" => -- up
+                   up_ctrl    <= load_up;
+					  when "0100" => -- sp
+                   sp_ctrl    <= load_sp;
+					  when "0101" => -- pc
+                   pc_ctrl    <= load_pc;
+					  when "1000" => -- acca
+                   acca_ctrl  <= load_acca;
+					  when "1001" => -- accb
+                   accb_ctrl  <= load_accb;
+					  when "1010" => -- cc
+                   cc_ctrl    <= load_cc;
+					  when "1011" => --dp
+                   dp_ctrl    <= load_dp;
+					  when others =>
+					    null;
+					  end case;
+				     next_state   <= fetch_state;
+
+				 when mul_state =>
+					  -- move acca to md
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_st16;
+                 md_ctrl    <= load_md;
+				     next_state <= mulea_state;
+
+				 when mulea_state =>
+					  -- move accb to ea
+                 left_ctrl  <= accb_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_st16;
+                 ea_ctrl    <= load_ea;
+				     next_state <= muld_state;
+
+				 when muld_state =>
+					  -- clear accd
+                 left_ctrl  <= acca_left;
+                 right_ctrl <= zero_right;
+                 alu_ctrl   <= alu_ld8;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+				     next_state <= mul0_state;
+
+				 when mul0_state =>
+					  -- if bit 0 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+					  if ea(0) = '1' then
+                   right_ctrl <= md_right;
+					  else
+                   right_ctrl <= zero_right;
+					  end if;
+                 alu_ctrl   <= alu_mul;
+                 cc_ctrl    <= load_cc;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+                 md_ctrl    <= shiftl_md;
+				     next_state <= mul1_state;
+
+				 when mul1_state =>
+					  -- if bit 1 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+					  if ea(1) = '1' then
+                   right_ctrl <= md_right;
+					  else
+                   right_ctrl <= zero_right;
+					  end if;
+                 alu_ctrl   <= alu_mul;
+                 cc_ctrl    <= load_cc;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+                 md_ctrl    <= shiftl_md;
+				     next_state <= mul2_state;
+
+				 when mul2_state =>
+					  -- if bit 2 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+					  if ea(2) = '1' then
+                   right_ctrl <= md_right;
+					  else
+                   right_ctrl <= zero_right;
+					  end if;
+                 alu_ctrl   <= alu_mul;
+                 cc_ctrl    <= load_cc;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+                 md_ctrl    <= shiftl_md;
+				     next_state <= mul3_state;
+
+				 when mul3_state =>
+					  -- if bit 3 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+					  if ea(3) = '1' then
+                   right_ctrl <= md_right;
+					  else
+                   right_ctrl <= zero_right;
+					  end if;
+                 alu_ctrl   <= alu_mul;
+                 cc_ctrl    <= load_cc;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+                 md_ctrl    <= shiftl_md;
+				     next_state <= mul4_state;
+
+				 when mul4_state =>
+					  -- if bit 4 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+					  if ea(4) = '1' then
+                   right_ctrl <= md_right;
+					  else
+                   right_ctrl <= zero_right;
+					  end if;
+                 alu_ctrl   <= alu_mul;
+                 cc_ctrl    <= load_cc;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+                 md_ctrl    <= shiftl_md;
+				     next_state <= mul5_state;
+
+				 when mul5_state =>
+					  -- if bit 5 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+					  if ea(5) = '1' then
+                   right_ctrl <= md_right;
+					  else
+                   right_ctrl <= zero_right;
+					  end if;
+                 alu_ctrl   <= alu_mul;
+                 cc_ctrl    <= load_cc;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+                 md_ctrl    <= shiftl_md;
+				     next_state <= mul6_state;
+
+				 when mul6_state =>
+					  -- if bit 6 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+					  if ea(6) = '1' then
+                   right_ctrl <= md_right;
+					  else
+                   right_ctrl <= zero_right;
+					  end if;
+                 alu_ctrl   <= alu_mul;
+                 cc_ctrl    <= load_cc;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+                 md_ctrl    <= shiftl_md;
+				     next_state <= mul7_state;
+
+				 when mul7_state =>
+					  -- if bit 7 of ea set, add accd to md
+                 left_ctrl  <= accd_left;
+					  if ea(7) = '1' then
+                   right_ctrl <= md_right;
+					  else
+                   right_ctrl <= zero_right;
+					  end if;
+                 alu_ctrl   <= alu_mul;
+                 cc_ctrl    <= load_cc;
+                 acca_ctrl  <= load_hi_acca;
+                 accb_ctrl  <= load_accb;
+                 md_ctrl    <= shiftl_md;
+				     next_state <= fetch_state;
+
+			  --
+			  -- Enter here on pushs
+			  -- ea holds post byte
+			  --
+			  when pshs_state =>
+             -- decrement sp if any registers to be pushed
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 -- idle	address
+             addr_ctrl  <= idle_ad;
+			    dout_ctrl  <= cc_dout; 
+				 if ea(7 downto 0) = "00000000" then
+               sp_ctrl    <= latch_sp;
+				 else
+               sp_ctrl    <= load_sp;
+				 end if;
+				 if ea(7) = '1' then
+               next_state <= pshs_pcl_state;
+				 elsif ea(6) = '1' then
+               next_state <= pshs_upl_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= pshs_iyl_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= pshs_ixl_state;
+				 elsif ea(3) = '1' then
+ 				   next_state <= pshs_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state <= pshs_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state <= pshs_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state <= pshs_cc_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when pshs_pcl_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write pc low
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= pc_lo_dout; 
+             next_state <= pshs_pch_state;
+
+			  when pshs_pch_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(6 downto 0) = "0000000" then
+               sp_ctrl    <= latch_sp;
+				 else
+               sp_ctrl    <= load_sp;
+				 end if;
+				 -- write pc hi
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= pc_hi_dout; 
+				 if ea(6) = '1' then
+               next_state <= pshs_upl_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= pshs_iyl_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= pshs_ixl_state;
+				 elsif ea(3) = '1' then
+ 				   next_state <= pshs_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state <= pshs_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state <= pshs_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state <= pshs_cc_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+
+			  when pshs_upl_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write pc low
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= up_lo_dout; 
+             next_state <= pshs_uph_state;
+
+			  when pshs_uph_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(5 downto 0) = "000000" then
+               sp_ctrl    <= latch_sp;
+				 else
+               sp_ctrl    <= load_sp;
+				 end if;
+				 -- write pc hi
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= up_hi_dout; 
+				 if ea(5) = '1' then
+ 				   next_state   <= pshs_iyl_state;
+				 elsif ea(4) = '1' then
+ 				   next_state   <= pshs_ixl_state;
+				 elsif ea(3) = '1' then
+ 				   next_state   <= pshs_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state   <= pshs_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshs_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshs_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshs_iyl_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write iy low
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= iy_lo_dout; 
+             next_state <= pshs_iyh_state;
+
+			  when pshs_iyh_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(4 downto 0) = "00000" then
+               sp_ctrl    <= latch_sp;
+				 else
+               sp_ctrl    <= load_sp;
+				 end if;
+				 -- write iy hi
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= iy_hi_dout; 
+				 if ea(4) = '1' then
+ 				   next_state   <= pshs_ixl_state;
+				 elsif ea(3) = '1' then
+ 				   next_state   <= pshs_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state   <= pshs_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshs_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshs_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshs_ixl_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write ix low
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= ix_lo_dout; 
+             next_state <= pshs_ixh_state;
+
+			  when pshs_ixh_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(3 downto 0) = "0000" then
+               sp_ctrl    <= latch_sp;
+				 else
+               sp_ctrl    <= load_sp;
+				 end if;
+				 -- write ix hi
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= ix_hi_dout; 
+				 if ea(3) = '1' then
+ 				   next_state   <= pshs_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state   <= pshs_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshs_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshs_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshs_dp_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(2 downto 0) = "000" then
+               sp_ctrl    <= latch_sp;
+				 else
+               sp_ctrl    <= load_sp;
+				 end if;
+				 -- write dp
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= dp_dout; 
+				 if ea(2) = '1' then
+ 				   next_state   <= pshs_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshs_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshs_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshs_accb_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(1 downto 0) = "00" then
+               sp_ctrl    <= latch_sp;
+				 else
+               sp_ctrl    <= load_sp;
+				 end if;
+				 -- write accb
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= accb_dout; 
+				 if ea(1) = '1' then
+ 				   next_state   <= pshs_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshs_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshs_acca_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(0) = '1' then
+               sp_ctrl    <= load_sp;
+				 else
+               sp_ctrl    <= latch_sp;
+				 end if;
+				 -- write acca
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= acca_dout; 
+				 if ea(0) = '1' then
+ 				   next_state   <= pshs_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshs_cc_state =>
+             -- idle sp
+				 -- write cc
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= cc_dout; 
+             next_state <= fetch_state;
+
+			  --
+			  -- enter here on PULS
+			  -- ea hold register mask
+			  --
+			  when puls_state =>
+				 if ea(0) = '1' then
+ 				   next_state <= puls_cc_state;
+				 elsif ea(1) = '1' then
+ 				   next_state <= puls_acca_state;
+				 elsif ea(2) = '1' then
+ 				   next_state <= puls_accb_state;
+				 elsif ea(3) = '1' then
+ 				   next_state <= puls_dp_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= puls_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= puls_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= puls_uph_state;
+				 elsif ea(7) = '1' then
+               next_state <= puls_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when puls_cc_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read cc
+             cc_ctrl    <= pull_cc;
+             addr_ctrl  <= pulls_ad;
+				 if ea(1) = '1' then
+ 				   next_state <= puls_acca_state;
+				 elsif ea(2) = '1' then
+ 				   next_state <= puls_accb_state;
+				 elsif ea(3) = '1' then
+ 				   next_state <= puls_dp_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= puls_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= puls_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= puls_uph_state;
+				 elsif ea(7) = '1' then
+               next_state <= puls_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when puls_acca_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read acca
+				 acca_ctrl  <= pull_acca;
+             addr_ctrl  <= pulls_ad;
+				 if ea(2) = '1' then
+ 				   next_state <= puls_accb_state;
+				 elsif ea(3) = '1' then
+ 				   next_state <= puls_dp_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= puls_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= puls_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= puls_uph_state;
+				 elsif ea(7) = '1' then
+               next_state <= puls_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when puls_accb_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read accb
+				 accb_ctrl  <= pull_accb;
+             addr_ctrl  <= pulls_ad;
+				 if ea(3) = '1' then
+ 				   next_state <= puls_dp_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= puls_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= puls_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= puls_uph_state;
+				 elsif ea(7) = '1' then
+               next_state <= puls_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when puls_dp_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read dp
+				 dp_ctrl    <= pull_dp;
+             addr_ctrl  <= pulls_ad;
+				 if ea(4) = '1' then
+ 				   next_state <= puls_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= puls_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= puls_uph_state;
+				 elsif ea(7) = '1' then
+               next_state <= puls_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+		  	  when puls_ixh_state =>
+             -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- pull ix hi
+				 ix_ctrl    <= pull_hi_ix;
+             addr_ctrl  <= pulls_ad;
+             next_state <= puls_ixl_state;
+
+		  	  when puls_ixl_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read ix low
+				 ix_ctrl    <= pull_lo_ix;
+             addr_ctrl  <= pulls_ad;
+				 if ea(5) = '1' then
+ 				   next_state <= puls_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= puls_uph_state;
+				 elsif ea(7) = '1' then
+               next_state <= puls_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+		  	  when puls_iyh_state =>
+             -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- pull iy hi
+				 iy_ctrl    <= pull_hi_iy;
+             addr_ctrl  <= pulls_ad;
+             next_state   <= puls_iyl_state;
+
+		  	  when puls_iyl_state =>
+             -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read iy low
+				 iy_ctrl    <= pull_lo_iy;
+             addr_ctrl  <= pulls_ad;
+				 if ea(6) = '1' then
+               next_state <= puls_uph_state;
+				 elsif ea(7) = '1' then
+               next_state <= puls_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+		  	  when puls_uph_state =>
+             -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- pull up hi
+				 up_ctrl    <= pull_hi_up;
+             addr_ctrl  <= pulls_ad;
+             next_state <= puls_upl_state;
+
+		  	  when puls_upl_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read up low
+				 up_ctrl    <= pull_lo_up;
+             addr_ctrl  <= pulls_ad;
+				 if ea(7) = '1' then
+               next_state <= puls_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+		  	  when puls_pch_state =>
+             -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- pull pc hi
+				 pc_ctrl    <= pull_hi_pc;
+             addr_ctrl  <= pulls_ad;
+             next_state <= puls_pcl_state;
+
+		  	  when puls_pcl_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read pc low
+				 pc_ctrl    <= pull_lo_pc;
+             addr_ctrl  <= pulls_ad;
+             next_state <= fetch_state;
+
+			  --
+			  -- Enter here on pshu
+			  -- ea holds post byte
+			  --
+			  when pshu_state =>
+             -- decrement up if any registers to be pushed
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(7 downto 0) = "00000000" then
+               up_ctrl    <= latch_up;
+				 else
+               up_ctrl    <= load_up;
+				 end if;
+				 -- write idle bus
+				 if ea(7) = '1' then
+               next_state   <= pshu_pcl_state;
+				 elsif ea(6) = '1' then
+               next_state   <= pshu_spl_state;
+				 elsif ea(5) = '1' then
+ 				   next_state   <= pshu_iyl_state;
+				 elsif ea(4) = '1' then
+ 				   next_state   <= pshu_ixl_state;
+				 elsif ea(3) = '1' then
+ 				   next_state   <= pshu_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state   <= pshu_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshu_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshu_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+			  --
+			  -- push PC onto U stack
+			  --
+			  when pshu_pcl_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             up_ctrl    <= load_up;
+				 -- write pc low
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= pc_lo_dout; 
+             next_state <= pshu_pch_state;
+
+			  when pshu_pch_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(6 downto 0) = "0000000" then
+               up_ctrl    <= latch_up;
+				 else
+               up_ctrl    <= load_up;
+				 end if;
+				 -- write pc hi
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= pc_hi_dout; 
+				 if ea(6) = '1' then
+               next_state   <= pshu_spl_state;
+				 elsif ea(5) = '1' then
+ 				   next_state   <= pshu_iyl_state;
+				 elsif ea(4) = '1' then
+ 				   next_state   <= pshu_ixl_state;
+				 elsif ea(3) = '1' then
+ 				   next_state   <= pshu_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state   <= pshu_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshu_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshu_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshu_spl_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             up_ctrl    <= load_up;
+				 -- write sp low
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= sp_lo_dout; 
+             next_state <= pshu_sph_state;
+
+			  when pshu_sph_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(5 downto 0) = "000000" then
+               up_ctrl    <= latch_up;
+				 else
+               up_ctrl    <= load_up;
+				 end if;
+				 -- write sp hi
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= sp_hi_dout; 
+				 if ea(5) = '1' then
+ 				   next_state   <= pshu_iyl_state;
+				 elsif ea(4) = '1' then
+ 				   next_state   <= pshu_ixl_state;
+				 elsif ea(3) = '1' then
+ 				   next_state   <= pshu_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state   <= pshu_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshu_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshu_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshu_iyl_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             up_ctrl    <= load_up;
+				 -- write iy low
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= iy_lo_dout; 
+             next_state <= pshu_iyh_state;
+
+			  when pshu_iyh_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(4 downto 0) = "00000" then
+               up_ctrl    <= latch_up;
+				 else
+               up_ctrl    <= load_up;
+				 end if;
+				 -- write iy hi
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= iy_hi_dout; 
+				 if ea(4) = '1' then
+ 				   next_state   <= pshu_ixl_state;
+				 elsif ea(3) = '1' then
+ 				   next_state   <= pshu_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state   <= pshu_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshu_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshu_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshu_ixl_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             up_ctrl    <= load_up;
+				 -- write ix low
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= ix_lo_dout; 
+             next_state <= pshu_ixh_state;
+
+			  when pshu_ixh_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(3 downto 0) = "0000" then
+               up_ctrl    <= latch_up;
+				 else
+               up_ctrl    <= load_up;
+				 end if;
+				 -- write ix hi
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= ix_hi_dout; 
+				 if ea(3) = '1' then
+ 				   next_state   <= pshu_dp_state;
+				 elsif ea(2) = '1' then
+ 				   next_state   <= pshu_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshu_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshu_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshu_dp_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(2 downto 0) = "000" then
+               up_ctrl    <= latch_up;
+				 else
+               up_ctrl    <= load_up;
+				 end if;
+				 -- write dp
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= dp_dout; 
+				 if ea(2) = '1' then
+ 				   next_state   <= pshu_accb_state;
+				 elsif ea(1) = '1' then
+ 				   next_state   <= pshu_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshu_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshu_accb_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(1 downto 0) = "00" then
+               up_ctrl    <= latch_up;
+				 else
+               up_ctrl    <= load_up;
+				 end if;
+				 -- write accb
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= accb_dout; 
+				 if ea(1) = '1' then
+ 				   next_state   <= pshu_acca_state;
+				 elsif ea(0) = '1' then
+ 				   next_state   <= pshu_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshu_acca_state =>
+             -- decrement up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+				 if ea(0) = '0' then
+               up_ctrl    <= latch_up;
+				 else
+               up_ctrl    <= load_up;
+				 end if;
+				 -- write acca
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= acca_dout; 
+				 if ea(0) = '1' then
+ 				   next_state   <= pshu_cc_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when pshu_cc_state =>
+             -- idle up
+				 -- write cc
+             addr_ctrl  <= pushu_ad;
+			    dout_ctrl  <= cc_dout; 
+             next_state <= fetch_state;
+
+			  --
+			  -- enter here on PULU
+			  -- ea hold register mask
+			  --
+			  when pulu_state =>
+				 -- idle UP
+				 -- idle bus
+				 if ea(0) = '1' then
+ 				   next_state <= pulu_cc_state;
+				 elsif ea(1) = '1' then
+ 				   next_state <= pulu_acca_state;
+				 elsif ea(2) = '1' then
+ 				   next_state <= pulu_accb_state;
+				 elsif ea(3) = '1' then
+ 				   next_state <= pulu_dp_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= pulu_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= pulu_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= pulu_sph_state;
+				 elsif ea(7) = '1' then
+               next_state <= pulu_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when pulu_cc_state =>
+				 -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read cc
+             cc_ctrl    <= pull_cc;
+             addr_ctrl  <= pullu_ad;
+				 if ea(1) = '1' then
+ 				   next_state <= pulu_acca_state;
+				 elsif ea(2) = '1' then
+ 				   next_state <= pulu_accb_state;
+				 elsif ea(3) = '1' then
+ 				   next_state <= pulu_dp_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= pulu_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= pulu_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= pulu_sph_state;
+				 elsif ea(7) = '1' then
+               next_state <= pulu_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when pulu_acca_state =>
+				 -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read acca
+				 acca_ctrl  <= pull_acca;
+             addr_ctrl  <= pullu_ad;
+				 if ea(2) = '1' then
+ 				   next_state <= pulu_accb_state;
+				 elsif ea(3) = '1' then
+ 				   next_state <= pulu_dp_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= pulu_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= pulu_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= pulu_sph_state;
+				 elsif ea(7) = '1' then
+               next_state <= pulu_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when pulu_accb_state =>
+				 -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read accb
+				 accb_ctrl  <= pull_accb;
+             addr_ctrl  <= pullu_ad;
+				 if ea(3) = '1' then
+ 				   next_state <= pulu_dp_state;
+				 elsif ea(4) = '1' then
+ 				   next_state <= pulu_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= pulu_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= pulu_sph_state;
+				 elsif ea(7) = '1' then
+               next_state <= pulu_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+			  when pulu_dp_state =>
+				 -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read dp
+				 dp_ctrl    <= pull_dp;
+             addr_ctrl  <= pullu_ad;
+				 if ea(4) = '1' then
+ 				   next_state <= pulu_ixh_state;
+				 elsif ea(5) = '1' then
+ 				   next_state <= pulu_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= pulu_sph_state;
+				 elsif ea(7) = '1' then
+               next_state <= pulu_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+		  	  when pulu_ixh_state =>
+             -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read ix hi
+				 ix_ctrl    <= pull_hi_ix;
+             addr_ctrl  <= pullu_ad;
+             next_state <= pulu_ixl_state;
+
+		  	  when pulu_ixl_state =>
+				 -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read ix low
+				 ix_ctrl    <= pull_lo_ix;
+             addr_ctrl  <= pullu_ad;
+				 if ea(5) = '1' then
+ 				   next_state <= pulu_iyh_state;
+				 elsif ea(6) = '1' then
+               next_state <= pulu_sph_state;
+				 elsif ea(7) = '1' then
+               next_state <= pulu_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+		  	  when pulu_iyh_state =>
+             -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read iy hi
+				 iy_ctrl    <= pull_hi_iy;
+             addr_ctrl  <= pullu_ad;
+             next_state <= pulu_iyl_state;
+
+		  	  when pulu_iyl_state =>
+             -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read iy low
+				 iy_ctrl    <= pull_lo_iy;
+             addr_ctrl  <= pullu_ad;
+				 if ea(6) = '1' then
+               next_state <= pulu_sph_state;
+				 elsif ea(7) = '1' then
+               next_state <= pulu_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+		  	  when pulu_sph_state =>
+             -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read sp hi
+				 sp_ctrl    <= pull_hi_sp;
+             addr_ctrl  <= pullu_ad;
+             next_state <= pulu_spl_state;
+
+		  	  when pulu_spl_state =>
+				 -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read sp low
+				 sp_ctrl    <= pull_lo_sp;
+             addr_ctrl  <= pullu_ad;
+				 if ea(7) = '1' then
+               next_state <= pulu_pch_state;
+				 else
+				   next_state <= fetch_state;
+				 end if;
+
+		  	  when pulu_pch_state =>
+             -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- pull pc hi
+				 pc_ctrl    <= pull_hi_pc;
+             addr_ctrl  <= pullu_ad;
+             next_state <= pulu_pcl_state;
+
+		  	  when pulu_pcl_state =>
+				 -- increment up
+             left_ctrl  <= up_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             up_ctrl    <= load_up;
+				 -- read pc low
+				 pc_ctrl    <= pull_lo_pc;
+             addr_ctrl  <= pullu_ad;
+             next_state <= fetch_state;
+
+			  --
+			  -- pop the Condition codes
+			  --
+			  when rti_cc_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read cc
+             cc_ctrl    <= pull_cc;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_entire_state;
+
+			  --
+			  -- Added RTI cycle 11th July 2006 John Kent.
+			  -- test the "Entire" Flag
+			  -- that has just been popped off the stack
+			  --
+			  when rti_entire_state =>
+				 --
+				 -- The Entire flag must be recovered from the stack
+				 -- before testing.
+				 --
+				 if cc(EBIT) = '1' then
+               next_state   <= rti_acca_state;
+				 else
+               next_state   <= rti_pch_state;
+				 end if;
+
+			  when rti_acca_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read acca
+				 acca_ctrl  <= pull_acca;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_accb_state;
+
+			  when rti_accb_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read accb
+				 accb_ctrl  <= pull_accb;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_dp_state;
+
+			  when rti_dp_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read dp
+				 dp_ctrl    <= pull_dp;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_ixh_state;
+
+			  when rti_ixh_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read ix hi
+				 ix_ctrl    <= pull_hi_ix;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_ixl_state;
+
+			  when rti_ixl_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read ix low
+				 ix_ctrl    <= pull_lo_ix;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_iyh_state;
+
+			  when rti_iyh_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read iy hi
+				 iy_ctrl    <= pull_hi_iy;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_iyl_state;
+
+			  when rti_iyl_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read iy low
+				 iy_ctrl    <= pull_lo_iy;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_uph_state;
+
+
+			  when rti_uph_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read up hi
+				 up_ctrl    <= pull_hi_up;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_upl_state;
+
+			  when rti_upl_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- read up low
+             up_ctrl    <= pull_lo_up;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_pch_state;
+
+			  when rti_pch_state =>
+	          -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+				 -- pull pc hi
+				 pc_ctrl    <= pull_hi_pc;
+             addr_ctrl  <= pulls_ad;
+             next_state <= rti_pcl_state;
+
+			  when rti_pcl_state =>
+				 -- increment sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_add16;
+             sp_ctrl    <= load_sp;
+	          -- pull pc low
+				 pc_ctrl    <= pull_lo_pc;
+             addr_ctrl  <= pulls_ad;
+             next_state <= fetch_state;
+
+			  --
+			  -- here on IRQ or NMI interrupt
+			  -- pre decrement the sp
+			  -- Idle bus cycle
+			  --
+			  when int_nmiirq_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+             next_state <= int_entire_state;
+
+			  --
+			  -- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
+			  -- clear Entire Flag on FIRQ
+			  -- before stacking all registers
+			  --
+			  when int_entire_state =>
+             -- set entire flag
+             alu_ctrl   <= alu_see;
+             cc_ctrl    <= load_cc;
+             next_state <= int_pcl_state;
+
+			  --
+			  -- here on FIRQ interrupt
+			  -- pre decrement the sp
+			  -- Idle bus cycle
+			  --
+			  when int_firq_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+             next_state <= int_fast_state;
+			  --
+			  -- clear Entire Flag on FIRQ
+			  -- before stacking all registers
+			  --
+			  when int_fast_state =>
+             -- clear entire flag
+             alu_ctrl   <= alu_cle;
+             cc_ctrl    <= load_cc;
+             next_state <= int_pcl_state;
+
+			  when int_pcl_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write pc low
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= pc_lo_dout; 
+             next_state <= int_pch_state;
+
+			  when int_pch_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write pc hi
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= pc_hi_dout; 
+				 if cc(EBIT) = '1' then
+               next_state   <= int_upl_state;
+				 else
+               next_state   <= int_cc_state;
+				 end if;
+
+			  when int_upl_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write up low
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= up_lo_dout; 
+             next_state <= int_uph_state;
+
+			  when int_uph_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write ix hi
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= up_hi_dout; 
+             next_state <= int_iyl_state;
+
+			  when int_iyl_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write ix low
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= iy_lo_dout; 
+             next_state <= int_iyh_state;
+
+			  when int_iyh_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write ix hi
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= iy_hi_dout; 
+             next_state <= int_ixl_state;
+
+			  when int_ixl_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write ix low
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= ix_lo_dout; 
+             next_state <= int_ixh_state;
+
+			  when int_ixh_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write ix hi
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= ix_hi_dout; 
+             next_state <= int_dp_state;
+
+			  when int_dp_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write accb
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= dp_dout; 
+             next_state <= int_accb_state;
+
+			  when int_accb_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write accb
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= accb_dout; 
+             next_state <= int_acca_state;
+
+			  when int_acca_state =>
+             -- decrement sp
+             left_ctrl  <= sp_left;
+             right_ctrl <= one_right;
+             alu_ctrl   <= alu_sub16;
+             sp_ctrl    <= load_sp;
+				 -- write acca
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= acca_dout; 
+             next_state <= int_cc_state;
+
+			  when int_cc_state =>
+				 -- write cc
+             addr_ctrl  <= pushs_ad;
+			    dout_ctrl  <= cc_dout;
+				 case iv is
+				 when NMI_VEC =>
+			      next_state <= int_maskif_state;
+				 when SWI_VEC =>
+			      next_state <= int_maskif_state;
+				 when FIRQ_VEC =>
+			      next_state <= int_maskif_state;
+				 when IRQ_VEC =>
+			      next_state <= int_maski_state;
+				 when SWI2_VEC =>
+	            next_state <= vect_hi_state;
+				 when SWI3_VEC =>
+	            next_state <= vect_hi_state;
+				 when others =>
+				   if op_code = "00111100" then -- CWAI
+					  next_state <= int_cwai_state;
+					else
+	              next_state <= rti_cc_state; -- spurious interrupt, do a RTI
+					end if;
+				 end case;
+
+			  --
+			  -- wait here for an inteerupt
+			  --
+			  when int_cwai_state =>
+			    if (nmi_req = '1') and (nmi_ack='0') then
+		  			iv_ctrl    <= nmi_iv;
+				   nmi_ctrl   <= set_nmi;
+			      next_state <= int_maskif_state;
+			    else
+				   --
+					-- nmi request is not cleared until nmi input goes low
+					--
+				   if (nmi_req = '0') and (nmi_ack='1') then
+				     nmi_ctrl <= reset_nmi;
+					end if;
+					--
+					-- FIRQ is level sensitive
+					--
+               if (firq = '1') and (cc(FBIT) = '0') then
+		  			  iv_ctrl    <= firq_iv;
+			        next_state <= int_maskif_state;
+					--
+					-- IRQ is level sensitive
+					--
+				   elsif (irq = '1') and (cc(IBIT) = '0') then
+		  			  iv_ctrl    <= irq_iv;
+			        next_state <= int_maski_state;
+               else
+                 iv_ctrl    <= reset_iv;
+	              next_state <= int_cwai_state;
+					end if;
+				 end if;
+
+			  when int_maski_state =>
+				 alu_ctrl   <= alu_sei;
+				 cc_ctrl    <= load_cc;
+             next_state <= vect_hi_state;
+
+			  when int_maskif_state =>
+			    alu_ctrl   <= alu_seif;
+				 cc_ctrl    <= load_cc;
+             next_state <= vect_hi_state;
+
+			  --
+			  -- According to the 6809 programming manual:
+			  -- If an interrupt is received and is masked 
+			  -- or lasts for less than three cycles, the PC 
+			  -- will advance to the next instruction.
+			  -- If an interrupt is unmasked and lasts
+			  -- for more than three cycles, an interrupt
+			  -- will be generated.
+			  -- Note that I don't wait 3 clock cycles.
+			  -- John Kent 11th July 2006
+			  --
+			  when sync_state =>
+			    if (nmi_req = '1') and (nmi_ack='0') then
+		  			iv_ctrl    <= nmi_iv;
+				   nmi_ctrl   <= set_nmi;
+               next_state <= int_nmiirq_state;
+			    else
+				   --
+					-- nmi request is not cleared until nmi input goes low
+					--
+				   if (nmi_req = '0') and (nmi_ack='1') then
+		  			  iv_ctrl  <= reset_iv;
+				     nmi_ctrl <= reset_nmi;
+					end if;
+					--
+					-- FIRQ is level sensitive
+					--
+               if (firq = '1') then
+					  if (cc(FBIT) = '0') then
+                   iv_ctrl    <= firq_iv;
+                   next_state <= int_firq_state;
+					  else
+                   iv_ctrl    <= reset_iv;
+			          next_state <= fetch_state;
+					  end if;
+					--
+					-- IRQ is level sensitive
+					--
+				   elsif (irq = '1') then
+					  if (cc(IBIT) = '0') then
+                   iv_ctrl    <= irq_iv;
+                   next_state <= int_nmiirq_state;
+					  else
+                   iv_ctrl    <= reset_iv;
+			          next_state <= fetch_state;
+					  end if;
+               else
+                 iv_ctrl    <= reset_iv;
+	              next_state <= sync_state;
+					end if;
+				 end if;
+
+
+			  when halt_state =>
+				 if halt = '1' then
+               next_state   <= halt_state;
+				 else
+				   next_state   <= fetch_state;
+				 end if;
+
+			  when others => -- halt on undefine states
+			    next_state <= error_state;
+		  end case;
+end process;
+
+end rtl;
+	
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dpram.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..672d33d3
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dpram.vhd	
@@ -0,0 +1,131 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram IS
+	GENERIC
+	(
+		init_file			: string := "";
+		--numwords_a		: natural;
+		widthad_a			: natural;
+		width_a				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED";
+    outdata_reg_b : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(width_a-1 DOWNTO 0);
+	q_b    <= sub_wire1(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		numwords_b => 2**widthad_a,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		outdata_reg_b => outdata_reg_a,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => widthad_a,
+		widthad_b => widthad_a,
+		width_a => width_a,
+		width_b => width_a,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dprom_2r.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dprom_2r.vhd
new file mode 100644
index 00000000..a17e0e58
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/dprom_2r.vhd	
@@ -0,0 +1,135 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dprom_2r IS
+	GENERIC
+	(
+		INIT_FILE			: string := "";
+		--NUMWORDS_A		: natural;
+		WIDTHAD_A			: natural;
+		WIDTH_A				: natural := 8;
+		--NUMWORDS_B		: natural;
+		WIDTHAD_B			: natural;
+		WIDTH_B				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED";
+    outdata_reg_b : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address_a		: in std_logic_vector (WIDTHAD_A-1 downto 0);
+		address_b		: in std_logic_vector (WIDTHAD_B-1 downto 0);
+		clock				: in std_logic ;
+		q_a					: out std_logic_vector (WIDTH_A-1 downto 0);
+		q_b					: out std_logic_vector (WIDTH_B-1 downto 0)
+	);
+END dprom_2r;
+
+
+ARCHITECTURE SYN OF dprom_2r IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3_bv	: BIT_VECTOR (WIDTH_A-1 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (WIDTH_B-1 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		init_file_layout		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		ram_block_type		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (WIDTHAD_A-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (WIDTHAD_B-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (WIDTH_A-1 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (WIDTH_B-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire2    <= '0';
+	sub_wire3_bv(WIDTH_A-1 DOWNTO 0) <= (others => '0');
+	sub_wire3    <= To_stdlogicvector(sub_wire3_bv);
+	sub_wire4_bv(WIDTH_B-1 DOWNTO 0) <= (others => '0');
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	q_a    <= sub_wire0(WIDTH_A-1 DOWNTO 0);
+	q_b    <= sub_wire1(WIDTH_B-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK0",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK0",
+		init_file => INIT_FILE,
+		init_file_layout => "PORT_A",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2**WIDTHAD_A,
+		numwords_b => 2**WIDTHAD_B,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		outdata_reg_b => outdata_reg_b,
+		power_up_uninitialized => "FALSE",
+		ram_block_type => "M9K",
+		widthad_a => WIDTHAD_A,
+		widthad_b => WIDTHAD_B,
+		width_a => WIDTH_A,
+		width_b => WIDTH_B,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK0"
+	)
+	PORT MAP (
+		wren_a => sub_wire2,
+		wren_b => sub_wire2,
+		clock0 => clock,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => sub_wire3,
+		data_b => sub_wire4,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+END SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/README.md b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/README.md
new file mode 100644
index 00000000..64469dad
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/README.md	
@@ -0,0 +1,109 @@
+# Cycle Accurate MC6809 Core
+
+## Details
+
+This is a Verilog implementation of the Motorola MC6809 and MC6809E microprocessors from late 1970s.  It is intentionally implemented in a manner to make it as similar as possible to the original microprocessors.
+
+When this was implemented, other 6809 cores already had been written.  These other cores were in use and had been verified.  Although I've never used any of these cores, I'm confident that they're excellent replications of the instruction set.  However, none (as far as I know) was verified to be cycle-accurate.  Encouragement from several sources (particularly one very generous source) convinced me to invest the time.
+
+Beyond merely cycle-accurate, the goal was to attempt to preserve as much of the actual bus signals and protocols as possible.  Signals such as DMABREQ, TSC, MRDY, and LIC, while infrequently used were still implemented.  Bus traffic was identified with a Logic Analyzer and matched to the 6809's specs (and, truthfully, when the specs were vague, details captured from hard MC6809/MC6809E part behavior).  The particulars in the Motorola specifications were replicated.
+
+The goal was cycle accuracy and that dictated much of the design. This was never intended to be a supercharged superset of a MC6809. If you're looking to mega-power your existing system, this might not be the best choice.  (Read the section on What This Is Not for explanation.)
+
+## Purpose, License
+
+I invested the time in the desire that *people use it*.  I haven't given away hardware designs or software since the 1980s.  However, this seems like a worthwhile exception.
+
+While the source is completely available, this is *not* an "open-source *group* project".  You may modify it as you see fit.  If you find errors, notifying me would be appreciated.  Still, this is **not** a group project.  I don't intend that to come off as rude quite so much as frank.  I may choose to modify the core in the future; many "open-source group projects" seem to me to become interesting social studies in design-by-commitee, and how much time is required just to manage multiple people with multiple inclinations becomes significant.  I confess that this scenario is not something that appeals to me. [Outside of a day job, I prefer to work with a very small and fairly private group.]  If you're enthusiastic or appreciative, use the core in a design and I'll be thrilled - tell me about it, and I'll explain to you how thrilled I am.  
+
+Refer to the [licensing](./documentation/LICENSE.md) requirements if you choose to leverage this work.
+
+This isn't an attempt to deal with part scarcity.  Any variant of 6809 is still quite easy to obtain (at darned cheap prices, too).  In truth, *far cheaper* than an FPGA.
+
+The actual target are people who are reimplementing retro-devices (Arcade games, Computers) that have incorporated entire designs into an FPGA, but require cycle accuracy.  The core's required space on an FPGA isn't overwhelming once you hit a certain range of parts and integration.  (If you're looking at CPLDs, you might want to scale up a bit.)
+
+## Implementation
+
+The core was implemented using Motorola's original documentation.  Particularly, **Figure 18** in the MC6809 and MC6809E datasheets.  There is a very close mapping between those five pages of diagrams and the bus and cycle activity of the CPU.  
+
+I have noticed that some repositories of HDL tend to be only slightly more organized than *people tossing HDL files "over the wall"*.  Explanations of how they work, how you as a consumer of the HDL should deal with it, etc. tend to be lacking or totally non-existent.
+
+I do have an interest (outside of this project) in HDL education; not quite in tutorials, but in implementations of HDMI, USB, SATA, etc. and explaining clearly how an implementation works - along with the hardware standard at the same time.  
+
+Please - if you're not experienced in an HDL already, this cpu core isn't likely very useful to you as a learning mechanism.  There are wonderful tutorials out there already; I highly recommend learning, experimenting, and so forth *first*, before attempting to absorb this design.
+
+## Validation
+
+The design was validated in multiple fashions, including against a Vectrex from 1982, a TRS-80 Color Computer 3, A slew of Williams Arcade games, and another wave of Taito Arcade games.  
+
+Literal bus compatibility was achieved using a [GODIL-40](http://www.oho-elektronik.de/) against the above scenarios. I can't say enough nice things about the [GODIL](http://www.oho-elektronik.de/) design.  Slick, compact.  It's darned nice work.  The only bad thing is that they're in short supply.  (Oh, and they're 10x-20x the price of a hard CPU.  I wouldn't recommend replacing your daily-use CPUs with a soft CPU in a GODIL unless you have a strong reason for doing so.)
+
+Functional testing was against the list of platforms above.  They all work.  
+
+Actual instruction cycle testing was done with the frequent help of Erik Gavriluk, who donated his time, consideration, and even hardware to the project.  In this case, MAME sports a cycle-accurate 6809 emulator; Erik generated code that ran (nearly) every instruction in every addressing mode, and then ran that through MAME and kept an absolute cycle count.  I captured the soft core's bus on a GODIL running the exact same code and matched the cycle counts.  To improve things, Erik provided me with the register contents after every instruction.  I wrote a testbench to run the same code and validated that the registers changed after each instruction identically in each scenario and in the exact same number of cycles. The result was gratifying.  (Ahem, once it worked.  Believe me, the CoCo, the cycle testing, the GODIL - they *all* pointed me at problems.  I won't claim that the design is flawless - nothing I've ever written truly is - but effort *has* been made to actually verify the thing, and I'll list each of the platforms and experiences.  [I'll even grumpily point out that Stargate has illegal instructions in it that they're darned lucky the 6809 happened to walk over.]
+
+Precise control signal testing (Interrupts, /HALT) were primarily done on JROK's Williams board.  The Williams arcade games had a blitter, and it used /HALT to gain the bus and take action.  JROK had done some extensive timing validation to prove that his implementation of the Williams design was **accurate**.  I contacted him and being as he's an incredibly nice person, he gave me some advice and access to his source + prebuilt binaries.  I was quite thankful - I found bus timing errors (related to /HALT and related to /IRQ latency) in the same vein (how many cycles before the next-new-instruction does each have to be asserted in order to be serviced at the beginning of the next instruction?) as a result.  A very worthwhile endeavor, as I'd been convinced that I was correct; however, his code led me to swap hard CPUs with my soft core on analyzer captures and to realize that despite my intention to match the documentation perfectly there were cases where the documentation left details unclear, requiring comparison between a hard CPU and my existing timing.
+
+## What This Is Not
+
+This isn't an attempt to deal with parts scarcity, nor prepare for it.  I can't imagine that 6809s will become *hard to get* in the next decade or so.  There isn't a ton of volume required and there are lots of warehouses from companies that make their entire businesses on out-of-production parts.
+
+This isn't an attempt to make a faster MC6809. The implementation would have been different had that been a goal. It has extensive 'dead' cycles on the bus to fit MC6809 specifications. If I conditionally remove them, it would be significantly more efficient than a real MC6809 (but once again, not cycle-accurate).
+
+This core does not include HD6309 instructions. I did check, and without the 'dead' cycles mentioned above (the things that make it cycle-accurate), every instruction is at least as efficient as the HD6309, and most are more efficient.  (I do have advantages of 40 years of technology over the original MC6809 design team, and at least 30 years over the HD6309 design team.)  New registers and instructions from the HD6309 aren't there.  Once again, that wasn't the goal.  [I may still enable a dynamic mechanism to switch between cycle-accurate and minimum-cycles-required as an instantiation parameter.]
+
+If your goal really is "a super 6809", I have [strong opinions](./documentation/super6809.md) on the topic.  
+
+## Perfection?
+
+While I'd love to say that this is a perfect replica, logic-level details of the implementation of the CPU aren't available.  The Motorola documentation is *excellent*, but still not complete.  
+
+I know of inconsistencies - but inconsistencies that I expect are trivial.  Anything deemed as serious has been dealt with as soon as I've been made aware of it.
+
+The instructions have been heavily validated, and I'm confident in their accuracy - but not quite so arrogant as to insist that there could not be an oversight.  (I'm not a young man any longer; I've been wrong too many times to be as remotely as confident as I was when I was 16.)
+
+Should issues be discovered, expect transparency and fixes - even if it's an incredibly rare edge case.  [If you're actively using `/DMABREQ`, please contact me.  You're the first.]
+
+## How does it work?
+
+This isn't quite the same question as the next, but if you really want to dig in and grasp the implementation, I've written a summary of the design [here](./documentation/CoreDesign.md).
+
+## How Do I Use It?
+
+### Samples
+
+Application of the core in a GODIL is provided.  With this, you can - although for what reason, I'm not sure - plug-replace a MC6809 or MC6809E in nearly any design (*note the oscillator in the Vectrex instead of the crystal*).  This is intended to demonstrate compatibility.
+
+A sample implementation is provided against a cheap Xilinx Spartan 6 LX9 board from eBay (China), a cheap Altera Cyclone IV EP4CE6 board (also from eBay, China), and two Cyclone V boards from terasic.  These aren't attempting to run at original speeds, so I set them to 25Mhz for no reason other than "I can".  These are intended to demonstrate use of the core entirely internal to an FPGA.
+
+### General Guidelines
+
+A list of general guidelines is provided.  They are likely worth reading if you consider using this core.
+
+## Documentation
+
+1. [Explanation of the CPU Core design.](./documentation/CoreDesign.md)
+2. [Validation Efforts.](./documentation/Validation.md)
+3. [Implementation Examples](./documentation/samples.md).
+
+## Who Am I?
+
+Despite a certain degree of desire to remain anonymous, that seems pointless in today's world. 
+
+My name is Greg Miller; I learned assembly in 1981 on a 6809 in a TRS-80 Color Computer, leaving me *fond* of this CPU architecture.  
+
+Not surprisingly, I work in the tech industry (although quite definitely not implementing legacy hardware in FPGAs), do not represent my employer in any capacity whatsoever here, and have a family and a mortgage.  
+
+You can contact me via:
+
+    gregmiller6809@gmail.com
+
+
+## Final Thoughts
+
+I'll keep track of my [Final Thoughts](./documentation/FinalThoughts.md) on the project.
+
+## Acknowledgements
+
+[I do want to thank a few people](documentation/Acknowledgements.md).
+
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809.v b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809.v
new file mode 100644
index 00000000..b19d1552
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809.v	
@@ -0,0 +1,80 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    08:11:34 09/23/2016 
+// Design Name: 
+// Module Name:    mc6809e 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mc6809(
+    input   [7:0] D,
+    output  [7:0] DOut,
+    output  [15:0] ADDR,
+    output  RnW,
+    output  E,
+    output  Q,
+    output  BS,
+    output  BA,
+    input   nIRQ,
+    input   nFIRQ,
+    input   nNMI,
+    input   EXTAL,
+    input   XTAL,
+    input   nHALT,	 
+    input   nRESET,
+    input   MRDY,
+    input   nDMABREQ
+    
+    , output  [111:0] RegData
+
+    );
+
+reg [1:0] clk_phase=2'b00;
+
+wire CLK;
+assign CLK=EXTAL;
+
+wire   LIC;
+wire   BUSY;
+wire   AVMA;
+reg    rE;
+reg    rQ;
+assign E = rE;
+assign Q = rQ;
+
+mc6809i cpucore(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), 
+                .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(nDMABREQ)
+                ,.RegData(RegData)
+                );
+
+always @(negedge CLK)
+begin
+    case (clk_phase)
+        2'b00:
+            rE <= 0;
+        2'b01:
+            rQ <= 1;
+        2'b10:
+            rE <= 1;
+        2'b11:
+            rQ <= 0;
+    endcase
+    
+    if (MRDY == 1'b1) 
+        clk_phase <= clk_phase + 2'b01;
+end
+
+
+endmodule
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809e.v b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809e.v
new file mode 100644
index 00000000..396a9fa3
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809e.v	
@@ -0,0 +1,48 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    08:11:34 09/23/2016 
+// Design Name: 
+// Module Name:    mc6809e 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mc6809e(
+    input   [7:0] D,
+    output  [7:0] DOut,
+    output  [15:0] ADDR,
+    output  RnW,
+    input   E,
+    input   Q,
+    output  BS,
+    output  BA,
+    input   nIRQ,
+    input   nFIRQ,
+    input   nNMI,
+    output  AVMA,
+    output  BUSY,
+    output  LIC,
+    input 	nHALT,	 
+    input   nRESET
+
+    );
+
+
+
+mc6809i cpucore (.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), 
+                .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(1)
+                );
+
+
+endmodule
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809i.v b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809i.v
new file mode 100644
index 00000000..5725aab4
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809i.v	
@@ -0,0 +1,4156 @@
+`timescale 1ns / 1ns
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: Greg Miller
+// Copyright (c) 2016, Greg Miller
+// 
+// Create Date:    14:26:59 08/13/2016 
+// Design Name: 
+// Module Name:    mc6809 
+// Project Name:   Cycle-Accurate 6809 Core 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: Intended to be standalone Vanilla Verilog.
+//
+// Revision: 
+// Revision 1.0 - Initial Release
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+//
+// The 6809 has incomplete instruction decoding.  A collection of instructions, if met, end up actually behaving like
+// a binary-adjacent neighbor.  
+//
+// The soft core permits three different behaviors for this situation, controlled by the instantiation parameter
+// ILLEGAL_INSTRUCTIONS
+//
+// "GHOST" - Mimic the 6809's incomplete decoding.  This is as similar to a hard 6809 as is practical.  [DEFAULT]
+//
+// "STOP"  - Cause the soft core to cease execution, placing $DEAD on the address bus and R/W to 'read'.  Interrupts,
+//           bus control (/HALT, /DMABREQ), etc. are ignored.  The core intentionally seizes in this instance.  
+//           (Frankly, this is useful when making changes to the core and you have a logic analyzer connected.)
+//
+// "IGNORE"- Cause the soft core to merely ignore illegal instructions.  It will consider them 1-byte instructions and
+//           attempt to fetch and run an exception 1 byte later.
+//
+
+module mc6809i
+#(
+    parameter ILLEGAL_INSTRUCTIONS="GHOST"
+) 
+(
+
+    input   [7:0]  D,
+    output  [7:0]  DOut,
+    output  [15:0] ADDR,
+    output  RnW,
+    input   E,
+    input   Q,
+    output  BS,
+    output  BA,
+    input   nIRQ,
+    input   nFIRQ,
+    input   nNMI,
+    output  AVMA,
+    output  BUSY,
+    output  LIC,
+    input   nHALT,
+    input   nRESET,
+    input   nDMABREQ,
+    output  [111:0] RegData
+);
+
+reg     [7:0]  DOutput;
+
+assign DOut = DOutput;
+
+reg     RnWOut;         // Combinatorial     
+
+reg     rLIC;
+assign LIC = rLIC;
+
+reg     rAVMA;
+assign AVMA = rAVMA;
+
+reg     rBUSY;
+assign BUSY = rBUSY;
+
+// Bus control
+// BS    BA
+//  0     0   normal (CPU running, CPU is master)
+//  0     1   Interrupt Ack
+//  1     0   Sync Ack
+//  1     1   CPU has gone high-Z on A, D, R/W
+//
+
+assign RnW = RnWOut;
+
+
+/////////////////////////////////////////////////
+// Vectors
+`define RESET_VECTOR        16'HFFFE
+`define NMI_VECTOR          16'HFFFC
+`define SWI_VECTOR          16'HFFFA
+`define IRQ_VECTOR          16'HFFF8
+`define FIRQ_VECTOR         16'HFFF6
+`define SWI2_VECTOR         16'HFFF4
+`define SWI3_VECTOR         16'HFFF2
+`define Reserved_VECTOR     16'HFFF0
+
+//////////////////////////////////////////////////////
+// Latched registers
+//
+
+// The last-latched copy.
+reg     [7:0]           a;
+reg     [7:0]           b;
+reg     [15:0]          x;
+reg     [15:0]          y;
+reg     [15:0]          u;
+reg     [15:0]          s;
+reg     [15:0]          pc;
+reg     [7:0]           dp;
+reg     [7:0]           cc;
+reg     [15:0]          tmp;
+reg     [15:0]          addr;
+reg     [15:0]          ea;
+
+
+// Debug ability to export register contents
+assign  RegData[7:0] = a;
+assign  RegData[15:8] = b;
+assign  RegData[31:16] = x;
+assign  RegData[47:32] = y;
+assign  RegData[63:48] = s;
+assign  RegData[79:64] = u;
+assign  RegData[87:80] = cc;
+assign  RegData[95:88] = dp;
+assign  RegData[111:96] = pc;
+
+
+
+// The values as being calculated
+reg     [7:0]           a_nxt;
+reg     [7:0]           b_nxt;
+reg     [15:0]          x_nxt;
+reg     [15:0]          y_nxt;
+reg     [15:0]          u_nxt;
+reg     [15:0]          s_nxt;
+reg     [15:0]          pc_nxt;
+reg     [7:0]           dp_nxt;
+reg     [7:0]           cc_nxt;
+reg     [15:0]          addr_nxt;
+reg     [15:0]          ea_nxt;
+reg     [15:0]          tmp_nxt;
+
+reg                     BS_nxt;
+reg                     BA_nxt;
+
+// for ADDR, BS/BA, assign them to the flops
+assign BS = BS_nxt;
+assign BA = BA_nxt;
+assign ADDR=addr_nxt;
+
+localparam CC_E=  8'H80;
+localparam CC_F=  8'H40;
+localparam CC_H=  8'H20;
+localparam CC_I=  8'H10;
+localparam CC_N=  8'H08;
+localparam CC_Z=  8'H04;
+localparam CC_V=  8'H02;
+localparam CC_C=  8'H01;
+
+localparam CC_E_BIT=  3'd7;
+localparam CC_F_BIT=  3'd6;
+localparam CC_H_BIT=  3'd5;
+localparam CC_I_BIT=  3'd4;
+localparam CC_N_BIT=  3'd3;
+localparam CC_Z_BIT=  3'd2;
+localparam CC_V_BIT=  3'd1;
+localparam CC_C_BIT=  3'd0;
+
+// Convenience calculations
+reg     [15:0] pc_p1;
+reg     [15:0] pc_p2;
+reg     [15:0] pc_p3;
+reg     [15:0] s_p1;
+reg     [15:0] s_m1;
+reg     [15:0] u_p1;
+reg     [15:0] u_m1;
+reg     [15:0] addr_p1;
+reg     [15:0] ea_p1;
+
+//////////////////////////////////////////////////////
+// NMI Mask
+//
+// NMI is supposed to be masked - despite the name - until the 6809 loads a value into S.
+// Frankly, I'm cheating slightly.  If someone does a LDS #$0, it won't disable the mask.  Pretty much anything else 
+// that changes the value of S from the default (which is currently $0) will clear the mask.  A reset will set the mask again.
+reg     NMIMask;
+
+reg     NMILatched;
+reg     NMISample;
+reg     NMISample2;
+reg     NMIClear;
+reg     NMIClear_nxt;
+wire    wNMIClear = NMIClear;
+
+reg     IRQLatched;
+
+reg     IRQSample;
+reg     IRQSample2;
+reg     FIRQLatched;
+reg     FIRQSample;
+reg     FIRQSample2;
+reg     HALTLatched;
+reg     HALTSample;
+reg     HALTSample2;
+reg     DMABREQLatched;
+reg     DMABREQSample;
+reg     DMABREQSample2;
+
+// Interrupt types
+localparam INTTYPE_NMI      = 3'H0 ;
+localparam INTTYPE_IRQ      = 3'H1 ;
+localparam INTTYPE_FIRQ     = 3'H2 ;
+localparam INTTYPE_SWI      = 3'H3 ;
+localparam INTTYPE_SWI2     = 3'H4 ;
+localparam INTTYPE_SWI3     = 3'H5 ;
+
+reg [2:0] IntType;
+reg [2:0] IntType_nxt;
+
+//////////////////////////////////////////////////////
+// Instruction Fetch Details
+//
+reg     InstPage2;
+reg     InstPage3;
+reg     InstPage2_nxt;
+reg     InstPage3_nxt;
+
+reg     [7:0]        Inst1;
+reg     [7:0]        Inst2;
+reg     [7:0]        Inst3;
+reg     [7:0]        Inst1_nxt;
+reg     [7:0]        Inst2_nxt;
+reg     [7:0]        Inst3_nxt;
+
+
+localparam CPUSTATE_RESET      =  7'd0;
+localparam CPUSTATE_RESET0     =  7'd1;
+
+localparam CPUSTATE_RESET2     =  7'd3;
+localparam CPUSTATE_FETCH_I1   =  7'd4;
+localparam CPUSTATE_FETCH_I1V2 =  7'd5;     
+localparam CPUSTATE_FETCH_I2   =  7'd8;
+
+localparam CPUSTATE_LBRA_OFFSETLOW =  7'd17;
+localparam CPUSTATE_LBRA_DONTCARE  =  7'd18;
+localparam CPUSTATE_LBRA_DONTCARE2 =  7'd19;
+
+
+
+localparam CPUSTATE_BRA_DONTCARE   =  7'd20;
+
+localparam CPUSTATE_BSR_DONTCARE1  =  7'd21;
+localparam CPUSTATE_BSR_DONTCARE2  =  7'd22;
+localparam CPUSTATE_BSR_RETURNLOW  =  7'd23;
+localparam CPUSTATE_BSR_RETURNHIGH =  7'd24;
+
+localparam CPUSTATE_TFR_DONTCARE1  =  7'd26;
+localparam CPUSTATE_TFR_DONTCARE2  =  7'd27;
+localparam CPUSTATE_TFR_DONTCARE3  =  7'd28;
+localparam CPUSTATE_TFR_DONTCARE4  =  7'd29;
+
+localparam CPUSTATE_EXG_DONTCARE1      =    7'd30;
+localparam CPUSTATE_EXG_DONTCARE2      =    7'd31;
+localparam CPUSTATE_EXG_DONTCARE3      =    7'd32;
+localparam CPUSTATE_EXG_DONTCARE4      =    7'd33;
+localparam CPUSTATE_EXG_DONTCARE5      =    7'd34;
+localparam CPUSTATE_EXG_DONTCARE6      =    7'd35;
+
+localparam CPUSTATE_ABX_DONTCARE       =    7'd36;
+
+localparam  CPUSTATE_RTS_HI            =    7'd38;
+localparam  CPUSTATE_RTS_LO            =    7'd39;     
+localparam  CPUSTATE_RTS_DONTCARE2     =    7'd40;          
+
+localparam  CPUSTATE_16IMM_LO          =    7'd41;
+localparam CPUSTATE_ALU16_DONTCARE     =    7'd42;
+localparam CPUSTATE_DIRECT_DONTCARE    =    7'd43;
+
+localparam CPUSTATE_ALU_EA             =    7'd44;
+
+localparam CPUSTATE_ALU_DONTCARE       =    7'd46;
+localparam CPUSTATE_ALU_WRITEBACK      =    7'd47;
+
+localparam CPUSTATE_LD16_LO            =    7'd48;
+
+localparam CPUSTATE_ST16_LO            =    7'd49;
+localparam CPUSTATE_ALU16_LO           =    7'd50;
+
+
+
+
+localparam CPUSTATE_JSR_DONTCARE       =    7'd53;
+localparam CPUSTATE_JSR_RETLO          =    7'd54;
+localparam CPUSTATE_JSR_RETHI          =    7'd55;      
+localparam CPUSTATE_EXTENDED_ADDRLO    =    7'd56;
+localparam CPUSTATE_EXTENDED_DONTCARE  =    7'd57;      
+localparam CPUSTATE_INDEXED_BASE       =    7'd58;                
+
+
+localparam CPUSTATE_IDX_DONTCARE3      =    7'd60;
+
+localparam CPUSTATE_IDX_OFFSET_LO      =    7'd61;
+localparam CPUSTATE_IDX_16OFFSET_LO    =    7'd62;
+
+localparam CPUSTATE_IDX_16OFF_DONTCARE0=    7'd63;
+localparam CPUSTATE_IDX_16OFF_DONTCARE1=    7'd64;
+localparam CPUSTATE_IDX_16OFF_DONTCARE2=    7'd65;
+localparam CPUSTATE_IDX_16OFF_DONTCARE3=    7'd66;
+
+localparam CPUSTATE_IDX_DOFF_DONTCARE1 =    7'd68;
+localparam CPUSTATE_IDX_DOFF_DONTCARE2 =    7'd69;
+localparam CPUSTATE_IDX_DOFF_DONTCARE3 =    7'd70;
+localparam CPUSTATE_IDX_PC16OFF_DONTCARE =  7'd71;
+
+localparam CPUSTATE_IDX_EXTIND_LO =         7'd72;
+localparam CPUSTATE_IDX_EXTIND_DONTCARE =   7'd73;
+
+localparam CPUSTATE_INDIRECT_HI         =   7'd74;
+localparam CPUSTATE_INDIRECT_LO         =   7'd75;
+localparam CPUSTATE_INDIRECT_DONTCARE   =   7'd76;
+localparam CPUSTATE_MUL_ACTION          =   7'd77;
+
+localparam CPUSTATE_PSH_DONTCARE1       =   7'd80;
+localparam CPUSTATE_PSH_DONTCARE2       =   7'd81;
+localparam CPUSTATE_PSH_DONTCARE3       =   7'd82;
+localparam CPUSTATE_PSH_ACTION          =   7'd83;
+
+localparam CPUSTATE_PUL_DONTCARE1       =   7'd84;
+localparam CPUSTATE_PUL_DONTCARE2       =   7'd85;
+localparam CPUSTATE_PUL_ACTION          =   7'd86;
+
+localparam CPUSTATE_NMI_START           =   7'd87;
+localparam CPUSTATE_IRQ_DONTCARE        =   7'd88;
+localparam CPUSTATE_IRQ_START           =   7'd89;
+localparam CPUSTATE_IRQ_DONTCARE2       =   7'd90;
+localparam CPUSTATE_IRQ_VECTOR_HI       =   7'd91;
+localparam CPUSTATE_IRQ_VECTOR_LO       =   7'd92;
+localparam CPUSTATE_FIRQ_START          =   7'd93;
+localparam CPUSTATE_CC_DONTCARE         =   7'd94;
+localparam CPUSTATE_SWI_START           =   7'd95;
+
+localparam CPUSTATE_TST_DONTCARE1       =   7'd96;
+localparam CPUSTATE_TST_DONTCARE2       =   7'd97;
+
+localparam CPUSTATE_DEBUG               =   7'd98;
+
+localparam CPUSTATE_16IMM_DONTCARE      =   7'd99;
+
+localparam CPUSTATE_HALTED              =  7'd100;
+
+localparam CPUSTATE_HALT_EXIT2          =  7'd102;
+localparam CPUSTATE_STOP                =  7'd105;
+localparam CPUSTATE_STOP2               =  7'd106;
+localparam CPUSTATE_STOP3               =  7'd107;
+
+
+localparam CPUSTATE_CWAI                =  7'd108;
+localparam CPUSTATE_CWAI_DONTCARE1      =  7'd109;
+localparam CPUSTATE_CWAI_POST           =  7'd110;
+
+localparam CPUSTATE_DMABREQ             =  7'd111;
+localparam CPUSTATE_DMABREQ_EXIT        =  7'd112;
+localparam CPUSTATE_SYNC                =  7'd113;
+localparam CPUSTATE_SYNC_EXIT           =  7'd114;
+
+localparam CPUSTATE_INT_DONTCARE        =  7'd115;
+
+
+reg     [6:0]    CpuState = CPUSTATE_RESET;
+reg     [6:0]    CpuState_nxt = CPUSTATE_RESET;
+
+reg     [6:0]    NextState = CPUSTATE_RESET;
+reg     [6:0]    NextState_nxt = CPUSTATE_RESET;
+
+wire    [6:0]    PostIllegalState;
+
+// If we encounter something like an illegal addressing mode (an index mode that's illegal for instance)
+// What state should we go to?
+generate
+if (ILLEGAL_INSTRUCTIONS=="STOP")
+begin : postillegal
+    assign PostIllegalState = CPUSTATE_STOP; 
+end
+else
+begin
+    assign PostIllegalState = CPUSTATE_FETCH_I1;
+end
+endgenerate
+
+
+
+///////////////////////////////////////////////////////////////////////
+
+//
+// MapInstruction - Considering how the core was instantiated, this 
+// will either directly return D[7:0] *or* remap values from D[7:0] 
+// that relate to undefined instructions in the 6809 to the instructions
+// that the 6809 actually executed when these were encountered, due to
+// incomplete decoding.
+//
+// NEG, COM, LSR, DEC - these four instructions, in Direct, Inherent (A or B)
+// Indexed, or Extended addressing do not actually decode bit 0 on the instruction.
+// Thus, for instance, a $51 encountered will be executed as a $50, which is a NEGB.
+//
+
+// Specifically, the input is an instruction; if it matches an unknown instruction that the 
+// 6809 is known to ghost to another instruction, the output of the function 
+// is the the instruction that actually gets executed.  Otherwise, the output is the 
+// input.
+
+function [7:0] MapInstruction(input [7:0] i);
+reg [3:0] topnyb;
+reg [3:0] btmnyb;
+reg [7:0] newinst;
+begin
+    newinst = i;
+    
+    topnyb = i[7:4];
+    btmnyb = i[3:0];
+    
+    if ( (topnyb == 4'H0) || 
+         (topnyb == 4'H4) || 
+         (topnyb == 4'H5) || 
+         (topnyb == 4'H6) ||
+         (topnyb == 4'H7) 
+        )
+    begin
+        if (btmnyb == 4'H1)
+            newinst = {topnyb, 4'H0};
+        if (btmnyb == 4'H2)
+            newinst = {topnyb, 4'H3};
+        if (btmnyb == 4'H5)
+            newinst = {topnyb, 4'H4};
+        if (btmnyb == 4'HB)
+            newinst = {topnyb, 4'HA};
+    end
+    MapInstruction = newinst;
+end
+endfunction
+
+
+wire [7:0] MappedInstruction;
+generate
+if (ILLEGAL_INSTRUCTIONS=="GHOST")
+begin : ghost
+    assign MappedInstruction = MapInstruction(D);  
+end
+else
+begin
+    assign MappedInstruction = D;
+end
+endgenerate
+
+
+
+///////////////////////////////////////////////////////////////////////
+
+function IllegalInstruction(input [7:0] i);
+reg [3:0] hi;
+reg [3:0] lo;
+reg       illegal;
+begin
+    illegal = 1'b0;
+    hi = i[7:4];
+    lo = i[3:0];
+    if ( (hi == 4'H0) || (hi == 4'H4) || (hi == 4'H5) || (hi == 4'H6) || (hi == 4'H7) )
+    begin
+        if ( (lo == 4'H1) || (lo == 4'H2) || (lo == 4'H5) || (lo == 4'HB) )
+            illegal = 1'b1;
+        if (lo == 4'HE)
+            if ( (hi == 4'H4) || (hi == 4'H5) )
+                illegal = 1'b1;
+    end
+    if (hi == 4'H3)
+    begin
+        if ( (lo == 4'H8) || (lo == 4'HE) )
+            illegal = 1'b1;
+    end
+    if (hi == 4'H1)
+    begin
+        if ( (lo == 4'H4) || (lo == 4'H5) || (lo == 4'H8) || (lo == 4'HB) )
+            illegal = 1'b1;
+    end
+    if ( (hi == 4'H8) || (hi == 4'HC) )
+    begin
+        if ( (lo == 4'H7) || (lo == 4'HF) )
+            illegal = 1'b1;
+        if ( lo == 4'HD )
+            if (hi == 4'HC)
+                illegal = 1'b1;
+    end
+    IllegalInstruction = illegal;
+end
+endfunction
+
+wire IsIllegalInstruction;
+
+generate
+if (ILLEGAL_INSTRUCTIONS=="GHOST")
+begin : never_illegal
+    assign IsIllegalInstruction = 1'b0; 
+end
+else
+begin
+    assign IsIllegalInstruction = IllegalInstruction(Inst1);
+end
+endgenerate
+
+wire [6:0] IllegalInstructionState;
+generate
+if (ILLEGAL_INSTRUCTIONS=="IGNORE")
+begin : illegal_state
+    assign IllegalInstructionState = CPUSTATE_FETCH_I1;
+end
+else if (ILLEGAL_INSTRUCTIONS=="STOP")
+begin
+    assign IllegalInstructionState = CPUSTATE_STOP;
+end
+else
+begin
+    assign IllegalInstructionState = 7'd0;
+end
+endgenerate
+
+
+///////////////////////////////////////////////////////////////////////
+
+
+always @(negedge NMISample2 or posedge wNMIClear)
+begin
+    if (wNMIClear == 1)
+        NMILatched <= 1;
+    else if (NMIMask == 0)
+        NMILatched <= 0;
+    else
+        NMILatched <= 1;
+end
+
+//
+// The 6809 specs say that the CPU control signals are sampled on the falling edge of Q.
+// It also says that the interrupts require 1 cycle of synchronization time.  
+// That's vague, as it doesn't say where "1 cycle" starts or ends.  Starting from the
+// falling edge of Q, the next cycle notices an assertion.  From checking a hard 6809 on
+// an analyzer, what they really mean is that it's sampled on the falling edge of Q, 
+// but there's a one cycle delay from the falling edge of E (0.25 clocks from the falling edge of Q
+// where the signals were sampled) before it can be noticed.  
+// So, SIGNALSample is the latched value at the falling edge of Q
+//     SIGNALSample2 is the latched value at the falling edge of E (0.25 clocks after the line above)
+//     SIGNALLatched is the latched value at the falling edge of E (1 cycle after the line above)
+//
+// /HALT and /DMABREQ are delayed one cycle less than interrupts.  The 6809 specs infer these details,
+// but don't list the point-of-reference they're written from (for instance, they say that an interrupt requires
+// a cycle for synchronization; however, it isn't clear whether that's from the falling Q to the next falling Q,
+// a complete intermediate cycle, the falling E to the next falling E, etc.) - which, in the end, required an
+// analyzer on the 6809 to determine how many cycles before a new instruction an interrupt (or /HALT & /DMABREQ)
+// had to be asserted to be noted instead of the next instruction running start to finish.  
+// 
+always @(negedge Q)
+begin
+    NMISample <= nNMI;
+    
+    IRQSample <= nIRQ;
+
+    FIRQSample <= nFIRQ;
+
+    HALTSample <= nHALT;
+    
+    DMABREQSample <= nDMABREQ;
+
+        
+end
+
+
+reg rnRESET=0; // The latched version of /RESET, useful 1 clock after it's latched
+always @(negedge E)
+begin
+    rnRESET <= nRESET;
+    
+    NMISample2 <= NMISample;
+    
+    IRQSample2 <= IRQSample;
+    IRQLatched <= IRQSample2;
+
+    FIRQSample2 <= FIRQSample;
+    FIRQLatched <= FIRQSample2;
+
+    HALTSample2 <= HALTSample;
+    HALTLatched <= HALTSample2;
+
+    DMABREQSample2 <= DMABREQSample;
+    DMABREQLatched <= DMABREQSample2;
+
+
+    if (rnRESET == 1)
+    begin
+        CpuState <= CpuState_nxt;
+        
+        // Don't interpret this next item as "The Next State"; it's a special case 'after this 
+        // generic state, go to this programmable state', so that a single state 
+        // can be shared for many tasks. [Specifically, the stack push/pull code, which is used
+        // for PSH, PUL, Interrupts, RTI, etc.
+        NextState <= NextState_nxt;
+         
+        // CPU registers latch from the combinatorial circuit
+        a <= a_nxt;
+        b <= b_nxt;
+        x <= x_nxt;
+        y <= y_nxt;
+        s <= s_nxt;
+        u <= u_nxt;
+        cc <= cc_nxt;
+        dp <= dp_nxt;
+        pc <= pc_nxt;
+        tmp <= tmp_nxt;
+        addr <= addr_nxt;
+        ea <= ea_nxt;
+        
+        InstPage2 <= InstPage2_nxt;
+        InstPage3 <= InstPage3_nxt;
+        Inst1 <= Inst1_nxt;
+        Inst2 <= Inst2_nxt;
+        Inst3 <= Inst3_nxt;
+        NMIClear <= NMIClear_nxt;
+        
+        IntType <= IntType_nxt;
+        
+        if (s != s_nxt)                 // Once S changes at all (default is '0'), release the NMI Mask.
+            NMIMask <= 1'b0;
+    end
+    else
+    begin
+        CpuState <= CPUSTATE_RESET; 
+        NMIMask <= 1'b1; // Mask NMI until S is loaded.
+        NMIClear <= 1'b0; // Mark us as not having serviced NMI
+    end
+end
+
+
+/////////////////////////////////////////////////////////////////
+// Decode the Index byte
+
+localparam IDX_REG_X   =  3'd0;
+localparam IDX_REG_Y   =  3'd1;
+localparam IDX_REG_U   =  3'd2;
+localparam IDX_REG_S   =  3'd3;
+localparam IDX_REG_PC  =  3'd4;
+
+localparam IDX_MODE_POSTINC1   =  4'd0;
+localparam IDX_MODE_POSTINC2   =  4'd1;
+localparam IDX_MODE_PREDEC1    =  4'd2;
+localparam IDX_MODE_PREDEC2    =  4'd3;
+localparam IDX_MODE_NOOFFSET   =  4'd4;
+localparam IDX_MODE_B_OFFSET   =  4'd5;
+localparam IDX_MODE_A_OFFSET   =  4'd6;
+localparam IDX_MODE_5BIT_OFFSET=  4'd7;    // Special case, not bit pattern 7; the offset sits in the bit pattern
+localparam IDX_MODE_8BIT_OFFSET=  4'd8;
+localparam IDX_MODE_16BIT_OFFSET   =  4'd9;
+localparam IDX_MODE_D_OFFSET       =  4'd11;
+localparam IDX_MODE_8BIT_OFFSET_PC =  4'd12;
+localparam IDX_MODE_16BIT_OFFSET_PC=  4'd13;
+localparam IDX_MODE_EXTENDED_INDIRECT  =  4'd15;
+
+// Return:
+//     Register base [3 bits]
+//     Indirect      [1 bit]
+//     Mode          [4 bits]
+
+function [7:0] IndexDecode(input   [7:0] postbyte);
+reg     [2:0]  regnum;
+reg     indirect;
+reg     [3:0]  mode;
+begin
+    indirect   =  0;
+    mode       =  0;
+    
+    if (postbyte[7] == 0)           // 5-bit
+    begin
+        mode   =  IDX_MODE_5BIT_OFFSET;
+    end
+    else
+    begin
+        mode   =  postbyte[3:0];
+        indirect   =  postbyte[4];
+    end            
+    if ((mode != IDX_MODE_8BIT_OFFSET_PC) && (mode != IDX_MODE_16BIT_OFFSET_PC))
+        regnum[2:0]    =  postbyte[6:5];
+    else
+        regnum[2:0]    =  IDX_REG_PC;
+    
+    IndexDecode    =  {indirect, mode, regnum};
+end
+endfunction
+
+wire    [3:0]  IndexedMode;
+wire    IndexedIndirect;
+wire    [2:0]  IndexedRegister;
+
+assign  {IndexedIndirect, IndexedMode, IndexedRegister}    =  IndexDecode(Inst2);
+
+/////////////////////////////////////////////////////////////////
+// Is this a JMP instruction?  (irrespective of addressing mode)
+function IsJMP(input   [7:0] inst);
+reg     [3:0] hi;
+reg     [3:0] lo;
+begin
+    hi =  inst[7:4];
+    lo =  inst[3:0];
+    
+    IsJMP  =  0;
+    if ((hi == 4'H0) || (hi == 4'H6) || (hi == 4'H7))
+        if (lo == 4'HE)
+            IsJMP  =  1;
+end
+endfunction
+
+///////////////////////////////////////////////////////////////////
+// Is this an 8-bit Store?
+
+localparam ST8_REG_A   =  1'b0;
+localparam ST8_REG_B   =  1'b1;
+
+function [1:0] IsST8(input   [7:0] inst);
+reg     regnum;
+reg     IsStore;
+begin
+    
+    IsStore        =  1'b0;
+    regnum =  1'b1;
+    
+    if ( (Inst1 == 8'H97) || (Inst1 == 8'HA7) || (Inst1 == 8'HB7) )
+    begin
+        IsStore    =  1'b1;
+        regnum     =  1'b0;
+    end
+    else if ( (Inst1 == 8'HD7) || (Inst1 == 8'HE7) || (Inst1 == 8'HF7) )
+    begin
+        IsStore    =  1'b1;
+        regnum     =  1'b1;
+    end
+    IsST8  =  {IsStore, regnum};
+end
+endfunction
+
+wire    IsStore8;
+wire    Store8RegisterNum;
+
+assign  {IsStore8, Store8RegisterNum}  =  IsST8(Inst1);        
+
+
+/////////////////////////////////////////////////////////////////
+// Is this a 16-bit Store?
+
+localparam ST16_REG_X  =  3'd0;
+localparam ST16_REG_Y  =  3'd1;
+localparam ST16_REG_U  =  3'd2;
+localparam ST16_REG_S  =  3'd3;
+localparam ST16_REG_D  =  3'd4;
+
+
+function [3:0] IsST16(input   [7:0] inst);
+reg     [3:0] hi;
+reg     [3:0] lo;
+reg     [2:0] regnum;
+reg     IsStore;
+begin
+    hi =  inst[7:4];
+    lo =  inst[3:0];
+    IsStore    =  1'b0;
+    regnum     =  3'b111;
+    
+    if ((inst == 8'H9F) || (inst == 8'HAF) || (inst == 8'HBF))
+    begin
+        IsStore    =  1;
+        if (~InstPage2)
+            regnum =  ST16_REG_X;
+        else
+            regnum =  ST16_REG_Y;
+    end
+    else if ((inst == 8'HDF) || (inst == 8'HEF) || (inst == 8'HFF))
+    begin
+        IsStore        =  1;
+        if (~InstPage2)
+            regnum =  ST16_REG_U;
+        else
+            regnum =  ST16_REG_S;
+    end
+    else if ((inst == 8'HDD) || (inst == 8'HED) || (inst == 8'HFD))
+    begin
+        IsStore        =  1;
+        regnum =  ST16_REG_D;
+    end
+    
+    IsST16 =  {IsStore, regnum};
+end
+endfunction
+
+wire    IsStore16;
+wire    [2:0] StoreRegisterNum;
+
+assign  {IsStore16, StoreRegisterNum}  =  IsST16(Inst1);
+
+/////////////////////////////////////////////////////////////////
+// Is this a special Immediate mode instruction, ala
+// PSH, PUL, EXG, TFR, ANDCC, ORCC
+function IsSpecialImm(input   [7:0] inst);
+reg     is;
+reg     [3:0] hi;
+reg     [3:0] lo;
+begin
+    hi =  inst[7:4];
+    lo =  inst[3:0];
+    is =  0;
+    
+    if (hi == 4'H1)
+    begin
+        if ( (lo == 4'HA) || (lo == 4'HC) || (lo == 4'HE) || (lo == 4'HF) )     // ORCC, ANDCC, EXG, TFR
+            is =  1;
+    end
+    else if (hi == 4'H3)
+    begin
+        if ( (lo >= 4'H3) && (lo <= 4'H7) )     // PSHS, PULS, PSHU, PULU
+            is =  1;
+    end
+    else
+        is =  0;
+    
+    IsSpecialImm   =  is;
+end
+endfunction
+wire    IsSpecialImmediate =  IsSpecialImm(Inst1);
+
+/////////////////////////////////////////////////////////////////
+// Is this a one-byte instruction?  [The 6809 reads 2 bytes for every instruction, minimum (it can read more).  On a one-byte, we have to ensure that we haven't skipped the PC ahead.
+function IsOneByteInstruction(input   [7:0] inst);
+reg     is;
+reg     [3:0] hi;
+reg     [3:0] lo;
+begin
+    hi =  inst[7:4];
+    lo =  inst[3:0];
+    is = 1'b0;
+    
+    if ( (hi == 4'H4) || (hi == 4'H5) )
+        is =  1'b1;
+    else if ( hi == 4'H1)
+    begin
+        if ( (lo == 4'H2) || (lo == 4'H3) || (lo == 4'H9) || (lo == 4'HD) )
+            is =  1'b1;
+    end
+    else if (hi == 4'H3)
+    begin
+        if ( (lo >= 4'H9) && (lo != 4'HC) )
+            is =  1'b1;
+    end
+    else
+        is =  1'b0;
+    
+    IsOneByteInstruction   =  is;           
+end
+endfunction 
+
+/////////////////////////////////////////////////////////////////
+// ALU16 - Simpler than the 8 bit ALU
+
+localparam ALU16_REG_X =  3'd0;
+localparam ALU16_REG_Y =  3'd1;
+localparam ALU16_REG_U =  3'd2;
+localparam ALU16_REG_S =  3'd3;
+localparam ALU16_REG_D =  3'd4;
+
+function [2:0] ALU16RegFromInst(input   Page2, input   Page3, input   [7:0] inst);
+reg     [2:0] srcreg;
+begin
+    srcreg =  3'b111;       // default
+    casex ({Page2, Page3, inst}) // Note pattern for the matching below
+        10'b1010xx0011:         // 1083, 1093, 10A3, 10B3 CMPD 
+            srcreg =  ALU16_REG_D;
+        10'b1010xx1100:         // 108C, 109C, 10AC, 10BC CMPY
+            srcreg =  ALU16_REG_Y;
+        10'b0110xx0011:         // 1183, 1193, 11A3, 11B3 CMPU
+            srcreg =  ALU16_REG_U;
+        10'b0110xx1100:         // 118C, 119C, 11AC, 11BC CMPS
+            srcreg =  ALU16_REG_S;
+        10'b0010xx1100:         // 8C,9C,AC,BC CMPX
+            srcreg =  ALU16_REG_X;
+        
+        10'b0011xx0011:         // C3, D3, E3, F3 ADDD
+            srcreg =  ALU16_REG_D;
+        
+        10'b0011xx1100:         // CC, DC, EC, FC LDD
+            srcreg =  ALU16_REG_D;            
+        10'b0010xx1110:         // 8E LDX, 9E LDX, AE LDX, BE LDX
+            srcreg =  ALU16_REG_X;
+        10'b0011xx1110:         // CE LDU, DE LDU, EE LDU, FE LDU
+            srcreg =  ALU16_REG_U;        
+        10'b1010xx1110:         // 108E LDY, 109E LDY, 10AE LDY, 10BE LDY
+            srcreg =  ALU16_REG_Y;
+        10'b1011xx1110:         // 10CE LDS, 10DE LDS, 10EE LDS, 10FE LDS
+            srcreg =  ALU16_REG_S;               
+        10'b0010xx0011:         // 83, 93, A3, B3 SUBD
+            srcreg =  ALU16_REG_D;
+        
+        10'H03A:                // 3A ABX
+            srcreg =  ALU16_REG_X;
+        10'H030:                // 30 LEAX
+            srcreg =  ALU16_REG_X;
+        10'H031:                // 31 LEAY
+            srcreg =  ALU16_REG_Y;
+        10'H032:                // 32 LEAS
+            srcreg =  ALU16_REG_S;
+        10'H033:                // 32 LEAU
+            srcreg =  ALU16_REG_U;
+        default:
+            srcreg =  3'b111;
+    endcase
+    ALU16RegFromInst   =  srcreg;
+end
+endfunction
+
+wire    [2:0] ALU16Reg     =  ALU16RegFromInst(InstPage2, InstPage3, Inst1);
+
+localparam  ALUOP16_SUB        =  3'H0;
+localparam  ALUOP16_ADD        =  3'H1;
+localparam  ALUOP16_LD         =  3'H2;
+localparam  ALUOP16_CMP        =  3'H3;
+localparam  ALUOP16_LEA        =  3'H4;
+localparam  ALUOP16_INVALID    =  3'H7;
+
+function [3:0] ALU16OpFromInst(input   Page2, input   Page3, input   [7:0] inst);
+reg     [2:0] aluop;
+reg     writeback;
+begin
+    aluop  =  3'b111;
+    writeback  =  1'b1;
+    casex ({Page2, Page3, inst})
+        10'b1010xx0011:         // 1083, 1093, 10A3, 10B3 CMPD
+        begin 
+            aluop  =  ALUOP16_CMP;
+            writeback  =  1'b0;
+        end                
+        10'b1010xx1100:         // 108C, 109C, 10AC, 10BC CMPY
+        begin 
+            aluop      =  ALUOP16_CMP;
+            writeback  =  1'b0;
+        end                
+        10'b0110xx0011:         // 1183, 1193, 11A3, 11B3 CMPU
+        begin 
+            aluop      =  ALUOP16_CMP;
+            writeback  =  1'b0;
+        end                
+        10'b0110xx1100:         // 118C, 119C, 11AC, 11BC CMPS
+        begin 
+            aluop      =  ALUOP16_CMP;
+            writeback  =  1'b0;
+        end                
+        10'b0010xx1100:         // 8C,9C,AC,BC CMPX
+        begin 
+            aluop      =  ALUOP16_CMP;
+            writeback  =  1'b0;
+        end                
+        
+        10'b0011xx0011:         // C3, D3, E3, F3 ADDD
+            aluop  =  ALUOP16_ADD;
+        
+        10'b0011xx1100:         // CC, DC, EC, FC LDD
+            aluop  =  ALUOP16_LD;                
+        10'b001xxx1110:         // 8E LDX, 9E LDX, AE LDX, BE LDX, CE LDU, DE LDU, EE LDU, FE LDU
+            aluop  =  ALUOP16_LD;
+        10'b101xxx1110:         // 108E LDY, 109E LDY, 10AE LDY, 10BE LDY, 10CE LDS, 10DE LDS, 10EE LDS, 10FE LDS
+            aluop  =  ALUOP16_LD;
+        
+        10'b0010xx0011:         // 83, 93, A3, B3 SUBD
+            aluop  =  ALUOP16_SUB;
+        
+        10'H03A:                // 3A ABX
+            aluop  =  ALUOP16_ADD;
+        
+        10'b00001100xx:         // $30-$33, LEAX, LEAY, LEAS, LEAU
+            aluop  =  ALUOP16_LEA;
+
+        default:
+            aluop  =  ALUOP16_INVALID;
+    endcase
+    ALU16OpFromInst    =  {writeback, aluop};
+end
+endfunction
+
+wire    ALU16OpWriteback;
+wire    [2:0]  ALU16Opcode;
+
+assign  {ALU16OpWriteback, ALU16Opcode}    =  ALU16OpFromInst(InstPage2, InstPage3, Inst1);  
+
+wire    IsALU16Opcode  =  (ALU16Opcode != 3'b111);          
+
+function [23:0] ALU16Inst(input   [2:0] operation16, input   [15:0] a_arg, input   [15:0] b_arg, input   [7:0] cc_arg);
+reg     [7:0]    cc_out;
+reg     [15:0]   ALUFn;
+reg     carry;
+reg     borrow;
+begin
+    cc_out =  cc_arg;
+    case (operation16)
+        ALUOP16_ADD:
+        begin
+            {cc_out[CC_C_BIT], ALUFn} =  {1'b0, a_arg} + b_arg;
+            cc_out[CC_V_BIT]   =  (a_arg[15] & b_arg[15] & ~ALUFn[15]) | (~a_arg[15] & ~b_arg[15] & ALUFn[15]);
+        end
+        
+        ALUOP16_SUB:
+        begin
+            {cc_out[CC_C_BIT], ALUFn} =  {1'b0, a_arg} - {1'b0, b_arg};
+            cc_out[CC_V_BIT]   =  (a_arg[15] & ~b_arg[15] & ~ALUFn[15]) | (~a_arg[15] & b_arg[15] & ALUFn[15]);
+        end
+        
+        ALUOP16_LD:
+        begin
+            ALUFn  =  b_arg;
+            cc_out[CC_V_BIT]   =  1'b0;
+        end
+        
+        ALUOP16_CMP:
+        begin
+            {cc_out[CC_C_BIT], ALUFn} =  {1'b0, a_arg} - {1'b0, b_arg};
+            cc_out[CC_V_BIT]   =  (a_arg[15] & ~b_arg[15] & ~ALUFn[15]) | (~a_arg[15] & b_arg[15] & ALUFn[15]);
+        end
+        
+        ALUOP16_LEA:
+        begin
+            ALUFn  =  a_arg;
+        end
+        
+        default:
+            ALUFn = 16'H0000;
+        
+    endcase
+    cc_out[CC_Z_BIT]   =  (ALUFn[15:0] == 16'H0000);
+    if (operation16 != ALUOP16_LEA)
+        cc_out[CC_N_BIT]   =  ALUFn[15];
+    ALU16Inst  =  {cc_out, ALUFn};
+end
+endfunction
+
+reg     [2:0]   ALU16_OP;
+reg     [15:0]  ALU16_A;
+reg     [15:0]  ALU16_B;
+reg     [7:0]   ALU16_CC;     
+
+// Top 8 bits == CC, bottom 8 bits = output value
+wire    [23:0] ALU16   =  ALU16Inst(ALU16_OP, ALU16_A, ALU16_B, ALU16_CC);
+
+
+/////////////////////////////////////////////////////////////////
+// ALU
+
+// The ops are organized from the 4 low-order bits of the instructions for the first set of ops, then 16-31 are the second set - even though bit 4 isn't representative.
+localparam        ALUOP_NEG  =  5'd0;
+localparam        ALUOP_COM  =  5'd3;
+localparam        ALUOP_LSR  =  5'd4;
+localparam        ALUOP_ROR  =  5'd6;
+localparam        ALUOP_ASR  =  5'd7;
+localparam        ALUOP_ASL  =  5'd8;
+localparam        ALUOP_LSL  =  5'd8;
+localparam        ALUOP_ROL  =  5'd9;
+localparam        ALUOP_DEC  =  5'd10;
+localparam        ALUOP_INC  =  5'd12;
+localparam        ALUOP_TST  =  5'd13;
+localparam        ALUOP_CLR  =  5'd15;
+
+localparam        ALUOP_SUB  =  5'd16;
+localparam        ALUOP_CMP  =  5'd17;
+localparam        ALUOP_SBC  =  5'd18;
+localparam        ALUOP_AND  =  5'd20;
+localparam        ALUOP_BIT  =  5'd21;
+localparam        ALUOP_LD   =  5'd22;
+localparam        ALUOP_EOR  =  5'd24;
+localparam        ALUOP_ADC  =  5'd25;
+localparam        ALUOP_OR   =  5'd26;
+localparam        ALUOP_ADD  =  5'd27;
+
+function [5:0] ALUOpFromInst(input   [7:0] inst);
+reg     [4:0] op;
+reg     writeback;
+begin
+    // Okay, this turned out to be simpler than I expected ...
+    op =  {inst[7], inst[3:0]};
+    case (op)
+        ALUOP_CMP:
+            writeback  =  0;
+        ALUOP_TST:
+            writeback  =  0;
+        ALUOP_BIT:
+            writeback  =  0;
+        default:
+            writeback  =  1;
+    endcase
+    ALUOpFromInst  =  {writeback, op};                        
+end
+endfunction
+
+wire    [4:0] ALU8Op;
+wire    ALU8Writeback;
+
+assign  {ALU8Writeback, ALU8Op}    =  ALUOpFromInst(Inst1);
+
+reg     [7:0] ALU_A;
+reg     [7:0] ALU_B;
+reg     [7:0] ALU_CC;
+reg     [4:0] ALU_OP;
+
+
+function [15:0] ALUInst(input   [4:0] operation, input   [7:0] a_arg, input   [7:0] b_arg, input   [7:0] cc_arg);
+reg     [7:0]    cc_out;
+reg     [7:0]    ALUFn;
+reg     carry;
+reg     borrow;
+begin
+    cc_out =  cc_arg;
+    case (operation)
+        ALUOP_NEG:
+        begin
+            ALUFn[7:0]             =  ~a_arg + 1'b1;
+            cc_out[CC_C_BIT]       =  (ALUFn[7:0] != 8'H00);
+            cc_out[CC_V_BIT]       =  (a_arg == 8'H80);
+        end
+        
+        ALUOP_LSL:
+        begin
+            {cc_out[CC_C_BIT], ALUFn}  =  {a_arg, 1'b0};
+            cc_out[CC_V_BIT]   =  a_arg[7] ^ a_arg[6];
+        end
+        
+        ALUOP_LSR:
+        begin
+            {ALUFn, cc_out[CC_C_BIT]}  =  {1'b0, a_arg}; 
+        end
+        
+        ALUOP_ASR:
+        begin
+            {ALUFn, cc_out[CC_C_BIT]}  =  {a_arg[7], a_arg}; 
+        end    
+        
+        ALUOP_ROL:
+        begin
+            {cc_out[CC_C_BIT], ALUFn}  =  {a_arg, cc_arg[CC_C_BIT]};
+            cc_out[CC_V_BIT]   =  a_arg[7] ^ a_arg[6];
+        end
+        
+        ALUOP_ROR:
+        begin
+            {ALUFn, cc_out[CC_C_BIT]}  =  {cc_arg[CC_C_BIT], a_arg}; 
+        end
+        
+        ALUOP_OR:
+        begin
+            ALUFn[7:0] =  (a_arg | b_arg);
+            cc_out[CC_V_BIT]   =  1'b0;
+        end
+        
+        ALUOP_ADD:
+        begin
+            {cc_out[CC_C_BIT], ALUFn[7:0]} =  {1'b0, a_arg} + {1'b0, b_arg};
+            cc_out[CC_V_BIT]   =  (a_arg[7] & b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & ~b_arg[7] & ALUFn[7]);
+            cc_out[CC_H_BIT]   =  a_arg[4] ^ b_arg[4] ^ ALUFn[4];
+        end
+        
+        ALUOP_SUB:
+        begin
+            {cc_out[CC_C_BIT], ALUFn[7:0]} = {1'b0, a_arg} - {1'b0, b_arg};
+            cc_out[CC_V_BIT]   =   (a_arg[7] & ~b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & b_arg[7] & ALUFn[7]);
+        end
+        
+        ALUOP_AND:
+        begin
+            ALUFn[7:0] =  (a_arg & b_arg);
+            cc_out[CC_V_BIT]   =  1'b0;
+        end
+        
+        ALUOP_BIT:
+        begin
+            ALUFn[7:0] =  (a_arg & b_arg);
+            cc_out[CC_V_BIT]   =  1'b0;
+        end
+        
+        ALUOP_EOR:
+        begin
+            ALUFn[7:0] =  (a_arg ^ b_arg);
+            cc_out[CC_V_BIT]   =  1'b0;                
+        end
+        
+        ALUOP_CMP:
+        begin
+            {cc_out[CC_C_BIT], ALUFn[7:0]} = {1'b0, a_arg} - {1'b0, b_arg};
+            cc_out[CC_V_BIT]   =   (a_arg[7] & ~b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & b_arg[7] & ALUFn[7]);
+        end
+        
+        ALUOP_COM:
+        begin
+            ALUFn[7:0] =  ~a_arg;
+            cc_out[CC_V_BIT]   =  1'b0;
+            cc_out[CC_C_BIT]   =  1'b1;
+        end
+        
+        ALUOP_ADC:
+        begin
+            {cc_out[CC_C_BIT], ALUFn[7:0]} =  {1'b0, a_arg} + {1'b0, b_arg} + cc_arg[CC_C_BIT];
+            cc_out[CC_V_BIT]   =  (a_arg[7] & b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & ~b_arg[7] & ALUFn[7]);
+            cc_out[CC_H_BIT]   =  a_arg[4] ^ b_arg[4] ^ ALUFn[4];
+        end
+        
+        ALUOP_LD:
+        begin
+            ALUFn[7:0] =  b_arg;
+            cc_out[CC_V_BIT] = 1'b0;
+        end
+        
+        ALUOP_INC:
+        begin
+            {carry, ALUFn} =  {1'b0, a_arg} + 1'b1;
+            cc_out[CC_V_BIT]   =  (~a_arg[7] & ALUFn[7]);             
+        end
+        
+        ALUOP_DEC:
+        begin
+            {carry, ALUFn[7:0]}    =  {1'b0, a_arg} - 1'b1;
+            cc_out[CC_V_BIT]       =   (a_arg[7] & ~ALUFn[7]);
+        end
+        
+        ALUOP_CLR:
+        begin
+            ALUFn[7:0] =  8'H00;
+            cc_out[CC_V_BIT]   =  1'b0;
+            cc_out[CC_C_BIT]   =  1'b0;
+        end
+        
+        ALUOP_TST:
+        begin
+            ALUFn[7:0] =  a_arg;
+            cc_out[CC_V_BIT]   =  1'b0;
+        end
+        
+        ALUOP_SBC:
+        begin
+            {cc_out[CC_C_BIT], ALUFn[7:0]} = {1'b0, a_arg} - {1'b0, b_arg} - cc_arg[CC_C_BIT];
+            cc_out[CC_V_BIT]   =   (a_arg[7] & ~b_arg[7] & ~ALUFn[7]) | (~a_arg[7] & b_arg[7] & ALUFn[7]);
+        end
+        
+        default:
+            ALUFn = 8'H00;
+    
+    endcase
+    
+    cc_out[CC_N_BIT]   =  ALUFn[7];
+    cc_out[CC_Z_BIT]   =  (ALUFn == 8'H00);
+    ALUInst    =  {cc_out[7:0], ALUFn[7:0]};
+end
+endfunction
+
+
+// Top 8 bits == CC, bottom 8 bits = output value
+wire    [15:0] ALU =  ALUInst(ALU_OP, ALU_A, ALU_B, ALU_CC);
+
+////////////////////////////////////////////////////////////
+
+localparam TYPE_INHERENT   =  3'd0;
+localparam TYPE_IMMEDIATE  =  3'd1;
+localparam TYPE_DIRECT     =  3'd2;
+localparam TYPE_RELATIVE   =  3'd3;
+localparam TYPE_INDEXED    =  3'd4;
+localparam TYPE_EXTENDED   =  3'd5;
+
+localparam TYPE_INVALID    =  3'd7;
+
+// Function to decode the addressing mode the instruction uses
+function [2:0] addressing_mode_type(input   [7:0] inst);
+begin
+    casex (inst)
+    8'b0000???? :                 addressing_mode_type   =  TYPE_DIRECT;
+    8'b0001???? :
+    begin
+        casex (inst[3:0])
+        4'b0010:
+            addressing_mode_type   =  TYPE_INHERENT;
+        
+        4'b0011:
+            addressing_mode_type   =  TYPE_INHERENT;
+        
+        4'b1001:
+            addressing_mode_type   =  TYPE_INHERENT;
+        
+        4'b1101:
+            addressing_mode_type   =  TYPE_INHERENT;
+        
+        4'b0110:
+            addressing_mode_type   =  TYPE_RELATIVE;
+        
+        4'b0111:
+            addressing_mode_type   =  TYPE_RELATIVE;
+        
+        4'b1010:
+            addressing_mode_type   =  TYPE_IMMEDIATE;
+        
+        4'b1100:
+            addressing_mode_type   =  TYPE_IMMEDIATE;
+        
+        4'b1110:
+            addressing_mode_type   =  TYPE_IMMEDIATE;
+        
+        4'b1111:
+            addressing_mode_type   =  TYPE_IMMEDIATE;
+        
+        default:
+            addressing_mode_type   =  TYPE_INVALID;
+        endcase
+    end
+    
+    8'b0010????:                     addressing_mode_type   =  TYPE_RELATIVE;
+    8'b0011????:
+    begin
+        casex(inst[3:0])
+        4'b00??:
+            addressing_mode_type   =  TYPE_INDEXED;
+        
+        4'b01??:
+            addressing_mode_type   =  TYPE_IMMEDIATE;
+        
+        4'b1001:
+            addressing_mode_type   =  TYPE_INHERENT;
+        
+        4'b101?:
+            addressing_mode_type   =  TYPE_INHERENT;
+        
+        4'b1100:
+            addressing_mode_type   =  TYPE_INHERENT;
+        
+        4'b1101:
+            addressing_mode_type   =  TYPE_INHERENT;
+        
+        4'b1111:
+            addressing_mode_type   =  TYPE_INHERENT;
+        
+        default:
+            addressing_mode_type   =  TYPE_INVALID;
+        endcase
+    end
+    
+    8'b010?????:                addressing_mode_type   =  TYPE_INHERENT;
+    
+    8'b0110????:                addressing_mode_type   =  TYPE_INDEXED;
+    
+    8'b0111????:                addressing_mode_type   =  TYPE_EXTENDED;
+    
+    8'b1000????:
+    begin
+        casex (inst[3:0])
+        4'b0111:                addressing_mode_type   =  TYPE_INVALID;
+        4'b1111:                addressing_mode_type   =  TYPE_INVALID;
+        4'b1101:                addressing_mode_type   =  TYPE_RELATIVE;
+        default:                addressing_mode_type   =  TYPE_IMMEDIATE;
+        endcase
+    end
+    
+    8'b1001????:                addressing_mode_type   =  TYPE_DIRECT;
+    8'b1010????:                addressing_mode_type   =  TYPE_INDEXED;
+    8'b1011????:                addressing_mode_type   =  TYPE_EXTENDED;
+    8'b1100????:                addressing_mode_type   =  TYPE_IMMEDIATE;
+    8'b1101????:                addressing_mode_type   =  TYPE_DIRECT;
+    8'b1110????:                addressing_mode_type   =  TYPE_INDEXED;
+    8'b1111????:                addressing_mode_type   =  TYPE_EXTENDED;
+    
+    endcase
+end
+endfunction
+
+wire    [2:0]    AddrModeType   =  addressing_mode_type(Inst1);
+
+//////////////////////////////////////////////////
+
+// Individual opcodes that are the top of a column of states.
+
+localparam OPCODE_INH_ABX           =  8'H3A;
+localparam OPCODE_INH_RTS           =  8'H39;
+localparam OPCODE_INH_RTI           =  8'H3B;
+localparam OPCODE_INH_CWAI          =  8'H3C;
+localparam OPCODE_INH_MUL           =  8'H3D;
+localparam OPCODE_INH_SWI           =  8'H3F;
+localparam OPCODE_INH_SEX           =  8'H1D;
+localparam OPCODE_INH_NOP           =  8'H12;
+localparam OPCODE_INH_SYNC          =  8'H13;
+localparam OPCODE_INH_DAA           =  8'H19;
+
+localparam OPCODE_IMM_ORCC          =  8'H1A;
+localparam OPCODE_IMM_ANDCC         =  8'H1C;
+localparam OPCODE_IMM_EXG           =  8'H1E;
+localparam OPCODE_IMM_TFR           =  8'H1F;
+localparam OPCODE_IMM_PSHS          =  8'H34;
+localparam OPCODE_IMM_PULS          =  8'H35;
+localparam OPCODE_IMM_PSHU          =  8'H36;
+localparam OPCODE_IMM_PULU          =  8'H37;
+
+localparam OPCODE_IMM_SUBD          =  8'H83;
+localparam OPCODE_IMM_CMPX          =  8'H8C;
+localparam OPCODE_IMM_LDX           =  8'H8E;
+localparam OPCODE_IMM_ADDD          =  8'HC3;
+localparam OPCODE_IMM_LDD           =  8'HCC;
+localparam OPCODE_IMM_LDU           =  8'HCE;
+localparam OPCODE_IMM_CMPD          =  8'H83;    // Page2
+localparam OPCODE_IMM_CMPY          =  8'H8C;    // Page2
+localparam OPCODE_IMM_LDY           =  8'H8E;    // Page2
+localparam OPCODE_IMM_LDS           =  8'HCE;    // Page2
+localparam OPCODE_IMM_CMPU          =  8'H83;    // Page3
+localparam OPCODE_IMM_CMPS          =  8'H8C;    // Page3
+
+localparam EXGTFR_REG_D             =  4'H0;
+localparam EXGTFR_REG_X             =  4'H1;
+localparam EXGTFR_REG_Y             =  4'H2;
+localparam EXGTFR_REG_U             =  4'H3;
+localparam EXGTFR_REG_S             =  4'H4;
+localparam EXGTFR_REG_PC            =  4'H5;
+localparam EXGTFR_REG_A             =  4'H8;
+localparam EXGTFR_REG_B             =  4'H9;
+localparam EXGTFR_REG_CC            =  4'HA;
+localparam EXGTFR_REG_DP            =  4'HB;
+
+function IsALU8Set0(input   [7:0] instr);
+reg     result;
+reg     [3:0] hi;
+reg     [3:0] lo;
+begin
+    hi =  instr[7:4];
+    lo =  instr[3:0];
+    if ( (hi == 4'H0) || (hi == 4'H4) || (hi == 4'H5) || (hi == 4'H6) || (hi == 4'H7) )
+    begin
+        if ( (lo != 4'H1) && (lo != 4'H2) && (lo != 4'H5) && (lo != 4'HB) && (lo != 4'HE) )     // permit NEG, COM, LSR, ROR, ASR, ASL/LSL, ROL, DEC, INC, TST, CLR 
+            result =  1;
+        else
+            result =  0;
+    end
+    else
+        result =  0;
+    IsALU8Set0     =  result;            
+end
+endfunction    
+
+function IsALU8Set1(input   [7:0] instr);
+reg     result;
+reg     [3:0] hi;
+reg     [3:0] lo;
+begin
+    hi =  instr[7:4];
+    lo =  instr[3:0];
+    if ( (hi >= 4'H8) )
+    begin
+        if ( (lo <= 4'HB) && (lo != 4'H3) && (lo != 4'H7) )     // 8-bit SUB, CMP, SBC, AND, BIT, LD, EOR, ADC, OR, ADD
+            result =  1;
+        else
+            result =  0;
+    end
+    else
+        result =  0;
+    IsALU8Set1     =  result;                
+end
+endfunction
+
+// Determine if the instruction is performing an 8-bit op (ALU only)    
+function ALU8BitOp(input   [7:0] instr);
+begin
+    ALU8BitOp      =  IsALU8Set0(instr) | IsALU8Set1(instr);
+end
+endfunction
+
+wire    Is8BitInst     =  ALU8BitOp(Inst1);
+
+function IsRegA(input   [7:0] instr);
+reg     result;
+reg     [3:0]    hi;
+begin
+    hi =  instr[7:4];
+    if ((hi == 4'H4) || (hi == 4'H8) || (hi == 4'H9) || (hi == 4'HA) || (hi == 4'HB) )
+        result =  1;
+    else
+        result =  0;
+    IsRegA =  result;
+end
+endfunction
+
+wire    IsTargetRegA   =  IsRegA(Inst1);
+
+//
+//
+// Decode 
+// 00-0F = DIRECT
+// 10-1F = INHERENT, RELATIVE, IMMEDIATE
+// 20-2F = RELATIVE
+// 30-3F = INDEXED, IMMEDIATE (pus, pul), INHERENT
+// 40-4F = INHERENT
+// 50-5F = INHERENT
+// 60-6F = INDEXED
+// 70-7F = EXTENDED
+// 80-8F = IMMEDIATE, RELATIVE (BSR)
+// 90-9F = DIRECT
+// A0-AF = INDEXED
+// B0-BF = EXTENDED
+// C0-CF = IMMEDIATE
+// D0-DF = DIRECT
+// E0-EF = INDEXED
+// F0-FF = EXTENDED
+
+// DIRECT; 00-0F, 90-9F, D0-DF
+// INHERENT; 10-1F (12, 13, 19, 1D), 30-3F (39-3F), 40-4F, 50-5F, 
+// RELATIVE: 10-1F (16, 17), 20-2F, 80-8F (8D)
+// IMMEDIATE: 10-1F (1A, 1C, 1E, 1F), 30-3F (34-37), 80-8F (80-8C, 8E), C0-CF
+// INDEXED: 60-6F, A0-AF, E0-EF
+// EXTENDED: 70-7F, B0-Bf, F0-FF
+
+localparam INST_LBRA   =  8'H16;                // always -- shitty numbering, damnit
+localparam INST_LBSR   =  8'H17;                // 
+
+localparam INST_BRA    =  8'H20;           // always
+localparam INST_BRN    =  8'H21;           // never
+localparam INST_BHI    =  8'H22;           // CC.Z = 0 && CC.C = 0
+localparam INST_BLS    =  8'H23;           // CC.Z != 0 && CC.C != 0
+localparam INST_BCC    =  8'H24;           // CC.C = 0
+localparam INST_BHS    =  8'H24;           // same as BCC
+localparam INST_BCS    =  8'H25;           // CC.C = 1
+localparam INST_BLO    =  8'H25;           // same as BCS
+localparam INST_BNE    =  8'H26;           // CC.Z = 0
+localparam INST_BEQ    =  8'H27;           // CC.Z = 1
+localparam INST_BVC    =  8'H28;           // V = 1
+localparam INST_BVS    =  8'H29;           // V = 0
+localparam INST_BPL    =  8'H2A;           // CC.N = 0
+localparam INST_BMI    =  8'H2B;           // CC.N = 1
+localparam INST_BGE    =  8'H2C;           // CC.N = CC.V
+localparam INST_BLT    =  8'H2D;           // CC.N != CC.V
+localparam INST_BGT    =  8'H2E;           // CC.N = CC.V && CC.Z = 0
+localparam INST_BLE    =  8'H2F;           // CC.N != CC.V && CC.Z = 1
+localparam INST_BSR    =  8'H8D;           // always
+
+localparam NYB_BRA     =  4'H0;            // always
+localparam NYB_BRN     =  4'H1;            // never
+localparam NYB_BHI     =  4'H2;            // CC.Z = 0 && CC.C = 0
+localparam NYB_BLS     =  4'H3;            // CC.Z != 0 && CC.C != 0
+localparam NYB_BCC     =  4'H4;            // CC.C = 0
+localparam NYB_BHS     =  4'H4;            // same as BCC
+localparam NYB_BCS     =  4'H5;            // CC.C = 1
+localparam NYB_BLO     =  4'H5;            // same as BCS
+localparam NYB_BNE     =  4'H6;            // CC.Z = 0
+localparam NYB_BEQ     =  4'H7;            // CC.Z = 1
+localparam NYB_BVC     =  4'H8;            // V = 0
+localparam NYB_BVS     =  4'H9;            // V = 1
+localparam NYB_BPL     =  4'HA;            // CC.N = 0
+localparam NYB_BMI     =  4'HB;            // CC.N = 1
+localparam NYB_BGE     =  4'HC;            // CC.N = CC.V
+localparam NYB_BLT     =  4'HD;            // CC.N != CC.V
+localparam NYB_BGT     =  4'HE;            // CC.N = CC.V && CC.Z = 0
+localparam NYB_BLE     =  4'HF;            // CC.N != CC.V && CC.Z = 1
+
+
+
+function take_branch(input   [7:0] Inst1, input   [7:0] cc);
+begin
+    take_branch    =  0;    //default
+    if ( (Inst1 == INST_BSR) || (Inst1 == INST_LBSR) || (Inst1 == INST_LBRA) )
+        take_branch    =  1;
+    else
+        case (Inst1[3:0])
+            NYB_BRA:
+                take_branch    =  1;
+            NYB_BRN:
+                take_branch    =  0;
+            NYB_BHI:
+                if ( ( cc[CC_Z_BIT] | cc[CC_C_BIT] ) == 0)
+                    take_branch    =  1;
+            NYB_BLS:
+                if ( cc[CC_Z_BIT] | cc[CC_C_BIT] )
+                    take_branch    =  1;
+            NYB_BCC:
+                if ( cc[CC_C_BIT] == 0 )
+                    take_branch    =  1;
+            NYB_BCS:
+                if ( cc[CC_C_BIT] == 1 )
+                    take_branch    =  1;
+            NYB_BNE:
+                if ( cc[CC_Z_BIT] == 0 )
+                    take_branch    =  1;
+            NYB_BEQ:
+                if ( cc[CC_Z_BIT] == 1 )
+                    take_branch    =  1;
+            NYB_BVC:
+                if ( cc[CC_V_BIT] == 0)
+                    take_branch    =  1;
+            NYB_BVS:
+                if ( cc[CC_V_BIT] == 1)
+                    take_branch    =  1;
+            NYB_BPL:
+                if ( cc[CC_N_BIT] == 0 )
+                    take_branch    =  1;
+            NYB_BMI:
+                if (cc[CC_N_BIT] == 1)
+                    take_branch    =  1;
+            NYB_BGE:
+                if ((cc[CC_N_BIT] ^ cc[CC_V_BIT]) == 0)
+                    take_branch    =  1;
+            NYB_BLT:
+                if ((cc[CC_N_BIT] ^ cc[CC_V_BIT]) == 1)
+                    take_branch    =  1;
+            NYB_BGT:
+                if ( ((cc[CC_N_BIT] ^ cc[CC_V_BIT]) == 0) & (cc[CC_Z_BIT] == 0) )
+                    take_branch    =  1;
+            NYB_BLE:
+                if ( ((cc[CC_N_BIT] ^ cc[CC_V_BIT]) == 1) | (cc[CC_Z_BIT] == 1) )
+                    take_branch    =  1;
+    endcase
+end
+endfunction
+
+wire    TakeBranch =  take_branch(Inst1, cc);
+
+/////////////////////////////////////////////////////////////////////
+// Convenience function for knowing the contents for TFR, EXG
+function [15:0] EXGTFRRegister(input [3:0] regid);
+begin
+        case (regid)
+            EXGTFR_REG_D:
+                EXGTFRRegister   =  {a, b};
+            EXGTFR_REG_X:
+                EXGTFRRegister   =  x;
+            EXGTFR_REG_Y:
+                EXGTFRRegister   =  y;
+            EXGTFR_REG_U:
+                EXGTFRRegister   =  u;
+            EXGTFR_REG_S:
+                EXGTFRRegister   =  s;
+            EXGTFR_REG_PC:
+                EXGTFRRegister   =  pc_p1; // For both EXG and TFR, this is used on the 2nd byte in the instruction's cycle.  The PC intended to transfer is actually the next byte.
+            EXGTFR_REG_DP:
+                EXGTFRRegister   =  {8'HFF, dp};
+            EXGTFR_REG_A:
+                EXGTFRRegister   =  {8'HFF, a};
+            EXGTFR_REG_B:
+                EXGTFRRegister   =  {8'HFF, b};
+            EXGTFR_REG_CC:
+                EXGTFRRegister   =  {8'HFF, cc};
+            default:
+                EXGTFRRegister   =  16'H0;                                       
+        endcase
+end
+endfunction
+wire [15:0] EXGTFRRegA = EXGTFRRegister(D[7:4]);
+wire [15:0] EXGTFRRegB = EXGTFRRegister(D[3:0]);
+
+// CPU state machine
+always @(*)
+begin
+    rLIC       =  1'b0;
+    rAVMA      =  1'b1;
+    rBUSY      =  1'b0;
+    
+    addr_nxt   =  16'HFFFF;
+    pc_p1      =  (pc+16'H1);
+    pc_p2      =  (pc+16'H2);
+    pc_p3      =  (pc+16'H3);
+    s_p1       =  (s+16'H1);
+    s_m1       =  (s-16'H1);
+    u_p1       =  (u+16'H1);
+    u_m1       =  (u-16'H1);
+    addr_p1    =  (addr+16'H1);
+    ea_p1      =  (ea+16'H1);
+    BS_nxt     =  1'b0;
+    BA_nxt     =  1'b0;
+    
+    // These may be overridden below, but the "next" version by default should be
+    // the last latched version.
+    IntType_nxt = IntType;
+    NMIClear_nxt = NMIClear;
+    NextState_nxt = NextState;
+    a_nxt      =  a;
+    b_nxt      =  b;
+    x_nxt      =  x;
+    y_nxt      =  y;
+    s_nxt      =  s;
+    u_nxt      =  u;
+    cc_nxt     =  cc;
+    dp_nxt     =  dp;
+    pc_nxt     =  pc;
+    tmp_nxt    =  tmp;
+    ea_nxt     =  ea;
+    
+    ALU_A      =  8'H00;
+    ALU_B      =  8'H00;
+    ALU_CC     =  8'H00;
+    ALU_OP     =  5'H00;
+    
+    ALU16_OP   =  3'H0;
+    ALU16_A    =  16'H0000;
+    ALU16_B    =  16'H0000;
+    ALU16_CC   =  8'H00;
+    
+    DOutput       =  8'H00;
+    RnWOut     =  1'b1;     // read
+    
+    Inst1_nxt  =  Inst1;
+    Inst2_nxt  =  Inst2;
+    Inst3_nxt  =  Inst3;
+    InstPage2_nxt  =  InstPage2;
+    InstPage3_nxt  =  InstPage3;
+    
+    CpuState_nxt   =  CpuState;
+    
+    case (CpuState)
+    CPUSTATE_RESET:
+    begin
+        addr_nxt   =  16'HFFFF;
+        a_nxt      =  0;
+        b_nxt      =  0;
+        x_nxt      =  0;
+        y_nxt      =  0;
+        s_nxt      =  16'HFFFD;    // Take care about removing the reset of S.  There's logic depending on the delta between s and s_nxt to clear NMIMask.
+        u_nxt      =  0;
+        cc_nxt     =  CC_F | CC_I; // reset disables interrupts
+        dp_nxt     =  0;
+        ea_nxt     =  16'HFFFF;
+        
+        RnWOut     =  1;        // read
+        rLIC       =  1'b0;     // Instruction incomplete
+        NMIClear_nxt= 1'b0;
+        IntType_nxt = 3'b111;
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_RESET0;
+    end
+    
+    CPUSTATE_RESET0:
+    begin
+        addr_nxt       =  `RESET_VECTOR;
+        rBUSY          =  1'b1;
+        pc_nxt[15:8]   =  D[7:0];
+        BS_nxt         =  1'b1; // ACK RESET
+        rAVMA = 1'b1;
+        rLIC = 1'b1;
+        CpuState_nxt   =  CPUSTATE_RESET2;
+    end
+    
+    CPUSTATE_RESET2:
+    begin
+        addr_nxt       =  addr_p1;
+        BS_nxt         =  1'b1; // ACK RESET        
+        pc_nxt[7:0]    =  D[7:0];
+        rAVMA = 1'b1;
+        rLIC = 1'b1;
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+    end
+    
+    CPUSTATE_FETCH_I1:
+    begin
+        if (~DMABREQLatched)
+        begin
+            addr_nxt      = pc;
+            RnWOut        = 1'b1;
+            rAVMA         = 1'b0;
+            tmp_nxt       = {tmp[15:4], 4'b1111};
+            BS_nxt         = 1'b1;
+            BA_nxt         = 1'b1;
+            rLIC           = 1'b1;
+            CpuState_nxt  = CPUSTATE_DMABREQ;
+        end
+        else if (~HALTLatched)
+        begin
+            addr_nxt       = pc;
+            RnWOut         = 1'b1;
+            rAVMA          = 1'b0;
+            BS_nxt         = 1'b1;
+            BA_nxt         = 1'b1;
+            rLIC           = 1'b1;            
+            CpuState_nxt = CPUSTATE_HALTED;
+        end
+        else // not halting, run the inst byte fetch
+        begin
+            addr_nxt       =  pc;   // Set the address bus for the next instruction, first byte
+            pc_nxt =  pc_p1;
+            RnWOut =  1;            // Set for a READ
+            Inst1_nxt  =  MappedInstruction;
+            InstPage2_nxt  =  0;
+            InstPage3_nxt  =  0;
+            
+            // New instruction fetch; service interrupts pending
+            if (NMILatched == 0)
+            begin
+                pc_nxt = pc;        
+                rAVMA = 1'b1;
+                CpuState_nxt = CPUSTATE_NMI_START;
+            end
+            else if ((FIRQLatched == 0) && (cc[CC_F_BIT] == 0))
+            begin
+                pc_nxt = pc;
+                rAVMA = 1'b1;
+                CpuState_nxt = CPUSTATE_FIRQ_START;
+            end
+            else if ((IRQLatched == 0) && (cc[CC_I_BIT] == 0))
+            begin
+                pc_nxt = pc; 
+                rAVMA = 1'b1;                
+                CpuState_nxt = CPUSTATE_IRQ_START;
+            end
+            
+            // The actual 1st byte checks
+            else if (Inst1_nxt == 8'H10) // Page 2  Note, like the 6809, $10 $10 $10 $10 has the same effect as a single $10.
+            begin
+                InstPage2_nxt  =  1;
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_FETCH_I1V2;
+            end
+            else if (Inst1_nxt == 8'H11)    // Page 3
+            begin
+                InstPage3_nxt  =  1;
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_FETCH_I1V2;
+            end
+            else
+            begin
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_FETCH_I2;
+            end
+        end // if not halting
+    end
+    
+    CPUSTATE_FETCH_I1V2:
+    begin
+        addr_nxt   =  pc;            // Set the address bus for the next instruction, first byte
+        pc_nxt     =  pc_p1;
+        RnWOut     =  1;            // Set for a READ
+        Inst1_nxt  =  MappedInstruction;
+
+        if (Inst1_nxt == 8'H10)         // Page 2  Note, like the 6809, $10 $10 $10 $10 has the same effect as a single $10.
+        begin
+            if (InstPage3 == 0)             // $11 $11 $11 $11 ... $11 $10 still = Page 3
+                InstPage2_nxt  =  1;
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1V2;
+        end
+        else if (Inst1_nxt == 8'H11)    // Page 3
+        begin
+            if (InstPage2 == 0)             // $10 $10 ... $10 $11 still = Page 2
+                InstPage3_nxt  =  1;
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1V2;
+        end
+        else
+        begin
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I2;
+        end
+    end
+    
+    
+    CPUSTATE_FETCH_I2:      // We've fetched the first byte.  If a $10 or $11 (page select), mark those flags and fetch the next byte as instruction byte 1.
+    begin
+        addr_nxt   =  addr_p1;    // Address bus++
+        pc_nxt     =  pc_p1;
+        Inst2_nxt  =  D[7:0];
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+
+        if (IsIllegalInstruction)           // Skip illegal instructions
+        begin
+            
+            rAVMA = 1'b1;
+            CpuState_nxt = IllegalInstructionState;
+            rLIC = 1'b1;
+        end
+        else
+        begin
+            // First byte Decode for this stage
+            case (AddrModeType)
+                TYPE_INDEXED:
+                begin
+                    rAVMA = 1'b1;
+                    CpuState_nxt   =  CPUSTATE_INDEXED_BASE;
+                end
+                
+                
+                TYPE_EXTENDED:
+                begin
+                    ea_nxt[15:8]   =  Inst2_nxt;
+                    rAVMA = 1'b1;
+                    CpuState_nxt   =  CPUSTATE_EXTENDED_ADDRLO;
+                end
+                TYPE_DIRECT:
+                begin
+                    ea_nxt =  {dp, Inst2_nxt};
+                    rAVMA = 1'b0;
+                    CpuState_nxt   =  CPUSTATE_DIRECT_DONTCARE;
+                end
+                
+                TYPE_INHERENT:
+                begin
+                    if (Inst1 == OPCODE_INH_NOP)
+                    begin
+                        rLIC = 1'b1; // Instruction done!
+                        rAVMA = 1'b1;
+                        CpuState_nxt = CPUSTATE_FETCH_I1;    
+                    end
+                    else if (Inst1 == OPCODE_INH_DAA)       // Bcd lunacy
+                    begin
+                        if ( ((cc[CC_C_BIT]) || (a[7:4] > 4'H9)) ||
+                             ((a[7:4] > 4'H8) && (a[3:0] > 4'H9)) )
+                            tmp_nxt[7:4] = 4'H6;
+                        else
+                            tmp_nxt[7:4] = 4'H0;
+                            
+                        if ((cc[CC_H_BIT]) || (a[3:0] > 4'H9))
+                            tmp_nxt[3:0] = 4'H6;
+                        else
+                            tmp_nxt[3:0] = 4'H0;
+                            
+                        // DAA handles carry in the weirdest way.  
+                        // If it's already set, it remains set, even if carry-out is 0.
+                        // If it wasn't set, but the output of the operation is set, carry-out gets set.
+                        {tmp_nxt[8], a_nxt} = {1'b0, a} + tmp_nxt[7:0];
+                        
+                        cc_nxt[CC_C_BIT] = cc_nxt[CC_C_BIT] | tmp_nxt[8];
+
+                        cc_nxt[CC_N_BIT] = a_nxt[7];
+                        cc_nxt[CC_Z_BIT] = (a_nxt == 8'H00);
+                        rLIC = 1'b1; // Instruction done!
+                        rAVMA = 1'b1;
+                        CpuState_nxt = CPUSTATE_FETCH_I1;    
+                    end
+                    else if (Inst1 == OPCODE_INH_SYNC)
+                    begin
+                        CpuState_nxt = CPUSTATE_SYNC;
+                        rLIC = 1'b1;
+                        rAVMA = 1'b0;
+                    end
+                    else if (Inst1 == OPCODE_INH_MUL)
+                    begin
+                        tmp_nxt = 16'H0000;
+                        ea_nxt[15:8] = 8'H00;
+                        ea_nxt[7:0] = a;
+                        a_nxt = 8;
+                        rAVMA = 1'b0;
+                        CpuState_nxt = CPUSTATE_MUL_ACTION;
+                    end
+                    else if (Inst1 == OPCODE_INH_RTS)
+                    begin
+                        rAVMA = 1'b1;
+                        CpuState_nxt   =  CPUSTATE_RTS_HI;
+                    end
+                    else if (Inst1 == OPCODE_INH_RTI)
+                    begin
+                        rAVMA = 1'b1;
+                        tmp_nxt = 16'H1001; // Set tmp[12] to indicate an RTI being processed, and at least pull CC.
+                        CpuState_nxt = CPUSTATE_PUL_ACTION;
+                        NextState_nxt = CPUSTATE_FETCH_I1;
+                    end
+                    else if (Inst1 == OPCODE_INH_SWI)
+                    begin
+                        rAVMA = 1'b1;
+                        CpuState_nxt = CPUSTATE_SWI_START;
+                    end
+                    else if (Inst1 == OPCODE_INH_CWAI)
+                    begin
+                        rAVMA = 1'b1;
+                        CpuState_nxt = CPUSTATE_CWAI;
+                    end
+                    else if (Inst1 == OPCODE_INH_SEX)
+                    begin
+                        a_nxt = {8{b[7]}};
+                        rLIC = 1'b1; // Instruction done!
+                        rAVMA = 1'b1;
+                        CpuState_nxt = CPUSTATE_FETCH_I1;
+                        end
+                    else if (Inst1 == OPCODE_INH_ABX)
+                    begin
+                        x_nxt  =  x + b;
+                        rAVMA = 1'b0;
+                        CpuState_nxt   =  CPUSTATE_ABX_DONTCARE;
+                    end                                                                        
+                    else
+                    begin
+                        ALU_OP =  ALU8Op; 
+                        if (IsTargetRegA)
+                            ALU_A  =  a;
+                        else
+                            ALU_A  =  b;
+                        
+                        ALU_B  =  0;
+                        ALU_CC =  cc;
+                        cc_nxt =  ALU[15:8];
+                        
+                        if (ALU8Writeback)
+                        begin
+                            if (IsTargetRegA)
+                                a_nxt  =  ALU[7:0];
+                            else
+                                b_nxt  =  ALU[7:0];
+                        end
+                        rLIC = 1'b1; // Instruction done!
+                        rAVMA = 1'b1;
+                        CpuState_nxt = CPUSTATE_FETCH_I1;  
+                    end
+                    if (IsOneByteInstruction(Inst1))        // This check is probably superfluous.  Every inherent instruction is 1 byte on the 6809.
+                        pc_nxt =  pc;                       // The 6809 auto-reads 2 bytes for every instruction.  :(  Adjust by not incrementing PC on the 2nd byte read.
+                 end
+                
+                TYPE_IMMEDIATE:
+                begin
+                    if (IsSpecialImmediate)
+                    begin
+                        if (Inst1 == OPCODE_IMM_ANDCC)
+                        begin
+                            pc_nxt = pc_p1;
+                            cc_nxt = cc & D; //cc_nxt & Inst2_nxt;
+                            rAVMA = 1'b1;
+                            CpuState_nxt = CPUSTATE_CC_DONTCARE;
+                        end
+                        else if (Inst1 == OPCODE_IMM_ORCC)
+                        begin
+                            pc_nxt = pc_p1;
+                            cc_nxt = cc | D; //cc_nxt | Inst2_nxt;
+                            rAVMA = 1'b1;
+                            CpuState_nxt = CPUSTATE_CC_DONTCARE;
+                        end
+                        else if ( (Inst1 == OPCODE_IMM_PSHS) | (Inst1 == OPCODE_IMM_PSHU) )
+                        begin
+                            pc_nxt = pc_p1;
+                            tmp_nxt[15] = 1'b0;
+                            tmp_nxt[14] = Inst1[1]; // Mark whether to save to U or S.
+                            tmp_nxt[13] = 1'b0; // Not pushing due to an interrupt.
+                            tmp_nxt[13:8] = 6'H00;
+                            tmp_nxt[7:0] = Inst2_nxt;
+                            rAVMA = 1'b0;
+                            CpuState_nxt = CPUSTATE_PSH_DONTCARE1;
+                            NextState_nxt = CPUSTATE_FETCH_I1;
+                        end
+                        else if ( (Inst1 == OPCODE_IMM_PULS) | (Inst1 == OPCODE_IMM_PULU) )
+                        begin
+                            pc_nxt = pc_p1;
+                            tmp_nxt[15] = 1'b0;
+                            tmp_nxt[14] = Inst1[1]; // S (0) or U (1) stack in use.
+                            tmp_nxt[13:8] = 6'H00;
+                            tmp_nxt[7:0] = Inst2_nxt;
+                            rAVMA = 1'b0;
+                            CpuState_nxt = CPUSTATE_PUL_DONTCARE1;
+                            NextState_nxt = CPUSTATE_FETCH_I1;
+                        end
+                        else if (Inst1 == OPCODE_IMM_TFR)
+                        begin
+                            // The second byte lists the registers; Top nybble is reg #1, bottom is reg #2.
+
+                            case (Inst2_nxt[3:0])
+                                EXGTFR_REG_D:
+                                    {a_nxt,b_nxt}  =  EXGTFRRegA;
+                                EXGTFR_REG_X:
+                                    x_nxt  =  EXGTFRRegA;
+                                EXGTFR_REG_Y:
+                                    y_nxt  =  EXGTFRRegA;
+                                EXGTFR_REG_U:
+                                    u_nxt  =  EXGTFRRegA;
+                                EXGTFR_REG_S:
+                                    s_nxt  =  EXGTFRRegA;
+                                EXGTFR_REG_PC:
+                                    pc_nxt =  EXGTFRRegA;
+                                EXGTFR_REG_DP:
+                                    dp_nxt =  EXGTFRRegA[7:0];
+                                EXGTFR_REG_A:
+                                    a_nxt  =  EXGTFRRegA[7:0];
+                                EXGTFR_REG_B:
+                                    b_nxt  =  EXGTFRRegA[7:0];
+                                EXGTFR_REG_CC:
+                                    cc_nxt =  EXGTFRRegA[7:0];
+                                default:
+                                begin
+                                end
+                            endcase                          
+                            rAVMA = 1'b0;
+                            CpuState_nxt   =  CPUSTATE_TFR_DONTCARE1;
+                            
+                        end
+                        else if (Inst1 == OPCODE_IMM_EXG)
+                        begin
+                            // The second byte lists the registers; Top nybble is reg #1, bottom is reg #2.
+                              
+                            case (Inst2_nxt[7:4])
+                                EXGTFR_REG_D:
+                                    {a_nxt,b_nxt}  =  EXGTFRRegB;
+                                EXGTFR_REG_X:
+                                    x_nxt  =  EXGTFRRegB;
+                                EXGTFR_REG_Y:
+                                    y_nxt  =  EXGTFRRegB;
+                                EXGTFR_REG_U:
+                                    u_nxt  =  EXGTFRRegB;
+                                EXGTFR_REG_S:
+                                    s_nxt  =  EXGTFRRegB;
+                                EXGTFR_REG_PC:
+                                    pc_nxt =  EXGTFRRegB;
+                                EXGTFR_REG_DP:
+                                    dp_nxt =  EXGTFRRegB[7:0];
+                                EXGTFR_REG_A:
+                                    a_nxt  =  EXGTFRRegB[7:0];
+                                EXGTFR_REG_B:
+                                    b_nxt  =  EXGTFRRegB[7:0];
+                                EXGTFR_REG_CC:
+                                    cc_nxt =  EXGTFRRegB[7:0];
+                                default:
+                                begin
+                                end
+                            endcase
+                            case (Inst2_nxt[3:0])
+                                EXGTFR_REG_D:
+                                    {a_nxt,b_nxt}  =  EXGTFRRegA;
+                                EXGTFR_REG_X:
+                                    x_nxt  =  EXGTFRRegA;
+                                EXGTFR_REG_Y:
+                                    y_nxt  =  EXGTFRRegA;
+                                EXGTFR_REG_U:
+                                    u_nxt  =  EXGTFRRegA;
+                                EXGTFR_REG_S:
+                                    s_nxt  =  EXGTFRRegA;
+                                EXGTFR_REG_PC:
+                                    pc_nxt =  EXGTFRRegA;
+                                EXGTFR_REG_DP:
+                                    dp_nxt =  EXGTFRRegA[7:0];
+                                EXGTFR_REG_A:
+                                    a_nxt  =  EXGTFRRegA[7:0];
+                                EXGTFR_REG_B:
+                                    b_nxt  =  EXGTFRRegA[7:0];
+                                EXGTFR_REG_CC:
+                                    cc_nxt =  EXGTFRRegA[7:0];
+                                default:
+                                begin
+                                end
+                            endcase                               
+                            rAVMA = 1'b0;
+                            CpuState_nxt   =  CPUSTATE_EXG_DONTCARE1;  
+                        end
+                    end
+                    // Determine if this is an 8-bit ALU operation.
+                    else if (Is8BitInst)
+                    begin
+                        ALU_OP =  ALU8Op;     
+                        if (IsTargetRegA)
+                            ALU_A  =  a;
+                        else
+                            ALU_A  =  b;
+                        
+                        ALU_B  =  Inst2_nxt;
+                        ALU_CC =  cc;
+                        cc_nxt =  ALU[15:8];
+                        
+                        if (ALU8Writeback)
+                        begin
+                            if (IsTargetRegA)
+                                a_nxt  =  ALU[7:0];
+                            else
+                                b_nxt  =  ALU[7:0];
+                        end
+                        rLIC = 1'b1; // Instruction done!               
+                        rAVMA = 1'b1;
+                        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+                    end
+                    else            // Then it must be a 16 bit instruction
+                    begin
+                                // 83 SUBD
+                                // 8C CMPX
+                                // 8E LDX
+                                // C3 ADDD
+                                // CC LDD
+                                // CE LDU
+                                // 108E CMPD
+                                // 108C CMPY
+                                // 108E LDY
+                                // 10CE LDS
+                                // 1183 CMPU
+                                // 118C CMPS
+                                // Wow, they were just stuffing them in willy-nilly ...
+                        
+                                // LD* 16 bit immediate
+                        if (IsALU16Opcode)
+                        begin
+                            rAVMA = 1'b1;
+                            CpuState_nxt   =  CPUSTATE_16IMM_LO;
+                        end
+                        // there's a dead zone here; I need an else to take us back to CPUSTATE_FETCHI1 if we want to ignore illegal instructions, to CPUSTATE_DEAD if we want to catch them.
+                        
+                    end
+                    
+                end
+                
+                TYPE_RELATIVE:
+                begin
+                    // Is this a LB** or a B**?
+                    // If InstPage2 is set, it's a long branch; if clear, a normal branch.
+                    if ( (InstPage2) || (Inst1 == INST_LBRA) || (Inst1 == INST_LBSR) )
+                    begin
+                        rAVMA = 1'b1;
+                        CpuState_nxt   =  CPUSTATE_LBRA_OFFSETLOW;
+                    end
+                    else
+                    begin
+                        rAVMA = 1'b0;
+                        CpuState_nxt   =  CPUSTATE_BRA_DONTCARE;
+                    end
+                    
+                end
+                default:
+                begin
+                    CpuState_nxt = CPUSTATE_FETCH_I1;
+                end
+            endcase
+        end
+    end
+    
+    
+    CPUSTATE_LBRA_OFFSETLOW:
+    begin
+        addr_nxt   =  pc;
+        pc_nxt     =  pc_p1;
+        Inst3_nxt  =  D[7:0];
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_LBRA_DONTCARE;
+    end
+    
+    CPUSTATE_LBRA_DONTCARE:
+    begin
+        addr_nxt       =  16'HFFFF;
+        if ( TakeBranch )
+        begin
+            rAVMA = 1'b0;
+            CpuState_nxt   =  CPUSTATE_LBRA_DONTCARE2;
+        end
+        else
+        begin
+            rLIC = 1'b1; // Instruction done!  
+            rAVMA = 1'b1;            
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+        end            
+    end
+    
+    CPUSTATE_BRA_DONTCARE:
+    begin
+        addr_nxt   =  16'HFFFF;
+        tmp_nxt    =  pc;
+        if (TakeBranch)
+        begin
+            pc_nxt =  pc + { {8{Inst2[7]}}, Inst2[7:0]}; // Sign-extend the 8 bit offset to 16.
+            
+            if (Inst1 == INST_BSR)
+            begin
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_BSR_DONTCARE1;
+            end
+            else
+            begin
+                rLIC = 1'b1; // Instruction done!  
+                rAVMA = 1'b1;                
+                CpuState_nxt   =  CPUSTATE_FETCH_I1;
+            end
+        end
+        else
+        begin
+            rLIC = 1'b1;
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+        end
+        
+    end
+    
+    CPUSTATE_LBRA_DONTCARE2:
+    begin
+        tmp_nxt=  pc;
+        addr_nxt   =  16'HFFFF;
+        
+        // Take branch
+        pc_nxt     =  pc + {Inst2[7:0], Inst3[7:0]};
+        if (Inst1 == INST_LBSR)
+        begin
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_BSR_DONTCARE1;
+        end
+        else
+        begin
+            rLIC = 1'b1; // Instruction done!        
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+        end
+    end
+    
+    CPUSTATE_BSR_DONTCARE1:
+    begin
+        addr_nxt   =  pc;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_BSR_DONTCARE2;
+    end
+    
+    CPUSTATE_BSR_DONTCARE2:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_BSR_RETURNLOW;
+    end
+    
+    CPUSTATE_BSR_RETURNLOW:
+    begin
+        addr_nxt       =  s_m1;
+        s_nxt  =  s_m1;
+        DOutput[7:0]  =  tmp[7:0];
+        RnWOut     =  0;
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_BSR_RETURNHIGH;
+    end
+    
+    CPUSTATE_BSR_RETURNHIGH:
+    begin
+        addr_nxt       =  s_m1;
+        s_nxt  =  s_m1;
+        DOutput[7:0]  =  tmp[15:8];
+        RnWOut     =  0;
+        rLIC = 1'b1; // Instruction done!
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;    // after this, RnWOut must go to 1, and the bus needs the PC placed on it.
+    end
+    
+    CPUSTATE_TFR_DONTCARE1:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_TFR_DONTCARE2;
+    end            
+    
+    CPUSTATE_TFR_DONTCARE2:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_TFR_DONTCARE3;
+    end            
+    
+    CPUSTATE_TFR_DONTCARE3:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_TFR_DONTCARE4;
+    end            
+    
+    CPUSTATE_TFR_DONTCARE4:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b1;
+        rLIC = 1'b1; // Instruction done!        
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+    end            
+    
+    CPUSTATE_EXG_DONTCARE1:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_EXG_DONTCARE2;
+    end            
+    
+    CPUSTATE_EXG_DONTCARE2:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_EXG_DONTCARE3;
+    end            
+    
+    CPUSTATE_EXG_DONTCARE3:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_EXG_DONTCARE4;
+    end            
+    
+    CPUSTATE_EXG_DONTCARE4:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_EXG_DONTCARE5;
+    end    
+    
+    CPUSTATE_EXG_DONTCARE5:
+    begin
+        rAVMA = 1'b0;
+        addr_nxt       =  16'HFFFF;
+        CpuState_nxt   =  CPUSTATE_EXG_DONTCARE6;
+    end    
+    
+    CPUSTATE_EXG_DONTCARE6:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b1;
+        rLIC = 1'b1; // Instruction done!        
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+    end            
+    
+    CPUSTATE_ABX_DONTCARE:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b1;
+        rLIC = 1'b1; // Instruction done!        
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+    end            
+    
+    CPUSTATE_RTS_HI:
+    begin
+        addr_nxt       =  s;
+        s_nxt  =  s_p1;
+        pc_nxt[15:8]   =  D[7:0];
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_RTS_LO;
+    end
+    
+    CPUSTATE_RTS_LO:
+    begin
+        addr_nxt       =  s;
+        s_nxt  =  s_p1;
+        pc_nxt[7:0]    =  D[7:0];
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_RTS_DONTCARE2;
+    end
+    
+    CPUSTATE_RTS_DONTCARE2:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rLIC = 1'b1; // Instruction done!        
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+    end
+    
+    CPUSTATE_16IMM_LO:
+    begin
+        addr_nxt       =  pc;
+        pc_nxt =  pc_p1;
+        
+        ALU16_OP   =  ALU16Opcode;
+        ALU16_CC   =  cc;
+        ALU16_B    =  {Inst2, D[7:0]};
+        
+        case (ALU16Reg)
+            ALU16_REG_X:
+                ALU16_A    =  x;
+            ALU16_REG_D:
+                ALU16_A    =  {a, b};
+            ALU16_REG_Y:
+                ALU16_A    =  y;
+            ALU16_REG_U:
+                ALU16_A    =  u;
+            ALU16_REG_S:
+                ALU16_A    =  s;
+            default:
+                ALU16_A    =  16'H0;
+        endcase
+        
+        if (ALU16OpWriteback)
+        begin
+            case (ALU16Reg)
+                ALU16_REG_X:
+                    {cc_nxt, x_nxt}        =  ALU16; 
+                ALU16_REG_D:
+                    {cc_nxt, a_nxt, b_nxt} =  ALU16;
+                ALU16_REG_Y:
+                    {cc_nxt, y_nxt}        =  ALU16;
+                ALU16_REG_U:
+                    {cc_nxt, u_nxt}        =  ALU16;
+                ALU16_REG_S:
+                    {cc_nxt, s_nxt}        =  ALU16;
+                default:
+                begin
+                end
+            endcase
+        end
+        else
+            cc_nxt = ALU16[23:16];
+
+        if (ALU16_OP == ALUOP16_LD)
+        begin
+            rLIC = 1'b1; // Instruction done!        
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+        end
+        else
+        begin
+            rAVMA = 1'b0;
+            CpuState_nxt   =  CPUSTATE_16IMM_DONTCARE;
+        end
+    end   
+    
+    CPUSTATE_DIRECT_DONTCARE:
+    begin
+        addr_nxt       =  16'HFFFF;
+        
+        if (IsJMP(Inst1))
+        begin
+            pc_nxt =  ea;
+            rLIC = 1'b1; // Instruction done!            
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+        end
+        else
+        begin
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_ALU_EA;
+        end
+    end
+    
+    CPUSTATE_ALU_EA:
+    begin
+        
+        // Is Figure 18/5 Column 2?  JMP (not Immediate Mode)
+        // This actually isn't done here.  All checks passing in to ALU_EA should check for a JMP; FIXME EVERYWHERE
+
+        // Is Figure 18/5 Column 8?  TST (not immediate mode)
+        // THIS IS BURIED IN THE COLUMN 3 section with comparisons to ALUOP_TST.
+        
+        // Is Figure 18/5 Column 3?
+        if (IsALU8Set1(Inst1))
+        begin
+            addr_nxt   =  ea;
+            
+            ALU_OP     =  ALU8Op;
+            ALU_B      =  D[7:0];
+            ALU_CC     =  cc;
+            
+            if (IsTargetRegA)
+                ALU_A  =  a;
+            else
+                ALU_A  =  b;
+            
+            cc_nxt =  ALU[15:8];
+            
+            if ( (ALU8Writeback) )
+            begin
+                if (IsTargetRegA)
+                    a_nxt  =  ALU[7:0];
+                else
+                    b_nxt  =  ALU[7:0];
+            end
+
+            rLIC = 1'b1; // Instruction done!             
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+        end
+        
+        // Is Figure 18/5 Column 4? (Store, 8 bits)
+        else if (IsStore8)
+        begin
+            addr_nxt       =  ea;
+            RnWOut =  0;    // write
+
+            ALU_OP     =  ALUOP_LD;  // load has the same CC characteristics as store
+            ALU_A      =  8'H00;
+            ALU_CC     =  cc;
+            
+            case (Store8RegisterNum)
+                ST8_REG_A:
+                begin
+                    DOutput   =  a;
+                    ALU_B  =  a;
+                end
+                ST8_REG_B:
+                begin
+                    DOutput   =  b;                                                
+                    ALU_B  =  b;
+                end
+
+
+            endcase
+            
+            cc_nxt =  ALU[15:8];
+
+            rLIC = 1'b1; // Instruction done!            
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+        end
+        
+        // Is Figure 18/5 Column 5?  (Load, 16 bits)
+        else if (IsALU16Opcode & (ALU16Opcode == ALUOP16_LD))
+        begin
+            addr_nxt   =  ea;
+            ea_nxt     =  ea_p1;
+            
+            case (ALU16Reg)
+                ALU16_REG_X:
+                    x_nxt[15:8]    =  D[7:0];
+                ALU16_REG_D:
+                    a_nxt          =  D[7:0];
+                ALU16_REG_Y:
+                    y_nxt[15:8]    =  D[7:0];
+                ALU16_REG_S:
+                    s_nxt[15:8]    =  D[7:0];                                
+                ALU16_REG_U:
+                    u_nxt[15:8]    =  D[7:0];
+                default:
+                begin
+                end
+            endcase
+            rAVMA = 1'b1;
+            rBUSY = 1'b1;
+            CpuState_nxt   =  CPUSTATE_LD16_LO;
+            
+        end
+        
+        // Is Figure 18/5 Column 6?  (Store, 16 bits)
+        else if (IsStore16)
+        begin
+            addr_nxt       =  ea;
+            ea_nxt         =  ea_p1;
+            
+            ALU16_OP       =  ALUOP16_LD;   // LD and ST have the same CC characteristics
+            ALU16_CC       =  cc;
+            ALU16_A        =  8'H00;
+            
+            case (StoreRegisterNum)
+                ST16_REG_X:
+                begin
+                    DOutput[7:0]  =  x[15:8];
+                    ALU16_B    =  x;
+                end
+                ST16_REG_Y:
+                begin
+                    DOutput[7:0]  =  y[15:8];
+                    ALU16_B    =  y;
+                end
+                ST16_REG_U:
+                begin
+                    DOutput[7:0]  =  u[15:8];
+                    ALU16_B    =  u;                    
+                end
+                ST16_REG_S:
+                begin
+                    DOutput[7:0]  =  s[15:8];
+                    ALU16_B    =  s;                    
+                end
+                ST16_REG_D:
+                begin
+                    DOutput[7:0]  =  a[7:0];
+                    ALU16_B    =  {a,b};
+                end
+                default:
+                begin
+                end
+            endcase
+            
+            cc_nxt = ALU16[23:16];
+            
+            RnWOut         =  0;        // Write
+            rAVMA          =  1'b1;
+            rBUSY          =  1'b1;
+            CpuState_nxt   =  CPUSTATE_ST16_LO;
+        end
+        
+        // Is Figure 18/5 Column 7?
+        else if (IsALU8Set0(Inst1))
+        begin
+            // These are registerless instructions, ala
+            // ASL, ASR, CLR, COM, DEC, INC, (LSL), LSR, NEG, ROL, ROR
+            // and TST (special!)
+            // They require READ, Modify (the operation above), WRITE.  Between the Read and the Write cycles, there's actually a /VMA
+            // cycle where the 6809 likely did the operation.  We'll include a /VMA cycle for accuracy, but we'll do the work primarily in the first cycle.              
+            addr_nxt       =  ea;
+            
+            ALU_OP =  ALU8Op;       
+            ALU_A  =  D[7:0];
+            ALU_CC =  cc;
+            tmp_nxt[15:8] = cc;  // for debug only
+            tmp_nxt[7:0]   =  ALU[7:0];
+            cc_nxt =  ALU[15:8];
+            if (ALU8Op == ALUOP_TST)
+            begin
+                rAVMA = 1'b0;
+                CpuState_nxt = CPUSTATE_TST_DONTCARE1;
+            end
+            else
+            begin
+                rAVMA = 1'b0;
+                rBUSY = 1'b1;
+                CpuState_nxt   =  CPUSTATE_ALU_DONTCARE;
+            end
+            
+        end
+        
+        // Is Figure 18/5 Column 8?  TST
+        // NOTE:
+        // THIS IS BURIED IN THE COLUMN 3 section with comparisons to ALUOP_TST.  [Directly above.]
+        
+        
+        // Is Figure 18/5 Column 9?  (16-bit ALU ops, non-load)
+        else if (IsALU16Opcode && (ALU16Opcode != ALUOP16_LD) && ((Inst1 < 8'H30) || (Inst1 > 8'H33)) ) // 30-33 = LEAX, LEAY, LEAS, LEAU; don't include them here.
+        begin
+            addr_nxt       =  ea;
+            ea_nxt =  ea_p1;
+            
+            tmp_nxt[15:8]  =  D[7:0];
+            rAVMA = 1'b1;
+            rBUSY = 1'b1;
+            CpuState_nxt   =  CPUSTATE_ALU16_LO;
+            
+        end
+        
+        // Is Figure 18/5 Column 10?  JSR (not Immediate Mode)
+        else if ((Inst1 == 8'H9D) || (Inst1 == 8'HAD) || (Inst1 == 8'HBD))      // JSR
+        begin
+            pc_nxt =  ea;
+            addr_nxt   =  ea;
+            tmp_nxt    =  pc;
+            rAVMA = 1'b0;
+            CpuState_nxt   =  CPUSTATE_JSR_DONTCARE;
+        end
+        // Is Figure 18/5 Column 11?  LEA(X,Y,S,U)
+        else if ((Inst1 >= 8'H30) && (Inst1<= 8'H33))
+        begin
+            addr_nxt = 16'HFFFF; // Ack, actually a valid cycle, this isn't a dontcare (/VMA) cycle!
+            
+            ALU16_OP       =  ALU16Opcode;
+            ALU16_CC       =  cc;
+            ALU16_A        =  ea;
+            
+            case (ALU16Reg)
+                ALU16_REG_X:
+                    {cc_nxt, x_nxt}    =  ALU16; 
+                ALU16_REG_Y:
+                    {cc_nxt, y_nxt}    =  ALU16;
+                ALU16_REG_U:
+                    u_nxt = ALU16[15:0];
+                ALU16_REG_S:
+                    s_nxt = ALU16[15:0];
+                default:
+                begin
+                end
+            endcase
+            
+            rLIC = 1'b1; // Instruction done!        
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+            
+        end
+        
+    end         
+    
+    
+    CPUSTATE_ALU_DONTCARE:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b1;
+        rBUSY = 1'b1; // We do nothing here, but on the real 6809, they did the modify phase here.  :|
+        CpuState_nxt   =  CPUSTATE_ALU_WRITEBACK;
+    end
+    
+    CPUSTATE_ALU_WRITEBACK:
+    begin
+        addr_nxt       =  ea;
+        RnWOut =  0;    // Write
+        DOutput   =  tmp[7:0];
+        rLIC = 1'b1; // Instruction done!      
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+    end
+    
+    CPUSTATE_LD16_LO:
+    begin
+        addr_nxt       =  ea;
+        
+        case (ALU16Reg)
+            ALU16_REG_X:
+            begin
+                x_nxt[7:0] =  D[7:0];
+                ALU16_B[15:8] = x[15:8];
+            end
+            ALU16_REG_D:
+            begin
+                b_nxt      =  D[7:0];
+                ALU16_B[15:8] = a;
+            end
+            ALU16_REG_Y:
+            begin
+                y_nxt[7:0] =  D[7:0];
+                ALU16_B[15:8] = y[15:8];                
+            end
+            ALU16_REG_S:
+            begin
+                s_nxt[7:0] =  D[7:0];                                
+                ALU16_B[15:8] = s[15:8];                
+            end
+            ALU16_REG_U:
+            begin
+                u_nxt[7:0] =  D[7:0];                                
+                ALU16_B[15:8] = u[15:8];                
+            end
+            default:
+            begin
+            end
+            
+        endcase
+
+        ALU16_OP       =    ALU16Opcode;
+        ALU16_CC       =    cc;
+        ALU16_A        =    8'H00;        
+        ALU16_B[7:0]   =    D[7:0];
+        cc_nxt         =    ALU16[23:16];
+        
+        rLIC = 1'b1; // Instruction done!        
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+    end
+    
+    CPUSTATE_ST16_LO:
+    begin
+        addr_nxt       =  ea;
+        ea_nxt =  ea_p1;
+        case (StoreRegisterNum)
+            ST16_REG_X:
+                DOutput[7:0]  =  x[7:0];
+            ST16_REG_Y:
+                DOutput[7:0]  =  y[7:0];
+            ST16_REG_U:
+                DOutput[7:0]  =  u[7:0];
+            ST16_REG_S:
+                DOutput[7:0]  =  s[7:0];
+            ST16_REG_D:
+                DOutput[7:0]  =  b[7:0];
+            default:
+            begin
+            end
+        endcase
+        RnWOut     =  0;        // write
+        
+        rLIC = 1'b1; // Instruction done!        
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;                
+    end
+    
+    CPUSTATE_ALU16_LO:
+    begin
+        addr_nxt       =  ea;
+        
+        ALU16_OP       =  ALU16Opcode;
+        ALU16_CC       =  cc;
+        
+        ALU16_B        =  {tmp[15:8], D[7:0]};
+        
+        case (ALU16Reg)
+            ALU16_REG_X:
+                ALU16_A        =  x;
+            ALU16_REG_D:
+                ALU16_A        =  {a, b};
+            ALU16_REG_Y:
+                ALU16_A        =  y;
+            ALU16_REG_S:
+                ALU16_A        =  s;                                
+            ALU16_REG_U:
+                ALU16_A        =  u;      
+            default:
+                ALU16_A        =  16'H0;
+                
+        endcase
+        
+        if (ALU16OpWriteback)
+        begin
+            case (ALU16Reg)
+                ALU16_REG_X:
+                    {cc_nxt, x_nxt}        =  ALU16; 
+                ALU16_REG_D:
+                    {cc_nxt, a_nxt, b_nxt} =  ALU16;
+                ALU16_REG_Y:
+                    {cc_nxt, y_nxt}        =  ALU16;
+                ALU16_REG_U:
+                    {cc_nxt, u_nxt}        =  ALU16;
+                ALU16_REG_S:
+                    {cc_nxt, s_nxt}        =  ALU16;
+                default:
+                begin
+                end
+            endcase
+        end
+        else
+            cc_nxt = ALU16[23:16];
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_ALU16_DONTCARE;
+    end
+    
+    CPUSTATE_ALU16_DONTCARE:
+    begin
+        addr_nxt = 16'HFFFF;
+        rLIC = 1'b1; // Instruction done!        
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+    end
+
+    
+    CPUSTATE_JSR_DONTCARE:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_JSR_RETLO;
+    end
+    
+    CPUSTATE_JSR_RETLO:
+    begin
+        addr_nxt       =  s_m1;
+        s_nxt  =  s_m1;
+        RnWOut =  0;
+        DOutput   =  tmp[7:0];
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_JSR_RETHI;
+    end
+    
+    CPUSTATE_JSR_RETHI:
+    begin
+        addr_nxt       =  s_m1;
+        s_nxt  =  s_m1;
+        RnWOut =  0;
+        DOutput   =  tmp[15:8];
+        rLIC = 1'b1; // Instruction done!        
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+    end
+    
+    CPUSTATE_EXTENDED_ADDRLO:
+    begin
+        addr_nxt       =  pc;
+        pc_nxt =  pc_p1;
+        ea_nxt[7:0]    =  D[7:0];
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_EXTENDED_DONTCARE;
+    end
+    
+    CPUSTATE_EXTENDED_DONTCARE:
+    begin
+        addr_nxt       =  16'HFFFF;
+        if (IsJMP(Inst1))
+        begin
+            pc_nxt =  ea;
+            rLIC = 1'b1; // Instruction done!            
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+        end
+        else
+        begin
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_ALU_EA;
+        end
+    end
+    
+    CPUSTATE_INDEXED_BASE:
+    begin
+        addr_nxt       =  pc;
+
+        Inst3_nxt      =  D[7:0];
+        
+        case (IndexedRegister)
+            IDX_REG_X:
+                ALU16_A        =  x;
+            IDX_REG_Y:
+                ALU16_A        =  y;
+            IDX_REG_U:
+                ALU16_A        =  u;
+            IDX_REG_S:
+                ALU16_A        =  s;
+            IDX_REG_PC:
+                ALU16_A        =  pc_p1;
+            default:
+                ALU16_A        =  16'H0;
+        endcase
+        ALU16_OP       =  ALUOP16_ADD;                    
+        
+        case (IndexedMode)
+            IDX_MODE_NOOFFSET:
+            begin
+                case (IndexedRegister)
+                    IDX_REG_X:
+                        ea_nxt =  x;
+                    IDX_REG_Y:
+                        ea_nxt =  y;
+                    IDX_REG_U:
+                        ea_nxt =  u;
+                    IDX_REG_S:
+                        ea_nxt =  s;
+                    default:
+                        ea_nxt =  16'H0;
+                endcase
+                
+                if (IndexedIndirect)
+                begin
+                    rAVMA = 1'b1;
+                    CpuState_nxt   =  CPUSTATE_INDIRECT_HI;
+                end
+                else
+                begin
+                    if (IsJMP(Inst1))
+                    begin
+                        pc_nxt =  ea_nxt;
+                        rLIC = 1'b1; // Instruction done!                        
+                        rAVMA = 1'b1;
+                        CpuState_nxt   =  CPUSTATE_FETCH_I1;
+                    end
+                    else
+                    begin
+                        rAVMA = 1'b1;
+                        CpuState_nxt   =  CPUSTATE_ALU_EA;
+                    end
+                end
+            end
+            
+            IDX_MODE_5BIT_OFFSET:
+            begin
+                // The offset is the bottom 5 bits of the Index Postbyte, which is Inst2 here.
+                // We'll sign-extend it to 16 bits.
+                ALU16_B    =  { {11{Inst2[4]}}, Inst2[4:0] };
+                ea_nxt     =  ALU16[15:0]; 
+                rAVMA = 1'b0;
+                CpuState_nxt   =  CPUSTATE_IDX_DONTCARE3;
+            end
+
+
+            IDX_MODE_8BIT_OFFSET_PC:
+            begin
+                ALU16_B        =  { {8{D[7]}}, D[7:0] };
+                pc_nxt =  pc_p1;
+                ea_nxt =  ALU16[15:0];
+                rAVMA = 1'b0;
+                CpuState_nxt   =  CPUSTATE_IDX_DONTCARE3;
+            end
+            
+            IDX_MODE_8BIT_OFFSET:
+            begin
+                ALU16_B        =  { {8{D[7]}}, D[7:0] };
+                pc_nxt =  pc_p1;
+                ea_nxt =  ALU16[15:0];
+                rAVMA = 1'b0;
+                CpuState_nxt   =  CPUSTATE_IDX_DONTCARE3;
+            end
+            
+            IDX_MODE_A_OFFSET:
+            begin
+                ALU16_B        =  { {8{a[7]}}, a[7:0] };
+                rAVMA = 1'b0;
+                CpuState_nxt   =  CPUSTATE_IDX_DONTCARE3;
+                ea_nxt =  ALU16[15:0];
+            end
+            
+            IDX_MODE_B_OFFSET:
+            begin
+                ALU16_B    =  { {8{b[7]}}, b[7:0] };
+                rAVMA = 1'b0;
+                CpuState_nxt   =  CPUSTATE_IDX_DONTCARE3;
+                ea_nxt =  ALU16[15:0];
+            end
+            
+            IDX_MODE_D_OFFSET:
+            begin
+                ALU16_B    =  {a, b};
+                
+                ea_nxt     =  ALU16[15:0];
+                rAVMA = 1'b1;
+                CpuState_nxt = CPUSTATE_IDX_DOFF_DONTCARE1;
+            end
+            
+            IDX_MODE_POSTINC1:
+            begin
+                ALU16_B    =  16'H1;
+                ea_nxt     =  ALU16_A;
+                case (IndexedRegister)
+                IDX_REG_X:
+                    x_nxt      =  ALU16[15:0];
+                IDX_REG_Y:
+                    y_nxt      =  ALU16[15:0];
+                IDX_REG_U:
+                    u_nxt      =  ALU16[15:0];
+                IDX_REG_S:
+                    s_nxt      =  ALU16[15:0];
+                default:
+                begin
+                end
+                endcase
+                rAVMA = 1'b0;
+                CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE2;  
+            end
+            
+            IDX_MODE_POSTINC2:
+            begin
+                ALU16_B        =  16'H2;
+                ea_nxt =  ALU16_A;
+                case (IndexedRegister)
+                    IDX_REG_X:
+                        x_nxt  =  ALU16[15:0];
+                    IDX_REG_Y:
+                        y_nxt  =  ALU16[15:0];
+                    IDX_REG_U:
+                        u_nxt  =  ALU16[15:0];
+                    IDX_REG_S:
+                        s_nxt  =  ALU16[15:0];
+                    default:
+                    begin
+                    end
+                endcase
+                rAVMA = 1'b0;
+                CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE0;
+            end
+            
+            IDX_MODE_PREDEC1:
+            begin
+                ALU16_B        =  16'HFFFF;     // -1
+                case (IndexedRegister)
+                    IDX_REG_X:
+                        x_nxt  =  ALU16[15:0];
+                    IDX_REG_Y:
+                        y_nxt  =  ALU16[15:0];
+                    IDX_REG_U:
+                        u_nxt  =  ALU16[15:0];
+                    IDX_REG_S:
+                        s_nxt  =  ALU16[15:0];
+                    default:
+                    begin
+                    end
+                endcase
+                ea_nxt =  ALU16[15:0];
+                rAVMA = 1'b0;
+                CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE2;                              
+            end
+            
+            IDX_MODE_PREDEC2:
+            begin
+                ALU16_B        =  16'HFFFE;     // -2
+                case (IndexedRegister)
+                    IDX_REG_X:
+                        x_nxt  =  ALU16[15:0];
+                    IDX_REG_Y:
+                        y_nxt  =  ALU16[15:0];
+                    IDX_REG_U:
+                        u_nxt  =  ALU16[15:0];
+                    IDX_REG_S:
+                        s_nxt  =  ALU16[15:0];
+                    default:
+                    begin
+                    end
+                endcase
+                ea_nxt =  ALU16[15:0];
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE0;                            
+            end
+            
+            IDX_MODE_16BIT_OFFSET_PC:            
+            begin
+                tmp_nxt[15:8]  =  D[7:0];
+                pc_nxt =  pc_p1;
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_IDX_16OFFSET_LO;
+            end
+
+            IDX_MODE_16BIT_OFFSET:
+            begin
+                tmp_nxt[15:8]  =  D[7:0];
+                pc_nxt =  pc_p1;
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_IDX_16OFFSET_LO;
+            end
+
+            IDX_MODE_EXTENDED_INDIRECT:
+            begin
+                ea_nxt[15:8] = D[7:0];
+                pc_nxt =  pc_p1;
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_IDX_EXTIND_LO;
+            end
+            
+            default:
+            begin
+                rLIC = 1'b1;
+                CpuState_nxt = PostIllegalState;
+            end
+            
+        endcase
+    end
+    
+    CPUSTATE_IDX_OFFSET_LO:
+    begin
+        tmp_nxt[7:0]   =  D[7:0];
+        addr_nxt       =  pc;
+        pc_nxt =  pc_p1;
+        ALU16_B    =  tmp_nxt;
+        
+        case (IndexedRegister)
+            IDX_REG_X:
+                ALU16_A    =  x;
+            IDX_REG_Y:
+                ALU16_A    =  y;
+            IDX_REG_U:
+                ALU16_A    =  u;
+            IDX_REG_S:
+                ALU16_A    =  s;
+            IDX_REG_PC:
+                ALU16_A    =  pc;
+            default:
+                ALU16_A    =  16'H0;
+        endcase
+        ALU16_OP   =  ALUOP16_ADD;                    
+        
+        ea_nxt     =  ALU16[15:0];
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE1;
+    end
+    
+    
+    CPUSTATE_IDX_DONTCARE3:
+    begin
+        addr_nxt   =  16'HFFFF;
+        if (IndexedIndirect)
+        begin
+            rAVMA = 1'b1;
+            CpuState_nxt = CPUSTATE_INDIRECT_HI;
+        end
+        else
+        begin
+            if (IsJMP(Inst1))
+            begin
+                pc_nxt =  ea;
+                rLIC = 1'b1; // Instruction done!                
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_FETCH_I1;
+            end
+            else
+            begin
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_ALU_EA;
+            end
+        end
+
+    end                
+    
+    CPUSTATE_IDX_16OFFSET_LO:
+    begin
+        addr_nxt       =  pc;
+        pc_nxt =  pc_p1;
+
+        case (IndexedRegister)
+            IDX_REG_X:
+                ALU16_A    =  x;
+            IDX_REG_Y:
+                ALU16_A    =  y;
+            IDX_REG_U:
+                ALU16_A    =  u;
+            IDX_REG_S:
+                ALU16_A    =  s;
+            IDX_REG_PC:
+                ALU16_A    =  pc_nxt;  // Whups; tricky; not part of the actual pattern
+            default:
+                ALU16_A    =  x; // Default to something
+        endcase
+
+        ALU16_OP   =  ALUOP16_ADD;                    
+        
+        ALU16_B    =  {tmp[15:8], D[7:0]};
+        
+        ea_nxt     =  ALU16[15:0];
+        rAVMA = 1'b1;
+        CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE1;
+    end
+    
+    CPUSTATE_IDX_16OFF_DONTCARE1:
+    begin
+        addr_nxt       =  pc;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE2;
+    end
+
+    CPUSTATE_IDX_16OFF_DONTCARE0:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE2;
+    end
+
+    CPUSTATE_IDX_16OFF_DONTCARE2:
+    begin
+        addr_nxt       =  16'HFFFF;
+        if (IndexedRegister == IDX_REG_PC)
+        begin
+            rAVMA = 1'b0;
+            CpuState_nxt = CPUSTATE_IDX_PC16OFF_DONTCARE;
+        end
+        else        
+        begin
+            rAVMA = 1'b0;
+            CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE3;
+        end
+    end
+    
+    CPUSTATE_IDX_PC16OFF_DONTCARE:
+    begin
+        addr_nxt       =  16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt   =  CPUSTATE_IDX_16OFF_DONTCARE3;
+    end
+    
+    
+    CPUSTATE_IDX_16OFF_DONTCARE3:
+    begin
+        addr_nxt       =  16'HFFFF;
+        if (IndexedIndirect)
+        begin
+            rAVMA = 1'b1;
+            CpuState_nxt = CPUSTATE_INDIRECT_HI;
+        end
+        else
+        begin
+            if (IsJMP(Inst1))
+            begin
+                pc_nxt =  ea;
+                rLIC = 1'b1; // Instruction done!                
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_FETCH_I1;
+            end
+            else
+            begin
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_ALU_EA;        
+            end
+        end
+    end
+
+    CPUSTATE_IDX_DOFF_DONTCARE1:
+    begin
+        addr_nxt = pc_p1;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_IDX_DOFF_DONTCARE2;
+    end
+
+    CPUSTATE_IDX_DOFF_DONTCARE2:
+    begin
+        addr_nxt = pc_p2;
+        rAVMA = 1'b0;
+        CpuState_nxt = CPUSTATE_IDX_16OFF_DONTCARE2;
+    end
+
+    CPUSTATE_IDX_DOFF_DONTCARE3:
+    begin
+        addr_nxt = pc_p3;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_IDX_DOFF_DONTCARE2;
+    end
+
+    CPUSTATE_IDX_EXTIND_LO:
+    begin
+        ea_nxt[7:0]   =  D[7:0];
+        addr_nxt       =  pc;
+        pc_nxt =  pc_p1;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_IDX_EXTIND_DONTCARE;        
+    end
+    
+    CPUSTATE_IDX_EXTIND_DONTCARE:
+    begin
+        addr_nxt = pc;
+        if (IndexedIndirect)
+        begin
+            rAVMA = 1'b1;
+            CpuState_nxt = CPUSTATE_INDIRECT_HI;
+        end
+        else
+        begin
+            if (IsJMP(Inst1))
+            begin
+                pc_nxt =  ea;
+                rLIC = 1'b1; // Instruction done!                
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_FETCH_I1;
+            end
+            else
+            begin
+                rAVMA = 1'b1;
+                CpuState_nxt   =  CPUSTATE_ALU_EA;        
+            end
+        end
+    end
+    
+    CPUSTATE_INDIRECT_HI:
+    begin
+        addr_nxt = ea;
+        tmp_nxt[15:8] = D[7:0];
+        rAVMA = 1'b1;
+        rBUSY = 1'b1;
+        CpuState_nxt = CPUSTATE_INDIRECT_LO;
+    end                        
+
+    CPUSTATE_INDIRECT_LO:
+    begin
+        addr_nxt = ea_p1;
+        ea_nxt[15:8] = tmp_nxt[15:8];
+        ea_nxt[7:0] = D[7:0];
+        rAVMA = 1'b0;
+        CpuState_nxt = CPUSTATE_INDIRECT_DONTCARE;
+    end
+ 
+    CPUSTATE_INDIRECT_DONTCARE:
+    begin
+        addr_nxt = 16'HFFFF;
+        if (IsJMP(Inst1))
+        begin
+            pc_nxt =  ea;
+            rLIC = 1'b1; // Instruction done!            
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_FETCH_I1;
+        end
+        else
+        begin
+            rAVMA = 1'b1;
+            CpuState_nxt   =  CPUSTATE_ALU_EA;
+        end
+    end
+    
+    CPUSTATE_MUL_ACTION:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b0;
+        // tmp = result
+        // ea = additor (the shifted multiplicand)
+        // a = counter
+        // b is the multiplier (which gets shifted right)
+        if (a != 8'H00)
+        begin
+            if (b[0])
+            begin
+                tmp_nxt = tmp + ea;
+            end
+            ea_nxt = {ea[14:0], 1'b0};
+            b_nxt = {1'b0, b[7:1]};
+            a_nxt = a - 8'H1;
+        end
+        else
+        begin
+            {a_nxt, b_nxt} = tmp;
+            
+            cc_nxt[CC_Z_BIT] = (tmp == 0);
+            cc_nxt[CC_C_BIT] = tmp[7];
+            rLIC = 1'b1; // Instruction done!            
+            rAVMA = 1'b1;
+            CpuState_nxt = CPUSTATE_FETCH_I1;
+        end
+    end
+    
+    CPUSTATE_PSH_DONTCARE1:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt = CPUSTATE_PSH_DONTCARE2;
+    end
+
+    CPUSTATE_PSH_DONTCARE2:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_PSH_DONTCARE3;
+    end
+    
+    CPUSTATE_PSH_DONTCARE3:
+    begin
+        addr_nxt = (Inst1[1]) ? u : s;
+        
+        CpuState_nxt = CPUSTATE_PSH_ACTION;
+    end    
+
+    CPUSTATE_PSH_ACTION:
+    begin
+        rAVMA = 1'b1;
+        if (tmp[7] & ~(tmp[15]))                    // PC_LO
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = pc[7:0];
+            RnWOut = 1'b0; // write
+            tmp_nxt[15] = 1'b1;            
+        end
+        else if (tmp[7] & (tmp[15]))                    // PC_HI
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = pc[15:8];
+            RnWOut = 1'b0; // write
+            tmp_nxt[7] = 1'b0;
+            tmp_nxt[15] = 1'b0;            
+        end
+        else if (tmp[6] & ~(tmp[15]))                    // U/S_LO
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = (tmp[14]) ? s[7:0] : u[7:0]; 
+            RnWOut = 1'b0; // write
+            tmp_nxt[15] = 1'b1;            
+        end
+        else if (tmp[6] & (tmp[15]))                    // U/S_HI
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = (tmp[14]) ? s[15:8] : u[15:8]; 
+            RnWOut = 1'b0; // write
+            tmp_nxt[6] = 1'b0;
+            tmp_nxt[15] = 1'b0;            
+        end
+        else if (tmp[5] & ~(tmp[15]))                    // Y_LO
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = y[7:0];
+            RnWOut = 1'b0; // write
+            tmp_nxt[15] = 1'b1;            
+        end
+        else if (tmp[5] & (tmp[15]))                    // Y_HI
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = y[15:8];
+            RnWOut = 1'b0; // write
+            tmp_nxt[5] = 1'b0;
+            tmp_nxt[15] = 1'b0;            
+        end        
+        else if (tmp[4] & ~(tmp[15]))                    // X_LO
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = x[7:0];
+            RnWOut = 1'b0; // write
+            tmp_nxt[15] = 1'b1;            
+        end
+        else if (tmp[4] & (tmp[15]))                    // X_HI
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = x[15:8];
+            RnWOut = 1'b0; // write
+            tmp_nxt[4] = 1'b0;
+            tmp_nxt[15] = 1'b0;            
+        end
+        else if (tmp[3])                    // DP
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = dp;
+            RnWOut = 1'b0; // write
+            tmp_nxt[3] = 1'b0;        
+        end
+        else if (tmp[2])                    // B
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = b;
+            RnWOut = 1'b0; // write
+            tmp_nxt[2] = 1'b0;        
+        end
+        else if (tmp[1])                    // A
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = a;
+            RnWOut = 1'b0; // write
+            tmp_nxt[1] = 1'b0;        
+        end
+        else if (tmp[0])                    // CC
+        begin
+            addr_nxt = (tmp[14]) ? u_m1 : s_m1;
+            if (tmp[14])
+                u_nxt = u_m1;
+            else
+                s_nxt = s_m1;
+            DOutput = cc;
+            RnWOut = 1'b0; // write
+            tmp_nxt[0] = 1'b0;        
+        end
+        if (tmp[13]) // Then we're pushing for an IRQ, and LIC is supposed to be set.
+            rLIC = 1'b1;
+        if (tmp_nxt[7:0] == 8'H00)
+        begin
+            if (NextState == CPUSTATE_FETCH_I1)
+            begin
+                rAVMA = 1'b1;
+                rLIC = 1'b1;
+            end
+            else
+                rAVMA = 1'b0;
+            CpuState_nxt  = NextState;
+        end                                           
+    end
+    
+    CPUSTATE_PUL_DONTCARE1:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt = CPUSTATE_PUL_DONTCARE2;
+    end
+
+    CPUSTATE_PUL_DONTCARE2:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_PUL_ACTION;
+    end    
+
+    CPUSTATE_PUL_ACTION:
+    begin
+        rAVMA = 1'b1;
+        if (tmp[0])                    // CC
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            cc_nxt = D[7:0];
+            if (tmp[12] == 1'b1) // This pull is from an RTI, the E flag comes from the retrieved CC, and set the tmp_nxt accordingly, indicating what other registers to retrieve
+            begin
+                if (D[CC_E_BIT])
+                    tmp_nxt[7:0] = 8'HFE;     // Retrieve all registers (ENTIRE) [CC is already retrieved]
+                else
+                    tmp_nxt[7:0] = 8'H80;     // Retrieve PC and CC [CC is already retrieved]
+            end
+            else
+                tmp_nxt[0] = 1'b0;
+        end 
+        else if (tmp[1])                    // A
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            a_nxt = D[7:0];
+            tmp_nxt[1] = 1'b0;
+        end         
+        else if (tmp[2])                    // B
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            b_nxt = D[7:0];
+            tmp_nxt[2] = 1'b0;
+        end 
+        else if (tmp[3])                    // DP
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            dp_nxt = D[7:0];
+            tmp_nxt[3] = 1'b0;
+        end        
+        else if (tmp[4] & (~tmp[15]))                    // X_HI
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            x_nxt[15:8] = D[7:0];
+            tmp_nxt[15] = 1'b1;            
+        end
+        else if (tmp[4] & tmp[15])                    // X_LO
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            x_nxt[7:0] = D[7:0];
+            tmp_nxt[4] = 1'b0;
+            tmp_nxt[15] = 1'b0;            
+        end
+        else if (tmp[5] & (~tmp[15]))                    // Y_HI
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            y_nxt[15:8] = D[7:0];
+            tmp_nxt[15] = 1'b1;            
+        end
+        else if (tmp[5] & tmp[15])                    // Y_LO
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            y_nxt[7:0] = D[7:0];
+            tmp_nxt[5] = 1'b0;
+            tmp_nxt[15] = 1'b0;            
+        end
+        else if (tmp[6] & (~tmp[15]))                    // U/S_HI
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            if (tmp[14])
+                s_nxt[15:8] = D[7:0];
+            else
+                u_nxt[15:8] = D[7:0];
+            tmp_nxt[15] = 1'b1;            
+        end
+        else if (tmp[6] & tmp[15])                    // U/S_LO
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            if (tmp[14])
+                s_nxt[7:0] = D[7:0];
+            else
+                u_nxt[7:0] = D[7:0];
+            tmp_nxt[6] = 1'b0;
+            tmp_nxt[15] = 1'b0;            
+        end
+        else if (tmp[7] & (~tmp[15]))                    // PC_HI
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            pc_nxt[15:8] = D[7:0];
+            tmp_nxt[15] = 1'b1;            
+        end
+        else if (tmp[7] & tmp[15])                    // PC_LO
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (tmp[14])
+                u_nxt = u_p1;
+            else
+                s_nxt = s_p1;
+            pc_nxt[7:0] = D[7:0];
+            tmp_nxt[7] = 1'b0;
+            tmp_nxt[15] = 1'b0;            
+        end
+        else
+        begin
+            addr_nxt = (tmp[14]) ? u : s;
+            if (NextState == CPUSTATE_FETCH_I1)
+            begin
+                rAVMA = 1'b1;
+                rLIC = 1'b1;
+            end
+            else
+                rAVMA = 1'b0;
+            CpuState_nxt  = NextState;
+        end  
+    end
+                                      
+    CPUSTATE_NMI_START:
+    begin
+        NMIClear_nxt = 1'b1;
+        addr_nxt = pc;
+        // tmp stands as the bits to push to the stack
+        tmp_nxt = 16'H20FF; // Save to the S stack, PC, U, Y, X, DP, B, A, CC; set LIC on every push 
+        NextState_nxt = CPUSTATE_IRQ_DONTCARE2;
+        rAVMA = 1'b0;
+        CpuState_nxt = CPUSTATE_IRQ_DONTCARE;
+        IntType_nxt = INTTYPE_NMI;
+        cc_nxt[CC_E_BIT] = 1'b1;
+    end
+    
+    CPUSTATE_IRQ_START:
+    begin
+        addr_nxt = pc;
+        tmp_nxt = 16'H20FF; // Save to the S stack, PC, U, Y, X, DP, B, A, CC; set LIC on every push 
+        NextState_nxt = CPUSTATE_IRQ_DONTCARE2;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_IRQ_DONTCARE;
+        IntType_nxt = INTTYPE_IRQ;        
+        cc_nxt[CC_E_BIT] = 1'b1;
+    end
+
+    CPUSTATE_FIRQ_START:
+    begin
+        addr_nxt = pc;
+        tmp_nxt = 16'H2081; // Save to the S stack, PC, CC; set LIC on every push 
+        NextState_nxt = CPUSTATE_IRQ_DONTCARE2;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_IRQ_DONTCARE;
+        IntType_nxt = INTTYPE_FIRQ;        
+        cc_nxt[CC_E_BIT] = 1'b0;
+    end
+    
+    CPUSTATE_SWI_START:
+    begin
+        addr_nxt = pc;
+        tmp_nxt = 16'H00FF; // Save to the S stack, PC, U, Y, X, DP, B, A, CC
+
+        NextState_nxt = CPUSTATE_IRQ_DONTCARE2;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_IRQ_DONTCARE;
+        if (InstPage3)
+            IntType_nxt = INTTYPE_SWI3;
+        if (InstPage2)
+            IntType_nxt = INTTYPE_SWI2;
+        else
+            IntType_nxt = INTTYPE_SWI;        
+            
+        cc_nxt[CC_E_BIT] = 1'b1;
+    end
+    
+    CPUSTATE_IRQ_DONTCARE:
+    begin
+        NMIClear_nxt = 1'b0;    
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_PSH_ACTION;
+    end
+    
+    
+    CPUSTATE_IRQ_DONTCARE2:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_IRQ_VECTOR_HI;
+        rLIC = 1'b1;
+    end
+    
+    CPUSTATE_IRQ_VECTOR_HI:
+    begin
+        case (IntType)
+            INTTYPE_NMI:
+            begin
+                addr_nxt = `NMI_VECTOR;
+                BS_nxt         =  1'b1; // ACK Interrupt
+            end
+            INTTYPE_IRQ:
+            begin
+                addr_nxt = `IRQ_VECTOR;
+                BS_nxt         =  1'b1; // ACK Interrupt
+            end
+            INTTYPE_SWI:
+            begin
+                addr_nxt = `SWI_VECTOR;
+            end
+            INTTYPE_FIRQ:
+            begin
+                addr_nxt = `FIRQ_VECTOR;
+                BS_nxt         =  1'b1; // ACK Interrupt
+            end
+            INTTYPE_SWI2:
+            begin
+                addr_nxt = `SWI2_VECTOR;
+            end
+            INTTYPE_SWI3:
+            begin
+                addr_nxt = `SWI3_VECTOR;
+            end
+            default: // make the default an IRQ, even though it really should never happen 
+            begin
+                addr_nxt = `IRQ_VECTOR;
+                BS_nxt         =  1'b1; // ACK Interrupt
+            end
+        endcase
+        
+        pc_nxt[15:8] = D[7:0];
+        rAVMA = 1'b1;
+        rBUSY = 1'b1;
+        rLIC = 1'b1;
+        CpuState_nxt = CPUSTATE_IRQ_VECTOR_LO;
+        
+        
+    end
+    
+    CPUSTATE_IRQ_VECTOR_LO:
+    begin
+        case (IntType)
+            INTTYPE_NMI:
+            begin
+                addr_nxt = `NMI_VECTOR+16'H1;
+                cc_nxt[CC_I_BIT] = 1'b1;
+                cc_nxt[CC_F_BIT] = 1'b1;
+                BS_nxt         =  1'b1; // ACK Interrupt
+            end                
+            INTTYPE_IRQ:
+            begin
+                addr_nxt = `IRQ_VECTOR+16'H1;
+                cc_nxt[CC_I_BIT] = 1'b1;                
+                BS_nxt         =  1'b1; // ACK Interrupt
+            end  
+            INTTYPE_SWI:
+            begin
+                addr_nxt = `SWI_VECTOR+16'H1;
+                cc_nxt[CC_F_BIT] = 1'b1;
+                cc_nxt[CC_I_BIT] = 1'b1;
+                rLIC = 1'b1;
+            end                  
+            INTTYPE_FIRQ:
+            begin
+                addr_nxt = `FIRQ_VECTOR+16'H1;
+                cc_nxt[CC_F_BIT] = 1'b1;                                
+                cc_nxt[CC_I_BIT] = 1'b1;
+                BS_nxt         =  1'b1; // ACK Interrupt
+            end                  
+            INTTYPE_SWI2:
+            begin
+                addr_nxt = `SWI2_VECTOR+16'H1;
+                rLIC = 1'b1;                
+            end                  
+            INTTYPE_SWI3:
+            begin
+                addr_nxt = `SWI3_VECTOR+16'H1;
+                rLIC = 1'b1;
+            end                
+            default:
+            begin
+            end
+        endcase
+    
+        pc_nxt[7:0] = D[7:0];
+        rAVMA = 1'b1;
+        rLIC = 1'b1;
+        CpuState_nxt = CPUSTATE_INT_DONTCARE;
+    end
+    
+    CPUSTATE_INT_DONTCARE:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b1;
+        rLIC = 1'b1;
+        CpuState_nxt = CPUSTATE_FETCH_I1;
+    end
+
+    CPUSTATE_CC_DONTCARE:
+    begin
+        addr_nxt = pc;
+        rLIC = 1'b1;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_FETCH_I1;
+    end
+
+    CPUSTATE_TST_DONTCARE1:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b0;
+        CpuState_nxt = CPUSTATE_TST_DONTCARE2;
+    end
+
+    CPUSTATE_TST_DONTCARE2:
+    begin
+        addr_nxt = 16'HFFFF;
+        rLIC = 1'b1;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_FETCH_I1;
+    end
+
+    CPUSTATE_DEBUG:
+    begin
+        addr_nxt = tmp;
+        rLIC = 1'b1;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_FETCH_I1;
+    end
+    
+    CPUSTATE_16IMM_DONTCARE:
+    begin
+        addr_nxt = 16'HFFFF;
+        rLIC = 1'b1;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_FETCH_I1;
+    end
+    
+    CPUSTATE_SYNC:
+    begin
+        addr_nxt = 16'HFFFF;
+        BA_nxt = 1'b1;
+        rLIC   = 1'b1;
+        rAVMA  = 1'b0;
+
+        if (~(NMILatched & FIRQLatched & IRQLatched))
+        begin
+            CpuState_nxt = CPUSTATE_SYNC_EXIT;
+        end
+    end
+
+    CPUSTATE_SYNC_EXIT:
+    begin
+        addr_nxt = 16'HFFFF;
+        BA_nxt = 1'b1;
+        rLIC   = 1'b1;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_FETCH_I1;
+    end
+
+
+    CPUSTATE_DMABREQ:
+    begin
+        rAVMA = 1'b0;
+        addr_nxt = 16'HFFFF;
+        BS_nxt = 1'b1;
+        BA_nxt = 1'b1;
+        rLIC   = 1'b1;
+        tmp_nxt[3:0] = tmp[3:0] - 1'b1;
+        if ( (tmp[3:0] == 4'H0) | (DMABREQSample2) )
+        begin
+            CpuState_nxt = CPUSTATE_DMABREQ_EXIT;
+        end
+    end
+    
+    CPUSTATE_DMABREQ_EXIT:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_FETCH_I1;
+    end
+    
+    CPUSTATE_HALTED:
+    begin
+        rAVMA = 1'b0;
+        addr_nxt = 16'HFFFF;
+        BS_nxt = 1'b1;
+        BA_nxt = 1'b1;
+        rLIC   = 1'b1;
+        if (HALTSample2)
+        begin
+            CpuState_nxt = CPUSTATE_HALT_EXIT2;
+        end
+    end
+
+
+    CPUSTATE_HALT_EXIT2:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_FETCH_I1;
+    end
+
+    CPUSTATE_STOP:
+    begin
+        addr_nxt = 16'HDEAD;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_STOP2;
+    end
+
+    CPUSTATE_STOP2:
+    begin
+        addr_nxt = pc;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_STOP3;
+    end
+
+    CPUSTATE_STOP3:
+    begin
+        addr_nxt = 16'H0000; //{Inst1, Inst2};
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_STOP;
+    end
+
+    // The otherwise critically useful Figure 18 in the 6809 datasheet contains an error;
+    // it lists that CWAI has a tri-stated bus while it waits for an interrupt.
+    // That is not true.  SYNC tristates the bus, as do things like /HALT and /DMABREQ.
+    // CWAI does not.  It waits with /VMA cycles on the bus until an interrupt occurs.
+    // The implementation here fits with the 6809 Programming Manual and other Motorola
+    // sources, not with that typo in Figure 18.
+    CPUSTATE_CWAI:
+    begin
+        addr_nxt = pc;
+        cc_nxt = {1'b1, (cc[6:0] & Inst2[6:0])}; // Set E flag, AND CC with CWAI argument
+        tmp_nxt = 16'H00FF; // Save to the S stack, PC, U, Y, X, DP, B, A, CC
+
+        NextState_nxt = CPUSTATE_CWAI_POST;
+        rAVMA = 1'b0;
+        CpuState_nxt = CPUSTATE_CWAI_DONTCARE1;
+    end
+    
+    CPUSTATE_CWAI_DONTCARE1:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b1;
+        CpuState_nxt = CPUSTATE_PSH_ACTION;
+    end
+    
+    CPUSTATE_CWAI_POST:
+    begin
+        addr_nxt = 16'HFFFF;
+        rAVMA = 1'b0;
+
+        CpuState_nxt = CPUSTATE_CWAI_POST;
+
+        // Wait for an interrupt
+        if (NMILatched == 0)
+        begin
+            rAVMA = 1'b1;
+            IntType_nxt = INTTYPE_NMI;
+            cc_nxt[CC_F_BIT] = 1'b1;
+            cc_nxt[CC_I_BIT] = 1'b1;
+            CpuState_nxt = CPUSTATE_IRQ_VECTOR_HI;
+        end
+        else if ((FIRQLatched == 0) && (cc[CC_F_BIT] == 0))
+        begin
+            rAVMA = 1'b1;
+            cc_nxt[CC_F_BIT] = 1'b1;
+            cc_nxt[CC_I_BIT] = 1'b1;
+            IntType_nxt = INTTYPE_FIRQ;
+            CpuState_nxt = CPUSTATE_IRQ_VECTOR_HI;
+        end
+        else if ((IRQLatched == 0) && (cc[CC_I_BIT] == 0))
+        begin
+            rAVMA = 1'b1;
+            cc_nxt[CC_I_BIT] = 1'b1;
+            IntType_nxt = INTTYPE_IRQ;
+            CpuState_nxt = CPUSTATE_IRQ_VECTOR_HI;
+        end
+    end
+
+    default: // Picky darned Verilog.
+    begin
+        CpuState_nxt = PostIllegalState;
+    end
+    
+    endcase
+end
+
+endmodule
+
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809s.v b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809s.v
new file mode 100644
index 00000000..9c49239a
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/mc6809-master/mc6809s.v	
@@ -0,0 +1,82 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 09/18/2016 09:25:01 PM
+// Design Name: 
+// Module Name: 6809 Superset module of MC6809 and MC6809E signals
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module mc6809s(
+    input   [7:0] D,
+    output  [7:0] DOut,
+    output  [15:0] ADDR,
+    output  RnW,
+    input   CLK4,
+    output  BS,
+    output  BA,
+    input   nIRQ,
+    input   nFIRQ,
+    input   nNMI,
+    output  AVMA,
+    output  BUSY,
+    output  LIC,
+    input   nRESET,
+    input   nHALT,
+    input   nDMABREQ,
+    output  E,
+    output  Q,
+    output reg [1:0] clk4_cnt,
+    output  [111:0] RegData
+);
+
+    reg     rE;
+    reg     rQ;
+    assign  E = rE;
+    assign  Q = rQ;
+    reg     nCoreRESET;
+    
+ mc6809i corecpu(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(rE), .Q(rQ), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ), .nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nRESET(nCoreRESET),
+                 .nDMABREQ(nDMABREQ), .nHALT(nHALT), .RegData(RegData) );
+                 
+ always @(posedge CLK4)
+ begin
+     clk4_cnt <= clk4_cnt+2'b01;
+     
+     if (nRESET == 0)
+     begin
+         clk4_cnt <= 0;
+         nCoreRESET <= 0;
+     end
+     
+     if ( clk4_cnt == 2'b00  )     // RISING EDGE OF E
+         rE <= 1;
+     
+     if (clk4_cnt == 2'b01)        // RISING EDGE OF Q
+        rQ <= 1;     
+
+     if (clk4_cnt == 2'b10)        // FALLING EDGE OF E
+        rE <= 0;
+     
+     if (clk4_cnt == 2'b11)        // FALLING EDGE OF Q
+     begin
+        rQ <= 0;
+        nCoreRESET <= 1;
+     end
+ end
+       
+    
+endmodule
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace.vhd
new file mode 100644
index 00000000..9693c4e4
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace.vhd	
@@ -0,0 +1,160 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+
+entity PACE is
+  port
+  (
+  	-- clocks and resets
+    clkrst_i        : in from_CLKRST_t;
+	 vma					: out std_logic;
+    -- controller inputs
+    inputs_p1			: in std_logic_vector(7 downto 0);
+    inputs_p2			: in std_logic_vector(7 downto 0);
+    inputs_sys			: in std_logic_vector(7 downto 0);
+    inputs_dip1		: in std_logic_vector(7 downto 0);
+    inputs_dip2		: in std_logic_vector(7 downto 0);
+    -- video
+    video_i         : in from_VIDEO_t;
+    video_o         : out to_VIDEO_t;
+
+    -- audio
+    audio_i         : in from_AUDIO_t;
+    audio_o         : out to_AUDIO_t;
+    platform_i      : in from_PLATFORM_IO_t;
+    platform_o      : out to_PLATFORM_IO_t;
+	 cpu_rom_addr		: out std_logic_vector(15 downto 0);
+	 cpu_rom_do			: in std_logic_vector(7 downto 0);
+	 tile_rom_addr		: out std_logic_vector(12 downto 0);
+	 tile_rom_do		: in std_logic_vector(15 downto 0)
+  );
+end entity PACE;
+
+architecture SYN of PACE is
+
+	constant CLK_1US_COUNTS : integer := 
+    integer(27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY);
+
+  signal to_tilemap_ctl   : to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+  signal from_tilemap_ctl : from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+
+  signal to_bitmap_ctl    : to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+  signal from_bitmap_ctl  : from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+
+  signal to_sprite_reg    : to_SPRITE_REG_t;
+  signal to_sprite_ctl    : to_SPRITE_CTL_t;
+  signal from_sprite_ctl  : from_SPRITE_CTL_t;
+	signal spr0_hit					: std_logic;
+
+  signal to_graphics      : to_GRAPHICS_t;
+	signal from_graphics    : from_GRAPHICS_t;
+	
+	signal to_sound         : to_SOUND_t;
+	signal from_sound       : from_sound_t;
+
+begin
+
+
+  platform_inst : entity work.platform
+    port map
+    (
+      -- clocking and reset
+      clkrst_i        => clkrst_i,
+		vma				 => vma,
+      -- controller inputs
+    inputs_p1       => inputs_p1, 
+    inputs_p2       => inputs_p2, 
+    inputs_sys       => inputs_sys,
+    inputs_dip1       => inputs_dip1, 
+    inputs_dip2       => inputs_dip2, 
+
+      -- graphics
+      bitmap_i        => from_bitmap_ctl,
+      bitmap_o        => to_bitmap_ctl,
+      
+      tilemap_i       => from_tilemap_ctl,
+      tilemap_o       => to_tilemap_ctl,
+      
+      sprite_reg_o    => to_sprite_reg,
+      sprite_i        => from_sprite_ctl,
+      sprite_o        => to_sprite_ctl,
+			spr0_hit				=> spr0_hit,
+      
+      graphics_i      => from_graphics,
+      graphics_o      => to_graphics,
+      
+      -- sound
+      snd_i           => from_sound,
+      snd_o           => to_sound,
+      platform_i      => platform_i,
+      platform_o      => platform_o,
+		cpu_rom_addr      => cpu_rom_addr,
+	   cpu_rom_do	      => cpu_rom_do,
+	   tile_rom_addr     => tile_rom_addr,
+	   tile_rom_do	      => tile_rom_do
+    );
+
+  graphics_inst : entity work.Graphics                                    
+    Port Map
+    (
+      bitmap_ctl_i    => to_bitmap_ctl,
+      bitmap_ctl_o    => from_bitmap_ctl,
+
+      tilemap_ctl_i   => to_tilemap_ctl,
+      tilemap_ctl_o   => from_tilemap_ctl,
+
+      sprite_reg_i    => to_sprite_reg,
+      sprite_ctl_i    => to_sprite_ctl,
+      sprite_ctl_o    => from_sprite_ctl,
+      spr0_hit				=> spr0_hit,
+      
+      graphics_i      => to_graphics,
+      graphics_o      => from_graphics,
+      
+			-- video (incl. clk)
+			video_i					=> video_i,
+			video_o					=> video_o
+    );
+
+	SOUND_BLOCK : block
+		signal snd_data_l	: std_logic_vector(7 downto 0);
+		signal snd_data_r : std_logic_vector(7 downto 0);
+    signal snd_a      : std_logic_vector(15 downto 0);
+	begin
+
+    snd_a <= std_logic_vector(resize(unsigned(to_sound.a), snd_a'length));
+    
+	  sound_inst : entity work.Sound
+      generic map
+      (
+        CLK_MHz     => CLK0_FREQ_MHz
+      )
+	    port map
+	    (
+	      sysclk      => clkrst_i.clk(0),    -- fudge for now
+	      reset       => clkrst_i.rst(0),
+
+	      sndif_rd    => to_sound.rd,              
+	      sndif_wr    => to_sound.wr,              
+	      sndif_addr  => snd_a,
+	      sndif_datai => to_sound.d,
+
+	      snd_clk     => audio_o.clk,
+	      snd_data_l  => snd_data_l,
+	      snd_data_r  => snd_data_r,
+	      sndif_datao => from_sound.d
+	    );
+
+		-- route audio to both channels
+		audio_o.ldata <= snd_data_l & "00000000";
+		audio_o.rdata <= snd_data_r & "00000000";
+	
+	end block SOUND_BLOCK;
+		
+end SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg.vhd
new file mode 100644
index 00000000..0a6944d6
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg.vhd	
@@ -0,0 +1,147 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+package pace_pkg is
+
+	--  
+	-- PACE constants which *MUST* be defined
+	--
+
+  type PACETargetType is
+  (
+    PACE_TARGET_NANOBOARD_NB1,
+    PACE_TARGET_DE0,
+    PACE_TARGET_DE0_CV,		-- 5CEBA4
+    PACE_TARGET_DE0_NANO,	-- EP4CE22
+    PACE_TARGET_DE1,
+    PACE_TARGET_DE2,
+    PACE_TARGET_DE2_70,		-- EP2C70
+    PACE_TARGET_DE2_115,	-- EP4CE115
+    PACE_TARGET_P2,		-- A02 build
+    PACE_TARGET_P2A,		-- A04/A build (SRAM byte selects)
+    PACE_TARGET_P3M,
+    PACE_TARGET_S3A_700,	-- Spartan 3A/N Starter Kit
+    PACE_TARGET_RC10,
+    PACE_TARGET_NX2_12,
+    PACE_TARGET_NEXYS_3,	-- Digilent S6 board
+    PACE_TARGET_CYC3DEV,
+    PACE_TARGET_CYC5GXDEV,
+    PACE_TARGET_COCO3PLUS,
+    PACE_TARGET_S5A,
+    PACE_TARGET_CARTEBLANCHE_250,
+    PACE_TARGET_CARTEBLANCHE_500,
+    PACE_TARGET_BEMICRO,
+    PACE_TARGET_OPENEP3C16,
+    PACE_TARGET_MIST,
+    PACE_TARGET_CHAMELEON64,
+    PACE_TARGET_RETRORAMBLINGS_CYC3,  -- Generic EP3C25 board with custom io boards
+    PACE_TARGET_S5A_R2_EP4C,
+    PACE_TARGET_S5A_R2_EP3SL,
+    PACE_TARGET_S5A_R2B0_EP4C,
+    PACE_TARGET_S5A_R2B0_EP3SL,
+    PACE_TARGET_S5A_R2C0_EP4C,
+    PACE_TARGET_S5A_R2C0_EP3SL,
+    PACE_TARGET_S5L_A0_EP4C,
+    PACE_TARGET_S5L_A0_EP3SL,
+    PACE_TARGET_NAVICO_ROCKY,
+    PACE_TARGET_NGPACE,
+    PACE_TARGET_S6M_A0
+  );
+
+	type PACEFpgaVendor_t is
+	(
+		PACE_FPGA_VENDOR_ALTERA,
+		PACE_FPGA_VENDOR_XILINX,
+		PACE_FPGA_VENDOR_LATTICE
+	);
+
+	type PACEFpgaFamily_t is
+	(
+		PACE_FPGA_FAMILY_CYCLONE1,
+		PACE_FPGA_FAMILY_CYCLONE2,
+		PACE_FPGA_FAMILY_CYCLONE3,
+		PACE_FPGA_FAMILY_CYCLONE4,
+		PACE_FPGA_FAMILY_CYCLONE5,
+		PACE_FPGA_FAMILY_CYCLONE6,
+		PACE_FPGA_FAMILY_STRATIX_III,
+		PACE_FPGA_FAMILY_SPARTAN3,
+		PACE_FPGA_FAMILY_SPARTAN3A,
+		PACE_FPGA_FAMILY_SPARTAN3E
+	);
+
+  type PACEJamma_t is
+  (
+    PACE_JAMMA_NONE,
+    PACE_JAMMA_MAPLE,
+    PACE_JAMMA_NGC,
+    PACE_JAMMA_PS2
+  );
+
+  -- Types
+
+	type ByteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
+
+  type from_CLKRST_t is record
+    arst      : std_logic;
+    arst_n    : std_logic;
+    rst       : std_logic_vector(0 to 3);
+    clk_ref   : std_logic;                  --reference clock
+    clk       : std_logic_vector(0 to 3);
+  end record;
+  
+
+
+  
+  type from_AUDIO_t is record
+    clk       : std_logic;
+  end record;
+  
+  type to_AUDIO_t is record
+    clk       : std_logic;
+    ldata     : std_logic_vector(15 downto 0);
+    rdata     : std_logic_vector(15 downto 0);
+  end record;
+  
+  function NULL_TO_AUDIO return to_AUDIO_t;
+
+  type from_SPI_t is record
+    din       : std_logic;
+  end record;
+  
+  type to_SPI_t is record
+    clk       : std_logic;
+    mode      : std_logic;
+    sel       : std_logic;
+    ena       : std_logic;
+    dout      : std_logic;
+  end record;
+  
+  subtype SND_A_t is std_logic_vector(7 downto 0);
+  subtype SND_D_t is std_logic_vector(7 downto 0);
+  
+  type to_SOUND_t is record
+    a         : SND_A_t;
+    d         : SND_D_t;
+    rd        : std_logic;
+    wr        : std_logic;
+  end record;
+  
+  type from_SOUND_t is record
+    d         : SND_D_t;
+  end record;
+
+  function NULL_TO_SOUND return to_SOUND_t;
+
+	-- create a constant that automatically determines 
+	-- whether this is simulation or synthesis
+	constant IN_SIMULATION : BOOLEAN := false
+	-- synthesis translate_off
+	or true
+	-- synthesis translate_on
+	;
+	constant IN_SYNTHESIS : boolean := not IN_SIMULATION;
+	
+end;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg_body.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg_body.vhd
new file mode 100644
index 00000000..552d7946
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pace_pkg_body.vhd	
@@ -0,0 +1,17 @@
+library work;
+
+package body pace_pkg is
+
+
+  function NULL_TO_AUDIO return to_AUDIO_t is
+  begin
+    return ('0', (others => '0'), (others => '0'));
+  end NULL_TO_AUDIO;
+
+  function NULL_TO_SOUND return to_SOUND_t is
+  begin
+    return ((others => '0'), (others => '0'), '0', '0');
+  end NULL_TO_SOUND;
+
+
+end package body pace_pkg;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd
new file mode 100644
index 00000000..bef11d3c
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform.vhd	
@@ -0,0 +1,567 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+
+entity platform is
+  port
+  (
+    -- clocking and reset
+    clkrst_i        	: in from_CLKRST_t;
+	 vma					: out std_logic;
+    -- controller inputs
+    inputs_p1			: in std_logic_vector(7 downto 0);
+    inputs_p2			: in std_logic_vector(7 downto 0);
+    inputs_sys			: in std_logic_vector(7 downto 0);
+    inputs_dip1		: in std_logic_vector(7 downto 0);
+    inputs_dip2		: in std_logic_vector(7 downto 0);
+    
+    bitmap_i        : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    bitmap_o        : out to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+    
+    tilemap_i       : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+    tilemap_o       : out to_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+
+    sprite_reg_o    : out to_SPRITE_REG_t;
+    sprite_i        : in from_SPRITE_CTL_t;
+    sprite_o        : out to_SPRITE_CTL_t;
+	 spr0_hit				: in std_logic;
+
+    -- various graphics information
+    graphics_i      : in from_GRAPHICS_t;
+    graphics_o      : out to_GRAPHICS_t;
+	 
+	 snd_i      : in from_SOUND_t;
+    snd_o      : out to_SOUND_t;
+    platform_i      : in from_PLATFORM_IO_t;
+    platform_o      : out to_PLATFORM_IO_t;
+	 
+	 cpu_rom_addr		: out std_logic_vector(15 downto 0);
+	 cpu_rom_do			: in std_logic_vector(7 downto 0);
+	 tile_rom_addr		: out std_logic_vector(12 downto 0);
+	 tile_rom_do		: in std_logic_vector(15 downto 0)
+  );
+
+end platform;
+
+architecture SYN of platform is
+
+	alias clk_20M					    : std_logic is clkrst_i.clk(0);
+  alias rst_20M             : std_logic is clkrst_i.rst(0);
+	alias clk_video				    : std_logic is clkrst_i.clk(1);
+	signal cpu_reset			    : std_logic;
+  
+  -- uP signals  
+  signal clk_2M_en			    : std_logic;
+	signal cpu_clk_en         : std_logic;
+	signal cpu_r_wn				    : std_logic;
+	signal cpu_a				      : std_logic_vector(15 downto 0);
+	signal cpu_d_i			      : std_logic_vector(7 downto 0);
+	signal cpu_d_o			      : std_logic_vector(7 downto 0);
+	signal cpu_irq				    : std_logic;
+
+  -- ROM signals        
+	signal rom_cs				      : std_logic;
+	
+  -- RAM signals        
+	signal wram_cs				    : std_logic;
+  signal wram_wr            : std_logic;
+  signal wram_d_o      	    : std_logic_vector(7 downto 0);
+  signal vram_cs				    : std_logic;
+  signal vram_d_o           : std_logic_vector(7 downto 0);
+  signal vram_wr            : std_logic;
+  signal cram_cs				    : std_logic;
+  signal cram_d_o           : std_logic_vector(7 downto 0);
+  signal cram_wr            : std_logic;
+  signal sprite_cs          : std_logic;
+  
+  -- I/O signals
+  signal scroll_cs          : std_logic;
+  signal in0_cs             : std_logic;
+  signal in1_cs             : std_logic;
+  signal in2_cs             : std_logic;
+  signal dsw1_cs            : std_logic;
+  signal dsw2_cs            : std_logic;
+  
+  signal rom4_d_o   : std_logic_vector(7 downto 0);
+  signal rom8_d_o   : std_logic_vector(7 downto 0);
+  signal romC_d_o   : std_logic_vector(7 downto 0);
+  signal rom_d_o    : std_logic_vector(7 downto 0);
+  
+  signal cpu_rn_w            : std_logic;
+  
+  COMPONENT mc6809i
+	GENERIC ( ILLEGAL_INSTRUCTIONS : STRING := "GHOST" );
+	PORT
+	(
+		D		:	 IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		DOut		:	 OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		ADDR		:	 OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		RnW		:	 OUT STD_LOGIC;
+		E		:	 IN STD_LOGIC;
+		Q		:	 IN STD_LOGIC;
+		BS		:	 OUT STD_LOGIC;
+		BA		:	 OUT STD_LOGIC;
+		nIRQ		:	 IN STD_LOGIC;
+		nFIRQ		:	 IN STD_LOGIC;
+		nNMI		:	 IN STD_LOGIC;
+		AVMA		:	 OUT STD_LOGIC;
+		BUSY		:	 OUT STD_LOGIC;
+		LIC		:	 OUT STD_LOGIC;
+		nHALT		:	 IN STD_LOGIC;
+		nRESET		:	 IN STD_LOGIC;
+		nDMABREQ		:	 IN STD_LOGIC;
+		RegData		:	 OUT STD_LOGIC_VECTOR(111 DOWNTO 0)
+	);
+END COMPONENT;
+
+begin
+	
+	wram_cs 		<=	'1' when STD_MATCH(cpu_a,  "0000------------") else '0';-- RAM $0000-$0FFF
+	vram_cs 		<=	'1' when STD_MATCH(cpu_a,  "000100----------") else '0';-- video ram $1000-$13FF 
+   cram_cs 		<=	'1' when STD_MATCH(cpu_a,  "000101----------") else '0';-- colour ram $1400-$17FF
+	sprite_cs 	<=	'1' when STD_MATCH(cpu_a,    X"20"&"001-----") else
+						'1' when STD_MATCH(cpu_a,    X"20"&"01------") else
+						'0';-- sprite 'ram' $2020-$207F
+  -- I/O
+	scroll_cs 	<= '1' when STD_MATCH(cpu_a, X"3000") else '0';
+	in0_cs 		<= '1' when STD_MATCH(cpu_a, X"3002") else '0';
+	in1_cs 		<= '1' when STD_MATCH(cpu_a, X"3003") else '0';
+	in2_cs 		<= '1' when STD_MATCH(cpu_a, X"3004") else '0';
+	dsw1_cs 		<= '1' when STD_MATCH(cpu_a, X"3005") else '0';
+	dsw2_cs 		<= '1' when STD_MATCH(cpu_a, X"3006") else '0';
+	rom_cs  		<= '1' when (cpu_a > X"3FFF") else '0';
+
+  -- memory block write enables
+  wram_wr <= wram_cs and clk_2M_en and not cpu_r_wn;
+  vram_wr <= vram_cs and clk_2M_en and not cpu_r_wn;
+  cram_wr <= cram_cs and clk_2M_en and not cpu_r_wn;
+
+	-- memory read mux
+	cpu_d_i <=  wram_d_o when wram_cs = '1' else
+					vram_d_o when vram_cs = '1' else
+					cram_d_o when cram_cs = '1' else
+					inputs_p1 when in0_cs = '1' else
+					inputs_p2 when in1_cs = '1' else
+					inputs_sys when in2_cs = '1' else
+					inputs_dip1 when dsw1_cs = '1' else
+					inputs_dip2 when dsw2_cs = '1' else
+					-- flip off, service off, coin A, 1C1C
+--              (X"80" or X"40" or X"10" or X"0F") when dsw1_cs = '1' else
+              -- freeze off, easy, 20K/80K/100K, 3 lives
+--              (X"80" or X"60" or X"08" or X"03") when dsw2_cs = '1' else
+				  rom_d_o when rom_cs = '1' else
+--				  cpu_rom_do when rom_cs = '1' else
+							(others => 'Z');
+	
+	
+  -- system timing
+  process (clk_20M, rst_20M)
+    variable count : integer range 0 to 10-1;
+  begin
+    if rst_20M = '1' then
+      count := 0;
+    elsif rising_edge(clk_20M) then
+      clk_2M_en <= '0'; -- default
+      case count is
+        when 0 =>
+          clk_2M_en <= '1';
+        when others =>
+          null;
+      end case;
+      if count = count'high then
+        count := 0;
+      else
+        count := count + 1;
+      end if;
+    end if;
+  end process;
+
+	-- cpu09 core uses negative clock edge
+	--cpu_clk_en <= not (clk_2M_en and not platform_pause);
+	cpu_clk_en <= clk_2M_en;
+
+	-- add game reset later
+	cpu_reset <= rst_20M;
+	
+--	cpu_inst : entity work.cpu09
+ --   generic map
+ --   (
+ --     CLK_POL   => '1'
+ --   )
+--		port map
+--		(	
+--			clk				=> clk_20M,
+ --     clk_en    => cpu_clk_en,
+--			rst				=> cpu_reset,
+--			rw				=> cpu_r_wn,
+	--		vma				=> vma,
+      --ba        => open,
+      --bs        => open,
+	--		addr		  => cpu_a,
+--		  data_in		=> cpu_d_i,
+--		  data_out	=> cpu_d_o,
+--			halt			=> '0',
+--			hold			=> '0',
+--			irq				=> cpu_irq,
+--			firq			=> '0',
+---			nmi				=> '0'
+--		);
+		
+--changed for test		
+	cpu_inst : mc6809i
+	port map
+    (
+    D				=> cpu_d_i,
+    DOut			=> cpu_d_o,
+    ADDR	  		=> cpu_a,
+    RnW			=> cpu_r_wn,
+    E   			=> cpu_clk_en,
+    Q				=> clk_20M,
+    BS     		=> open,
+    BA     		=> open,
+    nIRQ			=> not cpu_irq,
+    nFIRQ		=> '1',
+    nNMI			=> '1',
+    AVMA  		=> open,
+    BUSY  		=> open,
+	 LIC  		=> open,
+    nHALT		=> '1',	 
+    nRESET		=> not cpu_reset,
+    nDMABREQ  	=> '1',
+    RegData		=> open
+    );
+
+		
+		
+--WRAm_cs
+	wram_inst : entity work.spram
+    generic map
+	(
+		widthad_a	=> 12,
+		width_a		=> 8
+	)
+		port map
+	(
+		address		=> cpu_a(11 downto 0),
+		clock			=> clk_20M,
+		data			=> cpu_d_o,
+		wren			=> wram_wr,
+		q				=> wram_d_o
+	);	
+
+	-- irq vblank interrupt
+	process (clk_20M, rst_20M)
+    variable vblank_r : std_logic_vector(3 downto 0);
+    alias vblank_prev : std_logic is vblank_r(vblank_r'left);
+    alias vblank_um   : std_logic is vblank_r(vblank_r'left-1);
+	begin
+		if rst_20M = '1' then
+			vblank_r := (others => '0');
+      cpu_irq <= '0';
+		elsif rising_edge(clk_20M) then
+			if vblank_um = '1' and vblank_prev = '0' then
+				cpu_irq <= '1';
+      elsif vblank_um = '0' then
+        cpu_irq <= '0';
+			end if;
+      -- numeta the vblank
+      vblank_r := vblank_r(vblank_r'left-1 downto 0) & graphics_i.vblank;
+		end if;
+	end process;
+
+  -- scroll register
+  process (clk_20M, rst_20M)
+  begin
+    if rst_20M = '1' then
+      graphics_o.bit8(0) <= (others => '0');
+    elsif rising_edge(clk_20M) then
+      if scroll_cs and clk_2M_en and not cpu_r_wn then
+        graphics_o.bit8(0) <= cpu_d_o;
+      end if;
+    end if;
+  end process;
+
+  
+    rom_4000_inst : entity work.sprom
+     generic map
+      (
+        init_file		=> "./roms/ss_01e.hex",
+       widthad_a		=> 14
+     )
+      port map
+      (
+        clock			=> clk_20M,
+        address		=> cpu_a(13 downto 0),
+        q					=> rom4_d_o
+      );
+    
+   rom_8000_inst : entity work.sprom
+      generic map
+      (
+        init_file		=> "./roms/ss_02e.hex",
+        widthad_a		=> 14
+      )
+      port map
+      (
+        clock			=> clk_20M,
+        address		=> cpu_a(13 downto 0),
+        q					=> rom8_d_o
+      );
+      
+    rom_C000_inst : entity work.sprom
+      generic map
+      (
+        init_file		=> "./roms/ss_03e.hex",
+        widthad_a		=> 14
+      )
+      port map
+      (
+       clock			=> clk_20M,
+        address		=> cpu_a(13 downto 0),
+       q					=> romC_d_o
+      );
+		
+    rom_d_o <=  rom4_d_o when STD_MATCH(cpu_a, "01--------------") else
+                rom8_d_o when STD_MATCH(cpu_a, "10--------------") else
+                romC_d_o;
+                  
+--cpu_rom_addr <= cpu_a(15 downto 0);
+--rom_d_o <= cpu_rom_do;
+
+  -- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE
+  vram_inst : entity work.dpram
+    generic map
+    (
+      init_file		=> "./roms/vram.hex",
+      widthad_a		=> 10
+    )
+    port map
+    (
+      clock_b			=> clk_20M,
+      address_b		=> cpu_a(9 downto 0),
+      wren_b			=> vram_wr,
+      data_b			=> cpu_d_o,
+      q_b					=> vram_d_o,
+
+      clock_a			=> clk_video,
+      address_a		=> tilemap_i(1).map_a(9 downto 0),
+      wren_a			=> '0',
+      data_a			=> (others => 'X'),
+      q_a					=> tilemap_o(1).map_d(7 downto 0)
+    );
+  tilemap_o(1).map_d(tilemap_o(1).map_d'left downto 8) <= (others => 'Z');
+  
+  -- wren_a *MUST* be GND for CYCLONEII_SAFE_WRITE=VERIFIED_SAFE
+  cram_inst : entity work.dpram
+    generic map
+    (
+      init_file		=> "./roms/cram.hex",
+      widthad_a		=> 10
+    )
+    port map
+    (
+      clock_b			=> clk_20M,
+      address_b		=> cpu_a(9 downto 0),
+      wren_b			=> cram_wr,
+      data_b			=> cpu_d_o,
+      q_b					=> cram_d_o,
+
+      clock_a			=> clk_video,
+      address_a		=> tilemap_i(1).attr_a(9 downto 0),
+      wren_a			=> '0',
+      data_a			=> (others => 'X'),
+      q_a					=> tilemap_o(1).attr_d(7 downto 0)
+    );
+  tilemap_o(1).attr_d(tilemap_o(1).attr_d'left downto 8) <= (others => 'Z');
+
+   --tile rom (bit 0)
+  ss_7_b6_inst : entity work.sprom
+    generic map
+    (
+     init_file		=> "./roms/ss_7_b6.hex",
+      widthad_a		=> 13
+    )
+    port map
+    (
+      clock			=> clk_video,
+      address		=> tilemap_i(1).tile_a(12 downto 0),
+      q					=> tilemap_o(1).tile_d(7 downto 0)
+   );
+		
+  -- tile rom (bit 1)---will not fit in FPGA Block Ram
+ -- ss_8_b5_inst : entity work.sprom
+  --  generic map
+  --  (
+  --   init_file		=> "./roms/ss_8_b5.hex",
+  --    widthad_a		=> 13
+  --  )
+  --  port map
+  --  (
+  --    clock			=> clk_video,
+  --    address		=> tilemap_i(1).tile_a(12 downto 0),
+   --  q					=> tilemap_o(1).tile_d(15 downto 8)
+   -- );
+
+--tile_rom_addr <= tilemap_i(1).tile_a(12 downto 0);
+--tilemap_o(1).tile_d(15 downto 0) <= tile_rom_do(15 downto 0);
+
+  BLK_SPRITES : block---will not fit in FPGA Block Ram
+    signal bit0_1       : std_logic_vector(7 downto 0);   -- offset 0
+    signal bit0_2       : std_logic_vector(7 downto 0);   -- offset 0
+    signal bit0_3       : std_logic_vector(7 downto 0);   -- offset 16
+    signal bit0_4       : std_logic_vector(7 downto 0);   -- offset 16
+    signal bit1_1       : std_logic_vector(7 downto 0);
+    signal bit1_2       : std_logic_vector(7 downto 0);
+    signal bit1_3       : std_logic_vector(7 downto 0);
+    signal bit1_4       : std_logic_vector(7 downto 0);
+    signal bit2_1       : std_logic_vector(7 downto 0);
+    signal bit2_2       : std_logic_vector(7 downto 0);
+    signal bit2_3       : std_logic_vector(7 downto 0);
+    signal bit2_4       : std_logic_vector(7 downto 0);
+    
+    signal sprite_a_00  : std_logic_vector(12 downto 0);
+    signal sprite_a_16  : std_logic_vector(12 downto 0);
+    
+  begin
+
+    -- registers
+    sprite_reg_o.clk <= clk_20M;
+    sprite_reg_o.clk_ena <= clk_2M_en;
+    sprite_reg_o.a <= cpu_a(sprite_reg_o.a'range);
+    sprite_reg_o.d <= cpu_d_o;
+    sprite_reg_o.wr <= sprite_cs and clk_2M_en and not cpu_r_wn;
+
+    -- - sprite data consists of:
+    --   16 consecutive bytes for the 1st half
+    --   then the next 16 bytes for the 2nd half
+    -- - because we need to fetch an entire row at once
+    --   use dual-port memory to access both halves of each row
+
+    -- generate address for each port
+   -- sprite_a_00 <= sprite_i.a(12 downto 5) & '0' & sprite_i.a(3 downto 0);
+  --  sprite_a_16 <= sprite_i.a(12 downto 5) & '1' & sprite_i.a(3 downto 0);
+    
+    -- sprite rom (bit 0, part 1/2)
+   -- ss_9_m5_inst : entity work.dprom_2r
+  --    generic map
+  --    (
+  --      init_file		=> "./roms/ss_9_m5.hex",
+  --      widthad_a		=> 13,
+  --      widthad_b		=> 13
+ --     )
+  --    port map
+  --    (
+  --      clock			  => clk_video,
+  --      address_a   => sprite_a_00,
+  --      q_a 			  => bit0_1,
+  --      address_b   => sprite_a_16,
+  --      q_b         => bit0_3
+ --     );
+      
+    -- sprite rom (bit 0, part 2/2)
+  --  ss_10_m6_inst : entity work.dprom_2r
+  --    generic map
+  --    (
+  --      init_file		=> "./roms/ss_10_m6.hex",
+  --      widthad_a		=> 13,
+  --      widthad_b		=> 13
+  --    )
+ --     port map
+ --     (
+ --       clock			  => clk_video,
+ --       address_a   => sprite_a_00,
+ ---       q_a 			  => bit0_2,
+ --       address_b   => sprite_a_16,
+ --       q_b         => bit0_4
+ --     );
+      
+--    sprite_o.d(15 downto 0) <=  (bit0_1 & bit0_3) when sprite_i.a(13) = '0' else
+--                                (bit0_2 & bit0_4);
+                              
+    -- sprite rom (bit 1, part 1/2)
+ --   ss_11_m3_inst : entity work.dprom_2r
+ --     generic map
+ --     (
+ --       init_file		=> "./roms/ss_11_m3.hex",
+ --       widthad_a		=> 13,
+ --       widthad_b		=> 13
+ --     )
+ --     port map
+ --     (
+ --      clock			  => clk_video,
+ --      address_a   => sprite_a_00,
+ --      q_a 			  => bit1_1,
+ --      address_b   => sprite_a_16,
+ --      q_b         => bit1_3
+--      );
+      
+    -- sprite rom (bit 0, part 2/2)
+ --   ss_12_m4_inst : entity work.dprom_2r
+ --     generic map
+ --     (
+ --       init_file		=> "./roms/ss_12_m4.hex",
+ --       widthad_a		=> 13,
+ --       widthad_b		=> 13
+ --     )
+ --     port map
+ --     (
+ --       clock			  => clk_video,
+--        address_a   => sprite_a_00,
+ --       q_a 			  => bit1_2,
+ --       address_b   => sprite_a_16,
+---        q_b         => bit1_4
+ ---     );
+      
+ --   sprite_o.d(31 downto 16) <= (bit1_1 & bit1_3) when sprite_i.a(13) = '0' else
+--                                (bit1_2 & bit1_4);
+                              
+    -- sprite rom (bit 2, part 1/2)
+  --  ss_13_m1_inst : entity work.dprom_2r
+ --     generic map
+ --     (
+ --       init_file		=> "./roms/ss_13_m1.hex",
+ --       widthad_a		=> 13,
+ --       widthad_b		=> 13
+ --     )
+ --     port map
+ --     (
+ --       clock			  => clk_video,
+ --       address_a   => sprite_a_00,
+ --       q_a 			  => bit2_1,
+ --       address_b   => sprite_a_16,
+ --       q_b         => bit2_3
+ --     );
+      
+    -- sprite rom (bit 2, part 2/2)
+--    ss_14_m2_inst : entity work.dprom_2r
+--      generic map
+--      (
+--        init_file		=> "./roms/ss_14_m2.hex",
+ --       widthad_a		=> 13,
+--        widthad_b		=> 13
+ --     )
+ --     port map
+ --     (
+ --       clock			  => clk_video,
+ --       address_a   => sprite_a_00,
+ --       q_a 			  => bit2_2,
+ --       address_b   => sprite_a_16,
+ --       q_b         => bit2_4
+ --     );
+     
+ --   sprite_o.d(47 downto 32) <= (bit2_1 & bit2_3) when sprite_i.a(13) = '0' else
+ --                               (bit2_2 & bit2_4);
+
+  end block BLK_SPRITES;
+  
+  -- unused outputs
+
+  graphics_o.bit16(0) <= (others => '0');
+
+end SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform_pkg.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform_pkg.vhd
new file mode 100644
index 00000000..83d03cdc
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/platform_pkg.vhd	
@@ -0,0 +1,212 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+
+package platform_pkg is
+
+	constant PACE_HAS_PLL								      : boolean := true; 
+
+  constant PACE_VIDEO_CONTROLLER_TYPE       	: PACEVideoController_t := PACE_VIDEO_VGA_800x600_60Hz; --40
+  constant PACE_CLK0_DIVIDE_BY              	: natural := 27;
+  constant PACE_CLK0_MULTIPLY_BY            	: natural := 20;  -- 20MHz
+  constant PACE_CLK1_DIVIDE_BY        		  	: natural := 27;
+  constant PACE_CLK1_MULTIPLY_BY      		  	: natural := 40;  -- 40MHz
+	constant PACE_VIDEO_H_SCALE         	  	: integer := 2;
+	constant PACE_VIDEO_V_SCALE         		: integer := 2;
+  constant PACE_VIDEO_H_SYNC_POLARITY       	: std_logic := '1';
+  constant PACE_VIDEO_V_SYNC_POLARITY       	: std_logic := '1';
+
+  
+  constant PACE_VIDEO_BORDER_RGB            	: RGB_t := RGB_BLACK;
+
+	constant PACE_VIDEO_NUM_BITMAPS 	    		: natural := 0;
+	constant PACE_VIDEO_NUM_TILEMAPS 	    	: natural := 1;
+	constant PACE_VIDEO_NUM_SPRITES 	    		: natural := 24;
+	constant PACE_VIDEO_H_SIZE				    	: integer := 256;   -- 240
+	constant PACE_VIDEO_V_SIZE				    	: integer := 256;   -- 240
+  constant PACE_VIDEO_L_CROP            		: integer := (256-240)/2;
+  constant PACE_VIDEO_R_CROP            		: integer := PACE_VIDEO_L_CROP;
+	constant PACE_VIDEO_PIPELINE_DELAY    		: integer := 3;
+	
+	constant PACE_INPUTS_NUM_BYTES        		: integer := 4;
+		
+	--
+	-- Platform-specific constants (optional)
+	--
+
+	constant CLK0_FREQ_MHz			          : natural := 
+    27 * PACE_CLK0_MULTIPLY_BY / PACE_CLK0_DIVIDE_BY;
+
+	constant WILLIAMS_CPU_CLK_ENA_DIVIDE_BY	  : natural := 
+          CLK0_FREQ_MHz / 3;
+
+	type palette_entry_t is array (0 to 2) of std_logic_vector(5 downto 0);
+	type palette_entry_a is array (0 to 255) of palette_entry_t;
+
+	constant pal : palette_entry_a :=
+	(
+    1 => (0=>"100111", 1=>"100111", 2=>"100111"),
+    2 => (0=>"000000", 1=>"100011", 2=>"000000"),
+    3 => (0=>"011100", 1=>"001011", 2=>"000111"),
+    4 => (0=>"100111", 1=>"001011", 2=>"000111"),
+    5 => (0=>"101111", 1=>"011000", 2=>"000000"),
+    6 => (0=>"101111", 1=>"101111", 2=>"101111"),
+    7 => (0=>"011100", 1=>"011100", 2=>"011100"),
+    8 => (0=>"000000", 1=>"010000", 2=>"011000"),
+    9 => (0=>"010000", 1=>"011000", 2=>"100111"),
+    10 => (0=>"011000", 1=>"010000", 2=>"011000"),
+    11 => (0=>"100011", 1=>"011000", 2=>"100011"),
+    12 => (0=>"101011", 1=>"101011", 2=>"000000"),
+    13 => (0=>"101011", 1=>"100111", 2=>"101011"),
+    14 => (0=>"011100", 1=>"011100", 2=>"110100"),
+    15 => (0=>"110100", 1=>"000000", 2=>"000000"),
+    17 => (0=>"110100", 1=>"110100", 2=>"110100"),
+    18 => (0=>"100111", 1=>"100111", 2=>"100111"),
+    19 => (0=>"110100", 1=>"100111", 2=>"011100"),
+    20 => (0=>"101011", 1=>"000000", 2=>"000000"),
+    21 => (0=>"011100", 1=>"000000", 2=>"000000"),
+    22 => (0=>"101011", 1=>"011100", 2=>"000000"),
+    23 => (0=>"111000", 1=>"101111", 2=>"000000"),
+    24 => (0=>"111100", 1=>"000000", 2=>"000000"),
+    25 => (0=>"100011", 1=>"000000", 2=>"100111"),
+    26 => (0=>"011000", 1=>"000000", 2=>"101011"),
+    27 => (0=>"011100", 1=>"011100", 2=>"111000"),
+    28 => (0=>"111100", 1=>"011100", 2=>"000000"),
+    29 => (0=>"000000", 1=>"100011", 2=>"000000"),
+    30 => (0=>"000000", 1=>"101011", 2=>"000000"),
+    31 => (0=>"000011", 1=>"000011", 2=>"000011"),
+		others => (others => (others => '0'))
+	);
+
+	-- Colour Look-up Table (CLUT) : Table of palette entries
+	-- - each row has four (4) palette indexes
+	--   decoded from 2 bits of tile data
+	
+	type tile_clut_entry_t is array (0 to 3) of std_logic_vector(3 downto 0);
+	type tile_clut_entry_a is array (0 to 63) of tile_clut_entry_t;
+
+	constant tile_clut : tile_clut_entry_a :=
+	(
+     0 => (0=>X"0", 1=>X"B", 2=>X"0", 3=>X"0"),
+     1 => (0=>X"0", 1=>X"C", 2=>X"0", 3=>X"0"),
+     2 => (0=>X"0", 1=>X"D", 2=>X"0", 3=>X"0"),
+     3 => (0=>X"0", 1=>X"E", 2=>X"0", 3=>X"0"),
+     4 => (0=>X"0", 1=>X"F", 2=>X"0", 3=>X"0"),
+     6 => (0=>X"0", 1=>X"1", 2=>X"0", 3=>X"0"),
+     7 => (0=>X"0", 1=>X"2", 2=>X"0", 3=>X"0"),
+     8 => (0=>X"0", 1=>X"3", 2=>X"0", 3=>X"0"),
+     9 => (0=>X"0", 1=>X"4", 2=>X"0", 3=>X"0"),
+    10 => (0=>X"0", 1=>X"5", 2=>X"0", 3=>X"0"),
+    11 => (0=>X"0", 1=>X"6", 2=>X"0", 3=>X"0"),
+    12 => (0=>X"0", 1=>X"7", 2=>X"0", 3=>X"0"),
+    13 => (0=>X"0", 1=>X"8", 2=>X"0", 3=>X"0"),
+    14 => (0=>X"0", 1=>X"9", 2=>X"0", 3=>X"0"),
+    15 => (0=>X"0", 1=>X"A", 2=>X"0", 3=>X"0"),
+    16 => (0=>X"0", 1=>X"8", 2=>X"9", 3=>X"E"),
+    17 => (0=>X"0", 1=>X"A", 2=>X"B", 3=>X"D"),
+    18 => (0=>X"0", 1=>X"3", 2=>X"4", 3=>X"5"),
+    19 => (0=>X"0", 1=>X"7", 2=>X"1", 3=>X"6"),
+    20 => (0=>X"0", 1=>X"3", 2=>X"4", 3=>X"2"),
+    21 => (0=>X"0", 1=>X"7", 2=>X"0", 3=>X"6"),
+    22 => (0=>X"0", 1=>X"2", 2=>X"3", 3=>X"4"),
+    23 => (0=>X"0", 1=>X"2", 2=>X"A", 3=>X"B"),
+    24 => (0=>X"0", 1=>X"9", 2=>X"6", 3=>X"E"),
+    25 => (0=>X"0", 1=>X"1", 2=>X"6", 3=>X"7"),
+    26 => (0=>X"0", 1=>X"7", 2=>X"1", 3=>X"6"),
+    27 => (0=>X"0", 1=>X"2", 2=>X"C", 3=>X"6"),
+    28 => (0=>X"0", 1=>X"C", 2=>X"F", 3=>X"2"),
+    29 => (0=>X"0", 1=>X"2", 2=>X"B", 3=>X"6"),
+    30 => (0=>X"0", 1=>X"2", 2=>X"F", 3=>X"6"),
+    31 => (0=>X"0", 1=>X"2", 2=>X"B", 3=>X"D"),
+    32 => (0=>X"0", 1=>X"2", 2=>X"1", 3=>X"6"),
+    33 => (0=>X"0", 1=>X"2", 2=>X"9", 3=>X"E"),
+    34 => (0=>X"0", 1=>X"2", 2=>X"4", 3=>X"F"),
+    35 => (0=>X"0", 1=>X"2", 2=>X"9", 3=>X"6"),
+    36 => (0=>X"0", 1=>X"2", 2=>X"F", 3=>X"6"),
+    37 => (0=>X"0", 1=>X"C", 2=>X"3", 3=>X"5"),
+    38 => (0=>X"0", 1=>X"1", 2=>X"3", 3=>X"5"),
+    39 => (0=>X"0", 1=>X"4", 2=>X"5", 3=>X"6"),
+    40 => (0=>X"0", 1=>X"7", 2=>X"1", 3=>X"5"),
+    41 => (0=>X"0", 1=>X"9", 2=>X"E", 3=>X"C"),
+    42 => (0=>X"0", 1=>X"4", 2=>X"F", 3=>X"3"),
+    43 => (0=>X"0", 1=>X"4", 2=>X"F", 3=>X"6"),
+    44 => (0=>X"0", 1=>X"1", 2=>X"5", 3=>X"6"),
+    45 => (0=>X"0", 1=>X"4", 2=>X"5", 3=>X"2"),
+    46 => (0=>X"0", 1=>X"4", 2=>X"5", 3=>X"C"),
+    47 => (0=>X"0", 1=>X"E", 2=>X"9", 3=>X"6"),
+    48 => (0=>X"0", 1=>X"4", 2=>X"F", 3=>X"2"),
+    49 => (0=>X"0", 1=>X"4", 2=>X"F", 3=>X"6"),
+    50 => (0=>X"0", 1=>X"B", 2=>X"D", 3=>X"6"),
+    51 => (0=>X"C", 1=>X"D", 2=>X"E", 3=>X"0"),
+    52 => (0=>X"1", 1=>X"2", 2=>X"3", 3=>X"4"),
+    53 => (0=>X"5", 1=>X"6", 2=>X"7", 3=>X"8"),
+    54 => (0=>X"9", 1=>X"A", 2=>X"B", 3=>X"C"),
+    55 => (0=>X"D", 1=>X"E", 2=>X"0", 3=>X"F"),
+    56 => (0=>X"2", 1=>X"3", 2=>X"4", 3=>X"5"),
+    57 => (0=>X"6", 1=>X"7", 2=>X"8", 3=>X"9"),
+    58 => (0=>X"A", 1=>X"B", 2=>X"C", 3=>X"D"),
+    59 => (0=>X"E", 1=>X"0", 2=>X"F", 3=>X"1"),
+    60 => (0=>X"3", 1=>X"4", 2=>X"5", 3=>X"6"),
+    61 => (0=>X"7", 1=>X"8", 2=>X"9", 3=>X"A"),
+    62 => (0=>X"B", 1=>X"C", 2=>X"D", 3=>X"E"),
+    63 => (0=>X"0", 1=>X"F", 2=>X"1", 3=>X"2"),
+    others => (others => X"0")
+  );
+
+	-- Colour Look-up Table (CLUT) : Table of palette entries
+	-- - each row has four (8) palette indexes
+	--   decoded from 8 bits of sprite data
+	
+	type sprite_clut_entry_t is array (0 to 7) of std_logic_vector(3 downto 0);
+	type sprite_clut_entry_a is array (0 to 31) of sprite_clut_entry_t;
+
+	constant sprite_clut : sprite_clut_entry_a :=
+	(
+     0 => (0=>X"F", 1=>X"1", 2=>X"3", 3=>X"4", 4=>X"7", 5=>X"8", 6=>X"B", 7=>X"0"),
+     1 => (0=>X"F", 1=>X"1", 2=>X"3", 3=>X"4", 4=>X"C", 5=>X"6", 6=>X"B", 7=>X"0"),
+     2 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"4", 4=>X"C", 5=>X"8", 6=>X"B", 7=>X"0"),
+     3 => (0=>X"F", 1=>X"C", 2=>X"4", 3=>X"F", 4=>X"F", 5=>X"F", 6=>X"F", 7=>X"0"),
+     4 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"6", 4=>X"7", 5=>X"E", 6=>X"B", 7=>X"0"),
+     5 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"8", 4=>X"7", 5=>X"B", 6=>X"F", 7=>X"0"),
+     6 => (0=>X"F", 1=>X"3", 2=>X"6", 3=>X"A", 4=>X"D", 5=>X"E", 6=>X"B", 7=>X"0"),
+     7 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"8", 4=>X"7", 5=>X"B", 6=>X"E", 7=>X"C"),
+     8 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"5", 4=>X"8", 5=>X"D", 6=>X"E", 7=>X"0"),
+     9 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"F", 4=>X"7", 5=>X"E", 6=>X"D", 7=>X"0"),
+    10 => (0=>X"F", 1=>X"1", 2=>X"4", 3=>X"7", 4=>X"8", 5=>X"2", 6=>X"C", 7=>X"0"),
+    11 => (0=>X"F", 1=>X"1", 2=>X"4", 3=>X"7", 4=>X"5", 5=>X"2", 6=>X"C", 7=>X"0"),
+    12 => (0=>X"F", 1=>X"1", 2=>X"3", 3=>X"4", 4=>X"8", 5=>X"9", 6=>X"6", 7=>X"0"),
+    13 => (0=>X"F", 1=>X"F", 2=>X"F", 3=>X"4", 4=>X"8", 5=>X"5", 6=>X"F", 7=>X"0"),
+    14 => (0=>X"F", 1=>X"5", 2=>X"6", 3=>X"7", 4=>X"D", 5=>X"E", 6=>X"0", 7=>X"F"),
+    15 => (0=>X"F", 1=>X"1", 2=>X"3", 3=>X"4", 4=>X"C", 5=>X"F", 6=>X"B", 7=>X"0"),
+    16 => (0=>X"F", 1=>X"F", 2=>X"8", 3=>X"4", 4=>X"D", 5=>X"E", 6=>X"0", 7=>X"C"),
+    17 => (0=>X"F", 1=>X"F", 2=>X"8", 3=>X"4", 4=>X"D", 5=>X"E", 6=>X"0", 7=>X"C"),
+    18 => (0=>X"F", 1=>X"1", 2=>X"6", 3=>X"7", 4=>X"8", 5=>X"D", 6=>X"C", 7=>X"E"),
+    19 => (0=>X"F", 1=>X"1", 2=>X"3", 3=>X"5", 4=>X"D", 5=>X"8", 6=>X"E", 7=>X"0"),
+    20 => (0=>X"F", 1=>X"1", 2=>X"6", 3=>X"4", 4=>X"D", 5=>X"2", 6=>X"0", 7=>X"C"),
+    21 => (0=>X"F", 1=>X"1", 2=>X"8", 3=>X"7", 4=>X"A", 5=>X"B", 6=>X"0", 7=>X"C"),
+    22 => (0=>X"F", 1=>X"1", 2=>X"3", 3=>X"B", 4=>X"2", 5=>X"8", 6=>X"6", 7=>X"0"),
+    23 => (0=>X"F", 1=>X"1", 2=>X"4", 3=>X"C", 4=>X"7", 5=>X"8", 6=>X"6", 7=>X"0"),
+    24 => (0=>X"F", 1=>X"1", 2=>X"D", 3=>X"E", 4=>X"6", 5=>X"7", 6=>X"8", 7=>X"0"),
+    25 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"4", 4=>X"7", 5=>X"8", 6=>X"C", 7=>X"0"),
+    26 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"3", 4=>X"A", 5=>X"B", 6=>X"0", 7=>X"6"),
+    27 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"3", 4=>X"4", 5=>X"5", 6=>X"0", 7=>X"6"),
+    28 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"3", 4=>X"D", 5=>X"E", 6=>X"0", 7=>X"6"),
+    29 => (0=>X"F", 1=>X"1", 2=>X"F", 3=>X"E", 4=>X"7", 5=>X"A", 6=>X"B", 7=>X"0"),
+    30 => (0=>X"F", 1=>X"1", 2=>X"2", 3=>X"4", 4=>X"6", 5=>X"7", 6=>X"8", 7=>X"0"),
+    31 => (0=>X"F", 1=>X"1", 2=>X"3", 3=>X"7", 4=>X"A", 5=>X"6", 6=>X"9", 7=>X"0"),
+    others => (others => X"0")
+  );
+ 
+  type from_PLATFORM_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_PLATFORM_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+end;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.qip b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.qip
new file mode 100644
index 00000000..d4720390
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.qip	
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.vhd
new file mode 100644
index 00000000..faf66714
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/pll_mist.vhd	
@@ -0,0 +1,429 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_mist.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_mist IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_mist;
+
+
+ARCHITECTURE SYN OF pll_mist IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 20,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 40,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 50,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 163,
+		clk2_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "50"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "88.019997"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "163"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "13.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "88.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "163"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/cram.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/cram.hex
new file mode 100644
index 00000000..43e8f186
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/cram.hex	
@@ -0,0 +1,65 @@
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson.zip b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson.zip
new file mode 100644
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make.bat b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make.bat
new file mode 100644
index 00000000..1f1c106b
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/make.bat	
@@ -0,0 +1,7 @@
+copy /b ss.01e + ss.02e + ss.03e cpu.rom
+
+copy /b ss_7.b6 + ss_8.b5 tile.rom
+
+copy /b ss_9.m5 + ss_10.m6 + ss_11.m3 + ss_12.m4 + ss_13.m1 + ss_14.m2 sprite.rom
+
+copy /b cpu.rom + tile.rom + sprite.rom SONSON.ROM
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss.01e b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss.01e
new file mode 100644
index 0000000000000000000000000000000000000000..0efa9b568111bf8961b8a412103e6f2283e193f7
GIT binary patch
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss.02e b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss.02e
new file mode 100644
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss.03e b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss.03e
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_10.m6 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_10.m6
new file mode 100644
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_11.m3 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_11.m3
new file mode 100644
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_14.m2 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_14.m2
new file mode 100644
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_6.c11 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ss_6.c11
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HcmV?d00001

diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb1.k11 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb1.k11
new file mode 100644
index 0000000000000000000000000000000000000000..48de6994e0cb5c17a386a0bf286d4a89b921b2c4
GIT binary patch
literal 256
RcmZQzfB;4U0IF=*Q2-tg03iSX

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb2.c4 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb2.c4
new file mode 100644
index 0000000000000000000000000000000000000000..34c3eda62e2ec20168735fc0cedbd718f1588657
GIT binary patch
literal 256
zcmZ9_Sq=js3<bf5F=p8Bf7@x2uLP+C-mr$GiG_`WdlC#8j)FkNgNA<JZL5!^>_s&N
zx6u=_?6N-8Vk<@c)NF?4G1;Jgz??B-{9%5$zxkPq61)U+MQu;{$p|HKUJO&4e&@fN
WA1mf!6?;q6r}c5e^B1PyYO)vIw*<xj

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb3.h7 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb3.h7
new file mode 100644
index 0000000000000000000000000000000000000000..3d65b642870037666e8debbf51ca5f6fd996b35f
GIT binary patch
literal 256
zcmX|)NfN*y2n1aah_d|uw;4=TymYk;L-t9crzL1y9AxE2iC4}N_h03}CvX2f4D+QP
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a-~)&2?wH7Nk=94_!!xR&a$kPR=BK^ifCqU1

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb4.b2 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb4.b2
new file mode 100644
index 0000000000000000000000000000000000000000..86660493089a1037ca33b3601f2e320dfcce4945
GIT binary patch
literal 32
ocmZRW*<fUpu)EwX(=B7ctQrP}Gc%_%FcfTH;N+?;XjmW!0K&lwZ~y=R

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb5.b1 b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/sonson/ssb5.b1
new file mode 100644
index 0000000000000000000000000000000000000000..190bd6af106a013910dcd245817c7dbc0241af94
GIT binary patch
literal 32
lcmV~$feipK2m&ycEF#GK|J=0@s2So`+YF+Ze%r+b&Ib<Q0P6q%

literal 0
HcmV?d00001

diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_01e.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_01e.hex
new file mode 100644
index 00000000..f6fdf81e
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_01e.hex	
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_02e.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_02e.hex
new file mode 100644
index 00000000..5ce8268e
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_02e.hex	
@@ -0,0 +1,1025 @@
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_03e.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_03e.hex
new file mode 100644
index 00000000..1d572d63
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_03e.hex	
@@ -0,0 +1,1025 @@
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_10_m6.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_10_m6.hex
new file mode 100644
index 00000000..1f07a858
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_10_m6.hex	
@@ -0,0 +1,513 @@
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_11_m3.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_11_m3.hex
new file mode 100644
index 00000000..d0690684
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_11_m3.hex	
@@ -0,0 +1,513 @@
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_12_m4.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_12_m4.hex
new file mode 100644
index 00000000..aa9a3a68
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_12_m4.hex	
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_13_m1.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_13_m1.hex
new file mode 100644
index 00000000..79a23803
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_13_m1.hex	
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_14_m2.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_14_m2.hex
new file mode 100644
index 00000000..ccdd138f
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_14_m2.hex	
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_7_b6.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_7_b6.hex
new file mode 100644
index 00000000..cd07f54f
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_7_b6.hex	
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_8_b5.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_8_b5.hex
new file mode 100644
index 00000000..72679dc9
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_8_b5.hex	
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_9_m5.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_9_m5.hex
new file mode 100644
index 00000000..8bd65fe4
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/ss_9_m5.hex	
@@ -0,0 +1,513 @@
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/vram.hex b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/vram.hex
new file mode 100644
index 00000000..b2516eb4
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/roms/vram.hex	
@@ -0,0 +1,65 @@
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diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..41f5b7a8
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sdram.sv	
@@ -0,0 +1,348 @@
+//
+// sdram.v
+//
+// sdram controller implementation for the MiST board
+// https://github.com/mist-devel/mist-board
+// 
+// Copyright (c) 2013 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2019 Gyorgy Szombathelyi
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+
+module sdram (
+
+	// interface to the MT48LC16M16 chip
+	inout  reg [15:0] SDRAM_DQ,   // 16 bit bidirectional data bus
+	output reg [12:0] SDRAM_A,    // 13 bit multiplexed address bus
+	output reg        SDRAM_DQML, // two byte masks
+	output reg        SDRAM_DQMH, // two byte masks
+	output reg [1:0]  SDRAM_BA,   // two banks
+	output            SDRAM_nCS,  // a single chip select
+	output            SDRAM_nWE,  // write enable
+	output            SDRAM_nRAS, // row address select
+	output            SDRAM_nCAS, // columns address select
+
+	// cpu/chipset interface
+	input             init_n,     // init signal after FPGA config to initialize RAM
+	input             clk,        // sdram clock
+
+	input             port1_req,
+	output reg        port1_ack,
+	input             port1_we,
+	input      [23:1] port1_a,
+	input       [1:0] port1_ds,
+	input      [15:0] port1_d,
+	output reg [15:0] port1_q,
+
+	input      [16:1] cpu1_addr,
+	output reg [15:0] cpu1_q,
+	input      [16:1] cpu2_addr,
+	output reg [15:0] cpu2_q,
+
+	input             port2_req,
+	output reg        port2_ack,
+	input             port2_we,
+	input      [23:1] port2_a,
+	input       [1:0] port2_ds,
+	input      [15:0] port2_d,
+	output reg [31:0] port2_q,
+	
+	input      [16:2] sp_addr,
+	output reg [31:0] sp_q
+);
+
+localparam RASCAS_DELAY   = 3'd2;   // tRCD=20ns -> 2 cycles@<100MHz
+localparam BURST_LENGTH   = 3'b001; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE    = 1'b0;   // 0=sequential, 1=interleaved
+localparam CAS_LATENCY    = 3'd2;   // 2/3 allowed
+localparam OP_MODE        = 2'b00;  // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1;   // 0= write burst enabled, 1=only single access write
+
+localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 
+
+// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
+localparam RFRSH_CYCLES = 10'd842;
+
+// ---------------------------------------------------------------------
+// ------------------------ cycle state machine ------------------------
+// ---------------------------------------------------------------------
+
+/*
+ SDRAM state machine for 2 bank interleaved access
+ 1 word burst, CL2
+cmd issued  registered
+ 0 RAS0     cas1 - data0 read burst terminated
+ 1          ras0
+ 2          data1 returned
+ 3 CAS0     data1 returned
+ 4 RAS1     cas0
+ 5          ras1
+ 6 CAS1     data0 returned
+*/
+
+localparam STATE_RAS0      = 3'd0;   // first state in cycle
+localparam STATE_RAS1      = 3'd4;   // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_CAS0      = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
+localparam STATE_CAS1      = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
+localparam STATE_READ0     = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
+localparam STATE_READ1     = 3'd3;
+localparam STATE_DS1b      = 3'd0;
+localparam STATE_READ1b    = 3'd4;
+localparam STATE_LAST      = 3'd6;
+
+reg [2:0] t;
+
+always @(posedge clk) begin
+	t <= t + 1'd1;
+	if (t == STATE_LAST) t <= STATE_RAS0;
+end
+
+// ---------------------------------------------------------------------
+// --------------------------- startup/reset ---------------------------
+// ---------------------------------------------------------------------
+
+// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
+// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
+reg [4:0]  reset;
+reg        init = 1'b1;
+always @(posedge clk, negedge init_n) begin
+	if(!init_n) begin
+		reset <= 5'h1f;
+		init <= 1'b1;
+	end else begin
+		if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
+		init <= !(reset == 0);
+	end
+end
+
+// ---------------------------------------------------------------------
+// ------------------ generate ram control signals ---------------------
+// ---------------------------------------------------------------------
+
+// all possible commands
+localparam CMD_INHIBIT         = 4'b1111;
+localparam CMD_NOP             = 4'b0111;
+localparam CMD_ACTIVE          = 4'b0011;
+localparam CMD_READ            = 4'b0101;
+localparam CMD_WRITE           = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE       = 4'b0010;
+localparam CMD_AUTO_REFRESH    = 4'b0001;
+localparam CMD_LOAD_MODE       = 4'b0000;
+
+reg [3:0]  sd_cmd;   // current command sent to sd ram
+reg [15:0] sd_din;
+// drive control signals according to current command
+assign SDRAM_nCS  = sd_cmd[3];
+assign SDRAM_nRAS = sd_cmd[2];
+assign SDRAM_nCAS = sd_cmd[1];
+assign SDRAM_nWE  = sd_cmd[0];
+
+reg [24:1] addr_latch[2];
+reg [24:1] addr_latch_next[2];
+reg [16:1] addr_last[2];
+reg [16:2] addr_last2[2];
+reg [15:0] din_latch[2];
+reg  [1:0] oe_latch;
+reg  [1:0] we_latch;
+reg  [1:0] ds[2];
+
+reg        port1_state;
+reg        port2_state;
+
+localparam PORT_NONE  = 2'd0;
+localparam PORT_CPU1  = 2'd1;
+localparam PORT_CPU2  = 2'd2;
+localparam PORT_SP    = 2'd1;
+localparam PORT_REQ   = 2'd3;
+
+reg  [1:0] next_port[2];
+reg  [1:0] port[2];
+
+reg        refresh;
+reg [10:0] refresh_cnt;
+wire       need_refresh = (refresh_cnt >= RFRSH_CYCLES);
+
+// PORT1: bank 0,1
+always @(*) begin
+	if (refresh) begin
+		next_port[0] = PORT_NONE;
+		addr_latch_next[0] = addr_latch[0];
+	end else if (port1_req ^ port1_state) begin
+		next_port[0] = PORT_REQ;
+		addr_latch_next[0] = { 1'b0, port1_a };
+	end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
+		next_port[0] = PORT_CPU1;
+		addr_latch_next[0] = { 8'd0, cpu1_addr };
+	end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
+		next_port[0] = PORT_CPU2;
+		addr_latch_next[0] = { 8'd0, cpu2_addr };
+	end else begin
+		next_port[0] = PORT_NONE;
+		addr_latch_next[0] = addr_latch[0];
+	end
+end
+
+// PORT1: bank 2,3
+always @(*) begin
+	if (port2_req ^ port2_state) begin
+		next_port[1] = PORT_REQ;
+		addr_latch_next[1] = { 1'b1, port2_a };
+	end else if (sp_addr != addr_last2[PORT_SP]) begin
+		next_port[1] = PORT_SP;
+		addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
+	end else begin
+		next_port[1] = PORT_NONE;
+		addr_latch_next[1] = addr_latch[1];
+	end
+end
+
+always @(posedge clk) begin
+
+	// permanently latch ram data to reduce delays
+	sd_din <= SDRAM_DQ;
+	SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+	{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
+	sd_cmd <= CMD_NOP;  // default: idle
+	refresh_cnt <= refresh_cnt + 1'd1;
+
+	if(init) begin
+		// initialization takes place at the end of the reset phase
+		if(t == STATE_RAS0) begin
+
+			if(reset == 15) begin
+				sd_cmd <= CMD_PRECHARGE;
+				SDRAM_A[10] <= 1'b1;      // precharge all banks
+			end
+
+			if(reset == 10 || reset == 8) begin
+				sd_cmd <= CMD_AUTO_REFRESH;
+			end
+
+			if(reset == 2) begin
+				sd_cmd <= CMD_LOAD_MODE;
+				SDRAM_A <= MODE;
+				SDRAM_BA <= 2'b00;
+			end
+		end
+	end else begin
+		// RAS phase
+		// bank 0,1
+		if(t == STATE_RAS0) begin
+			addr_latch[0] <= addr_latch_next[0];
+			port[0] <= next_port[0];
+			{ oe_latch[0], we_latch[0] } <= 2'b00;
+
+			if (next_port[0] != PORT_NONE) begin
+				sd_cmd <= CMD_ACTIVE;
+				SDRAM_A <= addr_latch_next[0][22:10];
+				SDRAM_BA <= addr_latch_next[0][24:23];
+				addr_last[next_port[0]] <= addr_latch_next[0][16:1];
+				if (next_port[0] == PORT_REQ) begin
+					{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
+					ds[0] <= port1_ds;
+					din_latch[0] <= port1_d;
+					port1_state <= port1_req;
+				end else begin
+					{ oe_latch[0], we_latch[0] } <= 2'b10;
+					ds[0] <= 2'b11;
+				end
+			end
+		end
+
+		// bank 2,3
+		if(t == STATE_RAS1) begin
+			refresh <= 1'b0;
+			addr_latch[1] <= addr_latch_next[1];
+			{ oe_latch[1], we_latch[1] } <= 2'b00;
+			port[1] <= next_port[1];
+
+			if (next_port[1] != PORT_NONE) begin
+				sd_cmd <= CMD_ACTIVE;
+				SDRAM_A <= addr_latch_next[1][22:10];
+				SDRAM_BA <= addr_latch_next[1][24:23];
+				addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
+				if (next_port[1] == PORT_REQ) begin
+					{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
+					ds[1] <= port2_ds;
+					din_latch[1] <= port2_d;
+					port2_state <= port2_req;
+				end else begin
+					{ oe_latch[1], we_latch[1] } <= 2'b10;
+					ds[1] <= 2'b11;
+				end
+			end
+
+			if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
+				refresh <= 1'b1;
+				refresh_cnt <= 0;
+				sd_cmd <= CMD_AUTO_REFRESH;
+			end
+		end
+
+		// CAS phase
+		if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
+			sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
+			{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
+			if (we_latch[0]) begin
+				SDRAM_DQ <= din_latch[0];
+				port1_ack <= port1_req;
+			end
+			SDRAM_A <= { 4'b0010, addr_latch[0][9:1] };  // auto precharge
+			SDRAM_BA <= addr_latch[0][24:23];
+		end
+
+		if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
+			sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
+			{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+			if (we_latch[1]) begin
+				SDRAM_DQ <= din_latch[1];
+				port2_ack <= port2_req;
+			end
+			SDRAM_A <= { 4'b0010, addr_latch[1][9:1] };  // auto precharge
+			SDRAM_BA <= addr_latch[1][24:23];
+		end
+
+		// Data returned
+		if(t == STATE_READ0 && oe_latch[0]) begin
+			case(port[0])
+				PORT_REQ:  begin port1_q <= sd_din; port1_ack <= port1_req; end
+				PORT_CPU1: begin cpu1_q  <= sd_din; end
+				PORT_CPU2: begin cpu2_q  <= sd_din; end
+				default: ;
+			endcase;
+		end
+
+		if(t == STATE_READ1 && oe_latch[1]) begin
+			case(port[1])
+				PORT_REQ:	port2_q[15:0] <= sd_din;
+				PORT_SP :    sp_q[15:0] <= sd_din;
+				default: ;
+			endcase;
+		end
+
+		if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+
+		if(t == STATE_READ1b && oe_latch[1]) begin
+			case(port[1])
+				PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
+				PORT_SP : begin    sp_q[31:16] <= sd_din; end
+				default: ;
+			endcase;
+		end
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sound.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sound.vhd
new file mode 100644
index 00000000..7ffaf8f4
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sound.vhd	
@@ -0,0 +1,46 @@
+--------------------------------------------------------------------------------
+-- SubModule Sound
+-- Created   18/08/2005 6:39:14 PM
+--------------------------------------------------------------------------------
+Library IEEE;
+Use IEEE.Std_Logic_1164.all;
+
+entity Sound is 
+  generic
+  (
+    CLK_MHz           : natural := 0
+  );
+  port
+  (
+    sysClk            : in    std_logic;
+    reset             : in    std_logic;
+    
+    sndif_rd          : in    std_logic;
+    sndif_wr          : in    std_logic;
+    sndif_datai       : in    std_logic_vector(7 downto 0);
+    sndif_addr        : in    std_logic_vector(15 downto 0);
+    
+    snd_clk           : out   std_logic;
+    snd_data_l        : out   std_logic_vector(7 downto 0);
+    snd_data_r        : out   std_logic_vector(7 downto 0);
+    sndif_datao       : out   std_logic_vector(7 downto 0)
+  );
+  end entity Sound;
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+architecture Structure of Sound is
+
+-- Component Declarations
+
+-- Signal Declarations
+
+begin
+
+     snd_clk <= '0';
+     snd_data_l <= X"00";
+     snd_data_r <= X"00";
+     sndif_datao <= X"00";
+     
+end Structure;
+--------------------------------------------------------------------------------
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spram.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spram.vhd
new file mode 100644
index 00000000..d86010fc
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spram.vhd	
@@ -0,0 +1,91 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY spram IS
+	GENERIC
+	(
+		init_file			: string := "";
+		--numwords_a		: natural;
+		widthad_a			: natural;
+		width_a				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		wren_a => wren,
+		clock0 => clock,
+		address_a => address,
+		data_a => data,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_array.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_array.vhd
new file mode 100644
index 00000000..880f09f2
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_array.vhd	
@@ -0,0 +1,164 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+--use ieee.std_logic_arith.all;
+--use IEEE.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+
+entity sprite_array is
+  generic
+  (
+    N_SPRITES   : integer;
+    DELAY       : integer
+  );
+	port
+	(
+		reset				: in std_logic;
+
+    -- register interface
+    reg_i       : in to_SPRITE_REG_t;
+
+    -- video control signals
+    video_ctl   : in from_VIDEO_CTL_t;
+
+    -- extra data
+    graphics_i  : in to_GRAPHICS_t;
+
+		-- sprite data
+    row_a       : out SPRITE_ROW_A_t;
+    row_d       : in SPRITE_ROW_D_t;
+
+    -- video data
+    rgb         : out RGB_t;
+    set         : out std_logic;
+    pri         : out std_logic;
+    spr0_set    : out std_logic
+	);
+end entity sprite_array;
+
+architecture SYN of sprite_array is
+
+	type reg_a_t is array (natural range <>) of from_SPRITE_REG_t;
+  type ctl_i_a_t is array (natural range <>) of to_SPRITE_CTL_t;
+  type ctl_o_a_t is array (natural range <>) of from_SPRITE_CTL_t;
+  
+	alias clk       : std_logic is video_ctl.clk;
+	alias clk_ena   : std_logic is video_ctl.clk_ena;
+	
+	signal reg_o    : reg_a_t(0 to N_SPRITES-1);
+  signal ctl_i    : ctl_i_a_t(0 to N_SPRITES-1);
+  signal ctl_o    : ctl_o_a_t(0 to N_SPRITES-1);
+	
+	signal ld_r     : std_logic_vector(N_SPRITES-1 downto 0);
+	
+begin
+
+	-- Sprite Data Load Arbiter
+	-- - enables each sprite controller during hblank
+	--   to allow loading of sprite row data into row buffer
+	process (clk, clk_ena, reset)
+		variable i : integer range 0 to N_SPRITES-1;
+	begin
+		if reset = '1' then
+			-- enable must be 1 clock behind address to latch data after fetch
+			--ld_r <= (N_SPRITES-1 => '1', others => '0');
+      -- make ISE 9.2.03i happy...
+			ld_r(ld_r'left) <= '1';
+			ld_r(ld_r'left-1 downto 0) <= (others => '0');
+			i := 0;
+		elsif rising_edge(clk) and clk_ena = '1' then
+			ld_r <= ld_r(ld_r'left-1 downto 0) & ld_r(ld_r'left);
+			if i = N_SPRITES-1 then
+			  i := 0;
+			else
+			  i := i + 1;
+			end if;
+      row_a <= ctl_o(i).a;
+		end if;
+	end process;
+
+  -- sprite row data fan-out
+  GEN_ROW_D : for i in 0 to N_SPRITES-1 generate
+    ctl_i(i).ld <= ld_r(i);
+    ctl_i(i).d <= row_d;
+  end generate GEN_ROW_D;
+  
+	-- Sprite Priority Encoder
+	-- - determines which sprite pixel (if any) is to be displayed
+	-- We can use a clocked process here because the tilemap
+	-- output is 1 clock behind at this point
+	process (clk, clk_ena)
+		variable spr_on_v 	: std_logic := '0';
+		variable spr_pri_v 	: std_logic := '0';
+	begin
+		if rising_edge(clk) and clk_ena = '1' then
+			spr_on_v := '0';
+			spr_pri_v := '0';
+			for i in 0 to N_SPRITES-1 loop
+				-- if highest priority = 0 and pixel on
+				if spr_pri_v = '0' and ctl_o(i).set = '1' then
+					-- if no sprite on or this priority = 1
+					if spr_on_v = '0' or reg_o(i).pri = '1' then
+						rgb <= ctl_o(i).rgb;
+						spr_on_v := '1';					    -- flag as sprite on
+						spr_pri_v := reg_o(i).pri;		-- store priority
+					end if;
+				end if;
+			end loop;
+		end if;
+		set <= spr_on_v;
+		pri <= spr_pri_v;
+	end process;
+
+	-- for NES, and perhaps others
+	-- it's actually more complicated than this
+	-- but it'll do for now...
+	spr0_set <= ctl_o(0).set;
+		
+	--
+	-- Component Instantiation
+	--
+	
+	GEN_REGS : for i in 0 to N_SPRITES-1 generate
+	
+		sptReg_inst : entity work.sptReg
+			generic map
+			(
+				INDEX			=> i
+			)
+			port map
+			(
+        reg_i           => reg_i,
+				reg_o           => reg_o(i)
+			);
+
+		sptCtl_inst : entity work.spritectl
+			generic map
+			(
+				INDEX			=> i,
+				DELAY     => DELAY
+			)
+			port map
+			(
+        -- sprite registers
+        reg_i       => reg_o(i),
+        
+        -- video control signals
+        video_ctl   => video_ctl,
+
+        -- sprite control signals
+        ctl_i       => ctl_i(i),
+        ctl_o       => ctl_o(i),
+
+        graphics_i  => graphics_i
+      );
+				
+	end generate GEN_REGS;
+	
+end SYN;
+
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg.vhd
new file mode 100644
index 00000000..ee5cf179
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg.vhd	
@@ -0,0 +1,97 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+--use IEEE.numeric_std.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.video_controller_pkg.all;
+
+package sprite_pkg is
+
+  subtype SPRITE_N_t is std_logic_vector(11 downto 0);
+  subtype SPRITE_A_t is std_logic_vector(7 downto 0);
+  subtype SPRITE_D_t is std_logic_vector(7 downto 0);
+  
+  type from_SPRITE_REG_t is record
+    n         : SPRITE_N_t;
+    x         : std_logic_vector(10 downto 0);
+    y         : std_logic_vector(10 downto 0);
+    xflip     : std_logic;
+    yflip     : std_logic;
+    colour    : std_logic_vector(7 downto 0);
+    pri       : std_logic;
+  end record;
+  
+  type to_SPRITE_REG_t is record
+    clk       : std_logic;
+    clk_ena   : std_logic;
+    wr        : std_logic;
+    a         : SPRITE_A_t;
+    d         : SPRITE_D_t;
+  end record;
+
+  function NULL_TO_SPRITE_REG return to_SPRITE_REG_t;
+  
+  subtype SPRITE_ROW_D_t is std_logic_vector(63 downto 0);
+  subtype SPRITE_ROW_A_t is std_logic_vector(15 downto 0);
+  
+  type to_SPRITE_CTL_t is record
+    ld        : std_logic;
+    d         : SPRITE_ROW_D_t;
+  end record;
+  
+  type from_SPRITE_CTL_t is record
+    a         : SPRITE_ROW_A_t;
+    rgb       : RGB_t;
+    set       : std_logic;
+  end record;
+
+  function NULL_TO_SPRITE_CTL return to_SPRITE_CTL_t;
+
+  component sprite_array is
+    generic
+    (
+      N_SPRITES   : integer;
+      DELAY       : integer
+    );
+    port
+    (
+      reset				: in std_logic;
+
+      -- register interface
+      reg_i       : in to_SPRITE_REG_t;
+
+      -- video control signals
+      video_ctl   : in from_VIDEO_CTL_t;
+
+      -- extra data
+      graphics_i  : in to_GRAPHICS_t;
+
+      -- sprite data
+      row_a       : out SPRITE_ROW_A_t;
+      row_d       : in SPRITE_ROW_D_t;
+
+      -- video data
+      rgb         : out RGB_t;
+      set         : out std_logic;
+      pri         : out std_logic;
+      spr0_set    : out std_logic
+    );
+  end component sprite_array;
+
+  function flip_row
+  (
+    row_in      : std_logic_vector;
+    flip        : std_logic
+  )
+  return SPRITE_ROW_D_t;
+
+  function flip_1
+  (
+    d_i         : std_logic_vector;
+    flip        : std_logic
+  )
+  return std_logic_vector;
+
+end package sprite_pkg;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg_body.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg_body.vhd
new file mode 100644
index 00000000..551261b2
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprite_pkg_body.vhd	
@@ -0,0 +1,62 @@
+library work;
+use work.pace_pkg.all;
+--use work.sprite_pkg.all;
+
+package body sprite_pkg is
+
+  function NULL_TO_SPRITE_REG return to_SPRITE_REG_t is
+  begin
+    return ('0', '0', '0', (others => '0'), (others => '0'));
+  end function NULL_TO_SPRITE_REG;
+
+  function NULL_TO_SPRITE_CTL return to_SPRITE_CTL_t is
+  begin
+    return ('0', (others => '0'));
+  end function NULL_TO_SPRITE_CTL;
+
+  function flip_row
+  (
+    row_in      : std_logic_vector;
+    flip        : std_logic
+  )
+  return std_logic_vector is
+  
+    constant HALF	    : natural := (row_in'length / 2) - 1;
+
+    alias row_in_0    : std_logic_vector(row_in'length-1 downto 0)
+                          is row_in;
+    variable row_out  : std_logic_vector(row_in_0'range);
+    
+  begin
+
+    if flip = '0' then
+      return row_in;
+    else
+      for i in 0 to HALF loop
+        row_out ((HALF-i)*2+1 downto (HALF-i)*2) := row_in_0(i*2+1 downto i*2);
+      end loop;
+      return row_out;
+    end if;
+  
+  end flip_row;
+
+  function flip_1
+  (
+    d_i   : std_logic_vector;
+    flip  : std_logic
+   )
+   return std_logic_vector is
+    alias d_i_0   : std_logic_vector(d_i'length-1 downto 0) is d_i;
+    variable d_o  : std_logic_vector(d_i_0'range);
+   begin
+    if flip = '0' then
+      return d_i;
+    else
+      for i in d_i_0'range loop
+        d_o(i) := d_i_0(d_i_0'high-i);
+      end loop;
+      return d_o;
+    end if;
+   end function flip_1;
+    
+end package body sprite_pkg;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritectl.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritectl.vhd
new file mode 100644
index 00000000..d4758aa3
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritectl.vhd	
@@ -0,0 +1,160 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;    
+
+--
+-- SonSon Sprite Controller
+--
+--  Sprite data is 48 bits wide:
+--  <bitplane2><bitplane1><bitplane0>
+--  < 16 bits >< 16 bits >< 16 bits >
+--
+
+entity spritectl is
+	generic
+	(
+		INDEX		: natural;
+		DELAY   : integer
+	);
+	port               
+	(
+    -- sprite registers
+    reg_i       : in from_SPRITE_REG_t;
+    
+    -- video control signals
+    video_ctl   : in from_VIDEO_CTL_t;
+
+    -- sprite control signals
+    ctl_i       : in to_SPRITE_CTL_t;
+    ctl_o       : out from_SPRITE_CTL_t;
+    
+		graphics_i  : in to_GRAPHICS_t
+	);
+end entity spritectl;
+
+architecture SYN of spritectl is
+
+  alias clk       : std_logic is video_ctl.clk;
+  alias clk_ena   : std_logic is video_ctl.clk_ena;
+
+  signal flipData : std_logic_vector(47 downto 0);   -- flipped row data
+   
+begin
+
+  -- handle xflip
+  flipData(47 downto 32) <= flip_row (ctl_i.d(47 downto 32), reg_i.xflip);
+  flipData(31 downto 16) <= flip_row (ctl_i.d(31 downto 16), reg_i.xflip);
+  flipData(15 downto 0) <= flip_row (ctl_i.d(15 downto 0), reg_i.xflip);
+  
+	process (clk)
+
+   	variable rowStore : std_logic_vector(47 downto 0);  -- saved row of spt to show during visibile period
+		variable pel      : std_logic_vector(2 downto 0);
+    variable x        : unsigned(video_ctl.x'range);
+    variable y        : unsigned(video_ctl.y'range);
+    variable yMat     : boolean;    -- raster is between first and last line of sprite
+    variable xMat     : boolean;    -- raster in between left edge and end of line
+
+		-- the width of rowCount determines the scanline multipler
+		-- - eg.	(4 downto 0) is 1:1
+		-- 				(5 downto 0) is 2:1 (scan-doubling)
+  	variable rowCount : std_logic_vector(3+PACE_VIDEO_V_SCALE downto 0);
+
+    variable clut_i     : integer range 0 to 31;
+		variable clut_entry : sprite_clut_entry_t;
+    variable pel_i      : integer range 0 to 7;
+		variable pal_i      : integer range 0 to 15;
+		variable pal_entry  : palette_entry_t;
+
+  begin
+
+		if rising_edge(clk) then
+      if clk_ena = '1' then
+
+        x := unsigned(reg_i.x);
+        y := unsigned(reg_i.y);
+        
+        if video_ctl.hblank = '1' then
+
+          xMat := false;
+          -- stop sprites wrapping from bottom of screen
+          if unsigned(video_ctl.y) = 0 then
+            yMat := false;
+          end if;
+          
+          if y = unsigned(video_ctl.y) then
+            -- start counting sprite row
+            rowCount := (others => '0');
+            yMat := true;
+          elsif rowCount(rowCount'left downto rowCount'left-4) = "10000" then
+            yMat := false;				
+          end if;
+
+          if ctl_i.ld = '1' then
+            if yMat then
+              rowStore := flipData;			-- load sprite data
+            else
+              rowStore := (others => '0');
+            end if;
+          end if;
+              
+        elsif video_ctl.stb = '1' then
+        
+          if unsigned(video_ctl.x) = x then
+            -- count up at left edge of sprite
+            rowCount := std_logic_vector(unsigned(rowCount) + 1);
+            xMat := true;
+          end if;
+          
+          if xMat then
+            -- shift in next pixel
+            pel := rowStore(32) & rowStore(16) & rowStore(0);
+            rowStore(47 downto 32) := '0' & rowStore(47 downto 33);
+            rowStore(31 downto 16) := '0' & rowStore(31 downto 17);
+            rowStore(15 downto 0) := '0' & rowStore(15 downto 1);
+          end if;
+
+        end if;
+
+        -- extract R,G,B from colour palette
+        clut_i := to_integer(unsigned(reg_i.colour(4 downto 0)));
+        clut_entry := sprite_clut(clut_i);
+        pel_i := to_integer(unsigned(pel));
+        pal_i := to_integer(unsigned(clut_entry(pel_i)));
+        pal_entry := pal(16 + pal_i);
+        ctl_o.rgb.r <= pal_entry(0) & "0000";
+        ctl_o.rgb.g <= pal_entry(1) & "0000";
+        ctl_o.rgb.b <= pal_entry(2) & "0000";
+
+        -- set pixel transparency based on match
+        ctl_o.set <= '0';
+        if xMat and yMat and (pel_i /= 0) then
+          ctl_o.set <= '1';
+        end if;
+
+      end if; -- clk_ena='1'
+
+      -- generate sprite data address
+      ctl_o.a(ctl_o.a'left downto 14) <= (others => '0');
+      ctl_o.a(13 downto 5) <= reg_i.n(8 downto 0);
+      -- - sprite data consists of 16 consecutive bytes for the 1st half
+      -- then the next 16 bytes for the 2nd half
+      -- - because we need to fetch an entire row at once
+      --   use dual-port memory to access both halves of each row
+      ctl_o.a(4) <= '0'; -- used for 1st/2nd port of dual-port memory
+      if reg_i.yflip = '1' then
+        ctl_o.a(3 downto 0) <= not rowCount(rowCount'left-1 downto rowCount'left-4);
+      else
+        ctl_o.a(3 downto 0) <= rowCount(rowCount'left-1 downto rowCount'left-4);
+      end if;
+      
+    end if; -- rising_edge(clk)
+  end process;
+
+end SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritereg.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritereg.vhd
new file mode 100644
index 00000000..0635ea3e
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/spritereg.vhd	
@@ -0,0 +1,62 @@
+Library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.sprite_pkg.all;
+
+entity sptReg is
+
+	generic
+	(
+		INDEX			: natural
+	);
+	port
+	(
+    reg_i     : in to_SPRITE_REG_t;
+    reg_o     : out from_SPRITE_REG_t
+	);
+
+end sptReg;
+
+architecture SYN of sptReg is
+
+  alias clk       : std_logic is reg_i.clk;
+  alias clk_ena   : std_logic is reg_i.clk_ena;
+
+begin
+
+	process (clk)
+    variable i : integer range 0 to 31;
+	begin
+    -- sprite registers $2020-$207F, 4 bytes per sprite
+    i := to_integer(unsigned(reg_i.a(6 downto 2))) - 32/4;
+		if rising_edge(clk) then
+      if i = INDEX then
+        if reg_i.wr = '1' then
+          case reg_i.a(1 downto 0) is
+            when "00" =>
+              reg_o.y <= std_logic_vector(RESIZE(unsigned(reg_i.d), reg_o.y'length));
+            when "01" =>
+              reg_o.yflip <= not reg_i.d(7);
+              reg_o.xflip <= not reg_i.d(6);
+              reg_o.n(8) <= reg_i.d(5);
+              reg_o.colour <= std_logic_vector(RESIZE(unsigned(reg_i.d(4 downto 0)),
+                                                reg_o.colour'length));
+            when "10" =>
+              reg_o.n(7 downto 0) <= reg_i.d;
+            when others =>
+              reg_o.x <= std_logic_vector(RESIZE(unsigned(reg_i.d), reg_o.x'length));
+          end case;
+        end if;
+      end if;
+		end if;
+	end process;
+	
+  -- usused bits
+  reg_o.n(reg_o.n'left downto 9) <= (others => '0');
+  
+  reg_o.pri <= '1';
+
+end SYN;
+
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprom.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..292a214f
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/sprom.vhd	
@@ -0,0 +1,83 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		--numwords_a	  : natural;
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/target_top.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/target_top.vhd
new file mode 100644
index 00000000..cfd9a682
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/target_top.vhd	
@@ -0,0 +1,107 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.platform_pkg.all;
+
+entity target_top is
+  port(
+		vma				: out std_logic;
+      clk_sys      	: in std_logic;
+		clk_vid      	: in std_logic;
+		reset_in      	: in std_logic;
+      snd_l				: out std_logic_vector(7 downto 0);
+	   snd_r				: out std_logic_vector(7 downto 0);
+      vid_hs        	: out std_logic;
+      vid_vs        	: out std_logic;
+		vid_hb        	: out std_logic;
+      vid_vb        	: out std_logic;
+      vid_r         	: out std_logic_vector(3 downto 0);
+      vid_g         	: out std_logic_vector(3 downto 0);
+      vid_b         	: out std_logic_vector(3 downto 0);	
+		inputs_p1		: in std_logic_vector(7 downto 0);
+		inputs_p2		: in std_logic_vector(7 downto 0);
+		inputs_sys		: in std_logic_vector(7 downto 0);
+		inputs_dip1		: in std_logic_vector(7 downto 0);
+		inputs_dip2		: in std_logic_vector(7 downto 0);	
+		cpu_rom_addr	: out std_logic_vector(15 downto 0);
+	   cpu_rom_do		: in std_logic_vector(7 downto 0);
+	   tile_rom_addr	: out std_logic_vector(12 downto 0);
+	   tile_rom_do		: in std_logic_vector(15 downto 0)
+  );    
+  
+end target_top;
+
+architecture SYN of target_top is
+
+  signal clkrst_i       : from_CLKRST_t;
+  signal video_i        : from_VIDEO_t;
+  signal video_o        : to_VIDEO_t;
+  signal audio_i        : from_AUDIO_t;
+  signal audio_o        : to_AUDIO_t;
+  signal platform_i     : from_PLATFORM_IO_t;
+  signal platform_o     : to_PLATFORM_IO_t;
+
+
+begin
+
+clkrst_i.clk(0) <=clk_sys;
+clkrst_i.clk(1) <= clk_vid;
+clkrst_i.arst <= reset_in;
+clkrst_i.arst_n <= not clkrst_i.arst;
+
+video_i.clk <= clk_vid;
+video_i.clk_ena <= '1';
+video_i.reset <= reset_in;
+
+  GEN_RESETS : for i in 0 to 3 generate
+
+    process (clkrst_i.clk(i), clkrst_i.arst)
+      variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
+    begin
+      if clkrst_i.arst = '1' then
+        rst_r := (others => '1');
+      elsif rising_edge(clkrst_i.clk(i)) then
+        rst_r := rst_r(rst_r'left-1 downto 0) & '0';
+      end if;
+      clkrst_i.rst(i) <= rst_r(rst_r'left);
+    end process;
+
+  end generate GEN_RESETS;
+   
+vid_r <= video_o.rgb.r(9 downto 6);
+vid_g <= video_o.rgb.g(9 downto 6);
+vid_b <= video_o.rgb.b(9 downto 6);
+vid_hs <= video_o.hsync;
+vid_vs <= video_o.vsync;
+vid_hb <= video_o.hblank;
+vid_vb <= video_o.vblank;
+snd_l <= audio_o.ldata(15 downto 8);
+snd_r <= audio_o.rdata(15 downto 8);
+
+ pace_inst : entity work.pace                                            
+   port map(
+		clkrst_i				=> clkrst_i,
+		vma					=> vma,
+		inputs_p1       	=> inputs_p1, 
+		inputs_p2       	=> inputs_p2, 
+		inputs_sys       	=> inputs_sys,
+		inputs_dip1       => inputs_dip1, 
+		inputs_dip2       => inputs_dip2, 
+      video_i           => video_i,
+      video_o           => video_o,
+      audio_i           => audio_i,
+      audio_o           => audio_o,
+      platform_i        => platform_i,
+      platform_o        => platform_o,	
+		cpu_rom_addr      => cpu_rom_addr,
+	   cpu_rom_do	      => cpu_rom_do,
+	   tile_rom_addr     => tile_rom_addr,
+	   tile_rom_do	      => tile_rom_do
+    );
+	 
+end SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl.vhd
new file mode 100644
index 00000000..1b541124
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl.vhd	
@@ -0,0 +1,111 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.platform_pkg.all;
+use work.video_controller_pkg.all;
+
+--
+--	SonSon Tilemap Controller
+--
+
+architecture TILEMAP_1 of tilemapCtl is
+
+  alias clk       : std_logic is video_ctl.clk;
+  alias clk_ena   : std_logic is video_ctl.clk_ena;
+  alias stb       : std_logic is video_ctl.stb;
+  alias hblank    : std_logic is video_ctl.hblank;
+  alias vblank    : std_logic is video_ctl.vblank;
+  alias x         : std_logic_vector(video_ctl.x'range) is video_ctl.x;
+  alias y         : std_logic_vector(video_ctl.y'range) is video_ctl.y;
+  
+  alias scroll    : std_logic_vector(7 downto 0) is graphics_i.bit8(0);
+  
+begin
+
+	-- these are constant for a whole line
+  ctl_o.map_a(ctl_o.map_a'left downto 10) <= (others => '0');
+  ctl_o.map_a(9 downto 5) <= y(7 downto 3);
+  ctl_o.tile_a(ctl_o.tile_a'left downto 13) <= (others => '0');
+  ctl_o.tile_a(2 downto 0) <= y(2 downto 0);
+
+  -- generate attribute RAM address (same, different memory bank)
+  ctl_o.attr_a(ctl_o.map_a'left downto 10) <= (others => '0');
+  ctl_o.attr_a(9 downto 5) <= y(7 downto 3);
+  
+  -- generate pixel
+  process (clk, clk_ena)
+
+		variable x_adj		  : unsigned(x'range);
+    variable tile_d_r   : std_logic_vector(15 downto 0);
+		variable attr_d_r	  : std_logic_vector(7 downto 0);
+		variable map_d_r	  : std_logic_vector(7 downto 0);
+    variable pel        : std_logic_vector(1 downto 0);
+
+    variable clut_i     : integer range 0 to 63;
+    variable clut_entry : tile_clut_entry_t;
+    variable pel_i      : integer range 0 to 3;
+    variable pal_i      : integer range 0 to 255;
+    variable pal_entry  : palette_entry_t;
+
+  begin
+
+  	if rising_edge(clk) then
+      if clk_ena = '1' then
+
+        -- video is clipped left and right (only 224 wide)
+        if unsigned(y) < 40 then
+          x_adj := unsigned(x);
+          else
+          x_adj := unsigned(x) + unsigned(scroll);
+        end if;
+        
+        -- 1st stage of pipeline
+        -- - read tile from tilemap
+        -- - read attribute data
+        if stb = '1' then
+          ctl_o.map_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3));
+          ctl_o.attr_a(4 downto 0) <= std_logic_vector(x_adj(7 downto 3));
+        end if;
+        
+        -- 2nd stage of pipeline
+        -- - read tile data from tile ROM
+        if stb = '1' then
+          if x_adj(2 downto 0) = "001" then
+            attr_d_r := ctl_i.attr_d(attr_d_r'range);
+            --map_d_r := ctl_i.map_d(map_d_r'range);
+          end if;
+        end if;
+        ctl_o.tile_a(12 downto 11) <= attr_d_r(1 downto 0);
+        ctl_o.tile_a(10 downto 3) <= ctl_i.map_d(7 downto 0);
+
+        if stb = '1' then
+          if x_adj(2 downto 0) = "010" then
+            tile_d_r := ctl_i.tile_d(tile_d_r'range);
+          else
+            tile_d_r(15 downto 8) := tile_d_r(14 downto 8) & '0';
+            tile_d_r(7 downto 0) := tile_d_r(6 downto 0) & '0';
+          end if;
+        end if;
+        -- 1 bit from each byte
+        pel := tile_d_r(15) & tile_d_r(7);
+
+        -- extract R,G,B from colour palette
+        clut_i := to_integer(unsigned(attr_d_r(7 downto 2)));
+        clut_entry := tile_clut(clut_i);
+        pel_i := to_integer(unsigned(pel));
+        pal_i := to_integer(unsigned(clut_entry(pel_i)));
+        pal_entry := pal(pal_i);
+        ctl_o.rgb.r <= pal_entry(0) & "0000";
+        ctl_o.rgb.g <= pal_entry(1) & "0000";
+        ctl_o.rgb.b <= pal_entry(2) & "0000";
+
+        ctl_o.set <= '1';
+
+      end if; -- clk_ena
+		end if;
+  end process;
+
+end TILEMAP_1;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl_e.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl_e.vhd
new file mode 100644
index 00000000..ddb64495
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/tilemapctl_e.vhd	
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.platform_pkg.all;
+use work.video_controller_pkg.all;
+
+entity tilemapCtl is          
+  generic
+  (
+    DELAY       : integer
+  );
+  port               
+  (
+    reset				: in std_logic;
+
+    -- video control signals		
+    video_ctl   : in from_VIDEO_CTL_t;
+
+    -- tilemap controller signals
+    ctl_i       : in to_TILEMAP_CTL_t;
+    ctl_o       : out from_TILEMAP_CTL_t;
+
+    graphics_i  : in to_GRAPHICS_t
+  );
+end entity tilemapCtl;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller.vhd
new file mode 100644
index 00000000..14da0c20
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller.vhd	
@@ -0,0 +1,455 @@
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.video_controller_pkg.all;
+
+entity pace_video_controller is
+  generic
+  (
+		CONFIG		  : PACEVideoController_t := PACE_VIDEO_NONE;
+		DELAY       : integer := 1;
+		H_SIZE      : integer;
+		V_SIZE      : integer;
+    L_CROP      : integer range 0 to 255;
+    R_CROP      : integer range 0 to 255;
+		H_SCALE     : integer;
+		V_SCALE     : integer;
+    H_SYNC_POL  : std_logic := '1';
+    V_SYNC_POL  : std_logic := '1';
+		BORDER_RGB  : RGB_t := RGB_BLACK
+  );
+  port
+  (
+    -- clocking etc
+    video_i       : in from_VIDEO_t;
+
+		-- register interface
+		reg_i			    : in VIDEO_REG_t;
+    
+    -- video input data
+    rgb_i         : in RGB_t;
+
+		-- control signals (out)
+		video_ctl_o   : out from_VIDEO_CTL_t;
+
+    -- video output control & data
+    video_o       : out to_VIDEO_t
+  );
+end pace_video_controller;
+
+architecture SYN of pace_video_controller is
+
+  constant SIM_DELAY          : time := 2 ns;
+
+	constant VIDEO_H_SIZE				: integer := H_SIZE * H_SCALE;
+	constant VIDEO_V_SIZE				: integer := V_SIZE * V_SCALE;
+
+  subtype reg_t is integer range 0 to 2047;
+
+  alias clk       : std_logic is video_i.clk;
+  alias clk_ena   : std_logic is video_i.clk_ena;
+  alias reset     : std_logic is video_i.reset;
+  
+  -- registers
+  signal h_front_porch_r        : reg_t := 0;
+  signal h_sync_r               : reg_t := 0;
+  signal h_back_porch_r         : reg_t := 0;
+  signal h_border_r             : reg_t := 0;
+  signal h_video_r              : reg_t := 0;
+  signal v_front_porch_r        : reg_t := 0;
+  signal v_sync_r               : reg_t := 0;
+  signal v_back_porch_r         : reg_t := 0;
+  signal v_border_r             : reg_t := 0;
+  signal v_video_r              : reg_t := 0;
+
+  signal border_rgb_r           : RGB_t := ((others=>'0'), (others=>'0'), (others=>'0'));
+  
+  -- derived values
+  signal h_sync_start           : reg_t := 0;
+  signal h_back_porch_start     : reg_t := 0;
+  signal h_left_border_start    : reg_t := 0;
+  signal h_video_start          : reg_t := 0;
+  signal h_right_border_start   : reg_t := 0;
+  signal h_line_end             : reg_t := 0;
+  signal v_sync_start           : reg_t := 0;
+  signal v_back_porch_start     : reg_t := 0;
+  signal v_top_border_start     : reg_t := 0;
+  signal v_video_start          : reg_t := 0;
+  signal v_bottom_border_start  : reg_t := 0;
+  signal v_screen_end           : reg_t := 0;
+
+  signal hsync_s                : std_logic := '0';
+  signal vsync_s                : std_logic := '0';
+  signal hactive_s              : std_logic := '0';
+  signal vactive_s              : std_logic := '0';
+  signal hblank_s               : std_logic := '0';
+  signal vblank_s               : std_logic := '0';
+  
+  subtype count_t is integer range 0 to 2047;
+  signal x_count                : count_t := 0;
+  signal y_count                : count_t := 0;
+  
+  signal x_s                    : unsigned(10 downto 0) := (others => '0');
+  signal y_s                    : unsigned(10 downto 0) := (others => '0');
+  
+  --signal extended_reset         : std_logic := '1';
+  alias extended_reset          : std_logic is video_i.reset;
+  
+begin
+
+  -- registers
+	reg_proc: process (reset, clk)
+
+	begin
+		--if reset = '1' then
+			case CONFIG is
+
+        when PACE_VIDEO_VGA_240x320_60Hz =>
+          -- P3M, clk=11.136MHz, clk_ena=5.568MHz
+          h_front_porch_r <= 272-240;
+          h_sync_r <= 5;
+          h_back_porch_r <= 22;
+          h_border_r <= (240-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 326-320;
+          v_sync_r <= 1;
+          v_back_porch_r <= 5;
+          v_border_r <= (320-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_320x480_60Hz =>
+          -- VGA, clk=12.588MHz
+          --# 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio
+          --Modeline "320x240"    12.588    320  336  384  400    240  245  246  262 Doublescan
+          h_front_porch_r <= 16;
+          h_sync_r <= 48;
+          h_back_porch_r <= 16;
+          h_border_r <= (320-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= (5*2);
+          v_sync_r <= (1*2);
+          v_back_porch_r <= (16*2);
+          v_border_r <= (480-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_640x480_60Hz =>
+          -- VGA, clk=25.175MHz
+          h_front_porch_r <= 16;
+          h_sync_r <= 96;
+          h_back_porch_r <= 48;
+          h_border_r <= (640-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 10;
+          v_sync_r <= 2;
+          v_back_porch_r <= 33;
+          v_border_r <= (480-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_800x600_60Hz =>
+          -- SVGA, clk=40MHz
+          h_front_porch_r <= 40;
+          h_sync_r <= 128;
+          h_back_porch_r <= 88;
+          h_border_r <= (800-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 1;
+          v_sync_r <= 4;
+          v_back_porch_r <= 23;
+          v_border_r <= (600-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1024x768_60Hz =>
+          -- XVGA, clk=65MHz
+          h_front_porch_r <= 24;
+          h_sync_r <= 136;
+          h_back_porch_r <= 160;
+          h_border_r <= (1024-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 3;
+          v_sync_r <= 6;
+          v_back_porch_r <= 29;
+          v_border_r <= (768-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1366x768_60Hz =>
+          -- XVGA(NAVICO ROCKY), clk=72MHz
+          h_front_porch_r <= 88; --64;
+          h_sync_r <= 44; --112;
+          h_back_porch_r <= 148; --248;
+          h_border_r <= (1366-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 4; --3;
+          v_sync_r <= 5; --6;
+          v_back_porch_r <= 36; --18;
+          v_border_r <= (768-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1280x800_60Hz =>
+          -- Sentinel Mode 36, clk=103.2MHz
+          h_front_porch_r <= 64;
+          h_sync_r <= 32;
+          h_back_porch_r <= 362-32-64;
+          h_border_r <= (1280-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 3;
+          v_sync_r <= 4;
+          v_back_porch_r <= 38-4-3;
+          v_border_r <= (800-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1280x1024_60Hz =>
+          -- SXGA, clk=108MHz
+          h_front_porch_r <= 48;
+          h_sync_r <= 112;
+          h_back_porch_r <= 248;
+          h_border_r <= (1280-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 1;
+          v_sync_r <= 3;
+          v_back_porch_r <= 38;
+          v_border_r <= (1024-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_VGA_1680x1050_60Hz =>
+          -- WSXGA+, clk=147.14MHz
+          h_front_porch_r <= 104;
+          h_sync_r <= 184;
+          h_back_porch_r <= 288;
+          v_front_porch_r <= 1;
+          v_sync_r <= 3;
+          v_back_porch_r <= 33;
+          -- WSXGA+, clk=118MHz
+          --h_front_porch_r <= 48;
+          --h_sync_r <= 32;
+          --h_back_porch_r <= 80;
+          --v_front_porch_r <= 3;
+          --v_sync_r <= 6;
+          --v_back_porch_r <= 21;
+          h_border_r <= (1680-VIDEO_H_SIZE)/2;
+          v_border_r <= (1050-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_ARCADE_STD_336x240_60Hz =>
+          -- arcade standard resolution, clk=7.16MHz
+          h_front_porch_r <= 34;
+          h_sync_r <= 34;
+          h_back_porch_r <= 51;
+          h_border_r <= (336-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 3;
+          v_sync_r <= 3;
+          v_back_porch_r <= 16;
+          v_border_r <= (240-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64 =>
+          -- arcade standard resolution, clk=28.64MHz
+          h_front_porch_r <= 4*34;
+          h_sync_r <= 4*34;
+          h_back_porch_r <= 4*51;
+          h_border_r <= 4*(336-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 3;
+          v_sync_r <= 3;
+          v_back_porch_r <= 16;
+          v_border_r <= (240-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_CVBS_720x288p_50Hz =>
+          -- generic composite, clk=13.5MHz
+          h_front_porch_r <= (8+12);
+          h_sync_r <= 64;
+          h_back_porch_r <= (144-64-(8+12));
+          h_border_r <= (720-VIDEO_H_SIZE)/2;
+          v_front_porch_r <= 1;
+          v_sync_r <= 3;
+          v_back_porch_r <= 20;
+          v_border_r <= (288-VIDEO_V_SIZE)/2;
+
+        when PACE_VIDEO_LCM_320x240_60Hz =>
+          -- DE1/2, clk=18MHz
+          h_front_porch_r <= 59;
+          h_sync_r <= 1;
+          h_back_porch_r <= 151;
+          h_border_r <= (320-VIDEO_H_SIZE)*3/2;
+          v_front_porch_r <= 8;
+          v_sync_r <= 1;
+          v_back_porch_r <= 13;
+          v_border_r <= (240-VIDEO_V_SIZE)/2;
+
+				when others =>
+					null;
+			end case;
+
+      h_video_r <= VIDEO_H_SIZE;
+      v_video_r <= VIDEO_V_SIZE;
+      border_rgb_r <= BORDER_RGB;
+      
+		--end if;
+	end process reg_proc;
+
+  -- register some arithmetic
+  init_proc: process (reset, clk, clk_ena)
+  begin
+    if reset = '1' then
+      null;
+    elsif rising_edge(clk) then
+      h_sync_start <= h_front_porch_r - 1;
+      h_back_porch_start <= h_sync_start + h_sync_r;
+      h_left_border_start <= h_back_porch_start + h_back_porch_r;
+      h_video_start <= h_left_border_start + h_border_r;
+      h_right_border_start <= h_video_start + h_video_r;
+      h_line_end <= h_right_border_start + h_border_r;
+      v_sync_start <= v_front_porch_r - 1;
+      v_back_porch_start <= v_sync_start + v_sync_r;
+      v_top_border_start <= v_back_porch_start + v_back_porch_r;
+      v_video_start <= v_top_border_start + v_border_r;
+      v_bottom_border_start <= v_video_start + v_video_r;
+      v_screen_end <= v_bottom_border_start + v_border_r;
+    end if;
+  end process init_proc;
+  
+  reset_proc: process (reset, clk)
+    variable count_v : integer;
+  begin
+    if reset = '1' then
+      --extended_reset <= '1';
+      count_v := 7;
+    elsif rising_edge(clk) then
+      if count_v = 0 then
+        --extended_reset <= '0';
+      else
+        count_v := count_v - 1;
+      end if;
+    end if;
+  end process reset_proc;
+
+  -- video control outputs
+  timer_proc: process (extended_reset, clk, clk_ena)
+  begin
+    if extended_reset = '1' then
+      hblank_s <= '1';
+      vblank_s <= '1';
+      hactive_s <= '0';
+      vactive_s <= '0';
+      hsync_s <= not H_SYNC_POL;
+      x_count <= 0;
+      y_count <= 0;
+    elsif rising_edge(clk) and clk_ena = '1' then
+      if x_count = h_line_end then
+        hblank_s <= '1';
+        hactive_s <= '0';     -- for 0 borders
+        if y_count = v_screen_end then
+          vblank_s <= '1';
+          vactive_s <= '0';   -- for 0 borders
+          y_count <= 0;
+        else
+          y_s <= y_s + 1;
+          if y_count = v_sync_start then
+            vsync_s <= V_SYNC_POL;
+          elsif y_count = v_back_porch_start then
+            vsync_s <= not V_SYNC_POL;
+          elsif y_count = v_video_start then
+            vblank_s <= '0';  -- for 0 borders
+            vactive_s <= '1';
+            y_s <= (others => '0');
+          -- check the borders last in case they're 0
+          elsif y_count = v_top_border_start then
+            vblank_s <= '0';
+          elsif y_count = v_bottom_border_start then
+            vactive_s <= '0';
+          end if;
+          y_count <= y_count + 1;
+        end if;
+        x_count <= 0;
+      else
+        x_s <= x_s + 1;
+        if x_count = h_sync_start then
+          hsync_s <= H_SYNC_POL;
+        elsif x_count = h_back_porch_start then
+          hsync_s <= not H_SYNC_POL;
+        elsif x_count = h_video_start then
+          hblank_s <= '0'; -- for 0 borders
+          hactive_s <= '1';
+          x_s <= (others => '0');
+          -- check the borders last in case they're 0
+        elsif x_count = h_left_border_start then
+          hblank_s <= '0';
+        elsif x_count = h_right_border_start then
+          hactive_s <= '0';
+        end if;
+        x_count <= x_count + 1;
+      end if;
+    end if; -- rising_edge(clk) and clk_ena = '1'
+  end process timer_proc;
+
+  -- pass-through for tile/bitmap & sprite controllers
+  video_ctl_o.clk <= clk;
+  video_ctl_o.clk_ena <= clk_ena;
+  
+  -- for video DACs and TFT output
+  video_o.clk <= clk;
+
+  BLK_VIDEO_O : block
+
+    constant PIPELINE_DELAY : natural := DELAY+1;
+
+    -- won't synthesize correctly under ISE if these are variables
+    signal hactive_v_r  : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+    signal vactive_v_r  : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+
+  begin
+  
+    video_o_proc: process (extended_reset, clk, clk_ena)
+      variable hsync_v_r    : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      variable vsync_v_r    : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      --variable hactive_v_r  : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      --variable vactive_v_r  : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      variable hblank_v_r   : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      variable vblank_v_r   : std_logic_vector(PIPELINE_DELAY-1 downto 0) := (others => '0');
+      alias hsync_v         : std_logic is hsync_v_r(hsync_v_r'left);
+      alias vsync_v         : std_logic is vsync_v_r(vsync_v_r'left);
+      alias hactive_v       : std_logic is hactive_v_r(hactive_v_r'left);
+      alias vactive_v       : std_logic is vactive_v_r(vactive_v_r'left);
+      alias hblank_v        : std_logic is hblank_v_r(hblank_v_r'left);
+      alias vblank_v        : std_logic is vblank_v_r(vblank_v_r'left);
+      variable stb_cnt_v    : unsigned(3 downto 0); -- up to 16x scaling
+    begin
+      if extended_reset = '1' then
+        hsync_v_r := (others => not H_SYNC_POL);
+        vsync_v_r := (others => not V_SYNC_POL);
+        hactive_v_r <= (others => '0');
+        vactive_v_r <= (others => '0');
+        hblank_v_r := (others => '0');
+        vblank_v_r := (others => '0');
+        stb_cnt_v := (others => '1');
+      elsif rising_edge(clk) and clk_ena = '1' then
+  
+        -- register control signals and handle scaling
+        video_ctl_o.hblank <= not hactive_s after SIM_DELAY;	-- used only by the bitmap/tilemap/sprite controllers
+        video_ctl_o.vblank <= not vactive_s after SIM_DELAY;	-- used only by the bitmap/tilemap/sprite controllers
+        -- handle scaling
+        video_ctl_o.stb <= stb_cnt_v(H_SCALE-1) after SIM_DELAY;
+        if hactive_s = '1' and vactive_s = '1' then
+          stb_cnt_v := stb_cnt_v + 2;
+        elsif hblank_s = '0' and vblank_s = '0' then    
+          stb_cnt_v := (others => '1');
+        end if;
+        video_ctl_o.x <= std_logic_vector(resize(x_s(x_s'left downto H_SCALE-1), video_ctl_o.x'length)) after SIM_DELAY;
+        video_ctl_o.y <= std_logic_vector(resize(y_s(y_s'left downto V_SCALE-1), video_ctl_o.y'length)) after SIM_DELAY;
+  
+        -- register video outputs
+        if hactive_v = '1' and vactive_v = '1' then
+          -- active video
+          if  x_s(x_s'left downto H_SCALE-1) < (L_CROP + PIPELINE_DELAY) or 
+              x_s(x_s'left downto H_SCALE-1) >= (H_SIZE - R_CROP + PIPELINE_DELAY) then
+            video_o.rgb <= RGB_BLACK after SIM_DELAY;
+          else
+            video_o.rgb <= rgb_i after SIM_DELAY;
+          end if;
+        elsif hblank_v = '0' and vblank_v = '0' then
+          -- border
+          video_o.rgb <= border_rgb_r after SIM_DELAY;
+        else
+          video_o.rgb.r <= (others => '0') after SIM_DELAY;
+          video_o.rgb.g <= (others => '0') after SIM_DELAY;
+          video_o.rgb.b <= (others => '0') after SIM_DELAY;
+        end if;
+        video_o.hsync <= hsync_v after SIM_DELAY;
+        video_o.vsync <= vsync_v after SIM_DELAY;
+        video_o.hblank <= hblank_v after SIM_DELAY;
+        video_o.vblank <= vblank_v after SIM_DELAY;
+        -- pipelined signals
+        hsync_v_r := hsync_v_r(hsync_v_r'left-1 downto 0) & hsync_s;
+        vsync_v_r := vsync_v_r(vsync_v_r'left-1 downto 0) & vsync_s;
+        hactive_v_r <= hactive_v_r(hactive_v_r'left-1 downto 0) & hactive_s;
+        vactive_v_r <= vactive_v_r(vactive_v_r'left-1 downto 0) & vactive_s;
+        hblank_v_r := hblank_v_r(hblank_v_r'left-1 downto 0) & hblank_s;
+        vblank_v_r := vblank_v_r(vblank_v_r'left-1 downto 0) & vblank_s;
+      end if;
+    end process video_o_proc;
+
+  end block BLK_VIDEO_O;
+  
+end SYN;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg.vhd
new file mode 100644
index 00000000..183bfe23
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg.vhd	
@@ -0,0 +1,229 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+--use IEEE.numeric_std.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+package video_controller_pkg is
+
+  type PACEVideoController_t is
+  (
+    PACE_VIDEO_NONE,                      -- PACE video controller not used
+    PACE_VIDEO_VGA_240x320_60Hz,          -- P3M video
+    PACE_VIDEO_VGA_320x480_60Hz,          -- for 320x200 (12.588MHz)
+    PACE_VIDEO_VGA_640x480_60Hz,          -- generic VGA (25.175MHz)
+    PACE_VIDEO_VGA_800x600_60Hz,          -- generic VGA (40MHz)
+    PACE_VIDEO_VGA_1024x768_60Hz,         -- XVGA (65MHz)
+    PACE_VIDEO_VGA_1366x768_60Hz,         -- (NAVICO ROCKY) (72MHz)
+    PACE_VIDEO_VGA_1280x800_60Hz,         -- Sentinel Mode 36
+    PACE_VIDEO_VGA_1280x1024_60Hz,        -- SXGA (108MHz)
+    PACE_VIDEO_VGA_1680x1050_60Hz,        -- WSXGA+ (147MHz)
+    PACE_VIDEO_ARCADE_STD_336x240_60Hz,   -- arcade std resolution (7.16MHz)
+    PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64,   -- arcade std resolution (28.64MHz)
+    PACE_VIDEO_CVBS_720x288p_50Hz,        -- generic composite
+    PACE_VIDEO_LCM_320x240_60Hz           -- DE2 LCD
+  );
+
+  type PACEVideoDisplay_t is
+  (
+    PACE_DISPLAY_NONE,
+    PACE_DISPLAY_VGA,
+    PACE_DISPLAY_CVBS,
+    PACE_DISPLAY_TFT
+  );
+
+  type RGB_t is record
+    r : std_logic_vector(9 downto 0);
+    g : std_logic_vector(9 downto 0);
+    b : std_logic_vector(9 downto 0);
+  end record;
+
+  type RGB_a is array (natural range <>) of RGB_t;
+  
+  function NULL_RGB return RGB_t;
+
+  constant RGB_BLACK    : RGB_t := ((others=>'0'),(others=>'0'),(others=>'0'));
+  constant RGB_RED      : RGB_t := ((others=>'1'),(others=>'0'),(others=>'0'));
+  constant RGB_GREEN    : RGB_t := ((others=>'0'),(others=>'1'),(others=>'0'));
+  constant RGB_YELLOW   : RGB_t := ((others=>'1'),(others=>'1'),(others=>'0'));
+  constant RGB_BLUE     : RGB_t := ((others=>'0'),(others=>'0'),(others=>'1'));
+  constant RGB_MAGENTA  : RGB_t := ((others=>'1'),(others=>'0'),(others=>'1'));
+  constant RGB_CYAN     : RGB_t := ((others=>'0'),(others=>'1'),(others=>'1'));
+  constant RGB_WHITE    : RGB_t := ((others=>'1'),(others=>'1'),(others=>'1'));
+  
+	type VIDEO_REG_t is record
+		h_scale		: std_logic_vector(2 downto 0);
+		v_scale		: std_logic_vector(2 downto 0);
+	end record;
+
+  type from_VIDEO_t is record
+    clk       : std_logic;
+    clk_ena   : std_logic;
+    reset     : std_logic;
+  end record;
+  
+  type to_VIDEO_t is record
+    clk       : std_logic;
+    rgb       : rgb_t;
+    hsync     : std_logic;
+    vsync     : std_logic;
+    hblank    : std_logic;
+    vblank    : std_logic;
+    de        : std_logic;
+  end record;
+
+  type from_VIDEO_CTL_t is record
+    clk       : std_logic;
+    clk_ena   : std_logic;
+    stb       : std_logic;
+    hblank    : std_logic;
+    vblank    : std_logic;
+    x         : std_logic_vector(10 downto 0);
+    y         : std_logic_vector(10 downto 0);
+  end record;
+  
+  subtype BITMAP_D_t is std_logic_vector(23 downto 0);
+  subtype BITMAP_A_t is std_logic_vector(15 downto 0);
+  
+  type to_BITMAP_CTL_t is record
+    d         : BITMAP_D_t;
+  end record;
+  
+  type to_BITMAP_CTL_a is array (natural range <>) of to_BITMAP_CTL_t;
+
+  function NULL_TO_BITMAP_CTL return to_BITMAP_CTL_t;
+
+  type from_BITMAP_CTL_t is record
+    a         : BITMAP_A_t;
+    rgb       : RGB_t;
+    set       : std_logic;
+  end record;
+
+  type from_BITMAP_CTL_a is array (natural range <>) of from_BITMAP_CTL_t;
+
+  subtype TILEMAP_D_t is std_logic_vector(15 downto 0);
+  subtype TILEMAP_A_t is std_logic_vector(15 downto 0);
+  subtype TILE_A_t is std_logic_vector(16 downto 0);
+  subtype TILE_D_t is std_logic_vector(23 downto 0);
+  subtype ATTR_A_t is std_logic_vector(15 downto 0);
+  subtype ATTR_D_t is std_logic_vector(15 downto 0);
+  
+  type to_TILEMAP_CTL_t is record
+    map_d     : TILEMAP_D_t;
+    tile_d    : TILE_D_t;
+    attr_d    : ATTR_D_t;
+  end record;
+
+  type to_TILEMAP_CTL_a is array (natural range <>) of to_TILEMAP_CTL_t;
+  
+  function NULL_TO_TILEMAP_CTL return to_TILEMAP_CTL_t;
+
+  type from_TILEMAP_CTL_t is record
+    map_a     : TILEMAP_A_t;
+    tile_a    : TILE_A_t;
+    attr_a    : ATTR_A_t;
+    rgb       : RGB_t;
+    set       : std_logic;
+  end record;
+
+  type from_TILEMAP_CTL_a is array (natural range <>) of from_TILEMAP_CTL_t;
+  
+  subtype PAL_ENTRY_t is std_logic_vector(15 downto 0);
+  type PAL_A_t is array (natural range <>) of PAL_ENTRY_t;
+  
+  subtype BYTE_t is std_logic_vector(7 downto 0);
+  type BYTE_A_t is array (natural range <>) of BYTE_t;
+  
+  subtype WORD_t is std_logic_vector(15 downto 0);
+  type WORD_A_t is array (natural range <>) of WORD_t;
+  
+  type to_GRAPHICS_t is record
+    pal       : PAL_A_t(0 to 15);
+    -- for various uses
+    bit8      : BYTE_A_t(0 to 7);
+    bit16     : WORD_A_t(0 to 3);
+    -- 'native' graphics stream
+    hsync     : std_logic;
+    vsync     : std_logic;
+    rgb       : RGB_t;
+  end record;
+
+  function NULL_TO_GRAPHICS return to_GRAPHICS_t;
+
+  type from_GRAPHICS_t is record
+    y         : std_logic_vector(10 downto 0);
+    hblank    : std_logic;
+    vblank    : std_logic;
+  end record;
+
+  component pace_video_controller is
+    generic
+    (
+      CONFIG		  : PACEVideoController_t := PACE_VIDEO_NONE;
+      DELAY       : integer := 1;
+      H_SIZE      : integer;
+      V_SIZE      : integer;
+      --H_SCALE     : integer;
+      --V_SCALE     : integer;
+      BORDER_RGB  : RGB_t := RGB_BLACK
+    );
+    port
+    (
+      -- clocking etc
+      video_i       : in from_VIDEO_t;
+      
+      -- register interface
+      reg_i			    : in VIDEO_REG_t;
+      
+      -- video input data
+      rgb_i         : in RGB_t;
+
+      -- control signals (out)
+      video_ctl_o   : from_VIDEO_CTL_t;
+      
+      -- Outputs to video
+      video_o       : out to_VIDEO_t
+    );
+  end component pace_video_controller;
+
+	component tilemapCtl is          
+	  generic
+	  (
+	    DELAY       : integer
+	  );
+	  port               
+	  (
+	    reset				: in std_logic;
+	
+	    -- video control signals		
+	    video_ctl   : in from_VIDEO_CTL_t;
+	
+	    -- tilemap controller signals
+	    ctl_i       : in to_TILEMAP_CTL_t;
+	    ctl_o       : out from_TILEMAP_CTL_t;
+	
+	    graphics_i  : in to_GRAPHICS_t
+	  );
+	end component tilemapCtl;
+
+  component bitmapCtl is
+    generic
+    (
+      DELAY         : integer
+    );
+    port               
+    (
+      reset					: in std_logic;
+
+      -- video control signals		
+      video_ctl     : in from_VIDEO_CTL_t;
+
+      -- bitmap controller signals
+      ctl_i         : in to_BITMAP_CTL_t;
+      ctl_o         : out from_BITMAP_CTL_t;
+
+      graphics_i    : in to_GRAPHICS_t
+    );
+  end component bitmapCtl;
+
+end package video_controller_pkg;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg_body.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg_body.vhd
new file mode 100644
index 00000000..996e5867
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_controller_pkg_body.vhd	
@@ -0,0 +1,29 @@
+library work;
+--use work.pace_pkg.all;
+
+package body video_controller_pkg is
+
+  function NULL_RGB return RGB_t is
+  begin
+    return (others => (others => '0'));
+  end NULL_RGB;
+
+  function NULL_TO_BITMAP_CTL return to_BITMAP_CTL_t is
+  begin
+    return (others => (others => '0'));
+  end NULL_TO_BITMAP_CTL;
+
+  function NULL_TO_TILEMAP_CTL return to_TILEMAP_CTL_t is
+  begin
+    return ((others => '0'), (others => '0'), (others => '0'));
+  end NULL_TO_TILEMAP_CTL;
+  
+  function NULL_TO_GRAPHICS return to_GRAPHICS_t is
+  begin
+    return ((others => (others => '0')), 
+            (others => (others => '0')), 
+            (others => (others => '0')),
+            '0', '0', NULL_RGB);
+  end NULL_TO_GRAPHICS;
+
+end package body video_controller_pkg;
diff --git a/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_mixer.vhd b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_mixer.vhd
new file mode 100644
index 00000000..fb4b4aa4
--- /dev/null
+++ b/Arcade_MiST/SonSon Hardware/Sonson_MiST/rtl/video_mixer.vhd	
@@ -0,0 +1,66 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.video_controller_pkg.all;
+use work.sprite_pkg.all;
+use work.platform_pkg.all;
+
+entity pace_video_mixer is
+  port
+  (
+      --bitmap_rgb    : in RGB_t;
+      --bitmap_set    : in std_logic;
+      bitmap_ctl_o  : in from_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
+      tilemap_ctl_o : in from_TILEMAP_CTL_a(1 to PACE_VIDEO_NUM_TILEMAPS);
+      sprite_rgb    : in RGB_t;
+      sprite_set    : in std_logic;
+      sprite_pri    : in std_logic;
+      
+      video_ctl_i   : in from_VIDEO_CTL_t;
+      graphics_i    : in to_GRAPHICS_t;
+      rgb_o         : out RGB_t
+  );
+end entity pace_video_mixer;
+  
+architecture SYN of pace_video_mixer is
+  signal bg_rgb : RGB_t;
+begin
+
+  GEN_BITMAPS : 
+    if PACE_VIDEO_NUM_BITMAPS = 1 generate
+      bg_rgb <= bitmap_ctl_o(1).rgb;
+    elsif PACE_VIDEO_NUM_BITMAPS = 2 generate
+      bg_rgb <= bitmap_ctl_o(1).rgb when bitmap_ctl_o(1).set = '1' else
+                bitmap_ctl_o(2).rgb;
+    elsif PACE_VIDEO_NUM_BITMAPS = 3 generate
+      bg_rgb <= bitmap_ctl_o(1).rgb when bitmap_ctl_o(1).set = '1' else
+                bitmap_ctl_o(2).rgb when bitmap_ctl_o(2).set = '1' else
+                bitmap_ctl_o(3).rgb when bitmap_ctl_o(3).set = '1' else
+                (others => (others => '0'));
+    else generate
+      bg_rgb <= (others => (others => '0'));
+  end generate GEN_BITMAPS;
+    
+  GEN_TILEMAPS : 
+    if PACE_VIDEO_NUM_TILEMAPS = 1 generate
+      rgb_o <=  sprite_rgb when sprite_set = '1' and sprite_pri = '1' else
+                tilemap_ctl_o(1).rgb when tilemap_ctl_o(1).set = '1' else
+                sprite_rgb when sprite_set = '1' else
+                bg_rgb;
+    elsif PACE_VIDEO_NUM_TILEMAPS = 2 generate
+      rgb_o <=  sprite_rgb when sprite_set = '1' and sprite_pri = '1' else
+                tilemap_ctl_o(1).rgb when tilemap_ctl_o(1).set = '1' else
+                tilemap_ctl_o(2).rgb when tilemap_ctl_o(2).set = '1' else
+                sprite_rgb when sprite_set = '1' else
+                bg_rgb;
+    else generate
+      rgb_o <=  sprite_rgb when sprite_set = '1' and sprite_pri = '1' else
+                sprite_rgb when sprite_set = '1' else
+                bg_rgb;
+  end generate GEN_TILEMAPS;
+  
+end architecture SYN;