From 39d4ce193c4d3ee2639b1ce122215ffdb30de17d Mon Sep 17 00:00:00 2001
From: gehstock <marceljenke@googlemail.com>
Date: Sun, 3 Jun 2018 00:17:54 +0200
Subject: [PATCH] New Arcade Platform

---
 .../Custom Hardware/Sprint2_MiST/clean.bat    |   37 +
 .../Sprint2_MiST/rtl/EngineSound.vhd          |  159 +++
 .../Custom Hardware/Sprint2_MiST/rtl/IO.vhd   |  186 +++
 .../Sprint2_MiST/rtl/Inputs.vhd               |  183 +++
 .../Sprint2_MiST/rtl/T65/Char_LSB.qip         |    0
 .../Sprint2_MiST/rtl/T65/Char_MSB.qip         |    0
 .../Sprint2_MiST/rtl/T65/T65.vhd              |  564 +++++++++
 .../Sprint2_MiST/rtl/T65/T65_ALU.vhd          |  260 ++++
 .../Sprint2_MiST/rtl/T65/T65_MCode.vhd        | 1052 +++++++++++++++++
 .../Sprint2_MiST/rtl/T65/T65_Pack.vhd         |  117 ++
 .../Sprint2_MiST/rtl/T65/addec_prom.qip       |    0
 .../rtl/T65/greybox_tmp/cbx_args.txt          |   16 +
 .../Sprint2_MiST/rtl/T65/j6_prom.qip          |    0
 .../Sprint2_MiST/rtl/T65/k6_prom.qip          |    0
 .../Sprint2_MiST/rtl/T65/prog_rom1.qip        |    0
 .../Sprint2_MiST/rtl/T65/prog_rom2.qip        |    0
 .../Sprint2_MiST/rtl/T65/prog_rom3.qip        |    0
 .../Sprint2_MiST/rtl/T65/prog_rom4.qip        |    0
 .../Sprint2_MiST/rtl/T65/ram1k_dp.qip         |    0
 .../Sprint2_MiST/rtl/T65/sync_prom.qip        |    0
 .../Sprint2_MiST/rtl/build_id.sv              |    2 +
 .../Sprint2_MiST/rtl/build_id.tcl             |   35 +
 .../Sprint2_MiST/rtl/collision.vhd            |  122 ++
 .../Sprint2_MiST/rtl/cpu_mem.vhd              |  436 +++++++
 .../Custom Hardware/Sprint2_MiST/rtl/dac.sv   |   33 +
 .../Custom Hardware/Sprint2_MiST/rtl/hq2x.sv  |  454 +++++++
 .../Sprint2_MiST/rtl/keyboard.sv              |   79 ++
 .../Sprint2_MiST/rtl/mist_io.sv               |  491 ++++++++
 .../Sprint2_MiST/rtl/motion.vhd               |  361 ++++++
 .../Custom Hardware/Sprint2_MiST/rtl/osd.sv   |  179 +++
 .../Sprint2_MiST/rtl/playfield.vhd            |  148 +++
 .../Custom Hardware/Sprint2_MiST/rtl/pll.v    |  337 ++++++
 .../Sprint2_MiST/rtl/ram1k_dp.qip             |    3 +
 .../Sprint2_MiST/rtl/ram1k_dp.vhd             |  224 ++++
 .../Sprint2_MiST/rtl/roms/6290-01b1.hex       |  129 ++
 .../Sprint2_MiST/rtl/roms/6291-01c1.hex       |  129 ++
 .../Sprint2_MiST/rtl/roms/6396-01p4.hex       |   33 +
 .../Sprint2_MiST/rtl/roms/6397-01r4.hex       |   33 +
 .../Sprint2_MiST/rtl/roms/6398-01k6.hex       |   33 +
 .../Sprint2_MiST/rtl/roms/6399-01j6.hex       |   33 +
 .../Sprint2_MiST/rtl/roms/6400-01m2.hex       |   17 +
 .../Sprint2_MiST/rtl/roms/6401-01e2.hex       |    3 +
 .../Sprint2_MiST/rtl/roms/6404d1.hex          |  129 ++
 .../Sprint2_MiST/rtl/roms/6405-02e1.hex       |  129 ++
 .../Sprint2_MiST/rtl/roms/6442-01d1.hex       |  129 ++
 .../Sprint2_MiST/rtl/roms/6443-01e1.hex       |  129 ++
 .../Sprint2_MiST/rtl/roms/Char_LSB.qip        |    3 +
 .../Sprint2_MiST/rtl/roms/Char_LSB.vhd        |  141 +++
 .../Sprint2_MiST/rtl/roms/Char_MSB.qip        |    3 +
 .../Sprint2_MiST/rtl/roms/Char_MSB.vhd        |  141 +++
 .../Sprint2_MiST/rtl/roms/addec_prom.qip      |    3 +
 .../Sprint2_MiST/rtl/roms/addec_prom.vhd      |  141 +++
 .../Sprint2_MiST/rtl/roms/j6_prom.qip         |    3 +
 .../Sprint2_MiST/rtl/roms/j6_prom.vhd         |  141 +++
 .../Sprint2_MiST/rtl/roms/k6_prom.qip         |    3 +
 .../Sprint2_MiST/rtl/roms/k6_prom.vhd         |  141 +++
 .../Sprint2_MiST/rtl/roms/prog_rom1.qip       |    3 +
 .../Sprint2_MiST/rtl/roms/prog_rom1.vhd       |  141 +++
 .../Sprint2_MiST/rtl/roms/prog_rom2.qip       |    3 +
 .../Sprint2_MiST/rtl/roms/prog_rom2.vhd       |  141 +++
 .../Sprint2_MiST/rtl/roms/prog_rom3.qip       |    3 +
 .../Sprint2_MiST/rtl/roms/prog_rom3.vhd       |  141 +++
 .../Sprint2_MiST/rtl/roms/prog_rom4.qip       |    3 +
 .../Sprint2_MiST/rtl/roms/prog_rom4.vhd       |  141 +++
 .../Sprint2_MiST/rtl/roms/sync_prom.qip       |    3 +
 .../Sprint2_MiST/rtl/roms/sync_prom.vhd       |  141 +++
 .../Sprint2_MiST/rtl/scandoubler.sv           |  195 +++
 .../Sprint2_MiST/rtl/screech.vhd              |   72 ++
 .../Sprint2_MiST/rtl/sprint1.vhd              |  313 +++++
 .../Sprint2_MiST/rtl/sprint2.vhd              |  338 ++++++
 .../Sprint2_MiST/rtl/sprint2_mist.sv          |  157 +++
 .../Sprint2_MiST/rtl/sprint2_sound.vhd        |  245 ++++
 .../Custom Hardware/Sprint2_MiST/rtl/sync.vhd |  177 +++
 .../Sprint2_MiST/rtl/video_mixer.sv           |  242 ++++
 .../Sprint2_MiST/snapshot/sprint2.rbf         |  Bin 0 -> 252260 bytes
 .../Custom Hardware/Sprint2_MiST/sprint2.qpf  |   30 +
 .../Custom Hardware/Sprint2_MiST/sprint2.qsf  |  186 +++
 .../Custom Hardware/Sprint2_MiST/sprint2.srf  |    8 +
 .../Custom Hardware/SprintOne_MiST/clean.bat  |   37 +
 .../SprintOne_MiST/rtl/EngineSound.vhd        |  159 +++
 .../SprintOne_MiST/rtl/Inputs.vhd             |  137 +++
 .../SprintOne_MiST/rtl/T65/T65.vhd            |  551 +++++++++
 .../SprintOne_MiST/rtl/T65/T65_ALU.vhd        |  260 ++++
 .../SprintOne_MiST/rtl/T65/T65_MCode.vhd      | 1050 ++++++++++++++++
 .../SprintOne_MiST/rtl/T65/T65_Pack.vhd       |  117 ++
 .../SprintOne_MiST/rtl/build_id.sv            |    2 +
 .../SprintOne_MiST/rtl/build_id.tcl           |   35 +
 .../SprintOne_MiST/rtl/collision.vhd          |   95 ++
 .../SprintOne_MiST/rtl/cpu_mem.vhd            |  506 ++++++++
 .../Custom Hardware/SprintOne_MiST/rtl/dac.sv |   33 +
 .../SprintOne_MiST/rtl/dpram.vhd              |  130 ++
 .../SprintOne_MiST/rtl/hq2x.sv                |  454 +++++++
 .../SprintOne_MiST/rtl/keyboard.sv            |   84 ++
 .../SprintOne_MiST/rtl/mist_io.sv             |  491 ++++++++
 .../SprintOne_MiST/rtl/motion.vhd             |  381 ++++++
 .../Custom Hardware/SprintOne_MiST/rtl/osd.sv |  179 +++
 .../SprintOne_MiST/rtl/playfield.vhd          |  170 +++
 .../Custom Hardware/SprintOne_MiST/rtl/pll.v  |  337 ++++++
 .../SprintOne_MiST/rtl/roms/6290-01b1.hex     |  129 ++
 .../SprintOne_MiST/rtl/roms/6291-01c1.hex     |  129 ++
 .../SprintOne_MiST/rtl/roms/6396-01p4.hex     |   33 +
 .../SprintOne_MiST/rtl/roms/6397-01r4.hex     |   33 +
 .../SprintOne_MiST/rtl/roms/6398-01k6.hex     |   33 +
 .../SprintOne_MiST/rtl/roms/6399-01j6.hex     |   33 +
 .../SprintOne_MiST/rtl/roms/6400-01m2.hex     |   17 +
 .../SprintOne_MiST/rtl/roms/6401-01e2.hex     |    3 +
 .../SprintOne_MiST/rtl/roms/6442-01d1.hex     |  129 ++
 .../SprintOne_MiST/rtl/roms/6443-01e1.hex     |  129 ++
 .../SprintOne_MiST/rtl/scandoubler.sv         |  195 +++
 .../SprintOne_MiST/rtl/screech.vhd            |   73 ++
 .../SprintOne_MiST/rtl/sprint1.vhd            |  310 +++++
 .../SprintOne_MiST/rtl/sprint1_mist.sv        |  144 +++
 .../SprintOne_MiST/rtl/sprint1_sound.vhd      |  195 +++
 .../SprintOne_MiST/rtl/sprom.vhd              |   82 ++
 .../SprintOne_MiST/rtl/sync.vhd               |  188 +++
 .../SprintOne_MiST/rtl/video_mixer.sv         |  242 ++++
 .../SprintOne_MiST/snapshot/sprint1.rbf       |  Bin 0 -> 248468 bytes
 .../SprintOne_MiST/sprint1.qpf                |   31 +
 .../SprintOne_MiST/sprint1.qsf                |  174 +++
 .../SuperBreakout_MiST/SuperBreakout.qpf      |   30 +
 .../SuperBreakout_MiST/SuperBreakout.qsf      |  168 +++
 .../SuperBreakout_MiST/clean.bat              |   37 +
 .../SuperBreakout_MiST/rtl/IO.vhd             |  173 +++
 .../SuperBreakout_MiST/rtl/T65/Char_LSB.qip   |    0
 .../SuperBreakout_MiST/rtl/T65/Char_MSB.qip   |    0
 .../SuperBreakout_MiST/rtl/T65/T65.vhd        |  551 +++++++++
 .../SuperBreakout_MiST/rtl/T65/T65_ALU.vhd    |  260 ++++
 .../SuperBreakout_MiST/rtl/T65/T65_MCode.vhd  | 1050 ++++++++++++++++
 .../SuperBreakout_MiST/rtl/T65/T65_Pack.vhd   |  117 ++
 .../SuperBreakout_MiST/rtl/T65/addec_prom.qip |    0
 .../rtl/T65/greybox_tmp/cbx_args.txt          |   16 +
 .../SuperBreakout_MiST/rtl/T65/j6_prom.qip    |    0
 .../SuperBreakout_MiST/rtl/T65/k6_prom.qip    |    0
 .../SuperBreakout_MiST/rtl/T65/prog_rom1.qip  |    0
 .../SuperBreakout_MiST/rtl/T65/prog_rom2.qip  |    0
 .../SuperBreakout_MiST/rtl/T65/prog_rom3.qip  |    0
 .../SuperBreakout_MiST/rtl/T65/prog_rom4.qip  |    0
 .../SuperBreakout_MiST/rtl/T65/ram1k_dp.qip   |    0
 .../SuperBreakout_MiST/rtl/T65/sync_prom.qip  |    0
 .../SuperBreakout_MiST/rtl/audio.vhd          |   69 ++
 .../SuperBreakout_MiST/rtl/build_id.sv        |    2 +
 .../SuperBreakout_MiST/rtl/build_id.tcl       |   35 +
 .../SuperBreakout_MiST/rtl/cpu_mem.vhd        |  435 +++++++
 .../SuperBreakout_MiST/rtl/dac.sv             |   33 +
 .../SuperBreakout_MiST/rtl/dpram.vhd          |  130 ++
 .../SuperBreakout_MiST/rtl/hq2x.sv            |  454 +++++++
 .../SuperBreakout_MiST/rtl/keyboard.sv        |   79 ++
 .../SuperBreakout_MiST/rtl/mist_io.sv         |  491 ++++++++
 .../SuperBreakout_MiST/rtl/motion.vhd         |  290 +++++
 .../SuperBreakout_MiST/rtl/osd.sv             |  179 +++
 .../SuperBreakout_MiST/rtl/paddle.vhd         |  101 ++
 .../SuperBreakout_MiST/rtl/paddle_analog.vhd  |   53 +
 .../SuperBreakout_MiST/rtl/playfield.vhd      |  148 +++
 .../SuperBreakout_MiST/rtl/pll.v              |  337 ++++++
 .../rtl/quadrature_decoder.vhd                |  103 ++
 .../SuperBreakout_MiST/rtl/roms/006400_m2.hex |   17 +
 .../SuperBreakout_MiST/rtl/roms/006401_e2.hex |    3 +
 .../SuperBreakout_MiST/rtl/roms/033280_p4.hex |   33 +
 .../SuperBreakout_MiST/rtl/roms/033281_r4.hex |   33 +
 .../SuperBreakout_MiST/rtl/roms/033282_k6.hex |    3 +
 .../SuperBreakout_MiST/rtl/roms/033453_c1.hex |  129 ++
 .../SuperBreakout_MiST/rtl/roms/033454_d1.hex |  129 ++
 .../SuperBreakout_MiST/rtl/roms/033455_e1.hex |  129 ++
 .../SuperBreakout_MiST/rtl/roms/roms.rar      |  Bin 0 -> 35063 bytes
 .../SuperBreakout_MiST/rtl/scandoubler.sv     |  195 +++
 .../SuperBreakout_MiST/rtl/sprom.vhd          |   82 ++
 .../SuperBreakout_MiST/rtl/super_breakout.vhd |  254 ++++
 .../rtl/super_breakout_mist.sv                |  147 +++
 .../SuperBreakout_MiST/rtl/sync.vhd           |  190 +++
 .../SuperBreakout_MiST/rtl/video_mixer.sv     |  242 ++++
 .../snapshot/SuperBreakout.rbf                |  Bin 0 -> 239690 bytes
 171 files changed, 24244 insertions(+)
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/clean.bat
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/EngineSound.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/IO.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/Inputs.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/Char_LSB.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/Char_MSB.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_ALU.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_MCode.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_Pack.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/addec_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/greybox_tmp/cbx_args.txt
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/j6_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/k6_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom1.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom2.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom3.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom4.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/ram1k_dp.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/sync_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/build_id.sv
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/collision.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/cpu_mem.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/dac.sv
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/hq2x.sv
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/keyboard.sv
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/mist_io.sv
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/motion.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/osd.sv
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/playfield.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/pll.v
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/ram1k_dp.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/ram1k_dp.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6290-01b1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6291-01c1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6396-01p4.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6397-01r4.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6398-01k6.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6399-01j6.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6400-01m2.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6401-01e2.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6404d1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6405-02e1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6442-01d1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6443-01e1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_LSB.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_LSB.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_MSB.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_MSB.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/addec_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/addec_prom.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/j6_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/j6_prom.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/k6_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/k6_prom.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom1.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom1.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom2.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom2.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom3.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom3.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom4.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom4.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/sync_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/sync_prom.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/scandoubler.sv
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/screech.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint1.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2_mist.sv
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2_sound.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sync.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/video_mixer.sv
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/snapshot/sprint2.rbf
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.qpf
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.qsf
 create mode 100644 Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.srf
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/clean.bat
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/EngineSound.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/Inputs.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_ALU.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_MCode.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_Pack.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/build_id.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/collision.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/cpu_mem.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/dac.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/dpram.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/hq2x.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/keyboard.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/mist_io.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/motion.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/osd.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/playfield.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/pll.v
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6290-01b1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6291-01c1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6396-01p4.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6397-01r4.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6398-01k6.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6399-01j6.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6400-01m2.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6401-01e2.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6442-01d1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6443-01e1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/scandoubler.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/screech.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1_mist.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1_sound.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprom.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sync.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/video_mixer.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/snapshot/sprint1.rbf
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/sprint1.qpf
 create mode 100644 Arcade_MiST/Custom Hardware/SprintOne_MiST/sprint1.qsf
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/SuperBreakout.qpf
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/SuperBreakout.qsf
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/clean.bat
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/IO.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/Char_LSB.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/Char_MSB.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_ALU.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_MCode.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_Pack.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/addec_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/greybox_tmp/cbx_args.txt
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/j6_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/k6_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom1.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom2.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom3.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom4.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/ram1k_dp.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/sync_prom.qip
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/audio.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/build_id.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/build_id.tcl
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/cpu_mem.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/dac.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/dpram.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/hq2x.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/keyboard.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/mist_io.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/motion.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/osd.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/paddle.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/paddle_analog.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/playfield.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/pll.v
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/quadrature_decoder.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/006400_m2.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/006401_e2.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033280_p4.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033281_r4.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033282_k6.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033453_c1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033454_d1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033455_e1.hex
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/roms.rar
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/scandoubler.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/sprom.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/super_breakout.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/sync.vhd
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/video_mixer.sv
 create mode 100644 Arcade_MiST/Custom Hardware/SuperBreakout_MiST/snapshot/SuperBreakout.rbf

diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/clean.bat b/Arcade_MiST/Custom Hardware/Sprint2_MiST/clean.bat
new file mode 100644
index 00000000..b3b7c3b5
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/clean.bat	
@@ -0,0 +1,37 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+
+pause
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/EngineSound.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/EngineSound.vhd
new file mode 100644
index 00000000..d5dc9f3c
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/EngineSound.vhd	
@@ -0,0 +1,159 @@
+-- Motor sound generator for Kee Games Sprint 2 
+-- Similar circuits are used in a number of other games
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 555 configured as an astable oscillator with the frequency controlled by
+-- a four bit binary value. The output of this oscillator drives a counter configured to produce an
+-- irregular thumping simulating the sound of an engine.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity EngineSound is 
+generic(
+			constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the overall engine sound frequency
+			);
+port(		
+			Clk_6			: in  std_logic; 
+			Ena_3k		: in  std_logic;
+			EngineData	: in	std_logic_vector(3 downto 0);
+			Motor			: out std_logic_vector(5 downto 0)
+			);
+end EngineSound;
+
+architecture rtl of EngineSound is
+
+signal RPM_val 				: integer range 1 to 350;
+signal Ramp_term_unfilt		: integer range 1 to 80000;
+signal Ramp_Count 			: integer range 0 to 80000;
+signal Ramp_term				: integer range 1 to 80000;
+signal Freq_mod				: integer range 0 to 400;
+signal Motor_Clk				: std_logic;
+
+signal Counter_A				: std_logic;
+signal Counter_B 				: unsigned(2 downto 0);
+signal Counter_A_clk			: std_logic;
+
+signal Motor_prefilter 		: unsigned(1 downto 0);
+signal Motor_filter_t1 		: unsigned(3 downto 0);
+signal Motor_filter_t2 		: unsigned(3 downto 0);
+signal Motor_filter_t3 		: unsigned(3 downto 0);
+signal Motor_filtered		: unsigned(5 downto 0);
+
+
+begin
+
+-- The frequency of the oscillator is set by a 4 bit binary value controlled by the game CPU
+-- in the real hardware this is a 555 coupled to a 4 bit resistor DAC used to pull the frequency.
+-- The output of this DAC has a capacitor to smooth out the frequency variation.
+-- The constants assigned to RPM_val can be tweaked to adjust the frequency curve
+
+Speed_select: process(Clk_6)
+begin
+	if rising_edge(Clk_6) then
+		case EngineData is
+			when "0000" => RPM_val <= 280;
+			when "0001" => RPM_val <= 245;
+			when "0010" => RPM_val <= 230;
+			when "0011" => RPM_val <= 205;
+			when "0100" => RPM_val <= 190;
+			when "0101" => RPM_val <= 175;
+			when "0110" => RPM_val <= 160;
+			when "0111" => RPM_val <= 145;
+		   when "1000" => RPM_val <= 130;
+			when "1001" => RPM_val <= 115;
+			when "1010" => RPM_val <= 100;
+			when "1011" => RPM_val <= 85;
+			when "1100" => RPM_val <= 70;
+			when "1101" => RPM_val <= 55;
+			when "1110" => RPM_val <= 40;
+			when "1111" => RPM_val <= 25; 
+		end case;
+	end if;
+end process;
+
+
+-- There is a RC filter between the frequency control DAC and the 555 to smooth out the transitions between the
+-- 16 possible states. We can simulate a reasonable approximation of that behavior using a linear slope which is
+-- not truly accurate but should be close enough.
+RC_filt: process(clk_6, ena_3k, ramp_term_unfilt)
+begin
+	if rising_edge(clk_6) then
+		if ena_3k = '1' then
+			if ramp_term_unfilt > ramp_term then
+				ramp_term <= ramp_term + 5;
+			elsif ramp_term_unfilt = ramp_term then
+				ramp_term <= ramp_term;
+			else
+				ramp_term <= ramp_term - 3;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower
+-- the frequency. RPM_val is multiplied by a constant which can be adjusted by changing the value of freq_tune
+-- to simulate the function of the frequency adjustment pot in the original hardware.
+ramp_term_unfilt <= ((200 - freq_tune) * RPM_val);
+
+-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator
+Ramp_osc: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		motor_clk <= '1';
+		ramp_count <= ramp_count + 1;
+		if ramp_count > ramp_term then
+			ramp_count <= 0;
+			motor_clk <= '0';
+		end if;
+	end if;
+end process;
+		
+
+-- 7492 counter with XOR on two of the outputs creates lumpy engine sound from smooth pulse train
+-- 7492 has two sections, one div-by-2 and one div-by-6.
+Engine_counter: process(motor_clk, counter_A_clk, counter_B)
+begin
+	if rising_edge(motor_clk) then
+		Counter_B <= Counter_B + '1';
+	end if;
+	Counter_A_clk <= Counter_B(0) xor Counter_B(2);
+	if rising_edge(counter_A_clk) then 
+		Counter_A <= (not Counter_A);
+	end if;
+end process;
+motor_prefilter <= ('0' & Counter_B(2)) + ('0' & Counter_B(1)) + ('0' & Counter_A);
+
+-- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Engine_filter: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		if (ena_3k = '1') then
+			motor_filter_t1 <= ("00" & motor_prefilter) + ("00" & motor_prefilter);
+			motor_filter_t2 <= motor_filter_t1;
+			motor_filter_t3 <= motor_filter_t2;
+		end if;
+		motor_filtered <= ("00" & motor_filter_t1) +
+								('0'  & motor_filter_t2 & '0') +
+								("00" & motor_filter_t3);
+	end if;
+end process;	
+
+motor <= std_logic_vector(motor_filtered);
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/IO.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/IO.vhd
new file mode 100644
index 00000000..8f1523bc
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/IO.vhd	
@@ -0,0 +1,186 @@
+-- IO block for Kee Games Sprint 2
+-- 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+entity IO is 
+port(		
+			CLK6				: in  std_logic; 
+			SW1				: in  std_logic_vector(7 downto 0); -- DIP switches
+			Coin1_n			: in  std_logic; -- Coin switches
+			Coin2_n 			: in 	std_logic;
+			Start1			: in	std_logic; -- 1 and 2 player start switches
+			Start2			: in	std_logic;
+			Trak_Sel			: in  std_logic;
+			Gas1				: in  std_logic;
+			Gas2				: in  std_logic;
+			Gear1_1			: in  std_logic;
+			Gear1_2			: in  std_logic;
+			Gear2_1			: in  std_logic;
+			Gear2_2			: in  std_logic;
+			Gear3_1			: in  std_logic;
+			Gear3_2			: in  std_logic;
+			Test				: in	std_logic; -- Self test switch
+			Slam				: in	std_logic; -- Slam switch
+			
+			Steering1A		: in  std_logic;
+			Steering1B		: in  std_logic;
+			Steering2A		: in  std_logic;
+			Steering2B		: in  std_logic;
+			
+
+			Lamp1				: out std_logic; -- Player 1 lamp
+			Lamp2				: out std_logic; -- Player 2 lamp
+			
+			Timer_Reset_n	: out std_logic;
+			IntAck_n			: out std_logic;
+			IO_wr				: in  std_logic;
+			
+			Counter			: out std_logic; -- Coin counter
+			Adr				: in  std_logic_vector(9 downto 0); -- Adress bus, only the lower 9 bits used by IO circuitry
+			Inputs			: out std_logic_vector(1 downto 0)  -- Out to data bus, only upper two bits used
+			);
+end IO;
+
+architecture rtl of IO is
+
+signal A8_8				: std_logic;
+signal H9_Q_n			: std_logic;
+signal H8_en			: std_logic;
+signal Coin1			: std_logic;
+signal Coin2			: std_logic;
+signal SW2_bank1		: std_logic;
+signal SW2_bank2		: std_logic;
+signal DipSW			: std_logic_vector(7 downto 0);
+signal E8_in			: std_logic_vector(3 downto 0);
+signal J9_out			: std_logic_vector(7 downto 0);
+signal E8_out			: std_logic_vector(9 downto 0);
+
+
+begin
+
+-- Inputs
+--M8: process(Adr(7 downto 6), Coin1, Coin2, Start1_n, Start2_n, Test_n, Slam_n, A8_8, SW2_bank2)
+--begin
+--	case Adr(7 downto 6) is
+--		when "00" => Inputs <= A8_8 & SW2_bank2; -- There is actually an inverter N9 fed by A8_8 so we will just account for that
+--		when "01" => Inputs <= Coin2 & Coin1;
+--		when "10" => Inputs <= Start2_n & Start1_n;
+--		when "11" => Inputs <= Test_n & Slam_n;
+--		when others => Inputs <= "11";
+--		end case;
+--end process;
+---- Coin switch inputs are active-high internally but inverted on board from active-low inputs
+--Coin1 <= (not Coin1_n);
+--Coin2 <= (not Coin2_n);
+
+
+F9: process(Adr, Gear1_1, Gear1_2, Gear2_1, Gear2_2, Gear3_1, Gear3_2)
+begin
+	if Adr(5) = '0' then -- Adr(5) is connected to enable
+		case Adr(2 downto 0) is
+			when "000" => F9_Q_n <= (not Gear1_1);
+			when "001" => F9_Q_n <= (not Gear1_2);
+			when "010" => F9_Q_n <= (not Gear2_1);
+			when "011" => F9_Q_n <= (not Gear2_2);
+			when "100" => F9_Q_n <= (not Gear3_1);
+			when "101" => F9_Q_n <= (not Gear3_2);
+			when "110" => F9_Q_n <= '0'; -- "Spare" switch on schematic
+			when "111" => F9_Q_n <= '0'; -- "Spare" switch on schematic
+			when others => F9_Q_n <= '1';
+			end case;
+	else
+		F9_Q_n <= '1';
+	end if;
+end process;
+
+H9: process(Adr, Gas1, Gas2, Self_Test, Start1, Start2, Trak_Sel)
+begin
+	if Adr(4) = '0' then -- Adr(4) is connected to enable
+		case Adr(2 downto 0) is
+			when "000" => H9_Q_n <= (not Gas1);
+			when "001" => H9_Q_n <= (not Gas2);
+			when "010" => H9_Q_n <= (not Self_Test);
+			when "011" => H9_Q_n <= '0';
+			when "100" => H9_Q_n <= (not Start1);
+			when "101" => H9_Q_n <= (not Start2);
+			when "110" => H9_Q_n <= (not Trak_Sel);
+			when others => H9_Q_n <= '1';
+			end case;
+	else
+		H9_Q_n <= '1';
+	end if;
+end process;
+		
+	
+-- The way the dip switches are wired in the real hardware requires some changes 
+-- to achieve the same result while using standard active-low switch inputs.
+-- Switches are split into two banks, each bank fed from half of selector J9.
+J9: process(Adr)
+begin
+	if Adr(3) = '1' then
+		J9_out <= "11111111";
+	else
+		case Adr(1 downto 0) is
+			when "00" => J9_out <= "11101110";
+			when "01" => J9_out <= "11011101";
+			when "10" => J9_out <= "10111011";
+			when "11" => J9_out <= "01110111";
+			end case;
+	end if;
+end process;
+
+-- Re-order the dip switch signals to match the physical order of the switches
+-- Bank 1
+DipSW(7) <= J9_out(7) when SW2(1) = '0' else '1';
+DipSW(6) <= J9_out(6) when SW2(3) = '0' else '1';
+DipSW(5) <= J9_out(5) when SW2(5) = '0' else '1';
+DipSW(4) <= J9_out(4) when SW2(7) = '0' else '1';
+
+--Bank 2
+DipSW(3) <= J9_out(3) when SW2(0) = '0' else '1';
+DipSW(2) <= J9_out(2) when SW2(2) = '0' else '1';
+DipSW(1) <= J9_out(1) when SW2(4) = '0' else '1';
+DipSW(0) <= J9_out(0) when SW2(6) = '0' else '1';
+
+-- Outputs from each switch bank are tied together, logical AND since they are active low
+SW2_bank1 <= DipSW(7) and DipSW(6) and DipSW(5) and DipSW(4);
+SW2_bank2 <= DipSW(3) and DipSW(2) and DipSW(1) and DipSW(0);
+
+-- Bank 1 of dip switches is multiplexed with player inputs connected to selectors F9 and H9
+A8_8 <= SW2_bank1 and F9_Q_n and H9_Q_n;
+
+
+-- Outputs
+E8_in <= IO_wr & Adr(9 downto 7);
+E8: process(E8_in)
+begin
+	case E8_in is
+		when "0000" => E8_out <= "1111111110";
+		when "0001" => E8_out <= "1111111101";
+      when "0100" => E8_out <= "1111101111";
+      when others => E8_out <= "1111111111";
+      end case;
+end process;
+
+H8_en <= E8_out(0);
+TIMER_RESET_n <= E8_out(1);
+INTACK_n <= E8_out(4);
+
+
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/Inputs.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/Inputs.vhd
new file mode 100644
index 00000000..d99b16ee
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/Inputs.vhd	
@@ -0,0 +1,183 @@
+-- Input block for Kee Games Sprint 2
+-- 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+entity control_inputs is 
+port(		
+			Clk6				: in  std_logic; 
+			SW1				: in  std_logic_vector(7 downto 0); -- DIP switches
+			Coin1_n			: in  std_logic; -- Coin switches
+			Coin2_n			: in 	std_logic;
+			Start1			: in	std_logic; -- 1 and 2 player start switches
+			Start2			: in	std_logic;
+			Trak_Sel			: in  std_logic; -- Track selection button
+			Gas1				: in  std_logic; -- Gas pedals, these are simple on/off switches
+			Gas2				: in  std_logic;
+			Gear1_1			: in  std_logic; -- Player 1 and 2 gear select levers
+			Gear1_2			: in  std_logic;
+			Gear2_1			: in  std_logic;
+			Gear2_2			: in  std_logic;
+			Gear3_1			: in  std_logic;
+			Gear3_2			: in  std_logic;
+			Self_Test		: in	std_logic; -- Self test switch
+			Steering1A_n	: in  std_logic; -- Steering wheel signals
+			Steering1B_n	: in  std_logic;
+			Steering2A_n	: in  std_logic;
+			Steering2B_n	: in  std_logic;
+			SteerRst1_n		: in  std_logic;
+			SteerRst2_n		: in  std_logic;
+			Adr				: in  std_logic_vector(9 downto 0); -- Adress bus, only the lower 9 bits used by IO circuitry
+			Inputs			: out std_logic_vector(1 downto 0)  -- Out to data bus, only upper two bits used
+			);
+end control_inputs;
+
+architecture rtl of control_inputs is
+
+signal A8_8					: std_logic;
+signal F9_Q_n				: std_logic;
+signal H9_Q_n				: std_logic;
+signal H8_en				: std_logic;
+signal Coin1				: std_logic;
+signal Coin2				: std_logic;
+signal SW1_bank1			: std_logic;
+signal SW1_bank2			: std_logic;
+signal DipSW				: std_logic_vector(7 downto 0);
+signal E8_in				: std_logic_vector(3 downto 0);
+signal J9_out				: std_logic_vector(7 downto 0);
+signal E8_out				: std_logic_vector(9 downto 0);
+
+signal Steering1B_Q_n	: std_logic;
+signal Steering1A_Q		: std_logic;
+signal Steering2B_Q_n 	: std_logic;
+signal Steering2A_Q		: std_logic;
+
+
+begin
+
+-- Inputs
+M8: process(Adr, A8_8, SW1_bank2, Coin2_n, Coin1_n, Steering1B_Q_n, Steering1A_Q, Steering2B_Q_n, Steering2A_Q)
+begin
+	case Adr(7 downto 6) is
+		when "00" => Inputs <= A8_8 & SW1_bank2; -- There is actually an inverter N9 fed by A8_8 so we will just account for that
+		when "01" => Inputs <= Coin2_n & Coin1_n;
+		when "10" => Inputs <= Steering1B_Q_n & Steering1A_Q;
+		when "11" => Inputs <= Steering2B_Q_n & Steering2A_Q;
+		when others => Inputs <= "11";
+		end case;
+end process;
+
+
+F9: process(Adr, Gear1_1, Gear1_2, Gear2_1, Gear2_2, Gear3_1, Gear3_2)
+begin
+	if Adr(5) = '0' then -- Adr(5) is connected to enable
+		case Adr(2 downto 0) is
+			when "000" => F9_Q_n <= (not Gear1_1);
+			when "001" => F9_Q_n <= (not Gear1_2);
+			when "010" => F9_Q_n <= (not Gear2_1);
+			when "011" => F9_Q_n <= (not Gear2_2);
+			when "100" => F9_Q_n <= (not Gear3_1);
+			when "101" => F9_Q_n <= (not Gear3_2);
+			when "110" => F9_Q_n <= '1'; -- "Spare" switch on schematic
+			when "111" => F9_Q_n <= '1'; -- "Spare" switch on schematic
+			when others => F9_Q_n <= '1';
+			end case;
+	else
+		F9_Q_n <= '1';
+	end if;
+end process;
+
+H9: process(Adr, Gas1, Gas2, Self_Test, Start1, Start2, Trak_Sel)
+begin
+	if Adr(4) = '0' then -- Adr(4) is connected to enable
+		case Adr(2 downto 0) is
+			when "000" => H9_Q_n <= (not Gas1);
+			when "001" => H9_Q_n <= (not Gas2);
+			when "010" => H9_Q_n <= (not Self_Test);
+			when "011" => H9_Q_n <= '1';
+			when "100" => H9_Q_n <= (not Start1);
+			when "101" => H9_Q_n <= (not Start2);
+			when "110" => H9_Q_n <= (not Trak_Sel);
+			when others => H9_Q_n <= '1';
+			end case;
+	else
+		H9_Q_n <= '1';
+	end if;
+end process;
+
+-- Steering
+M9: process(Steering1A_n, Steering1B_n, SteerRst1_n)
+begin
+	if SteerRst1_n <= '0' then -- Asynchronous clear
+		Steering1B_Q_n <= '1';
+	elsif rising_edge(Steering1B_n) then -- Steering encoders are active low but inverted on board
+		Steering1A_Q <= Steering1A_n;
+		Steering1B_Q_n <= '0';
+	end if;
+end process;
+	
+L9: process(Steering2A_n, Steering2B_n, SteerRst2_n)
+begin
+	if SteerRst2_n <= '0' then -- Asynchronous clear
+		Steering2B_Q_n <= '1';
+	elsif rising_edge(Steering2B_n) then 
+		Steering2A_Q <= Steering2A_n;
+		Steering2B_Q_n <= '0';
+	end if;
+end process;		
+		
+	
+-- The way the dip switches are wired in the real hardware requires OR logic 
+-- to achieve the same result while using standard active-low switch inputs.
+-- Switches are split into two banks, each bank fed from half of selector J9.
+J9: process(Adr)
+begin
+	if Adr(3) = '1' then
+		J9_out <= "11111111";
+	else
+		case Adr(1 downto 0) is
+			when "00" => J9_out <= "11101110";
+			when "01" => J9_out <= "11011101";
+			when "10" => J9_out <= "10111011";
+			when "11" => J9_out <= "01110111";
+			end case;
+	end if;
+end process;
+
+-- Re-order the dip switch signals to match the physical order of the switches
+-- Bank 1
+DipSW(7) <= J9_out(7) or SW1(1);
+DipSW(6) <= J9_out(6) or SW1(3);
+DipSW(5) <= J9_out(5) or SW1(5);
+DipSW(4) <= J9_out(4) or SW1(7);
+
+--Bank 2
+DipSW(3) <= J9_out(3) or SW1(0);
+DipSW(2) <= J9_out(2) or SW1(2);
+DipSW(1) <= J9_out(1) or SW1(4);
+DipSW(0) <= J9_out(0) or SW1(6);
+
+-- Outputs from each switch bank are tied together, logical AND since they are active low
+SW1_bank1 <= DipSW(7) and DipSW(6) and DipSW(5) and DipSW(4);
+SW1_bank2 <= DipSW(3) and DipSW(2) and DipSW(1) and DipSW(0);
+
+-- Bank 1 of dip switches is multiplexed with player inputs connected to selectors F9 and H9
+A8_8 <= SW1_bank1 and F9_Q_n and H9_Q_n;
+
+
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/Char_LSB.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/Char_LSB.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/Char_MSB.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/Char_MSB.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65.vhd
new file mode 100644
index 00000000..09253fe0
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65.vhd	
@@ -0,0 +1,564 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 more merging
+-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- 65C02 and 65C816 modes are incomplete
+-- Undocumented instructions are not supported
+-- Some interface signals behaves incorrect
+--
+-- File history :
+--
+--      0246 : First release
+--
+
+library IEEE;
+  use IEEE.std_logic_1164.all;
+  use IEEE.numeric_std.all;
+  use work.T65_Pack.all;
+
+-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
+-- the ready signal to limit the CPU.
+entity T65 is
+	port(
+		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+		Res_n   : in  std_logic;
+		Enable  : in  std_logic;
+		Clk     : in  std_logic;
+		Rdy     : in  std_logic;
+		Abort_n : in  std_logic;
+		IRQ_n   : in  std_logic;
+		NMI_n   : in  std_logic;
+		SO_n    : in  std_logic;
+		R_W_n   : out std_logic;
+		Sync    : out std_logic;
+		EF      : out std_logic;
+		MF      : out std_logic;
+		XF      : out std_logic;
+		ML_n    : out std_logic;
+		VP_n    : out std_logic;
+		VDA     : out std_logic;
+		VPA     : out std_logic;
+		A       : out std_logic_vector(23 downto 0);
+		DI      : in  std_logic_vector(7 downto 0);
+		DO      : out std_logic_vector(7 downto 0)
+	);
+end T65;
+
+architecture rtl of T65 is
+
+	-- Registers
+	signal ABC, X, Y, D       : std_logic_vector(15 downto 0);
+	signal P, AD, DL          : std_logic_vector(7 downto 0) :=  x"00";
+	signal BAH                : std_logic_vector(7 downto 0);
+	signal BAL                : std_logic_vector(8 downto 0);
+	signal PBR                : std_logic_vector(7 downto 0);
+	signal DBR                : std_logic_vector(7 downto 0);
+	signal PC                 : unsigned(15 downto 0);
+	signal S                  : unsigned(15 downto 0);
+	signal EF_i               : std_logic;
+	signal MF_i               : std_logic;
+	signal XF_i               : std_logic;
+
+	signal IR                 : std_logic_vector(7 downto 0);
+	signal MCycle             : std_logic_vector(2 downto 0);
+
+	signal Mode_r             : std_logic_vector(1 downto 0);
+	signal ALU_Op_r           : std_logic_vector(3 downto 0);
+	signal Write_Data_r       : std_logic_vector(2 downto 0);
+	signal Set_Addr_To_r      : std_logic_vector(1 downto 0);
+	signal PCAdder            : unsigned(8 downto 0);
+
+	signal RstCycle           : std_logic;
+	signal IRQCycle           : std_logic;
+	signal NMICycle           : std_logic;
+
+	signal B_o                : std_logic;
+	signal SO_n_o             : std_logic;
+	signal IRQ_n_o            : std_logic;
+	signal NMI_n_o            : std_logic;
+	signal NMIAct             : std_logic;
+
+	signal Break              : std_logic;
+
+	-- ALU signals
+	signal BusA               : std_logic_vector(7 downto 0);
+	signal BusA_r             : std_logic_vector(7 downto 0);
+	signal BusB               : std_logic_vector(7 downto 0);
+	signal ALU_Q              : std_logic_vector(7 downto 0);
+	signal P_Out              : std_logic_vector(7 downto 0);
+
+	-- Micro code outputs
+	signal LCycle             : std_logic_vector(2 downto 0);
+	signal ALU_Op             : std_logic_vector(3 downto 0);
+	signal Set_BusA_To        : std_logic_vector(2 downto 0);
+	signal Set_Addr_To        : std_logic_vector(1 downto 0);
+	signal Write_Data         : std_logic_vector(2 downto 0);
+	signal Jump               : std_logic_vector(1 downto 0);
+	signal BAAdd              : std_logic_vector(1 downto 0);
+	signal BreakAtNA          : std_logic;
+	signal ADAdd              : std_logic;
+	signal AddY               : std_logic;
+	signal PCAdd              : std_logic;
+	signal Inc_S              : std_logic;
+	signal Dec_S              : std_logic;
+	signal LDA                : std_logic;
+	signal LDP                : std_logic;
+	signal LDX                : std_logic;
+	signal LDY                : std_logic;
+	signal LDS                : std_logic;
+	signal LDDI               : std_logic;
+	signal LDALU              : std_logic;
+	signal LDAD               : std_logic;
+	signal LDBAL              : std_logic;
+	signal LDBAH              : std_logic;
+	signal SaveP              : std_logic;
+	signal Write              : std_logic;
+
+	signal really_rdy         : std_logic;
+	signal R_W_n_i            : std_logic;
+
+begin
+	-- ehenciak : gate Rdy with read/write to make an "OK, it's
+	--            really OK to stop the processor now if Rdy is
+	--            deasserted" signal
+	really_rdy <= Rdy or not(R_W_n_i);
+
+	-- ehenciak : Drive R_W_n_i off chip.
+	R_W_n      <= R_W_n_i;
+
+	Sync <= '1' when MCycle = "000" else '0';
+	EF <= EF_i;
+	MF <= MF_i;
+	XF <= XF_i;
+	ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
+	VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
+	VDA <= '1' when Set_Addr_To_r /= "00" else '0';             -- Incorrect !!!!!!!!!!!!
+	VPA <= '1' when Jump(1) = '0' else '0';                     -- Incorrect !!!!!!!!!!!!
+
+	mcode : T65_MCode
+		port map(
+			Mode        => Mode_r,
+			IR          => IR,
+			MCycle      => MCycle,
+			P           => P,
+			LCycle      => LCycle,
+			ALU_Op      => ALU_Op,
+			Set_BusA_To => Set_BusA_To,
+			Set_Addr_To => Set_Addr_To,
+			Write_Data  => Write_Data,
+			Jump        => Jump,
+			BAAdd       => BAAdd,
+			BreakAtNA   => BreakAtNA,
+			ADAdd       => ADAdd,
+			AddY        => AddY,
+			PCAdd       => PCAdd,
+			Inc_S       => Inc_S,
+			Dec_S       => Dec_S,
+			LDA         => LDA,
+			LDP         => LDP,
+			LDX         => LDX,
+			LDY         => LDY,
+			LDS         => LDS,
+			LDDI        => LDDI,
+			LDALU       => LDALU,
+			LDAD        => LDAD,
+			LDBAL       => LDBAL,
+			LDBAH       => LDBAH,
+			SaveP       => SaveP,
+			Write       => Write
+			);
+
+	alu : T65_ALU
+		port map(
+			Mode => Mode_r,
+			Op => ALU_Op_r,
+			BusA => BusA_r,
+			BusB => BusB,
+			P_In => P,
+			P_Out => P_Out,
+			Q => ALU_Q
+			);
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			IR <= "00000000";
+			S <= (others => '0');       -- Dummy !!!!!!!!!!!!!!!!!!!!!
+			D <= (others => '0');
+			PBR <= (others => '0');
+			DBR <= (others => '0');
+
+			Mode_r <= (others => '0');
+			ALU_Op_r <= "1100";
+			Write_Data_r <= "000";
+			Set_Addr_To_r <= "00";
+
+			R_W_n_i <= '1';
+			EF_i <= '1';
+			MF_i <= '1';
+			XF_i <= '1';
+
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				R_W_n_i <= not Write or RstCycle;
+
+				D <= (others => '1');   -- Dummy
+				PBR <= (others => '1'); -- Dummy
+				DBR <= (others => '1'); -- Dummy
+				EF_i <= '0';    -- Dummy
+				MF_i <= '0';    -- Dummy
+				XF_i <= '0';    -- Dummy
+
+				if MCycle  = "000" then
+					Mode_r <= Mode;
+
+					if IRQCycle = '0' and NMICycle = '0' then
+						PC <= PC + 1;
+					end if;
+
+					if IRQCycle = '1' or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DI;
+					end if;
+				end if;
+
+				ALU_Op_r <= ALU_Op;
+				Write_Data_r <= Write_Data;
+				if Break = '1' then
+					Set_Addr_To_r <= "00";
+				else
+					Set_Addr_To_r <= Set_Addr_To;
+				end if;
+
+				if Inc_S = '1' then
+					S <= S + 1;
+				end if;
+				if Dec_S = '1' and RstCycle = '0' then
+					S <= S - 1;
+				end if;
+				if LDS = '1' then
+					S(7 downto 0) <= unsigned(ALU_Q);
+				end if;
+
+				if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
+					PC <= PC + 1;
+				end if;
+				--
+				-- jump control logic
+				--
+				case Jump is
+				  when "01" =>
+					  PC <= PC + 1;
+
+				  when "10" =>
+					  PC <= unsigned(DI & DL);
+
+				  when "11" =>
+					  if PCAdder(8) = '1' then
+						  if DL(7) = '0' then
+							  PC(15 downto 8) <= PC(15 downto 8) + 1;
+						  else
+							  PC(15 downto 8) <= PC(15 downto 8) - 1;
+						  end if;
+					  end if;
+					  PC(7 downto 0) <= PCAdder(7 downto 0);
+
+				  when others => null;
+				end case;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+	PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
+			   else "0" & PC(7 downto 0);
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				if MCycle = "000" then
+					if LDA = '1' then
+						ABC(7 downto 0) <= ALU_Q;
+					end if;
+					if LDX = '1' then
+						X(7 downto 0) <= ALU_Q;
+					end if;
+					if LDY = '1' then
+						Y(7 downto 0) <= ALU_Q;
+					end if;
+					if (LDA or LDX or LDY) = '1' then
+						P <= P_Out;
+					end if;
+				end if;
+				if SaveP = '1' then
+					P <= P_Out;
+				end if;
+				if LDP = '1' then
+					P <= ALU_Q;
+				end if;
+				if IR(4 downto 0) = "11000" then
+					case IR(7 downto 5) is
+					when "000" =>
+						P(Flag_C) <= '0';
+					when "001" =>
+						P(Flag_C) <= '1';
+					when "010" =>
+						P(Flag_I) <= '0';
+					when "011" =>
+						P(Flag_I) <= '1';
+					when "101" =>
+						P(Flag_V) <= '0';
+					when "110" =>
+						P(Flag_D) <= '0';
+					when "111" =>
+						P(Flag_D) <= '1';
+					when others =>
+					end case;
+				end if;
+
+				--if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
+				--	P(Flag_B) <= '1';
+				--end if;
+				--if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1')  then
+				--	P(Flag_I) <= '1';
+				--	P(Flag_B) <= B_o;
+				--end if;
+
+        -- B=1 always on the 6502
+				P(Flag_B) <= '1';
+				if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
+          if MCycle = "011" then
+            -- B=0 in *copy* of P pushed onto the stack
+            P(Flag_B) <= '0';
+          elsif MCycle = "100" then
+            P(Flag_I) <= '1';
+          end if;
+				end if;
+
+				if SO_n_o = '1' and SO_n = '0' then
+					P(Flag_V) <= '1';
+				end if;
+				if RstCycle = '1' and Mode_r /= "00" then
+					P(Flag_1) <= '1';
+					P(Flag_D) <= '0';
+					P(Flag_I) <= '1';
+				end if;
+				P(Flag_1) <= '1';
+
+				B_o     <= P(Flag_B);
+				SO_n_o <= SO_n;
+				IRQ_n_o <= IRQ_n;
+				NMI_n_o <= NMI_n;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			BusA_r <= (others => '0');
+			BusB <= (others => '0');
+			AD <= (others => '0');
+			BAL <= (others => '0');
+			BAH <= (others => '0');
+			DL <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (Rdy = '1') then
+				BusA_r <= BusA;
+				BusB <= DI;
+
+				case BAAdd is
+				when "01" =>
+					-- BA Inc
+					AD <= std_logic_vector(unsigned(AD) + 1);
+					BAL <= std_logic_vector(unsigned(BAL) + 1);
+				when "10" =>
+					-- BA Add
+					BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
+				when "11" =>
+					-- BA Adj
+					if BAL(8) = '1' then
+						BAH <= std_logic_vector(unsigned(BAH) + 1);
+					end if;
+				when others =>
+				end case;
+
+				-- ehenciak : modified to use Y register as well (bugfix)
+				if ADAdd = '1' then
+				  if (AddY = '1') then
+					AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
+				  else
+					AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
+				  end if;
+				end if;
+
+				if IR = "00000000" then
+					BAL <= (others => '1');
+					BAH <= (others => '1');
+					if RstCycle = '1' then
+						BAL(2 downto 0) <= "100";
+					elsif NMICycle = '1' then
+						BAL(2 downto 0) <= "010";
+					else
+						BAL(2 downto 0) <= "110";
+					end if;
+					if Set_addr_To_r = "11" then
+						BAL(0) <= '1';
+					end if;
+				end if;
+
+
+				if LDDI = '1' then
+					DL <= DI;
+				end if;
+				if LDALU = '1' then
+					DL <= ALU_Q;
+				end if;
+				if LDAD = '1' then
+					AD <= DI;
+				end if;
+				if LDBAL = '1' then
+					BAL(7 downto 0) <= DI;
+				end if;
+				if LDBAH = '1' then
+					BAH <= DI;
+				end if;
+			end if;
+		end if;
+	  end if;
+	end process;
+
+	Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
+
+
+	with Set_BusA_To select
+		BusA <= DI when "000",
+			ABC(7 downto 0) when "001",
+			X(7 downto 0) when "010",
+			Y(7 downto 0) when "011",
+			std_logic_vector(S(7 downto 0)) when "100",
+			P when "101",
+			(others => '-') when others;
+
+	with Set_Addr_To_r select
+		A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
+			DBR & "00000000" & AD when "10",
+			"00000000" & BAH & BAL(7 downto 0) when "11",
+			PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
+
+	with Write_Data_r select
+		DO <= DL when "000",
+			ABC(7 downto 0) when "001",
+			X(7 downto 0) when "010",
+			Y(7 downto 0) when "011",
+			std_logic_vector(S(7 downto 0)) when "100",
+			P when "101",
+			std_logic_vector(PC(7 downto 0)) when "110",
+			std_logic_vector(PC(15 downto 8)) when others;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			MCycle <= "001";
+			RstCycle <= '1';
+			IRQCycle <= '0';
+			NMICycle <= '0';
+			NMIAct <= '0';
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				if MCycle = LCycle or Break = '1' then
+					MCycle <= "000";
+					RstCycle <= '0';
+					IRQCycle <= '0';
+					NMICycle <= '0';
+					if NMIAct = '1' then
+						NMICycle <= '1';
+					elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
+						IRQCycle <= '1';
+					end if;
+				else
+					MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+				end if;
+
+				if NMICycle = '1' then
+					NMIAct <= '0';
+				end if;
+				if NMI_n_o = '1' and NMI_n = '0' then
+					NMIAct <= '1';
+				end if;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_ALU.vhd
new file mode 100644
index 00000000..b1f6d632
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_ALU.vhd	
@@ -0,0 +1,260 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 6502 compatible microprocessor core
+--
+-- Version : 0245
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0245 : First version
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T65_Pack.all;
+
+entity T65_ALU is
+	port(
+		Mode    : in std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		Op      : in std_logic_vector(3 downto 0);
+		BusA    : in std_logic_vector(7 downto 0);
+		BusB    : in std_logic_vector(7 downto 0);
+		P_In    : in std_logic_vector(7 downto 0);
+		P_Out   : out std_logic_vector(7 downto 0);
+		Q       : out std_logic_vector(7 downto 0)
+	);
+end T65_ALU;
+
+architecture rtl of T65_ALU is
+
+	-- AddSub variables (temporary signals)
+	signal      ADC_Z           : std_logic;
+	signal      ADC_C           : std_logic;
+	signal      ADC_V           : std_logic;
+	signal      ADC_N           : std_logic;
+	signal      ADC_Q           : std_logic_vector(7 downto 0);
+	signal      SBC_Z           : std_logic;
+	signal      SBC_C           : std_logic;
+	signal      SBC_V           : std_logic;
+	signal      SBC_N           : std_logic;
+	signal      SBC_Q           : std_logic_vector(7 downto 0);
+
+begin
+
+	process (P_In, BusA, BusB)
+		variable AL : unsigned(6 downto 0);
+		variable AH : unsigned(6 downto 0);
+		variable C : std_logic;
+	begin
+		AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
+		AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+			ADC_Z <= '1';
+		else
+			ADC_Z <= '0';
+		end if;
+
+		if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+			AL(6 downto 1) := AL(6 downto 1) + 6;
+		end if;
+
+		C := AL(6) or AL(5);
+		AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+		ADC_N <= AH(4);
+		ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+		if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+			AH(6 downto 1) := AH(6 downto 1) + 6;
+		end if;
+
+		ADC_C <= AH(6) or AH(5);
+
+		ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+	end process;
+
+	process (Op, P_In, BusA, BusB)
+		variable AL : unsigned(6 downto 0);
+		variable AH : unsigned(5 downto 0);
+		variable C : std_logic;
+	begin
+		C := P_In(Flag_C) or not Op(0);
+		AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
+		AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+			if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
+-- pragma translate_on
+
+		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+			SBC_Z <= '1';
+		else
+			SBC_Z <= '0';
+		end if;
+
+		SBC_C <= not AH(5);
+		SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
+		SBC_N <= AH(4);
+
+		if P_In(Flag_D) = '1' then
+			if AL(5) = '1' then
+				AL(5 downto 1) := AL(5 downto 1) - 6;
+			end if;
+			AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
+			if AH(5) = '1' then
+				AH(5 downto 1) := AH(5 downto 1) - 6;
+			end if;
+		end if;
+
+		SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+	end process;
+
+	process (Op, P_In, BusA, BusB,
+			ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
+			SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
+		variable Q_t : std_logic_vector(7 downto 0);
+	begin
+		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
+		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
+		P_Out <= P_In;
+		Q_t := BusA;
+		case Op(3 downto 0) is
+		when "0000" =>
+			-- ORA
+			Q_t := BusA or BusB;
+		when "0001" =>
+			-- AND
+			Q_t := BusA and BusB;
+		when "0010" =>
+			-- EOR
+			Q_t := BusA xor BusB;
+		when "0011" =>
+			-- ADC
+			P_Out(Flag_V) <= ADC_V;
+			P_Out(Flag_C) <= ADC_C;
+			Q_t := ADC_Q;
+		when "0101" | "1101" =>
+			-- LDA
+		when "0110" =>
+			-- CMP
+			P_Out(Flag_C) <= SBC_C;
+		when "0111" =>
+			-- SBC
+			P_Out(Flag_V) <= SBC_V;
+			P_Out(Flag_C) <= SBC_C;
+			Q_t := SBC_Q;
+		when "1000" =>
+			-- ASL
+			Q_t := BusA(6 downto 0) & "0";
+			P_Out(Flag_C) <= BusA(7);
+		when "1001" =>
+			-- ROL
+			Q_t := BusA(6 downto 0) & P_In(Flag_C);
+			P_Out(Flag_C) <= BusA(7);
+		when "1010" =>
+			-- LSR
+			Q_t := "0" & BusA(7 downto 1);
+			P_Out(Flag_C) <= BusA(0);
+		when "1011" =>
+			-- ROR
+			Q_t := P_In(Flag_C) & BusA(7 downto 1);
+			P_Out(Flag_C) <= BusA(0);
+		when "1100" =>
+			-- BIT
+			P_Out(Flag_V) <= BusB(6);
+		when "1110" =>
+			-- DEC
+			Q_t := std_logic_vector(unsigned(BusA) - 1);
+		when "1111" =>
+			-- INC
+			Q_t := std_logic_vector(unsigned(BusA) + 1);
+		when others =>
+		end case;
+
+		case Op(3 downto 0) is
+		when "0011" =>
+			P_Out(Flag_N) <= ADC_N;
+			P_Out(Flag_Z) <= ADC_Z;
+		when "0110" | "0111" =>
+			P_Out(Flag_N) <= SBC_N;
+			P_Out(Flag_Z) <= SBC_Z;
+		when "0100" =>
+		when "1100" =>
+			P_Out(Flag_N) <= BusB(7);
+			if (BusA and BusB) = "00000000" then
+				P_Out(Flag_Z) <= '1';
+			else
+				P_Out(Flag_Z) <= '0';
+			end if;
+		when others =>
+			P_Out(Flag_N) <= Q_t(7);
+			if Q_t = "00000000" then
+				P_Out(Flag_Z) <= '1';
+			else
+				P_Out(Flag_Z) <= '0';
+			end if;
+		end case;
+
+		Q <= Q_t;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_MCode.vhd
new file mode 100644
index 00000000..6c6c864a
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_MCode.vhd	
@@ -0,0 +1,1052 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 302 minor timing fixes
+-- Ver 301 Jump timing fixed
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246 + fix
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- 65C02
+-- supported : inc, dec, phx, plx, phy, ply
+-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
+--
+-- File history :
+--
+--      0246 : First release
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T65_Pack.all;
+
+entity T65_MCode is
+	port(
+		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		IR                      : in  std_logic_vector(7 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		P                       : in  std_logic_vector(7 downto 0);
+		LCycle                  : out std_logic_vector(2 downto 0);
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
+		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
+		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
+		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
+		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
+		BreakAtNA               : out std_logic;
+		ADAdd                   : out std_logic;
+		AddY                    : out std_logic;
+		PCAdd                   : out std_logic;
+		Inc_S                   : out std_logic;
+		Dec_S                   : out std_logic;
+		LDA                     : out std_logic;
+		LDP                     : out std_logic;
+		LDX                     : out std_logic;
+		LDY                     : out std_logic;
+		LDS                     : out std_logic;
+		LDDI                    : out std_logic;
+		LDALU                   : out std_logic;
+		LDAD                    : out std_logic;
+		LDBAL                   : out std_logic;
+		LDBAH                   : out std_logic;
+		SaveP                   : out std_logic;
+		Write                   : out std_logic
+	);
+end T65_MCode;
+
+architecture rtl of T65_MCode is
+
+	signal Branch : std_logic;
+
+begin
+
+	with IR(7 downto 5) select
+		Branch <= not P(Flag_N) when "000",
+					  P(Flag_N) when "001",
+				  not P(Flag_V) when "010",
+					  P(Flag_V) when "011",
+				  not P(Flag_C) when "100",
+					  P(Flag_C) when "101",
+				  not P(Flag_Z) when "110",
+					  P(Flag_Z) when others;
+
+	process (IR, MCycle, P, Branch, Mode)
+	begin
+		LCycle      <= "001";
+		Set_BusA_To <= "001"; -- A
+		Set_Addr_To <= (others => '0');
+		Write_Data  <= (others => '0');
+		Jump        <= (others => '0');
+		BAAdd       <= "00";
+		BreakAtNA   <= '0';
+		ADAdd       <= '0';
+		PCAdd       <= '0';
+		Inc_S       <= '0';
+		Dec_S       <= '0';
+		LDA         <= '0';
+		LDP         <= '0';
+		LDX         <= '0';
+		LDY         <= '0';
+		LDS         <= '0';
+		LDDI        <= '0';
+		LDALU       <= '0';
+		LDAD        <= '0';
+		LDBAL       <= '0';
+		LDBAH       <= '0';
+		SaveP       <= '0';
+		Write       <= '0';
+		AddY        <= '0';
+
+		case IR(7 downto 5) is
+		when "100" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				Set_BusA_To <= "011"; -- Y
+				Write_Data <= "011"; -- Y
+			when "10" =>
+				Set_BusA_To <= "010"; -- X
+				Write_Data <= "010"; -- X
+			when others =>
+				Write_Data <= "001"; -- A
+			end case;
+		--}}}
+		when "101" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) /= '1' or IR(2) /= '0' then
+					LDY <= '1';
+				end if;
+			when "10" =>
+				LDX <= '1';
+			when others =>
+				LDA <= '1';
+			end case;
+			Set_BusA_To <= "000"; -- DI
+		--}}}
+		when "110" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) = '0' then
+					LDY <= '1';
+				end if;
+				Set_BusA_To <= "011"; -- Y
+			when others =>
+				Set_BusA_To <= "001"; -- A
+			end case;
+		--}}}
+		when "111" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) = '0' then
+					LDX <= '1';
+				end if;
+				Set_BusA_To <= "010"; -- X
+			when others =>
+				Set_BusA_To <= "001"; -- A
+			end case;
+		--}}}
+		when others =>
+		end case;
+
+		if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+			Set_BusA_To <= "000"; -- DI
+		end if;
+
+		case IR(4 downto 0) is
+		when "00000" | "01000" | "01010" | "11000" | "11010" =>
+		--{{{
+			-- Implied
+			case IR is
+			when "00000000" =>
+				-- BRK
+				LCycle <= "110";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "111"; -- PCH
+					Write <= '1';
+				when 2 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "110"; -- PCL
+					Write <= '1';
+				when 3 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "101"; -- P
+					Write <= '1';
+				when 4 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					LDDI <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 6 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "00100000" =>
+				-- JSR
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "111"; -- PCH
+					Write <= '1';
+				when 3 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "110"; -- PCL
+					Write <= '1';
+				when 4 =>
+					Dec_S <= '1';
+				when 5 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "01000000" =>
+				-- RTI
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Set_BusA_To <= "000"; -- DI
+				when 4 =>
+					LDP <= '1';
+					Inc_S <= '1';
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 5 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "01100000" =>
+				-- RTS
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Inc_S <= '1';
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 4 =>
+					Jump <= "10"; -- DIDL
+				when 5 =>
+					Jump <= "01";
+				when others =>
+				end case;
+			when "00001000" | "01001000" | "01011010" | "11011010" =>
+				-- PHP, PHA, PHY*, PHX*
+				LCycle <= "010";
+				if Mode = "00" and IR(1) = '1' then
+					LCycle <= "001";
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					case IR(7 downto 4) is
+					when "0000" =>
+						Write_Data <= "101"; -- P
+					when "0100" =>
+						Write_Data <= "001"; -- A
+					when "0101" =>
+						Write_Data <= "011"; -- Y
+					when "1101" =>
+						Write_Data <= "010"; -- X
+					when others =>
+					end case;
+					Write <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Dec_S <= '1';
+				when others =>
+				end case;
+			when "00101000" | "01101000" | "01111010" | "11111010" =>
+				-- PLP, PLA, PLY*, PLX*
+				LCycle <= "011";
+				if Mode = "00" and IR(1) = '1' then
+					LCycle <= "001";
+				end if;
+				case IR(7 downto 4) is
+				when "0010" =>
+					LDP <= '1';
+				when "0110" =>
+					LDA <= '1';
+				when "0111" =>
+					if Mode /= "00" then
+						LDY <= '1';
+					end if;
+				when "1111" =>
+					if Mode /= "00" then
+						LDX <= '1';
+					end if;
+				when others =>
+				end case;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					SaveP <= '1';
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Set_BusA_To <= "000"; -- DI
+				when others =>
+				end case;
+			when "10100000" | "11000000" | "11100000" =>
+				-- LDY, CPY, CPX
+				-- Immediate
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+				when others =>
+				end case;
+			when "10001000" =>
+				-- DEY
+				LDY <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "011"; -- Y
+				when others =>
+				end case;
+			when "11001010" =>
+				-- DEX
+				LDX <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "010"; -- X
+				when others =>
+				end case;
+			when "00011010" | "00111010" =>
+				-- INC*, DEC*
+				if Mode /= "00" then
+					LDA <= '1'; -- A
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "100"; -- S
+				when others =>
+				end case;
+			when "00001010" | "00101010" | "01001010" | "01101010" =>
+				-- ASL, ROL, LSR, ROR
+				LDA <= '1'; -- A
+				Set_BusA_To <= "001"; -- A
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+				when others =>
+				end case;
+			when "10001010" | "10011000" =>
+				-- TYA, TXA
+				LDA <= '1'; -- A
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+				when others =>
+				end case;
+			when "10101010" | "10101000" =>
+				-- TAX, TAY
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "001"; -- A
+				when others =>
+				end case;
+			when "10011010" =>
+				-- TXS
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					LDS <= '1';
+				when 1 =>
+				when others =>
+				end case;
+			when "10111010" =>
+				-- TSX
+				LDX <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "100"; -- S
+				when others =>
+				end case;
+
+		--                      when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" =>
+		--                              -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX
+		--                              case to_integer(unsigned(MCycle)) is
+		--                              when 1 =>
+		--                              when others =>
+		--                              end case;
+			when others =>
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when others =>
+				end case;
+			end case;
+		--}}}
+
+		when "00001" | "00011" =>
+		--{{{
+			-- Zero Page Indexed Indirect (d,x)
+			LCycle <= "101";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+				ADAdd <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 3 =>
+				BAAdd <= "01";  -- DB Inc
+				LDBAL <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 4 =>
+				LDBAH <= '1';
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 5 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "01001" | "01011" =>
+		--{{{
+			-- Immediate
+			LDA <= '1';
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+			when others =>
+			end case;
+
+		--}}}
+
+		when "00010" | "10010" =>
+		--{{{
+			-- Immediate, KIL
+			LDX <= '1';
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				if IR = "10100010" then
+					-- LDX
+					Jump <= "01";
+				else
+					-- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+				end if;
+			when others =>
+			end case;
+		--}}}
+
+		when "00100" =>
+		--{{{
+			-- Zero Page
+			LCycle <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+				if IR(7 downto 5) = "001" then
+					SaveP <= '1';
+				end if;
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				end if;
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "00101" | "00110" | "00111" =>
+		--{{{
+			-- Zero Page
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 3 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 4 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "010";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "01100" =>
+		--{{{
+			-- Absolute
+			if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then
+				-- JMP
+				if IR(5) = '0' then
+					--LCycle <= "011";
+					LCycle <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Jump <= "01";
+						LDDI <= '1';
+					when 2 =>
+						Jump <= "10"; -- DIDL
+					when others =>
+					end case;
+				else
+					--LCycle <= "101";
+					LCycle <= "100"; -- mikej
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Jump <= "01";
+						LDDI <= '1';
+						LDBAL <= '1';
+					when 2 =>
+						LDBAH <= '1';
+						if Mode /= "00" then
+							Jump <= "10"; -- DIDL
+						end if;
+						if Mode = "00" then
+							Set_Addr_To <= "11"; -- BA
+						end if;
+					when 3 =>
+						LDDI <= '1';
+						if Mode = "00" then
+							Set_Addr_To <= "11"; -- BA
+							BAAdd <= "01";      -- DB Inc
+						else
+							Jump <= "01";
+						end if;
+					when 4 =>
+						Jump <= "10"; -- DIDL
+					when others =>
+					end case;
+				end if;
+			else
+				LCycle <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					if IR(7 downto 5) = "001" then
+						SaveP <= '1';
+					end if;
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "01101" | "01110" | "01111" =>
+		--{{{
+			-- Absolute
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+					Write <= '1';
+					LDALU <= '1';
+					SaveP <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					SaveP <= '0'; -- MIKEJ was 1
+				when others =>
+				end case;
+			else
+				LCycle <= "011";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "10000" =>
+		--{{{
+			-- Relative
+
+						-- This circuit dictates when the last
+						-- microcycle occurs for the branch depending on
+						-- whether or not the branch is taken and if a page
+						-- is crossed...
+			if (Branch = '1') then
+
+							 LCycle <= "011"; -- We're done @ T3 if branching...upper
+											  -- level logic will stop at T2 if no page cross
+											  -- (See the Break signal)
+			else
+
+							 LCycle <= "001";
+
+			end if;
+
+						-- This decodes the current microcycle and takes the
+						-- proper course of action...
+			case to_integer(unsigned(MCycle)) is
+
+							-- On the T1 microcycle, increment the program counter
+							-- and instruct the upper level logic to fetch the offset
+							-- from the Din bus and store it in the data latches. This
+							-- will be the last microcycle if the branch isn't taken.
+				when 1 =>
+
+					Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
+											  -- from microcycle T0.
+
+				LDDI <= '1';  -- Tells logic in top level (T65.vhd) to route
+											  -- the Din bus to the memory data latch (DL)
+											  -- so that the branch offset is fetched.
+
+							-- In microcycle T2, tell the logic in the top level to
+							-- add the offset.  If the most significant byte of the
+							-- program counter (i.e. the current "page") does not need
+							-- updating, we are done here...the Break signal at the
+							-- T65.vhd level takes care of that...
+				when 2 =>
+
+				Jump    <= "11"; -- Tell the PC Jump logic to use relative mode.
+
+				PCAdd   <= '1';  -- This tells the PC adder to update itself with
+												 -- the current offset recently fetched from
+												 -- memory.
+
+							-- The following is microcycle T3 :
+							-- The program counter should be completely updated
+							-- on this cycle after the page cross is detected.
+							-- We don't need to do anything here...
+				when 3 =>
+
+
+				when others => null; -- Do nothing.
+
+			end case;
+		--}}}
+
+		when "10001" | "10011" =>
+		--{{{
+			-- Zero Page Indirect Indexed (d),y
+			LCycle <= "101";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+				LDBAL <= '1';
+				BAAdd <= "01";  -- DB Inc
+				Set_Addr_To <= "10"; -- AD
+			when 3 =>
+				Set_BusA_To <= "011"; -- Y
+				BAAdd <= "10";  -- BA Add
+				LDBAH <= '1';
+				Set_Addr_To <= "11"; -- BA
+			when 4 =>
+				BAAdd <= "11";  -- BA Adj
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				else
+					BreakAtNA <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 5 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "10100" | "10101" | "10110" | "10111" =>
+		--{{{
+			-- Zero Page, X
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					ADAdd <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 3 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 4 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 5 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "011";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					ADAdd <= '1';
+					-- Added this check for Y reg. use...
+					if (IR(3 downto 0) = "0110") then
+					  AddY <= '1';
+					end if;
+
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "10"; -- AD
+				when 3 => null;
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "11001" | "11011" =>
+		--{{{
+			-- Absolute Y
+			LCycle <= "100";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDBAL <= '1';
+			when 2 =>
+				Jump <= "01";
+				Set_BusA_To <= "011"; -- Y
+				BAAdd <= "10";  -- BA Add
+				LDBAH <= '1';
+				Set_Addr_To <= "11"; -- BA
+			when 3 =>
+				BAAdd <= "11";  -- BA adj
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				else
+					BreakAtNA <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 4 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "11100" | "11101" | "11110" | "11111" =>
+		--{{{
+			-- Absolute X
+
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "110";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					Set_BusA_To <= "010"; -- X
+					BAAdd <= "10";      -- BA Add
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					BAAdd <= "11";      -- BA adj
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 6 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "100";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					-- mikej
+					-- special case 0xBE which uses Y reg as index!!
+					if (IR = "10111110") then
+					  Set_BusA_To <= "011"; -- Y
+					else
+					  Set_BusA_To <= "010"; -- X
+					end if;
+					BAAdd <= "10";      -- BA Add
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					BAAdd <= "11";      -- BA adj
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					else
+						BreakAtNA <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+		when others =>
+		end case;
+	end process;
+
+	process (IR, MCycle)
+	begin
+		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
+		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
+		case IR(1 downto 0) is
+		when "00" =>
+		--{{{
+			case IR(4 downto 2) is
+			when "000" | "001" | "011" =>
+				case IR(7 downto 5) is
+				when "110" | "111" =>
+					-- CP
+					ALU_Op <= "0110";
+				when "101" =>
+					-- LD
+					ALU_Op <= "0101";
+				when "001" =>
+					-- BIT
+					ALU_Op <= "1100";
+				when others =>
+					-- NOP/ST
+					ALU_Op <= "0100";
+				end case;
+			when "010" =>
+				case IR(7 downto 5) is
+				when "111" | "110" =>
+					-- IN
+					ALU_Op <= "1111";
+				when "100" =>
+					-- DEY
+					ALU_Op <= "1110";
+				when others =>
+					-- LD
+					ALU_Op <= "1101";
+				end case;
+			when "110" =>
+				case IR(7 downto 5) is
+				when "100" =>
+					-- TYA
+					ALU_Op <= "1101";
+				when others =>
+					ALU_Op <= "----";
+				end case;
+			when others =>
+				case IR(7 downto 5) is
+				when "101" =>
+					-- LD
+					ALU_Op <= "1101";
+				when others =>
+					ALU_Op <= "0100";
+				end case;
+			end case;
+		--}}}
+		when "01" => -- OR
+		--{{{
+			ALU_Op(3) <= '0';
+			ALU_Op(2 downto 0) <= IR(7 downto 5);
+		--}}}
+		when "10" =>
+		--{{{
+			ALU_Op(3) <= '1';
+			ALU_Op(2 downto 0) <= IR(7 downto 5);
+			case IR(7 downto 5) is
+			when "000" =>
+				if IR(4 downto 2) = "110" then
+					-- INC
+					ALU_Op <= "1111";
+				end if;
+			when "001" =>
+				if IR(4 downto 2) = "110" then
+					-- DEC
+					ALU_Op <= "1110";
+				end if;
+			when "100" =>
+				if IR(4 downto 2) = "010" then
+					-- TXA
+					ALU_Op <= "0101";
+				else
+					ALU_Op <= "0100";
+				end if;
+			when others =>
+			end case;
+		--}}}
+		when others =>
+		--{{{
+			case IR(7 downto 5) is
+			when "100" =>
+				ALU_Op <= "0100";
+			when others =>
+				if MCycle = "000" then
+					ALU_Op(3) <= '0';
+					ALU_Op(2 downto 0) <= IR(7 downto 5);
+				else
+					ALU_Op(3) <= '1';
+					ALU_Op(2 downto 0) <= IR(7 downto 5);
+				end if;
+			end case;
+		--}}}
+		end case;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_Pack.vhd
new file mode 100644
index 00000000..e025e1bf
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/T65_Pack.vhd	
@@ -0,0 +1,117 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T65_Pack is
+
+	constant Flag_C : integer := 0;
+	constant Flag_Z : integer := 1;
+	constant Flag_I : integer := 2;
+	constant Flag_D : integer := 3;
+	constant Flag_B : integer := 4;
+	constant Flag_1 : integer := 5;
+	constant Flag_V : integer := 6;
+	constant Flag_N : integer := 7;
+
+	component T65_MCode
+	port(
+		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		IR                      : in  std_logic_vector(7 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		P                       : in  std_logic_vector(7 downto 0);
+		LCycle                  : out std_logic_vector(2 downto 0);
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
+		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
+		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
+		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
+		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
+		BreakAtNA               : out std_logic;
+		ADAdd                   : out std_logic;
+		AddY                    : out std_logic;
+		PCAdd                   : out std_logic;
+		Inc_S                   : out std_logic;
+		Dec_S                   : out std_logic;
+		LDA                     : out std_logic;
+		LDP                     : out std_logic;
+		LDX                     : out std_logic;
+		LDY                     : out std_logic;
+		LDS                     : out std_logic;
+		LDDI                    : out std_logic;
+		LDALU                   : out std_logic;
+		LDAD                    : out std_logic;
+		LDBAL                   : out std_logic;
+		LDBAH                   : out std_logic;
+		SaveP                   : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T65_ALU
+	port(
+		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+		Op      : in  std_logic_vector(3 downto 0);
+		BusA    : in  std_logic_vector(7 downto 0);
+		BusB    : in  std_logic_vector(7 downto 0);
+		P_In    : in  std_logic_vector(7 downto 0);
+		P_Out   : out std_logic_vector(7 downto 0);
+		Q       : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/addec_prom.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/addec_prom.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/greybox_tmp/cbx_args.txt b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/greybox_tmp/cbx_args.txt
new file mode 100644
index 00000000..deea9283
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/greybox_tmp/cbx_args.txt	
@@ -0,0 +1,16 @@
+ADDRESS_ACLR_A=NONE
+CLOCK_ENABLE_INPUT_A=BYPASS
+CLOCK_ENABLE_OUTPUT_A=BYPASS
+INIT_FILE=../roms/6400-01m2.hex
+INTENDED_DEVICE_FAMILY="Cyclone III"
+NUMWORDS_A=256
+OPERATION_MODE=ROM
+OUTDATA_ACLR_A=NONE
+OUTDATA_REG_A=UNREGISTERED
+WIDTHAD_A=8
+WIDTH_A=4
+WIDTH_BYTEENA_A=1
+DEVICE_FAMILY="Cyclone III"
+address_a
+clock0
+q_a
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/j6_prom.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/j6_prom.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/k6_prom.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/k6_prom.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom1.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom1.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom2.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom2.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom3.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom3.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom4.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/prog_rom4.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/ram1k_dp.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/ram1k_dp.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/sync_prom.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/T65/sync_prom.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/build_id.sv b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/build_id.sv
new file mode 100644
index 00000000..1d53a3f2
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/build_id.sv	
@@ -0,0 +1,2 @@
+`define BUILD_DATE "171221"
+`define BUILD_TIME "172231"
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/build_id.tcl b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..be673dac
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.sv"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/collision.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/collision.vhd
new file mode 100644
index 00000000..ec1d8dbb
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/collision.vhd	
@@ -0,0 +1,122 @@
+-- Collision detection logic for for Kee Games Sprint 2
+-- This is called the "Car/Playfield Comparator" in the manual and works by comparing the
+-- video signals representing player and computer cars, track boundaries and oil slicks generating 
+-- collision signals when multiple objects appear at the same time (location) in the video. 
+-- Car 1 and Car 2 are human players, Car 3 and Car 4 are computer controlled. 
+--
+-- NOTE: There is an error in the original schematic, F8 pin 5 should go to CAR1 (not inverted) and 
+-- F8 pin 9 to CAR2 (not inverted) while the schematic shows them connecting to the inverted signals
+-- 
+-- Tests for the following conditions:
+-- Car 1 equals Car 2
+-- Car 1 equals Car 3 or 4
+-- Car 2 equals Car 3 or 4
+-- Car 1 equals Black Playfield (Oil slick)
+-- Car 2 equals Black Playfield (Oil slick)
+-- Car 1 equals White Playfield (Track boundary)
+-- Car 2 equals White Playfield (Track boundary)
+--
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity collision_detect is 
+port(		
+			Clk6					: in	std_logic;
+			Car1					: in  std_logic;
+			Car1_n				: in  std_logic;
+			Car2					: in	std_logic;
+			Car2_n				: in	std_logic;
+			Car3_4_n				: in	std_logic;
+			WhitePF_n			: in  std_logic;
+			BlackPF_n			: in	std_logic;
+			CollRst1_n			: in  std_logic;
+			CollRst2_n			: in  std_logic;
+			Collisions1			: out std_logic_vector(1 downto 0);
+			Collisions2			: out std_logic_vector(1 downto 0)
+			);
+end collision_detect;
+
+architecture rtl of collision_detect is
+
+signal Col_latch_Q		: std_logic_vector(4 downto 1) := (others => '0');
+signal S1_n					: std_logic_vector(4 downto 1);
+signal S2_n					: std_logic_vector(4 downto 1);
+signal R_n					: std_logic_vector(4 downto 1);
+
+
+begin
+
+-- Tristate buffers at E5 and E6 route collision signals to data bus 7-6
+Collisions1 <= Col_latch_Q(2 downto 1);
+Collisions2 <= Col_latch_Q(4 downto 3);
+	
+-- 74LS279 quad SR latch at H6, all inputs are active low
+-- These should probably be written as synchronous latches
+H6: process(Clk6, S1_n, S2_n, R_n, Col_latch_Q)
+begin
+	if rising_edge(Clk6) then
+-- Units 1 and 3 each have an extra Set element
+-- Ordered from top to bottom as drawn in the schematic
+		if R_n(1) = '0' then
+			Col_latch_Q(1) <= '0';
+		elsif (S1_n(1) and S2_n(1)) = '0' then 
+			Col_latch_Q(1) <= '1';
+		else
+			Col_latch_Q(1) <= Col_latch_Q(1);
+		end if;
+		if R_n(2) = '0' then
+			Col_latch_Q(2) <= '0';
+		elsif S1_n(2) = '0' then 
+			Col_latch_Q(2) <= '1';
+		else
+			Col_latch_Q(2) <= Col_latch_Q(2);
+		end if;
+		if R_n(4) = '0' then
+			Col_latch_Q(4) <= '0';
+		elsif S1_n(4) = '0' then 
+			Col_latch_Q(4) <= '1';
+		else
+			Col_latch_Q(4) <= Col_latch_Q(4);
+		end if;
+		if R_n(3) = '0' then
+			Col_latch_Q(3) <= '0';
+		elsif (S1_n(3) and S2_n(3)) = '0' then 
+			Col_latch_Q(3) <= '1';
+		else
+			Col_latch_Q(3) <= Col_latch_Q(3);
+		end if;
+	end if;
+end process;	
+
+-- Glue logic	
+S2_n(1) <= BlackPF_n or Car1_n;
+S1_n(1) <= Car1 nand (Car2_n nand Car3_4_n);
+R_n(1) <= CollRst1_n; 
+
+R_n(2) <= CollRst1_n; 
+S1_n(2) <= Car1_n or WhitePF_n;
+
+R_n(4) <= CollRst2_n;
+S1_n(4) <= Car2_n or WhitePF_n; 
+
+S2_n(3) <= BlackPF_n or Car2_n;
+S1_n(3) <= Car2 nand (Car1_n nand Car3_4_n);
+R_n(3) <= CollRst2_n; 
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/cpu_mem.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/cpu_mem.vhd
new file mode 100644
index 00000000..8f4813d3
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/cpu_mem.vhd	
@@ -0,0 +1,436 @@
+-- CPU, RAM, ROM and address decoder for Kee Games Sprint 2
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity CPU_mem is 
+port(		
+			CLK12					: in  std_logic;
+			CLK6					: in  std_logic; -- 6MHz on schematic
+			Reset_n				: in  std_logic;
+			VCount				: in 	std_logic_vector(7 downto 0);
+			HCount				: in  std_logic_vector(8 downto 0);
+			Vblank_s				: in  std_logic; -- Vblank* on schematic
+			Vreset				: in 	std_logic;
+			Hsync_n				: in  std_logic;
+			Test_n				: in  std_logic;
+			Attract				: out std_logic;
+			Skid1					: out std_logic;
+			Skid2					: out std_logic;
+			NoiseReset_n		: out std_logic;
+			CollRst1_n			: out std_logic;
+			CollRst2_n			: out std_logic;
+			Lamp1					: out std_logic;
+			Lamp2					: out std_logic;
+			SteerRst1_n			: out std_logic;
+			SteerRst2_n			: out std_logic;
+			PHI1_O				: out std_logic;
+			PHI2_O				: out std_logic;
+			DISPLAY				: out	std_logic_vector(7 downto 0);
+			IO_Adr				: out std_logic_vector(9 downto 0);
+			Collisions1			: in  std_logic_vector(1 downto 0);
+			Collisions2			: in  std_logic_vector(1 downto 0);
+			Inputs				: in  std_logic_vector(1 downto 0)
+			);
+end CPU_mem;
+
+architecture rtl of CPU_mem is
+
+signal cpu_clk			: std_logic;
+signal PHI1				: std_logic;
+signal PHI2				: std_logic;
+signal Q5				: std_logic;
+signal Q6				: std_logic;
+signal A7_2				: std_logic;
+signal A7_5				: std_logic;
+signal A7_7				: std_logic;
+
+signal A8_6				: std_logic;
+
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H4				: std_logic;
+
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+
+signal IRQ_n			: std_logic;
+signal NMI_n			: std_logic;
+signal RW_n				: std_logic;
+signal RnW 				: std_logic;
+signal A					: std_logic_vector(15 downto 0);
+signal ADR				: std_logic_vector(9 downto 0);
+signal cpuDin			: std_logic_vector(7 downto 0);
+signal cpuDout			: std_logic_vector(7 downto 0);
+signal DBUS_n			: std_logic_vector(7 downto 0);
+signal DBUS				: std_logic_vector(7 downto 0);
+
+
+signal ROM1_dout		: std_logic_vector(7 downto 0);
+signal ROM2_dout		: std_logic_vector(7 downto 0);
+signal ROM3_dout		: std_logic_vector(7 downto 0);
+signal ROM4_dout		: std_logic_vector(7 downto 0);
+signal ROM_dout		: std_logic_vector(7 downto 0);
+
+signal ROM1				: std_logic;
+signal ROM2				: std_logic;
+signal ROM3				: std_logic;
+signal ROM4				: std_logic;
+signal ROM_ce			: std_logic;
+signal ROM_mux_in		: std_logic_vector(3 downto 0);
+
+signal cpuRAM_dout	: std_logic_vector(7 downto 0);
+signal Vram_dout		: std_logic_vector(7 downto 0);
+signal RAM_addr		: std_logic_vector(9 downto 0) := (others => '0');
+signal Vram_addr		: std_logic_vector(9 downto 0) := (others => '0');
+signal Scanbus			: std_logic_vector(9 downto 0) := (others => '0');
+signal RAM_dout		: std_logic_vector(7 downto 0);
+signal RAM_we			: std_logic := '0';
+signal RAM_RW_n 		: std_logic := '1';
+signal RAM_ce_n		: std_logic := '1';
+signal RAM_n			: std_logic := '1'; 
+signal WRAM				: std_logic := '0';
+signal WRITE_n			: std_logic := '1';
+
+signal F2_in			: std_logic_vector(3 downto 0) := "0000";
+signal F2_out			: std_logic_vector(9 downto 0) := "1111111111";
+signal D2_in			: std_logic_vector(3 downto 0) := "0000";
+signal D2_out			: std_logic_vector(9 downto 0) := "1111111111";
+signal E8_in			: std_logic_vector(3 downto 0) := "0000";
+signal E8_out			: std_logic_vector(9 downto 0) := "1111111111";
+signal P3_8				: std_logic := '0';
+
+signal Sync			   : std_logic := '0';
+signal Sync_n			: std_logic := '1';
+signal Switch_n		: std_logic := '1';
+signal Display_n		: std_logic := '1';
+signal Addec_bus		: std_logic_vector(7 downto 0);
+
+signal Timer_Reset_n	: std_logic := '1';
+signal Collision1_n	: std_logic := '1';
+signal Collision2_n	: std_logic := '1';
+
+signal J6_5				: std_logic := '0';
+signal J6_9				: std_logic := '0';
+
+signal Coin1			: std_logic := '0';
+signal Coin2			: std_logic := '0';
+signal Input_mux 		: std_logic := '0';
+signal A8_8				: std_logic := '0';
+signal H9_Q_n			: std_logic := '1';
+signal J9_out			: std_logic_vector(7 downto 0);
+signal H8_en			: std_logic := '0';
+signal Attract_int	: std_logic := '1';
+
+begin
+
+H8 <= HCount(3);
+H16 <=  HCount(4);
+H32 <= HCount(5);
+H64 <= HCount(6);
+H128 <= HCount(7);
+H256 <= HCount(8);
+H256_n <= (not HCount(8));
+
+V8 <= VCount(3);
+V16 <= VCount(4);
+V32 <= VCount(5);
+V64 <= VCount(6);
+V128 <= VCount(7);
+
+
+CPU: entity work.T65
+port map(
+		Enable => '1',
+		Mode => "00",
+		Res_n => reset_n,
+		Clk => phi1,
+		Rdy => '1',
+		Abort_n => '1',
+		IRQ_n => '1',
+		NMI_n => NMI_n,
+		SO_n => '1',
+		R_W_n => RW_n,
+		A(15 downto 0) => A,
+		DI => cpuDin,
+		DO => cpuDout
+		);
+		
+DBUS_n <= (not cpuDout); -- Data bus to video RAM is inverted
+ADR(9 downto 7) <= (A(9) or WRAM) & (A(8) or WRAM) & (A(7) or WRAM);
+ADR(6 downto 0) <= A(6 downto 0);
+RnW <= (not RW_n);
+IO_Adr <= Adr;
+
+NMI_n <= not (Vblank_s and Test_n);
+
+		
+-- CPU clock
+H4 <= Hcount(2);
+CPU_clock: process(clk12, H4, Q5, Q6)
+begin
+	if rising_edge(clk12) then
+		Q5 <= H4;
+		Q6 <= Q5;
+	end if;
+	phi1 <= not (Q5 or Q6); --?
+end process;
+
+PHI2 <= (not PHI1);
+PHI1_O <= PHI1;
+PHI2_O <= PHI2;
+
+	
+A8_6 <= not(RnW and PHI2 and H4 and WRITE_n);
+A7: process(clk12, A8_6) -- Shift register chain of 4 DFF's clocked by clk12, creates a delayed WRITE_n
+begin
+	if rising_edge(clk12) then
+		A7_2 <= A8_6;
+		A7_5 <= A7_2;
+		A7_7 <= A7_5;
+		WRITE_n <= A7_7;
+	end if;
+end process;
+		
+
+-- Program ROMs
+A1: entity work.prog_rom1
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom1_dout
+		);
+		
+C1: entity work.prog_rom2
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom2_dout
+		);
+
+D1: entity work.prog_rom3
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom3_dout
+		);
+
+E1: entity work.prog_rom4
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom4_dout
+		);
+
+-- ROM data mux
+ROM_mux_in <= (ROM1 & ROM2 & ROM3 & ROM4);
+ROM_mux: process(ROM_mux_in, rom1_dout, rom2_dout, rom3_dout, rom4_dout)
+begin
+	ROM_dout <= (others => '0');
+ case ROM_mux_in is
+ 	when "1000" => rom_dout <= rom1_dout;
+	when "0100" => rom_dout <= rom2_dout;
+	when "0010" => rom_dout <= rom3_dout;
+	when "0001" => rom_dout <= rom4_dout;
+	when others => null;
+ end case;
+end process;
+
+-- RAM 
+-- The original hardware multiplexes access to the RAM between the CPU and video hardware. In the FPGA it's
+-- easier to use dual-ported RAM
+RAM: entity work.ram1k_dp
+port map(
+	clock => clk6,
+-- CPU side	
+	address_a => adr(9 downto 0),
+	wren_a => ram_we,
+	data_a => DBUS_n,
+	q_a=> CPUram_dout,
+
+-- Video side
+	address_b => Vram_addr,
+	wren_b => '0',
+	data_b => x"FF",
+	q_b => Vram_dout
+	);
+
+Vram_addr <= (V128 or H256_n) & (V64 or H256_n) & (V32 or H256_n) & (V16 and H256) & 	(V8 and H256) & H128 & H64 & H32 & H16 & H8;
+
+-- Real hardware has both WE and CE which are selected by K2 according to the state of the phase 2 clock
+-- Altera block RAM has active high WE, original RAM had active low WE
+ram_we <= (not Write_n) and (not Display_n) and Phi2;
+	
+-- Rising edge of phi2 clock latches inverted output of VRAM data bus 	
+F5: process(phi2)
+begin
+	if rising_edge(phi2) then
+		display <= not Vram_dout;
+	end if;
+end process;
+
+	
+-- Address decoder
+-- A15 and A14 are not used
+-- Original circuit uses a bipolar PROM in the address decoder, this could be replaced with combinational logic
+
+-- E2 PROM 
+E2: entity work.addec_prom
+port map(
+	clock => clk12,
+	address => A(13 downto 9),
+	q => addec_bus
+	);
+
+F2_in <= addec_bus(0) & addec_bus(1) & addec_bus(2) & addec_bus(3);	
+WRAM <= addec_bus(4);
+D2_in <= RnW & addec_bus(5) & addec_bus(6) & addec_bus(7);
+	
+-- Decoder code could be cleaned up a bit, unused decoder states are not explicitly implemented
+F2: process(F2_in)
+begin
+	case F2_in is
+      when "0000" =>
+         F2_out <= "1111111110";
+      when "0001" =>
+         F2_out <= "1111111101";
+      when "0010" =>
+         F2_out <= "1111111011";
+      when "0011" =>
+         F2_out <= "1111110111";
+      when "0100" =>
+         F2_out <= "1111101111";
+      when "0101" =>
+         F2_out <= "1111011111";
+      when "0110" =>
+         F2_out <= "1110111111";
+      when "0111" =>
+         F2_out <= "1101111111";
+      when others =>
+         F2_out <= "1111111111";
+      end case;
+end process;
+
+ROM1 <= (F2_out(0) nand F2_out(1));
+ROM2 <= (F2_out(2) nand F2_out(3));
+ROM3 <= (F2_out(4) nand F2_out(5));
+ROM4 <= (F2_out(6) nand F2_out(7));
+ROM_ce <= (ROM1 or ROM2 or ROM3 or ROM4);
+
+D2: process(D2_in)
+begin
+	case D2_in is
+		when "0000" =>
+         D2_out <= "1111111110";
+		when "0001" =>
+         D2_out <= "1111111101";
+      when "0010" =>
+         D2_out <= "1111111011";
+      when "0011" =>
+         D2_out <= "1111110111";
+      when "0100" =>
+         D2_out <= "1111101111";
+      when "1000" =>
+         D2_out <= "1011111111";
+      when "1001" =>
+         D2_out <= "0111111111";
+      when others =>
+         D2_out <= "1111111111";
+      end case;
+end process;	
+
+RAM_n <= D2_out(0);
+SYNC_n <= D2_out(1);
+SYNC <= (not SYNC_n);
+SWITCH_n <= D2_out(2);
+COLLISION1_n <= D2_out(3);
+COLLISION2_n <= D2_out(4);
+DISPLAY_n <= (D2_out(0) and D2_out(8));
+P3_8 <= (D2_out(9) or WRITE_n);
+
+E8_in <= P3_8 & ADR(9 downto 7);
+
+E8: process(E8_in)
+begin
+	case E8_in is
+		when "0000" =>
+         E8_out <= "1111111110";
+		when "0001" =>
+         E8_out <= "1111111101";
+		when "0010" =>
+         E8_out <= "1111111011";
+		when "0011" =>
+         E8_out <= "1111110111";
+      when "0100" =>
+         E8_out <= "1111101111";
+      when "0101" =>
+         E8_out <= "1111011111";
+      when "0110" =>
+         E8_out <= "1110111111";
+      when others =>
+         E8_out <= "1111111111";
+      end case;
+end process;
+
+H8_en <= E8_out(0);
+Timer_Reset_n <= E8_out(1);
+CollRst1_n <= E8_out(2);
+CollRst2_n <= E8_out(3);
+SteerRst1_n <= E8_out(4);
+SteerRst2_n <= E8_out(5);
+NoiseReset_n <= E8_out(6);
+
+-- H8 9334 
+H8_dec: process(clk6, Adr)
+begin
+if rising_edge(clk6) then
+	if (H8_en = '0') then
+	  case Adr(6 downto 4) is
+		 when "000" => Attract_int <= Adr(0);
+		 when "001" => Skid1 <= Adr(0);
+		 when "010" => Skid2 <= Adr(0);
+		 when "011" => LAMP1 <= Adr(0);
+		 when "100" => LAMP2 <= Adr(0);
+		 when "101" => null; -- "Spare" on schematic
+		 when "110" => null;
+		 when "111" => null;
+		 when others => null;
+	  end case;
+	end if;
+ end if;
+end process;		
+Attract <= Attract_Int;
+
+-- CPU Din mux
+cpuDin <= 	ROM_dout when rom_ce = '1' else 
+				(not CPUram_dout) when Display_n = '0' else -- Remember RAM data is inverted
+				VCount(7) & VBlank_s & Vreset & Attract_int & "1111" when Sync_n = '0' else -- Using V128 (VCount(7)) in place of 60Hz mains reference
+				Collisions1 & "111111" when Collision1_n = '0' else
+				Collisions2 & "111111" when Collision2_n = '0' else
+				Inputs & "111111" when SWITCH_n = '0' else
+				x"FF";
+	
+end rtl;
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/dac.sv b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/dac.sv
new file mode 100644
index 00000000..d5f08d27
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/dac.sv	
@@ -0,0 +1,33 @@
+//
+// PWM DAC
+//
+// MSBI is the highest bit number. NOT amount of bits!
+//
+module dac #(parameter MSBI=13, parameter INV=1'b1)
+(
+   output reg      DACout, //Average Output feeding analog lowpass
+   input  [MSBI:0] DACin,  //DAC input (excess 2**MSBI)
+   input           CLK,
+   input           RESET
+);
+
+reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
+reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
+reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
+reg [MSBI+2:0] DeltaB;     //B input of Delta Adder
+
+always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
+always @(*) DeltaAdder = DACin + DeltaB;
+always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
+
+always @(posedge CLK or posedge RESET) begin
+   if(RESET) begin
+      SigmaLatch <= 1'b1 << (MSBI+1);
+      DACout <= INV;
+   end else begin
+      SigmaLatch <= SigmaAdder;
+      DACout <= SigmaLatch[MSBI+2] ^ INV;
+   end
+end
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/hq2x.sv b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/hq2x.sv
new file mode 100644
index 00000000..f17732b6
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/hq2x.sv	
@@ -0,0 +1,454 @@
+//
+//
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+`define BITS_TO_FIT(N) ( \
+     N <=   2 ? 0 : \
+     N <=   4 ? 1 : \
+     N <=   8 ? 2 : \
+     N <=  16 ? 3 : \
+     N <=  32 ? 4 : \
+     N <=  64 ? 5 : \
+     N <= 128 ? 6 : \
+     N <= 256 ? 7 : \
+     N <= 512 ? 8 : \
+     N <=1024 ? 9 : 10 )
+
+module hq2x_in #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input            rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input            wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+	wire [DWIDTH:0] out[2];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+endmodule
+
+
+module hq2x_out #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input      [1:0] rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input      [1:0] wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
+	wire  [DWIDTH:0] out[4];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
+endmodule
+
+
+module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
+(
+	input	            clock,
+	input	 [DWIDTH:0] data,
+	input	 [AWIDTH:0] rdaddress,
+	input	 [AWIDTH:0] wraddress,
+	input	            wren,
+	output [DWIDTH:0] q
+);
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b(q),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({(DWIDTH+1){1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = NUMWORDS,
+		altsyncram_component.numwords_b = NUMWORDS,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = AWIDTH+1,
+		altsyncram_component.widthad_b = AWIDTH+1,
+		altsyncram_component.width_a = DWIDTH+1,
+		altsyncram_component.width_b = DWIDTH+1,
+		altsyncram_component.width_byteena_a = 1;
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DiffCheck
+(
+	input [17:0] rgb1,
+	input [17:0] rgb2,
+	output result
+);
+
+	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
+	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
+	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
+	wire [6:0] t = $signed(r) + $signed(b);
+	wire [6:0] gx = {g[5], g};
+	wire [7:0] y = $signed(t) + $signed(gx);
+	wire [6:0] u = $signed(r) - $signed(b);
+	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
+
+	// if y is inside (-24..24)
+	wire y_inside = (y < 8'h18 || y >= 8'he8);
+
+	// if u is inside (-4, 4)
+	wire u_inside = (u < 7'h4 || u >= 7'h7c);
+
+	// if v is inside (-6, 6)
+	wire v_inside = (v < 8'h6 || v >= 8'hfA);
+	assign result = !(y_inside && u_inside && v_inside);
+endmodule
+
+module InnerBlend
+(
+	input  [8:0] Op,
+	input  [5:0] A,
+	input  [5:0] B,
+	input  [5:0] C,
+	output [5:0] O
+);
+
+	function  [8:0] mul6x3;
+		input  [5:0] op1;
+		input  [2:0] op2;
+	begin
+		mul6x3 = 9'd0;
+		if(op2[0]) mul6x3 = mul6x3 + op1;
+		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
+		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
+	end
+	endfunction
+
+	wire OpOnes = Op[4];
+	wire [8:0] Amul = mul6x3(A, Op[7:5]);
+	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
+	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
+	wire [8:0] At =  Amul;
+	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
+	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
+	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
+	assign O = Op[8] ? A : Res[9:4];
+endmodule
+
+module Blend
+(
+	input   [5:0] rule,
+	input         disable_hq2x,
+	input  [17:0] E,
+	input  [17:0] A,
+	input  [17:0] B,
+	input  [17:0] D,
+	input  [17:0] F,
+	input  [17:0] H,
+	output [17:0] Result
+);
+
+	reg [1:0] input_ctrl;
+	reg [8:0] op;
+	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
+	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
+	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
+	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
+	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
+	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
+	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
+	localparam AB = 2'b00;
+	localparam AD = 2'b01;
+	localparam DB = 2'b10;
+	localparam BD = 2'b11;
+	wire is_diff;
+	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
+
+	always @* begin
+		case({!is_diff, rule[5:2]})
+			1,17:  {op, input_ctrl} = {BLEND1, AB};
+			2,18:  {op, input_ctrl} = {BLEND1, DB};
+			3,19:  {op, input_ctrl} = {BLEND1, BD};
+			4,20:  {op, input_ctrl} = {BLEND2, DB};
+			5,21:  {op, input_ctrl} = {BLEND2, AB};
+			6,22:  {op, input_ctrl} = {BLEND2, AD};
+
+			8: {op, input_ctrl} = {BLEND0, 2'bxx};
+			9: {op, input_ctrl} = {BLEND0, 2'bxx};
+			10: {op, input_ctrl} = {BLEND0, 2'bxx};
+			11: {op, input_ctrl} = {BLEND1, AB};
+			12: {op, input_ctrl} = {BLEND1, AB};
+			13: {op, input_ctrl} = {BLEND1, AB};
+			14: {op, input_ctrl} = {BLEND1, DB};
+			15: {op, input_ctrl} = {BLEND1, BD};
+
+			24: {op, input_ctrl} = {BLEND2, DB};
+			25: {op, input_ctrl} = {BLEND5, DB};
+			26: {op, input_ctrl} = {BLEND6, DB};
+			27: {op, input_ctrl} = {BLEND2, DB};
+			28: {op, input_ctrl} = {BLEND4, DB};
+			29: {op, input_ctrl} = {BLEND5, DB};
+			30: {op, input_ctrl} = {BLEND3, BD};
+			31: {op, input_ctrl} = {BLEND3, DB};
+			default: {op, input_ctrl} = 11'bx;
+		endcase
+
+		// Setting op[8] effectively disables HQ2X because blend will always return E.
+		if (disable_hq2x) op[8] = 1;
+	end
+
+	// Generate inputs to the inner blender. Valid combinations.
+	// 00: E A B
+	// 01: E A D 
+	// 10: E D B
+	// 11: E B D
+	wire [17:0] Input1 = E;
+	wire [17:0] Input2 = !input_ctrl[1] ? A :
+                        !input_ctrl[0] ? D : B;
+
+	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
+	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
+	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
+	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
+endmodule
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	input               clk,
+	input               ce_x4,
+	input    [DWIDTH:0] inputpixel,
+	input               mono,
+	input               disable_hq2x,
+	input               reset_frame,
+	input               reset_line,
+	input         [1:0] read_y,
+	input  [AWIDTH+1:0] read_x,
+	output   [DWIDTH:0] outpixel
+);
+
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+localparam DWIDTH = HALF_DEPTH ? 8 : 17;
+
+wire [5:0] hqTable[256] = '{
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
+};
+
+reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
+reg [17:0] A, B, D, F, G, H;
+reg  [7:0] pattern, nextpatt;
+reg  [1:0] i;
+reg  [7:0] y;
+
+wire curbuf = y[0];
+reg  prevbuf = 0;
+wire iobuf = !curbuf;
+
+wire diff0, diff1;
+DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
+DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
+
+wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
+
+wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
+wire [17:0] blend_result;
+Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
+
+reg             Curr2_addr1;
+reg  [AWIDTH:0] Curr2_addr2;
+wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
+wire [DWIDTH:0] Curr2tmp;
+
+reg  [AWIDTH:0] wrin_addr2;
+reg  [DWIDTH:0] wrpix;
+reg             wrin_en;
+
+function [17:0] h2rgb;
+	input  [8:0] v;
+begin
+	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
+end
+endfunction
+
+function  [8:0] rgb2h;
+	input [17:0] v;
+begin
+	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
+end
+endfunction
+
+hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
+(
+	.clk(clk),
+
+	.rdaddr(Curr2_addr2),
+	.rdbuf(Curr2_addr1),
+	.q(Curr2tmp),
+
+	.wraddr(wrin_addr2),
+	.wrbuf(iobuf),
+	.data(wrpix),
+	.wren(wrin_en)
+);
+
+reg         [1:0] wrout_addr1;
+reg  [AWIDTH+1:0] wrout_addr2;
+reg               wrout_en;
+reg    [DWIDTH:0] wrdata;
+
+hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
+(
+	.clk(clk),
+
+	.rdaddr(read_x),
+	.rdbuf(read_y),
+	.q(outpixel),
+
+	.wraddr(wrout_addr2),
+	.wrbuf(wrout_addr1),
+	.data(wrdata),
+	.wren(wrout_en)
+);
+
+always @(posedge clk) begin
+	reg [AWIDTH:0] offs;
+	reg old_reset_line;
+	reg old_reset_frame;
+
+	wrout_en <= 0;
+	wrin_en  <= 0;
+
+	if(ce_x4) begin
+
+		pattern <= new_pattern;
+
+		if(~&offs) begin
+			if (i == 0) begin
+				Curr2_addr1 <= prevbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 1) begin
+				Prev2 <= Curr2;
+				Curr2_addr1 <= curbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 2) begin
+				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
+				wrpix <= inputpixel;
+				wrin_addr2 <= offs;
+				wrin_en <= 1;
+			end
+			if (i == 3) begin
+				offs <= offs + 1'd1;
+			end
+
+			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
+			else           wrdata <= blend_result;
+
+			wrout_addr1 <= {curbuf, i[1]};
+			wrout_addr2 <= {offs, i[1]^i[0]};
+			wrout_en    <= 1;
+		end
+
+		if(i==3) begin
+			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
+			{A, G} <= {Prev0, Next0};
+			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
+			{Prev0, Prev1} <= {Prev1, Prev2};
+			{Curr0, Curr1} <= {Curr1, Curr2};
+			{Next0, Next1} <= {Next1, Next2};
+		end else begin
+			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
+			{B, F, H, D} <= {F, H, D, B};
+		end
+
+		i <= i + 1'b1;
+		if(old_reset_line && ~reset_line) begin
+			old_reset_frame <= reset_frame;
+			offs <= 0;
+			i <= 0;
+			y <= y + 1'd1;
+			prevbuf <= curbuf;
+			if(old_reset_frame & ~reset_frame) begin
+				y <= 0;
+				prevbuf <= 0;
+			end
+		end
+
+		old_reset_line  <= reset_line;
+	end
+end
+
+endmodule  // Hq2x
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/keyboard.sv b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/keyboard.sv
new file mode 100644
index 00000000..01625319
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/keyboard.sv	
@@ -0,0 +1,79 @@
+
+
+module keyboard
+(
+	input  clk,
+	input  reset,
+	input  ps2_kbd_clk,
+	input  ps2_kbd_data,
+
+	output reg[7:0] joystick
+);
+
+reg [11:0] shift_reg = 12'hFFF;
+wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
+wire [7:0] kcode = kdata[9:2];
+reg        release_btn = 0;
+
+reg  [7:0] code;
+reg        input_strobe = 0;
+
+always @(negedge clk) begin
+	reg old_reset = 0;
+
+	old_reset <= reset;
+
+	if(~old_reset & reset)begin
+		joystick <= 0;
+	end
+
+	if(input_strobe) begin
+		case(code)
+			'h75: joystick[3] <= ~release_btn; // arrow up
+			'h72: joystick[2] <= ~release_btn; // arrow down
+			'h6B: joystick[1] <= ~release_btn; // arrow left
+			'h74: joystick[0] <= ~release_btn; // arrow right
+
+			'h29: joystick[4] <= ~release_btn; // Space
+			'h05: joystick[5] <= ~release_btn; // F1
+			'h06: joystick[6] <= ~release_btn; // F2
+			'h76: joystick[7] <= ~release_btn; // Escape
+		endcase
+	end
+end
+
+always @(posedge clk) begin
+	reg [3:0] prev_clk  = 0;
+	reg       old_reset = 0;
+	reg       action = 0;
+
+	old_reset <= reset;
+	input_strobe <= 0;
+
+	if(~old_reset & reset)begin
+		prev_clk  <= 0;
+		shift_reg <= 12'hFFF;
+	end else begin
+		prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
+		if(prev_clk == 1) begin
+			if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
+				shift_reg <= 12'hFFF;
+				if (kcode == 8'he0) ;
+				// Extended key code follows
+				else if (kcode == 8'hf0)
+					// Release code follows
+					action <= 1;
+				else begin
+					// Cancel extended/release flags for next time
+					action <= 0;
+					release_btn <= action;
+					code <= kcode;
+					input_strobe <= 1;
+				end
+			end else begin
+				shift_reg <= kdata;
+			end
+		end
+	end
+end
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/mist_io.sv b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/mist_io.sv
new file mode 100644
index 00000000..dcc7ecde
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/mist_io.sv	
@@ -0,0 +1,491 @@
+//
+// mist_io.v
+//
+// mist_io for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+//
+// Use buffer to access SD card. It's time-critical part.
+// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
+//                                                           (Sorgelig)
+//
+// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
+// clk_ps2 = clk_sys/(PS2DIV*2)
+//
+
+module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
+(
+
+	// parameter STRLEN and the actual length of conf_str have to match
+	input [(8*STRLEN)-1:0] conf_str,
+
+	// Global clock. It should be around 100MHz (higher is better).
+	input             clk_sys,
+
+	// Global SPI clock from ARM. 24MHz
+	input             SPI_SCK,
+
+	input             CONF_DATA0,
+	input             SPI_SS2,
+	output            SPI_DO,
+	input             SPI_DI,
+
+	output reg  [7:0] joystick_0,
+	output reg  [7:0] joystick_1,
+	output reg [15:0] joystick_analog_0,
+	output reg [15:0] joystick_analog_1,
+	output      [1:0] buttons,
+	output      [1:0] switches,
+	output            scandoubler_disable,
+	output            ypbpr,
+
+	output reg [31:0] status,
+
+	// SD config
+	input             sd_conf,
+	input             sd_sdhc,
+	output            img_mounted, // signaling that new image has been mounted
+	output reg [31:0] img_size,    // size of image in bytes
+
+	// SD block level access
+	input      [31:0] sd_lba,
+	input             sd_rd,
+	input             sd_wr,
+	output reg        sd_ack,
+	output reg        sd_ack_conf,
+
+	// SD byte level access. Signals for 2-PORT altsyncram.
+	output reg  [8:0] sd_buff_addr,
+	output reg  [7:0] sd_buff_dout,
+	input       [7:0] sd_buff_din,
+	output reg        sd_buff_wr,
+
+	// ps2 keyboard emulation
+	output            ps2_kbd_clk,
+	output reg        ps2_kbd_data,
+	output            ps2_mouse_clk,
+	output reg        ps2_mouse_data,
+	input             ps2_caps_led,
+
+	// ARM -> FPGA download
+	output reg        ioctl_download = 0, // signal indicating an active download
+	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output            ioctl_wr,
+	output reg [23:0] ioctl_addr,
+	output reg  [7:0] ioctl_dout
+);
+
+reg [7:0] b_data;
+reg [6:0] sbuf;
+reg [7:0] cmd;
+reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
+reg [9:0] byte_cnt;   // counts bytes
+reg [7:0] but_sw;
+reg [2:0] stick_idx;
+
+reg    mount_strobe = 0;
+assign img_mounted  = mount_strobe;
+
+assign buttons = but_sw[1:0];
+assign switches = but_sw[3:2];
+assign scandoubler_disable = but_sw[4];
+assign ypbpr = but_sw[5];
+
+wire [7:0] spi_dout = { sbuf, SPI_DI};
+
+// this variant of user_io is for 8 bit cores (type == a4) only
+wire [7:0] core_type = 8'ha4;
+
+// command byte read by the io controller
+wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
+
+reg spi_do;
+assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
+
+wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
+
+// drive MISO only when transmitting core id
+always@(negedge SPI_SCK) begin
+	if(!CONF_DATA0) begin
+		// first byte returned is always core type, further bytes are 
+		// command dependent
+      if(byte_cnt == 0) begin
+		  spi_do <= core_type[~bit_cnt];
+
+		end else begin
+			case(cmd)
+				// reading config string
+				8'h14: begin
+					// returning a byte from string
+						if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
+							else spi_do <= 0;
+					end
+
+				// reading sd card status
+				8'h16: begin
+						if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
+						else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
+						else spi_do <= 0;
+					end
+
+				// reading sd card write data
+				8'h18:
+						spi_do <= b_data[~bit_cnt];
+
+				// reading keyboard LED status
+				8'h1f:
+						spi_do <= kbd_led[~bit_cnt];
+
+				default:
+						spi_do <= 0;
+			endcase
+		end
+   end
+end
+
+reg b_wr2,b_wr3;
+always @(negedge clk_sys) begin
+	b_wr3      <= b_wr2;
+	sd_buff_wr <= b_wr3;
+end
+
+// SPI receiver
+always@(posedge SPI_SCK or posedge CONF_DATA0) begin
+
+	if(CONF_DATA0) begin
+		b_wr2 <= 0;
+	   bit_cnt <= 0;
+	   byte_cnt <= 0;
+		sd_ack <= 0;
+		sd_ack_conf <= 0;
+	end else begin
+		b_wr2 <= 0;
+
+		sbuf <= spi_dout[6:0];
+		bit_cnt <= bit_cnt + 1'd1;
+		if(bit_cnt == 5) begin
+			if (byte_cnt == 0) sd_buff_addr <= 0;
+			if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
+			if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
+		end
+
+		// finished reading command byte
+      if(bit_cnt == 7) begin
+			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
+			if(byte_cnt == 0) begin
+				cmd <= spi_dout;
+
+				if(spi_dout == 8'h19) begin
+					sd_ack_conf  <= 1;
+					sd_buff_addr <= 0;
+				end
+				if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
+					sd_ack       <= 1;
+					sd_buff_addr <= 0;
+				end
+				if(spi_dout == 8'h18) b_data <= sd_buff_din;
+
+				mount_strobe <= 0;
+
+			end else begin
+			
+				case(cmd)
+					// buttons and switches
+					8'h01: but_sw <= spi_dout; 
+					8'h02: joystick_0 <= spi_dout;
+					8'h03: joystick_1 <= spi_dout;
+
+					// store incoming ps2 mouse bytes 
+					8'h04: begin
+							ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; 
+							ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
+						end
+
+					// store incoming ps2 keyboard bytes 
+					8'h05: begin
+							ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; 
+							ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
+						end
+				
+					8'h15: status[7:0] <= spi_dout;
+				
+					// send SD config IO -> FPGA
+					// flag that download begins
+					// sd card knows data is config if sd_dout_strobe is asserted
+					// with sd_ack still being inactive (low)
+					8'h19,
+					// send sector IO -> FPGA
+					// flag that download begins
+					8'h17: begin
+							sd_buff_dout <= spi_dout;
+							b_wr2 <= 1;
+						end
+
+					8'h18: b_data <= sd_buff_din;
+
+					// joystick analog
+					8'h1a: begin
+							// first byte is joystick index
+							if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
+							else if(byte_cnt == 2) begin
+								// second byte is x axis
+								if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
+									else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
+							end else if(byte_cnt == 3) begin
+								// third byte is y axis
+								if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
+									else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
+							end
+						end
+
+					// notify image selection
+					8'h1c: mount_strobe <= 1;
+
+					// send image info
+					8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
+
+					// status, 32bit version
+					8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
+					default: ;
+				endcase
+			end
+		end
+	end
+end
+
+
+///////////////////////////////   PS2   ///////////////////////////////
+// 8 byte fifos to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
+
+reg clk_ps2;
+always @(negedge clk_sys) begin
+	integer cnt;
+	cnt <= cnt + 1'd1;
+	if(cnt == PS2DIV) begin
+		clk_ps2 <= ~clk_ps2;
+		cnt <= 0;
+	end
+end
+
+// keyboard
+reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_kbd_tx_state;
+reg [7:0] ps2_kbd_tx_byte;
+reg ps2_kbd_parity;
+
+assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_kbd_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_kbd_r_inc <= 0;
+
+		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_kbd_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
+				// load tx register from fifo
+				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
+				ps2_kbd_r_inc <= 1;
+
+				// reset parity
+				ps2_kbd_parity <= 1;
+
+				// start transmitter
+				ps2_kbd_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_kbd_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
+				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
+				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
+				if(ps2_kbd_tx_byte[0]) 
+					ps2_kbd_parity <= !ps2_kbd_parity;
+			end
+
+			// transmission of parity
+			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
+
+			// transmission of stop bit
+			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
+
+			// advance state machine
+			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
+				else ps2_kbd_tx_state <= 0;
+		end
+	end
+end
+
+// mouse
+reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_mouse_tx_state;
+reg [7:0] ps2_mouse_tx_byte;
+reg ps2_mouse_parity;
+
+assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_mouse_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_mouse_r_inc <= 0;
+
+		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_mouse_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
+				// load tx register from fifo
+				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
+				ps2_mouse_r_inc <= 1;
+
+				// reset parity
+				ps2_mouse_parity <= 1;
+
+				// start transmitter
+				ps2_mouse_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_mouse_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
+				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
+				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
+				if(ps2_mouse_tx_byte[0]) 
+					ps2_mouse_parity <= !ps2_mouse_parity;
+			end
+
+			// transmission of parity
+			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
+
+			// transmission of stop bit
+			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
+
+			// advance state machine
+			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
+				else ps2_mouse_tx_state <= 0;
+		end
+	end
+end
+
+
+///////////////////////////////   DOWNLOADING   ///////////////////////////////
+
+reg  [7:0] data_w;
+reg [23:0] addr_w;
+reg        rclk   = 0;
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+
+// data_io has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS2) begin
+	reg  [6:0] sbuf;
+	reg  [7:0] cmd;
+	reg  [4:0] cnt;
+	reg [23:0] addr;
+
+	if(SPI_SS2) cnt <= 0;
+	else begin
+		rclk <= 0;
+
+		// don't shift in last bit. It is evaluated directly
+		// when writing to ram
+		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
+
+		// increase target address after write
+		if(rclk) addr <= addr + 1'd1;
+
+		// count 0-7 8-15 8-15 ... 
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		// finished command byte
+      if(cnt == 7) cmd <= {sbuf, SPI_DI};
+
+		// prepare/end transmission
+		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
+			// prepare 
+			if(SPI_DI) begin
+				addr <= 0;
+				ioctl_download <= 1; 
+			end else begin
+				addr_w <= addr;
+				ioctl_download <= 0;
+			end
+		end
+
+		// command 0x54: UIO_FILE_TX
+		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
+			addr_w <= addr;
+			data_w <= {sbuf, SPI_DI};
+			rclk <= 1;
+		end
+
+      // expose file (menu) index
+      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
+	end
+end
+
+assign ioctl_wr = |ioctl_wrd;
+reg [1:0] ioctl_wrd;
+
+always@(negedge clk_sys) begin
+	reg        rclkD, rclkD2;
+
+	rclkD    <= rclk;
+	rclkD2   <= rclkD;
+	ioctl_wrd<= {ioctl_wrd[0],1'b0};
+
+	if(rclkD & ~rclkD2) begin
+		ioctl_dout <= data_w;
+		ioctl_addr <= addr_w;
+		ioctl_wrd  <= 2'b11;
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/motion.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/motion.vhd
new file mode 100644
index 00000000..f9010db1
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/motion.vhd	
@@ -0,0 +1,361 @@
+-- Motion object generation circuitry for Kee Games Sprint 2
+-- This generates the four cars which are the only moving objects in the game
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity motion is 
+port(		
+			CLK6			: in  std_logic; -- 6MHz* on schematic
+			CLK12			: in  std_logic;
+			PHI2			: in  std_logic;
+			DISPLAY		: in  std_logic_vector(7 downto 0);
+			H256_s		: in  std_logic; -- 256H* on schematic
+			VCount		: in  std_logic_vector(7 downto 0);
+			HCount		: in  std_logic_vector(8 downto 0);
+			Crash_n		: out std_logic;
+			Motor1_n		: out std_logic;
+			Motor2_n		: out std_logic;
+			Car1  		: out std_logic;
+			Car1_n  		: out std_logic;
+			Car2  		: out std_logic;
+			Car2_n  		: out std_logic;
+			Car3_4_n  	: out std_logic
+			);
+end motion;
+
+architecture rtl of motion is
+
+signal phi0			: std_logic;
+
+signal LDH1_n		: std_logic;
+signal LDH2_n		: std_logic;
+signal LDH3_n		: std_logic;
+signal LDH4_n		: std_logic;
+
+signal LDV1A_n		: std_logic;
+signal LDV2A_n		: std_logic;
+signal LDV3A_n		: std_logic;
+signal LDV4A_n		: std_logic;
+
+signal LDV1B_n		: std_logic;
+signal LDV2B_n		: std_logic;
+signal LDV3B_n		: std_logic;
+signal LDV4B_n		: std_logic;
+
+signal Car1_Inh	: std_logic;
+signal Car2_Inh	: std_logic;
+signal Car3_Inh	: std_logic;
+signal Car4_Inh	: std_logic;
+
+signal LM4_sum		: std_logic_vector(7 downto 0) := x"00";
+signal N4_8			: std_logic;
+
+signal H256_n		: std_logic;
+signal H256			: std_logic;
+signal H64 			: std_logic;
+signal H32			: std_logic;
+signal H16			: std_logic;
+signal H8			: std_logic;
+signal H4			: std_logic;
+
+signal L5_reg		: std_logic_vector(3 downto 0);
+
+signal J8_3			: std_logic;
+signal J8_6			: std_logic;
+
+signal K8_in		: std_logic_vector(3 downto 0);
+signal K8_out		: std_logic_vector(9 downto 0);
+signal P7_in		: std_logic_vector(3 downto 0);
+signal P7_out		: std_logic_vector(9 downto 0);
+
+signal Car1_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+signal Car2_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+signal Car3_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+signal Car4_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+
+signal Car1_reg	: std_logic_vector(15 downto 0) := x"0000";
+signal Car2_reg	: std_logic_vector(15 downto 0) := x"0000";
+signal Car3_reg 	: std_logic_vector(15 downto 0) := x"0000";
+signal Car4_reg 	: std_logic_vector(15 downto 0) := x"0000";
+
+signal Vid			: std_logic_vector(7 downto 0);
+
+
+begin
+phi0 <= phi2;
+
+H4 <= Hcount(2);
+H8 <= Hcount(3);
+H16 <= Hcount(4);
+H32 <= Hcount(5);
+H64 <= Hcount(6);
+H256 <= Hcount(8);
+H256_n <= not(Hcount(8));
+
+-- Vertical line comparator
+LM4_sum <= Display + VCount; 
+N4_8 <= not(LM4_sum(7) and LM4_sum(6) and LM4_sum(5) and LM4_sum(4) and LM4_sum(3) and H256_n and H64 and H8);
+
+
+-- D type flip-flops in L5
+L5: process(phi2, N4_8, LM4_sum(2 downto 0))
+begin
+	if rising_edge(phi2) then
+		L5_reg <= N4_8 & LM4_sum(2 downto 0);
+	end if;
+end process;
+
+
+-- Motion object PROMs - These contain the car images for all 32 possible orientations
+J6: entity work.j6_prom
+port map(
+	clock => clk6,
+	address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+	q => Vid(7 downto 4)
+	);
+
+K6: entity work.k6_prom
+port map(
+	clock => clk6,
+	address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+	q => Vid(3 downto 0)
+	);
+
+	
+-- Some glue logic
+J8_3 <= (H4 or L5_reg(3));
+J8_6 <= (H256 or H64 or H4);
+
+
+-- Decoders
+-- Making K8 synchronous fixes weird problem with ghost artifacts of motion objects
+K8_in <= J8_3 & H32 & H16 & phi0;
+K8: process(clk6, K8_in)
+begin
+	if rising_edge(clk6) then
+		case K8_in is
+			when "0000" =>
+				K8_out <= "1111111110";
+			when "0001" =>
+				K8_out <= "1111111101"; 
+			when "0010" =>
+				K8_out <= "1111111011"; 
+			when "0011" =>
+				K8_out <= "1111110111";
+			when "0100" =>
+				K8_out <= "1111101111"; 
+			when "0101" =>
+				K8_out <= "1111011111";
+			when "0110" =>
+				K8_out <= "1110111111"; 
+			when "0111" =>
+				K8_out <= "1101111111";
+			when "1000" =>
+				K8_out <= "1011111111";
+			when "1001" =>
+				K8_out <= "0111111111";
+			when others =>
+				K8_out <= "1111111111";
+			end case;
+		end if;
+end process;
+LDV3B_n <= K8_out(7);
+LDV3A_n <= K8_out(6);
+LDV2B_n <= K8_out(5);
+LDV2A_n <= K8_out(4);
+LDV1B_n <= K8_out(3);
+LDV1A_n <= K8_out(2);
+LDV4B_n <= K8_out(1);
+LDV4A_n <= K8_out(0);
+
+P7_in <= J8_6 & H32 & H16 & H8;
+P7: process(P7_in)
+begin
+	case P7_in is
+		when "0000" =>
+         P7_out <= "1111111110";
+		when "0001" =>
+         P7_out <= "1111111101";
+      when "0010" =>
+         P7_out <= "1111111011";
+      when "0011" =>
+         P7_out <= "1111110111";
+      when "0100" =>
+         P7_out <= "1111101111";
+      when "0101" =>
+         P7_out <= "1111011111";
+      when "0110" =>
+         P7_out <= "1110111111";
+      when "0111" =>
+         P7_out <= "1101111111";
+      when "1000" =>
+         P7_out <= "1011111111";
+      when "1001" =>
+         P7_out <= "0111111111";
+      when others =>
+         P7_out <= "1111111111";
+      end case;
+end process;
+Crash_n <= P7_out(7);
+Motor2_n <= P7_out(6);
+Motor1_n <= P7_out(5);	
+LDH4_n <= P7_out(4);
+LDH3_n <= P7_out(3); 
+LDH2_n <= P7_out(2);
+LDH1_n <= P7_out(1);
+
+
+-- Car 1 Horizontal position counter
+-- This combines two 74163s at locations R5 and R6 on the PCB 
+R5_6: process(clk6, H256_s, LDH1_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH1_n = '0' then -- preload the counter
+			Car1_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car1_Hpos <= Car1_Hpos + '1';		
+		end if;
+		if Car1_Hpos(7 downto 3) = "11111" then
+			Car1_Inh <= '0';
+		else
+			Car1_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 1 video shift register
+-- This combines two 74165s at locations M7 and N7 on the PCB
+M_N7: process(clk12, Car1_Inh, LDV1A_n, LDV1B_n, Vid)
+begin
+	if LDV1A_n = '0' then
+			Car1_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV1B_n = '0' then
+			Car1_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car1_Inh = '0' then
+			Car1_reg <= '0' & Car1_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car1 <= Car1_reg(0);
+Car1_n <= not Car1_reg(0);
+
+
+-- Car 2 Horizontal position counter
+-- This combines two 74LS163s at locations P5 and P6 on the PCB 
+P5_6: process(clk6, H256_s, LDH2_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH2_n = '0' then -- preload the counter
+			Car2_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car2_Hpos <= Car2_Hpos + '1';
+		end if;
+		if Car2_Hpos(7 downto 3) = "11111" then
+			Car2_Inh <= '0';
+		else
+			Car2_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 2 video shift register
+K_L7: process(clk12, Car2_Inh, LDV2A_n, LDV2B_n, Vid)
+begin
+	if LDV2A_n = '0' then
+			Car2_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV2B_n = '0' then
+			Car2_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car2_Inh = '0' then
+			Car2_reg <= '0' & Car2_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car2 <= Car2_reg(0);
+Car2_n <= not Car2_reg(0);
+
+
+-- Car 3 Horizontal position counter
+-- This combines two 74LS163s at locations N5 and N6 on the PCB 
+N5_6: process(clk6, H256_s, LDH3_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH3_n = '0' then -- preload the counter
+			Car3_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car3_Hpos <= Car3_Hpos + '1';
+		end if;
+		if Car3_Hpos(7 downto 3) = "11111" then
+			Car3_Inh <= '0';
+		else
+			Car3_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 3 video shift register
+H_J7: process(clk12, Car3_Inh, LDV3A_n, LDV3B_n, Vid)
+begin
+	if LDV3A_n = '0' then
+			Car3_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV3B_n = '0' then
+			Car3_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car3_Inh = '0' then
+			Car3_reg <= '0' & Car3_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+
+
+-- Car 4 Horizontal position counter
+-- This combines two 74LS163s at locations M5 and M6 on the PCB 
+M5_6: process(clk6, H256_s, LDH4_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH4_n = '0' then -- preload the counter
+			Car4_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car4_Hpos <= Car4_Hpos + '1';
+		end if;
+		if Car4_Hpos(7 downto 3) = "11111" then
+			Car4_Inh <= '0';
+		else
+			Car4_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 4 video shift register
+E_F7: process(clk12, Car4_Inh, LDV4A_n, LDV4B_n, Vid)
+begin
+	if LDV4A_n = '0' then
+			Car4_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV4B_n = '0' then
+			Car4_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car4_Inh = '0' then
+			Car4_reg <= '0' & Car4_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car3_4_n <= not (Car3_reg(0) or Car4_reg(0));
+
+end rtl;
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/osd.sv b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/osd.sv
new file mode 100644
index 00000000..c62c10af
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/osd.sv	
@@ -0,0 +1,179 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd (
+	// OSDs pixel clock, should be synchronous to cores pixel clock to
+	// avoid jitter.
+	input        clk_sys,
+
+	// SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// VGA signals coming from core
+	input  [5:0] R_in,
+	input  [5:0] G_in,
+	input  [5:0] B_in,
+	input        HSync,
+	input        VSync,
+	
+	// VGA signals going to video connector
+	output [5:0] R_out,
+	output [5:0] G_out,
+	output [5:0] B_out
+);
+
+parameter OSD_X_OFFSET = 10'd0;
+parameter OSD_Y_OFFSET = 10'd0;
+parameter OSD_COLOR    = 3'd0;
+
+localparam OSD_WIDTH   = 10'd256;
+localparam OSD_HEIGHT  = 10'd128;
+
+// *********************************************************************************
+// spi client
+// *********************************************************************************
+
+// this core supports only the display related OSD commands
+// of the minimig
+reg        osd_enable;
+(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
+
+// the OSD has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS3) begin
+	reg  [4:0] cnt;
+	reg [10:0] bcnt;
+	reg  [7:0] sbuf;
+	reg  [7:0] cmd;
+
+	if(SPI_SS3) begin
+		cnt  <= 0;
+		bcnt <= 0;
+	end else begin
+		sbuf <= {sbuf[6:0], SPI_DI};
+
+		// 0:7 is command, rest payload
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		if(cnt == 7) begin
+			cmd <= {sbuf[6:0], SPI_DI};
+      
+			// lower three command bits are line address
+			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
+
+			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
+		end
+
+		// command 0x20: OSDCMDWRITE
+		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
+			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
+			bcnt <= bcnt + 1'd1;
+		end
+	end
+end
+
+// *********************************************************************************
+// video timing and sync polarity anaylsis
+// *********************************************************************************
+
+// horizontal counter
+reg  [9:0] h_cnt;
+reg  [9:0] hs_low, hs_high;
+wire       hs_pol = hs_high < hs_low;
+wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
+
+// vertical counter
+reg  [9:0] v_cnt;
+reg  [9:0] vs_low, vs_high;
+wire       vs_pol = vs_high < vs_low;
+wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
+
+wire doublescan = (dsp_height>350); 
+
+reg ce_pix;
+always @(negedge clk_sys) begin
+	integer cnt = 0;
+	integer pixsz, pixcnt;
+	reg hs;
+
+	cnt <= cnt + 1;
+	hs <= HSync;
+
+	pixcnt <= pixcnt + 1;
+	if(pixcnt == pixsz) pixcnt <= 0;
+	ce_pix <= !pixcnt;
+
+	if(hs && ~HSync) begin
+		cnt    <= 0;
+		pixsz  <= (cnt >> 9) - 1;
+		pixcnt <= 0;
+		ce_pix <= 1;
+	end
+end
+
+always @(posedge clk_sys) begin
+	reg hsD, hsD2;
+	reg vsD, vsD2;
+
+	if(ce_pix) begin
+		// bring hsync into local clock domain
+		hsD <= HSync;
+		hsD2 <= hsD;
+
+		// falling edge of HSync
+		if(!hsD && hsD2) begin	
+			h_cnt <= 0;
+			hs_high <= h_cnt;
+		end
+
+		// rising edge of HSync
+		else if(hsD && !hsD2) begin	
+			h_cnt <= 0;
+			hs_low <= h_cnt;
+			v_cnt <= v_cnt + 1'd1;
+		end else begin
+			h_cnt <= h_cnt + 1'd1;
+		end
+
+		vsD <= VSync;
+		vsD2 <= vsD;
+
+		// falling edge of VSync
+		if(!vsD && vsD2) begin	
+			v_cnt <= 0;
+			vs_high <= v_cnt;
+		end
+
+		// rising edge of VSync
+		else if(vsD && !vsD2) begin	
+			v_cnt <= 0;
+			vs_low <= v_cnt;
+		end
+	end
+end
+
+// area in which OSD is being displayed
+wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
+wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
+wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
+wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
+wire [9:0] osd_hcnt    = h_cnt - h_osd_start + 1'd1;  // one pixel offset for osd_byte register
+wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
+
+wire osd_de = osd_enable && 
+              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
+              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
+
+reg  [7:0] osd_byte; 
+always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
+
+wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
+
+assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
+assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
+assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/playfield.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/playfield.vhd
new file mode 100644
index 00000000..86425cbc
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/playfield.vhd	
@@ -0,0 +1,148 @@
+-- Playfield generation circuitry for Sprint 2 by Kee Games
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity playfield is 
+port(   
+			clk6				: in	std_logic;
+			display			: in	std_logic_vector(7 downto 0);
+			HCount			: in  std_logic_vector(8 downto 0);
+			VCount			: in  std_logic_vector(7 downto 0);
+			H256_s			: out std_logic;
+			HBlank			: in	std_logic;
+			VBlank			: in	std_logic;
+			VBlank_n_s		: in  std_logic; -- VBLANK* on the schematic	
+			HSync				: in	std_logic;
+			VSync				: in	std_logic;
+			CompSync_n_s	: out std_logic; -- COMP SYNC* on schematic
+			CompBlank_s		: out std_logic; -- COMP BLANK* on schematic
+			WhitePF_n		: out	std_logic; 
+			BlackPF_n		: out	std_logic 
+			);
+end playfield;
+
+architecture rtl of playfield is
+
+signal H1				: std_logic;
+signal H2				: std_logic;
+signal H4				: std_logic;
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+
+signal V1				: std_logic;
+signal V2				: std_logic;
+signal V4				: std_logic;
+
+signal char_addr		: std_logic_vector(8 downto 0) := (others => '0');
+signal char_data		: std_logic_vector(7 downto 0) := (others => '0');
+
+signal shift_data		: std_logic_vector(7 downto 0) := (others => '0');
+signal QH				: std_logic;
+
+signal R2_reg		: std_logic_vector(3 downto 0) := (others => '0');
+
+
+-- These signals are based off the schematic and are formatted as Designator_PinNumber
+signal R7_12			: std_logic;
+signal P3_3				: std_logic;
+signal P2_13			: std_logic;
+signal P3_6				: std_logic;
+signal A6_6				: std_logic;
+signal A6_3				: std_logic;
+
+begin
+
+-- Video synchronization signals
+H1 <= Hcount(0);
+H2 <= Hcount(1);
+H4 <= Hcount(2);
+H256 <= Hcount(8);
+H256_n <= not(Hcount(8));
+
+V1 <= Vcount(0);
+V2 <= Vcount(1);
+V4 <= Vcount(2);
+
+-- Some glue logic, may be re-written later to be cleaner and easier to follow without referring to schematic
+R7_12 <= not(H1 and H2 and H4);
+
+P3_3 <= (H256_n or R7_12);
+
+P2_13 <= (HSync nor VSync);
+
+P3_6 <= (HBlank or VBlank);
+
+
+
+char_addr <= display(5 downto 0) & V4 & V2 & V1;
+
+-- Background character ROMs
+R4: entity work.Char_MSB
+port map(
+	clock => clk6,
+	Address => char_addr,
+	q => char_data(3 downto 0) 
+	);
+
+P4: entity work.Char_LSB
+port map(
+	clock => clk6,
+	Address => char_addr,
+	q => char_data(7 downto 4) 
+	);
+
+
+-- 74LS166 video shift register	
+R3: process(clk6, P3_3, VBlank_n_s, char_data, shift_data)
+begin
+	if VBlank_n_s = '0' then -- Connected Clear input
+		shift_data <= (others => '0');
+	elsif rising_edge(clk6) then 
+		if P3_3 = '0' then -- Parallel load
+			shift_data <= char_data(7 downto 0);
+		else
+			shift_data <= shift_data(6 downto 0) & '0';
+		end if;
+	end if;
+	QH <= shift_data(7);
+end process;
+
+
+-- 9316 counter at R2
+-- CEP and CET tied to ground, counter is used only as a synchronous latch
+R2: process(clk6, R7_12, display, H256, P2_13, P3_6)
+begin
+	if rising_edge(clk6) then
+		if R7_12 = '0' then
+			R2_reg <= (H256 & display(7) & P3_6 & P2_13);
+		end if;
+	end if;
+end process;
+
+
+H256_s <= R2_reg(3);
+CompBlank_s <= R2_reg(1);
+CompSync_n_s <= R2_reg(0);
+A6_6 <= (R2_reg(2) and QH);
+A6_3 <= ((not R2_reg(2)) and QH);
+
+WhitePF_n <= (not A6_6);
+BlackPF_n <= (not A6_3);
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/pll.v b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/pll.v
new file mode 100644
index 00000000..6a352243
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/pll.v	
@@ -0,0 +1,337 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	inclk0,
+	c0,
+	c1,
+	locked);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  locked;
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire6 = 1'h0;
+	wire [0:0] sub_wire3 = sub_wire0[0:0];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  c0 = sub_wire3;
+	wire  sub_wire4 = inclk0;
+	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+	altpll	altpll_component (
+				.inclk (sub_wire5),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 125,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 224,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 125,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 56,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.383999"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "224"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.38400000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "224"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/ram1k_dp.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/ram1k_dp.qip
new file mode 100644
index 00000000..a2e1e6a2
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/ram1k_dp.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram1k_dp.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/ram1k_dp.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/ram1k_dp.vhd
new file mode 100644
index 00000000..0907d677
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/ram1k_dp.vhd	
@@ -0,0 +1,224 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: ram1k_dp.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY ram1k_dp IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END ram1k_dp;
+
+
+ARCHITECTURE SYN OF ram1k_dp IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK0",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK0",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 1024,
+		numwords_b => 1024,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "CLOCK0",
+		outdata_reg_b => "CLOCK0",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_mixed_ports => "DONT_CARE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => 10,
+		widthad_b => 10,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK0"
+	)
+	PORT MAP (
+		clock0 => clock,
+		wren_a => wren_a,
+		address_b => address_b,
+		data_b => data_b,
+		wren_b => wren_b,
+		address_a => address_a,
+		data_a => data_a,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "../roms/033455e1.hex"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
+-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
+-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ram1k_dp_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6290-01b1.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6290-01b1.hex
new file mode 100644
index 00000000..e99c247b
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6290-01b1.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6291-01c1.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6291-01c1.hex
new file mode 100644
index 00000000..e362de36
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6291-01c1.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6396-01p4.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6396-01p4.hex
new file mode 100644
index 00000000..28243917
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6396-01p4.hex	
@@ -0,0 +1,33 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6397-01r4.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6397-01r4.hex
new file mode 100644
index 00000000..72e395fe
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6397-01r4.hex	
@@ -0,0 +1,33 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6398-01k6.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6398-01k6.hex
new file mode 100644
index 00000000..391da240
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6398-01k6.hex	
@@ -0,0 +1,33 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6399-01j6.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6399-01j6.hex
new file mode 100644
index 00000000..74a9d0b9
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6399-01j6.hex	
@@ -0,0 +1,33 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6400-01m2.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6400-01m2.hex
new file mode 100644
index 00000000..9dbfacea
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6400-01m2.hex	
@@ -0,0 +1,17 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6401-01e2.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6401-01e2.hex
new file mode 100644
index 00000000..975d72ea
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6401-01e2.hex	
@@ -0,0 +1,3 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6404d1.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6404d1.hex
new file mode 100644
index 00000000..aa71f3fd
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6404d1.hex	
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6405-02e1.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6405-02e1.hex
new file mode 100644
index 00000000..d06308f0
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6405-02e1.hex	
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6442-01d1.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6442-01d1.hex
new file mode 100644
index 00000000..160cbf39
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6442-01d1.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6443-01e1.hex b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6443-01e1.hex
new file mode 100644
index 00000000..ae79880b
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/6443-01e1.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_LSB.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_LSB.qip
new file mode 100644
index 00000000..2ce4cc47
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_LSB.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Char_LSB.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_LSB.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_LSB.vhd
new file mode 100644
index 00000000..9c7bdfc3
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_LSB.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: Char_LSB.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY Char_LSB IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END Char_LSB;
+
+
+ARCHITECTURE SYN OF char_lsb IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(3 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6396-01p4.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 9,
+		width_a => 4,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6396-01p4.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6396-01p4.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_LSB_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_MSB.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_MSB.qip
new file mode 100644
index 00000000..9c809207
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_MSB.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Char_MSB.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_MSB.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_MSB.vhd
new file mode 100644
index 00000000..bfa538dd
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/Char_MSB.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: Char_MSB.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY Char_MSB IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END Char_MSB;
+
+
+ARCHITECTURE SYN OF char_msb IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(3 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6397-01r4.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 9,
+		width_a => 4,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6397-01r4.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6397-01r4.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Char_MSB_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/addec_prom.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/addec_prom.qip
new file mode 100644
index 00000000..81a66586
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/addec_prom.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "addec_prom.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/addec_prom.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/addec_prom.vhd
new file mode 100644
index 00000000..6cd74f62
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/addec_prom.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: addec_prom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY addec_prom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END addec_prom;
+
+
+ARCHITECTURE SYN OF addec_prom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6401-01e2.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 32,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 5,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6401-01e2.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6401-01e2.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL addec_prom_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/j6_prom.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/j6_prom.qip
new file mode 100644
index 00000000..a6b355f4
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/j6_prom.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "j6_prom.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/j6_prom.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/j6_prom.vhd
new file mode 100644
index 00000000..cc6c3558
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/j6_prom.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: j6_prom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY j6_prom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END j6_prom;
+
+
+ARCHITECTURE SYN OF j6_prom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(3 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6399-01j6.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 9,
+		width_a => 4,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6399-01j6.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6399-01j6.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL j6_prom_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/k6_prom.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/k6_prom.qip
new file mode 100644
index 00000000..9735dccb
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/k6_prom.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "k6_prom.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/k6_prom.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/k6_prom.vhd
new file mode 100644
index 00000000..5c772b25
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/k6_prom.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: k6_prom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY k6_prom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END k6_prom;
+
+
+ARCHITECTURE SYN OF k6_prom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(3 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6398-01k6.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 9,
+		width_a => 4,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6398-01k6.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6398-01k6.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL k6_prom_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom1.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom1.qip
new file mode 100644
index 00000000..ca8648de
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom1.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom1.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom1.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom1.vhd
new file mode 100644
index 00000000..0539e859
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom1.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: prog_rom1.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY prog_rom1 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END prog_rom1;
+
+
+ARCHITECTURE SYN OF prog_rom1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6290-01b1.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 11,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6290-01b1.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6290-01b1.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom2.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom2.qip
new file mode 100644
index 00000000..aefde75d
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom2.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom2.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom2.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom2.vhd
new file mode 100644
index 00000000..d2ee7a7e
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom2.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: prog_rom2.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY prog_rom2 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END prog_rom2;
+
+
+ARCHITECTURE SYN OF prog_rom2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6291-01c1.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 11,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6291-01c1.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6291-01c1.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom3.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom3.qip
new file mode 100644
index 00000000..562f4ad7
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom3.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom3.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom3.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom3.vhd
new file mode 100644
index 00000000..41a5470c
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom3.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: prog_rom3.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY prog_rom3 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END prog_rom3;
+
+
+ARCHITECTURE SYN OF prog_rom3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6404d1.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 11,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6404d1.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6404d1.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom4.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom4.qip
new file mode 100644
index 00000000..30906c90
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom4.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prog_rom4.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom4.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom4.vhd
new file mode 100644
index 00000000..b71ccb64
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/prog_rom4.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: prog_rom4.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY prog_rom4 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END prog_rom4;
+
+
+ARCHITECTURE SYN OF prog_rom4 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6405-02e1.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 11,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6405-02e1.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6405-02e1.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL prog_rom4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/sync_prom.qip b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/sync_prom.qip
new file mode 100644
index 00000000..9a31148f
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/sync_prom.qip	
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sync_prom.vhd"]
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/sync_prom.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/sync_prom.vhd
new file mode 100644
index 00000000..b078c62d
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/roms/sync_prom.vhd	
@@ -0,0 +1,141 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: sync_prom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY sync_prom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END sync_prom;
+
+
+ARCHITECTURE SYN OF sync_prom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(3 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./rtl/roms/6400-01m2.hex",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 8,
+		width_a => 4,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./rtl/roms/6400-01m2.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./rtl/roms/6400-01m2.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL sync_prom_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/scandoubler.sv b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/scandoubler.sv
new file mode 100644
index 00000000..0213d20c
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/scandoubler.sv	
@@ -0,0 +1,195 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2017 Sorgelig
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+// TODO: Delay vsync one line
+
+module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	// system interface
+	input             clk_sys,
+	input             ce_pix,
+	input             ce_pix_actual,
+
+	input             hq2x,
+
+	// shifter video interface
+	input             hs_in,
+	input             vs_in,
+	input             line_start,
+
+	input  [DWIDTH:0] r_in,
+	input  [DWIDTH:0] g_in,
+	input  [DWIDTH:0] b_in,
+	input             mono,
+
+	// output interface
+	output reg        hs_out,
+	output            vs_out,
+	output [DWIDTH:0] r_out,
+	output [DWIDTH:0] g_out,
+	output [DWIDTH:0] b_out
+);
+
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+assign vs_out = vs_in;
+
+reg  [2:0] phase;
+reg  [2:0] ce_div;
+reg  [7:0] pix_len = 0;
+wire [7:0] pl = pix_len + 1'b1;
+
+reg ce_x1, ce_x4;
+reg req_line_reset;
+wire ls_in = hs_in | line_start;
+always @(negedge clk_sys) begin
+	reg old_ce;
+	reg [2:0] ce_cnt;
+
+	reg [7:0] pixsz2, pixsz4 = 0;
+
+	old_ce <= ce_pix;
+	if(~&pix_len) pix_len <= pix_len + 1'd1;
+
+	ce_x4 <= 0;
+	ce_x1 <= 0;
+
+	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
+	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
+		phase <= phase + 1'd1;
+		ce_x4 <= 1;
+	end
+
+	if(~old_ce & ce_pix) begin
+		pixsz2 <= {1'b0,  pl[7:1]};
+		pixsz4 <= {2'b00, pl[7:2]};
+		ce_x1 <= 1;
+		ce_x4 <= 1;
+		pix_len <= 0;
+		phase <= phase + 1'd1;
+
+		ce_cnt <= ce_cnt + 1'd1;
+		if(ce_pix_actual) begin
+			phase <= 0;
+			ce_div <= ce_cnt + 1'd1;
+			ce_cnt <= 0;
+			req_line_reset <= 0;
+		end
+
+		if(ls_in) req_line_reset <= 1;
+	end
+end
+
+reg ce_sd;
+always @(*) begin
+	case(ce_div)
+		2: ce_sd = !phase[0];
+		4: ce_sd = !phase[1:0];
+		default: ce_sd <= 1;
+	endcase
+end
+
+`define BITS_TO_FIT(N) ( \
+     N <=   2 ? 0 : \
+     N <=   4 ? 1 : \
+     N <=   8 ? 2 : \
+     N <=  16 ? 3 : \
+     N <=  32 ? 4 : \
+     N <=  64 ? 5 : \
+     N <= 128 ? 6 : \
+     N <= 256 ? 7 : \
+     N <= 512 ? 8 : \
+     N <=1024 ? 9 : 10 )
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
+(
+	.clk(clk_sys),
+	.ce_x4(ce_x4 & ce_sd),
+	.inputpixel({b_in,g_in,r_in}),
+	.mono(mono),
+	.disable_hq2x(~hq2x),
+	.reset_frame(vs_in),
+	.reset_line(req_line_reset),
+	.read_y(sd_line),
+	.read_x(sd_h_actual),
+	.outpixel({b_out,g_out,r_out})
+);
+
+reg [10:0] sd_h_actual;
+always @(*) begin
+	case(ce_div)
+		2: sd_h_actual = sd_h[10:1];
+		4: sd_h_actual = sd_h[10:2];
+		default: sd_h_actual = sd_h;
+	endcase
+end
+
+reg [10:0] sd_h;
+reg  [1:0] sd_line;
+always @(posedge clk_sys) begin
+
+	reg [11:0] hs_max,hs_rise,hs_ls;
+	reg [10:0] hcnt;
+	reg [11:0] sd_hcnt;
+
+	reg hs, hs2, vs, ls;
+
+	if(ce_x1) begin
+		hs <= hs_in;
+		ls <= ls_in;
+
+		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
+
+		// falling edge of hsync indicates start of line
+		if(hs && !hs_in) begin
+			hs_max <= {hcnt,1'b1};
+			hcnt <= 0;
+			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
+		end else begin
+			hcnt <= hcnt + 1'd1;
+		end
+
+		// save position of rising edge
+		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
+
+		vs <= vs_in;
+		if(vs && ~vs_in) sd_line <= 0;
+	end
+
+	if(ce_x4) begin
+		hs2 <= hs_in;
+
+		// output counter synchronous to input and at twice the rate
+		sd_hcnt <= sd_hcnt + 1'd1;
+		sd_h    <= sd_h    + 1'd1;
+		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
+		if(sd_hcnt == hs_max) sd_hcnt <= 0;
+
+		// replicate horizontal sync at twice the speed
+		if(sd_hcnt == hs_max)  hs_out <= 0;
+		if(sd_hcnt == hs_rise) hs_out <= 1;
+
+		if(sd_hcnt == hs_ls)   sd_h    <= 0;
+		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/screech.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/screech.vhd
new file mode 100644
index 00000000..10dcab3e
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/screech.vhd	
@@ -0,0 +1,72 @@
+-- Tire screech sound generator for Kee Games Sprint 2 
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 7414 Schmitt trigger oscillator operating at approximately
+-- 1.2kHz producing a sawtooth with the frequency modulated slightly by the pseudo-random 
+-- noise generator. This is an extension of work initially done in Verilog by Jonas Elofsson.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity tire_screech is 
+generic(
+			constant Inc1 : integer := 24; -- These constants can be adjusted to tune the frequency and modulation
+			constant Inc2 : integer := 34;
+			constant Dec1 : integer := 23;
+			constant Dec2 : integer := 12
+			);
+port(		
+			Clk			: in  std_logic;  -- 750kHz from the horizontal line counter chain works well here
+			Noise			: in	std_logic;  -- Output from LFSR pseudo-random noise generator
+			Screech_out	: out std_logic	-- Screech output - single bit
+			);
+end tire_screech;
+
+architecture rtl of tire_screech is
+
+signal Screech_count	: integer range 1000 to 11000;
+signal Screech_state	: std_logic;
+
+begin
+
+Screech: process(Clk, Screech_state)
+begin
+	if rising_edge(Clk) then
+		if screech_state = '1' then -- screech_state is 1, counter is rising
+			if noise = '1' then 	-- Noise signal from LFSR, when high increases the slope of the rising ramp
+				screech_count <= screech_count + inc2;
+			else 						-- When Noise is low, decreas the slope of the ramp
+				screech_count <= screech_count + inc1; 
+			end if;
+			if screech_count > 10000 then -- Reverse the ramp direction when boundary value of 10,000 is reached
+				screech_state <= '0';
+			end if;
+		elsif screech_state = '0' then -- screech_state is now low, decrement the counter (ramp down)
+			if noise = '1' then 
+				screech_count <= screech_count - dec2; -- Slope is influenced by the Noise signal
+			else
+				screech_count <= screech_count - dec1;
+			end if;
+			if screech_count < 1000 then -- Reverse the ramp direction again when the lower boundary of 1,000 is crossed
+				screech_state <= '1';
+			end if;
+		end if;
+	end if;
+screech_out <= screech_state;
+end process;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint1.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint1.vhd
new file mode 100644
index 00000000..83424a60
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint1.vhd	
@@ -0,0 +1,313 @@
+-- Top level file for Kee Games Sprint 1 
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple
+-- See Sprint 1 manual for video output details. Resistor values listed here have been scaled 
+-- for 3.3V logic. 
+-- R48 1k Ohm
+-- R49 1k Ohm
+-- R50 680R
+-- R51 330R
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+
+entity sprint1 is 
+port(		
+			Clk_50_I		: in	std_logic;	-- 50MHz input clock
+			clk_12		: in	std_logic;	-- 12MHz input clock
+			Reset_n		: in	std_logic;	-- Reset button (Active low)
+			
+			
+			VideoW_O		: out std_logic;  -- White video output (680 Ohm)
+			VideoB_O		: out std_logic;	-- Black video output (1.2k)
+			Sync_O		: out std_logic;  -- Composite sync output (1.2k)
+			
+			
+			Hs				: out std_logic;
+			Vs				: out std_logic;
+			Vb				: out std_logic;			
+			Hb				: out std_logic;	
+			Video			: out std_logic;
+			
+			Audio			: out std_logic_vector(6 downto 0);
+			Coin1_I		: in  std_logic;  -- Coin switches (Active low)
+			Coin2_I		: in  std_logic;
+			Start_I		: in  std_logic;  -- Start button
+			Gas_I			: in  std_logic;	-- Gas pedal
+			Gear1_I		: in  std_logic;  -- Gear shifter, 4th gear = no other gear selected
+			Gear2_I		: in  std_logic;
+			Gear3_I		: in  std_logic;
+			Test_I		: in  std_logic;  -- Self-test switch
+			SteerA_I		: in  std_logic;	-- Steering wheel inputs, these are quadrature encoders
+			SteerB_I		: in	std_logic;
+			StartLamp_O	: out std_logic	-- Start button lamp
+			);
+end sprint1;
+
+architecture rtl of sprint1 is
+
+signal clk_6			: std_logic;
+signal phi1 			: std_logic;
+signal phi2				: std_logic;
+
+signal Hcount		   : std_logic_vector(8 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_s			: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+
+
+signal Vcount  		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+
+signal Vreset			: std_logic;
+signal Vblank_s		: std_logic;
+signal Vblank_n_s		: std_logic;
+signal Vblank			: std_logic;			
+signal Hblank			: std_logic;
+signal Hsync			: std_logic;
+signal Vsync			: std_logic;
+
+signal CompBlank_s	: std_logic;
+signal CompSync_n_s	: std_logic;
+
+signal WhitePF_n		: std_logic;
+signal BlackPF_n		: std_logic;
+
+signal Display			: std_logic_vector(7 downto 0);
+
+-- Address decoder
+signal addec_bus		: std_logic_vector(7 downto 0);
+signal RnW				: std_logic;
+signal Write_n			: std_logic;
+signal ROM1				: std_logic;
+signal ROM2				: std_logic;
+signal ROM3				: std_logic;
+signal WRAM				: std_logic;
+signal RAM_n			: std_logic;
+signal Sync_n			: std_logic;
+signal Switch_n		: std_logic;
+signal Collision1_n	: std_logic;
+signal Collision2_n	: std_logic;
+signal Display_n		: std_logic;
+signal TimerReset_n	: std_logic;
+signal CollRst1_n		: std_logic;
+signal CollRst2_n		: std_logic;
+signal SteerRst1_n	: std_logic;
+signal SteerRst2_n	: std_logic;
+signal NoiseRst_n		: std_logic;
+signal Attract			: std_logic;	
+signal Skid1			: std_logic;
+signal Skid2			: std_logic;
+
+signal Crash_n			: std_logic;
+signal Motor1_n 		: std_logic;
+signal Motor2_n		: std_logic;
+signal Car1				: std_logic;
+signal Car1_n			: std_logic;
+signal Car2				: std_logic;
+signal Car2_n			: std_logic;
+signal Car3_4_n		: std_logic;	
+
+signal NMI_n			: std_logic;
+
+signal Adr				: std_logic_vector(9 downto 0);
+
+signal SW1				: std_logic_vector(7 downto 0);
+
+signal Inputs			: std_logic_vector(1 downto 0);
+signal Collisions1	: std_logic_vector(1 downto 0);
+signal Collisions2	: std_logic_vector(1 downto 0);
+
+begin
+-- Configuration DIP switches, these can be brought out to external switches if desired
+-- See Sprint 2 manual page 11 for complete information. Active low (0 = On, 1 = Off)
+--    1 								Oil slicks			(0 - Oil slicks enabled)
+--			2							Cycle tracks      (0/1 - Cycle every lap/every two laps)
+--   			3	4					Coins per play		(00 - 1 Coin per player) 
+--						5				Extended Play		(0 - Extended Play enabled)
+--							6			Not used				(X - Don't care)
+--								7	8	Game time			(01 - 120 Seconds)
+SW1 <= "11000101"; -- Config dip switches
+		
+		
+Vid_sync: entity work.synchronizer
+port map(
+		clk_12 => clk_12,
+		clk_6 => clk_6,
+		hcount => hcount,
+		vcount => vcount,
+		hsync => hsync,
+		hblank => hblank,
+		vblank_s => vblank_s,
+		vblank_n_s => vblank_n_s,
+		vblank => vblank,
+		vsync => vsync,
+		vreset => vreset
+		);
+
+
+Background: entity work.playfield
+port map( 
+		clk6 => clk_6,
+		display => display,
+		HCount => HCount,
+		VCount => VCount,
+		HBlank => HBlank,		
+		H256_s => H256_s,
+		VBlank => VBlank,
+		VBlank_n_s => Vblank_n_s,
+		HSync => Hsync,
+		VSync => VSync,
+		CompSync_n_s => CompSync_n_s,
+		CompBlank_s => CompBlank_s,
+		WhitePF_n => WhitePF_n,
+		BlackPF_n => BlackPF_n 
+		);
+
+		
+Cars: entity work.motion
+port map(
+		CLK6 => clk_6,
+		CLK12 => clk_12,
+		PHI2 => phi2,
+		DISPLAY => Display,
+		H256_s => H256_s,
+		VCount => VCount,
+		HCount => HCount,
+		Crash_n => Crash_n,
+		Motor1_n => Motor1_n,
+		Car1 => Car1,
+		Car1_n => Car1_n,
+		Car2 => Car2,
+		Car2_n => Car2_n,
+		Car3_4_n => Car3_4_n	
+		);
+		
+		
+PF_Comparator: entity work.collision_detect
+port map(
+		Clk6 => Clk_6,
+		Car1 => Car1,
+		Car1_n => Car1_n,
+		Car2 => Car2,
+		Car2_n => Car2_n,
+		Car3_4_n	=> Car3_4_n,
+		WhitePF_n => WhitePF_n,
+		BlackPF_n => BlackPF_n,
+		CollRst1_n => CollRst1_n,
+		Collisions1 => Collisions1
+		);
+	
+	
+CPU: entity work.cpu_mem
+port map(
+		Clk12 => clk_12,
+		Clk6 => clk_6,
+		Reset_n => reset_n,
+		VCount => VCount,
+		HCount => HCount,
+		Hsync_n => not Hsync,
+		Vblank_s => Vblank_s,
+		Vreset => Vreset,
+		Test_n => not Test_I,
+		Attract => Attract,
+		Skid1 => Skid1,
+		Skid2 => Skid2,
+		NoiseReset_n => NoiseRst_n,
+		CollRst1_n => CollRst1_n,
+		CollRst2_n => CollRst2_n,
+		SteerRst1_n => SteerRst1_n,
+		Lamp1 => StartLamp_O,
+		Phi1_o => Phi1,
+		Phi2_o => Phi2,
+		Display => Display,
+		IO_Adr => Adr,
+		Collisions1 => Collisions1,
+		Collisions2 => Collisions2,
+		Inputs => Inputs
+		);
+
+
+Input: entity work.Control_Inputs
+port map(
+		clk6 => clk_6,
+		SW1 => SW1, -- DIP switches
+		Coin1_n => Coin1_I,
+		Coin2_n => Coin2_I,
+		Start => not Start_I, -- Active high in real hardware, inverting these makes more sense with the FPGA
+		Gas => not Gas_I,
+		Gear1 => not Gear1_I,
+		Gear2 => not Gear2_I,
+		Gear3 => not Gear3_I,
+		Self_Test => not Test_I,
+		Steering1A_n => SteerA_I,
+		Steering1B_n => SteerB_I,
+		SteerRst1_n => SteerRst1_n,
+		Adr => Adr,
+		Inputs => Inputs
+	);	
+
+	
+Sound: entity work.audio
+port map( 
+		Clk_50 => Clk_50_I,
+		Clk_6 => Clk_6,
+		Reset_n => Reset_n,
+		Motor1_n => Motor1_n,
+		Skid1 => Skid1,
+		Crash_n => Crash_n,
+		NoiseReset_n => NoiseRst_n,
+		Attract => Attract,
+		Display => Display,
+		HCount => HCount,
+		VCount => VCount,
+		Audio1 => Audio
+		);
+
+-- Video mixing	
+VideoB_O <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s;	
+VideoW_O <= not(WhitePF_n and Car1_n);  
+Sync_O <= CompSync_n_s;
+
+Vb <= VBLANK;
+Hb <= HBLANK;
+Hs <= Hsync;
+Vs <= Vsync;
+Video <= (WhitePF_n and blackpf_n and car1_n and Car2_n and Car3_4_n) nor CompBlank_s;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2.vhd
new file mode 100644
index 00000000..d147f567
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2.vhd	
@@ -0,0 +1,338 @@
+-- Top level file for Kee Games Sprint 2 
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple
+-- See Sprint 2 manual for video output details. Resistor values listed here have been scaled 
+-- for 3.3V logic. 
+-- R48 1k Ohm
+-- R49 1k Ohm
+-- R50 680R
+-- R51 330R
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+
+entity sprint2 is 
+port(		
+			clk_12		: in	std_logic;	-- 12MHz input clock
+			Reset_n		: in	std_logic;	-- Reset button (Active low)
+			VideoW_O		: out std_logic;  -- White video output (680 Ohm)
+			VideoB_O		: out std_logic;	-- Black video output (1.2k)
+			Sync_O		: out std_logic;  -- Composite sync output (1.2k)
+			Audio1_O		: out std_logic_vector(6 downto 0);  -- Ideally this should have a simple low pass filter
+			Audio2_O		: out std_logic_vector(6 downto 0);
+			
+			Hs				: out std_logic;
+			Vs				: out std_logic;
+			Vb				: out std_logic;			
+			Hb				: out std_logic;	
+			Video			: out std_logic;
+
+			Coin1_I		: in  std_logic;  -- Coin switches (Active low)
+			Coin2_I		: in  std_logic;
+			Start1_I		: in  std_logic;  -- Start buttons
+			Start2_I		: in  std_logic;
+			Trak_Sel_I	: in  std_logic;  -- Track select button 
+			Gas1_I		: in  std_logic;	-- Gas pedals 
+			Gas2_I		: in  std_logic;
+			Gear1_1_I	: in  std_logic;  -- Gear shifters, 4th gear = no other gear selected
+			Gear1_2_I	: in  std_logic;
+			Gear2_1_I	: in  std_logic;
+			Gear2_2_I	: in  std_logic;
+			Gear3_1_I	: in  std_logic;
+			Gear3_2_I	: in  std_logic;
+			Test_I		: in  std_logic;  -- Self-test switch
+			Steer_1A_I	: in  std_logic;	-- Steering wheel inputs, these are quadrature encoders
+			Steer_1B_I	: in	std_logic;
+			Steer_2A_I	: in	std_logic;
+			Steer_2B_I	: in 	std_logic;
+			Lamp1_O		: out std_logic;	-- Player 1 and 2 start button LEDs
+			Lamp2_O		: out std_logic
+			);
+end sprint2;
+
+architecture rtl of sprint2 is
+
+signal clk_6			: std_logic;
+signal phi1 			: std_logic;
+signal phi2				: std_logic;
+
+signal Hcount		   : std_logic_vector(8 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_s			: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+signal Hsync			: std_logic;
+signal Vsync			: std_logic;
+
+signal Vcount  		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+signal Vblank			: std_logic;
+signal Vreset			: std_logic;
+signal Vblank_s		: std_logic;
+signal Vblank_n_s		: std_logic;
+signal HBlank			: std_logic;
+
+signal CompBlank_s	: std_logic;
+signal CompSync_n_s	: std_logic;
+
+signal WhitePF_n		: std_logic;
+signal BlackPF_n		: std_logic;
+
+signal Display			: std_logic_vector(7 downto 0);
+
+
+-- Address decoder
+signal addec_bus		: std_logic_vector(7 downto 0);
+signal RnW				: std_logic;
+signal Write_n			: std_logic;
+signal ROM1				: std_logic;
+signal ROM2				: std_logic;
+signal ROM3				: std_logic;
+signal WRAM				: std_logic;
+signal RAM_n			: std_logic;
+signal Sync_n			: std_logic;
+signal Switch_n		: std_logic;
+signal Collision1_n	: std_logic;
+signal Collision2_n	: std_logic;
+signal Display_n		: std_logic;
+signal TimerReset_n	: std_logic;
+signal CollRst1_n		: std_logic;
+signal CollRst2_n		: std_logic;
+signal SteerRst1_n	: std_logic;
+signal SteerRst2_n	: std_logic;
+signal NoiseRst_n		: std_logic;
+signal Attract			: std_logic := '1';	
+signal Skid1			: std_logic;
+signal Skid2			: std_logic;
+signal Lamp1			: std_logic;
+signal Lamp2			: std_logic;
+
+signal Crash_n			: std_logic;
+signal Motor1_n 		: std_logic;
+signal Motor2_n		: std_logic;
+signal Car1				: std_logic;
+signal Car1_n			: std_logic;
+signal Car2				: std_logic;
+signal Car2_n			: std_logic;
+signal Car3_4_n		: std_logic;	
+
+signal NMI_n			: std_logic;
+
+signal Adr				: std_logic_vector(9 downto 0);
+
+signal SW1				: std_logic_vector(7 downto 0);
+
+signal Inputs			: std_logic_vector(1 downto 0);
+signal Collisions1	: std_logic_vector(1 downto 0);
+signal Collisions2	: std_logic_vector(1 downto 0);
+
+
+begin
+-- Configuration DIP switches, these can be brought out to external switches if desired
+-- See Sprint 2 manual page 11 for complete information. Active low (0 = On, 1 = Off)
+--    1 								Oil slicks			(0 - Oil slicks enabled)
+--			2							Cycle tracks      (1 - Cycle through all tracks in attract mode)
+--   			3	4					Coins per play		(00 - 1 Coin per player) 
+--						5				Extended Play		(0 - Extended Play enabled)
+--							6			Not used				(X - Don't care)
+--								7	8	Game time			(01 - 120 Seconds)
+SW1 <= "01000101"; -- Config dip switches
+		
+		
+Vid_sync: entity work.synchronizer
+port map(
+		clk_12 => clk_12,
+		clk_6 => clk_6,
+		hcount => hcount,
+		vcount => vcount,
+		hsync => hsync,
+		hblank => hblank,
+		vblank_s => vblank_s,
+		vblank_n_s => vblank_n_s,
+		vblank => vblank,
+		vsync => vsync,
+		vreset => vreset
+		);
+
+
+Background: entity work.playfield
+port map( 
+		clk6 => clk_6,
+		display => display,
+		HCount => HCount,
+		VCount => VCount,
+		HBlank => HBlank,		
+		H256_s => H256_s,
+		VBlank => VBlank,
+		VBlank_n_s => Vblank_n_s,
+		HSync => Hsync,
+		VSync => VSync,
+		CompSync_n_s => CompSync_n_s,
+		CompBlank_s => CompBlank_s,
+		WhitePF_n => WhitePF_n,
+		BlackPF_n => BlackPF_n 
+		);
+
+		
+Cars: entity work.motion
+port map(
+		CLK6 => clk_6,
+		CLK12 => clk_12,
+		PHI2 => phi2,
+		DISPLAY => Display,
+		H256_s => H256_s,
+		VCount => VCount,
+		HCount => HCount,
+		Crash_n => Crash_n,
+		Motor1_n => Motor1_n,
+		Motor2_n => Motor2_n,
+		Car1 => Car1,
+		Car1_n => Car1_n,
+		Car2 => Car2,
+		Car2_n => Car2_n,
+		Car3_4_n => Car3_4_n	
+		);
+		
+		
+PF_Comparator: entity work.collision_detect
+port map(	
+		Clk6 => clk_6,
+		Car1 => Car1,
+		Car1_n => Car1_n,
+		Car2 => Car2,
+		Car2_n => Car2_n,
+		Car3_4_n	=> Car3_4_n,
+		WhitePF_n => WhitePF_n,
+		BlackPF_n => BlackPF_n,
+		CollRst1_n => CollRst1_n,
+		CollRst2_n => CollRst2_n,
+		Collisions1 => Collisions1,
+		Collisions2 => Collisions2
+		);
+	
+	
+CPU: entity work.cpu_mem
+port map(
+		Clk12 => clk_12,
+		Clk6 => clk_6,
+		Reset_n => reset_n,
+		VCount => VCount,
+		HCount => HCount,
+		Hsync_n => not Hsync,
+		Vblank_s => Vblank_s,
+		Vreset => Vreset,
+		Test_n => not Test_I,
+		Attract => Attract,
+		Skid1 => Skid1,
+		Skid2 => Skid2,
+		NoiseReset_n => NoiseRst_n,
+		CollRst1_n => CollRst1_n,
+		CollRst2_n => CollRst2_n,
+		SteerRst1_n => SteerRst1_n,
+		SteerRst2_n => SteerRst2_n,
+		Lamp1 => Lamp1_O,
+		Lamp2 => Lamp2_O,
+		Phi1_o => Phi1,
+		Phi2_o => Phi2,
+		Display => Display,
+		IO_Adr => Adr,
+		Collisions1 => Collisions1,
+		Collisions2 => Collisions2,
+		Inputs => Inputs
+		);
+
+
+Input: entity work.Control_Inputs
+port map(
+		clk6 => clk_6,
+		SW1 => SW1, -- DIP switches
+		Coin1_n => Coin1_I,
+		Coin2_n => Coin2_I,
+		Start1 => not Start1_I, -- Active high in real hardware, inverting these makes more sense with the FPGA
+		Start2 => not Start2_I,
+		Trak_Sel => not Trak_Sel_I,
+		Gas1 => not Gas1_I,
+		Gas2 => not Gas2_I,
+		Gear1_1 => not Gear1_1_I,
+		Gear1_2 => not Gear1_2_I,
+		Gear2_1 => not Gear2_1_I,
+		Gear2_2 => not Gear2_2_I,
+		Gear3_1 => not Gear3_1_I,
+		Gear3_2 => not Gear3_2_I,
+		Self_Test => not Test_I,
+		Steering1A_n => Steer_1A_I,
+		Steering1B_n => Steer_1B_I,
+		Steering2A_n => Steer_2A_I,
+		Steering2B_n => Steer_2B_I,
+		SteerRst1_n => SteerRst1_n,
+		SteerRst2_n => SteerRst2_n,
+		Adr => Adr,
+		Inputs => Inputs
+	);	
+
+	
+Sound: entity work.audio
+port map( 
+		Clk_6 => Clk_6,
+		Reset_n => Reset_n,
+		Motor1_n => Motor1_n,
+		Motor2_n => Motor2_n,
+		Skid1 => Skid1,
+		Skid2 => Skid2,
+		Crash_n => Crash_n,
+		NoiseReset_n => NoiseRst_n,
+		Attract => Attract,
+		Display => Display,
+		HCount => HCount,
+		VCount => VCount,
+		Audio1 => Audio1_O,
+		Audio2 => Audio2_O
+		);
+
+-- Video mixing	
+VideoB_O <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s;	
+VideoW_O <= not(WhitePF_n and Car1_n and Car3_4_n);  
+Sync_O <= CompSync_n_s;
+
+
+Vb <= VBLANK;
+Hb <= HBLANK;
+Hs <= Hsync;
+Vs <= Vsync;
+Video <= (WhitePF_n and blackpf_n and car1_n and Car2_n and Car3_4_n) nor CompBlank_s;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2_mist.sv b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2_mist.sv
new file mode 100644
index 00000000..eef9fcb4
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2_mist.sv	
@@ -0,0 +1,157 @@
+module sprint2_mist(
+	output        LED,
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.sv" 
+
+localparam CONF_STR = {
+	"Sprint2;;",
+	"O1,Test Mode,Off,On;",
+	"T2,Next Track;",
+	"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+	"T6,Reset;",
+	"V,v1.00.",`BUILD_DATE
+};
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [9:0] kbjoy;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoubler_disable;
+wire        ypbpr;
+wire        ps2_kbd_clk, ps2_kbd_data;
+wire  [6:0] audio1, audio2;
+wire			video;
+
+wire clk_48, clk_12;
+wire locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.c0(clk_48),
+	.c1(clk_12),
+	.locked(locked)
+);
+
+wire led1, led2;
+assign LED = (led1 | led2);
+
+sprint2 sprint2 (
+	.clk_12(clk_12),
+	.Reset_n(~(status[0] | status[6] | buttons[1])),
+	.VideoW_O(),
+	.VideoB_O(),
+	.Sync_O(),					
+	.Hs(hs),
+	.Vs(vs),
+	.Vb(vb),		
+	.Hb(hb),
+	.Video(video),			
+	.Audio1_O(audio1),
+	.Audio2_O(audio2),
+	.Coin1_I(~kbjoy[7]),
+	.Coin2_I(~kbjoy[7]),
+	.Start1_I(~kbjoy[5]),
+	.Start2_I(~kbjoy[6]),
+	.Trak_Sel_I(~status[2]),
+	.Gas1_I(~kbjoy[4]),
+	.Gas2_I(),
+//	.Gear1_1_I(),//                                                                                                                                                                                                                                                                                                           Gear shifters, 4th gear = no other gear selected
+//	.Gear1_2_I(),
+//	.Gear1_3_I(),
+//	.Gear2_1_I(),
+//	.Gear2_2_I(),
+//	.Gear2_3_I(),
+	.Test_I(~status[1]),
+	.Steer_1A_I(~kbjoy[1]),// Steering wheel inputs, these are quadrature encoders
+	.Steer_1B_I(~kbjoy[0]),
+//	.Steer_2A_I(),
+//	.Steer_2B_I(),
+	.Lamp1_O(led1),
+	.Lamp2_O(led2)
+);
+
+dac dac (
+	.CLK(clk_48),
+	.RESET(1'b0),
+	.DACin({audio1, audio2}),
+	.DACout(AUDIO_L)
+	);
+
+assign AUDIO_R = AUDIO_L;
+
+wire hs, vs;
+wire hb, vb;
+wire blankn = ~(hb | vb);
+video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
+(
+	.clk_sys(clk_48),
+	.ce_pix(clk_12),
+	.ce_pix_actual(clk_12),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(blankn ? {video,video,video} : "000"),
+	.G(blankn ? {video,video,video} : "000"),
+	.B(blankn ? {video,video,video} : "000"),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoubler_disable),
+	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
+	.hq2x(status[4:3]==1),
+	.ypbpr_full(1),
+	.line_start(0),
+	.mono(0)
+);
+
+mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
+(
+	.clk_sys        (clk_48   	     ),
+	.conf_str       (CONF_STR       ),
+	.SPI_SCK        (SPI_SCK        ),
+	.CONF_DATA0     (CONF_DATA0     ),
+	.SPI_SS2			 (SPI_SS2        ),
+	.SPI_DO         (SPI_DO         ),
+	.SPI_DI         (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches   	 (switches       ),
+	.scandoubler_disable(scandoubler_disable),
+	.ypbpr          (ypbpr          ),
+	.ps2_kbd_clk    (ps2_kbd_clk    ),
+	.ps2_kbd_data   (ps2_kbd_data   ),
+	.joystick_0   	 (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+);
+
+keyboard keyboard(
+	.clk(clk_48),
+	.reset(),
+	.ps2_kbd_clk(ps2_kbd_clk),
+	.ps2_kbd_data(ps2_kbd_data),
+	.joystick(kbjoy)
+	);
+
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2_sound.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2_sound.vhd
new file mode 100644
index 00000000..f0bd0765
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sprint2_sound.vhd	
@@ -0,0 +1,245 @@
+-- Audio for Sprint 2
+-- First attempt at modeling the analog sound circuits used in Sprint 2, may be room for improvement as
+-- I do not have a real board to compare.
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity audio is 
+port(		
+			Clk_6				: in  std_logic;
+			Reset_n			: in	std_logic;
+			Motor1_n			: in	std_logic;
+			Motor2_n			: in  std_logic;
+			Skid1				: in  std_logic;
+			Skid2				: in  std_logic;
+			Crash_n			: in  std_logic;
+			NoiseReset_n	: in  std_logic;
+			Attract			: in  std_logic;
+			Display			: in	std_logic_vector(7 downto 0);
+			HCount			: in  std_logic_vector(8 downto 0);
+			VCount			: in  std_logic_vector(7 downto 0);
+			Audio1			: out std_logic_vector(6 downto 0);
+			Audio2	   	: out std_logic_vector(6 downto 0)
+			);
+end audio;
+
+architecture rtl of audio is
+
+signal reset			: std_logic;
+
+signal H4				: std_logic;
+signal V2				: std_logic;
+
+signal Noise			: std_logic;
+signal Noise_Shift	: std_logic_vector(15 downto 0);
+signal Shift_in  		: std_logic;
+
+signal Screech_count	: integer range 1000 to 11000;
+signal Screech_state	: std_logic;
+signal Screech_snd1	: std_logic;
+signal Screech_snd2	: std_logic;
+signal Screech1		: std_logic_vector(3 downto 0);
+signal Screech2		: std_logic_vector(3 downto 0);
+
+signal Crash			: std_logic_vector(3 downto 0);
+signal Bang				: std_logic_vector(3 downto 0);
+
+signal Mtr1_Freq		: std_logic_vector(3 downto 0);
+signal Mtr2_Freq		: std_logic_vector(3 downto 0);
+signal Motor1_speed	: std_logic_vector(3 downto 0);
+signal Motor1_snd		: std_logic_vector(5 downto 0);
+signal Motor2_speed	: std_logic_vector(3 downto 0);
+signal Motor2_snd		: std_logic_vector(5 downto 0);
+
+signal ena_count		: std_logic_vector(10 downto 0);
+signal ena_3k			: std_logic;
+
+signal bang_prefilter     : std_logic_vector(3 downto 0);
+signal bang_filter_t1     : std_logic_vector(3 downto 0);
+signal bang_filter_t2     : std_logic_vector(3 downto 0);
+signal bang_filter_t3     : std_logic_vector(3 downto 0);
+signal bang_filtered      : std_logic_vector(5 downto 0);
+
+
+begin
+
+-- HCount
+-- (0) 1H 	3 MHz
+-- (1) 2H   1.5MHz
+-- (2) 4H	750 kHz
+-- (3) 8H	375 kHz
+-- (4) 16H	187 kHz
+-- (5) 32H	93 kHz
+-- (6) 64H	46 kHz
+-- (7) 128H 23 kHz
+-- (8) 256H 12 kHz
+
+reset <= (not reset_n);
+
+H4 <= HCount(2);
+V2 <= VCount(1);
+
+-- Generate the 3kHz clock enable used by the filter
+Enable: process(clk_6)
+begin
+	if rising_edge(CLK_6) then
+		ena_count <= ena_count + "1";
+		ena_3k <= '0';
+		if (ena_count(10 downto 0) = "00000000000") then
+			ena_3k <= '1';
+		end if;
+	end if;
+end process;
+
+
+-- LFSR that generates pseudo-random noise
+Noise_gen: process(NoiseReset_n, V2)
+begin
+	if (noisereset_n = '0') then
+		noise_shift <= (others => '0');
+		noise <= '0';
+	elsif rising_edge(V2) then
+		shift_in <= not(noise_shift(6) xor noise_shift(8));
+		noise_shift <= shift_in & noise_shift(15 downto 1);
+		noise <= noise_shift(0); 
+	end if;
+end process;
+
+
+-- Tire screech sound for player 1 and 2 cars. These can be tuned slightly differently to model variations in analog sound hardware.
+Screech_gen1: entity work.tire_screech
+generic map( -- These values can be tweaked to tune the screech sound
+		Inc1 => 24, -- Ramp increase rate when noise = 0
+		Inc2 => 33, -- Ramp increase rate when noise = 1
+		Dec1 => 29, -- Ramp decrease rate when noise = 0
+		Dec2 => 16  -- Ramp decrease rate when noise = 1
+		)
+port map(
+		Clk => H4,
+		Noise => noise,
+		Screech_out => screech_snd1
+		);
+		
+		
+Screech_gen2: entity work.tire_screech
+generic map( -- These values can be tweaked to tune the screech sound
+		Inc1 => 24, -- Ramp increase rate when noise = 0
+		Inc2 => 34, -- Ramp increase rate when noise = 1
+		Dec1 => 23, -- Ramp decrease rate when noise = 0
+		Dec2 => 12  -- Ramp decrease rate when noise = 1
+		)
+port map(
+		Clk => H4,
+		Noise => noise,
+		Screech_out => screech_snd2
+		);
+
+-- Convert screech from 1 bit to 4 bits wide and enable via skid1 and skid2 signals
+Screech_ctrl: process(screech_snd1, screech_snd2, skid1, skid2)
+begin
+	if (skid1 and screech_snd1) = '1' then
+		screech1 <= "1111";
+	else
+		screech1 <= "0000";
+	end if;
+	
+	if (skid2 and screech_snd2) = '1' then
+		screech2 <= "1111";
+	else
+		screech2 <= "0000";
+	end if;
+end process;
+		
+	
+Crash_sound: process(crash_n, crash, display, noise)		
+begin
+	if crash_n = '0' then
+		crash <= display(3 downto 0);
+	end if;
+	if noise = '1' then
+		bang_prefilter <= crash;
+	else
+		bang_prefilter <= "0000";
+	end if;
+end process;
+
+---- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Crash_filter: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		if (ena_3k = '1') then
+			bang_filter_t1 <= bang_prefilter;
+			bang_filter_t2 <= bang_filter_t1;
+			bang_filter_t3 <= bang_filter_t2;
+		end if;
+		bang_filtered <=  ("00" & bang_filter_t1) +
+								('0'  & bang_filter_t2 & '0') +
+								("00" & bang_filter_t3);
+	end if;
+end process;	
+
+
+Motor1_latch: process(Motor1_n, Display)
+begin
+	if Motor1_n = '0' then
+		Motor1_speed <= Display(3 downto 0);
+	end if;
+end process;
+
+Motor1: entity work.EngineSound 
+generic map( 
+		Freq_tune => 50 -- Tuning pot for engine sound frequency
+		)
+port map(		
+		Clk_6 => clk_6, 
+		Ena_3k => ena_3k,
+		EngineData => motor1_speed,
+		Motor => motor1_snd
+		);
+	
+
+Motor2_latch: process(Motor2_n, Display)
+begin
+	if Motor2_n = '0' then
+		Motor2_speed <= Display(3 downto 0);
+	end if;
+end process;
+	
+Motor2: entity work.EngineSound 
+generic map( 
+		Freq_tune => 48 -- Tuning pot for engine sound frequency
+		)
+port map(		
+		Clk_6 => clk_6, 
+		Ena_3k => ena_3k,
+		EngineData => motor2_speed,
+		Motor => motor2_snd
+		);		
+	
+	
+-- Audio mixer, also mutes sound in attract mode
+Audio1 <= ('0' & motor1_snd) + ("00" & screech1) + ('0' & bang_filtered);-- when attract = '0'
+				--else "0000000";
+				
+Audio2 <= ('0' & motor2_snd) + ("00" & screech2) + ('0' & bang_filtered);-- when attract = '0'
+				--else "0000000";	
+		
+
+
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sync.vhd b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sync.vhd
new file mode 100644
index 00000000..544cee27
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/sync.vhd	
@@ -0,0 +1,177 @@
+-- Video synchronizer circuit for Sprint 2
+-- Similar circuit used in many other Atari and Kee Games arcade games
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity synchronizer is 
+port(		
+			clk_12		: in	std_logic;
+			clk_6			: out	std_logic;
+			hcount		: out	std_logic_vector(8 downto 0);
+			vcount		: out	std_logic_vector(7 downto 0);
+		   hsync			: out	std_logic;
+			hblank		: out std_logic;
+			vblank_s		: out std_logic;
+			vblank_n_s	: out std_logic;
+			vblank		: out	std_logic;
+			vsync			: out std_logic;
+			vreset		: out	std_logic);
+end synchronizer;
+
+architecture rtl of synchronizer is
+
+signal h_counter		: std_logic_vector(9 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+signal v_counter		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+signal sync_bus		: std_logic_vector(3 downto 0) := (others => '0');
+signal sync_reg		: std_logic_vector(3 downto 0) := (others => '0');
+signal vblank_int		: std_logic := '0';
+signal vreset_n		: std_logic := '0';
+
+signal hblank_int		: std_logic := '0';
+signal hsync_int		: std_logic := '0';
+signal hsync_reset 	: std_logic := '0';
+
+
+begin
+
+-- Horizontal counter is 9 bits long plus additional flip flop. The last 4 bit IC in the chain resets to 0010 so total count resets to 128 
+-- using only the last three count states
+H_count: process(clk_12)
+begin
+	if rising_edge(clk_12) then
+		if h_counter = "1111111111" then
+			h_counter <= "0100000000";
+		else
+			h_counter <= h_counter + 1;
+		end if;
+	end if;
+end process;
+
+-- Vertical counter is 8 bits, clocked by the rising edge of H256 at the end of each horizontal line
+V_count: process(hsync_int)
+begin
+	if rising_edge(Hsync_int) then
+		if vreset_n = '0' then
+			v_counter <= (others => '0');
+		else
+			v_counter <= v_counter + '1';
+		end if;
+	end if;
+end process;
+
+-- Many Atari raster games use a 256 x 4 bit prom to decode vertical sync signals
+-- This could be replaced by combinatorial logic
+M2: entity work.sync_prom
+port map(
+		clock => clk_12, 
+		address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
+		q => sync_bus
+		);
+
+-- Register fed by the sync PROM, in the original hardware this also creates the complements of these signals
+sync_register: process(hsync_int)
+begin
+	if rising_edge(hsync_int) then
+		sync_reg <= sync_bus;
+	end if;
+end process;
+
+-- Outputs of sync PROM
+vblank_s <= sync_reg(3);
+vblank_n_s <= not sync_reg(3);
+vreset <= sync_reg(2);
+vreset_n <= not sync_reg(2);
+vblank <= sync_reg(1);
+vsync <= sync_reg(0);
+
+-- A pair of D type flip-flops that generate the Hsync signal
+Hsync_1: process(H256_n, H32)
+begin	
+	if H256_n = '0' then	
+		hblank_int <= '0';
+	else
+		if rising_edge(H32) then
+			hblank_int <= not H64;
+		end if;
+	end if;
+end process;
+
+Hsync_2: process(hblank_int, H8) 
+begin
+	if hblank_int = '0' then
+		hsync_int <= '0';
+	else
+		if rising_edge(H8) then
+			hsync_int <= H32;
+		end if;
+	end if;
+end process;
+
+-- Assign various signals
+clk_6 <= h_counter(0);
+H1 <= h_counter(1);
+H2 <= h_counter(2);
+H4 <= h_counter(3);
+H8 <= h_counter(4);
+H16 <=  h_counter(5);
+H32 <= h_counter(6);
+H64 <= h_counter(7);
+H128 <= h_counter(8);
+H256 <= h_counter(9);
+H4_n <= not H4;
+H8_n <= not H8;
+H256_n <= not H256;
+
+V1 <= v_counter(0);
+V2 <= v_counter(1);
+V4 <= v_counter(2);
+V8 <= v_counter(3);
+V16 <= v_counter(4);
+V32 <= v_counter(5);
+V64 <= v_counter(6);
+V128 <= v_counter(7);
+
+hcount <= h_counter(9 downto 1);
+vcount <= v_counter;
+hsync <= hsync_int;
+hblank <= hblank_int;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/video_mixer.sv b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/video_mixer.sv
new file mode 100644
index 00000000..04cfd4ba
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/rtl/video_mixer.sv	
@@ -0,0 +1,242 @@
+//
+//
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+//
+// LINE_LENGTH: Length of  display line in pixels
+//              Usually it's length from HSync to HSync.
+//              May be less if line_start is used.
+//
+// HALF_DEPTH:  If =1 then color dept is 3 bits per component
+//              For half depth 6 bits monochrome is available with
+//              mono signal enabled and color = {G, R}
+
+module video_mixer
+#(
+	parameter LINE_LENGTH  = 768,
+	parameter HALF_DEPTH   = 0,
+
+	parameter OSD_COLOR    = 3'd4,
+	parameter OSD_X_OFFSET = 10'd0,
+	parameter OSD_Y_OFFSET = 10'd0
+)
+(
+	// master clock
+	// it should be multiple by (ce_pix*4).
+	input        clk_sys,
+	
+	// Pixel clock or clock_enable (both are accepted).
+	input        ce_pix,
+
+	// Some systems have multiple resolutions.
+	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
+	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
+	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
+	input        ce_pix_actual,
+
+	// OSD SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// scanlines (00-none 01-25% 10-50% 11-75%)
+	input  [1:0] scanlines,
+
+	// 0 = HVSync 31KHz, 1 = CSync 15KHz
+	input        scandoubler_disable,
+
+	// High quality 2x scaling
+	input        hq2x,
+
+	// YPbPr always uses composite sync
+	input        ypbpr,
+
+	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
+	input        ypbpr_full,
+
+	// color
+	input [DWIDTH:0] R,
+	input [DWIDTH:0] G,
+	input [DWIDTH:0] B,
+
+	// Monochrome mode (for HALF_DEPTH only)
+	input            mono,
+
+	// interlace sync. Positive pulses.
+	input        HSync,
+	input        VSync,
+
+	// Falling of this signal means start of informative part of line.
+	// It can be horizontal blank signal.
+	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
+	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
+	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
+	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
+	// before first informative pixel.
+	input        line_start,
+
+	// MiST video output signals
+	output [5:0] VGA_R,
+	output [5:0] VGA_G,
+	output [5:0] VGA_B,
+	output       VGA_VS,
+	output       VGA_HS
+);
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+wire [DWIDTH:0] R_sd;
+wire [DWIDTH:0] G_sd;
+wire [DWIDTH:0] B_sd;
+wire hs_sd, vs_sd;
+
+scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
+(
+	.*,
+	.hs_in(HSync),
+	.vs_in(VSync),
+	.r_in(R),
+	.g_in(G),
+	.b_in(B),
+
+	.hs_out(hs_sd),
+	.vs_out(vs_sd),
+	.r_out(R_sd),
+	.g_out(G_sd),
+	.b_out(B_sd)
+);
+
+wire [DWIDTH:0] rt  = (scandoubler_disable ? R : R_sd);
+wire [DWIDTH:0] gt  = (scandoubler_disable ? G : G_sd);
+wire [DWIDTH:0] bt  = (scandoubler_disable ? B : B_sd);
+
+generate
+	if(HALF_DEPTH) begin
+		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
+		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
+		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
+	end else begin
+		wire [5:0] r  = rt;
+		wire [5:0] g  = gt;
+		wire [5:0] b  = bt;
+	end
+endgenerate
+
+wire       hs = (scandoubler_disable ? HSync : hs_sd);
+wire       vs = (scandoubler_disable ? VSync : vs_sd);
+
+reg scanline = 0;
+always @(posedge clk_sys) begin
+	reg old_hs, old_vs;
+	
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) scanline <= ~scanline;
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire [5:0] r_out, g_out, b_out;
+always @(*) begin
+	case(scanlines & {scanline, scanline})
+		1: begin // reduce 25% = 1/2 + 1/4
+			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
+			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
+			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
+		end
+
+		2: begin // reduce 50% = 1/2
+			r_out = {1'b0, r[5:1]};
+			g_out = {1'b0, g[5:1]};
+			b_out = {1'b0, b[5:1]};
+		end
+
+		3: begin // reduce 75% = 1/4
+			r_out = {2'b00, r[5:2]};
+			g_out = {2'b00, g[5:2]};
+			b_out = {2'b00, b[5:2]};
+		end
+
+		default: begin
+			r_out = r;
+			g_out = g;
+			b_out = b;
+		end
+	endcase
+end
+
+wire [5:0] red, green, blue;
+osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
+(
+	.*,
+
+	.R_in(r_out),
+	.G_in(g_out),
+	.B_in(b_out),
+	.HSync(hs),
+	.VSync(vs),
+
+	.R_out(red),
+	.G_out(green),
+	.B_out(blue)
+);
+
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+// http://marsee101.blog19.fc2.com/blog-entry-2311.html
+// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
+// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
+// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
+assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
+assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
+assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
+assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/snapshot/sprint2.rbf b/Arcade_MiST/Custom Hardware/Sprint2_MiST/snapshot/sprint2.rbf
new file mode 100644
index 0000000000000000000000000000000000000000..1a2d62dc7346bf60cf839fa348c514f06345bb09
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diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.qpf b/Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.qpf
new file mode 100644
index 00000000..ed1cbb49
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 19:51:47  November 12, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "19:51:47  November 12, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "sprint2"
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.qsf b/Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.qsf
new file mode 100644
index 00000000..291514ff
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.qsf	
@@ -0,0 +1,186 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 15:18:38  May 31, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		sprint1_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16  OCTOBER 10, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY sprint2_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# ---------------------
+# start ENTITY(sprint1)
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+# end ENTITY(sprint1)
+# -------------------
+
+# --------------------------
+# start ENTITY(sprint1_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(sprint1_mist)
+# ------------------------
+set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
+set_global_assignment -name VHDL_FILE rtl/sprint2.vhd
+set_global_assignment -name VHDL_FILE rtl/sync.vhd
+set_global_assignment -name VHDL_FILE rtl/playfield.vhd
+set_global_assignment -name VHDL_FILE rtl/motion.vhd
+set_global_assignment -name VHDL_FILE rtl/collision.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd
+set_global_assignment -name VHDL_FILE rtl/Inputs.vhd
+set_global_assignment -name VHDL_FILE rtl/sprint2_sound.vhd
+set_global_assignment -name QIP_FILE rtl/ram1k_dp.qip
+set_global_assignment -name VHDL_FILE rtl/screech.vhd
+set_global_assignment -name VHDL_FILE rtl/EngineSound.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprint2_mist.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name QIP_FILE rtl/roms/addec_prom.qip
+set_global_assignment -name QIP_FILE rtl/roms/Char_LSB.qip
+set_global_assignment -name QIP_FILE rtl/roms/Char_MSB.qip
+set_global_assignment -name QIP_FILE rtl/roms/j6_prom.qip
+set_global_assignment -name QIP_FILE rtl/roms/k6_prom.qip
+set_global_assignment -name QIP_FILE rtl/roms/prog_rom1.qip
+set_global_assignment -name QIP_FILE rtl/roms/prog_rom2.qip
+set_global_assignment -name QIP_FILE rtl/roms/prog_rom3.qip
+set_global_assignment -name QIP_FILE rtl/roms/prog_rom4.qip
+set_global_assignment -name QIP_FILE rtl/roms/sync_prom.qip
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.srf b/Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.srf
new file mode 100644
index 00000000..e2f3a55c
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/Sprint2_MiST/sprint2.srf	
@@ -0,0 +1,8 @@
+{ "" "" "" "PCI-clamp diode is not supported in this mode. The following 1 pins must meet the Altera requirements for 3.3V, 3.0V, and 2.5V interfaces if they are connected to devices other than the supported configuration devices. In these cases, Altera recommends termination method as specified in the Application Note 447." {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10631 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 13004 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/clean.bat b/Arcade_MiST/Custom Hardware/SprintOne_MiST/clean.bat
new file mode 100644
index 00000000..b3b7c3b5
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/clean.bat	
@@ -0,0 +1,37 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+
+pause
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/EngineSound.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/EngineSound.vhd
new file mode 100644
index 00000000..4d608eac
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/EngineSound.vhd	
@@ -0,0 +1,159 @@
+-- Motor sound generator for Kee Games Sprint 1
+-- Identical circuits are used in a number of other related games
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 555 configured as an astable oscillator with the frequency controlled by
+-- a four bit binary value. The output of this oscillator drives a counter configured to produce an
+-- irregular thumping simulating the sound of an engine.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity EngineSound is 
+generic(
+			constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the overall engine sound frequency
+			);
+port(		
+			Clk_6			: in  std_logic; 
+			Ena_3k		: in  std_logic;
+			EngineData	: in	std_logic_vector(3 downto 0);
+			Motor			: out std_logic_vector(5 downto 0)
+			);
+end EngineSound;
+
+architecture rtl of EngineSound is
+
+signal RPM_val 				: integer range 1 to 350;
+signal Ramp_term_unfilt		: integer range 1 to 80000;
+signal Ramp_Count 			: integer range 0 to 80000;
+signal Ramp_term				: integer range 1 to 80000;
+signal Freq_mod				: integer range 0 to 400;
+signal Motor_Clk				: std_logic;
+
+signal Counter_A				: std_logic;
+signal Counter_B 				: unsigned(2 downto 0);
+signal Counter_A_clk			: std_logic;
+
+signal Motor_prefilter 		: unsigned(1 downto 0);
+signal Motor_filter_t1 		: unsigned(3 downto 0);
+signal Motor_filter_t2 		: unsigned(3 downto 0);
+signal Motor_filter_t3 		: unsigned(3 downto 0);
+signal Motor_filtered		: unsigned(5 downto 0);
+
+
+begin
+
+-- The frequency of the oscillator is set by a 4 bit binary value controlled by the game CPU
+-- in the real hardware this is a 555 coupled to a 4 bit resistor DAC used to pull the frequency.
+-- The output of this DAC has a capacitor to smooth out the frequency variation.
+-- The constants assigned to RPM_val can be tweaked to adjust the frequency curve
+
+Speed_select: process(Clk_6)
+begin
+	if rising_edge(Clk_6) then
+		case EngineData is
+			when "0000" => RPM_val <= 280;
+			when "0001" => RPM_val <= 245;
+			when "0010" => RPM_val <= 230;
+			when "0011" => RPM_val <= 205;
+			when "0100" => RPM_val <= 190;
+			when "0101" => RPM_val <= 175;
+			when "0110" => RPM_val <= 160;
+			when "0111" => RPM_val <= 145;
+		   when "1000" => RPM_val <= 130;
+			when "1001" => RPM_val <= 115;
+			when "1010" => RPM_val <= 100;
+			when "1011" => RPM_val <= 85;
+			when "1100" => RPM_val <= 70;
+			when "1101" => RPM_val <= 55;
+			when "1110" => RPM_val <= 40;
+			when "1111" => RPM_val <= 25; 
+		end case;
+	end if;
+end process;
+
+
+-- There is a RC filter between the frequency control DAC and the 555 to smooth out the transitions between the
+-- 16 possible states. We can simulate a reasonable approximation of that behavior using a linear slope which is
+-- not truly accurate but should be close enough.
+RC_filt: process(clk_6, ena_3k, ramp_term_unfilt)
+begin
+	if rising_edge(clk_6) then
+		if ena_3k = '1' then
+			if ramp_term_unfilt > ramp_term then
+				ramp_term <= ramp_term + 5;
+			elsif ramp_term_unfilt = ramp_term then
+				ramp_term <= ramp_term;
+			else
+				ramp_term <= ramp_term - 3;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower
+-- the frequency. RPM_val is multiplied by a constant which can be adjusted by changing the value of freq_tune
+-- to simulate the function of the frequency adjustment pot in the original hardware.
+ramp_term_unfilt <= ((200 - freq_tune) * RPM_val);
+
+-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator
+Ramp_osc: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		motor_clk <= '1';
+		ramp_count <= ramp_count + 1;
+		if ramp_count > ramp_term then
+			ramp_count <= 0;
+			motor_clk <= '0';
+		end if;
+	end if;
+end process;
+		
+
+-- 7492 counter with XOR on two of the outputs creates lumpy engine sound from smooth pulse train
+-- 7492 has two sections, one div-by-2 and one div-by-6.
+Engine_counter: process(motor_clk, Counter_A_clk, Counter_B)
+begin
+	if rising_edge(motor_clk) then
+		Counter_B <= Counter_B + '1';
+	end if;
+	Counter_A_clk <= Counter_B(0) xor Counter_B(2);
+	if rising_edge(counter_A_clk) then 
+		Counter_A <= (not Counter_A);
+	end if;
+end process;
+motor_prefilter <= ('0' & Counter_B(2)) + ('0' & Counter_B(1)) + ('0' & Counter_A);
+
+-- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Engine_filter: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		if (ena_3k = '1') then
+			motor_filter_t1 <= ("00" & motor_prefilter) + ("00" & motor_prefilter);
+			motor_filter_t2 <= motor_filter_t1;
+			motor_filter_t3 <= motor_filter_t2;
+		end if;
+		motor_filtered <= ("00" & motor_filter_t1) +
+								('0'  & motor_filter_t2 & '0') +
+								("00" & motor_filter_t3);
+	end if;
+end process;	
+
+motor <= std_logic_vector(motor_filtered);
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/Inputs.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/Inputs.vhd
new file mode 100644
index 00000000..56944d09
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/Inputs.vhd	
@@ -0,0 +1,137 @@
+-- Input block for Kee Games Sprint 1
+-- 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+entity control_inputs is 
+port(		
+			Clk6				: in  std_logic; 
+			SW1				: in  std_logic_vector(7 downto 0); -- DIP switches
+			Coin1_n			: in  std_logic; -- Coin switches
+			Coin2_n			: in 	std_logic;
+			Start				: in	std_logic; -- player start switch
+			Gas				: in  std_logic; -- Gas pedal, simple on/off switche
+			Gear1				: in  std_logic; -- Gear select lever
+			Gear2				: in  std_logic;
+			Gear3				: in  std_logic;
+			Self_Test		: in	std_logic; -- Self test switch
+			Steering1A_n	: in  std_logic; -- Steering wheel signals
+			Steering1B_n	: in  std_logic;
+			SteerRst1_n		: in  std_logic;
+			Adr				: in  std_logic_vector(9 downto 0); -- Adress bus, only the lower 9 bits used by IO circuitry
+			Inputs			: out std_logic_vector(1 downto 0)  -- Out to data bus, only upper two bits used
+			);
+end control_inputs;
+
+architecture rtl of control_inputs is
+
+signal A8_8					: std_logic;
+signal H9_Q_n				: std_logic;
+signal H8_en				: std_logic;
+signal Coin1				: std_logic;
+signal Coin2				: std_logic;
+signal SW1_bank1			: std_logic;
+signal SW1_bank2			: std_logic;
+signal DipSW				: std_logic_vector(7 downto 0);
+signal E8_in				: std_logic_vector(3 downto 0);
+signal J9_out				: std_logic_vector(7 downto 0);
+signal E8_out				: std_logic_vector(9 downto 0);
+
+signal Steering1B_Q_n		: std_logic;
+signal Steering1A_Q		: std_logic;
+
+
+begin
+
+-- Inputs
+M8: process(Adr, A8_8, SW1_bank2, Coin2_n, Coin1_n, Steering1B_Q_n, Steering1A_Q)
+begin
+	case Adr(7 downto 6) is
+		when "00" => Inputs <= A8_8 & SW1_bank2; -- There is actually an inverter N9 fed by A8_8 so we will just account for that
+		when "01" => Inputs <= Coin2_n & Coin1_n;
+		when "10" => Inputs <= Steering1B_Q_n & Steering1A_Q;
+		when others => Inputs <= "11";
+		end case;
+end process;
+
+H9: process(Adr, Gear1, Gear2, Gear3, Gas, Self_Test, Start)
+begin
+	if Adr(4) = '0' then -- Adr(4) is connected to enable
+		case Adr(2 downto 0) is
+			when "000" => H9_Q_n <= (not Gear1);
+			when "001" => H9_Q_n <= (not Gear2);
+			when "010" => H9_Q_n <= (not Gear3);
+			when "011" => H9_Q_n <= (not Gas);
+			when "100" => H9_Q_n <= (not Self_Test);
+			when "101" => H9_Q_n <= (not Start);
+			when "110" => H9_Q_n <= '1';
+			when others => H9_Q_n <= '1';
+			end case;
+	else
+		H9_Q_n <= '1';
+	end if;
+end process;
+
+-- Steering
+M9: process(Steering1A_n, Steering1B_n, SteerRst1_n)
+begin
+	if SteerRst1_n <= '0' then -- Asynchronous clear
+		Steering1B_Q_n <= '1';
+	elsif rising_edge(Steering1B_n) then -- Steering encoders are active low but inverted on board
+		Steering1A_Q <= Steering1A_n;
+		Steering1B_Q_n <= '0';
+	end if;
+end process;		
+		
+-- The way the dip switches are wired in the real hardware requires OR logic 
+-- to achieve the same result while using standard active-low switch inputs.
+-- Switches are split into two banks, each bank fed from half of selector J9.
+J9: process(Adr)
+begin
+	if Adr(3) = '1' then
+		J9_out <= "11111111";
+	else
+		case Adr(1 downto 0) is
+			when "00" => J9_out <= "11101110";
+			when "01" => J9_out <= "11011101";
+			when "10" => J9_out <= "10111011";
+			when "11" => J9_out <= "01110111";
+			end case;
+	end if;
+end process;
+
+-- Re-order the dip switch signals to match the physical order of the switches
+-- Bank 1
+DipSW(7) <= J9_out(7) or SW1(1);
+DipSW(6) <= J9_out(6) or SW1(3);
+DipSW(5) <= J9_out(5) or SW1(5);
+DipSW(4) <= J9_out(4) or SW1(7);
+
+--Bank 2
+DipSW(3) <= J9_out(3) or SW1(0);
+DipSW(2) <= J9_out(2) or SW1(2);
+DipSW(1) <= J9_out(1) or SW1(4);
+DipSW(0) <= J9_out(0) or SW1(6);
+
+-- Outputs from each switch bank are tied together, logical AND since they are active low
+SW1_bank1 <= DipSW(7) and DipSW(6) and DipSW(5) and DipSW(4);
+SW1_bank2 <= DipSW(3) and DipSW(2) and DipSW(1) and DipSW(0);
+
+-- Bank 1 of dip switches is multiplexed with player inputs connected to selectors F9 and H9
+A8_8 <= SW1_bank1 and H9_Q_n;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65.vhd
new file mode 100644
index 00000000..161debea
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65.vhd	
@@ -0,0 +1,551 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 more merging
+-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- 65C02 and 65C816 modes are incomplete
+-- Undocumented instructions are not supported
+-- Some interface signals behaves incorrect
+--
+-- File history :
+--
+--      0246 : First release
+--
+
+library IEEE;
+  use IEEE.std_logic_1164.all;
+  use IEEE.numeric_std.all;
+  use work.T65_Pack.all;
+
+-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
+-- the ready signal to limit the CPU.
+entity T65 is
+	port(
+		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+		Res_n   : in  std_logic;
+		Enable  : in  std_logic;
+		Clk     : in  std_logic;
+		Rdy     : in  std_logic;
+		Abort_n : in  std_logic;
+		IRQ_n   : in  std_logic;
+		NMI_n   : in  std_logic;
+		SO_n    : in  std_logic;
+		R_W_n   : out std_logic;
+		Sync    : out std_logic;
+		EF      : out std_logic;
+		MF      : out std_logic;
+		XF      : out std_logic;
+		ML_n    : out std_logic;
+		VP_n    : out std_logic;
+		VDA     : out std_logic;
+		VPA     : out std_logic;
+		A       : out std_logic_vector(23 downto 0);
+		DI      : in  std_logic_vector(7 downto 0);
+		DO      : out std_logic_vector(7 downto 0)
+	);
+end T65;
+
+architecture rtl of T65 is
+
+	-- Registers
+	signal ABC, X, Y, D       : std_logic_vector(15 downto 0);
+	signal P, AD, DL          : std_logic_vector(7 downto 0) :=  x"00";
+	signal BAH                : std_logic_vector(7 downto 0);
+	signal BAL                : std_logic_vector(8 downto 0);
+	signal PBR                : std_logic_vector(7 downto 0);
+	signal DBR                : std_logic_vector(7 downto 0);
+	signal PC                 : unsigned(15 downto 0);
+	signal S                  : unsigned(15 downto 0);
+	signal EF_i               : std_logic;
+	signal MF_i               : std_logic;
+	signal XF_i               : std_logic;
+
+	signal IR                 : std_logic_vector(7 downto 0);
+	signal MCycle             : std_logic_vector(2 downto 0);
+
+	signal Mode_r             : std_logic_vector(1 downto 0);
+	signal ALU_Op_r           : std_logic_vector(3 downto 0);
+	signal Write_Data_r       : std_logic_vector(2 downto 0);
+	signal Set_Addr_To_r      : std_logic_vector(1 downto 0);
+	signal PCAdder            : unsigned(8 downto 0);
+
+	signal RstCycle           : std_logic;
+	signal IRQCycle           : std_logic;
+	signal NMICycle           : std_logic;
+
+	signal B_o                : std_logic;
+	signal SO_n_o             : std_logic;
+	signal IRQ_n_o            : std_logic;
+	signal NMI_n_o            : std_logic;
+	signal NMIAct             : std_logic;
+
+	signal Break              : std_logic;
+
+	-- ALU signals
+	signal BusA               : std_logic_vector(7 downto 0);
+	signal BusA_r             : std_logic_vector(7 downto 0);
+	signal BusB               : std_logic_vector(7 downto 0);
+	signal ALU_Q              : std_logic_vector(7 downto 0);
+	signal P_Out              : std_logic_vector(7 downto 0);
+
+	-- Micro code outputs
+	signal LCycle             : std_logic_vector(2 downto 0);
+	signal ALU_Op             : std_logic_vector(3 downto 0);
+	signal Set_BusA_To        : std_logic_vector(2 downto 0);
+	signal Set_Addr_To        : std_logic_vector(1 downto 0);
+	signal Write_Data         : std_logic_vector(2 downto 0);
+	signal Jump               : std_logic_vector(1 downto 0);
+	signal BAAdd              : std_logic_vector(1 downto 0);
+	signal BreakAtNA          : std_logic;
+	signal ADAdd              : std_logic;
+	signal AddY               : std_logic;
+	signal PCAdd              : std_logic;
+	signal Inc_S              : std_logic;
+	signal Dec_S              : std_logic;
+	signal LDA                : std_logic;
+	signal LDP                : std_logic;
+	signal LDX                : std_logic;
+	signal LDY                : std_logic;
+	signal LDS                : std_logic;
+	signal LDDI               : std_logic;
+	signal LDALU              : std_logic;
+	signal LDAD               : std_logic;
+	signal LDBAL              : std_logic;
+	signal LDBAH              : std_logic;
+	signal SaveP              : std_logic;
+	signal Write              : std_logic;
+
+	signal really_rdy         : std_logic;
+	signal R_W_n_i            : std_logic;
+
+begin
+	-- ehenciak : gate Rdy with read/write to make an "OK, it's
+	--            really OK to stop the processor now if Rdy is
+	--            deasserted" signal
+	really_rdy <= Rdy or not(R_W_n_i);
+
+	-- ehenciak : Drive R_W_n_i off chip.
+	R_W_n      <= R_W_n_i;
+
+	Sync <= '1' when MCycle = "000" else '0';
+	EF <= EF_i;
+	MF <= MF_i;
+	XF <= XF_i;
+	ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
+	VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
+	VDA <= '1' when Set_Addr_To_r /= "000" else '0';            -- Incorrect !!!!!!!!!!!!
+	VPA <= '1' when Jump(1) = '0' else '0';                     -- Incorrect !!!!!!!!!!!!
+
+	mcode : T65_MCode
+		port map(
+			Mode        => Mode_r,
+			IR          => IR,
+			MCycle      => MCycle,
+			P           => P,
+			LCycle      => LCycle,
+			ALU_Op      => ALU_Op,
+			Set_BusA_To => Set_BusA_To,
+			Set_Addr_To => Set_Addr_To,
+			Write_Data  => Write_Data,
+			Jump        => Jump,
+			BAAdd       => BAAdd,
+			BreakAtNA   => BreakAtNA,
+			ADAdd       => ADAdd,
+			AddY        => AddY,
+			PCAdd       => PCAdd,
+			Inc_S       => Inc_S,
+			Dec_S       => Dec_S,
+			LDA         => LDA,
+			LDP         => LDP,
+			LDX         => LDX,
+			LDY         => LDY,
+			LDS         => LDS,
+			LDDI        => LDDI,
+			LDALU       => LDALU,
+			LDAD        => LDAD,
+			LDBAL       => LDBAL,
+			LDBAH       => LDBAH,
+			SaveP       => SaveP,
+			Write       => Write
+			);
+
+	alu : T65_ALU
+		port map(
+			Mode => Mode_r,
+			Op => ALU_Op_r,
+			BusA => BusA_r,
+			BusB => BusB,
+			P_In => P,
+			P_Out => P_Out,
+			Q => ALU_Q
+			);
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			IR <= "00000000";
+			S <= (others => '0');       -- Dummy !!!!!!!!!!!!!!!!!!!!!
+			D <= (others => '0');
+			PBR <= (others => '0');
+			DBR <= (others => '0');
+
+			Mode_r <= (others => '0');
+			ALU_Op_r <= "1100";
+			Write_Data_r <= "000";
+			Set_Addr_To_r <= "00";
+
+			R_W_n_i <= '1';
+			EF_i <= '1';
+			MF_i <= '1';
+			XF_i <= '1';
+
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				R_W_n_i <= not Write or RstCycle;
+
+				D <= (others => '1');   -- Dummy
+				PBR <= (others => '1'); -- Dummy
+				DBR <= (others => '1'); -- Dummy
+				EF_i <= '0';    -- Dummy
+				MF_i <= '0';    -- Dummy
+				XF_i <= '0';    -- Dummy
+
+				if MCycle  = "000" then
+					Mode_r <= Mode;
+
+					if IRQCycle = '0' and NMICycle = '0' then
+						PC <= PC + 1;
+					end if;
+
+					if IRQCycle = '1' or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DI;
+					end if;
+				end if;
+
+				ALU_Op_r <= ALU_Op;
+				Write_Data_r <= Write_Data;
+				if Break = '1' then
+					Set_Addr_To_r <= "00";
+				else
+					Set_Addr_To_r <= Set_Addr_To;
+				end if;
+
+				if Inc_S = '1' then
+					S <= S + 1;
+				end if;
+				if Dec_S = '1' and RstCycle = '0' then
+					S <= S - 1;
+				end if;
+				if LDS = '1' then
+					S(7 downto 0) <= unsigned(ALU_Q);
+				end if;
+
+				if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
+					PC <= PC + 1;
+				end if;
+				--
+				-- jump control logic
+				--
+				case Jump is
+				  when "01" =>
+					  PC <= PC + 1;
+
+				  when "10" =>
+					  PC <= unsigned(DI & DL);
+
+				  when "11" =>
+					  if PCAdder(8) = '1' then
+						  if DL(7) = '0' then
+							  PC(15 downto 8) <= PC(15 downto 8) + 1;
+						  else
+							  PC(15 downto 8) <= PC(15 downto 8) - 1;
+						  end if;
+					  end if;
+					  PC(7 downto 0) <= PCAdder(7 downto 0);
+
+				  when others => null;
+				end case;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+	PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
+			   else "0" & PC(7 downto 0);
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				if MCycle = "000" then
+					if LDA = '1' then
+						ABC(7 downto 0) <= ALU_Q;
+					end if;
+					if LDX = '1' then
+						X(7 downto 0) <= ALU_Q;
+					end if;
+					if LDY = '1' then
+						Y(7 downto 0) <= ALU_Q;
+					end if;
+					if (LDA or LDX or LDY) = '1' then
+						P <= P_Out;
+					end if;
+				end if;
+				if SaveP = '1' then
+					P <= P_Out;
+				end if;
+				if LDP = '1' then
+					P <= ALU_Q;
+				end if;
+				if IR(4 downto 0) = "11000" then
+					case IR(7 downto 5) is
+					when "000" =>
+						P(Flag_C) <= '0';
+					when "001" =>
+						P(Flag_C) <= '1';
+					when "010" =>
+						P(Flag_I) <= '0';
+					when "011" =>
+						P(Flag_I) <= '1';
+					when "101" =>
+						P(Flag_V) <= '0';
+					when "110" =>
+						P(Flag_D) <= '0';
+					when "111" =>
+						P(Flag_D) <= '1';
+					when others =>
+					end case;
+				end if;
+				if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
+					P(Flag_B) <= '1';
+				end if;
+				if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1')  then
+					P(Flag_I) <= '1';
+					P(Flag_B) <= B_o;
+				end if;
+				if SO_n_o = '1' and SO_n = '0' then
+					P(Flag_V) <= '1';
+				end if;
+				if RstCycle = '1' and Mode_r /= "00" then
+					P(Flag_1) <= '1';
+					P(Flag_D) <= '0';
+					P(Flag_I) <= '1';
+				end if;
+				P(Flag_1) <= '1';
+
+				B_o     <= P(Flag_B);
+				SO_n_o <= SO_n;
+				IRQ_n_o <= IRQ_n;
+				NMI_n_o <= NMI_n;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			BusA_r <= (others => '0');
+			BusB <= (others => '0');
+			AD <= (others => '0');
+			BAL <= (others => '0');
+			BAH <= (others => '0');
+			DL <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (Rdy = '1') then
+				BusA_r <= BusA;
+				BusB <= DI;
+
+				case BAAdd is
+				when "01" =>
+					-- BA Inc
+					AD <= std_logic_vector(unsigned(AD) + 1);
+					BAL <= std_logic_vector(unsigned(BAL) + 1);
+				when "10" =>
+					-- BA Add
+					BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
+				when "11" =>
+					-- BA Adj
+					if BAL(8) = '1' then
+						BAH <= std_logic_vector(unsigned(BAH) + 1);
+					end if;
+				when others =>
+				end case;
+
+				-- ehenciak : modified to use Y register as well (bugfix)
+				if ADAdd = '1' then
+				  if (AddY = '1') then
+					AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
+				  else
+					AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
+				  end if;
+				end if;
+
+				if IR = "00000000" then
+					BAL <= (others => '1');
+					BAH <= (others => '1');
+					if RstCycle = '1' then
+						BAL(2 downto 0) <= "100";
+					elsif NMICycle = '1' then
+						BAL(2 downto 0) <= "010";
+					else
+						BAL(2 downto 0) <= "110";
+					end if;
+					if Set_addr_To_r = "11" then
+						BAL(0) <= '1';
+					end if;
+				end if;
+
+
+				if LDDI = '1' then
+					DL <= DI;
+				end if;
+				if LDALU = '1' then
+					DL <= ALU_Q;
+				end if;
+				if LDAD = '1' then
+					AD <= DI;
+				end if;
+				if LDBAL = '1' then
+					BAL(7 downto 0) <= DI;
+				end if;
+				if LDBAH = '1' then
+					BAH <= DI;
+				end if;
+			end if;
+		end if;
+	  end if;
+	end process;
+
+	Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
+
+
+	with Set_BusA_To select
+		BusA <= DI when "000",
+			ABC(7 downto 0) when "001",
+			X(7 downto 0) when "010",
+			Y(7 downto 0) when "011",
+			std_logic_vector(S(7 downto 0)) when "100",
+			P when "101",
+			(others => '-') when others;
+
+	with Set_Addr_To_r select
+		A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
+			DBR & "00000000" & AD when "10",
+			"00000000" & BAH & BAL(7 downto 0) when "11",
+			PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
+
+	with Write_Data_r select
+		DO <= DL when "000",
+			ABC(7 downto 0) when "001",
+			X(7 downto 0) when "010",
+			Y(7 downto 0) when "011",
+			std_logic_vector(S(7 downto 0)) when "100",
+			P when "101",
+			std_logic_vector(PC(7 downto 0)) when "110",
+			std_logic_vector(PC(15 downto 8)) when others;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			MCycle <= "001";
+			RstCycle <= '1';
+			IRQCycle <= '0';
+			NMICycle <= '0';
+			NMIAct <= '0';
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				if MCycle = LCycle or Break = '1' then
+					MCycle <= "000";
+					RstCycle <= '0';
+					IRQCycle <= '0';
+					NMICycle <= '0';
+					if NMIAct = '1' then
+						NMICycle <= '1';
+					elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
+						IRQCycle <= '1';
+					end if;
+				else
+					MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+				end if;
+
+				if NMICycle = '1' then
+					NMIAct <= '0';
+				end if;
+				if NMI_n_o = '1' and NMI_n = '0' then
+					NMIAct <= '1';
+				end if;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_ALU.vhd
new file mode 100644
index 00000000..b1f6d632
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_ALU.vhd	
@@ -0,0 +1,260 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 6502 compatible microprocessor core
+--
+-- Version : 0245
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0245 : First version
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T65_Pack.all;
+
+entity T65_ALU is
+	port(
+		Mode    : in std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		Op      : in std_logic_vector(3 downto 0);
+		BusA    : in std_logic_vector(7 downto 0);
+		BusB    : in std_logic_vector(7 downto 0);
+		P_In    : in std_logic_vector(7 downto 0);
+		P_Out   : out std_logic_vector(7 downto 0);
+		Q       : out std_logic_vector(7 downto 0)
+	);
+end T65_ALU;
+
+architecture rtl of T65_ALU is
+
+	-- AddSub variables (temporary signals)
+	signal      ADC_Z           : std_logic;
+	signal      ADC_C           : std_logic;
+	signal      ADC_V           : std_logic;
+	signal      ADC_N           : std_logic;
+	signal      ADC_Q           : std_logic_vector(7 downto 0);
+	signal      SBC_Z           : std_logic;
+	signal      SBC_C           : std_logic;
+	signal      SBC_V           : std_logic;
+	signal      SBC_N           : std_logic;
+	signal      SBC_Q           : std_logic_vector(7 downto 0);
+
+begin
+
+	process (P_In, BusA, BusB)
+		variable AL : unsigned(6 downto 0);
+		variable AH : unsigned(6 downto 0);
+		variable C : std_logic;
+	begin
+		AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
+		AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+			ADC_Z <= '1';
+		else
+			ADC_Z <= '0';
+		end if;
+
+		if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+			AL(6 downto 1) := AL(6 downto 1) + 6;
+		end if;
+
+		C := AL(6) or AL(5);
+		AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+		ADC_N <= AH(4);
+		ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+		if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+			AH(6 downto 1) := AH(6 downto 1) + 6;
+		end if;
+
+		ADC_C <= AH(6) or AH(5);
+
+		ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+	end process;
+
+	process (Op, P_In, BusA, BusB)
+		variable AL : unsigned(6 downto 0);
+		variable AH : unsigned(5 downto 0);
+		variable C : std_logic;
+	begin
+		C := P_In(Flag_C) or not Op(0);
+		AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
+		AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+			if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
+-- pragma translate_on
+
+		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+			SBC_Z <= '1';
+		else
+			SBC_Z <= '0';
+		end if;
+
+		SBC_C <= not AH(5);
+		SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
+		SBC_N <= AH(4);
+
+		if P_In(Flag_D) = '1' then
+			if AL(5) = '1' then
+				AL(5 downto 1) := AL(5 downto 1) - 6;
+			end if;
+			AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
+			if AH(5) = '1' then
+				AH(5 downto 1) := AH(5 downto 1) - 6;
+			end if;
+		end if;
+
+		SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+	end process;
+
+	process (Op, P_In, BusA, BusB,
+			ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
+			SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
+		variable Q_t : std_logic_vector(7 downto 0);
+	begin
+		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
+		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
+		P_Out <= P_In;
+		Q_t := BusA;
+		case Op(3 downto 0) is
+		when "0000" =>
+			-- ORA
+			Q_t := BusA or BusB;
+		when "0001" =>
+			-- AND
+			Q_t := BusA and BusB;
+		when "0010" =>
+			-- EOR
+			Q_t := BusA xor BusB;
+		when "0011" =>
+			-- ADC
+			P_Out(Flag_V) <= ADC_V;
+			P_Out(Flag_C) <= ADC_C;
+			Q_t := ADC_Q;
+		when "0101" | "1101" =>
+			-- LDA
+		when "0110" =>
+			-- CMP
+			P_Out(Flag_C) <= SBC_C;
+		when "0111" =>
+			-- SBC
+			P_Out(Flag_V) <= SBC_V;
+			P_Out(Flag_C) <= SBC_C;
+			Q_t := SBC_Q;
+		when "1000" =>
+			-- ASL
+			Q_t := BusA(6 downto 0) & "0";
+			P_Out(Flag_C) <= BusA(7);
+		when "1001" =>
+			-- ROL
+			Q_t := BusA(6 downto 0) & P_In(Flag_C);
+			P_Out(Flag_C) <= BusA(7);
+		when "1010" =>
+			-- LSR
+			Q_t := "0" & BusA(7 downto 1);
+			P_Out(Flag_C) <= BusA(0);
+		when "1011" =>
+			-- ROR
+			Q_t := P_In(Flag_C) & BusA(7 downto 1);
+			P_Out(Flag_C) <= BusA(0);
+		when "1100" =>
+			-- BIT
+			P_Out(Flag_V) <= BusB(6);
+		when "1110" =>
+			-- DEC
+			Q_t := std_logic_vector(unsigned(BusA) - 1);
+		when "1111" =>
+			-- INC
+			Q_t := std_logic_vector(unsigned(BusA) + 1);
+		when others =>
+		end case;
+
+		case Op(3 downto 0) is
+		when "0011" =>
+			P_Out(Flag_N) <= ADC_N;
+			P_Out(Flag_Z) <= ADC_Z;
+		when "0110" | "0111" =>
+			P_Out(Flag_N) <= SBC_N;
+			P_Out(Flag_Z) <= SBC_Z;
+		when "0100" =>
+		when "1100" =>
+			P_Out(Flag_N) <= BusB(7);
+			if (BusA and BusB) = "00000000" then
+				P_Out(Flag_Z) <= '1';
+			else
+				P_Out(Flag_Z) <= '0';
+			end if;
+		when others =>
+			P_Out(Flag_N) <= Q_t(7);
+			if Q_t = "00000000" then
+				P_Out(Flag_Z) <= '1';
+			else
+				P_Out(Flag_Z) <= '0';
+			end if;
+		end case;
+
+		Q <= Q_t;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_MCode.vhd
new file mode 100644
index 00000000..06229751
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_MCode.vhd	
@@ -0,0 +1,1050 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 Jump timing fixed
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246 + fix
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- 65C02
+-- supported : inc, dec, phx, plx, phy, ply
+-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
+--
+-- File history :
+--
+--      0246 : First release
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T65_Pack.all;
+
+entity T65_MCode is
+	port(
+		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		IR                      : in  std_logic_vector(7 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		P                       : in  std_logic_vector(7 downto 0);
+		LCycle                  : out std_logic_vector(2 downto 0);
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
+		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
+		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
+		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
+		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
+		BreakAtNA               : out std_logic;
+		ADAdd                   : out std_logic;
+		AddY                    : out std_logic;
+		PCAdd                   : out std_logic;
+		Inc_S                   : out std_logic;
+		Dec_S                   : out std_logic;
+		LDA                     : out std_logic;
+		LDP                     : out std_logic;
+		LDX                     : out std_logic;
+		LDY                     : out std_logic;
+		LDS                     : out std_logic;
+		LDDI                    : out std_logic;
+		LDALU                   : out std_logic;
+		LDAD                    : out std_logic;
+		LDBAL                   : out std_logic;
+		LDBAH                   : out std_logic;
+		SaveP                   : out std_logic;
+		Write                   : out std_logic
+	);
+end T65_MCode;
+
+architecture rtl of T65_MCode is
+
+	signal Branch : std_logic;
+
+begin
+
+	with IR(7 downto 5) select
+		Branch <= not P(Flag_N) when "000",
+					  P(Flag_N) when "001",
+				  not P(Flag_V) when "010",
+					  P(Flag_V) when "011",
+				  not P(Flag_C) when "100",
+					  P(Flag_C) when "101",
+				  not P(Flag_Z) when "110",
+					  P(Flag_Z) when others;
+
+	process (IR, MCycle, P, Branch, Mode)
+	begin
+		LCycle      <= "001";
+		Set_BusA_To <= "001"; -- A
+		Set_Addr_To <= (others => '0');
+		Write_Data  <= (others => '0');
+		Jump        <= (others => '0');
+		BAAdd       <= "00";
+		BreakAtNA   <= '0';
+		ADAdd       <= '0';
+		PCAdd       <= '0';
+		Inc_S       <= '0';
+		Dec_S       <= '0';
+		LDA         <= '0';
+		LDP         <= '0';
+		LDX         <= '0';
+		LDY         <= '0';
+		LDS         <= '0';
+		LDDI        <= '0';
+		LDALU       <= '0';
+		LDAD        <= '0';
+		LDBAL       <= '0';
+		LDBAH       <= '0';
+		SaveP       <= '0';
+		Write       <= '0';
+		AddY        <= '0';
+
+		case IR(7 downto 5) is
+		when "100" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				Set_BusA_To <= "011"; -- Y
+				Write_Data <= "011"; -- Y
+			when "10" =>
+				Set_BusA_To <= "010"; -- X
+				Write_Data <= "010"; -- X
+			when others =>
+				Write_Data <= "001"; -- A
+			end case;
+		--}}}
+		when "101" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) /= '1' or IR(2) /= '0' then
+					LDY <= '1';
+				end if;
+			when "10" =>
+				LDX <= '1';
+			when others =>
+				LDA <= '1';
+			end case;
+			Set_BusA_To <= "000"; -- DI
+		--}}}
+		when "110" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) = '0' then
+					LDY <= '1';
+				end if;
+				Set_BusA_To <= "011"; -- Y
+			when others =>
+				Set_BusA_To <= "001"; -- A
+			end case;
+		--}}}
+		when "111" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) = '0' then
+					LDX <= '1';
+				end if;
+				Set_BusA_To <= "010"; -- X
+			when others =>
+				Set_BusA_To <= "001"; -- A
+			end case;
+		--}}}
+		when others =>
+		end case;
+
+		if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+			Set_BusA_To <= "000"; -- DI
+		end if;
+
+		case IR(4 downto 0) is
+		when "00000" | "01000" | "01010" | "11000" | "11010" =>
+		--{{{
+			-- Implied
+			case IR is
+			when "00000000" =>
+				-- BRK
+				LCycle <= "110";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "111"; -- PCH
+					Write <= '1';
+				when 2 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "110"; -- PCL
+					Write <= '1';
+				when 3 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "101"; -- P
+					Write <= '1';
+				when 4 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					LDDI <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 6 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "00100000" =>
+				-- JSR
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "111"; -- PCH
+					Write <= '1';
+				when 3 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "110"; -- PCL
+					Write <= '1';
+				when 4 =>
+					Dec_S <= '1';
+				when 5 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "01000000" =>
+				-- RTI
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Set_BusA_To <= "000"; -- DI
+				when 4 =>
+					LDP <= '1';
+					Inc_S <= '1';
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 5 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "01100000" =>
+				-- RTS
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Inc_S <= '1';
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 4 =>
+					Jump <= "10"; -- DIDL
+				when 5 =>
+					Jump <= "01";
+				when others =>
+				end case;
+			when "00001000" | "01001000" | "01011010" | "11011010" =>
+				-- PHP, PHA, PHY*, PHX*
+				LCycle <= "010";
+				if Mode = "00" and IR(1) = '1' then
+					LCycle <= "001";
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					case IR(7 downto 4) is
+					when "0000" =>
+						Write_Data <= "101"; -- P
+					when "0100" =>
+						Write_Data <= "001"; -- A
+					when "0101" =>
+						Write_Data <= "011"; -- Y
+					when "1101" =>
+						Write_Data <= "010"; -- X
+					when others =>
+					end case;
+					Write <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Dec_S <= '1';
+				when others =>
+				end case;
+			when "00101000" | "01101000" | "01111010" | "11111010" =>
+				-- PLP, PLA, PLY*, PLX*
+				LCycle <= "011";
+				if Mode = "00" and IR(1) = '1' then
+					LCycle <= "001";
+				end if;
+				case IR(7 downto 4) is
+				when "0010" =>
+					LDP <= '1';
+				when "0110" =>
+					LDA <= '1';
+				when "0111" =>
+					if Mode /= "00" then
+						LDY <= '1';
+					end if;
+				when "1111" =>
+					if Mode /= "00" then
+						LDX <= '1';
+					end if;
+				when others =>
+				end case;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					SaveP <= '1';
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Set_BusA_To <= "000"; -- DI
+				when others =>
+				end case;
+			when "10100000" | "11000000" | "11100000" =>
+				-- LDY, CPY, CPX
+				-- Immediate
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+				when others =>
+				end case;
+			when "10001000" =>
+				-- DEY
+				LDY <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "011"; -- Y
+				when others =>
+				end case;
+			when "11001010" =>
+				-- DEX
+				LDX <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "010"; -- X
+				when others =>
+				end case;
+			when "00011010" | "00111010" =>
+				-- INC*, DEC*
+				if Mode /= "00" then
+					LDA <= '1'; -- A
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "100"; -- S
+				when others =>
+				end case;
+			when "00001010" | "00101010" | "01001010" | "01101010" =>
+				-- ASL, ROL, LSR, ROR
+				LDA <= '1'; -- A
+				Set_BusA_To <= "001"; -- A
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+				when others =>
+				end case;
+			when "10001010" | "10011000" =>
+				-- TYA, TXA
+				LDA <= '1'; -- A
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+				when others =>
+				end case;
+			when "10101010" | "10101000" =>
+				-- TAX, TAY
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "001"; -- A
+				when others =>
+				end case;
+			when "10011010" =>
+				-- TXS
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					LDS <= '1';
+				when 1 =>
+				when others =>
+				end case;
+			when "10111010" =>
+				-- TSX
+				LDX <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "100"; -- S
+				when others =>
+				end case;
+
+		--                      when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" =>
+		--                              -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX
+		--                              case to_integer(unsigned(MCycle)) is
+		--                              when 1 =>
+		--                              when others =>
+		--                              end case;
+			when others =>
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when others =>
+				end case;
+			end case;
+		--}}}
+
+		when "00001" | "00011" =>
+		--{{{
+			-- Zero Page Indexed Indirect (d,x)
+			LCycle <= "101";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+				ADAdd <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 3 =>
+				BAAdd <= "01";  -- DB Inc
+				LDBAL <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 4 =>
+				LDBAH <= '1';
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 5 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "01001" | "01011" =>
+		--{{{
+			-- Immediate
+			LDA <= '1';
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+			when others =>
+			end case;
+
+		--}}}
+
+		when "00010" | "10010" =>
+		--{{{
+			-- Immediate, KIL
+			LDX <= '1';
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				if IR = "10100010" then
+					-- LDX
+					Jump <= "01";
+				else
+					-- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+				end if;
+			when others =>
+			end case;
+		--}}}
+
+		when "00100" =>
+		--{{{
+			-- Zero Page
+			LCycle <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+				if IR(7 downto 5) = "001" then
+					SaveP <= '1';
+				end if;
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				end if;
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "00101" | "00110" | "00111" =>
+		--{{{
+			-- Zero Page
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 3 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 4 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "010";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "01100" =>
+		--{{{
+			-- Absolute
+			if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then
+				-- JMP
+				if IR(5) = '0' then
+					--LCycle <= "011";
+					LCycle <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Jump <= "01";
+						LDDI <= '1';
+					when 2 =>
+						Jump <= "10"; -- DIDL
+					when others =>
+					end case;
+				else
+					LCycle <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Jump <= "01";
+						LDDI <= '1';
+						LDBAL <= '1';
+					when 3 =>
+						LDBAH <= '1';
+						if Mode /= "00" then
+							Jump <= "10"; -- DIDL
+						end if;
+						if Mode = "00" then
+							Set_Addr_To <= "11"; -- BA
+						end if;
+					when 4 =>
+						LDDI <= '1';
+						if Mode = "00" then
+							Set_Addr_To <= "11"; -- BA
+							BAAdd <= "01";      -- DB Inc
+						else
+							Jump <= "01";
+						end if;
+					when 5 =>
+						Jump <= "10"; -- DIDL
+					when others =>
+					end case;
+				end if;
+			else
+				LCycle <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					if IR(7 downto 5) = "001" then
+						SaveP <= '1';
+					end if;
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "01101" | "01110" | "01111" =>
+		--{{{
+			-- Absolute
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+					Write <= '1';
+					LDALU <= '1';
+					SaveP <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					SaveP <= '0'; -- MIKEJ was 1
+				when others =>
+				end case;
+			else
+				LCycle <= "011";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "10000" =>
+		--{{{
+			-- Relative
+
+						-- This circuit dictates when the last
+						-- microcycle occurs for the branch depending on
+						-- whether or not the branch is taken and if a page
+						-- is crossed...
+			if (Branch = '1') then
+
+							 LCycle <= "011"; -- We're done @ T3 if branching...upper
+											  -- level logic will stop at T2 if no page cross
+											  -- (See the Break signal)
+			else
+
+							 LCycle <= "001";
+
+			end if;
+
+						-- This decodes the current microcycle and takes the
+						-- proper course of action...
+			case to_integer(unsigned(MCycle)) is
+
+							-- On the T1 microcycle, increment the program counter
+							-- and instruct the upper level logic to fetch the offset
+							-- from the Din bus and store it in the data latches. This
+							-- will be the last microcycle if the branch isn't taken.
+				when 1 =>
+
+					Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
+											  -- from microcycle T0.
+
+				LDDI <= '1';  -- Tells logic in top level (T65.vhd) to route
+											  -- the Din bus to the memory data latch (DL)
+											  -- so that the branch offset is fetched.
+
+							-- In microcycle T2, tell the logic in the top level to
+							-- add the offset.  If the most significant byte of the
+							-- program counter (i.e. the current "page") does not need
+							-- updating, we are done here...the Break signal at the
+							-- T65.vhd level takes care of that...
+				when 2 =>
+
+				Jump    <= "11"; -- Tell the PC Jump logic to use relative mode.
+
+				PCAdd   <= '1';  -- This tells the PC adder to update itself with
+												 -- the current offset recently fetched from
+												 -- memory.
+
+							-- The following is microcycle T3 :
+							-- The program counter should be completely updated
+							-- on this cycle after the page cross is detected.
+							-- We don't need to do anything here...
+				when 3 =>
+
+
+				when others => null; -- Do nothing.
+
+			end case;
+		--}}}
+
+		when "10001" | "10011" =>
+		--{{{
+			-- Zero Page Indirect Indexed (d),y
+			LCycle <= "101";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+				LDBAL <= '1';
+				BAAdd <= "01";  -- DB Inc
+				Set_Addr_To <= "10"; -- AD
+			when 3 =>
+				Set_BusA_To <= "011"; -- Y
+				BAAdd <= "10";  -- BA Add
+				LDBAH <= '1';
+				Set_Addr_To <= "11"; -- BA
+			when 4 =>
+				BAAdd <= "11";  -- BA Adj
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				else
+					BreakAtNA <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 5 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "10100" | "10101" | "10110" | "10111" =>
+		--{{{
+			-- Zero Page, X
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					ADAdd <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 3 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 4 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 5 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "011";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					ADAdd <= '1';
+					-- Added this check for Y reg. use...
+					if (IR(3 downto 0) = "0110") then
+					  AddY <= '1';
+					end if;
+
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "10"; -- AD
+				when 3 => null;
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "11001" | "11011" =>
+		--{{{
+			-- Absolute Y
+			LCycle <= "100";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDBAL <= '1';
+			when 2 =>
+				Jump <= "01";
+				Set_BusA_To <= "011"; -- Y
+				BAAdd <= "10";  -- BA Add
+				LDBAH <= '1';
+				Set_Addr_To <= "11"; -- BA
+			when 3 =>
+				BAAdd <= "11";  -- BA adj
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				else
+					BreakAtNA <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 4 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "11100" | "11101" | "11110" | "11111" =>
+		--{{{
+			-- Absolute X
+
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "110";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					Set_BusA_To <= "010"; -- X
+					BAAdd <= "10";      -- BA Add
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					BAAdd <= "11";      -- BA adj
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 6 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "100";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					-- mikej
+					-- special case 0xBE which uses Y reg as index!!
+					if (IR = "10111110") then
+					  Set_BusA_To <= "011"; -- Y
+					else
+					  Set_BusA_To <= "010"; -- X
+					end if;
+					BAAdd <= "10";      -- BA Add
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					BAAdd <= "11";      -- BA adj
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					else
+						BreakAtNA <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+		when others =>
+		end case;
+	end process;
+
+	process (IR, MCycle)
+	begin
+		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
+		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
+		case IR(1 downto 0) is
+		when "00" =>
+		--{{{
+			case IR(4 downto 2) is
+			when "000" | "001" | "011" =>
+				case IR(7 downto 5) is
+				when "110" | "111" =>
+					-- CP
+					ALU_Op <= "0110";
+				when "101" =>
+					-- LD
+					ALU_Op <= "0101";
+				when "001" =>
+					-- BIT
+					ALU_Op <= "1100";
+				when others =>
+					-- NOP/ST
+					ALU_Op <= "0100";
+				end case;
+			when "010" =>
+				case IR(7 downto 5) is
+				when "111" | "110" =>
+					-- IN
+					ALU_Op <= "1111";
+				when "100" =>
+					-- DEY
+					ALU_Op <= "1110";
+				when others =>
+					-- LD
+					ALU_Op <= "1101";
+				end case;
+			when "110" =>
+				case IR(7 downto 5) is
+				when "100" =>
+					-- TYA
+					ALU_Op <= "1101";
+				when others =>
+					ALU_Op <= "----";
+				end case;
+			when others =>
+				case IR(7 downto 5) is
+				when "101" =>
+					-- LD
+					ALU_Op <= "1101";
+				when others =>
+					ALU_Op <= "0100";
+				end case;
+			end case;
+		--}}}
+		when "01" => -- OR
+		--{{{
+			ALU_Op(3) <= '0';
+			ALU_Op(2 downto 0) <= IR(7 downto 5);
+		--}}}
+		when "10" =>
+		--{{{
+			ALU_Op(3) <= '1';
+			ALU_Op(2 downto 0) <= IR(7 downto 5);
+			case IR(7 downto 5) is
+			when "000" =>
+				if IR(4 downto 2) = "110" then
+					-- INC
+					ALU_Op <= "1111";
+				end if;
+			when "001" =>
+				if IR(4 downto 2) = "110" then
+					-- DEC
+					ALU_Op <= "1110";
+				end if;
+			when "100" =>
+				if IR(4 downto 2) = "010" then
+					-- TXA
+					ALU_Op <= "0101";
+				else
+					ALU_Op <= "0100";
+				end if;
+			when others =>
+			end case;
+		--}}}
+		when others =>
+		--{{{
+			case IR(7 downto 5) is
+			when "100" =>
+				ALU_Op <= "0100";
+			when others =>
+				if MCycle = "000" then
+					ALU_Op(3) <= '0';
+					ALU_Op(2 downto 0) <= IR(7 downto 5);
+				else
+					ALU_Op(3) <= '1';
+					ALU_Op(2 downto 0) <= IR(7 downto 5);
+				end if;
+			end case;
+		--}}}
+		end case;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_Pack.vhd
new file mode 100644
index 00000000..e025e1bf
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/T65/T65_Pack.vhd	
@@ -0,0 +1,117 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T65_Pack is
+
+	constant Flag_C : integer := 0;
+	constant Flag_Z : integer := 1;
+	constant Flag_I : integer := 2;
+	constant Flag_D : integer := 3;
+	constant Flag_B : integer := 4;
+	constant Flag_1 : integer := 5;
+	constant Flag_V : integer := 6;
+	constant Flag_N : integer := 7;
+
+	component T65_MCode
+	port(
+		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		IR                      : in  std_logic_vector(7 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		P                       : in  std_logic_vector(7 downto 0);
+		LCycle                  : out std_logic_vector(2 downto 0);
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
+		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
+		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
+		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
+		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
+		BreakAtNA               : out std_logic;
+		ADAdd                   : out std_logic;
+		AddY                    : out std_logic;
+		PCAdd                   : out std_logic;
+		Inc_S                   : out std_logic;
+		Dec_S                   : out std_logic;
+		LDA                     : out std_logic;
+		LDP                     : out std_logic;
+		LDX                     : out std_logic;
+		LDY                     : out std_logic;
+		LDS                     : out std_logic;
+		LDDI                    : out std_logic;
+		LDALU                   : out std_logic;
+		LDAD                    : out std_logic;
+		LDBAL                   : out std_logic;
+		LDBAH                   : out std_logic;
+		SaveP                   : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T65_ALU
+	port(
+		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+		Op      : in  std_logic_vector(3 downto 0);
+		BusA    : in  std_logic_vector(7 downto 0);
+		BusB    : in  std_logic_vector(7 downto 0);
+		P_In    : in  std_logic_vector(7 downto 0);
+		P_Out   : out std_logic_vector(7 downto 0);
+		Q       : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/build_id.sv b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/build_id.sv
new file mode 100644
index 00000000..1d53a3f2
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/build_id.sv	
@@ -0,0 +1,2 @@
+`define BUILD_DATE "171221"
+`define BUILD_TIME "172231"
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/build_id.tcl b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..be673dac
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.sv"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/collision.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/collision.vhd
new file mode 100644
index 00000000..7720199f
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/collision.vhd	
@@ -0,0 +1,95 @@
+-- Collision detection logic for for Kee Games Sprint 1
+-- This is called the "Car/Playfield Comparator" in the manual and works by comparing the
+-- video signals representing player and computer cars, track boundaries and oil slicks generating 
+-- collision signals when multiple objects appear at the same time (location) in the video. 
+-- Car 1 is the human player, Cars 2, 3 and Car 4 are computer controlled. 
+--
+-- NOTE: There is an error in the original schematic, F8 pin 5 should go to CAR1 (not inverted) and 
+-- F8 pin 9 to CAR2 (not inverted) while the schematic shows them connecting to the inverted signals
+-- 
+-- Tests for the following conditions:
+-- Car 1 equals Car 2
+-- Car 1 equals Car 3 or 4
+-- Car 1 equals Black Playfield (Oil slick)
+-- Car 1 equals White Playfield (Track boundary)
+--
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity collision_detect is 
+port(		
+			Clk6					: in  std_logic;
+			Car1					: in  std_logic;
+			Car1_n				: in  std_logic;
+			Car2					: in	std_logic;
+			Car2_n				: in	std_logic;
+			Car3_4_n				: in	std_logic;
+			WhitePF_n			: in  std_logic;
+			BlackPF_n			: in	std_logic;
+			CollRst1_n			: in  std_logic;
+			Collisions1			: out std_logic_vector(1 downto 0)
+			);
+end collision_detect;
+
+architecture rtl of collision_detect is
+
+signal Col_latch_Q		: std_logic_vector(2 downto 1) := (others => '0');
+signal S1_n					: std_logic_vector(2 downto 1);
+signal S2_n					: std_logic_vector(2 downto 1);
+signal R_n					: std_logic_vector(2 downto 1);
+
+
+begin
+
+-- Tristate buffer at E5 route collision signals to data bus 7-6
+Collisions1 <= Col_latch_Q(2 downto 1);
+	
+-- 74LS279 quad SR latch at H6, all inputs are active low
+-- Made synchronous here
+H6: process(Clk6, S1_n, S2_n, R_n, Col_latch_Q)
+begin
+	if rising_edge(Clk6) then
+-- Units 1 and 3 each have an extra Set element, only half of IC is used in Sprint 1
+-- Ordered from top to bottom as drawn in the schematic
+		if R_n(1) = '0' then
+			Col_latch_Q(1) <= '0';
+		elsif (S1_n(1) and S2_n(1)) = '0' then 
+			Col_latch_Q(1) <= '1';
+		else
+			Col_latch_Q(1) <= Col_latch_Q(1);
+		end if;
+		if R_n(2) = '0' then
+			Col_latch_Q(2) <= '0';
+		elsif S1_n(2) = '0' then 
+			Col_latch_Q(2) <= '1';
+		else
+			Col_latch_Q(2) <= Col_latch_Q(2);
+		end if;
+	end if;
+end process;	
+
+-- Glue logic	
+S2_n(1) <= BlackPF_n or Car1_n;
+S1_n(1) <= Car1 nand (Car2_n nand Car3_4_n);
+R_n(1) <= CollRst1_n; 
+
+R_n(2) <= CollRst1_n; 
+S1_n(2) <= Car1_n or WhitePF_n;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/cpu_mem.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/cpu_mem.vhd
new file mode 100644
index 00000000..ff20635b
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/cpu_mem.vhd	
@@ -0,0 +1,506 @@
+-- CPU, RAM, ROM and address decoder for Kee Games Sprint 1
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity CPU_mem is 
+port(		
+			CLK12					: in  std_logic;
+			CLK6					: in  std_logic; -- 6MHz on schematic
+			Reset_n				: in  std_logic;
+			VCount				: in 	std_logic_vector(7 downto 0);
+			HCount				: in  std_logic_vector(8 downto 0);
+			Vblank_s				: in  std_logic; -- Vblank* on schematic
+			Vreset				: in 	std_logic;
+			Hsync_n				: in  std_logic;
+			Test_n				: in  std_logic;
+			Attract				: out std_logic;
+			Skid1					: out std_logic;
+			Skid2					: out std_logic;
+			NoiseReset_n		: out std_logic;
+			CollRst1_n			: out std_logic;
+			CollRst2_n			: out std_logic;
+			Lamp1					: out std_logic;
+			SteerRst1_n			: out std_logic;
+			PHI1_O				: out std_logic;
+			PHI2_O				: out std_logic;
+			DISPLAY				: out	std_logic_vector(7 downto 0);
+			IO_Adr				: out std_logic_vector(9 downto 0);
+			Collisions1			: in  std_logic_vector(1 downto 0);
+			Collisions2			: in  std_logic_vector(1 downto 0);
+			Inputs				: in  std_logic_vector(1 downto 0)
+			);
+end CPU_mem;
+
+architecture rtl of CPU_mem is
+
+signal cpu_clk			: std_logic;
+signal PHI1				: std_logic;
+signal PHI2				: std_logic;
+signal Q5				: std_logic;
+signal Q6				: std_logic;
+signal A7_2				: std_logic;
+signal A7_5				: std_logic;
+signal A7_7				: std_logic;
+
+signal A8_6				: std_logic;
+
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H4				: std_logic;
+
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+
+signal IRQ_n			: std_logic;
+signal NMI_n			: std_logic;
+signal RW_n				: std_logic;
+signal RnW 				: std_logic;
+signal A					: std_logic_vector(15 downto 0);
+signal ADR				: std_logic_vector(9 downto 0);
+signal cpuDin			: std_logic_vector(7 downto 0);
+signal cpuDout			: std_logic_vector(7 downto 0);
+signal DBUS_n			: std_logic_vector(7 downto 0);
+signal DBUS				: std_logic_vector(7 downto 0);
+
+signal ROM1_dout		: std_logic_vector(7 downto 0);
+signal ROM2_dout		: std_logic_vector(7 downto 0);
+signal ROM3_dout		: std_logic_vector(7 downto 0);
+signal ROM4_dout		: std_logic_vector(7 downto 0);
+signal ROM_dout		: std_logic_vector(7 downto 0);
+
+signal ROM1				: std_logic;
+signal ROM2				: std_logic;
+signal ROM3				: std_logic;
+signal ROM4				: std_logic;
+signal ROM_ce			: std_logic;
+signal ROM_mux_in		: std_logic_vector(3 downto 0);
+
+signal cpuRAM_dout	: std_logic_vector(7 downto 0);
+signal Vram_dout		: std_logic_vector(7 downto 0);
+signal RAM_addr		: std_logic_vector(9 downto 0) := (others => '0');
+signal Vram_addr		: std_logic_vector(9 downto 0) := (others => '0');
+signal scanbus			: std_logic_vector(9 downto 0) := (others => '0');
+signal RAM_dout		: std_logic_vector(7 downto 0);
+signal RAM_we			: std_logic;
+signal RAM_RW_n 		: std_logic;
+signal RAM_ce_n		: std_logic;
+signal RAM_n			: std_logic; 
+signal WRAM				: std_logic;
+signal WRITE_n			: std_logic;
+
+signal F2_in			: std_logic_vector(3 downto 0);
+signal F2_out			: std_logic_vector(9 downto 0);
+signal D2_in			: std_logic_vector(3 downto 0);
+signal D2_out			: std_logic_vector(9 downto 0);
+signal E8_in			: std_logic_vector(3 downto 0);
+signal E8_out			: std_logic_vector(9 downto 0);
+signal P3_8				: std_logic;
+
+signal Sync			   : std_logic;
+signal Sync_n			: std_logic;
+signal Switch_n		: std_logic;
+signal Display_n		: std_logic;
+signal Addec_bus		: std_logic_vector(7 downto 0);
+
+signal Timer_Reset_n	: std_logic := '1';
+signal Collision1_n	: std_logic := '1';
+signal Collision2_n	: std_logic := '1';
+signal Attract_int	: std_logic := '1';
+
+signal J6_5				: std_logic;
+signal J6_9				: std_logic;
+
+signal Coin1			: std_logic;
+signal Coin2			: std_logic;
+signal Input_mux 		: std_logic;
+signal A8_8				: std_logic;
+signal H9_Q_n			: std_logic;
+signal J9_out			: std_logic_vector(7 downto 0);
+
+signal H8_en			: std_logic;
+
+begin
+
+H8 <= HCount(3);
+H16 <=  HCount(4);
+H32 <= HCount(5);
+H64 <= HCount(6);
+H128 <= HCount(7);
+H256 <= HCount(8);
+H256_n <= (not HCount(8));
+
+V8 <= VCount(3);
+V16 <= VCount(4);
+V32 <= VCount(5);
+V64 <= VCount(6);
+V128 <= VCount(7);
+
+
+CPU: entity work.T65
+port map(
+		Enable => '1',
+		Mode => "00",
+		Res_n => reset_n,
+		Clk => phi1,
+		Rdy => '1',
+		Abort_n => '1',
+		IRQ_n => '1',
+		NMI_n => NMI_n,
+		SO_n => '1',
+		R_W_n => RW_n,
+		A(15 downto 0) => A,
+		DI => cpuDin,
+		DO => cpuDout
+		);
+		
+DBUS_n <= (not cpuDout); -- Data bus to video RAM is inverted
+ADR(9 downto 7) <= (A(9) or WRAM) & (A(8) or WRAM) & (A(7) or WRAM);
+ADR(6 downto 0) <= A(6 downto 0);
+RnW <= (not RW_n);
+IO_Adr <= Adr;
+NMI_n <= not (Vblank_s and Test_n);
+
+		
+-- CPU clock
+H4 <= Hcount(2);
+CPU_clock: process(clk12, H4, Q5, Q6)
+begin
+	if rising_edge(clk12) then
+		Q5 <= H4;
+		Q6 <= Q5;
+	end if;
+	phi1 <= not (Q5 or Q6); --?
+end process;
+
+PHI2 <= (not PHI1);
+PHI1_O <= PHI1;
+PHI2_O <= PHI2;
+
+
+A8_6 <= not(RnW and PHI2 and H4 and WRITE_n);
+A7: process(clk12, A8_6) -- Shift register chain of 4 DFF's clocked by clk12, creates a delayed WRITE_n
+begin
+	if rising_edge(clk12) then
+		A7_2 <= A8_6;
+		A7_5 <= A7_2;
+		A7_7 <= A7_5;
+		WRITE_n <= A7_7;
+	end if;
+end process;
+		
+
+-- Program ROMs
+A1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6290-01b1.hex",
+		widthad_a => 11,
+		width_a => 8)
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom1_dout
+		);
+		
+--A1: entity work.prog_rom1
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom1_dout
+--		);
+
+C1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6291-01c1.hex",
+		widthad_a => 11,
+		width_a => 8)
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom2_dout
+		);
+		
+--C1: entity work.prog_rom2
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom2_dout
+--		);
+
+D1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6442-01d1.hex",
+		widthad_a => 11,
+		width_a => 8)
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom3_dout
+		);
+
+--D1: entity work.prog_rom3
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom3_dout
+--		);
+
+E1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6443-01e1.hex",
+		widthad_a => 11,
+		width_a => 8)
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom4_dout
+		);
+		
+--E1: entity work.prog_rom4
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom4_dout
+--		);
+
+-- ROM data mux
+ROM_mux_in <= (ROM1 & ROM2 & ROM3 & ROM4);
+ROM_mux: process(ROM_mux_in, rom1_dout, rom2_dout, rom3_dout, rom4_dout)
+begin
+	ROM_dout <= (others => '0');
+ case ROM_mux_in is
+ 	when "1000" => rom_dout <= rom1_dout;
+	when "0100" => rom_dout <= rom2_dout;
+	when "0010" => rom_dout <= rom3_dout;
+	when "0001" => rom_dout <= rom4_dout;
+	when others => null;
+ end case;
+end process;
+
+-- RAM 
+-- The original hardware multiplexes access to the RAM between the CPU and video hardware. In the FPGA it's
+-- easier to use dual-ported RAM
+RAM: entity work.dpram
+generic map(
+	widthad_a => 10,
+	width_a => 8)
+port map(
+	clock_a => clk6,
+-- CPU side	
+	address_a => adr(9 downto 0),
+	wren_a => ram_we,
+	data_a => DBUS_n,
+	q_a=> CPUram_dout,
+
+-- Video side
+	clock_b => clk6,
+	address_b => Vram_addr,
+	wren_b => '0',
+	data_b => x"FF",
+	q_b => Vram_dout
+	);
+	
+--RAM: entity work.ram1k_dp
+--port map(
+--	clock => clk6,
+-- CPU side	
+--	address_a => adr(9 downto 0),
+--	wren_a => ram_we,
+--	data_a => DBUS_n,
+--	q_a=> CPUram_dout,
+
+-- Video side
+--	address_b => Vram_addr,
+--	wren_b => '0',
+--	data_b => x"FF",
+--	q_b => Vram_dout
+--	);
+
+Vram_addr <= (V128 or H256_n) & (V64 or H256_n) & (V32 or H256_n) & (V16 and H256) & 	(V8 and H256) & H128 & H64 & H32 & H16 & H8;
+
+-- Real hardware has both WE and CE which are selected by K2 according to the state of the phase 2 clock
+-- Altera block RAM has active high WE, original RAM had active low WE
+ram_we <= (not Write_n) and (not Display_n) and Phi2;
+	
+-- Rising edge of phi2 clock latches inverted output of VRAM data bus 	
+F5: process(phi2)
+begin
+	if rising_edge(phi2) then
+		display <= not Vram_dout;
+	end if;
+end process;
+
+	
+-- Address decoder
+-- A15 and A14 are not used
+-- Original circuit uses a bipolar PROM in the address decoder, this could be replaced with combinational logic
+
+-- E2 PROM 
+K6: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6401-01e2.hex",
+		widthad_a => 5,
+		width_a => 8)
+port map(
+		clock => clk12,
+	address => A(13 downto 9),
+	q => addec_bus
+	);
+		
+--E2: entity work.addec_prom
+--port map(
+--	clock => clk12,
+--	address => A(13 downto 9),
+--	q => addec_bus
+--	);
+
+F2_in <= addec_bus(0) & addec_bus(1) & addec_bus(2) & addec_bus(3);	
+WRAM <= addec_bus(4);
+D2_in <= RnW & addec_bus(5) & addec_bus(6) & addec_bus(7);
+	
+-- Decoder code could be cleaned up a bit, unused decoder states are not explicitly implemented
+F2: process(F2_in)
+begin
+	case F2_in is
+      when "0000" =>
+         F2_out <= "1111111110";
+      when "0001" =>
+         F2_out <= "1111111101";
+      when "0010" =>
+         F2_out <= "1111111011";
+      when "0011" =>
+         F2_out <= "1111110111";
+      when "0100" =>
+         F2_out <= "1111101111";
+      when "0101" =>
+         F2_out <= "1111011111";
+      when "0110" =>
+         F2_out <= "1110111111";
+      when "0111" =>
+         F2_out <= "1101111111";
+      when others =>
+         F2_out <= "1111111111";
+      end case;
+end process;
+
+ROM1 <= (F2_out(0) nand F2_out(1));
+ROM2 <= (F2_out(2) nand F2_out(3));
+ROM3 <= (F2_out(4) nand F2_out(5));
+ROM4 <= (F2_out(6) nand F2_out(7));
+ROM_ce <= (ROM1 or ROM2 or ROM3 or ROM4);
+
+D2: process(D2_in)
+begin
+	case D2_in is
+		when "0000" =>
+         D2_out <= "1111111110";
+		when "0001" =>
+         D2_out <= "1111111101";
+      when "0010" =>
+         D2_out <= "1111111011";
+      when "0011" =>
+         D2_out <= "1111110111";
+      when "0100" =>
+         D2_out <= "1111101111";
+      when "1000" =>
+         D2_out <= "1011111111";
+      when "1001" =>
+         D2_out <= "0111111111";
+      when others =>
+         D2_out <= "1111111111";
+      end case;
+end process;	
+
+RAM_n <= D2_out(0);
+SYNC_n <= D2_out(1);
+SYNC <= (not SYNC_n);
+SWITCH_n <= D2_out(2);
+COLLISION1_n <= D2_out(3);
+COLLISION2_n <= D2_out(4);
+DISPLAY_n <= (D2_out(0) and D2_out(8));
+P3_8 <= (D2_out(9) or WRITE_n);
+
+E8_in <= P3_8 & ADR(9 downto 7);
+
+E8: process(E8_in)
+begin
+	case E8_in is
+		when "0000" =>
+         E8_out <= "1111111110";
+		when "0001" =>
+         E8_out <= "1111111101";
+		when "0010" =>
+         E8_out <= "1111111011";
+		when "0011" =>
+         E8_out <= "1111110111";
+      when "0100" =>
+         E8_out <= "1111101111";
+      when "0101" =>
+         E8_out <= "1111011111";
+      when "0110" =>
+         E8_out <= "1110111111";
+      when others =>
+         E8_out <= "1111111111";
+      end case;
+end process;
+
+H8_en <= E8_out(0);
+Timer_Reset_n <= E8_out(1);
+CollRst1_n <= E8_out(2);
+CollRst2_n <= E8_out(3);
+SteerRst1_n <= E8_out(4);
+NoiseReset_n <= E8_out(6);
+
+-- H8 9334 
+H8_dec: process(clk6, Adr)
+begin
+if rising_edge(clk6) then
+	if (H8_en = '0') then
+	  case Adr(6 downto 4) is
+		 when "000" => Attract_int <= Adr(0);
+		 when "001" => Skid1 <= Adr(0);
+		 when "010" => null;
+		 when "011" => LAMP1 <= Adr(0);
+		 when "100" => null;
+		 when "101" => null; -- "Spare" on schematic
+		 when "110" => null;
+		 when "111" => null;
+		 when others => null;
+	  end case;
+	end if;
+ end if;
+end process;		
+Attract <= Attract_Int;
+
+-- CPU Din mux
+cpuDin <= 	ROM_dout when rom_ce = '1' else 
+				(not CPUram_dout) when Display_n = '0' else -- Remember RAM data is inverted
+				VCount(7) & VBlank_s & Vreset & Attract_int & "1111" when Sync_n = '0' else -- Using V128 (VCount(7)) in place of 60Hz mains reference
+				Collisions1 & "111111" when Collision1_n = '0' else
+				Inputs & "111111" when SWITCH_n = '0' else
+				x"FF";
+				
+end rtl;
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/dac.sv b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/dac.sv
new file mode 100644
index 00000000..22ae8f07
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/dac.sv	
@@ -0,0 +1,33 @@
+//
+// PWM DAC
+//
+// MSBI is the highest bit number. NOT amount of bits!
+//
+module dac #(parameter MSBI=6, parameter INV=1'b1)
+(
+   output reg      DACout, //Average Output feeding analog lowpass
+   input  [MSBI:0] DACin,  //DAC input (excess 2**MSBI)
+   input           CLK,
+   input           RESET
+);
+
+reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
+reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
+reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
+reg [MSBI+2:0] DeltaB;     //B input of Delta Adder
+
+always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
+always @(*) DeltaAdder = DACin + DeltaB;
+always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
+
+always @(posedge CLK or posedge RESET) begin
+   if(RESET) begin
+      SigmaLatch <= 1'b1 << (MSBI+1);
+      DACout <= INV;
+   end else begin
+      SigmaLatch <= SigmaAdder;
+      DACout <= SigmaLatch[MSBI+2] ^ INV;
+   end
+end
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/dpram.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..9ea85a26
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/dpram.vhd	
@@ -0,0 +1,130 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram IS
+	GENERIC
+	(
+		init_file			: string := "";
+		widthad_a			: natural;
+		width_a				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED";
+    outdata_reg_b : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(width_a-1 DOWNTO 0);
+	q_b    <= sub_wire1(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		numwords_b => 2**widthad_a,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		outdata_reg_b => outdata_reg_a,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => widthad_a,
+		widthad_b => widthad_a,
+		width_a => width_a,
+		width_b => width_a,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/hq2x.sv b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/hq2x.sv
new file mode 100644
index 00000000..f17732b6
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/hq2x.sv	
@@ -0,0 +1,454 @@
+//
+//
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+`define BITS_TO_FIT(N) ( \
+     N <=   2 ? 0 : \
+     N <=   4 ? 1 : \
+     N <=   8 ? 2 : \
+     N <=  16 ? 3 : \
+     N <=  32 ? 4 : \
+     N <=  64 ? 5 : \
+     N <= 128 ? 6 : \
+     N <= 256 ? 7 : \
+     N <= 512 ? 8 : \
+     N <=1024 ? 9 : 10 )
+
+module hq2x_in #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input            rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input            wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+	wire [DWIDTH:0] out[2];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+endmodule
+
+
+module hq2x_out #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input      [1:0] rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input      [1:0] wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
+	wire  [DWIDTH:0] out[4];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
+endmodule
+
+
+module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
+(
+	input	            clock,
+	input	 [DWIDTH:0] data,
+	input	 [AWIDTH:0] rdaddress,
+	input	 [AWIDTH:0] wraddress,
+	input	            wren,
+	output [DWIDTH:0] q
+);
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b(q),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({(DWIDTH+1){1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = NUMWORDS,
+		altsyncram_component.numwords_b = NUMWORDS,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = AWIDTH+1,
+		altsyncram_component.widthad_b = AWIDTH+1,
+		altsyncram_component.width_a = DWIDTH+1,
+		altsyncram_component.width_b = DWIDTH+1,
+		altsyncram_component.width_byteena_a = 1;
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DiffCheck
+(
+	input [17:0] rgb1,
+	input [17:0] rgb2,
+	output result
+);
+
+	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
+	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
+	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
+	wire [6:0] t = $signed(r) + $signed(b);
+	wire [6:0] gx = {g[5], g};
+	wire [7:0] y = $signed(t) + $signed(gx);
+	wire [6:0] u = $signed(r) - $signed(b);
+	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
+
+	// if y is inside (-24..24)
+	wire y_inside = (y < 8'h18 || y >= 8'he8);
+
+	// if u is inside (-4, 4)
+	wire u_inside = (u < 7'h4 || u >= 7'h7c);
+
+	// if v is inside (-6, 6)
+	wire v_inside = (v < 8'h6 || v >= 8'hfA);
+	assign result = !(y_inside && u_inside && v_inside);
+endmodule
+
+module InnerBlend
+(
+	input  [8:0] Op,
+	input  [5:0] A,
+	input  [5:0] B,
+	input  [5:0] C,
+	output [5:0] O
+);
+
+	function  [8:0] mul6x3;
+		input  [5:0] op1;
+		input  [2:0] op2;
+	begin
+		mul6x3 = 9'd0;
+		if(op2[0]) mul6x3 = mul6x3 + op1;
+		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
+		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
+	end
+	endfunction
+
+	wire OpOnes = Op[4];
+	wire [8:0] Amul = mul6x3(A, Op[7:5]);
+	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
+	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
+	wire [8:0] At =  Amul;
+	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
+	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
+	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
+	assign O = Op[8] ? A : Res[9:4];
+endmodule
+
+module Blend
+(
+	input   [5:0] rule,
+	input         disable_hq2x,
+	input  [17:0] E,
+	input  [17:0] A,
+	input  [17:0] B,
+	input  [17:0] D,
+	input  [17:0] F,
+	input  [17:0] H,
+	output [17:0] Result
+);
+
+	reg [1:0] input_ctrl;
+	reg [8:0] op;
+	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
+	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
+	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
+	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
+	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
+	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
+	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
+	localparam AB = 2'b00;
+	localparam AD = 2'b01;
+	localparam DB = 2'b10;
+	localparam BD = 2'b11;
+	wire is_diff;
+	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
+
+	always @* begin
+		case({!is_diff, rule[5:2]})
+			1,17:  {op, input_ctrl} = {BLEND1, AB};
+			2,18:  {op, input_ctrl} = {BLEND1, DB};
+			3,19:  {op, input_ctrl} = {BLEND1, BD};
+			4,20:  {op, input_ctrl} = {BLEND2, DB};
+			5,21:  {op, input_ctrl} = {BLEND2, AB};
+			6,22:  {op, input_ctrl} = {BLEND2, AD};
+
+			8: {op, input_ctrl} = {BLEND0, 2'bxx};
+			9: {op, input_ctrl} = {BLEND0, 2'bxx};
+			10: {op, input_ctrl} = {BLEND0, 2'bxx};
+			11: {op, input_ctrl} = {BLEND1, AB};
+			12: {op, input_ctrl} = {BLEND1, AB};
+			13: {op, input_ctrl} = {BLEND1, AB};
+			14: {op, input_ctrl} = {BLEND1, DB};
+			15: {op, input_ctrl} = {BLEND1, BD};
+
+			24: {op, input_ctrl} = {BLEND2, DB};
+			25: {op, input_ctrl} = {BLEND5, DB};
+			26: {op, input_ctrl} = {BLEND6, DB};
+			27: {op, input_ctrl} = {BLEND2, DB};
+			28: {op, input_ctrl} = {BLEND4, DB};
+			29: {op, input_ctrl} = {BLEND5, DB};
+			30: {op, input_ctrl} = {BLEND3, BD};
+			31: {op, input_ctrl} = {BLEND3, DB};
+			default: {op, input_ctrl} = 11'bx;
+		endcase
+
+		// Setting op[8] effectively disables HQ2X because blend will always return E.
+		if (disable_hq2x) op[8] = 1;
+	end
+
+	// Generate inputs to the inner blender. Valid combinations.
+	// 00: E A B
+	// 01: E A D 
+	// 10: E D B
+	// 11: E B D
+	wire [17:0] Input1 = E;
+	wire [17:0] Input2 = !input_ctrl[1] ? A :
+                        !input_ctrl[0] ? D : B;
+
+	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
+	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
+	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
+	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
+endmodule
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	input               clk,
+	input               ce_x4,
+	input    [DWIDTH:0] inputpixel,
+	input               mono,
+	input               disable_hq2x,
+	input               reset_frame,
+	input               reset_line,
+	input         [1:0] read_y,
+	input  [AWIDTH+1:0] read_x,
+	output   [DWIDTH:0] outpixel
+);
+
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+localparam DWIDTH = HALF_DEPTH ? 8 : 17;
+
+wire [5:0] hqTable[256] = '{
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
+};
+
+reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
+reg [17:0] A, B, D, F, G, H;
+reg  [7:0] pattern, nextpatt;
+reg  [1:0] i;
+reg  [7:0] y;
+
+wire curbuf = y[0];
+reg  prevbuf = 0;
+wire iobuf = !curbuf;
+
+wire diff0, diff1;
+DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
+DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
+
+wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
+
+wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
+wire [17:0] blend_result;
+Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
+
+reg             Curr2_addr1;
+reg  [AWIDTH:0] Curr2_addr2;
+wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
+wire [DWIDTH:0] Curr2tmp;
+
+reg  [AWIDTH:0] wrin_addr2;
+reg  [DWIDTH:0] wrpix;
+reg             wrin_en;
+
+function [17:0] h2rgb;
+	input  [8:0] v;
+begin
+	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
+end
+endfunction
+
+function  [8:0] rgb2h;
+	input [17:0] v;
+begin
+	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
+end
+endfunction
+
+hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
+(
+	.clk(clk),
+
+	.rdaddr(Curr2_addr2),
+	.rdbuf(Curr2_addr1),
+	.q(Curr2tmp),
+
+	.wraddr(wrin_addr2),
+	.wrbuf(iobuf),
+	.data(wrpix),
+	.wren(wrin_en)
+);
+
+reg         [1:0] wrout_addr1;
+reg  [AWIDTH+1:0] wrout_addr2;
+reg               wrout_en;
+reg    [DWIDTH:0] wrdata;
+
+hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
+(
+	.clk(clk),
+
+	.rdaddr(read_x),
+	.rdbuf(read_y),
+	.q(outpixel),
+
+	.wraddr(wrout_addr2),
+	.wrbuf(wrout_addr1),
+	.data(wrdata),
+	.wren(wrout_en)
+);
+
+always @(posedge clk) begin
+	reg [AWIDTH:0] offs;
+	reg old_reset_line;
+	reg old_reset_frame;
+
+	wrout_en <= 0;
+	wrin_en  <= 0;
+
+	if(ce_x4) begin
+
+		pattern <= new_pattern;
+
+		if(~&offs) begin
+			if (i == 0) begin
+				Curr2_addr1 <= prevbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 1) begin
+				Prev2 <= Curr2;
+				Curr2_addr1 <= curbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 2) begin
+				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
+				wrpix <= inputpixel;
+				wrin_addr2 <= offs;
+				wrin_en <= 1;
+			end
+			if (i == 3) begin
+				offs <= offs + 1'd1;
+			end
+
+			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
+			else           wrdata <= blend_result;
+
+			wrout_addr1 <= {curbuf, i[1]};
+			wrout_addr2 <= {offs, i[1]^i[0]};
+			wrout_en    <= 1;
+		end
+
+		if(i==3) begin
+			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
+			{A, G} <= {Prev0, Next0};
+			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
+			{Prev0, Prev1} <= {Prev1, Prev2};
+			{Curr0, Curr1} <= {Curr1, Curr2};
+			{Next0, Next1} <= {Next1, Next2};
+		end else begin
+			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
+			{B, F, H, D} <= {F, H, D, B};
+		end
+
+		i <= i + 1'b1;
+		if(old_reset_line && ~reset_line) begin
+			old_reset_frame <= reset_frame;
+			offs <= 0;
+			i <= 0;
+			y <= y + 1'd1;
+			prevbuf <= curbuf;
+			if(old_reset_frame & ~reset_frame) begin
+				y <= 0;
+				prevbuf <= 0;
+			end
+		end
+
+		old_reset_line  <= reset_line;
+	end
+end
+
+endmodule  // Hq2x
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/keyboard.sv b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/keyboard.sv
new file mode 100644
index 00000000..ce182b0a
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/keyboard.sv	
@@ -0,0 +1,84 @@
+
+
+module keyboard
+(
+	input  clk,
+	input  reset,
+	input  ps2_kbd_clk,
+	input  ps2_kbd_data,
+
+	output reg[11:0] joystick
+);
+
+reg [11:0] shift_reg = 12'hFFF;
+wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
+wire [7:0] kcode = kdata[9:2];
+reg        release_btn = 0;
+
+reg  [7:0] code;
+reg        input_strobe = 0;
+
+always @(negedge clk) begin
+	reg old_reset = 0;
+
+	old_reset <= reset;
+
+	if(~old_reset & reset)begin
+		joystick <= 0;
+	end
+
+	if(input_strobe) begin
+		case(code)
+			'h75: joystick[3] <= ~release_btn; // arrow up
+			'h72: joystick[2] <= ~release_btn; // arrow down
+			'h6B: joystick[1] <= ~release_btn; // arrow left
+			'h74: joystick[0] <= ~release_btn; // arrow right
+
+			'h29: joystick[4] <= ~release_btn; // Space
+			'h05: joystick[5] <= ~release_btn; // F1
+			'h06: joystick[6] <= ~release_btn; // F2
+			'h76: joystick[7] <= ~release_btn; // Escape
+			
+			'h69: joystick[8] <= ~release_btn; // 1
+			'h72: joystick[9] <= ~release_btn; // 2
+			'h7A: joystick[10] <= ~release_btn; // 3
+			'h6B: joystick[11] <= ~release_btn; // 4
+		endcase
+	end
+end
+
+always @(posedge clk) begin
+	reg [3:0] prev_clk  = 0;
+	reg       old_reset = 0;
+	reg       action = 0;
+
+	old_reset <= reset;
+	input_strobe <= 0;
+
+	if(~old_reset & reset)begin
+		prev_clk  <= 0;
+		shift_reg <= 12'hFFF;
+	end else begin
+		prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
+		if(prev_clk == 1) begin
+			if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
+				shift_reg <= 12'hFFF;
+				if (kcode == 8'he0) ;
+				// Extended key code follows
+				else if (kcode == 8'hf0)
+					// Release code follows
+					action <= 1;
+				else begin
+					// Cancel extended/release flags for next time
+					action <= 0;
+					release_btn <= action;
+					code <= kcode;
+					input_strobe <= 1;
+				end
+			end else begin
+				shift_reg <= kdata;
+			end
+		end
+	end
+end
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/mist_io.sv b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/mist_io.sv
new file mode 100644
index 00000000..dcc7ecde
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/mist_io.sv	
@@ -0,0 +1,491 @@
+//
+// mist_io.v
+//
+// mist_io for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+//
+// Use buffer to access SD card. It's time-critical part.
+// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
+//                                                           (Sorgelig)
+//
+// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
+// clk_ps2 = clk_sys/(PS2DIV*2)
+//
+
+module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
+(
+
+	// parameter STRLEN and the actual length of conf_str have to match
+	input [(8*STRLEN)-1:0] conf_str,
+
+	// Global clock. It should be around 100MHz (higher is better).
+	input             clk_sys,
+
+	// Global SPI clock from ARM. 24MHz
+	input             SPI_SCK,
+
+	input             CONF_DATA0,
+	input             SPI_SS2,
+	output            SPI_DO,
+	input             SPI_DI,
+
+	output reg  [7:0] joystick_0,
+	output reg  [7:0] joystick_1,
+	output reg [15:0] joystick_analog_0,
+	output reg [15:0] joystick_analog_1,
+	output      [1:0] buttons,
+	output      [1:0] switches,
+	output            scandoubler_disable,
+	output            ypbpr,
+
+	output reg [31:0] status,
+
+	// SD config
+	input             sd_conf,
+	input             sd_sdhc,
+	output            img_mounted, // signaling that new image has been mounted
+	output reg [31:0] img_size,    // size of image in bytes
+
+	// SD block level access
+	input      [31:0] sd_lba,
+	input             sd_rd,
+	input             sd_wr,
+	output reg        sd_ack,
+	output reg        sd_ack_conf,
+
+	// SD byte level access. Signals for 2-PORT altsyncram.
+	output reg  [8:0] sd_buff_addr,
+	output reg  [7:0] sd_buff_dout,
+	input       [7:0] sd_buff_din,
+	output reg        sd_buff_wr,
+
+	// ps2 keyboard emulation
+	output            ps2_kbd_clk,
+	output reg        ps2_kbd_data,
+	output            ps2_mouse_clk,
+	output reg        ps2_mouse_data,
+	input             ps2_caps_led,
+
+	// ARM -> FPGA download
+	output reg        ioctl_download = 0, // signal indicating an active download
+	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output            ioctl_wr,
+	output reg [23:0] ioctl_addr,
+	output reg  [7:0] ioctl_dout
+);
+
+reg [7:0] b_data;
+reg [6:0] sbuf;
+reg [7:0] cmd;
+reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
+reg [9:0] byte_cnt;   // counts bytes
+reg [7:0] but_sw;
+reg [2:0] stick_idx;
+
+reg    mount_strobe = 0;
+assign img_mounted  = mount_strobe;
+
+assign buttons = but_sw[1:0];
+assign switches = but_sw[3:2];
+assign scandoubler_disable = but_sw[4];
+assign ypbpr = but_sw[5];
+
+wire [7:0] spi_dout = { sbuf, SPI_DI};
+
+// this variant of user_io is for 8 bit cores (type == a4) only
+wire [7:0] core_type = 8'ha4;
+
+// command byte read by the io controller
+wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
+
+reg spi_do;
+assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
+
+wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
+
+// drive MISO only when transmitting core id
+always@(negedge SPI_SCK) begin
+	if(!CONF_DATA0) begin
+		// first byte returned is always core type, further bytes are 
+		// command dependent
+      if(byte_cnt == 0) begin
+		  spi_do <= core_type[~bit_cnt];
+
+		end else begin
+			case(cmd)
+				// reading config string
+				8'h14: begin
+					// returning a byte from string
+						if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
+							else spi_do <= 0;
+					end
+
+				// reading sd card status
+				8'h16: begin
+						if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
+						else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
+						else spi_do <= 0;
+					end
+
+				// reading sd card write data
+				8'h18:
+						spi_do <= b_data[~bit_cnt];
+
+				// reading keyboard LED status
+				8'h1f:
+						spi_do <= kbd_led[~bit_cnt];
+
+				default:
+						spi_do <= 0;
+			endcase
+		end
+   end
+end
+
+reg b_wr2,b_wr3;
+always @(negedge clk_sys) begin
+	b_wr3      <= b_wr2;
+	sd_buff_wr <= b_wr3;
+end
+
+// SPI receiver
+always@(posedge SPI_SCK or posedge CONF_DATA0) begin
+
+	if(CONF_DATA0) begin
+		b_wr2 <= 0;
+	   bit_cnt <= 0;
+	   byte_cnt <= 0;
+		sd_ack <= 0;
+		sd_ack_conf <= 0;
+	end else begin
+		b_wr2 <= 0;
+
+		sbuf <= spi_dout[6:0];
+		bit_cnt <= bit_cnt + 1'd1;
+		if(bit_cnt == 5) begin
+			if (byte_cnt == 0) sd_buff_addr <= 0;
+			if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
+			if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
+		end
+
+		// finished reading command byte
+      if(bit_cnt == 7) begin
+			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
+			if(byte_cnt == 0) begin
+				cmd <= spi_dout;
+
+				if(spi_dout == 8'h19) begin
+					sd_ack_conf  <= 1;
+					sd_buff_addr <= 0;
+				end
+				if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
+					sd_ack       <= 1;
+					sd_buff_addr <= 0;
+				end
+				if(spi_dout == 8'h18) b_data <= sd_buff_din;
+
+				mount_strobe <= 0;
+
+			end else begin
+			
+				case(cmd)
+					// buttons and switches
+					8'h01: but_sw <= spi_dout; 
+					8'h02: joystick_0 <= spi_dout;
+					8'h03: joystick_1 <= spi_dout;
+
+					// store incoming ps2 mouse bytes 
+					8'h04: begin
+							ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; 
+							ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
+						end
+
+					// store incoming ps2 keyboard bytes 
+					8'h05: begin
+							ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; 
+							ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
+						end
+				
+					8'h15: status[7:0] <= spi_dout;
+				
+					// send SD config IO -> FPGA
+					// flag that download begins
+					// sd card knows data is config if sd_dout_strobe is asserted
+					// with sd_ack still being inactive (low)
+					8'h19,
+					// send sector IO -> FPGA
+					// flag that download begins
+					8'h17: begin
+							sd_buff_dout <= spi_dout;
+							b_wr2 <= 1;
+						end
+
+					8'h18: b_data <= sd_buff_din;
+
+					// joystick analog
+					8'h1a: begin
+							// first byte is joystick index
+							if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
+							else if(byte_cnt == 2) begin
+								// second byte is x axis
+								if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
+									else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
+							end else if(byte_cnt == 3) begin
+								// third byte is y axis
+								if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
+									else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
+							end
+						end
+
+					// notify image selection
+					8'h1c: mount_strobe <= 1;
+
+					// send image info
+					8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
+
+					// status, 32bit version
+					8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
+					default: ;
+				endcase
+			end
+		end
+	end
+end
+
+
+///////////////////////////////   PS2   ///////////////////////////////
+// 8 byte fifos to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
+
+reg clk_ps2;
+always @(negedge clk_sys) begin
+	integer cnt;
+	cnt <= cnt + 1'd1;
+	if(cnt == PS2DIV) begin
+		clk_ps2 <= ~clk_ps2;
+		cnt <= 0;
+	end
+end
+
+// keyboard
+reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_kbd_tx_state;
+reg [7:0] ps2_kbd_tx_byte;
+reg ps2_kbd_parity;
+
+assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_kbd_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_kbd_r_inc <= 0;
+
+		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_kbd_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
+				// load tx register from fifo
+				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
+				ps2_kbd_r_inc <= 1;
+
+				// reset parity
+				ps2_kbd_parity <= 1;
+
+				// start transmitter
+				ps2_kbd_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_kbd_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
+				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
+				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
+				if(ps2_kbd_tx_byte[0]) 
+					ps2_kbd_parity <= !ps2_kbd_parity;
+			end
+
+			// transmission of parity
+			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
+
+			// transmission of stop bit
+			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
+
+			// advance state machine
+			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
+				else ps2_kbd_tx_state <= 0;
+		end
+	end
+end
+
+// mouse
+reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_mouse_tx_state;
+reg [7:0] ps2_mouse_tx_byte;
+reg ps2_mouse_parity;
+
+assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_mouse_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_mouse_r_inc <= 0;
+
+		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_mouse_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
+				// load tx register from fifo
+				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
+				ps2_mouse_r_inc <= 1;
+
+				// reset parity
+				ps2_mouse_parity <= 1;
+
+				// start transmitter
+				ps2_mouse_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_mouse_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
+				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
+				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
+				if(ps2_mouse_tx_byte[0]) 
+					ps2_mouse_parity <= !ps2_mouse_parity;
+			end
+
+			// transmission of parity
+			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
+
+			// transmission of stop bit
+			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
+
+			// advance state machine
+			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
+				else ps2_mouse_tx_state <= 0;
+		end
+	end
+end
+
+
+///////////////////////////////   DOWNLOADING   ///////////////////////////////
+
+reg  [7:0] data_w;
+reg [23:0] addr_w;
+reg        rclk   = 0;
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+
+// data_io has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS2) begin
+	reg  [6:0] sbuf;
+	reg  [7:0] cmd;
+	reg  [4:0] cnt;
+	reg [23:0] addr;
+
+	if(SPI_SS2) cnt <= 0;
+	else begin
+		rclk <= 0;
+
+		// don't shift in last bit. It is evaluated directly
+		// when writing to ram
+		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
+
+		// increase target address after write
+		if(rclk) addr <= addr + 1'd1;
+
+		// count 0-7 8-15 8-15 ... 
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		// finished command byte
+      if(cnt == 7) cmd <= {sbuf, SPI_DI};
+
+		// prepare/end transmission
+		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
+			// prepare 
+			if(SPI_DI) begin
+				addr <= 0;
+				ioctl_download <= 1; 
+			end else begin
+				addr_w <= addr;
+				ioctl_download <= 0;
+			end
+		end
+
+		// command 0x54: UIO_FILE_TX
+		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
+			addr_w <= addr;
+			data_w <= {sbuf, SPI_DI};
+			rclk <= 1;
+		end
+
+      // expose file (menu) index
+      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
+	end
+end
+
+assign ioctl_wr = |ioctl_wrd;
+reg [1:0] ioctl_wrd;
+
+always@(negedge clk_sys) begin
+	reg        rclkD, rclkD2;
+
+	rclkD    <= rclk;
+	rclkD2   <= rclkD;
+	ioctl_wrd<= {ioctl_wrd[0],1'b0};
+
+	if(rclkD & ~rclkD2) begin
+		ioctl_dout <= data_w;
+		ioctl_addr <= addr_w;
+		ioctl_wrd  <= 2'b11;
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/motion.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/motion.vhd
new file mode 100644
index 00000000..561209eb
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/motion.vhd	
@@ -0,0 +1,381 @@
+-- Motion object generation circuitry for Kee Games Sprint 1
+-- This generates the four cars which are the only moving objects in the game
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity motion is 
+port(		
+			CLK6			: in  std_logic; -- 6MHz* on schematic
+			CLK12			: in  std_logic;
+			PHI2			: in  std_logic;
+			DISPLAY		: in  std_logic_vector(7 downto 0);
+			H256_s		: in  std_logic; -- 256H* on schematic
+			VCount		: in  std_logic_vector(7 downto 0);
+			HCount		: in  std_logic_vector(8 downto 0);
+			Crash_n		: out std_logic;
+			Motor1_n		: out std_logic;
+			Car1  		: out std_logic;
+			Car1_n  		: out std_logic;
+			Car2  		: out std_logic;
+			Car2_n  		: out std_logic;
+			Car3_4_n  	: out std_logic
+			);
+end motion;
+
+architecture rtl of motion is
+
+signal phi0			: std_logic;
+
+signal LDH1_n		: std_logic;
+signal LDH2_n		: std_logic;
+signal LDH3_n		: std_logic;
+signal LDH4_n		: std_logic;
+
+signal LDV1A_n		: std_logic;
+signal LDV2A_n		: std_logic;
+signal LDV3A_n		: std_logic;
+signal LDV4A_n		: std_logic;
+
+signal LDV1B_n		: std_logic;
+signal LDV2B_n		: std_logic;
+signal LDV3B_n		: std_logic;
+signal LDV4B_n		: std_logic;
+
+signal Car1_Inh	: std_logic;
+signal Car2_Inh	: std_logic;
+signal Car3_Inh	: std_logic;
+signal Car4_Inh	: std_logic;
+
+signal VPos_sum		: std_logic_vector(7 downto 0) := x"00";
+signal N4_8			: std_logic;
+
+signal H256_n		: std_logic;
+signal H256			: std_logic;
+signal H64 			: std_logic;
+signal H32			: std_logic;
+signal H16			: std_logic;
+signal H8			: std_logic;
+signal H4			: std_logic;
+
+signal L5_reg		: std_logic_vector(3 downto 0);
+
+signal J8_3			: std_logic;
+signal J8_6			: std_logic;
+
+signal K8_in		: std_logic_vector(3 downto 0);
+signal K8_out		: std_logic_vector(9 downto 0);
+signal P7_in		: std_logic_vector(3 downto 0);
+signal P7_out		: std_logic_vector(9 downto 0);
+
+signal Car1_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+signal Car2_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+signal Car3_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+signal Car4_Hpos	    : std_logic_vector(7 downto 0) := x"00";
+
+signal Car1_reg	: std_logic_vector(15 downto 0) := x"0000";
+signal Car2_reg	: std_logic_vector(15 downto 0) := x"0000";
+signal Car3_reg 	: std_logic_vector(15 downto 0) := x"0000";
+signal Car4_reg 	: std_logic_vector(15 downto 0) := x"0000";
+
+signal Vid			: std_logic_vector(7 downto 0);
+
+
+begin
+phi0 <= phi2;
+
+H4 <= Hcount(2);
+H8 <= Hcount(3);
+H16 <= Hcount(4);
+H32 <= Hcount(5);
+H64 <= Hcount(6);
+H256 <= Hcount(8);
+H256_n <= not(Hcount(8));
+
+-- Vertical line comparator
+VPos_sum <= Display + VCount; 
+N4_8 <= not(VPos_sum(7) and VPos_sum(6) and VPos_sum(5) and VPos_sum(4) and VPos_sum(3) and H256_n and H64 and H8);
+
+
+-- D type flip-flops in L5
+L5: process(phi2, N4_8, VPos_sum(2 downto 0))
+begin
+	if rising_edge(phi2) then
+		L5_reg <= N4_8 & VPos_sum(2 downto 0);
+	end if;
+end process;
+
+
+-- Motion object PROMs - These contain the car images for all 32 possible orientations
+J6: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6399-01j6.hex",
+		widthad_a => 9,
+		width_a => 4)
+port map(
+		clock => clk6,
+		address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+		q => Vid(7 downto 4)
+		);
+		
+--J6: entity work.j6_prom
+--port map(
+--	clock => clk6,
+--	address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+--	q => Vid(7 downto 4)
+--	);
+
+K6: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6398-01k6.hex",
+		widthad_a => 9,
+		width_a => 4)
+port map(
+		clock => clk6,
+		address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+		q => Vid(3 downto 0)
+		);
+		
+--K6: entity work.k6_prom
+--port map(
+--	clock => clk6,
+--	address => Display(7 downto 3) & L5_reg(2 downto 0) & phi2,
+--	q => Vid(3 downto 0)
+--	);
+
+	
+-- Some glue logic
+J8_3 <= (H4 or L5_reg(3));
+J8_6 <= (H256 or H64 or H4);
+
+
+-- Decoders
+-- Making K8 synchronous fixes weird problem with ghost artifacts of motion objects
+K8_in <= J8_3 & H32 & H16 & phi0;
+K8: process(clk6, K8_in)
+begin
+	if rising_edge(clk6) then
+		case K8_in is
+			when "0000" =>
+				K8_out <= "1111111110";
+			when "0001" =>
+				K8_out <= "1111111101"; 
+			when "0010" =>
+				K8_out <= "1111111011"; 
+			when "0011" =>
+				K8_out <= "1111110111";
+			when "0100" =>
+				K8_out <= "1111101111"; 
+			when "0101" =>
+				K8_out <= "1111011111";
+			when "0110" =>
+				K8_out <= "1110111111"; 
+			when "0111" =>
+				K8_out <= "1101111111";
+			when "1000" =>
+				K8_out <= "1011111111";
+			when "1001" =>
+				K8_out <= "0111111111";
+			when others =>
+				K8_out <= "1111111111";
+			end case;
+		end if;
+end process;
+LDV3B_n <= K8_out(7);
+LDV3A_n <= K8_out(6);
+LDV2B_n <= K8_out(5);
+LDV2A_n <= K8_out(4);
+LDV1B_n <= K8_out(3);
+LDV1A_n <= K8_out(2);
+LDV4B_n <= K8_out(1);
+LDV4A_n <= K8_out(0);
+
+P7_in <= J8_6 & H32 & H16 & H8;
+P7: process(P7_in)
+begin
+	case P7_in is
+		when "0000" =>
+         P7_out <= "1111111110";
+		when "0001" =>
+         P7_out <= "1111111101";
+      when "0010" =>
+         P7_out <= "1111111011";
+      when "0011" =>
+         P7_out <= "1111110111";
+      when "0100" =>
+         P7_out <= "1111101111";
+      when "0101" =>
+         P7_out <= "1111011111";
+      when "0110" =>
+         P7_out <= "1110111111";
+      when "0111" =>
+         P7_out <= "1101111111";
+      when "1000" =>
+         P7_out <= "1011111111";
+      when "1001" =>
+         P7_out <= "0111111111";
+      when others =>
+         P7_out <= "1111111111";
+      end case;
+end process;
+Crash_n <= P7_out(7);
+Motor1_n <= P7_out(5);	
+LDH4_n <= P7_out(4);
+LDH3_n <= P7_out(3); 
+LDH2_n <= P7_out(2);
+LDH1_n <= P7_out(1);
+
+
+-- Car 1 Horizontal position counter
+-- This combines two 74163s at locations R5 and R6 on the PCB 
+R5_6: process(clk6, H256_s, LDH1_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH1_n = '0' then -- preload the counter
+			Car1_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car1_Hpos <= Car1_Hpos + '1';		
+		end if;
+		if Car1_Hpos(7 downto 3) = "11111" then
+			Car1_Inh <= '0';
+		else
+			Car1_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 1 video shift register
+-- This combines two 74165s at locations M7 and N7 on the PCB
+M_N7: process(clk12, Car1_Inh, LDV1A_n, LDV1B_n, Vid)
+begin
+	if LDV1A_n = '0' then
+			Car1_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV1B_n = '0' then
+			Car1_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car1_Inh = '0' then
+			Car1_reg <= '0' & Car1_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car1 <= Car1_reg(0);
+Car1_n <= not Car1_reg(0);
+
+
+-- Car 2 Horizontal position counter
+-- This combines two 74LS163s at locations P5 and P6 on the PCB 
+P5_6: process(clk6, H256_s, LDH2_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH2_n = '0' then -- preload the counter
+			Car2_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car2_Hpos <= Car2_Hpos + '1';
+		end if;
+		if Car2_Hpos(7 downto 3) = "11111" then
+			Car2_Inh <= '0';
+		else
+			Car2_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 2 video shift register
+K_L7: process(clk12, Car2_Inh, LDV2A_n, LDV2B_n, Vid)
+begin
+	if LDV2A_n = '0' then
+			Car2_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV2B_n = '0' then
+			Car2_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car2_Inh = '0' then
+			Car2_reg <= '0' & Car2_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car2 <= Car2_reg(0);
+Car2_n <= not Car2_reg(0);
+
+
+-- Car 3 Horizontal position counter
+-- This combines two 74LS163s at locations N5 and N6 on the PCB 
+N5_6: process(clk6, H256_s, LDH3_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH3_n = '0' then -- preload the counter
+			Car3_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car3_Hpos <= Car3_Hpos + '1';
+		end if;
+		if Car3_Hpos(7 downto 3) = "11111" then
+			Car3_Inh <= '0';
+		else
+			Car3_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 3 video shift register
+H_J7: process(clk12, Car3_Inh, LDV3A_n, LDV3B_n, Vid)
+begin
+	if LDV3A_n = '0' then
+			Car3_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV3B_n = '0' then
+			Car3_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car3_Inh = '0' then
+			Car3_reg <= '0' & Car3_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+
+
+-- Car 4 Horizontal position counter
+-- This combines two 74LS163s at locations M5 and M6 on the PCB 
+M5_6: process(clk6, H256_s, LDH4_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH4_n = '0' then -- preload the counter
+			Car4_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Car4_Hpos <= Car4_Hpos + '1';
+		end if;
+		if Car4_Hpos(7 downto 3) = "11111" then
+			Car4_Inh <= '0';
+		else
+			Car4_Inh <= '1';
+		end if;
+	end if;
+end process;
+
+-- Car 4 video shift register
+E_F7: process(clk12, Car4_Inh, LDV4A_n, LDV4B_n, Vid)
+begin
+	if LDV4A_n = '0' then
+			Car4_reg(7 downto 0) <= Vid(7 downto 1) & '0'; -- Preload the LSB register
+	elsif LDV4B_n = '0' then
+			Car4_reg(15 downto 8) <= Vid(7 downto 0); -- Preload the MSB register
+	elsif rising_edge(clk12) then
+		if Car4_Inh = '0' then
+			Car4_reg <= '0' & Car4_reg(15 downto 1);
+		end if;
+	end if;
+end process;
+Car3_4_n <= not (Car3_reg(0) or Car4_reg(0));
+
+end rtl;
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/osd.sv b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/osd.sv
new file mode 100644
index 00000000..c62c10af
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/osd.sv	
@@ -0,0 +1,179 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd (
+	// OSDs pixel clock, should be synchronous to cores pixel clock to
+	// avoid jitter.
+	input        clk_sys,
+
+	// SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// VGA signals coming from core
+	input  [5:0] R_in,
+	input  [5:0] G_in,
+	input  [5:0] B_in,
+	input        HSync,
+	input        VSync,
+	
+	// VGA signals going to video connector
+	output [5:0] R_out,
+	output [5:0] G_out,
+	output [5:0] B_out
+);
+
+parameter OSD_X_OFFSET = 10'd0;
+parameter OSD_Y_OFFSET = 10'd0;
+parameter OSD_COLOR    = 3'd0;
+
+localparam OSD_WIDTH   = 10'd256;
+localparam OSD_HEIGHT  = 10'd128;
+
+// *********************************************************************************
+// spi client
+// *********************************************************************************
+
+// this core supports only the display related OSD commands
+// of the minimig
+reg        osd_enable;
+(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
+
+// the OSD has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS3) begin
+	reg  [4:0] cnt;
+	reg [10:0] bcnt;
+	reg  [7:0] sbuf;
+	reg  [7:0] cmd;
+
+	if(SPI_SS3) begin
+		cnt  <= 0;
+		bcnt <= 0;
+	end else begin
+		sbuf <= {sbuf[6:0], SPI_DI};
+
+		// 0:7 is command, rest payload
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		if(cnt == 7) begin
+			cmd <= {sbuf[6:0], SPI_DI};
+      
+			// lower three command bits are line address
+			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
+
+			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
+		end
+
+		// command 0x20: OSDCMDWRITE
+		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
+			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
+			bcnt <= bcnt + 1'd1;
+		end
+	end
+end
+
+// *********************************************************************************
+// video timing and sync polarity anaylsis
+// *********************************************************************************
+
+// horizontal counter
+reg  [9:0] h_cnt;
+reg  [9:0] hs_low, hs_high;
+wire       hs_pol = hs_high < hs_low;
+wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
+
+// vertical counter
+reg  [9:0] v_cnt;
+reg  [9:0] vs_low, vs_high;
+wire       vs_pol = vs_high < vs_low;
+wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
+
+wire doublescan = (dsp_height>350); 
+
+reg ce_pix;
+always @(negedge clk_sys) begin
+	integer cnt = 0;
+	integer pixsz, pixcnt;
+	reg hs;
+
+	cnt <= cnt + 1;
+	hs <= HSync;
+
+	pixcnt <= pixcnt + 1;
+	if(pixcnt == pixsz) pixcnt <= 0;
+	ce_pix <= !pixcnt;
+
+	if(hs && ~HSync) begin
+		cnt    <= 0;
+		pixsz  <= (cnt >> 9) - 1;
+		pixcnt <= 0;
+		ce_pix <= 1;
+	end
+end
+
+always @(posedge clk_sys) begin
+	reg hsD, hsD2;
+	reg vsD, vsD2;
+
+	if(ce_pix) begin
+		// bring hsync into local clock domain
+		hsD <= HSync;
+		hsD2 <= hsD;
+
+		// falling edge of HSync
+		if(!hsD && hsD2) begin	
+			h_cnt <= 0;
+			hs_high <= h_cnt;
+		end
+
+		// rising edge of HSync
+		else if(hsD && !hsD2) begin	
+			h_cnt <= 0;
+			hs_low <= h_cnt;
+			v_cnt <= v_cnt + 1'd1;
+		end else begin
+			h_cnt <= h_cnt + 1'd1;
+		end
+
+		vsD <= VSync;
+		vsD2 <= vsD;
+
+		// falling edge of VSync
+		if(!vsD && vsD2) begin	
+			v_cnt <= 0;
+			vs_high <= v_cnt;
+		end
+
+		// rising edge of VSync
+		else if(vsD && !vsD2) begin	
+			v_cnt <= 0;
+			vs_low <= v_cnt;
+		end
+	end
+end
+
+// area in which OSD is being displayed
+wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
+wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
+wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
+wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
+wire [9:0] osd_hcnt    = h_cnt - h_osd_start + 1'd1;  // one pixel offset for osd_byte register
+wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
+
+wire osd_de = osd_enable && 
+              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
+              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
+
+reg  [7:0] osd_byte; 
+always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
+
+wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
+
+assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
+assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
+assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/playfield.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/playfield.vhd
new file mode 100644
index 00000000..350742f2
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/playfield.vhd	
@@ -0,0 +1,170 @@
+-- Playfield generation circuitry for Sprint 1 by Kee Games
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity playfield is 
+port(   
+			Clk6				: in	std_logic;
+			Display			: in	std_logic_vector(7 downto 0);
+			HCount			: in  std_logic_vector(8 downto 0);
+			VCount			: in  std_logic_vector(7 downto 0);
+			H256_s			: out std_logic;
+			HBlank			: in	std_logic;
+			VBlank			: in	std_logic;
+			VBlank_n_s		: in  std_logic; -- VBLANK* on the schematic	
+			HSync				: in	std_logic;
+			VSync				: in	std_logic;
+			CompSync_n_s	: out std_logic; -- COMP SYNC* on schematic
+			CompBlank_s		: out std_logic; -- COMP BLANK* on schematic
+			WhitePF_n		: out	std_logic; 
+			BlackPF_n		: out	std_logic 
+			);
+end playfield;
+
+architecture rtl of playfield is
+
+signal H1				: std_logic;
+signal H2				: std_logic;
+signal H4				: std_logic;
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+
+signal V1				: std_logic;
+signal V2				: std_logic;
+signal V4				: std_logic;
+
+signal char_addr		: std_logic_vector(8 downto 0) := (others => '0');
+signal char_data		: std_logic_vector(7 downto 0) := (others => '0');
+
+signal shift_data		: std_logic_vector(7 downto 0) := (others => '0');
+signal QH				: std_logic;
+
+signal R2_reg		: std_logic_vector(3 downto 0) := (others => '0');
+
+
+-- These signals are based off the schematic and are formatted as Designator_PinNumber
+signal R7_12			: std_logic;
+signal P3_3				: std_logic;
+signal P2_13			: std_logic;
+signal P3_6				: std_logic;
+signal A6_6				: std_logic;
+signal A6_3				: std_logic;
+
+begin
+
+-- Video synchronization signals
+H1 <= Hcount(0);
+H2 <= Hcount(1);
+H4 <= Hcount(2);
+H256 <= Hcount(8);
+H256_n <= not(Hcount(8));
+
+V1 <= Vcount(0);
+V2 <= Vcount(1);
+V4 <= Vcount(2);
+
+-- Some glue logic, may be re-written later to be cleaner and easier to follow without referring to schematic
+R7_12 <= not(H1 and H2 and H4);
+
+P3_3 <= (H256_n or R7_12);
+
+P2_13 <= (HSync nor VSync);
+
+P3_6 <= (HBlank or VBlank);
+
+
+
+char_addr <= display(5 downto 0) & V4 & V2 & V1;
+
+-- Background character ROMs
+R4: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6397-01r4.hex",
+		widthad_a => 9,
+		width_a => 4)
+port map(
+		clock => clk6,
+		Address => char_addr,
+		q => char_data(3 downto 0) 
+		);
+		
+--R4: entity work.Char_MSB
+--port map(
+--	clock => clk6,
+--	Address => char_addr,
+--	q => char_data(3 downto 0) 
+--	);
+
+P4: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6396-01p4.hex",
+		widthad_a => 9,
+		width_a => 4)
+port map(
+		clock => clk6,
+		Address => char_addr,
+		q => char_data(7 downto 4) 
+		);
+
+--P4: entity work.Char_LSB
+--port map(
+--	clock => clk6,
+--	Address => char_addr,
+--	q => char_data(7 downto 4) 
+--	);
+
+
+-- 74LS166 video shift register	
+R3: process(clk6, P3_3, VBlank_n_s, char_data, shift_data)
+begin
+	if VBlank_n_s = '0' then -- Connected Clear input
+		shift_data <= (others => '0');
+	elsif rising_edge(clk6) then 
+		if P3_3 = '0' then -- Parallel load
+			shift_data <= char_data(7 downto 0);
+		else
+			shift_data <= shift_data(6 downto 0) & '0';
+		end if;
+	end if;
+	QH <= shift_data(7);
+end process;
+
+
+-- 9316 counter at R2
+-- CEP and CET tied to ground, counter is used only as a synchronous latch
+R2: process(clk6, R7_12, display, H256, P2_13, P3_6)
+begin
+	if rising_edge(clk6) then
+		if R7_12 = '0' then
+			R2_reg <= (H256 & display(7) & P3_6 & P2_13);
+		end if;
+	end if;
+end process;
+
+
+H256_s <= R2_reg(3);
+CompBlank_s <= R2_reg(1);
+CompSync_n_s <= R2_reg(0);
+A6_6 <= (R2_reg(2) and QH);
+A6_3 <= ((not R2_reg(2)) and QH);
+
+WhitePF_n <= (not A6_6);
+BlackPF_n <= (not A6_3);
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/pll.v b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/pll.v
new file mode 100644
index 00000000..6a352243
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/pll.v	
@@ -0,0 +1,337 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	inclk0,
+	c0,
+	c1,
+	locked);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  locked;
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire6 = 1'h0;
+	wire [0:0] sub_wire3 = sub_wire0[0:0];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  c0 = sub_wire3;
+	wire  sub_wire4 = inclk0;
+	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+	altpll	altpll_component (
+				.inclk (sub_wire5),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 125,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 224,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 125,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 56,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.383999"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "224"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.38400000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "224"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6290-01b1.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6290-01b1.hex
new file mode 100644
index 00000000..e99c247b
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6290-01b1.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6291-01c1.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6291-01c1.hex
new file mode 100644
index 00000000..e362de36
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6291-01c1.hex	
@@ -0,0 +1,129 @@
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6396-01p4.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6396-01p4.hex
new file mode 100644
index 00000000..28243917
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6396-01p4.hex	
@@ -0,0 +1,33 @@
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6397-01r4.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6397-01r4.hex
new file mode 100644
index 00000000..72e395fe
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6397-01r4.hex	
@@ -0,0 +1,33 @@
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6398-01k6.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6398-01k6.hex
new file mode 100644
index 00000000..391da240
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6398-01k6.hex	
@@ -0,0 +1,33 @@
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6399-01j6.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6399-01j6.hex
new file mode 100644
index 00000000..74a9d0b9
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6399-01j6.hex	
@@ -0,0 +1,33 @@
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6400-01m2.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6400-01m2.hex
new file mode 100644
index 00000000..9dbfacea
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6400-01m2.hex	
@@ -0,0 +1,17 @@
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6401-01e2.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6401-01e2.hex
new file mode 100644
index 00000000..975d72ea
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6401-01e2.hex	
@@ -0,0 +1,3 @@
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6442-01d1.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6442-01d1.hex
new file mode 100644
index 00000000..160cbf39
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6442-01d1.hex	
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6443-01e1.hex b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6443-01e1.hex
new file mode 100644
index 00000000..ae79880b
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/roms/6443-01e1.hex	
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diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/scandoubler.sv b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/scandoubler.sv
new file mode 100644
index 00000000..0213d20c
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/scandoubler.sv	
@@ -0,0 +1,195 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2017 Sorgelig
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+// TODO: Delay vsync one line
+
+module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	// system interface
+	input             clk_sys,
+	input             ce_pix,
+	input             ce_pix_actual,
+
+	input             hq2x,
+
+	// shifter video interface
+	input             hs_in,
+	input             vs_in,
+	input             line_start,
+
+	input  [DWIDTH:0] r_in,
+	input  [DWIDTH:0] g_in,
+	input  [DWIDTH:0] b_in,
+	input             mono,
+
+	// output interface
+	output reg        hs_out,
+	output            vs_out,
+	output [DWIDTH:0] r_out,
+	output [DWIDTH:0] g_out,
+	output [DWIDTH:0] b_out
+);
+
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+assign vs_out = vs_in;
+
+reg  [2:0] phase;
+reg  [2:0] ce_div;
+reg  [7:0] pix_len = 0;
+wire [7:0] pl = pix_len + 1'b1;
+
+reg ce_x1, ce_x4;
+reg req_line_reset;
+wire ls_in = hs_in | line_start;
+always @(negedge clk_sys) begin
+	reg old_ce;
+	reg [2:0] ce_cnt;
+
+	reg [7:0] pixsz2, pixsz4 = 0;
+
+	old_ce <= ce_pix;
+	if(~&pix_len) pix_len <= pix_len + 1'd1;
+
+	ce_x4 <= 0;
+	ce_x1 <= 0;
+
+	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
+	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
+		phase <= phase + 1'd1;
+		ce_x4 <= 1;
+	end
+
+	if(~old_ce & ce_pix) begin
+		pixsz2 <= {1'b0,  pl[7:1]};
+		pixsz4 <= {2'b00, pl[7:2]};
+		ce_x1 <= 1;
+		ce_x4 <= 1;
+		pix_len <= 0;
+		phase <= phase + 1'd1;
+
+		ce_cnt <= ce_cnt + 1'd1;
+		if(ce_pix_actual) begin
+			phase <= 0;
+			ce_div <= ce_cnt + 1'd1;
+			ce_cnt <= 0;
+			req_line_reset <= 0;
+		end
+
+		if(ls_in) req_line_reset <= 1;
+	end
+end
+
+reg ce_sd;
+always @(*) begin
+	case(ce_div)
+		2: ce_sd = !phase[0];
+		4: ce_sd = !phase[1:0];
+		default: ce_sd <= 1;
+	endcase
+end
+
+`define BITS_TO_FIT(N) ( \
+     N <=   2 ? 0 : \
+     N <=   4 ? 1 : \
+     N <=   8 ? 2 : \
+     N <=  16 ? 3 : \
+     N <=  32 ? 4 : \
+     N <=  64 ? 5 : \
+     N <= 128 ? 6 : \
+     N <= 256 ? 7 : \
+     N <= 512 ? 8 : \
+     N <=1024 ? 9 : 10 )
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
+(
+	.clk(clk_sys),
+	.ce_x4(ce_x4 & ce_sd),
+	.inputpixel({b_in,g_in,r_in}),
+	.mono(mono),
+	.disable_hq2x(~hq2x),
+	.reset_frame(vs_in),
+	.reset_line(req_line_reset),
+	.read_y(sd_line),
+	.read_x(sd_h_actual),
+	.outpixel({b_out,g_out,r_out})
+);
+
+reg [10:0] sd_h_actual;
+always @(*) begin
+	case(ce_div)
+		2: sd_h_actual = sd_h[10:1];
+		4: sd_h_actual = sd_h[10:2];
+		default: sd_h_actual = sd_h;
+	endcase
+end
+
+reg [10:0] sd_h;
+reg  [1:0] sd_line;
+always @(posedge clk_sys) begin
+
+	reg [11:0] hs_max,hs_rise,hs_ls;
+	reg [10:0] hcnt;
+	reg [11:0] sd_hcnt;
+
+	reg hs, hs2, vs, ls;
+
+	if(ce_x1) begin
+		hs <= hs_in;
+		ls <= ls_in;
+
+		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
+
+		// falling edge of hsync indicates start of line
+		if(hs && !hs_in) begin
+			hs_max <= {hcnt,1'b1};
+			hcnt <= 0;
+			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
+		end else begin
+			hcnt <= hcnt + 1'd1;
+		end
+
+		// save position of rising edge
+		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
+
+		vs <= vs_in;
+		if(vs && ~vs_in) sd_line <= 0;
+	end
+
+	if(ce_x4) begin
+		hs2 <= hs_in;
+
+		// output counter synchronous to input and at twice the rate
+		sd_hcnt <= sd_hcnt + 1'd1;
+		sd_h    <= sd_h    + 1'd1;
+		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
+		if(sd_hcnt == hs_max) sd_hcnt <= 0;
+
+		// replicate horizontal sync at twice the speed
+		if(sd_hcnt == hs_max)  hs_out <= 0;
+		if(sd_hcnt == hs_rise) hs_out <= 1;
+
+		if(sd_hcnt == hs_ls)   sd_h    <= 0;
+		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/screech.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/screech.vhd
new file mode 100644
index 00000000..251ad2ec
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/screech.vhd	
@@ -0,0 +1,73 @@
+-- Tire screech sound generator for Kee Games Sprint 1
+-- Identical circuit is used in a number of related Kee/Atari games 
+-- (c) 2017 James Sweet
+--
+-- Original circuit used a 7414 Schmitt trigger oscillator operating at approximately
+-- 1.2kHz producing a sawtooth with the frequency modulated slightly by the pseudo-random 
+-- noise generator. This is an extension of work initially done in Verilog by Jonas Elofsson.
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity tire_screech is 
+generic(
+			constant Inc1 : integer := 24; -- These constants can be adjusted to tune the frequency and modulation
+			constant Inc2 : integer := 34;
+			constant Dec1 : integer := 23;
+			constant Dec2 : integer := 12
+			);
+port(		
+			Clk			: in  std_logic;  -- 750kHz from the horizontal line counter chain works well here
+			Noise			: in	std_logic;  -- Output from LFSR pseudo-random noise generator
+			Screech_out	: out std_logic	-- Screech output - single bit
+			);
+end tire_screech;
+
+architecture rtl of tire_screech is
+
+signal Screech_count	: integer range 1000 to 11000;
+signal Screech_state	: std_logic;
+
+begin
+
+Screech: process(Clk, Screech_state)
+begin
+	if rising_edge(Clk) then
+		if screech_state = '1' then -- screech_state is 1, counter is rising
+			if noise = '1' then 	-- Noise signal from LFSR, when high increases the slope of the rising ramp
+				screech_count <= screech_count + inc2;
+			else 						-- When Noise is low, decreas the slope of the ramp
+				screech_count <= screech_count + inc1; 
+			end if;
+			if screech_count > 10000 then -- Reverse the ramp direction when boundary value of 10,000 is reached
+				screech_state <= '0';
+			end if;
+		elsif screech_state = '0' then -- screech_state is now low, decrement the counter (ramp down)
+			if noise = '1' then 
+				screech_count <= screech_count - dec2; -- Slope is influenced by the Noise signal
+			else
+				screech_count <= screech_count - dec1;
+			end if;
+			if screech_count < 1000 then -- Reverse the ramp direction again when the lower boundary of 1,000 is crossed
+				screech_state <= '1';
+			end if;
+		end if;
+	end if;
+screech_out <= screech_state;
+end process;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1.vhd
new file mode 100644
index 00000000..7811fbef
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1.vhd	
@@ -0,0 +1,310 @@
+-- Top level file for Kee Games Sprint 1 
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple
+-- See Sprint 1 manual for video output details. Resistor values listed here have been scaled 
+-- for 3.3V logic. 
+-- R48 1k Ohm
+-- R49 1k Ohm
+-- R50 680R
+-- R51 330R
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+
+entity sprint1 is 
+port(		
+			clk_12		: in	std_logic;	-- 12MHz input clock
+			Reset_n		: in	std_logic;	-- Reset button (Active low)
+			
+			
+			VideoW_O		: out std_logic;  -- White video output (680 Ohm)
+			VideoB_O		: out std_logic;	-- Black video output (1.2k)
+			Sync_O		: out std_logic;  -- Composite sync output (1.2k)
+			
+			
+			Hs				: out std_logic;
+			Vs				: out std_logic;
+			Vb				: out std_logic;			
+			Hb				: out std_logic;	
+			Video			: out std_logic;
+			Audio			: out std_logic_vector(6 downto 0);
+			Coin1_I		: in  std_logic;  -- Coin switches (Active low)
+			Coin2_I		: in  std_logic;
+			Start_I		: in  std_logic;  -- Start button
+			Gas_I			: in  std_logic;	-- Gas pedal
+			Gear1_I		: in  std_logic;  -- Gear shifter, 4th gear = no other gear selected
+			Gear2_I		: in  std_logic;
+			Gear3_I		: in  std_logic;
+			Test_I		: in  std_logic;  -- Self-test switch
+			SteerA_I		: in  std_logic;	-- Steering wheel inputs, these are quadrature encoders
+			SteerB_I		: in	std_logic;
+			StartLamp_O	: out std_logic	-- Start button lamp
+			);
+end sprint1;
+
+architecture rtl of sprint1 is
+
+signal clk_6			: std_logic;
+signal phi1 			: std_logic;
+signal phi2				: std_logic;
+
+signal Hcount		   : std_logic_vector(8 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_s			: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+
+
+signal Vcount  		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+
+signal Vreset			: std_logic;
+signal Vblank_s		: std_logic;
+signal Vblank_n_s		: std_logic;
+signal Vblank			: std_logic;			
+signal Hblank			: std_logic;
+signal Hsync			: std_logic;
+signal Vsync			: std_logic;
+
+signal CompBlank_s	: std_logic;
+signal CompSync_n_s	: std_logic;
+
+signal WhitePF_n		: std_logic;
+signal BlackPF_n		: std_logic;
+
+signal Display			: std_logic_vector(7 downto 0);
+
+-- Address decoder
+signal addec_bus		: std_logic_vector(7 downto 0);
+signal RnW				: std_logic;
+signal Write_n			: std_logic;
+signal ROM1				: std_logic;
+signal ROM2				: std_logic;
+signal ROM3				: std_logic;
+signal WRAM				: std_logic;
+signal RAM_n			: std_logic;
+signal Sync_n			: std_logic;
+signal Switch_n		: std_logic;
+signal Collision1_n	: std_logic;
+signal Collision2_n	: std_logic;
+signal Display_n		: std_logic;
+signal TimerReset_n	: std_logic;
+signal CollRst1_n		: std_logic;
+signal CollRst2_n		: std_logic;
+signal SteerRst1_n	: std_logic;
+signal SteerRst2_n	: std_logic;
+signal NoiseRst_n		: std_logic;
+signal Attract			: std_logic;	
+signal Skid1			: std_logic;
+signal Skid2			: std_logic;
+
+signal Crash_n			: std_logic;
+signal Motor1_n 		: std_logic;
+signal Motor2_n		: std_logic;
+signal Car1				: std_logic;
+signal Car1_n			: std_logic;
+signal Car2				: std_logic;
+signal Car2_n			: std_logic;
+signal Car3_4_n		: std_logic;	
+
+signal NMI_n			: std_logic;
+
+signal Adr				: std_logic_vector(9 downto 0);
+
+signal SW1				: std_logic_vector(7 downto 0);
+
+signal Inputs			: std_logic_vector(1 downto 0);
+signal Collisions1	: std_logic_vector(1 downto 0);
+signal Collisions2	: std_logic_vector(1 downto 0);
+
+begin
+-- Configuration DIP switches, these can be brought out to external switches if desired
+-- See Sprint 2 manual page 11 for complete information. Active low (0 = On, 1 = Off)
+--    1 								Oil slicks			(0 - Oil slicks enabled)
+--			2							Cycle tracks      (0/1 - Cycle every lap/every two laps)
+--   			3	4					Coins per play		(00 - 1 Coin per player) 
+--						5				Extended Play		(0 - Extended Play enabled)
+--							6			Not used				(X - Don't care)
+--								7	8	Game time			(01 - 120 Seconds)
+SW1 <= "11000101"; -- Config dip switches
+		
+		
+Vid_sync: entity work.synchronizer
+port map(
+		clk_12 => clk_12,
+		clk_6 => clk_6,
+		hcount => hcount,
+		vcount => vcount,
+		hsync => hsync,
+		hblank => hblank,
+		vblank_s => vblank_s,
+		vblank_n_s => vblank_n_s,
+		vblank => vblank,
+		vsync => vsync,
+		vreset => vreset
+		);
+
+
+Background: entity work.playfield
+port map( 
+		clk6 => clk_6,
+		display => display,
+		HCount => HCount,
+		VCount => VCount,
+		HBlank => HBlank,		
+		H256_s => H256_s,
+		VBlank => VBlank,
+		VBlank_n_s => Vblank_n_s,
+		HSync => Hsync,
+		VSync => VSync,
+		CompSync_n_s => CompSync_n_s,
+		CompBlank_s => CompBlank_s,
+		WhitePF_n => WhitePF_n,
+		BlackPF_n => BlackPF_n 
+		);
+
+		
+Cars: entity work.motion
+port map(
+		CLK6 => clk_6,
+		CLK12 => clk_12,
+		PHI2 => phi2,
+		DISPLAY => Display,
+		H256_s => H256_s,
+		VCount => VCount,
+		HCount => HCount,
+		Crash_n => Crash_n,
+		Motor1_n => Motor1_n,
+		Car1 => Car1,
+		Car1_n => Car1_n,
+		Car2 => Car2,
+		Car2_n => Car2_n,
+		Car3_4_n => Car3_4_n	
+		);
+		
+		
+PF_Comparator: entity work.collision_detect
+port map(
+		Clk6 => Clk_6,
+		Car1 => Car1,
+		Car1_n => Car1_n,
+		Car2 => Car2,
+		Car2_n => Car2_n,
+		Car3_4_n	=> Car3_4_n,
+		WhitePF_n => WhitePF_n,
+		BlackPF_n => BlackPF_n,
+		CollRst1_n => CollRst1_n,
+		Collisions1 => Collisions1
+		);
+	
+	
+CPU: entity work.cpu_mem
+port map(
+		Clk12 => clk_12,
+		Clk6 => clk_6,
+		Reset_n => reset_n,
+		VCount => VCount,
+		HCount => HCount,
+		Hsync_n => not Hsync,
+		Vblank_s => Vblank_s,
+		Vreset => Vreset,
+		Test_n => not Test_I,
+		Attract => Attract,
+		Skid1 => Skid1,
+		Skid2 => Skid2,
+		NoiseReset_n => NoiseRst_n,
+		CollRst1_n => CollRst1_n,
+		CollRst2_n => CollRst2_n,
+		SteerRst1_n => SteerRst1_n,
+		Lamp1 => StartLamp_O,
+		Phi1_o => Phi1,
+		Phi2_o => Phi2,
+		Display => Display,
+		IO_Adr => Adr,
+		Collisions1 => Collisions1,
+		Collisions2 => Collisions2,
+		Inputs => Inputs
+		);
+
+
+Input: entity work.Control_Inputs
+port map(
+		clk6 => clk_6,
+		SW1 => SW1, -- DIP switches
+		Coin1_n => Coin1_I,
+		Coin2_n => Coin2_I,
+		Start => not Start_I, -- Active high in real hardware, inverting these makes more sense with the FPGA
+		Gas => not Gas_I,
+		Gear1 => not Gear1_I,
+		Gear2 => not Gear2_I,
+		Gear3 => not Gear3_I,
+		Self_Test => not Test_I,
+		Steering1A_n => SteerA_I,
+		Steering1B_n => SteerB_I,
+		SteerRst1_n => SteerRst1_n,
+		Adr => Adr,
+		Inputs => Inputs
+	);	
+
+	
+Sound: entity work.audio
+port map(
+		Clk_6 => Clk_6,
+		Reset_n => Reset_n,
+		Motor1_n => Motor1_n,
+		Skid1 => Skid1,
+		Crash_n => Crash_n,
+		NoiseReset_n => NoiseRst_n,
+		Attract => Attract,
+		Display => Display,
+		HCount => HCount,
+		VCount => VCount,
+		Audio1 => Audio
+		);
+
+-- Video mixing	
+VideoB_O <= (not(BlackPF_n and Car2_n and Car3_4_n)) nor CompBlank_s;	
+VideoW_O <= not(WhitePF_n and Car1_n);  
+Sync_O <= CompSync_n_s;
+
+Vb <= VBLANK;
+Hb <= HBLANK;
+Hs <= Hsync;
+Vs <= Vsync;
+Video <= (WhitePF_n and blackpf_n and car1_n and Car2_n and Car3_4_n) nor CompBlank_s;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1_mist.sv b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1_mist.sv
new file mode 100644
index 00000000..f367af5e
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1_mist.sv	
@@ -0,0 +1,144 @@
+module sprint1_mist(
+	output        LED,
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.sv" 
+
+localparam CONF_STR = {
+	"Sprint1;;",
+	"O1,Test Mode,Off,On;",
+	"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+	"T6,Reset;",
+	"V,v1.00.",`BUILD_DATE
+};
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [11:0] kbjoy;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoubler_disable;
+wire        ypbpr;
+wire        ps2_kbd_clk, ps2_kbd_data;
+wire  [6:0] audio;
+wire			video;
+
+wire clk_48, clk_12;
+wire locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.c0(clk_48),//48.384
+	.c1(clk_12),//12.096
+	.locked(locked)
+);
+
+
+sprint1 sprint1 (
+	.clk_12(clk_12),
+	.Reset_n(~(status[0] | status[6] | buttons[1])),
+	.VideoW_O(),
+	.VideoB_O(),
+	.Sync_O(),					
+	.Hs(hs),
+	.Vs(vs),
+	.Vb(vb),		
+	.Hb(hb),
+	.Video(video),			
+	.Audio(audio),
+	.Coin1_I(~kbjoy[7]),
+	.Coin2_I(~kbjoy[7]),
+	.Start_I(~kbjoy[5]),
+	.Gas_I(~kbjoy[4]),
+//	.Gear1_I(~kbjoy[8]),
+//	.Gear2_I(~kbjoy[9]),
+//	.Gear3_I(~kbjoy[10]),
+	.Test_I(~status[1]),
+	.SteerA_I(),
+	.SteerB_I(),
+	.StartLamp_O(~LED)
+);
+
+dac dac (
+	.CLK(clk_48),
+	.RESET(1'b0),
+	.DACin(audio),
+	.DACout(AUDIO_L)
+	);
+
+assign AUDIO_R = AUDIO_L;
+
+wire hs, vs;
+wire hb, vb;
+wire blankn = ~(hb | vb);
+video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
+(
+	.clk_sys(clk_48),
+	.ce_pix(clk_12),
+	.ce_pix_actual(clk_12),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(blankn ? {video,video,video} : "000"),
+	.G(blankn ? {video,video,video} : "000"),
+	.B(blankn ? {video,video,video} : "000"),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoubler_disable),
+	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
+	.hq2x(status[4:3]==1),
+	.ypbpr_full(1),
+	.line_start(0),
+	.mono(0)
+);
+
+mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
+(
+	.clk_sys        (clk_48   	     ),
+	.conf_str       (CONF_STR       ),
+	.SPI_SCK        (SPI_SCK        ),
+	.CONF_DATA0     (CONF_DATA0     ),
+	.SPI_SS2			 (SPI_SS2        ),
+	.SPI_DO         (SPI_DO         ),
+	.SPI_DI         (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches   	 (switches       ),
+	.scandoubler_disable(scandoubler_disable),
+	.ypbpr          (ypbpr          ),
+	.ps2_kbd_clk    (ps2_kbd_clk    ),
+	.ps2_kbd_data   (ps2_kbd_data   ),
+	.joystick_0   	 (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+);
+
+keyboard keyboard(
+	.clk(clk_48),
+	.reset(),
+	.ps2_kbd_clk(ps2_kbd_clk),
+	.ps2_kbd_data(ps2_kbd_data),
+	.joystick(kbjoy)
+	);
+
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1_sound.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1_sound.vhd
new file mode 100644
index 00000000..268fe1fd
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprint1_sound.vhd	
@@ -0,0 +1,195 @@
+-- Audio for Sprint 1
+-- First attempt at modeling the analog sound circuits used in Sprint 1, may be room for improvement as
+-- I do not have a real board to compare.
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity audio is 
+port(		
+			Clk_6				: in  std_logic;
+			Reset_n			: in	std_logic;
+			Motor1_n			: in	std_logic;
+			Skid1				: in  std_logic;
+			Crash_n			: in  std_logic;
+			NoiseReset_n	: in  std_logic;
+			Attract			: in  std_logic;
+			Display			: in	std_logic_vector(7 downto 0);
+			HCount			: in  std_logic_vector(8 downto 0);
+			VCount			: in  std_logic_vector(7 downto 0);
+			Audio1			: out std_logic_vector(6 downto 0)
+			);
+end audio;
+
+architecture rtl of audio is
+
+signal reset			: std_logic;
+
+signal H4				: std_logic;
+signal V2				: std_logic;
+
+signal Noise			: std_logic;
+signal Noise_Shift	: std_logic_vector(15 downto 0);
+signal Shift_in  		: std_logic;
+
+signal Screech_count	: integer range 1000 to 11000;
+signal Screech_state	: std_logic;
+signal Screech_snd1	: std_logic;
+signal Screech1		: std_logic_vector(3 downto 0);
+
+signal Crash			: std_logic_vector(3 downto 0);
+signal Bang				: std_logic_vector(3 downto 0);
+
+signal Mtr1_Freq		: std_logic_vector(3 downto 0);
+signal Motor1_speed	: std_logic_vector(3 downto 0);
+signal Motor1_snd		: std_logic_vector(5 downto 0);
+
+signal ena_count		: std_logic_vector(10 downto 0);
+signal ena_3k			: std_logic;
+
+signal bang_prefilter     : std_logic_vector(3 downto 0);
+signal bang_filter_t1     : std_logic_vector(3 downto 0);
+signal bang_filter_t2     : std_logic_vector(3 downto 0);
+signal bang_filter_t3     : std_logic_vector(3 downto 0);
+signal bang_filtered      : std_logic_vector(5 downto 0);
+
+
+begin
+
+-- HCount
+-- (0) 1H 	3 MHz
+-- (1) 2H   1.5MHz
+-- (2) 4H	750 kHz
+-- (3) 8H	375 kHz
+-- (4) 16H	187 kHz
+-- (5) 32H	93 kHz
+-- (6) 64H	46 kHz
+-- (7) 128H 23 kHz
+-- (8) 256H 12 kHz
+
+reset <= (not reset_n);
+
+H4 <= HCount(2);
+V2 <= VCount(1);
+
+-- Generate the 3kHz clock enable used by the filter
+Enable: process(clk_6)
+begin
+	if rising_edge(CLK_6) then
+		ena_count <= ena_count + "1";
+		ena_3k <= '0';
+		if (ena_count(10 downto 0) = "00000000000") then
+			ena_3k <= '1';
+		end if;
+	end if;
+end process;
+
+
+-- LFSR that generates pseudo-random noise
+Noise_gen: process(NoiseReset_n, V2)
+begin
+	if (noisereset_n = '0') then
+		noise_shift <= (others => '0');
+		noise <= '0';
+	elsif rising_edge(V2) then
+		shift_in <= not(noise_shift(6) xor noise_shift(8));
+		noise_shift <= shift_in & noise_shift(15 downto 1);
+		noise <= noise_shift(0); 
+	end if;
+end process;
+
+
+-- Tire screech sound
+Screech_gen1: entity work.tire_screech
+generic map( -- These values can be tweaked to tune the screech sound
+		Inc1 => 24, -- Ramp increase rate when noise = 0
+		Inc2 => 33, -- Ramp increase rate when noise = 1
+		Dec1 => 29, -- Ramp decrease rate when noise = 0
+		Dec2 => 16  -- Ramp decrease rate when noise = 1
+		)
+port map(
+		Clk => H4,
+		Noise => noise,
+		Screech_out => screech_snd1
+		);
+		
+	
+-- Convert screech from 1 bit to 4 bits wide and enable via skid1  signal
+Screech_ctrl: process(screech_snd1, skid1)
+begin
+	if (skid1 and screech_snd1) = '1' then
+		screech1 <= "1111";
+	else
+		screech1 <= "0000";
+	end if;
+end process;
+		
+	
+Crash_sound: process(crash_n, display, noise)		
+begin
+	if crash_n = '0' then
+		crash <= display(3 downto 0);
+	end if;
+	if noise = '1' then
+		bang_prefilter <= crash;
+	else
+		bang_prefilter <= "0000";
+	end if;
+end process;
+
+
+---- Very simple low pass filter, borrowed from MikeJ's Asteroids code
+Crash_filter: process(clk_6)
+begin
+	if rising_edge(clk_6) then
+		if (ena_3k = '1') then
+			bang_filter_t1 <= bang_prefilter;
+			bang_filter_t2 <= bang_filter_t1;
+			bang_filter_t3 <= bang_filter_t2;
+		end if;
+		bang_filtered <=  ("00" & bang_filter_t1) +
+								('0'  & bang_filter_t2 & '0') +
+								("00" & bang_filter_t3);
+	end if;
+end process;	
+
+
+Motor1_latch: process(Motor1_n, Display)
+begin
+	if Motor1_n = '0' then
+		Motor1_speed <= Display(3 downto 0);
+	end if;
+end process;
+
+Motor1: entity work.EngineSound 
+generic map( 
+		Freq_tune => 50 -- Tuning pot for engine sound frequency
+		)
+port map(		
+		Clk_6 => clk_6, 
+		Ena_3k => ena_3k,
+		EngineData => motor1_speed,
+		Motor => motor1_snd
+		);
+	
+	
+-- Audio mixer, also mutes sound in attract mode
+audio1 <= ('0' & motor1_snd) + ("00" & screech1) + ('0' & bang_filtered) when attract = '0'
+				else "0000000";
+
+	
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprom.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sync.vhd b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sync.vhd
new file mode 100644
index 00000000..6ef8fef9
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/sync.vhd	
@@ -0,0 +1,188 @@
+-- Video synchronizer circuit for Sprint 1
+-- Similar circuit used in many other Atari and Kee Games arcade games
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity synchronizer is 
+port(		
+			clk_12		: in	std_logic;
+			clk_6			: out	std_logic;
+			hcount		: out	std_logic_vector(8 downto 0);
+			vcount		: out	std_logic_vector(7 downto 0);
+		   hsync			: out	std_logic;
+			hblank		: out std_logic;
+			vblank_s		: out std_logic;
+			vblank_n_s	: out std_logic;
+			vblank		: out	std_logic;
+			vsync			: out std_logic;
+			vreset		: out	std_logic);
+end synchronizer;
+
+architecture rtl of synchronizer is
+
+signal h_counter		: std_logic_vector(9 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+signal v_counter		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+signal sync_bus		: std_logic_vector(3 downto 0) := (others => '0');
+signal sync_reg		: std_logic_vector(3 downto 0) := (others => '0');
+signal vblank_int		: std_logic := '0';
+signal vreset_n		: std_logic := '0';
+
+signal hblank_int		: std_logic := '0';
+signal hsync_int		: std_logic := '0';
+signal hsync_reset 	: std_logic := '0';
+
+
+begin
+
+-- Horizontal counter is 9 bits long plus additional flip flop. The last 4 bit IC in the chain resets to 0010 so total count resets to 128 
+-- using only the last three count states
+H_count: process(clk_12)
+begin
+	if rising_edge(clk_12) then
+		if h_counter = "1111111111" then
+			h_counter <= "0100000000";
+		else
+			h_counter <= h_counter + 1;
+		end if;
+	end if;
+end process;
+
+-- Vertical counter is 8 bits, clocked by the rising edge of H256 at the end of each horizontal line
+V_count: process(hsync_int)
+begin
+	if rising_edge(Hsync_int) then
+		if vreset_n = '0' then
+			v_counter <= (others => '0');
+		else
+			v_counter <= v_counter + '1';
+		end if;
+	end if;
+end process;
+
+-- Many Atari raster games use a 256 x 4 bit prom to decode vertical sync signals
+-- This could be replaced by combinatorial logic
+M2: entity work.sprom
+generic map(
+		init_file => "rtl/roms/6400-01m2.hex",
+		widthad_a => 8,
+		width_a => 4)
+port map(
+		clock => clk_12, 
+		address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
+		q => sync_bus
+		);
+		
+--M2: entity work.sync_prom
+--port map(
+--		clock => clk_12, 
+--		address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
+--		q => sync_bus
+--		);
+
+-- Register fed by the sync PROM, in the original hardware this also creates the complements of these signals
+sync_register: process(hsync_int)
+begin
+	if rising_edge(hsync_int) then
+		sync_reg <= sync_bus;
+	end if;
+end process;
+
+-- Outputs of sync PROM
+vblank_s <= sync_reg(3);
+vblank_n_s <= not sync_reg(3);
+vreset <= sync_reg(2);
+vreset_n <= not sync_reg(2);
+vblank <= sync_reg(1);
+vsync <= sync_reg(0);
+
+-- A pair of D type flip-flops that generate the Hsync signal
+Hsync_1: process(H256_n, H32)
+begin	
+	if H256_n = '0' then	
+		hblank_int <= '0';
+	else
+		if rising_edge(H32) then
+			hblank_int <= not H64;
+		end if;
+	end if;
+end process;
+
+Hsync_2: process(hblank_int, H8) 
+begin
+	if hblank_int = '0' then
+		hsync_int <= '0';
+	else
+		if rising_edge(H8) then
+			hsync_int <= H32;
+		end if;
+	end if;
+end process;
+
+-- Assign various signals
+clk_6 <= h_counter(0);
+H1 <= h_counter(1);
+H2 <= h_counter(2);
+H4 <= h_counter(3);
+H8 <= h_counter(4);
+H16 <=  h_counter(5);
+H32 <= h_counter(6);
+H64 <= h_counter(7);
+H128 <= h_counter(8);
+H256 <= h_counter(9);
+H4_n <= not H4;
+H8_n <= not H8;
+H256_n <= not H256;
+
+V1 <= v_counter(0);
+V2 <= v_counter(1);
+V4 <= v_counter(2);
+V8 <= v_counter(3);
+V16 <= v_counter(4);
+V32 <= v_counter(5);
+V64 <= v_counter(6);
+V128 <= v_counter(7);
+
+hcount <= h_counter(9 downto 1);
+vcount <= v_counter;
+hsync <= hsync_int;
+hblank <= hblank_int;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/video_mixer.sv b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/video_mixer.sv
new file mode 100644
index 00000000..04cfd4ba
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/rtl/video_mixer.sv	
@@ -0,0 +1,242 @@
+//
+//
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+//
+// LINE_LENGTH: Length of  display line in pixels
+//              Usually it's length from HSync to HSync.
+//              May be less if line_start is used.
+//
+// HALF_DEPTH:  If =1 then color dept is 3 bits per component
+//              For half depth 6 bits monochrome is available with
+//              mono signal enabled and color = {G, R}
+
+module video_mixer
+#(
+	parameter LINE_LENGTH  = 768,
+	parameter HALF_DEPTH   = 0,
+
+	parameter OSD_COLOR    = 3'd4,
+	parameter OSD_X_OFFSET = 10'd0,
+	parameter OSD_Y_OFFSET = 10'd0
+)
+(
+	// master clock
+	// it should be multiple by (ce_pix*4).
+	input        clk_sys,
+	
+	// Pixel clock or clock_enable (both are accepted).
+	input        ce_pix,
+
+	// Some systems have multiple resolutions.
+	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
+	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
+	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
+	input        ce_pix_actual,
+
+	// OSD SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// scanlines (00-none 01-25% 10-50% 11-75%)
+	input  [1:0] scanlines,
+
+	// 0 = HVSync 31KHz, 1 = CSync 15KHz
+	input        scandoubler_disable,
+
+	// High quality 2x scaling
+	input        hq2x,
+
+	// YPbPr always uses composite sync
+	input        ypbpr,
+
+	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
+	input        ypbpr_full,
+
+	// color
+	input [DWIDTH:0] R,
+	input [DWIDTH:0] G,
+	input [DWIDTH:0] B,
+
+	// Monochrome mode (for HALF_DEPTH only)
+	input            mono,
+
+	// interlace sync. Positive pulses.
+	input        HSync,
+	input        VSync,
+
+	// Falling of this signal means start of informative part of line.
+	// It can be horizontal blank signal.
+	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
+	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
+	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
+	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
+	// before first informative pixel.
+	input        line_start,
+
+	// MiST video output signals
+	output [5:0] VGA_R,
+	output [5:0] VGA_G,
+	output [5:0] VGA_B,
+	output       VGA_VS,
+	output       VGA_HS
+);
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+wire [DWIDTH:0] R_sd;
+wire [DWIDTH:0] G_sd;
+wire [DWIDTH:0] B_sd;
+wire hs_sd, vs_sd;
+
+scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
+(
+	.*,
+	.hs_in(HSync),
+	.vs_in(VSync),
+	.r_in(R),
+	.g_in(G),
+	.b_in(B),
+
+	.hs_out(hs_sd),
+	.vs_out(vs_sd),
+	.r_out(R_sd),
+	.g_out(G_sd),
+	.b_out(B_sd)
+);
+
+wire [DWIDTH:0] rt  = (scandoubler_disable ? R : R_sd);
+wire [DWIDTH:0] gt  = (scandoubler_disable ? G : G_sd);
+wire [DWIDTH:0] bt  = (scandoubler_disable ? B : B_sd);
+
+generate
+	if(HALF_DEPTH) begin
+		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
+		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
+		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
+	end else begin
+		wire [5:0] r  = rt;
+		wire [5:0] g  = gt;
+		wire [5:0] b  = bt;
+	end
+endgenerate
+
+wire       hs = (scandoubler_disable ? HSync : hs_sd);
+wire       vs = (scandoubler_disable ? VSync : vs_sd);
+
+reg scanline = 0;
+always @(posedge clk_sys) begin
+	reg old_hs, old_vs;
+	
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) scanline <= ~scanline;
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire [5:0] r_out, g_out, b_out;
+always @(*) begin
+	case(scanlines & {scanline, scanline})
+		1: begin // reduce 25% = 1/2 + 1/4
+			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
+			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
+			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
+		end
+
+		2: begin // reduce 50% = 1/2
+			r_out = {1'b0, r[5:1]};
+			g_out = {1'b0, g[5:1]};
+			b_out = {1'b0, b[5:1]};
+		end
+
+		3: begin // reduce 75% = 1/4
+			r_out = {2'b00, r[5:2]};
+			g_out = {2'b00, g[5:2]};
+			b_out = {2'b00, b[5:2]};
+		end
+
+		default: begin
+			r_out = r;
+			g_out = g;
+			b_out = b;
+		end
+	endcase
+end
+
+wire [5:0] red, green, blue;
+osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
+(
+	.*,
+
+	.R_in(r_out),
+	.G_in(g_out),
+	.B_in(b_out),
+	.HSync(hs),
+	.VSync(vs),
+
+	.R_out(red),
+	.G_out(green),
+	.B_out(blue)
+);
+
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+// http://marsee101.blog19.fc2.com/blog-entry-2311.html
+// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
+// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
+// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
+assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
+assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
+assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
+assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/snapshot/sprint1.rbf b/Arcade_MiST/Custom Hardware/SprintOne_MiST/snapshot/sprint1.rbf
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HcmV?d00001

diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/sprint1.qpf b/Arcade_MiST/Custom Hardware/SprintOne_MiST/sprint1.qpf
new file mode 100644
index 00000000..07be4a15
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/sprint1.qpf	
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 19:51:47  November 12, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "19:51:47  November 12, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "sprint1"
+PROJECT_REVISION = "sprint2"
diff --git a/Arcade_MiST/Custom Hardware/SprintOne_MiST/sprint1.qsf b/Arcade_MiST/Custom Hardware/SprintOne_MiST/sprint1.qsf
new file mode 100644
index 00000000..e1165832
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SprintOne_MiST/sprint1.qsf	
@@ -0,0 +1,174 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 15:18:38  May 31, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		sprint1_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16  OCTOBER 10, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY sprint1_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# ---------------------
+# start ENTITY(sprint1)
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+# end ENTITY(sprint1)
+# -------------------
+
+# --------------------------
+# start ENTITY(sprint1_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(sprint1_mist)
+# ------------------------
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sprint1_mist.sv
+set_global_assignment -name VHDL_FILE rtl/sprint1.vhd
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VHDL_FILE rtl/sprint1_sound.vhd
+set_global_assignment -name VHDL_FILE rtl/sync.vhd
+set_global_assignment -name VHDL_FILE rtl/collision.vhd
+set_global_assignment -name VHDL_FILE rtl/screech.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd
+set_global_assignment -name VHDL_FILE rtl/playfield.vhd
+set_global_assignment -name VHDL_FILE rtl/EngineSound.vhd
+set_global_assignment -name VHDL_FILE rtl/Inputs.vhd
+set_global_assignment -name VHDL_FILE rtl/motion.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/build_id.sv
+set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/SuperBreakout.qpf b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/SuperBreakout.qpf
new file mode 100644
index 00000000..626e8c9d
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/SuperBreakout.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 19:51:47  November 12, 2017
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "19:51:47  November 12, 2017"
+
+# Revisions
+
+PROJECT_REVISION = "SuperBreakout"
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/SuperBreakout.qsf b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/SuperBreakout.qsf
new file mode 100644
index 00000000..6bd41995
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/SuperBreakout.qsf	
@@ -0,0 +1,168 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 15:18:38  May 31, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		sprint1_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:52:16  OCTOBER 10, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
+set_global_assignment -name VHDL_FILE rtl/sync.vhd
+set_global_assignment -name VHDL_FILE rtl/playfield.vhd
+set_global_assignment -name VHDL_FILE rtl/motion.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu_mem.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/scandoubler.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist_io.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/osd.sv
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name TOP_LEVEL_ENTITY super_breakout_mist
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# ---------------------
+# start ENTITY(sprint1)
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+# end ENTITY(sprint1)
+# -------------------
+
+# --------------------------
+# start ENTITY(sprint1_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(sprint1_mist)
+# ------------------------
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VHDL_FILE rtl/super_breakout.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/super_breakout_mist.sv
+set_global_assignment -name VHDL_FILE rtl/audio.vhd
+set_global_assignment -name VHDL_FILE rtl/paddle.vhd
+set_global_assignment -name VHDL_FILE rtl/IO.vhd
+set_global_assignment -name VHDL_FILE rtl/quadrature_decoder.vhd
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/clean.bat b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/clean.bat
new file mode 100644
index 00000000..b3b7c3b5
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/clean.bat	
@@ -0,0 +1,37 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+
+pause
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/IO.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/IO.vhd
new file mode 100644
index 00000000..7dccec6d
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/IO.vhd	
@@ -0,0 +1,173 @@
+-- IO block for Atari Super Breakout
+-- 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+entity IO is 
+port(		
+			CLK6				: in  std_logic; 
+			SW2				: in  std_logic_vector(7 downto 0); -- DIP switches
+			Coin1_n			: in  std_logic; -- Coin switches
+			Coin2_n			: in 	std_logic;
+			Start1_n			: in	std_logic; -- 1 and 2 player start switches
+			Start2_n			: in	std_logic;
+			Select1_n		: in  std_logic; -- Game select inputs from rotary switch
+			Select2_n		: in  std_logic;
+			Serve_n			: in	std_logic; -- Serve button
+			Test_n			: in	std_logic; -- Self test switch
+			Slam_n			: in	std_logic; -- Slam switch
+			Sense1			: in  std_logic; -- Sense signals from paddle input circuit
+			Sense2			: in	std_logic;
+			Mask1_n			: out std_logic; -- Mask signals to paddle input circuit
+			Mask2_n			: out std_logic;
+			Timer_Reset_n	: out std_logic;
+			IntAck_n			: out std_logic;
+			IO_wr				: in  std_logic;
+			Lamp1				: out std_logic; -- Player start button lamps
+			Lamp2				: out std_logic; -- Active high to trigger SCRs controlling incandescent lamps
+			Serv_LED_n		: out std_logic; -- Serve button LED is active low
+			Counter			: out std_logic; -- Coin counter
+			Adr				: in  std_logic_vector(9 downto 0); -- Adress bus, only the lower 9 bits used by IO circuitry
+			Inputs			: out std_logic_vector(1 downto 0)  -- Out to data bus, only upper two bits used
+			);
+end IO;
+
+architecture rtl of IO is
+
+signal A8_8				: std_logic;
+signal H9_Q_n			: std_logic;
+signal H8_en			: std_logic;
+signal Coin1			: std_logic;
+signal Coin2			: std_logic;
+signal SW2_bank1		: std_logic;
+signal SW2_bank2		: std_logic;
+signal DipSW			: std_logic_vector(7 downto 0);
+signal E8_in			: std_logic_vector(3 downto 0);
+signal J9_out			: std_logic_vector(7 downto 0);
+signal E8_out			: std_logic_vector(9 downto 0);
+
+
+begin
+
+-- Inputs
+M8: process(Adr(7 downto 6), Coin1, Coin2, Start1_n, Start2_n, Test_n, Slam_n, A8_8, SW2_bank2)
+begin
+	case Adr(7 downto 6) is
+		when "00" => Inputs <= A8_8 & SW2_bank2; -- There is actually an inverter N9 fed by A8_8 so we will just account for that
+		when "01" => Inputs <= Coin2 & Coin1;
+		when "10" => Inputs <= Start2_n & Start1_n;
+		when "11" => Inputs <= Test_n & Slam_n;
+		when others => Inputs <= "11";
+		end case;
+end process;
+-- Coin switch inputs are active-high internally but inverted on board from active-low inputs
+Coin1 <= (not Coin1_n);
+Coin2 <= (not Coin2_n);
+
+
+H9: process(Adr, Select1_n, Select2_n, Serve_n, Sense1, Sense2)
+begin
+	if Adr(4) = '0' then -- Adr(4) is connected to enable
+		case Adr(2 downto 0) is
+			when "000" => H9_Q_n <= (not Select1_n);
+			when "100" => H9_Q_n <= (not Sense1);
+			when "101" => H9_Q_n <= (not Sense2);
+			when "110" => H9_Q_n <= (not Serve_n);
+			when "111" => H9_Q_n <= (not Select2_n);
+			when others => H9_Q_n <= '1';
+			end case;
+	else
+		H9_Q_n <= '1';
+	end if;
+end process;
+		
+	
+-- The way the dip switches are wired in the real hardware requires some changes 
+-- to achieve the same result while using standard active-low switch inputs.
+-- Switches are split into two banks, each bank fed from half of selector J9.
+J9: process(Adr)
+begin
+	if Adr(3) = '1' then
+		J9_out <= "11111111";
+	else
+		case Adr(1 downto 0) is
+			when "00" => J9_out <= "11101110";
+			when "01" => J9_out <= "11011101";
+			when "10" => J9_out <= "10111011";
+			when "11" => J9_out <= "01110111";
+			end case;
+	end if;
+end process;
+
+-- Re-order the dip switch signals to match the physical order of the switches
+-- Bank 1
+DipSW(7) <= J9_out(7) when SW2(1) = '0' else '1';
+DipSW(6) <= J9_out(6) when SW2(3) = '0' else '1';
+DipSW(5) <= J9_out(5) when SW2(5) = '0' else '1';
+DipSW(4) <= J9_out(4) when SW2(7) = '0' else '1';
+
+--Bank 2
+DipSW(3) <= J9_out(3) when SW2(0) = '0' else '1';
+DipSW(2) <= J9_out(2) when SW2(2) = '0' else '1';
+DipSW(1) <= J9_out(1) when SW2(4) = '0' else '1';
+DipSW(0) <= J9_out(0) when SW2(6) = '0' else '1';
+
+-- Outputs from each switch bank are tied together, logical AND since they are active low
+SW2_bank1 <= DipSW(7) and DipSW(6) and DipSW(5) and DipSW(4);
+SW2_bank2 <= DipSW(3) and DipSW(2) and DipSW(1) and DipSW(0);
+
+-- Bank 1 of dip switches is multiplexed with player inputs connected to selector H9
+A8_8 <= SW2_bank1 and H9_Q_n;
+
+
+-- Outputs
+E8_in <= IO_wr & Adr(9 downto 7);
+E8: process(E8_in)
+begin
+	case E8_in is
+		when "0000" => E8_out <= "1111111110";
+		when "0001" => E8_out <= "1111111101";
+      when "0100" => E8_out <= "1111101111";
+      when others => E8_out <= "1111111111";
+      end case;
+end process;
+
+H8_en <= E8_out(0);
+TIMER_RESET_n <= E8_out(1);
+INTACK_n <= E8_out(4);
+
+-- H8 9334 
+H8_dec: process(clk6)
+begin
+if rising_edge(clk6) then
+	if (H8_en = '0') then
+	  case Adr(6 downto 4) is
+		 when "000" => null;
+		 when "001" => SERV_LED_n <= Adr(0);
+		 when "010" => null;
+		 when "011" => LAMP1 <= Adr(0);
+		 when "100" => LAMP2 <= Adr(0);
+		 when "101" => MASK1_n <= Adr(0);
+		 when "110" => MASK2_n <= Adr(0);
+		 when "111" => COUNTER <= Adr(0);
+		 when others => null;
+	  end case;
+	end if;
+ end if;
+end process;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/Char_LSB.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/Char_LSB.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/Char_MSB.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/Char_MSB.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65.vhd
new file mode 100644
index 00000000..161debea
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65.vhd	
@@ -0,0 +1,551 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 more merging
+-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- 65C02 and 65C816 modes are incomplete
+-- Undocumented instructions are not supported
+-- Some interface signals behaves incorrect
+--
+-- File history :
+--
+--      0246 : First release
+--
+
+library IEEE;
+  use IEEE.std_logic_1164.all;
+  use IEEE.numeric_std.all;
+  use work.T65_Pack.all;
+
+-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
+-- the ready signal to limit the CPU.
+entity T65 is
+	port(
+		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+		Res_n   : in  std_logic;
+		Enable  : in  std_logic;
+		Clk     : in  std_logic;
+		Rdy     : in  std_logic;
+		Abort_n : in  std_logic;
+		IRQ_n   : in  std_logic;
+		NMI_n   : in  std_logic;
+		SO_n    : in  std_logic;
+		R_W_n   : out std_logic;
+		Sync    : out std_logic;
+		EF      : out std_logic;
+		MF      : out std_logic;
+		XF      : out std_logic;
+		ML_n    : out std_logic;
+		VP_n    : out std_logic;
+		VDA     : out std_logic;
+		VPA     : out std_logic;
+		A       : out std_logic_vector(23 downto 0);
+		DI      : in  std_logic_vector(7 downto 0);
+		DO      : out std_logic_vector(7 downto 0)
+	);
+end T65;
+
+architecture rtl of T65 is
+
+	-- Registers
+	signal ABC, X, Y, D       : std_logic_vector(15 downto 0);
+	signal P, AD, DL          : std_logic_vector(7 downto 0) :=  x"00";
+	signal BAH                : std_logic_vector(7 downto 0);
+	signal BAL                : std_logic_vector(8 downto 0);
+	signal PBR                : std_logic_vector(7 downto 0);
+	signal DBR                : std_logic_vector(7 downto 0);
+	signal PC                 : unsigned(15 downto 0);
+	signal S                  : unsigned(15 downto 0);
+	signal EF_i               : std_logic;
+	signal MF_i               : std_logic;
+	signal XF_i               : std_logic;
+
+	signal IR                 : std_logic_vector(7 downto 0);
+	signal MCycle             : std_logic_vector(2 downto 0);
+
+	signal Mode_r             : std_logic_vector(1 downto 0);
+	signal ALU_Op_r           : std_logic_vector(3 downto 0);
+	signal Write_Data_r       : std_logic_vector(2 downto 0);
+	signal Set_Addr_To_r      : std_logic_vector(1 downto 0);
+	signal PCAdder            : unsigned(8 downto 0);
+
+	signal RstCycle           : std_logic;
+	signal IRQCycle           : std_logic;
+	signal NMICycle           : std_logic;
+
+	signal B_o                : std_logic;
+	signal SO_n_o             : std_logic;
+	signal IRQ_n_o            : std_logic;
+	signal NMI_n_o            : std_logic;
+	signal NMIAct             : std_logic;
+
+	signal Break              : std_logic;
+
+	-- ALU signals
+	signal BusA               : std_logic_vector(7 downto 0);
+	signal BusA_r             : std_logic_vector(7 downto 0);
+	signal BusB               : std_logic_vector(7 downto 0);
+	signal ALU_Q              : std_logic_vector(7 downto 0);
+	signal P_Out              : std_logic_vector(7 downto 0);
+
+	-- Micro code outputs
+	signal LCycle             : std_logic_vector(2 downto 0);
+	signal ALU_Op             : std_logic_vector(3 downto 0);
+	signal Set_BusA_To        : std_logic_vector(2 downto 0);
+	signal Set_Addr_To        : std_logic_vector(1 downto 0);
+	signal Write_Data         : std_logic_vector(2 downto 0);
+	signal Jump               : std_logic_vector(1 downto 0);
+	signal BAAdd              : std_logic_vector(1 downto 0);
+	signal BreakAtNA          : std_logic;
+	signal ADAdd              : std_logic;
+	signal AddY               : std_logic;
+	signal PCAdd              : std_logic;
+	signal Inc_S              : std_logic;
+	signal Dec_S              : std_logic;
+	signal LDA                : std_logic;
+	signal LDP                : std_logic;
+	signal LDX                : std_logic;
+	signal LDY                : std_logic;
+	signal LDS                : std_logic;
+	signal LDDI               : std_logic;
+	signal LDALU              : std_logic;
+	signal LDAD               : std_logic;
+	signal LDBAL              : std_logic;
+	signal LDBAH              : std_logic;
+	signal SaveP              : std_logic;
+	signal Write              : std_logic;
+
+	signal really_rdy         : std_logic;
+	signal R_W_n_i            : std_logic;
+
+begin
+	-- ehenciak : gate Rdy with read/write to make an "OK, it's
+	--            really OK to stop the processor now if Rdy is
+	--            deasserted" signal
+	really_rdy <= Rdy or not(R_W_n_i);
+
+	-- ehenciak : Drive R_W_n_i off chip.
+	R_W_n      <= R_W_n_i;
+
+	Sync <= '1' when MCycle = "000" else '0';
+	EF <= EF_i;
+	MF <= MF_i;
+	XF <= XF_i;
+	ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
+	VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
+	VDA <= '1' when Set_Addr_To_r /= "000" else '0';            -- Incorrect !!!!!!!!!!!!
+	VPA <= '1' when Jump(1) = '0' else '0';                     -- Incorrect !!!!!!!!!!!!
+
+	mcode : T65_MCode
+		port map(
+			Mode        => Mode_r,
+			IR          => IR,
+			MCycle      => MCycle,
+			P           => P,
+			LCycle      => LCycle,
+			ALU_Op      => ALU_Op,
+			Set_BusA_To => Set_BusA_To,
+			Set_Addr_To => Set_Addr_To,
+			Write_Data  => Write_Data,
+			Jump        => Jump,
+			BAAdd       => BAAdd,
+			BreakAtNA   => BreakAtNA,
+			ADAdd       => ADAdd,
+			AddY        => AddY,
+			PCAdd       => PCAdd,
+			Inc_S       => Inc_S,
+			Dec_S       => Dec_S,
+			LDA         => LDA,
+			LDP         => LDP,
+			LDX         => LDX,
+			LDY         => LDY,
+			LDS         => LDS,
+			LDDI        => LDDI,
+			LDALU       => LDALU,
+			LDAD        => LDAD,
+			LDBAL       => LDBAL,
+			LDBAH       => LDBAH,
+			SaveP       => SaveP,
+			Write       => Write
+			);
+
+	alu : T65_ALU
+		port map(
+			Mode => Mode_r,
+			Op => ALU_Op_r,
+			BusA => BusA_r,
+			BusB => BusB,
+			P_In => P,
+			P_Out => P_Out,
+			Q => ALU_Q
+			);
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			PC <= (others => '0');  -- Program Counter
+			IR <= "00000000";
+			S <= (others => '0');       -- Dummy !!!!!!!!!!!!!!!!!!!!!
+			D <= (others => '0');
+			PBR <= (others => '0');
+			DBR <= (others => '0');
+
+			Mode_r <= (others => '0');
+			ALU_Op_r <= "1100";
+			Write_Data_r <= "000";
+			Set_Addr_To_r <= "00";
+
+			R_W_n_i <= '1';
+			EF_i <= '1';
+			MF_i <= '1';
+			XF_i <= '1';
+
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				R_W_n_i <= not Write or RstCycle;
+
+				D <= (others => '1');   -- Dummy
+				PBR <= (others => '1'); -- Dummy
+				DBR <= (others => '1'); -- Dummy
+				EF_i <= '0';    -- Dummy
+				MF_i <= '0';    -- Dummy
+				XF_i <= '0';    -- Dummy
+
+				if MCycle  = "000" then
+					Mode_r <= Mode;
+
+					if IRQCycle = '0' and NMICycle = '0' then
+						PC <= PC + 1;
+					end if;
+
+					if IRQCycle = '1' or NMICycle = '1' then
+						IR <= "00000000";
+					else
+						IR <= DI;
+					end if;
+				end if;
+
+				ALU_Op_r <= ALU_Op;
+				Write_Data_r <= Write_Data;
+				if Break = '1' then
+					Set_Addr_To_r <= "00";
+				else
+					Set_Addr_To_r <= Set_Addr_To;
+				end if;
+
+				if Inc_S = '1' then
+					S <= S + 1;
+				end if;
+				if Dec_S = '1' and RstCycle = '0' then
+					S <= S - 1;
+				end if;
+				if LDS = '1' then
+					S(7 downto 0) <= unsigned(ALU_Q);
+				end if;
+
+				if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
+					PC <= PC + 1;
+				end if;
+				--
+				-- jump control logic
+				--
+				case Jump is
+				  when "01" =>
+					  PC <= PC + 1;
+
+				  when "10" =>
+					  PC <= unsigned(DI & DL);
+
+				  when "11" =>
+					  if PCAdder(8) = '1' then
+						  if DL(7) = '0' then
+							  PC(15 downto 8) <= PC(15 downto 8) + 1;
+						  else
+							  PC(15 downto 8) <= PC(15 downto 8) - 1;
+						  end if;
+					  end if;
+					  PC(7 downto 0) <= PCAdder(7 downto 0);
+
+				  when others => null;
+				end case;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+	PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
+			   else "0" & PC(7 downto 0);
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				if MCycle = "000" then
+					if LDA = '1' then
+						ABC(7 downto 0) <= ALU_Q;
+					end if;
+					if LDX = '1' then
+						X(7 downto 0) <= ALU_Q;
+					end if;
+					if LDY = '1' then
+						Y(7 downto 0) <= ALU_Q;
+					end if;
+					if (LDA or LDX or LDY) = '1' then
+						P <= P_Out;
+					end if;
+				end if;
+				if SaveP = '1' then
+					P <= P_Out;
+				end if;
+				if LDP = '1' then
+					P <= ALU_Q;
+				end if;
+				if IR(4 downto 0) = "11000" then
+					case IR(7 downto 5) is
+					when "000" =>
+						P(Flag_C) <= '0';
+					when "001" =>
+						P(Flag_C) <= '1';
+					when "010" =>
+						P(Flag_I) <= '0';
+					when "011" =>
+						P(Flag_I) <= '1';
+					when "101" =>
+						P(Flag_V) <= '0';
+					when "110" =>
+						P(Flag_D) <= '0';
+					when "111" =>
+						P(Flag_D) <= '1';
+					when others =>
+					end case;
+				end if;
+				if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
+					P(Flag_B) <= '1';
+				end if;
+				if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1')  then
+					P(Flag_I) <= '1';
+					P(Flag_B) <= B_o;
+				end if;
+				if SO_n_o = '1' and SO_n = '0' then
+					P(Flag_V) <= '1';
+				end if;
+				if RstCycle = '1' and Mode_r /= "00" then
+					P(Flag_1) <= '1';
+					P(Flag_D) <= '0';
+					P(Flag_I) <= '1';
+				end if;
+				P(Flag_1) <= '1';
+
+				B_o     <= P(Flag_B);
+				SO_n_o <= SO_n;
+				IRQ_n_o <= IRQ_n;
+				NMI_n_o <= NMI_n;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			BusA_r <= (others => '0');
+			BusB <= (others => '0');
+			AD <= (others => '0');
+			BAL <= (others => '0');
+			BAH <= (others => '0');
+			DL <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (Rdy = '1') then
+				BusA_r <= BusA;
+				BusB <= DI;
+
+				case BAAdd is
+				when "01" =>
+					-- BA Inc
+					AD <= std_logic_vector(unsigned(AD) + 1);
+					BAL <= std_logic_vector(unsigned(BAL) + 1);
+				when "10" =>
+					-- BA Add
+					BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
+				when "11" =>
+					-- BA Adj
+					if BAL(8) = '1' then
+						BAH <= std_logic_vector(unsigned(BAH) + 1);
+					end if;
+				when others =>
+				end case;
+
+				-- ehenciak : modified to use Y register as well (bugfix)
+				if ADAdd = '1' then
+				  if (AddY = '1') then
+					AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
+				  else
+					AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
+				  end if;
+				end if;
+
+				if IR = "00000000" then
+					BAL <= (others => '1');
+					BAH <= (others => '1');
+					if RstCycle = '1' then
+						BAL(2 downto 0) <= "100";
+					elsif NMICycle = '1' then
+						BAL(2 downto 0) <= "010";
+					else
+						BAL(2 downto 0) <= "110";
+					end if;
+					if Set_addr_To_r = "11" then
+						BAL(0) <= '1';
+					end if;
+				end if;
+
+
+				if LDDI = '1' then
+					DL <= DI;
+				end if;
+				if LDALU = '1' then
+					DL <= ALU_Q;
+				end if;
+				if LDAD = '1' then
+					AD <= DI;
+				end if;
+				if LDBAL = '1' then
+					BAL(7 downto 0) <= DI;
+				end if;
+				if LDBAH = '1' then
+					BAH <= DI;
+				end if;
+			end if;
+		end if;
+	  end if;
+	end process;
+
+	Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
+
+
+	with Set_BusA_To select
+		BusA <= DI when "000",
+			ABC(7 downto 0) when "001",
+			X(7 downto 0) when "010",
+			Y(7 downto 0) when "011",
+			std_logic_vector(S(7 downto 0)) when "100",
+			P when "101",
+			(others => '-') when others;
+
+	with Set_Addr_To_r select
+		A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
+			DBR & "00000000" & AD when "10",
+			"00000000" & BAH & BAL(7 downto 0) when "11",
+			PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
+
+	with Write_Data_r select
+		DO <= DL when "000",
+			ABC(7 downto 0) when "001",
+			X(7 downto 0) when "010",
+			Y(7 downto 0) when "011",
+			std_logic_vector(S(7 downto 0)) when "100",
+			P when "101",
+			std_logic_vector(PC(7 downto 0)) when "110",
+			std_logic_vector(PC(15 downto 8)) when others;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+
+	process (Res_n, Clk)
+	begin
+		if Res_n = '0' then
+			MCycle <= "001";
+			RstCycle <= '1';
+			IRQCycle <= '0';
+			NMICycle <= '0';
+			NMIAct <= '0';
+		elsif Clk'event and Clk = '1' then
+		  if (Enable = '1') then
+			if (really_rdy = '1') then
+				if MCycle = LCycle or Break = '1' then
+					MCycle <= "000";
+					RstCycle <= '0';
+					IRQCycle <= '0';
+					NMICycle <= '0';
+					if NMIAct = '1' then
+						NMICycle <= '1';
+					elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
+						IRQCycle <= '1';
+					end if;
+				else
+					MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+				end if;
+
+				if NMICycle = '1' then
+					NMIAct <= '0';
+				end if;
+				if NMI_n_o = '1' and NMI_n = '0' then
+					NMIAct <= '1';
+				end if;
+			end if;
+		  end if;
+		end if;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_ALU.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_ALU.vhd
new file mode 100644
index 00000000..b1f6d632
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_ALU.vhd	
@@ -0,0 +1,260 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 6502 compatible microprocessor core
+--
+-- Version : 0245
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0245 : First version
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T65_Pack.all;
+
+entity T65_ALU is
+	port(
+		Mode    : in std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		Op      : in std_logic_vector(3 downto 0);
+		BusA    : in std_logic_vector(7 downto 0);
+		BusB    : in std_logic_vector(7 downto 0);
+		P_In    : in std_logic_vector(7 downto 0);
+		P_Out   : out std_logic_vector(7 downto 0);
+		Q       : out std_logic_vector(7 downto 0)
+	);
+end T65_ALU;
+
+architecture rtl of T65_ALU is
+
+	-- AddSub variables (temporary signals)
+	signal      ADC_Z           : std_logic;
+	signal      ADC_C           : std_logic;
+	signal      ADC_V           : std_logic;
+	signal      ADC_N           : std_logic;
+	signal      ADC_Q           : std_logic_vector(7 downto 0);
+	signal      SBC_Z           : std_logic;
+	signal      SBC_C           : std_logic;
+	signal      SBC_V           : std_logic;
+	signal      SBC_N           : std_logic;
+	signal      SBC_Q           : std_logic_vector(7 downto 0);
+
+begin
+
+	process (P_In, BusA, BusB)
+		variable AL : unsigned(6 downto 0);
+		variable AH : unsigned(6 downto 0);
+		variable C : std_logic;
+	begin
+		AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
+		AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+			ADC_Z <= '1';
+		else
+			ADC_Z <= '0';
+		end if;
+
+		if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+			AL(6 downto 1) := AL(6 downto 1) + 6;
+		end if;
+
+		C := AL(6) or AL(5);
+		AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
+
+		ADC_N <= AH(4);
+		ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
+-- pragma translate_on
+
+		if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
+			AH(6 downto 1) := AH(6 downto 1) + 6;
+		end if;
+
+		ADC_C <= AH(6) or AH(5);
+
+		ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+	end process;
+
+	process (Op, P_In, BusA, BusB)
+		variable AL : unsigned(6 downto 0);
+		variable AH : unsigned(5 downto 0);
+		variable C : std_logic;
+	begin
+		C := P_In(Flag_C) or not Op(0);
+		AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
+		AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
+
+-- pragma translate_off
+			if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
+			if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
+-- pragma translate_on
+
+		if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
+			SBC_Z <= '1';
+		else
+			SBC_Z <= '0';
+		end if;
+
+		SBC_C <= not AH(5);
+		SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
+		SBC_N <= AH(4);
+
+		if P_In(Flag_D) = '1' then
+			if AL(5) = '1' then
+				AL(5 downto 1) := AL(5 downto 1) - 6;
+			end if;
+			AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
+			if AH(5) = '1' then
+				AH(5 downto 1) := AH(5 downto 1) - 6;
+			end if;
+		end if;
+
+		SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
+	end process;
+
+	process (Op, P_In, BusA, BusB,
+			ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
+			SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
+		variable Q_t : std_logic_vector(7 downto 0);
+	begin
+		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
+		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
+		P_Out <= P_In;
+		Q_t := BusA;
+		case Op(3 downto 0) is
+		when "0000" =>
+			-- ORA
+			Q_t := BusA or BusB;
+		when "0001" =>
+			-- AND
+			Q_t := BusA and BusB;
+		when "0010" =>
+			-- EOR
+			Q_t := BusA xor BusB;
+		when "0011" =>
+			-- ADC
+			P_Out(Flag_V) <= ADC_V;
+			P_Out(Flag_C) <= ADC_C;
+			Q_t := ADC_Q;
+		when "0101" | "1101" =>
+			-- LDA
+		when "0110" =>
+			-- CMP
+			P_Out(Flag_C) <= SBC_C;
+		when "0111" =>
+			-- SBC
+			P_Out(Flag_V) <= SBC_V;
+			P_Out(Flag_C) <= SBC_C;
+			Q_t := SBC_Q;
+		when "1000" =>
+			-- ASL
+			Q_t := BusA(6 downto 0) & "0";
+			P_Out(Flag_C) <= BusA(7);
+		when "1001" =>
+			-- ROL
+			Q_t := BusA(6 downto 0) & P_In(Flag_C);
+			P_Out(Flag_C) <= BusA(7);
+		when "1010" =>
+			-- LSR
+			Q_t := "0" & BusA(7 downto 1);
+			P_Out(Flag_C) <= BusA(0);
+		when "1011" =>
+			-- ROR
+			Q_t := P_In(Flag_C) & BusA(7 downto 1);
+			P_Out(Flag_C) <= BusA(0);
+		when "1100" =>
+			-- BIT
+			P_Out(Flag_V) <= BusB(6);
+		when "1110" =>
+			-- DEC
+			Q_t := std_logic_vector(unsigned(BusA) - 1);
+		when "1111" =>
+			-- INC
+			Q_t := std_logic_vector(unsigned(BusA) + 1);
+		when others =>
+		end case;
+
+		case Op(3 downto 0) is
+		when "0011" =>
+			P_Out(Flag_N) <= ADC_N;
+			P_Out(Flag_Z) <= ADC_Z;
+		when "0110" | "0111" =>
+			P_Out(Flag_N) <= SBC_N;
+			P_Out(Flag_Z) <= SBC_Z;
+		when "0100" =>
+		when "1100" =>
+			P_Out(Flag_N) <= BusB(7);
+			if (BusA and BusB) = "00000000" then
+				P_Out(Flag_Z) <= '1';
+			else
+				P_Out(Flag_Z) <= '0';
+			end if;
+		when others =>
+			P_Out(Flag_N) <= Q_t(7);
+			if Q_t = "00000000" then
+				P_Out(Flag_Z) <= '1';
+			else
+				P_Out(Flag_Z) <= '0';
+			end if;
+		end case;
+
+		Q <= Q_t;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_MCode.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_MCode.vhd
new file mode 100644
index 00000000..06229751
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_MCode.vhd	
@@ -0,0 +1,1050 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 Jump timing fixed
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246 + fix
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- 65C02
+-- supported : inc, dec, phx, plx, phy, ply
+-- missing : bra, ora, lda, cmp, sbc, tsb*2, trb*2, stz*2, bit*2, wai, stp, jmp, bbr*8, bbs*8
+--
+-- File history :
+--
+--      0246 : First release
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T65_Pack.all;
+
+entity T65_MCode is
+	port(
+		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		IR                      : in  std_logic_vector(7 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		P                       : in  std_logic_vector(7 downto 0);
+		LCycle                  : out std_logic_vector(2 downto 0);
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
+		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
+		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
+		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
+		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
+		BreakAtNA               : out std_logic;
+		ADAdd                   : out std_logic;
+		AddY                    : out std_logic;
+		PCAdd                   : out std_logic;
+		Inc_S                   : out std_logic;
+		Dec_S                   : out std_logic;
+		LDA                     : out std_logic;
+		LDP                     : out std_logic;
+		LDX                     : out std_logic;
+		LDY                     : out std_logic;
+		LDS                     : out std_logic;
+		LDDI                    : out std_logic;
+		LDALU                   : out std_logic;
+		LDAD                    : out std_logic;
+		LDBAL                   : out std_logic;
+		LDBAH                   : out std_logic;
+		SaveP                   : out std_logic;
+		Write                   : out std_logic
+	);
+end T65_MCode;
+
+architecture rtl of T65_MCode is
+
+	signal Branch : std_logic;
+
+begin
+
+	with IR(7 downto 5) select
+		Branch <= not P(Flag_N) when "000",
+					  P(Flag_N) when "001",
+				  not P(Flag_V) when "010",
+					  P(Flag_V) when "011",
+				  not P(Flag_C) when "100",
+					  P(Flag_C) when "101",
+				  not P(Flag_Z) when "110",
+					  P(Flag_Z) when others;
+
+	process (IR, MCycle, P, Branch, Mode)
+	begin
+		LCycle      <= "001";
+		Set_BusA_To <= "001"; -- A
+		Set_Addr_To <= (others => '0');
+		Write_Data  <= (others => '0');
+		Jump        <= (others => '0');
+		BAAdd       <= "00";
+		BreakAtNA   <= '0';
+		ADAdd       <= '0';
+		PCAdd       <= '0';
+		Inc_S       <= '0';
+		Dec_S       <= '0';
+		LDA         <= '0';
+		LDP         <= '0';
+		LDX         <= '0';
+		LDY         <= '0';
+		LDS         <= '0';
+		LDDI        <= '0';
+		LDALU       <= '0';
+		LDAD        <= '0';
+		LDBAL       <= '0';
+		LDBAH       <= '0';
+		SaveP       <= '0';
+		Write       <= '0';
+		AddY        <= '0';
+
+		case IR(7 downto 5) is
+		when "100" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				Set_BusA_To <= "011"; -- Y
+				Write_Data <= "011"; -- Y
+			when "10" =>
+				Set_BusA_To <= "010"; -- X
+				Write_Data <= "010"; -- X
+			when others =>
+				Write_Data <= "001"; -- A
+			end case;
+		--}}}
+		when "101" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) /= '1' or IR(2) /= '0' then
+					LDY <= '1';
+				end if;
+			when "10" =>
+				LDX <= '1';
+			when others =>
+				LDA <= '1';
+			end case;
+			Set_BusA_To <= "000"; -- DI
+		--}}}
+		when "110" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) = '0' then
+					LDY <= '1';
+				end if;
+				Set_BusA_To <= "011"; -- Y
+			when others =>
+				Set_BusA_To <= "001"; -- A
+			end case;
+		--}}}
+		when "111" =>
+		--{{{
+			case IR(1 downto 0) is
+			when "00" =>
+				if IR(4) = '0' then
+					LDX <= '1';
+				end if;
+				Set_BusA_To <= "010"; -- X
+			when others =>
+				Set_BusA_To <= "001"; -- A
+			end case;
+		--}}}
+		when others =>
+		end case;
+
+		if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+			Set_BusA_To <= "000"; -- DI
+		end if;
+
+		case IR(4 downto 0) is
+		when "00000" | "01000" | "01010" | "11000" | "11010" =>
+		--{{{
+			-- Implied
+			case IR is
+			when "00000000" =>
+				-- BRK
+				LCycle <= "110";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "111"; -- PCH
+					Write <= '1';
+				when 2 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "110"; -- PCL
+					Write <= '1';
+				when 3 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "101"; -- P
+					Write <= '1';
+				when 4 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					LDDI <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 6 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "00100000" =>
+				-- JSR
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "111"; -- PCH
+					Write <= '1';
+				when 3 =>
+					Dec_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Write_Data <= "110"; -- PCL
+					Write <= '1';
+				when 4 =>
+					Dec_S <= '1';
+				when 5 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "01000000" =>
+				-- RTI
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+					Set_BusA_To <= "000"; -- DI
+				when 4 =>
+					LDP <= '1';
+					Inc_S <= '1';
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 5 =>
+					Jump <= "10"; -- DIDL
+				when others =>
+				end case;
+			when "01100000" =>
+				-- RTS
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Inc_S <= '1';
+					LDDI <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 4 =>
+					Jump <= "10"; -- DIDL
+				when 5 =>
+					Jump <= "01";
+				when others =>
+				end case;
+			when "00001000" | "01001000" | "01011010" | "11011010" =>
+				-- PHP, PHA, PHY*, PHX*
+				LCycle <= "010";
+				if Mode = "00" and IR(1) = '1' then
+					LCycle <= "001";
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					case IR(7 downto 4) is
+					when "0000" =>
+						Write_Data <= "101"; -- P
+					when "0100" =>
+						Write_Data <= "001"; -- A
+					when "0101" =>
+						Write_Data <= "011"; -- Y
+					when "1101" =>
+						Write_Data <= "010"; -- X
+					when others =>
+					end case;
+					Write <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Dec_S <= '1';
+				when others =>
+				end case;
+			when "00101000" | "01101000" | "01111010" | "11111010" =>
+				-- PLP, PLA, PLY*, PLX*
+				LCycle <= "011";
+				if Mode = "00" and IR(1) = '1' then
+					LCycle <= "001";
+				end if;
+				case IR(7 downto 4) is
+				when "0010" =>
+					LDP <= '1';
+				when "0110" =>
+					LDA <= '1';
+				when "0111" =>
+					if Mode /= "00" then
+						LDY <= '1';
+					end if;
+				when "1111" =>
+					if Mode /= "00" then
+						LDX <= '1';
+					end if;
+				when others =>
+				end case;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					SaveP <= '1';
+				when 1 =>
+					Set_Addr_To <= "01"; -- S
+				when 2 =>
+					Inc_S <= '1';
+					Set_Addr_To <= "01"; -- S
+				when 3 =>
+					Set_BusA_To <= "000"; -- DI
+				when others =>
+				end case;
+			when "10100000" | "11000000" | "11100000" =>
+				-- LDY, CPY, CPX
+				-- Immediate
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+				when others =>
+				end case;
+			when "10001000" =>
+				-- DEY
+				LDY <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "011"; -- Y
+				when others =>
+				end case;
+			when "11001010" =>
+				-- DEX
+				LDX <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "010"; -- X
+				when others =>
+				end case;
+			when "00011010" | "00111010" =>
+				-- INC*, DEC*
+				if Mode /= "00" then
+					LDA <= '1'; -- A
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "100"; -- S
+				when others =>
+				end case;
+			when "00001010" | "00101010" | "01001010" | "01101010" =>
+				-- ASL, ROL, LSR, ROR
+				LDA <= '1'; -- A
+				Set_BusA_To <= "001"; -- A
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+				when others =>
+				end case;
+			when "10001010" | "10011000" =>
+				-- TYA, TXA
+				LDA <= '1'; -- A
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+				when others =>
+				end case;
+			when "10101010" | "10101000" =>
+				-- TAX, TAY
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "001"; -- A
+				when others =>
+				end case;
+			when "10011010" =>
+				-- TXS
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					LDS <= '1';
+				when 1 =>
+				when others =>
+				end case;
+			when "10111010" =>
+				-- TSX
+				LDX <= '1';
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Set_BusA_To <= "100"; -- S
+				when others =>
+				end case;
+
+		--                      when "00011000" | "00111000" | "01011000" | "01111000" | "10111000" | "11011000" | "11111000" | "11001000" | "11101000" =>
+		--                              -- CLC, SEC, CLI, SEI, CLV, CLD, SED, INY, INX
+		--                              case to_integer(unsigned(MCycle)) is
+		--                              when 1 =>
+		--                              when others =>
+		--                              end case;
+			when others =>
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when others =>
+				end case;
+			end case;
+		--}}}
+
+		when "00001" | "00011" =>
+		--{{{
+			-- Zero Page Indexed Indirect (d,x)
+			LCycle <= "101";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+				ADAdd <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 3 =>
+				BAAdd <= "01";  -- DB Inc
+				LDBAL <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 4 =>
+				LDBAH <= '1';
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 5 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "01001" | "01011" =>
+		--{{{
+			-- Immediate
+			LDA <= '1';
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+			when others =>
+			end case;
+
+		--}}}
+
+		when "00010" | "10010" =>
+		--{{{
+			-- Immediate, KIL
+			LDX <= '1';
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				if IR = "10100010" then
+					-- LDX
+					Jump <= "01";
+				else
+					-- KIL !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+				end if;
+			when others =>
+			end case;
+		--}}}
+
+		when "00100" =>
+		--{{{
+			-- Zero Page
+			LCycle <= "010";
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+				if IR(7 downto 5) = "001" then
+					SaveP <= '1';
+				end if;
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				end if;
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "00101" | "00110" | "00111" =>
+		--{{{
+			-- Zero Page
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 3 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 4 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "010";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "01100" =>
+		--{{{
+			-- Absolute
+			if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then
+				-- JMP
+				if IR(5) = '0' then
+					--LCycle <= "011";
+					LCycle <= "010";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						Jump <= "01";
+						LDDI <= '1';
+					when 2 =>
+						Jump <= "10"; -- DIDL
+					when others =>
+					end case;
+				else
+					LCycle <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						Jump <= "01";
+						LDDI <= '1';
+						LDBAL <= '1';
+					when 3 =>
+						LDBAH <= '1';
+						if Mode /= "00" then
+							Jump <= "10"; -- DIDL
+						end if;
+						if Mode = "00" then
+							Set_Addr_To <= "11"; -- BA
+						end if;
+					when 4 =>
+						LDDI <= '1';
+						if Mode = "00" then
+							Set_Addr_To <= "11"; -- BA
+							BAAdd <= "01";      -- DB Inc
+						else
+							Jump <= "01";
+						end if;
+					when 5 =>
+						Jump <= "10"; -- DIDL
+					when others =>
+					end case;
+				end if;
+			else
+				LCycle <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+					if IR(7 downto 5) = "001" then
+						SaveP <= '1';
+					end if;
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "01101" | "01110" | "01111" =>
+		--{{{
+			-- Absolute
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+					Write <= '1';
+					LDALU <= '1';
+					SaveP <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					SaveP <= '0'; -- MIKEJ was 1
+				when others =>
+				end case;
+			else
+				LCycle <= "011";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					LDBAH <= '1';
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "10000" =>
+		--{{{
+			-- Relative
+
+						-- This circuit dictates when the last
+						-- microcycle occurs for the branch depending on
+						-- whether or not the branch is taken and if a page
+						-- is crossed...
+			if (Branch = '1') then
+
+							 LCycle <= "011"; -- We're done @ T3 if branching...upper
+											  -- level logic will stop at T2 if no page cross
+											  -- (See the Break signal)
+			else
+
+							 LCycle <= "001";
+
+			end if;
+
+						-- This decodes the current microcycle and takes the
+						-- proper course of action...
+			case to_integer(unsigned(MCycle)) is
+
+							-- On the T1 microcycle, increment the program counter
+							-- and instruct the upper level logic to fetch the offset
+							-- from the Din bus and store it in the data latches. This
+							-- will be the last microcycle if the branch isn't taken.
+				when 1 =>
+
+					Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
+											  -- from microcycle T0.
+
+				LDDI <= '1';  -- Tells logic in top level (T65.vhd) to route
+											  -- the Din bus to the memory data latch (DL)
+											  -- so that the branch offset is fetched.
+
+							-- In microcycle T2, tell the logic in the top level to
+							-- add the offset.  If the most significant byte of the
+							-- program counter (i.e. the current "page") does not need
+							-- updating, we are done here...the Break signal at the
+							-- T65.vhd level takes care of that...
+				when 2 =>
+
+				Jump    <= "11"; -- Tell the PC Jump logic to use relative mode.
+
+				PCAdd   <= '1';  -- This tells the PC adder to update itself with
+												 -- the current offset recently fetched from
+												 -- memory.
+
+							-- The following is microcycle T3 :
+							-- The program counter should be completely updated
+							-- on this cycle after the page cross is detected.
+							-- We don't need to do anything here...
+				when 3 =>
+
+
+				when others => null; -- Do nothing.
+
+			end case;
+		--}}}
+
+		when "10001" | "10011" =>
+		--{{{
+			-- Zero Page Indirect Indexed (d),y
+			LCycle <= "101";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDAD <= '1';
+				Set_Addr_To <= "10"; -- AD
+			when 2 =>
+				LDBAL <= '1';
+				BAAdd <= "01";  -- DB Inc
+				Set_Addr_To <= "10"; -- AD
+			when 3 =>
+				Set_BusA_To <= "011"; -- Y
+				BAAdd <= "10";  -- BA Add
+				LDBAH <= '1';
+				Set_Addr_To <= "11"; -- BA
+			when 4 =>
+				BAAdd <= "11";  -- BA Adj
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				else
+					BreakAtNA <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 5 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "10100" | "10101" | "10110" | "10111" =>
+		--{{{
+			-- Zero Page, X
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "101";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					ADAdd <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 3 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 4 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 5 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "011";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDAD <= '1';
+					Set_Addr_To <= "10"; -- AD
+				when 2 =>
+					ADAdd <= '1';
+					-- Added this check for Y reg. use...
+					if (IR(3 downto 0) = "0110") then
+					  AddY <= '1';
+					end if;
+
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					end if;
+					Set_Addr_To <= "10"; -- AD
+				when 3 => null;
+				when others =>
+				end case;
+			end if;
+		--}}}
+
+		when "11001" | "11011" =>
+		--{{{
+			-- Absolute Y
+			LCycle <= "100";
+			if IR(7 downto 6) /= "10" then
+				LDA <= '1';
+			end if;
+			case to_integer(unsigned(MCycle)) is
+			when 0 =>
+			when 1 =>
+				Jump <= "01";
+				LDBAL <= '1';
+			when 2 =>
+				Jump <= "01";
+				Set_BusA_To <= "011"; -- Y
+				BAAdd <= "10";  -- BA Add
+				LDBAH <= '1';
+				Set_Addr_To <= "11"; -- BA
+			when 3 =>
+				BAAdd <= "11";  -- BA adj
+				if IR(7 downto 5) = "100" then
+					Write <= '1';
+				else
+					BreakAtNA <= '1';
+				end if;
+				Set_Addr_To <= "11"; -- BA
+			when 4 =>
+			when others =>
+			end case;
+		--}}}
+
+		when "11100" | "11101" | "11110" | "11111" =>
+		--{{{
+			-- Absolute X
+
+			if IR(7 downto 6) /= "10" and IR(1 downto 0) = "10" then
+				-- Read-Modify-Write
+				LCycle <= "110";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					Set_BusA_To <= "010"; -- X
+					BAAdd <= "10";      -- BA Add
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					BAAdd <= "11";      -- BA adj
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+					LDDI <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 5 =>
+					LDALU <= '1';
+					SaveP <= '1';
+					Write <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 6 =>
+				when others =>
+				end case;
+			else
+				LCycle <= "100";
+				if IR(7 downto 6) /= "10" then
+					LDA <= '1';
+				end if;
+				case to_integer(unsigned(MCycle)) is
+				when 0 =>
+				when 1 =>
+					Jump <= "01";
+					LDBAL <= '1';
+				when 2 =>
+					Jump <= "01";
+					-- mikej
+					-- special case 0xBE which uses Y reg as index!!
+					if (IR = "10111110") then
+					  Set_BusA_To <= "011"; -- Y
+					else
+					  Set_BusA_To <= "010"; -- X
+					end if;
+					BAAdd <= "10";      -- BA Add
+					LDBAH <= '1';
+					Set_Addr_To <= "11"; -- BA
+				when 3 =>
+					BAAdd <= "11";      -- BA adj
+					if IR(7 downto 5) = "100" then
+						Write <= '1';
+					else
+						BreakAtNA <= '1';
+					end if;
+					Set_Addr_To <= "11"; -- BA
+				when 4 =>
+				when others =>
+				end case;
+			end if;
+		--}}}
+		when others =>
+		end case;
+	end process;
+
+	process (IR, MCycle)
+	begin
+		-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
+		-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
+		case IR(1 downto 0) is
+		when "00" =>
+		--{{{
+			case IR(4 downto 2) is
+			when "000" | "001" | "011" =>
+				case IR(7 downto 5) is
+				when "110" | "111" =>
+					-- CP
+					ALU_Op <= "0110";
+				when "101" =>
+					-- LD
+					ALU_Op <= "0101";
+				when "001" =>
+					-- BIT
+					ALU_Op <= "1100";
+				when others =>
+					-- NOP/ST
+					ALU_Op <= "0100";
+				end case;
+			when "010" =>
+				case IR(7 downto 5) is
+				when "111" | "110" =>
+					-- IN
+					ALU_Op <= "1111";
+				when "100" =>
+					-- DEY
+					ALU_Op <= "1110";
+				when others =>
+					-- LD
+					ALU_Op <= "1101";
+				end case;
+			when "110" =>
+				case IR(7 downto 5) is
+				when "100" =>
+					-- TYA
+					ALU_Op <= "1101";
+				when others =>
+					ALU_Op <= "----";
+				end case;
+			when others =>
+				case IR(7 downto 5) is
+				when "101" =>
+					-- LD
+					ALU_Op <= "1101";
+				when others =>
+					ALU_Op <= "0100";
+				end case;
+			end case;
+		--}}}
+		when "01" => -- OR
+		--{{{
+			ALU_Op(3) <= '0';
+			ALU_Op(2 downto 0) <= IR(7 downto 5);
+		--}}}
+		when "10" =>
+		--{{{
+			ALU_Op(3) <= '1';
+			ALU_Op(2 downto 0) <= IR(7 downto 5);
+			case IR(7 downto 5) is
+			when "000" =>
+				if IR(4 downto 2) = "110" then
+					-- INC
+					ALU_Op <= "1111";
+				end if;
+			when "001" =>
+				if IR(4 downto 2) = "110" then
+					-- DEC
+					ALU_Op <= "1110";
+				end if;
+			when "100" =>
+				if IR(4 downto 2) = "010" then
+					-- TXA
+					ALU_Op <= "0101";
+				else
+					ALU_Op <= "0100";
+				end if;
+			when others =>
+			end case;
+		--}}}
+		when others =>
+		--{{{
+			case IR(7 downto 5) is
+			when "100" =>
+				ALU_Op <= "0100";
+			when others =>
+				if MCycle = "000" then
+					ALU_Op(3) <= '0';
+					ALU_Op(2 downto 0) <= IR(7 downto 5);
+				else
+					ALU_Op(3) <= '1';
+					ALU_Op(2 downto 0) <= IR(7 downto 5);
+				end if;
+			end case;
+		--}}}
+		end case;
+	end process;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_Pack.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_Pack.vhd
new file mode 100644
index 00000000..e025e1bf
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/T65_Pack.vhd	
@@ -0,0 +1,117 @@
+-- ****
+-- T65(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 Bugfixes by ehenciak added
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- 65xx compatible microprocessor core
+--
+-- Version : 0246
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t65/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T65_Pack is
+
+	constant Flag_C : integer := 0;
+	constant Flag_Z : integer := 1;
+	constant Flag_I : integer := 2;
+	constant Flag_D : integer := 3;
+	constant Flag_B : integer := 4;
+	constant Flag_1 : integer := 5;
+	constant Flag_V : integer := 6;
+	constant Flag_N : integer := 7;
+
+	component T65_MCode
+	port(
+		Mode                    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65816
+		IR                      : in  std_logic_vector(7 downto 0);
+		MCycle                  : in  std_logic_vector(2 downto 0);
+		P                       : in  std_logic_vector(7 downto 0);
+		LCycle                  : out std_logic_vector(2 downto 0);
+		ALU_Op                  : out std_logic_vector(3 downto 0);
+		Set_BusA_To             : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
+		Set_Addr_To             : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
+		Write_Data              : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
+		Jump                    : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
+		BAAdd                   : out std_logic_vector(1 downto 0);     -- None,DB Inc,BA Add,BA Adj
+		BreakAtNA               : out std_logic;
+		ADAdd                   : out std_logic;
+		AddY                    : out std_logic;
+		PCAdd                   : out std_logic;
+		Inc_S                   : out std_logic;
+		Dec_S                   : out std_logic;
+		LDA                     : out std_logic;
+		LDP                     : out std_logic;
+		LDX                     : out std_logic;
+		LDY                     : out std_logic;
+		LDS                     : out std_logic;
+		LDDI                    : out std_logic;
+		LDALU                   : out std_logic;
+		LDAD                    : out std_logic;
+		LDBAL                   : out std_logic;
+		LDBAH                   : out std_logic;
+		SaveP                   : out std_logic;
+		Write                   : out std_logic
+	);
+	end component;
+
+	component T65_ALU
+	port(
+		Mode    : in  std_logic_vector(1 downto 0);      -- "00" => 6502, "01" => 65C02, "10" => 65C816
+		Op      : in  std_logic_vector(3 downto 0);
+		BusA    : in  std_logic_vector(7 downto 0);
+		BusB    : in  std_logic_vector(7 downto 0);
+		P_In    : in  std_logic_vector(7 downto 0);
+		P_Out   : out std_logic_vector(7 downto 0);
+		Q       : out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/addec_prom.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/addec_prom.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/greybox_tmp/cbx_args.txt b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/greybox_tmp/cbx_args.txt
new file mode 100644
index 00000000..deea9283
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/greybox_tmp/cbx_args.txt	
@@ -0,0 +1,16 @@
+ADDRESS_ACLR_A=NONE
+CLOCK_ENABLE_INPUT_A=BYPASS
+CLOCK_ENABLE_OUTPUT_A=BYPASS
+INIT_FILE=../roms/6400-01m2.hex
+INTENDED_DEVICE_FAMILY="Cyclone III"
+NUMWORDS_A=256
+OPERATION_MODE=ROM
+OUTDATA_ACLR_A=NONE
+OUTDATA_REG_A=UNREGISTERED
+WIDTHAD_A=8
+WIDTH_A=4
+WIDTH_BYTEENA_A=1
+DEVICE_FAMILY="Cyclone III"
+address_a
+clock0
+q_a
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/j6_prom.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/j6_prom.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/k6_prom.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/k6_prom.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom1.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom1.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom2.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom2.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom3.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom3.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom4.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/prog_rom4.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/ram1k_dp.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/ram1k_dp.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/sync_prom.qip b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/T65/sync_prom.qip
new file mode 100644
index 00000000..e69de29b
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/audio.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/audio.vhd
new file mode 100644
index 00000000..635efa1f
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/audio.vhd	
@@ -0,0 +1,69 @@
+-- Audio for Super Breakout
+-- This is a very simple circuit, tones are created by gating signals from the vertical scan counter
+-- Original hardware used resistors to mix the tones, here we are mixing them digitally and using a delta-sigma
+-- DAC to produce audio on a single pin
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity audio is 
+port(		
+			Reset_n		: in	std_logic;
+			Tones_n		: in	std_logic;
+			Display		: in	std_logic_vector(3 downto 0);
+			VCount		: in  std_logic_vector(7 downto 0);
+			Audio_PWM	: out std_logic_vector(7 downto 0));
+end audio;
+
+architecture rtl of audio is
+
+signal reset		: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal tone_V4		: std_logic;
+signal tone_V8 	: std_logic;
+signal tone_V16	: std_logic;
+signal tone_V32	: std_logic;
+signal tone_reg 	: std_logic_vector(3 downto 0);
+
+begin
+
+reset <= (not reset_n);
+
+V32 <= Vcount(5);
+V16 <= Vcount(4);
+V8 <= Vcount(3);
+V4 <= Vcount(2);
+
+C4: process(tones_n, V4, V8, V16, V32, display) is
+begin
+	if tones_n <= '0' then
+		tone_reg <= display;
+	end if;
+end process;
+
+tone_V4 <= tone_reg(0) and V4;
+tone_V8 <= tone_reg(1) and V8;
+tone_V16 <= tone_reg(2) and V16;
+tone_V32 <= tone_reg(3) and V32;
+
+Audio_PWM <= tone_V4 & '0' & tone_V8 & '0' & tone_V16 & '0' & tone_V32 & '0';
+
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/build_id.sv b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/build_id.sv
new file mode 100644
index 00000000..1d53a3f2
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/build_id.sv	
@@ -0,0 +1,2 @@
+`define BUILD_DATE "171221"
+`define BUILD_TIME "172231"
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/build_id.tcl b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..be673dac
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.sv"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/cpu_mem.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/cpu_mem.vhd
new file mode 100644
index 00000000..189a884a
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/cpu_mem.vhd	
@@ -0,0 +1,435 @@
+-- CPU, RAM, ROM and address decoder for Atari Super Breakout
+-- 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity CPU_mem is 
+port(	
+			Clk12				: in  std_logic;
+			Clk6				: in  std_logic;
+			Reset_n			: in  std_logic;
+			NMI_n				: in  std_logic;
+			VCount			: in 	std_logic_vector(7 downto 0);
+			HCount			: in  std_logic_vector(8 downto 0);
+			Hsync_n			: in  std_logic;
+			Timer_Reset_n	: in  std_logic;
+			IntAck_n			: in  std_logic;
+			IO_wr				: out std_logic;
+			PHI2_O			: out std_logic;
+			Display			: out	std_logic_vector(7 downto 0);
+			IO_Adr			: out std_logic_vector(9 downto 0);
+			Inputs			: in	std_logic_vector(1 downto 0)
+			);
+end CPU_mem;
+
+architecture rtl of CPU_mem is
+
+signal cpu_clk			: std_logic;
+signal PHI1				: std_logic;
+signal PHI2				: std_logic;
+signal Q5				: std_logic;
+signal Q6				: std_logic;
+signal A7_2				: std_logic;
+signal A7_5				: std_logic;
+signal A7_7				: std_logic;
+
+signal A8_6				: std_logic;
+
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H4				: std_logic;
+
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+
+signal CPU_Reset_n	: std_logic;
+signal IRQ_n			: std_logic;
+signal RW_n				: std_logic;
+signal RnW 				: std_logic;
+signal A					: std_logic_vector(15 downto 0);
+signal Adr				: std_logic_vector(9 downto 0);
+signal cpuDin			: std_logic_vector(7 downto 0);
+signal cpuDout			: std_logic_vector(7 downto 0);
+signal DBUS_n			: std_logic_vector(7 downto 0);
+signal DBUS				: std_logic_vector(7 downto 0);
+
+-- No ROM 0 or 1 on the EPROM based version
+signal ROM2_dout		: std_logic_vector(7 downto 0);
+signal ROM3_dout		: std_logic_vector(7 downto 0);
+signal ROM4_dout		: std_logic_vector(7 downto 0);
+signal ROM_dout		: std_logic_vector(7 downto 0);
+
+signal ROM2				: std_logic;
+signal ROM3				: std_logic;
+signal ROM4				: std_logic;
+signal ROM_ce			: std_logic;
+signal ROM_mux_in		: std_logic_vector(2 downto 0);
+
+signal cpuRAM_dout	: std_logic_vector(7 downto 0);
+signal Vram_dout		: std_logic_vector(7 downto 0);
+signal RAM_addr		: std_logic_vector(9 downto 0) := (others => '0');
+signal Vram_addr		: std_logic_vector(9 downto 0) := (others => '0');
+signal scanbus			: std_logic_vector(9 downto 0) := (others => '0');
+signal RAM_dout		: std_logic_vector(7 downto 0);
+signal RAM_we			: std_logic;
+signal RAM_RW_n 		: std_logic;
+signal RAM_ce_n		: std_logic;
+signal RAM_n			: std_logic; 
+signal WRAM				: std_logic;
+signal WRITE_n			: std_logic;
+
+signal F2_in			: std_logic_vector(3 downto 0);
+signal F2_out			: std_logic_vector(9 downto 0);
+signal D2_in			: std_logic_vector(3 downto 0);
+signal D2_out			: std_logic_vector(9 downto 0);
+signal E8_in			: std_logic_vector(3 downto 0);
+signal E8_out			: std_logic_vector(9 downto 0);
+
+signal Sync1			: std_logic;
+signal Sync1_n			: std_logic;
+signal Sync2_n			: std_logic;
+signal Switch_n		: std_logic;
+signal Display_n		: std_logic;
+signal Addec_bus		: std_logic_vector(7 downto 0);
+
+signal J6_5				: std_logic;
+signal J6_9				: std_logic;
+
+signal D7 				: std_logic; 
+
+
+begin
+
+H8 <= HCount(3);
+H16 <= HCount(4);
+H32 <= HCount(5);
+H64 <= HCount(6);
+H128 <= HCount(7);
+H256 <= HCount(8);
+H256_n <= (not HCount(8));
+
+V8 <= VCount(3);
+V16 <= VCount(4);
+V32 <= VCount(5);
+V64 <= VCount(6);
+V128 <= VCount(7);
+
+
+CPU: entity work.T65
+port map(
+		Enable => '1',
+		Mode => "00",
+		Res_n => CPU_reset_n,
+		Clk => phi1,
+		Rdy => '1',
+		Abort_n => '1',
+		IRQ_n => IRQ_n,
+		NMI_n => NMI_n,
+		SO_n => '1',
+		R_W_n => RW_n,
+		A(15 downto 0) => A,
+		DI => cpuDin,
+		DO => cpuDout
+		);
+		
+DBUS_n <= (not cpuDout); -- Data bus to video RAM is inverted
+Adr(9 downto 7) <= (A(9) or WRAM) & (A(8) or WRAM) & (A(7) or WRAM);
+Adr(6 downto 0) <= A(6 downto 0);
+IO_Adr <= Adr;
+RnW <= (not RW_n);
+
+
+-- CPU Din mux
+cpuDin <= 	ROM_dout when rom_ce = '1' else 
+				(not CPUram_dout) when DISPLAY_n = '0' else -- Remember RAM data is inverted
+				Vcount when Sync1_n = '0' else
+				Inputs & "111111" when SWITCH_n = '0' else
+				D7 & "1111111" when Sync2_n = '0' else
+				x"FF";
+
+
+-- Watchdog timer
+-- need to implement for sake of completeness
+CPU_reset_n <= Reset_n; -- Bypass it for now
+  
+		
+-- CPU clock
+H4 <= Hcount(2);
+CPU_clock: process(clk12, H4, Q5, Q6)
+begin
+	if rising_edge(clk12) then
+		Q5 <= H4;
+		Q6 <= Q5;
+	end if;
+	phi1 <= not (Q5 or Q6); --?
+end process;
+
+PHI2 <= (not PHI1);
+PHI2_O <= PHI2;
+
+-- IRQ, M9
+CPU_IRQ: process(V16, INTACK_n)
+begin
+	if INTACK_n = '1' then -- asynchronous preset
+		if rising_edge(V16) then
+			IRQ_n <= '0';
+		end if;
+	else
+		IRQ_n <= '1';
+	end if;
+end process;
+		
+
+A8_6 <= not(RnW and PHI2 and H4 and WRITE_n);
+A7: process(clk12, A8_6) -- Shift register chain of 4 DFF's clocked by clk12, creates a delayed WRITE_n
+begin
+	if rising_edge(clk12) then
+		A7_2 <= A8_6;
+		A7_5 <= A7_2;
+		A7_7 <= A7_5;
+		WRITE_n <= A7_7;
+	end if;
+end process;
+		
+
+-- Program ROMs
+-- Note that Super Breakout only uses three ROMs, there is no ROM 1
+C1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/033453_c1.hex",
+		widthad_a => 11,
+		width_a => 8)
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom2_dout
+		);
+		
+--C1: entity work.prog_rom2
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom2_dout
+--		);
+
+
+D1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/033454_d1.hex",
+		widthad_a => 11,
+		width_a => 8)
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom3_dout
+		);
+
+--D1: entity work.prog_rom3
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom3_dout
+--		);
+
+
+E1: entity work.sprom
+generic map(
+		init_file => "rtl/roms/033455_e1.hex",
+		widthad_a => 11,
+		width_a => 8)
+port map(
+		clock => clk6,
+		address => A(10) & ADR(9 downto 0),
+		q => rom4_dout
+		);
+		
+--E1: entity work.prog_rom4
+--port map(
+--		clock => clk6,
+--		address => A(10) & ADR(9 downto 0),
+--		q => rom4_dout
+--		);
+
+
+-- ROM data mux
+ROM_mux_in <= (ROM2 & ROM3 & ROM4);
+ROM_mux: process(ROM_mux_in, rom2_dout, rom3_dout, rom4_dout)
+begin
+	ROM_dout <= (others => '0');
+	case ROM_mux_in is
+		when "100" => rom_dout <= rom2_dout;
+		when "010" => rom_dout <= rom3_dout;
+		when "001" => rom_dout <= rom4_dout;
+		when others => null;
+		end case;
+end process;
+  
+-- RAM 
+-- The original hardware multiplexes access to the RAM between the CPU and video hardware depending on the state of
+-- the phi2 clock. In the FPGA it's easier to use dual-ported RAM which is less dependent on precise timing.
+RAM: entity work.dpram
+generic map(
+	widthad_a => 10,
+	width_a => 8)
+port map(
+	clock_a => clk6,
+-- CPU side	
+	address_a => adr(9 downto 0),
+	wren_a => ram_we,
+	data_a => DBUS_n,
+	q_a=> CPUram_dout,
+
+-- Video side
+	clock_b => clk6,
+	address_b => Vram_addr,
+	wren_b => '0',
+	data_b => x"FF",
+	q_b => Vram_dout
+	);
+	
+--RAM: entity work.ram1k_dp
+--port map(
+--	clock => clk6,
+-- CPU side	
+--	address_a => adr(9 downto 0),
+--	wren_a => ram_we,
+--	data_a => DBUS_n,
+--	q_a=> CPUram_dout,
+
+-- Video side
+--	address_b => Vram_addr,
+--	wren_b => '0',
+--	data_b => x"FF",
+--	q_b => Vram_dout
+--	);
+
+-- Data selectors at K2, J2 and H2 are not needed due to the use of dual ported RAM. Here is some glue logic that
+-- drives the video side RAM address
+Vram_addr <= (V128 or H256_n) & (V64 or H256_n) & (V32 or H256_n) & (V16 and H256) & (V8 and H256) & H128 & H64 & H32 & H16 & H8;
+
+-- Real hardware has both WE and CE which are selected by K2 according to the state of the phase 2 clock
+-- Altera block RAM has active high WE, original RAM had active low WE
+ram_we <= (not Write_n) and (not Display_n) and Phi2;
+	
+-- Rising edge of phi2 clock latches inverted output of VRAM data bus. This is not strictly necessary with the dual ported RAM	
+F5: process(phi2)
+begin
+	if rising_edge(phi2) then
+		display <= not Vram_dout;
+	end if;
+end process;
+	
+	
+-- Address decoder
+-- A15 and A14 are not used
+-- E2 PROM - Original circuit uses a 32 byte bipolar PROM in the address decoder, this could easily be replaced with combinational logic
+E2: entity work.sprom
+generic map(
+		init_file => "rtl/roms/006401_e2.hex",
+		widthad_a => 5,
+		width_a => 8)
+port map(
+		clock => clk12,
+	address => A(13 downto 9),
+	q => addec_bus
+	);
+		
+--E2: entity work.addec_prom
+--port map(
+--	clock => clk12,
+--	address => A(13 downto 9),
+--	q => addec_bus
+--	);
+	
+WRAM <= addec_bus(4);
+
+	
+-- Address Decoder -unused decoder states are not explicitly implemented
+F2_in <= addec_bus(0) & addec_bus(1) & addec_bus(2) & addec_bus(3);
+F2: process(F2_in)
+begin
+	case F2_in is
+      when "0010" => F2_out <= "1111111011";
+      when "0011" => F2_out <= "1111110111";
+      when "0100" => F2_out <= "1111101111";
+      when "0101" => F2_out <= "1111011111";
+      when "0110" => F2_out <= "1110111111";
+      when "0111" => F2_out <= "1101111111";
+      when others => F2_out <= "1111111111";
+      end case;
+end process;
+
+ROM2 <= (F2_out(2) nand F2_out(3));
+ROM3 <= (F2_out(4) nand F2_out(5));
+ROM4 <= (F2_out(6) nand F2_out(7));
+ROM_ce <= (ROM2 or ROM3 or ROM4);
+
+
+D2_in <= RnW & addec_bus(5) & addec_bus(6) & addec_bus(7);
+D2: process(clk6, D2_in)
+begin
+	if rising_edge(clk6) then
+		case D2_in is
+		when "0000" => D2_out <= "1111111110";
+		when "0001" => D2_out <= "1111111101";
+		when "0010" => D2_out <= "1111111011";
+		when "0011" => D2_out <= "1111110111";
+		when "1000" => D2_out <= "1011111111";
+		when "1001" => D2_out <= "0111111111";
+		when others => D2_out <= "1111111111";
+		end case;
+	end if;
+end process;	
+
+RAM_n <= D2_out(0);
+SYNC1_n <= D2_out(1);
+SYNC1 <= (not SYNC1_n);
+SWITCH_n <= D2_out(2);
+SYNC2_n <= D2_out(3);
+DISPLAY_n <= (D2_out(0) and D2_out(8));
+IO_wr <= (D2_out(9) or WRITE_n); -- IO_wr comes from P3_8
+
+
+
+J6: process(H128, Hsync_n, Sync1_n, Sync2_n, J6_9)
+begin
+	if Hsync_n = '0' then -- asynchronous clear
+		J6_5 <= '0';
+	elsif rising_edge(H128) then
+		J6_5 <= '1';
+	end if;
+	
+	if rising_edge(Sync1_n) then
+		J6_9 <= J6_5;
+	end if;
+   if sync2_n = '0' then
+		D7 <= J6_9;
+	else
+		D7 <= '1';
+	end if;
+end process;
+	
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/dac.sv b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/dac.sv
new file mode 100644
index 00000000..441e2cf2
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/dac.sv	
@@ -0,0 +1,33 @@
+//
+// PWM DAC
+//
+// MSBI is the highest bit number. NOT amount of bits!
+//
+module dac #(parameter MSBI=8, parameter INV=1'b1)
+(
+   output reg      DACout, //Average Output feeding analog lowpass
+   input  [MSBI:0] DACin,  //DAC input (excess 2**MSBI)
+   input           CLK,
+   input           RESET
+);
+
+reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
+reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
+reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
+reg [MSBI+2:0] DeltaB;     //B input of Delta Adder
+
+always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
+always @(*) DeltaAdder = DACin + DeltaB;
+always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
+
+always @(posedge CLK or posedge RESET) begin
+   if(RESET) begin
+      SigmaLatch <= 1'b1 << (MSBI+1);
+      DACout <= INV;
+   end else begin
+      SigmaLatch <= SigmaAdder;
+      DACout <= SigmaLatch[MSBI+2] ^ INV;
+   end
+end
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/dpram.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/dpram.vhd
new file mode 100644
index 00000000..9ea85a26
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/dpram.vhd	
@@ -0,0 +1,130 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram IS
+	GENERIC
+	(
+		init_file			: string := "";
+		widthad_a			: natural;
+		width_a				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED";
+    outdata_reg_b : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(width_a-1 DOWNTO 0);
+	q_b    <= sub_wire1(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		numwords_b => 2**widthad_a,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		outdata_reg_b => outdata_reg_a,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => widthad_a,
+		widthad_b => widthad_a,
+		width_a => width_a,
+		width_b => width_a,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/hq2x.sv b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/hq2x.sv
new file mode 100644
index 00000000..f17732b6
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/hq2x.sv	
@@ -0,0 +1,454 @@
+//
+//
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+`define BITS_TO_FIT(N) ( \
+     N <=   2 ? 0 : \
+     N <=   4 ? 1 : \
+     N <=   8 ? 2 : \
+     N <=  16 ? 3 : \
+     N <=  32 ? 4 : \
+     N <=  64 ? 5 : \
+     N <= 128 ? 6 : \
+     N <= 256 ? 7 : \
+     N <= 512 ? 8 : \
+     N <=1024 ? 9 : 10 )
+
+module hq2x_in #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input            rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input            wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+	wire [DWIDTH:0] out[2];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+endmodule
+
+
+module hq2x_out #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input      [1:0] rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input      [1:0] wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
+	wire  [DWIDTH:0] out[4];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
+endmodule
+
+
+module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
+(
+	input	            clock,
+	input	 [DWIDTH:0] data,
+	input	 [AWIDTH:0] rdaddress,
+	input	 [AWIDTH:0] wraddress,
+	input	            wren,
+	output [DWIDTH:0] q
+);
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b(q),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({(DWIDTH+1){1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = NUMWORDS,
+		altsyncram_component.numwords_b = NUMWORDS,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = AWIDTH+1,
+		altsyncram_component.widthad_b = AWIDTH+1,
+		altsyncram_component.width_a = DWIDTH+1,
+		altsyncram_component.width_b = DWIDTH+1,
+		altsyncram_component.width_byteena_a = 1;
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DiffCheck
+(
+	input [17:0] rgb1,
+	input [17:0] rgb2,
+	output result
+);
+
+	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
+	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
+	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
+	wire [6:0] t = $signed(r) + $signed(b);
+	wire [6:0] gx = {g[5], g};
+	wire [7:0] y = $signed(t) + $signed(gx);
+	wire [6:0] u = $signed(r) - $signed(b);
+	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
+
+	// if y is inside (-24..24)
+	wire y_inside = (y < 8'h18 || y >= 8'he8);
+
+	// if u is inside (-4, 4)
+	wire u_inside = (u < 7'h4 || u >= 7'h7c);
+
+	// if v is inside (-6, 6)
+	wire v_inside = (v < 8'h6 || v >= 8'hfA);
+	assign result = !(y_inside && u_inside && v_inside);
+endmodule
+
+module InnerBlend
+(
+	input  [8:0] Op,
+	input  [5:0] A,
+	input  [5:0] B,
+	input  [5:0] C,
+	output [5:0] O
+);
+
+	function  [8:0] mul6x3;
+		input  [5:0] op1;
+		input  [2:0] op2;
+	begin
+		mul6x3 = 9'd0;
+		if(op2[0]) mul6x3 = mul6x3 + op1;
+		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
+		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
+	end
+	endfunction
+
+	wire OpOnes = Op[4];
+	wire [8:0] Amul = mul6x3(A, Op[7:5]);
+	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
+	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
+	wire [8:0] At =  Amul;
+	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
+	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
+	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
+	assign O = Op[8] ? A : Res[9:4];
+endmodule
+
+module Blend
+(
+	input   [5:0] rule,
+	input         disable_hq2x,
+	input  [17:0] E,
+	input  [17:0] A,
+	input  [17:0] B,
+	input  [17:0] D,
+	input  [17:0] F,
+	input  [17:0] H,
+	output [17:0] Result
+);
+
+	reg [1:0] input_ctrl;
+	reg [8:0] op;
+	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
+	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
+	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
+	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
+	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
+	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
+	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
+	localparam AB = 2'b00;
+	localparam AD = 2'b01;
+	localparam DB = 2'b10;
+	localparam BD = 2'b11;
+	wire is_diff;
+	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
+
+	always @* begin
+		case({!is_diff, rule[5:2]})
+			1,17:  {op, input_ctrl} = {BLEND1, AB};
+			2,18:  {op, input_ctrl} = {BLEND1, DB};
+			3,19:  {op, input_ctrl} = {BLEND1, BD};
+			4,20:  {op, input_ctrl} = {BLEND2, DB};
+			5,21:  {op, input_ctrl} = {BLEND2, AB};
+			6,22:  {op, input_ctrl} = {BLEND2, AD};
+
+			8: {op, input_ctrl} = {BLEND0, 2'bxx};
+			9: {op, input_ctrl} = {BLEND0, 2'bxx};
+			10: {op, input_ctrl} = {BLEND0, 2'bxx};
+			11: {op, input_ctrl} = {BLEND1, AB};
+			12: {op, input_ctrl} = {BLEND1, AB};
+			13: {op, input_ctrl} = {BLEND1, AB};
+			14: {op, input_ctrl} = {BLEND1, DB};
+			15: {op, input_ctrl} = {BLEND1, BD};
+
+			24: {op, input_ctrl} = {BLEND2, DB};
+			25: {op, input_ctrl} = {BLEND5, DB};
+			26: {op, input_ctrl} = {BLEND6, DB};
+			27: {op, input_ctrl} = {BLEND2, DB};
+			28: {op, input_ctrl} = {BLEND4, DB};
+			29: {op, input_ctrl} = {BLEND5, DB};
+			30: {op, input_ctrl} = {BLEND3, BD};
+			31: {op, input_ctrl} = {BLEND3, DB};
+			default: {op, input_ctrl} = 11'bx;
+		endcase
+
+		// Setting op[8] effectively disables HQ2X because blend will always return E.
+		if (disable_hq2x) op[8] = 1;
+	end
+
+	// Generate inputs to the inner blender. Valid combinations.
+	// 00: E A B
+	// 01: E A D 
+	// 10: E D B
+	// 11: E B D
+	wire [17:0] Input1 = E;
+	wire [17:0] Input2 = !input_ctrl[1] ? A :
+                        !input_ctrl[0] ? D : B;
+
+	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
+	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
+	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
+	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
+endmodule
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	input               clk,
+	input               ce_x4,
+	input    [DWIDTH:0] inputpixel,
+	input               mono,
+	input               disable_hq2x,
+	input               reset_frame,
+	input               reset_line,
+	input         [1:0] read_y,
+	input  [AWIDTH+1:0] read_x,
+	output   [DWIDTH:0] outpixel
+);
+
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+localparam DWIDTH = HALF_DEPTH ? 8 : 17;
+
+wire [5:0] hqTable[256] = '{
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
+};
+
+reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
+reg [17:0] A, B, D, F, G, H;
+reg  [7:0] pattern, nextpatt;
+reg  [1:0] i;
+reg  [7:0] y;
+
+wire curbuf = y[0];
+reg  prevbuf = 0;
+wire iobuf = !curbuf;
+
+wire diff0, diff1;
+DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
+DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
+
+wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
+
+wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
+wire [17:0] blend_result;
+Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
+
+reg             Curr2_addr1;
+reg  [AWIDTH:0] Curr2_addr2;
+wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
+wire [DWIDTH:0] Curr2tmp;
+
+reg  [AWIDTH:0] wrin_addr2;
+reg  [DWIDTH:0] wrpix;
+reg             wrin_en;
+
+function [17:0] h2rgb;
+	input  [8:0] v;
+begin
+	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
+end
+endfunction
+
+function  [8:0] rgb2h;
+	input [17:0] v;
+begin
+	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
+end
+endfunction
+
+hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
+(
+	.clk(clk),
+
+	.rdaddr(Curr2_addr2),
+	.rdbuf(Curr2_addr1),
+	.q(Curr2tmp),
+
+	.wraddr(wrin_addr2),
+	.wrbuf(iobuf),
+	.data(wrpix),
+	.wren(wrin_en)
+);
+
+reg         [1:0] wrout_addr1;
+reg  [AWIDTH+1:0] wrout_addr2;
+reg               wrout_en;
+reg    [DWIDTH:0] wrdata;
+
+hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
+(
+	.clk(clk),
+
+	.rdaddr(read_x),
+	.rdbuf(read_y),
+	.q(outpixel),
+
+	.wraddr(wrout_addr2),
+	.wrbuf(wrout_addr1),
+	.data(wrdata),
+	.wren(wrout_en)
+);
+
+always @(posedge clk) begin
+	reg [AWIDTH:0] offs;
+	reg old_reset_line;
+	reg old_reset_frame;
+
+	wrout_en <= 0;
+	wrin_en  <= 0;
+
+	if(ce_x4) begin
+
+		pattern <= new_pattern;
+
+		if(~&offs) begin
+			if (i == 0) begin
+				Curr2_addr1 <= prevbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 1) begin
+				Prev2 <= Curr2;
+				Curr2_addr1 <= curbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 2) begin
+				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
+				wrpix <= inputpixel;
+				wrin_addr2 <= offs;
+				wrin_en <= 1;
+			end
+			if (i == 3) begin
+				offs <= offs + 1'd1;
+			end
+
+			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
+			else           wrdata <= blend_result;
+
+			wrout_addr1 <= {curbuf, i[1]};
+			wrout_addr2 <= {offs, i[1]^i[0]};
+			wrout_en    <= 1;
+		end
+
+		if(i==3) begin
+			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
+			{A, G} <= {Prev0, Next0};
+			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
+			{Prev0, Prev1} <= {Prev1, Prev2};
+			{Curr0, Curr1} <= {Curr1, Curr2};
+			{Next0, Next1} <= {Next1, Next2};
+		end else begin
+			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
+			{B, F, H, D} <= {F, H, D, B};
+		end
+
+		i <= i + 1'b1;
+		if(old_reset_line && ~reset_line) begin
+			old_reset_frame <= reset_frame;
+			offs <= 0;
+			i <= 0;
+			y <= y + 1'd1;
+			prevbuf <= curbuf;
+			if(old_reset_frame & ~reset_frame) begin
+				y <= 0;
+				prevbuf <= 0;
+			end
+		end
+
+		old_reset_line  <= reset_line;
+	end
+end
+
+endmodule  // Hq2x
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/keyboard.sv b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/keyboard.sv
new file mode 100644
index 00000000..01625319
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/keyboard.sv	
@@ -0,0 +1,79 @@
+
+
+module keyboard
+(
+	input  clk,
+	input  reset,
+	input  ps2_kbd_clk,
+	input  ps2_kbd_data,
+
+	output reg[7:0] joystick
+);
+
+reg [11:0] shift_reg = 12'hFFF;
+wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
+wire [7:0] kcode = kdata[9:2];
+reg        release_btn = 0;
+
+reg  [7:0] code;
+reg        input_strobe = 0;
+
+always @(negedge clk) begin
+	reg old_reset = 0;
+
+	old_reset <= reset;
+
+	if(~old_reset & reset)begin
+		joystick <= 0;
+	end
+
+	if(input_strobe) begin
+		case(code)
+			'h75: joystick[3] <= ~release_btn; // arrow up
+			'h72: joystick[2] <= ~release_btn; // arrow down
+			'h6B: joystick[1] <= ~release_btn; // arrow left
+			'h74: joystick[0] <= ~release_btn; // arrow right
+
+			'h29: joystick[4] <= ~release_btn; // Space
+			'h05: joystick[5] <= ~release_btn; // F1
+			'h06: joystick[6] <= ~release_btn; // F2
+			'h76: joystick[7] <= ~release_btn; // Escape
+		endcase
+	end
+end
+
+always @(posedge clk) begin
+	reg [3:0] prev_clk  = 0;
+	reg       old_reset = 0;
+	reg       action = 0;
+
+	old_reset <= reset;
+	input_strobe <= 0;
+
+	if(~old_reset & reset)begin
+		prev_clk  <= 0;
+		shift_reg <= 12'hFFF;
+	end else begin
+		prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
+		if(prev_clk == 1) begin
+			if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
+				shift_reg <= 12'hFFF;
+				if (kcode == 8'he0) ;
+				// Extended key code follows
+				else if (kcode == 8'hf0)
+					// Release code follows
+					action <= 1;
+				else begin
+					// Cancel extended/release flags for next time
+					action <= 0;
+					release_btn <= action;
+					code <= kcode;
+					input_strobe <= 1;
+				end
+			end else begin
+				shift_reg <= kdata;
+			end
+		end
+	end
+end
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/mist_io.sv b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/mist_io.sv
new file mode 100644
index 00000000..dcc7ecde
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/mist_io.sv	
@@ -0,0 +1,491 @@
+//
+// mist_io.v
+//
+// mist_io for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+//
+// Use buffer to access SD card. It's time-critical part.
+// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
+//                                                           (Sorgelig)
+//
+// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
+// clk_ps2 = clk_sys/(PS2DIV*2)
+//
+
+module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
+(
+
+	// parameter STRLEN and the actual length of conf_str have to match
+	input [(8*STRLEN)-1:0] conf_str,
+
+	// Global clock. It should be around 100MHz (higher is better).
+	input             clk_sys,
+
+	// Global SPI clock from ARM. 24MHz
+	input             SPI_SCK,
+
+	input             CONF_DATA0,
+	input             SPI_SS2,
+	output            SPI_DO,
+	input             SPI_DI,
+
+	output reg  [7:0] joystick_0,
+	output reg  [7:0] joystick_1,
+	output reg [15:0] joystick_analog_0,
+	output reg [15:0] joystick_analog_1,
+	output      [1:0] buttons,
+	output      [1:0] switches,
+	output            scandoubler_disable,
+	output            ypbpr,
+
+	output reg [31:0] status,
+
+	// SD config
+	input             sd_conf,
+	input             sd_sdhc,
+	output            img_mounted, // signaling that new image has been mounted
+	output reg [31:0] img_size,    // size of image in bytes
+
+	// SD block level access
+	input      [31:0] sd_lba,
+	input             sd_rd,
+	input             sd_wr,
+	output reg        sd_ack,
+	output reg        sd_ack_conf,
+
+	// SD byte level access. Signals for 2-PORT altsyncram.
+	output reg  [8:0] sd_buff_addr,
+	output reg  [7:0] sd_buff_dout,
+	input       [7:0] sd_buff_din,
+	output reg        sd_buff_wr,
+
+	// ps2 keyboard emulation
+	output            ps2_kbd_clk,
+	output reg        ps2_kbd_data,
+	output            ps2_mouse_clk,
+	output reg        ps2_mouse_data,
+	input             ps2_caps_led,
+
+	// ARM -> FPGA download
+	output reg        ioctl_download = 0, // signal indicating an active download
+	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output            ioctl_wr,
+	output reg [23:0] ioctl_addr,
+	output reg  [7:0] ioctl_dout
+);
+
+reg [7:0] b_data;
+reg [6:0] sbuf;
+reg [7:0] cmd;
+reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
+reg [9:0] byte_cnt;   // counts bytes
+reg [7:0] but_sw;
+reg [2:0] stick_idx;
+
+reg    mount_strobe = 0;
+assign img_mounted  = mount_strobe;
+
+assign buttons = but_sw[1:0];
+assign switches = but_sw[3:2];
+assign scandoubler_disable = but_sw[4];
+assign ypbpr = but_sw[5];
+
+wire [7:0] spi_dout = { sbuf, SPI_DI};
+
+// this variant of user_io is for 8 bit cores (type == a4) only
+wire [7:0] core_type = 8'ha4;
+
+// command byte read by the io controller
+wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
+
+reg spi_do;
+assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
+
+wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
+
+// drive MISO only when transmitting core id
+always@(negedge SPI_SCK) begin
+	if(!CONF_DATA0) begin
+		// first byte returned is always core type, further bytes are 
+		// command dependent
+      if(byte_cnt == 0) begin
+		  spi_do <= core_type[~bit_cnt];
+
+		end else begin
+			case(cmd)
+				// reading config string
+				8'h14: begin
+					// returning a byte from string
+						if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
+							else spi_do <= 0;
+					end
+
+				// reading sd card status
+				8'h16: begin
+						if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
+						else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
+						else spi_do <= 0;
+					end
+
+				// reading sd card write data
+				8'h18:
+						spi_do <= b_data[~bit_cnt];
+
+				// reading keyboard LED status
+				8'h1f:
+						spi_do <= kbd_led[~bit_cnt];
+
+				default:
+						spi_do <= 0;
+			endcase
+		end
+   end
+end
+
+reg b_wr2,b_wr3;
+always @(negedge clk_sys) begin
+	b_wr3      <= b_wr2;
+	sd_buff_wr <= b_wr3;
+end
+
+// SPI receiver
+always@(posedge SPI_SCK or posedge CONF_DATA0) begin
+
+	if(CONF_DATA0) begin
+		b_wr2 <= 0;
+	   bit_cnt <= 0;
+	   byte_cnt <= 0;
+		sd_ack <= 0;
+		sd_ack_conf <= 0;
+	end else begin
+		b_wr2 <= 0;
+
+		sbuf <= spi_dout[6:0];
+		bit_cnt <= bit_cnt + 1'd1;
+		if(bit_cnt == 5) begin
+			if (byte_cnt == 0) sd_buff_addr <= 0;
+			if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
+			if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
+		end
+
+		// finished reading command byte
+      if(bit_cnt == 7) begin
+			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
+			if(byte_cnt == 0) begin
+				cmd <= spi_dout;
+
+				if(spi_dout == 8'h19) begin
+					sd_ack_conf  <= 1;
+					sd_buff_addr <= 0;
+				end
+				if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
+					sd_ack       <= 1;
+					sd_buff_addr <= 0;
+				end
+				if(spi_dout == 8'h18) b_data <= sd_buff_din;
+
+				mount_strobe <= 0;
+
+			end else begin
+			
+				case(cmd)
+					// buttons and switches
+					8'h01: but_sw <= spi_dout; 
+					8'h02: joystick_0 <= spi_dout;
+					8'h03: joystick_1 <= spi_dout;
+
+					// store incoming ps2 mouse bytes 
+					8'h04: begin
+							ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; 
+							ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
+						end
+
+					// store incoming ps2 keyboard bytes 
+					8'h05: begin
+							ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; 
+							ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
+						end
+				
+					8'h15: status[7:0] <= spi_dout;
+				
+					// send SD config IO -> FPGA
+					// flag that download begins
+					// sd card knows data is config if sd_dout_strobe is asserted
+					// with sd_ack still being inactive (low)
+					8'h19,
+					// send sector IO -> FPGA
+					// flag that download begins
+					8'h17: begin
+							sd_buff_dout <= spi_dout;
+							b_wr2 <= 1;
+						end
+
+					8'h18: b_data <= sd_buff_din;
+
+					// joystick analog
+					8'h1a: begin
+							// first byte is joystick index
+							if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
+							else if(byte_cnt == 2) begin
+								// second byte is x axis
+								if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
+									else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
+							end else if(byte_cnt == 3) begin
+								// third byte is y axis
+								if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
+									else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
+							end
+						end
+
+					// notify image selection
+					8'h1c: mount_strobe <= 1;
+
+					// send image info
+					8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
+
+					// status, 32bit version
+					8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
+					default: ;
+				endcase
+			end
+		end
+	end
+end
+
+
+///////////////////////////////   PS2   ///////////////////////////////
+// 8 byte fifos to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
+
+reg clk_ps2;
+always @(negedge clk_sys) begin
+	integer cnt;
+	cnt <= cnt + 1'd1;
+	if(cnt == PS2DIV) begin
+		clk_ps2 <= ~clk_ps2;
+		cnt <= 0;
+	end
+end
+
+// keyboard
+reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_kbd_tx_state;
+reg [7:0] ps2_kbd_tx_byte;
+reg ps2_kbd_parity;
+
+assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_kbd_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_kbd_r_inc <= 0;
+
+		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_kbd_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
+				// load tx register from fifo
+				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
+				ps2_kbd_r_inc <= 1;
+
+				// reset parity
+				ps2_kbd_parity <= 1;
+
+				// start transmitter
+				ps2_kbd_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_kbd_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
+				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
+				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
+				if(ps2_kbd_tx_byte[0]) 
+					ps2_kbd_parity <= !ps2_kbd_parity;
+			end
+
+			// transmission of parity
+			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
+
+			// transmission of stop bit
+			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
+
+			// advance state machine
+			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
+				else ps2_kbd_tx_state <= 0;
+		end
+	end
+end
+
+// mouse
+reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_mouse_tx_state;
+reg [7:0] ps2_mouse_tx_byte;
+reg ps2_mouse_parity;
+
+assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_mouse_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_mouse_r_inc <= 0;
+
+		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_mouse_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
+				// load tx register from fifo
+				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
+				ps2_mouse_r_inc <= 1;
+
+				// reset parity
+				ps2_mouse_parity <= 1;
+
+				// start transmitter
+				ps2_mouse_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_mouse_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
+				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
+				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
+				if(ps2_mouse_tx_byte[0]) 
+					ps2_mouse_parity <= !ps2_mouse_parity;
+			end
+
+			// transmission of parity
+			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
+
+			// transmission of stop bit
+			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
+
+			// advance state machine
+			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
+				else ps2_mouse_tx_state <= 0;
+		end
+	end
+end
+
+
+///////////////////////////////   DOWNLOADING   ///////////////////////////////
+
+reg  [7:0] data_w;
+reg [23:0] addr_w;
+reg        rclk   = 0;
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+
+// data_io has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS2) begin
+	reg  [6:0] sbuf;
+	reg  [7:0] cmd;
+	reg  [4:0] cnt;
+	reg [23:0] addr;
+
+	if(SPI_SS2) cnt <= 0;
+	else begin
+		rclk <= 0;
+
+		// don't shift in last bit. It is evaluated directly
+		// when writing to ram
+		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
+
+		// increase target address after write
+		if(rclk) addr <= addr + 1'd1;
+
+		// count 0-7 8-15 8-15 ... 
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		// finished command byte
+      if(cnt == 7) cmd <= {sbuf, SPI_DI};
+
+		// prepare/end transmission
+		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
+			// prepare 
+			if(SPI_DI) begin
+				addr <= 0;
+				ioctl_download <= 1; 
+			end else begin
+				addr_w <= addr;
+				ioctl_download <= 0;
+			end
+		end
+
+		// command 0x54: UIO_FILE_TX
+		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
+			addr_w <= addr;
+			data_w <= {sbuf, SPI_DI};
+			rclk <= 1;
+		end
+
+      // expose file (menu) index
+      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
+	end
+end
+
+assign ioctl_wr = |ioctl_wrd;
+reg [1:0] ioctl_wrd;
+
+always@(negedge clk_sys) begin
+	reg        rclkD, rclkD2;
+
+	rclkD    <= rclk;
+	rclkD2   <= rclkD;
+	ioctl_wrd<= {ioctl_wrd[0],1'b0};
+
+	if(rclkD & ~rclkD2) begin
+		ioctl_dout <= data_w;
+		ioctl_addr <= addr_w;
+		ioctl_wrd  <= 2'b11;
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/motion.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/motion.vhd
new file mode 100644
index 00000000..bb2e85ac
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/motion.vhd	
@@ -0,0 +1,290 @@
+-- Motion object generation circuitry for Atari Super Breakout
+-- This generates the motion objects, three balls in the case of Super Breakout
+-- 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity motion is 
+port(		
+			Clk6			: in  std_logic; -- 6MHz on schematic
+			Phi2			: in  std_logic;
+			Display		: in  std_logic_vector(7 downto 0);
+			H256_s		: in  std_logic; -- 256H* on schematic
+			VCount		: in  std_logic_vector(7 downto 0);
+			HCount		: in  std_logic_vector(8 downto 0);
+			Tones_n		: out std_logic; -- Used by sound circuit, comes from decoder here
+			Ball1_n  	: out std_logic; 
+			Ball2_n  	: out std_logic; -- Ball video outputs, summed by video output circuit
+			Ball3_n  	: out std_logic
+			);
+end motion;
+
+architecture rtl of motion is
+
+signal A			: std_logic;
+signal B			: std_logic;
+signal C			: std_logic;
+signal D			: std_logic;
+signal E			: std_logic;
+signal F			: std_logic;
+signal G			: std_logic;
+signal H			: std_logic;
+signal I			: std_logic;
+signal J 		: std_logic;
+signal K			: std_logic;
+signal L			: std_logic;
+signal M			: std_logic;
+signal N			: std_logic;
+
+signal phi0		: std_logic;
+
+signal LDH1_n	: std_logic;
+signal LDH2_n	: std_logic;
+signal LDH3_n	: std_logic;
+
+signal LDV1A_n		: std_logic;
+signal LDV2A_n		: std_logic;
+signal LDV3A_n		: std_logic;
+
+signal Ball1_Inh	: std_logic;
+signal Ball2_Inh	: std_logic;
+signal Ball3_Inh	: std_logic;
+
+signal LM4_sum		: std_logic_vector(7 downto 0) := (others => '0');
+
+signal N4_8			: std_logic;
+
+signal H256_n		: std_logic;
+signal H256			: std_logic;
+signal H64 			: std_logic;
+signal H32			: std_logic;
+signal H16			: std_logic;
+signal H8			: std_logic;
+signal H4			: std_logic;
+
+signal L5_reg		: std_logic_vector(4 downto 0) := (others => '0');
+
+signal J8_3			: std_logic;
+signal J8_6			: std_logic;
+
+signal K8_in		: std_logic_vector(3 downto 0) := (others => '0');
+signal K8_out		: std_logic_vector(9 downto 0) := (others => '0');
+signal D7_in		: std_logic_vector(3 downto 0) := (others => '0');
+signal D7_out		: std_logic_vector(9 downto 0) := (others => '0');
+
+signal Ball1_Hpos	: std_logic_vector(7 downto 0) := (others => '0');
+signal Ball2_Hpos	: std_logic_vector(7 downto 0) := (others => '0');
+signal Ball3_Hpos	: std_logic_vector(7 downto 0) := (others => '0');
+
+signal Ball1_reg	: std_logic_vector(7 downto 0) := (others => '0');
+signal Ball2_reg	: std_logic_vector(7 downto 0) := (others => '0');
+signal Ball3_reg 	: std_logic_vector(7 downto 0) := (others => '0');
+
+signal Vid			: std_logic_vector(7 downto 0) := (others => '0');
+
+
+begin
+phi0 <= phi2;
+
+H4 <= Hcount(2);
+H8 <= Hcount(3);
+H16 <= Hcount(4);
+H32 <= Hcount(5);
+H64 <= Hcount(6);
+H256 <= Hcount(8);
+H256_n <= not(Hcount(8));
+
+LM4_sum <= Display + VCount; -- Binary adder and wide NAND gate forms the motion object comparator
+N4_8 <= not(LM4_sum(7) and LM4_sum(6) and LM4_sum(5) and LM4_sum(4) and H256_n and H64 and H8);
+
+-- D type latches in L5 and M9 clocked by phi2
+L5: process(phi2, N4_8, LM4_sum(3 downto 0))
+begin
+	if rising_edge(phi2) then
+		L5_reg <= N4_8 & LM4_sum(3 downto 0);
+	end if;
+end process;
+	
+K6: entity work.sprom
+generic map(
+		init_file => "rtl/roms/033282_k6.hex",
+		widthad_a => 5,
+		width_a => 8)
+port map(
+		clock => clk6,
+		address => Display(7) & L5_reg(3 downto 0),
+		q => Vid
+		);
+		
+--K6: entity work.k6_prom
+--port map(
+--	clock => clk6,
+--	address => Display(7) & L5_reg(3 downto 0),
+--	q => Vid
+--	);
+	
+
+J8_3 <= (H4 or L5_reg(4));
+
+J8_6 <= (H256 or H64 or H4);
+
+-- Decoder code could be cleaned up a bit
+K8_in <= J8_3 & H32 & H16 & not phi0;
+K8: process(clk6, K8_in)
+begin
+	if rising_edge(clk6) then
+		case K8_in is
+			when "0000" => K8_out <= "1111111110";
+			when "0001" => K8_out <= "1111111101"; 
+			when "0010" => K8_out <= "1111111011"; 
+			when "0011" => K8_out <= "1111110111";
+			when "0100" => K8_out <= "1111101111"; 
+			when "0101" => K8_out <= "1111011111";
+			when "0110" => K8_out <= "1110111111"; 
+			when "0111" => K8_out <= "1101111111";
+			when "1000" => K8_out <= "1011111111";
+			when "1001" => K8_out <= "0111111111";
+			when others => K8_out <= "1111111111";
+			end case;
+		LDV3A_n <= K8_out(6);
+		LDV2A_n <= K8_out(4);
+		LDV1A_n <= K8_out(2);
+		end if;
+end process;
+
+
+D7_in <= J8_6 & H32 & H16 & H8;
+D7: process(D7_in)
+begin
+	case D7_in is
+		when "0000" => D7_out <= "1111111110";
+		when "0001" => D7_out <= "1111111101";
+		when "0010" => D7_out <= "1111111011";
+      when "0011" => D7_out <= "1111110111";
+      when "0100" => D7_out <= "1111101111";
+      when "0101" => D7_out <= "1111011111";
+      when "0110" => D7_out <= "1110111111";
+      when "0111" => D7_out <= "1101111111";
+      when "1000" => D7_out <= "1011111111";
+      when "1001" => D7_out <= "0111111111";
+      when others => D7_out <= "1111111111";
+      end case;
+end process;
+	
+Tones_n <= D7_out(2);
+LDH1_n <= D7_out(1);
+LDH2_n <= D7_out(3); 
+LDH3_n <= D7_out(5);
+
+
+-- Ball 1 Horizontal ball position counter
+-- This combines two 74LS163s at locations R5 and R6 on the PCB 
+R5_6: process(clk6, H256_s, LDH1_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH1_n = '0' then -- preload the counter
+			Ball1_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Ball1_Hpos <= Ball1_Hpos + '1';
+		end if;
+	end if;
+end process;
+D <= Ball1_Hpos(7);
+C <= Ball1_Hpos(6);
+B <= Ball1_Hpos(5);
+A <= Ball1_Hpos(4);
+Ball1_Inh <= not(A and B and C and D);
+
+-- Ball 1 video shift register
+N7: process(clk6, Ball1_Inh, LDV1A_n, Vid)
+begin
+	if LDV1A_n = '0' then
+			Ball1_reg <= Vid; -- Preload the register with a line from the motion object PROM
+	elsif rising_edge(clk6) then
+		if Ball1_Inh = '0' then
+			Ball1_reg <= '0' & Ball1_reg(7 downto 1);
+		end if;
+	end if;
+end process;
+Ball1_n <= not Ball1_reg(0);
+
+
+-- Ball 2 Horizontal ball position counter
+-- This combines two 74LS163s at locations P5 and P6 on the PCB 
+P5_6: process(clk6, H256_s, LDH2_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH2_n = '0' then -- preload the counter
+			Ball2_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Ball2_Hpos <= Ball2_Hpos + '1';
+		end if;
+	end if;
+end process;
+J <= Ball2_Hpos(7);
+H <= Ball2_Hpos(6);
+F <= Ball2_Hpos(5);
+E <= Ball2_Hpos(4);
+Ball2_Inh <= not(E and F and H and J);
+
+-- Ball 2 video shift register
+L7: process(clk6, Ball2_Inh, LDV2A_n, Vid)
+begin
+	if LDV2A_n = '0' then
+			Ball2_reg <= Vid; -- Preload the register with a line from the motion object PROM
+	elsif rising_edge(clk6) then
+		if Ball2_Inh = '0' then
+			Ball2_reg <= '0' & Ball2_reg(7 downto 1);
+		end if;
+	end if;
+end process;
+Ball2_n <= not Ball2_reg(0);
+
+
+-- Ball 3 Horizontal ball position counter
+-- This combines two 74LS163s at locations N5 and N6 on the PCB 
+N5_6: process(clk6, H256_s, LDH3_n, Display)
+begin
+	if rising_edge(clk6) then
+		if LDH3_n = '0' then -- preload the counter
+			Ball3_Hpos <= Display;
+		elsif H256_s = '1' then -- increment the counter
+			Ball3_Hpos <= Ball3_Hpos + '1';
+		end if;
+	end if;
+end process;
+N <= Ball3_Hpos(7);
+M <= Ball3_Hpos(6);
+L <= Ball3_Hpos(5);
+K <= Ball3_Hpos(4);
+Ball3_Inh <= not(K and L and M and N);
+
+-- Ball 3 video shift register
+J7: process(clk6, Ball3_Inh, LDV3A_n, Vid)
+begin
+	if LDV3A_n = '0' then
+			Ball3_reg <= Vid; -- Preload the register with a line from the motion object PROM
+	elsif rising_edge(clk6) then
+		if Ball3_Inh = '0' then
+			Ball3_reg <= '0' & Ball3_reg(7 downto 1);
+		end if;
+	end if;
+end process;
+Ball3_n <= not Ball3_reg(0);
+
+end rtl;
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/osd.sv b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/osd.sv
new file mode 100644
index 00000000..c62c10af
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/osd.sv	
@@ -0,0 +1,179 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd (
+	// OSDs pixel clock, should be synchronous to cores pixel clock to
+	// avoid jitter.
+	input        clk_sys,
+
+	// SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// VGA signals coming from core
+	input  [5:0] R_in,
+	input  [5:0] G_in,
+	input  [5:0] B_in,
+	input        HSync,
+	input        VSync,
+	
+	// VGA signals going to video connector
+	output [5:0] R_out,
+	output [5:0] G_out,
+	output [5:0] B_out
+);
+
+parameter OSD_X_OFFSET = 10'd0;
+parameter OSD_Y_OFFSET = 10'd0;
+parameter OSD_COLOR    = 3'd0;
+
+localparam OSD_WIDTH   = 10'd256;
+localparam OSD_HEIGHT  = 10'd128;
+
+// *********************************************************************************
+// spi client
+// *********************************************************************************
+
+// this core supports only the display related OSD commands
+// of the minimig
+reg        osd_enable;
+(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
+
+// the OSD has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS3) begin
+	reg  [4:0] cnt;
+	reg [10:0] bcnt;
+	reg  [7:0] sbuf;
+	reg  [7:0] cmd;
+
+	if(SPI_SS3) begin
+		cnt  <= 0;
+		bcnt <= 0;
+	end else begin
+		sbuf <= {sbuf[6:0], SPI_DI};
+
+		// 0:7 is command, rest payload
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		if(cnt == 7) begin
+			cmd <= {sbuf[6:0], SPI_DI};
+      
+			// lower three command bits are line address
+			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
+
+			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
+		end
+
+		// command 0x20: OSDCMDWRITE
+		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
+			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
+			bcnt <= bcnt + 1'd1;
+		end
+	end
+end
+
+// *********************************************************************************
+// video timing and sync polarity anaylsis
+// *********************************************************************************
+
+// horizontal counter
+reg  [9:0] h_cnt;
+reg  [9:0] hs_low, hs_high;
+wire       hs_pol = hs_high < hs_low;
+wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
+
+// vertical counter
+reg  [9:0] v_cnt;
+reg  [9:0] vs_low, vs_high;
+wire       vs_pol = vs_high < vs_low;
+wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
+
+wire doublescan = (dsp_height>350); 
+
+reg ce_pix;
+always @(negedge clk_sys) begin
+	integer cnt = 0;
+	integer pixsz, pixcnt;
+	reg hs;
+
+	cnt <= cnt + 1;
+	hs <= HSync;
+
+	pixcnt <= pixcnt + 1;
+	if(pixcnt == pixsz) pixcnt <= 0;
+	ce_pix <= !pixcnt;
+
+	if(hs && ~HSync) begin
+		cnt    <= 0;
+		pixsz  <= (cnt >> 9) - 1;
+		pixcnt <= 0;
+		ce_pix <= 1;
+	end
+end
+
+always @(posedge clk_sys) begin
+	reg hsD, hsD2;
+	reg vsD, vsD2;
+
+	if(ce_pix) begin
+		// bring hsync into local clock domain
+		hsD <= HSync;
+		hsD2 <= hsD;
+
+		// falling edge of HSync
+		if(!hsD && hsD2) begin	
+			h_cnt <= 0;
+			hs_high <= h_cnt;
+		end
+
+		// rising edge of HSync
+		else if(hsD && !hsD2) begin	
+			h_cnt <= 0;
+			hs_low <= h_cnt;
+			v_cnt <= v_cnt + 1'd1;
+		end else begin
+			h_cnt <= h_cnt + 1'd1;
+		end
+
+		vsD <= VSync;
+		vsD2 <= vsD;
+
+		// falling edge of VSync
+		if(!vsD && vsD2) begin	
+			v_cnt <= 0;
+			vs_high <= v_cnt;
+		end
+
+		// rising edge of VSync
+		else if(vsD && !vsD2) begin	
+			v_cnt <= 0;
+			vs_low <= v_cnt;
+		end
+	end
+end
+
+// area in which OSD is being displayed
+wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
+wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
+wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
+wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
+wire [9:0] osd_hcnt    = h_cnt - h_osd_start + 1'd1;  // one pixel offset for osd_byte register
+wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
+
+wire osd_de = osd_enable && 
+              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
+              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
+
+reg  [7:0] osd_byte; 
+always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
+
+wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
+
+assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
+assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
+assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/paddle.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/paddle.vhd
new file mode 100644
index 00000000..efedbe21
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/paddle.vhd	
@@ -0,0 +1,101 @@
+-- Paddle input circuitry for Atari Super Breakout
+-- This interfaces the player control knob that moves the paddle. The original hardware
+-- used an analog potentiometer that was read by comparing the voltage of a ramp generated
+-- by a charging capacitor against the voltage from the pot wiper. That could be duplicated 
+-- with external circuitry but here an optical encoder will be used. The hardware included 
+-- two channels but Super Breakout only made use of one.
+-- 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+
+entity paddle is 
+port(		
+			CLK6			: in  std_logic; 
+			Enc_A			: in  std_logic;
+			Enc_B			: in  std_logic;
+			Mask1_n			: in	std_logic;
+			Mask2_n			: in  std_logic;
+			Vblank			: in	std_logic;
+			Sense1			: out std_logic;
+			Sense2			: out std_logic;
+			NMI_n			: out std_logic
+			);
+end paddle;
+
+architecture rtl of paddle is
+
+signal sense1_int	: std_logic;
+signal sense2_int	: std_logic;
+signal comp1_n: std_logic;
+signal ramp: integer range 0 to 100000;
+signal position: integer range 0 to 160000;
+signal pad_pos: integer range 400 to 2500;
+
+
+begin
+
+-- Ramp is reset by Vblank pulse and begins to rise. Originally an analog comparator compared the pot position
+-- against the ramp voltage, the output of this comparator going high when the ramp voltage rises above the pot value
+-- Since this ramp counter is clocked at 6MHz, position output from encoder interface is multiplied
+Ramp_Compare: process(clk6, Vblank)
+begin
+	if rising_edge(clk6) then
+		if Vblank = '1' then
+			comp1_n <= '0';
+			ramp <= 0;
+		else
+			ramp <= ramp + 1;
+		end if;
+		
+		if ramp > (pad_pos * 35) then 
+			comp1_n <= '1';
+		end if;
+	end if;
+end process;
+	
+-- Logic gates in IC at M10
+sense1_int <= not(comp1_n and mask1_n);
+NMI_n <= sense1_int and sense2_int;
+
+Sense1 <= Sense1_int;
+Sense2 <= Sense2_int;
+
+-- The original hardware has support for two pots however the game code only supports one so hardwire this high
+sense2_int <= '1';	
+
+-- If the pulse from the ramp comparator comes too soon after Vblank the paddle interrupt is triggered too 
+-- early and this causes problems so make the minimum position 500. 
+pad_pos <= (position + 500);
+
+
+-- Interface for the quadrature encoder. The optical encoder used in the prototype has a very high resolution, it 
+-- will be necessary to adjust values for other encoders
+encoder: entity work.quadrature_decoder
+	generic map(
+		positions => 2000, 		--size of the position counter (i.e. number of positions counted)
+		debounce_time => 500, 	--number of clock cycles required to register a new position = debounce_time + 2
+		set_origin_debounce_time => 50_000)	--number of clock cycles required to register a new set_origin_n value = set_origin_debounce_time + 2
+	port map(
+		clk => clk6,								--system clock
+		a => Enc_a,									--quadrature encoded signal a
+		b => Enc_b,									--quadrature encoded signal b
+		set_origin_n => '1',  					--active-low synchronous clear of position counter
+		direction => open,						--direction of last change, 1 = positive, 0 = negative
+		position => position
+		);
+
+end rtl;
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/paddle_analog.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/paddle_analog.vhd
new file mode 100644
index 00000000..5292ab50
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/paddle_analog.vhd	
@@ -0,0 +1,53 @@
+-- Paddle interface using analog potentiometer for Super Breakout arcade game by Atari
+-- (c) 2017 James Sweet
+--
+-- Use this file if you want to use a potentiometer as used in the original arcade machine
+-- instead of an encoder to control the paddle. An external analog comparator and ramp generator
+-- circuit is required, see schematic in Super Breakout manual.  
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity paddle_analog is 
+port(		
+			Pot_Comp1_n		: in  std_logic;
+			Pot_Comp2_n		: in  std_logic;
+			Mask1_n			: in	std_logic;
+			Mask2_n			: in  std_logic;
+			Vblank			: in	std_logic;
+			Sense1			: out std_logic;
+			Sense2			: out std_logic;
+			NMI_n				: out std_logic
+			);
+end paddle_analog;
+
+architecture rtl of paddle_analog is
+
+signal sense1_int		: std_logic;
+signal sense2_int		: std_logic;
+
+begin
+
+sense1 <= sense1_int;
+sense2 <= sense2_int;
+
+-- Logic gates in IC at M10
+-- These should be a 74LS132 with Schmitt trigger inputs, may not work reliably using FPGA pins directly
+sense1_int <= not(Pot_Comp1_n and mask1_n);
+sense2_int <= not(Pot_Comp2_n and mask2_n);
+NMI_n <= sense1_int and sense2_int;
+
+end rtl;
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/playfield.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/playfield.vhd
new file mode 100644
index 00000000..78b1bd1b
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/playfield.vhd	
@@ -0,0 +1,148 @@
+-- Playfield generation circuitry for Atari Super Breakout
+-- Several other games use a virtually identical circuit
+-- (c)2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity playfield is 
+port(		
+			Clk6				: in	std_logic;
+			Display			: in	std_logic_vector(7 downto 0);
+			HCount			: in  std_logic_vector(8 downto 0);
+			VCount			: in	std_logic_vector(7 downto 0);
+			H256_s			: out std_logic; -- 256H* on schematic
+			HBlank			: in	std_logic;
+			VBlank			: in	std_logic;
+			VBlank_n_s		: in  std_logic; -- VBLANK* on the schematic	
+			HSync				: in	std_logic;
+			VSync				: in	std_logic;
+			CompSync_n_s	: out std_logic; -- COMP SYNC* on schematic
+			CompBlank_s		: out std_logic; -- COMP BLANK* on schematic
+			Playfield_n		: out	std_logic
+			);
+end playfield;
+
+architecture rtl of playfield is
+
+signal H1				: std_logic;
+signal H2				: std_logic;
+signal H4				: std_logic;
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+
+signal V1				: std_logic;
+signal V2				: std_logic;
+signal V4				: std_logic;
+
+signal char_addr		: std_logic_vector(8 downto 0) := (others => '0');
+signal char_data		: std_logic_vector(7 downto 0) := (others => '0');
+signal shift_data		: std_logic_vector(7 downto 0) := (others => '0');
+signal QH				: std_logic := '0';
+signal R7_12			: std_logic := '0';
+signal P3_3				: std_logic := '0';
+signal Display7_s		: std_logic := '0';
+
+begin
+-- Video synchronization signals
+H1 <= Hcount(0);
+H2 <= Hcount(1);
+H4 <= Hcount(2);
+H256 <= Hcount(8);
+H256_n <= not(Hcount(8));
+
+V1 <= Vcount(0);
+V2 <= Vcount(1);
+V4 <= Vcount(2);
+
+
+-- Some glue logic, some signals could be renamed to be easier to follow without referring to schematic
+R7_12 <= not(H1 and H2 and H4); -- 3-input NAND gate at R7
+P3_3 <= (H256_n or R7_12); -- OR gate at P3
+char_addr <= display(5 downto 0) & V4 & V2 & V1;
+
+-- Background character ROMs
+R4: entity work.sprom
+generic map(
+		init_file => "rtl/roms/033281_r4.hex",
+		widthad_a => 9,
+		width_a => 4)
+port map(
+		clock => clk6,
+		Address => char_addr,
+		q => char_data(3 downto 0) 
+		);
+		
+--R4: entity work.Char_MSB
+--port map(
+--	clock => clk6,
+--	Address => char_addr,
+--	q => char_data(3 downto 0) 
+--	);
+
+P4: entity work.sprom
+generic map(
+		init_file => "rtl/roms/033280_p4.hex",
+		widthad_a => 9,
+		width_a => 4)
+port map(
+		clock => clk6,
+		Address => char_addr,
+		q => char_data(7 downto 4) 
+		);
+
+--P4: entity work.Char_LSB
+--port map(
+--	clock => clk6,
+--	Address => char_addr,
+--	q => char_data(7 downto 4) 
+--	);	
+
+
+-- 74LS166 video shift register	
+R3: process(clk6, P3_3, VBlank_n_s, char_data)
+begin
+	if VBlank_n_s = '0' then -- Connected Clear input
+		shift_data <= (others => '0');
+	elsif rising_edge(clk6) then 
+		if P3_3 = '0' then -- Parallel load
+			shift_data <= char_data;
+		else
+			shift_data <= shift_data(6 downto 0) & '0';
+		end if;
+	end if;
+	QH <= shift_data(7);
+end process;
+
+
+-- 9316 counter at R2
+-- CEP and CET tied to ground, counter is used only as a synchronous latch
+R2: process(clk6, R7_12, display(7), H256, Hblank, Vblank, Hsync, Vsync)
+begin
+	if rising_edge(clk6) then
+		if R7_12 = '0' then
+			H256_s <= H256;
+			Display7_s <= display(7);
+			CompBlank_s <= (Hblank or Vblank);
+			CompSync_n_s <= not(Hsync or Vsync);
+		end if;
+	end if;
+end process;
+
+Playfield_n <= not(QH and Display7_s);
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/pll.v b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/pll.v
new file mode 100644
index 00000000..6a352243
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/pll.v	
@@ -0,0 +1,337 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	inclk0,
+	c0,
+	c1,
+	locked);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  locked;
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire6 = 1'h0;
+	wire [0:0] sub_wire3 = sub_wire0[0:0];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  c0 = sub_wire3;
+	wire  sub_wire4 = inclk0;
+	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+	altpll	altpll_component (
+				.inclk (sub_wire5),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 125,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 224,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 125,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 56,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "125"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "125"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.383999"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.096000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "224"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "56"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.38400000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.09600000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "224"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "125"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/quadrature_decoder.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/quadrature_decoder.vhd
new file mode 100644
index 00000000..4e347271
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/quadrature_decoder.vhd	
@@ -0,0 +1,103 @@
+--------------------------------------------------------------------------------
+--
+--   FileName:         quadrature_decoder.vhd
+--   Dependencies:     None
+--   Design Software:  Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition
+--
+--   HDL CODE IS PROVIDED "AS IS."  DIGI-KEY EXPRESSLY DISCLAIMS ANY
+--   WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+--   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+--   PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+--   BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+--   DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+--   PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+--   BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+--   ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+--   Version History
+--   Version 1.0 9/7/2017 Scott Larson
+--     Initial Public Release
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY quadrature_decoder IS
+	GENERIC(
+		positions						:	INTEGER := 16; 		--size of the position counter (i.e. number of positions counted)
+		debounce_time					:	INTEGER := 50_000; 	--number of clock cycles required to register a new position = debounce_time + 2
+		set_origin_debounce_time	:	INTEGER := 500_000);	--number of clock cycles required to register a new set_origin_n value = set_origin_debounce_time + 2
+	PORT(
+		clk				:	IN			STD_LOGIC;										--system clock
+		a					:	IN			STD_LOGIC;										--quadrature encoded signal a
+		b					:	IN			STD_LOGIC;  									--quadrature encoded signal b
+		set_origin_n	:	IN			STD_LOGIC;  									--active-low synchronous clear of position counter
+		direction		:	OUT		STD_LOGIC;										--direction of last change, 1 = positive, 0 = negative
+		position			:	BUFFER	INTEGER RANGE 0 TO positions-1 := 0);	--current position relative to index or initial value
+END quadrature_decoder;
+
+ARCHITECTURE logic OF quadrature_decoder IS
+	SIGNAL	a_new 				:	STD_LOGIC_VECTOR(1 DOWNTO 0);						--synchronizer/debounce registers for encoded signal a
+	SIGNAL	b_new					:	STD_LOGIC_VECTOR(1 DOWNTO 0); 					--synchronizer/debounce registers for encoded signal b
+	SIGNAL	a_prev				:	STD_LOGIC;												--last previous stable value of encoded signal a
+	SIGNAL	b_prev				:	STD_LOGIC;												--last previous stable value of encoded signal b
+	SIGNAL	debounce_cnt		:	INTEGER RANGE 0 TO debounce_time;				--timer to remove glitches and validate stable values of inputs
+	SIGNAL	set_origin_n_new	:	STD_LOGIC_VECTOR(1 DOWNTO 0);						--synchronizer/debounce registers for the set_origin_n input
+	SIGNAL	set_origin_n_int	:	STD_LOGIC;												--last debounced value of set_origin_n signal
+	SIGNAL	set_origin_cnt		:	INTEGER RANGE 0 TO set_origin_debounce_time;	--debounce counter for set_origin_n signal
+BEGIN
+
+	PROCESS(clk)
+	BEGIN
+		IF(clk'EVENT AND clk = '1') THEN													--rising edge of system clock
+		
+			--synchronize and debounce a and b inputs
+			a_new <= a_new(0) & a;																--shift in new values of 'a'	
+			b_new <= b_new(0) & b;																--shift in new values of 'b'
+			IF(((a_new(0) XOR a_new(1)) OR (b_new(0) XOR b_new(1))) = '1') THEN	--a input or b input is changing
+				debounce_cnt <= 0;																	--clear debounce counter
+			ELSIF(debounce_cnt = debounce_time) THEN										--debounce time is met
+				a_prev <= a_new(1);																	--update value of a_prev
+				b_prev <= b_new(1);																	--update value of b_prev
+			ELSE																						--debounce time is not yet met		
+				debounce_cnt <= debounce_cnt + 1;												--increment debounce counter
+			END IF;
+			
+			--synchronize and debounce set_origin_n input
+			set_origin_n_new <= set_origin_n_new(0) & set_origin_n;					--shift in new values of set_origin_n	
+			IF((set_origin_n_new(0) XOR set_origin_n_new(1)) = '1') THEN			--set_origin_n input is changing
+				set_origin_cnt <= 0;																	--clear debounce counter
+			ELSIF(set_origin_cnt = set_origin_debounce_time) THEN						--debounce time is met
+				set_origin_n_int <= set_origin_n_new(1);										--update value of set_origin_n_int
+			ELSE																						--debounce time is not yet met		
+				set_origin_cnt <= set_origin_cnt + 1;											--increment debounce counter
+			END IF;
+			
+			--determine direction and position
+			IF(set_origin_n_int = '0') THEN														--inital position is being set
+				position <= 0;																				--clear position counter
+			ELSIF(debounce_cnt = debounce_time													--debounce time for a and b is met
+					AND ((a_prev XOR a_new(1)) OR (b_prev XOR b_new(1))) = '1') THEN	--AND the new value is different than the previous value
+				direction <= b_prev XOR a_new(1);													--update the direction
+				IF((b_prev XOR a_new(1)) = '1') THEN												--clockwise direction
+					IF(position < positions-1) THEN														--not at position limit
+						position <= position + 1;																--advance position counter
+					ELSE																							--at position limit
+						--position <= 0;																				--roll over position counter to zero
+						null;
+					END IF;
+				ELSE																							--counter-clockwise direction
+					IF(position > 0) THEN																	--not at position limit
+						position <= position - 1;																--decrement position counter
+					ELSE																							--at position limit
+						--position <= positions-1;																--roll over position counter maximum
+						null;
+					END IF;
+				END IF;
+			END IF;
+			
+		END IF;
+	END PROCESS;
+
+END logic;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/006400_m2.hex b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/006400_m2.hex
new file mode 100644
index 00000000..9dbfacea
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/006400_m2.hex	
@@ -0,0 +1,17 @@
+:1000000000000000000000000000000000000000F0
+:1000100000000000000000000000000000000000E0
+:1000200000000000000000000000000000000000D0
+:1000300000000000000000000000000000000000C0
+:1000400000000000000000000000000000000000B0
+:1000500000000000000000000000000000000000A0
+:100060000000000000000000000000000000000090
+:100070000000000000000000000000000000000878
+:100080000A0A0A0A0A0E0000000000000000000030
+:100090000000000000000000000000000000000060
+:1000A0000000000000000000000000000000000050
+:1000B0000000000000000000000000000000000040
+:1000C0000000000000000000000000000000000030
+:1000D0000000000000000000000000000000000020
+:1000E0000808080808080808080808080808080A8E
+:1000F0000A0A0B0B0B0A0A0A0A0A0A0A0A0A0A0A5D
+:00000001FF
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/006401_e2.hex b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/006401_e2.hex
new file mode 100644
index 00000000..975d72ea
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/006401_e2.hex	
@@ -0,0 +1,3 @@
+:100000001111010141418181C1C12121E1E1E1E100
+:10001000E0E0E8E8E4E4ECECE2E2EAEAE6E6EEEE70
+:00000001FF
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033280_p4.hex b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033280_p4.hex
new file mode 100644
index 00000000..743eadb7
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033280_p4.hex	
@@ -0,0 +1,33 @@
+:1000000000000000000000000F0F0202020F0F00AE
+:100010000F0F0909090F060003070C08080C04005C
+:100020000F0F08080C0703000F0F09090908080043
+:100030000F0F01010101000003070C08090F0F0059
+:100040000F0F0101010F0F0008080F0F0808000033
+:10005000040C0808080F07000F0F03070E0C080018
+:100060000F0F0808080808000F0F0103010F0F0009
+:100070000F0F0103070F0F00070F0808080F0700F5
+:100080000F0F020202030100070F080A0E070B0000
+:100090000F0F02060F0D0900040D0909090F0600D4
+:1000A00000000F0F00000000070F0808080F0700EE
+:1000B0000103070E070301000F0F0703070F0F00CF
+:1000C0000C0E0703070E0C0000010F0F01000000CB
+:1000D0000C0E0F0B090808000000000000000000D3
+:1000E0000000000000000000000000000000000010
+:1000F0000000000000000000000000000000000000
+:1001000000000000000000000300000000000000EC
+:1001100003030000000000000303030000000000D0
+:1001200003030303000000000303030303000000B4
+:100130000303030303030000030303030303030098
+:100140000303030303030303000303030303030382
+:10015000000003030303030300000003030303037E
+:10016000000000000303030300000000000303037A
+:100170000000000000000303000000000000000376
+:1001800003070C080807030008080F0F0808000001
+:100190000C0E0F0B0B090800040C0909090F0600CF
+:1001A000030302020F0F0200040C0808080F0700E7
+:1001B000070F0909090F060000000E0F01000000DB
+:1001C0000609090B0B0E0600000909090D070300BB
+:1001D000000000000000000003000F0F0F0F0F0FC2
+:1001E00003030F0F0F0F0F0F00000F0F0F0F0F0F55
+:1001F00000000F0F0F0F0F0F0F0F0F0F0F0F0F0F2D
+:00000001FF
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033281_r4.hex b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033281_r4.hex
new file mode 100644
index 00000000..000d461b
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033281_r4.hex	
@@ -0,0 +1,33 @@
+:100000000000000000000000080C0602060C0800BA
+:100010000E0E0202020E0C00080C0602020604007C
+:100020000E0E0202060C08000E0E02020202000072
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+:100040000E0E0000000E0E0002020E0E0202000054
+:1000500000000000000E0E000E0E00080C0602004C
+:100060000E0E0000000000000E0E0C080C0E0E001C
+:100070000E0E0C08000E0E000C0E0202020E0C00FA
+:100080000E0E0202020E0C000C0E0202020E0C00FA
+:100090000E0E0202020E0C000C0E020206040000FC
+:1000A00002020E0E020200000E0E0000000E0E00F4
+:1000B0000E0E0000000E0E000E0E0008000E0E00C8
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diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033282_k6.hex b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033282_k6.hex
new file mode 100644
index 00000000..0e7a352d
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033282_k6.hex	
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diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033453_c1.hex b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033453_c1.hex
new file mode 100644
index 00000000..dfc82906
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+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033453_c1.hex	
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diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033454_d1.hex b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/033454_d1.hex
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index 00000000..ae94647e
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diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/roms.rar b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/roms/roms.rar
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HcmV?d00001

diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/scandoubler.sv b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/scandoubler.sv
new file mode 100644
index 00000000..0213d20c
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/scandoubler.sv	
@@ -0,0 +1,195 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2017 Sorgelig
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+// TODO: Delay vsync one line
+
+module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	// system interface
+	input             clk_sys,
+	input             ce_pix,
+	input             ce_pix_actual,
+
+	input             hq2x,
+
+	// shifter video interface
+	input             hs_in,
+	input             vs_in,
+	input             line_start,
+
+	input  [DWIDTH:0] r_in,
+	input  [DWIDTH:0] g_in,
+	input  [DWIDTH:0] b_in,
+	input             mono,
+
+	// output interface
+	output reg        hs_out,
+	output            vs_out,
+	output [DWIDTH:0] r_out,
+	output [DWIDTH:0] g_out,
+	output [DWIDTH:0] b_out
+);
+
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+assign vs_out = vs_in;
+
+reg  [2:0] phase;
+reg  [2:0] ce_div;
+reg  [7:0] pix_len = 0;
+wire [7:0] pl = pix_len + 1'b1;
+
+reg ce_x1, ce_x4;
+reg req_line_reset;
+wire ls_in = hs_in | line_start;
+always @(negedge clk_sys) begin
+	reg old_ce;
+	reg [2:0] ce_cnt;
+
+	reg [7:0] pixsz2, pixsz4 = 0;
+
+	old_ce <= ce_pix;
+	if(~&pix_len) pix_len <= pix_len + 1'd1;
+
+	ce_x4 <= 0;
+	ce_x1 <= 0;
+
+	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
+	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
+		phase <= phase + 1'd1;
+		ce_x4 <= 1;
+	end
+
+	if(~old_ce & ce_pix) begin
+		pixsz2 <= {1'b0,  pl[7:1]};
+		pixsz4 <= {2'b00, pl[7:2]};
+		ce_x1 <= 1;
+		ce_x4 <= 1;
+		pix_len <= 0;
+		phase <= phase + 1'd1;
+
+		ce_cnt <= ce_cnt + 1'd1;
+		if(ce_pix_actual) begin
+			phase <= 0;
+			ce_div <= ce_cnt + 1'd1;
+			ce_cnt <= 0;
+			req_line_reset <= 0;
+		end
+
+		if(ls_in) req_line_reset <= 1;
+	end
+end
+
+reg ce_sd;
+always @(*) begin
+	case(ce_div)
+		2: ce_sd = !phase[0];
+		4: ce_sd = !phase[1:0];
+		default: ce_sd <= 1;
+	endcase
+end
+
+`define BITS_TO_FIT(N) ( \
+     N <=   2 ? 0 : \
+     N <=   4 ? 1 : \
+     N <=   8 ? 2 : \
+     N <=  16 ? 3 : \
+     N <=  32 ? 4 : \
+     N <=  64 ? 5 : \
+     N <= 128 ? 6 : \
+     N <= 256 ? 7 : \
+     N <= 512 ? 8 : \
+     N <=1024 ? 9 : 10 )
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
+(
+	.clk(clk_sys),
+	.ce_x4(ce_x4 & ce_sd),
+	.inputpixel({b_in,g_in,r_in}),
+	.mono(mono),
+	.disable_hq2x(~hq2x),
+	.reset_frame(vs_in),
+	.reset_line(req_line_reset),
+	.read_y(sd_line),
+	.read_x(sd_h_actual),
+	.outpixel({b_out,g_out,r_out})
+);
+
+reg [10:0] sd_h_actual;
+always @(*) begin
+	case(ce_div)
+		2: sd_h_actual = sd_h[10:1];
+		4: sd_h_actual = sd_h[10:2];
+		default: sd_h_actual = sd_h;
+	endcase
+end
+
+reg [10:0] sd_h;
+reg  [1:0] sd_line;
+always @(posedge clk_sys) begin
+
+	reg [11:0] hs_max,hs_rise,hs_ls;
+	reg [10:0] hcnt;
+	reg [11:0] sd_hcnt;
+
+	reg hs, hs2, vs, ls;
+
+	if(ce_x1) begin
+		hs <= hs_in;
+		ls <= ls_in;
+
+		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
+
+		// falling edge of hsync indicates start of line
+		if(hs && !hs_in) begin
+			hs_max <= {hcnt,1'b1};
+			hcnt <= 0;
+			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
+		end else begin
+			hcnt <= hcnt + 1'd1;
+		end
+
+		// save position of rising edge
+		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
+
+		vs <= vs_in;
+		if(vs && ~vs_in) sd_line <= 0;
+	end
+
+	if(ce_x4) begin
+		hs2 <= hs_in;
+
+		// output counter synchronous to input and at twice the rate
+		sd_hcnt <= sd_hcnt + 1'd1;
+		sd_h    <= sd_h    + 1'd1;
+		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
+		if(sd_hcnt == hs_max) sd_hcnt <= 0;
+
+		// replicate horizontal sync at twice the speed
+		if(sd_hcnt == hs_max)  hs_out <= 0;
+		if(sd_hcnt == hs_rise) hs_out <= 1;
+
+		if(sd_hcnt == hs_ls)   sd_h    <= 0;
+		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/sprom.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/sprom.vhd
new file mode 100644
index 00000000..a81ac959
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/sprom.vhd	
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/super_breakout.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/super_breakout.vhd
new file mode 100644
index 00000000..6eda769b
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/super_breakout.vhd	
@@ -0,0 +1,254 @@
+-- Top level file for FPGA implementation of Super Breakout arcade game by Atari
+-- (c) 2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+-- Targeted to EP2C5T144C8 mini board but porting to nearly any FPGA should be fairly simple
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity super_breakout is 
+port(		
+			clk_12		: in	std_logic;	-- 50MHz input clock
+			Reset_n		: in	std_logic;	-- Reset (Active low)
+			Coin1_I		: in	std_logic;	-- Coin switches 
+			Coin2_I		: in 	std_logic;
+			Start1_I		: in	std_logic;	-- Player start buttons
+			Start2_I		: in	std_logic;
+			Serve_I		: in 	std_logic;
+			Select1_I	: in  std_logic;  -- Select inputs from game type select knob
+			Select2_I	: in  std_logic;
+			Test_I		: in 	std_logic; 	-- Self test switch
+			Slam_I		: in	std_logic;	-- Slam switch
+			Enc_A			: in  std_logic;	-- Rotary encoder, used in place of a pot to control the paddle
+			Enc_B			: in  std_logic;
+			Pot_Comp1_I	: in  std_logic;	-- If you want to use a pot instead, this goes to the output of the comparator
+			VBlank_O		: out std_logic;  -- VBlank signal to reset the ramp genrator used by the pot reading circuitry
+			Lamp1_O		: out	std_logic;	-- Player start button lamps (Active high to control incandescent lamps via SCR or transistors)
+			Lamp2_O		: out	std_logic;
+			Serve_LED_O	: out std_logic;	-- Serve button LED (Active low)
+			Counter_O	: out std_logic;	-- Coin counter output (Active high)
+			Audio_O		: out std_logic_vector(7 downto 0);	-- PWM audio, low pass filter is desirable but not really necessary for the simple SFX in this game
+			Video_O		: out std_logic;	-- Video output, sum this through a 470R resistor to composite video
+			HS				: out std_logic;
+			VS				: out std_logic;
+			HB				: out std_logic;
+			VB				: out std_logic;
+			CompSync_O	: out std_logic); -- Composite sync, sum this through a 1k resistor to composite video
+end super_breakout;
+
+architecture rtl of super_breakout is
+
+signal clk_6			: std_logic;
+signal phi2				: std_logic;
+
+signal reset_h			: std_logic;
+
+signal NMI_n			: std_logic;
+signal Timer_Reset_n	: std_logic;
+signal IntAck_n		: std_logic;
+signal IO_wr			: std_logic;
+signal Adr				: std_logic_vector(9 downto 0);
+signal Inputs			: std_logic_vector(1 downto 0);
+
+-- Video timing signals
+signal Hcount		   : std_logic_vector(8 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_s			: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+signal Vcount  		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+signal Hsync			: std_logic;
+signal Vsync			: std_logic;
+signal Vblank			: std_logic;
+signal Vreset			: std_logic;
+signal Vblank_s		: std_logic;
+signal Vblank_n_s		: std_logic;
+signal HBlank			: std_logic;
+signal CompBlank_s	: std_logic;
+signal CompSync_n_s	: std_logic;
+
+-- Video output signals
+signal Playfield_n	: std_logic;
+signal Ball1_n			: std_logic := '1';
+signal Ball2_n			: std_logic := '1';
+signal Ball3_n			: std_logic := '1';
+
+signal Display			: std_logic_vector(7 downto 0);
+
+signal Tones_n			: std_logic;
+
+signal SW2				: std_logic_vector(7 downto 0) := (others => '0');
+signal Mask1_n			: std_logic;
+signal Mask2_n			: std_logic;
+signal Sense1			: std_logic;
+signal Sense2			: std_logic;
+
+begin
+-- Configuration DIP switches, these can be brought out to external switches if desired
+-- See Super Breakout manual page 13 for complete information. Active low (0 = On, 1 = Off)
+--    1 	2							Language				(00 - English)
+--   			3	4					Coins per play		(10 - 1 Coin, 1 Play) 
+--						5				3/5 Balls			(1 - 3 Balls)
+--							6	7	8	Bonus play			(011 - 600 Progressive, 400 Cavity, 600 Double)
+		
+SW2 <= "00101011";
+
+-- Video mixer
+Video_O <= not(Playfield_n and Ball1_n and Ball2_n and Ball3_n);
+CompSync_O <= CompSync_n_s;
+HS <= Hsync; 
+VS <= Vsync; 
+HB <= Hblank;
+VB <= Vblank; 
+
+Reset_h <= (not Reset_n); -- Some components need an active-high reset
+Vblank_O <= Vblank; -- Resets ramp in analog paddle circuit (if used)
+
+		
+Vid_sync: entity work.synchronizer
+port map(
+		clk_12 => clk_12,
+		clk_6 => clk_6,
+		hcount => hcount,
+		vcount => vcount,
+		hsync => hsync,
+		hblank => hblank,
+		vblank_s => vblank_s,
+		vblank_n_s => vblank_n_s,
+		vblank => vblank,
+		vsync => vsync,
+		vreset => vreset
+		);		
+
+PF: entity work.playfield
+port map(
+		Clk6 => clk_6,
+		Display => Display,
+		HCount => HCount,
+		VCount => VCount,
+		H256_s => H256_s,
+		HBlank => HBlank,
+		VBlank => VBlank,
+		VBlank_n_s => VBlank_n_s,
+		HSync => HSync,
+		VSync => VSync,
+		CompSync_n_s => CompSync_n_s,
+		CompBlank_s => CompBlank_s,
+		Playfield_n => Playfield_n
+		);
+	
+Ball_motion: entity work.motion
+port map(
+		Clk6 => clk_6,
+		PHI2 => phi2,
+		Display => Display,
+		H256_s => H256_s,
+		VCount => VCount,
+		HCount => HCount,
+		Tones_n => Tones_n,
+		Ball1_n => Ball1_n,
+		Ball2_n => Ball2_n,
+		Ball3_n => Ball3_n	
+		);
+
+Sounds: entity work.audio
+port map(
+		Reset_n => Reset_n,
+		Tones_n => Tones_n,
+		Display => Display(3 downto 0),
+		VCount => VCount,
+		Audio_PWM => Audio_O
+		);
+	
+Knob: entity work.paddle
+port map(
+		Clk6 => Clk_6,
+		Enc_A => Enc_A,
+		Enc_B => Enc_B,
+		Mask1_n => Mask1_n,
+		Mask2_n => Mask2_n,
+		Vblank => Vblank,
+		Sense1 => Sense1,
+		Sense2 => Sense2,
+		NMI_n => NMI_n
+		);
+	
+CPU: entity work.cpu_mem
+port map(
+		Clk12 => Clk_12,
+		Clk6 => Clk_6,
+		Reset_n => Reset_n,
+		NMI_n => NMI_n,
+		VCount => VCount,
+		HCount => HCount,
+		Hsync_n => not Hsync,
+		Timer_Reset_n => Timer_Reset_n,
+		IntAck_n => IntAck_n,
+		IO_wr => IO_wr,
+		Phi2_o => Phi2,
+		Display => Display,
+		IO_Adr => Adr,
+		Inputs => Inputs
+		);
+	
+Input_Output: entity work.IO
+port map(
+		clk6 => clk_6,
+		SW2 => SW2, -- DIP switches
+		Coin1_n => Coin1_I,
+		Coin2_n => Coin2_I,
+		Start1_n => Start1_I,
+		Start2_n => Start2_I,
+		Select1_n => Select1_I,
+		Select2_n => Select2_I,
+		Serve_n => Serve_I,
+		Test_n => Test_I,
+		Slam_n => Slam_I,
+		Sense1 => Sense1,
+		Sense2 => Sense2,
+		Mask1_n => Mask1_n,
+		Mask2_n => Mask2_n,
+		Timer_Reset_n => Timer_Reset_n,
+		IntAck_n => IntAck_n,
+		IO_wr => IO_wr,
+		Lamp1 => Lamp1_O,
+		Lamp2 => Lamp2_O,
+		Serv_LED_n => Serve_LED_O, 
+		Counter => Counter_O,
+		Adr => Adr,
+		Inputs => Inputs
+	);	
+	
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv
new file mode 100644
index 00000000..20f01e14
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/super_breakout_mist.sv	
@@ -0,0 +1,147 @@
+module super_breakout_mist(
+	output        LED,
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.sv" 
+
+localparam CONF_STR = {
+	"S. Breakout;;",
+	"O1,Test Mode,Off,On;",
+	"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+	"T6,Reset;",
+	"V,v1.00.",`BUILD_DATE
+};
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [9:0] kbjoy;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoubler_disable;
+wire        ypbpr;
+wire        ps2_kbd_clk, ps2_kbd_data;
+wire  [7:0] audio;
+wire			video;
+
+wire clk_48, clk_12;
+wire locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.c0(clk_48),//48.384
+	.c1(clk_12),//12.096
+	.locked(locked)
+);
+
+
+super_breakout super_breakout (
+	.clk_12(clk_12),
+	.Reset_n(~(status[0] | status[6] | buttons[1])),
+	.CompSync_O(),					
+	.HS(hs),
+	.VS(vs),
+	.VB(vb),		
+	.HB(hb),
+	.Video_O(video),			
+	.Audio_O(audio),
+	.Coin1_I(~kbjoy[7]),
+	.Coin2_I(~kbjoy[7]),
+	.Start1_I(~kbjoy[5]),
+	.Start2_I(~kbjoy[6]),
+	.Select1_I(),
+	.Select2_I(),
+	.Enc_A(),
+	.Enc_B(),
+	.Pot_Comp1_I(),
+	.Slam_I(),
+	.Serve_I(~kbjoy[4]),
+	.Test_I(~status[1]),	
+	.Lamp1_O(~LED),
+	.Lamp2_O(),
+	.Serve_LED_O(),
+	.Counter_O()
+	);
+
+dac dac (
+	.CLK(clk_48),
+	.RESET(1'b0),
+	.DACin(audio),
+	.DACout(AUDIO_L)
+	);
+
+assign AUDIO_R = AUDIO_L;
+
+wire hs, vs;
+wire hb, vb;
+wire blankn = ~(hb | vb);
+video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
+(
+	.clk_sys(clk_48),
+	.ce_pix(clk_12),
+	.ce_pix_actual(clk_12),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(blankn ? {video,video,video} : "000"),
+	.G(blankn ? {video,video,video} : "000"),
+	.B(blankn ? {video,video,video} : "000"),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoubler_disable),
+	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
+	.hq2x(status[4:3]==1),
+	.ypbpr_full(1),
+	.line_start(0),
+	.mono(1)
+);
+
+mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
+(
+	.clk_sys        (clk_48   	     ),
+	.conf_str       (CONF_STR       ),
+	.SPI_SCK        (SPI_SCK        ),
+	.CONF_DATA0     (CONF_DATA0     ),
+	.SPI_SS2			 (SPI_SS2        ),
+	.SPI_DO         (SPI_DO         ),
+	.SPI_DI         (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches   	 (switches       ),
+	.scandoubler_disable(scandoubler_disable),
+	.ypbpr          (ypbpr          ),
+	.ps2_kbd_clk    (ps2_kbd_clk    ),
+	.ps2_kbd_data   (ps2_kbd_data   ),
+	.joystick_0   	 (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+);
+
+keyboard keyboard(
+	.clk(clk_48),
+	.reset(),
+	.ps2_kbd_clk(ps2_kbd_clk),
+	.ps2_kbd_data(ps2_kbd_data),
+	.joystick(kbjoy)
+	);
+
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/sync.vhd b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/sync.vhd
new file mode 100644
index 00000000..0e15e09c
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/sync.vhd	
@@ -0,0 +1,190 @@
+-- Video synchronizer circuit for Super Breakout
+-- Similar circuit used in many other Atari and Kee Games arcade games
+-- (c)2017 James Sweet
+--
+-- This is free software: you can redistribute
+-- it and/or modify it under the terms of the GNU General
+-- Public License as published by the Free Software
+-- Foundation, either version 3 of the License, or (at your
+-- option) any later version.
+--
+-- This is distributed in the hope that it will
+-- be useful, but WITHOUT ANY WARRANTY; without even the
+-- implied warranty of MERCHANTABILITY or FITNESS FOR A
+-- PARTICULAR PURPOSE. See the GNU General Public License
+-- for more details.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity synchronizer is 
+port(		
+			clk_12		: in	std_logic;
+			clk_6			: out	std_logic;
+			hcount		: out	std_logic_vector(8 downto 0);
+			vcount		: out	std_logic_vector(7 downto 0);
+		   hsync			: out	std_logic;
+			hblank		: out std_logic;
+			vblank_s		: out std_logic;
+			vblank_n_s	: out std_logic;
+			vblank		: out	std_logic;
+			vsync			: out std_logic;
+			vreset		: out	std_logic);
+end synchronizer;
+
+architecture rtl of synchronizer is
+
+signal h_counter		: std_logic_vector(9 downto 0) := (others => '0');
+signal H256				: std_logic;
+signal H256_n			: std_logic;
+signal H128				: std_logic;
+signal H64				: std_logic;
+signal H32				: std_logic;
+signal H16				: std_logic;
+signal H8				: std_logic;
+signal H8_n				: std_logic;
+signal H4				: std_logic;
+signal H4_n				: std_logic;
+signal H2				: std_logic;
+signal H1				: std_logic;
+
+signal v_counter		: std_logic_vector(7 downto 0) := (others => '0');
+signal V128				: std_logic;
+signal V64				: std_logic;
+signal V32				: std_logic;
+signal V16				: std_logic;
+signal V8				: std_logic;
+signal V4				: std_logic;
+signal V2				: std_logic;
+signal V1				: std_logic;
+
+signal sync_bus		: std_logic_vector(3 downto 0) := (others => '0');
+signal sync_reg		: std_logic_vector(3 downto 0) := (others => '0');
+signal vblank_int		: std_logic := '0';
+signal vreset_n		: std_logic := '0';
+
+signal hblank_int		: std_logic := '0';
+signal hsync_int		: std_logic := '0';
+signal hsync_reset 	: std_logic := '0';
+
+
+begin
+
+-- Horizontal counter is 9 bits long plus additional flip flop. The last 4 bit IC in the chain resets to 0010 so total count resets to 128 
+-- using only the last three count states
+H_count: process(clk_12)
+begin
+	if rising_edge(clk_12) then
+		if h_counter = "1111111111" then
+			h_counter <= "0100000000";
+		else
+			h_counter <= h_counter + 1;
+		end if;
+	end if;
+end process;
+
+-- Vertical counter is 8 bits, clocked by the rising edge of H256 at the end of each horizontal line
+V_count: process(hsync_int)
+begin
+	if rising_edge(Hsync_int) then
+		if vreset_n = '0' then
+			v_counter <= (others => '0');
+		else
+			v_counter <= v_counter + '1';
+		end if;
+	end if;
+end process;
+
+-- Many Atari raster games use a 256 x 4 bit prom to decode vertical sync signals
+-- This could be replaced with combinatorial logic
+M2: entity work.sprom
+generic map(
+		init_file => "rtl/roms/006400_m2.hex",
+		widthad_a => 8,
+		width_a => 4)
+port map(
+		clock => clk_12, 
+		address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
+		q => sync_bus
+		);
+
+
+		
+--M2: entity work.sync_prom
+--port map(
+--		clock => clk_12, 
+--		address => sync_reg(3) & V128 & V64 & V16 & V8 & V4 & V2 & V1,
+--		q => sync_bus
+--		);
+
+-- Register fed by the sync PROM, in the original hardware this also creates the complements of these signals
+sync_register: process(hsync_int)
+begin
+	if rising_edge(hsync_int) then
+		sync_reg <= sync_bus;
+	end if;
+end process;
+
+-- Outputs of sync PROM
+vblank_s <= sync_reg(3);
+vblank_n_s <= not sync_reg(3);
+vreset <= sync_reg(2);
+vreset_n <= not sync_reg(2);
+vblank <= sync_reg(1);
+vsync <= sync_reg(0);
+
+-- A pair of D type flip-flops that generate the Hsync signal
+R1_a: process(H256_n, H32)
+begin	
+	if H256_n = '0' then	
+		hblank_int <= '0';
+	else
+		if rising_edge(H32) then
+			hblank_int <= not H64;
+		end if;
+	end if;
+end process;
+
+R1_b: process(hblank_int, H8) 
+begin
+	if hblank_int = '0' then
+		hsync_int <= '0';
+	else
+		if rising_edge(H8) then
+			hsync_int <= H32;
+		end if;
+	end if;
+end process;
+
+-- Assign various signals
+clk_6 <= h_counter(0);
+H1 <= h_counter(1);
+H2 <= h_counter(2);
+H4 <= h_counter(3);
+H8 <= h_counter(4);
+H16 <=  h_counter(5);
+H32 <= h_counter(6);
+H64 <= h_counter(7);
+H128 <= h_counter(8);
+H256 <= h_counter(9);
+H4_n <= not H4;
+H8_n <= not H8;
+H256_n <= not H256;
+
+V1 <= v_counter(0);
+V2 <= v_counter(1);
+V4 <= v_counter(2);
+V8 <= v_counter(3);
+V16 <= v_counter(4);
+V32 <= v_counter(5);
+V64 <= v_counter(6);
+V128 <= v_counter(7);
+
+hcount <= h_counter(9 downto 1);
+vcount <= v_counter;
+hsync <= hsync_int;
+hblank <= hblank_int;
+
+end rtl;
\ No newline at end of file
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/video_mixer.sv b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/video_mixer.sv
new file mode 100644
index 00000000..04cfd4ba
--- /dev/null
+++ b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/rtl/video_mixer.sv	
@@ -0,0 +1,242 @@
+//
+//
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+//
+// LINE_LENGTH: Length of  display line in pixels
+//              Usually it's length from HSync to HSync.
+//              May be less if line_start is used.
+//
+// HALF_DEPTH:  If =1 then color dept is 3 bits per component
+//              For half depth 6 bits monochrome is available with
+//              mono signal enabled and color = {G, R}
+
+module video_mixer
+#(
+	parameter LINE_LENGTH  = 768,
+	parameter HALF_DEPTH   = 0,
+
+	parameter OSD_COLOR    = 3'd4,
+	parameter OSD_X_OFFSET = 10'd0,
+	parameter OSD_Y_OFFSET = 10'd0
+)
+(
+	// master clock
+	// it should be multiple by (ce_pix*4).
+	input        clk_sys,
+	
+	// Pixel clock or clock_enable (both are accepted).
+	input        ce_pix,
+
+	// Some systems have multiple resolutions.
+	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
+	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
+	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
+	input        ce_pix_actual,
+
+	// OSD SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// scanlines (00-none 01-25% 10-50% 11-75%)
+	input  [1:0] scanlines,
+
+	// 0 = HVSync 31KHz, 1 = CSync 15KHz
+	input        scandoubler_disable,
+
+	// High quality 2x scaling
+	input        hq2x,
+
+	// YPbPr always uses composite sync
+	input        ypbpr,
+
+	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
+	input        ypbpr_full,
+
+	// color
+	input [DWIDTH:0] R,
+	input [DWIDTH:0] G,
+	input [DWIDTH:0] B,
+
+	// Monochrome mode (for HALF_DEPTH only)
+	input            mono,
+
+	// interlace sync. Positive pulses.
+	input        HSync,
+	input        VSync,
+
+	// Falling of this signal means start of informative part of line.
+	// It can be horizontal blank signal.
+	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
+	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
+	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
+	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
+	// before first informative pixel.
+	input        line_start,
+
+	// MiST video output signals
+	output [5:0] VGA_R,
+	output [5:0] VGA_G,
+	output [5:0] VGA_B,
+	output       VGA_VS,
+	output       VGA_HS
+);
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+wire [DWIDTH:0] R_sd;
+wire [DWIDTH:0] G_sd;
+wire [DWIDTH:0] B_sd;
+wire hs_sd, vs_sd;
+
+scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
+(
+	.*,
+	.hs_in(HSync),
+	.vs_in(VSync),
+	.r_in(R),
+	.g_in(G),
+	.b_in(B),
+
+	.hs_out(hs_sd),
+	.vs_out(vs_sd),
+	.r_out(R_sd),
+	.g_out(G_sd),
+	.b_out(B_sd)
+);
+
+wire [DWIDTH:0] rt  = (scandoubler_disable ? R : R_sd);
+wire [DWIDTH:0] gt  = (scandoubler_disable ? G : G_sd);
+wire [DWIDTH:0] bt  = (scandoubler_disable ? B : B_sd);
+
+generate
+	if(HALF_DEPTH) begin
+		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
+		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
+		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
+	end else begin
+		wire [5:0] r  = rt;
+		wire [5:0] g  = gt;
+		wire [5:0] b  = bt;
+	end
+endgenerate
+
+wire       hs = (scandoubler_disable ? HSync : hs_sd);
+wire       vs = (scandoubler_disable ? VSync : vs_sd);
+
+reg scanline = 0;
+always @(posedge clk_sys) begin
+	reg old_hs, old_vs;
+	
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) scanline <= ~scanline;
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire [5:0] r_out, g_out, b_out;
+always @(*) begin
+	case(scanlines & {scanline, scanline})
+		1: begin // reduce 25% = 1/2 + 1/4
+			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
+			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
+			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
+		end
+
+		2: begin // reduce 50% = 1/2
+			r_out = {1'b0, r[5:1]};
+			g_out = {1'b0, g[5:1]};
+			b_out = {1'b0, b[5:1]};
+		end
+
+		3: begin // reduce 75% = 1/4
+			r_out = {2'b00, r[5:2]};
+			g_out = {2'b00, g[5:2]};
+			b_out = {2'b00, b[5:2]};
+		end
+
+		default: begin
+			r_out = r;
+			g_out = g;
+			b_out = b;
+		end
+	endcase
+end
+
+wire [5:0] red, green, blue;
+osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
+(
+	.*,
+
+	.R_in(r_out),
+	.G_in(g_out),
+	.B_in(b_out),
+	.HSync(hs),
+	.VSync(vs),
+
+	.R_out(red),
+	.G_out(green),
+	.B_out(blue)
+);
+
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+// http://marsee101.blog19.fc2.com/blog-entry-2311.html
+// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
+// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
+// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
+assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
+assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
+assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
+assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
+
+endmodule
diff --git a/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/snapshot/SuperBreakout.rbf b/Arcade_MiST/Custom Hardware/SuperBreakout_MiST/snapshot/SuperBreakout.rbf
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