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Add Interact Project Files
This commit is contained in:
Marcel
30
Computer_MiST/Interact_MiST/Interact_MiST.qpf
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30
Computer_MiST/Interact_MiST/Interact_MiST.qpf
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|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 14:59:16 November 16, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.1"
|
||||
DATE = "14:59:16 November 16, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Interact_MiST"
|
||||
246
Computer_MiST/Interact_MiST/Interact_MiST.qsf
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246
Computer_MiST/Interact_MiST/Interact_MiST.qsf
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@@ -0,0 +1,246 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
# Date created = 21:01:44 September 02, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Interact_MiST_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Interact_MiST
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# ---------------------------
|
||||
# start ENTITY(Interact_MiST)
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(Interact_MiST)
|
||||
# -------------------------
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Interact_MiST.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Interact_top.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/video_timing.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cassette.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/rom/interact.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/rom/hector1.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/dpram.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/spram.v
|
||||
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/vm80a.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ttl/SN74LS73.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ttl/SN74LS74.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ttl/SN74LS92.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ttl/SN74LS138.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ttl/SN74LS195.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ttl/SN74LS393.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/pll.v
|
||||
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
|
||||
339
Computer_MiST/Interact_MiST/LICENSE
Normal file
339
Computer_MiST/Interact_MiST/LICENSE
Normal file
@@ -0,0 +1,339 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 2, June 1991
|
||||
|
||||
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
|
||||
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The licenses for most software are designed to take away your
|
||||
freedom to share and change it. By contrast, the GNU General Public
|
||||
License is intended to guarantee your freedom to share and change free
|
||||
software--to make sure the software is free for all its users. This
|
||||
General Public License applies to most of the Free Software
|
||||
Foundation's software and to any other program whose authors commit to
|
||||
using it. (Some other Free Software Foundation software is covered by
|
||||
the GNU Lesser General Public License instead.) You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
this service if you wish), that you receive source code or can get it
|
||||
if you want it, that you can change the software or use pieces of it
|
||||
in new free programs; and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to make restrictions that forbid
|
||||
anyone to deny you these rights or to ask you to surrender the rights.
|
||||
These restrictions translate to certain responsibilities for you if you
|
||||
distribute copies of the software, or if you modify it.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must give the recipients all the rights that
|
||||
you have. You must make sure that they, too, receive or can get the
|
||||
source code. And you must show them these terms so they know their
|
||||
rights.
|
||||
|
||||
We protect your rights with two steps: (1) copyright the software, and
|
||||
(2) offer you this license which gives you legal permission to copy,
|
||||
distribute and/or modify the software.
|
||||
|
||||
Also, for each author's protection and ours, we want to make certain
|
||||
that everyone understands that there is no warranty for this free
|
||||
software. If the software is modified by someone else and passed on, we
|
||||
want its recipients to know that what they have is not the original, so
|
||||
that any problems introduced by others will not reflect on the original
|
||||
authors' reputations.
|
||||
|
||||
Finally, any free program is threatened constantly by software
|
||||
patents. We wish to avoid the danger that redistributors of a free
|
||||
program will individually obtain patent licenses, in effect making the
|
||||
program proprietary. To prevent this, we have made it clear that any
|
||||
patent must be licensed for everyone's free use or not licensed at all.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
|
||||
|
||||
0. This License applies to any program or other work which contains
|
||||
a notice placed by the copyright holder saying it may be distributed
|
||||
under the terms of this General Public License. The "Program", below,
|
||||
refers to any such program or work, and a "work based on the Program"
|
||||
means either the Program or any derivative work under copyright law:
|
||||
that is to say, a work containing the Program or a portion of it,
|
||||
either verbatim or with modifications and/or translated into another
|
||||
language. (Hereinafter, translation is included without limitation in
|
||||
the term "modification".) Each licensee is addressed as "you".
|
||||
|
||||
Activities other than copying, distribution and modification are not
|
||||
covered by this License; they are outside its scope. The act of
|
||||
running the Program is not restricted, and the output from the Program
|
||||
is covered only if its contents constitute a work based on the
|
||||
Program (independent of having been made by running the Program).
|
||||
Whether that is true depends on what the Program does.
|
||||
|
||||
1. You may copy and distribute verbatim copies of the Program's
|
||||
source code as you receive it, in any medium, provided that you
|
||||
conspicuously and appropriately publish on each copy an appropriate
|
||||
copyright notice and disclaimer of warranty; keep intact all the
|
||||
notices that refer to this License and to the absence of any warranty;
|
||||
and give any other recipients of the Program a copy of this License
|
||||
along with the Program.
|
||||
|
||||
You may charge a fee for the physical act of transferring a copy, and
|
||||
you may at your option offer warranty protection in exchange for a fee.
|
||||
|
||||
2. You may modify your copy or copies of the Program or any portion
|
||||
of it, thus forming a work based on the Program, and copy and
|
||||
distribute such modifications or work under the terms of Section 1
|
||||
above, provided that you also meet all of these conditions:
|
||||
|
||||
a) You must cause the modified files to carry prominent notices
|
||||
stating that you changed the files and the date of any change.
|
||||
|
||||
b) You must cause any work that you distribute or publish, that in
|
||||
whole or in part contains or is derived from the Program or any
|
||||
part thereof, to be licensed as a whole at no charge to all third
|
||||
parties under the terms of this License.
|
||||
|
||||
c) If the modified program normally reads commands interactively
|
||||
when run, you must cause it, when started running for such
|
||||
interactive use in the most ordinary way, to print or display an
|
||||
announcement including an appropriate copyright notice and a
|
||||
notice that there is no warranty (or else, saying that you provide
|
||||
a warranty) and that users may redistribute the program under
|
||||
these conditions, and telling the user how to view a copy of this
|
||||
License. (Exception: if the Program itself is interactive but
|
||||
does not normally print such an announcement, your work based on
|
||||
the Program is not required to print an announcement.)
|
||||
|
||||
These requirements apply to the modified work as a whole. If
|
||||
identifiable sections of that work are not derived from the Program,
|
||||
and can be reasonably considered independent and separate works in
|
||||
themselves, then this License, and its terms, do not apply to those
|
||||
sections when you distribute them as separate works. But when you
|
||||
distribute the same sections as part of a whole which is a work based
|
||||
on the Program, the distribution of the whole must be on the terms of
|
||||
this License, whose permissions for other licensees extend to the
|
||||
entire whole, and thus to each and every part regardless of who wrote it.
|
||||
|
||||
Thus, it is not the intent of this section to claim rights or contest
|
||||
your rights to work written entirely by you; rather, the intent is to
|
||||
exercise the right to control the distribution of derivative or
|
||||
collective works based on the Program.
|
||||
|
||||
In addition, mere aggregation of another work not based on the Program
|
||||
with the Program (or with a work based on the Program) on a volume of
|
||||
a storage or distribution medium does not bring the other work under
|
||||
the scope of this License.
|
||||
|
||||
3. You may copy and distribute the Program (or a work based on it,
|
||||
under Section 2) in object code or executable form under the terms of
|
||||
Sections 1 and 2 above provided that you also do one of the following:
|
||||
|
||||
a) Accompany it with the complete corresponding machine-readable
|
||||
source code, which must be distributed under the terms of Sections
|
||||
1 and 2 above on a medium customarily used for software interchange; or,
|
||||
|
||||
b) Accompany it with a written offer, valid for at least three
|
||||
years, to give any third party, for a charge no more than your
|
||||
cost of physically performing source distribution, a complete
|
||||
machine-readable copy of the corresponding source code, to be
|
||||
distributed under the terms of Sections 1 and 2 above on a medium
|
||||
customarily used for software interchange; or,
|
||||
|
||||
c) Accompany it with the information you received as to the offer
|
||||
to distribute corresponding source code. (This alternative is
|
||||
allowed only for noncommercial distribution and only if you
|
||||
received the program in object code or executable form with such
|
||||
an offer, in accord with Subsection b above.)
|
||||
|
||||
The source code for a work means the preferred form of the work for
|
||||
making modifications to it. For an executable work, complete source
|
||||
code means all the source code for all modules it contains, plus any
|
||||
associated interface definition files, plus the scripts used to
|
||||
control compilation and installation of the executable. However, as a
|
||||
special exception, the source code distributed need not include
|
||||
anything that is normally distributed (in either source or binary
|
||||
form) with the major components (compiler, kernel, and so on) of the
|
||||
operating system on which the executable runs, unless that component
|
||||
itself accompanies the executable.
|
||||
|
||||
If distribution of executable or object code is made by offering
|
||||
access to copy from a designated place, then offering equivalent
|
||||
access to copy the source code from the same place counts as
|
||||
distribution of the source code, even though third parties are not
|
||||
compelled to copy the source along with the object code.
|
||||
|
||||
4. You may not copy, modify, sublicense, or distribute the Program
|
||||
except as expressly provided under this License. Any attempt
|
||||
otherwise to copy, modify, sublicense or distribute the Program is
|
||||
void, and will automatically terminate your rights under this License.
|
||||
However, parties who have received copies, or rights, from you under
|
||||
this License will not have their licenses terminated so long as such
|
||||
parties remain in full compliance.
|
||||
|
||||
5. You are not required to accept this License, since you have not
|
||||
signed it. However, nothing else grants you permission to modify or
|
||||
distribute the Program or its derivative works. These actions are
|
||||
prohibited by law if you do not accept this License. Therefore, by
|
||||
modifying or distributing the Program (or any work based on the
|
||||
Program), you indicate your acceptance of this License to do so, and
|
||||
all its terms and conditions for copying, distributing or modifying
|
||||
the Program or works based on it.
|
||||
|
||||
6. Each time you redistribute the Program (or any work based on the
|
||||
Program), the recipient automatically receives a license from the
|
||||
original licensor to copy, distribute or modify the Program subject to
|
||||
these terms and conditions. You may not impose any further
|
||||
restrictions on the recipients' exercise of the rights granted herein.
|
||||
You are not responsible for enforcing compliance by third parties to
|
||||
this License.
|
||||
|
||||
7. If, as a consequence of a court judgment or allegation of patent
|
||||
infringement or for any other reason (not limited to patent issues),
|
||||
conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot
|
||||
distribute so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you
|
||||
may not distribute the Program at all. For example, if a patent
|
||||
license would not permit royalty-free redistribution of the Program by
|
||||
all those who receive copies directly or indirectly through you, then
|
||||
the only way you could satisfy both it and this License would be to
|
||||
refrain entirely from distribution of the Program.
|
||||
|
||||
If any portion of this section is held invalid or unenforceable under
|
||||
any particular circumstance, the balance of the section is intended to
|
||||
apply and the section as a whole is intended to apply in other
|
||||
circumstances.
|
||||
|
||||
It is not the purpose of this section to induce you to infringe any
|
||||
patents or other property right claims or to contest validity of any
|
||||
such claims; this section has the sole purpose of protecting the
|
||||
integrity of the free software distribution system, which is
|
||||
implemented by public license practices. Many people have made
|
||||
generous contributions to the wide range of software distributed
|
||||
through that system in reliance on consistent application of that
|
||||
system; it is up to the author/donor to decide if he or she is willing
|
||||
to distribute software through any other system and a licensee cannot
|
||||
impose that choice.
|
||||
|
||||
This section is intended to make thoroughly clear what is believed to
|
||||
be a consequence of the rest of this License.
|
||||
|
||||
8. If the distribution and/or use of the Program is restricted in
|
||||
certain countries either by patents or by copyrighted interfaces, the
|
||||
original copyright holder who places the Program under this License
|
||||
may add an explicit geographical distribution limitation excluding
|
||||
those countries, so that distribution is permitted only in or among
|
||||
countries not thus excluded. In such case, this License incorporates
|
||||
the limitation as if written in the body of this License.
|
||||
|
||||
9. The Free Software Foundation may publish revised and/or new versions
|
||||
of the General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the Program
|
||||
specifies a version number of this License which applies to it and "any
|
||||
later version", you have the option of following the terms and conditions
|
||||
either of that version or of any later version published by the Free
|
||||
Software Foundation. If the Program does not specify a version number of
|
||||
this License, you may choose any version ever published by the Free Software
|
||||
Foundation.
|
||||
|
||||
10. If you wish to incorporate parts of the Program into other free
|
||||
programs whose distribution conditions are different, write to the author
|
||||
to ask for permission. For software which is copyrighted by the Free
|
||||
Software Foundation, write to the Free Software Foundation; we sometimes
|
||||
make exceptions for this. Our decision will be guided by the two goals
|
||||
of preserving the free status of all derivatives of our free software and
|
||||
of promoting the sharing and reuse of software generally.
|
||||
|
||||
NO WARRANTY
|
||||
|
||||
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
|
||||
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
|
||||
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
|
||||
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
|
||||
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
|
||||
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
|
||||
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
|
||||
REPAIR OR CORRECTION.
|
||||
|
||||
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
|
||||
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
|
||||
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
|
||||
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
|
||||
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
|
||||
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
|
||||
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGES.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
convey the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program is interactive, make it output a short notice like this
|
||||
when it starts in an interactive mode:
|
||||
|
||||
Gnomovision version 69, Copyright (C) year name of author
|
||||
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, the commands you use may
|
||||
be called something other than `show w' and `show c'; they could even be
|
||||
mouse-clicks or menu items--whatever suits your program.
|
||||
|
||||
You should also get your employer (if you work as a programmer) or your
|
||||
school, if any, to sign a "copyright disclaimer" for the program, if
|
||||
necessary. Here is a sample; alter the names:
|
||||
|
||||
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
|
||||
`Gnomovision' (which makes passes at compilers) written by James Hacker.
|
||||
|
||||
<signature of Ty Coon>, 1 April 1989
|
||||
Ty Coon, President of Vice
|
||||
|
||||
This General Public License does not permit incorporating your program into
|
||||
proprietary programs. If your program is a subroutine library, you may
|
||||
consider it more useful to permit linking proprietary applications with the
|
||||
library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License.
|
||||
2
Computer_MiST/Interact_MiST/Neuer Ordner/.gitattributes
vendored
Normal file
2
Computer_MiST/Interact_MiST/Neuer Ordner/.gitattributes
vendored
Normal file
@@ -0,0 +1,2 @@
|
||||
# Auto detect text files and perform LF normalization
|
||||
* text=auto
|
||||
40
Computer_MiST/Interact_MiST/Neuer Ordner/.gitignore
vendored
Normal file
40
Computer_MiST/Interact_MiST/Neuer Ordner/.gitignore
vendored
Normal file
@@ -0,0 +1,40 @@
|
||||
db
|
||||
greybox_tmp
|
||||
incremental_db
|
||||
output_files
|
||||
simulation
|
||||
hc_output
|
||||
scaler
|
||||
hps_isw_handoff
|
||||
vip
|
||||
*_sim
|
||||
.qsys_edit
|
||||
PLLJ_PLLSPE_INFO.txt
|
||||
*.bak
|
||||
*.orig
|
||||
*.rej
|
||||
*.qdf
|
||||
*.rpt
|
||||
*.smsg
|
||||
*.summary
|
||||
*.done
|
||||
*.jdi
|
||||
*.pin
|
||||
*.sof
|
||||
*.qws
|
||||
*.ppf
|
||||
*.ddb
|
||||
build_id.v
|
||||
c5_pin_model_dump.txt
|
||||
*.sopcinfo
|
||||
*.csv
|
||||
*.f
|
||||
*.cmp
|
||||
*.sip
|
||||
*.spd
|
||||
*.bsf
|
||||
*~
|
||||
*.xml
|
||||
*_netlist
|
||||
*.cdf
|
||||
**/.DS_Store
|
||||
2
Computer_MiST/Interact_MiST/Neuer Ordner/Interact.qpf
Normal file
2
Computer_MiST/Interact_MiST/Neuer Ordner/Interact.qpf
Normal file
@@ -0,0 +1,2 @@
|
||||
QUARTUS_VERSION = "17.0"
|
||||
PROJECT_REVISION = "Interact"
|
||||
66
Computer_MiST/Interact_MiST/Neuer Ordner/Interact.qsf
Normal file
66
Computer_MiST/Interact_MiST/Neuer Ordner/Interact.qsf
Normal file
@@ -0,0 +1,66 @@
|
||||
# --------------------------------------------------------------------------
|
||||
#
|
||||
# MiSTer project
|
||||
#
|
||||
# WARNING WARNING WARNING:
|
||||
# Do not add files to project in Quartus IDE! It will mess this file!
|
||||
# Add the files manually to files.qip file.
|
||||
#
|
||||
# --------------------------------------------------------------------------
|
||||
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Lite Edition"
|
||||
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
|
||||
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name MUX_RESTRUCTURE ON
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
|
||||
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
|
||||
set_global_assignment -name SEED 1
|
||||
|
||||
#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
|
||||
|
||||
#enable it only if 8bit indexed mode is used in core
|
||||
#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
|
||||
|
||||
#set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1"
|
||||
|
||||
#do not enable DEBUG_NOHDMI in release!
|
||||
#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
|
||||
|
||||
source sys/sys.tcl
|
||||
source sys/sys_analog.tcl
|
||||
source files.qip
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
11
Computer_MiST/Interact_MiST/Neuer Ordner/Interact.sdc
Normal file
11
Computer_MiST/Interact_MiST/Neuer Ordner/Interact.sdc
Normal file
@@ -0,0 +1,11 @@
|
||||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
|
||||
set CLK_VIDEO {*|pll|pll_inst|altera_pll_i|*[0].*|divclk}
|
||||
set clk_sys {*|pll|pll_inst|altera_pll_i|*[1].*|divclk}
|
||||
|
||||
set_multicycle_path -to {emu|video|video_mixer|*} -setup 2
|
||||
set_multicycle_path -to {emu|video|video_mixer|*} -hold 1
|
||||
|
||||
set_multicycle_path -to {emu|cpu|*} -setup 2
|
||||
set_multicycle_path -to {emu|cpu|*} -hold 1
|
||||
881
Computer_MiST/Interact_MiST/Neuer Ordner/Interact.sv
Normal file
881
Computer_MiST/Interact_MiST/Neuer Ordner/Interact.sv
Normal file
@@ -0,0 +1,881 @@
|
||||
//============================================================================
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//
|
||||
//============================================================================
|
||||
|
||||
module emu
|
||||
(
|
||||
//Master input clock
|
||||
input CLK_50M,
|
||||
|
||||
//Async reset from top-level module.
|
||||
//Can be used as initial reset.
|
||||
input RESET,
|
||||
|
||||
//Must be passed to hps_io module
|
||||
inout [45:0] HPS_BUS,
|
||||
|
||||
//Base video clock. Usually equals to CLK_SYS.
|
||||
output CLK_VIDEO,
|
||||
|
||||
//Multiple resolutions are supported using different CE_PIXEL rates.
|
||||
//Must be based on CLK_VIDEO
|
||||
output CE_PIXEL,
|
||||
|
||||
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
|
||||
//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
|
||||
output [12:0] VIDEO_ARX,
|
||||
output [12:0] VIDEO_ARY,
|
||||
|
||||
output [7:0] VGA_R,
|
||||
output [7:0] VGA_G,
|
||||
output [7:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output VGA_DE, // = ~(VBlank | HBlank)
|
||||
output VGA_F1,
|
||||
output [1:0] VGA_SL,
|
||||
output VGA_SCALER, // Force VGA scaler
|
||||
|
||||
input [11:0] HDMI_WIDTH,
|
||||
input [11:0] HDMI_HEIGHT,
|
||||
output HDMI_FREEZE,
|
||||
|
||||
`ifdef MISTER_FB
|
||||
// Use framebuffer in DDRAM (USE_FB=1 in qsf)
|
||||
// FB_FORMAT:
|
||||
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
|
||||
// [3] : 0=16bits 565 1=16bits 1555
|
||||
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
|
||||
//
|
||||
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
|
||||
output FB_EN,
|
||||
output [4:0] FB_FORMAT,
|
||||
output [11:0] FB_WIDTH,
|
||||
output [11:0] FB_HEIGHT,
|
||||
output [31:0] FB_BASE,
|
||||
output [13:0] FB_STRIDE,
|
||||
input FB_VBL,
|
||||
input FB_LL,
|
||||
output FB_FORCE_BLANK,
|
||||
|
||||
`ifdef MISTER_FB_PALETTE
|
||||
// Palette control for 8bit modes.
|
||||
// Ignored for other video modes.
|
||||
output FB_PAL_CLK,
|
||||
output [7:0] FB_PAL_ADDR,
|
||||
output [23:0] FB_PAL_DOUT,
|
||||
input [23:0] FB_PAL_DIN,
|
||||
output FB_PAL_WR,
|
||||
`endif
|
||||
`endif
|
||||
|
||||
output LED_USER, // 1 - ON, 0 - OFF.
|
||||
|
||||
// b[1]: 0 - LED status is system status OR'd with b[0]
|
||||
// 1 - LED status is controled solely by b[0]
|
||||
// hint: supply 2'b00 to let the system control the LED.
|
||||
output [1:0] LED_POWER,
|
||||
output [1:0] LED_DISK,
|
||||
|
||||
// I/O board button press simulation (active high)
|
||||
// b[1]: user button
|
||||
// b[0]: osd button
|
||||
output [1:0] BUTTONS,
|
||||
|
||||
input CLK_AUDIO, // 24.576 MHz
|
||||
output [15:0] AUDIO_L,
|
||||
output [15:0] AUDIO_R,
|
||||
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
|
||||
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
|
||||
|
||||
//ADC
|
||||
inout [3:0] ADC_BUS,
|
||||
|
||||
//SD-SPI
|
||||
output SD_SCK,
|
||||
output SD_MOSI,
|
||||
input SD_MISO,
|
||||
output SD_CS,
|
||||
input SD_CD,
|
||||
|
||||
//High latency DDR3 RAM interface
|
||||
//Use for non-critical time purposes
|
||||
output DDRAM_CLK,
|
||||
input DDRAM_BUSY,
|
||||
output [7:0] DDRAM_BURSTCNT,
|
||||
output [28:0] DDRAM_ADDR,
|
||||
input [63:0] DDRAM_DOUT,
|
||||
input DDRAM_DOUT_READY,
|
||||
output DDRAM_RD,
|
||||
output [63:0] DDRAM_DIN,
|
||||
output [7:0] DDRAM_BE,
|
||||
output DDRAM_WE,
|
||||
|
||||
//SDRAM interface with lower latency
|
||||
output SDRAM_CLK,
|
||||
output SDRAM_CKE,
|
||||
output [12:0] SDRAM_A,
|
||||
output [1:0] SDRAM_BA,
|
||||
inout [15:0] SDRAM_DQ,
|
||||
output SDRAM_DQML,
|
||||
output SDRAM_DQMH,
|
||||
output SDRAM_nCS,
|
||||
output SDRAM_nCAS,
|
||||
output SDRAM_nRAS,
|
||||
output SDRAM_nWE,
|
||||
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
//Secondary SDRAM
|
||||
//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
|
||||
input SDRAM2_EN,
|
||||
output SDRAM2_CLK,
|
||||
output [12:0] SDRAM2_A,
|
||||
output [1:0] SDRAM2_BA,
|
||||
inout [15:0] SDRAM2_DQ,
|
||||
output SDRAM2_nCS,
|
||||
output SDRAM2_nCAS,
|
||||
output SDRAM2_nRAS,
|
||||
output SDRAM2_nWE,
|
||||
`endif
|
||||
|
||||
input UART_CTS,
|
||||
output UART_RTS,
|
||||
input UART_RXD,
|
||||
output UART_TXD,
|
||||
output UART_DTR,
|
||||
input UART_DSR,
|
||||
|
||||
// Open-drain User port.
|
||||
// 0 - D+/RX
|
||||
// 1 - D-/TX
|
||||
// 2..6 - USR2..USR6
|
||||
// Set USER_OUT to 1 to read from USER_IN.
|
||||
input [6:0] USER_IN,
|
||||
output [6:0] USER_OUT,
|
||||
|
||||
input OSD_STATUS
|
||||
);
|
||||
|
||||
///////// Default values for ports not used in this core /////////
|
||||
|
||||
assign ADC_BUS = 'Z;
|
||||
assign USER_OUT = '1;
|
||||
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
|
||||
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
|
||||
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
|
||||
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
|
||||
|
||||
assign VGA_SCALER = 0;
|
||||
assign HDMI_FREEZE = 0;
|
||||
|
||||
assign AUDIO_S = 1;
|
||||
assign AUDIO_L = AUDIO_R;
|
||||
//assign AUDIO_R = sound_pad;
|
||||
assign AUDIO_MIX = 0;
|
||||
|
||||
assign LED_DISK = 0;
|
||||
assign LED_POWER = 0;
|
||||
assign BUTTONS = 0;
|
||||
|
||||
//////////////////////////////////////////////////////////////////
|
||||
|
||||
wire [1:0] ar = status[11:10];
|
||||
|
||||
video_freak video_freak
|
||||
(
|
||||
.*,
|
||||
.VGA_DE_IN(VGA_DE),
|
||||
.VGA_DE(),
|
||||
.ARX((!ar) ? 12'd4 : (ar - 1'd1)),
|
||||
.ARY((!ar) ? 12'd3 : 12'd0),
|
||||
.CROP_SIZE(0),
|
||||
.CROP_OFF(0),
|
||||
.SCALE(status[13:12])
|
||||
);
|
||||
|
||||
wire tape_play = status[14];
|
||||
wire tape_rewind = status[15];
|
||||
|
||||
`include "build_id.v"
|
||||
localparam CONF_STR = {
|
||||
"Interact;;",
|
||||
"F,CINK7 ,Load tape;",
|
||||
"TE,Play;",
|
||||
"TF,Stop & Rewind;",
|
||||
"-;",
|
||||
"OAB,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
|
||||
"O24,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
|
||||
"OCD,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
|
||||
"-;",
|
||||
"O6,Test Pattern,Off,On;",
|
||||
"-;",
|
||||
"T0,Reset;",
|
||||
"R0,Reset and close OSD;",
|
||||
"V,v",`BUILD_DATE
|
||||
};
|
||||
|
||||
wire forced_scandoubler;
|
||||
wire freeze_sync;
|
||||
wire [21:0] gamma_bus;
|
||||
wire [1:0] buttons;
|
||||
wire [31:0] status;
|
||||
wire [10:0] ps2_key;
|
||||
wire [15:0] joystick_0,joystick_1;
|
||||
wire [15:0] joystick_analog_0, joystick_analog_1;
|
||||
wire [7:0] paddle_0, paddle_1;
|
||||
|
||||
wire ioctl_download;
|
||||
wire ioctl_wr;
|
||||
wire [15:0] ioctl_addr;
|
||||
wire [7:0] ioctl_data;
|
||||
wire [7:0] ioctl_index;
|
||||
|
||||
hps_io #(.CONF_STR(CONF_STR)) hps_io
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
.HPS_BUS(HPS_BUS),
|
||||
.EXT_BUS(),
|
||||
.gamma_bus(gamma_bus),
|
||||
|
||||
.forced_scandoubler(forced_scandoubler),
|
||||
|
||||
.buttons(buttons),
|
||||
.status(status),
|
||||
.status_menumask({status[5]}),
|
||||
|
||||
.ioctl_download(ioctl_download),
|
||||
.ioctl_wr(ioctl_wr),
|
||||
.ioctl_addr(ioctl_addr),
|
||||
.ioctl_dout(ioctl_data),
|
||||
.ioctl_index(ioctl_index),
|
||||
|
||||
.joystick_0(joystick_0),
|
||||
.joystick_1(joystick_1),
|
||||
.joystick_analog_0(joystick_analog_0),
|
||||
.joystick_analog_1(joystick_analog_1),
|
||||
.paddle_0(paddle_0),
|
||||
.paddle_1(paddle_1),
|
||||
.ps2_key(ps2_key)
|
||||
);
|
||||
|
||||
wire rom_download = ioctl_download && (ioctl_index == 0);
|
||||
wire tape_download = ioctl_download && (ioctl_index != 0);
|
||||
|
||||
/////////////////////// CLOCKS ///////////////////////////////
|
||||
|
||||
wire clk_sys;
|
||||
wire locked;
|
||||
|
||||
pll pll
|
||||
(
|
||||
.refclk(CLK_50M),
|
||||
.rst(0),
|
||||
.outclk_0(CLK_VIDEO),
|
||||
.outclk_1(clk_sys),
|
||||
.locked(locked)
|
||||
);
|
||||
|
||||
wire reset = RESET | status[0] | buttons[1] | rom_download;
|
||||
wire rst_n = ~reset;
|
||||
|
||||
// vm80a needs a nice long reset
|
||||
reg [7:0] rcnt = 8'h00;
|
||||
wire cpu_rst_n = (rcnt == 8'hFF);
|
||||
|
||||
always @(posedge clk_sys)
|
||||
begin
|
||||
if (reset)
|
||||
rcnt <= 8'h00;
|
||||
else
|
||||
if (rcnt != 8'hFF) rcnt <= rcnt + 8'h01;
|
||||
end
|
||||
|
||||
|
||||
wire ph1;
|
||||
wire ph2;
|
||||
wire cbclk;
|
||||
wire pix_a;
|
||||
wire vid_sel;
|
||||
wire [11:0] vid_a;
|
||||
wire vid_sel_n;
|
||||
wire nrr_n;
|
||||
wire ce_n;
|
||||
wire pce;
|
||||
wire vid_ltc;
|
||||
wire ram_clk;
|
||||
wire brst;
|
||||
wire tpclk;
|
||||
wire cmp_blank;
|
||||
wire irq;
|
||||
wire inte;
|
||||
wire cmp_sync;
|
||||
wire hblank_n;
|
||||
wire vblank_n;
|
||||
wire hsync_n;
|
||||
wire vsync_n;
|
||||
|
||||
video_timing timing
|
||||
(
|
||||
.clk_14m(clk_sys),
|
||||
.rst_n(rst_n),
|
||||
.ph1(ph1),
|
||||
.ph2(ph2),
|
||||
.cbclk(cbclk),
|
||||
.pix_a(pix_a),
|
||||
.vid_sel(vid_sel),
|
||||
.vid_a0(vid_a[0]),
|
||||
.vid_a1(vid_a[1]),
|
||||
.vid_a2(vid_a[2]),
|
||||
.vid_a3(vid_a[3]),
|
||||
.vid_a4(vid_a[4]),
|
||||
.vid_a5(vid_a[5]),
|
||||
.vid_a6(vid_a[6]),
|
||||
.vid_a7(vid_a[7]),
|
||||
.vid_a8(vid_a[8]),
|
||||
.vid_a9(vid_a[9]),
|
||||
.vid_a10(vid_a[10]),
|
||||
.vid_a11(vid_a[11]),
|
||||
.vid_sel_n(vid_sel_n),
|
||||
.nrr_n(nrr_n),
|
||||
.ce_n(ce_n),
|
||||
.pce(pce),
|
||||
.vid_ltc(vid_ltc),
|
||||
.ram_clk(ram_clk),
|
||||
.brst(brst),
|
||||
.tpclk(tpclk),
|
||||
.cmp_blank(cmp_blank),
|
||||
.irq(irq),
|
||||
.inte(inte),
|
||||
.cmp_sync(cmp_sync),
|
||||
.hblank_n(hblank_n),
|
||||
.vblank_n(vblank_n),
|
||||
.hsync_n(hsync_n),
|
||||
.vsync_n(vsync_n)
|
||||
);
|
||||
|
||||
/////////////////// CPU ///////////////////
|
||||
|
||||
wire [15:0] addr;
|
||||
reg [7:0] cpu_din;
|
||||
wire [7:0] cpu_dout;
|
||||
wire wr_n;
|
||||
wire ready;
|
||||
wire hold;
|
||||
wire rd;
|
||||
wire sync;
|
||||
wire vait;
|
||||
wire hlda;
|
||||
wire pin_aena;
|
||||
wire pin_dena;
|
||||
|
||||
assign hold = 1'b0;
|
||||
assign ready = 1'b1;
|
||||
|
||||
vm80a_core cpu
|
||||
(
|
||||
.pin_clk(clk_sys),
|
||||
.pin_f1(~ph2),
|
||||
.pin_f2(ph2),
|
||||
.pin_reset(~cpu_rst_n),
|
||||
.pin_a(addr),
|
||||
.pin_dout(cpu_dout),
|
||||
.pin_din(cpu_din),
|
||||
.pin_aena (pin_aena),
|
||||
.pin_dena (pin_dena),
|
||||
.pin_hold(hold),
|
||||
.pin_ready(ready),
|
||||
.pin_int(irq),
|
||||
.pin_wr_n(wr_n),
|
||||
.pin_dbin(rd),
|
||||
.pin_inte(inte),
|
||||
.pin_hlda(hlda),
|
||||
.pin_wait(vait),
|
||||
.pin_sync(sync)
|
||||
);
|
||||
|
||||
//////// STATUS system control ////////////
|
||||
|
||||
reg[7:0] cpu_status;
|
||||
wire status_inta = cpu_status[0];
|
||||
//wire status_wo_n = cpu_status[1];
|
||||
//wire status_stack = cpu_status[2];
|
||||
//wire status_hlta = cpu_status[3];
|
||||
//wire status_out = cpu_status[4];
|
||||
//wire status_m1 = cpu_status[5];
|
||||
//wire status_inp = cpu_status[6];
|
||||
//wire status_memr = cpu_status[7];
|
||||
|
||||
always @(posedge clk_sys or negedge rst_n)
|
||||
begin
|
||||
reg old_sync;
|
||||
if (!rst_n)
|
||||
cpu_status <= 8'b0;
|
||||
else
|
||||
begin
|
||||
old_sync <= sync;
|
||||
if(~old_sync & sync)
|
||||
cpu_status <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
casez({status_inta, rom_e, ram_e, ~io_3800_r_n, ~io_3000_r_n})
|
||||
5'b1????: cpu_din <= 8'hFF;
|
||||
5'b00001: cpu_din <= io_rd_rtc_ad;
|
||||
5'b00010: cpu_din <= key_data;
|
||||
5'b00100: cpu_din <= ram_out;
|
||||
5'b01000: cpu_din <= rom_out;
|
||||
default: cpu_din <= 8'hFF;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
/////////////////// MEMORY ///////////////////
|
||||
// 1111110000000000
|
||||
// 5432109876543210
|
||||
// ROM A 0000H 0000000000000000
|
||||
// ROM B 0800H 0000100000000000
|
||||
// IO 10 1000H 0001000000000000
|
||||
// IO 18 1800H 0001100000000000
|
||||
// IO 20 2000H 0010000000000000
|
||||
// IO 28 2800H 0010100000000000
|
||||
// IO 30 3000H 0011000000000000
|
||||
// IO 38 3800H 0011100000000000
|
||||
// VRAM 4000H 0100000000000000
|
||||
// 49FFH 0100100111111111
|
||||
// RAM 4800H 0100101000000000
|
||||
|
||||
wire rom_e = ~addr[15] & ~addr[14] & ~addr[13] & ~addr[12] & ~addr[11];
|
||||
wire [7:0] rom_out;
|
||||
|
||||
dpram #(.ADDRWIDTH(12), .NUMWORDS(4096), .MEM_INIT_FILE("rtl/boot.mif")) rom
|
||||
(
|
||||
.clock(clk_sys),
|
||||
.address_a(ioctl_addr),
|
||||
.data_a(ioctl_data),
|
||||
.wren_a(rom_download && ioctl_wr),
|
||||
|
||||
.address_b(addr[11:0]),
|
||||
.q_b(rom_out)
|
||||
);
|
||||
|
||||
wire ram_e = ~addr[15] & addr[14];
|
||||
wire [7:0] ram_out;
|
||||
wire ram_w = ram_e & ~wr_n;
|
||||
wire [7:0] vid_out;
|
||||
|
||||
dpram #(.ADDRWIDTH(14)) ram
|
||||
(
|
||||
.clock(clk_sys),
|
||||
.address_a(addr[13:0]),
|
||||
.data_a(cpu_dout),
|
||||
.wren_a(ram_w),
|
||||
.q_a(ram_out),
|
||||
|
||||
.address_b({2'b0, vid_a[11:0]}),
|
||||
.q_b(vid_out)
|
||||
);
|
||||
|
||||
/////////////////// Memory Mapped IO Registers ///////////////////
|
||||
|
||||
// sure we could do this with some simple verilog conditionals, but digging the old-time TTL ICs
|
||||
|
||||
wire io_0000_r_n;
|
||||
wire io_0800_r_n;
|
||||
wire io_1000_r_n;
|
||||
wire io_1800_r_n;
|
||||
wire io_2000_r_n;
|
||||
wire io_2800_r_n;
|
||||
wire io_3000_r_n;
|
||||
wire io_3800_r_n;
|
||||
|
||||
wire io_0000_w_n;
|
||||
wire io_0800_w_n;
|
||||
wire io_1000_w_n;
|
||||
wire io_1800_w_n;
|
||||
wire io_2000_w_n;
|
||||
wire io_2800_w_n;
|
||||
wire io_3000_w_n;
|
||||
wire io_3800_w_n;
|
||||
|
||||
SN74LS138 IC25 (
|
||||
.a(addr[11]),
|
||||
.b(addr[12]),
|
||||
.c(addr[13]),
|
||||
.g1(rd),
|
||||
.g2an(addr[15]),
|
||||
.g2bn(addr[14]),
|
||||
.y0n(io_0000_r_n),
|
||||
.y1n(io_0800_r_n),
|
||||
.y2n(io_1000_r_n),
|
||||
.y3n(io_1800_r_n),
|
||||
.y4n(io_2000_r_n),
|
||||
.y5n(io_2800_r_n),
|
||||
.y6n(io_3000_r_n),
|
||||
.y7n(io_3800_r_n)
|
||||
);
|
||||
|
||||
SN74LS138 IC26 (
|
||||
.a(addr[11]),
|
||||
.b(addr[12]),
|
||||
.c(addr[13]),
|
||||
.g1(~wr_n),
|
||||
.g2an(addr[15]),
|
||||
.g2bn(addr[14]),
|
||||
.y0n(io_0000_w_n),
|
||||
.y1n(io_0800_w_n),
|
||||
.y2n(io_1000_w_n),
|
||||
.y3n(io_1800_w_n),
|
||||
.y4n(io_2000_w_n),
|
||||
.y5n(io_2800_w_n),
|
||||
.y6n(io_3000_w_n),
|
||||
.y7n(io_3800_w_n)
|
||||
);
|
||||
|
||||
|
||||
//wire [7:0] io_rd_rtc_ad = {(io_wr_misc[7:6] ? (io_wr_misc[7:6] == 2'b10 ? rtc[7] : 1'b0) : tape_flux), rtc[6:0]};
|
||||
wire [7:0] io_rd_rtc_ad;
|
||||
always_comb
|
||||
casez (io_wr_misc[7:3])
|
||||
5'b00111 : io_rd_rtc_ad = {tape_flux, rtc[6:0]};
|
||||
5'b10111 : io_rd_rtc_ad = rtc;
|
||||
5'b?1111 : io_rd_rtc_ad = {1'b0, rtc[6:0]};
|
||||
5'b??001 : io_rd_rtc_ad = joystick_0[4] ? 8'h00 : 8'h80;
|
||||
5'b??010 : io_rd_rtc_ad = {~joystick_analog_0[7], joystick_analog_0[6:0]};
|
||||
5'b??100 : io_rd_rtc_ad = joystick_1[4] ? 8'h00 : 8'h80;
|
||||
5'b??101 : io_rd_rtc_ad = {~joystick_analog_1[7], joystick_analog_1[6:0]};
|
||||
default: io_rd_rtc_ad = 8'h00;
|
||||
endcase
|
||||
|
||||
|
||||
wire rtc_clr = ~rst_n | io_wr_misc[6];
|
||||
reg [7:0] rtc;
|
||||
wire rtc_clk = io_wr_misc[6] ? 1'b0 : (io_wr_misc[7] ? pix_a : tpclk);
|
||||
|
||||
always@(negedge rtc_clk or posedge rtc_clr)
|
||||
begin
|
||||
if (rtc_clr)
|
||||
begin
|
||||
rtc <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rtc <= rtc + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
wire [7:0] keys [7:0];
|
||||
wire [7:0] key_data = keys[addr[3:0]];
|
||||
|
||||
keyboard keyboard
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
.rst_n(rst_n),
|
||||
.ps2_key(ps2_key),
|
||||
.joystick_0(joystick_0),
|
||||
.joystick_1(joystick_1),
|
||||
.keys(keys)
|
||||
);
|
||||
|
||||
|
||||
reg [7:0] io_wr_color_a_tape;
|
||||
reg [7:0] io_wr_color_b_snd;
|
||||
|
||||
reg [7:0] io_wr_sound_a [3:0];
|
||||
reg [7:0] io_wr_sound_b [3:0];
|
||||
|
||||
reg [7:0] io_wr_misc;
|
||||
|
||||
always@(posedge io_1000_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_color_a_tape <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_color_a_tape <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge io_1800_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_color_b_snd <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_color_b_snd <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge io_2000_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_sound_a[2'b00] <= 8'b0;
|
||||
io_wr_sound_a[2'b01] <= 8'b0;
|
||||
io_wr_sound_a[2'b10] <= 8'b0;
|
||||
io_wr_sound_a[2'b11] <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_sound_a[addr[1:0]] <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge io_2800_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_sound_b[2'b00] <= 8'b0;
|
||||
io_wr_sound_b[2'b01] <= 8'b0;
|
||||
io_wr_sound_b[2'b10] <= 8'b0;
|
||||
io_wr_sound_b[2'b11] <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_sound_b[addr[1:0]] <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge io_3000_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_misc <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_misc <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////// Video ///////////////////
|
||||
|
||||
|
||||
//// Test generator start
|
||||
|
||||
reg [7:0] vidtest_x;
|
||||
reg [7:0] vidtest_y;
|
||||
wire [6:0] vidtest_scanline = vid_a[11:5];
|
||||
|
||||
always@(posedge vid_ltc or negedge hblank_n)
|
||||
begin
|
||||
if (!hblank_n)
|
||||
vidtest_x <= 8'b0;
|
||||
else
|
||||
vidtest_x <= vidtest_x + 1'b1;
|
||||
end
|
||||
|
||||
always@(posedge hsync_n or negedge vblank_n)
|
||||
begin
|
||||
if (!vblank_n)
|
||||
vidtest_y <= 8'b0;
|
||||
else
|
||||
vidtest_y <= vidtest_y + 1'b1;
|
||||
end
|
||||
|
||||
//// Test generator end
|
||||
|
||||
|
||||
reg [7:0] pix_byte;
|
||||
wire pix_en = vid_sel & vid_ltc & ~(ce_n | pce);
|
||||
|
||||
always@(posedge pix_en or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
pix_byte <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
pix_byte <= vid_out;
|
||||
end
|
||||
end
|
||||
|
||||
reg [3:0] pix_nib;
|
||||
|
||||
always@(posedge vid_sel_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
pix_nib <= 4'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
pix_nib <= pix_byte[7:4];
|
||||
end
|
||||
end
|
||||
|
||||
reg [7:0] R;
|
||||
reg [7:0] G;
|
||||
reg [7:0] B;
|
||||
|
||||
wire [1:0] pix = vid_sel ? (pix_a ? pix_nib[3:2] : pix_nib[1:0]) : (pix_a ? pix_byte[3:2] : pix_byte[1:0]);
|
||||
|
||||
wire [2:0] cr [3:0];
|
||||
|
||||
assign cr[2'b00] = io_wr_color_a_tape[2:0];
|
||||
assign cr[2'b01] = io_wr_color_b_snd[2:0];
|
||||
assign cr[2'b10] = io_wr_color_a_tape[5:3];
|
||||
assign cr[2'b11] = io_wr_color_b_snd[5:3];
|
||||
|
||||
wire [2:0] color = cr[pix];
|
||||
wire color_intensity = (pix == 2'b10) ? io_wr_color_b_snd[6] : 1'b0;
|
||||
|
||||
wire test_pattern = status[6];
|
||||
|
||||
always@(posedge vid_ltc or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
R <= 8'b0;
|
||||
G <= 8'b0;
|
||||
B <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (cmp_blank)
|
||||
begin
|
||||
R <= 8'b0;
|
||||
G <= 8'b0;
|
||||
B <= 8'b0;
|
||||
end
|
||||
else if (test_pattern & (vidtest_x === 8'd0))
|
||||
begin
|
||||
R <= 8'h00; //darkgreen
|
||||
G <= 8'h64;
|
||||
B <= 8'h00;
|
||||
end
|
||||
else if (test_pattern & (vidtest_x === 8'd110))
|
||||
begin
|
||||
R <= 8'h7c; //lawngreen
|
||||
G <= 8'hfc;
|
||||
B <= 8'h00;
|
||||
end
|
||||
else if (test_pattern & (vidtest_scanline === 7'd0))
|
||||
begin
|
||||
R <= 8'h8A; //blueviolet
|
||||
G <= 8'h2B;
|
||||
B <= 8'hE2;
|
||||
end
|
||||
else if (test_pattern & (vidtest_scanline === 7'd75))
|
||||
begin
|
||||
R <= 8'h1e; //dodgerblue
|
||||
G <= 8'h90;
|
||||
B <= 8'hff;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (color_intensity)
|
||||
begin
|
||||
if (test_pattern)
|
||||
begin
|
||||
R <= 8'h7c; //lawngreen
|
||||
G <= 8'hfc;
|
||||
B <= 8'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
R <= {1'b0, {7{color[0]}}};
|
||||
G <= {1'b0, {7{color[1]}}};
|
||||
B <= {1'b0, {7{color[2]}}};
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
R <= {8{color[0]}};
|
||||
G <= {8{color[1]}};
|
||||
B <= {8{color[2]}};
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [2:0] scale = status[4:2];
|
||||
wire [2:0] sl = scale ? scale - 1'd1 : 3'd0;
|
||||
|
||||
assign VGA_F1 = 0;
|
||||
assign VGA_SL = sl[1:0];
|
||||
|
||||
video_mixer #(.LINE_LENGTH(112), .GAMMA(1)) video_mixer
|
||||
(
|
||||
.*,
|
||||
.ce_pix(vid_ltc),
|
||||
.HSync(~hsync_n),
|
||||
.VSync(~vsync_n),
|
||||
.HBlank(~hblank_n),
|
||||
.VBlank(~vblank_n),
|
||||
.hq2x(scale == 1),
|
||||
.scandoubler(|scale || forced_scandoubler)
|
||||
);
|
||||
|
||||
|
||||
//// Tape Loading
|
||||
|
||||
wire [15:0] tape_addr;
|
||||
wire [7:0] tape_data;
|
||||
reg [15:0] tape_end;
|
||||
|
||||
dpram #(.ADDRWIDTH(16)) tape
|
||||
(
|
||||
.clock(CLK_VIDEO),
|
||||
.address_a(ioctl_addr),
|
||||
.data_a(ioctl_data),
|
||||
.wren_a(tape_download && ioctl_wr),
|
||||
|
||||
.address_b(tape_addr),
|
||||
.q_b(tape_data)
|
||||
);
|
||||
|
||||
always@(posedge CLK_VIDEO or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
tape_end <= 16'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (tape_download) tape_end <= ioctl_addr;
|
||||
end
|
||||
end
|
||||
|
||||
wire tape_playing;
|
||||
wire tape_flux;
|
||||
|
||||
cassette cassette(
|
||||
.clk(clk_sys),
|
||||
.rst_n(rst_n),
|
||||
.play(tape_play),
|
||||
.rewind(tape_rewind),
|
||||
.playing(tape_playing),
|
||||
.motor(io_wr_color_a_tape[6]),
|
||||
|
||||
.tape_addr(tape_addr),
|
||||
.tape_data(tape_data),
|
||||
.tape_end(tape_end),
|
||||
|
||||
.flux(tape_flux),
|
||||
.audio(AUDIO_R)
|
||||
);
|
||||
|
||||
assign LED_USER = tape_playing;
|
||||
|
||||
endmodule
|
||||
36
Computer_MiST/Interact_MiST/Neuer Ordner/clean.bat
Normal file
36
Computer_MiST/Interact_MiST/Neuer Ordner/clean.bat
Normal file
@@ -0,0 +1,36 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
for /d %%i in (sys\*_sim) do rmdir /s /q "%%i"
|
||||
for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del *.cdf
|
||||
del *.rpt
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
pause
|
||||
12
Computer_MiST/Interact_MiST/Neuer Ordner/files.qip
Normal file
12
Computer_MiST/Interact_MiST/Neuer Ordner/files.qip
Normal file
@@ -0,0 +1,12 @@
|
||||
set_global_assignment -name VERILOG_FILE rtl/vm80a.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/dpram.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cassette.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/video_timing.v
|
||||
set_global_assignment -name SEARCH_PATH rtl/SN74LS
|
||||
set_global_assignment -name VERILOG_FILE rtl/SN74LS/SN74LS195.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/SN74LS/SN74LS73.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/SN74LS/SN74LS74.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/SN74LS/SN74LS92.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/SN74LS/SN74LS138.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE Interact.sv
|
||||
BIN
Computer_MiST/Interact_MiST/Neuer Ordner/rtl.rar
Normal file
BIN
Computer_MiST/Interact_MiST/Neuer Ordner/rtl.rar
Normal file
Binary file not shown.
337
Computer_MiST/Interact_MiST/Neuer Ordner/rtl/pll.qip
Normal file
337
Computer_MiST/Interact_MiST/Neuer Ordner/rtl/pll.qip
Normal file
@@ -0,0 +1,337 @@
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NTcuMjcyNzI=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::NjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NTU=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTQuMzE4MTg=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::NjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MjIw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::NDM0MCBwcw==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::ODAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MjEuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NTcuMjcyNzI3IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTQuMzE4MTgxIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MzIsMzEsMywyLGZhbHNlLGZhbHNlLHRydWUsdHJ1ZSw2LDUsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyMiwyMiwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDYwMDAsNjMwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
|
||||
|
||||
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
|
||||
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"]
|
||||
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim"
|
||||
255
Computer_MiST/Interact_MiST/Neuer Ordner/rtl/pll.v
Normal file
255
Computer_MiST/Interact_MiST/Neuer Ordner/rtl/pll.v
Normal file
@@ -0,0 +1,255 @@
|
||||
// megafunction wizard: %Altera PLL v17.0%
|
||||
// GENERATION: XML
|
||||
// pll.v
|
||||
|
||||
// Generated using ACDS version 17.0 602
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll (
|
||||
input wire refclk, // refclk.clk
|
||||
input wire rst, // reset.reset
|
||||
output wire outclk_0, // outclk0.clk
|
||||
output wire outclk_1, // outclk1.clk
|
||||
output wire locked // locked.export
|
||||
);
|
||||
|
||||
pll_0002 pll_inst (
|
||||
.refclk (refclk), // refclk.clk
|
||||
.rst (rst), // reset.reset
|
||||
.outclk_0 (outclk_0), // outclk0.clk
|
||||
.outclk_1 (outclk_1), // outclk1.clk
|
||||
.locked (locked) // locked.export
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2019 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
|
||||
// Retrieval info: <generic name="debug_print_output" value="false" />
|
||||
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
|
||||
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
|
||||
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
|
||||
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
|
||||
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
|
||||
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
|
||||
// Retrieval info: <generic name="gui_use_locked" value="true" />
|
||||
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
|
||||
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
|
||||
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency0" value="57.27272" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency1" value="14.31818" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg1" value="180.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift1" value="4340 ps" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency2" value="10.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency3" value="30.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency4" value="80.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency5" value="21.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
|
||||
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
|
||||
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
|
||||
// Retrieval info: <generic name="gui_en_reconf" value="false" />
|
||||
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
|
||||
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
|
||||
// Retrieval info: <generic name="gui_phout_division" value="1" />
|
||||
// Retrieval info: <generic name="gui_mif_generate" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
|
||||
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
|
||||
// Retrieval info: <generic name="gui_dps_num" value="1" />
|
||||
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
|
||||
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
|
||||
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
|
||||
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
|
||||
// Retrieval info: <generic name="gui_active_clk" value="false" />
|
||||
// Retrieval info: <generic name="gui_clk_bad" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
|
||||
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
|
||||
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
|
||||
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : pll.vo
|
||||
// RELATED_FILES: pll.v, pll_0002.v
|
||||
@@ -0,0 +1,4 @@
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
|
||||
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
90
Computer_MiST/Interact_MiST/Neuer Ordner/rtl/pll/pll_0002.v
Normal file
90
Computer_MiST/Interact_MiST/Neuer Ordner/rtl/pll/pll_0002.v
Normal file
@@ -0,0 +1,90 @@
|
||||
`timescale 1ns/10ps
|
||||
module pll_0002(
|
||||
|
||||
// interface 'refclk'
|
||||
input wire refclk,
|
||||
|
||||
// interface 'reset'
|
||||
input wire rst,
|
||||
|
||||
// interface 'outclk0'
|
||||
output wire outclk_0,
|
||||
|
||||
// interface 'outclk1'
|
||||
output wire outclk_1,
|
||||
|
||||
// interface 'locked'
|
||||
output wire locked
|
||||
);
|
||||
|
||||
altera_pll #(
|
||||
.fractional_vco_multiplier("false"),
|
||||
.reference_clock_frequency("50.0 MHz"),
|
||||
.operation_mode("direct"),
|
||||
.number_of_clocks(2),
|
||||
.output_clock_frequency0("57.272727 MHz"),
|
||||
.phase_shift0("0 ps"),
|
||||
.duty_cycle0(50),
|
||||
.output_clock_frequency1("14.318181 MHz"),
|
||||
.phase_shift1("0 ps"),
|
||||
.duty_cycle1(50),
|
||||
.output_clock_frequency2("0 MHz"),
|
||||
.phase_shift2("0 ps"),
|
||||
.duty_cycle2(50),
|
||||
.output_clock_frequency3("0 MHz"),
|
||||
.phase_shift3("0 ps"),
|
||||
.duty_cycle3(50),
|
||||
.output_clock_frequency4("0 MHz"),
|
||||
.phase_shift4("0 ps"),
|
||||
.duty_cycle4(50),
|
||||
.output_clock_frequency5("0 MHz"),
|
||||
.phase_shift5("0 ps"),
|
||||
.duty_cycle5(50),
|
||||
.output_clock_frequency6("0 MHz"),
|
||||
.phase_shift6("0 ps"),
|
||||
.duty_cycle6(50),
|
||||
.output_clock_frequency7("0 MHz"),
|
||||
.phase_shift7("0 ps"),
|
||||
.duty_cycle7(50),
|
||||
.output_clock_frequency8("0 MHz"),
|
||||
.phase_shift8("0 ps"),
|
||||
.duty_cycle8(50),
|
||||
.output_clock_frequency9("0 MHz"),
|
||||
.phase_shift9("0 ps"),
|
||||
.duty_cycle9(50),
|
||||
.output_clock_frequency10("0 MHz"),
|
||||
.phase_shift10("0 ps"),
|
||||
.duty_cycle10(50),
|
||||
.output_clock_frequency11("0 MHz"),
|
||||
.phase_shift11("0 ps"),
|
||||
.duty_cycle11(50),
|
||||
.output_clock_frequency12("0 MHz"),
|
||||
.phase_shift12("0 ps"),
|
||||
.duty_cycle12(50),
|
||||
.output_clock_frequency13("0 MHz"),
|
||||
.phase_shift13("0 ps"),
|
||||
.duty_cycle13(50),
|
||||
.output_clock_frequency14("0 MHz"),
|
||||
.phase_shift14("0 ps"),
|
||||
.duty_cycle14(50),
|
||||
.output_clock_frequency15("0 MHz"),
|
||||
.phase_shift15("0 ps"),
|
||||
.duty_cycle15(50),
|
||||
.output_clock_frequency16("0 MHz"),
|
||||
.phase_shift16("0 ps"),
|
||||
.duty_cycle16(50),
|
||||
.output_clock_frequency17("0 MHz"),
|
||||
.phase_shift17("0 ps"),
|
||||
.duty_cycle17(50),
|
||||
.pll_type("General"),
|
||||
.pll_subtype("General")
|
||||
) altera_pll_i (
|
||||
.rst (rst),
|
||||
.outclk ({outclk_1, outclk_0}),
|
||||
.locked (locked),
|
||||
.fboutclk ( ),
|
||||
.fbclk (1'b0),
|
||||
.refclk (refclk)
|
||||
);
|
||||
endmodule
|
||||
|
||||
157
Computer_MiST/Interact_MiST/Neuer Ordner/sys/alsa.sv
Normal file
157
Computer_MiST/Interact_MiST/Neuer Ordner/sys/alsa.sv
Normal file
@@ -0,0 +1,157 @@
|
||||
//============================================================================
|
||||
//
|
||||
// ALSA sound support for MiSTer
|
||||
// (c)2019,2020 Alexey Melnikov
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//
|
||||
//============================================================================
|
||||
|
||||
module alsa
|
||||
#(
|
||||
parameter CLK_RATE = 24576000
|
||||
)
|
||||
(
|
||||
input reset,
|
||||
input clk,
|
||||
|
||||
output reg [31:3] ram_address,
|
||||
input [63:0] ram_data,
|
||||
output reg ram_req = 0,
|
||||
input ram_ready,
|
||||
|
||||
input spi_ss,
|
||||
input spi_sck,
|
||||
input spi_mosi,
|
||||
output spi_miso,
|
||||
|
||||
output reg [15:0] pcm_l,
|
||||
output reg [15:0] pcm_r
|
||||
);
|
||||
|
||||
reg [60:0] buf_info;
|
||||
reg [6:0] spicnt = 0;
|
||||
always @(posedge spi_sck, posedge spi_ss) begin
|
||||
reg [95:0] spi_data;
|
||||
|
||||
if(spi_ss) spicnt <= 0;
|
||||
else begin
|
||||
spi_data[{spicnt[6:3],~spicnt[2:0]}] <= spi_mosi;
|
||||
if(&spicnt) buf_info <= {spi_data[82:67],spi_data[50:35],spi_data[31:3]};
|
||||
spicnt <= spicnt + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
assign spi_miso = spi_out[{spicnt[4:3],~spicnt[2:0]}];
|
||||
|
||||
reg [31:0] spi_out = 0;
|
||||
always @(posedge clk) if(spi_ss) spi_out <= {buf_rptr, hurryup, 8'h00};
|
||||
|
||||
|
||||
reg [31:3] buf_addr;
|
||||
reg [18:3] buf_len;
|
||||
reg [18:3] buf_wptr = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [60:0] data1,data2;
|
||||
|
||||
data1 <= buf_info;
|
||||
data2 <= data1;
|
||||
if(data2 == data1) {buf_wptr,buf_len,buf_addr} <= data2;
|
||||
end
|
||||
|
||||
reg [2:0] hurryup = 0;
|
||||
reg [18:3] buf_rptr = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [18:3] len = 0;
|
||||
reg [1:0] ready = 0;
|
||||
reg [63:0] readdata;
|
||||
reg got_first = 0;
|
||||
reg [7:0] ce_cnt = 0;
|
||||
reg [1:0] state = 0;
|
||||
|
||||
if(reset) begin
|
||||
ready <= 0;
|
||||
ce_cnt <= 0;
|
||||
state <= 0;
|
||||
got_first <= 0;
|
||||
len <= 0;
|
||||
end
|
||||
else begin
|
||||
|
||||
//ramp up
|
||||
if(len[18:14] && (hurryup < 1)) hurryup <= 1;
|
||||
if(len[18:16] && (hurryup < 2)) hurryup <= 2;
|
||||
if(len[18:17] && (hurryup < 4)) hurryup <= 4;
|
||||
|
||||
//ramp down
|
||||
if(!len[18:15] && (hurryup > 2)) hurryup <= 2;
|
||||
if(!len[18:13] && (hurryup > 1)) hurryup <= 1;
|
||||
if(!len[18:10]) hurryup <= 0;
|
||||
|
||||
if(ce_sample && ~&ce_cnt) ce_cnt <= ce_cnt + 1'd1;
|
||||
|
||||
case(state)
|
||||
0: if(!ce_sample) begin
|
||||
if(ready) begin
|
||||
if(ce_cnt) begin
|
||||
{readdata[31:0],pcm_r,pcm_l} <= readdata;
|
||||
ready <= ready - 1'd1;
|
||||
ce_cnt <= ce_cnt - 1'd1;
|
||||
end
|
||||
end
|
||||
else if(buf_rptr != buf_wptr) begin
|
||||
if(~got_first) begin
|
||||
buf_rptr <= buf_wptr;
|
||||
got_first <= 1;
|
||||
end
|
||||
else begin
|
||||
ram_address <= buf_addr + buf_rptr;
|
||||
ram_req <= ~ram_req;
|
||||
buf_rptr <= buf_rptr + 1'd1;
|
||||
len <= (buf_wptr < buf_rptr) ? (buf_len + buf_wptr - buf_rptr) : (buf_wptr - buf_rptr);
|
||||
state <= 1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
len <= 0;
|
||||
ce_cnt <= 0;
|
||||
hurryup <= 0;
|
||||
end
|
||||
end
|
||||
1: if(ram_ready) begin
|
||||
ready <= 2;
|
||||
readdata <= ram_data;
|
||||
if(buf_rptr >= buf_len) buf_rptr <= buf_rptr - buf_len;
|
||||
state <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg ce_sample;
|
||||
always @(posedge clk) begin
|
||||
reg [31:0] acc = 0;
|
||||
|
||||
ce_sample <= 0;
|
||||
acc <= acc + 48000 + {hurryup,6'd0};
|
||||
if(acc >= CLK_RATE) begin
|
||||
acc <= acc - CLK_RATE;
|
||||
ce_sample <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
302
Computer_MiST/Interact_MiST/Neuer Ordner/sys/arcade_video.v
Normal file
302
Computer_MiST/Interact_MiST/Neuer Ordner/sys/arcade_video.v
Normal file
@@ -0,0 +1,302 @@
|
||||
//============================================================================
|
||||
//
|
||||
// Copyright (C) 2017-2020 Sorgelig
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//
|
||||
//============================================================================
|
||||
|
||||
//////////////////////////////////////////////////////////
|
||||
// DW:
|
||||
// 6 : 2R 2G 2B
|
||||
// 8 : 3R 3G 2B
|
||||
// 9 : 3R 3G 3B
|
||||
// 12 : 4R 4G 4B
|
||||
// 24 : 8R 8G 8B
|
||||
|
||||
module arcade_video #(parameter WIDTH=320, DW=8, GAMMA=1)
|
||||
(
|
||||
input clk_video,
|
||||
input ce_pix,
|
||||
|
||||
input[DW-1:0] RGB_in,
|
||||
input HBlank,
|
||||
input VBlank,
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
output CLK_VIDEO,
|
||||
output CE_PIXEL,
|
||||
output [7:0] VGA_R,
|
||||
output [7:0] VGA_G,
|
||||
output [7:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output VGA_DE,
|
||||
output [1:0] VGA_SL,
|
||||
|
||||
input [2:0] fx,
|
||||
input forced_scandoubler,
|
||||
inout [21:0] gamma_bus
|
||||
);
|
||||
|
||||
assign CLK_VIDEO = clk_video;
|
||||
|
||||
wire hs_fix,vs_fix;
|
||||
sync_fix sync_v(CLK_VIDEO, HSync, hs_fix);
|
||||
sync_fix sync_h(CLK_VIDEO, VSync, vs_fix);
|
||||
|
||||
reg [DW-1:0] RGB_fix;
|
||||
|
||||
reg CE,HS,VS,HBL,VBL;
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg old_ce;
|
||||
old_ce <= ce_pix;
|
||||
CE <= 0;
|
||||
if(~old_ce & ce_pix) begin
|
||||
CE <= 1;
|
||||
HS <= hs_fix;
|
||||
if(~HS & hs_fix) VS <= vs_fix;
|
||||
|
||||
RGB_fix <= RGB_in;
|
||||
HBL <= HBlank;
|
||||
if(HBL & ~HBlank) VBL <= VBlank;
|
||||
end
|
||||
end
|
||||
|
||||
wire [7:0] R,G,B;
|
||||
|
||||
generate
|
||||
if(DW == 6) begin
|
||||
assign R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]};
|
||||
assign G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]};
|
||||
assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
|
||||
end
|
||||
else if(DW == 8) begin
|
||||
assign R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]};
|
||||
assign G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]};
|
||||
assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
|
||||
end
|
||||
else if(DW == 9) begin
|
||||
assign R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]};
|
||||
assign G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]};
|
||||
assign B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]};
|
||||
end
|
||||
else if(DW == 12) begin
|
||||
assign R = {RGB_fix[11:8],RGB_fix[11:8]};
|
||||
assign G = {RGB_fix[7:4],RGB_fix[7:4]};
|
||||
assign B = {RGB_fix[3:0],RGB_fix[3:0]};
|
||||
end
|
||||
else begin // 24
|
||||
assign R = RGB_fix[23:16];
|
||||
assign G = RGB_fix[15:8];
|
||||
assign B = RGB_fix[7:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign VGA_SL = sl[1:0];
|
||||
wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
|
||||
wire scandoubler = fx || forced_scandoubler;
|
||||
|
||||
video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer
|
||||
(
|
||||
.CLK_VIDEO(CLK_VIDEO),
|
||||
.ce_pix(CE),
|
||||
.CE_PIXEL(CE_PIXEL),
|
||||
|
||||
.scandoubler(scandoubler),
|
||||
.hq2x(fx==1),
|
||||
.gamma_bus(gamma_bus),
|
||||
|
||||
.R((DW!=24) ? R[7:4] : R),
|
||||
.G((DW!=24) ? G[7:4] : G),
|
||||
.B((DW!=24) ? B[7:4] : B),
|
||||
|
||||
.HSync (HS),
|
||||
.VSync (VS),
|
||||
.HBlank(HBL),
|
||||
.VBlank(VBL),
|
||||
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.VGA_DE(VGA_DE)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
//============================================================================
|
||||
//
|
||||
// Screen +90/-90 deg. rotation
|
||||
// Copyright (C) 2020 Sorgelig
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//
|
||||
//============================================================================
|
||||
|
||||
module screen_rotate
|
||||
(
|
||||
input CLK_VIDEO,
|
||||
input CE_PIXEL,
|
||||
|
||||
input [7:0] VGA_R,
|
||||
input [7:0] VGA_G,
|
||||
input [7:0] VGA_B,
|
||||
input VGA_HS,
|
||||
input VGA_VS,
|
||||
input VGA_DE,
|
||||
|
||||
input rotate_ccw,
|
||||
input no_rotate,
|
||||
|
||||
output FB_EN,
|
||||
output [4:0] FB_FORMAT,
|
||||
output [11:0] FB_WIDTH,
|
||||
output [11:0] FB_HEIGHT,
|
||||
output [31:0] FB_BASE,
|
||||
output [13:0] FB_STRIDE,
|
||||
input FB_VBL,
|
||||
input FB_LL,
|
||||
|
||||
output DDRAM_CLK,
|
||||
input DDRAM_BUSY,
|
||||
output [7:0] DDRAM_BURSTCNT,
|
||||
output [28:0] DDRAM_ADDR,
|
||||
output [63:0] DDRAM_DIN,
|
||||
output [7:0] DDRAM_BE,
|
||||
output DDRAM_WE,
|
||||
output DDRAM_RD
|
||||
);
|
||||
|
||||
parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB
|
||||
|
||||
assign DDRAM_CLK = CLK_VIDEO;
|
||||
assign DDRAM_BURSTCNT = 1;
|
||||
assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]};
|
||||
assign DDRAM_BE = ram_addr[2] ? 8'hF0 : 8'h0F;
|
||||
assign DDRAM_DIN = {ram_data,ram_data};
|
||||
assign DDRAM_WE = ram_wr;
|
||||
assign DDRAM_RD = 0;
|
||||
|
||||
assign FB_EN = fb_en[2];
|
||||
assign FB_FORMAT = 5'b00110;
|
||||
assign FB_BASE = {MEM_BASE,o_fb,23'd0};
|
||||
assign FB_WIDTH = vsz;
|
||||
assign FB_HEIGHT = hsz;
|
||||
assign FB_STRIDE = stride;
|
||||
|
||||
function [1:0] buf_next;
|
||||
input [1:0] a,b;
|
||||
begin
|
||||
buf_next = 1;
|
||||
if ((a==0 && b==1) || (a==1 && b==0)) buf_next = 2;
|
||||
if ((a==1 && b==2) || (a==2 && b==1)) buf_next = 0;
|
||||
end
|
||||
endfunction
|
||||
|
||||
reg [1:0] i_fb,o_fb;
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg old_vbl,old_vs;
|
||||
old_vbl <= FB_VBL;
|
||||
old_vs <= VGA_VS;
|
||||
|
||||
if(FB_LL) begin
|
||||
if(~old_vbl & FB_VBL) o_fb<={1'b0,~i_fb[0]};
|
||||
if(~old_vs & VGA_VS) i_fb<={1'b0,~i_fb[0]};
|
||||
end
|
||||
else begin
|
||||
if(~old_vbl & FB_VBL) o_fb<=buf_next(o_fb,i_fb);
|
||||
if(~old_vs & VGA_VS) i_fb<=buf_next(i_fb,o_fb);
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
fb_en = 0;
|
||||
end
|
||||
|
||||
reg [2:0] fb_en = 0;
|
||||
reg [11:0] hsz = 320, vsz = 240;
|
||||
reg [11:0] bwidth;
|
||||
reg [22:0] bufsize;
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg [11:0] hcnt = 0, vcnt = 0;
|
||||
reg old_vs, old_de;
|
||||
|
||||
if(CE_PIXEL) begin
|
||||
old_vs <= VGA_VS;
|
||||
old_de <= VGA_DE;
|
||||
|
||||
hcnt <= hcnt + 1'd1;
|
||||
if(~old_de & VGA_DE) begin
|
||||
hcnt <= 1;
|
||||
vcnt <= vcnt + 1'd1;
|
||||
end
|
||||
if(old_de & ~VGA_DE) hsz <= hcnt;
|
||||
if(~old_vs & VGA_VS) begin
|
||||
vsz <= vcnt;
|
||||
bwidth <= vcnt + 2'd3;
|
||||
vcnt <= 0;
|
||||
fb_en <= {fb_en[1:0], ~no_rotate};
|
||||
end
|
||||
if(old_vs & ~VGA_VS) bufsize <= hsz * stride;
|
||||
end
|
||||
end
|
||||
|
||||
wire [13:0] stride = {bwidth[11:2], 4'd0};
|
||||
|
||||
reg [22:0] ram_addr, next_addr;
|
||||
reg [31:0] ram_data;
|
||||
reg ram_wr;
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg [13:0] hcnt = 0;
|
||||
reg old_vs, old_de;
|
||||
|
||||
ram_wr <= 0;
|
||||
if(CE_PIXEL) begin
|
||||
old_vs <= VGA_VS;
|
||||
old_de <= VGA_DE;
|
||||
|
||||
if(~old_vs & VGA_VS) begin
|
||||
next_addr <= rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
|
||||
hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00};
|
||||
end
|
||||
if(VGA_DE) begin
|
||||
ram_wr <= 1;
|
||||
ram_data <= {VGA_B,VGA_G,VGA_R};
|
||||
ram_addr <= next_addr;
|
||||
next_addr <= rotate_ccw ? (next_addr - stride) : (next_addr + stride);
|
||||
end
|
||||
if(old_de & ~VGA_DE) begin
|
||||
next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt;
|
||||
hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
2577
Computer_MiST/Interact_MiST/Neuer Ordner/sys/ascal.vhd
Normal file
2577
Computer_MiST/Interact_MiST/Neuer Ordner/sys/ascal.vhd
Normal file
File diff suppressed because it is too large
Load Diff
296
Computer_MiST/Interact_MiST/Neuer Ordner/sys/audio_out.v
Normal file
296
Computer_MiST/Interact_MiST/Neuer Ordner/sys/audio_out.v
Normal file
@@ -0,0 +1,296 @@
|
||||
|
||||
module audio_out
|
||||
#(
|
||||
parameter CLK_RATE = 24576000
|
||||
)
|
||||
(
|
||||
input reset,
|
||||
input clk,
|
||||
|
||||
//0 - 48KHz, 1 - 96KHz
|
||||
input sample_rate,
|
||||
|
||||
input [31:0] flt_rate,
|
||||
input [39:0] cx,
|
||||
input [7:0] cx0,
|
||||
input [7:0] cx1,
|
||||
input [7:0] cx2,
|
||||
input [23:0] cy0,
|
||||
input [23:0] cy1,
|
||||
input [23:0] cy2,
|
||||
|
||||
input [4:0] att,
|
||||
input [1:0] mix,
|
||||
|
||||
input is_signed,
|
||||
input [15:0] core_l,
|
||||
input [15:0] core_r,
|
||||
|
||||
input [15:0] alsa_l,
|
||||
input [15:0] alsa_r,
|
||||
|
||||
// I2S
|
||||
output i2s_bclk,
|
||||
output i2s_lrclk,
|
||||
output i2s_data,
|
||||
|
||||
// SPDIF
|
||||
output spdif,
|
||||
|
||||
// Sigma-Delta DAC
|
||||
output dac_l,
|
||||
output dac_r
|
||||
);
|
||||
|
||||
localparam AUDIO_RATE = 48000;
|
||||
localparam AUDIO_DW = 16;
|
||||
|
||||
localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8;
|
||||
localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1;
|
||||
|
||||
wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0];
|
||||
|
||||
reg mclk_ce;
|
||||
always @(posedge clk) begin
|
||||
reg [31:0] cnt;
|
||||
|
||||
mclk_ce = 0;
|
||||
cnt = cnt + real_ce;
|
||||
if(cnt >= CLK_RATE) begin
|
||||
cnt = cnt - CLK_RATE;
|
||||
mclk_ce = 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg i2s_ce;
|
||||
always @(posedge clk) begin
|
||||
reg div;
|
||||
i2s_ce <= 0;
|
||||
if(mclk_ce) begin
|
||||
div <= ~div;
|
||||
i2s_ce <= div;
|
||||
end
|
||||
end
|
||||
|
||||
i2s i2s
|
||||
(
|
||||
.reset(reset),
|
||||
|
||||
.clk(clk),
|
||||
.ce(i2s_ce),
|
||||
|
||||
.sclk(i2s_bclk),
|
||||
.lrclk(i2s_lrclk),
|
||||
.sdata(i2s_data),
|
||||
|
||||
.left_chan(al),
|
||||
.right_chan(ar)
|
||||
);
|
||||
|
||||
spdif toslink
|
||||
(
|
||||
.rst_i(reset),
|
||||
|
||||
.clk_i(clk),
|
||||
.bit_out_en_i(mclk_ce),
|
||||
|
||||
.sample_i({ar,al}),
|
||||
.spdif_o(spdif)
|
||||
);
|
||||
|
||||
sigma_delta_dac #(15) sd_l
|
||||
(
|
||||
.CLK(clk),
|
||||
.RESET(reset),
|
||||
.DACin({~al[15], al[14:0]}),
|
||||
.DACout(dac_l)
|
||||
);
|
||||
|
||||
sigma_delta_dac #(15) sd_r
|
||||
(
|
||||
.CLK(clk),
|
||||
.RESET(reset),
|
||||
.DACin({~ar[15], ar[14:0]}),
|
||||
.DACout(dac_r)
|
||||
);
|
||||
|
||||
reg sample_ce;
|
||||
always @(posedge clk) begin
|
||||
reg [8:0] div = 0;
|
||||
reg [1:0] add = 0;
|
||||
|
||||
div <= div + add;
|
||||
if(!div) begin
|
||||
div <= 2'd1 << sample_rate;
|
||||
add <= 2'd1 << sample_rate;
|
||||
end
|
||||
|
||||
sample_ce <= !div;
|
||||
end
|
||||
|
||||
reg flt_ce;
|
||||
always @(posedge clk) begin
|
||||
reg [31:0] cnt = 0;
|
||||
|
||||
flt_ce = 0;
|
||||
cnt = cnt + {flt_rate[30:0],1'b0};
|
||||
if(cnt >= CLK_RATE) begin
|
||||
cnt = cnt - CLK_RATE;
|
||||
flt_ce = 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg [15:0] cl,cr;
|
||||
always @(posedge clk) begin
|
||||
reg [15:0] cl1,cl2;
|
||||
reg [15:0] cr1,cr2;
|
||||
|
||||
cl1 <= core_l; cl2 <= cl1;
|
||||
if(cl2 == cl1) cl <= cl2;
|
||||
|
||||
cr1 <= core_r; cr2 <= cr1;
|
||||
if(cr2 == cr1) cr <= cr2;
|
||||
end
|
||||
|
||||
reg a_en1 = 0, a_en2 = 0;
|
||||
always @(posedge clk, posedge reset) begin
|
||||
reg [1:0] dly1 = 0;
|
||||
reg [14:0] dly2 = 0;
|
||||
|
||||
if(reset) begin
|
||||
dly1 <= 0;
|
||||
dly2 <= 0;
|
||||
a_en1 <= 0;
|
||||
a_en2 <= 0;
|
||||
end
|
||||
else begin
|
||||
if(flt_ce) begin
|
||||
if(~&dly1) dly1 <= dly1 + 1'd1;
|
||||
else a_en1 <= 1;
|
||||
end
|
||||
|
||||
if(sample_ce) begin
|
||||
if(!dly2[13+sample_rate]) dly2 <= dly2 + 1'd1;
|
||||
else a_en2 <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [15:0] acl, acr;
|
||||
IIR_filter #(.use_params(0)) IIR_filter
|
||||
(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.ce(flt_ce & a_en1),
|
||||
.sample_ce(sample_ce),
|
||||
|
||||
.cx(cx),
|
||||
.cx0(cx0),
|
||||
.cx1(cx1),
|
||||
.cx2(cx2),
|
||||
.cy0(cy0),
|
||||
.cy1(cy1),
|
||||
.cy2(cy2),
|
||||
|
||||
.input_l({~is_signed ^ cl[15], cl[14:0]}),
|
||||
.input_r({~is_signed ^ cr[15], cr[14:0]}),
|
||||
.output_l(acl),
|
||||
.output_r(acr)
|
||||
);
|
||||
|
||||
wire [15:0] adl;
|
||||
DC_blocker dcb_l
|
||||
(
|
||||
.clk(clk),
|
||||
.ce(sample_ce),
|
||||
.sample_rate(sample_rate),
|
||||
.mute(~a_en2),
|
||||
.din(acl),
|
||||
.dout(adl)
|
||||
);
|
||||
|
||||
wire [15:0] adr;
|
||||
DC_blocker dcb_r
|
||||
(
|
||||
.clk(clk),
|
||||
.ce(sample_ce),
|
||||
.sample_rate(sample_rate),
|
||||
.mute(~a_en2),
|
||||
.din(acr),
|
||||
.dout(adr)
|
||||
);
|
||||
|
||||
wire [15:0] al, audio_l_pre;
|
||||
aud_mix_top audmix_l
|
||||
(
|
||||
.clk(clk),
|
||||
.ce(sample_ce),
|
||||
.att(att),
|
||||
.mix(mix),
|
||||
|
||||
.core_audio(adl),
|
||||
.pre_in(audio_r_pre),
|
||||
.linux_audio(alsa_l),
|
||||
|
||||
.pre_out(audio_l_pre),
|
||||
.out(al)
|
||||
);
|
||||
|
||||
wire [15:0] ar, audio_r_pre;
|
||||
aud_mix_top audmix_r
|
||||
(
|
||||
.clk(clk),
|
||||
.ce(sample_ce),
|
||||
.att(att),
|
||||
.mix(mix),
|
||||
|
||||
.core_audio(adr),
|
||||
.pre_in(audio_l_pre),
|
||||
.linux_audio(alsa_r),
|
||||
|
||||
.pre_out(audio_r_pre),
|
||||
.out(ar)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
module aud_mix_top
|
||||
(
|
||||
input clk,
|
||||
input ce,
|
||||
|
||||
input [4:0] att,
|
||||
input [1:0] mix,
|
||||
|
||||
input [15:0] core_audio,
|
||||
input [15:0] linux_audio,
|
||||
input [15:0] pre_in,
|
||||
|
||||
output reg [15:0] pre_out = 0,
|
||||
output reg [15:0] out = 0
|
||||
);
|
||||
|
||||
reg signed [16:0] a1, a2, a3, a4;
|
||||
always @(posedge clk) if (ce) begin
|
||||
|
||||
a1 <= {core_audio[15],core_audio};
|
||||
a2 <= a1 + {linux_audio[15],linux_audio};
|
||||
|
||||
pre_out <= a2[16:1];
|
||||
|
||||
case(mix)
|
||||
0: a3 <= a2;
|
||||
1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
|
||||
2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
|
||||
3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
|
||||
endcase
|
||||
|
||||
if(att[4]) a4 <= 0;
|
||||
else a4 <= a3 >>> att[3:0];
|
||||
|
||||
//clamping
|
||||
out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
|
||||
end
|
||||
|
||||
endmodule
|
||||
73
Computer_MiST/Interact_MiST/Neuer Ordner/sys/build_id.tcl
Normal file
73
Computer_MiST/Interact_MiST/Neuer Ordner/sys/build_id.tcl
Normal file
@@ -0,0 +1,73 @@
|
||||
|
||||
# Build TimeStamp Verilog Module
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
# Sorgelig - 02/11/2019
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\""
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "build_id.v"
|
||||
|
||||
set fileData ""
|
||||
if { [file exists $outputFileName]} {
|
||||
set outputFile [open $outputFileName "r"]
|
||||
set fileData [read $outputFile]
|
||||
close $outputFile
|
||||
}
|
||||
|
||||
if {$buildDate ne $fileData} {
|
||||
set outputFile [open $outputFileName "w"]
|
||||
puts -nonewline $outputFile $buildDate
|
||||
close $outputFile
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated: [pwd]/$outputFileName: $buildDate"
|
||||
}
|
||||
}
|
||||
|
||||
# Build CDF file
|
||||
# Sorgelig - 17/2/2018
|
||||
proc generateCDF {revision device outpath} {
|
||||
|
||||
set outputFileName "jtag.cdf"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
puts $outputFile "JedecChain;"
|
||||
puts $outputFile " FileRevision(JESD32A);"
|
||||
puts $outputFile " DefaultMfr(6E);"
|
||||
puts $outputFile ""
|
||||
puts $outputFile " P ActionCode(Ign)"
|
||||
puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
|
||||
puts $outputFile " P ActionCode(Cfg)"
|
||||
puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
|
||||
puts $outputFile "ChainEnd;"
|
||||
puts $outputFile ""
|
||||
puts $outputFile "AlteraBegin;"
|
||||
puts $outputFile " ChainType(JTAG);"
|
||||
puts $outputFile "AlteraEnd;"
|
||||
}
|
||||
|
||||
set project_name [lindex $quartus(args) 1]
|
||||
set revision [lindex $quartus(args) 2]
|
||||
|
||||
if {[project_exists $project_name]} {
|
||||
if {[string equal "" $revision]} {
|
||||
project_open $project_name -revision [get_current_revision $project_name]
|
||||
} else {
|
||||
project_open $project_name -revision $revision
|
||||
}
|
||||
} else {
|
||||
post_message -type error "Project $project_name does not exist"
|
||||
exit
|
||||
}
|
||||
|
||||
set device [get_global_assignment -name DEVICE]
|
||||
set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
|
||||
|
||||
if [is_project_open] {
|
||||
project_close
|
||||
}
|
||||
|
||||
generateBuildID_Verilog
|
||||
generateCDF $revision $device $outpath
|
||||
108
Computer_MiST/Interact_MiST/Neuer Ordner/sys/ddr_svc.sv
Normal file
108
Computer_MiST/Interact_MiST/Neuer Ordner/sys/ddr_svc.sv
Normal file
@@ -0,0 +1,108 @@
|
||||
//
|
||||
// Copyright (c) 2020 Alexey Melnikov
|
||||
//
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// ------------------------------------------
|
||||
//
|
||||
|
||||
// 16-bit version
|
||||
|
||||
module ddr_svc
|
||||
(
|
||||
input clk,
|
||||
|
||||
input ram_waitrequest,
|
||||
output [7:0] ram_burstcnt,
|
||||
output [28:0] ram_addr,
|
||||
input [63:0] ram_readdata,
|
||||
input ram_read_ready,
|
||||
output reg ram_read,
|
||||
output [63:0] ram_writedata,
|
||||
output [7:0] ram_byteenable,
|
||||
output reg ram_write,
|
||||
|
||||
output [7:0] ram_bcnt,
|
||||
|
||||
input [31:3] ch0_addr,
|
||||
input [7:0] ch0_burst,
|
||||
output [63:0] ch0_data,
|
||||
input ch0_req,
|
||||
output ch0_ready,
|
||||
|
||||
input [31:3] ch1_addr,
|
||||
input [7:0] ch1_burst,
|
||||
output [63:0] ch1_data,
|
||||
input ch1_req,
|
||||
output ch1_ready
|
||||
);
|
||||
|
||||
assign ram_burstcnt = ram_burst;
|
||||
assign ram_byteenable = 8'hFF;
|
||||
assign ram_addr = ram_address;
|
||||
assign ram_writedata = 0;
|
||||
|
||||
assign ch0_data = ram_q[0];
|
||||
assign ch1_data = ram_q[1];
|
||||
assign ch0_ready = ready[0];
|
||||
assign ch1_ready = ready[1];
|
||||
|
||||
reg [7:0] ram_burst;
|
||||
reg [63:0] ram_q[2];
|
||||
reg [31:3] ram_address;
|
||||
reg [1:0] ack = 0;
|
||||
reg [1:0] ready;
|
||||
reg state = 0;
|
||||
reg ch = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
ready <= 0;
|
||||
|
||||
if(!ram_waitrequest) begin
|
||||
ram_read <= 0;
|
||||
ram_write <= 0;
|
||||
|
||||
case(state)
|
||||
0: if(ch0_req != ack[0]) begin
|
||||
ack[0] <= ch0_req;
|
||||
ram_address <= ch0_addr;
|
||||
ram_burst <= ch0_burst;
|
||||
ram_read <= 1;
|
||||
ch <= 0;
|
||||
ram_bcnt <= 8'hFF;
|
||||
state <= 1;
|
||||
end
|
||||
else if(ch1_req != ack[1]) begin
|
||||
ack[1] <= ch1_req;
|
||||
ram_address <= ch1_addr;
|
||||
ram_burst <= ch1_burst;
|
||||
ram_read <= 1;
|
||||
ch <= 1;
|
||||
ram_bcnt <= 8'hFF;
|
||||
state <= 1;
|
||||
end
|
||||
1: begin
|
||||
if(ram_read_ready) begin
|
||||
ram_bcnt <= ram_bcnt + 1'd1;
|
||||
ram_q[ch] <= ram_readdata;
|
||||
ready[ch] <= 1;
|
||||
if ((ram_bcnt+2'd2) == ram_burst) state <= 0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,250 @@
|
||||
// ============================================================================
|
||||
//
|
||||
// f2sdram_safe_terminator for MiSTer platform
|
||||
//
|
||||
// ============================================================================
|
||||
// Copyright (c) 2021 bellwood420
|
||||
//
|
||||
// Background:
|
||||
//
|
||||
// Terminating a transaction of burst writing(/reading) in its midstream
|
||||
// seems to cause an illegal state to f2sdram interface.
|
||||
//
|
||||
// Forced reset request that occurs when loading other core is inevitable.
|
||||
//
|
||||
// So if it happens exactly within the transaction period,
|
||||
// unexpected issues with accessing to f2sdram interface will be caused
|
||||
// in next loaded core.
|
||||
//
|
||||
// It seems that only way to reset broken f2sdram interface is to reset
|
||||
// whole SDRAM Controller Subsystem from HPS via permodrst register
|
||||
// in Reset Manager.
|
||||
// But it cannot be done safely while Linux is running.
|
||||
// It is usually done when cold or warm reset is issued in HPS.
|
||||
//
|
||||
// Main_MiSTer is issuing reset for FPGA <> HPS bridges
|
||||
// via brgmodrst register in Reset Manager when loading rbf.
|
||||
// But it has no effect on f2sdram interface.
|
||||
// f2sdram interface seems to belong to SDRAM Controller Subsystem
|
||||
// rather than FPGA-to-HPS bridge.
|
||||
//
|
||||
// Main_MiSTer is also trying to issuing reset for f2sdram ports
|
||||
// via fpgaportrst register in SDRAM Controller Subsystem when loading rbf.
|
||||
// But according to the Intel's document, fpgaportrst register can be
|
||||
// used to stretch the port reset.
|
||||
// It seems that it cannot be used to assert the port reset.
|
||||
//
|
||||
// According to the Intel's document, there seems to be a reset port on
|
||||
// Avalon-MM slave interface, but it cannot be found in Qsys generated HDL.
|
||||
//
|
||||
// To conclude, the only thing FPGA can do is not to break the transaction.
|
||||
// ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
//
|
||||
// Purpose:
|
||||
// To prevent the issue, this module completes ongoing transaction
|
||||
// on behalf of user logic, when reset is asserted.
|
||||
//
|
||||
// Usage:
|
||||
// Insert this module into the bus line between
|
||||
// f2sdram (Avalon-MM slave) and user logic (Avalon-MM master).
|
||||
//
|
||||
// Notice:
|
||||
// Asynchronous reset request is not supported.
|
||||
// Please feed reset request synchronized to clock.
|
||||
//
|
||||
module f2sdram_safe_terminator #(
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter BURSTCOUNT_WIDTH = 8
|
||||
) (
|
||||
// clk should be the same as one provided to f2sdram port
|
||||
// clk should not be stop when reset is asserted
|
||||
input clk,
|
||||
// rst_req_sync should be synchronized to clk
|
||||
// Asynchronous reset request is not supported
|
||||
input rst_req_sync,
|
||||
|
||||
// Master port: connecting to Alavon-MM slave(f2sdram)
|
||||
input waitrequest_master,
|
||||
output [BURSTCOUNT_WIDTH-1:0] burstcount_master,
|
||||
output [ADDRESS_WITDH-1:0] address_master,
|
||||
input [DATA_WIDTH-1:0] readdata_master,
|
||||
input readdatavalid_master,
|
||||
output read_master,
|
||||
output [DATA_WIDTH-1:0] writedata_master,
|
||||
output [BYTEENABLE_WIDTH-1:0] byteenable_master,
|
||||
output write_master,
|
||||
|
||||
// Slave port: connecting to Alavon-MM master(user logic)
|
||||
output waitrequest_slave,
|
||||
input [BURSTCOUNT_WIDTH-1:0] burstcount_slave,
|
||||
input [ADDRESS_WITDH-1:0] address_slave,
|
||||
output [DATA_WIDTH-1:0] readdata_slave,
|
||||
output readdatavalid_slave,
|
||||
input read_slave,
|
||||
input [DATA_WIDTH-1:0] writedata_slave,
|
||||
input [BYTEENABLE_WIDTH-1:0] byteenable_slave,
|
||||
input write_slave
|
||||
);
|
||||
|
||||
localparam BYTEENABLE_WIDTH = DATA_WIDTH/8;
|
||||
localparam ADDRESS_WITDH = 32-$clog2(BYTEENABLE_WIDTH);
|
||||
|
||||
/*
|
||||
* Capture init reset deaseert
|
||||
*/
|
||||
reg init_reset_deasserted = 1'b0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (!rst_req_sync) begin
|
||||
init_reset_deasserted <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* Lock stage
|
||||
*/
|
||||
reg lock_stage = 1'b0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst_req_sync) begin
|
||||
// Reset assert
|
||||
if (init_reset_deasserted) begin
|
||||
lock_stage <= 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
// Reset deassert
|
||||
lock_stage <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* Write burst transaction observer
|
||||
*/
|
||||
reg state_write = 1'b0;
|
||||
wire next_state_write;
|
||||
|
||||
wire burst_write_start = !state_write && next_state_write;
|
||||
wire valid_write_data = state_write && !waitrequest_master;
|
||||
wire burst_write_end = state_write && (write_burstcounter == write_burstcount_latch - 1'd1);
|
||||
wire valid_non_burst_write = !state_write && write_slave && (burstcount_slave == 1) && !waitrequest_master;
|
||||
|
||||
reg [BURSTCOUNT_WIDTH-1:0] write_burstcounter = 0;
|
||||
reg [BURSTCOUNT_WIDTH-1:0] write_burstcount_latch = 0;
|
||||
reg [ADDRESS_WITDH-1:0] write_address_latch = 0;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
state_write <= next_state_write;
|
||||
|
||||
if (burst_write_start) begin
|
||||
write_burstcounter <= waitrequest_master ? 1'd0 : 1'd1;
|
||||
write_burstcount_latch <= burstcount_slave;
|
||||
write_address_latch <= address_slave;
|
||||
end
|
||||
else if (valid_write_data) begin
|
||||
write_burstcounter <= write_burstcounter + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
if (!state_write) begin
|
||||
if (valid_non_burst_write)
|
||||
next_state_write = 1'b0;
|
||||
else if (write_slave)
|
||||
next_state_write = 1'b1;
|
||||
else
|
||||
next_state_write = 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (burst_write_end)
|
||||
next_state_write = 1'b0;
|
||||
else
|
||||
next_state_write = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
reg [BURSTCOUNT_WIDTH-1:0] write_terminate_counter = 0;
|
||||
reg [BURSTCOUNT_WIDTH-1:0] burstcount_latch = 0;
|
||||
reg [ADDRESS_WITDH-1:0] address_latch = 0;
|
||||
|
||||
reg terminating = 0;
|
||||
reg read_terminating = 0;
|
||||
reg write_terminating = 0;
|
||||
|
||||
wire on_write_transaction = state_write && next_state_write;
|
||||
wire on_start_write_transaction = !state_write && next_state_write;
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst_req_sync) begin
|
||||
// Reset assert
|
||||
if (init_reset_deasserted) begin
|
||||
if (!lock_stage) begin
|
||||
// Even not knowing reading is in progress or not,
|
||||
// if it is in progress, it will finish at some point, and no need to do anything.
|
||||
// Assume that reading is in progress when we are not on write transaction.
|
||||
burstcount_latch <= burstcount_slave;
|
||||
address_latch <= address_slave;
|
||||
terminating <= 1;
|
||||
|
||||
if (on_write_transaction) begin
|
||||
write_terminating <= 1;
|
||||
burstcount_latch <= write_burstcount_latch;
|
||||
address_latch <= write_address_latch;
|
||||
write_terminate_counter <= waitrequest_master ? write_burstcounter : write_burstcounter + 1'd1;
|
||||
end
|
||||
else if (on_start_write_transaction) begin
|
||||
if (!valid_non_burst_write) begin
|
||||
write_terminating <= 1;
|
||||
write_terminate_counter <= waitrequest_master ? 1'd0 : 1'd1;
|
||||
end
|
||||
end
|
||||
else if (read_slave && waitrequest_master) begin
|
||||
// Need to keep read signal, burstcount and address until waitrequest_master deasserted
|
||||
read_terminating <= 1;
|
||||
end
|
||||
end
|
||||
else if (!waitrequest_master) begin
|
||||
read_terminating <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
// Reset deassert
|
||||
if (!write_terminating) terminating <= 0;
|
||||
read_terminating <= 0;
|
||||
end
|
||||
|
||||
if (write_terminating) begin
|
||||
// Continue write transaction until the end
|
||||
if (!waitrequest_master) write_terminate_counter <= write_terminate_counter + 1'd1;
|
||||
if (write_terminate_counter == burstcount_latch - 1'd1) write_terminating <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* Bus mux depending on the stage.
|
||||
*/
|
||||
always_comb begin
|
||||
if (terminating) begin
|
||||
burstcount_master = burstcount_latch;
|
||||
address_master = address_latch;
|
||||
read_master = read_terminating;
|
||||
write_master = write_terminating;
|
||||
byteenable_master = 0;
|
||||
end
|
||||
else begin
|
||||
burstcount_master = burstcount_slave;
|
||||
address_master = address_slave;
|
||||
read_master = read_slave;
|
||||
byteenable_master = byteenable_slave;
|
||||
write_master = write_slave;
|
||||
end
|
||||
end
|
||||
|
||||
// Just passing master <-> slave
|
||||
assign writedata_master = writedata_slave;
|
||||
assign readdata_slave = readdata_master;
|
||||
assign readdatavalid_slave = readdatavalid_master;
|
||||
assign waitrequest_slave = waitrequest_master;
|
||||
|
||||
endmodule
|
||||
124
Computer_MiST/Interact_MiST/Neuer Ordner/sys/gamma_corr.sv
Normal file
124
Computer_MiST/Interact_MiST/Neuer Ordner/sys/gamma_corr.sv
Normal file
@@ -0,0 +1,124 @@
|
||||
module gamma_corr
|
||||
(
|
||||
input clk_sys,
|
||||
input clk_vid,
|
||||
input ce_pix,
|
||||
input gamma_en,
|
||||
input gamma_wr,
|
||||
input [9:0] gamma_wr_addr,
|
||||
input [7:0] gamma_value,
|
||||
input HSync,
|
||||
input VSync,
|
||||
input HBlank,
|
||||
input VBlank,
|
||||
input [23:0] RGB_in,
|
||||
output reg HSync_out,
|
||||
output reg VSync_out,
|
||||
output reg HBlank_out,
|
||||
output reg VBlank_out,
|
||||
output reg [23:0] RGB_out
|
||||
);
|
||||
|
||||
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve[768];
|
||||
|
||||
always @(posedge clk_sys) if (gamma_wr) gamma_curve[gamma_wr_addr] <= gamma_value;
|
||||
always @(posedge clk_vid) gamma <= gamma_curve[gamma_index];
|
||||
|
||||
reg [9:0] gamma_index;
|
||||
reg [7:0] gamma;
|
||||
|
||||
always @(posedge clk_vid) begin
|
||||
reg [7:0] R_in, G_in, B_in;
|
||||
reg [7:0] R_gamma, G_gamma;
|
||||
reg hs,vs,hb,vb;
|
||||
reg [1:0] ctr = 0;
|
||||
reg old_ce;
|
||||
|
||||
old_ce <= ce_pix;
|
||||
if(~old_ce & ce_pix) begin
|
||||
{R_in,G_in,B_in} <= RGB_in;
|
||||
hs <= HSync; vs <= VSync;
|
||||
hb <= HBlank; vb <= VBlank;
|
||||
|
||||
RGB_out <= gamma_en ? {R_gamma,G_gamma,gamma} : {R_in,G_in,B_in};
|
||||
HSync_out <= hs; VSync_out <= vs;
|
||||
HBlank_out <= hb; VBlank_out <= vb;
|
||||
|
||||
ctr <= 1;
|
||||
gamma_index <= {2'b00,RGB_in[23:16]};
|
||||
end
|
||||
|
||||
if (|ctr) ctr <= ctr + 1'd1;
|
||||
|
||||
case(ctr)
|
||||
1: begin gamma_index <= {2'b01,G_in}; end
|
||||
2: begin R_gamma <= gamma; gamma_index <= {2'b10,B_in}; end
|
||||
3: begin G_gamma <= gamma; end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module gamma_fast
|
||||
(
|
||||
input clk_vid,
|
||||
input ce_pix,
|
||||
|
||||
inout [21:0] gamma_bus,
|
||||
|
||||
input HSync,
|
||||
input VSync,
|
||||
input HBlank,
|
||||
input VBlank,
|
||||
input DE,
|
||||
input [23:0] RGB_in,
|
||||
|
||||
output reg HSync_out,
|
||||
output reg VSync_out,
|
||||
output reg HBlank_out,
|
||||
output reg VBlank_out,
|
||||
output reg DE_out,
|
||||
output reg [23:0] RGB_out
|
||||
);
|
||||
|
||||
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_r[256];
|
||||
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_g[256];
|
||||
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_b[256];
|
||||
|
||||
assign gamma_bus[21] = 1;
|
||||
wire clk_sys = gamma_bus[20];
|
||||
wire gamma_en = gamma_bus[19];
|
||||
wire gamma_wr = gamma_bus[18];
|
||||
wire [9:0] gamma_wr_addr = gamma_bus[17:8];
|
||||
wire [7:0] gamma_value = gamma_bus[7:0];
|
||||
|
||||
always @(posedge clk_sys) if (gamma_wr) begin
|
||||
case(gamma_wr_addr[9:8])
|
||||
0: gamma_curve_r[gamma_wr_addr[7:0]] <= gamma_value;
|
||||
1: gamma_curve_g[gamma_wr_addr[7:0]] <= gamma_value;
|
||||
2: gamma_curve_b[gamma_wr_addr[7:0]] <= gamma_value;
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [7:0] gamma_index_r,gamma_index_g,gamma_index_b;
|
||||
|
||||
always @(posedge clk_vid) begin
|
||||
reg [7:0] R_in, G_in, B_in;
|
||||
reg [7:0] R_gamma, G_gamma;
|
||||
reg hs,vs,hb,vb,de;
|
||||
|
||||
if(ce_pix) begin
|
||||
{gamma_index_r,gamma_index_g,gamma_index_b} <= RGB_in;
|
||||
hs <= HSync; vs <= VSync;
|
||||
hb <= HBlank; vb <= VBlank;
|
||||
de <= DE;
|
||||
|
||||
RGB_out <= gamma_en ? {gamma_curve_r[gamma_index_r],gamma_curve_g[gamma_index_g],gamma_curve_b[gamma_index_b]}
|
||||
: {gamma_index_r,gamma_index_g,gamma_index_b};
|
||||
HSync_out <= hs; VSync_out <= vs;
|
||||
HBlank_out <= hb; VBlank_out <= vb;
|
||||
DE_out <= de;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
239
Computer_MiST/Interact_MiST/Neuer Ordner/sys/hdmi_config.sv
Normal file
239
Computer_MiST/Interact_MiST/Neuer Ordner/sys/hdmi_config.sv
Normal file
@@ -0,0 +1,239 @@
|
||||
|
||||
module hdmi_config
|
||||
(
|
||||
// Host Side
|
||||
input iCLK,
|
||||
input iRST_N,
|
||||
|
||||
input dvi_mode,
|
||||
input audio_96k,
|
||||
input [1:0] limited,
|
||||
input ypbpr,
|
||||
|
||||
output reg done,
|
||||
|
||||
// I2C Side
|
||||
output I2C_SCL,
|
||||
inout I2C_SDA
|
||||
);
|
||||
|
||||
// Internal Registers/Wires
|
||||
reg mI2C_GO = 0;
|
||||
wire mI2C_END;
|
||||
wire mI2C_ACK;
|
||||
reg [15:0] LUT_DATA;
|
||||
reg [7:0] LUT_INDEX = 0;
|
||||
|
||||
i2c #(50_000_000, 20_000) i2c_av
|
||||
(
|
||||
.CLK(iCLK),
|
||||
|
||||
.I2C_SCL(I2C_SCL), // I2C CLOCK
|
||||
.I2C_SDA(I2C_SDA), // I2C DATA
|
||||
|
||||
.I2C_ADDR('h39), // 0x39 is the Slave Address of the ADV7513 chip!
|
||||
.I2C_WLEN(1),
|
||||
.I2C_WDATA1(init_data[LUT_INDEX][15:8]), // SUB_ADDR
|
||||
.I2C_WDATA2(init_data[LUT_INDEX][7:0]), // DATA
|
||||
.START(mI2C_GO), // START transfer
|
||||
.READ(0),
|
||||
.END(mI2C_END), // END transfer
|
||||
.ACK(mI2C_ACK) // ACK
|
||||
);
|
||||
|
||||
////////////////////// Config Control ////////////////////////////
|
||||
always@(posedge iCLK or negedge iRST_N) begin
|
||||
reg [1:0] mSetup_ST = 0;
|
||||
|
||||
if(!iRST_N) begin
|
||||
LUT_INDEX <= 0;
|
||||
mSetup_ST <= 0;
|
||||
mI2C_GO <= 0;
|
||||
done <= 0;
|
||||
end else begin
|
||||
if(init_data[LUT_INDEX] != 16'hFFFF) begin
|
||||
case(mSetup_ST)
|
||||
0: begin
|
||||
mI2C_GO <= 1;
|
||||
mSetup_ST <= 1;
|
||||
end
|
||||
1: if(~mI2C_END) mSetup_ST <= 2;
|
||||
2: begin
|
||||
mI2C_GO <= 0;
|
||||
if(mI2C_END) begin
|
||||
mSetup_ST <= 0;
|
||||
if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else done <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
///////////////////// Config Data LUT //////////////////////////
|
||||
|
||||
wire [15:0] init_data[82] =
|
||||
'{
|
||||
16'h9803, // ADI required Write.
|
||||
|
||||
{8'hD6, 8'b1100_0000}, // [7:6] HPD Control...
|
||||
// 00 = HPD is from both HPD pin or CDC HPD
|
||||
// 01 = HPD is from CDC HPD
|
||||
// 10 = HPD is from HPD pin
|
||||
// 11 = HPD is always high
|
||||
|
||||
16'h4110, // Power Down control
|
||||
16'h9A70, // ADI required Write.
|
||||
16'h9C30, // ADI required Write.
|
||||
{8'h9D, 8'b0110_0001}, // [7:4] must be b0110!.
|
||||
// [3:2] b00 = Input clock not divided. b01 = Clk divided by 2. b10 = Clk divided by 4. b11 = invalid!
|
||||
// [1:0] must be b01!
|
||||
16'hA2A4, // ADI required Write.
|
||||
16'hA3A4, // ADI required Write.
|
||||
16'hE0D0, // ADI required Write.
|
||||
|
||||
|
||||
16'h35_40,
|
||||
16'h36_D9,
|
||||
16'h37_0A,
|
||||
16'h38_00,
|
||||
16'h39_2D,
|
||||
16'h3A_00,
|
||||
|
||||
{8'h16, 8'b0011_1000}, // Output Format 444 [7]=0.
|
||||
// [6] must be 0!
|
||||
// Colour Depth for Input Video data [5:4] b11 = 8-bit.
|
||||
// Input Style [3:2] b10 = Style 1 (ignored when using 444 input).
|
||||
// DDR Input Edge falling [1]=0 (not using DDR atm).
|
||||
// Output Colour Space RGB [0]=0.
|
||||
|
||||
{8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
|
||||
|
||||
{8'h18, ypbpr ? 8'h86 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00}, // CSC Scaling Factors and Coefficients for RGB Full->Limited.
|
||||
{8'h19, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE}, // Taken from table in ADV7513 Programming Guide.
|
||||
{8'h1A, ypbpr ? 8'h1A : 8'h00}, // CSC Channel A.
|
||||
{8'h1B, ypbpr ? 8'h3F : 8'h00},
|
||||
{8'h1C, ypbpr ? 8'h1E : 8'h00},
|
||||
{8'h1D, ypbpr ? 8'hE2 : 8'h00},
|
||||
{8'h1E, ypbpr ? 8'h07 : 8'h01},
|
||||
{8'h1F, ypbpr ? 8'hE7 : 8'h00},
|
||||
|
||||
{8'h20, ypbpr ? 8'h04 : 8'h00}, // CSC Channel B.
|
||||
{8'h21, ypbpr ? 8'h1C : 8'h00},
|
||||
{8'h22, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E},
|
||||
{8'h23, ypbpr ? 8'h11 : limited[0] ? 8'hBC : 8'hFE},
|
||||
{8'h24, ypbpr ? 8'h01 : 8'h00},
|
||||
{8'h25, ypbpr ? 8'h91 : 8'h00},
|
||||
{8'h26, ypbpr ? 8'h01 : 8'h01},
|
||||
{8'h27, 8'h00},
|
||||
|
||||
{8'h28, ypbpr ? 8'h1D : 8'h00}, // CSC Channel C.
|
||||
{8'h29, ypbpr ? 8'hAE : 8'h00},
|
||||
{8'h2A, ypbpr ? 8'h1B : 8'h00},
|
||||
{8'h2B, ypbpr ? 8'h73 : 8'h00},
|
||||
{8'h2C, ypbpr ? 8'h06 : limited[0] ? 8'h0D : 8'h0E},
|
||||
{8'h2D, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE},
|
||||
{8'h2E, ypbpr ? 8'h07 : 8'h01},
|
||||
{8'h2F, ypbpr ? 8'hE7 : 8'h00},
|
||||
|
||||
{8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
|
||||
|
||||
16'h4000, // General Control Packet Enable
|
||||
|
||||
{8'h48, 8'b0000_1000}, // [6]=0 Normal bus order!
|
||||
// [5] DDR Alignment.
|
||||
// [4:3] b01 Data right justified (for YCbCr 422 input modes).
|
||||
|
||||
16'h49A8, // ADI required Write.
|
||||
16'h4C00, // ADI required Write.
|
||||
|
||||
{8'h55, 8'b0001_0000}, // [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
|
||||
// AVI InfoFrame Valid [4].
|
||||
// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
|
||||
// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
|
||||
|
||||
{8'h57, 1'b0, // [7] IT Content. 0 - No. 1 - Yes (type set in register h59).
|
||||
3'b000, // [6:4] Color space (ignored for RGB)
|
||||
(ypbpr | limited) ? 2'b01 : 2'b10, // [3:2] RGB Quantization range
|
||||
2'b00}, // [1:0] Non-Uniform Scaled: 00 - None. 01 - Horiz. 10 - Vert. 11 - Both.
|
||||
|
||||
16'h7301,
|
||||
|
||||
{8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled.
|
||||
|
||||
16'h9902, // ADI required Write.
|
||||
16'h9B18, // ADI required Write.
|
||||
|
||||
16'h9F00, // ADI required Write.
|
||||
|
||||
{8'hA1, 8'b0000_0000}, // [6]=1 Monitor Sense Power Down DISabled.
|
||||
|
||||
16'hA408, // ADI required Write.
|
||||
16'hA504, // ADI required Write.
|
||||
16'hA600, // ADI required Write.
|
||||
16'hA700, // ADI required Write.
|
||||
16'hA800, // ADI required Write.
|
||||
16'hA900, // ADI required Write.
|
||||
16'hAA00, // ADI required Write.
|
||||
16'hAB40, // ADI required Write.
|
||||
|
||||
{8'hAF, 6'b0000_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
|
||||
// [6:5] must be b00!
|
||||
// [4]=0 Current frame is unencrypted
|
||||
// [3:2] must be b01!
|
||||
// [1]=1 HDMI Mode.
|
||||
// [0] must be b0!
|
||||
|
||||
16'hB900, // ADI required Write.
|
||||
|
||||
{8'hBA, 8'b0110_0000}, // [7:5] Input Clock delay...
|
||||
// b000 = -1.2ns.
|
||||
// b001 = -0.8ns.
|
||||
// b010 = -0.4ns.
|
||||
// b011 = No delay.
|
||||
// b100 = 0.4ns.
|
||||
// b101 = 0.8ns.
|
||||
// b110 = 1.2ns.
|
||||
// b111 = 1.6ns.
|
||||
|
||||
16'hBB00, // ADI required Write.
|
||||
|
||||
16'hDE9C, // ADI required Write.
|
||||
16'hE460, // ADI required Write.
|
||||
16'hFA7D, // Nbr of times to search for good phase
|
||||
|
||||
|
||||
// (Audio stuff on Programming Guide, Page 66)...
|
||||
|
||||
{8'h0A, 8'b0000_0000}, // [6:4] Audio Select. b000 = I2S.
|
||||
// [3:2] Audio Mode. (HBR stuff, leave at 00!).
|
||||
|
||||
{8'h0B, 8'b0000_1110}, //
|
||||
|
||||
{8'h0C, 8'b0000_0100}, // [7] 0 = Use sampling rate from I2S stream. 1 = Use samp rate from I2C Register.
|
||||
// [6] 0 = Use Channel Status bits from stream. 1 = Use Channel Status bits from I2C register.
|
||||
// [2] 1 = I2S0 Enable.
|
||||
// [1:0] I2S Format: 00 = Standard. 01 = Right Justified. 10 = Left Justified. 11 = AES.
|
||||
|
||||
{8'h0D, 8'b0001_0000}, // [4:0] I2S Bit (Word) Width for Right-Justified.
|
||||
{8'h14, 8'b0000_0010}, // [3:0] Audio Word Length. b0010 = 16 bits.
|
||||
{8'h15, audio_96k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
|
||||
// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
|
||||
|
||||
// Audio Clock Config
|
||||
16'h0100, //
|
||||
audio_96k ? 16'h0230 : 16'h0218, // Set N Value 12288/6144
|
||||
16'h0300, //
|
||||
|
||||
16'h0701, //
|
||||
16'h0822, // Set CTS Value 74250
|
||||
16'h090A, //
|
||||
|
||||
16'hFFFF // END
|
||||
};
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
|
||||
endmodule
|
||||
948
Computer_MiST/Interact_MiST/Neuer Ordner/sys/hps_io.sv
Normal file
948
Computer_MiST/Interact_MiST/Neuer Ordner/sys/hps_io.sv
Normal file
@@ -0,0 +1,948 @@
|
||||
//
|
||||
// hps_io.v
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2017-2020 Alexey Melnikov
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// altera message_off 10665
|
||||
|
||||
//
|
||||
// Use buffer to access SD card. It's time-critical part.
|
||||
//
|
||||
// WIDE=1 for 16 bit file I/O
|
||||
// VDNUM 1..4
|
||||
// BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384
|
||||
//
|
||||
module hps_io #(parameter CONF_STR, CONF_STR_BRAM=1, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0)
|
||||
(
|
||||
input clk_sys,
|
||||
inout [45:0] HPS_BUS,
|
||||
|
||||
// buttons up to 32
|
||||
output reg [31:0] joystick_0,
|
||||
output reg [31:0] joystick_1,
|
||||
output reg [31:0] joystick_2,
|
||||
output reg [31:0] joystick_3,
|
||||
output reg [31:0] joystick_4,
|
||||
output reg [31:0] joystick_5,
|
||||
|
||||
// analog -127..+127, Y: [15:8], X: [7:0]
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output reg [15:0] joystick_analog_2,
|
||||
output reg [15:0] joystick_analog_3,
|
||||
output reg [15:0] joystick_analog_4,
|
||||
output reg [15:0] joystick_analog_5,
|
||||
|
||||
// paddle 0..255
|
||||
output reg [7:0] paddle_0,
|
||||
output reg [7:0] paddle_1,
|
||||
output reg [7:0] paddle_2,
|
||||
output reg [7:0] paddle_3,
|
||||
output reg [7:0] paddle_4,
|
||||
output reg [7:0] paddle_5,
|
||||
|
||||
// spinner [7:0] -128..+127, [8] - toggle with every update
|
||||
output reg [8:0] spinner_0,
|
||||
output reg [8:0] spinner_1,
|
||||
output reg [8:0] spinner_2,
|
||||
output reg [8:0] spinner_3,
|
||||
output reg [8:0] spinner_4,
|
||||
output reg [8:0] spinner_5,
|
||||
|
||||
output [1:0] buttons,
|
||||
output forced_scandoubler,
|
||||
output direct_video,
|
||||
|
||||
output reg [63:0] status,
|
||||
input [63:0] status_in,
|
||||
input status_set,
|
||||
input [15:0] status_menumask,
|
||||
|
||||
input info_req,
|
||||
input [7:0] info,
|
||||
|
||||
//toggle to force notify of video mode change
|
||||
input new_vmode,
|
||||
|
||||
// SD config
|
||||
output reg [VD:0] img_mounted, // signaling that new image has been mounted
|
||||
output reg img_readonly, // mounted as read only. valid only for active bit in img_mounted
|
||||
output reg [63:0] img_size, // size of image in bytes. valid only for active bit in img_mounted
|
||||
|
||||
// SD block level access
|
||||
input [31:0] sd_lba[VDNUM],
|
||||
input [5:0] sd_blk_cnt[VDNUM], // number of blocks-1, total size ((sd_blk_cnt+1)*(1<<(BLKSZ+7))) must be <= 16384!
|
||||
input [VD:0] sd_rd,
|
||||
input [VD:0] sd_wr,
|
||||
output reg [VD:0] sd_ack,
|
||||
|
||||
// SD byte level access. Signals for 2-PORT altsyncram.
|
||||
output reg [AW:0] sd_buff_addr,
|
||||
output reg [DW:0] sd_buff_dout,
|
||||
input [DW:0] sd_buff_din[VDNUM],
|
||||
output reg sd_buff_wr,
|
||||
|
||||
// ARM -> FPGA download
|
||||
output reg ioctl_download = 0, // signal indicating an active download
|
||||
output reg [15:0] ioctl_index, // menu index used to upload the file
|
||||
output reg ioctl_wr,
|
||||
output reg [26:0] ioctl_addr, // in WIDE mode address will be incremented by 2
|
||||
output reg [DW:0] ioctl_dout,
|
||||
output reg ioctl_upload = 0, // signal indicating an active upload
|
||||
input [DW:0] ioctl_din,
|
||||
output reg ioctl_rd,
|
||||
output reg [31:0] ioctl_file_ext,
|
||||
input ioctl_wait,
|
||||
|
||||
// [15]: 0 - unset, 1 - set. [1:0]: 0 - none, 1 - 32MB, 2 - 64MB, 3 - 128MB
|
||||
// [14]: debug mode: [8]: 1 - phase up, 0 - phase down. [7:0]: amount of shift.
|
||||
output reg [15:0] sdram_sz,
|
||||
|
||||
// RTC MSM6242B layout
|
||||
output reg [64:0] RTC,
|
||||
|
||||
// Seconds since 1970-01-01 00:00:00
|
||||
output reg [32:0] TIMESTAMP,
|
||||
|
||||
// UART flags
|
||||
output reg [7:0] uart_mode,
|
||||
output reg [31:0] uart_speed,
|
||||
|
||||
// ps2 keyboard emulation
|
||||
output ps2_kbd_clk_out,
|
||||
output ps2_kbd_data_out,
|
||||
input ps2_kbd_clk_in,
|
||||
input ps2_kbd_data_in,
|
||||
|
||||
input [2:0] ps2_kbd_led_status,
|
||||
input [2:0] ps2_kbd_led_use,
|
||||
|
||||
output ps2_mouse_clk_out,
|
||||
output ps2_mouse_data_out,
|
||||
input ps2_mouse_clk_in,
|
||||
input ps2_mouse_data_in,
|
||||
|
||||
// ps2 alternative interface.
|
||||
|
||||
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
|
||||
output reg [10:0] ps2_key = 0,
|
||||
|
||||
// [24] - toggles with every event
|
||||
output reg [24:0] ps2_mouse = 0,
|
||||
output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements
|
||||
|
||||
inout [21:0] gamma_bus,
|
||||
|
||||
// for core-specific extensions
|
||||
inout [35:0] EXT_BUS
|
||||
);
|
||||
|
||||
assign EXT_BUS[31:16] = HPS_BUS[31:16];
|
||||
assign EXT_BUS[35:33] = HPS_BUS[35:33];
|
||||
|
||||
localparam DW = (WIDE) ? 15 : 7;
|
||||
localparam AW = (WIDE) ? 12 : 13;
|
||||
localparam VD = VDNUM-1;
|
||||
|
||||
wire io_strobe= HPS_BUS[33];
|
||||
wire io_enable= HPS_BUS[34];
|
||||
wire fp_enable= HPS_BUS[35];
|
||||
wire io_wide = (WIDE) ? 1'b1 : 1'b0;
|
||||
wire [15:0] io_din = HPS_BUS[31:16];
|
||||
reg [15:0] io_dout;
|
||||
|
||||
assign HPS_BUS[37] = ioctl_wait;
|
||||
assign HPS_BUS[36] = clk_sys;
|
||||
assign HPS_BUS[32] = io_wide;
|
||||
assign HPS_BUS[15:0] = EXT_BUS[32] ? EXT_BUS[15:0] : fp_enable ? fp_dout : io_dout;
|
||||
|
||||
reg [15:0] cfg;
|
||||
assign buttons = cfg[1:0];
|
||||
//cfg[2] - vga_scaler handled in sys_top
|
||||
//cfg[3] - csync handled in sys_top
|
||||
assign forced_scandoubler = cfg[4];
|
||||
//cfg[5] - ypbpr handled in sys_top
|
||||
assign direct_video = cfg[10];
|
||||
|
||||
reg [3:0] sdn;
|
||||
reg [3:0] sd_rrb = 0;
|
||||
always_comb begin
|
||||
int n, i;
|
||||
|
||||
sdn = 0;
|
||||
for(i = VDNUM - 1; i >= 0; i = i - 1) begin
|
||||
n = i + sd_rrb;
|
||||
if(n >= VDNUM) n = n - VDNUM;
|
||||
if(sd_wr[n] | sd_rd[n]) sdn = n[3:0];
|
||||
end
|
||||
end
|
||||
|
||||
/////////////////////////////////////////////////////////
|
||||
|
||||
wire [15:0] vc_dout;
|
||||
video_calc video_calc
|
||||
(
|
||||
.clk_100(HPS_BUS[43]),
|
||||
.clk_vid(HPS_BUS[42]),
|
||||
.clk_sys(clk_sys),
|
||||
.ce_pix(HPS_BUS[41]),
|
||||
.de(HPS_BUS[40]),
|
||||
.hs(HPS_BUS[39]),
|
||||
.vs(HPS_BUS[38]),
|
||||
.vs_hdmi(HPS_BUS[44]),
|
||||
.f1(HPS_BUS[45]),
|
||||
.new_vmode(new_vmode),
|
||||
|
||||
.par_num(byte_cnt[3:0]),
|
||||
.dout(vc_dout)
|
||||
);
|
||||
|
||||
/////////////////////////////////////////////////////////
|
||||
|
||||
localparam STRLEN = $size(CONF_STR)>>3;
|
||||
localparam MAX_W = $clog2((32 > (STRLEN+2)) ? 32 : (STRLEN+2))-1;
|
||||
|
||||
wire [7:0] conf_byte;
|
||||
generate
|
||||
if(CONF_STR_BRAM) begin
|
||||
confstr_rom #(CONF_STR, STRLEN) confstr_rom(.*, .conf_addr(byte_cnt - 1'd1));
|
||||
end
|
||||
else begin
|
||||
assign conf_byte = CONF_STR[{(STRLEN - byte_cnt),3'b000} +:8];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign gamma_bus[20:0] = {clk_sys, gamma_en, gamma_wr, gamma_wr_addr, gamma_value};
|
||||
reg gamma_en;
|
||||
reg gamma_wr;
|
||||
reg [9:0] gamma_wr_addr;
|
||||
reg [7:0] gamma_value;
|
||||
|
||||
reg [31:0] ps2_key_raw = 0;
|
||||
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
|
||||
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
|
||||
|
||||
reg [MAX_W:0] byte_cnt;
|
||||
reg [3:0] sdn_ack;
|
||||
wire [15:0] disk = 16'd1 << io_din[11:8];
|
||||
|
||||
always@(posedge clk_sys) begin : uio_block
|
||||
reg [15:0] cmd;
|
||||
reg [2:0] b_wr;
|
||||
reg [3:0] stick_idx;
|
||||
reg [3:0] pdsp_idx;
|
||||
reg ps2skip = 0;
|
||||
reg [3:0] stflg = 0;
|
||||
reg [63:0] status_req;
|
||||
reg old_status_set = 0;
|
||||
reg old_info = 0;
|
||||
reg [7:0] info_n = 0;
|
||||
reg [15:0] tmp1;
|
||||
reg [7:0] tmp2;
|
||||
reg [3:0] sdn_r;
|
||||
|
||||
old_status_set <= status_set;
|
||||
if(~old_status_set & status_set) begin
|
||||
stflg <= stflg + 1'd1;
|
||||
status_req <= status_in;
|
||||
end
|
||||
|
||||
old_info <= info_req;
|
||||
if(~old_info & info_req) info_n <= info;
|
||||
|
||||
sd_buff_wr <= b_wr[0];
|
||||
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
b_wr <= (b_wr<<1);
|
||||
|
||||
if(PS2DIV) {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
|
||||
|
||||
gamma_wr <= 0;
|
||||
|
||||
if(~io_enable) begin
|
||||
if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
|
||||
if(cmd == 5 && !ps2skip) begin
|
||||
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
|
||||
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
|
||||
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
|
||||
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
|
||||
end
|
||||
if(cmd == 'h22) RTC[64] <= ~RTC[64];
|
||||
if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
|
||||
cmd <= 0;
|
||||
byte_cnt <= 0;
|
||||
sd_ack <= 0;
|
||||
io_dout <= 0;
|
||||
ps2skip <= 0;
|
||||
img_mounted <= 0;
|
||||
end
|
||||
else if(io_strobe) begin
|
||||
|
||||
io_dout <= 0;
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
|
||||
|
||||
if(byte_cnt == 0) begin
|
||||
cmd <= io_din;
|
||||
|
||||
casex(io_din)
|
||||
'h16: begin io_dout <= {1'b1, sd_blk_cnt[sdn], BLKSZ[2:0], sdn, sd_wr[sdn], sd_rd[sdn]}; sdn_r <= sdn; end
|
||||
'h0X17,
|
||||
'h0X18: begin sd_ack <= disk[VD:0]; sdn_ack <= io_din[11:8]; end
|
||||
'h29: io_dout <= {4'hA, stflg};
|
||||
'h2B: io_dout <= 1;
|
||||
'h2F: io_dout <= 1;
|
||||
'h32: io_dout <= gamma_bus[21];
|
||||
'h36: begin io_dout <= info_n; info_n <= 0; end
|
||||
'h39: io_dout <= 1;
|
||||
endcase
|
||||
|
||||
sd_buff_addr <= 0;
|
||||
if(io_din == 5) ps2_key_raw <= 0;
|
||||
end else begin
|
||||
|
||||
casex(cmd)
|
||||
// buttons and switches
|
||||
'h01: cfg <= io_din;
|
||||
'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din;
|
||||
'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din;
|
||||
'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din;
|
||||
'h11: if(byte_cnt==1) joystick_3[15:0] <= io_din; else joystick_3[31:16] <= io_din;
|
||||
'h12: if(byte_cnt==1) joystick_4[15:0] <= io_din; else joystick_4[31:16] <= io_din;
|
||||
'h13: if(byte_cnt==1) joystick_5[15:0] <= io_din; else joystick_5[31:16] <= io_din;
|
||||
|
||||
// store incoming ps2 mouse bytes
|
||||
'h04: begin
|
||||
if(PS2DIV) begin
|
||||
mouse_data <= io_din[7:0];
|
||||
mouse_we <= 1;
|
||||
end
|
||||
if(&io_din[15:8]) ps2skip <= 1;
|
||||
if(~&io_din[15:8] && ~ps2skip && !byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: ps2_mouse[7:0] <= io_din[7:0];
|
||||
2: ps2_mouse[15:8] <= io_din[7:0];
|
||||
3: ps2_mouse[23:16] <= io_din[7:0];
|
||||
endcase
|
||||
case(byte_cnt[1:0])
|
||||
1: ps2_mouse_ext[7:0] <= {io_din[14], io_din[14:8]};
|
||||
2: ps2_mouse_ext[11:8] <= io_din[11:8];
|
||||
3: ps2_mouse_ext[15:12]<= io_din[11:8];
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
'h05: begin
|
||||
if(&io_din[15:8]) ps2skip <= 1;
|
||||
if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
|
||||
if(PS2DIV) begin
|
||||
kbd_data <= io_din[7:0];
|
||||
kbd_we <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
// reading config string, returning a byte from string
|
||||
'h14: if(byte_cnt <= STRLEN) io_dout[7:0] <= conf_byte;
|
||||
|
||||
// reading sd card status
|
||||
'h16: if(!byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: sd_rrb <= (sd_rrb == VD) ? 4'd0 : (sd_rrb + 1'd1);
|
||||
2: io_dout <= sd_lba[sdn_r][15:0];
|
||||
3: io_dout <= sd_lba[sdn_r][31:16];
|
||||
endcase
|
||||
end
|
||||
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
'hX17: begin
|
||||
sd_buff_dout <= io_din[DW:0];
|
||||
b_wr <= 1;
|
||||
end
|
||||
|
||||
// reading sd card write data
|
||||
'hX18: begin
|
||||
if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
io_dout <= sd_buff_din[sdn_ack];
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
'h1a: if(!byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index
|
||||
2: case(stick_idx)
|
||||
0: joystick_analog_0 <= io_din;
|
||||
1: joystick_analog_1 <= io_din;
|
||||
2: joystick_analog_2 <= io_din;
|
||||
3: joystick_analog_3 <= io_din;
|
||||
4: joystick_analog_4 <= io_din;
|
||||
5: joystick_analog_5 <= io_din;
|
||||
15: case(pdsp_idx)
|
||||
0: paddle_0 <= io_din[7:0];
|
||||
1: paddle_1 <= io_din[7:0];
|
||||
2: paddle_2 <= io_din[7:0];
|
||||
3: paddle_3 <= io_din[7:0];
|
||||
4: paddle_4 <= io_din[7:0];
|
||||
5: paddle_5 <= io_din[7:0];
|
||||
8: spinner_0 <= {~spinner_0[8],io_din[7:0]};
|
||||
9: spinner_1 <= {~spinner_1[8],io_din[7:0]};
|
||||
10: spinner_2 <= {~spinner_2[8],io_din[7:0]};
|
||||
11: spinner_3 <= {~spinner_3[8],io_din[7:0]};
|
||||
12: spinner_4 <= {~spinner_4[8],io_din[7:0]};
|
||||
13: spinner_5 <= {~spinner_5[8],io_din[7:0]};
|
||||
endcase
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
'h1c: begin
|
||||
img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
|
||||
img_readonly <= io_din[7];
|
||||
end
|
||||
|
||||
// send image info
|
||||
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
|
||||
|
||||
// status, 64bit version
|
||||
'h1e: if(!byte_cnt[MAX_W:3]) begin
|
||||
case(byte_cnt[2:0])
|
||||
1: status[15:00] <= io_din;
|
||||
2: status[31:16] <= io_din;
|
||||
3: status[47:32] <= io_din;
|
||||
4: status[63:48] <= io_din;
|
||||
endcase
|
||||
end
|
||||
|
||||
// reading keyboard LED status
|
||||
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
|
||||
|
||||
// reading ps2 keyboard/mouse control
|
||||
'h21: if(PS2DIV) begin
|
||||
if(byte_cnt == 1) begin
|
||||
io_dout <= kbd_data_host;
|
||||
kbd_rd <= 1;
|
||||
end
|
||||
else
|
||||
if(byte_cnt == 2) begin
|
||||
io_dout <= mouse_data_host;
|
||||
mouse_rd <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
//RTC
|
||||
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
||||
|
||||
//Video res.
|
||||
'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
|
||||
|
||||
//RTC
|
||||
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
||||
|
||||
//status set
|
||||
'h29: if(!byte_cnt[MAX_W:3]) begin
|
||||
case(byte_cnt[2:0])
|
||||
1: io_dout <= status_req[15:00];
|
||||
2: io_dout <= status_req[31:16];
|
||||
3: io_dout <= status_req[47:32];
|
||||
4: io_dout <= status_req[63:48];
|
||||
endcase
|
||||
end
|
||||
|
||||
//menu mask
|
||||
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
|
||||
|
||||
//sdram size set
|
||||
'h31: if(byte_cnt == 1) sdram_sz <= io_din;
|
||||
|
||||
// Gamma
|
||||
'h32: gamma_en <= io_din[0];
|
||||
'h33: begin
|
||||
gamma_wr_addr <= {(byte_cnt[1:0]-1'b1),io_din[15:8]};
|
||||
{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
|
||||
if (byte_cnt[1:0] == 3) byte_cnt <= 1;
|
||||
end
|
||||
|
||||
// UART
|
||||
'h3b: if(!byte_cnt[MAX_W:2]) begin
|
||||
case(byte_cnt[1:0])
|
||||
1: tmp2 <= io_din[7:0];
|
||||
2: tmp1 <= io_din;
|
||||
3: {uart_speed, uart_mode} <= {io_din, tmp1, tmp2};
|
||||
endcase
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// PS2 ///////////////////////////////
|
||||
generate
|
||||
if(PS2DIV) begin
|
||||
reg clk_ps2;
|
||||
always @(posedge clk_sys) begin
|
||||
integer cnt;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt == PS2DIV) begin
|
||||
clk_ps2 <= ~clk_ps2;
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [7:0] kbd_data;
|
||||
reg kbd_we;
|
||||
wire [8:0] kbd_data_host;
|
||||
reg kbd_rd;
|
||||
|
||||
ps2_device keyboard
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
.wdata(kbd_data),
|
||||
.we(kbd_we),
|
||||
|
||||
.ps2_clk(clk_ps2),
|
||||
.ps2_clk_out(ps2_kbd_clk_out),
|
||||
.ps2_dat_out(ps2_kbd_data_out),
|
||||
|
||||
.ps2_clk_in(ps2_kbd_clk_in || !PS2WE),
|
||||
.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
|
||||
|
||||
.rdata(kbd_data_host),
|
||||
.rd(kbd_rd)
|
||||
);
|
||||
|
||||
reg [7:0] mouse_data;
|
||||
reg mouse_we;
|
||||
wire [8:0] mouse_data_host;
|
||||
reg mouse_rd;
|
||||
|
||||
ps2_device mouse
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
.wdata(mouse_data),
|
||||
.we(mouse_we),
|
||||
|
||||
.ps2_clk(clk_ps2),
|
||||
.ps2_clk_out(ps2_mouse_clk_out),
|
||||
.ps2_dat_out(ps2_mouse_data_out),
|
||||
|
||||
.ps2_clk_in(ps2_mouse_clk_in || !PS2WE),
|
||||
.ps2_dat_in(ps2_mouse_data_in || !PS2WE),
|
||||
|
||||
.rdata(mouse_data_host),
|
||||
.rd(mouse_rd)
|
||||
);
|
||||
end
|
||||
else begin
|
||||
assign ps2_kbd_clk_out = 0;
|
||||
assign ps2_kbd_data_out = 0;
|
||||
assign ps2_mouse_clk_out = 0;
|
||||
assign ps2_mouse_data_out = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/////////////////////////////// DOWNLOADING ///////////////////////////////
|
||||
|
||||
localparam FIO_FILE_TX = 8'h53;
|
||||
localparam FIO_FILE_TX_DAT = 8'h54;
|
||||
localparam FIO_FILE_INDEX = 8'h55;
|
||||
localparam FIO_FILE_INFO = 8'h56;
|
||||
|
||||
reg [15:0] fp_dout;
|
||||
always@(posedge clk_sys) begin : fio_block
|
||||
reg [15:0] cmd;
|
||||
reg [2:0] cnt;
|
||||
reg has_cmd;
|
||||
reg [26:0] addr;
|
||||
reg wr;
|
||||
|
||||
ioctl_rd <= 0;
|
||||
ioctl_wr <= wr;
|
||||
wr <= 0;
|
||||
|
||||
if(~fp_enable) has_cmd <= 0;
|
||||
else begin
|
||||
if(io_strobe) begin
|
||||
|
||||
if(!has_cmd) begin
|
||||
cmd <= io_din;
|
||||
has_cmd <= 1;
|
||||
cnt <= 0;
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
FIO_FILE_INFO:
|
||||
if(~cnt[1]) begin
|
||||
case(cnt)
|
||||
0: ioctl_file_ext[31:16] <= io_din;
|
||||
1: ioctl_file_ext[15:00] <= io_din;
|
||||
endcase
|
||||
cnt <= cnt + 1'd1;
|
||||
end
|
||||
|
||||
FIO_FILE_INDEX:
|
||||
begin
|
||||
ioctl_index <= io_din[15:0];
|
||||
end
|
||||
|
||||
FIO_FILE_TX:
|
||||
begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt)
|
||||
0: if(io_din[7:0] == 8'hAA) begin
|
||||
ioctl_addr <= 0;
|
||||
ioctl_upload <= 1;
|
||||
ioctl_rd <= 1;
|
||||
end
|
||||
else if(io_din[7:0]) begin
|
||||
addr <= 0;
|
||||
ioctl_download <= 1;
|
||||
end
|
||||
else begin
|
||||
if(ioctl_download) ioctl_addr <= addr;
|
||||
ioctl_download <= 0;
|
||||
ioctl_upload <= 0;
|
||||
end
|
||||
|
||||
1: begin
|
||||
ioctl_addr[15:0] <= io_din;
|
||||
addr[15:0] <= io_din;
|
||||
end
|
||||
|
||||
2: begin
|
||||
ioctl_addr[26:16] <= io_din[10:0];
|
||||
addr[26:16] <= io_din[10:0];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
FIO_FILE_TX_DAT:
|
||||
if(ioctl_download) begin
|
||||
ioctl_addr <= addr;
|
||||
ioctl_dout <= io_din[DW:0];
|
||||
wr <= 1;
|
||||
addr <= addr + (WIDE ? 2'd2 : 2'd1);
|
||||
end
|
||||
else begin
|
||||
ioctl_addr <= ioctl_addr + (WIDE ? 2'd2 : 2'd1);
|
||||
fp_dout <= ioctl_din;
|
||||
ioctl_rd <= 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ps2_device #(parameter PS2_FIFO_BITS=5)
|
||||
(
|
||||
input clk_sys,
|
||||
|
||||
input [7:0] wdata,
|
||||
input we,
|
||||
|
||||
input ps2_clk,
|
||||
output reg ps2_clk_out,
|
||||
output reg ps2_dat_out,
|
||||
output reg tx_empty,
|
||||
|
||||
input ps2_clk_in,
|
||||
input ps2_dat_in,
|
||||
|
||||
output [8:0] rdata,
|
||||
input rd
|
||||
);
|
||||
|
||||
|
||||
(* ramstyle = "logic" *) reg [7:0] fifo[1<<PS2_FIFO_BITS];
|
||||
|
||||
reg [PS2_FIFO_BITS-1:0] wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] rptr;
|
||||
|
||||
reg [2:0] rx_state = 0;
|
||||
reg [3:0] tx_state = 0;
|
||||
|
||||
reg has_data;
|
||||
reg [7:0] data;
|
||||
assign rdata = {has_data, data};
|
||||
|
||||
always@(posedge clk_sys) begin
|
||||
reg [7:0] tx_byte;
|
||||
reg parity;
|
||||
reg r_inc;
|
||||
reg old_clk;
|
||||
reg [1:0] timeout;
|
||||
|
||||
reg [3:0] rx_cnt;
|
||||
|
||||
reg c1,c2,d1;
|
||||
|
||||
tx_empty <= ((wptr == rptr) && (tx_state == 0));
|
||||
|
||||
if(we && !has_data) begin
|
||||
fifo[wptr] <= wdata;
|
||||
wptr <= wptr + 1'd1;
|
||||
end
|
||||
|
||||
if(rd) has_data <= 0;
|
||||
|
||||
c1 <= ps2_clk_in;
|
||||
c2 <= c1;
|
||||
d1 <= ps2_dat_in;
|
||||
if(!rx_state && !tx_state && ~c2 && c1 && ~d1) begin
|
||||
rx_state <= rx_state + 1'b1;
|
||||
ps2_dat_out <= 1;
|
||||
end
|
||||
|
||||
old_clk <= ps2_clk;
|
||||
if(~old_clk & ps2_clk) begin
|
||||
|
||||
if(rx_state) begin
|
||||
case(rx_state)
|
||||
1: begin
|
||||
rx_state <= rx_state + 1'b1;
|
||||
rx_cnt <= 0;
|
||||
end
|
||||
|
||||
2: begin
|
||||
if(rx_cnt <= 7) data <= {d1, data[7:1]};
|
||||
else rx_state <= rx_state + 1'b1;
|
||||
rx_cnt <= rx_cnt + 1'b1;
|
||||
end
|
||||
|
||||
3: if(d1) begin
|
||||
rx_state <= rx_state + 1'b1;
|
||||
ps2_dat_out <= 0;
|
||||
end
|
||||
|
||||
4: begin
|
||||
ps2_dat_out <= 1;
|
||||
has_data <= 1;
|
||||
rx_state <= 0;
|
||||
rptr <= 0;
|
||||
wptr <= 0;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
|
||||
// transmitter is idle?
|
||||
if(tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(c2 && c1 && d1 && wptr != rptr) begin
|
||||
|
||||
timeout <= timeout - 1'd1;
|
||||
if(!timeout) begin
|
||||
tx_byte <= fifo[rptr];
|
||||
rptr <= rptr + 1'd1;
|
||||
|
||||
// reset parity
|
||||
parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_dat_out <= 0; // start bit is 0
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((tx_state >= 1)&&(tx_state < 9)) begin
|
||||
ps2_dat_out <= tx_byte[0]; // data bits
|
||||
tx_byte[6:0] <= tx_byte[7:1]; // shift down
|
||||
if(tx_byte[0])
|
||||
parity <= !parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(tx_state == 9) ps2_dat_out <= parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(tx_state == 10) ps2_dat_out <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(tx_state < 11) tx_state <= tx_state + 1'd1;
|
||||
else tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if(~old_clk & ps2_clk) ps2_clk_out <= 1;
|
||||
if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2));
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
///////////////// calc video parameters //////////////////
|
||||
module video_calc
|
||||
(
|
||||
input clk_100,
|
||||
input clk_vid,
|
||||
input clk_sys,
|
||||
|
||||
input ce_pix,
|
||||
input de,
|
||||
input hs,
|
||||
input vs,
|
||||
input vs_hdmi,
|
||||
input f1,
|
||||
input new_vmode,
|
||||
|
||||
input [3:0] par_num,
|
||||
output reg [15:0] dout
|
||||
);
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
case(par_num)
|
||||
1: dout <= {|vid_int, vid_nres};
|
||||
2: dout <= vid_hcnt[15:0];
|
||||
3: dout <= vid_hcnt[31:16];
|
||||
4: dout <= vid_vcnt[15:0];
|
||||
5: dout <= vid_vcnt[31:16];
|
||||
6: dout <= vid_htime[15:0];
|
||||
7: dout <= vid_htime[31:16];
|
||||
8: dout <= vid_vtime[15:0];
|
||||
9: dout <= vid_vtime[31:16];
|
||||
10: dout <= vid_pix[15:0];
|
||||
11: dout <= vid_pix[31:16];
|
||||
12: dout <= vid_vtime_hdmi[15:0];
|
||||
13: dout <= vid_vtime_hdmi[31:16];
|
||||
default dout <= 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [31:0] vid_hcnt = 0;
|
||||
reg [31:0] vid_vcnt = 0;
|
||||
reg [7:0] vid_nres = 0;
|
||||
reg [1:0] vid_int = 0;
|
||||
|
||||
always @(posedge clk_vid) begin
|
||||
integer hcnt;
|
||||
integer vcnt;
|
||||
reg old_vs= 0, old_de = 0, old_vmode = 0;
|
||||
reg [3:0] resto = 0;
|
||||
reg calch = 0;
|
||||
|
||||
if(ce_pix) begin
|
||||
old_vs <= vs;
|
||||
old_de <= de;
|
||||
|
||||
if(~vs & ~old_de & de) vcnt <= vcnt + 1;
|
||||
if(calch & de) hcnt <= hcnt + 1;
|
||||
if(old_de & ~de) calch <= 0;
|
||||
|
||||
if(old_vs & ~vs) begin
|
||||
vid_int <= {vid_int[0],f1};
|
||||
if(~f1) begin
|
||||
if(hcnt && vcnt) begin
|
||||
old_vmode <= new_vmode;
|
||||
|
||||
//report new resolution after timeout
|
||||
if(resto) resto <= resto + 1'd1;
|
||||
if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) resto <= 1;
|
||||
if(&resto) vid_nres <= vid_nres + 1'd1;
|
||||
vid_hcnt <= hcnt;
|
||||
vid_vcnt <= vcnt;
|
||||
end
|
||||
vcnt <= 0;
|
||||
hcnt <= 0;
|
||||
calch <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [31:0] vid_htime = 0;
|
||||
reg [31:0] vid_vtime = 0;
|
||||
reg [31:0] vid_pix = 0;
|
||||
|
||||
always @(posedge clk_100) begin
|
||||
integer vtime, htime, hcnt;
|
||||
reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2;
|
||||
reg calch = 0;
|
||||
|
||||
old_vs <= vs;
|
||||
old_hs <= hs;
|
||||
|
||||
old_vs2 <= old_vs;
|
||||
old_hs2 <= old_hs;
|
||||
|
||||
vtime <= vtime + 1'd1;
|
||||
htime <= htime + 1'd1;
|
||||
|
||||
if(~old_vs2 & old_vs) begin
|
||||
vid_pix <= hcnt;
|
||||
vid_vtime <= vtime;
|
||||
vtime <= 0;
|
||||
hcnt <= 0;
|
||||
end
|
||||
|
||||
if(old_vs2 & ~old_vs) calch <= 1;
|
||||
|
||||
if(~old_hs2 & old_hs) begin
|
||||
vid_htime <= htime;
|
||||
htime <= 0;
|
||||
end
|
||||
|
||||
old_de <= de;
|
||||
old_de2 <= old_de;
|
||||
|
||||
if(calch & old_de) hcnt <= hcnt + 1;
|
||||
if(old_de2 & ~old_de) calch <= 0;
|
||||
end
|
||||
|
||||
reg [31:0] vid_vtime_hdmi;
|
||||
always @(posedge clk_100) begin
|
||||
integer vtime;
|
||||
reg old_vs, old_vs2;
|
||||
|
||||
old_vs <= vs_hdmi;
|
||||
old_vs2 <= old_vs;
|
||||
|
||||
vtime <= vtime + 1'd1;
|
||||
|
||||
if(~old_vs2 & old_vs) begin
|
||||
vid_vtime_hdmi <= vtime;
|
||||
vtime <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module confstr_rom #(parameter CONF_STR, STRLEN)
|
||||
(
|
||||
input clk_sys,
|
||||
input [$clog2(STRLEN+1)-1:0] conf_addr,
|
||||
output reg [7:0] conf_byte
|
||||
);
|
||||
|
||||
wire [7:0] rom[STRLEN];
|
||||
initial for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8];
|
||||
always @ (posedge clk_sys) conf_byte <= rom[conf_addr];
|
||||
|
||||
endmodule
|
||||
371
Computer_MiST/Interact_MiST/Neuer Ordner/sys/hq2x.sv
Normal file
371
Computer_MiST/Interact_MiST/Neuer Ordner/sys/hq2x.sv
Normal file
@@ -0,0 +1,371 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2012-2013 Ludvig Strigeus
|
||||
// Copyright (c) 2017,2018 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// altera message_off 10030
|
||||
|
||||
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input ce_in,
|
||||
input [DWIDTH:0] inputpixel,
|
||||
input mono,
|
||||
input disable_hq2x,
|
||||
input reset_frame,
|
||||
input reset_line,
|
||||
|
||||
input ce_out,
|
||||
input [1:0] read_y,
|
||||
input hblank,
|
||||
output [DWIDTH:0] outpixel
|
||||
);
|
||||
|
||||
|
||||
localparam AWIDTH = $clog2(LENGTH)-1;
|
||||
localparam DWIDTH = HALF_DEPTH ? 11 : 23;
|
||||
localparam DWIDTH1 = DWIDTH+1;
|
||||
|
||||
(* romstyle = "MLAB" *) reg [5:0] hqTable[256];
|
||||
initial begin
|
||||
hqTable = '{
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
|
||||
};
|
||||
end
|
||||
|
||||
wire [5:0] hqrule = hqTable[nextpatt];
|
||||
|
||||
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
|
||||
reg [23:0] A, B, D, F, G, H;
|
||||
reg [7:0] pattern, nextpatt;
|
||||
reg [1:0] cyc;
|
||||
|
||||
reg curbuf;
|
||||
reg prevbuf = 0;
|
||||
wire iobuf = !curbuf;
|
||||
|
||||
wire diff0, diff1;
|
||||
DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0);
|
||||
DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1);
|
||||
|
||||
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
|
||||
|
||||
wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
|
||||
wire [23:0] blend_result_pre;
|
||||
Blend blender(clk, ce_in, disable_hq2x ? 6'd0 : hqrule, Curr0, X, B, D, F, H, blend_result_pre);
|
||||
|
||||
wire [DWIDTH:0] Curr20tmp;
|
||||
wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
|
||||
wire [DWIDTH:0] Curr21tmp;
|
||||
wire [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
|
||||
|
||||
reg [AWIDTH:0] wrin_addr2;
|
||||
reg [DWIDTH:0] wrpix;
|
||||
reg wrin_en;
|
||||
|
||||
function [23:0] h2rgb;
|
||||
input [11:0] v;
|
||||
begin
|
||||
h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [11:0] rgb2h;
|
||||
input [23:0] v;
|
||||
begin
|
||||
rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(offs),
|
||||
.rdbuf0(prevbuf),
|
||||
.rdbuf1(curbuf),
|
||||
.q0(Curr20tmp),
|
||||
.q1(Curr21tmp),
|
||||
|
||||
.wraddr(wrin_addr2),
|
||||
.wrbuf(iobuf),
|
||||
.data(wrpix),
|
||||
.wren(wrin_en)
|
||||
);
|
||||
|
||||
reg [AWIDTH+1:0] read_x;
|
||||
reg [AWIDTH+1:0] wrout_addr;
|
||||
reg wrout_en;
|
||||
reg [DWIDTH1*4-1:0] wrdata, wrdata_pre;
|
||||
wire [DWIDTH1*4-1:0] outpixel_x4;
|
||||
reg [DWIDTH1*2-1:0] outpixel_x2;
|
||||
|
||||
assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
|
||||
(
|
||||
.clock(clk),
|
||||
|
||||
.rdaddress({read_x[AWIDTH+1:1],read_y[1]}),
|
||||
.q(outpixel_x4),
|
||||
|
||||
.data(wrdata),
|
||||
.wraddress(wrout_addr),
|
||||
.wren(wrout_en)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(ce_out) begin
|
||||
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
|
||||
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
|
||||
if(hblank) read_x <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
|
||||
|
||||
reg [AWIDTH:0] offs;
|
||||
always @(posedge clk) begin
|
||||
reg old_reset_line;
|
||||
reg old_reset_frame;
|
||||
reg [3:0] wrdata_finished;
|
||||
reg [AWIDTH+1:0] waddr;
|
||||
|
||||
wrout_en <= 0;
|
||||
wrin_en <= 0;
|
||||
|
||||
if(ce_in) begin
|
||||
|
||||
// blend_result has been delayed by 4 cycles
|
||||
case(cyc)
|
||||
0: wrdata[DWIDTH:0] <= blend_result;
|
||||
1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
|
||||
2: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
|
||||
3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
|
||||
endcase
|
||||
|
||||
wrdata_finished <= wrdata_finished << 1;
|
||||
if(wrdata_finished[3]) begin
|
||||
wrout_en <= 1;
|
||||
wrout_addr <= waddr;
|
||||
end
|
||||
|
||||
if(~&offs) begin
|
||||
if (cyc == 1) begin
|
||||
Prev2 <= Curr20;
|
||||
Curr2 <= Curr21;
|
||||
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
|
||||
wrpix <= inputpixel;
|
||||
wrin_addr2 <= offs;
|
||||
wrin_en <= 1;
|
||||
end
|
||||
|
||||
if(cyc==3) begin
|
||||
offs <= offs + 1'd1;
|
||||
waddr <= {offs, curbuf};
|
||||
wrdata_finished[0] <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
pattern <= new_pattern;
|
||||
if(cyc==3) begin
|
||||
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
|
||||
{A, G} <= {Prev0, Next0};
|
||||
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
|
||||
{Prev0, Prev1} <= {Prev1, Prev2};
|
||||
{Curr0, Curr1} <= {Curr1, Curr2};
|
||||
{Next0, Next1} <= {Next1, Next2};
|
||||
end else begin
|
||||
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
|
||||
{B, F, H, D} <= {F, H, D, B};
|
||||
end
|
||||
|
||||
cyc <= cyc + 1'b1;
|
||||
if(old_reset_line && ~reset_line) begin
|
||||
old_reset_frame <= reset_frame;
|
||||
offs <= 0;
|
||||
cyc <= 0;
|
||||
curbuf <= ~curbuf;
|
||||
prevbuf <= curbuf;
|
||||
{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
|
||||
if(old_reset_frame & ~reset_frame) begin
|
||||
curbuf <= 0;
|
||||
prevbuf <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
old_reset_line <= reset_line;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input rdbuf0, rdbuf1,
|
||||
output[DWIDTH:0] q0,q1,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = $clog2(LENGTH)-1;
|
||||
wire [DWIDTH:0] out[2];
|
||||
assign q0 = out[rdbuf0];
|
||||
assign q1 = out[rdbuf1];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
|
||||
endmodule
|
||||
|
||||
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
|
||||
(
|
||||
input clock,
|
||||
input [DWIDTH:0] data,
|
||||
input [AWIDTH:0] rdaddress,
|
||||
input [AWIDTH:0] wraddress,
|
||||
input wren,
|
||||
output reg [DWIDTH:0] q
|
||||
);
|
||||
|
||||
reg [DWIDTH:0] ram[0:NUMWORDS-1];
|
||||
|
||||
always_ff@(posedge clock) begin
|
||||
if(wren) ram[wraddress] <= data;
|
||||
q <= ram[rdaddress];
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module DiffCheck
|
||||
(
|
||||
input [23:0] rgb1,
|
||||
input [23:0] rgb2,
|
||||
output result
|
||||
);
|
||||
|
||||
wire [7:0] r = rgb1[7:1] - rgb2[7:1];
|
||||
wire [7:0] g = rgb1[15:9] - rgb2[15:9];
|
||||
wire [7:0] b = rgb1[23:17] - rgb2[23:17];
|
||||
wire [8:0] t = $signed(r) + $signed(b);
|
||||
wire [9:0] y = $signed(t) + $signed({g[7], g});
|
||||
wire [8:0] u = $signed(r) - $signed(b);
|
||||
wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
|
||||
|
||||
// if y is inside (-96..96)
|
||||
wire y_inside = (y < 10'h60 || y >= 10'h3a0);
|
||||
|
||||
// if u is inside (-16, 16)
|
||||
wire u_inside = (!u[8:4] || &u[8:4]); //(u < 9'h10 || u >= 9'h1f0);
|
||||
|
||||
// if v is inside (-24, 24)
|
||||
wire v_inside = (v < 10'h18 || v >= 10'h3e8);
|
||||
assign result = !(y_inside && u_inside && v_inside);
|
||||
|
||||
endmodule
|
||||
|
||||
module Blend
|
||||
(
|
||||
input clk,
|
||||
input clk_en,
|
||||
input [5:0] rule,
|
||||
input [23:0] E,
|
||||
input [23:0] A,
|
||||
input [23:0] B,
|
||||
input [23:0] D,
|
||||
input [23:0] F,
|
||||
input [23:0] H,
|
||||
output [23:0] Result
|
||||
);
|
||||
|
||||
localparam BLEND1 = 7'b110_10_00; // (A * 12 + B * 4 ) >> 4
|
||||
localparam BLEND2 = 7'b100_10_10; // (A * 8 + B * 4 + C * 4) >> 4
|
||||
localparam BLEND3 = 7'b101_10_01; // (A * 10 + B * 4 + C * 2) >> 4
|
||||
localparam BLEND4 = 7'b110_01_01; // (A * 12 + B * 2 + C * 2) >> 4
|
||||
localparam BLEND5 = 7'b010_11_11; // (A * 4 + B * 6 + C * 6) >> 4
|
||||
localparam BLEND6 = 7'b111_00_00; // (A * 14 + B * 1 + C * 1) >> 4
|
||||
|
||||
reg [23:0] a,b,d,e,h,f;
|
||||
reg [3:0] bl_rule;
|
||||
reg [1:0] df_rule;
|
||||
always @(posedge clk) if (clk_en) begin
|
||||
{bl_rule,df_rule} <= rule;
|
||||
a <= A; b <= B; d <= D; e <= E; f <= F; h <= H;
|
||||
end
|
||||
|
||||
wire is_diff;
|
||||
DiffCheck diff_checker(df_rule[1] ? b : h, df_rule[0] ? d : f, is_diff);
|
||||
|
||||
reg [23:0] i10,i20,i30;
|
||||
reg [6:0] op0;
|
||||
always @(posedge clk) if (clk_en) begin
|
||||
i10 <= e;
|
||||
case({!is_diff, bl_rule})
|
||||
1,11,12,13,17: {op0, i20, i30} <= {BLEND1, a, 24'd0};
|
||||
2,14,18: {op0, i20, i30} <= {BLEND1, d, 24'd0};
|
||||
3,15,19: {op0, i20, i30} <= {BLEND1, b, 24'd0};
|
||||
4,20,24,27: {op0, i20, i30} <= {BLEND2, d, b};
|
||||
5,21: {op0, i20, i30} <= {BLEND2, a, b};
|
||||
6,22: {op0, i20, i30} <= {BLEND2, a, d};
|
||||
25,29: {op0, i20, i30} <= {BLEND5, d, b};
|
||||
26: {op0, i20, i30} <= {BLEND6, d, b};
|
||||
28: {op0, i20, i30} <= {BLEND4, d, b};
|
||||
30: {op0, i20, i30} <= {BLEND3, b, d};
|
||||
31: {op0, i20, i30} <= {BLEND3, d, b};
|
||||
default: {op0, i20, i30} <= {BLEND1, e, 24'd0};
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [23:0] i1,i2,i3;
|
||||
reg [6:0] op;
|
||||
always @(posedge clk) if (clk_en) begin
|
||||
op <= op0; i1 <= i10; i2 <= i20; i3 <= i30;
|
||||
end
|
||||
|
||||
function [34:0] mul24x3;
|
||||
input [23:0] op1;
|
||||
input [2:0] op2;
|
||||
begin
|
||||
mul24x3 = 0;
|
||||
if(op2[0]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0]};
|
||||
if(op2[1]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 1'b0};
|
||||
if(op2[2]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 2'b00};
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire [35:0] res = {mul24x3(i1, op[6:4]), 1'b0} + mul24x3(i2, {op[3:2], !op[3:2]}) + mul24x3(i3, {op[1:0], !op[3:2]});
|
||||
|
||||
always @(posedge clk) if (clk_en) Result <= {res[35:28],res[23:16],res[11:4]};
|
||||
|
||||
endmodule
|
||||
103
Computer_MiST/Interact_MiST/Neuer Ordner/sys/i2c.v
Normal file
103
Computer_MiST/Interact_MiST/Neuer Ordner/sys/i2c.v
Normal file
@@ -0,0 +1,103 @@
|
||||
|
||||
module i2c
|
||||
(
|
||||
input CLK,
|
||||
|
||||
input START,
|
||||
input READ,
|
||||
input [6:0] I2C_ADDR,
|
||||
input I2C_WLEN, // 0 - one byte, 1 - two bytes
|
||||
input [7:0] I2C_WDATA1,
|
||||
input [7:0] I2C_WDATA2,
|
||||
output [7:0] I2C_RDATA,
|
||||
output reg END = 1,
|
||||
output reg ACK = 0,
|
||||
|
||||
//I2C bus
|
||||
output I2C_SCL,
|
||||
inout I2C_SDA
|
||||
);
|
||||
|
||||
|
||||
// Clock Setting
|
||||
parameter CLK_Freq = 50_000_000; // 50 MHz
|
||||
parameter I2C_Freq = 400_000; // 400 KHz
|
||||
|
||||
localparam I2C_FreqX2 = I2C_Freq*2;
|
||||
|
||||
reg I2C_CLOCK;
|
||||
reg [31:0] cnt;
|
||||
wire [31:0] cnt_next = cnt + I2C_FreqX2;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
cnt <= cnt_next;
|
||||
if(cnt_next >= CLK_Freq) begin
|
||||
cnt <= cnt_next - CLK_Freq;
|
||||
I2C_CLOCK <= ~I2C_CLOCK;
|
||||
end
|
||||
end
|
||||
|
||||
assign I2C_SCL = (SCLK | I2C_CLOCK) ? 1'bZ : 1'b0;
|
||||
assign I2C_SDA = SDO[3] ? 1'bz : 1'b0;
|
||||
|
||||
reg SCLK;
|
||||
reg [3:0] SDO;
|
||||
reg [0:7] rdata;
|
||||
|
||||
reg [5:0] SD_COUNTER;
|
||||
reg [0:31] SD;
|
||||
|
||||
initial begin
|
||||
SD_COUNTER = 'b111111;
|
||||
SD = 'hFFFF;
|
||||
SCLK = 1;
|
||||
SDO = 4'b1111;
|
||||
end
|
||||
|
||||
assign I2C_RDATA = rdata;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
reg old_clk;
|
||||
reg old_st;
|
||||
reg rd,len;
|
||||
|
||||
old_clk <= I2C_CLOCK;
|
||||
old_st <= START;
|
||||
|
||||
// delay to make sure SDA changed while SCL is stabilized at low
|
||||
if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]];
|
||||
SDO[3:1] <= SDO[2:0];
|
||||
|
||||
if(~old_st && START) begin
|
||||
SCLK <= 1;
|
||||
SDO <= 4'b1111;
|
||||
ACK <= 0;
|
||||
END <= 0;
|
||||
rd <= READ;
|
||||
len <= I2C_WLEN;
|
||||
if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111};
|
||||
else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011};
|
||||
SD_COUNTER <= 0;
|
||||
end else begin
|
||||
if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
|
||||
SD_COUNTER <= SD_COUNTER + 6'd1;
|
||||
case(SD_COUNTER)
|
||||
01: SCLK <= 0;
|
||||
10: ACK <= ACK | I2C_SDA;
|
||||
19: if(~rd) begin
|
||||
ACK <= ACK | I2C_SDA;
|
||||
if(~len) SD_COUNTER <= 29;
|
||||
end
|
||||
20: if(rd) SCLK <= 1;
|
||||
23: if(rd) END <= 1;
|
||||
28: if(~rd) ACK <= ACK | I2C_SDA;
|
||||
29: if(~rd) SCLK <= 1;
|
||||
32: if(~rd) END <= 1;
|
||||
endcase
|
||||
|
||||
if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
54
Computer_MiST/Interact_MiST/Neuer Ordner/sys/i2s.v
Normal file
54
Computer_MiST/Interact_MiST/Neuer Ordner/sys/i2s.v
Normal file
@@ -0,0 +1,54 @@
|
||||
|
||||
module i2s
|
||||
#(
|
||||
parameter AUDIO_DW = 16
|
||||
)
|
||||
(
|
||||
input reset,
|
||||
input clk,
|
||||
input ce,
|
||||
|
||||
output reg sclk,
|
||||
output reg lrclk,
|
||||
output reg sdata,
|
||||
|
||||
input [AUDIO_DW-1:0] left_chan,
|
||||
input [AUDIO_DW-1:0] right_chan
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [7:0] bit_cnt;
|
||||
reg msclk;
|
||||
|
||||
reg [AUDIO_DW-1:0] left;
|
||||
reg [AUDIO_DW-1:0] right;
|
||||
|
||||
if (reset) begin
|
||||
bit_cnt <= 1;
|
||||
lrclk <= 1;
|
||||
sclk <= 1;
|
||||
msclk <= 1;
|
||||
end
|
||||
else begin
|
||||
sclk <= msclk;
|
||||
if(ce) begin
|
||||
msclk <= ~msclk;
|
||||
if(msclk) begin
|
||||
if(bit_cnt >= AUDIO_DW) begin
|
||||
bit_cnt <= 1;
|
||||
lrclk <= ~lrclk;
|
||||
if(lrclk) begin
|
||||
left <= left_chan;
|
||||
right <= right_chan;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
bit_cnt <= bit_cnt + 1'd1;
|
||||
end
|
||||
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
213
Computer_MiST/Interact_MiST/Neuer Ordner/sys/iir_filter.v
Normal file
213
Computer_MiST/Interact_MiST/Neuer Ordner/sys/iir_filter.v
Normal file
@@ -0,0 +1,213 @@
|
||||
|
||||
// 3-tap IIR filter for 2 channels.
|
||||
// Copyright (C) 2020 Sorgelig
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
//
|
||||
// Can be converted to 2-tap (coeff_x2 = 0, coeff_y2 = 0) or 1-tap (coeff_x1,2 = 0, coeff_y1,2 = 0)
|
||||
//
|
||||
module IIR_filter
|
||||
#(
|
||||
parameter use_params = 1, // set to 1 to use following parameters, 0 for input port variables.
|
||||
parameter stereo = 1, // 0 for mono (input_l)
|
||||
|
||||
parameter coeff_x = 0.00000774701983513660, // Base gain value for X. Float. Range: 0.0 ... 0.999(9)
|
||||
parameter coeff_x0 = 3, // Gain scale factor for X0. Integer. Range -7 ... +7
|
||||
parameter coeff_x1 = 3, // Gain scale factor for X1. Integer. Range -7 ... +7
|
||||
parameter coeff_x2 = 1, // Gain scale factor for X2. Integer. Range -7 ... +7
|
||||
parameter coeff_y0 = -2.96438150626551080000, // Coefficient for Y0. Float. Range -3.999(9) ... 3.999(9)
|
||||
parameter coeff_y1 = 2.92939452735121100000, // Coefficient for Y1. Float. Range -3.999(9) ... 3.999(9)
|
||||
parameter coeff_y2 = -0.96500747158831091000 // Coefficient for Y2. Float. Range -3.999(9) ... 3.999(9)
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input ce, // must be double of calculated rate for stereo!
|
||||
input sample_ce, // desired output sample rate
|
||||
|
||||
input [39:0] cx,
|
||||
input [7:0] cx0,
|
||||
input [7:0] cx1,
|
||||
input [7:0] cx2,
|
||||
input [23:0] cy0,
|
||||
input [23:0] cy1,
|
||||
input [23:0] cy2,
|
||||
|
||||
input [15:0] input_l, input_r, // signed samples
|
||||
output [15:0] output_l, output_r // signed samples
|
||||
);
|
||||
|
||||
localparam [39:0] pcoeff_x = coeff_x * 40'h8000000000;
|
||||
localparam [31:0] pcoeff_y0 = coeff_y0 * 24'h200000;
|
||||
localparam [31:0] pcoeff_y1 = coeff_y1 * 24'h200000;
|
||||
localparam [31:0] pcoeff_y2 = coeff_y2 * 24'h200000;
|
||||
|
||||
wire [39:0] vcoeff = use_params ? pcoeff_x : cx;
|
||||
wire [23:0] vcoeff_y0 = use_params ? pcoeff_y0[23:0] : cy0;
|
||||
wire [23:0] vcoeff_y1 = use_params ? pcoeff_y1[23:0] : cy1;
|
||||
wire [23:0] vcoeff_y2 = use_params ? pcoeff_y2[23:0] : cy2;
|
||||
|
||||
wire [59:0] inp_mul = $signed(inp) * $signed(vcoeff);
|
||||
|
||||
wire [39:0] x = inp_mul[59:20];
|
||||
wire [39:0] y = x + tap0;
|
||||
|
||||
wire [39:0] tap0;
|
||||
iir_filter_tap iir_tap_0
|
||||
(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.ce(ce),
|
||||
.ch(ch),
|
||||
.cx(use_params ? coeff_x0[7:0] : cx0),
|
||||
.cy(vcoeff_y0),
|
||||
.x(x),
|
||||
.y(y),
|
||||
.z(tap1),
|
||||
.tap(tap0)
|
||||
);
|
||||
|
||||
wire [39:0] tap1;
|
||||
iir_filter_tap iir_tap_1
|
||||
(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.ce(ce),
|
||||
.ch(ch),
|
||||
.cx(use_params ? coeff_x1[7:0] : cx1),
|
||||
.cy(vcoeff_y1),
|
||||
.x(x),
|
||||
.y(y),
|
||||
.z(tap2),
|
||||
.tap(tap1)
|
||||
);
|
||||
|
||||
wire [39:0] tap2;
|
||||
iir_filter_tap iir_tap_2
|
||||
(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.ce(ce),
|
||||
.ch(ch),
|
||||
.cx(use_params ? coeff_x2[7:0] : cx2),
|
||||
.cy(vcoeff_y2),
|
||||
.x(x),
|
||||
.y(y),
|
||||
.z(0),
|
||||
.tap(tap2)
|
||||
);
|
||||
|
||||
wire [15:0] y_clamp = (~y[39] & |y[38:35]) ? 16'h7FFF : (y[39] & ~&y[38:35]) ? 16'h8000 : y[35:20];
|
||||
|
||||
reg ch = 0;
|
||||
reg [15:0] out_l, out_r, out_m;
|
||||
reg [15:0] inp, inp_m;
|
||||
always @(posedge clk) if (ce) begin
|
||||
if(!stereo) begin
|
||||
ch <= 0;
|
||||
inp <= input_l;
|
||||
out_l <= y_clamp;
|
||||
out_r <= y_clamp;
|
||||
end
|
||||
else begin
|
||||
ch <= ~ch;
|
||||
if(ch) begin
|
||||
out_m <= y_clamp;
|
||||
inp <= inp_m;
|
||||
end
|
||||
else begin
|
||||
out_l <= out_m;
|
||||
out_r <= y_clamp;
|
||||
inp <= input_l;
|
||||
inp_m <= input_r;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [31:0] out;
|
||||
always @(posedge clk) if (sample_ce) out <= {out_l, out_r};
|
||||
|
||||
assign {output_l, output_r} = out;
|
||||
|
||||
endmodule
|
||||
|
||||
module iir_filter_tap
|
||||
(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input ce,
|
||||
input ch,
|
||||
|
||||
input [7:0] cx,
|
||||
input [23:0] cy,
|
||||
|
||||
input [39:0] x,
|
||||
input [39:0] y,
|
||||
input [39:0] z,
|
||||
output [39:0] tap
|
||||
);
|
||||
|
||||
wire signed [60:0] y_mul = $signed(y[36:0]) * $signed(cy);
|
||||
|
||||
function [39:0] x_mul;
|
||||
input [39:0] x;
|
||||
begin
|
||||
x_mul = 0;
|
||||
if(cx[0]) x_mul = x_mul + {{4{x[39]}}, x[39:4]};
|
||||
if(cx[1]) x_mul = x_mul + {{3{x[39]}}, x[39:3]};
|
||||
if(cx[2]) x_mul = x_mul + {{2{x[39]}}, x[39:2]};
|
||||
if(cx[7]) x_mul = ~x_mul; //cheap NEG
|
||||
end
|
||||
endfunction
|
||||
|
||||
(* ramstyle = "logic" *) reg [39:0] intreg[2];
|
||||
always @(posedge clk, posedge reset) begin
|
||||
if(reset) {intreg[0],intreg[1]} <= 80'd0;
|
||||
else if(ce) intreg[ch] <= x_mul(x) - y_mul[60:21] + z;
|
||||
end
|
||||
|
||||
assign tap = intreg[ch];
|
||||
|
||||
endmodule
|
||||
|
||||
// simplified IIR 1-tap.
|
||||
module DC_blocker
|
||||
(
|
||||
input clk,
|
||||
input ce, // 48/96 KHz
|
||||
input mute,
|
||||
|
||||
input sample_rate,
|
||||
input [15:0] din,
|
||||
output [15:0] dout
|
||||
);
|
||||
|
||||
wire [39:0] x = {din[15], din, 23'd0};
|
||||
wire [39:0] x0 = x - (sample_rate ? {{11{x[39]}}, x[39:11]} : {{10{x[39]}}, x[39:10]});
|
||||
wire [39:0] y1 = y - (sample_rate ? {{10{y[39]}}, y[39:10]} : {{09{y[39]}}, y[39:09]});
|
||||
wire [39:0] y0 = x0 - x1 + y1;
|
||||
|
||||
reg [39:0] x1, y;
|
||||
always @(posedge clk) if(ce) begin
|
||||
x1 <= x0;
|
||||
y <= ^y0[39:38] ? {{2{y0[39]}},{38{y0[38]}}} : y0;
|
||||
end
|
||||
|
||||
assign dout = mute ? 16'd0 : y[38:23];
|
||||
|
||||
endmodule
|
||||
162
Computer_MiST/Interact_MiST/Neuer Ordner/sys/ltc2308.sv
Normal file
162
Computer_MiST/Interact_MiST/Neuer Ordner/sys/ltc2308.sv
Normal file
@@ -0,0 +1,162 @@
|
||||
//============================================================================
|
||||
//
|
||||
// LTC2308 controller
|
||||
// Copyright (C) 2019 Sorgelig
|
||||
//
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
//
|
||||
//============================================================================
|
||||
|
||||
|
||||
// NUM_CH 1..8
|
||||
// Sampling rate = ADC_RATE/NUM_CH
|
||||
// ADC_RATE max is ~500KHz
|
||||
// CLK_RATE max is ~80MHz
|
||||
module ltc2308 #(parameter NUM_CH = 2, ADC_RATE = 96000, CLK_RATE = 50000000)
|
||||
(
|
||||
input reset,
|
||||
input clk,
|
||||
|
||||
inout [3:0] ADC_BUS,
|
||||
|
||||
output reg dout_sync, // toggle with every ADC round
|
||||
output reg [(NUM_CH*12)-1:0] dout // 12 bits per channel (unsigned)
|
||||
);
|
||||
|
||||
localparam TCONV = CLK_RATE/625000;
|
||||
|
||||
reg sck;
|
||||
wire sdo = cfg[5];
|
||||
|
||||
assign ADC_BUS[3] = sck;
|
||||
wire sdi = ADC_BUS[2];
|
||||
assign ADC_BUS[1] = sdo;
|
||||
assign ADC_BUS[0] = convst;
|
||||
|
||||
reg convst;
|
||||
reg [5:0] cfg;
|
||||
|
||||
reg [31:0] sum;
|
||||
wire [31:0] next_sum = sum + ADC_RATE;
|
||||
|
||||
reg [2:0] pin;
|
||||
wire [2:0] next_pin = (pin == (NUM_CH-1)) ? 3'd0 : (pin + 1'd1);
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [7:0] tconv;
|
||||
reg [3:0] bitcnt;
|
||||
reg [10:0] adcin;
|
||||
|
||||
convst <= 0;
|
||||
|
||||
if(reset) begin
|
||||
sum <= 0;
|
||||
tconv <= 0;
|
||||
bitcnt <= 0;
|
||||
sck <= 0;
|
||||
cfg <= 0;
|
||||
dout <= 0;
|
||||
pin <= NUM_CH[2:0]-1'd1;
|
||||
end
|
||||
else begin
|
||||
sum <= next_sum;
|
||||
if(next_sum >= CLK_RATE) begin
|
||||
sum <= next_sum - CLK_RATE;
|
||||
tconv <= TCONV[7:0];
|
||||
convst <= 1;
|
||||
bitcnt <= 12;
|
||||
cfg <= {1'b1, next_pin[0], next_pin[2:1], 1'b1, 1'b0};
|
||||
if(!next_pin) dout_sync <= ~dout_sync;
|
||||
end
|
||||
|
||||
if(tconv) tconv <= tconv - 1'd1;
|
||||
else if(bitcnt) begin
|
||||
sck <= ~sck;
|
||||
|
||||
if(sck) cfg <= cfg<<1;
|
||||
else begin
|
||||
adcin <= {adcin[9:0],sdi};
|
||||
bitcnt <= bitcnt - 1'd1;
|
||||
if(bitcnt == 1) begin
|
||||
dout[pin*12 +:12] <= {adcin,sdi};
|
||||
pin <= next_pin;
|
||||
end
|
||||
end
|
||||
end
|
||||
else sck <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000)
|
||||
(
|
||||
input reset,
|
||||
input clk,
|
||||
|
||||
inout [3:0] ADC_BUS,
|
||||
output reg dout,
|
||||
output active
|
||||
);
|
||||
|
||||
wire [11:0] adc_data;
|
||||
wire adc_sync;
|
||||
ltc2308 #(1, ADC_RATE, CLK_RATE) adc
|
||||
(
|
||||
.reset(reset),
|
||||
.clk(clk),
|
||||
|
||||
.ADC_BUS(ADC_BUS),
|
||||
.dout(adc_data),
|
||||
.dout_sync(adc_sync)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [13:0] data1,data2,data3,data4, sum;
|
||||
reg adc_sync_d;
|
||||
|
||||
adc_sync_d<=adc_sync;
|
||||
if(adc_sync_d ^ adc_sync) begin
|
||||
data1 <= data2;
|
||||
data2 <= data3;
|
||||
data3 <= data4;
|
||||
data4 <= adc_data;
|
||||
|
||||
sum <= data1+data2+data3+data4;
|
||||
|
||||
if(sum[13:2]<HIST_LOW) dout <= 0;
|
||||
if(sum[13:2]>HIST_HIGH) dout <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
assign active = |act;
|
||||
|
||||
reg [1:0] act;
|
||||
always @(posedge clk) begin
|
||||
reg [31:0] onesec;
|
||||
reg old_dout;
|
||||
|
||||
onesec <= onesec + 1;
|
||||
if(onesec>CLK_RATE) begin
|
||||
onesec <= 0;
|
||||
if(act) act <= act - 1'd1;
|
||||
end
|
||||
|
||||
old_dout <= dout;
|
||||
if(old_dout ^ dout) act <= 2;
|
||||
end
|
||||
|
||||
endmodule
|
||||
109
Computer_MiST/Interact_MiST/Neuer Ordner/sys/math.sv
Normal file
109
Computer_MiST/Interact_MiST/Neuer Ordner/sys/math.sv
Normal file
@@ -0,0 +1,109 @@
|
||||
|
||||
// result = num/div
|
||||
module sys_udiv
|
||||
#(
|
||||
parameter NB_NUM,
|
||||
parameter NB_DIV
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input start,
|
||||
output busy,
|
||||
|
||||
input [NB_NUM-1:0] num,
|
||||
input [NB_DIV-1:0] div,
|
||||
output reg [NB_NUM-1:0] result,
|
||||
output reg [NB_DIV-1:0] remainder
|
||||
);
|
||||
|
||||
reg run;
|
||||
assign busy = run;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [5:0] cpt;
|
||||
reg [NB_NUM+NB_DIV+1:0] rem;
|
||||
|
||||
if (start) begin
|
||||
cpt <= 0;
|
||||
run <= 1;
|
||||
rem <= num;
|
||||
end
|
||||
else if (run) begin
|
||||
cpt <= cpt + 1'd1;
|
||||
run <= (cpt != NB_NUM + 1'd1);
|
||||
remainder <= rem[NB_NUM+NB_DIV:NB_NUM+1];
|
||||
if (!rem[NB_DIV + NB_NUM + 1'd1])
|
||||
rem <= {rem[NB_DIV+NB_NUM:0] - (div << NB_NUM),1'b0};
|
||||
else
|
||||
rem <= {rem[NB_DIV+NB_NUM:0] + (div << NB_NUM),1'b0};
|
||||
result <= {result[NB_NUM-2:0], !rem[NB_DIV + NB_NUM + 1'd1]};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// result = mul1*mul2
|
||||
module sys_umul
|
||||
#(
|
||||
parameter NB_MUL1,
|
||||
parameter NB_MUL2
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input start,
|
||||
output busy,
|
||||
|
||||
input [NB_MUL1-1:0] mul1,
|
||||
input [NB_MUL2-1:0] mul2,
|
||||
output reg [NB_MUL1+NB_MUL2-1:0] result
|
||||
);
|
||||
|
||||
reg run;
|
||||
assign busy = run;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [NB_MUL1+NB_MUL2-1:0] add;
|
||||
reg [NB_MUL2-1:0] map;
|
||||
|
||||
if (start) begin
|
||||
run <= 1;
|
||||
result <= 0;
|
||||
add <= mul1;
|
||||
map <= mul2;
|
||||
end
|
||||
else if (run) begin
|
||||
if(!map) run <= 0;
|
||||
if(map[0]) result <= result + add;
|
||||
add <= add << 1;
|
||||
map <= map >> 1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// result = (mul1*mul2)/div
|
||||
module sys_umuldiv
|
||||
#(
|
||||
parameter NB_MUL1,
|
||||
parameter NB_MUL2,
|
||||
parameter NB_DIV
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input start,
|
||||
output busy,
|
||||
|
||||
input [NB_MUL1-1:0] mul1,
|
||||
input [NB_MUL2-1:0] mul2,
|
||||
input [NB_DIV-1:0] div,
|
||||
output [NB_MUL1+NB_MUL2-1:0] result,
|
||||
output [NB_DIV-1:0] remainder
|
||||
);
|
||||
|
||||
wire mul_run;
|
||||
wire [NB_MUL1+NB_MUL2-1:0] mul_res;
|
||||
sys_umul #(NB_MUL1,NB_MUL2) umul(clk,start,mul_run,mul1,mul2,mul_res);
|
||||
|
||||
sys_udiv #(NB_MUL1+NB_MUL2,NB_DIV) udiv(clk,start|mul_run,busy,mul_res,div,result,remainder);
|
||||
|
||||
endmodule
|
||||
113
Computer_MiST/Interact_MiST/Neuer Ordner/sys/mcp23009.sv
Normal file
113
Computer_MiST/Interact_MiST/Neuer Ordner/sys/mcp23009.sv
Normal file
@@ -0,0 +1,113 @@
|
||||
//
|
||||
// MCP23009
|
||||
// (C) 2019 Alexey Melnikov
|
||||
//
|
||||
module mcp23009
|
||||
(
|
||||
input clk,
|
||||
|
||||
output reg [2:0] btn,
|
||||
input [2:0] led,
|
||||
output reg sd_cd,
|
||||
|
||||
output scl,
|
||||
inout sda
|
||||
);
|
||||
|
||||
|
||||
reg start = 0;
|
||||
wire ready;
|
||||
wire error;
|
||||
reg rw;
|
||||
wire [7:0] dout;
|
||||
reg [15:0] din;
|
||||
|
||||
i2c #(50_000_000, 500_000) i2c
|
||||
(
|
||||
.CLK(clk),
|
||||
.START(start),
|
||||
.READ(rw),
|
||||
.I2C_ADDR('h20),
|
||||
.I2C_WLEN(1),
|
||||
.I2C_WDATA1(din[15:8]),
|
||||
.I2C_WDATA2(din[7:0]),
|
||||
.I2C_RDATA(dout),
|
||||
.END(ready),
|
||||
.ACK(error),
|
||||
.I2C_SCL(scl),
|
||||
.I2C_SDA(sda)
|
||||
);
|
||||
|
||||
always@(posedge clk) begin
|
||||
reg [3:0] idx = 0;
|
||||
reg [1:0] state = 0;
|
||||
reg [15:0] timeout = 0;
|
||||
|
||||
if(~&timeout) begin
|
||||
timeout <= timeout + 1'd1;
|
||||
start <= 0;
|
||||
state <= 0;
|
||||
idx <= 0;
|
||||
btn <= 0;
|
||||
rw <= 0;
|
||||
sd_cd <= 1;
|
||||
end
|
||||
else begin
|
||||
if(~&init_data[idx]) begin
|
||||
case(state)
|
||||
0: begin
|
||||
start <= 1;
|
||||
state <= 1;
|
||||
din <= init_data[idx];
|
||||
end
|
||||
1: if(~ready) state <= 2;
|
||||
2: begin
|
||||
start <= 0;
|
||||
if(ready) begin
|
||||
state <= 0;
|
||||
if(!error) idx <= idx + 1'd1;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
case(state)
|
||||
0: begin
|
||||
start <= 1;
|
||||
state <= 1;
|
||||
din <= {8'h09,5'b00000,led};
|
||||
end
|
||||
1: if(~ready) state <= 2;
|
||||
2: begin
|
||||
start <= 0;
|
||||
if(ready) begin
|
||||
state <= 0;
|
||||
rw <= 0;
|
||||
if(!error) begin
|
||||
if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]};
|
||||
rw <= ~rw;
|
||||
end
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [15:0] init_data[12] =
|
||||
'{
|
||||
16'h00F8,
|
||||
16'h0138,
|
||||
16'h0200,
|
||||
16'h0300,
|
||||
16'h0400,
|
||||
16'h0524,
|
||||
16'h06FF,
|
||||
16'h0700,
|
||||
16'h0800,
|
||||
16'h0900,
|
||||
16'h0A00,
|
||||
16'hFFFF
|
||||
};
|
||||
|
||||
endmodule
|
||||
283
Computer_MiST/Interact_MiST/Neuer Ordner/sys/mt32pi.sv
Normal file
283
Computer_MiST/Interact_MiST/Neuer Ordner/sys/mt32pi.sv
Normal file
@@ -0,0 +1,283 @@
|
||||
//
|
||||
// Communication module to MT32-pi (external MIDI emulator on RPi)
|
||||
// (C) 2020 Sorgelig, Kitrinx
|
||||
//
|
||||
// https://github.com/dwhinham/mt32-pi
|
||||
//
|
||||
|
||||
module mt32pi
|
||||
(
|
||||
input CLK_AUDIO,
|
||||
|
||||
input CLK_VIDEO,
|
||||
input CE_PIXEL,
|
||||
input VGA_VS,
|
||||
input VGA_DE,
|
||||
|
||||
input [6:0] USER_IN,
|
||||
output [6:0] USER_OUT,
|
||||
|
||||
input reset,
|
||||
input midi_tx,
|
||||
output midi_rx,
|
||||
|
||||
output reg [15:0] mt32_i2s_r,
|
||||
output reg [15:0] mt32_i2s_l,
|
||||
|
||||
output reg mt32_available,
|
||||
|
||||
input mt32_mode_req,
|
||||
input [1:0] mt32_rom_req,
|
||||
input [7:0] mt32_sf_req,
|
||||
|
||||
output reg [7:0] mt32_mode,
|
||||
output reg [7:0] mt32_rom,
|
||||
output reg [7:0] mt32_sf,
|
||||
output reg mt32_newmode,
|
||||
|
||||
output reg mt32_lcd_en,
|
||||
output reg mt32_lcd_pix,
|
||||
output reg mt32_lcd_update
|
||||
);
|
||||
|
||||
//
|
||||
// Pin | USB Name | Signal
|
||||
// ----+----------+--------------
|
||||
// 0 | D+ | I/O I2C_SDA / RX (midi in)
|
||||
// 1 | D- | O TX (midi out)
|
||||
// 2 | TX- | I I2S_WS (1 == right)
|
||||
// 3 | GND_d | I I2C_SCL
|
||||
// 4 | RX+ | I I2S_BCLK
|
||||
// 5 | RX- | I I2S_DAT
|
||||
// 6 | TX+ | - none
|
||||
//
|
||||
|
||||
assign USER_OUT[0] = sda_out;
|
||||
assign USER_OUT[1] = midi_tx;
|
||||
assign USER_OUT[6:2] = '1;
|
||||
|
||||
|
||||
//
|
||||
// crossed/straight cable selection
|
||||
//
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for(i = 0; i<2; i++) begin : clk_rate
|
||||
wire clk_in = i ? USER_IN[6] : USER_IN[4];
|
||||
reg [4:0] cnt;
|
||||
always @(posedge CLK_AUDIO) begin : clkr
|
||||
reg clk_sr, clk, old_clk;
|
||||
reg [4:0] cnt_tmp;
|
||||
|
||||
clk_sr <= clk_in;
|
||||
if (clk_sr == clk_in) clk <= clk_sr;
|
||||
|
||||
if(~&cnt_tmp) cnt_tmp <= cnt_tmp + 1'd1;
|
||||
else cnt <= '1;
|
||||
|
||||
old_clk <= clk;
|
||||
if(~old_clk & clk) begin
|
||||
cnt <= cnt_tmp;
|
||||
cnt_tmp <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg crossed;
|
||||
always @(posedge CLK_AUDIO) crossed <= (clk_rate[0].cnt <= clk_rate[1].cnt);
|
||||
endgenerate
|
||||
|
||||
wire i2s_ws = crossed ? USER_IN[2] : USER_IN[5];
|
||||
wire i2s_data = crossed ? USER_IN[5] : USER_IN[2];
|
||||
wire i2s_bclk = crossed ? USER_IN[4] : USER_IN[6];
|
||||
assign midi_rx = ~mt32_available ? USER_IN[0] : crossed ? USER_IN[6] : USER_IN[4];
|
||||
|
||||
|
||||
//
|
||||
// i2s receiver
|
||||
//
|
||||
|
||||
always @(posedge CLK_AUDIO) begin : i2s_proc
|
||||
reg [15:0] i2s_buf = 0;
|
||||
reg [4:0] i2s_cnt = 0;
|
||||
reg clk_sr;
|
||||
reg i2s_clk = 0;
|
||||
reg old_clk, old_ws;
|
||||
reg i2s_next = 0;
|
||||
|
||||
// Debounce clock
|
||||
clk_sr <= i2s_bclk;
|
||||
if (clk_sr == i2s_bclk) i2s_clk <= clk_sr;
|
||||
|
||||
// Latch data and ws on rising edge
|
||||
old_clk <= i2s_clk;
|
||||
if (i2s_clk && ~old_clk) begin
|
||||
|
||||
if (~i2s_cnt[4]) begin
|
||||
i2s_cnt <= i2s_cnt + 1'd1;
|
||||
i2s_buf[~i2s_cnt[3:0]] <= i2s_data;
|
||||
end
|
||||
|
||||
// Word Select will change 1 clock before the new word starts
|
||||
old_ws <= i2s_ws;
|
||||
if (old_ws != i2s_ws) i2s_next <= 1;
|
||||
end
|
||||
|
||||
if (i2s_next) begin
|
||||
i2s_next <= 0;
|
||||
i2s_cnt <= 0;
|
||||
i2s_buf <= 0;
|
||||
|
||||
if (i2s_ws) mt32_i2s_l <= i2s_buf;
|
||||
else mt32_i2s_r <= i2s_buf;
|
||||
end
|
||||
|
||||
if (reset) begin
|
||||
i2s_buf <= 0;
|
||||
mt32_i2s_l <= 0;
|
||||
mt32_i2s_r <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//
|
||||
// i2c slave
|
||||
//
|
||||
|
||||
reg sda_out;
|
||||
reg [7:0] lcd_data[1024];
|
||||
reg lcd_sz;
|
||||
|
||||
reg reset_r = 0;
|
||||
wire [7:0] mode_req = reset_r ? 8'hA0 : mt32_mode_req ? 8'hA2 : 8'hA1;
|
||||
wire [7:0] rom_req = {6'd0, mt32_rom_req};
|
||||
|
||||
always @(posedge CLK_AUDIO) begin : i2c_slave
|
||||
reg sda_sr, scl_sr;
|
||||
reg old_sda, old_scl;
|
||||
reg sda, scl;
|
||||
reg [7:0] tmp;
|
||||
reg [3:0] cnt = 0;
|
||||
reg [10:0] bcnt = 0;
|
||||
reg ack;
|
||||
reg i2c_rw;
|
||||
reg disp, dispdata;
|
||||
reg [2:0] div;
|
||||
reg old_reset;
|
||||
|
||||
old_reset <= reset;
|
||||
if(old_reset & ~reset) sda_out <= 1;
|
||||
|
||||
div <= div + 1'd1;
|
||||
if(!div) begin
|
||||
sda_sr <= USER_IN[0];
|
||||
if(sda_sr == USER_IN[0]) sda <= sda_sr;
|
||||
old_sda <= sda;
|
||||
|
||||
scl_sr <= USER_IN[3];
|
||||
if(scl_sr == USER_IN[3]) scl <= scl_sr;
|
||||
old_scl <= scl;
|
||||
|
||||
//start
|
||||
if(old_scl & scl & old_sda & ~sda) begin
|
||||
cnt <= 9;
|
||||
bcnt <= 0;
|
||||
ack <= 0;
|
||||
i2c_rw <= 0;
|
||||
disp <= 0;
|
||||
dispdata <= 0;
|
||||
end
|
||||
|
||||
//stop
|
||||
if(old_scl & scl & ~old_sda & sda) begin
|
||||
cnt <= 0;
|
||||
if(dispdata) begin
|
||||
lcd_sz <= ~bcnt[9];
|
||||
mt32_lcd_update <= ~mt32_lcd_update;
|
||||
end
|
||||
end
|
||||
|
||||
//data latch
|
||||
if(~old_scl && scl && cnt) begin
|
||||
tmp <= {tmp[6:0], sda};
|
||||
cnt <= cnt - 1'd1;
|
||||
end
|
||||
|
||||
if(!cnt) sda_out <= 1;
|
||||
|
||||
//data set
|
||||
if(old_scl && ~scl) begin
|
||||
sda_out <= 1;
|
||||
if(cnt == 1) begin
|
||||
if(!bcnt) begin
|
||||
if(tmp[7:1] == 'h45 || tmp[7:1] == 'h3c) begin
|
||||
disp <= (tmp[7:1] == 'h3c);
|
||||
sda_out <= 0;
|
||||
mt32_available <= 1;
|
||||
ack <= 1;
|
||||
i2c_rw <= tmp[0];
|
||||
bcnt <= bcnt + 1'd1;
|
||||
cnt <= 10;
|
||||
end
|
||||
else begin
|
||||
// wrong address, stop
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
else if(ack) begin
|
||||
if(~i2c_rw) begin
|
||||
if(disp) begin
|
||||
if(bcnt == 1) dispdata <= (tmp[7:6] == 2'b01);
|
||||
else if(dispdata) lcd_data[bcnt[9:0] - 2'd2] <= tmp;
|
||||
end
|
||||
else begin
|
||||
if(bcnt == 1) mt32_mode <= tmp;
|
||||
if(bcnt == 2) mt32_rom <= tmp;
|
||||
if(bcnt == 3) mt32_sf <= tmp;
|
||||
if(bcnt == 3) mt32_newmode <= ~mt32_newmode;
|
||||
end
|
||||
end
|
||||
if(~&bcnt) bcnt <= bcnt + 1'd1;
|
||||
sda_out <= 0;
|
||||
cnt <= 10;
|
||||
end
|
||||
end
|
||||
else if(i2c_rw && ack && cnt && ~disp) begin
|
||||
if(bcnt == 1) sda_out <= mode_req[cnt[2:0] - 2'd2];
|
||||
if(bcnt == 2) sda_out <= rom_req[cnt[2:0] - 2'd2];
|
||||
if(bcnt == 3) sda_out <= mt32_sf_req[cnt[2:0] - 2'd2];
|
||||
if(bcnt == 3) reset_r <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if(reset) begin
|
||||
reset_r <= 1;
|
||||
mt32_available <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg old_de, old_vs;
|
||||
reg [7:0] hcnt;
|
||||
reg [6:0] vcnt;
|
||||
reg [7:0] sh;
|
||||
|
||||
if(CE_PIXEL) begin
|
||||
old_de <= VGA_DE;
|
||||
old_vs <= VGA_VS;
|
||||
|
||||
if(~&hcnt) hcnt <= hcnt + 1'd1;
|
||||
sh <= (sh << 1) | (~old_de & VGA_DE);
|
||||
if(sh[7]) hcnt <= 0;
|
||||
|
||||
if(old_de & ~VGA_DE & ~&vcnt) vcnt <= vcnt + 1'd1;
|
||||
if(~old_vs & VGA_VS) vcnt <= 0;
|
||||
|
||||
mt32_lcd_en <= mt32_available & ~hcnt[7] && (lcd_sz ? !vcnt[6] : !vcnt[6:5]);
|
||||
mt32_lcd_pix <= lcd_data[{vcnt[5:3],hcnt[6:0]}][vcnt[2:0]];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
286
Computer_MiST/Interact_MiST/Neuer Ordner/sys/osd.v
Normal file
286
Computer_MiST/Interact_MiST/Neuer Ordner/sys/osd.v
Normal file
@@ -0,0 +1,286 @@
|
||||
// A simple OSD implementation. Can be hooked up between a cores
|
||||
// VGA output and the physical VGA pins
|
||||
|
||||
module osd
|
||||
(
|
||||
input clk_sys,
|
||||
input io_osd,
|
||||
input io_strobe,
|
||||
input [15:0] io_din,
|
||||
|
||||
input clk_video,
|
||||
input [23:0] din,
|
||||
input de_in,
|
||||
input vs_in,
|
||||
input hs_in,
|
||||
output [23:0] dout,
|
||||
output reg de_out,
|
||||
output reg vs_out,
|
||||
output reg hs_out,
|
||||
|
||||
output reg osd_status
|
||||
);
|
||||
|
||||
parameter OSD_COLOR = 3'd4;
|
||||
|
||||
localparam OSD_WIDTH = 12'd256;
|
||||
localparam OSD_HEIGHT = 12'd64;
|
||||
|
||||
`ifdef OSD_HEADER
|
||||
localparam OSD_HDR = 12'd24;
|
||||
`else
|
||||
localparam OSD_HDR = 12'd0;
|
||||
`endif
|
||||
|
||||
reg osd_enable;
|
||||
(* ramstyle="no_rw_check" *) reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096];
|
||||
|
||||
reg info = 0;
|
||||
reg [8:0] infoh;
|
||||
reg [8:0] infow;
|
||||
reg [21:0] infox;
|
||||
reg [21:0] infoy;
|
||||
reg [21:0] osd_h;
|
||||
reg [21:0] osd_t;
|
||||
reg [21:0] osd_w;
|
||||
|
||||
reg [1:0] rot = 0;
|
||||
|
||||
always@(posedge clk_sys) begin
|
||||
reg [12:0] bcnt;
|
||||
reg [7:0] cmd;
|
||||
reg has_cmd;
|
||||
reg old_strobe;
|
||||
reg highres = 0;
|
||||
|
||||
osd_t <= rot[0] ? OSD_WIDTH : (OSD_HEIGHT<<1);
|
||||
osd_h <= rot[0] ? (info ? infow : OSD_WIDTH) : info ? infoh : (OSD_HEIGHT<<highres);
|
||||
osd_w <= rot[0] ? (info ? infoh : (OSD_HEIGHT<<highres)) : (info ? infow : OSD_WIDTH);
|
||||
|
||||
old_strobe <= io_strobe;
|
||||
|
||||
if(~io_osd) begin
|
||||
bcnt <= 0;
|
||||
has_cmd <= 0;
|
||||
cmd <= 0;
|
||||
if(cmd[7:4] == 4) osd_enable <= cmd[0];
|
||||
end else begin
|
||||
if(~old_strobe & io_strobe) begin
|
||||
if(!has_cmd) begin
|
||||
has_cmd <= 1;
|
||||
cmd <= io_din[7:0];
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(io_din[7:4] == 4) begin
|
||||
if(!io_din[0]) {osd_status,highres} <= 0;
|
||||
else {osd_status,info} <= {~io_din[2] & ~io_din[3],io_din[2]};
|
||||
bcnt <= 0;
|
||||
end
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if(io_din[7:5] == 'b001) begin
|
||||
if(io_din[3]) highres <= 1;
|
||||
bcnt <= {io_din[4:0], 8'h00};
|
||||
end
|
||||
end else begin
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(cmd[7:4] == 4) begin
|
||||
if(bcnt == 0) infox <= io_din[11:0];
|
||||
if(bcnt == 1) infoy <= io_din[11:0];
|
||||
if(bcnt == 2) infow <= {io_din[5:0], 3'b000};
|
||||
if(bcnt == 3) infoh <= {io_din[5:0], 3'b000};
|
||||
if(bcnt == 4) rot <= io_din[1:0];
|
||||
end
|
||||
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if(cmd[7:5] == 'b001) osd_buffer[bcnt] <= io_din[7:0];
|
||||
|
||||
bcnt <= bcnt + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
(* direct_enable *) reg ce_pix;
|
||||
always @(posedge clk_video) begin
|
||||
reg [21:0] cnt = 0;
|
||||
reg [21:0] pixsz, pixcnt;
|
||||
reg deD;
|
||||
|
||||
cnt <= cnt + 1'd1;
|
||||
deD <= de_in;
|
||||
|
||||
pixcnt <= pixcnt + 1'd1;
|
||||
if(pixcnt == pixsz) pixcnt <= 0;
|
||||
ce_pix <= !pixcnt;
|
||||
|
||||
if(~deD && de_in) cnt <= 0;
|
||||
|
||||
if(deD && ~de_in) begin
|
||||
pixsz <= (((cnt+1'b1) >> (9-rot[0])) > 1) ? (((cnt+1'b1) >> (9-rot[0])) - 1'd1) : 22'd0;
|
||||
pixcnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [2:0] osd_de;
|
||||
reg osd_pixel;
|
||||
reg [21:0] v_cnt;
|
||||
reg v_cnt_h, v_cnt_1, v_cnt_2, v_cnt_3, v_cnt_4;
|
||||
reg [21:0] v_osd_start_h, v_osd_start_1, v_osd_start_2, v_osd_start_3, v_osd_start_4, v_osd_start_5;
|
||||
reg [21:0] v_info_start_h, v_info_start_1, v_info_start_2, v_info_start_3, v_info_start_4, v_info_start_5;
|
||||
|
||||
wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
|
||||
|
||||
// pipeline the comparisons a bit
|
||||
always @(posedge clk_video) if(ce_pix) begin
|
||||
v_cnt_h <= v_cnt < osd_t;
|
||||
v_cnt_1 <= v_cnt < 320;
|
||||
v_cnt_2 <= v_cnt < 640;
|
||||
v_cnt_3 <= v_cnt < 960;
|
||||
v_cnt_4 <= v_cnt < 1280;
|
||||
|
||||
v_osd_start_h <= (v_cnt-(osd_h_hdr>>1))>>1;
|
||||
v_osd_start_1 <= (v_cnt-osd_h_hdr)>>1;
|
||||
v_osd_start_2 <= (v_cnt-(osd_h_hdr<<1))>>1;
|
||||
v_osd_start_3 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1;
|
||||
v_osd_start_4 <= (v_cnt-(osd_h_hdr<<2))>>1;
|
||||
v_osd_start_5 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<2)))>>1;
|
||||
|
||||
v_info_start_h <= rot[0] ? infox : infoy;
|
||||
v_info_start_1 <= rot[0] ? infox : infoy;
|
||||
v_info_start_2 <= rot[0] ? (infox<<1) : (infoy<<1);
|
||||
v_info_start_3 <= rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1));
|
||||
v_info_start_4 <= rot[0] ? (infox << 2) : (infoy << 2);
|
||||
v_info_start_5 <= rot[0] ? (infox + (infox << 2)) : (infoy + (infoy << 2));
|
||||
end
|
||||
|
||||
always @(posedge clk_video) begin
|
||||
reg deD;
|
||||
reg [2:0] osd_div;
|
||||
reg [2:0] multiscan;
|
||||
reg [7:0] osd_byte;
|
||||
reg [23:0] h_cnt;
|
||||
reg [21:0] dsp_width;
|
||||
reg [21:0] osd_vcnt;
|
||||
reg [21:0] h_osd_start;
|
||||
reg [21:0] v_osd_start;
|
||||
reg [21:0] osd_hcnt;
|
||||
reg [21:0] osd_hcnt2;
|
||||
reg osd_de1,osd_de2;
|
||||
reg [1:0] osd_en;
|
||||
reg f1;
|
||||
reg half;
|
||||
|
||||
if(ce_pix) begin
|
||||
|
||||
deD <= de_in;
|
||||
if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
|
||||
|
||||
if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
|
||||
if(~&osd_hcnt2) osd_hcnt2 <= osd_hcnt2 + 1'd1;
|
||||
|
||||
if (h_cnt == h_osd_start) begin
|
||||
osd_de[0] <= osd_en[1] && osd_h && (
|
||||
osd_vcnt[11] ? (osd_vcnt[7] && (osd_vcnt[6:0] >= 4) && (osd_vcnt[6:0] < 19)) :
|
||||
(info && (rot == 3)) ? !osd_vcnt[21:8] :
|
||||
(osd_vcnt < osd_h)
|
||||
);
|
||||
osd_hcnt <= 0;
|
||||
osd_hcnt2 <= 0;
|
||||
if(info && rot == 1) osd_hcnt2 <= 22'd128-infoh;
|
||||
end
|
||||
if (osd_hcnt+1 == osd_w) osd_de[0] <= 0;
|
||||
|
||||
// falling edge of de
|
||||
if(!de_in && deD) dsp_width <= h_cnt[21:0];
|
||||
|
||||
// rising edge of de
|
||||
if(de_in && !deD) begin
|
||||
h_cnt <= 0;
|
||||
v_cnt <= v_cnt + 1'd1;
|
||||
h_osd_start <= info ? (rot[0] ? infoy : infox) : (((dsp_width - osd_w)>>1) - 2'd2);
|
||||
|
||||
if(h_cnt > {dsp_width, 2'b00}) begin
|
||||
v_cnt <= 1;
|
||||
f1 <= ~f1; // skip every other frame for interlace compatibility.
|
||||
if(~f1) begin
|
||||
|
||||
osd_en <= (osd_en << 1) | osd_enable;
|
||||
if(~osd_enable) osd_en <= 0;
|
||||
|
||||
half <= 0;
|
||||
if(v_cnt_h) begin
|
||||
multiscan <= 0;
|
||||
v_osd_start <= info ? v_info_start_h : v_osd_start_h;
|
||||
half <= 1;
|
||||
end
|
||||
else if(v_cnt_1 | (rot[0] & v_cnt_2)) begin
|
||||
multiscan <= 0;
|
||||
v_osd_start <= info ? v_info_start_1 : v_osd_start_1;
|
||||
end
|
||||
else if(rot[0] ? v_cnt_3 : v_cnt_2) begin
|
||||
multiscan <= 1;
|
||||
v_osd_start <= info ? v_info_start_2 : v_osd_start_2;
|
||||
end
|
||||
else if(rot[0] ? v_cnt_4 : v_cnt_3) begin
|
||||
multiscan <= 2;
|
||||
v_osd_start <= info ? v_info_start_3 : v_osd_start_3;
|
||||
end
|
||||
else if(rot[0] | v_cnt_4) begin
|
||||
multiscan <= 3;
|
||||
v_osd_start <= info ? v_info_start_4 : v_osd_start_4;
|
||||
end
|
||||
else begin
|
||||
multiscan <= 4;
|
||||
v_osd_start <= info ? v_info_start_5 : v_osd_start_5;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
osd_div <= osd_div + 1'd1;
|
||||
if(osd_div == multiscan) begin
|
||||
osd_div <= 0;
|
||||
if(~osd_vcnt[10]) osd_vcnt <= osd_vcnt + 1'd1 + half;
|
||||
if(osd_vcnt == 'b100010011111 && ~info) osd_vcnt <= 0;
|
||||
end
|
||||
if(v_osd_start == v_cnt) begin
|
||||
{osd_div,osd_vcnt} <= 0;
|
||||
if(info && rot == 3) osd_vcnt <= 22'd256-infow;
|
||||
else if(OSD_HDR && !rot) osd_vcnt <= {~info, 3'b000, ~info, 7'b0000000};
|
||||
end
|
||||
end
|
||||
|
||||
osd_byte <= osd_buffer[rot[0] ? ({osd_hcnt2[6:3], osd_vcnt[7:0]} ^ { {4{~rot[1]}}, {8{rot[1]}} }) : {osd_vcnt[7:3], osd_hcnt[7:0]}];
|
||||
osd_pixel <= osd_byte[rot[0] ? ((osd_hcnt2[2:0]-1'd1) ^ {3{~rot[1]}}) : osd_vcnt[2:0]];
|
||||
osd_de[2:1] <= osd_de[1:0];
|
||||
end
|
||||
end
|
||||
|
||||
reg [23:0] rdout;
|
||||
assign dout = rdout;
|
||||
|
||||
always @(posedge clk_video) begin
|
||||
reg [23:0] ordout1, nrdout1, rdout2, rdout3;
|
||||
reg de1,de2,de3;
|
||||
reg osd_mux;
|
||||
reg vs1,vs2,vs3;
|
||||
reg hs1,hs2,hs3;
|
||||
|
||||
nrdout1 <= din;
|
||||
ordout1 <= {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},// 23:16
|
||||
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},// 15:8
|
||||
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; // 7:0
|
||||
|
||||
osd_mux <= ~osd_de[2];
|
||||
rdout2 <= osd_mux ? nrdout1 : ordout1;
|
||||
rdout3 <= rdout2;
|
||||
|
||||
de1 <= de_in; de2 <= de1; de3 <= de2;
|
||||
hs1 <= hs_in; hs2 <= hs1; hs3 <= hs2;
|
||||
vs1 <= vs_in; vs2 <= vs1; vs3 <= vs2;
|
||||
|
||||
rdout <= rdout3;
|
||||
de_out <= de3;
|
||||
hs_out <= hs3;
|
||||
vs_out <= vs3;
|
||||
end
|
||||
|
||||
endmodule
|
||||
17
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll.13.qip
Normal file
17
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll.13.qip
Normal file
@@ -0,0 +1,17 @@
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
|
||||
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v
|
||||
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v
|
||||
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim"
|
||||
@@ -0,0 +1,17 @@
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"]
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
|
||||
set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"]
|
||||
set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"]
|
||||
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
|
||||
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
|
||||
337
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_audio.qip
Normal file
337
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_audio.qip
Normal file
@@ -0,0 +1,337 @@
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"]
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_QSYS_MODE "UNKNOWN"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlv"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlvXzAwMDI="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjQuNTc2::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTUyODMyMTE2Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTc=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjQuNTc2MDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw5LDgsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDE3Ljc5MiBNSHosMTUyODMyMTE2Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
|
||||
|
||||
set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"]
|
||||
set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"]
|
||||
set_global_assignment -library "pll_audio" -name QIP_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.qip"]
|
||||
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
|
||||
252
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_audio.v
Normal file
252
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_audio.v
Normal file
@@ -0,0 +1,252 @@
|
||||
// megafunction wizard: %Altera PLL v17.0%
|
||||
// GENERATION: XML
|
||||
// pll_audio.v
|
||||
|
||||
// Generated using ACDS version 17.0 602
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll_audio (
|
||||
input wire refclk, // refclk.clk
|
||||
input wire rst, // reset.reset
|
||||
output wire outclk_0 // outclk0.clk
|
||||
);
|
||||
|
||||
pll_audio_0002 pll_audio_inst (
|
||||
.refclk (refclk), // refclk.clk
|
||||
.rst (rst), // reset.reset
|
||||
.outclk_0 (outclk_0), // outclk0.clk
|
||||
.locked () // (terminated)
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2020 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
|
||||
// Retrieval info: <generic name="debug_print_output" value="false" />
|
||||
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
|
||||
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
|
||||
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
|
||||
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
|
||||
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
|
||||
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
|
||||
// Retrieval info: <generic name="gui_use_locked" value="false" />
|
||||
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
|
||||
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
|
||||
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency0" value="24.576" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
|
||||
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
|
||||
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
|
||||
// Retrieval info: <generic name="gui_en_reconf" value="false" />
|
||||
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
|
||||
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
|
||||
// Retrieval info: <generic name="gui_phout_division" value="1" />
|
||||
// Retrieval info: <generic name="gui_mif_generate" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
|
||||
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
|
||||
// Retrieval info: <generic name="gui_dps_num" value="1" />
|
||||
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
|
||||
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
|
||||
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
|
||||
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
|
||||
// Retrieval info: <generic name="gui_active_clk" value="false" />
|
||||
// Retrieval info: <generic name="gui_clk_bad" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
|
||||
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
|
||||
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
|
||||
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : pll_audio.vo
|
||||
// RELATED_FILES: pll_audio.v, pll_audio_0002.v
|
||||
@@ -0,0 +1,4 @@
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
|
||||
@@ -0,0 +1,87 @@
|
||||
`timescale 1ns/10ps
|
||||
module pll_audio_0002(
|
||||
|
||||
// interface 'refclk'
|
||||
input wire refclk,
|
||||
|
||||
// interface 'reset'
|
||||
input wire rst,
|
||||
|
||||
// interface 'outclk0'
|
||||
output wire outclk_0,
|
||||
|
||||
// interface 'locked'
|
||||
output wire locked
|
||||
);
|
||||
|
||||
altera_pll #(
|
||||
.fractional_vco_multiplier("true"),
|
||||
.reference_clock_frequency("50.0 MHz"),
|
||||
.operation_mode("direct"),
|
||||
.number_of_clocks(1),
|
||||
.output_clock_frequency0("24.576000 MHz"),
|
||||
.phase_shift0("0 ps"),
|
||||
.duty_cycle0(50),
|
||||
.output_clock_frequency1("0 MHz"),
|
||||
.phase_shift1("0 ps"),
|
||||
.duty_cycle1(50),
|
||||
.output_clock_frequency2("0 MHz"),
|
||||
.phase_shift2("0 ps"),
|
||||
.duty_cycle2(50),
|
||||
.output_clock_frequency3("0 MHz"),
|
||||
.phase_shift3("0 ps"),
|
||||
.duty_cycle3(50),
|
||||
.output_clock_frequency4("0 MHz"),
|
||||
.phase_shift4("0 ps"),
|
||||
.duty_cycle4(50),
|
||||
.output_clock_frequency5("0 MHz"),
|
||||
.phase_shift5("0 ps"),
|
||||
.duty_cycle5(50),
|
||||
.output_clock_frequency6("0 MHz"),
|
||||
.phase_shift6("0 ps"),
|
||||
.duty_cycle6(50),
|
||||
.output_clock_frequency7("0 MHz"),
|
||||
.phase_shift7("0 ps"),
|
||||
.duty_cycle7(50),
|
||||
.output_clock_frequency8("0 MHz"),
|
||||
.phase_shift8("0 ps"),
|
||||
.duty_cycle8(50),
|
||||
.output_clock_frequency9("0 MHz"),
|
||||
.phase_shift9("0 ps"),
|
||||
.duty_cycle9(50),
|
||||
.output_clock_frequency10("0 MHz"),
|
||||
.phase_shift10("0 ps"),
|
||||
.duty_cycle10(50),
|
||||
.output_clock_frequency11("0 MHz"),
|
||||
.phase_shift11("0 ps"),
|
||||
.duty_cycle11(50),
|
||||
.output_clock_frequency12("0 MHz"),
|
||||
.phase_shift12("0 ps"),
|
||||
.duty_cycle12(50),
|
||||
.output_clock_frequency13("0 MHz"),
|
||||
.phase_shift13("0 ps"),
|
||||
.duty_cycle13(50),
|
||||
.output_clock_frequency14("0 MHz"),
|
||||
.phase_shift14("0 ps"),
|
||||
.duty_cycle14(50),
|
||||
.output_clock_frequency15("0 MHz"),
|
||||
.phase_shift15("0 ps"),
|
||||
.duty_cycle15(50),
|
||||
.output_clock_frequency16("0 MHz"),
|
||||
.phase_shift16("0 ps"),
|
||||
.duty_cycle16(50),
|
||||
.output_clock_frequency17("0 MHz"),
|
||||
.phase_shift17("0 ps"),
|
||||
.duty_cycle17(50),
|
||||
.pll_type("General"),
|
||||
.pll_subtype("General")
|
||||
) altera_pll_i (
|
||||
.rst (rst),
|
||||
.outclk ({outclk_0}),
|
||||
.locked (locked),
|
||||
.fboutclk ( ),
|
||||
.fbclk (1'b0),
|
||||
.refclk (refclk)
|
||||
);
|
||||
endmodule
|
||||
|
||||
44
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_cfg.qip
Normal file
44
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_cfg.qip
Normal file
@@ -0,0 +1,44 @@
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"]
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
|
||||
set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
|
||||
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"]
|
||||
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
|
||||
86
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_cfg.v
Normal file
86
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_cfg.v
Normal file
@@ -0,0 +1,86 @@
|
||||
// megafunction wizard: %Altera PLL Reconfig v17.0%
|
||||
// GENERATION: XML
|
||||
// pll_cfg.v
|
||||
|
||||
// Generated using ACDS version 17.0 598
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll_cfg #(
|
||||
parameter ENABLE_BYTEENABLE = 0,
|
||||
parameter BYTEENABLE_WIDTH = 4,
|
||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||
parameter RECONFIG_DATA_WIDTH = 32,
|
||||
parameter reconf_width = 64,
|
||||
parameter WAIT_FOR_LOCK = 1
|
||||
) (
|
||||
input wire mgmt_clk, // mgmt_clk.clk
|
||||
input wire mgmt_reset, // mgmt_reset.reset
|
||||
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
|
||||
input wire mgmt_read, // .read
|
||||
input wire mgmt_write, // .write
|
||||
output wire [31:0] mgmt_readdata, // .readdata
|
||||
input wire [5:0] mgmt_address, // .address
|
||||
input wire [31:0] mgmt_writedata, // .writedata
|
||||
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
|
||||
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
|
||||
);
|
||||
|
||||
altera_pll_reconfig_top #(
|
||||
.device_family ("Cyclone V"),
|
||||
.ENABLE_MIF (0),
|
||||
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
|
||||
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
|
||||
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
|
||||
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
|
||||
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
|
||||
.reconf_width (reconf_width),
|
||||
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
|
||||
) pll_cfg_inst (
|
||||
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
|
||||
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
|
||||
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
|
||||
.mgmt_read (mgmt_read), // .read
|
||||
.mgmt_write (mgmt_write), // .write
|
||||
.mgmt_readdata (mgmt_readdata), // .readdata
|
||||
.mgmt_address (mgmt_address), // .address
|
||||
.mgmt_writedata (mgmt_writedata), // .writedata
|
||||
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
|
||||
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
|
||||
.mgmt_byteenable (4'b0000) // (terminated)
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2018 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
|
||||
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
|
||||
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : pll_cfg.vo
|
||||
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,428 @@
|
||||
// (C) 2001-2017 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel MegaCore Function License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module altera_pll_reconfig_top
|
||||
#(
|
||||
parameter reconf_width = 64,
|
||||
parameter device_family = "Stratix V",
|
||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||
parameter RECONFIG_DATA_WIDTH = 32,
|
||||
|
||||
parameter ROM_ADDR_WIDTH = 9,
|
||||
parameter ROM_DATA_WIDTH = 32,
|
||||
parameter ROM_NUM_WORDS = 512,
|
||||
|
||||
parameter ENABLE_MIF = 0,
|
||||
parameter MIF_FILE_NAME = "",
|
||||
|
||||
parameter ENABLE_BYTEENABLE = 0,
|
||||
parameter BYTEENABLE_WIDTH = 4,
|
||||
parameter WAIT_FOR_LOCK = 1
|
||||
) (
|
||||
|
||||
//input
|
||||
input wire mgmt_clk,
|
||||
input wire mgmt_reset,
|
||||
|
||||
|
||||
//conduits
|
||||
output wire [reconf_width-1:0] reconfig_to_pll,
|
||||
input wire [reconf_width-1:0] reconfig_from_pll,
|
||||
|
||||
// user data (avalon-MM slave interface)
|
||||
output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata,
|
||||
output wire mgmt_waitrequest,
|
||||
input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address,
|
||||
input wire mgmt_read,
|
||||
input wire mgmt_write,
|
||||
input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata,
|
||||
|
||||
//conditional input
|
||||
input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable
|
||||
);
|
||||
|
||||
localparam NM28_START_REG = 6'b000010;
|
||||
localparam NM20_START_REG = 9'b000000000;
|
||||
localparam NM20_MIFSTART_ADDR = 9'b000010000;
|
||||
|
||||
localparam MIF_STATE_DONE = 2'b00;
|
||||
localparam MIF_STATE_START = 2'b01;
|
||||
localparam MIF_STATE_BUSY = 2'b10;
|
||||
|
||||
wire mgmt_byteenable_write;
|
||||
assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ?
|
||||
((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) :
|
||||
mgmt_write;
|
||||
|
||||
generate
|
||||
if (device_family == "Arria 10")
|
||||
begin:nm20_reconfig
|
||||
if(ENABLE_MIF == 1)
|
||||
begin:mif_reconfig_20nm // Generate Reconfig with MIF
|
||||
|
||||
// MIF-related regs/wires
|
||||
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
|
||||
reg reconfig_mgmt_read;
|
||||
reg reconfig_mgmt_write;
|
||||
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
|
||||
wire reconfig_mgmt_waitrequest;
|
||||
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
|
||||
|
||||
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
|
||||
wire mif_busy;
|
||||
wire mif2reconfig_read;
|
||||
wire mif2reconfig_write;
|
||||
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
|
||||
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
|
||||
reg mif_select;
|
||||
//wire mif_user_start; // start signal provided by user to start mif
|
||||
//reg user_start;
|
||||
|
||||
reg [1:0] mif_curstate;
|
||||
reg [1:0] mif_nextstate;
|
||||
|
||||
wire mif_start; //start signal to mif reader
|
||||
|
||||
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start;
|
||||
// Don't output readdata if MIF streaming is taking place
|
||||
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
|
||||
|
||||
//user must lower this by the time mif streaming is done - suggest to lower after 1 cycle
|
||||
assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR);
|
||||
|
||||
//mif base addr is initially specified by the user
|
||||
assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0];
|
||||
|
||||
//MIF statemachine
|
||||
always @(posedge mgmt_clk)
|
||||
begin
|
||||
if(mgmt_reset)
|
||||
mif_curstate <= MIF_STATE_DONE;
|
||||
else
|
||||
mif_curstate <= mif_nextstate;
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
case (mif_curstate)
|
||||
MIF_STATE_DONE:
|
||||
begin
|
||||
if(mif_start)
|
||||
mif_nextstate <= MIF_STATE_START;
|
||||
else
|
||||
mif_nextstate <= MIF_STATE_DONE;
|
||||
end
|
||||
MIF_STATE_START:
|
||||
begin
|
||||
mif_nextstate <= MIF_STATE_BUSY;
|
||||
end
|
||||
MIF_STATE_BUSY:
|
||||
begin
|
||||
if(mif_busy)
|
||||
mif_nextstate <= MIF_STATE_BUSY;
|
||||
else
|
||||
mif_nextstate <= MIF_STATE_DONE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
//Mif muxes
|
||||
always @(*)
|
||||
begin
|
||||
if (mgmt_reset)
|
||||
begin
|
||||
reconfig_mgmt_addr <= 0;
|
||||
reconfig_mgmt_read <= 0;
|
||||
reconfig_mgmt_write <= 0;
|
||||
reconfig_mgmt_writedata <= 0;
|
||||
//user_start <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
|
||||
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
|
||||
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
|
||||
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
|
||||
//user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (mgmt_reset)
|
||||
begin
|
||||
mif_select <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
twentynm_pll_reconfig_mif_reader
|
||||
#(
|
||||
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
|
||||
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
|
||||
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
|
||||
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
|
||||
.ROM_NUM_WORDS(ROM_NUM_WORDS),
|
||||
.DEVICE_FAMILY(device_family),
|
||||
.ENABLE_MIF(ENABLE_MIF),
|
||||
.MIF_FILE_NAME(MIF_FILE_NAME)
|
||||
) twentynm_pll_reconfig_mif_reader_inst0 (
|
||||
.mif_clk(mgmt_clk),
|
||||
.mif_rst(mgmt_reset),
|
||||
|
||||
//Altera_PLL Reconfig interface
|
||||
//inputs
|
||||
.reconfig_waitrequest(reconfig_mgmt_waitrequest),
|
||||
//.reconfig_read_data(reconfig_mgmt_readdata),
|
||||
//outputs
|
||||
.reconfig_write_data(mif2reconfig_writedata),
|
||||
.reconfig_addr(mif2reconfig_addr),
|
||||
.reconfig_write(mif2reconfig_write),
|
||||
.reconfig_read(mif2reconfig_read),
|
||||
|
||||
//MIF Ctrl Interface
|
||||
//inputs
|
||||
.mif_base_addr(mif_base_addr),
|
||||
.mif_start(mif_start),
|
||||
//outputs
|
||||
.mif_busy(mif_busy)
|
||||
);
|
||||
|
||||
// ------ END MIF-RELATED MANAGEMENT ------
|
||||
|
||||
twentynm_iopll_reconfig_core
|
||||
#(
|
||||
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
|
||||
) twentynm_iopll_reconfig_core_inst (
|
||||
// Inputs
|
||||
.mgmt_clk(mgmt_clk),
|
||||
.mgmt_rst_n(~mgmt_reset),
|
||||
.mgmt_read(reconfig_mgmt_read),
|
||||
.mgmt_write(reconfig_mgmt_write),
|
||||
.mgmt_address(reconfig_mgmt_addr),
|
||||
.mgmt_writedata(reconfig_mgmt_writedata),
|
||||
|
||||
// Outputs
|
||||
.mgmt_readdata(reconfig_mgmt_readdata),
|
||||
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
|
||||
|
||||
// PLL Conduits
|
||||
.reconfig_to_pll(reconfig_to_pll),
|
||||
.reconfig_from_pll(reconfig_from_pll)
|
||||
);
|
||||
|
||||
end // End generate reconfig with MIF
|
||||
else
|
||||
begin:reconfig_core_20nm
|
||||
twentynm_iopll_reconfig_core
|
||||
#(
|
||||
.WAIT_FOR_LOCK(WAIT_FOR_LOCK)
|
||||
) twentynm_iopll_reconfig_core_inst (
|
||||
// Inputs
|
||||
.mgmt_clk(mgmt_clk),
|
||||
.mgmt_rst_n(~mgmt_reset),
|
||||
.mgmt_read(mgmt_read),
|
||||
.mgmt_write(mgmt_byteenable_write),
|
||||
.mgmt_address(mgmt_address),
|
||||
.mgmt_writedata(mgmt_writedata),
|
||||
|
||||
// Outputs
|
||||
.mgmt_readdata(mgmt_readdata),
|
||||
.mgmt_waitrequest(mgmt_waitrequest),
|
||||
|
||||
// PLL Conduits
|
||||
.reconfig_to_pll(reconfig_to_pll),
|
||||
.reconfig_from_pll(reconfig_from_pll)
|
||||
);
|
||||
end
|
||||
end // 20nm reconfig
|
||||
else
|
||||
begin:NM28_reconfig
|
||||
if (ENABLE_MIF == 1)
|
||||
begin:mif_reconfig // Generate Reconfig with MIF
|
||||
|
||||
// MIF-related regs/wires
|
||||
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
|
||||
reg reconfig_mgmt_read;
|
||||
reg reconfig_mgmt_write;
|
||||
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
|
||||
wire reconfig_mgmt_waitrequest;
|
||||
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
|
||||
|
||||
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
|
||||
wire mif2reconfig_busy;
|
||||
wire mif2reconfig_read;
|
||||
wire mif2reconfig_write;
|
||||
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
|
||||
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
|
||||
reg mif_select;
|
||||
reg user_start;
|
||||
|
||||
wire reconfig2mif_start_out;
|
||||
|
||||
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
|
||||
// Don't output readdata if MIF streaming is taking place
|
||||
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
|
||||
|
||||
always @(posedge mgmt_clk)
|
||||
begin
|
||||
if (mgmt_reset)
|
||||
begin
|
||||
reconfig_mgmt_addr <= 0;
|
||||
reconfig_mgmt_read <= 0;
|
||||
reconfig_mgmt_write <= 0;
|
||||
reconfig_mgmt_writedata <= 0;
|
||||
user_start <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
|
||||
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
|
||||
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
|
||||
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
|
||||
user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (mgmt_reset)
|
||||
begin
|
||||
mif_select <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
altera_pll_reconfig_mif_reader
|
||||
#(
|
||||
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
|
||||
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
|
||||
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
|
||||
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
|
||||
.ROM_NUM_WORDS(ROM_NUM_WORDS),
|
||||
.DEVICE_FAMILY(device_family),
|
||||
.ENABLE_MIF(ENABLE_MIF),
|
||||
.MIF_FILE_NAME(MIF_FILE_NAME)
|
||||
) altera_pll_reconfig_mif_reader_inst0 (
|
||||
.mif_clk(mgmt_clk),
|
||||
.mif_rst(mgmt_reset),
|
||||
|
||||
//Altera_PLL Reconfig interface
|
||||
//inputs
|
||||
.reconfig_busy(reconfig_mgmt_waitrequest),
|
||||
.reconfig_read_data(reconfig_mgmt_readdata),
|
||||
//outputs
|
||||
.reconfig_write_data(mif2reconfig_writedata),
|
||||
.reconfig_addr(mif2reconfig_addr),
|
||||
.reconfig_write(mif2reconfig_write),
|
||||
.reconfig_read(mif2reconfig_read),
|
||||
|
||||
//MIF Ctrl Interface
|
||||
//inputs
|
||||
.mif_base_addr(mif_base_addr),
|
||||
.mif_start(reconfig2mif_start_out),
|
||||
//outputs
|
||||
.mif_busy(mif2reconfig_busy)
|
||||
);
|
||||
|
||||
// ------ END MIF-RELATED MANAGEMENT ------
|
||||
|
||||
|
||||
altera_pll_reconfig_core
|
||||
#(
|
||||
.reconf_width(reconf_width),
|
||||
.device_family(device_family),
|
||||
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
|
||||
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
|
||||
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
|
||||
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
|
||||
.ROM_NUM_WORDS(ROM_NUM_WORDS)
|
||||
) altera_pll_reconfig_core_inst0 (
|
||||
//inputs
|
||||
.mgmt_clk(mgmt_clk),
|
||||
.mgmt_reset(mgmt_reset),
|
||||
|
||||
//PLL interface conduits
|
||||
.reconfig_to_pll(reconfig_to_pll),
|
||||
.reconfig_from_pll(reconfig_from_pll),
|
||||
|
||||
//User data outputs
|
||||
.mgmt_readdata(reconfig_mgmt_readdata),
|
||||
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
|
||||
|
||||
//User data inputs
|
||||
.mgmt_address(reconfig_mgmt_addr),
|
||||
.mgmt_read(reconfig_mgmt_read),
|
||||
.mgmt_write(reconfig_mgmt_write),
|
||||
.mgmt_writedata(reconfig_mgmt_writedata),
|
||||
|
||||
// other
|
||||
.mif_start_out(reconfig2mif_start_out),
|
||||
.mif_base_addr(mif_base_addr)
|
||||
);
|
||||
|
||||
end // End generate reconfig with MIF
|
||||
else
|
||||
begin:reconfig_core // Generate Reconfig core only
|
||||
|
||||
wire reconfig2mif_start_out;
|
||||
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
|
||||
|
||||
altera_pll_reconfig_core
|
||||
#(
|
||||
.reconf_width(reconf_width),
|
||||
.device_family(device_family),
|
||||
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
|
||||
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
|
||||
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
|
||||
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
|
||||
.ROM_NUM_WORDS(ROM_NUM_WORDS)
|
||||
) altera_pll_reconfig_core_inst0 (
|
||||
//inputs
|
||||
.mgmt_clk(mgmt_clk),
|
||||
.mgmt_reset(mgmt_reset),
|
||||
|
||||
//PLL interface conduits
|
||||
.reconfig_to_pll(reconfig_to_pll),
|
||||
.reconfig_from_pll(reconfig_from_pll),
|
||||
|
||||
//User data outputs
|
||||
.mgmt_readdata(mgmt_readdata),
|
||||
.mgmt_waitrequest(mgmt_waitrequest),
|
||||
|
||||
//User data inputs
|
||||
.mgmt_address(mgmt_address),
|
||||
.mgmt_read(mgmt_read),
|
||||
.mgmt_write(mgmt_byteenable_write),
|
||||
.mgmt_writedata(mgmt_writedata),
|
||||
|
||||
// other
|
||||
.mif_start_out(reconfig2mif_start_out),
|
||||
.mif_base_addr(mif_base_addr)
|
||||
);
|
||||
|
||||
|
||||
end // End generate reconfig core only
|
||||
end // End 28nm Reconfig
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
17
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_hdmi.13.qip
Normal file
17
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_hdmi.13.qip
Normal file
@@ -0,0 +1,17 @@
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
|
||||
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
|
||||
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
|
||||
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
|
||||
483
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_hdmi.qip
Normal file
483
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_hdmi.qip
Normal file
@@ -0,0 +1,483 @@
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
|
||||
set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_QSYS_MODE "UNKNOWN"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWk="
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWlfMDAwMg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfY291dA==::MzI=::cGxsX2ZyYWN0aW9uYWxfY291dA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::cGxsX2RzbV9vdXRfc2Vs"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTQ4LjU=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTQ4LjUwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::dHJ1ZQ==::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NA==::bV9jbnRfaGlfZGl2"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::Mg==::Y19jbnRfaGlfZGl2MA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::MQ==::Y19jbnRfbG9fZGl2MA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::MQ==::Y19jbnRfaGlfZGl2MQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::MQ==::Y19jbnRfbG9fZGl2MQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::MQ==::Y19jbnRfaGlfZGl2Mg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::MQ==::Y19jbnRfbG9fZGl2Mg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::MQ==::Y19jbnRfaGlfZGl2Mw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::MQ==::Y19jbnRfbG9fZGl2Mw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDM=::MQ==::Y19jbnRfcHJzdDM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qz::MA==::Y19jbnRfcGhfbXV4X3Byc3Qz"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NA==::MQ==::Y19jbnRfaGlfZGl2NA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NA==::MQ==::Y19jbnRfbG9fZGl2NA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDQ=::MQ==::Y19jbnRfcHJzdDQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q0::MA==::Y19jbnRfcGhfbXV4X3Byc3Q0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDY=::MQ==::Y19jbnRfcHJzdDY="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q2::MA==::Y19jbnRfcGhfbXV4X3Byc3Q2"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Nw==::MQ==::Y19jbnRfaGlfZGl2Nw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Nw==::MQ==::Y19jbnRfbG9fZGl2Nw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDc=::MQ==::Y19jbnRfcHJzdDc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q3::MA==::Y19jbnRfcGhfbXV4X3Byc3Q3"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OA==::MQ==::Y19jbnRfaGlfZGl2OA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OA==::MQ==::Y19jbnRfbG9fZGl2OA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDg=::MQ==::Y19jbnRfcHJzdDg="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q4::MA==::Y19jbnRfcGhfbXV4X3Byc3Q4"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OQ==::MQ==::Y19jbnRfaGlfZGl2OQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OQ==::MQ==::Y19jbnRfbG9fZGl2OQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDk=::MQ==::Y19jbnRfcHJzdDk="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q5::MA==::Y19jbnRfcGhfbXV4X3Byc3Q5"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTA=::MQ==::Y19jbnRfaGlfZGl2MTA="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTA=::MQ==::Y19jbnRfbG9fZGl2MTA="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEw::MQ==::Y19jbnRfcHJzdDEw"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTA=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTA="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTA=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTA="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTE=::MQ==::Y19jbnRfaGlfZGl2MTE="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTE=::MQ==::Y19jbnRfbG9fZGl2MTE="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEx::MQ==::Y19jbnRfcHJzdDEx"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTE=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTE="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTE=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTE="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTI=::MQ==::Y19jbnRfaGlfZGl2MTI="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTI=::MQ==::Y19jbnRfbG9fZGl2MTI="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEy::MQ==::Y19jbnRfcHJzdDEy"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTI=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTI="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTI=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTI="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTM=::MQ==::Y19jbnRfaGlfZGl2MTM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTM=::MQ==::Y19jbnRfbG9fZGl2MTM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEz::MQ==::Y19jbnRfcHJzdDEz"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTM=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTM=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTQ=::MQ==::Y19jbnRfaGlfZGl2MTQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTQ=::MQ==::Y19jbnRfbG9fZGl2MTQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE0::MQ==::Y19jbnRfcHJzdDE0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTQ=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTQ=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTU=::MQ==::Y19jbnRfaGlfZGl2MTU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTU=::MQ==::Y19jbnRfbG9fZGl2MTU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE1::MQ==::Y19jbnRfcHJzdDE1"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTU=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTU=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTY=::MQ==::Y19jbnRfaGlfZGl2MTY="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTY=::MQ==::Y19jbnRfbG9fZGl2MTY="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE2::MQ==::Y19jbnRfcHJzdDE2"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNg=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTY=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTY="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTY=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTY="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTc=::MQ==::Y19jbnRfaGlfZGl2MTc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTc=::MQ==::Y19jbnRfbG9fZGl2MTc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE3::MQ==::Y19jbnRfcHJzdDE3"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTc=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTc=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::Mg==::cGxsX3Zjb19kaXY="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MjA=::cGxsX2NwX2N1cnJlbnQ="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::NDAwMA==::cGxsX2J3Y3RybA=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NDQ1LjQ5OTk5OSBNSHo=::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MzkwODQyMDE1Mw==::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::bm9uZQ==::bWltaWNfZmJjbGtfdHlwZQ=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDQ1LjQ5OTk5OSBNSHosMzkwODQyMDE1Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
|
||||
|
||||
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
|
||||
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
|
||||
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.qip"]
|
||||
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
|
||||
256
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_hdmi.v
Normal file
256
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_hdmi.v
Normal file
@@ -0,0 +1,256 @@
|
||||
// megafunction wizard: %Altera PLL v17.0%
|
||||
// GENERATION: XML
|
||||
// pll_hdmi.v
|
||||
|
||||
// Generated using ACDS version 17.0 598
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll_hdmi (
|
||||
input wire refclk, // refclk.clk
|
||||
input wire rst, // reset.reset
|
||||
output wire outclk_0, // outclk0.clk
|
||||
input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
|
||||
output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
|
||||
);
|
||||
|
||||
pll_hdmi_0002 pll_hdmi_inst (
|
||||
.refclk (refclk), // refclk.clk
|
||||
.rst (rst), // reset.reset
|
||||
.outclk_0 (outclk_0), // outclk0.clk
|
||||
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
|
||||
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
|
||||
.locked () // (terminated)
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2018 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
|
||||
// Retrieval info: <generic name="debug_print_output" value="false" />
|
||||
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
|
||||
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
|
||||
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
|
||||
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
|
||||
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
|
||||
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
|
||||
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
|
||||
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
|
||||
// Retrieval info: <generic name="gui_use_locked" value="false" />
|
||||
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
|
||||
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
|
||||
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency0" value="148.5" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency1" value="65.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency2" value="27.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
|
||||
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
|
||||
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
|
||||
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
|
||||
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
|
||||
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
|
||||
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
|
||||
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
|
||||
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
|
||||
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
|
||||
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
|
||||
// Retrieval info: <generic name="gui_en_reconf" value="true" />
|
||||
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
|
||||
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
|
||||
// Retrieval info: <generic name="gui_phout_division" value="1" />
|
||||
// Retrieval info: <generic name="gui_mif_generate" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
|
||||
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
|
||||
// Retrieval info: <generic name="gui_dps_num" value="1" />
|
||||
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
|
||||
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
|
||||
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
|
||||
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
|
||||
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
|
||||
// Retrieval info: <generic name="gui_active_clk" value="false" />
|
||||
// Retrieval info: <generic name="gui_clk_bad" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
|
||||
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
|
||||
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
|
||||
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : pll_hdmi.vo
|
||||
// RELATED_FILES: pll_hdmi.v, pll_hdmi_0002.v
|
||||
@@ -0,0 +1,2 @@
|
||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||
set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||
@@ -0,0 +1,241 @@
|
||||
`timescale 1ns/10ps
|
||||
module pll_hdmi_0002(
|
||||
|
||||
// interface 'refclk'
|
||||
input wire refclk,
|
||||
|
||||
// interface 'reset'
|
||||
input wire rst,
|
||||
|
||||
// interface 'outclk0'
|
||||
output wire outclk_0,
|
||||
|
||||
// interface 'locked'
|
||||
output wire locked,
|
||||
|
||||
// interface 'reconfig_to_pll'
|
||||
input wire [63:0] reconfig_to_pll,
|
||||
|
||||
// interface 'reconfig_from_pll'
|
||||
output wire [63:0] reconfig_from_pll
|
||||
);
|
||||
|
||||
altera_pll #(
|
||||
.fractional_vco_multiplier("true"),
|
||||
.reference_clock_frequency("50.0 MHz"),
|
||||
.pll_fractional_cout(32),
|
||||
.pll_dsm_out_sel("1st_order"),
|
||||
.operation_mode("direct"),
|
||||
.number_of_clocks(1),
|
||||
.output_clock_frequency0("148.500000 MHz"),
|
||||
.phase_shift0("0 ps"),
|
||||
.duty_cycle0(50),
|
||||
.output_clock_frequency1("0 MHz"),
|
||||
.phase_shift1("0 ps"),
|
||||
.duty_cycle1(50),
|
||||
.output_clock_frequency2("0 MHz"),
|
||||
.phase_shift2("0 ps"),
|
||||
.duty_cycle2(50),
|
||||
.output_clock_frequency3("0 MHz"),
|
||||
.phase_shift3("0 ps"),
|
||||
.duty_cycle3(50),
|
||||
.output_clock_frequency4("0 MHz"),
|
||||
.phase_shift4("0 ps"),
|
||||
.duty_cycle4(50),
|
||||
.output_clock_frequency5("0 MHz"),
|
||||
.phase_shift5("0 ps"),
|
||||
.duty_cycle5(50),
|
||||
.output_clock_frequency6("0 MHz"),
|
||||
.phase_shift6("0 ps"),
|
||||
.duty_cycle6(50),
|
||||
.output_clock_frequency7("0 MHz"),
|
||||
.phase_shift7("0 ps"),
|
||||
.duty_cycle7(50),
|
||||
.output_clock_frequency8("0 MHz"),
|
||||
.phase_shift8("0 ps"),
|
||||
.duty_cycle8(50),
|
||||
.output_clock_frequency9("0 MHz"),
|
||||
.phase_shift9("0 ps"),
|
||||
.duty_cycle9(50),
|
||||
.output_clock_frequency10("0 MHz"),
|
||||
.phase_shift10("0 ps"),
|
||||
.duty_cycle10(50),
|
||||
.output_clock_frequency11("0 MHz"),
|
||||
.phase_shift11("0 ps"),
|
||||
.duty_cycle11(50),
|
||||
.output_clock_frequency12("0 MHz"),
|
||||
.phase_shift12("0 ps"),
|
||||
.duty_cycle12(50),
|
||||
.output_clock_frequency13("0 MHz"),
|
||||
.phase_shift13("0 ps"),
|
||||
.duty_cycle13(50),
|
||||
.output_clock_frequency14("0 MHz"),
|
||||
.phase_shift14("0 ps"),
|
||||
.duty_cycle14(50),
|
||||
.output_clock_frequency15("0 MHz"),
|
||||
.phase_shift15("0 ps"),
|
||||
.duty_cycle15(50),
|
||||
.output_clock_frequency16("0 MHz"),
|
||||
.phase_shift16("0 ps"),
|
||||
.duty_cycle16(50),
|
||||
.output_clock_frequency17("0 MHz"),
|
||||
.phase_shift17("0 ps"),
|
||||
.duty_cycle17(50),
|
||||
.pll_type("Cyclone V"),
|
||||
.pll_subtype("Reconfigurable"),
|
||||
.m_cnt_hi_div(4),
|
||||
.m_cnt_lo_div(4),
|
||||
.n_cnt_hi_div(256),
|
||||
.n_cnt_lo_div(256),
|
||||
.m_cnt_bypass_en("false"),
|
||||
.n_cnt_bypass_en("true"),
|
||||
.m_cnt_odd_div_duty_en("false"),
|
||||
.n_cnt_odd_div_duty_en("false"),
|
||||
.c_cnt_hi_div0(2),
|
||||
.c_cnt_lo_div0(1),
|
||||
.c_cnt_prst0(1),
|
||||
.c_cnt_ph_mux_prst0(0),
|
||||
.c_cnt_in_src0("ph_mux_clk"),
|
||||
.c_cnt_bypass_en0("false"),
|
||||
.c_cnt_odd_div_duty_en0("true"),
|
||||
.c_cnt_hi_div1(1),
|
||||
.c_cnt_lo_div1(1),
|
||||
.c_cnt_prst1(1),
|
||||
.c_cnt_ph_mux_prst1(0),
|
||||
.c_cnt_in_src1("ph_mux_clk"),
|
||||
.c_cnt_bypass_en1("true"),
|
||||
.c_cnt_odd_div_duty_en1("false"),
|
||||
.c_cnt_hi_div2(1),
|
||||
.c_cnt_lo_div2(1),
|
||||
.c_cnt_prst2(1),
|
||||
.c_cnt_ph_mux_prst2(0),
|
||||
.c_cnt_in_src2("ph_mux_clk"),
|
||||
.c_cnt_bypass_en2("true"),
|
||||
.c_cnt_odd_div_duty_en2("false"),
|
||||
.c_cnt_hi_div3(1),
|
||||
.c_cnt_lo_div3(1),
|
||||
.c_cnt_prst3(1),
|
||||
.c_cnt_ph_mux_prst3(0),
|
||||
.c_cnt_in_src3("ph_mux_clk"),
|
||||
.c_cnt_bypass_en3("true"),
|
||||
.c_cnt_odd_div_duty_en3("false"),
|
||||
.c_cnt_hi_div4(1),
|
||||
.c_cnt_lo_div4(1),
|
||||
.c_cnt_prst4(1),
|
||||
.c_cnt_ph_mux_prst4(0),
|
||||
.c_cnt_in_src4("ph_mux_clk"),
|
||||
.c_cnt_bypass_en4("true"),
|
||||
.c_cnt_odd_div_duty_en4("false"),
|
||||
.c_cnt_hi_div5(1),
|
||||
.c_cnt_lo_div5(1),
|
||||
.c_cnt_prst5(1),
|
||||
.c_cnt_ph_mux_prst5(0),
|
||||
.c_cnt_in_src5("ph_mux_clk"),
|
||||
.c_cnt_bypass_en5("true"),
|
||||
.c_cnt_odd_div_duty_en5("false"),
|
||||
.c_cnt_hi_div6(1),
|
||||
.c_cnt_lo_div6(1),
|
||||
.c_cnt_prst6(1),
|
||||
.c_cnt_ph_mux_prst6(0),
|
||||
.c_cnt_in_src6("ph_mux_clk"),
|
||||
.c_cnt_bypass_en6("true"),
|
||||
.c_cnt_odd_div_duty_en6("false"),
|
||||
.c_cnt_hi_div7(1),
|
||||
.c_cnt_lo_div7(1),
|
||||
.c_cnt_prst7(1),
|
||||
.c_cnt_ph_mux_prst7(0),
|
||||
.c_cnt_in_src7("ph_mux_clk"),
|
||||
.c_cnt_bypass_en7("true"),
|
||||
.c_cnt_odd_div_duty_en7("false"),
|
||||
.c_cnt_hi_div8(1),
|
||||
.c_cnt_lo_div8(1),
|
||||
.c_cnt_prst8(1),
|
||||
.c_cnt_ph_mux_prst8(0),
|
||||
.c_cnt_in_src8("ph_mux_clk"),
|
||||
.c_cnt_bypass_en8("true"),
|
||||
.c_cnt_odd_div_duty_en8("false"),
|
||||
.c_cnt_hi_div9(1),
|
||||
.c_cnt_lo_div9(1),
|
||||
.c_cnt_prst9(1),
|
||||
.c_cnt_ph_mux_prst9(0),
|
||||
.c_cnt_in_src9("ph_mux_clk"),
|
||||
.c_cnt_bypass_en9("true"),
|
||||
.c_cnt_odd_div_duty_en9("false"),
|
||||
.c_cnt_hi_div10(1),
|
||||
.c_cnt_lo_div10(1),
|
||||
.c_cnt_prst10(1),
|
||||
.c_cnt_ph_mux_prst10(0),
|
||||
.c_cnt_in_src10("ph_mux_clk"),
|
||||
.c_cnt_bypass_en10("true"),
|
||||
.c_cnt_odd_div_duty_en10("false"),
|
||||
.c_cnt_hi_div11(1),
|
||||
.c_cnt_lo_div11(1),
|
||||
.c_cnt_prst11(1),
|
||||
.c_cnt_ph_mux_prst11(0),
|
||||
.c_cnt_in_src11("ph_mux_clk"),
|
||||
.c_cnt_bypass_en11("true"),
|
||||
.c_cnt_odd_div_duty_en11("false"),
|
||||
.c_cnt_hi_div12(1),
|
||||
.c_cnt_lo_div12(1),
|
||||
.c_cnt_prst12(1),
|
||||
.c_cnt_ph_mux_prst12(0),
|
||||
.c_cnt_in_src12("ph_mux_clk"),
|
||||
.c_cnt_bypass_en12("true"),
|
||||
.c_cnt_odd_div_duty_en12("false"),
|
||||
.c_cnt_hi_div13(1),
|
||||
.c_cnt_lo_div13(1),
|
||||
.c_cnt_prst13(1),
|
||||
.c_cnt_ph_mux_prst13(0),
|
||||
.c_cnt_in_src13("ph_mux_clk"),
|
||||
.c_cnt_bypass_en13("true"),
|
||||
.c_cnt_odd_div_duty_en13("false"),
|
||||
.c_cnt_hi_div14(1),
|
||||
.c_cnt_lo_div14(1),
|
||||
.c_cnt_prst14(1),
|
||||
.c_cnt_ph_mux_prst14(0),
|
||||
.c_cnt_in_src14("ph_mux_clk"),
|
||||
.c_cnt_bypass_en14("true"),
|
||||
.c_cnt_odd_div_duty_en14("false"),
|
||||
.c_cnt_hi_div15(1),
|
||||
.c_cnt_lo_div15(1),
|
||||
.c_cnt_prst15(1),
|
||||
.c_cnt_ph_mux_prst15(0),
|
||||
.c_cnt_in_src15("ph_mux_clk"),
|
||||
.c_cnt_bypass_en15("true"),
|
||||
.c_cnt_odd_div_duty_en15("false"),
|
||||
.c_cnt_hi_div16(1),
|
||||
.c_cnt_lo_div16(1),
|
||||
.c_cnt_prst16(1),
|
||||
.c_cnt_ph_mux_prst16(0),
|
||||
.c_cnt_in_src16("ph_mux_clk"),
|
||||
.c_cnt_bypass_en16("true"),
|
||||
.c_cnt_odd_div_duty_en16("false"),
|
||||
.c_cnt_hi_div17(1),
|
||||
.c_cnt_lo_div17(1),
|
||||
.c_cnt_prst17(1),
|
||||
.c_cnt_ph_mux_prst17(0),
|
||||
.c_cnt_in_src17("ph_mux_clk"),
|
||||
.c_cnt_bypass_en17("true"),
|
||||
.c_cnt_odd_div_duty_en17("false"),
|
||||
.pll_vco_div(2),
|
||||
.pll_cp_current(20),
|
||||
.pll_bwctrl(4000),
|
||||
.pll_output_clk_frequency("445.499999 MHz"),
|
||||
.pll_fractional_division("3908420153"),
|
||||
.mimic_fbclk_type("none"),
|
||||
.pll_fbclk_mux_1("glb"),
|
||||
.pll_fbclk_mux_2("m_cnt"),
|
||||
.pll_m_cnt_in_src("ph_mux_clk"),
|
||||
.pll_slf_rst("true")
|
||||
) altera_pll_i (
|
||||
.rst (rst),
|
||||
.outclk ({outclk_0}),
|
||||
.locked (locked),
|
||||
.reconfig_to_pll (reconfig_to_pll),
|
||||
.fboutclk ( ),
|
||||
.fbclk (1'b0),
|
||||
.refclk (refclk),
|
||||
.reconfig_from_pll (reconfig_from_pll)
|
||||
);
|
||||
endmodule
|
||||
|
||||
433
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_hdmi_adj.vhd
Normal file
433
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_hdmi_adj.vhd
Normal file
@@ -0,0 +1,433 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- HDMI PLL Adjust
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
-- Changes the HDMI PLL frequency according to the scaler suggestions.
|
||||
--------------------------------------------
|
||||
-- LLTUNE :
|
||||
-- 0 : Input Display Enable
|
||||
-- 1 : Input Vsync
|
||||
-- 2 : Input Interlaced mode
|
||||
-- 3 : Input Interlaced field
|
||||
-- 4 : Output Image frame
|
||||
-- 5 :
|
||||
-- 6 : Input clock
|
||||
-- 7 : Output clock
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY pll_hdmi_adj IS
|
||||
PORT (
|
||||
-- Scaler
|
||||
llena : IN std_logic; -- 0=Disabled 1=Enabled
|
||||
lltune : IN unsigned(15 DOWNTO 0); -- Outputs from scaler
|
||||
|
||||
locked : OUT std_logic;
|
||||
|
||||
-- Signals from reconfig commands
|
||||
i_waitrequest : OUT std_logic;
|
||||
i_write : IN std_logic;
|
||||
i_address : IN unsigned(5 DOWNTO 0);
|
||||
i_writedata : IN unsigned(31 DOWNTO 0);
|
||||
|
||||
-- Outputs to PLL_HDMI_CFG
|
||||
o_waitrequest : IN std_logic;
|
||||
o_write : OUT std_logic;
|
||||
o_address : OUT unsigned(5 DOWNTO 0);
|
||||
o_writedata : OUT unsigned(31 DOWNTO 0);
|
||||
|
||||
------------------------------------
|
||||
clk : IN std_logic;
|
||||
reset_na : IN std_logic
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
END ENTITY pll_hdmi_adj;
|
||||
|
||||
--##############################################################################
|
||||
|
||||
ARCHITECTURE rtl OF pll_hdmi_adj IS
|
||||
|
||||
SIGNAL i_clk,i_de,i_de2,i_vss,i_vss2,i_vss_delay,i_ce : std_logic;
|
||||
SIGNAL i_linecpt,i_line : natural RANGE 0 TO 2**12-1;
|
||||
SIGNAL i_delay : natural RANGE 0 TO 2**14-1;
|
||||
|
||||
SIGNAL pwrite : std_logic;
|
||||
SIGNAL paddress : unsigned(5 DOWNTO 0);
|
||||
SIGNAL pdata : unsigned(31 DOWNTO 0);
|
||||
TYPE enum_state IS (sIDLE,sW1,sW2,sW3,sW4,sW5,sW6);
|
||||
SIGNAL state : enum_state;
|
||||
SIGNAL tune_freq,tune_phase : unsigned(5 DOWNTO 0);
|
||||
SIGNAL lltune_sync,lltune_sync2,lltune_sync3 : unsigned(15 DOWNTO 0);
|
||||
SIGNAL mfrac,mfrac_mem,mfrac_ref,diff : unsigned(40 DOWNTO 0);
|
||||
SIGNAL mul : unsigned(15 DOWNTO 0);
|
||||
SIGNAL sign,sign_pre : std_logic;
|
||||
SIGNAL expand : boolean;
|
||||
SIGNAL up,modo,phm,dir : std_logic;
|
||||
SIGNAL cpt : natural RANGE 0 TO 3;
|
||||
SIGNAL col : natural RANGE 0 TO 15;
|
||||
|
||||
SIGNAL icpt,ocpt,o2cpt,ssh,ofsize,ifsize : natural RANGE 0 TO 2**24-1;
|
||||
SIGNAL ivss,ivss2,itog : std_logic;
|
||||
SIGNAL ovss,ovss2,otog : std_logic;
|
||||
SIGNAL sync,pulse,los,lop : std_logic;
|
||||
SIGNAL osize,offset,osizep,offsetp : signed(23 DOWNTO 0);
|
||||
SIGNAL logcpt : natural RANGE 0 TO 31;
|
||||
SIGNAL udiff : integer RANGE -2**23 TO 2**23-1 :=0;
|
||||
|
||||
BEGIN
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- 4 lines delay to input
|
||||
i_vss<=lltune(0);
|
||||
i_de <=lltune(1);
|
||||
i_ce <=lltune(5);
|
||||
i_clk<=lltune(6);
|
||||
|
||||
Delay:PROCESS(i_clk) IS
|
||||
BEGIN
|
||||
IF rising_edge(i_clk) THEN
|
||||
IF i_ce='1' THEN
|
||||
-- Measure input line time.
|
||||
i_de2<=i_de;
|
||||
|
||||
IF i_de='1' AND i_de2='0' THEN
|
||||
i_linecpt<=0;
|
||||
IF i_vss='1' THEN
|
||||
i_line<=i_linecpt;
|
||||
END IF;
|
||||
ELSE
|
||||
i_linecpt<=i_linecpt+1;
|
||||
END IF;
|
||||
|
||||
-- Delay 4 lines
|
||||
i_vss2<=i_vss;
|
||||
IF i_vss/=i_vss2 THEN
|
||||
i_delay<=0;
|
||||
ELSIF i_delay=i_line * 4 THEN
|
||||
i_vss_delay<=i_vss;
|
||||
ELSE
|
||||
i_delay<=i_delay+1;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS Delay;
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- Sample image sizes
|
||||
Sampler:PROCESS(clk,reset_na) IS
|
||||
BEGIN
|
||||
IF reset_na='0' THEN
|
||||
--pragma synthesis_off
|
||||
otog<='0';
|
||||
itog<='0';
|
||||
ivss<='0';
|
||||
ivss2<='0';
|
||||
ovss<='0';
|
||||
ovss2<='0';
|
||||
--pragma synthesis_on
|
||||
|
||||
ELSIF rising_edge(clk) THEN
|
||||
-- Clock domain crossing
|
||||
|
||||
ivss<=i_vss_delay; -- <ASYNC>
|
||||
ivss2<=ivss;
|
||||
|
||||
ovss<=lltune(4); -- <ASYNC>
|
||||
ovss2<=ovss;
|
||||
|
||||
otog<=otog XOR (ovss AND NOT ovss2);
|
||||
|
||||
-- Measure output frame time
|
||||
IF ovss='1' AND ovss2='0' AND otog='1' THEN
|
||||
ocpt<=0;
|
||||
osizep<=to_signed(ocpt,24);
|
||||
ELSE
|
||||
ocpt<=ocpt+1;
|
||||
END IF;
|
||||
IF ovss='0' AND ovss2='1' AND otog='0' THEN
|
||||
o2cpt<=0;
|
||||
ELSE
|
||||
o2cpt<=o2cpt+1;
|
||||
END IF;
|
||||
|
||||
-- Measure output image time
|
||||
IF ovss='0' AND ovss2='1' AND otog='0' THEN
|
||||
ofsize<=ocpt;
|
||||
END IF;
|
||||
|
||||
itog<=itog XOR (ivss AND NOT ivss2);
|
||||
|
||||
-- Measure input frame time
|
||||
IF ivss='1' AND ivss2='0' AND itog='1' THEN
|
||||
icpt<=0;
|
||||
osize<=osizep;
|
||||
udiff<=integer(to_integer(osizep)) - integer(icpt);
|
||||
sync<='1';
|
||||
ELSE
|
||||
icpt<=icpt+1;
|
||||
sync<='0';
|
||||
END IF;
|
||||
|
||||
-- Measure input image time
|
||||
IF ivss='0' AND ivss2='1' AND itog='0' THEN
|
||||
ifsize<=icpt;
|
||||
END IF;
|
||||
|
||||
expand<=(ofsize>=ifsize);
|
||||
-- IN | ######### | EXPAND = 1
|
||||
-- OUT | ############# |
|
||||
|
||||
-- IN | ######### | EXPAND = 0
|
||||
-- OUT | ###### |
|
||||
|
||||
IF expand THEN
|
||||
IF ivss='1' AND ivss2='0' AND itog='1' THEN
|
||||
offset<=to_signed(ocpt,24);
|
||||
END IF;
|
||||
ELSE
|
||||
IF ivss='0' AND ivss2='1' AND itog='0' THEN
|
||||
offset<=to_signed(o2cpt,24);
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
--------------------------------------------
|
||||
pulse<='0';
|
||||
IF sync='1' THEN
|
||||
logcpt<=0;
|
||||
ssh<=to_integer(osize);
|
||||
los<='0';
|
||||
lop<='0';
|
||||
|
||||
ELSIF logcpt<24 THEN
|
||||
-- Frequency difference
|
||||
IF udiff>0 AND ssh<udiff AND los='0' THEN
|
||||
tune_freq<='0' & to_unsigned(logcpt,5);
|
||||
los<='1';
|
||||
ELSIF udiff<=0 AND ssh<-udiff AND los='0' THEN
|
||||
tune_freq<='1' & to_unsigned(logcpt,5);
|
||||
los<='1';
|
||||
END IF;
|
||||
-- Phase difference
|
||||
IF offset<osize/2 AND ssh<offset AND lop='0' THEN
|
||||
tune_phase<='0' & to_unsigned(logcpt,5);
|
||||
lop<='1';
|
||||
ELSIF offset>=osize/2 AND ssh<(osize-offset) AND lop='0' THEN
|
||||
tune_phase<='1' & to_unsigned(logcpt,5);
|
||||
lop<='1';
|
||||
END IF;
|
||||
ssh<=ssh/2;
|
||||
logcpt<=logcpt+1;
|
||||
|
||||
ELSIF logcpt=24 THEN
|
||||
pulse<='1';
|
||||
ssh<=ssh/2;
|
||||
logcpt<=logcpt+1;
|
||||
END IF;
|
||||
|
||||
END IF;
|
||||
END PROCESS Sampler;
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
-- 000010 : Start reg "Write either 0 or 1 to start fractional PLL reconf.
|
||||
-- 000100 : M counter
|
||||
-- 000111 : M counter Fractional Value K
|
||||
|
||||
Comb:PROCESS(i_write,i_address,
|
||||
i_writedata,pwrite,paddress,pdata) IS
|
||||
BEGIN
|
||||
IF i_write='1' THEN
|
||||
o_write <=i_write;
|
||||
o_address <=i_address;
|
||||
o_writedata <=i_writedata;
|
||||
ELSE
|
||||
o_write <=pwrite;
|
||||
o_address <=paddress;
|
||||
o_writedata<=pdata;
|
||||
END IF;
|
||||
END PROCESS Comb;
|
||||
|
||||
i_waitrequest<=o_waitrequest WHEN state=sIDLE ELSE '0';
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
Schmurtz:PROCESS(clk,reset_na) IS
|
||||
VARIABLE off_v,ofp_v : natural RANGE 0 TO 63;
|
||||
VARIABLE diff_v : unsigned(40 DOWNTO 0);
|
||||
VARIABLE mulco : unsigned(15 DOWNTO 0);
|
||||
VARIABLE up_v,sign_v : std_logic;
|
||||
BEGIN
|
||||
IF reset_na='0' THEN
|
||||
modo<='0';
|
||||
state<=sIDLE;
|
||||
ELSIF rising_edge(clk) THEN
|
||||
------------------------------------------------------
|
||||
-- Snoop accesses to PLL reconfiguration
|
||||
IF i_address="000100" AND i_write='1' THEN
|
||||
mfrac (40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
|
||||
('0' & i_writedata(7 DOWNTO 0));
|
||||
mfrac_ref(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
|
||||
('0' & i_writedata(7 DOWNTO 0));
|
||||
mfrac_mem(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
|
||||
('0' & i_writedata(7 DOWNTO 0));
|
||||
mul<=i_writedata(15 DOWNTO 0);
|
||||
modo<='1';
|
||||
END IF;
|
||||
|
||||
IF i_address="000111" AND i_write='1' THEN
|
||||
mfrac (31 DOWNTO 0)<=i_writedata;
|
||||
mfrac_ref(31 DOWNTO 0)<=i_writedata;
|
||||
mfrac_mem(31 DOWNTO 0)<=i_writedata;
|
||||
modo<='1';
|
||||
END IF;
|
||||
|
||||
------------------------------------------------------
|
||||
-- Tuning
|
||||
off_v:=to_integer('0' & tune_freq(4 DOWNTO 0));
|
||||
ofp_v:=to_integer('0' & tune_phase(4 DOWNTO 0));
|
||||
--IF off_v<8 THEN off_v:=8; END IF;
|
||||
--IF ofp_v<7 THEN ofp_v:=7; END IF;
|
||||
IF off_v<4 THEN off_v:=4; END IF;
|
||||
IF ofp_v<4 THEN ofp_v:=4; END IF;
|
||||
|
||||
IF off_v>=18 AND ofp_v>=18 THEN
|
||||
locked<=llena;
|
||||
ELSE
|
||||
locked<='0';
|
||||
END IF;
|
||||
|
||||
up_v:='0';
|
||||
IF pulse='1' THEN
|
||||
cpt<=(cpt+1) MOD 4;
|
||||
IF llena='0' THEN
|
||||
-- Recover original freq when disabling low lag mode
|
||||
cpt<=0;
|
||||
col<=0;
|
||||
IF modo='1' THEN
|
||||
mfrac<=mfrac_mem;
|
||||
mfrac_ref<=mfrac_mem;
|
||||
up<='1';
|
||||
modo<='0';
|
||||
END IF;
|
||||
|
||||
ELSIF phm='0' AND cpt=0 THEN
|
||||
-- Frequency adjust
|
||||
sign_v:=tune_freq(5);
|
||||
IF col<10 THEN col<=col+1; END IF;
|
||||
IF off_v>=16 AND col>=10 THEN
|
||||
phm<='1';
|
||||
col<=0;
|
||||
ELSE
|
||||
off_v:=off_v+1;
|
||||
IF off_v>17 THEN
|
||||
off_v:=off_v + 3;
|
||||
END IF;
|
||||
up_v:='1';
|
||||
up<='1';
|
||||
END IF;
|
||||
|
||||
ELSIF cpt=0 THEN
|
||||
-- Phase adjust
|
||||
sign_v:=NOT tune_phase(5);
|
||||
col<=col+1;
|
||||
IF col>=10 THEN
|
||||
phm<='0';
|
||||
up_v:='1';
|
||||
off_v:=31;
|
||||
col<=0;
|
||||
ELSE
|
||||
off_v:=ofp_v + 1;
|
||||
IF ofp_v>7 THEN
|
||||
off_v:=off_v + 1;
|
||||
END IF;
|
||||
IF ofp_v>14 THEN
|
||||
off_v:=off_v + 2;
|
||||
END IF;
|
||||
IF ofp_v>17 THEN
|
||||
off_v:=off_v + 3;
|
||||
END IF;
|
||||
up_v:='1';
|
||||
END IF;
|
||||
up<='1';
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
diff_v:=shift_right(mfrac_ref,off_v);
|
||||
IF sign_v='0' THEN
|
||||
diff_v:=mfrac_ref + diff_v;
|
||||
ELSE
|
||||
diff_v:=mfrac_ref - diff_v;
|
||||
END IF;
|
||||
|
||||
IF up_v='1' THEN
|
||||
mfrac<=diff_v;
|
||||
END IF;
|
||||
|
||||
IF up_v='1' AND phm='0' THEN
|
||||
mfrac_ref<=diff_v;
|
||||
END IF;
|
||||
|
||||
------------------------------------------------------
|
||||
-- Update PLL registers
|
||||
mulco:=mfrac(40 DOWNTO 33) & (mfrac(40 DOWNTO 33) + ('0' & mfrac(32)));
|
||||
|
||||
CASE state IS
|
||||
WHEN sIDLE =>
|
||||
pwrite<='0';
|
||||
IF up='1' THEN
|
||||
up<='0';
|
||||
IF mulco/=mul THEN
|
||||
state<=sW1;
|
||||
ELSE
|
||||
state<=sW3;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
WHEN sW1 => -- Change M multiplier
|
||||
mul<=mulco;
|
||||
pdata<=x"0000" & mulco;
|
||||
paddress<="000100";
|
||||
pwrite<='1';
|
||||
state<=sW2;
|
||||
|
||||
WHEN sW2 =>
|
||||
IF pwrite='1' AND o_waitrequest='0' THEN
|
||||
state<=sW3;
|
||||
pwrite<='0';
|
||||
END IF;
|
||||
|
||||
WHEN sW3 => -- Change M fractional value
|
||||
pdata<=mfrac(31 DOWNTO 0);
|
||||
paddress<="000111";
|
||||
pwrite<='1';
|
||||
state<=sW4;
|
||||
|
||||
WHEN sW4 =>
|
||||
IF pwrite='1' AND o_waitrequest='0' THEN
|
||||
state<=sW5;
|
||||
pwrite<='0';
|
||||
END IF;
|
||||
|
||||
WHEN sW5 =>
|
||||
pdata<=x"0000_0001";
|
||||
paddress<="000010";
|
||||
pwrite<='1';
|
||||
state<=sW6;
|
||||
|
||||
WHEN sW6 =>
|
||||
IF pwrite='1' AND o_waitrequest='0' THEN
|
||||
pwrite<='0';
|
||||
state<=sIDLE;
|
||||
END IF;
|
||||
END CASE;
|
||||
|
||||
END IF;
|
||||
END PROCESS Schmurtz;
|
||||
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
END ARCHITECTURE rtl;
|
||||
|
||||
6
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_q13.qip
Normal file
6
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_q13.qip
Normal file
@@ -0,0 +1,6 @@
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ]
|
||||
4
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_q17.qip
Normal file
4
Computer_MiST/Interact_MiST/Neuer Ordner/sys/pll_q17.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name QIP_FILE rtl/pll.qip
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]
|
||||
211
Computer_MiST/Interact_MiST/Neuer Ordner/sys/scandoubler.v
Normal file
211
Computer_MiST/Interact_MiST/Neuer Ordner/sys/scandoubler.v
Normal file
@@ -0,0 +1,211 @@
|
||||
//
|
||||
// scandoubler.v
|
||||
//
|
||||
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2017-2021 Alexey Melnikov
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
// TODO: Delay vsync one line
|
||||
|
||||
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
// system interface
|
||||
input clk_vid,
|
||||
input hq2x,
|
||||
|
||||
// shifter video interface
|
||||
input ce_pix,
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input hb_in,
|
||||
input vb_in,
|
||||
input [DWIDTH:0] r_in,
|
||||
input [DWIDTH:0] g_in,
|
||||
input [DWIDTH:0] b_in,
|
||||
|
||||
// output interface
|
||||
output ce_pix_out,
|
||||
output reg hs_out,
|
||||
output vs_out,
|
||||
output hb_out,
|
||||
output vb_out,
|
||||
output [DWIDTH:0] r_out,
|
||||
output [DWIDTH:0] g_out,
|
||||
output [DWIDTH:0] b_out
|
||||
);
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
|
||||
|
||||
reg [7:0] pix_len = 0;
|
||||
wire [7:0] pl = pix_len + 1'b1;
|
||||
|
||||
reg [7:0] pix_in_cnt = 0;
|
||||
wire [7:0] pc_in = pix_in_cnt + 1'b1;
|
||||
reg [7:0] pixsz, pixsz2, pixsz4 = 0;
|
||||
|
||||
reg ce_x4i, ce_x1i;
|
||||
always @(posedge clk_vid) begin
|
||||
reg old_ce, valid, hs;
|
||||
|
||||
if(~&pix_len) pix_len <= pl;
|
||||
if(~&pix_in_cnt) pix_in_cnt <= pc_in;
|
||||
|
||||
ce_x4i <= 0;
|
||||
ce_x1i <= 0;
|
||||
|
||||
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
|
||||
if((pc_in == pixsz4) || (pc_in == pixsz2) || (pc_in == (pixsz2+pixsz4))) ce_x4i <= 1;
|
||||
|
||||
old_ce <= ce_pix;
|
||||
if(~old_ce & ce_pix) begin
|
||||
if(valid & ~hb_in & ~vb_in) begin
|
||||
pixsz <= pl;
|
||||
pixsz2 <= {1'b0, pl[7:1]};
|
||||
pixsz4 <= {2'b00, pl[7:2]};
|
||||
end
|
||||
pix_len <= 0;
|
||||
valid <= 1;
|
||||
end
|
||||
|
||||
hs <= hs_in;
|
||||
if((~hs & hs_in) || (pc_in >= pixsz)) begin
|
||||
ce_x4i <= 1;
|
||||
ce_x1i <= 1;
|
||||
pix_in_cnt <= 0;
|
||||
end
|
||||
|
||||
if(hb_in | vb_in) valid <= 0;
|
||||
end
|
||||
|
||||
reg req_line_reset;
|
||||
reg [DWIDTH:0] r_d, g_d, b_d;
|
||||
always @(posedge clk_vid) begin
|
||||
if(ce_x1i) begin
|
||||
req_line_reset <= hb_in;
|
||||
r_d <= r_in;
|
||||
g_d <= g_in;
|
||||
b_d <= b_in;
|
||||
end
|
||||
end
|
||||
|
||||
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
|
||||
(
|
||||
.clk(clk_vid),
|
||||
|
||||
.ce_in(ce_x4i),
|
||||
.inputpixel({b_d,g_d,r_d}),
|
||||
.disable_hq2x(~hq2x),
|
||||
.reset_frame(vb_in),
|
||||
.reset_line(req_line_reset),
|
||||
|
||||
.ce_out(ce_x4o),
|
||||
.read_y(sd_line),
|
||||
.hblank(hbo[0]&hbo[8]),
|
||||
.outpixel({b_out,g_out,r_out})
|
||||
);
|
||||
|
||||
reg [7:0] pix_out_cnt = 0;
|
||||
wire [7:0] pc_out = pix_out_cnt + 1'b1;
|
||||
|
||||
reg ce_x4o, ce_x2o;
|
||||
always @(posedge clk_vid) begin
|
||||
reg hs;
|
||||
|
||||
if(~&pix_out_cnt) pix_out_cnt <= pc_out;
|
||||
|
||||
ce_x4o <= 0;
|
||||
ce_x2o <= 0;
|
||||
|
||||
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
|
||||
if((pc_out == pixsz4) || (pc_out == pixsz2) || (pc_out == (pixsz2+pixsz4))) ce_x4o <= 1;
|
||||
if( pc_out == pixsz2) ce_x2o <= 1;
|
||||
|
||||
hs <= hs_out;
|
||||
if((~hs & hs_out) || (pc_out >= pixsz)) begin
|
||||
ce_x2o <= 1;
|
||||
ce_x4o <= 1;
|
||||
pix_out_cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [1:0] sd_line;
|
||||
reg [3:0] vbo;
|
||||
reg [3:0] vso;
|
||||
reg [8:0] hbo;
|
||||
always @(posedge clk_vid) begin
|
||||
|
||||
reg [31:0] hcnt;
|
||||
reg [30:0] sd_hcnt;
|
||||
reg [30:0] hs_start, hs_end;
|
||||
reg [30:0] hde_start, hde_end;
|
||||
|
||||
reg hs, hb;
|
||||
|
||||
if(ce_x4o) begin
|
||||
hbo[8:1] <= hbo[7:0];
|
||||
end
|
||||
|
||||
// output counter synchronous to input and at twice the rate
|
||||
sd_hcnt <= sd_hcnt + 1'd1;
|
||||
if(sd_hcnt == hde_start) begin
|
||||
sd_hcnt <= 0;
|
||||
vbo[3:1] <= vbo[2:0];
|
||||
end
|
||||
|
||||
if(sd_hcnt == hs_end) begin
|
||||
sd_line <= sd_line + 1'd1;
|
||||
if(&vbo[3:2]) sd_line <= 1;
|
||||
vso[3:1] <= vso[2:0];
|
||||
end
|
||||
|
||||
if(sd_hcnt == hde_start)hbo[0] <= 0;
|
||||
if(sd_hcnt == hde_end) hbo[0] <= 1;
|
||||
|
||||
// replicate horizontal sync at twice the speed
|
||||
if(sd_hcnt == hs_end) hs_out <= 0;
|
||||
if(sd_hcnt == hs_start) hs_out <= 1;
|
||||
|
||||
hs <= hs_in;
|
||||
hb <= hb_in;
|
||||
|
||||
hcnt <= hcnt + 1'd1;
|
||||
if(hb && !hb_in) begin
|
||||
hde_start <= hcnt[31:1];
|
||||
hbo[0] <= 0;
|
||||
hcnt <= 0;
|
||||
sd_hcnt <= 0;
|
||||
vbo <= {vbo[2:0],vb_in};
|
||||
end
|
||||
|
||||
if(!hb && hb_in) hde_end <= hcnt[31:1];
|
||||
|
||||
// falling edge of hsync indicates start of line
|
||||
if(hs && !hs_in) begin
|
||||
hs_end <= hcnt[31:1];
|
||||
vso[0] <= vs_in;
|
||||
end
|
||||
|
||||
// save position of rising edge
|
||||
if(!hs && hs_in) hs_start <= hcnt[31:1];
|
||||
end
|
||||
|
||||
assign vs_out = vso[3];
|
||||
assign ce_pix_out = hq2x ? ce_x4o : ce_x2o;
|
||||
|
||||
//Compensate picture shift after HQ2x
|
||||
assign vb_out = vbo[3];
|
||||
assign hb_out = hbo[6];
|
||||
|
||||
endmodule
|
||||
67
Computer_MiST/Interact_MiST/Neuer Ordner/sys/scanlines.v
Normal file
67
Computer_MiST/Interact_MiST/Neuer Ordner/sys/scanlines.v
Normal file
@@ -0,0 +1,67 @@
|
||||
module scanlines #(parameter v2=0)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [1:0] scanlines,
|
||||
input [23:0] din,
|
||||
input hs_in,vs_in,
|
||||
input de_in,
|
||||
|
||||
output reg [23:0] dout,
|
||||
output reg hs_out,vs_out,
|
||||
output reg de_out
|
||||
);
|
||||
|
||||
reg [1:0] scanline;
|
||||
always @(posedge clk) begin
|
||||
reg old_hs, old_vs;
|
||||
|
||||
old_hs <= hs_in;
|
||||
old_vs <= vs_in;
|
||||
|
||||
if(old_hs && ~hs_in) begin
|
||||
if(v2) begin
|
||||
scanline <= scanline + 1'd1;
|
||||
if (scanline == scanlines) scanline <= 0;
|
||||
end
|
||||
else scanline <= scanline ^ scanlines;
|
||||
end
|
||||
if(old_vs && ~vs_in) scanline <= 0;
|
||||
end
|
||||
|
||||
wire [7:0] r,g,b;
|
||||
assign {r,g,b} = din;
|
||||
|
||||
reg [23:0] d;
|
||||
always @(*) begin
|
||||
case(scanline)
|
||||
1: // reduce 25% = 1/2 + 1/4
|
||||
d = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
|
||||
{1'b0, g[7:1]} + {2'b00, g[7:2]},
|
||||
{1'b0, b[7:1]} + {2'b00, b[7:2]}};
|
||||
|
||||
2: // reduce 50% = 1/2
|
||||
d = {{1'b0, r[7:1]},
|
||||
{1'b0, g[7:1]},
|
||||
{1'b0, b[7:1]}};
|
||||
|
||||
3: // reduce 75% = 1/4
|
||||
d = {{2'b00, r[7:2]},
|
||||
{2'b00, g[7:2]},
|
||||
{2'b00, b[7:2]}};
|
||||
|
||||
default: d = {r,g,b};
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [23:0] dout1, dout2;
|
||||
reg de1,de2,vs1,vs2,hs1,hs2;
|
||||
|
||||
dout <= dout2; dout2 <= dout1; dout1 <= d;
|
||||
vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in;
|
||||
hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in;
|
||||
de_out <= de2; de2 <= de1; de1 <= de_in;
|
||||
end
|
||||
|
||||
endmodule
|
||||
463
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sd_card.sv
Normal file
463
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sd_card.sv
Normal file
@@ -0,0 +1,463 @@
|
||||
//
|
||||
// sd_card.v
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2015-2018 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the Lesser GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// http://elm-chan.org/docs/mmc/mmc_e.html
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
// Made module syncrhronous. Total code refactoring. (Sorgelig)
|
||||
// clk_spi must be at least 2 x sck for proper work.
|
||||
|
||||
module sd_card #(parameter WIDE = 0, OCTAL=0)
|
||||
(
|
||||
input clk_sys,
|
||||
input reset,
|
||||
|
||||
input sdhc,
|
||||
input img_mounted,
|
||||
input [63:0] img_size,
|
||||
|
||||
output reg [31:0] sd_lba,
|
||||
output reg sd_rd,
|
||||
output reg sd_wr,
|
||||
input sd_ack,
|
||||
|
||||
input [AW:0] sd_buff_addr,
|
||||
input [DW:0] sd_buff_dout,
|
||||
output [DW:0] sd_buff_din,
|
||||
input sd_buff_wr,
|
||||
|
||||
// SPI interface
|
||||
input clk_spi,
|
||||
|
||||
input ss,
|
||||
input sck,
|
||||
input [SW:0] mosi,
|
||||
output reg [SW:0] miso
|
||||
);
|
||||
|
||||
localparam AW = WIDE ? 7 : 8;
|
||||
localparam DW = WIDE ? 15 : 7;
|
||||
localparam SZ = OCTAL ? 8 : 1;
|
||||
localparam SW = SZ-1;
|
||||
|
||||
wire [7:0] DATA_TOKEN_CMD25 = 8'hfc;
|
||||
wire [7:0] STOP_TRAN = 8'hfd;
|
||||
wire [7:0] DATA_TOKEN = 8'hfe;
|
||||
wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
|
||||
|
||||
// number of bytes to wait after a command before sending the reply
|
||||
localparam NCR = 5+3; // 5 bytes are required (command length)
|
||||
|
||||
localparam RD_STATE_IDLE = 0;
|
||||
localparam RD_STATE_START = 1;
|
||||
localparam RD_STATE_WAIT_IO = 2;
|
||||
localparam RD_STATE_SEND_TOKEN = 3;
|
||||
localparam RD_STATE_SEND_DATA = 4;
|
||||
localparam RD_STATE_WAIT_M = 5;
|
||||
|
||||
localparam WR_STATE_IDLE = 0;
|
||||
localparam WR_STATE_EXP_DTOKEN = 1;
|
||||
localparam WR_STATE_RECV_DATA = 2;
|
||||
localparam WR_STATE_RECV_CRC0 = 3;
|
||||
localparam WR_STATE_RECV_CRC1 = 4;
|
||||
localparam WR_STATE_SEND_DRESP = 5;
|
||||
localparam WR_STATE_BUSY = 6;
|
||||
|
||||
localparam PREF_STATE_IDLE = 0;
|
||||
localparam PREF_STATE_RD = 1;
|
||||
localparam PREF_STATE_FINISH = 2;
|
||||
|
||||
altsyncram sdbuf
|
||||
(
|
||||
.clock0 (clk_sys),
|
||||
.address_a ({sd_buf,sd_buff_addr}),
|
||||
.data_a (sd_buff_dout),
|
||||
.wren_a (sd_ack & sd_buff_wr),
|
||||
.q_a (sd_buff_din),
|
||||
|
||||
.clock1 (clk_spi),
|
||||
.address_b ({spi_buf,buffer_ptr}),
|
||||
.data_b (buffer_din),
|
||||
.wren_b (buffer_wr),
|
||||
.q_b (buffer_dout),
|
||||
|
||||
.aclr0(1'b0),
|
||||
.aclr1(1'b0),
|
||||
.addressstall_a(1'b0),
|
||||
.addressstall_b(1'b0),
|
||||
.byteena_a(1'b1),
|
||||
.byteena_b(1'b1),
|
||||
.clocken0(1'b1),
|
||||
.clocken1(1'b1),
|
||||
.clocken2(1'b1),
|
||||
.clocken3(1'b1),
|
||||
.eccstatus(),
|
||||
.rden_a(1'b1),
|
||||
.rden_b(1'b1)
|
||||
);
|
||||
defparam
|
||||
sdbuf.numwords_a = 1<<(AW+3),
|
||||
sdbuf.widthad_a = AW+3,
|
||||
sdbuf.width_a = DW+1,
|
||||
sdbuf.numwords_b = 2048,
|
||||
sdbuf.widthad_b = 11,
|
||||
sdbuf.width_b = 8,
|
||||
sdbuf.address_reg_b = "CLOCK1",
|
||||
sdbuf.clock_enable_input_a = "BYPASS",
|
||||
sdbuf.clock_enable_input_b = "BYPASS",
|
||||
sdbuf.clock_enable_output_a = "BYPASS",
|
||||
sdbuf.clock_enable_output_b = "BYPASS",
|
||||
sdbuf.indata_reg_b = "CLOCK1",
|
||||
sdbuf.intended_device_family = "Cyclone V",
|
||||
sdbuf.lpm_type = "altsyncram",
|
||||
sdbuf.operation_mode = "BIDIR_DUAL_PORT",
|
||||
sdbuf.outdata_aclr_a = "NONE",
|
||||
sdbuf.outdata_aclr_b = "NONE",
|
||||
sdbuf.outdata_reg_a = "UNREGISTERED",
|
||||
sdbuf.outdata_reg_b = "UNREGISTERED",
|
||||
sdbuf.power_up_uninitialized = "FALSE",
|
||||
sdbuf.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
|
||||
sdbuf.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
|
||||
sdbuf.width_byteena_a = 1,
|
||||
sdbuf.width_byteena_b = 1,
|
||||
sdbuf.wrcontrol_wraddress_reg_b = "CLOCK1";
|
||||
|
||||
reg [26:0] csd_size;
|
||||
reg csd_sdhc;
|
||||
always @(posedge clk_sys) begin
|
||||
if (img_mounted) begin
|
||||
csd_sdhc <= sdhc;
|
||||
if (sdhc) begin
|
||||
csd_size[0] <= 0;
|
||||
csd_size[22:1] <= img_size[40:19]; // in 512K units
|
||||
csd_size[26:23] <= 0;
|
||||
end
|
||||
else begin
|
||||
csd_size[2:0] <= 7; // C_SIZE_MULT
|
||||
csd_size[14:3] <= 12'b101101101101;
|
||||
csd_size[26:15] <= img_size[29:18]; // in 256K units ((2**(C_SIZE_MULT+2))*512)
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [127:0] CSD = {1'b0,csd_sdhc,6'h00,8'h0e,8'h00,8'h32,8'h5b,8'h59,6'h00,csd_size,7'h7f,8'h80,8'h0a,8'h40,8'h40,8'hf1};
|
||||
wire [127:0] CID = {8'hcd,8'hc7,8'h00,8'h93,8'h6f,8'h2f,8'h73,8'h00,8'h00,8'h44,8'h32,8'h38,8'h34,8'h00,8'h00,8'h3e};
|
||||
|
||||
reg [8:0] buffer_ptr;
|
||||
reg [7:0] buffer_din;
|
||||
wire [7:0] buffer_dout;
|
||||
reg buffer_wr;
|
||||
|
||||
reg [1:0] sd_buf, spi_buf;
|
||||
|
||||
reg [6:0] sbuf;
|
||||
reg [2:0] bit_cnt;
|
||||
|
||||
wire last_bit = &bit_cnt || OCTAL;
|
||||
wire [7:0] ibuf = OCTAL ? mosi : {sbuf,mosi[0]};
|
||||
|
||||
always @(posedge clk_spi) begin
|
||||
reg [2:0] read_state;
|
||||
reg [2:0] write_state;
|
||||
reg [1:0] pref_state;
|
||||
reg [5:0] cmd;
|
||||
reg cmd55;
|
||||
reg [39:0] reply;
|
||||
reg [3:0] byte_cnt;
|
||||
reg old_sck;
|
||||
reg [2:0] ack;
|
||||
reg [2:0] wait_m_cnt;
|
||||
reg [31:0] arg;
|
||||
|
||||
ack[1:0] <= {ack[0],sd_ack};
|
||||
if(ack[1] == ack[0]) ack[2] <= ack[1];
|
||||
|
||||
if(~ack[2] & ack[1]) {sd_rd,sd_wr} <= 0;
|
||||
if( ack[2] & ~ack[1]) begin
|
||||
sd_buf <= sd_buf + 1'd1;
|
||||
sd_lba <= sd_lba + 1;
|
||||
end
|
||||
|
||||
buffer_wr <= 0;
|
||||
|
||||
if(reset) begin
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= '1;
|
||||
miso <= '1;
|
||||
cmd <= 0;
|
||||
sd_wr <= 0;
|
||||
sd_rd <= 0;
|
||||
read_state <= RD_STATE_IDLE;
|
||||
write_state <= WR_STATE_IDLE;
|
||||
pref_state <= PREF_STATE_IDLE;
|
||||
end
|
||||
else begin
|
||||
|
||||
if(buffer_wr) begin
|
||||
if(~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1;
|
||||
else begin
|
||||
spi_buf <= spi_buf + 1'd1;
|
||||
sd_wr <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
case(pref_state)
|
||||
PREF_STATE_IDLE:
|
||||
if(((sd_buf - spi_buf) <= 1) && (read_state != RD_STATE_IDLE) && (cmd == 17 || cmd == 18)) begin
|
||||
sd_rd <= 1;
|
||||
pref_state <= PREF_STATE_RD;
|
||||
end
|
||||
|
||||
PREF_STATE_RD:
|
||||
if(read_state == RD_STATE_IDLE) begin
|
||||
pref_state <= PREF_STATE_IDLE;
|
||||
end
|
||||
else if(ack[2] & ~ack[1]) begin
|
||||
pref_state <= (cmd == 18) ? PREF_STATE_IDLE : PREF_STATE_FINISH;
|
||||
end
|
||||
|
||||
PREF_STATE_FINISH:
|
||||
if(read_state == RD_STATE_IDLE) begin
|
||||
pref_state <= PREF_STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
|
||||
old_sck <= sck;
|
||||
if(ss) begin
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= '1;
|
||||
miso <= '1;
|
||||
end
|
||||
else if(old_sck & ~sck) begin
|
||||
miso <= '1; // default: send 1's (busy/wait)
|
||||
if(byte_cnt >= NCR) {miso,reply} <= {reply, {SZ{1'b1}}};
|
||||
|
||||
// ---------- read state machine processing -------------
|
||||
case(read_state)
|
||||
RD_STATE_IDLE: ;
|
||||
|
||||
RD_STATE_START: begin
|
||||
if(byte_cnt == NCR && last_bit) read_state <= (cmd == 9 || cmd == 10) ? RD_STATE_SEND_TOKEN : RD_STATE_WAIT_IO;
|
||||
end
|
||||
|
||||
// waiting for io controller to return data
|
||||
RD_STATE_WAIT_IO: begin
|
||||
if(sd_buf != spi_buf && last_bit) read_state <= RD_STATE_SEND_TOKEN;
|
||||
end
|
||||
|
||||
// send data token
|
||||
RD_STATE_SEND_TOKEN: begin
|
||||
miso <= DATA_TOKEN[~bit_cnt -:SZ];
|
||||
if(last_bit) begin
|
||||
read_state <= RD_STATE_SEND_DATA; // next: send data
|
||||
buffer_ptr <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// send data
|
||||
RD_STATE_SEND_DATA: begin
|
||||
|
||||
miso <= (cmd == 9) ? CSD[{buffer_ptr[3:0],~bit_cnt} -:SZ] : (cmd == 10) ? CID[{buffer_ptr[3:0],~bit_cnt} -:SZ] : buffer_dout[~bit_cnt -:SZ];
|
||||
|
||||
if(last_bit) begin
|
||||
|
||||
// sent 512 sector data bytes?
|
||||
if(cmd == 17 && &buffer_ptr) read_state <= RD_STATE_IDLE;
|
||||
else if(cmd == 18 && &buffer_ptr) begin
|
||||
read_state <= RD_STATE_WAIT_M;
|
||||
wait_m_cnt <= 0;
|
||||
end
|
||||
|
||||
// sent 16 cid/csd data bytes?
|
||||
else if((cmd == 9 || cmd == 10) && &buffer_ptr[3:0]) read_state <= RD_STATE_IDLE;
|
||||
|
||||
// not done yet -> trigger read of next data byte
|
||||
else buffer_ptr <= buffer_ptr + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
RD_STATE_WAIT_M: begin
|
||||
if(last_bit) begin
|
||||
wait_m_cnt <= wait_m_cnt + 1'd1;
|
||||
if(&wait_m_cnt) begin
|
||||
spi_buf <= spi_buf + 1'd1;
|
||||
read_state <= RD_STATE_WAIT_IO;
|
||||
end
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// ------------------ write support ----------------------
|
||||
// send write data response
|
||||
if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt -:SZ];
|
||||
|
||||
// busy after write until the io controller sends ack
|
||||
if(write_state == WR_STATE_BUSY) miso <= 0;
|
||||
end
|
||||
else if(~old_sck & sck) begin
|
||||
|
||||
sbuf[6:0] <= {sbuf[5:0],mosi[0]};
|
||||
bit_cnt <= bit_cnt + SZ[2:0];
|
||||
|
||||
if(last_bit) begin
|
||||
// finished reading one byte
|
||||
// byte counter runs against 15 byte boundary
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
|
||||
|
||||
// byte_cnt > 6 -> complete command received
|
||||
// first byte of valid command is 01xxxxxx
|
||||
// don't accept new commands once a write or read command has been accepted
|
||||
if(byte_cnt > 5 &&
|
||||
((write_state == WR_STATE_IDLE && read_state == RD_STATE_IDLE && ibuf[7:6] == 1) ||
|
||||
(read_state != RD_STATE_IDLE && ibuf == 8'h4c))) begin
|
||||
byte_cnt <= 0;
|
||||
cmd <= ibuf[5:0];
|
||||
cmd55 <= (cmd == 55); // set cmd55 flag if previous command was 55
|
||||
if(ibuf[5:0] == 12) read_state <= RD_STATE_IDLE;
|
||||
end
|
||||
|
||||
// parse additional command bytes
|
||||
if(byte_cnt == 0) arg[31:24] <= ibuf;
|
||||
if(byte_cnt == 1) arg[23:16] <= ibuf;
|
||||
if(byte_cnt == 2) arg[15:8] <= ibuf;
|
||||
if(byte_cnt == 3) arg[7:0] <= ibuf;
|
||||
|
||||
// last byte (crc) received, evaluate
|
||||
if(byte_cnt == 4) begin
|
||||
|
||||
// default:
|
||||
reply <= 40'h04FFFFFFFF; // illegal command
|
||||
|
||||
case(cmd)
|
||||
// CMD0: GO_IDLE_STATE
|
||||
0: reply[39:32] <= 1; // ok, busy
|
||||
|
||||
// CMD1: SEND_OP_COND
|
||||
1: reply[39:32] <= 0;
|
||||
|
||||
// CMD8: SEND_IF_COND (V2 only)
|
||||
8: reply <= 40'h01000001AA; // ok, busy
|
||||
|
||||
// CMD9: SEND_CSD
|
||||
9,
|
||||
// CMD10: SEND_CID
|
||||
10: begin
|
||||
reply[39:32] <= 0;
|
||||
read_state <= RD_STATE_START;
|
||||
end
|
||||
|
||||
// CMD12: STOP_TRANSMISSION
|
||||
12: reply[39:32] <= 0;
|
||||
|
||||
// CMD13: SEND_STATUS
|
||||
13: reply[39:24] <= 16'h0000;
|
||||
|
||||
// CMD16: SET_BLOCKLEN
|
||||
16: reply[39:32] <= (arg == 512) ? 8'h00 : 8'h40; // we only support a block size of 512
|
||||
|
||||
// CMD17: READ_SINGLE_BLOCK
|
||||
17,
|
||||
// CMD18: READ_MULTIPLE
|
||||
18: begin
|
||||
reply[39:32] <= 0;
|
||||
read_state <= RD_STATE_START;
|
||||
spi_buf <= 0;
|
||||
sd_buf <= 0;
|
||||
sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]};
|
||||
end
|
||||
|
||||
// ACMD23: SET_WR_BLK_ERASE_COUNT
|
||||
23: reply[39:32] <= 0;
|
||||
|
||||
// CMD24: WRITE_BLOCK
|
||||
24,
|
||||
// CMD25: WRITE_MULTIPLE
|
||||
25: begin
|
||||
reply[39:32] <= 0;
|
||||
write_state <= WR_STATE_EXP_DTOKEN; // expect data token
|
||||
spi_buf <= 0;
|
||||
sd_buf <= 0;
|
||||
sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]};
|
||||
end
|
||||
|
||||
// ACMD41: APP_SEND_OP_COND
|
||||
41: if(cmd55) reply[39:32] <= 0; // ok, not busy
|
||||
|
||||
// CMD55: APP_COND
|
||||
55: reply[39:32] <= 1; // ok, busy
|
||||
|
||||
// CMD58: READ_OCR
|
||||
58: reply <= { 8'h00, 1'b1, csd_sdhc, 30'd0 }; // bit 30 = 1 -> high capacity card
|
||||
|
||||
// CMD59: CRC_ON_OFF
|
||||
59: reply[39:32] <= 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// ---------- handle write -----------
|
||||
case(write_state)
|
||||
// do nothing in idle state
|
||||
WR_STATE_IDLE: ;
|
||||
|
||||
// waiting for data token
|
||||
WR_STATE_EXP_DTOKEN: begin
|
||||
buffer_ptr <= 0;
|
||||
if(cmd == 24) begin
|
||||
if(ibuf == DATA_TOKEN) write_state <= WR_STATE_RECV_DATA;
|
||||
end
|
||||
else begin
|
||||
if(ibuf == DATA_TOKEN_CMD25) write_state <= WR_STATE_RECV_DATA;
|
||||
if(ibuf == STOP_TRAN) write_state <= WR_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
|
||||
// transfer 512 bytes
|
||||
WR_STATE_RECV_DATA: begin
|
||||
// push one byte into local buffer
|
||||
buffer_wr <= 1;
|
||||
buffer_din <= ibuf;
|
||||
|
||||
// all bytes written?
|
||||
if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0;
|
||||
end
|
||||
|
||||
// transfer 1st crc byte
|
||||
WR_STATE_RECV_CRC0:
|
||||
write_state <= WR_STATE_RECV_CRC1;
|
||||
|
||||
// transfer 2nd crc byte
|
||||
WR_STATE_RECV_CRC1:
|
||||
write_state <= WR_STATE_SEND_DRESP;
|
||||
|
||||
// send data response
|
||||
WR_STATE_SEND_DRESP:
|
||||
write_state <= WR_STATE_BUSY;
|
||||
|
||||
// wait for io controller to accept data
|
||||
WR_STATE_BUSY:
|
||||
if(spi_buf == sd_buf) write_state <= (cmd == 25) ? WR_STATE_EXP_DTOKEN : WR_STATE_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,33 @@
|
||||
//
|
||||
// PWM DAC
|
||||
//
|
||||
// MSBI is the highest bit number. NOT amount of bits!
|
||||
//
|
||||
module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1)
|
||||
(
|
||||
output reg DACout, //Average Output feeding analog lowpass
|
||||
input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
|
||||
input CLK,
|
||||
input RESET
|
||||
);
|
||||
|
||||
reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
|
||||
reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
|
||||
reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
|
||||
reg [MSBI+2:0] DeltaB; //B input of Delta Adder
|
||||
|
||||
always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
|
||||
always @(*) DeltaAdder = DACin + DeltaB;
|
||||
always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
|
||||
|
||||
always @(posedge CLK or posedge RESET) begin
|
||||
if(RESET) begin
|
||||
SigmaLatch <= 1'b1 << (MSBI+1);
|
||||
DACout <= INV;
|
||||
end else begin
|
||||
SigmaLatch <= SigmaAdder;
|
||||
DACout <= SigmaLatch[MSBI+2] ^ INV;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
320
Computer_MiST/Interact_MiST/Neuer Ordner/sys/spdif.v
Normal file
320
Computer_MiST/Interact_MiST/Neuer Ordner/sys/spdif.v
Normal file
@@ -0,0 +1,320 @@
|
||||
//-----------------------------------------------------------------
|
||||
// SPDIF Transmitter
|
||||
// V0.1
|
||||
// Ultra-Embedded.com
|
||||
// Copyright 2012
|
||||
//
|
||||
// Email: admin@ultra-embedded.com
|
||||
//
|
||||
// License: GPL
|
||||
// If you would like a version with a more permissive license for
|
||||
// use in closed source commercial applications please contact me
|
||||
// for details.
|
||||
//-----------------------------------------------------------------
|
||||
//
|
||||
// This file is open source HDL; you can redistribute it and/or
|
||||
// modify it under the terms of the GNU General Public License as
|
||||
// published by the Free Software Foundation; either version 2 of
|
||||
// the License, or (at your option) any later version.
|
||||
//
|
||||
// This file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public
|
||||
// License along with this file; if not, write to the Free Software
|
||||
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
// USA
|
||||
//-----------------------------------------------------------------
|
||||
// altera message_off 10762
|
||||
// altera message_off 10240
|
||||
|
||||
module spdif
|
||||
(
|
||||
input clk_i,
|
||||
input rst_i,
|
||||
|
||||
// SPDIF bit output enable
|
||||
// Single cycle pulse synchronous to clk_i which drives
|
||||
// the output bit rate.
|
||||
// For 44.1KHz, 44100×32×2×2 = 5,644,800Hz
|
||||
// For 48KHz, 48000×32×2×2 = 6,144,000Hz
|
||||
input bit_out_en_i,
|
||||
|
||||
// Output
|
||||
output spdif_o,
|
||||
|
||||
// Audio interface (16-bit x 2 = RL)
|
||||
input [31:0] sample_i,
|
||||
output reg sample_req_o
|
||||
);
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Registers
|
||||
//-----------------------------------------------------------------
|
||||
reg [15:0] audio_sample_q;
|
||||
reg [8:0] subframe_count_q;
|
||||
|
||||
reg load_subframe_q;
|
||||
reg [7:0] preamble_q;
|
||||
wire [31:0] subframe_w;
|
||||
|
||||
reg [5:0] bit_count_q;
|
||||
reg bit_toggle_q;
|
||||
|
||||
reg spdif_out_q;
|
||||
|
||||
reg [5:0] parity_count_q;
|
||||
|
||||
reg channel_status_bit_q;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Subframe Counter
|
||||
//-----------------------------------------------------------------
|
||||
always @ (posedge rst_i or posedge clk_i )
|
||||
begin
|
||||
if (rst_i == 1'b1)
|
||||
subframe_count_q <= 9'd0;
|
||||
else if (load_subframe_q)
|
||||
begin
|
||||
// 192 frames (384 subframes) in an audio block
|
||||
if (subframe_count_q == 9'd383)
|
||||
subframe_count_q <= 9'd0;
|
||||
else
|
||||
subframe_count_q <= subframe_count_q + 9'd1;
|
||||
end
|
||||
end
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Sample capture
|
||||
//-----------------------------------------------------------------
|
||||
reg [15:0] sample_buf_q;
|
||||
|
||||
always @ (posedge rst_i or posedge clk_i )
|
||||
begin
|
||||
if (rst_i == 1'b1)
|
||||
begin
|
||||
audio_sample_q <= 16'h0000;
|
||||
sample_buf_q <= 16'h0000;
|
||||
sample_req_o <= 1'b0;
|
||||
end
|
||||
else if (load_subframe_q)
|
||||
begin
|
||||
// Start of frame (first subframe)?
|
||||
if (subframe_count_q[0] == 1'b0)
|
||||
begin
|
||||
// Use left sample
|
||||
audio_sample_q <= sample_i[15:0];
|
||||
|
||||
// Store right sample
|
||||
sample_buf_q <= sample_i[31:16];
|
||||
|
||||
// Request next sample
|
||||
sample_req_o <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// Use right sample
|
||||
audio_sample_q <= sample_buf_q;
|
||||
|
||||
sample_req_o <= 1'b0;
|
||||
end
|
||||
end
|
||||
else
|
||||
sample_req_o <= 1'b0;
|
||||
end
|
||||
|
||||
// Timeslots 3 - 0 = Preamble
|
||||
assign subframe_w[3:0] = 4'b0000;
|
||||
|
||||
// Timeslots 7 - 4 = 24-bit audio LSB
|
||||
assign subframe_w[7:4] = 4'b0000;
|
||||
|
||||
// Timeslots 11 - 8 = 20-bit audio LSB
|
||||
assign subframe_w[11:8] = 4'b0000;
|
||||
|
||||
// Timeslots 27 - 12 = 16-bit audio
|
||||
assign subframe_w[27:12] = audio_sample_q;
|
||||
|
||||
// Timeslots 28 = Validity
|
||||
assign subframe_w[28] = 1'b0; // Valid
|
||||
|
||||
// Timeslots 29 = User bit
|
||||
assign subframe_w[29] = 1'b0;
|
||||
|
||||
// Timeslots 30 = Channel status bit
|
||||
assign subframe_w[30] = channel_status_bit_q ; //was constant 1'b0 enabling copy-bit;
|
||||
|
||||
// Timeslots 31 = Even Parity bit (31:4)
|
||||
assign subframe_w[31] = 1'b0;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Preamble and Channel status bit
|
||||
//-----------------------------------------------------------------
|
||||
localparam PREAMBLE_Z = 8'b00010111; // "B" channel A data at start of block
|
||||
localparam PREAMBLE_Y = 8'b00100111; // "W" channel B data
|
||||
localparam PREAMBLE_X = 8'b01000111; // "M" channel A data not at start of block
|
||||
|
||||
reg [7:0] preamble_r;
|
||||
reg channel_status_bit_r;
|
||||
|
||||
always @ *
|
||||
begin
|
||||
// Start of audio block?
|
||||
// Z(B) - Left channel
|
||||
if (subframe_count_q == 9'd0)
|
||||
preamble_r = PREAMBLE_Z; // Z(B)
|
||||
// Right Channel?
|
||||
else if (subframe_count_q[0] == 1'b1)
|
||||
preamble_r = PREAMBLE_Y; // Y(W)
|
||||
// Left Channel (but not start of block)?
|
||||
else
|
||||
preamble_r = PREAMBLE_X; // X(M)
|
||||
|
||||
if (subframe_count_q[8:1] == 8'd2) // frame 2 => subframes 4 and 5 => 0 = copy inhibited, 1 = copy permitted
|
||||
channel_status_bit_r = 1'b1;
|
||||
else if (subframe_count_q[8:1] == 8'd15) // frame 15 => 0 = no indication, 1 = original media
|
||||
channel_status_bit_r = 1'b1;
|
||||
else if (subframe_count_q[8:1] == 8'd25) // frame 24 to 27 => sample frequency, 0100 = 48kHz, 0000 = 44kHz (l2r)
|
||||
channel_status_bit_r = 1'b1;
|
||||
else
|
||||
channel_status_bit_r = 1'b0; // everything else defaults to 0
|
||||
end
|
||||
|
||||
always @ (posedge rst_i or posedge clk_i )
|
||||
begin
|
||||
if (rst_i == 1'b1)
|
||||
begin
|
||||
preamble_q <= 8'h00;
|
||||
channel_status_bit_q <= 1'b0;
|
||||
end
|
||||
else if (load_subframe_q)
|
||||
begin
|
||||
preamble_q <= preamble_r;
|
||||
channel_status_bit_q <= channel_status_bit_r;
|
||||
end
|
||||
end
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Parity Counter
|
||||
//-----------------------------------------------------------------
|
||||
always @ (posedge rst_i or posedge clk_i )
|
||||
begin
|
||||
if (rst_i == 1'b1)
|
||||
begin
|
||||
parity_count_q <= 6'd0;
|
||||
end
|
||||
// Time to output a bit?
|
||||
else if (bit_out_en_i)
|
||||
begin
|
||||
// Preamble bits?
|
||||
if (bit_count_q < 6'd8)
|
||||
begin
|
||||
parity_count_q <= 6'd0;
|
||||
end
|
||||
// Normal timeslots
|
||||
else if (bit_count_q < 6'd62)
|
||||
begin
|
||||
// On first pass through this timeslot, count number of high bits
|
||||
if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
|
||||
parity_count_q <= parity_count_q + 6'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Bit Counter
|
||||
//-----------------------------------------------------------------
|
||||
always @ (posedge rst_i or posedge clk_i)
|
||||
begin
|
||||
if (rst_i == 1'b1)
|
||||
begin
|
||||
bit_count_q <= 6'b0;
|
||||
load_subframe_q <= 1'b1;
|
||||
end
|
||||
// Time to output a bit?
|
||||
else if (bit_out_en_i)
|
||||
begin
|
||||
// 32 timeslots (x2 for double frequency)
|
||||
if (bit_count_q == 6'd63)
|
||||
begin
|
||||
bit_count_q <= 6'd0;
|
||||
load_subframe_q <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_count_q <= bit_count_q + 6'd1;
|
||||
load_subframe_q <= 1'b0;
|
||||
end
|
||||
end
|
||||
else
|
||||
load_subframe_q <= 1'b0;
|
||||
end
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Bit half toggle
|
||||
//-----------------------------------------------------------------
|
||||
always @ (posedge rst_i or posedge clk_i)
|
||||
if (rst_i == 1'b1)
|
||||
bit_toggle_q <= 1'b0;
|
||||
// Time to output a bit?
|
||||
else if (bit_out_en_i)
|
||||
bit_toggle_q <= ~bit_toggle_q;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Output bit (BMC encoded)
|
||||
//-----------------------------------------------------------------
|
||||
reg bit_r;
|
||||
|
||||
always @ *
|
||||
begin
|
||||
bit_r = spdif_out_q;
|
||||
|
||||
// Time to output a bit?
|
||||
if (bit_out_en_i)
|
||||
begin
|
||||
// Preamble bits?
|
||||
if (bit_count_q < 6'd8)
|
||||
begin
|
||||
bit_r = preamble_q[bit_count_q[2:0]];
|
||||
end
|
||||
// Normal timeslots
|
||||
else if (bit_count_q < 6'd62)
|
||||
begin
|
||||
if (subframe_w[bit_count_q / 2] == 1'b0)
|
||||
begin
|
||||
if (bit_toggle_q == 1'b0)
|
||||
bit_r = ~spdif_out_q;
|
||||
else
|
||||
bit_r = spdif_out_q;
|
||||
end
|
||||
else
|
||||
bit_r = ~spdif_out_q;
|
||||
end
|
||||
// Parity timeslot
|
||||
else
|
||||
begin
|
||||
// Even number of high bits, make odd
|
||||
if (parity_count_q[0] == 1'b0)
|
||||
begin
|
||||
if (bit_toggle_q == 1'b0)
|
||||
bit_r = ~spdif_out_q;
|
||||
else
|
||||
bit_r = spdif_out_q;
|
||||
end
|
||||
else
|
||||
bit_r = ~spdif_out_q;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge rst_i or posedge clk_i )
|
||||
if (rst_i == 1'b1)
|
||||
spdif_out_q <= 1'b0;
|
||||
else
|
||||
spdif_out_q <= bit_r;
|
||||
|
||||
assign spdif_o = spdif_out_q;
|
||||
|
||||
endmodule
|
||||
33
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys.qip
Normal file
33
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys.qip
Normal file
@@ -0,0 +1,33 @@
|
||||
set_global_assignment -name QIP_FILE [join [list $::quartus(qip_path) pll_q [regexp -inline {[0-9]+} $quartus(version)] .qip] {}]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
|
||||
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) math.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freak.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freezer.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) iir_filter.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) f2sdram_safe_terminator.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ]
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hps_io.sv ]
|
||||
227
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys.tcl
Normal file
227
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys.tcl
Normal file
@@ -0,0 +1,227 @@
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name DEVICE 5CSEBA6U23I7
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
|
||||
|
||||
#============================================================
|
||||
# ADC
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
|
||||
set_location_assignment PIN_U9 -to ADC_CONVST
|
||||
set_location_assignment PIN_V10 -to ADC_SCK
|
||||
set_location_assignment PIN_AC4 -to ADC_SDI
|
||||
set_location_assignment PIN_AD4 -to ADC_SDO
|
||||
|
||||
#============================================================
|
||||
# ARDUINO
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
|
||||
|
||||
#============================================================
|
||||
# I2C LEDS/BUTTONS
|
||||
#============================================================
|
||||
set_location_assignment PIN_U14 -to IO_SCL
|
||||
set_location_assignment PIN_AG9 -to IO_SDA
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S*
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S*
|
||||
|
||||
#============================================================
|
||||
# USER PORT
|
||||
#============================================================
|
||||
set_location_assignment PIN_AF17 -to USER_IO[6]
|
||||
set_location_assignment PIN_AF15 -to USER_IO[5]
|
||||
set_location_assignment PIN_AG16 -to USER_IO[4]
|
||||
set_location_assignment PIN_AH11 -to USER_IO[3]
|
||||
set_location_assignment PIN_AH12 -to USER_IO[2]
|
||||
set_location_assignment PIN_AH9 -to USER_IO[1]
|
||||
set_location_assignment PIN_AG11 -to USER_IO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*]
|
||||
|
||||
#============================================================
|
||||
# SDIO_CD or SPDIF_OUT
|
||||
#============================================================
|
||||
set_location_assignment PIN_AH7 -to SDCD_SPDIF
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF
|
||||
|
||||
#============================================================
|
||||
# SDRAM
|
||||
#============================================================
|
||||
set_location_assignment PIN_Y11 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_AA26 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_AA13 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_AA11 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_W11 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_Y19 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_AB23 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_AC23 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_AC22 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_C12 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_AB26 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_AD17 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_D12 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_AG13 -to SDRAM_DQML
|
||||
set_location_assignment PIN_AF13 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_AD20 -to SDRAM_CLK
|
||||
set_location_assignment PIN_AG10 -to SDRAM_CKE
|
||||
set_location_assignment PIN_AA19 -to SDRAM_nWE
|
||||
set_location_assignment PIN_AA18 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_Y18 -to SDRAM_nCS
|
||||
set_location_assignment PIN_W14 -to SDRAM_nRAS
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_*
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
|
||||
|
||||
#============================================================
|
||||
# SPI SD
|
||||
#============================================================
|
||||
set_location_assignment PIN_AE15 -to SD_SPI_CS
|
||||
set_location_assignment PIN_AH8 -to SD_SPI_MISO
|
||||
set_location_assignment PIN_AG8 -to SD_SPI_CLK
|
||||
set_location_assignment PIN_U13 -to SD_SPI_MOSI
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI*
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI*
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI*
|
||||
|
||||
|
||||
#============================================================
|
||||
# CLOCK
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
|
||||
set_location_assignment PIN_V11 -to FPGA_CLK1_50
|
||||
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
|
||||
set_location_assignment PIN_E11 -to FPGA_CLK3_50
|
||||
|
||||
#============================================================
|
||||
# HDMI
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_*
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_*
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK
|
||||
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
|
||||
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
|
||||
set_location_assignment PIN_T13 -to HDMI_I2S
|
||||
set_location_assignment PIN_T11 -to HDMI_LRCLK
|
||||
set_location_assignment PIN_U11 -to HDMI_MCLK
|
||||
set_location_assignment PIN_T12 -to HDMI_SCLK
|
||||
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
|
||||
set_location_assignment PIN_AD19 -to HDMI_TX_DE
|
||||
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
|
||||
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
|
||||
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
|
||||
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
|
||||
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
|
||||
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
|
||||
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
|
||||
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
|
||||
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
|
||||
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
|
||||
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
|
||||
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
|
||||
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
|
||||
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
|
||||
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
|
||||
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
|
||||
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
|
||||
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
|
||||
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
|
||||
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
|
||||
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
|
||||
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
|
||||
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
|
||||
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
|
||||
set_location_assignment PIN_T8 -to HDMI_TX_HS
|
||||
set_location_assignment PIN_AF11 -to HDMI_TX_INT
|
||||
set_location_assignment PIN_V13 -to HDMI_TX_VS
|
||||
|
||||
#============================================================
|
||||
# KEY
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
|
||||
set_location_assignment PIN_AH17 -to KEY[0]
|
||||
set_location_assignment PIN_AH16 -to KEY[1]
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
|
||||
set_location_assignment PIN_W15 -to LED[0]
|
||||
set_location_assignment PIN_AA24 -to LED[1]
|
||||
set_location_assignment PIN_V16 -to LED[2]
|
||||
set_location_assignment PIN_V15 -to LED[3]
|
||||
set_location_assignment PIN_AF26 -to LED[4]
|
||||
set_location_assignment PIN_AE26 -to LED[5]
|
||||
set_location_assignment PIN_Y16 -to LED[6]
|
||||
set_location_assignment PIN_AA23 -to LED[7]
|
||||
|
||||
#============================================================
|
||||
# SW
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
||||
set_location_assignment PIN_Y24 -to SW[0]
|
||||
set_location_assignment PIN_W24 -to SW[1]
|
||||
set_location_assignment PIN_W21 -to SW[2]
|
||||
set_location_assignment PIN_W20 -to SW[3]
|
||||
|
||||
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
|
||||
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart
|
||||
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALI2C_X52_Y60_N111 -entity sys_top -to hdmi_i2c
|
||||
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
|
||||
|
||||
set_global_assignment -name CDF_FILE jtag.cdf
|
||||
set_global_assignment -name QIP_FILE sys/sys.qip
|
||||
|
||||
71
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys_analog.tcl
Normal file
71
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys_analog.tcl
Normal file
@@ -0,0 +1,71 @@
|
||||
#============================================================
|
||||
# SDIO
|
||||
#============================================================
|
||||
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
|
||||
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
|
||||
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
|
||||
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
|
||||
set_location_assignment PIN_AF27 -to SDIO_CMD
|
||||
set_location_assignment PIN_AH26 -to SDIO_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
|
||||
|
||||
#============================================================
|
||||
# VGA
|
||||
#============================================================
|
||||
set_location_assignment PIN_AE17 -to VGA_R[0]
|
||||
set_location_assignment PIN_AE20 -to VGA_R[1]
|
||||
set_location_assignment PIN_AF20 -to VGA_R[2]
|
||||
set_location_assignment PIN_AH18 -to VGA_R[3]
|
||||
set_location_assignment PIN_AH19 -to VGA_R[4]
|
||||
set_location_assignment PIN_AF21 -to VGA_R[5]
|
||||
|
||||
set_location_assignment PIN_AE19 -to VGA_G[0]
|
||||
set_location_assignment PIN_AG15 -to VGA_G[1]
|
||||
set_location_assignment PIN_AF18 -to VGA_G[2]
|
||||
set_location_assignment PIN_AG18 -to VGA_G[3]
|
||||
set_location_assignment PIN_AG19 -to VGA_G[4]
|
||||
set_location_assignment PIN_AG20 -to VGA_G[5]
|
||||
|
||||
set_location_assignment PIN_AG21 -to VGA_B[0]
|
||||
set_location_assignment PIN_AA20 -to VGA_B[1]
|
||||
set_location_assignment PIN_AE22 -to VGA_B[2]
|
||||
set_location_assignment PIN_AF22 -to VGA_B[3]
|
||||
set_location_assignment PIN_AH23 -to VGA_B[4]
|
||||
set_location_assignment PIN_AH21 -to VGA_B[5]
|
||||
|
||||
set_location_assignment PIN_AH22 -to VGA_HS
|
||||
set_location_assignment PIN_AG24 -to VGA_VS
|
||||
|
||||
set_location_assignment PIN_AH27 -to VGA_EN
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
|
||||
|
||||
#============================================================
|
||||
# AUDIO
|
||||
#============================================================
|
||||
set_location_assignment PIN_AC24 -to AUDIO_L
|
||||
set_location_assignment PIN_AE25 -to AUDIO_R
|
||||
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
|
||||
|
||||
#============================================================
|
||||
# I/O #1
|
||||
#============================================================
|
||||
set_location_assignment PIN_Y15 -to LED_USER
|
||||
set_location_assignment PIN_AA15 -to LED_HDD
|
||||
set_location_assignment PIN_AG28 -to LED_POWER
|
||||
|
||||
set_location_assignment PIN_AH24 -to BTN_USER
|
||||
set_location_assignment PIN_AG25 -to BTN_OSD
|
||||
set_location_assignment PIN_AG23 -to BTN_RESET
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
|
||||
@@ -0,0 +1,50 @@
|
||||
#============================================================
|
||||
# Secondary SDRAM
|
||||
#============================================================
|
||||
set_location_assignment PIN_Y15 -to SDRAM2_DQ[0]
|
||||
set_location_assignment PIN_AC24 -to SDRAM2_DQ[1]
|
||||
set_location_assignment PIN_AA15 -to SDRAM2_DQ[2]
|
||||
set_location_assignment PIN_AD26 -to SDRAM2_DQ[3]
|
||||
set_location_assignment PIN_AG28 -to SDRAM2_DQ[4]
|
||||
set_location_assignment PIN_AF28 -to SDRAM2_DQ[5]
|
||||
set_location_assignment PIN_AE25 -to SDRAM2_DQ[6]
|
||||
set_location_assignment PIN_AF27 -to SDRAM2_DQ[7]
|
||||
set_location_assignment PIN_AG26 -to SDRAM2_DQ[14]
|
||||
set_location_assignment PIN_AH27 -to SDRAM2_DQ[15]
|
||||
|
||||
set_location_assignment PIN_AG25 -to SDRAM2_DQ[13]
|
||||
set_location_assignment PIN_AH26 -to SDRAM2_DQ[12]
|
||||
set_location_assignment PIN_AH24 -to SDRAM2_DQ[11]
|
||||
set_location_assignment PIN_AF25 -to SDRAM2_DQ[10]
|
||||
set_location_assignment PIN_AG23 -to SDRAM2_DQ[9]
|
||||
set_location_assignment PIN_AF23 -to SDRAM2_DQ[8]
|
||||
set_location_assignment PIN_AG24 -to SDRAM2_A[12]
|
||||
set_location_assignment PIN_AH22 -to SDRAM2_CLK
|
||||
set_location_assignment PIN_AH21 -to SDRAM2_A[9]
|
||||
set_location_assignment PIN_AG21 -to SDRAM2_A[11]
|
||||
set_location_assignment PIN_AH23 -to SDRAM2_A[7]
|
||||
set_location_assignment PIN_AA20 -to SDRAM2_A[8]
|
||||
set_location_assignment PIN_AF22 -to SDRAM2_A[5]
|
||||
set_location_assignment PIN_AE22 -to SDRAM2_A[6]
|
||||
set_location_assignment PIN_AG20 -to SDRAM2_nWE
|
||||
set_location_assignment PIN_AF21 -to SDRAM2_A[4]
|
||||
|
||||
set_location_assignment PIN_AG19 -to SDRAM2_nCAS
|
||||
set_location_assignment PIN_AH19 -to SDRAM2_nRAS
|
||||
set_location_assignment PIN_AG18 -to SDRAM2_nCS
|
||||
set_location_assignment PIN_AH18 -to SDRAM2_BA[0]
|
||||
set_location_assignment PIN_AF18 -to SDRAM2_BA[1]
|
||||
set_location_assignment PIN_AF20 -to SDRAM2_A[10]
|
||||
set_location_assignment PIN_AG15 -to SDRAM2_A[0]
|
||||
set_location_assignment PIN_AE20 -to SDRAM2_A[1]
|
||||
set_location_assignment PIN_AE19 -to SDRAM2_A[2]
|
||||
set_location_assignment PIN_AE17 -to SDRAM2_A[3]
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_*
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_*
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_*
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*]
|
||||
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_*
|
||||
|
||||
set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1"
|
||||
71
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys_top.sdc
Normal file
71
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys_top.sdc
Normal file
@@ -0,0 +1,71 @@
|
||||
# Specify root clocks
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
|
||||
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
|
||||
create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
|
||||
create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
|
||||
create_clock -period "10.0 MHz" [get_pins -compatibility_mode hdmi_i2c|out_clk] -name hdmi_sck
|
||||
|
||||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
|
||||
# Decouple different clock groups (to simplify routing)
|
||||
set_clock_groups -exclusive \
|
||||
-group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \
|
||||
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
|
||||
-group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \
|
||||
-group [get_clocks { spi_sck}] \
|
||||
-group [get_clocks { hdmi_sck}] \
|
||||
-group [get_clocks { *|h2f_user0_clk}] \
|
||||
-group [get_clocks { FPGA_CLK1_50 }] \
|
||||
-group [get_clocks { FPGA_CLK2_50 }] \
|
||||
-group [get_clocks { FPGA_CLK3_50 }]
|
||||
|
||||
set_false_path -from [get_ports {KEY*}]
|
||||
set_false_path -from [get_ports {BTN_*}]
|
||||
set_false_path -to [get_ports {LED_*}]
|
||||
set_false_path -to [get_ports {VGA_*}]
|
||||
set_false_path -to [get_ports {AUDIO_SPDIF}]
|
||||
set_false_path -to [get_ports {AUDIO_L}]
|
||||
set_false_path -to [get_ports {AUDIO_R}]
|
||||
set_false_path -to {cfg[*]}
|
||||
set_false_path -from {cfg[*]}
|
||||
set_false_path -from {VSET[*]}
|
||||
set_false_path -to {wcalc[*] hcalc[*]}
|
||||
set_false_path -to {hdmi_width[*] hdmi_height[*]}
|
||||
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
|
||||
|
||||
set_false_path -to {*_osd|v_cnt*}
|
||||
set_false_path -to {*_osd|v_osd_start*}
|
||||
set_false_path -to {*_osd|v_info_start*}
|
||||
set_false_path -to {*_osd|h_osd_start*}
|
||||
set_false_path -from {*_osd|v_osd_start*}
|
||||
set_false_path -from {*_osd|v_info_start*}
|
||||
set_false_path -from {*_osd|h_osd_start*}
|
||||
set_false_path -from {*_osd|rot*}
|
||||
set_false_path -from {*_osd|dsp_width*}
|
||||
set_false_path -to {*_osd|half}
|
||||
|
||||
set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
|
||||
set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
|
||||
set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
|
||||
set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
|
||||
set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
|
||||
set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
|
||||
set_false_path -from {aflt_* acx* acy* areset* arc*}
|
||||
set_false_path -from {vs_line*}
|
||||
|
||||
set_false_path -from {ascal|o_ihsize*}
|
||||
set_false_path -from {ascal|o_ivsize*}
|
||||
set_false_path -from {ascal|o_format*}
|
||||
set_false_path -from {ascal|o_hdown}
|
||||
set_false_path -from {ascal|o_vdown}
|
||||
set_false_path -from {ascal|o_hmin* ascal|o_hmax* ascal|o_vmin* ascal|o_vmax*}
|
||||
set_false_path -from {ascal|o_hdisp* ascal|o_vdisp*}
|
||||
set_false_path -from {ascal|o_htotal* ascal|o_vtotal*}
|
||||
set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
|
||||
set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
|
||||
|
||||
set_false_path -from {mcp23009|sd_cd}
|
||||
1700
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys_top.v
Normal file
1700
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sys_top.v
Normal file
File diff suppressed because it is too large
Load Diff
570
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sysmem.sv
Normal file
570
Computer_MiST/Interact_MiST/Neuer Ordner/sys/sysmem.sv
Normal file
@@ -0,0 +1,570 @@
|
||||
`timescale 1 ps / 1 ps
|
||||
module sysmem_lite
|
||||
(
|
||||
output clock,
|
||||
output reset_out,
|
||||
|
||||
input reset_hps_cold_req,
|
||||
input reset_hps_warm_req,
|
||||
input reset_core_req,
|
||||
|
||||
input ram1_clk,
|
||||
input [28:0] ram1_address,
|
||||
input [7:0] ram1_burstcount,
|
||||
output ram1_waitrequest,
|
||||
output [63:0] ram1_readdata,
|
||||
output ram1_readdatavalid,
|
||||
input ram1_read,
|
||||
input [63:0] ram1_writedata,
|
||||
input [7:0] ram1_byteenable,
|
||||
input ram1_write,
|
||||
|
||||
input ram2_clk,
|
||||
input [28:0] ram2_address,
|
||||
input [7:0] ram2_burstcount,
|
||||
output ram2_waitrequest,
|
||||
output [63:0] ram2_readdata,
|
||||
output ram2_readdatavalid,
|
||||
input ram2_read,
|
||||
input [63:0] ram2_writedata,
|
||||
input [7:0] ram2_byteenable,
|
||||
input ram2_write,
|
||||
|
||||
input vbuf_clk,
|
||||
input [27:0] vbuf_address,
|
||||
input [7:0] vbuf_burstcount,
|
||||
output vbuf_waitrequest,
|
||||
output [127:0] vbuf_readdata,
|
||||
output vbuf_readdatavalid,
|
||||
input vbuf_read,
|
||||
input [127:0] vbuf_writedata,
|
||||
input [15:0] vbuf_byteenable,
|
||||
input vbuf_write
|
||||
);
|
||||
|
||||
assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req;
|
||||
|
||||
////////////////////////////////////////////////////////
|
||||
//// f2sdram_safe_terminator_ram1 ////
|
||||
////////////////////////////////////////////////////////
|
||||
wire [28:0] f2h_ram1_address;
|
||||
wire [7:0] f2h_ram1_burstcount;
|
||||
wire f2h_ram1_waitrequest;
|
||||
wire [63:0] f2h_ram1_readdata;
|
||||
wire f2h_ram1_readdatavalid;
|
||||
wire f2h_ram1_read;
|
||||
wire [63:0] f2h_ram1_writedata;
|
||||
wire [7:0] f2h_ram1_byteenable;
|
||||
wire f2h_ram1_write;
|
||||
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_0 = 1'b1;
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_1 = 1'b1;
|
||||
always @(posedge ram1_clk) begin
|
||||
ram1_reset_0 <= reset_out;
|
||||
ram1_reset_1 <= ram1_reset_0;
|
||||
end
|
||||
|
||||
f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram1
|
||||
(
|
||||
.clk (ram1_clk),
|
||||
.rst_req_sync (ram1_reset_1),
|
||||
|
||||
.waitrequest_slave (ram1_waitrequest),
|
||||
.burstcount_slave (ram1_burstcount),
|
||||
.address_slave (ram1_address),
|
||||
.readdata_slave (ram1_readdata),
|
||||
.readdatavalid_slave (ram1_readdatavalid),
|
||||
.read_slave (ram1_read),
|
||||
.writedata_slave (ram1_writedata),
|
||||
.byteenable_slave (ram1_byteenable),
|
||||
.write_slave (ram1_write),
|
||||
|
||||
.waitrequest_master (f2h_ram1_waitrequest),
|
||||
.burstcount_master (f2h_ram1_burstcount),
|
||||
.address_master (f2h_ram1_address),
|
||||
.readdata_master (f2h_ram1_readdata),
|
||||
.readdatavalid_master (f2h_ram1_readdatavalid),
|
||||
.read_master (f2h_ram1_read),
|
||||
.writedata_master (f2h_ram1_writedata),
|
||||
.byteenable_master (f2h_ram1_byteenable),
|
||||
.write_master (f2h_ram1_write)
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////
|
||||
//// f2sdram_safe_terminator_ram2 ////
|
||||
////////////////////////////////////////////////////////
|
||||
wire [28:0] f2h_ram2_address;
|
||||
wire [7:0] f2h_ram2_burstcount;
|
||||
wire f2h_ram2_waitrequest;
|
||||
wire [63:0] f2h_ram2_readdata;
|
||||
wire f2h_ram2_readdatavalid;
|
||||
wire f2h_ram2_read;
|
||||
wire [63:0] f2h_ram2_writedata;
|
||||
wire [7:0] f2h_ram2_byteenable;
|
||||
wire f2h_ram2_write;
|
||||
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_0 = 1'b1;
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_1 = 1'b1;
|
||||
always @(posedge ram2_clk) begin
|
||||
ram2_reset_0 <= reset_out;
|
||||
ram2_reset_1 <= ram2_reset_0;
|
||||
end
|
||||
|
||||
f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram2
|
||||
(
|
||||
.clk (ram2_clk),
|
||||
.rst_req_sync (ram2_reset_1),
|
||||
|
||||
.waitrequest_slave (ram2_waitrequest),
|
||||
.burstcount_slave (ram2_burstcount),
|
||||
.address_slave (ram2_address),
|
||||
.readdata_slave (ram2_readdata),
|
||||
.readdatavalid_slave (ram2_readdatavalid),
|
||||
.read_slave (ram2_read),
|
||||
.writedata_slave (ram2_writedata),
|
||||
.byteenable_slave (ram2_byteenable),
|
||||
.write_slave (ram2_write),
|
||||
|
||||
.waitrequest_master (f2h_ram2_waitrequest),
|
||||
.burstcount_master (f2h_ram2_burstcount),
|
||||
.address_master (f2h_ram2_address),
|
||||
.readdata_master (f2h_ram2_readdata),
|
||||
.readdatavalid_master (f2h_ram2_readdatavalid),
|
||||
.read_master (f2h_ram2_read),
|
||||
.writedata_master (f2h_ram2_writedata),
|
||||
.byteenable_master (f2h_ram2_byteenable),
|
||||
.write_master (f2h_ram2_write)
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////
|
||||
//// f2sdram_safe_terminator_vbuf ////
|
||||
////////////////////////////////////////////////////////
|
||||
wire [27:0] f2h_vbuf_address;
|
||||
wire [7:0] f2h_vbuf_burstcount;
|
||||
wire f2h_vbuf_waitrequest;
|
||||
wire [127:0] f2h_vbuf_readdata;
|
||||
wire f2h_vbuf_readdatavalid;
|
||||
wire f2h_vbuf_read;
|
||||
wire [127:0] f2h_vbuf_writedata;
|
||||
wire [15:0] f2h_vbuf_byteenable;
|
||||
wire f2h_vbuf_write;
|
||||
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_0 = 1'b1;
|
||||
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_1 = 1'b1;
|
||||
always @(posedge vbuf_clk) begin
|
||||
vbuf_reset_0 <= reset_out;
|
||||
vbuf_reset_1 <= vbuf_reset_0;
|
||||
end
|
||||
|
||||
f2sdram_safe_terminator #(128, 8) f2sdram_safe_terminator_vbuf
|
||||
(
|
||||
.clk (vbuf_clk),
|
||||
.rst_req_sync (vbuf_reset_1),
|
||||
|
||||
.waitrequest_slave (vbuf_waitrequest),
|
||||
.burstcount_slave (vbuf_burstcount),
|
||||
.address_slave (vbuf_address),
|
||||
.readdata_slave (vbuf_readdata),
|
||||
.readdatavalid_slave (vbuf_readdatavalid),
|
||||
.read_slave (vbuf_read),
|
||||
.writedata_slave (vbuf_writedata),
|
||||
.byteenable_slave (vbuf_byteenable),
|
||||
.write_slave (vbuf_write),
|
||||
|
||||
.waitrequest_master (f2h_vbuf_waitrequest),
|
||||
.burstcount_master (f2h_vbuf_burstcount),
|
||||
.address_master (f2h_vbuf_address),
|
||||
.readdata_master (f2h_vbuf_readdata),
|
||||
.readdatavalid_master (f2h_vbuf_readdatavalid),
|
||||
.read_master (f2h_vbuf_read),
|
||||
.writedata_master (f2h_vbuf_writedata),
|
||||
.byteenable_master (f2h_vbuf_byteenable),
|
||||
.write_master (f2h_vbuf_write)
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////
|
||||
//// HPS <> FPGA interfaces ////
|
||||
////////////////////////////////////////////////////////
|
||||
sysmem_HPS_fpga_interfaces fpga_interfaces (
|
||||
.f2h_cold_rst_req_n (~reset_hps_cold_req),
|
||||
.f2h_warm_rst_req_n (~reset_hps_warm_req),
|
||||
.h2f_user0_clk (clock),
|
||||
.h2f_rst_n (hps_h2f_reset_n),
|
||||
.f2h_sdram0_clk (vbuf_clk),
|
||||
.f2h_sdram0_ADDRESS (f2h_vbuf_address),
|
||||
.f2h_sdram0_BURSTCOUNT (f2h_vbuf_burstcount),
|
||||
.f2h_sdram0_WAITREQUEST (f2h_vbuf_waitrequest),
|
||||
.f2h_sdram0_READDATA (f2h_vbuf_readdata),
|
||||
.f2h_sdram0_READDATAVALID (f2h_vbuf_readdatavalid),
|
||||
.f2h_sdram0_READ (f2h_vbuf_read),
|
||||
.f2h_sdram0_WRITEDATA (f2h_vbuf_writedata),
|
||||
.f2h_sdram0_BYTEENABLE (f2h_vbuf_byteenable),
|
||||
.f2h_sdram0_WRITE (f2h_vbuf_write),
|
||||
.f2h_sdram1_clk (ram1_clk),
|
||||
.f2h_sdram1_ADDRESS (f2h_ram1_address),
|
||||
.f2h_sdram1_BURSTCOUNT (f2h_ram1_burstcount),
|
||||
.f2h_sdram1_WAITREQUEST (f2h_ram1_waitrequest),
|
||||
.f2h_sdram1_READDATA (f2h_ram1_readdata),
|
||||
.f2h_sdram1_READDATAVALID (f2h_ram1_readdatavalid),
|
||||
.f2h_sdram1_READ (f2h_ram1_read),
|
||||
.f2h_sdram1_WRITEDATA (f2h_ram1_writedata),
|
||||
.f2h_sdram1_BYTEENABLE (f2h_ram1_byteenable),
|
||||
.f2h_sdram1_WRITE (f2h_ram1_write),
|
||||
.f2h_sdram2_clk (ram2_clk),
|
||||
.f2h_sdram2_ADDRESS (f2h_ram2_address),
|
||||
.f2h_sdram2_BURSTCOUNT (f2h_ram2_burstcount),
|
||||
.f2h_sdram2_WAITREQUEST (f2h_ram2_waitrequest),
|
||||
.f2h_sdram2_READDATA (f2h_ram2_readdata),
|
||||
.f2h_sdram2_READDATAVALID (f2h_ram2_readdatavalid),
|
||||
.f2h_sdram2_READ (f2h_ram2_read),
|
||||
.f2h_sdram2_WRITEDATA (f2h_ram2_writedata),
|
||||
.f2h_sdram2_BYTEENABLE (f2h_ram2_byteenable),
|
||||
.f2h_sdram2_WRITE (f2h_ram2_write)
|
||||
);
|
||||
|
||||
wire hps_h2f_reset_n;
|
||||
|
||||
reg init_reset_n = 0;
|
||||
always @(posedge clock) begin
|
||||
integer timeout = 0;
|
||||
|
||||
if(timeout < 2000000) begin
|
||||
init_reset_n <= 0;
|
||||
timeout <= timeout + 1;
|
||||
end
|
||||
else init_reset_n <= 1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module sysmem_HPS_fpga_interfaces
|
||||
(
|
||||
// h2f_reset
|
||||
output wire [1 - 1 : 0 ] h2f_rst_n
|
||||
|
||||
// f2h_cold_reset_req
|
||||
,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
|
||||
|
||||
// f2h_warm_reset_req
|
||||
,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
|
||||
|
||||
// h2f_user0_clock
|
||||
,output wire [1 - 1 : 0 ] h2f_user0_clk
|
||||
|
||||
// f2h_sdram0_data
|
||||
,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
|
||||
,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
|
||||
,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
|
||||
,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
|
||||
,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
|
||||
,input wire [1 - 1 : 0 ] f2h_sdram0_READ
|
||||
,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
|
||||
,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
|
||||
,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
|
||||
|
||||
// f2h_sdram0_clock
|
||||
,input wire [1 - 1 : 0 ] f2h_sdram0_clk
|
||||
|
||||
// f2h_sdram1_data
|
||||
,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
|
||||
,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
|
||||
,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
|
||||
,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
|
||||
,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
|
||||
,input wire [1 - 1 : 0 ] f2h_sdram1_READ
|
||||
,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
|
||||
,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
|
||||
,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
|
||||
|
||||
// f2h_sdram1_clock
|
||||
,input wire [1 - 1 : 0 ] f2h_sdram1_clk
|
||||
|
||||
// f2h_sdram2_data
|
||||
,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
|
||||
,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
|
||||
,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
|
||||
,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
|
||||
,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
|
||||
,input wire [1 - 1 : 0 ] f2h_sdram2_READ
|
||||
,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
|
||||
,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
|
||||
,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
|
||||
|
||||
// f2h_sdram2_clock
|
||||
,input wire [1 - 1 : 0 ] f2h_sdram2_clk
|
||||
);
|
||||
|
||||
|
||||
wire [29 - 1 : 0] intermediate;
|
||||
assign intermediate[0:0] = ~intermediate[1:1];
|
||||
assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
|
||||
assign intermediate[2:2] = intermediate[9:9];
|
||||
assign intermediate[3:3] = intermediate[9:9];
|
||||
assign intermediate[5:5] = intermediate[9:9];
|
||||
assign intermediate[6:6] = intermediate[9:9];
|
||||
assign intermediate[10:10] = intermediate[9:9];
|
||||
assign intermediate[11:11] = ~intermediate[12:12];
|
||||
assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
|
||||
assign intermediate[13:13] = intermediate[18:18];
|
||||
assign intermediate[15:15] = intermediate[18:18];
|
||||
assign intermediate[19:19] = intermediate[18:18];
|
||||
assign intermediate[20:20] = ~intermediate[21:21];
|
||||
assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
|
||||
assign intermediate[22:22] = intermediate[27:27];
|
||||
assign intermediate[24:24] = intermediate[27:27];
|
||||
assign intermediate[28:28] = intermediate[27:27];
|
||||
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
|
||||
assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
|
||||
assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
|
||||
assign intermediate[4:4] = f2h_sdram0_READ[0:0];
|
||||
assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
|
||||
assign intermediate[9:9] = f2h_sdram0_clk[0:0];
|
||||
assign intermediate[14:14] = f2h_sdram1_READ[0:0];
|
||||
assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
|
||||
assign intermediate[18:18] = f2h_sdram1_clk[0:0];
|
||||
assign intermediate[23:23] = f2h_sdram2_READ[0:0];
|
||||
assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
|
||||
assign intermediate[27:27] = f2h_sdram2_clk[0:0];
|
||||
|
||||
cyclonev_hps_interface_clocks_resets clocks_resets(
|
||||
.f2h_warm_rst_req_n({
|
||||
f2h_warm_rst_req_n[0:0] // 0:0
|
||||
})
|
||||
,.f2h_pending_rst_ack({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
,.f2h_dbg_rst_req_n({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
,.h2f_rst_n({
|
||||
h2f_rst_n[0:0] // 0:0
|
||||
})
|
||||
,.f2h_cold_rst_req_n({
|
||||
f2h_cold_rst_req_n[0:0] // 0:0
|
||||
})
|
||||
,.h2f_user0_clk({
|
||||
h2f_user0_clk[0:0] // 0:0
|
||||
})
|
||||
);
|
||||
|
||||
|
||||
cyclonev_hps_interface_dbg_apb debug_apb(
|
||||
.DBG_APB_DISABLE({
|
||||
1'b0 // 0:0
|
||||
})
|
||||
,.P_CLK_EN({
|
||||
1'b0 // 0:0
|
||||
})
|
||||
);
|
||||
|
||||
|
||||
cyclonev_hps_interface_tpiu_trace tpiu(
|
||||
.traceclk_ctl({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
);
|
||||
|
||||
|
||||
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
|
||||
.boot_from_fpga_ready({
|
||||
1'b0 // 0:0
|
||||
})
|
||||
,.boot_from_fpga_on_failure({
|
||||
1'b0 // 0:0
|
||||
})
|
||||
,.bsel_en({
|
||||
1'b0 // 0:0
|
||||
})
|
||||
,.csel_en({
|
||||
1'b0 // 0:0
|
||||
})
|
||||
,.csel({
|
||||
2'b01 // 1:0
|
||||
})
|
||||
,.bsel({
|
||||
3'b001 // 2:0
|
||||
})
|
||||
);
|
||||
|
||||
|
||||
cyclonev_hps_interface_fpga2hps fpga2hps(
|
||||
.port_size_config({
|
||||
2'b11 // 1:0
|
||||
})
|
||||
);
|
||||
|
||||
|
||||
cyclonev_hps_interface_hps2fpga hps2fpga(
|
||||
.port_size_config({
|
||||
2'b11 // 1:0
|
||||
})
|
||||
);
|
||||
|
||||
|
||||
cyclonev_hps_interface_fpga2sdram f2sdram(
|
||||
.cfg_rfifo_cport_map({
|
||||
16'b0010000100000000 // 15:0
|
||||
})
|
||||
,.cfg_wfifo_cport_map({
|
||||
16'b0010000100000000 // 15:0
|
||||
})
|
||||
,.rd_ready_3({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
,.cmd_port_clk_2({
|
||||
intermediate[28:28] // 0:0
|
||||
})
|
||||
,.rd_ready_2({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
,.cmd_port_clk_1({
|
||||
intermediate[19:19] // 0:0
|
||||
})
|
||||
,.rd_ready_1({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
,.cmd_port_clk_0({
|
||||
intermediate[10:10] // 0:0
|
||||
})
|
||||
,.rd_ready_0({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
,.wrack_ready_2({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
,.wrack_ready_1({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
,.wrack_ready_0({
|
||||
1'b1 // 0:0
|
||||
})
|
||||
,.cmd_ready_2({
|
||||
intermediate[21:21] // 0:0
|
||||
})
|
||||
,.cmd_ready_1({
|
||||
intermediate[12:12] // 0:0
|
||||
})
|
||||
,.cmd_ready_0({
|
||||
intermediate[1:1] // 0:0
|
||||
})
|
||||
,.cfg_port_width({
|
||||
12'b000000010110 // 11:0
|
||||
})
|
||||
,.rd_valid_3({
|
||||
f2h_sdram2_READDATAVALID[0:0] // 0:0
|
||||
})
|
||||
,.rd_valid_2({
|
||||
f2h_sdram1_READDATAVALID[0:0] // 0:0
|
||||
})
|
||||
,.rd_valid_1({
|
||||
f2h_sdram0_READDATAVALID[0:0] // 0:0
|
||||
})
|
||||
,.rd_clk_3({
|
||||
intermediate[22:22] // 0:0
|
||||
})
|
||||
,.rd_data_3({
|
||||
f2h_sdram2_READDATA[63:0] // 63:0
|
||||
})
|
||||
,.rd_clk_2({
|
||||
intermediate[13:13] // 0:0
|
||||
})
|
||||
,.rd_data_2({
|
||||
f2h_sdram1_READDATA[63:0] // 63:0
|
||||
})
|
||||
,.rd_clk_1({
|
||||
intermediate[3:3] // 0:0
|
||||
})
|
||||
,.rd_data_1({
|
||||
f2h_sdram0_READDATA[127:64] // 63:0
|
||||
})
|
||||
,.rd_clk_0({
|
||||
intermediate[2:2] // 0:0
|
||||
})
|
||||
,.rd_data_0({
|
||||
f2h_sdram0_READDATA[63:0] // 63:0
|
||||
})
|
||||
,.cfg_axi_mm_select({
|
||||
6'b000000 // 5:0
|
||||
})
|
||||
,.cmd_valid_2({
|
||||
intermediate[26:26] // 0:0
|
||||
})
|
||||
,.cmd_valid_1({
|
||||
intermediate[17:17] // 0:0
|
||||
})
|
||||
,.cmd_valid_0({
|
||||
intermediate[8:8] // 0:0
|
||||
})
|
||||
,.cfg_cport_rfifo_map({
|
||||
18'b000000000011010000 // 17:0
|
||||
})
|
||||
,.wr_data_3({
|
||||
2'b00 // 89:88
|
||||
,f2h_sdram2_BYTEENABLE[7:0] // 87:80
|
||||
,16'b0000000000000000 // 79:64
|
||||
,f2h_sdram2_WRITEDATA[63:0] // 63:0
|
||||
})
|
||||
,.wr_data_2({
|
||||
2'b00 // 89:88
|
||||
,f2h_sdram1_BYTEENABLE[7:0] // 87:80
|
||||
,16'b0000000000000000 // 79:64
|
||||
,f2h_sdram1_WRITEDATA[63:0] // 63:0
|
||||
})
|
||||
,.wr_data_1({
|
||||
2'b00 // 89:88
|
||||
,f2h_sdram0_BYTEENABLE[15:8] // 87:80
|
||||
,16'b0000000000000000 // 79:64
|
||||
,f2h_sdram0_WRITEDATA[127:64] // 63:0
|
||||
})
|
||||
,.cfg_cport_type({
|
||||
12'b000000111111 // 11:0
|
||||
})
|
||||
,.wr_data_0({
|
||||
2'b00 // 89:88
|
||||
,f2h_sdram0_BYTEENABLE[7:0] // 87:80
|
||||
,16'b0000000000000000 // 79:64
|
||||
,f2h_sdram0_WRITEDATA[63:0] // 63:0
|
||||
})
|
||||
,.cfg_cport_wfifo_map({
|
||||
18'b000000000011010000 // 17:0
|
||||
})
|
||||
,.wr_clk_3({
|
||||
intermediate[24:24] // 0:0
|
||||
})
|
||||
,.wr_clk_2({
|
||||
intermediate[15:15] // 0:0
|
||||
})
|
||||
,.wr_clk_1({
|
||||
intermediate[6:6] // 0:0
|
||||
})
|
||||
,.wr_clk_0({
|
||||
intermediate[5:5] // 0:0
|
||||
})
|
||||
,.cmd_data_2({
|
||||
18'b000000000000000000 // 59:42
|
||||
,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
|
||||
,3'b000 // 33:31
|
||||
,f2h_sdram2_ADDRESS[28:0] // 30:2
|
||||
,intermediate[25:25] // 1:1
|
||||
,intermediate[23:23] // 0:0
|
||||
})
|
||||
,.cmd_data_1({
|
||||
18'b000000000000000000 // 59:42
|
||||
,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
|
||||
,3'b000 // 33:31
|
||||
,f2h_sdram1_ADDRESS[28:0] // 30:2
|
||||
,intermediate[16:16] // 1:1
|
||||
,intermediate[14:14] // 0:0
|
||||
})
|
||||
,.cmd_data_0({
|
||||
18'b000000000000000000 // 59:42
|
||||
,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
|
||||
,4'b0000 // 33:30
|
||||
,f2h_sdram0_ADDRESS[27:0] // 29:2
|
||||
,intermediate[7:7] // 1:1
|
||||
,intermediate[4:4] // 0:0
|
||||
})
|
||||
);
|
||||
|
||||
endmodule
|
||||
68
Computer_MiST/Interact_MiST/Neuer Ordner/sys/vga_out.sv
Normal file
68
Computer_MiST/Interact_MiST/Neuer Ordner/sys/vga_out.sv
Normal file
@@ -0,0 +1,68 @@
|
||||
|
||||
module vga_out
|
||||
(
|
||||
input clk,
|
||||
input ypbpr_en,
|
||||
|
||||
input hsync,
|
||||
input vsync,
|
||||
input csync,
|
||||
|
||||
input [23:0] din,
|
||||
output [23:0] dout,
|
||||
|
||||
output reg hsync_o,
|
||||
output reg vsync_o,
|
||||
output reg csync_o
|
||||
);
|
||||
|
||||
wire [5:0] red = din[23:18];
|
||||
wire [5:0] green = din[15:10];
|
||||
wire [5:0] blue = din[7:2];
|
||||
|
||||
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
|
||||
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
reg [7:0] y, pb, pr;
|
||||
reg [23:0] rgb;
|
||||
always @(posedge clk) begin
|
||||
reg [18:0] y_1r, pb_1r, pr_1r;
|
||||
reg [18:0] y_1g, pb_1g, pr_1g;
|
||||
reg [18:0] y_1b, pb_1b, pr_1b;
|
||||
reg [18:0] y_2, pb_2, pr_2;
|
||||
reg [23:0] din1, din2;
|
||||
reg hsync2, vsync2, csync2;
|
||||
reg hsync1, vsync1, csync1;
|
||||
|
||||
y_1r <= 19'd04096 + ({red, 8'd0} + {red, 3'd0});
|
||||
pb_1r <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0});
|
||||
pr_1r <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0});
|
||||
|
||||
y_1g <= {green, 9'd0} + {green, 2'd0};
|
||||
pb_1g <= {green, 8'd0} + {green, 5'd0} + {green, 3'd0};
|
||||
pr_1g <= {green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0};
|
||||
|
||||
y_1b <= {blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0};
|
||||
pb_1b <= {blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0};
|
||||
pr_1b <= {blue, 6'd0} + {blue, 3'd0};
|
||||
|
||||
y_2 <= y_1r + y_1g + y_1b;
|
||||
pb_2 <= pb_1r - pb_1g + pb_1b;
|
||||
pr_2 <= pr_1r - pr_1g - pr_1b;
|
||||
|
||||
y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8];
|
||||
pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8];
|
||||
pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8];
|
||||
|
||||
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
|
||||
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
|
||||
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
|
||||
|
||||
rgb <= din2; din2 <= din1; din1 <= din;
|
||||
end
|
||||
|
||||
assign dout = ypbpr_en ? {pr, y, pb} : rgb;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,99 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2018 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module video_cleaner
|
||||
(
|
||||
input clk_vid,
|
||||
input ce_pix,
|
||||
|
||||
input [7:0] R,
|
||||
input [7:0] G,
|
||||
input [7:0] B,
|
||||
|
||||
input HSync,
|
||||
input VSync,
|
||||
input HBlank,
|
||||
input VBlank,
|
||||
|
||||
//optional de
|
||||
input DE_in,
|
||||
|
||||
// video output signals
|
||||
output reg [7:0] VGA_R,
|
||||
output reg [7:0] VGA_G,
|
||||
output reg [7:0] VGA_B,
|
||||
output reg VGA_VS,
|
||||
output reg VGA_HS,
|
||||
output VGA_DE,
|
||||
|
||||
// optional aligned blank
|
||||
output reg HBlank_out,
|
||||
output reg VBlank_out,
|
||||
|
||||
// optional aligned de
|
||||
output reg DE_out
|
||||
);
|
||||
|
||||
wire hs, vs;
|
||||
s_fix sync_v(clk_vid, HSync, hs);
|
||||
s_fix sync_h(clk_vid, VSync, vs);
|
||||
|
||||
wire hbl = hs | HBlank;
|
||||
wire vbl = vs | VBlank;
|
||||
|
||||
assign VGA_DE = ~(HBlank_out | VBlank_out);
|
||||
|
||||
always @(posedge clk_vid) begin
|
||||
if(ce_pix) begin
|
||||
HBlank_out <= hbl;
|
||||
|
||||
VGA_HS <= hs;
|
||||
if(~VGA_HS & hs) VGA_VS <= vs;
|
||||
|
||||
VGA_R <= R;
|
||||
VGA_G <= G;
|
||||
VGA_B <= B;
|
||||
DE_out <= DE_in;
|
||||
|
||||
if(HBlank_out & ~hbl) VBlank_out <= vbl;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module s_fix
|
||||
(
|
||||
input clk,
|
||||
|
||||
input sync_in,
|
||||
output sync_out
|
||||
);
|
||||
|
||||
assign sync_out = sync_in ^ pol;
|
||||
|
||||
reg pol;
|
||||
always @(posedge clk) begin
|
||||
integer pos = 0, neg = 0, cnt = 0;
|
||||
reg s1,s2;
|
||||
|
||||
s1 <= sync_in;
|
||||
s2 <= s1;
|
||||
|
||||
if(~s2 & s1) neg <= cnt;
|
||||
if(s2 & ~s1) pos <= cnt;
|
||||
|
||||
cnt <= cnt + 1;
|
||||
if(s2 != s1) cnt <= 0;
|
||||
|
||||
pol <= pos > neg;
|
||||
end
|
||||
|
||||
endmodule
|
||||
278
Computer_MiST/Interact_MiST/Neuer Ordner/sys/video_freak.sv
Normal file
278
Computer_MiST/Interact_MiST/Neuer Ordner/sys/video_freak.sv
Normal file
@@ -0,0 +1,278 @@
|
||||
//
|
||||
//
|
||||
// Video crop
|
||||
// Copyright (c) 2020 Grabulosaure, (c) 2021 Alexey Melnikov
|
||||
//
|
||||
// Integer scaling
|
||||
// Copyright (c) 2021 Alexey Melnikov
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module video_freak
|
||||
(
|
||||
input CLK_VIDEO,
|
||||
input CE_PIXEL,
|
||||
input VGA_VS,
|
||||
input [11:0] HDMI_WIDTH,
|
||||
input [11:0] HDMI_HEIGHT,
|
||||
output VGA_DE,
|
||||
output reg [12:0] VIDEO_ARX,
|
||||
output reg [12:0] VIDEO_ARY,
|
||||
|
||||
input VGA_DE_IN,
|
||||
input [11:0] ARX,
|
||||
input [11:0] ARY,
|
||||
input [11:0] CROP_SIZE,
|
||||
input [4:0] CROP_OFF, // -16...+15
|
||||
input [2:0] SCALE //0 - normal, 1 - V-integer, 2 - HV-Integer-, 3 - HV-Integer+, 4 - HV-Integer
|
||||
);
|
||||
|
||||
reg mul_start;
|
||||
wire mul_run;
|
||||
reg [11:0] mul_arg1, mul_arg2;
|
||||
wire [23:0] mul_res;
|
||||
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
|
||||
|
||||
reg vde;
|
||||
reg [11:0] arxo,aryo;
|
||||
reg [11:0] vsize;
|
||||
reg [11:0] hsize;
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg old_de, old_vs,ovde;
|
||||
reg [11:0] vtot,vcpt,vcrop,voff;
|
||||
reg [11:0] hcpt;
|
||||
reg [11:0] vadj;
|
||||
reg [23:0] ARXG,ARYG;
|
||||
reg [11:0] arx,ary;
|
||||
reg [1:0] vcalc;
|
||||
|
||||
if (CE_PIXEL) begin
|
||||
old_de <= VGA_DE_IN;
|
||||
old_vs <= VGA_VS;
|
||||
if (VGA_VS & ~old_vs) begin
|
||||
vcpt <= 0;
|
||||
vtot <= vcpt;
|
||||
vcalc <= 1;
|
||||
vcrop <= (CROP_SIZE >= vcpt) ? 12'd0 : CROP_SIZE;
|
||||
end
|
||||
|
||||
if (VGA_DE_IN) hcpt <= hcpt + 1'd1;
|
||||
if (~VGA_DE_IN & old_de) begin
|
||||
vcpt <= vcpt + 1'd1;
|
||||
if(!vcpt) hsize <= hcpt;
|
||||
hcpt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
arx <= ARX;
|
||||
ary <= ARY;
|
||||
|
||||
vsize <= vcrop ? vcrop : vtot;
|
||||
|
||||
mul_start <= 0;
|
||||
|
||||
if(!vcrop || !ary || !arx) begin
|
||||
arxo <= arx;
|
||||
aryo <= ary;
|
||||
end
|
||||
else if (vcalc) begin
|
||||
if(~mul_start & ~mul_run) begin
|
||||
vcalc <= vcalc + 1'd1;
|
||||
case(vcalc)
|
||||
1: begin
|
||||
mul_arg1 <= arx;
|
||||
mul_arg2 <= vtot;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
2: begin
|
||||
ARXG <= mul_res;
|
||||
mul_arg1 <= ary;
|
||||
mul_arg2 <= vcrop;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
3: begin
|
||||
ARYG <= mul_res;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else if (ARXG[23] | ARYG[23]) begin
|
||||
arxo <= ARXG[23:12];
|
||||
aryo <= ARYG[23:12];
|
||||
end
|
||||
else begin
|
||||
ARXG <= ARXG << 1;
|
||||
ARYG <= ARYG << 1;
|
||||
end
|
||||
|
||||
vadj <= (vtot-vcrop) + {{6{CROP_OFF[4]}},CROP_OFF,1'b0};
|
||||
voff <= vadj[11] ? 12'd0 : ((vadj[11:1] + vcrop) > vtot) ? vtot-vcrop : vadj[11:1];
|
||||
ovde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop;
|
||||
vde <= ovde;
|
||||
end
|
||||
|
||||
assign VGA_DE = vde & VGA_DE_IN;
|
||||
|
||||
video_scale_int scale
|
||||
(
|
||||
.CLK_VIDEO(CLK_VIDEO),
|
||||
.HDMI_WIDTH(HDMI_WIDTH),
|
||||
.HDMI_HEIGHT(HDMI_HEIGHT),
|
||||
.SCALE(SCALE),
|
||||
.hsize(hsize),
|
||||
.vsize(vsize),
|
||||
.arx_i(arxo),
|
||||
.ary_i(aryo),
|
||||
.arx_o(VIDEO_ARX),
|
||||
.ary_o(VIDEO_ARY)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module video_scale_int
|
||||
(
|
||||
input CLK_VIDEO,
|
||||
|
||||
input [11:0] HDMI_WIDTH,
|
||||
input [11:0] HDMI_HEIGHT,
|
||||
|
||||
input [2:0] SCALE,
|
||||
|
||||
input [11:0] hsize,
|
||||
input [11:0] vsize,
|
||||
|
||||
input [11:0] arx_i,
|
||||
input [11:0] ary_i,
|
||||
|
||||
output reg [12:0] arx_o,
|
||||
output reg [12:0] ary_o
|
||||
);
|
||||
|
||||
reg div_start;
|
||||
wire div_run;
|
||||
reg [23:0] div_num;
|
||||
reg [11:0] div_den;
|
||||
wire [23:0] div_res;
|
||||
sys_udiv #(24,12) div(CLK_VIDEO,div_start,div_run, div_num,div_den,div_res);
|
||||
|
||||
reg mul_start;
|
||||
wire mul_run;
|
||||
reg [11:0] mul_arg1, mul_arg2;
|
||||
wire [23:0] mul_res;
|
||||
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
|
||||
|
||||
wire [11:0] wideres = mul_res[11:0] + hsize;
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg [11:0] oheight,wres;
|
||||
reg [12:0] arxf,aryf;
|
||||
reg [3:0] cnt;
|
||||
reg narrow;
|
||||
|
||||
div_start <= 0;
|
||||
mul_start <= 0;
|
||||
|
||||
if (!SCALE || (!ary_i && arx_i)) begin
|
||||
arxf <= arx_i;
|
||||
aryf <= ary_i;
|
||||
end
|
||||
else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt)
|
||||
0: begin
|
||||
div_num <= HDMI_HEIGHT;
|
||||
div_den <= vsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
|
||||
1: if(!div_res[11:0]) begin
|
||||
// screen resolution is lower than video resolution.
|
||||
// Integer scaling is impossible.
|
||||
arxf <= arx_i;
|
||||
aryf <= ary_i;
|
||||
cnt <= 0;
|
||||
end
|
||||
else begin
|
||||
mul_arg1 <= vsize;
|
||||
mul_arg2 <= div_res[11:0];
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
2: begin
|
||||
oheight <= mul_res[11:0];
|
||||
if(!ary_i) begin
|
||||
cnt <= 8;
|
||||
end
|
||||
end
|
||||
|
||||
3: begin
|
||||
mul_arg1 <= mul_res[11:0];
|
||||
mul_arg2 <= arx_i;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
4: begin
|
||||
div_num <= mul_res;
|
||||
div_den <= ary_i;
|
||||
div_start <= 1;
|
||||
end
|
||||
|
||||
5: begin
|
||||
div_num <= div_res;
|
||||
div_den <= hsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
|
||||
6: begin
|
||||
mul_arg1 <= hsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
7: if(mul_res <= HDMI_WIDTH) begin
|
||||
cnt <= 10;
|
||||
end
|
||||
|
||||
8: begin
|
||||
div_num <= HDMI_WIDTH;
|
||||
div_den <= hsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
|
||||
9: begin
|
||||
mul_arg1 <= hsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
10: begin
|
||||
narrow <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH);
|
||||
wres <= wideres;
|
||||
end
|
||||
|
||||
11: begin
|
||||
case(SCALE)
|
||||
2: arxf <= {1'b1, mul_res[11:0]};
|
||||
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
|
||||
4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres};
|
||||
default: arxf <= {1'b1, div_num[11:0]};
|
||||
endcase
|
||||
aryf <= {1'b1, oheight};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
arx_o <= arxf;
|
||||
ary_o <= aryf;
|
||||
end
|
||||
|
||||
endmodule
|
||||
143
Computer_MiST/Interact_MiST/Neuer Ordner/sys/video_freezer.sv
Normal file
143
Computer_MiST/Interact_MiST/Neuer Ordner/sys/video_freezer.sv
Normal file
@@ -0,0 +1,143 @@
|
||||
//
|
||||
// video freeze with sync
|
||||
// (C) Alexey Melnikov
|
||||
//
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify it
|
||||
// under the terms of the GNU General Public License as published by the Free
|
||||
// Software Foundation; either version 2 of the License, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
// more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
|
||||
module video_freezer
|
||||
(
|
||||
input clk,
|
||||
|
||||
output sync,
|
||||
input freeze,
|
||||
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input hbl_in,
|
||||
input vbl_in,
|
||||
|
||||
output hs_out,
|
||||
output vs_out,
|
||||
output hbl_out,
|
||||
output vbl_out
|
||||
);
|
||||
|
||||
sync_lock #(33) vs_lock
|
||||
(
|
||||
.clk(clk),
|
||||
.sync_in(vs_in),
|
||||
.sync_out(vs_out),
|
||||
.de_in(vbl_in),
|
||||
.de_out(vbl_out),
|
||||
.freeze(freeze)
|
||||
);
|
||||
|
||||
wire sync_pt;
|
||||
sync_lock #(21) hs_lock
|
||||
(
|
||||
.clk(clk),
|
||||
.sync_in(hs_in),
|
||||
.sync_out(hs_out),
|
||||
.de_in(hbl_in),
|
||||
.de_out(hbl_out),
|
||||
.freeze(freeze),
|
||||
.sync_pt(sync_pt)
|
||||
);
|
||||
|
||||
reg sync_o;
|
||||
always @(posedge clk) begin
|
||||
reg old_hs, old_vs;
|
||||
reg vs_sync;
|
||||
|
||||
old_vs <= vs_out;
|
||||
|
||||
if(~old_vs & vs_out) vs_sync <= 1;
|
||||
if(sync_pt & vs_sync) begin
|
||||
vs_sync <= 0;
|
||||
sync_o <= ~sync_o;
|
||||
end
|
||||
end
|
||||
|
||||
assign sync = sync_o;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module sync_lock #(parameter WIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input sync_in,
|
||||
input de_in,
|
||||
|
||||
output sync_out,
|
||||
output de_out,
|
||||
|
||||
input freeze,
|
||||
output sync_pt,
|
||||
output valid
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] f_len, s_len, de_start, de_end;
|
||||
reg sync_valid;
|
||||
|
||||
reg old_sync;
|
||||
always @(posedge clk) old_sync <= sync_in;
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [WIDTH-1:0] cnti;
|
||||
reg f_valid;
|
||||
reg old_de;
|
||||
|
||||
cnti <= cnti + 1'd1;
|
||||
if(~old_sync & sync_in) begin
|
||||
if(sync_valid) f_len <= cnti;
|
||||
f_valid <= 1;
|
||||
sync_valid <= f_valid;
|
||||
cnti <= 0;
|
||||
end
|
||||
|
||||
if(old_sync & ~sync_in & sync_valid) s_len <= cnti;
|
||||
|
||||
old_de <= de_in;
|
||||
if(~old_de & de_in & sync_valid) de_start <= cnti;
|
||||
if(old_de & ~de_in & sync_valid) de_end <= cnti;
|
||||
|
||||
if(freeze) {f_valid, sync_valid} <= 0;
|
||||
end
|
||||
|
||||
reg sync_o, de_o, sync_o_pre;
|
||||
always @(posedge clk) begin
|
||||
reg [WIDTH-1:0] cnto;
|
||||
|
||||
cnto <= cnto + 1'd1;
|
||||
if(old_sync & ~sync_in & sync_valid) cnto <= s_len + 2'd2;
|
||||
if(cnto == f_len) cnto <= 0;
|
||||
|
||||
sync_o_pre <= (cnto == (s_len>>1)); // middle in sync
|
||||
if(cnto == f_len) sync_o <= 1;
|
||||
if(cnto == s_len) sync_o <= 0;
|
||||
if(cnto == de_start) de_o <= 1;
|
||||
if(cnto == de_end) de_o <= 0;
|
||||
end
|
||||
|
||||
assign sync_out = freeze ? sync_o : sync_in;
|
||||
assign valid = sync_valid;
|
||||
assign sync_pt = sync_o_pre;
|
||||
assign de_out = freeze ? de_o : de_in;
|
||||
|
||||
endmodule
|
||||
219
Computer_MiST/Interact_MiST/Neuer Ordner/sys/video_mixer.sv
Normal file
219
Computer_MiST/Interact_MiST/Neuer Ordner/sys/video_mixer.sv
Normal file
@@ -0,0 +1,219 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2017,2021 Alexey Melnikov
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
// LINE_LENGTH: Length of display line in pixels when HBlank = 0;
|
||||
// HALF_DEPTH: If =1 then color dept is 4 bits per component
|
||||
//
|
||||
// altera message_off 10720
|
||||
// altera message_off 12161
|
||||
|
||||
module video_mixer
|
||||
#(
|
||||
parameter LINE_LENGTH = 768,
|
||||
parameter HALF_DEPTH = 0,
|
||||
parameter GAMMA = 0
|
||||
)
|
||||
(
|
||||
input CLK_VIDEO, // should be multiple by (ce_pix*4)
|
||||
output reg CE_PIXEL, // output pixel clock enable
|
||||
|
||||
input ce_pix, // input pixel clock or clock_enable
|
||||
|
||||
input scandoubler,
|
||||
input hq2x, // high quality 2x scaling
|
||||
|
||||
inout [21:0] gamma_bus,
|
||||
|
||||
// color
|
||||
input [DWIDTH:0] R,
|
||||
input [DWIDTH:0] G,
|
||||
input [DWIDTH:0] B,
|
||||
|
||||
// Positive pulses.
|
||||
input HSync,
|
||||
input VSync,
|
||||
input HBlank,
|
||||
input VBlank,
|
||||
|
||||
// Freeze engine
|
||||
// HDMI: displays last frame
|
||||
// VGA: black screen with HSync and VSync
|
||||
input HDMI_FREEZE,
|
||||
output freeze_sync,
|
||||
|
||||
// video output signals
|
||||
output reg [7:0] VGA_R,
|
||||
output reg [7:0] VGA_G,
|
||||
output reg [7:0] VGA_B,
|
||||
output reg VGA_VS,
|
||||
output reg VGA_HS,
|
||||
output reg VGA_DE
|
||||
);
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
|
||||
localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH;
|
||||
localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH;
|
||||
|
||||
wire frz_hs, frz_vs;
|
||||
wire frz_hbl, frz_vbl;
|
||||
video_freezer freezer
|
||||
(
|
||||
.clk(CLK_VIDEO),
|
||||
.freeze(HDMI_FREEZE),
|
||||
.hs_in(HSync),
|
||||
.vs_in(VSync),
|
||||
.hbl_in(HBlank),
|
||||
.vbl_in(VBlank),
|
||||
.sync(freeze_sync),
|
||||
.hs_out(frz_hs),
|
||||
.vs_out(frz_vs),
|
||||
.hbl_out(frz_hbl),
|
||||
.vbl_out(frz_vbl)
|
||||
);
|
||||
|
||||
reg frz;
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg frz1;
|
||||
|
||||
frz1 <= HDMI_FREEZE;
|
||||
frz <= frz1;
|
||||
end
|
||||
|
||||
generate
|
||||
if(GAMMA && HALF_DEPTH) begin
|
||||
wire [7:0] R_in = frz ? 8'd0 : {R,R};
|
||||
wire [7:0] G_in = frz ? 8'd0 : {G,G};
|
||||
wire [7:0] B_in = frz ? 8'd0 : {B,B};
|
||||
end else begin
|
||||
wire [DWIDTH:0] R_in = frz ? 1'd0 : R;
|
||||
wire [DWIDTH:0] G_in = frz ? 1'd0 : G;
|
||||
wire [DWIDTH:0] B_in = frz ? 1'd0 : B;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire hs_g, vs_g;
|
||||
wire hb_g, vb_g;
|
||||
wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma;
|
||||
|
||||
generate
|
||||
if(GAMMA) begin
|
||||
assign gamma_bus[21] = 1;
|
||||
gamma_corr gamma(
|
||||
.clk_sys(gamma_bus[20]),
|
||||
.clk_vid(CLK_VIDEO),
|
||||
.ce_pix(ce_pix),
|
||||
|
||||
.gamma_en(gamma_bus[19]),
|
||||
.gamma_wr(gamma_bus[18]),
|
||||
.gamma_wr_addr(gamma_bus[17:8]),
|
||||
.gamma_value(gamma_bus[7:0]),
|
||||
|
||||
.HSync(frz_hs),
|
||||
.VSync(frz_vs),
|
||||
.HBlank(frz_hbl),
|
||||
.VBlank(frz_vbl),
|
||||
.RGB_in({R_in,G_in,B_in}),
|
||||
|
||||
.HSync_out(hs_g),
|
||||
.VSync_out(vs_g),
|
||||
.HBlank_out(hb_g),
|
||||
.VBlank_out(vb_g),
|
||||
.RGB_out({R_gamma,G_gamma,B_gamma})
|
||||
);
|
||||
end else begin
|
||||
assign gamma_bus[21] = 0;
|
||||
assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in};
|
||||
assign {hs_g, vs_g, hb_g, vb_g} = {frz_hs, frz_vs, frz_hbl, frz_vbl};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire [DWIDTH_SD:0] R_sd;
|
||||
wire [DWIDTH_SD:0] G_sd;
|
||||
wire [DWIDTH_SD:0] B_sd;
|
||||
wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
|
||||
|
||||
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd
|
||||
(
|
||||
.clk_vid(CLK_VIDEO),
|
||||
.hq2x(hq2x),
|
||||
|
||||
.ce_pix(ce_pix),
|
||||
.hs_in(hs_g),
|
||||
.vs_in(vs_g),
|
||||
.hb_in(hb_g),
|
||||
.vb_in(vb_g),
|
||||
.r_in(R_gamma),
|
||||
.g_in(G_gamma),
|
||||
.b_in(B_gamma),
|
||||
|
||||
.ce_pix_out(ce_pix_sd),
|
||||
.hs_out(hs_sd),
|
||||
.vs_out(vs_sd),
|
||||
.hb_out(hb_sd),
|
||||
.vb_out(vb_sd),
|
||||
.r_out(R_sd),
|
||||
.g_out(G_sd),
|
||||
.b_out(B_sd)
|
||||
);
|
||||
|
||||
wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma);
|
||||
wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma);
|
||||
wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma);
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg [7:0] r,g,b;
|
||||
reg hde,vde,hs,vs, old_vs;
|
||||
reg old_hde;
|
||||
reg old_ce;
|
||||
reg ce_osc, fs_osc;
|
||||
|
||||
old_ce <= ce_pix;
|
||||
ce_osc <= ce_osc | (old_ce ^ ce_pix);
|
||||
|
||||
old_vs <= vs;
|
||||
if(~old_vs & vs) begin
|
||||
fs_osc <= ce_osc;
|
||||
ce_osc <= 0;
|
||||
end
|
||||
|
||||
CE_PIXEL <= scandoubler ? ce_pix_sd : fs_osc ? (~old_ce & ce_pix) : ce_pix;
|
||||
|
||||
if(!GAMMA && HALF_DEPTH) begin
|
||||
r <= {rt,rt};
|
||||
g <= {gt,gt};
|
||||
b <= {bt,bt};
|
||||
end
|
||||
else begin
|
||||
r <= rt;
|
||||
g <= gt;
|
||||
b <= bt;
|
||||
end
|
||||
|
||||
hde <= scandoubler ? ~hb_sd : ~hb_g;
|
||||
vde <= scandoubler ? ~vb_sd : ~vb_g;
|
||||
vs <= scandoubler ? vs_sd : vs_g;
|
||||
hs <= scandoubler ? hs_sd : hs_g;
|
||||
|
||||
if(CE_PIXEL) begin
|
||||
VGA_R <= r;
|
||||
VGA_G <= g;
|
||||
VGA_B <= b;
|
||||
|
||||
VGA_VS <= vs;
|
||||
VGA_HS <= hs;
|
||||
|
||||
old_hde <= hde;
|
||||
if(old_hde ^ hde) VGA_DE <= vde & hde;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
26
Computer_MiST/Interact_MiST/README.md
Normal file
26
Computer_MiST/Interact_MiST/README.md
Normal file
@@ -0,0 +1,26 @@
|
||||
# [Interact](https://en.wikipedia.org/wiki/Interact_Home_Computer) for [MiSTer Platform](https://github.com/MiSTer-devel/Main_MiSTer/wiki)
|
||||
|
||||
<p align="center">
|
||||
<img width="320" height="240" src="https://user-images.githubusercontent.com/105246/129508473-bd14a5fa-3d2d-439b-a9a8-3a239660182f.gif">
|
||||
</p>
|
||||
|
||||
FPGA recreation of the Interact Home Computer from 1978. You can read about it on [Wikipedia](https://en.wikipedia.org/wiki/Interact_Home_Computer) and [Old-Computers.com](https://www.old-computers.com/museum/computer.asp?c=1004&st=1). Core created by [@edanuff](https://github.com/edanuff).
|
||||
|
||||
### Features
|
||||
- Cycle accurate, used the original schematics to recreate the discrete logic as closely as possible in Verilog
|
||||
- Uses the [vm80a](https://github.com/1801BM1/vm80a) reverse-engineered 8080a core
|
||||
- Compatible with .K7 and .CIN tape formats used by the MAME Interact, [DCHector](http://dchector.free.fr/index.html), and [Virtual Interact](http://www.geocities.ws/emucompboy/) emulators
|
||||
- An [Online Tape Converter](https://interact-tape-converter.netlify.app/) is available for converting tapes to .K7 files
|
||||
- PS/2 to Interact Keyboard mapping
|
||||
- Joystick support
|
||||
- HDMI output
|
||||
|
||||
### Roadmap
|
||||
- SN76477 Sound
|
||||
- RS232C Peripheral Interface Emulation (MC6850)
|
||||
|
||||
Usage
|
||||
- Select Tape File
|
||||
- Press L
|
||||
|
||||
Not All Games will Work, Reduced the Ram for the Tape (BRAM)
|
||||
41
Computer_MiST/Interact_MiST/clean.bat
Normal file
41
Computer_MiST/Interact_MiST/clean.bat
Normal file
@@ -0,0 +1,41 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
cd sys
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
cd ..
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del *.cdf
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
del sys\vip.qip
|
||||
del sys\sysmem.qip
|
||||
del sys\sdram.sv
|
||||
del sys\ddram.sv
|
||||
pause
|
||||
173
Computer_MiST/Interact_MiST/rtl/Interact_MiST.sv
Normal file
173
Computer_MiST/Interact_MiST/rtl/Interact_MiST.sv
Normal file
@@ -0,0 +1,173 @@
|
||||
module Interact_MiST(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27
|
||||
);
|
||||
|
||||
`include "rtl\build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"Interact;CINK7;",
|
||||
"T8,Play;",
|
||||
"T9,Stop & Rewind;",
|
||||
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"O5,Blend,Off,On;",
|
||||
"O7,Test Pattern,Off,On;",
|
||||
"T0,Reset;",
|
||||
"V,v1.00.",`BUILD_DATE
|
||||
};
|
||||
|
||||
|
||||
wire [1:0] scanlines = status[4:3];
|
||||
wire blend = status[5];
|
||||
assign LED = ~tape_playing;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire clk_cas, clk_sys, pll_locked;
|
||||
pll pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.c0(clk_cas),//57.272727 MHz
|
||||
.c1(clk_sys),//14.318181 MHz 14.38180
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
wire [63:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [31:0] joystick_0;
|
||||
wire [31:0] joystick_1;
|
||||
wire [15:0] joystick_analog_0;
|
||||
wire [15:0] joystick_analog_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire no_csync;
|
||||
wire [15:0] audio;
|
||||
wire hsn, vsn;
|
||||
wire hbn, vbn;
|
||||
wire blankn = hbn | vbn;
|
||||
wire [7:0] r, g, b;
|
||||
wire key_strobe;
|
||||
wire key_pressed;
|
||||
wire key_extended;
|
||||
wire [7:0] key_code;
|
||||
wire tape_playing;
|
||||
|
||||
Interact_top Interact_top(
|
||||
.clk_cas(clk_cas),
|
||||
.clk_sys(clk_sys),
|
||||
.reset(status[0] | buttons[1]),
|
||||
.ps2_key({key_strobe,key_pressed,key_extended,key_code}),
|
||||
.joystick_0(joystick_0[15:0]),
|
||||
.joystick_1(joystick_1[15:0]),
|
||||
.joystick_analog_0(joystick_analog_0),
|
||||
.joystick_analog_1(joystick_analog_1),
|
||||
.hblank_n(hbn),
|
||||
.vblank_n(vbn),
|
||||
.hsync_n(hsn),
|
||||
.vsync_n(vsn),
|
||||
.R(r),
|
||||
.G(g),
|
||||
.B(b),
|
||||
.audio(audio),
|
||||
.test_sw(status[7]),
|
||||
.tape_play(status[8]),
|
||||
.tape_rewind(status[9]),
|
||||
.ioctl_data(ioctl_dout),
|
||||
.ioctl_wr(ioctl_wr),
|
||||
.ioctl_addr(ioctl_addr[14:0]),
|
||||
.ioctl_download(ioctl_downl),
|
||||
.tape_playing(tape_playing)
|
||||
);
|
||||
|
||||
wire ioctl_downl;
|
||||
wire ioctl_upl;
|
||||
wire [7:0] ioctl_index;
|
||||
wire ioctl_wr;
|
||||
wire [24:0] ioctl_addr;
|
||||
wire [7:0] ioctl_dout;
|
||||
wire [7:0] ioctl_din;
|
||||
|
||||
data_io data_io(
|
||||
.clk_sys ( clk_cas ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS2 ( SPI_SS2 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.SPI_DO ( SPI_DO ),
|
||||
.ioctl_download( ioctl_downl ),
|
||||
.ioctl_upload ( ioctl_upl ),
|
||||
.ioctl_index ( ioctl_index ),
|
||||
.ioctl_wr ( ioctl_wr ),
|
||||
.ioctl_addr ( ioctl_addr ),
|
||||
.ioctl_dout ( ioctl_dout ),
|
||||
.ioctl_din ( ioctl_din )
|
||||
);
|
||||
|
||||
|
||||
mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video(
|
||||
.clk_sys ( clk_cas ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.R ( r[7:2] ),
|
||||
.G ( g[7:2] ),
|
||||
.B ( b[7:2] ),
|
||||
.HSync ( hsn ),
|
||||
.VSync ( vsn ),
|
||||
.VGA_R ( VGA_R ),
|
||||
.VGA_G ( VGA_G ),
|
||||
.VGA_B ( VGA_B ),
|
||||
.VGA_VS ( VGA_VS ),
|
||||
.VGA_HS ( VGA_HS ),
|
||||
.blend ( blend ),
|
||||
.scandoubler_disable( scandoublerD ),
|
||||
.scanlines ( scanlines ),
|
||||
.ypbpr ( ypbpr ),
|
||||
.no_csync ( no_csync )
|
||||
);
|
||||
|
||||
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
|
||||
.clk_sys (clk_cas ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD),
|
||||
.ypbpr (ypbpr ),
|
||||
.no_csync (no_csync ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_extended (key_extended ),
|
||||
.key_code (key_code ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.joystick_analog_0(joystick_analog_0),
|
||||
.joystick_analog_1(joystick_analog_1),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac #(.C_bits(16))dac_l(
|
||||
.clk_i(clk_cas),
|
||||
.res_n_i(1),
|
||||
.dac_i({~audio[15],audio[14:0]}),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
622
Computer_MiST/Interact_MiST/rtl/Interact_top.sv
Normal file
622
Computer_MiST/Interact_MiST/rtl/Interact_top.sv
Normal file
@@ -0,0 +1,622 @@
|
||||
module Interact_top(
|
||||
input clk_cas,
|
||||
input clk_sys,
|
||||
input reset,
|
||||
input [10:0] ps2_key,
|
||||
input [15:0] joystick_0,
|
||||
input [15:0] joystick_1,
|
||||
input [15:0] joystick_analog_0,
|
||||
input [15:0] joystick_analog_1,
|
||||
input test_sw,
|
||||
input tape_play,
|
||||
input tape_rewind,
|
||||
input [7:0] ioctl_data,
|
||||
input ioctl_wr,
|
||||
input [15:0] ioctl_addr,
|
||||
input ioctl_download,
|
||||
output [15:0] audio,
|
||||
output reg hblank_n,
|
||||
output vblank_n,
|
||||
output hsync_n,
|
||||
output vsync_n,
|
||||
output [7:0] R,
|
||||
output [7:0] G,
|
||||
output [7:0] B,
|
||||
output reg tape_playing
|
||||
);
|
||||
|
||||
/////////////////////// CLOCKS ///////////////////////////////
|
||||
wire rst_n = ~reset;
|
||||
|
||||
// vm80a needs a nice long reset
|
||||
reg [7:0] rcnt = 8'h00;
|
||||
wire cpu_rst_n = (rcnt == 8'hFF);
|
||||
|
||||
always @(posedge clk_sys)
|
||||
begin
|
||||
if (reset)
|
||||
rcnt <= 8'h00;
|
||||
else
|
||||
if (rcnt != 8'hFF) rcnt <= rcnt + 8'h01;
|
||||
end
|
||||
|
||||
|
||||
wire ph1;
|
||||
wire ph2;
|
||||
wire cbclk;
|
||||
wire pix_a;
|
||||
wire vid_sel;
|
||||
wire [11:0] vid_a;
|
||||
wire vid_sel_n;
|
||||
wire nrr_n;
|
||||
wire ce_n;
|
||||
wire pce;
|
||||
wire vid_ltc;
|
||||
wire ram_clk;
|
||||
wire brst;
|
||||
wire tpclk;
|
||||
wire irq;
|
||||
wire inte;
|
||||
wire cmp_blank;
|
||||
wire cmp_sync;
|
||||
|
||||
video_timing timing(
|
||||
.clk_14m(clk_sys),
|
||||
.rst_n(rst_n),
|
||||
.ph1(ph1),
|
||||
.ph2(ph2),
|
||||
.cbclk(cbclk),
|
||||
.pix_a(pix_a),
|
||||
.vid_sel(vid_sel),
|
||||
.vid_addr(vid_a),
|
||||
.vid_sel_n(vid_sel_n),
|
||||
.nrr_n(nrr_n),
|
||||
.ce_n(ce_n),
|
||||
.pce(pce),
|
||||
.vid_ltc(vid_ltc),
|
||||
.ram_clk(ram_clk),
|
||||
.brst(brst),
|
||||
.tpclk(tpclk),
|
||||
.cmp_blank(cmp_blank),
|
||||
.irq(irq),
|
||||
.inte(inte),
|
||||
.cmp_sync(cmp_sync),
|
||||
.hblank_n(hblank_n),
|
||||
.vblank_n(vblank_n),
|
||||
.hsync_n(hsync_n),
|
||||
.vsync_n(vsync_n)
|
||||
);
|
||||
|
||||
/////////////////// CPU ///////////////////
|
||||
|
||||
wire [15:0] addr;
|
||||
reg [7:0] cpu_din;
|
||||
wire [7:0] cpu_dout;
|
||||
wire wr_n;
|
||||
wire ready;
|
||||
wire hold;
|
||||
wire rd;
|
||||
wire sync;
|
||||
wire vait;
|
||||
wire hlda;
|
||||
wire pin_aena;
|
||||
wire pin_dena;
|
||||
|
||||
assign hold = 1'b0;
|
||||
assign ready = 1'b1;
|
||||
|
||||
vm80a_core cpu(
|
||||
.pin_clk(clk_sys),
|
||||
.pin_f1(~ph2),
|
||||
.pin_f2(ph2),
|
||||
.pin_reset(~cpu_rst_n),
|
||||
.pin_a(addr),
|
||||
.pin_dout(cpu_dout),
|
||||
.pin_din(cpu_din),
|
||||
.pin_aena (pin_aena),
|
||||
.pin_dena (pin_dena),
|
||||
.pin_hold(hold),
|
||||
.pin_ready(ready),
|
||||
.pin_int(irq),
|
||||
.pin_wr_n(wr_n),
|
||||
.pin_dbin(rd),
|
||||
.pin_inte(inte),
|
||||
.pin_hlda(hlda),
|
||||
.pin_wait(vait),
|
||||
.pin_sync(sync)
|
||||
);
|
||||
|
||||
|
||||
//////// STATUS system control ////////////
|
||||
|
||||
reg[7:0] cpu_status;
|
||||
wire status_inta = cpu_status[0];
|
||||
//wire status_wo_n = cpu_status[1];
|
||||
//wire status_stack = cpu_status[2];
|
||||
//wire status_hlta = cpu_status[3];
|
||||
//wire status_out = cpu_status[4];
|
||||
//wire status_m1 = cpu_status[5];
|
||||
//wire status_inp = cpu_status[6];
|
||||
//wire status_memr = cpu_status[7];
|
||||
|
||||
always @(posedge clk_sys or negedge rst_n)
|
||||
begin
|
||||
reg old_sync;
|
||||
if (!rst_n)
|
||||
cpu_status <= 8'b0;
|
||||
else
|
||||
begin
|
||||
old_sync <= sync;
|
||||
if(~old_sync & sync)
|
||||
cpu_status <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
casez({status_inta, rom_e, ram_e, ~io_3800_r_n, ~io_3000_r_n})
|
||||
5'b1????: cpu_din <= 8'hFF;
|
||||
5'b00001: cpu_din <= io_rd_rtc_ad;
|
||||
5'b00010: cpu_din <= key_data;
|
||||
5'b00100: cpu_din <= ram_out;
|
||||
5'b01000: cpu_din <= rom_out;
|
||||
default: cpu_din <= 8'hFF;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
/////////////////// MEMORY ///////////////////
|
||||
// 1111110000000000
|
||||
// 5432109876543210
|
||||
// ROM A 0000H 0000000000000000
|
||||
// ROM B 0800H 0000100000000000
|
||||
// IO 10 1000H 0001000000000000
|
||||
// IO 18 1800H 0001100000000000
|
||||
// IO 20 2000H 0010000000000000
|
||||
// IO 28 2800H 0010100000000000
|
||||
// IO 30 3000H 0011000000000000
|
||||
// IO 38 3800H 0011100000000000
|
||||
// VRAM 4000H 0100000000000000
|
||||
// 49FFH 0100100111111111
|
||||
// RAM 4800H 0100101000000000
|
||||
|
||||
wire rom_e = ~addr[15] & ~addr[14] & ~addr[13] & ~addr[12] & ~addr[11];
|
||||
//wire rom_e = (addr[15:11] == 5'b00000) ? 1'b1 : 1'b0;
|
||||
wire [7:0] rom_out;
|
||||
|
||||
interact interact(
|
||||
.clk(clk_sys),
|
||||
.addr(addr[10:0]),
|
||||
.data(rom_out)
|
||||
);
|
||||
|
||||
//hector1 hector1(
|
||||
// .clk(clk_sys),
|
||||
// .addr(addr[11:0]),
|
||||
// .data(rom_out)
|
||||
//);
|
||||
|
||||
wire ram_e = ~addr[15] & addr[14];
|
||||
//wire ram_e = (addr[15:14] == 2'b01) ? 1'b1 : 1'b0;
|
||||
wire [7:0] ram_out;
|
||||
wire ram_w = ram_e & ~wr_n;
|
||||
wire [7:0] vid_out;
|
||||
|
||||
dpram #(.ADDRWIDTH(14)) ram(
|
||||
.clock(clk_sys),
|
||||
.address_a(addr[13:0]),
|
||||
.data_a(cpu_dout),
|
||||
.wren_a(ram_w),
|
||||
.q_a(ram_out),
|
||||
.address_b({2'b0, vid_a}),
|
||||
.q_b(vid_out)
|
||||
);
|
||||
|
||||
/////////////////// Memory Mapped IO Registers ///////////////////
|
||||
wire io_0000_r_n;//00_00 0_000 0000 0000
|
||||
wire io_0800_r_n;//00_00 1_000 0000 0000
|
||||
wire io_1000_r_n;//00_01 0_000 0000 0000
|
||||
wire io_1800_r_n;//00_01 1_000 0000 0000
|
||||
wire io_2000_r_n;//00_01 1_000 0000 0000
|
||||
wire io_2800_r_n;//00_10 0_000 0000 0000
|
||||
wire io_3000_r_n;//00_10 1_000 0000 0000
|
||||
wire io_3800_r_n;//00_11 1_000 0000 0000
|
||||
|
||||
always_comb//Fix GFX Glitches
|
||||
begin
|
||||
io_0000_r_n = 1'b1;
|
||||
io_0800_r_n = 1'b1;
|
||||
io_1000_r_n = 1'b1;
|
||||
io_1800_r_n = 1'b1;
|
||||
io_2000_r_n = 1'b1;
|
||||
io_2800_r_n = 1'b1;
|
||||
io_3000_r_n = 1'b1;
|
||||
io_3800_r_n = 1'b1;
|
||||
casez({rd,addr[13:11]})
|
||||
4'b1000 : io_0000_r_n = 1'b0;
|
||||
4'b1001 : io_0800_r_n = 1'b0;
|
||||
4'b1010 : io_1000_r_n = 1'b0;
|
||||
4'b1011 : io_1800_r_n = 1'b0;
|
||||
4'b1100 : io_2000_r_n = 1'b0;
|
||||
4'b1101 : io_2800_r_n = 1'b0;
|
||||
4'b1110 : io_3000_r_n = 1'b0;
|
||||
4'b1111 : io_3800_r_n = 1'b0;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
|
||||
wire io_0000_w_n;
|
||||
wire io_0800_w_n;
|
||||
wire io_1000_w_n;
|
||||
wire io_1800_w_n;
|
||||
wire io_2000_w_n;
|
||||
wire io_2800_w_n;
|
||||
wire io_3000_w_n;
|
||||
wire io_3800_w_n;
|
||||
|
||||
//always_comb//Brings GFX Glitches Back
|
||||
//begin
|
||||
// io_0000_w_n = 1'b1;
|
||||
// io_0800_w_n = 1'b1;
|
||||
// io_1000_w_n = 1'b1;
|
||||
// io_1800_w_n = 1'b1;
|
||||
// io_2000_w_n = 1'b1;
|
||||
// io_2800_w_n = 1'b1;
|
||||
// io_3000_w_n = 1'b1;
|
||||
// io_3800_w_n = 1'b1;
|
||||
// casez({~wr_n,addr[13:11]})
|
||||
// 4'b1000 : io_0000_w_n = 1'b0;
|
||||
// 4'b1001 : io_0800_w_n = 1'b0;
|
||||
// 4'b1010 : io_1000_w_n = 1'b0;
|
||||
// 4'b1011 : io_1800_w_n = 1'b0;
|
||||
// 4'b1100 : io_2000_w_n = 1'b0;
|
||||
// 4'b1101 : io_2800_w_n = 1'b0;
|
||||
// 4'b1110 : io_3000_w_n = 1'b0;
|
||||
// 4'b1111 : io_3800_w_n = 1'b0;
|
||||
// default: ;
|
||||
// endcase
|
||||
// end
|
||||
|
||||
//SN74LS138 IC25 (
|
||||
// .a(addr[11]),
|
||||
// .b(addr[12]),
|
||||
// .c(addr[13]),
|
||||
// .g1(rd),
|
||||
// .g2an(addr[15]),
|
||||
// .g2bn(addr[14]),
|
||||
// .y0n(io_0000_r_n),
|
||||
// .y1n(io_0800_r_n),
|
||||
// .y2n(io_1000_r_n),
|
||||
// .y3n(io_1800_r_n),
|
||||
// .y4n(io_2000_r_n),
|
||||
// .y5n(io_2800_r_n),
|
||||
// .y6n(io_3000_r_n),
|
||||
// .y7n(io_3800_r_n)
|
||||
//);
|
||||
|
||||
SN74LS138 IC26 (
|
||||
.a(addr[11]),
|
||||
.b(addr[12]),
|
||||
.c(addr[13]),
|
||||
.g1(~wr_n),
|
||||
.g2an(addr[15]),
|
||||
.g2bn(addr[14]),
|
||||
.y0n(io_0000_w_n),
|
||||
.y1n(io_0800_w_n),
|
||||
.y2n(io_1000_w_n),
|
||||
.y3n(io_1800_w_n),
|
||||
.y4n(io_2000_w_n),
|
||||
.y5n(io_2800_w_n),
|
||||
.y6n(io_3000_w_n),
|
||||
.y7n(io_3800_w_n)
|
||||
);
|
||||
|
||||
|
||||
wire [7:0] io_rd_rtc_ad;
|
||||
always_comb
|
||||
casez (io_wr_misc[7:3])
|
||||
5'b00111 : io_rd_rtc_ad = {tape_flux, rtc[6:0]};
|
||||
5'b10111 : io_rd_rtc_ad = rtc;
|
||||
5'b?1111 : io_rd_rtc_ad = {1'b0, rtc[6:0]};
|
||||
5'b??001 : io_rd_rtc_ad = joystick_0[4] ? 8'h00 : 8'h80;
|
||||
5'b??010 : io_rd_rtc_ad = {~joystick_analog_0[7], joystick_analog_0[6:0]};
|
||||
5'b??100 : io_rd_rtc_ad = joystick_1[4] ? 8'h00 : 8'h80;
|
||||
5'b??101 : io_rd_rtc_ad = {~joystick_analog_1[7], joystick_analog_1[6:0]};
|
||||
default: io_rd_rtc_ad = 8'h00;
|
||||
endcase
|
||||
|
||||
|
||||
wire rtc_clr = ~rst_n | io_wr_misc[6];
|
||||
reg [7:0] rtc;
|
||||
wire rtc_clk = io_wr_misc[6] ? 1'b0 : (io_wr_misc[7] ? pix_a : tpclk);
|
||||
|
||||
always@(negedge rtc_clk or posedge rtc_clr)
|
||||
begin
|
||||
if (rtc_clr)
|
||||
begin
|
||||
rtc <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rtc <= rtc + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
wire [7:0] keys [7:0];
|
||||
wire [7:0] key_data = keys[addr[3:0]];
|
||||
|
||||
keyboard keyboard
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
.rst_n(rst_n),
|
||||
.ps2_key(ps2_key),
|
||||
.joystick_0(joystick_0),
|
||||
.joystick_1(joystick_1),
|
||||
.keys(keys)
|
||||
);
|
||||
|
||||
|
||||
reg [7:0] io_wr_color_a_tape;
|
||||
reg [7:0] io_wr_color_b_snd;
|
||||
|
||||
reg [7:0] io_wr_sound_a [3:0];
|
||||
reg [7:0] io_wr_sound_b [3:0];
|
||||
|
||||
reg [7:0] io_wr_misc;
|
||||
|
||||
always@(posedge io_1000_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_color_a_tape <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_color_a_tape <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge io_1800_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_color_b_snd <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_color_b_snd <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge io_2000_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_sound_a[2'b00] <= 8'b0;
|
||||
io_wr_sound_a[2'b01] <= 8'b0;
|
||||
io_wr_sound_a[2'b10] <= 8'b0;
|
||||
io_wr_sound_a[2'b11] <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_sound_a[addr[1:0]] <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge io_2800_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_sound_b[2'b00] <= 8'b0;
|
||||
io_wr_sound_b[2'b01] <= 8'b0;
|
||||
io_wr_sound_b[2'b10] <= 8'b0;
|
||||
io_wr_sound_b[2'b11] <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_sound_b[addr[1:0]] <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge io_3000_w_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
io_wr_misc <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
io_wr_misc <= cpu_dout;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////// Video ///////////////////
|
||||
|
||||
|
||||
//// Test generator start
|
||||
|
||||
reg [7:0] vidtest_x;
|
||||
reg [7:0] vidtest_y;
|
||||
wire [6:0] vidtest_scanline = vid_a[11:5];
|
||||
|
||||
always@(posedge vid_ltc or negedge hblank_n)
|
||||
begin
|
||||
if (!hblank_n)
|
||||
vidtest_x <= 8'b0;
|
||||
else
|
||||
vidtest_x <= vidtest_x + 1'b1;
|
||||
end
|
||||
|
||||
always@(posedge hsync_n or negedge vblank_n)
|
||||
begin
|
||||
if (!vblank_n)
|
||||
vidtest_y <= 8'b0;
|
||||
else
|
||||
vidtest_y <= vidtest_y + 1'b1;
|
||||
end
|
||||
|
||||
//// Test generator end
|
||||
|
||||
|
||||
reg [7:0] pix_byte;
|
||||
wire pix_en = vid_sel & vid_ltc & ~(ce_n | pce);
|
||||
|
||||
always@(posedge pix_en or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
pix_byte <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
pix_byte <= vid_out;
|
||||
end
|
||||
end
|
||||
|
||||
reg [3:0] pix_nib;
|
||||
|
||||
always@(posedge vid_sel_n or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
pix_nib <= 4'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
pix_nib <= pix_byte[7:4];
|
||||
end
|
||||
end
|
||||
|
||||
wire [1:0] pix = vid_sel ? (pix_a ? pix_nib[3:2] : pix_nib[1:0]) : (pix_a ? pix_byte[3:2] : pix_byte[1:0]);
|
||||
|
||||
wire [2:0] cr [3:0];
|
||||
|
||||
assign cr[2'b00] = io_wr_color_a_tape[2:0];
|
||||
assign cr[2'b01] = io_wr_color_b_snd[2:0];
|
||||
assign cr[2'b10] = io_wr_color_a_tape[5:3];
|
||||
assign cr[2'b11] = io_wr_color_b_snd[5:3];
|
||||
|
||||
wire [2:0] color = cr[pix];
|
||||
wire color_intensity = (pix == 2'b10) ? io_wr_color_b_snd[6] : 1'b0;
|
||||
|
||||
wire test_pattern = test_sw;
|
||||
|
||||
always@(posedge vid_ltc or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
R <= 8'b0;
|
||||
G <= 8'b0;
|
||||
B <= 8'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (cmp_blank)
|
||||
begin
|
||||
R <= 8'b0;
|
||||
G <= 8'b0;
|
||||
B <= 8'b0;
|
||||
end
|
||||
else if (test_pattern & (vidtest_x === 8'd0))
|
||||
begin
|
||||
R <= 8'h00; //darkgreen
|
||||
G <= 8'h64;
|
||||
B <= 8'h00;
|
||||
end
|
||||
else if (test_pattern & (vidtest_x === 8'd110))
|
||||
begin
|
||||
R <= 8'h7c; //lawngreen
|
||||
G <= 8'hfc;
|
||||
B <= 8'h00;
|
||||
end
|
||||
else if (test_pattern & (vidtest_scanline === 7'd0))
|
||||
begin
|
||||
R <= 8'h8A; //blueviolet
|
||||
G <= 8'h2B;
|
||||
B <= 8'hE2;
|
||||
end
|
||||
else if (test_pattern & (vidtest_scanline === 7'd75))
|
||||
begin
|
||||
R <= 8'h1e; //dodgerblue
|
||||
G <= 8'h90;
|
||||
B <= 8'hff;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (color_intensity)
|
||||
begin
|
||||
if (test_pattern)
|
||||
begin
|
||||
R <= 8'h7c; //lawngreen
|
||||
G <= 8'hfc;
|
||||
B <= 8'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
R <= {1'b0, {7{color[0]}}};
|
||||
G <= {1'b0, {7{color[1]}}};
|
||||
B <= {1'b0, {7{color[2]}}};
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
R <= {8{color[0]}};
|
||||
G <= {8{color[1]}};
|
||||
B <= {8{color[2]}};
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//// Tape Loading
|
||||
|
||||
wire [15:0] tape_addr;
|
||||
wire [7:0] tape_data;
|
||||
reg [15:0] tape_end;
|
||||
|
||||
dpram #(.ADDRWIDTH(15)) tape// 16 reduced, lack of BRAM
|
||||
(
|
||||
.clock(clk_cas),
|
||||
.address_a(ioctl_addr),
|
||||
.data_a(ioctl_data),
|
||||
.wren_a(ioctl_wr),
|
||||
|
||||
.address_b(tape_addr),
|
||||
.q_b(tape_data)
|
||||
);
|
||||
|
||||
|
||||
always@(posedge clk_cas or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
tape_end <= 16'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (ioctl_download) tape_end <= ioctl_addr;
|
||||
end
|
||||
end
|
||||
|
||||
wire tape_flux;
|
||||
|
||||
cassette cassette(
|
||||
.clk(clk_sys),
|
||||
.rst_n(rst_n),
|
||||
.play(tape_play),
|
||||
.rewind(tape_rewind),
|
||||
.playing(tape_playing),
|
||||
.motor(io_wr_color_a_tape[6]),
|
||||
|
||||
.tape_addr(tape_addr),
|
||||
.tape_data(tape_data),
|
||||
.tape_end(tape_end),
|
||||
|
||||
.flux(tape_flux),
|
||||
.audio(audio)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
35
Computer_MiST/Interact_MiST/rtl/build_id.tcl
Normal file
35
Computer_MiST/Interact_MiST/rtl/build_id.tcl
Normal file
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
300
Computer_MiST/Interact_MiST/rtl/cassette.sv
Normal file
300
Computer_MiST/Interact_MiST/rtl/cassette.sv
Normal file
@@ -0,0 +1,300 @@
|
||||
//
|
||||
// Decoder for .CIN and K7 formats based on MAME/MESS hect_tap.cpp written by JJ Stacino
|
||||
//
|
||||
// See https://github.com/mamedev/mame/blob/master/src/lib/formats/hect_tap.cpp
|
||||
//
|
||||
// The .K7 format appears to be identical to the .CIN format used by the
|
||||
// Virtual Interact emulator created by "James The Animal Tamer"
|
||||
//
|
||||
// The Interact stores data on tape by using a "bit banged" machanism to drive square
|
||||
// waves of with periods of different duration for zero, one, and gap bits.
|
||||
//
|
||||
// At the start of the tape, a set of gap bits is read. A minimum of 356 gap bits
|
||||
// must be found. Following the initial gaps, the tape data is read.
|
||||
//
|
||||
// Data is orgaanized into records. Each record starts with a length byte followed
|
||||
// by up to 256 additional bytes.
|
||||
//
|
||||
// Records with a length of 5 are special command records. The last byte of the
|
||||
// command record is the command byte. A value of FE indicates a fill command
|
||||
// and the following record contains the data to use to fill. A value of FD
|
||||
// indicates end of file.
|
||||
//
|
||||
// At the end of the tape is a stop ID that consists of:
|
||||
// 0 - gap - 0 - gap
|
||||
//
|
||||
//
|
||||
|
||||
module cassette(
|
||||
input clk,
|
||||
input rst_n,
|
||||
input play,
|
||||
input rewind,
|
||||
input motor,
|
||||
|
||||
output reg [15:0] tape_addr,
|
||||
input [7:0] tape_data,
|
||||
input [15:0] tape_end,
|
||||
|
||||
output playing,
|
||||
output reg flux,
|
||||
output reg [15:0] audio
|
||||
);
|
||||
|
||||
localparam GAP_CLK = 14'd12500;
|
||||
localparam ZERO_CLK = 14'd4383;
|
||||
localparam ONE_CLK = 14'd8117;
|
||||
localparam HI = 16'h7FFF;
|
||||
localparam LO = 16'h8000;
|
||||
localparam START_GAP_DURATION = 10'd764;
|
||||
localparam RECORD_GAP_DURATION = 10'd4;
|
||||
localparam WAIT_GAP_DURATION = 10'd150;
|
||||
|
||||
parameter
|
||||
IDLE = 3'd0,
|
||||
START = 3'd1,
|
||||
START_RECORD = 3'd2,
|
||||
WRITE_RECORD_LENGTH = 3'd3,
|
||||
WRITE_RECORD_DATA = 3'd4,
|
||||
FINISH = 3'd5;
|
||||
|
||||
reg [2:0] state;
|
||||
reg wr_cycle;
|
||||
reg wr_gap;
|
||||
reg wr_byte;
|
||||
|
||||
reg [13:0] cycle_high_count;
|
||||
reg [13:0] cycle_low_count;
|
||||
|
||||
reg [9:0] gap_counter;
|
||||
|
||||
reg [7:0] byte_output;
|
||||
reg [7:0] byte_output_index;
|
||||
|
||||
reg [8:0] record_size;
|
||||
reg [7:0] previous_record;
|
||||
|
||||
reg prev_play;
|
||||
reg prev_rewind;
|
||||
reg prev_motor;
|
||||
|
||||
assign playing = state !== IDLE;
|
||||
|
||||
always @(posedge clk or negedge rst_n)
|
||||
begin
|
||||
if (!rst_n)
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, IDLE};
|
||||
|
||||
cycle_high_count <= 14'b0;
|
||||
cycle_low_count <= 14'b0;
|
||||
|
||||
gap_counter <= 10'b0;
|
||||
|
||||
byte_output <= 8'b0;
|
||||
byte_output_index <= 8'b0;
|
||||
|
||||
record_size <= 9'b0;
|
||||
previous_record <= 8'b0;
|
||||
|
||||
tape_addr <= 16'b0;
|
||||
audio <= 16'b0;
|
||||
flux <= 1'b0;
|
||||
|
||||
prev_play <= 1'b0;
|
||||
prev_rewind <= 1'b0;
|
||||
prev_motor <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
|
||||
casez ({wr_cycle, wr_gap, wr_byte, state})
|
||||
|
||||
{1'b1, 1'b?, 1'b?, 3'b???}:
|
||||
begin
|
||||
if (cycle_high_count)
|
||||
begin
|
||||
audio <= HI;
|
||||
//flux <= 1'b1;
|
||||
cycle_high_count <= cycle_high_count - 14'd1;
|
||||
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b1, wr_gap, wr_byte, state};
|
||||
end
|
||||
else if (cycle_low_count)
|
||||
begin
|
||||
audio <= LO;
|
||||
//flux <= 1'b0;
|
||||
cycle_low_count <= cycle_low_count - 14'd1;
|
||||
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b1, wr_gap, wr_byte, state};
|
||||
end
|
||||
else
|
||||
begin
|
||||
flux <= ~flux;
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, wr_gap, wr_byte, state};
|
||||
end
|
||||
end
|
||||
|
||||
{1'b0, 1'b1, 1'b0, 3'b???}:
|
||||
begin
|
||||
if (gap_counter)
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b1, 1'b1, 1'b0, state};
|
||||
|
||||
cycle_high_count <= GAP_CLK;
|
||||
cycle_low_count <= GAP_CLK;
|
||||
|
||||
gap_counter <= gap_counter - 10'd1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, state};
|
||||
end
|
||||
end
|
||||
|
||||
{1'b0, 1'b0, 1'b1, 3'b???}:
|
||||
begin
|
||||
if (byte_output_index)
|
||||
begin
|
||||
if (byte_output & byte_output_index)
|
||||
begin
|
||||
cycle_high_count <= ONE_CLK;
|
||||
cycle_low_count <= ONE_CLK;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cycle_high_count <= ZERO_CLK;
|
||||
cycle_low_count <= ZERO_CLK;
|
||||
end
|
||||
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b1, 1'b0, 1'b1, state};
|
||||
byte_output_index <= byte_output_index << 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, state};
|
||||
end
|
||||
end
|
||||
|
||||
{1'b0, 1'b0, 1'b0, IDLE}:
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, IDLE};
|
||||
|
||||
tape_addr <= 16'b0;
|
||||
audio <= 16'b0;
|
||||
flux <= 1'b0;
|
||||
previous_record <= 8'b0;
|
||||
end
|
||||
|
||||
{1'b0, 1'b0, 1'b0, START}:
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b1, 1'b0, START_RECORD};
|
||||
|
||||
tape_addr <= 16'b0;
|
||||
audio <= 16'b0;
|
||||
flux <= 1'b0;
|
||||
previous_record <= 8'b0;
|
||||
|
||||
gap_counter <= START_GAP_DURATION;
|
||||
end
|
||||
|
||||
{1'b0, 1'b0, 1'b0, START_RECORD}:
|
||||
begin
|
||||
if (tape_addr <= tape_end)
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b1, 1'b0, WRITE_RECORD_LENGTH};
|
||||
|
||||
if (previous_record === 8'hFE)
|
||||
gap_counter <= WAIT_GAP_DURATION;
|
||||
else
|
||||
gap_counter <= RECORD_GAP_DURATION;
|
||||
|
||||
previous_record <= byte_output;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state <= FINISH;
|
||||
end
|
||||
end
|
||||
|
||||
{1'b0, 1'b0, 1'b0, WRITE_RECORD_LENGTH}:
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b1, WRITE_RECORD_DATA};
|
||||
|
||||
byte_output <= tape_data;
|
||||
byte_output_index <= 8'b1;
|
||||
|
||||
record_size <= (tape_data == 8'd0 ? 9'd256 : {1'b0, tape_data});
|
||||
tape_addr <= tape_addr + 16'd1;
|
||||
|
||||
end
|
||||
|
||||
{1'b0, 1'b0, 1'b0, WRITE_RECORD_DATA}:
|
||||
begin
|
||||
if ((tape_addr <= tape_end) && (|record_size))
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b1, WRITE_RECORD_DATA};
|
||||
|
||||
byte_output <= tape_data;
|
||||
byte_output_index <= 8'b1;
|
||||
|
||||
tape_addr <= tape_addr + 16'd1;
|
||||
record_size <= record_size - 9'd1;
|
||||
end
|
||||
else if (tape_addr > tape_end)
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, FINISH};
|
||||
end
|
||||
else
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, START_RECORD};
|
||||
end
|
||||
end
|
||||
|
||||
{1'b0, 1'b0, 1'b0, FINISH}:
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b1, IDLE};
|
||||
|
||||
byte_output <= 8'b0;
|
||||
byte_output_index <= 8'b1;
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, IDLE};
|
||||
end
|
||||
|
||||
endcase
|
||||
|
||||
prev_play <= play;
|
||||
if (play && !prev_play)
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, START};
|
||||
end
|
||||
|
||||
prev_rewind <= rewind;
|
||||
if (rewind && !prev_rewind)
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, IDLE};
|
||||
end
|
||||
|
||||
// for enabling the tape to start under software control (color register A, bit 6)
|
||||
// for now, this will also rewind and restart tape from beginning, since that's
|
||||
// the likely preferred behavior for the user but many need to instead
|
||||
// create a pause and resume state to correctly emulate behavior
|
||||
prev_motor <= motor;
|
||||
if (motor && !prev_motor)
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, START};
|
||||
end
|
||||
else if (prev_motor && !motor)
|
||||
begin
|
||||
{wr_cycle, wr_gap, wr_byte, state} <= {1'b0, 1'b0, 1'b0, IDLE};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
72
Computer_MiST/Interact_MiST/rtl/dpram.v
Normal file
72
Computer_MiST/Interact_MiST/rtl/dpram.v
Normal file
@@ -0,0 +1,72 @@
|
||||
|
||||
module dpram #(parameter DATAWIDTH=8, ADDRWIDTH=8, NUMWORDS=1<<ADDRWIDTH, MEM_INIT_FILE="")
|
||||
(
|
||||
input clock,
|
||||
|
||||
input [ADDRWIDTH-1:0] address_a,
|
||||
input [DATAWIDTH-1:0] data_a,
|
||||
input wren_a,
|
||||
output [DATAWIDTH-1:0] q_a,
|
||||
|
||||
input [ADDRWIDTH-1:0] address_b,
|
||||
input [DATAWIDTH-1:0] data_b,
|
||||
input wren_b,
|
||||
output [DATAWIDTH-1:0] q_b
|
||||
);
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (address_a),
|
||||
.address_b (address_b),
|
||||
.clock0 (clock),
|
||||
.data_a (data_a),
|
||||
.data_b (data_b),
|
||||
.wren_a (wren_a),
|
||||
.wren_b (wren_b),
|
||||
.q_a (q_a),
|
||||
.q_b (q_b),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.eccstatus (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1));
|
||||
defparam
|
||||
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
|
||||
altsyncram_component.address_reg_b = "CLOCK0",
|
||||
altsyncram_component.indata_reg_b = "CLOCK0",
|
||||
altsyncram_component.numwords_a = NUMWORDS,
|
||||
altsyncram_component.numwords_b = NUMWORDS,
|
||||
altsyncram_component.widthad_a = ADDRWIDTH,
|
||||
altsyncram_component.widthad_b = ADDRWIDTH,
|
||||
altsyncram_component.width_a = DATAWIDTH,
|
||||
altsyncram_component.width_b = DATAWIDTH,
|
||||
altsyncram_component.width_byteena_a = 1,
|
||||
altsyncram_component.width_byteena_b = 1,
|
||||
|
||||
altsyncram_component.init_file = MEM_INIT_FILE,
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "UNREGISTERED",
|
||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
||||
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
|
||||
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ";
|
||||
|
||||
|
||||
endmodule
|
||||
261
Computer_MiST/Interact_MiST/rtl/keyboard.sv
Normal file
261
Computer_MiST/Interact_MiST/rtl/keyboard.sv
Normal file
@@ -0,0 +1,261 @@
|
||||
|
||||
module keyboard
|
||||
(
|
||||
input clk_sys,
|
||||
input rst_n,
|
||||
|
||||
input [10:0] ps2_key,
|
||||
|
||||
input [3:0] joystick_0,
|
||||
input [3:0] joystick_1,
|
||||
|
||||
output reg [7:0] keys [7:0]
|
||||
);
|
||||
|
||||
reg release_btn = 0;
|
||||
reg [7:0] code;
|
||||
reg shift = 0;
|
||||
|
||||
reg input_strobe = 0;
|
||||
|
||||
always @(posedge clk_sys or negedge rst_n) begin
|
||||
|
||||
if (!rst_n)
|
||||
begin
|
||||
keys[0] <= 8'b11111111;
|
||||
keys[1] <= 8'b11111111;
|
||||
keys[2] <= 8'b11111111;
|
||||
keys[3] <= 8'b11111111;
|
||||
keys[4] <= 8'b11111111;
|
||||
keys[5] <= 8'b11111111;
|
||||
keys[6] <= 8'b11111111;
|
||||
keys[7] <= 8'b11111111;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// unused or unmapped keys
|
||||
keys[2][0] = 1'b1;
|
||||
keys[3][2] = 1'b1;
|
||||
keys[3][4] = 1'b1;
|
||||
keys[3][6] = 1'b1;
|
||||
keys[7][4] = 1'b1;
|
||||
keys[7][5] = 1'b1;
|
||||
keys[7][6] = 1'b1;
|
||||
keys[7][7] = 1'b1;
|
||||
|
||||
if (input_strobe)
|
||||
case(code)
|
||||
|
||||
// @ 3800H
|
||||
|
||||
8'h3e : // 8
|
||||
if (shift == 1)
|
||||
begin
|
||||
keys[0][0] <= release_btn; // *
|
||||
keys[0][7] <= 1'b1; // unshift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[2][2] <= release_btn; // 8
|
||||
keys[0][7] <= 1'b1; // unshift
|
||||
end
|
||||
8'h29 : keys[0][1] <= release_btn; // SPACE
|
||||
8'h5a : keys[0][2] <= release_btn; // ENTER
|
||||
8'h0d : keys[0][3] <= release_btn; // TAB
|
||||
8'h66 : keys[0][4] <= release_btn; // BACKSPACE
|
||||
8'h58 : keys[0][5] <= release_btn; // CAPS
|
||||
8'h14 : keys[0][6] <= release_btn; // CONTROL
|
||||
8'h12 :
|
||||
begin
|
||||
keys[0][7] <= release_btn; // Left shift
|
||||
shift <= ~release_btn;
|
||||
end
|
||||
8'h59 :
|
||||
begin
|
||||
keys[0][7] <= release_btn; // Right shift
|
||||
shift <= ~release_btn;
|
||||
end
|
||||
8'h1e : keys[1][0] <= release_btn; // 2
|
||||
8'h52 : // "
|
||||
if (shift == 1)
|
||||
begin
|
||||
keys[1][0] <= release_btn; // 2
|
||||
keys[0][7] <= 1'b0; // shift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[3][7] <= release_btn; // 3
|
||||
keys[0][7] <= 1'b0; // shift
|
||||
end
|
||||
|
||||
// @ 3801H
|
||||
|
||||
8'h16 : // 1
|
||||
if (shift == 1)
|
||||
begin // !
|
||||
keys[2][4] <= release_btn; // 6
|
||||
keys[0][7] <= 1'b0; // shift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[1][1] <= release_btn; // 1
|
||||
end
|
||||
8'h45 : // 0
|
||||
if (shift == 1)
|
||||
begin
|
||||
keys[2][1] <= release_btn; // 9
|
||||
keys[0][7] <= 1'b0; // shift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[1][2] <= release_btn; // 0
|
||||
end
|
||||
8'h4a : // /
|
||||
if (shift == 1)
|
||||
begin // ?
|
||||
keys[3][3] <= release_btn; // ?
|
||||
keys[0][7] <= 1'b1; // unshift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[1][3] <= release_btn; // /
|
||||
end
|
||||
8'h49 : // .
|
||||
if (shift == 1)
|
||||
begin // >
|
||||
keys[1][1] <= release_btn; // 1
|
||||
keys[0][7] <= 1'b0; // shift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[1][4] <= release_btn; // .
|
||||
end
|
||||
8'h4e : keys[1][5] <= release_btn; // -
|
||||
8'h41 : // ,
|
||||
if (shift == 1)
|
||||
begin // <
|
||||
keys[1][2] <= release_btn; // 0
|
||||
keys[0][7] <= 1'b0; // shift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[1][6] <= release_btn; // ,
|
||||
end
|
||||
8'h55 : // =
|
||||
if (shift == 1)
|
||||
begin
|
||||
keys[1][7] <= release_btn; // +
|
||||
keys[0][7] <= 1'b1; // unshift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[3][5] <= release_btn; // =
|
||||
end
|
||||
|
||||
// @ 3802H
|
||||
|
||||
8'h46 : // 9
|
||||
if (shift == 1)
|
||||
begin
|
||||
keys[2][2] <= release_btn; // 8
|
||||
keys[0][7] <= 1'b0; // shift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[2][1] <= release_btn; // 9
|
||||
end
|
||||
8'h3d : keys[2][3] <= release_btn; // 7
|
||||
8'h36 : // 6
|
||||
if (shift == 1)
|
||||
begin
|
||||
keys[1][7] <= release_btn; // +
|
||||
keys[0][7] <= 1'b0; // shift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[2][4] <= release_btn; // 6
|
||||
end
|
||||
8'h2e : keys[2][5] <= release_btn; // 5
|
||||
8'h25 : keys[2][6] <= release_btn; // 4
|
||||
8'h26 : keys[2][7] <= release_btn; // 3
|
||||
|
||||
// @ 3803H
|
||||
|
||||
8'h32 : keys[3][0] <= release_btn; // B
|
||||
8'h1c : keys[3][1] <= release_btn; // A
|
||||
8'h4c : // ;
|
||||
if (shift == 1)
|
||||
begin
|
||||
keys[2][3] <= release_btn; // :, shift-7
|
||||
keys[0][7] <= 1'b1; // shift
|
||||
end
|
||||
else
|
||||
begin
|
||||
keys[3][7] <= release_btn; // ;
|
||||
keys[0][7] <= 1'b1; // unshift
|
||||
end
|
||||
|
||||
// @ 3804H
|
||||
|
||||
8'h3b : keys[4][0] <= release_btn; // J
|
||||
8'h43 : keys[4][1] <= release_btn; // I
|
||||
8'h33 : keys[4][2] <= release_btn; // H
|
||||
8'h34 : keys[4][3] <= release_btn; // G
|
||||
8'h2b : keys[4][4] <= release_btn; // F
|
||||
8'h24 : keys[4][5] <= release_btn; // E
|
||||
8'h23 : keys[4][6] <= release_btn; // D
|
||||
8'h21 : keys[4][7] <= release_btn; // C
|
||||
|
||||
// @ 3805H
|
||||
|
||||
8'h2d : keys[5][0] <= release_btn; // R
|
||||
8'h15 : keys[5][1] <= release_btn; // Q
|
||||
8'h4d : keys[5][2] <= release_btn; // P
|
||||
8'h44 : keys[5][3] <= release_btn; // O
|
||||
8'h31 : keys[5][4] <= release_btn; // N
|
||||
8'h3a : keys[5][5] <= release_btn; // M
|
||||
8'h4b : keys[5][6] <= release_btn; // L
|
||||
8'h42 : keys[5][7] <= release_btn; // K
|
||||
|
||||
// @ 3806H
|
||||
|
||||
8'h1a : keys[6][0] <= release_btn; // Z
|
||||
8'h35 : keys[6][1] <= release_btn; // Y
|
||||
8'h22 : keys[6][2] <= release_btn; // X
|
||||
8'h1d : keys[6][3] <= release_btn; // W
|
||||
8'h2a : keys[6][4] <= release_btn; // V
|
||||
8'h3c : keys[6][5] <= release_btn; // U
|
||||
8'h2c : keys[6][6] <= release_btn; // T
|
||||
8'h1b : keys[6][7] <= release_btn; // S
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
|
||||
// @ 3807H
|
||||
|
||||
keys[7][0] <= ~joystick_0[1]; // left
|
||||
keys[7][1] <= ~joystick_0[0]; // right
|
||||
keys[7][2] <= ~joystick_0[3]; // up
|
||||
keys[7][3] <= ~joystick_0[2]; // down
|
||||
keys[7][4] <= ~joystick_1[1]; // left
|
||||
keys[7][5] <= ~joystick_1[0]; // right
|
||||
keys[7][6] <= ~joystick_1[3]; // up
|
||||
keys[7][7] <= ~joystick_1[2]; // down
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg old_state;
|
||||
|
||||
input_strobe <= 0;
|
||||
old_state <= ps2_key[10];
|
||||
|
||||
if (old_state != ps2_key[10]) begin
|
||||
release_btn <= ~ps2_key[9];
|
||||
code <= ps2_key[7:0];
|
||||
input_strobe <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
4
Computer_MiST/Interact_MiST/rtl/pll.qip
Normal file
4
Computer_MiST/Interact_MiST/rtl/pll.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
348
Computer_MiST/Interact_MiST/rtl/pll.v
Normal file
348
Computer_MiST/Interact_MiST/rtl/pll.v
Normal file
@@ -0,0 +1,348 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
areset,
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
|
||||
input areset;
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.inclk (sub_wire5),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 33,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 70,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 66,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 35,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "66"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "57.272728"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "14.318182"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "70"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "35"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.27272700"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "14.31818100"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "70"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "66"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "35"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
278
Computer_MiST/Interact_MiST/rtl/rom/hector1.vhd
Normal file
278
Computer_MiST/Interact_MiST/rtl/rom/hector1.vhd
Normal file
@@ -0,0 +1,278 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity hector1 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(11 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of hector1 is
|
||||
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"3E",X"40",X"32",X"02",X"28",X"C3",X"0C",X"00",X"F3",X"C3",X"04",X"08",X"3E",X"38",X"32",X"00",
|
||||
X"30",X"AF",X"32",X"00",X"10",X"32",X"00",X"18",X"06",X"3E",X"21",X"C0",X"5F",X"F9",X"77",X"23",
|
||||
X"05",X"C2",X"1E",X"00",X"3A",X"00",X"08",X"B7",X"CA",X"00",X"08",X"3A",X"00",X"30",X"77",X"3E",
|
||||
X"80",X"32",X"DB",X"5F",X"C3",X"8C",X"01",X"FF",X"E5",X"D5",X"C5",X"F5",X"3A",X"F5",X"5F",X"B7",
|
||||
X"C2",X"6A",X"00",X"21",X"C0",X"5F",X"7E",X"1F",X"1F",X"1F",X"E6",X"07",X"F5",X"11",X"F6",X"5F",
|
||||
X"83",X"5F",X"3A",X"00",X"30",X"12",X"F1",X"3D",X"C2",X"5D",X"00",X"3E",X"06",X"87",X"87",X"87",
|
||||
X"AE",X"E6",X"F8",X"AE",X"F6",X"40",X"77",X"32",X"00",X"30",X"2A",X"EF",X"5F",X"23",X"22",X"EF",
|
||||
X"5F",X"11",X"06",X"38",X"21",X"C8",X"5F",X"01",X"CF",X"5F",X"1A",X"2F",X"A6",X"C2",X"89",X"00",
|
||||
X"2B",X"0B",X"1D",X"F2",X"7A",X"00",X"C3",X"24",X"01",X"F5",X"0A",X"2F",X"E3",X"A4",X"E1",X"CA",
|
||||
X"80",X"00",X"11",X"02",X"07",X"F5",X"21",X"C9",X"5F",X"7E",X"87",X"D2",X"9F",X"00",X"1D",X"C2",
|
||||
X"9A",X"00",X"23",X"15",X"C2",X"99",X"00",X"F1",X"1D",X"FA",X"24",X"01",X"16",X"08",X"0F",X"D2",
|
||||
X"B5",X"00",X"5A",X"3E",X"80",X"15",X"C2",X"AE",X"00",X"57",X"0A",X"B2",X"02",X"79",X"D6",X"C9",
|
||||
X"87",X"87",X"87",X"83",X"3D",X"FE",X"02",X"21",X"D2",X"5F",X"C2",X"D3",X"00",X"7E",X"2F",X"77",
|
||||
X"C3",X"24",X"01",X"FE",X"07",X"DA",X"E9",X"00",X"57",X"3A",X"00",X"38",X"2F",X"E6",X"80",X"B6",
|
||||
X"7A",X"CA",X"F5",X"00",X"FE",X"17",X"D2",X"F0",X"00",X"21",X"75",X"01",X"85",X"6F",X"7E",X"11",
|
||||
X"C6",X"23",X"C3",X"03",X"01",X"C6",X"23",X"FE",X"41",X"DA",X"03",X"01",X"FE",X"5B",X"D2",X"03",
|
||||
X"01",X"C6",X"20",X"57",X"3A",X"00",X"38",X"E6",X"C0",X"EE",X"80",X"7A",X"C2",X"16",X"01",X"FE",
|
||||
X"60",X"DA",X"16",X"01",X"D6",X"60",X"32",X"D1",X"5F",X"21",X"D0",X"5F",X"7E",X"B7",X"CA",X"23",
|
||||
X"01",X"36",X"80",X"34",X"01",X"00",X"38",X"11",X"C2",X"5F",X"21",X"C9",X"5F",X"0A",X"F6",X"C0",
|
||||
X"FE",X"0A",X"2F",X"12",X"A6",X"77",X"03",X"13",X"23",X"3E",X"07",X"B9",X"C2",X"31",X"01",X"21",
|
||||
X"C1",X"5F",X"46",X"3A",X"07",X"38",X"2F",X"77",X"A0",X"47",X"1F",X"1F",X"1F",X"1F",X"E6",X"0F",
|
||||
X"21",X"F2",X"5F",X"77",X"2B",X"78",X"E6",X"0F",X"77",X"3A",X"F5",X"5F",X"B7",X"C2",X"6A",X"01",
|
||||
X"21",X"C0",X"5F",X"7E",X"EE",X"C0",X"77",X"32",X"00",X"30",X"2A",X"F3",X"5F",X"7D",X"B4",X"E5",
|
||||
X"C0",X"E1",X"F1",X"C1",X"D1",X"E1",X"FB",X"C9",X"08",X"09",X"0D",X"20",X"2A",X"5E",X"23",X"5F",
|
||||
X"26",X"40",X"3C",X"3E",X"22",X"27",X"24",X"25",X"21",X"3A",X"28",X"29",X"FB",X"CD",X"73",X"05",
|
||||
X"01",X"E8",X"01",X"CD",X"D3",X"01",X"3A",X"00",X"4C",X"FE",X"31",X"F5",X"03",X"01",X"EB",X"0F",
|
||||
X"CC",X"D3",X"01",X"01",X"17",X"02",X"CD",X"36",X"06",X"CD",X"E0",X"07",X"47",X"F1",X"78",X"20",
|
||||
X"05",X"FE",X"72",X"CA",X"00",X"4C",X"D6",X"6D",X"CA",X"57",X"08",X"3C",X"20",X"D8",X"01",X"01",
|
||||
X"01",X"11",X"00",X"00",X"CD",X"1C",X"02",X"B7",X"20",X"08",X"3A",X"00",X"4C",X"FE",X"31",X"CA",
|
||||
X"00",X"4C",X"C7",X"0A",X"FE",X"FF",X"C8",X"CD",X"2F",X"06",X"03",X"0A",X"5F",X"03",X"0A",X"57",
|
||||
X"03",X"CD",X"4F",X"05",X"03",X"C3",X"D3",X"01",X"03",X"0C",X"0A",X"54",X"41",X"50",X"45",X"5A",
|
||||
X"00",X"02",X"1C",X"0A",X"4C",X"3A",X"4C",X"45",X"43",X"54",X"55",X"52",X"45",X"20",X"4B",X"37",
|
||||
X"00",X"02",X"26",X"0A",X"4D",X"3A",X"4D",X"4F",X"4E",X"49",X"54",X"45",X"55",X"52",X"00",X"FF",
|
||||
X"4C",X"41",X"4E",X"43",X"45",X"00",X"FF",X"04",X"01",X"02",X"07",X"00",X"F3",X"AF",X"32",X"D3",
|
||||
X"5F",X"D5",X"C5",X"CD",X"CA",X"02",X"CD",X"DD",X"02",X"01",X"1D",X"00",X"CD",X"F6",X"07",X"01",
|
||||
X"64",X"01",X"1E",X"00",X"CD",X"B1",X"03",X"C1",X"C5",X"01",X"05",X"00",X"11",X"D4",X"5F",X"CD",
|
||||
X"1A",X"03",X"C1",X"B7",X"CA",X"5D",X"02",X"32",X"D3",X"5F",X"78",X"B7",X"C2",X"38",X"02",X"D1",
|
||||
X"7A",X"B7",X"C2",X"58",X"02",X"CD",X"E3",X"02",X"3A",X"D3",X"5F",X"FB",X"C9",X"C5",X"2A",X"DD",
|
||||
X"5F",X"7C",X"B5",X"CA",X"6F",X"02",X"22",X"D4",X"5F",X"2A",X"DF",X"5F",X"22",X"D6",X"5F",X"3A",
|
||||
X"D8",X"5F",X"FE",X"FD",X"C2",X"7B",X"02",X"C1",X"C3",X"4F",X"02",X"FE",X"FE",X"C2",X"AE",X"02",
|
||||
X"21",X"D9",X"5F",X"01",X"01",X"00",X"CD",X"1A",X"03",X"C1",X"B7",X"CA",X"99",X"02",X"32",X"D3",
|
||||
X"5F",X"78",X"B7",X"C2",X"38",X"02",X"C3",X"4F",X"02",X"2A",X"D6",X"5F",X"EB",X"2A",X"D4",X"5F",
|
||||
X"3A",X"D9",X"5F",X"77",X"23",X"1B",X"7A",X"B3",X"C2",X"A0",X"02",X"C3",X"38",X"02",X"2A",X"D4",
|
||||
X"5F",X"EB",X"2A",X"D6",X"5F",X"44",X"4D",X"CD",X"00",X"03",X"C1",X"B7",X"CA",X"38",X"02",X"32",
|
||||
X"D3",X"5F",X"78",X"B7",X"C2",X"38",X"02",X"C3",X"4F",X"02",X"0F",X"2F",X"E6",X"40",X"32",X"02",
|
||||
X"28",X"3A",X"C0",X"5F",X"F6",X"07",X"32",X"C0",X"5F",X"32",X"00",X"30",X"C9",X"F5",X"3E",X"FF",
|
||||
X"C3",X"E5",X"02",X"F5",X"AF",X"E5",X"21",X"DB",X"5F",X"AE",X"E6",X"40",X"AE",X"77",X"32",X"00",
|
||||
X"10",X"21",X"C0",X"5F",X"7E",X"E6",X"07",X"F6",X"38",X"77",X"32",X"00",X"30",X"E1",X"F1",X"C9",
|
||||
X"E5",X"CD",X"DD",X"02",X"AF",X"32",X"D3",X"5F",X"CD",X"1A",X"03",X"21",X"D3",X"5F",X"B6",X"77",
|
||||
X"78",X"B1",X"C2",X"08",X"03",X"E1",X"3A",X"D3",X"5F",X"C9",X"E5",X"C5",X"CD",X"4F",X"03",X"C1",
|
||||
X"67",X"D2",X"36",X"03",X"6F",X"7B",X"84",X"5F",X"7A",X"CE",X"00",X"57",X"79",X"94",X"4F",X"7A",
|
||||
X"DE",X"00",X"47",X"7D",X"E1",X"C9",X"CD",X"9A",X"03",X"DA",X"24",X"03",X"12",X"13",X"0B",X"25",
|
||||
X"CA",X"4C",X"03",X"78",X"B1",X"C2",X"36",X"03",X"3E",X"04",X"E1",X"C9",X"E1",X"AF",X"C9",X"CD",
|
||||
X"D0",X"03",X"FE",X"15",X"DA",X"4F",X"03",X"CD",X"D0",X"03",X"FE",X"21",X"D2",X"4F",X"03",X"FE",
|
||||
X"15",X"D2",X"57",X"03",X"C5",X"FE",X"0E",X"3F",X"0E",X"80",X"DA",X"A8",X"03",X"CD",X"D0",X"03",
|
||||
X"FE",X"21",X"D2",X"95",X"03",X"FE",X"15",X"0E",X"40",X"DA",X"A5",X"03",X"CD",X"D0",X"03",X"FE",
|
||||
X"0E",X"D2",X"95",X"03",X"CD",X"D0",X"03",X"FE",X"21",X"D2",X"95",X"03",X"FE",X"15",X"DA",X"95",
|
||||
X"03",X"00",X"3E",X"01",X"01",X"3E",X"02",X"C1",X"37",X"C9",X"C5",X"0E",X"80",X"CD",X"D0",X"03",
|
||||
X"FE",X"15",X"D2",X"95",X"03",X"FE",X"0E",X"3F",X"79",X"1F",X"4F",X"D2",X"9D",X"03",X"B7",X"C1",
|
||||
X"C9",X"C5",X"CD",X"D0",X"03",X"FE",X"21",X"D2",X"CC",X"03",X"FE",X"15",X"DA",X"CC",X"03",X"0B",
|
||||
X"78",X"B1",X"C2",X"B2",X"03",X"7B",X"B7",X"C4",X"CA",X"02",X"C1",X"C9",X"C1",X"C3",X"B1",X"03",
|
||||
X"E5",X"2A",X"DA",X"5F",X"3A",X"00",X"30",X"AD",X"F2",X"D4",X"03",X"AD",X"32",X"DA",X"5F",X"95",
|
||||
X"E1",X"E6",X"7F",X"C9",X"C5",X"06",X"08",X"79",X"0F",X"4F",X"9F",X"E6",X"08",X"C6",X"08",X"CD",
|
||||
X"F8",X"03",X"05",X"C2",X"E7",X"03",X"C1",X"C9",X"D6",X"02",X"CD",X"FF",X"03",X"3E",X"02",X"E5",
|
||||
X"2A",X"DA",X"5F",X"85",X"E6",X"7F",X"6F",X"3A",X"00",X"30",X"E6",X"7F",X"BD",X"C2",X"07",X"04",
|
||||
X"7C",X"EE",X"80",X"32",X"00",X"10",X"67",X"22",X"DA",X"5F",X"E1",X"C9",X"3A",X"00",X"30",X"E6",
|
||||
X"7F",X"32",X"DA",X"5F",X"78",X"B1",X"C8",X"3E",X"1B",X"CD",X"F8",X"03",X"0B",X"C3",X"24",X"04",
|
||||
X"CD",X"33",X"04",X"3E",X"08",X"CD",X"F8",X"03",X"01",X"01",X"00",X"C3",X"24",X"04",X"79",X"B7",
|
||||
X"C8",X"E5",X"D5",X"57",X"2A",X"E1",X"5F",X"7C",X"B5",X"C2",X"4F",X"04",X"21",X"7A",X"06",X"7A",
|
||||
X"FE",X"61",X"DA",X"5A",X"04",X"D6",X"43",X"C3",X"6F",X"04",X"FE",X"1E",X"3D",X"DA",X"6F",X"04",
|
||||
X"D6",X"1D",X"57",X"2A",X"E3",X"5F",X"7C",X"B5",X"7A",X"C2",X"6F",X"04",X"21",X"6E",X"06",X"5E",
|
||||
X"23",X"56",X"23",X"E5",X"D5",X"CD",X"18",X"05",X"D1",X"7A",X"C6",X"07",X"1F",X"1F",X"1F",X"E6",
|
||||
X"1F",X"EB",X"E3",X"CD",X"1D",X"05",X"22",X"E5",X"5F",X"E1",X"D1",X"D5",X"C5",X"01",X"00",X"00",
|
||||
X"CD",X"9D",X"04",X"C1",X"D1",X"E1",X"C9",X"CD",X"F7",X"05",X"CD",X"B3",X"05",X"E5",X"21",X"DB",
|
||||
X"04",X"22",X"EB",X"5F",X"E1",X"7C",X"B7",X"C8",X"7D",X"B7",X"C8",X"C5",X"D5",X"E5",X"22",X"E9",
|
||||
X"5F",X"E5",X"C5",X"D5",X"E5",X"2A",X"EB",X"5F",X"CD",X"DA",X"04",X"E1",X"D1",X"C1",X"0C",X"1C",
|
||||
X"2D",X"C2",X"B2",X"04",X"E3",X"7D",X"E3",X"6F",X"79",X"95",X"4F",X"7B",X"95",X"5F",X"04",X"14",
|
||||
X"25",X"C2",X"B2",X"04",X"E1",X"E1",X"D1",X"C1",X"37",X"C9",X"E9",X"CD",X"ED",X"04",X"C8",X"3A",
|
||||
X"EE",X"5F",X"4F",X"CD",X"2D",X"05",X"47",X"79",X"AE",X"A0",X"AE",X"77",X"C9",X"3A",X"EA",X"5F",
|
||||
X"C6",X"07",X"1F",X"1F",X"1F",X"E6",X"1F",X"D5",X"59",X"16",X"00",X"2A",X"E5",X"5F",X"CD",X"1D",
|
||||
X"05",X"78",X"1F",X"1F",X"1F",X"E6",X"1F",X"5F",X"16",X"00",X"19",X"78",X"E6",X"07",X"5F",X"7E",
|
||||
X"87",X"1D",X"F2",X"10",X"05",X"9F",X"D1",X"C9",X"16",X"00",X"21",X"00",X"00",X"D5",X"B7",X"1F",
|
||||
X"D2",X"24",X"05",X"19",X"EB",X"29",X"EB",X"B7",X"C2",X"1F",X"05",X"D1",X"C9",X"6B",X"26",X"00",
|
||||
X"29",X"29",X"29",X"29",X"29",X"7A",X"1F",X"1F",X"E6",X"3F",X"B5",X"6F",X"7A",X"EB",X"E6",X"03",
|
||||
X"21",X"4B",X"05",X"85",X"6F",X"7E",X"2A",X"E7",X"5F",X"19",X"C9",X"03",X"0C",X"30",X"C0",X"CD",
|
||||
X"F7",X"05",X"0A",X"CD",X"5C",X"05",X"D0",X"03",X"C3",X"52",X"05",X"79",X"CD",X"3F",X"04",X"D0",
|
||||
X"3A",X"EA",X"5F",X"3C",X"82",X"FE",X"67",X"57",X"D8",X"3A",X"E9",X"5F",X"3C",X"83",X"5F",X"16",
|
||||
X"06",X"37",X"C9",X"0E",X"00",X"E5",X"D5",X"79",X"CD",X"E8",X"05",X"4F",X"21",X"00",X"40",X"11",
|
||||
X"A0",X"09",X"71",X"23",X"1B",X"7A",X"B3",X"C2",X"82",X"05",X"D1",X"E1",X"C9",X"CD",X"F7",X"05",
|
||||
X"21",X"D2",X"05",X"22",X"EB",X"5F",X"CD",X"B3",X"05",X"CD",X"E8",X"05",X"32",X"ED",X"5F",X"C3",
|
||||
X"A5",X"04",X"CD",X"F7",X"05",X"21",X"DF",X"04",X"22",X"EB",X"5F",X"60",X"69",X"CD",X"BE",X"05",
|
||||
X"C3",X"A5",X"04",X"60",X"69",X"5E",X"23",X"56",X"23",X"EB",X"22",X"E5",X"5F",X"EB",X"5E",X"23",
|
||||
X"56",X"23",X"D5",X"7E",X"23",X"CD",X"2F",X"06",X"5E",X"23",X"56",X"23",X"7E",X"E1",X"01",X"00",
|
||||
X"00",X"C9",X"CD",X"ED",X"04",X"C8",X"CD",X"2D",X"05",X"47",X"A6",X"4F",X"3A",X"EE",X"5F",X"A0",
|
||||
X"B9",X"C0",X"3A",X"ED",X"5F",X"C3",X"E8",X"04",X"E6",X"03",X"C5",X"4F",X"87",X"87",X"81",X"87",
|
||||
X"87",X"81",X"87",X"87",X"81",X"C1",X"C9",X"E5",X"21",X"00",X"40",X"22",X"E7",X"5F",X"E1",X"C9",
|
||||
X"E5",X"D5",X"C5",X"CD",X"F7",X"05",X"79",X"CD",X"E8",X"05",X"CD",X"E2",X"04",X"C1",X"D1",X"E1",
|
||||
X"CD",X"F7",X"05",X"E5",X"D5",X"C5",X"50",X"59",X"78",X"E6",X"03",X"47",X"CD",X"2D",X"05",X"7E",
|
||||
X"0F",X"0F",X"05",X"F2",X"20",X"06",X"07",X"07",X"E6",X"03",X"C1",X"D1",X"E1",X"C9",X"79",X"CD",
|
||||
X"E8",X"05",X"32",X"EE",X"5F",X"C9",X"D5",X"3A",X"DB",X"5F",X"E6",X"C0",X"CD",X"5E",X"06",X"32",
|
||||
X"00",X"10",X"32",X"DB",X"5F",X"0B",X"3A",X"DC",X"5F",X"E6",X"80",X"CD",X"5E",X"06",X"57",X"03",
|
||||
X"0A",X"0F",X"0F",X"E6",X"40",X"B2",X"32",X"00",X"18",X"32",X"DC",X"5F",X"D1",X"C9",X"57",X"0A",
|
||||
X"03",X"E6",X"07",X"B2",X"57",X"03",X"0A",X"E6",X"07",X"17",X"17",X"17",X"B2",X"C9",X"05",X"05",
|
||||
X"00",X"50",X"20",X"50",X"00",X"C0",X"60",X"30",X"60",X"C0",X"00",X"00",X"00",X"00",X"00",X"20",
|
||||
X"20",X"20",X"00",X"20",X"50",X"50",X"00",X"00",X"00",X"50",X"F8",X"50",X"F8",X"50",X"70",X"A0",
|
||||
X"70",X"28",X"70",X"C8",X"D0",X"20",X"58",X"98",X"20",X"50",X"20",X"50",X"28",X"20",X"40",X"00",
|
||||
X"00",X"00",X"20",X"40",X"40",X"40",X"20",X"20",X"10",X"10",X"10",X"20",X"A8",X"70",X"F8",X"70",
|
||||
X"A8",X"00",X"20",X"70",X"20",X"00",X"00",X"00",X"00",X"20",X"40",X"00",X"00",X"70",X"00",X"00",
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||||
X"00",X"00",X"00",X"00",X"20",X"08",X"10",X"20",X"40",X"80",X"70",X"88",X"88",X"88",X"70",X"20",
|
||||
X"60",X"20",X"20",X"70",X"F8",X"08",X"F8",X"80",X"F8",X"F8",X"08",X"38",X"08",X"F8",X"90",X"90",
|
||||
X"F8",X"10",X"10",X"F0",X"80",X"F0",X"08",X"F0",X"F8",X"80",X"F8",X"88",X"F8",X"F8",X"08",X"10",
|
||||
X"20",X"20",X"F8",X"88",X"F8",X"88",X"F8",X"F8",X"88",X"F8",X"08",X"F8",X"00",X"20",X"00",X"20",
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||||
X"00",X"00",X"20",X"00",X"20",X"40",X"10",X"20",X"40",X"20",X"10",X"00",X"70",X"00",X"70",X"00",
|
||||
X"40",X"20",X"10",X"20",X"40",X"F8",X"88",X"38",X"00",X"20",X"30",X"48",X"50",X"40",X"38",X"70",
|
||||
X"88",X"F8",X"88",X"88",X"F8",X"88",X"F0",X"88",X"F8",X"F8",X"80",X"80",X"80",X"F8",X"F0",X"88",
|
||||
X"88",X"88",X"F0",X"F8",X"80",X"E0",X"80",X"F8",X"F8",X"80",X"E0",X"80",X"80",X"F8",X"80",X"98",
|
||||
X"88",X"F8",X"88",X"88",X"F8",X"88",X"88",X"70",X"20",X"20",X"20",X"70",X"08",X"08",X"08",X"88",
|
||||
X"F8",X"88",X"90",X"E0",X"90",X"88",X"80",X"80",X"80",X"80",X"F8",X"88",X"D8",X"A8",X"88",X"88",
|
||||
X"88",X"C8",X"A8",X"98",X"88",X"F8",X"88",X"88",X"88",X"F8",X"F8",X"88",X"F8",X"80",X"80",X"F8",
|
||||
X"88",X"A8",X"90",X"E8",X"F8",X"88",X"F8",X"90",X"88",X"F8",X"80",X"F8",X"08",X"F8",X"F8",X"20",
|
||||
X"20",X"20",X"20",X"88",X"88",X"88",X"88",X"F8",X"88",X"88",X"50",X"70",X"20",X"88",X"88",X"A8",
|
||||
X"D8",X"88",X"88",X"50",X"20",X"50",X"88",X"88",X"50",X"20",X"20",X"20",X"F8",X"10",X"20",X"40",
|
||||
X"F8",X"30",X"20",X"20",X"20",X"30",X"80",X"40",X"20",X"10",X"08",X"60",X"20",X"20",X"20",X"60",
|
||||
X"20",X"50",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"20",X"10",X"00",X"00",X"00",X"21",
|
||||
X"DC",X"5F",X"7E",X"EE",X"80",X"77",X"32",X"00",X"18",X"F5",X"C5",X"60",X"69",X"01",X"FF",X"FF",
|
||||
X"09",X"DA",X"D0",X"07",X"C1",X"F1",X"FA",X"BF",X"07",X"1B",X"7A",X"B3",X"C2",X"BF",X"07",X"C9",
|
||||
X"3A",X"D0",X"5F",X"B7",X"CA",X"E0",X"07",X"3A",X"D0",X"5F",X"B7",X"C8",X"07",X"3E",X"00",X"32",
|
||||
X"D0",X"5F",X"3A",X"D1",X"5F",X"C9",X"C5",X"0B",X"78",X"B1",X"C2",X"F7",X"07",X"C1",X"C9",X"FF",
|
||||
X"FF",X"FF",X"FF",X"FF",X"22",X"B5",X"49",X"E1",X"22",X"B3",X"49",X"F5",X"E1",X"22",X"AB",X"49",
|
||||
X"21",X"00",X"00",X"39",X"31",X"B3",X"49",X"E5",X"D5",X"C5",X"31",X"C0",X"5F",X"3A",X"A0",X"49",
|
||||
X"3C",X"3C",X"BD",X"CA",X"49",X"08",X"0E",X"40",X"3A",X"A5",X"49",X"B7",X"C2",X"3D",X"08",X"23",
|
||||
X"23",X"22",X"B1",X"49",X"2A",X"B3",X"49",X"2B",X"22",X"B3",X"49",X"0E",X"2A",X"2A",X"B3",X"49",
|
||||
X"CD",X"74",X"0B",X"CD",X"67",X"0C",X"C3",X"A7",X"08",X"2B",X"2B",X"22",X"B1",X"49",X"21",X"00",
|
||||
X"00",X"22",X"B3",X"49",X"C3",X"A7",X"08",X"CD",X"73",X"05",X"01",X"CC",X"0F",X"CD",X"36",X"06",
|
||||
X"01",X"D1",X"0F",X"CD",X"D3",X"01",X"FB",X"CD",X"56",X"09",X"FE",X"03",X"20",X"11",X"F3",X"21",
|
||||
X"E0",X"48",X"F9",X"11",X"FF",X"7F",X"0E",X"00",X"CD",X"46",X"09",X"D2",X"57",X"08",X"76",X"3E",
|
||||
X"C3",X"32",X"03",X"4C",X"21",X"57",X"08",X"22",X"04",X"4C",X"00",X"00",X"00",X"21",X"00",X"4A",
|
||||
X"22",X"B1",X"49",X"CD",X"BC",X"09",X"21",X"DF",X"0F",X"22",X"E1",X"5F",X"3A",X"DB",X"5F",X"F6",
|
||||
X"80",X"32",X"DB",X"5F",X"CD",X"73",X"05",X"31",X"C0",X"5F",X"21",X"A7",X"08",X"E5",X"FB",X"AF",
|
||||
X"32",X"FF",X"5F",X"32",X"A5",X"49",X"CD",X"E3",X"02",X"3E",X"01",X"CD",X"2F",X"06",X"21",X"DE",
|
||||
X"08",X"3E",X"1F",X"CD",X"93",X"0C",X"CD",X"2F",X"06",X"CD",X"CC",X"0C",X"D6",X"41",X"F8",X"FE",
|
||||
X"1A",X"F0",X"0E",X"02",X"87",X"16",X"00",X"5F",X"19",X"CD",X"B4",X"0C",X"EB",X"E9",X"28",X"09",
|
||||
X"2B",X"00",X"A4",X"08",X"12",X"09",X"75",X"0F",X"40",X"09",X"6B",X"09",X"91",X"09",X"F7",X"4B",
|
||||
X"FA",X"4B",X"FD",X"4B",X"AF",X"0D",X"C2",X"09",X"03",X"0A",X"29",X"0A",X"AA",X"09",X"00",X"08",
|
||||
X"53",X"09",X"59",X"0A",X"C2",X"0E",X"2C",X"0B",X"5D",X"0B",X"F5",X"0D",X"8C",X"0A",X"7B",X"0D",
|
||||
X"00",X"4C",X"CD",X"F0",X"0B",X"CD",X"74",X"0B",X"CD",X"8B",X"0C",X"7D",X"E6",X"03",X"C2",X"18",
|
||||
X"09",X"CD",X"3E",X"0C",X"D8",X"C3",X"15",X"09",X"CD",X"F0",X"0B",X"CD",X"74",X"0B",X"7E",X"CD",
|
||||
X"2B",X"0C",X"23",X"7D",X"E6",X"07",X"C2",X"2E",X"09",X"CD",X"3E",X"0C",X"D8",X"C3",X"2B",X"09",
|
||||
X"CD",X"C0",X"0B",X"C1",X"D1",X"E1",X"71",X"CD",X"AA",X"0B",X"D8",X"CD",X"7F",X"0B",X"3F",X"DA",
|
||||
X"46",X"09",X"C9",X"CD",X"DD",X"02",X"CD",X"E0",X"07",X"F5",X"C5",X"D5",X"E5",X"01",X"18",X"00",
|
||||
X"11",X"35",X"00",X"F3",X"CD",X"BF",X"07",X"FB",X"C3",X"86",X"0C",X"CD",X"99",X"0C",X"CA",X"7A",
|
||||
X"09",X"CD",X"A9",X"0C",X"CD",X"F0",X"0B",X"22",X"B3",X"49",X"31",X"AB",X"49",X"F1",X"C1",X"D1",
|
||||
X"E1",X"22",X"A0",X"49",X"F9",X"21",X"08",X"00",X"E5",X"2A",X"B3",X"49",X"E5",X"2A",X"B5",X"49",
|
||||
X"C9",X"CD",X"C4",X"0B",X"D1",X"E1",X"E5",X"19",X"CD",X"74",X"0B",X"E1",X"E5",X"CD",X"BA",X"0C",
|
||||
X"CD",X"77",X"0B",X"E1",X"CD",X"B9",X"0C",X"C3",X"53",X"0C",X"CD",X"F0",X"0B",X"7D",X"B7",X"CA",
|
||||
X"ED",X"0D",X"87",X"85",X"87",X"C6",X"05",X"FE",X"4D",X"DA",X"BE",X"09",X"3E",X"4D",X"32",X"A4",
|
||||
X"49",X"C9",X"CD",X"C0",X"0B",X"C1",X"D1",X"E1",X"79",X"95",X"78",X"9C",X"D2",X"E8",X"09",X"CD",
|
||||
X"DB",X"09",X"D8",X"03",X"CD",X"7F",X"0B",X"D2",X"CF",X"09",X"C9",X"7E",X"02",X"E5",X"C5",X"60",
|
||||
X"69",X"4F",X"CD",X"AA",X"0B",X"C1",X"E1",X"C9",X"D5",X"C5",X"CD",X"B9",X"0C",X"EB",X"DA",X"ED",
|
||||
X"0D",X"E1",X"19",X"E5",X"C1",X"E1",X"CD",X"DB",X"09",X"D8",X"2B",X"0B",X"7B",X"B2",X"1B",X"C2",
|
||||
X"F6",X"09",X"C9",X"21",X"00",X"00",X"CD",X"99",X"0C",X"CA",X"23",X"0A",X"D6",X"30",X"DA",X"ED",
|
||||
X"0D",X"FE",X"0A",X"D2",X"ED",X"0D",X"E5",X"D1",X"29",X"29",X"19",X"29",X"5F",X"16",X"00",X"19",
|
||||
X"C3",X"06",X"0A",X"CD",X"7A",X"0B",X"C3",X"77",X"0B",X"CD",X"F0",X"0B",X"CD",X"7A",X"0B",X"11",
|
||||
X"F0",X"D8",X"CD",X"4A",X"0A",X"11",X"18",X"FC",X"CD",X"4A",X"0A",X"11",X"9C",X"FF",X"CD",X"4A",
|
||||
X"0A",X"11",X"F6",X"FF",X"CD",X"4A",X"0A",X"11",X"FF",X"FF",X"AF",X"E5",X"19",X"D2",X"55",X"0A",
|
||||
X"C1",X"3C",X"C3",X"4B",X"0A",X"E1",X"C3",X"61",X"0C",X"CD",X"F0",X"0B",X"CD",X"74",X"0B",X"7E",
|
||||
X"CD",X"58",X"0C",X"CD",X"89",X"0B",X"DA",X"79",X"0A",X"CA",X"79",X"0A",X"E5",X"CD",X"C2",X"0B",
|
||||
X"50",X"C1",X"E1",X"71",X"CD",X"AA",X"0B",X"D8",X"7A",X"FE",X"2E",X"C8",X"FE",X"0D",X"23",X"CA",
|
||||
X"5C",X"0A",X"FE",X"08",X"2B",X"2B",X"CA",X"5C",X"0A",X"C3",X"ED",X"0D",X"CD",X"99",X"0C",X"21",
|
||||
X"9F",X"0F",X"CA",X"F3",X"0A",X"BE",X"CA",X"B4",X"0A",X"57",X"7E",X"B7",X"FA",X"ED",X"0D",X"23",
|
||||
X"23",X"23",X"23",X"7A",X"C3",X"95",X"0A",X"FE",X"4D",X"C0",X"E3",X"23",X"E3",X"E5",X"2A",X"B5",
|
||||
X"49",X"7E",X"E1",X"C9",X"7E",X"F5",X"CD",X"19",X"0B",X"F1",X"CD",X"A7",X"0A",X"1A",X"CD",X"58",
|
||||
X"0C",X"05",X"CA",X"CA",X"0A",X"1B",X"1A",X"CD",X"58",X"0C",X"04",X"CD",X"89",X"0B",X"4F",X"DA",
|
||||
X"E9",X"0A",X"CA",X"E9",X"0A",X"E5",X"D5",X"C5",X"CD",X"F0",X"0B",X"78",X"C1",X"D1",X"4F",X"7D",
|
||||
X"12",X"05",X"CA",X"E8",X"0A",X"13",X"7C",X"12",X"E1",X"7E",X"B7",X"F8",X"79",X"FE",X"0D",X"CA",
|
||||
X"B4",X"0A",X"C9",X"CD",X"19",X"0B",X"F8",X"CD",X"A7",X"0A",X"1A",X"CD",X"58",X"0C",X"05",X"CA",
|
||||
X"0A",X"0B",X"1B",X"1A",X"CD",X"58",X"0C",X"C3",X"F3",X"0A",X"CD",X"7A",X"0B",X"CD",X"1C",X"0B",
|
||||
X"F8",X"FE",X"50",X"CA",X"FA",X"0A",X"C3",X"03",X"0B",X"CD",X"31",X"0D",X"7E",X"B7",X"F8",X"CD",
|
||||
X"B3",X"0C",X"46",X"23",X"CD",X"37",X"0C",X"0E",X"3D",X"C3",X"67",X"0C",X"CD",X"F5",X"0B",X"C2",
|
||||
X"35",X"0B",X"21",X"00",X"00",X"46",X"23",X"7C",X"B5",X"C8",X"7E",X"BB",X"C2",X"35",X"0B",X"23",
|
||||
X"7E",X"2B",X"BA",X"C2",X"35",X"0B",X"3E",X"02",X"CD",X"93",X"0C",X"CD",X"77",X"0B",X"78",X"CD",
|
||||
X"8D",X"0C",X"CD",X"52",X"0C",X"EB",X"CD",X"3E",X"0C",X"D8",X"C3",X"35",X"0B",X"CD",X"C4",X"0B",
|
||||
X"D1",X"E1",X"01",X"00",X"00",X"7E",X"81",X"4F",X"D2",X"6C",X"0B",X"04",X"CD",X"7F",X"0B",X"D2",
|
||||
X"65",X"0B",X"60",X"69",X"CD",X"31",X"0D",X"CD",X"53",X"0C",X"3E",X"20",X"C3",X"37",X"0C",X"23",
|
||||
X"7C",X"B5",X"37",X"C8",X"7B",X"95",X"7A",X"9C",X"C9",X"3E",X"2D",X"CD",X"37",X"0C",X"CD",X"CC",
|
||||
X"0C",X"CD",X"A9",X"0C",X"FE",X"20",X"C8",X"FE",X"2C",X"C8",X"FE",X"2E",X"C8",X"FE",X"3F",X"C8",
|
||||
X"FE",X"08",X"C8",X"FE",X"0D",X"37",X"3F",X"C0",X"37",X"C9",X"7E",X"47",X"B9",X"C8",X"3E",X"3F",
|
||||
X"CD",X"93",X"0C",X"CD",X"23",X"0A",X"79",X"CD",X"8D",X"0C",X"78",X"CD",X"58",X"0C",X"37",X"C9",
|
||||
X"0C",X"21",X"0E",X"01",X"21",X"00",X"00",X"CD",X"99",X"0C",X"47",X"CD",X"02",X"0C",X"DA",X"DA",
|
||||
X"0B",X"29",X"29",X"29",X"29",X"B5",X"6F",X"C3",X"C7",X"0B",X"E3",X"E5",X"78",X"CD",X"94",X"0B",
|
||||
X"D2",X"E8",X"0B",X"0D",X"C2",X"ED",X"0D",X"C9",X"C2",X"ED",X"0D",X"0D",X"C2",X"C4",X"0B",X"C9",
|
||||
X"CD",X"C2",X"0B",X"E1",X"C9",X"CD",X"C2",X"0B",X"D1",X"78",X"FE",X"0D",X"C8",X"CD",X"F0",X"0B",
|
||||
X"0D",X"C9",X"D6",X"30",X"D8",X"C6",X"E9",X"D8",X"C6",X"06",X"F2",X"10",X"0C",X"C6",X"07",X"D8",
|
||||
X"C6",X"0A",X"B7",X"C9",X"E6",X"0F",X"FE",X"0A",X"FA",X"1D",X"0C",X"C6",X"07",X"C6",X"30",X"C9",
|
||||
X"CD",X"56",X"09",X"FE",X"08",X"DA",X"37",X"0C",X"FE",X"1F",X"D8",X"FE",X"61",X"FA",X"37",X"0C",
|
||||
X"FE",X"7B",X"F2",X"37",X"0C",X"D6",X"20",X"C5",X"4F",X"CD",X"67",X"0C",X"C1",X"C9",X"CD",X"E7",
|
||||
X"07",X"C8",X"CD",X"59",X"09",X"FE",X"0D",X"37",X"C8",X"CD",X"56",X"09",X"FE",X"0D",X"37",X"C8",
|
||||
X"B7",X"C9",X"EB",X"7C",X"CD",X"58",X"0C",X"7D",X"F5",X"0F",X"0F",X"0F",X"0F",X"CD",X"61",X"0C",
|
||||
X"F1",X"CD",X"14",X"0C",X"C3",X"37",X"0C",X"F5",X"C5",X"D5",X"E5",X"2A",X"A6",X"49",X"3E",X"44",
|
||||
X"BD",X"DC",X"31",X"0D",X"3A",X"FF",X"5F",X"B7",X"C4",X"A8",X"49",X"2A",X"A6",X"49",X"EB",X"CD",
|
||||
X"5B",X"05",X"EB",X"22",X"A6",X"49",X"E1",X"D1",X"C1",X"F1",X"C9",X"7E",X"23",X"CD",X"58",X"0C",
|
||||
X"C3",X"7A",X"0B",X"CD",X"31",X"0D",X"C3",X"37",X"0C",X"E5",X"2A",X"B9",X"49",X"7E",X"23",X"FE",
|
||||
X"20",X"CA",X"9D",X"0C",X"FE",X"0D",X"C3",X"AE",X"0C",X"E5",X"2A",X"B9",X"49",X"2B",X"22",X"B9",
|
||||
X"49",X"E1",X"C9",X"23",X"5E",X"23",X"56",X"23",X"C9",X"EB",X"7D",X"93",X"6F",X"7C",X"9A",X"67",
|
||||
X"C9",X"23",X"4E",X"23",X"46",X"23",X"78",X"B1",X"C9",X"37",X"3F",X"C9",X"E5",X"D5",X"C5",X"06",
|
||||
X"00",X"21",X"BB",X"49",X"22",X"B9",X"49",X"CD",X"20",X"0C",X"FE",X"18",X"CA",X"A7",X"08",X"FE",
|
||||
X"0D",X"CA",X"2A",X"0D",X"FE",X"08",X"CA",X"FA",X"0C",X"DA",X"F1",X"0C",X"FE",X"1F",X"DA",X"D7",
|
||||
X"0C",X"77",X"23",X"04",X"78",X"FE",X"1A",X"DA",X"D7",X"0C",X"05",X"FA",X"2A",X"0D",X"2B",X"E5",
|
||||
X"2A",X"A6",X"49",X"7C",X"FE",X"07",X"D2",X"12",X"0D",X"26",X"66",X"7D",X"D6",X"06",X"6F",X"C3",
|
||||
X"15",X"0D",X"D6",X"06",X"67",X"22",X"A6",X"49",X"AF",X"32",X"EE",X"5F",X"EB",X"3C",X"CD",X"5C",
|
||||
X"05",X"0E",X"03",X"CD",X"2E",X"06",X"E1",X"C3",X"D7",X"0C",X"77",X"CD",X"99",X"0C",X"C3",X"93",
|
||||
X"04",X"F5",X"C5",X"D5",X"E5",X"21",X"E0",X"48",X"3E",X"C0",X"36",X"00",X"23",X"3D",X"C2",X"3A",
|
||||
X"0D",X"21",X"A4",X"49",X"7E",X"B7",X"CC",X"BC",X"09",X"CD",X"B7",X"09",X"7E",X"D6",X"06",X"4F",
|
||||
X"3E",X"4D",X"96",X"6F",X"26",X"00",X"29",X"29",X"29",X"29",X"29",X"11",X"00",X"40",X"19",X"EB",
|
||||
X"21",X"C0",X"00",X"19",X"06",X"20",X"7E",X"12",X"23",X"13",X"05",X"C2",X"66",X"0D",X"0D",X"C2",
|
||||
X"64",X"0D",X"21",X"42",X"06",X"22",X"A6",X"49",X"C3",X"86",X"0C",X"CD",X"99",X"0C",X"C2",X"D4",
|
||||
X"0D",X"21",X"88",X"0D",X"22",X"F3",X"5F",X"C9",X"21",X"D0",X"5F",X"7E",X"B7",X"CA",X"72",X"01",
|
||||
X"23",X"7E",X"2B",X"FE",X"11",X"C2",X"9D",X"0D",X"AF",X"77",X"C3",X"A7",X"08",X"FE",X"10",X"C2",
|
||||
X"72",X"01",X"AF",X"77",X"3C",X"32",X"A5",X"49",X"F1",X"C1",X"D1",X"E1",X"C3",X"04",X"08",X"21",
|
||||
X"00",X"00",X"22",X"DD",X"5F",X"CD",X"99",X"0C",X"CA",X"C9",X"0D",X"CD",X"A9",X"0C",X"CD",X"C4",
|
||||
X"0B",X"E1",X"22",X"DF",X"5F",X"E1",X"22",X"DD",X"5F",X"01",X"01",X"01",X"11",X"00",X"00",X"CD",
|
||||
X"1C",X"02",X"F3",X"06",X"AF",X"B7",X"F5",X"2A",X"F3",X"5F",X"7C",X"B5",X"CA",X"EB",X"0D",X"22",
|
||||
X"A2",X"49",X"CD",X"74",X"0B",X"21",X"00",X"00",X"22",X"F3",X"5F",X"F1",X"C8",X"3E",X"3F",X"CD",
|
||||
X"93",X"0C",X"C3",X"A7",X"08",X"CD",X"99",X"0C",X"CA",X"20",X"0E",X"CD",X"A9",X"0C",X"CD",X"C4",
|
||||
X"0B",X"21",X"D5",X"49",X"11",X"07",X"00",X"72",X"19",X"36",X"FF",X"19",X"36",X"FD",X"D1",X"E1",
|
||||
X"22",X"DD",X"49",X"22",X"E1",X"49",X"CD",X"B9",X"0C",X"DA",X"ED",X"0D",X"23",X"22",X"DF",X"49",
|
||||
X"01",X"D5",X"49",X"F3",X"E5",X"D5",X"C5",X"60",X"69",X"CD",X"DD",X"02",X"01",X"00",X"06",X"CD",
|
||||
X"24",X"04",X"7E",X"FE",X"FC",X"CA",X"61",X"0E",X"32",X"D8",X"5F",X"CD",X"B3",X"0C",X"EB",X"22",
|
||||
X"D4",X"5F",X"EB",X"CD",X"B4",X"0C",X"EB",X"22",X"D6",X"5F",X"EB",X"CD",X"B4",X"0C",X"B7",X"CA",
|
||||
X"2C",X"0E",X"F5",X"D5",X"CD",X"A1",X"0E",X"D1",X"F1",X"FE",X"FD",X"C2",X"6E",X"0E",X"CD",X"30",
|
||||
X"04",X"01",X"FF",X"7F",X"CD",X"F6",X"07",X"CD",X"E3",X"02",X"FB",X"C3",X"93",X"04",X"FE",X"FE",
|
||||
X"C2",X"82",X"0E",X"0E",X"01",X"CD",X"E4",X"03",X"4B",X"CD",X"E4",X"03",X"01",X"80",X"00",X"C3",
|
||||
X"2F",X"0E",X"E5",X"2A",X"D6",X"5F",X"4D",X"44",X"E1",X"78",X"B7",X"C2",X"95",X"0E",X"B1",X"C4",
|
||||
X"A7",X"0E",X"C3",X"32",X"0E",X"C5",X"0E",X"00",X"CD",X"A7",X"0E",X"C1",X"05",X"14",X"C3",X"89",
|
||||
X"0E",X"01",X"05",X"00",X"11",X"D4",X"5F",X"E5",X"D5",X"C5",X"CD",X"E4",X"03",X"EB",X"C5",X"4E",
|
||||
X"CD",X"E4",X"03",X"C1",X"23",X"0D",X"C2",X"AE",X"0E",X"01",X"04",X"00",X"CD",X"24",X"04",X"C3",
|
||||
X"93",X"04",X"CD",X"F5",X"0B",X"CA",X"CB",X"0E",X"22",X"B7",X"49",X"EB",X"CD",X"3E",X"0C",X"D8",
|
||||
X"CD",X"74",X"0B",X"5E",X"23",X"CD",X"00",X"0F",X"CD",X"23",X"0F",X"FE",X"03",X"C2",X"E9",X"0E",
|
||||
X"CD",X"B4",X"0C",X"CD",X"52",X"0C",X"C3",X"CB",X"0E",X"FE",X"02",X"C2",X"CC",X"0E",X"56",X"CD",
|
||||
X"8B",X"0C",X"3E",X"3B",X"CD",X"37",X"0C",X"7A",X"E6",X"7F",X"CD",X"2B",X"0C",X"C3",X"CC",X"0E",
|
||||
X"E5",X"D5",X"2A",X"B7",X"49",X"7C",X"B5",X"CA",X"ED",X"0D",X"1C",X"7E",X"23",X"B7",X"F2",X"0B",
|
||||
X"0F",X"1D",X"C2",X"0B",X"0F",X"E6",X"7F",X"CD",X"37",X"0C",X"7E",X"23",X"B7",X"F2",X"17",X"0F",
|
||||
X"D1",X"E1",X"C9",X"E5",X"D5",X"16",X"01",X"3E",X"F3",X"BB",X"CA",X"44",X"0F",X"21",X"47",X"0F",
|
||||
X"14",X"23",X"7E",X"BB",X"CA",X"44",X"0F",X"FE",X"F3",X"C2",X"31",X"0F",X"3E",X"03",X"BA",X"C2",
|
||||
X"30",X"0F",X"16",X"01",X"7A",X"D1",X"E1",X"C9",X"06",X"0E",X"16",X"1E",X"26",X"2E",X"36",X"3E",
|
||||
X"C6",X"CE",X"D3",X"D6",X"DB",X"DE",X"E6",X"EE",X"F6",X"FE",X"F3",X"01",X"11",X"21",X"22",X"2A",
|
||||
X"31",X"32",X"3A",X"C2",X"C3",X"C4",X"CA",X"CC",X"CD",X"D2",X"D4",X"DA",X"DC",X"E2",X"E4",X"EA",
|
||||
X"EC",X"F2",X"F4",X"FA",X"FC",X"F3",X"06",X"00",X"21",X"00",X"40",X"7D",X"AC",X"A8",X"77",X"23",
|
||||
X"7C",X"FE",X"80",X"C2",X"7B",X"0F",X"21",X"00",X"40",X"7D",X"AC",X"A8",X"BE",X"C2",X"9B",X"0F",
|
||||
X"23",X"7C",X"FE",X"80",X"C2",X"89",X"0F",X"04",X"C3",X"78",X"0F",X"22",X"A2",X"49",X"C7",X"41",
|
||||
X"AC",X"49",X"01",X"46",X"AB",X"49",X"01",X"42",X"AE",X"49",X"01",X"43",X"AD",X"49",X"01",X"44",
|
||||
X"B0",X"49",X"01",X"45",X"AF",X"49",X"01",X"48",X"B6",X"49",X"01",X"4C",X"B5",X"49",X"01",X"4D",
|
||||
X"00",X"00",X"01",X"50",X"B4",X"49",X"02",X"53",X"B2",X"49",X"02",X"FF",X"00",X"07",X"06",X"03",
|
||||
X"00",X"02",X"26",X"1D",X"4D",X"4F",X"4E",X"49",X"54",X"45",X"55",X"52",X"00",X"FF",X"00",X"05",
|
||||
X"05",X"F8",X"F8",X"F8",X"F8",X"F8",X"00",X"08",X"10",X"A0",X"40",X"02",X"30",X"0A",X"52",X"3A",
|
||||
X"52",X"45",X"44",X"45",X"4D",X"41",X"52",X"52",X"41",X"47",X"45",X"00",X"FF",X"FF",X"FF",X"FF");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
150
Computer_MiST/Interact_MiST/rtl/rom/interact.vhd
Normal file
150
Computer_MiST/Interact_MiST/rtl/rom/interact.vhd
Normal file
@@ -0,0 +1,150 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity interact is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(10 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of interact is
|
||||
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"3E",X"40",X"32",X"02",X"28",X"C3",X"0C",X"00",X"F3",X"C3",X"04",X"08",X"3E",X"38",X"32",X"00",
|
||||
X"30",X"AF",X"32",X"00",X"10",X"32",X"00",X"18",X"06",X"3E",X"21",X"C0",X"5F",X"F9",X"77",X"23",
|
||||
X"05",X"C2",X"1E",X"00",X"3A",X"00",X"08",X"B7",X"CA",X"00",X"08",X"3A",X"00",X"30",X"77",X"3E",
|
||||
X"80",X"32",X"DB",X"5F",X"C3",X"8C",X"01",X"FF",X"E5",X"D5",X"C5",X"F5",X"3A",X"F5",X"5F",X"B7",
|
||||
X"C2",X"6A",X"00",X"21",X"C0",X"5F",X"7E",X"1F",X"1F",X"1F",X"E6",X"07",X"F5",X"11",X"F6",X"5F",
|
||||
X"83",X"5F",X"3A",X"00",X"30",X"12",X"F1",X"3D",X"C2",X"5D",X"00",X"3E",X"06",X"87",X"87",X"87",
|
||||
X"AE",X"E6",X"F8",X"AE",X"F6",X"40",X"77",X"32",X"00",X"30",X"2A",X"EF",X"5F",X"23",X"22",X"EF",
|
||||
X"5F",X"11",X"06",X"38",X"21",X"C8",X"5F",X"01",X"CF",X"5F",X"1A",X"2F",X"A6",X"C2",X"89",X"00",
|
||||
X"2B",X"0B",X"1D",X"F2",X"7A",X"00",X"C3",X"24",X"01",X"F5",X"0A",X"2F",X"E3",X"A4",X"E1",X"CA",
|
||||
X"80",X"00",X"11",X"02",X"07",X"F5",X"21",X"C9",X"5F",X"7E",X"87",X"D2",X"9F",X"00",X"1D",X"C2",
|
||||
X"9A",X"00",X"23",X"15",X"C2",X"99",X"00",X"F1",X"1D",X"FA",X"24",X"01",X"16",X"08",X"0F",X"D2",
|
||||
X"B5",X"00",X"5A",X"3E",X"80",X"15",X"C2",X"AE",X"00",X"57",X"0A",X"B2",X"02",X"79",X"D6",X"C9",
|
||||
X"87",X"87",X"87",X"83",X"3D",X"FE",X"02",X"21",X"D2",X"5F",X"C2",X"D3",X"00",X"7E",X"2F",X"77",
|
||||
X"C3",X"24",X"01",X"FE",X"07",X"DA",X"E9",X"00",X"57",X"3A",X"00",X"38",X"2F",X"E6",X"80",X"B6",
|
||||
X"7A",X"CA",X"F5",X"00",X"FE",X"17",X"D2",X"F0",X"00",X"21",X"75",X"01",X"85",X"6F",X"7E",X"11",
|
||||
X"C6",X"23",X"C3",X"03",X"01",X"C6",X"23",X"FE",X"41",X"DA",X"03",X"01",X"FE",X"5B",X"D2",X"03",
|
||||
X"01",X"C6",X"20",X"57",X"3A",X"00",X"38",X"E6",X"C0",X"EE",X"80",X"7A",X"C2",X"16",X"01",X"FE",
|
||||
X"60",X"DA",X"16",X"01",X"D6",X"60",X"32",X"D1",X"5F",X"21",X"D0",X"5F",X"7E",X"B7",X"CA",X"23",
|
||||
X"01",X"36",X"80",X"34",X"01",X"00",X"38",X"11",X"C2",X"5F",X"21",X"C9",X"5F",X"0A",X"F6",X"C0",
|
||||
X"FE",X"0A",X"2F",X"12",X"A6",X"77",X"03",X"13",X"23",X"3E",X"07",X"B9",X"C2",X"31",X"01",X"21",
|
||||
X"C1",X"5F",X"46",X"3A",X"07",X"38",X"2F",X"77",X"A0",X"47",X"1F",X"1F",X"1F",X"1F",X"E6",X"0F",
|
||||
X"21",X"F2",X"5F",X"77",X"2B",X"78",X"E6",X"0F",X"77",X"3A",X"F5",X"5F",X"B7",X"C2",X"6A",X"01",
|
||||
X"21",X"C0",X"5F",X"7E",X"EE",X"C0",X"77",X"32",X"00",X"30",X"2A",X"F3",X"5F",X"7D",X"B4",X"E5",
|
||||
X"C0",X"E1",X"F1",X"C1",X"D1",X"E1",X"FB",X"C9",X"08",X"09",X"0D",X"20",X"2A",X"5E",X"2C",X"5F",
|
||||
X"2E",X"2F",X"3C",X"3E",X"22",X"27",X"24",X"25",X"21",X"3A",X"28",X"29",X"FB",X"CD",X"73",X"05",
|
||||
X"01",X"E8",X"01",X"CD",X"D3",X"01",X"3A",X"00",X"4C",X"FE",X"31",X"F5",X"03",X"01",X"06",X"02",
|
||||
X"CC",X"D3",X"01",X"01",X"17",X"02",X"CD",X"36",X"06",X"CD",X"E0",X"07",X"47",X"F1",X"78",X"C2",
|
||||
X"B7",X"01",X"FE",X"72",X"CA",X"00",X"4C",X"FE",X"6C",X"C2",X"96",X"01",X"06",X"01",X"0E",X"01",
|
||||
X"11",X"00",X"00",X"CD",X"1C",X"02",X"B7",X"C2",X"00",X"00",X"3A",X"00",X"4C",X"FE",X"31",X"CA",
|
||||
X"00",X"4C",X"C7",X"0A",X"FE",X"FF",X"C8",X"CD",X"2F",X"06",X"03",X"0A",X"5F",X"03",X"0A",X"57",
|
||||
X"03",X"CD",X"4F",X"05",X"03",X"C3",X"D3",X"01",X"03",X"12",X"23",X"44",X"45",X"50",X"52",X"45",
|
||||
X"53",X"53",X"00",X"03",X"26",X"0E",X"4C",X"20",X"54",X"4F",X"20",X"4C",X"4F",X"41",X"44",X"20",
|
||||
X"54",X"41",X"50",X"45",X"00",X"FF",X"03",X"3A",X"14",X"52",X"20",X"54",X"4F",X"20",X"52",X"45",
|
||||
X"53",X"54",X"41",X"52",X"54",X"00",X"FF",X"04",X"01",X"02",X"07",X"00",X"F3",X"AF",X"32",X"D3",
|
||||
X"5F",X"D5",X"C5",X"CD",X"CA",X"02",X"CD",X"DD",X"02",X"01",X"1D",X"00",X"CD",X"F6",X"07",X"01",
|
||||
X"64",X"01",X"1E",X"00",X"CD",X"B1",X"03",X"C1",X"C5",X"01",X"05",X"00",X"11",X"D4",X"5F",X"CD",
|
||||
X"1A",X"03",X"C1",X"B7",X"CA",X"5D",X"02",X"32",X"D3",X"5F",X"78",X"B7",X"C2",X"38",X"02",X"D1",
|
||||
X"7A",X"B7",X"C2",X"58",X"02",X"CD",X"E3",X"02",X"3A",X"D3",X"5F",X"FB",X"C9",X"C5",X"2A",X"DD",
|
||||
X"5F",X"7C",X"B5",X"CA",X"6F",X"02",X"22",X"D4",X"5F",X"2A",X"DF",X"5F",X"22",X"D6",X"5F",X"3A",
|
||||
X"D8",X"5F",X"FE",X"FD",X"C2",X"7B",X"02",X"C1",X"C3",X"4F",X"02",X"FE",X"FE",X"C2",X"AE",X"02",
|
||||
X"21",X"D9",X"5F",X"01",X"01",X"00",X"CD",X"1A",X"03",X"C1",X"B7",X"CA",X"99",X"02",X"32",X"D3",
|
||||
X"5F",X"78",X"B7",X"C2",X"38",X"02",X"C3",X"4F",X"02",X"2A",X"D6",X"5F",X"EB",X"2A",X"D4",X"5F",
|
||||
X"3A",X"D9",X"5F",X"77",X"23",X"1B",X"7A",X"B3",X"C2",X"A0",X"02",X"C3",X"38",X"02",X"2A",X"D4",
|
||||
X"5F",X"EB",X"2A",X"D6",X"5F",X"44",X"4D",X"CD",X"00",X"03",X"C1",X"B7",X"CA",X"38",X"02",X"32",
|
||||
X"D3",X"5F",X"78",X"B7",X"C2",X"38",X"02",X"C3",X"4F",X"02",X"0F",X"2F",X"E6",X"40",X"32",X"02",
|
||||
X"28",X"3A",X"C0",X"5F",X"F6",X"07",X"32",X"C0",X"5F",X"32",X"00",X"30",X"C9",X"F5",X"3E",X"FF",
|
||||
X"C3",X"E5",X"02",X"F5",X"AF",X"E5",X"21",X"DB",X"5F",X"AE",X"E6",X"40",X"AE",X"77",X"32",X"00",
|
||||
X"10",X"21",X"C0",X"5F",X"7E",X"E6",X"07",X"F6",X"38",X"77",X"32",X"00",X"30",X"E1",X"F1",X"C9",
|
||||
X"E5",X"CD",X"DD",X"02",X"AF",X"32",X"D3",X"5F",X"CD",X"1A",X"03",X"21",X"D3",X"5F",X"B6",X"77",
|
||||
X"78",X"B1",X"C2",X"08",X"03",X"E1",X"3A",X"D3",X"5F",X"C9",X"E5",X"C5",X"CD",X"4F",X"03",X"C1",
|
||||
X"67",X"D2",X"36",X"03",X"6F",X"7B",X"84",X"5F",X"7A",X"CE",X"00",X"57",X"79",X"94",X"4F",X"7A",
|
||||
X"DE",X"00",X"47",X"7D",X"E1",X"C9",X"CD",X"9A",X"03",X"DA",X"24",X"03",X"12",X"13",X"0B",X"25",
|
||||
X"CA",X"4C",X"03",X"78",X"B1",X"C2",X"36",X"03",X"3E",X"04",X"E1",X"C9",X"E1",X"AF",X"C9",X"CD",
|
||||
X"D0",X"03",X"FE",X"15",X"DA",X"4F",X"03",X"CD",X"D0",X"03",X"FE",X"21",X"D2",X"4F",X"03",X"FE",
|
||||
X"15",X"D2",X"57",X"03",X"C5",X"FE",X"0D",X"3F",X"0E",X"80",X"DA",X"A8",X"03",X"CD",X"D0",X"03",
|
||||
X"FE",X"21",X"D2",X"95",X"03",X"FE",X"15",X"0E",X"40",X"DA",X"A5",X"03",X"CD",X"D0",X"03",X"FE",
|
||||
X"0D",X"D2",X"95",X"03",X"CD",X"D0",X"03",X"FE",X"21",X"D2",X"95",X"03",X"FE",X"15",X"DA",X"95",
|
||||
X"03",X"00",X"3E",X"01",X"01",X"3E",X"02",X"C1",X"37",X"C9",X"C5",X"0E",X"80",X"CD",X"D0",X"03",
|
||||
X"FE",X"15",X"D2",X"95",X"03",X"FE",X"0D",X"3F",X"79",X"1F",X"4F",X"D2",X"9D",X"03",X"B7",X"C1",
|
||||
X"C9",X"C5",X"CD",X"D0",X"03",X"FE",X"21",X"D2",X"CC",X"03",X"FE",X"15",X"DA",X"CC",X"03",X"0B",
|
||||
X"78",X"B1",X"C2",X"B2",X"03",X"7B",X"B7",X"C4",X"CA",X"02",X"C1",X"C9",X"C1",X"C3",X"B1",X"03",
|
||||
X"E5",X"2A",X"DA",X"5F",X"3A",X"00",X"30",X"AD",X"F2",X"D4",X"03",X"AD",X"32",X"DA",X"5F",X"95",
|
||||
X"E1",X"E6",X"7F",X"C9",X"C5",X"06",X"08",X"79",X"0F",X"4F",X"9F",X"E6",X"08",X"C6",X"08",X"CD",
|
||||
X"F8",X"03",X"05",X"C2",X"E7",X"03",X"C1",X"C9",X"D6",X"02",X"CD",X"FF",X"03",X"3E",X"02",X"E5",
|
||||
X"2A",X"DA",X"5F",X"85",X"E6",X"7F",X"6F",X"3A",X"00",X"30",X"E6",X"7F",X"BD",X"C2",X"07",X"04",
|
||||
X"7C",X"EE",X"80",X"32",X"00",X"10",X"67",X"22",X"DA",X"5F",X"E1",X"C9",X"3A",X"00",X"30",X"E6",
|
||||
X"7F",X"32",X"DA",X"5F",X"78",X"B1",X"C8",X"3E",X"1B",X"CD",X"F8",X"03",X"0B",X"C3",X"24",X"04",
|
||||
X"CD",X"33",X"04",X"3E",X"08",X"CD",X"F8",X"03",X"01",X"01",X"00",X"C3",X"24",X"04",X"79",X"B7",
|
||||
X"C8",X"E5",X"D5",X"57",X"2A",X"E1",X"5F",X"7C",X"B5",X"C2",X"4F",X"04",X"21",X"7A",X"06",X"7A",
|
||||
X"FE",X"61",X"DA",X"5A",X"04",X"D6",X"43",X"C3",X"6F",X"04",X"FE",X"1E",X"3D",X"DA",X"6F",X"04",
|
||||
X"D6",X"1D",X"57",X"2A",X"E3",X"5F",X"7C",X"B5",X"7A",X"C2",X"6F",X"04",X"21",X"6E",X"06",X"5E",
|
||||
X"23",X"56",X"23",X"E5",X"D5",X"CD",X"18",X"05",X"D1",X"7A",X"C6",X"07",X"1F",X"1F",X"1F",X"E6",
|
||||
X"1F",X"EB",X"E3",X"CD",X"1D",X"05",X"22",X"E5",X"5F",X"E1",X"D1",X"D5",X"C5",X"01",X"00",X"00",
|
||||
X"CD",X"9D",X"04",X"C1",X"D1",X"E1",X"C9",X"CD",X"F7",X"05",X"CD",X"B3",X"05",X"E5",X"21",X"DB",
|
||||
X"04",X"22",X"EB",X"5F",X"E1",X"7C",X"B7",X"C8",X"7D",X"B7",X"C8",X"C5",X"D5",X"E5",X"22",X"E9",
|
||||
X"5F",X"E5",X"C5",X"D5",X"E5",X"2A",X"EB",X"5F",X"CD",X"DA",X"04",X"E1",X"D1",X"C1",X"0C",X"1C",
|
||||
X"2D",X"C2",X"B2",X"04",X"E3",X"7D",X"E3",X"6F",X"79",X"95",X"4F",X"7B",X"95",X"5F",X"04",X"14",
|
||||
X"25",X"C2",X"B2",X"04",X"E1",X"E1",X"D1",X"C1",X"37",X"C9",X"E9",X"CD",X"ED",X"04",X"C8",X"3A",
|
||||
X"EE",X"5F",X"4F",X"CD",X"2D",X"05",X"47",X"79",X"AE",X"A0",X"AE",X"77",X"C9",X"3A",X"EA",X"5F",
|
||||
X"C6",X"07",X"1F",X"1F",X"1F",X"E6",X"1F",X"D5",X"59",X"16",X"00",X"2A",X"E5",X"5F",X"CD",X"1D",
|
||||
X"05",X"78",X"1F",X"1F",X"1F",X"E6",X"1F",X"5F",X"16",X"00",X"19",X"78",X"E6",X"07",X"5F",X"7E",
|
||||
X"87",X"1D",X"F2",X"10",X"05",X"9F",X"D1",X"C9",X"16",X"00",X"21",X"00",X"00",X"D5",X"B7",X"1F",
|
||||
X"D2",X"24",X"05",X"19",X"EB",X"29",X"EB",X"B7",X"C2",X"1F",X"05",X"D1",X"C9",X"6B",X"26",X"00",
|
||||
X"29",X"29",X"29",X"29",X"29",X"7A",X"1F",X"1F",X"E6",X"3F",X"B5",X"6F",X"7A",X"EB",X"E6",X"03",
|
||||
X"21",X"4B",X"05",X"85",X"6F",X"7E",X"2A",X"E7",X"5F",X"19",X"C9",X"03",X"0C",X"30",X"C0",X"CD",
|
||||
X"F7",X"05",X"0A",X"CD",X"5C",X"05",X"D0",X"03",X"C3",X"52",X"05",X"79",X"CD",X"3F",X"04",X"D0",
|
||||
X"3A",X"EA",X"5F",X"3C",X"82",X"FE",X"67",X"57",X"D8",X"3A",X"E9",X"5F",X"3C",X"83",X"5F",X"16",
|
||||
X"06",X"37",X"C9",X"0E",X"00",X"E5",X"D5",X"79",X"CD",X"E8",X"05",X"4F",X"21",X"00",X"40",X"11",
|
||||
X"A0",X"09",X"71",X"23",X"1B",X"7A",X"B3",X"C2",X"82",X"05",X"D1",X"E1",X"C9",X"CD",X"F7",X"05",
|
||||
X"21",X"D2",X"05",X"22",X"EB",X"5F",X"CD",X"B3",X"05",X"CD",X"E8",X"05",X"32",X"ED",X"5F",X"C3",
|
||||
X"A5",X"04",X"CD",X"F7",X"05",X"21",X"DF",X"04",X"22",X"EB",X"5F",X"60",X"69",X"CD",X"BE",X"05",
|
||||
X"C3",X"A5",X"04",X"60",X"69",X"5E",X"23",X"56",X"23",X"EB",X"22",X"E5",X"5F",X"EB",X"5E",X"23",
|
||||
X"56",X"23",X"D5",X"7E",X"23",X"CD",X"2F",X"06",X"5E",X"23",X"56",X"23",X"7E",X"E1",X"01",X"00",
|
||||
X"00",X"C9",X"CD",X"ED",X"04",X"C8",X"CD",X"2D",X"05",X"47",X"A6",X"4F",X"3A",X"EE",X"5F",X"A0",
|
||||
X"B9",X"C0",X"3A",X"ED",X"5F",X"C3",X"E8",X"04",X"E6",X"03",X"C5",X"4F",X"87",X"87",X"81",X"87",
|
||||
X"87",X"81",X"87",X"87",X"81",X"C1",X"C9",X"E5",X"21",X"00",X"40",X"22",X"E7",X"5F",X"E1",X"C9",
|
||||
X"E5",X"D5",X"C5",X"CD",X"F7",X"05",X"79",X"CD",X"E8",X"05",X"CD",X"E2",X"04",X"C1",X"D1",X"E1",
|
||||
X"CD",X"F7",X"05",X"E5",X"D5",X"C5",X"50",X"59",X"78",X"E6",X"03",X"47",X"CD",X"2D",X"05",X"7E",
|
||||
X"0F",X"0F",X"05",X"F2",X"20",X"06",X"07",X"07",X"E6",X"03",X"C1",X"D1",X"E1",X"C9",X"79",X"CD",
|
||||
X"E8",X"05",X"32",X"EE",X"5F",X"C9",X"D5",X"3A",X"DB",X"5F",X"E6",X"C0",X"CD",X"5E",X"06",X"32",
|
||||
X"00",X"10",X"32",X"DB",X"5F",X"0B",X"3A",X"DC",X"5F",X"E6",X"80",X"CD",X"5E",X"06",X"57",X"03",
|
||||
X"0A",X"0F",X"0F",X"E6",X"40",X"B2",X"32",X"00",X"18",X"32",X"DC",X"5F",X"D1",X"C9",X"57",X"0A",
|
||||
X"03",X"E6",X"07",X"B2",X"57",X"03",X"0A",X"E6",X"07",X"17",X"17",X"17",X"B2",X"C9",X"05",X"05",
|
||||
X"00",X"50",X"20",X"50",X"00",X"20",X"00",X"70",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"20",
|
||||
X"20",X"20",X"00",X"20",X"50",X"50",X"00",X"00",X"00",X"50",X"F8",X"50",X"F8",X"50",X"70",X"A0",
|
||||
X"70",X"28",X"70",X"C8",X"D0",X"20",X"58",X"98",X"20",X"50",X"20",X"50",X"28",X"20",X"40",X"00",
|
||||
X"00",X"00",X"20",X"40",X"40",X"40",X"20",X"20",X"10",X"10",X"10",X"20",X"A8",X"70",X"F8",X"70",
|
||||
X"A8",X"00",X"20",X"70",X"20",X"00",X"00",X"00",X"00",X"20",X"40",X"00",X"00",X"70",X"00",X"00",
|
||||
X"00",X"00",X"00",X"00",X"20",X"08",X"10",X"20",X"40",X"80",X"70",X"88",X"88",X"88",X"70",X"20",
|
||||
X"60",X"20",X"20",X"70",X"F8",X"08",X"F8",X"80",X"F8",X"F8",X"08",X"38",X"08",X"F8",X"90",X"90",
|
||||
X"F8",X"10",X"10",X"F0",X"80",X"F0",X"08",X"F0",X"F8",X"80",X"F8",X"88",X"F8",X"F8",X"08",X"10",
|
||||
X"20",X"20",X"F8",X"88",X"F8",X"88",X"F8",X"F8",X"88",X"F8",X"08",X"F8",X"00",X"20",X"00",X"20",
|
||||
X"00",X"00",X"20",X"00",X"20",X"40",X"10",X"20",X"40",X"20",X"10",X"00",X"70",X"00",X"70",X"00",
|
||||
X"40",X"20",X"10",X"20",X"40",X"F8",X"88",X"38",X"00",X"20",X"30",X"48",X"50",X"40",X"38",X"70",
|
||||
X"88",X"F8",X"88",X"88",X"F8",X"88",X"F0",X"88",X"F8",X"F8",X"80",X"80",X"80",X"F8",X"F0",X"88",
|
||||
X"88",X"88",X"F0",X"F8",X"80",X"E0",X"80",X"F8",X"F8",X"80",X"E0",X"80",X"80",X"F8",X"80",X"98",
|
||||
X"88",X"F8",X"88",X"88",X"F8",X"88",X"88",X"70",X"20",X"20",X"20",X"70",X"08",X"08",X"08",X"88",
|
||||
X"F8",X"88",X"90",X"E0",X"90",X"88",X"80",X"80",X"80",X"80",X"F8",X"88",X"D8",X"A8",X"88",X"88",
|
||||
X"88",X"C8",X"A8",X"98",X"88",X"F8",X"88",X"88",X"88",X"F8",X"F8",X"88",X"F8",X"80",X"80",X"F8",
|
||||
X"88",X"A8",X"90",X"E8",X"F8",X"88",X"F8",X"90",X"88",X"F8",X"80",X"F8",X"08",X"F8",X"F8",X"20",
|
||||
X"20",X"20",X"20",X"88",X"88",X"88",X"88",X"F8",X"88",X"88",X"50",X"70",X"20",X"88",X"88",X"A8",
|
||||
X"D8",X"88",X"88",X"50",X"20",X"50",X"88",X"88",X"50",X"20",X"20",X"20",X"F8",X"10",X"20",X"40",
|
||||
X"F8",X"30",X"20",X"20",X"20",X"30",X"80",X"40",X"20",X"10",X"08",X"60",X"20",X"20",X"20",X"60",
|
||||
X"20",X"50",X"88",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"20",X"10",X"00",X"00",X"00",X"21",
|
||||
X"DC",X"5F",X"7E",X"EE",X"80",X"77",X"32",X"00",X"18",X"F5",X"C5",X"60",X"69",X"01",X"FF",X"FF",
|
||||
X"09",X"DA",X"D0",X"07",X"C1",X"F1",X"FA",X"BF",X"07",X"1B",X"7A",X"B3",X"C2",X"BF",X"07",X"C9",
|
||||
X"3A",X"D0",X"5F",X"B7",X"CA",X"E0",X"07",X"3A",X"D0",X"5F",X"B7",X"C8",X"07",X"3E",X"00",X"32",
|
||||
X"D0",X"5F",X"3A",X"D1",X"5F",X"C9",X"C5",X"0B",X"78",X"B1",X"C2",X"F7",X"07",X"C1",X"C9",X"FF");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
57
Computer_MiST/Interact_MiST/rtl/spram.v
Normal file
57
Computer_MiST/Interact_MiST/rtl/spram.v
Normal file
@@ -0,0 +1,57 @@
|
||||
|
||||
module spram #(parameter DATAWIDTH=8, ADDRWIDTH=8, NUMWORDS=1<<ADDRWIDTH, MEM_INIT_FILE="") (
|
||||
address,
|
||||
clock,
|
||||
data,
|
||||
wren,
|
||||
q);
|
||||
|
||||
input [ADDRWIDTH-1:0] address;
|
||||
input clock;
|
||||
input [DATAWIDTH-1:0] data;
|
||||
input wren;
|
||||
output [DATAWIDTH-1:0] q;
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (address),
|
||||
.clock0 (clock),
|
||||
.data_a (data),
|
||||
.wren_a (wren),
|
||||
.q_a (q),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.address_b (1'b1),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_b (1'b1),
|
||||
.eccstatus (),
|
||||
.q_b (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = NUMWORDS,
|
||||
altsyncram_component.operation_mode = "SINGLE_PORT",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "UNREGISTERED",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
|
||||
altsyncram_component.widthad_a = ADDRWIDTH,
|
||||
altsyncram_component.width_a = DATAWIDTH,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
82
Computer_MiST/Interact_MiST/rtl/sprom.vhd
Normal file
82
Computer_MiST/Interact_MiST/rtl/sprom.vhd
Normal file
@@ -0,0 +1,82 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY sprom IS
|
||||
GENERIC
|
||||
(
|
||||
init_file : string := "";
|
||||
widthad_a : natural;
|
||||
width_a : natural := 8;
|
||||
outdata_reg_a : string := "UNREGISTERED"
|
||||
);
|
||||
PORT
|
||||
(
|
||||
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
clock : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END sprom;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF sprom IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altsyncram
|
||||
GENERIC (
|
||||
address_aclr_a : STRING;
|
||||
clock_enable_input_a : STRING;
|
||||
clock_enable_output_a : STRING;
|
||||
init_file : STRING;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
numwords_a : NATURAL;
|
||||
operation_mode : STRING;
|
||||
outdata_aclr_a : STRING;
|
||||
outdata_reg_a : STRING;
|
||||
widthad_a : NATURAL;
|
||||
width_a : NATURAL;
|
||||
width_byteena_a : NATURAL
|
||||
);
|
||||
PORT (
|
||||
clock0 : IN STD_LOGIC ;
|
||||
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q <= sub_wire0(width_a-1 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_aclr_a => "NONE",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
init_file => init_file,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 2**widthad_a,
|
||||
operation_mode => "ROM",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_reg_a => outdata_reg_a,
|
||||
widthad_a => widthad_a,
|
||||
width_a => width_a,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
PORT MAP (
|
||||
clock0 => clock,
|
||||
address_a => address,
|
||||
q_a => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
31
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS138.v
Normal file
31
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS138.v
Normal file
@@ -0,0 +1,31 @@
|
||||
module SN74LS138 (
|
||||
input a, //01
|
||||
input b, //02
|
||||
input c, //03
|
||||
input g2an, //04
|
||||
input g2bn, //05
|
||||
input g1, //06
|
||||
output y7n, //07
|
||||
|
||||
output y6n, //09
|
||||
output y5n, //10
|
||||
output y4n, //11
|
||||
output y3n, //12
|
||||
output y2n, //13
|
||||
output y1n, //14
|
||||
output y0n //15
|
||||
);
|
||||
|
||||
wire en;
|
||||
assign en = ~(~g1 | g2bn | g2an);
|
||||
|
||||
assign y0n = ~(~a & ~b & ~c & en);
|
||||
assign y1n = ~(a & ~b & ~c & en);
|
||||
assign y2n = ~(~a & b & ~c & en);
|
||||
assign y3n = ~(a & b & ~c & en);
|
||||
assign y4n = ~(~a & ~b & c & en);
|
||||
assign y5n = ~(~b & c & a & en);
|
||||
assign y6n = ~(~a & c & b & en);
|
||||
assign y7n = ~(en & b & a & c);
|
||||
|
||||
endmodule
|
||||
73
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS195.v
Normal file
73
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS195.v
Normal file
@@ -0,0 +1,73 @@
|
||||
// based on TI SN74LS195 datasheet
|
||||
module SN74LS195(
|
||||
input clrn, //01
|
||||
input j, //02
|
||||
input kn, //03
|
||||
input a, //04
|
||||
input b, //05
|
||||
input c, //06
|
||||
input d, //07
|
||||
|
||||
input sh_ldn, //09
|
||||
input clk, //10
|
||||
output qdn, //11
|
||||
output reg qd, //12
|
||||
output reg qc, //13
|
||||
output reg qb, //14
|
||||
output reg qa //15
|
||||
);
|
||||
|
||||
always@(posedge clk or negedge clrn)
|
||||
begin
|
||||
if (!clrn)
|
||||
begin
|
||||
qa <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
qa <= (~qa & j & sh_ldn) | (sh_ldn & kn & qa) | (~sh_ldn & a);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge clrn)
|
||||
begin
|
||||
if (!clrn)
|
||||
begin
|
||||
qb <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
qb <= (qa & sh_ldn) | (~sh_ldn & b);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge clrn)
|
||||
begin
|
||||
if (!clrn)
|
||||
begin
|
||||
qc <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
qc <= (qb & sh_ldn) | (~sh_ldn & c);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk or negedge clrn)
|
||||
begin
|
||||
if (!clrn)
|
||||
begin
|
||||
qd <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
qd <= (qc & sh_ldn) | (~sh_ldn & d);
|
||||
end
|
||||
end
|
||||
|
||||
assign qdn = ~qd;
|
||||
|
||||
endmodule
|
||||
597
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS393.bdf
Normal file
597
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS393.bdf
Normal file
@@ -0,0 +1,597 @@
|
||||
//DO NOT EDIT THIS FILE IN A TEXT EDITOR!
|
||||
/*
|
||||
Copyright (C) 1988-1999 Altera Corporation
|
||||
Any megafunction design, and related net list (encrypted or decrypted),
|
||||
support information, device programming or simulation file, and any other
|
||||
associated documentation or information provided by Altera or a partner
|
||||
under Altera's Megafunction Partnership Program may be used only to
|
||||
program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
use of such megafunction design, net list, support information, device
|
||||
programming or simulation file, or any other related documentation or
|
||||
information is prohibited for any other purpose, including, but not
|
||||
limited to modification, reverse engineering, de-compiling, or use with
|
||||
any other silicon devices, unless such use is explicitly licensed under
|
||||
a separate agreement with Altera or a megafunction partner. Title to
|
||||
the intellectual property, including patents, copyrights, trademarks,
|
||||
trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
net list, support information, device programming or simulation file, or
|
||||
any other related documentation or information provided by Altera or a
|
||||
megafunction partner, remains with Altera, the megafunction partner, or
|
||||
their respective licensors. No other licenses, including any licenses
|
||||
needed under any third party's intellectual property, are provided herein.
|
||||
*/
|
||||
(header "graphic" (version "1.1"))
|
||||
(pin (input)(rect 8 688 176 704)(text "INPUT"(rect 133 -1 157 9)(font "Arial"(font_size 6)))(text "CLR2"(rect 45 1 71 15)(font "Arial"(font_size 8)))(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12)(line_width 1))
|
||||
(line (pt 92 4)(pt 117 4)(line_width 1))
|
||||
(line (pt 121 8)(pt 168 8)(line_width 1))
|
||||
(line (pt 92 12)(pt 92 4)(line_width 1))
|
||||
(line (pt 117 4)(pt 121 8)(line_width 1))
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1)))(text "GND"(rect 136 7 154 17)(font "Arial"(font_size 6))))
|
||||
(pin (input)(rect 8 584 176 600)(text "INPUT"(rect 133 -1 157 9)(font "Arial"(font_size 6)))(text "A2"(rect 57 1 71 15)(font "Arial"(font_size 8)))(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12)(line_width 1))
|
||||
(line (pt 92 4)(pt 117 4)(line_width 1))
|
||||
(line (pt 121 8)(pt 168 8)(line_width 1))
|
||||
(line (pt 92 12)(pt 92 4)(line_width 1))
|
||||
(line (pt 117 4)(pt 121 8)(line_width 1))
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1)))(text "VCC"(rect 136 7 153 17)(font "Arial"(font_size 6))))
|
||||
(pin (input)(rect 8 128 176 144)(text "INPUT"(rect 133 -1 157 9)(font "Arial"(font_size 6)))(text "A1"(rect 57 1 71 15)(font "Arial"(font_size 8)))(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12)(line_width 1))
|
||||
(line (pt 92 4)(pt 117 4)(line_width 1))
|
||||
(line (pt 121 8)(pt 168 8)(line_width 1))
|
||||
(line (pt 92 12)(pt 92 4)(line_width 1))
|
||||
(line (pt 117 4)(pt 121 8)(line_width 1))
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1)))(text "VCC"(rect 136 7 153 17)(font "Arial"(font_size 6))))
|
||||
(pin (input)(rect 8 232 176 248)(text "INPUT"(rect 133 -1 157 9)(font "Arial"(font_size 6)))(text "CLR1"(rect 45 1 71 15)(font "Arial"(font_size 8)))(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 92 12)(pt 117 12)(line_width 1))
|
||||
(line (pt 92 4)(pt 117 4)(line_width 1))
|
||||
(line (pt 121 8)(pt 168 8)(line_width 1))
|
||||
(line (pt 92 12)(pt 92 4)(line_width 1))
|
||||
(line (pt 117 4)(pt 121 8)(line_width 1))
|
||||
(line (pt 117 12)(pt 121 8)(line_width 1)))(text "GND"(rect 136 7 154 17)(font "Arial"(font_size 6))))
|
||||
(pin (output)(rect 536 544 712 560)(text "OUTPUT"(rect 1 -1 34 9)(font "Arial"(font_size 6)))(text "Q2A"(rect 90 0 112 14)(font "Arial"(font_size 8)))(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8)(line_width 1))
|
||||
(line (pt 52 4)(pt 78 4)(line_width 1))
|
||||
(line (pt 52 12)(pt 78 12)(line_width 1))
|
||||
(line (pt 52 12)(pt 52 4)(line_width 1))
|
||||
(line (pt 78 4)(pt 82 8)(line_width 1))
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))))
|
||||
(pin (output)(rect 536 648 712 664)(text "OUTPUT"(rect 1 -1 34 9)(font "Arial"(font_size 6)))(text "Q2B"(rect 90 0 111 14)(font "Arial"(font_size 8)))(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8)(line_width 1))
|
||||
(line (pt 52 4)(pt 78 4)(line_width 1))
|
||||
(line (pt 52 12)(pt 78 12)(line_width 1))
|
||||
(line (pt 52 12)(pt 52 4)(line_width 1))
|
||||
(line (pt 78 4)(pt 82 8)(line_width 1))
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))))
|
||||
(pin (output)(rect 536 760 712 776)(text "OUTPUT"(rect 1 -1 34 9)(font "Arial"(font_size 6)))(text "Q2C"(rect 90 0 111 14)(font "Arial"(font_size 8)))(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8)(line_width 1))
|
||||
(line (pt 52 4)(pt 78 4)(line_width 1))
|
||||
(line (pt 52 12)(pt 78 12)(line_width 1))
|
||||
(line (pt 52 12)(pt 52 4)(line_width 1))
|
||||
(line (pt 78 4)(pt 82 8)(line_width 1))
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))))
|
||||
(pin (output)(rect 536 872 712 888)(text "OUTPUT"(rect 1 -1 34 9)(font "Arial"(font_size 6)))(text "Q2D"(rect 90 0 111 14)(font "Arial"(font_size 8)))(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8)(line_width 1))
|
||||
(line (pt 52 4)(pt 78 4)(line_width 1))
|
||||
(line (pt 52 12)(pt 78 12)(line_width 1))
|
||||
(line (pt 52 12)(pt 52 4)(line_width 1))
|
||||
(line (pt 78 4)(pt 82 8)(line_width 1))
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))))
|
||||
(pin (output)(rect 536 416 712 432)(text "OUTPUT"(rect 1 -1 34 9)(font "Arial"(font_size 6)))(text "Q1D"(rect 90 0 111 14)(font "Arial"(font_size 8)))(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8)(line_width 1))
|
||||
(line (pt 52 4)(pt 78 4)(line_width 1))
|
||||
(line (pt 52 12)(pt 78 12)(line_width 1))
|
||||
(line (pt 52 12)(pt 52 4)(line_width 1))
|
||||
(line (pt 78 4)(pt 82 8)(line_width 1))
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))))
|
||||
(pin (output)(rect 536 304 712 320)(text "OUTPUT"(rect 1 -1 34 9)(font "Arial"(font_size 6)))(text "Q1C"(rect 90 0 111 14)(font "Arial"(font_size 8)))(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8)(line_width 1))
|
||||
(line (pt 52 4)(pt 78 4)(line_width 1))
|
||||
(line (pt 52 12)(pt 78 12)(line_width 1))
|
||||
(line (pt 52 12)(pt 52 4)(line_width 1))
|
||||
(line (pt 78 4)(pt 82 8)(line_width 1))
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))))
|
||||
(pin (output)(rect 536 192 712 208)(text "OUTPUT"(rect 1 -1 34 9)(font "Arial"(font_size 6)))(text "Q1B"(rect 90 0 111 14)(font "Arial"(font_size 8)))(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8)(line_width 1))
|
||||
(line (pt 52 4)(pt 78 4)(line_width 1))
|
||||
(line (pt 52 12)(pt 78 12)(line_width 1))
|
||||
(line (pt 52 12)(pt 52 4)(line_width 1))
|
||||
(line (pt 78 4)(pt 82 8)(line_width 1))
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))))
|
||||
(pin (output)(rect 536 88 712 104)(text "OUTPUT"(rect 1 -1 34 9)(font "Arial"(font_size 6)))(text "Q1A"(rect 90 0 112 14)(font "Arial"(font_size 8)))(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8)(line_width 1))
|
||||
(line (pt 52 4)(pt 78 4)(line_width 1))
|
||||
(line (pt 52 12)(pt 78 12)(line_width 1))
|
||||
(line (pt 52 12)(pt 52 4)(line_width 1))
|
||||
(line (pt 78 4)(pt 82 8)(line_width 1))
|
||||
(line (pt 82 8)(pt 78 12)(line_width 1))
|
||||
(line (pt 78 12)(pt 82 8)(line_width 1))))
|
||||
(symbol (rect 248 848 312 888)(text "AND3"(rect 1 -1 22 9)(font "Arial"(font_size 6)))(text "35"(rect 1 30 9 40)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 32)(input)(text "IN3"(rect 7 24 12 36)(font "Courier New"(bold))(invisible))(text "IN3"(rect 7 24 22 36)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1)))
|
||||
(port (pt 0 24)(input)(text "IN2"(rect 7 16 12 28)(font "Courier New"(bold))(invisible))(text "IN2"(rect 7 16 22 28)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 24)(pt 16 24)(line_width 1)))
|
||||
(port (pt 0 16)(input)(text "IN1"(rect 7 7 12 19)(font "Courier New"(bold))(invisible))(text "IN1"(rect 7 7 22 19)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 16 16)(line_width 1)))
|
||||
(port (pt 64 24)(output)(text "OUT"(rect 52 15 57 27)(font "Courier New"(bold))(invisible))(text "OUT"(rect 52 15 67 27)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 43 24)(pt 64 24)(line_width 1)))
|
||||
(drawing
|
||||
(line (pt 16 36)(pt 31 36)(line_width 1))
|
||||
(line (pt 16 12)(pt 31 12)(line_width 1))
|
||||
(line (pt 16 36)(pt 16 12)(line_width 1))(arc (pt 31 36) (pt 31 12) (rect 19 12 44 37) (line_width 1))))
|
||||
(symbol (rect 248 392 312 432)(text "AND3"(rect 1 -1 22 9)(font "Arial"(font_size 6)))(text "11"(rect 1 30 9 40)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 32)(input)(text "IN3"(rect 7 24 12 36)(font "Courier New"(bold))(invisible))(text "IN3"(rect 7 24 22 36)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1)))
|
||||
(port (pt 0 24)(input)(text "IN2"(rect 7 16 12 28)(font "Courier New"(bold))(invisible))(text "IN2"(rect 7 16 22 28)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 24)(pt 16 24)(line_width 1)))
|
||||
(port (pt 0 16)(input)(text "IN1"(rect 7 7 12 19)(font "Courier New"(bold))(invisible))(text "IN1"(rect 7 7 22 19)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 16 16)(line_width 1)))
|
||||
(port (pt 64 24)(output)(text "OUT"(rect 52 15 57 27)(font "Courier New"(bold))(invisible))(text "OUT"(rect 52 15 67 27)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 43 24)(pt 64 24)(line_width 1)))
|
||||
(drawing
|
||||
(line (pt 16 36)(pt 31 36)(line_width 1))
|
||||
(line (pt 16 12)(pt 31 12)(line_width 1))
|
||||
(line (pt 16 36)(pt 16 12)(line_width 1))(arc (pt 31 36) (pt 31 12) (rect 19 12 44 37) (line_width 1))))
|
||||
(symbol (rect 328 856 392 896)(text "XOR"(rect 1 -1 18 9)(font "Arial"(font_size 6)))(text "34"(rect 1 30 9 40)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 16)(input)(text "IN1"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))(text "IN1"(rect 0 6 15 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 11 16)(line_width 1)))
|
||||
(port (pt 0 32)(input)(text "IN2"(rect 5 22 10 34)(font "Courier New"(bold))(invisible))(text "IN2"(rect 5 22 20 34)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 32)(pt 11 32)(line_width 1)))
|
||||
(port (pt 64 24)(output)(text "OUT"(rect 53 14 58 26)(font "Courier New"(bold))(invisible))(text "OUT"(rect 53 14 68 26)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 49 24)(pt 64 24)(line_width 1)))
|
||||
(drawing
|
||||
(line (pt 14 13)(pt 25 13)(line_width 1))
|
||||
(line (pt 14 35)(pt 25 35)(line_width 1))(arc (pt 7 29) (pt 7 19) (rect -14 8 19 41) (line_width 1))(arc (pt 49 24) (pt 25 13) (rect -6 13 57 76) (line_width 1))(arc (pt 25 35) (pt 49 24) (rect -6 -27 57 36) (line_width 1))(arc (pt 8 36) (pt 8 12) (rect -21 7 14 42) (line_width 1))))
|
||||
(symbol (rect 328 744 392 784)(text "XOR"(rect 1 -1 18 9)(font "Arial"(font_size 6)))(text "33"(rect 1 30 9 40)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 16)(input)(text "IN1"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))(text "IN1"(rect 0 6 15 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 11 16)(line_width 1)))
|
||||
(port (pt 0 32)(input)(text "IN2"(rect 5 22 10 34)(font "Courier New"(bold))(invisible))(text "IN2"(rect 5 22 20 34)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 32)(pt 11 32)(line_width 1)))
|
||||
(port (pt 64 24)(output)(text "OUT"(rect 53 14 58 26)(font "Courier New"(bold))(invisible))(text "OUT"(rect 53 14 68 26)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 49 24)(pt 64 24)(line_width 1)))
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(port (pt 64 24)(output)(text "OUT"(rect 51 14 56 26)(font "Courier New"(bold))(invisible))(text "OUT"(rect 51 14 66 26)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 42 24)(pt 64 24)(line_width 1)))
|
||||
(drawing
|
||||
(line (pt 14 36)(pt 31 36)(line_width 1))
|
||||
(line (pt 14 12)(pt 32 12)(line_width 1))
|
||||
(line (pt 14 36)(pt 14 12)(line_width 1))(arc (pt 31 37) (pt 30 12) (rect 18 12 43 37) (line_width 1))))
|
||||
(symbol (rect 328 536 376 568)(text "NOT"(rect 1 -1 18 9)(font "Arial"(font_size 6)))(text "26"(rect 1 22 9 32)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 16)(input)(text "IN"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))(text "IN"(rect 0 6 10 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 13 16)(line_width 1)))
|
||||
(port (pt 48 16)(output)(text "OUT"(rect 41 6 46 18)(font "Courier New"(bold))(invisible))(text "OUT"(rect 41 6 56 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 39 16)(pt 48 16)(line_width 1)))
|
||||
(drawing (text "2"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 13 25)(pt 13 7)(line_width 1))
|
||||
(line (pt 13 7)(pt 31 16)(line_width 1))
|
||||
(line (pt 13 25)(pt 31 16)(line_width 1))(circle (rect 31 12 39 20)(line_width 1))))
|
||||
(symbol (rect 256 576 304 608)(text "NOT"(rect 1 -1 18 9)(font "Arial"(font_size 6)))(text "25"(rect 1 22 9 32)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 16)(input)(text "IN"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))(text "IN"(rect 0 6 10 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 13 16)(line_width 1)))
|
||||
(port (pt 48 16)(output)(text "OUT"(rect 41 6 46 18)(font "Courier New"(bold))(invisible))(text "OUT"(rect 41 6 56 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 39 16)(pt 48 16)(line_width 1)))
|
||||
(drawing (text "2"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 13 25)(pt 13 7)(line_width 1))
|
||||
(line (pt 13 7)(pt 31 16)(line_width 1))
|
||||
(line (pt 13 25)(pt 31 16)(line_width 1))(circle (rect 31 12 39 20)(line_width 1))))
|
||||
(symbol (rect 256 680 304 712)(text "NOT"(rect 1 -1 18 9)(font "Arial"(font_size 6)))(text "24"(rect 1 22 9 32)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 16)(input)(text "IN"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))(text "IN"(rect 0 6 10 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 13 16)(line_width 1)))
|
||||
(port (pt 48 16)(output)(text "OUT"(rect 41 6 46 18)(font "Courier New"(bold))(invisible))(text "OUT"(rect 41 6 56 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 39 16)(pt 48 16)(line_width 1)))
|
||||
(drawing (text "2"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 13 25)(pt 13 7)(line_width 1))
|
||||
(line (pt 13 7)(pt 31 16)(line_width 1))
|
||||
(line (pt 13 25)(pt 31 16)(line_width 1))(circle (rect 31 12 39 20)(line_width 1))))
|
||||
(symbol (rect 256 224 304 256)(text "NOT"(rect 1 -1 18 9)(font "Arial"(font_size 6)))(text "15"(rect 1 22 9 32)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 16)(input)(text "IN"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))(text "IN"(rect 0 6 10 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 13 16)(line_width 1)))
|
||||
(port (pt 48 16)(output)(text "OUT"(rect 41 6 46 18)(font "Courier New"(bold))(invisible))(text "OUT"(rect 41 6 56 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 39 16)(pt 48 16)(line_width 1)))
|
||||
(drawing (text "2"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 13 25)(pt 13 7)(line_width 1))
|
||||
(line (pt 13 7)(pt 31 16)(line_width 1))
|
||||
(line (pt 13 25)(pt 31 16)(line_width 1))(circle (rect 31 12 39 20)(line_width 1))))
|
||||
(symbol (rect 256 120 304 152)(text "NOT"(rect 1 -1 18 9)(font "Arial"(font_size 6)))(text "14"(rect 1 22 9 32)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 16)(input)(text "IN"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))(text "IN"(rect 0 6 10 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 13 16)(line_width 1)))
|
||||
(port (pt 48 16)(output)(text "OUT"(rect 41 6 46 18)(font "Courier New"(bold))(invisible))(text "OUT"(rect 41 6 56 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 39 16)(pt 48 16)(line_width 1)))
|
||||
(drawing (text "2"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 13 25)(pt 13 7)(line_width 1))
|
||||
(line (pt 13 7)(pt 31 16)(line_width 1))
|
||||
(line (pt 13 25)(pt 31 16)(line_width 1))(circle (rect 31 12 39 20)(line_width 1))))
|
||||
(symbol (rect 328 80 376 112)(text "NOT"(rect 1 -1 18 9)(font "Arial"(font_size 6)))(text "2"(rect 1 22 5 32)(font "Arial"(font_size 6)))
|
||||
(port (pt 0 16)(input)(text "IN"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))(text "IN"(rect 0 6 10 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 0 16)(pt 13 16)(line_width 1)))
|
||||
(port (pt 48 16)(output)(text "OUT"(rect 41 6 46 18)(font "Courier New"(bold))(invisible))(text "OUT"(rect 41 6 56 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 39 16)(pt 48 16)(line_width 1)))
|
||||
(drawing (text "2"(rect 0 6 5 18)(font "Courier New"(bold))(invisible))
|
||||
(line (pt 13 25)(pt 13 7)(line_width 1))
|
||||
(line (pt 13 7)(pt 31 16)(line_width 1))
|
||||
(line (pt 13 25)(pt 31 16)(line_width 1))(circle (rect 31 12 39 20)(line_width 1))))
|
||||
(connector (pt 240 496)(pt 520 496))
|
||||
(connector (pt 240 432)(pt 328 432))
|
||||
(connector (pt 216 424)(pt 248 424))
|
||||
(connector (pt 224 416)(pt 248 416))
|
||||
(connector (pt 232 408)(pt 248 408))
|
||||
(connector (pt 232 384)(pt 520 384))
|
||||
(connector (pt 232 320)(pt 328 320))
|
||||
(connector (pt 312 416)(pt 328 416))
|
||||
(connector (pt 392 424)(pt 440 424))
|
||||
(connector (pt 424 440)(pt 440 440))
|
||||
(connector (pt 416 488)(pt 472 488))
|
||||
(connector (pt 424 328)(pt 440 328))
|
||||
(connector (pt 416 376)(pt 472 376))
|
||||
(connector (pt 216 296)(pt 248 296))
|
||||
(connector (pt 224 64)(pt 520 64))
|
||||
(connector (pt 224 312)(pt 248 312))
|
||||
(connector (pt 312 304)(pt 328 304))
|
||||
(connector (pt 392 312)(pt 440 312))
|
||||
(connector (pt 504 312)(pt 520 312))
|
||||
(connector (pt 376 96)(pt 440 96))
|
||||
(connector (pt 224 96)(pt 328 96))
|
||||
(connector (pt 216 208)(pt 328 208))
|
||||
(connector (pt 216 272)(pt 520 272))
|
||||
(connector (pt 504 200)(pt 520 200))
|
||||
(connector (pt 224 192)(pt 328 192))
|
||||
(connector (pt 504 96)(pt 520 96))
|
||||
(connector (pt 424 112)(pt 440 112))
|
||||
(connector (pt 416 168)(pt 472 168))
|
||||
(connector (pt 392 200)(pt 440 200))
|
||||
(connector (pt 416 264)(pt 472 264))
|
||||
(connector (pt 424 216)(pt 440 216))
|
||||
(connector (pt 176 136)(pt 256 136))
|
||||
(connector (pt 304 136)(pt 424 136))
|
||||
(connector (pt 176 240)(pt 256 240))
|
||||
(connector (pt 304 240)(pt 416 240))
|
||||
(connector (pt 520 96)(pt 536 96))
|
||||
(connector (pt 520 200)(pt 536 200))
|
||||
(connector (pt 520 312)(pt 536 312))
|
||||
(connector (pt 520 424)(pt 536 424))
|
||||
(connector (pt 504 424)(pt 520 424))
|
||||
(connector (pt 504 880)(pt 520 880))
|
||||
(connector (pt 520 880)(pt 536 880))
|
||||
(connector (pt 520 768)(pt 536 768))
|
||||
(connector (pt 520 656)(pt 536 656))
|
||||
(connector (pt 520 552)(pt 536 552))
|
||||
(connector (pt 304 696)(pt 416 696))
|
||||
(connector (pt 176 696)(pt 256 696))
|
||||
(connector (pt 304 592)(pt 424 592))
|
||||
(connector (pt 176 592)(pt 256 592))
|
||||
(connector (pt 424 672)(pt 440 672))
|
||||
(connector (pt 416 720)(pt 472 720))
|
||||
(connector (pt 392 656)(pt 440 656))
|
||||
(connector (pt 416 624)(pt 472 624))
|
||||
(connector (pt 424 568)(pt 440 568))
|
||||
(connector (pt 504 552)(pt 520 552))
|
||||
(connector (pt 224 648)(pt 328 648))
|
||||
(connector (pt 504 656)(pt 520 656))
|
||||
(connector (pt 216 728)(pt 520 728))
|
||||
(connector (pt 216 664)(pt 328 664))
|
||||
(connector (pt 224 552)(pt 328 552))
|
||||
(connector (pt 376 552)(pt 440 552))
|
||||
(connector (pt 504 768)(pt 520 768))
|
||||
(connector (pt 392 768)(pt 440 768))
|
||||
(connector (pt 312 760)(pt 328 760))
|
||||
(connector (pt 224 768)(pt 248 768))
|
||||
(connector (pt 224 520)(pt 520 520))
|
||||
(connector (pt 216 752)(pt 248 752))
|
||||
(connector (pt 416 832)(pt 472 832))
|
||||
(connector (pt 424 784)(pt 440 784))
|
||||
(connector (pt 416 944)(pt 472 944))
|
||||
(connector (pt 424 896)(pt 440 896))
|
||||
(connector (pt 392 880)(pt 440 880))
|
||||
(connector (pt 312 872)(pt 328 872))
|
||||
(connector (pt 232 776)(pt 328 776))
|
||||
(connector (pt 232 840)(pt 520 840))
|
||||
(connector (pt 232 864)(pt 248 864))
|
||||
(connector (pt 224 872)(pt 248 872))
|
||||
(connector (pt 216 880)(pt 248 880))
|
||||
(connector (pt 240 888)(pt 328 888))
|
||||
(connector (pt 240 952)(pt 520 952))
|
||||
(connector (pt 416 696)(pt 416 624))
|
||||
(connector (pt 416 720)(pt 416 696))
|
||||
(connector (pt 472 720)(pt 472 712))
|
||||
(connector (pt 472 624)(pt 472 608))
|
||||
(connector (pt 424 592)(pt 424 568))
|
||||
(connector (pt 424 672)(pt 424 592))
|
||||
(connector (pt 216 728)(pt 216 664))
|
||||
(connector (pt 224 768)(pt 224 648))
|
||||
(connector (pt 224 648)(pt 224 552))
|
||||
(connector (pt 224 552)(pt 224 520))
|
||||
(connector (pt 216 752)(pt 216 728))
|
||||
(connector (pt 472 832)(pt 472 824))
|
||||
(connector (pt 424 784)(pt 424 672))
|
||||
(connector (pt 416 832)(pt 416 720))
|
||||
(connector (pt 416 944)(pt 416 832))
|
||||
(connector (pt 472 944)(pt 472 936))
|
||||
(connector (pt 424 896)(pt 424 784))
|
||||
(connector (pt 232 840)(pt 232 776))
|
||||
(connector (pt 232 864)(pt 232 840))
|
||||
(connector (pt 224 872)(pt 224 768))
|
||||
(connector (pt 216 880)(pt 216 752))
|
||||
(connector (pt 240 952)(pt 240 888))
|
||||
(connector (pt 240 496)(pt 240 432))
|
||||
(connector (pt 216 424)(pt 216 296))
|
||||
(connector (pt 224 416)(pt 224 312))
|
||||
(connector (pt 232 408)(pt 232 384))
|
||||
(connector (pt 232 384)(pt 232 320))
|
||||
(connector (pt 424 440)(pt 424 328))
|
||||
(connector (pt 472 488)(pt 472 480))
|
||||
(connector (pt 416 488)(pt 416 376))
|
||||
(connector (pt 416 376)(pt 416 264))
|
||||
(connector (pt 424 328)(pt 424 216))
|
||||
(connector (pt 472 376)(pt 472 368))
|
||||
(connector (pt 216 296)(pt 216 272))
|
||||
(connector (pt 224 96)(pt 224 64))
|
||||
(connector (pt 224 192)(pt 224 96))
|
||||
(connector (pt 224 312)(pt 224 192))
|
||||
(connector (pt 216 272)(pt 216 208))
|
||||
(connector (pt 424 216)(pt 424 136))
|
||||
(connector (pt 424 136)(pt 424 112))
|
||||
(connector (pt 472 168)(pt 472 152))
|
||||
(connector (pt 472 264)(pt 472 256))
|
||||
(connector (pt 416 264)(pt 416 240))
|
||||
(connector (pt 416 240)(pt 416 168))
|
||||
(connector (pt 520 552)(pt 520 520))
|
||||
(connector (pt 520 728)(pt 520 656))
|
||||
(connector (pt 520 840)(pt 520 768))
|
||||
(connector (pt 520 952)(pt 520 880))
|
||||
(connector (pt 520 496)(pt 520 424))
|
||||
(connector (pt 520 384)(pt 520 312))
|
||||
(connector (pt 520 272)(pt 520 200))
|
||||
(connector (pt 520 96)(pt 520 64))
|
||||
(junction (pt 232 384))
|
||||
(junction (pt 424 328))
|
||||
(junction (pt 416 376))
|
||||
(junction (pt 216 296))
|
||||
(junction (pt 224 312))
|
||||
(junction (pt 520 312))
|
||||
(junction (pt 224 96))
|
||||
(junction (pt 216 272))
|
||||
(junction (pt 520 200))
|
||||
(junction (pt 224 192))
|
||||
(junction (pt 520 96))
|
||||
(junction (pt 416 264))
|
||||
(junction (pt 424 216))
|
||||
(junction (pt 424 136))
|
||||
(junction (pt 416 240))
|
||||
(junction (pt 520 424))
|
||||
(junction (pt 520 880))
|
||||
(junction (pt 520 768))
|
||||
(junction (pt 520 656))
|
||||
(junction (pt 520 552))
|
||||
(junction (pt 416 696))
|
||||
(junction (pt 424 592))
|
||||
(junction (pt 424 672))
|
||||
(junction (pt 416 720))
|
||||
(junction (pt 224 648))
|
||||
(junction (pt 216 728))
|
||||
(junction (pt 224 552))
|
||||
(junction (pt 224 768))
|
||||
(junction (pt 216 752))
|
||||
(junction (pt 416 832))
|
||||
(junction (pt 424 784))
|
||||
(junction (pt 232 840))
|
||||
190
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS393.v
Normal file
190
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS393.v
Normal file
@@ -0,0 +1,190 @@
|
||||
module SN74LS393(
|
||||
input A2, //01
|
||||
input CLR2, //02
|
||||
output Q2A, //03
|
||||
output Q2B, //04
|
||||
output Q2C, //05
|
||||
output Q2D, //06
|
||||
|
||||
output Q1D, //03
|
||||
output Q1C, //09
|
||||
output Q1B, //10
|
||||
output Q1A, //11
|
||||
input CLR1, //12
|
||||
input A1 //01
|
||||
);
|
||||
|
||||
wire SYNTHESIZED_WIRE_28;
|
||||
wire SYNTHESIZED_WIRE_29;
|
||||
wire SYNTHESIZED_WIRE_2;
|
||||
wire SYNTHESIZED_WIRE_3;
|
||||
reg DFF_9;
|
||||
reg SYNTHESIZED_WIRE_30;
|
||||
reg SYNTHESIZED_WIRE_31;
|
||||
reg SYNTHESIZED_WIRE_32;
|
||||
reg SYNTHESIZED_WIRE_33;
|
||||
reg SYNTHESIZED_WIRE_34;
|
||||
wire SYNTHESIZED_WIRE_35;
|
||||
wire SYNTHESIZED_WIRE_36;
|
||||
wire SYNTHESIZED_WIRE_6;
|
||||
wire SYNTHESIZED_WIRE_9;
|
||||
wire SYNTHESIZED_WIRE_12;
|
||||
wire SYNTHESIZED_WIRE_15;
|
||||
wire SYNTHESIZED_WIRE_18;
|
||||
wire SYNTHESIZED_WIRE_19;
|
||||
reg SYNTHESIZED_WIRE_37;
|
||||
wire SYNTHESIZED_WIRE_20;
|
||||
reg DFF_31;
|
||||
wire SYNTHESIZED_WIRE_23;
|
||||
wire SYNTHESIZED_WIRE_24;
|
||||
wire SYNTHESIZED_WIRE_27;
|
||||
|
||||
assign Q2A = SYNTHESIZED_WIRE_33;
|
||||
assign Q2B = SYNTHESIZED_WIRE_34;
|
||||
assign Q2C = SYNTHESIZED_WIRE_37;
|
||||
assign Q2D = DFF_31;
|
||||
assign Q1D = DFF_9;
|
||||
assign Q1C = SYNTHESIZED_WIRE_32;
|
||||
assign Q1B = SYNTHESIZED_WIRE_30;
|
||||
assign Q1A = SYNTHESIZED_WIRE_31;
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_28)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_28)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_31 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
SYNTHESIZED_WIRE_31 <= SYNTHESIZED_WIRE_2;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_27 = SYNTHESIZED_WIRE_3 ^ DFF_9;
|
||||
|
||||
assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31 & SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_29 = ~A1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_28 = ~CLR1;
|
||||
|
||||
assign SYNTHESIZED_WIRE_2 = ~SYNTHESIZED_WIRE_31;
|
||||
|
||||
assign SYNTHESIZED_WIRE_35 = ~CLR2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_36 = ~A2;
|
||||
|
||||
assign SYNTHESIZED_WIRE_6 = ~SYNTHESIZED_WIRE_33;
|
||||
|
||||
assign SYNTHESIZED_WIRE_19 = SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_33;
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_36 or negedge SYNTHESIZED_WIRE_35)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_35)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_33 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
SYNTHESIZED_WIRE_33 <= SYNTHESIZED_WIRE_6;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_36 or negedge SYNTHESIZED_WIRE_35)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_35)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_34 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
SYNTHESIZED_WIRE_34 <= SYNTHESIZED_WIRE_9;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_28)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_28)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_30 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
SYNTHESIZED_WIRE_30 <= SYNTHESIZED_WIRE_12;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_36 or negedge SYNTHESIZED_WIRE_35)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_35)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_37 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
SYNTHESIZED_WIRE_37 <= SYNTHESIZED_WIRE_15;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_36 or negedge SYNTHESIZED_WIRE_35)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_35)
|
||||
begin
|
||||
DFF_31 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_31 <= SYNTHESIZED_WIRE_18;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_33 ^ SYNTHESIZED_WIRE_34;
|
||||
|
||||
assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_19 ^ SYNTHESIZED_WIRE_37;
|
||||
|
||||
assign SYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_20 ^ DFF_31;
|
||||
|
||||
assign SYNTHESIZED_WIRE_20 = SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_33 & SYNTHESIZED_WIRE_37;
|
||||
|
||||
assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_31 ^ SYNTHESIZED_WIRE_30;
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_28)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_28)
|
||||
begin
|
||||
SYNTHESIZED_WIRE_32 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
SYNTHESIZED_WIRE_32 <= SYNTHESIZED_WIRE_23;
|
||||
end
|
||||
end
|
||||
|
||||
assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_24 ^ SYNTHESIZED_WIRE_32;
|
||||
|
||||
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;
|
||||
|
||||
|
||||
always@(posedge SYNTHESIZED_WIRE_29 or negedge SYNTHESIZED_WIRE_28)
|
||||
begin
|
||||
if (!SYNTHESIZED_WIRE_28)
|
||||
begin
|
||||
DFF_9 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DFF_9 <= SYNTHESIZED_WIRE_27;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
46
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS73.v
Normal file
46
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS73.v
Normal file
@@ -0,0 +1,46 @@
|
||||
module SN74LS73(
|
||||
input clk1, //01
|
||||
input clrn1, //02
|
||||
input k1, //03
|
||||
|
||||
input clk2, //05
|
||||
input clrn2, //06
|
||||
input j2, //07
|
||||
output qn2, //08
|
||||
output reg q2, //09
|
||||
input k2, //10
|
||||
|
||||
output reg q1, //12
|
||||
output qn1, //13
|
||||
input j1 //14
|
||||
);
|
||||
|
||||
always@(posedge clk1 or negedge clrn1)
|
||||
begin
|
||||
if (!clrn1)
|
||||
begin
|
||||
q1 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
q1 <= ~q1 & j1 | q1 & ~k1;
|
||||
end
|
||||
end
|
||||
|
||||
assign qn1 = ~q1;
|
||||
|
||||
always@(posedge clk2 or negedge clrn2)
|
||||
begin
|
||||
if (!clrn2)
|
||||
begin
|
||||
q2 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
q2 <= ~q2 & j2 | q2 & ~k2;
|
||||
end
|
||||
end
|
||||
|
||||
assign qn2 = ~q2;
|
||||
|
||||
endmodule
|
||||
57
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS74.v
Normal file
57
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS74.v
Normal file
@@ -0,0 +1,57 @@
|
||||
module SN74LS74(
|
||||
input clrn1, //01
|
||||
input d1, //02
|
||||
input clk1, //03
|
||||
input prn1, //04
|
||||
output reg q1, //05
|
||||
output qn1, //06
|
||||
|
||||
output qn2, //08
|
||||
output reg q2, //09
|
||||
input prn2, //10
|
||||
input clk2, //11
|
||||
input d2, //12
|
||||
input clrn2 //13
|
||||
);
|
||||
|
||||
|
||||
|
||||
always@(posedge clk1 or negedge clrn1 or negedge prn1)
|
||||
begin
|
||||
if (!clrn1)
|
||||
begin
|
||||
q1 <= 0;
|
||||
end
|
||||
else
|
||||
if (!prn1)
|
||||
begin
|
||||
q1 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
q1 <= d1;
|
||||
end
|
||||
end
|
||||
|
||||
assign qn1 = ~q1;
|
||||
|
||||
always@(posedge clk2 or negedge clrn2 or negedge prn2)
|
||||
begin
|
||||
if (!clrn2)
|
||||
begin
|
||||
q2 <= 0;
|
||||
end
|
||||
else
|
||||
if (!prn2)
|
||||
begin
|
||||
q2 <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
q2 <= d2;
|
||||
end
|
||||
end
|
||||
|
||||
assign qn2 = ~q2;
|
||||
|
||||
endmodule
|
||||
63
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS92.v
Normal file
63
Computer_MiST/Interact_MiST/rtl/ttl/SN74LS92.v
Normal file
@@ -0,0 +1,63 @@
|
||||
module SN74LS92(
|
||||
input clkb, //01
|
||||
input clra, //06
|
||||
input clrb, //07
|
||||
output reg qd, //08
|
||||
output reg qc, //09
|
||||
output reg qa, //12
|
||||
output reg qb, //13
|
||||
input clka //14
|
||||
);
|
||||
|
||||
wire reset;
|
||||
assign reset = clra & clrb;
|
||||
|
||||
always@(negedge clka or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
qa <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
qa <= ~qa;
|
||||
end
|
||||
end
|
||||
|
||||
always@(negedge clkb or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
qb <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
qb <= ~(qb | qc);
|
||||
end
|
||||
end
|
||||
|
||||
always@(negedge clkb or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
qc <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
qc <= qb;
|
||||
end
|
||||
end
|
||||
|
||||
always@(negedge clkb or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
qd <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
qd <= qd ^ qc;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
281
Computer_MiST/Interact_MiST/rtl/video_timing.v
Normal file
281
Computer_MiST/Interact_MiST/rtl/video_timing.v
Normal file
@@ -0,0 +1,281 @@
|
||||
// Video timings for Interact Model One based on sheet #2 of the Interact I Main Electronics Schematics
|
||||
// Tries as much as possible to map modules to physical ICs on the original schematics
|
||||
|
||||
module video_timing (
|
||||
input clk_14m, // 14.38180 MHz Clock
|
||||
input rst_n, // active low reset
|
||||
output ph1, // CPU phase1 clock for 8080a
|
||||
output ph2, // CPU phase2 clock
|
||||
output cbclk, // colorburst clock
|
||||
output pix_a, // pixel select
|
||||
output reg vid_sel, // video select
|
||||
output reg [11:0] vid_addr,
|
||||
output vid_sel_n, // video select low
|
||||
input nrr_n, // refresh
|
||||
output ce_n, // RAS#
|
||||
output pce, // video data latch enable
|
||||
output vid_ltc, // video latch/pixel clock
|
||||
output ram_clk, // ram clock
|
||||
output brst, // color burst enable
|
||||
output reg tpclk, // tape clock, once per scanline
|
||||
output cmp_blank, // composite blank
|
||||
output irq, // interrupt request low
|
||||
input inte, // interrupt enable
|
||||
output cmp_sync, // composite sync
|
||||
output hblank_n, // horizontal blank
|
||||
output vblank_n, // vertical blank
|
||||
output hsync_n, // horizontal sync
|
||||
output vsync_n // vertical sync
|
||||
);
|
||||
|
||||
wire ic15_qb;
|
||||
wire ic15_qc;
|
||||
wire ic15_qdn;
|
||||
|
||||
wire ic16_qa;
|
||||
wire ic16_qc;
|
||||
|
||||
wire ic18_q1;
|
||||
wire vclk_n;
|
||||
wire vclk;
|
||||
|
||||
wire vreset_n;
|
||||
|
||||
wire ic20_d1;
|
||||
|
||||
wire hblank_en;
|
||||
|
||||
wire brst_n;
|
||||
wire hreset_n;
|
||||
|
||||
wire ic24_q;
|
||||
|
||||
SN74LS195 IC15(
|
||||
.clk(clk_14m),
|
||||
.clrn(rst_n),
|
||||
.j(ic15_qdn),
|
||||
.kn(ic15_qdn),
|
||||
.sh_ldn(~(ic16_qa & ic16_qc & pix_a & vid_sel)),
|
||||
.a(0),
|
||||
.b(0),
|
||||
.c(0),
|
||||
.d(0),
|
||||
|
||||
.qb(ic15_qb),
|
||||
.qc(ic15_qc),
|
||||
.qd(ph2),
|
||||
.qdn(ic15_qdn));
|
||||
|
||||
assign ph1 = ic15_qb & ~ic15_qc;
|
||||
|
||||
|
||||
SN74LS92 IC16(
|
||||
.clka(~clk_14m),
|
||||
.clra(~rst_n),
|
||||
.clkb(ic16_qa),
|
||||
.clrb(~rst_n),
|
||||
|
||||
.qa(ic16_qa),
|
||||
.qb(vid_ltc),
|
||||
.qc(ic16_qc),
|
||||
.qd(pix_a));
|
||||
|
||||
|
||||
SN74LS74 IC20(
|
||||
.clk1(ic16_qa),
|
||||
.clrn1(rst_n),
|
||||
.prn1(rst_n),
|
||||
.d1(ic20_d1),
|
||||
|
||||
.qn1(ic20_d1),
|
||||
.q1(cbclk),
|
||||
|
||||
|
||||
.clk2(vid_ltc & vid_sel & ~pix_a & vid_addr[0]),
|
||||
.clrn2(rst_n),
|
||||
.prn2(rst_n),
|
||||
.d2(hblank_en),
|
||||
|
||||
.q2(hblank_n)
|
||||
);
|
||||
|
||||
//dff IC20a(.clk(ic16_qa), .clrn(rst_n), .prn(rst_n), .d(~cbclk), .q(cbclk));
|
||||
|
||||
|
||||
//SN74LS393 IC17(
|
||||
// .a1(pix_a),
|
||||
// .clr1(~hreset_n | ~rst_n),
|
||||
// .a2(vid_a2),
|
||||
// .clr2(~hreset_n | ~rst_n),
|
||||
//
|
||||
// .q1a(vid_sel),
|
||||
// .q1b(vid_a0),
|
||||
// .q1c(vid_a1),
|
||||
// .q1d(vid_a2),
|
||||
// .q2a(vid_a3),
|
||||
// .q2b(vid_a4),
|
||||
// .q2c(tpclk));
|
||||
|
||||
wire hclr = ~hreset_n | ~rst_n;
|
||||
always@(negedge pix_a or posedge hclr)
|
||||
begin
|
||||
if (hclr)
|
||||
begin
|
||||
{tpclk, vid_addr[4:0], vid_sel} <= 7'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
{tpclk, vid_addr[4:0], vid_sel} <= {tpclk, vid_addr[4:0], vid_sel} + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign vid_sel_n = ~vid_sel;
|
||||
|
||||
// SR Latch just not stable in simulation and probably no better in synthesis
|
||||
//
|
||||
//SN7LS279 IC21 (
|
||||
// .r1n(),
|
||||
// .s11n(),
|
||||
// .s12n(),
|
||||
// .q1(),
|
||||
//
|
||||
// .r2n(~(vid_addr[5] & vid_addr[6] & vid_addr[11]) & rst_n),
|
||||
// .s2n(vreset_n),
|
||||
// .q2(vblank_n),
|
||||
//
|
||||
// .r3n(~(vid_addr[2] & vid_addr[3] & vid_addr[4]) & rst_n),
|
||||
// .s31n(hreset_n),
|
||||
// .s32n(hreset_n),
|
||||
// .q3(hblank_en),
|
||||
//
|
||||
// .r4n(),
|
||||
// .s4n(),
|
||||
// .q4()
|
||||
//);
|
||||
|
||||
// Substitute SR Flip-Flop for SR Latch, address signals only change on master clock anyway
|
||||
|
||||
srff IC21b (
|
||||
.s(1'b0),
|
||||
.r(vid_addr[5] & vid_addr[6] & vid_addr[11] & rst_n),
|
||||
.clk(clk_14m),
|
||||
.clrn(1'b1),
|
||||
.prn(vreset_n),
|
||||
.q(vblank_n)
|
||||
);
|
||||
|
||||
srff IC21c (
|
||||
.s(1'b0),
|
||||
.r(vid_addr[2] & vid_addr[3] & vid_addr[4] & rst_n),
|
||||
.clk(clk_14m),
|
||||
.clrn(1'b1),
|
||||
.prn(hreset_n),
|
||||
.q(hblank_en)
|
||||
);
|
||||
|
||||
assign cmp_blank = ~(vblank_n & hblank_n);
|
||||
|
||||
SN74LS138 IC22 (
|
||||
.a(vid_addr[1]),
|
||||
.b(vid_addr[2]),
|
||||
.c(vid_addr[3]),
|
||||
.g1(1'b1),
|
||||
.g2an(hblank_en),
|
||||
.g2bn(hblank_en),
|
||||
.y0n(hsync_n),
|
||||
.y1n(brst_n),
|
||||
.y2n(),
|
||||
.y3n(hreset_n),
|
||||
.y4n(),
|
||||
.y5n(),
|
||||
.y6n(),
|
||||
.y7n()
|
||||
);
|
||||
|
||||
assign brst = ~brst_n;
|
||||
|
||||
SN74LS73 IC18 (
|
||||
.clk1(tpclk),
|
||||
.j1(vclk_n),
|
||||
.k1(1'b1),
|
||||
.clrn1(vreset_n & rst_n),
|
||||
.q1(ic18_q1),
|
||||
|
||||
.clk2(tpclk),
|
||||
.j2(ic18_q1),
|
||||
.k2(1'b1),
|
||||
.clrn2(vreset_n & rst_n),
|
||||
.q2(vclk),
|
||||
.qn2(vclk_n));
|
||||
|
||||
//jkff IC18a (.clk(tpclk), .j(~vclk), .k(1'b1), .clrn(vreset_n & rst_n), .prn(rst_n), .q(ic18_q1));
|
||||
//jkff IC18b (.clk(tpclk), .j(ic18_q1), .k(1'b1), .clrn(vreset_n & rst_n), .prn(rst_n), .q(vclk));
|
||||
|
||||
//SN74LS393 IC19(
|
||||
// .a1(vclk),
|
||||
// .clr1(~vreset_n | ~rst_n),
|
||||
// .a2(vid_a8),
|
||||
// .clr2(~vreset_n | ~rst_n),
|
||||
//
|
||||
// .q1a(vid_a5),
|
||||
// .q1b(vid_a6),
|
||||
// .q1c(vid_a7),
|
||||
// .q1d(vid_a8),
|
||||
// .q2a(vid_a9),
|
||||
// .q2b(vid_a10),
|
||||
// .q2c(vid_a11));
|
||||
|
||||
wire vclr = ~vreset_n | ~rst_n;
|
||||
always@(negedge vclk or posedge vclr)
|
||||
begin
|
||||
if (vclr)
|
||||
begin
|
||||
vid_addr[11:5] <= 7'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
vid_addr[11:5] <= vid_addr[11:5] + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign vreset_n = (~(vid_addr[5] & vid_addr[6] & vid_addr[7])) | (~(ic18_q1 & vid_addr[9] & vid_addr[11]));
|
||||
|
||||
assign vsync_n = ((vid_addr[6] | vid_addr[7]) | ~(vid_addr[9] & vid_addr[11]));
|
||||
assign cmp_sync = !(vsync_n & hsync_n);
|
||||
|
||||
dff IC24(
|
||||
.d(1'b0),
|
||||
.q(ic24_q),
|
||||
.clk(~vblank_n),
|
||||
.prn(inte),
|
||||
.clrn(rst_n)
|
||||
);
|
||||
|
||||
assign irq = ~ic24_q;
|
||||
|
||||
wire ce;
|
||||
wire nrr_en = ~(~(nrr_n | ~vid_sel) & pix_a & vid_ltc);
|
||||
srff IC21a (
|
||||
.s(1'b0),
|
||||
.r(ic16_qc & ~pix_a),
|
||||
.clk(clk_14m),
|
||||
.clrn(1'b1),
|
||||
.prn(~(~vid_sel & pix_a & vid_ltc) & nrr_en & rst_n),
|
||||
.q(ce)
|
||||
);
|
||||
|
||||
srff IC21d (
|
||||
.s(1'b0),
|
||||
.r(ic16_qc & ~pix_a),
|
||||
.clk(clk_14m),
|
||||
.clrn(1'b1),
|
||||
.prn(nrr_en & rst_n),
|
||||
.q(pce)
|
||||
);
|
||||
|
||||
assign ce_n = ~ce;
|
||||
|
||||
assign ram_clk = ~pix_a & pce;
|
||||
|
||||
endmodule
|
||||
955
Computer_MiST/Interact_MiST/rtl/vm80a.v
Normal file
955
Computer_MiST/Interact_MiST/rtl/vm80a.v
Normal file
@@ -0,0 +1,955 @@
|
||||
//
|
||||
// Copyright (c) 2014-2018 by 1801BM1@gmail.com
|
||||
// Licensed under CC-BY 3.0 (https://creativecommons.org/licenses/by/3.0/)
|
||||
//
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// vm80a wrapper for direct replacement of microprocessor package
|
||||
// extra high-speed clock should be provided to operate, F1 and F2
|
||||
// phases serve as clock enable gates
|
||||
//
|
||||
module vm80a
|
||||
(
|
||||
input pin_clk, // global module clock (no in original 8080)
|
||||
input pin_f1, // clock phase 1 (used as clock enable)
|
||||
input pin_f2, // clock phase 2 (used as clock enable)
|
||||
input pin_reset, // module reset
|
||||
output[15:0] pin_a, // address bus outputs
|
||||
inout [7:0] pin_d, // data bus inouts
|
||||
input pin_hold, //
|
||||
output pin_hlda, //
|
||||
input pin_ready, //
|
||||
output pin_wait, //
|
||||
input pin_int, //
|
||||
output pin_inte, //
|
||||
output pin_sync, //
|
||||
output pin_dbin, //
|
||||
output pin_wr_n
|
||||
);
|
||||
|
||||
wire pin_aena, pin_dena;
|
||||
wire [7:0] pin_din, pin_dout;
|
||||
wire [15:0] pin_addr;
|
||||
reg f1_core, f2_core;
|
||||
|
||||
assign pin_a = pin_aena ? pin_addr : 16'hZZZZ;
|
||||
assign pin_d = pin_dena ? pin_dout : 8'hZZ;
|
||||
assign pin_din = pin_d;
|
||||
|
||||
always @(posedge pin_clk)
|
||||
begin
|
||||
f1_core <= pin_f1;
|
||||
f2_core <= pin_f2;
|
||||
end
|
||||
|
||||
vm80a_core core
|
||||
(
|
||||
.pin_clk (pin_clk),
|
||||
.pin_f1 (f1_core),
|
||||
.pin_f2 (f2_core),
|
||||
.pin_reset (pin_reset),
|
||||
.pin_a (pin_addr),
|
||||
.pin_dout (pin_dout),
|
||||
.pin_din (pin_din),
|
||||
.pin_aena (pin_aena),
|
||||
.pin_dena (pin_dena),
|
||||
.pin_hold (pin_hold),
|
||||
.pin_hlda (pin_hlda),
|
||||
.pin_ready (pin_ready),
|
||||
.pin_wait (pin_wait),
|
||||
.pin_int (pin_int),
|
||||
.pin_inte (pin_inte),
|
||||
.pin_sync (pin_sync),
|
||||
.pin_dbin (pin_dbin),
|
||||
.pin_wr_n (pin_wr_n)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module vm80a_core
|
||||
(
|
||||
input pin_clk, // global module clock (no in original 8080)
|
||||
input pin_f1, // clock phase 1 (used as clock enable)
|
||||
input pin_f2, // clock phase 2 (used as clock enable)
|
||||
input pin_reset, // module reset
|
||||
output[15:0] pin_a, // address bus outputs
|
||||
output[7:0] pin_dout, // data bus output
|
||||
input [7:0] pin_din, // data bus input
|
||||
output pin_aena, // address outputs enable
|
||||
output pin_dena, // data outputs enable
|
||||
input pin_hold, //
|
||||
output pin_hlda, //
|
||||
input pin_ready, //
|
||||
output pin_wait, //
|
||||
input pin_int, //
|
||||
output pin_inte, //
|
||||
output pin_sync, //
|
||||
output pin_dbin, //
|
||||
output pin_wr_n
|
||||
);
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
wire [7:0] d;
|
||||
reg [7:0] db, di;
|
||||
reg [15:0] a;
|
||||
wire clk, f1, f2;
|
||||
reg abufena, db_ena, db_stb, dbin_pin, dbin_ext;
|
||||
reg reset;
|
||||
wire ready;
|
||||
|
||||
reg t851, t404, t382, t383, t712, t735, t773;
|
||||
reg hold, hlda_pin;
|
||||
wire hlda, h889;
|
||||
|
||||
reg wr_n, t1124, t1011, sync;
|
||||
wire ready_int;
|
||||
|
||||
reg [15:0] r16_pc, r16_hl, r16_de, r16_bc, r16_sp, r16_wz, mxo;
|
||||
wire [15:0] mxi;
|
||||
wire mxr0, mxr1, mxr2, mxr3, mxr4, mxr5;
|
||||
wire mxwh, mxwl, mxrh, mxrl, mxw16, mxwadr;
|
||||
wire dec16, inc16, iad16;
|
||||
reg xchg_dh, xchg_tt, t3144;
|
||||
wire t1460, t1467, t1513, t1514, t1519;
|
||||
|
||||
wire sy_inta, sy_wo_n, sy_hlta, sy_out, sy_m1, sy_inp, sy_memr;
|
||||
reg sy_stack;
|
||||
|
||||
wire thalt, twt2;
|
||||
reg t1, t2, tw, t3, t4, t5;
|
||||
reg t1f1, t2f1, twf1, t3f1, t4f1, t5f1;
|
||||
reg m1, m2, m3, m4, m5;
|
||||
reg m1f1, m2f1, m3f1, m4f1, m5f1;
|
||||
|
||||
wire start, ms0, ms1, m836, m839, m871;
|
||||
reg eom, t789, t887, t953, t976, t980;
|
||||
|
||||
reg intr, inta, inte, mstart, minta;
|
||||
wire irq;
|
||||
|
||||
reg [7:0] i;
|
||||
reg i25, i14, i03;
|
||||
wire imx, acc_sel;
|
||||
wire id_op, id_io, id_in, id_popsw, id_pupsw,
|
||||
id_nop, id_lxi, id_inx, id_inr, id_dcr, id_idr, id_mvi, id_dad,
|
||||
id_dcx, id_opa, id_idm, id_hlt, id_mov, id_opm, id_pop, id_rst,
|
||||
id_cxx, id_jxx, id_rxx, id_ret, id_jmp, id_opi, id_out, id_11x,
|
||||
id_rlc, id_rxc, id_rar, id_sha, id_daa, id_cma, id_stc, id_cmc,
|
||||
id_add, id_adc, id_sub, id_sbb, id_ana, id_xra, id_ora, id_cmp,
|
||||
id_lsax, id_mvim, id_shld, id_lhld, id_mvmr, id_mvrm, id_push,
|
||||
id_xthl, id_sphl, id_pchl, id_xchg, id_call, id_eidi, id_stlda;
|
||||
|
||||
wire id80, id81, id82, id83, id84, id85, id86, id00, id01,
|
||||
id02, id03, id04, id05, id06, id07, id08, id09, id10;
|
||||
wire goto, jmpflag;
|
||||
reg jmptake, tree0, tree1, tree2;
|
||||
reg t2806, t2817, t2819, t3047, t2998, t3363, t3403, t3335, t3361;
|
||||
|
||||
reg [7:0] xr, r, acc;
|
||||
wire [7:0] x, s, c;
|
||||
wire cl, ch, daa, daa_6x, daa_x6;
|
||||
wire a398;
|
||||
reg a327, a357, a358;
|
||||
wire alu_xout, alu_xwr, alu_xrd, alu_ald, alu_awr, alu_ard,
|
||||
alu_rld, alu_r00, alu_rwr, alu_srd, alu_zrd, alu_frd;
|
||||
|
||||
reg psw_z, psw_s, psw_p, psw_c, psw_ac, tmp_c;
|
||||
reg t2222, t1375, t1497, t1698, t1668, t1780, t1993, t1994;
|
||||
reg psw_ld, psw_wr, t2046, t2133, t2175;
|
||||
|
||||
//_____________________________________________________________________________
|
||||
//
|
||||
assign clk = pin_clk;
|
||||
assign f1 = pin_f1;
|
||||
assign f2 = pin_f2;
|
||||
|
||||
assign pin_a = a;
|
||||
assign pin_aena = abufena;
|
||||
assign pin_dout = db;
|
||||
assign pin_dena = db_ena;
|
||||
|
||||
assign d[7] = ~reset & ~alu_zrd &
|
||||
( dbin_ext & di[7]
|
||||
| mxrl & mxo[7]
|
||||
| mxrh & mxo[15]
|
||||
| t1f1 & sy_memr
|
||||
| alu_xrd & xr[7]
|
||||
| alu_ard & acc[7]
|
||||
| alu_frd & psw_s
|
||||
| alu_srd & s[7] );
|
||||
|
||||
assign d[6] = ~reset & ~alu_zrd &
|
||||
( dbin_ext & di[6]
|
||||
| mxrl & mxo[6]
|
||||
| mxrh & mxo[14]
|
||||
| t1f1 & sy_inp
|
||||
| alu_xrd & xr[6]
|
||||
| alu_ard & acc[6]
|
||||
| alu_frd & psw_z
|
||||
| alu_srd & s[6] );
|
||||
|
||||
assign d[5] = ~reset & ~alu_zrd &
|
||||
( dbin_ext & di[5]
|
||||
| mxrl & mxo[5]
|
||||
| mxrh & mxo[13]
|
||||
| t1f1 & sy_m1
|
||||
| alu_xrd & xr[5]
|
||||
| alu_ard & acc[5]
|
||||
| alu_frd & 1'b0
|
||||
| alu_srd & s[5] );
|
||||
|
||||
assign d[4] = ~reset & ~alu_zrd &
|
||||
( dbin_ext & di[4]
|
||||
| mxrl & mxo[4]
|
||||
| mxrh & mxo[12]
|
||||
| t1f1 & sy_out
|
||||
| alu_xrd & xr[4]
|
||||
| alu_ard & acc[4]
|
||||
| alu_frd & psw_ac
|
||||
| alu_srd & s[4] );
|
||||
|
||||
assign d[3] = ~reset & ~alu_zrd &
|
||||
( dbin_ext & di[3]
|
||||
| mxrl & mxo[3]
|
||||
| mxrh & mxo[11]
|
||||
| t1f1 & sy_hlta
|
||||
| alu_xrd & xr[3]
|
||||
| alu_ard & acc[3]
|
||||
| alu_frd & 1'b0
|
||||
| alu_srd & s[3] );
|
||||
|
||||
assign d[2] = ~reset & ~alu_zrd &
|
||||
( dbin_ext & di[2]
|
||||
| mxrl & mxo[2]
|
||||
| mxrh & mxo[10]
|
||||
| t1f1 & sy_stack
|
||||
| alu_xrd & xr[2]
|
||||
| alu_ard & acc[2]
|
||||
| alu_frd & psw_p
|
||||
| alu_srd & s[2] );
|
||||
|
||||
assign d[1] = ~reset & ~alu_zrd &
|
||||
( dbin_ext & di[1]
|
||||
| mxrl & mxo[1]
|
||||
| mxrh & mxo[9]
|
||||
| t1f1 & sy_wo_n
|
||||
| alu_xrd & xr[1]
|
||||
| alu_ard & acc[1]
|
||||
| alu_frd & 1'b1
|
||||
| alu_srd & s[1] );
|
||||
|
||||
assign d[0] = ~reset & ~alu_zrd &
|
||||
( dbin_ext & di[0]
|
||||
| mxrl & mxo[0]
|
||||
| mxrh & mxo[8]
|
||||
| t1f1 & sy_inta
|
||||
| alu_xrd & xr[0]
|
||||
| alu_ard & acc[0]
|
||||
| alu_frd & psw_c
|
||||
| alu_srd & s[0] );
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f2 & db_stb) db <= d;
|
||||
if (f2) abufena <= (~twt2 | ~thalt) & ~hlda_pin;
|
||||
if (f1) db_stb <= t1 | (~sy_wo_n & t2);
|
||||
if (f1) t851 <= t1 | (~sy_wo_n & (t2 | tw | t3));
|
||||
if (f2) db_ena <= ~reset & t851;
|
||||
end
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// reset input buffer
|
||||
//
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f1) t404 <= pin_reset;
|
||||
if (f2) reset <= t404;
|
||||
end
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// hold input buffer
|
||||
//
|
||||
assign pin_hlda = hlda_pin;
|
||||
assign hlda = hold & (t773 | (t3 & sy_wo_n) | (~m1 & sy_hlta) | t735);
|
||||
assign h889 = t2f1 | twf1;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f1) t712 <= ~sy_wo_n & t3;
|
||||
if (f2) t735 <= t712;
|
||||
if (~f2) t382 <= pin_hold;
|
||||
if (f2) t383 <= ((~t382 & hold) | t383); // extend the front detector pulse for entire F2 duration
|
||||
if (~f2) t383 <= 1'b0;
|
||||
if (f2) t773 <= hlda_pin;
|
||||
if (f1) hlda_pin <= hlda;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (reset)
|
||||
hold <= 1'b0;
|
||||
else
|
||||
if (f2)
|
||||
begin
|
||||
if (t382)
|
||||
begin
|
||||
if (~sy_inta & h889) hold <= 1'b1;
|
||||
end
|
||||
else
|
||||
hold <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
assign pin_dbin = dbin_pin;
|
||||
assign pin_wr_n = wr_n;
|
||||
assign pin_sync = sync;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
dbin_ext <= (f2 | dbin_pin) & ((t1124 & (m1f1 | ~sy_hlta)) | dbin_ext);
|
||||
|
||||
if (dbin_pin) di <= pin_din;
|
||||
if (f2) dbin_pin <= t1124 & (m1f1 | ~sy_hlta);
|
||||
if (f2) sync <= ~ready_int & t1011;
|
||||
if (f1) t1011 <= t1 & ~reset;
|
||||
if (f1) t1124 <= (t2 | tw) & sy_wo_n;
|
||||
if (f1) wr_n <= ~(t3 | tw) | ready_int | sy_wo_n;
|
||||
end
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// ready pin and internal circuits
|
||||
//
|
||||
assign ready_int = (m4 | m5) & id_dad;
|
||||
assign ready = ready_int | pin_ready;
|
||||
assign pin_wait = twf1;
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// register unit - 6 16-bit registers
|
||||
//
|
||||
// r0 - pc
|
||||
// r1 - hl, de
|
||||
// r2 - de, hl
|
||||
// r3 - bc
|
||||
// r4 - sp
|
||||
// r5 - wz
|
||||
//
|
||||
assign t1467 = tree1 | (id04 & t4f1 & ~id_xthl);
|
||||
assign t1519 = tree2 | (id00 & t4f1 & ~id_xthl);
|
||||
assign mxi = inc16 ? (a + 16'h0001)
|
||||
: dec16 ? (a - 16'h0001)
|
||||
: a;
|
||||
|
||||
assign inc16 = iad16 & ~dec16;
|
||||
assign dec16 = iad16 & id05 & (t4f1 | t5f1 | m4f1 | m5f1);
|
||||
assign iad16 = ~(id00 & (t4f1 | t5f1)) & (~minta | m5 | t3144);
|
||||
|
||||
assign mxw16 = t3403;
|
||||
assign mxwadr = t3363 | (t4f1 & ~id_dad & ~id_hlt);
|
||||
assign t1513 = (t4f1 & id07) | t3335;
|
||||
assign t1514 = (t4f1 & id08) | t3361;
|
||||
|
||||
assign mxrh = t2998 | (id08 & t4f1 & ~i03);
|
||||
assign mxrl = t3047 | (id08 & t4f1 & i03);
|
||||
assign mxwh = t2817 | (t2806 & ~i03);
|
||||
assign mxwl = t2819 | (t2806 & i03);
|
||||
|
||||
assign mxr0 = tree0;
|
||||
assign mxr1 = xchg_dh & (((t1513 | t1514) & (~i14 & i25)) | t1519)
|
||||
| ~xchg_dh & (t1513 | t1514) & (i14 & ~i25);
|
||||
assign mxr2 = xchg_dh & (t1513 | t1514) & (i14 & ~i25)
|
||||
| ~xchg_dh & (((t1513 | t1514) & (~i14 & i25)) | t1519);
|
||||
assign mxr3 = (t1513 | t1514) & (~i14 & ~i25);
|
||||
assign mxr4 = t1467 | (t1513 & i14 & i25);
|
||||
assign mxr5 = ~(t1467 | t1513 | t1514 | t1519 | mxr0);
|
||||
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (f1) t3144 <= t4 | t5 | (m4 & ~id02);
|
||||
xchg_tt <= id_xchg & t2;
|
||||
xchg_dh <= ~reset & ((xchg_tt & ~(id_xchg & t2)) ? ~xchg_dh : xchg_dh);
|
||||
end
|
||||
|
||||
always @ (*)
|
||||
case ({mxr0, mxr1, mxr2, mxr3, mxr4, mxr5})
|
||||
6'b100000: mxo = r16_pc;
|
||||
6'b010000: mxo = r16_hl;
|
||||
6'b001000: mxo = r16_de;
|
||||
6'b000100: mxo = r16_bc;
|
||||
6'b000010: mxo = r16_sp;
|
||||
6'b000001: mxo = r16_wz;
|
||||
default: mxo = 16'h0000;
|
||||
endcase
|
||||
|
||||
always @ (posedge clk)
|
||||
if (f2)
|
||||
begin
|
||||
if (mxwadr) a <= mxo;
|
||||
if (mxw16)
|
||||
begin
|
||||
if (mxr0) r16_pc <= mxi;
|
||||
if (mxr1) r16_hl <= mxi;
|
||||
if (mxr2) r16_de <= mxi;
|
||||
if (mxr3) r16_bc <= mxi;
|
||||
if (mxr4) r16_sp <= mxi;
|
||||
if (mxr5) r16_wz <= mxi;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (mxwl)
|
||||
begin
|
||||
if (mxr0) r16_pc[7:0] <= d;
|
||||
if (mxr1) r16_hl[7:0] <= d;
|
||||
if (mxr2) r16_de[7:0] <= d;
|
||||
if (mxr3) r16_bc[7:0] <= d;
|
||||
if (mxr4) r16_sp[7:0] <= d;
|
||||
if (mxr5) r16_wz[7:0] <= d;
|
||||
end
|
||||
if (mxwh)
|
||||
begin
|
||||
if (mxr0) r16_pc[15:8] <= d;
|
||||
if (mxr1) r16_hl[15:8] <= d;
|
||||
if (mxr2) r16_de[15:8] <= d;
|
||||
if (mxr3) r16_bc[15:8] <= d;
|
||||
if (mxr4) r16_sp[15:8] <= d;
|
||||
if (mxr5) r16_wz[15:8] <= d;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// processor state
|
||||
//
|
||||
assign sy_hlta = id_hlt;
|
||||
assign sy_m1 = m1;
|
||||
assign sy_inp = m5 & id_in;
|
||||
assign sy_out = m5 & id_out;
|
||||
assign sy_inta = inta;
|
||||
assign sy_memr = sy_wo_n & ~sy_inp & ~minta;
|
||||
assign sy_wo_n = m1 | m2 | m3 | (((m4 & ~id86) | (m5 & ~id85)) & ~ready_int);
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f1)
|
||||
begin
|
||||
sy_stack <= (t1 & t1460)
|
||||
| (t3 & m3 & id_cxx & ~jmptake)
|
||||
| (t5 & m1 & id_rxx & ~jmptake);
|
||||
end
|
||||
end
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// ticks state machine
|
||||
//
|
||||
assign twt2 = (t2f1 | twf1) & ~start;
|
||||
assign thalt = ~m1 & sy_hlta;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f1)
|
||||
begin
|
||||
t1f1 <= t1 & ~reset; // ensure the reliable start after reset
|
||||
t2f1 <= t2;
|
||||
twf1 <= tw;
|
||||
t3f1 <= t3;
|
||||
t4f1 <= t4;
|
||||
t5f1 <= t5;
|
||||
end
|
||||
if (f2)
|
||||
begin
|
||||
t1 <= start;
|
||||
t2 <= ~start & t1f1;
|
||||
tw <= ~start & (t2f1 | twf1) & (~ready | thalt);
|
||||
t3 <= ~start & (t2f1 | twf1) & ready & ~thalt;
|
||||
t4 <= ~start & t3f1 & ms0 & ~ms1;
|
||||
t5 <= ~start & t4f1 & ms0 & ~ms1;
|
||||
end
|
||||
end
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
assign m836 = m1f1 & id82;
|
||||
assign m839 = ~t976 | ~sy_hlta;
|
||||
assign m871 = t789 | id81;
|
||||
|
||||
assign start = ~m839
|
||||
| t953
|
||||
| (eom & ~(hold & t887))
|
||||
| (f2 & ((~t382 & hold) | t383) & ~(twf1 | t3f1 | t4f1 | t5f1));
|
||||
|
||||
assign ms0 = ~reset & m839 & ~(sy_stack & ~t1f1) & ~(eom & ~m836);
|
||||
assign ms1 = ~reset & m839 & ~(sy_stack & ~t1f1) & ~(m871 & ~m836) & eom;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f1)
|
||||
begin
|
||||
t789 <= (id84 & m3) | (id83 & ~id_mvim & m4) | m5;
|
||||
t887 <= hold;
|
||||
t953 <= reset;
|
||||
t976 <= t980 & m4;
|
||||
eom <= t5
|
||||
| t4 & m1 & id80
|
||||
| t3 & m2
|
||||
| t3 & m3
|
||||
| t3 & m4
|
||||
| t3 & m5 & ~id_xthl;
|
||||
end
|
||||
if (f2)
|
||||
begin
|
||||
t980 <= sy_inta;
|
||||
end
|
||||
end
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// processor cycles state machine
|
||||
//
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f1)
|
||||
begin
|
||||
m1f1 <= m1;
|
||||
m2f1 <= m2;
|
||||
m3f1 <= m3;
|
||||
m4f1 <= m4;
|
||||
m5f1 <= m5;
|
||||
end
|
||||
if (f2)
|
||||
begin
|
||||
m1 <= (~ms0 & ~ms1) | (~ms1 & m1f1);
|
||||
m2 <= (~ms0 | ~ms1) & ((ms0 & m2f1) | (ms1 & m1f1));
|
||||
m3 <= (ms0 & m3f1) | (ms1 & m2f1);
|
||||
m4 <= (ms0 & m4f1) | (ms1 & m3f1) | (ms0 & ms1);
|
||||
m5 <= (ms0 & m5f1) | (ms1 & m4f1);
|
||||
end
|
||||
end
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// interrupt logic
|
||||
//
|
||||
assign irq = intr & inte & ~reset & ~hold;
|
||||
assign pin_inte = inte;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f2) intr <= pin_int;
|
||||
if (f2) mstart <= ~ms0 & ~ms1;
|
||||
if (sy_inta) minta <= 1;
|
||||
if (f1 & t1 & m1) minta <= 0;
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge reset)
|
||||
begin
|
||||
if (reset)
|
||||
begin
|
||||
inta <= 0;
|
||||
inte <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (f1)
|
||||
begin
|
||||
if (irq & ((tw & sy_hlta) | (mstart & ~id_eidi))) inta <= 1;
|
||||
if (~intr | id_eidi | (t5 & id_rst)) inta <= 0;
|
||||
end
|
||||
if (f2)
|
||||
begin
|
||||
if (t1f1 & id_eidi) inte <= i[3];
|
||||
if (t1f1 & sy_inta) inte <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// instruction register and decoder
|
||||
//
|
||||
function cmp
|
||||
(
|
||||
input [7:0] i,
|
||||
input [7:0] c,
|
||||
input [7:0] m
|
||||
);
|
||||
cmp = &(~(i ^ c) | m);
|
||||
endfunction
|
||||
|
||||
assign imx = ~(id_op | (id_mov & t4));
|
||||
assign acc_sel = imx ? (i[5:3] == 3'b111) : (i[2:0] == 3'b111);
|
||||
assign jmpflag = (psw_c & i14 & ~i25) // Intel original: d[0] instead of psw_c
|
||||
| (psw_p & ~i14 & i25) // Intel original: d[2] instead of psw_p
|
||||
| (psw_z & ~i14 & ~i25) // Intel original: d[6] instead of psw_z
|
||||
| (psw_s & i14 & i25); // Intel original: d[7] instead of psw_s
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
//
|
||||
// Simplify the D-bus multiplexer and feed the I-register by input pins directly
|
||||
// if (f2 & dbin_pin & (reset | (m1 & t3))) i <= pin_din;
|
||||
//
|
||||
if (~f2 & (reset | (m1 & t3))) i <= pin_din;
|
||||
if (f1)
|
||||
begin
|
||||
i25 <= imx ? i[5] : i[2];
|
||||
i14 <= imx ? i[4] : i[1];
|
||||
i03 <= imx ? i[3] : i[0];
|
||||
end
|
||||
end
|
||||
|
||||
assign goto = id_rst | id_jmp | id_call | (jmptake & (id_cxx | id_jxx));
|
||||
assign t1460 = (t1 & ((m2 & id00)
|
||||
| (m3 & id00)
|
||||
| (m4 & (id01 | id04))
|
||||
| (m5 & (id01 | id04)))
|
||||
| t2 & ( (m2 & id00)
|
||||
| (m4 & id01)
|
||||
| (m5 & id01))
|
||||
| t3 & ( (m4 & (id04 | id_sphl)))
|
||||
| t5 & ( (m1 & (id04 | id_sphl)))) & ~(~jmptake & id_cxx & t5);
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f2 & t4f1)
|
||||
begin
|
||||
jmptake <= i03 ? jmpflag : ~jmpflag;
|
||||
end
|
||||
if (f1)
|
||||
begin
|
||||
tree0 <= t1 & ( (m1 & ~goto)
|
||||
| (m2 & ~id_xthl)
|
||||
| (m3 & ~id_xthl)
|
||||
| (m4 & id02))
|
||||
| t2 & ( m1
|
||||
| (m2 & ~id_xthl)
|
||||
| (m3 & ~id_xthl)
|
||||
| (m4 & (id02 | id_rst | id_cxx | id_call))
|
||||
| (m5 & (id_rst | id_cxx | id_call)))
|
||||
| t3 & ( (m4 & (id_ret | id_rxx))
|
||||
| (m5 & (id_ret | id_rxx)))
|
||||
| t5 & id_pchl;
|
||||
|
||||
tree1 <= t1460;
|
||||
|
||||
tree2 <= t1 & ( (m4 & (id_mov | id_idr | id_op))
|
||||
| (m5 & id08))
|
||||
| t2 & ( (m4 & (id_shld | id00 | id_dad))
|
||||
| (m5 & (id_shld | id00 | id_dad)))
|
||||
| t3 & ( (m4 & (id_lhld | id_dad))
|
||||
| (m5 & (id_lhld | id_dad)))
|
||||
| t5 & m5;
|
||||
|
||||
t2806 <= id08 & ((t3 & m4) | (t5 & m1));
|
||||
t2817 <= reset | (t3 & (m1 | m3 | (m4 & id_io) | (m5 & id06)));
|
||||
t2819 <= reset | (t3 & (m2 | (m4 & id06) | (m5 & id_rst)));
|
||||
|
||||
t3047 <= (t1 | t2) & m4 & id_dad
|
||||
| t2 & ((m4 & id_shld) | (m5 & id03));
|
||||
|
||||
t2998 <= (t1 | t2) & m5 & id_dad
|
||||
| t2 & ((m5 & id_shld) | (m4 & id03));
|
||||
|
||||
t3403 <= t2 & ( (m1 | m2)
|
||||
| (m3 & ~id_xthl)
|
||||
| ((m4 | m5) & ~id_dad & ~id09))
|
||||
| t3 & m4 & id09
|
||||
| t5 & (m5 | (m1 & ~id08));
|
||||
|
||||
t3363 <= t1 & (m1 | m2 | m3 | ((m4 | m5) & ~id_hlt & ~id_dad));
|
||||
t3335 <= id07 & ((t1 & (m4 | m5)) | (t3 & (m2 | m3)) | t5);
|
||||
|
||||
t3361 <= t1 & m4 & id_lsax
|
||||
| t2 & id10 & ~sy_wo_n
|
||||
| t3 & id10 & sy_wo_n & (m4 | m5)
|
||||
| t5 & id08 & m1;
|
||||
end
|
||||
end
|
||||
|
||||
assign id_nop = cmp(i, 8'b00xxx000, 8'b00111000);
|
||||
assign id_lxi = cmp(i, 8'b00xx0001, 8'b00110000);
|
||||
assign id_lsax = cmp(i, 8'b000xx010, 8'b00011000);
|
||||
assign id_inx = cmp(i, 8'b00xx0011, 8'b00110000);
|
||||
assign id_inr = cmp(i, 8'b00xxx100, 8'b00111000);
|
||||
assign id_dcr = cmp(i, 8'b00xxx101, 8'b00111000);
|
||||
assign id_idr = cmp(i, 8'b00xxx10x, 8'b00111001);
|
||||
assign id_mvi = cmp(i, 8'b00xxx110, 8'b00111000);
|
||||
assign id_dad = cmp(i, 8'b00xx1001, 8'b00110000);
|
||||
assign id_dcx = cmp(i, 8'b00xx1011, 8'b00110000);
|
||||
assign id_opa = cmp(i, 8'b00xxx111, 8'b00111000);
|
||||
assign id_idm = cmp(i, 8'b0011010x, 8'b00000001);
|
||||
assign id_stlda = cmp(i, 8'b0011x010, 8'b00001000);
|
||||
assign id_mvim = cmp(i, 8'b00110110, 8'b00000000);
|
||||
assign id_shld = cmp(i, 8'b00100010, 8'b00000000);
|
||||
assign id_lhld = cmp(i, 8'b00101010, 8'b00000000);
|
||||
assign id_mvmr = cmp(i, 8'b01110xxx, 8'b00000111) & ~id_hlt;
|
||||
assign id_mvrm = cmp(i, 8'b01xxx110, 8'b00111000) & ~id_hlt;
|
||||
assign id_hlt = cmp(i, 8'b01110110, 8'b00000000);
|
||||
assign id_mov = cmp(i, 8'b01xxxxxx, 8'b00111111);
|
||||
assign id_op = cmp(i, 8'b10xxxxxx, 8'b00111111);
|
||||
assign id_opm = cmp(i, 8'b10xxx110, 8'b00111000);
|
||||
assign id_pop = cmp(i, 8'b11xx0001, 8'b00110000);
|
||||
assign id_push = cmp(i, 8'b11xx0101, 8'b00110000);
|
||||
assign id_rst = cmp(i, 8'b11xxx111, 8'b00111000);
|
||||
assign id_xthl = cmp(i, 8'b11100011, 8'b00000000);
|
||||
assign id_sphl = cmp(i, 8'b11111001, 8'b00000000);
|
||||
assign id_pchl = cmp(i, 8'b11101001, 8'b00000000);
|
||||
assign id_xchg = cmp(i, 8'b11101011, 8'b00000000);
|
||||
assign id_cxx = cmp(i, 8'b11xxx100, 8'b00111000);
|
||||
assign id_jxx = cmp(i, 8'b11xxx010, 8'b00111000);
|
||||
assign id_rxx = cmp(i, 8'b11xxx000, 8'b00111000);
|
||||
assign id_ret = cmp(i, 8'b110x1001, 8'b00010000);
|
||||
assign id_call = cmp(i, 8'b11xx1101, 8'b00110000);
|
||||
assign id_eidi = cmp(i, 8'b1111x011, 8'b00001000);
|
||||
assign id_jmp = cmp(i, 8'b1100x011, 8'b00001000);
|
||||
assign id_io = cmp(i, 8'b1101x011, 8'b00001000);
|
||||
assign id_opi = cmp(i, 8'b11xxx110, 8'b00111000);
|
||||
assign id_in = cmp(i, 8'b11011011, 8'b00000000);
|
||||
assign id_popsw = cmp(i, 8'b11110001, 8'b00000000);
|
||||
assign id_out = cmp(i, 8'b11010011, 8'b00000000);
|
||||
assign id_11x = cmp(i, 8'b11xxxxxx, 8'b00111111);
|
||||
assign id_pupsw = cmp(i, 8'b11110101, 8'b00000000);
|
||||
|
||||
assign id_rxc = ~i[5] & i[3] & id_opa;
|
||||
assign id_sha = ~i[5] & id_opa;
|
||||
assign id_rlc = (i[5:3] == 3'b000) & id_opa;
|
||||
assign id_rar = (i[5:3] == 3'b011) & id_opa;
|
||||
assign id_daa = (i[5:3] == 3'b100) & id_opa;
|
||||
assign id_cma = (i[5:3] == 3'b101) & id_opa;
|
||||
assign id_stc = (i[5:3] == 3'b110) & id_opa;
|
||||
assign id_cmc = (i[5:3] == 3'b111) & id_opa;
|
||||
|
||||
assign id_add = (i[5:3] == 3'b000) & (id_op | id_opi);
|
||||
assign id_adc = (i[5:3] == 3'b001) & (id_op | id_opi);
|
||||
assign id_sub = (i[5:3] == 3'b010) & (id_op | id_opi);
|
||||
assign id_sbb = (i[5:3] == 3'b011) & (id_op | id_opi);
|
||||
assign id_ana = (i[5:3] == 3'b100) & (id_op | id_opi);
|
||||
assign id_xra = (i[5:3] == 3'b101) & (id_op | id_opi);
|
||||
assign id_ora = (i[5:3] == 3'b110) & (id_op | id_opi);
|
||||
assign id_cmp = (i[5:3] == 3'b111) & (id_op | id_opi);
|
||||
|
||||
assign id80 = id_lxi | id_pop | id_opm | id_idm | id_dad
|
||||
| id_xthl | id_xchg | id_jxx | id_ret | id_eidi
|
||||
| id_nop | id_stlda | id_mvmr | id_mvrm | id_hlt
|
||||
| id_opa | id_mvim | id_jmp | id_io | id_opi
|
||||
| id_mvi | id_lsax | id_lhld | id_shld | id_op;
|
||||
assign id81 = id_dcx | id_inx | id_sphl | id_pchl | id_xchg
|
||||
| id_eidi | id_nop | id_opa | id_op | id_mov
|
||||
| (id_idr & ~id82);
|
||||
assign id82 = id_pop | id_push | id_opm | id_idm | id_dad
|
||||
| id_rst | id_ret | id_rxx | id_mvrm | id_mvmr
|
||||
| id_hlt | id_mvim | id_io | id_opi | id_mvi
|
||||
| id_lsax;
|
||||
assign id83 = id_opm | id_stlda | id_mvmr | id_mvrm | id_opi
|
||||
| id_mvi | id_lsax;
|
||||
assign id84 = id_lxi | id_jxx | id_jmp;
|
||||
assign id85 = id_push | id_idm | id_rst | id_xthl | id_cxx
|
||||
| id_call | id_mvim | id_shld | (id_io & ~i[3]);
|
||||
assign id86 = id_push | id_rst | id_xthl | id_cxx | id_call
|
||||
| id_mvmr | id_shld | (~i[3] & (id_lsax | id_stlda));
|
||||
|
||||
assign id00 = id_xthl | id_pchl | id_sphl;
|
||||
assign id01 = id_pop | id_rxx | id_ret;
|
||||
assign id02 = id_mvi | id_opi | id_io;
|
||||
assign id03 = id_rst | id_push | id_xthl | id_cxx | id_call;
|
||||
assign id04 = id_rst | id_push | id_xthl | id_cxx | id_call;
|
||||
assign id05 = id_rst | id_push | id_xthl | id_cxx | id_call | id_dcx;
|
||||
assign id06 = id_pop | id_rxx | id_ret | id_dad | id_lhld | id_io;
|
||||
assign id07 = id_dcx | id_inx | id_lxi | id_dad;
|
||||
assign id08 = id_mov | id_mvi | id_idr | id_op;
|
||||
assign id09 = id_rst | id_push | id_xthl | id_cxx | id_call | id_shld;
|
||||
assign id10 = id_pop | id_push | id_mvrm | id_mvi;
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// function alu
|
||||
// (
|
||||
// input rxc,
|
||||
// input ora,
|
||||
// input ana,
|
||||
// input xra,
|
||||
// input x,
|
||||
// input r,
|
||||
// input nc,
|
||||
// input rn,
|
||||
// input cp
|
||||
// );
|
||||
// alu = x & r & cp & ~(rxc | ora | ana | xra)
|
||||
// | nc & (cp | x | r) & ~(rxc | ora | ana | xra)
|
||||
// | rxc & rn
|
||||
// | ora & (x | r)
|
||||
// | ana & (x & r)
|
||||
// | xra & (x ^ r);
|
||||
// endfunction
|
||||
//
|
||||
//
|
||||
// assign s[0] = alu(id_rxc, id_ora, id_ana, id_xra, x[0], r[0], ~c[0], r[1], cl) | (id_rlc & c[7]);
|
||||
// assign s[1] = alu(id_rxc, id_ora, id_ana, id_xra, x[1], r[1], ~c[1], r[2], c[0]);
|
||||
// assign s[2] = alu(id_rxc, id_ora, id_ana, id_xra, x[2], r[2], ~c[2], r[3], c[1]);
|
||||
// assign s[3] = alu(id_rxc, id_ora, id_ana, id_xra, x[3], r[3], ~c[3], r[4], c[2]);
|
||||
// assign s[4] = alu(id_rxc, id_ora, id_ana, id_xra, x[4], r[4], ~c[4], r[5], c[3]);
|
||||
// assign s[5] = alu(id_rxc, id_ora, id_ana, id_xra, x[5], r[5], ~c[5], r[6], c[4]);
|
||||
// assign s[6] = alu(id_rxc, id_ora, id_ana, id_xra, x[6], r[6], ~c[6], r[7], c[5]);
|
||||
// assign s[7] = alu(id_rxc, id_ora, id_ana, id_xra, x[7], r[7], ~c[7], ch, c[6]);
|
||||
//
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
// arithmetic and logic unit
|
||||
//
|
||||
// assign alu_xwr = (f1 & m1 & t3) | (f2 & (a327 | t4f1 & (id_out | ~id_11x)));
|
||||
//
|
||||
assign alu_xwr = (a327 | t4f1 & (id_rst | id_out | ~id_11x));
|
||||
assign alu_xout = ~(id_sub | id_sbb | id_cmp | id_cma);
|
||||
assign alu_xrd = t1698 | a358;
|
||||
assign x = alu_xout ? xr : ~xr;
|
||||
|
||||
assign alu_ald = t2222 & ( id_adc | id_add | id_daa | id_xra | id_sbb
|
||||
| id_sub | id_ana | id_ora | id_sha | id_cma);
|
||||
assign alu_ard = t1375 | a398;
|
||||
assign alu_awr = t1497 | a357;
|
||||
|
||||
assign alu_r00 = id_dcr & t4f1;
|
||||
assign alu_srd = t1668;
|
||||
assign alu_rwr = t1780;
|
||||
assign alu_rld = t4f1 & (id_sha | id_op | id_opi);
|
||||
|
||||
assign daa = id_daa & t4f1;
|
||||
assign daa_x6 = (acc[3] & (acc[2] | acc[1])) | psw_ac;
|
||||
assign daa_6x = ((acc[3] & (acc[2] | acc[1])) & acc[4] & acc[7])
|
||||
| (acc[7] & (acc[6] | acc[5])) | tmp_c;
|
||||
|
||||
assign s = {7'b0000000, id_rlc & c[7]}
|
||||
| ((id_rxc | id_ora | id_ana | id_xra) ? 8'h00 : (x + r + cl))
|
||||
| (id_rxc ? {ch, r[7:1]} : 8'h00)
|
||||
| (id_ora ? (x | r) : 8'h00)
|
||||
| (id_ana ? (x & r) : 8'h00)
|
||||
| (id_xra ? (x ^ r) : 8'h00);
|
||||
|
||||
assign cl = tmp_c & ~id_daa & ~id_rlc & ~id_ora & ~id_xra & ~id_rxc;
|
||||
assign ch = tmp_c & id_rar | r[0] & ~id_rar;
|
||||
|
||||
//
|
||||
// wire ca0_n, ca2_n, ca1, ca3;
|
||||
// assign ca0_n = ~(cl & (x[0] | r[0])) & ~(x[0] & r[0]) & ~(id_ana & id_rxc);
|
||||
// assign ca2_n = ~(ca1 & (x[2] | r[2])) & ~(x[2] & r[2]) & ~(id_ana & id_rxc);
|
||||
// assign ca1 = ~(~x[1] & ~r[1]) & ~(ca0_n & (~x[1] | ~r[1])) & ~(id_ora | id_rxc | id_xra);
|
||||
// assign ca3 = ~(~x[3] & ~r[3]) & ~(ca2_n & (~x[3] | ~r[3])) & ~(id_ora | id_rxc | id_xra);
|
||||
//
|
||||
assign c[0] = (r[0] & x[0]) | (cl & (r[0] | x[0]));
|
||||
assign c[1] = (r[1] & x[1]) | (c[0] & (r[1] | x[1]));
|
||||
assign c[2] = (r[2] & x[2]) | (c[1] & (r[2] | x[2]));
|
||||
assign c[3] = (r[3] & x[3]) | (c[2] & (r[3] | x[3]));
|
||||
assign c[4] = (r[4] & x[4]) | (c[3] & (r[4] | x[4]));
|
||||
assign c[5] = (r[5] & x[5]) | (c[4] & (r[5] | x[5]));
|
||||
assign c[6] = (r[6] & x[6]) | (c[5] & (r[6] | x[6]));
|
||||
assign c[7] = (r[7] & x[7]) | (c[6] & (r[7] | x[7]));
|
||||
|
||||
assign alu_zrd = m1f1 & t3f1;
|
||||
assign alu_frd = t2046; /* | t4f1 & (id_11x & ~id_out);
|
||||
// as we do need to translate flags on the bus for conditional unit anymore */
|
||||
|
||||
assign a398 = t1993 & ((t1994 & id08) | id_opa | id_stlda | id_lsax | id_io);
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f1)
|
||||
begin
|
||||
t1375 <= t2 & m4 & id_pupsw;
|
||||
t1497 <= t3 & m5 & id_popsw;
|
||||
t1698 <= t5 & m1 & ~id_inr & ~id_dcr
|
||||
| t3 & m5 & id_rst;
|
||||
t1668 <= t2 & m5 & (id_inr | id_dcr)
|
||||
| t3 & m5 & id_dad
|
||||
| t3 & m4 & id_dad
|
||||
| t5 & m1 & (id_inr | id_dcr);
|
||||
t1780 <= t3 & m1
|
||||
| t1 & (m4 | m5) & id_dad;
|
||||
t2222 <= (t2 & m1) | (t1 & m5);
|
||||
a327 <= t3 & m4 & ~(id_dad | id_out | id_rst)
|
||||
| t2 & (m4 | m5) & id_dad;
|
||||
a357 <= t3 & m5 & (id_io | id_mvim) & sy_wo_n
|
||||
| t3 & m4 & (id_stlda | id_lsax | id_mvmr) & sy_wo_n
|
||||
| acc_sel & id08 & (t5 & m1 | t3 & m4);
|
||||
a358 <= t2 & ~sy_wo_n & (id_io | id_mvim | id_stlda | id_lsax | id_mvmr);
|
||||
|
||||
psw_ld <= t3 & m4 & id_popsw;
|
||||
psw_wr <= t2 & m1 & (id_opi | id_inr | id_dcr | id_daa | id_op);
|
||||
t2046 <= t2 & m5 & id_pupsw; /* | reset | t3 & m1; */
|
||||
//
|
||||
// t2047 <= reset
|
||||
// | t3 & m1
|
||||
// | t3 & m5 & id_rst;
|
||||
//
|
||||
t1993 <= t4 & m1;
|
||||
t1994 <= acc_sel;
|
||||
t2133 <= ~id_rxc & c[7];
|
||||
t2175 <= t3 & m1
|
||||
| t2 & m5 & id_dad;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (f2)
|
||||
begin
|
||||
if (alu_xwr) xr <= id_rst ? (i & 8'b00111000) : d;
|
||||
if (alu_awr) acc <= d;
|
||||
if (alu_ald) acc <= s;
|
||||
if (alu_rld) r <= acc;
|
||||
if (alu_rwr) r <= d;
|
||||
if (alu_r00) r <= 8'hff;
|
||||
if (daa)
|
||||
begin
|
||||
r[1] <= daa_x6;
|
||||
r[2] <= daa_x6;
|
||||
r[5] <= daa_6x;
|
||||
r[6] <= daa_6x;
|
||||
end
|
||||
if (psw_ld)
|
||||
begin
|
||||
psw_c <= d[0]; // x register was in original Intel design
|
||||
psw_p <= d[2];
|
||||
psw_ac <= d[4];
|
||||
psw_z <= d[6];
|
||||
psw_s <= d[7];
|
||||
end
|
||||
if (psw_wr)
|
||||
begin
|
||||
psw_p <= ~(^s);
|
||||
psw_ac <= (c[3] & ~id_xra & ~id_ora & ~id_rxc) | (id_ana & (x[3] | r[3]));
|
||||
psw_z <= ~(|s);
|
||||
psw_s <= s[7];
|
||||
end
|
||||
if (t2222)
|
||||
begin
|
||||
if (id_xra | id_stc | id_ora | id_ana | id_cmc)
|
||||
psw_c <= ~tmp_c;
|
||||
if (id_cmp | id_sbb | id_sub)
|
||||
psw_c <= ~(t2133 | id_rxc & x[0]);
|
||||
if (id_dad | id_sha | id_adc | id_add)
|
||||
psw_c <= t2133 | id_rxc & x[0];
|
||||
end
|
||||
if (daa & daa_6x)
|
||||
psw_c <= 1'b1;
|
||||
|
||||
if (t2175)
|
||||
tmp_c <= psw_c;
|
||||
if (t4f1)
|
||||
begin
|
||||
if (id_sbb)
|
||||
tmp_c <= ~psw_c;
|
||||
if (id_inr | id_ora | id_xra | id_ana | id_cmp | id_sub)
|
||||
tmp_c <= 1'b1;
|
||||
if (id_dad | id_cma | id_dcr | id_add | id_stc)
|
||||
tmp_c <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//______________________________________________________________________________
|
||||
//
|
||||
endmodule
|
||||
Reference in New Issue
Block a user