diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/README.txt b/Arcade_MiST/Midway MCR 3/Timber_MiST/README.txt
new file mode 100644
index 00000000..37c5d19b
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/README.txt	
@@ -0,0 +1,325 @@
+---------------------------------------------------------------------------------
+-- DE10_lite Top level for Timber (Midway MCR) by Dar (darfpga@aol.fr) (22/11/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+
+MiST port: create TIMBER.ROM with
+cat timpg0.bin timpg1.bin timpg2.bin timpg3.bin tima7.bin tima8.bin tima9.bin timfg1.bin timfg0.bin timfg3.bin timfg2.bin timfg5.bin timfg4.bin timfg7.bin timfg6.bin > timber.rom
+from MAME ROM file
+--
+-- release rev 00 : initial release
+--  (22/11/2019)
+--
+--   /!\ /!\ cannot fit de10_lite : Full size sprite rom required more room or
+--           sdram usage (TO DO)
+--
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+-- Use timber_de10_lite.sdc to compile (Timequest constraints)
+-- /!\
+-- Don't forget to set device configuration mode with memory initialization 
+--  (Assignments/Device/Pin options/Configuration mode)
+---------------------------------------------------------------------------------
+--
+-- Main features :
+--  PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection) 
+--  Audio pwm output   @gpio pins 1/3 (beware voltage translation/protection) 
+--
+--  Video         : VGA 31kHz/60Hz progressive and TV 15kHz interlaced
+--  Cocktail mode : NO
+--  Sound         : OK
+-- 
+-- For hardware schematic see my other project : NES
+--
+-- Uses 1 pll 40MHz from 50MHz to make 20MHz and 8Mhz 
+--
+-- Board key :
+--   0 : reset game
+--
+-- Keyboard players inputs :
+--
+--   F1 : Add coin
+--   F2 : Start 1 player
+--   F3 : Start 2 players
+--   F4 : Demo sound
+--   F5 : Separate audio
+--   F7 : Service mode
+--   F8 : 15kHz interlaced / 31 kHz progressive
+
+--   SPACE       : bouton 1
+--   v key       : bouton 2
+--   RIGHT arrow : move right
+--   LEFT  arrow : move left
+--   UP    arrow : move up
+--   DOWN  arrow : move down
+--
+-- Other details : see timber.vhd
+-- For USB inputs and SGT5000 audio output see my other project: xevious_de10_lite
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+-- Timber by Dar (darfpga@aol.fr) (22/11/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+--
+-- release rev 00 : initial release
+--  (22/11/2019)
+--
+---------------------------------------------------------------------------------
+-- gen_ram.vhd & io_ps2_keyboard
+-------------------------------- 
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- T80/T80se - Version : 304
+-----------------------------
+-- Z80 compatible microprocessor core
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+---------------------------------------------------------------------------------
+-- YM2149 (AY-3-8910)
+-- Copyright (c) MikeJ - Jan 2005
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+
+--  Features :
+--   Video        : VGA 31Khz/60Hz progressive and TV 15kHz interlaced
+--   Coctail mode : NO
+--   Sound        : OK
+
+--  Use with MAME roms from timber.zip
+--
+--  Use make_timber_proms.bat to build vhd file from binaries
+--  (CRC list included)
+
+--  Timber (midway mcr) Hardware caracteristics :
+--
+--  VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram,
+--    sprite data ram, I/O, sound board register and trigger.
+--		  56Kx8bits program rom
+--
+--    One char/background tile map 30x32
+--      2x8Kx8bits graphics rom 4bits/pixel + 2 bit color set
+--      rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
+--
+--    128 sprites, up to ~30/line, 32x32 with flip H/V
+--      4x32Kx8bits graphics rom 4bits/pixel + 2 bit color set
+--      rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue 
+--
+--    Working ram : 2Kx8bits
+--    video (char/background) ram  : 2Kx8bits
+--    Sprites ram : 512x8bits + 512x8bits cache buffer
+
+--    Sprites line buffer rams (graphics and colors) : 1 scan line delay flip/flop 2x256x16bits
+--
+--  SOUND : see tron_sound_board.vhd
+
+---------------------------------------------------------------------------------
+--  Schematics remarks :
+--
+--		Display is 512x480 pixels  (video 635x525 lines @ 20MHz )
+
+--       635/20e6  = 31.75us per line  (31.750KHz)
+--       31.75*525 = 16.67ms per frame (59.99Hz)
+--        
+--    Original video is interlaced 240 display lines per 1/2 frame
+--
+--       H0 and V0 are not use for background => each bg tile is 16x16 pixel but 
+--			background graphics is 2x2 pixels defintion.
+--
+--			Sprite are 32x32 pixels with 1x1 pixel definition, 16 lines for odd 1/2
+--       frame and 16 lines for even 2/2 frame thanks to V8 on sprite rom ROMAD2
+--       (look at 74ls86 G1 pin 9 on video genration board schematics)
+--
+--    *H and V stand for Horizontal en Vertical counter (Hcnt, Vcnt in VHDL code)
+--
+--    /!\ For VHDL port interlaced video mode is replaced with progressive video 
+--        mode.
+--
+--    Real hardware uses background ram access after each 1/2 frame (~line 240
+--    and 480). In these areas cpu can access ram since scanlines are out of
+--    visible display. In progessive mode there are video access around lines 240.
+--    These accesses will create video artfacts aound mid display. In VHDL code
+--    ram access is muliplexed between cpu and scanlines by using hcnt(0) in
+--    order to avoid these artefacts.
+--
+--    Sprite data are stored first by cpu into a 'cache' buffer (staging ram at
+--    K6/L6) this buffer is read and write for cpu. After visible display, cache
+--    buffer (512x8) is moved to actual sprite ram buffer (512x8). Actual sprite
+--    buffer is access by transfer address counter during 2 scanlines after 
+--    visible area and only by sprite machine during visible area.
+--
+--    Thus cpu can read and update sprites position during entire frame except
+--    during 2 lines.
+-- 
+--    Sprite data are organised (as seen by cpu F000-F1FF) into 128 * 4bytes.
+--    bytes #1 : Vertical position
+--    bytes #2 : code and attribute
+--    bytes #3 : Horizontal position
+--    bytes #4 : not used
+--
+--		Athough 1x1 pixel defintion sprite position horizontal/vertical is made on
+--    on a 2x2 grid (due to only 8bits for position data)
+--
+--    Z80-CTC : interruption ar managed by CTC chip. ONly channel 3 is trigered
+--    by hardware signal line 493. channel 0 to 2 are in timer mode. Schematic 
+--    show zc/to of channel 0 connected to clk/trg of channel 1. This seems to be
+--    unsued for that (Kick) game. 
+--
+--    Z80-CTC VHDL port keep separated interrupt controler and each counter so 
+--    one can use them on its own. Priority daisy-chain is not done (not used in
+--    that game). clock polarity selection is not done since it has no meaning
+--    with digital clock/enable (e.g cpu_ena signal) method.
+--
+--    Ressource : input clock 40MHz is chosen to allow easy making of 20MHz for
+--    pixel clock and 8MHz signal for amplitude modulation circuit of ssio board
+--
+--  TODO :
+--    Working ram could be initialized to set initial difficulty level and
+--    initial bases (live) number. Otherwise one can set it up by using service
+--    menu at each power up.
+--
+---------------------------------------------------------------------------------
+
+ /!\ /!\ HALF SIZE SPRITE ROM  /!\ /!\
+
+Full size sprite rom would required more room or external ram
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++------------------------------------+---------------------------------------------+
+; Fitter Status                      ; Successful - Fri Nov 22 17:33:36 2019       ;
+; Quartus Prime Version              ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
+; Revision Name                      ; timber_de10_lite                            ;
+; Top-level Entity Name              ; timber_de10_lite                            ;
+; Family                             ; MAX 10                                      ;
+; Device                             ; 10M50DAF484C6GES                            ;
+; Timing Models                      ; Preliminary                                 ;
+; Total logic elements               ; 6,779 / 49,760 ( 14 % )                     ;
+;     Total combinational functions  ; 6,540 / 49,760 ( 13 % )                     ;
+;     Dedicated logic registers      ; 1,724 / 49,760 ( 3 % )                      ;
+; Total registers                    ; 1724                                        ;
+; Total pins                         ; 105 / 360 ( 29 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 1,399,360 / 1,677,312 ( 83 % )  <--  WITH HALF SIZE SPRITE ROM ONLY
+; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % )                             ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
+; UFM blocks                         ; 0 / 1 ( 0 % )                               ;
+; ADC blocks                         ; 0 / 2 ( 0 % )                               ;
++------------------------------------+---------------------------------------------+
+
+---------------
+VHDL File list 
+---------------
+
+de10_lite/max10_pll_40M.vhd        Pll 40MHz from 50MHz altera mf 
+
+rtl_dar/timber_de10_lite.vhd       Top level for de10_lite board
+rtl_dar/timber.vhd                 Main CPU and video boards logic
+rtl_dar/timber_sound_board.vhd     Main sound board logic
+rtl_dar/ctc_controler.vhd          Z80-CTC controler 
+rtl_dar/ctc_counter.vhd            Z80-CTC counter
+
+rtl_mikej/YM2149_linmix.vhd        Copyright (c) MikeJ - Jan 2005
+
+rtl_T80_304/T80se.vhdT80           Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+rtl_T80_304/T80_Reg.vhd
+rtl_T80_304/T80_Pack.vhd
+rtl_T80_304/T80_MCode.vhd
+rtl_T80_304/T80_ALU.vhd
+rtl_T80_304/T80.vhd
+
+rtl_dar/kbd_joystick.vhd           Keyboard key to player/coin input
+rtl_dar/io_ps2_keyboard.vhd        Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+rtl_dar/gen_ram.vhd                Generic RAM (Peter Wendrich + DAR Modification)
+rtl_dar/decodeur_7_seg.vhd         7 segments display decoder
+
+rtl_dar/proms/timber_cpu.vhd         CPU board PROMS
+rtl_dar/proms/timber_bg_bits_2.vhd
+rtl_dar/proms/timber_bg_bits_1.vhd
+
+rtl_dar/proms/timber_sp_bits.vhd     Video board PROMS
+
+rtl_dar/proms/timber_sound_cpu.vhd   Sound board PROMS
+rtl_dar/proms/midssio_82s123.vhd
+
+----------------------
+Quartus project files
+----------------------
+de10_lite/timber_de10_lite.sdc   Timequest constraints file
+de10_lite/timber_de10_lite.qsf   de10_lite settings (files,pins...) 
+de10_lite/timber_de10_lite.qpf   de10_lite project
+
+-----------------------------
+Required ROMs (Not included)
+-----------------------------
+You need the following 18 ROMs binary files from timber.zip and midssio.zip(MAME)
+
+timpg0.bin  CRC 377032ab
+timpg1.bin  CRC fd772836
+timpg2.bin  CRC 632989f9
+timpg3.bin  CRC dae8a0dc
+
+tima7.bin   CRC c615dc3e
+tima8.bin   CRC 83841c87
+tima9.bin   CRC 22bcdcd3
+
+timbg1.bin  CRC b1cb2651
+timbg0.bin  CRC 2ae352c4
+
+timfg1.bin  CRC 81de4a73
+timfg0.bin  CRC 7f3a4f59
+timfg3.bin  CRC 37c03272
+timfg2.bin  CRC e2c2885c
+timfg5.bin  CRC eb636216
+timfg4.bin  CRC b7105eb7
+timfg7.bin  CRC d9c27475
+timfg6.bin  CRC 244778e8
+
+midssio_82s123.12d CRC e1281ee9
+
+------
+Tools 
+------
+You need to build vhdl files from the binary file :
+ - Unzip the roms file in the tools/timber_unzip directory
+ - Double click (execute) the script tools/make_timber_proms.bat to get the following 6 files
+
+timber_cpu.vhd
+timber_sound_cpu.vhd
+timber_bg_bits_1.vhd
+timber_bg_bits_2.vhd 
+timber_sp_bits.vhd
+midssio_82s123.vhd
+
+
+*DO NOT REDISTRIBUTE THESE FILES*
+
+VHDL files are needed to compile and include roms into the project 
+
+The script make_timber_proms.bat uses make_vhdl_prom executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux.
+
+Source code of make_vhdl_prom.c is also delivered.
+
+---------------------------------
+Compiling for de10_lite
+---------------------------------
+You can build the project with ROM image embeded in the sof file.
+*DO NOT REDISTRIBUTE THESE FILES*
+
+3 steps
+
+ - put the VHDL ROM files (.vhd) into the rtl_dar/proms directory
+ - build timber_de10_lite
+ - program timber_de10_lite.sof
+
+------------------------
+------------------------
+End of file
+------------------------
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/Timber.qpf b/Arcade_MiST/Midway MCR 3/Timber_MiST/Timber.qpf
new file mode 100644
index 00000000..7a17d5e4
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/Timber.qpf	
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 13:02:51  November 09, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "13:02:51  November 09, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "Timber"
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/Timber.qsf b/Arcade_MiST/Midway MCR 3/Timber_MiST/Timber.qsf
new file mode 100644
index 00000000..2bd1c215
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/Timber.qsf	
@@ -0,0 +1,243 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 19:17:51  November 03, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Timber_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY Timber_MiST
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# --------------------------
+# start ENTITY(Kickman_MiST)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(Kickman_MiST)
+# ------------------------
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/reset.stp
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Timber_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
+set_global_assignment -name VHDL_FILE rtl/ctc_counter.vhd
+set_global_assignment -name VHDL_FILE rtl/ctc_controler.vhd
+set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd
+set_global_assignment -name VHDL_FILE rtl/timber.vhd
+set_global_assignment -name VHDL_FILE rtl/timber_sound_board.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/timber_bg_bits_2.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/timber_bg_bits_1.vhd
+set_global_assignment -name VHDL_FILE rtl/rom/midssio_82s123.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/sdram.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/reset.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/Timber.sdc b/Arcade_MiST/Midway MCR 3/Timber_MiST/Timber.sdc
new file mode 100644
index 00000000..e1813b4a
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/Timber.sdc	
@@ -0,0 +1,134 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+set sys_clk   "pll|altpll_component|auto_generated|pll1|clk[0]"
+set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks $sys_clk]  1.000 [get_ports {VGA_*}]
+
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/Timber_MiST.sv b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/Timber_MiST.sv
new file mode 100644
index 00000000..afbbb181
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/Timber_MiST.sv	
@@ -0,0 +1,337 @@
+//============================================================================
+//  Arcade: Timber by DarFPGA
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+
+module Timber_MiST(
+	output        LED,
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27,
+	output [12:0] SDRAM_A,
+	inout  [15:0] SDRAM_DQ,
+	output        SDRAM_DQML,
+	output        SDRAM_DQMH,
+	output        SDRAM_nWE,
+	output        SDRAM_nCAS,
+	output        SDRAM_nRAS,
+	output        SDRAM_nCS,
+	output  [1:0] SDRAM_BA,
+	output        SDRAM_CLK,
+	output        SDRAM_CKE
+);
+
+`include "rtl/build_id.v"
+
+localparam CONF_STR = {
+	"TIMBER;;",
+	"O2,Rotate Controls,Off,On;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"O5,Blend,Off,On;",
+	"O6,Service,Off,On;",
+	"O7,Swap Joystick,Off,On;",
+	"T0,Reset;",
+	"V,v1.1.",`BUILD_DATE
+};
+
+assign LED = ~ioctl_downl;
+assign SDRAM_CLK = clk_mem;
+assign SDRAM_CKE = 1;
+
+wire clk_sys, clk_mem;
+wire pll_locked;
+pll_mist pll(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clk_sys),
+	.c1(clk_mem),
+	.locked(pll_locked)
+	);
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [7:0] joy_0;
+wire  [7:0] joy_1;
+wire        scandoublerD;
+wire        ypbpr;
+wire [15:0] audio_l, audio_r;
+wire        hs, vs, cs;
+wire        blankn;
+wire  [2:0] g, r, b;
+wire [15:0] rom_addr;
+wire [15:0] rom_do;
+wire [13:0] snd_addr;
+wire [15:0] snd_do;
+wire [14:0] sp_addr;
+wire [31:0] sp_do;
+wire        ioctl_downl;
+wire  [7:0] ioctl_index;
+wire        ioctl_wr;
+wire [24:0] ioctl_addr;
+wire  [7:0] ioctl_dout;
+
+data_io data_io(
+	.clk_sys       ( clk_sys      ),
+	.SPI_SCK       ( SPI_SCK      ),
+	.SPI_SS2       ( SPI_SS2      ),
+	.SPI_DI        ( SPI_DI       ),
+	.ioctl_download( ioctl_downl  ),
+	.ioctl_index   ( ioctl_index  ),
+	.ioctl_wr      ( ioctl_wr     ),
+	.ioctl_addr    ( ioctl_addr   ),
+	.ioctl_dout    ( ioctl_dout   )
+);
+
+wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h11000; //SP ROM offset: 0x11000
+
+reg port1_req, port2_req;
+sdram sdram(
+	.*,
+	.init_n        ( pll_locked   ),
+	.clk           ( clk_mem      ),
+
+	// port1 used for main + sound CPU
+	.port1_req     ( port1_req    ),
+	.port1_ack     ( ),
+	.port1_a       ( ioctl_addr[23:1] ),
+	.port1_ds      ( {ioctl_addr[0], ~ioctl_addr[0]} ),
+	.port1_we      ( ioctl_downl ),
+	.port1_d       ( {ioctl_dout, ioctl_dout} ),
+	.port1_q       ( ),
+
+	.cpu1_addr     ( ioctl_downl ? 16'hffff : {1'b0, rom_addr[15:1]} ),
+	.cpu1_q        ( rom_do ),
+	.cpu2_addr     ( ioctl_downl ? 16'hffff : (16'h7000 + snd_addr[13:1]) ),
+	.cpu2_q        ( snd_do ),
+
+	// port2 for sprite graphics
+	.port2_req     ( port2_req ),
+	.port2_ack     ( ),
+	.port2_a       ( {sp_ioctl_addr[14:0], sp_ioctl_addr[16]} ), // merge sprite roms to 32-bit wide words
+	.port2_ds      ( {sp_ioctl_addr[15], ~sp_ioctl_addr[15]} ),
+	.port2_we      ( ioctl_downl ),
+	.port2_d       ( {ioctl_dout, ioctl_dout} ),
+	.port2_q       ( ),
+
+	.sp_addr       ( ioctl_downl ? 15'h7fff : sp_addr ),
+	.sp_q          ( sp_do )
+);
+
+// ROM download controller
+always @(posedge clk_sys) begin
+	reg        ioctl_wr_last = 0;
+
+	ioctl_wr_last <= ioctl_wr;
+	if (ioctl_downl) begin
+		if (~ioctl_wr_last && ioctl_wr) begin
+			port1_req <= ~port1_req;
+			port2_req <= ~port2_req;
+		end
+	end
+end
+
+// reset signal generation
+reg reset = 1;
+reg rom_loaded = 0;
+always @(posedge clk_sys) begin
+	reg ioctl_downlD;
+	reg [15:0] reset_count;
+	ioctl_downlD <= ioctl_downl;
+
+	// generate a second reset signal - needed for some reason
+	if (status[0] | buttons[1] | ~rom_loaded) reset_count <= 16'hffff;
+	else if (reset_count != 0) reset_count <= reset_count - 1'd1;
+
+	if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
+	reset <= status[0] | buttons[1] | ~rom_loaded | (reset_count == 16'h0001);
+
+end
+
+timber timber (
+	.clock_40(clk_sys),
+	.reset(reset),
+	.video_r(r),
+	.video_g(g),
+	.video_b(b),
+	.video_blankn(blankn),
+	.video_hs(hs),
+	.video_vs(vs),
+	.video_csync(cs),
+	.tv15Khz_mode(scandoublerD),
+	.separate_audio(1'b0),
+	.audio_out_l(audio_l),
+	.audio_out_r(audio_r),
+	.coin1(btn_coin),
+	.coin2(1'b0),
+	.start2(btn_two_players),
+	.start1(btn_one_player),
+
+	.p1_left(m_left1), 
+	.p1_right(m_right1),
+	.p1_up(m_up1),
+	.p1_down(m_down1),
+	.p1_fire1(m_fire1),
+	.p1_fire2(m_fire1b),
+
+	.p2_left(m_left2),
+	.p2_right(m_right2),
+	.p2_up(m_up2),
+	.p2_down(m_down2),
+	.p2_fire1(m_fire2),
+	.p2_fire2(m_fire2b),
+
+	.upright(1'b1),
+	.coin_meters(1),
+	.service(status[6]),
+
+	.cpu_rom_addr ( rom_addr        ),
+	.cpu_rom_do   ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
+	.snd_rom_addr ( snd_addr        ),
+	.snd_rom_do   ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ),
+	.sp_addr      ( sp_addr         ),
+	.sp_graphx32_do ( sp_do         )
+);
+
+wire vs_out;
+wire hs_out;
+assign VGA_VS = scandoublerD | vs_out;
+assign VGA_HS = scandoublerD ? cs : hs_out;
+
+mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
+	.clk_sys        ( clk_sys          ),
+	.SPI_SCK        ( SPI_SCK          ),
+	.SPI_SS3        ( SPI_SS3          ),
+	.SPI_DI         ( SPI_DI           ),
+	.R              ( blankn ? r : 0   ),
+	.G              ( blankn ? g : 0   ),
+	.B              ( blankn ? b : 0   ),
+	.HSync          ( hs               ),
+	.VSync          ( vs               ),
+	.VGA_R          ( VGA_R            ),
+	.VGA_G          ( VGA_G            ),
+	.VGA_B          ( VGA_B            ),
+	.VGA_VS         ( vs_out           ),
+	.VGA_HS         ( hs_out           ),
+	.rotate         ( {1'b1,status[2]} ),
+	.ce_divider     ( 1                ),
+	.blend          ( status[5]        ),
+	.scandoubler_disable(1),//scandoublerD ),
+	.no_csync       ( 1'b1             ),
+	.scanlines      ( status[4:3]      ),
+	.ypbpr          ( ypbpr            )
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_sys        ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joy_0          ),
+	.joystick_1     (joy_1          ),
+	.status         (status         )
+	);
+
+dac #(
+	.C_bits(16))
+dac_l(
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio_l),
+	.dac_o(AUDIO_L)
+	);
+	
+dac #(
+	.C_bits(16))
+dac_r(
+	.clk_i(clk_sys),
+	.res_n_i(1),
+	.dac_i(audio_r),
+	.dac_o(AUDIO_R)
+	);	
+
+wire  [7:0] joystick_0 = status[7] ? joy_1 : joy_0;
+wire  [7:0] joystick_1 = status[7] ? joy_0 : joy_1;
+
+//											Rotated														Normal
+wire m_up1     = status[2] ? btn_left  | joystick_0[1] : btn_up    | joystick_0[3];
+wire m_down1   = status[2] ? btn_right | joystick_0[0] : btn_down  | joystick_0[2];
+wire m_left1   = status[2] ? btn_down  | joystick_0[2] : btn_left  | joystick_0[1];
+wire m_right1  = status[2] ? btn_up    | joystick_0[3] : btn_right | joystick_0[0];
+wire m_fire1   = btn_fire1 | joystick_0[4];
+wire m_fire1b  = btn_fire2 | joystick_0[5];
+
+wire m_up2     = status[2] ? joystick_1[1] : joystick_1[3];
+wire m_down2   = status[2] ? joystick_1[0] : joystick_1[2];
+wire m_left2   = status[2] ? joystick_1[2] : joystick_1[1];
+wire m_right2  = status[2] ? joystick_1[3] : joystick_1[0];
+wire m_fire2   = joystick_1[4];
+wire m_fire2b  = joystick_1[5];
+
+reg btn_one_player = 0;
+reg btn_two_players = 0;
+reg btn_left = 0;
+reg btn_right = 0;
+reg btn_down = 0;
+reg btn_up = 0;
+reg btn_fire1 = 0;
+reg btn_fire2 = 0;
+//reg btn_fire3 = 0;
+reg btn_coin  = 0;
+wire       key_pressed;
+wire [7:0] key_code;
+wire       key_strobe;
+
+always @(posedge clk_sys) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up          <= key_pressed; // up
+			'h72: btn_down        <= key_pressed; // down
+			'h6B: btn_left        <= key_pressed; // left
+			'h74: btn_right       <= key_pressed; // right
+			'h76: btn_coin        <= key_pressed; // ESC
+			'h05: btn_one_player  <= key_pressed; // F1
+			'h06: btn_two_players <= key_pressed; // F2
+//			'h14: btn_fire3       <= key_pressed; // ctrl
+			'h11: btn_fire2       <= key_pressed; // alt
+			'h29: btn_fire1       <= key_pressed; // Space
+		endcase
+	end
+end
+
+endmodule 
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/YM2149_linmix_sep.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/YM2149_linmix_sep.vhd
new file mode 100644
index 00000000..6ed2498a
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/YM2149_linmix_sep.vhd	
@@ -0,0 +1,574 @@
+-- changes for seperate audio outputs and enable now enables cpu access as well
+--
+-- A simulation model of YM2149 (AY-3-8910 with bells on)
+
+-- Copyright (c) MikeJ - Jan 2005
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
+--
+-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
+-- vol 15 .. 0
+-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
+-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
+-- to produced all the required values.
+-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
+--
+-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
+-- accurate for designs where the outputs are buffered and not simply wired together.
+-- The ouput level is more complex in that case and requires a larger table.
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_arith.all;
+  use ieee.std_logic_unsigned.all;
+
+entity YM2149 is
+  port (
+  -- data bus
+  I_DA                : in  std_logic_vector(7 downto 0);
+  O_DA                : out std_logic_vector(7 downto 0);
+  O_DA_OE_L           : out std_logic;
+  -- control
+  I_A9_L              : in  std_logic;
+  I_A8                : in  std_logic;
+  I_BDIR              : in  std_logic;
+  I_BC2               : in  std_logic;
+  I_BC1               : in  std_logic;
+  I_SEL_L             : in  std_logic;
+
+  O_AUDIO             : out std_logic_vector(7 downto 0);
+  O_CHAN              : out std_logic_vector(1 downto 0);
+  -- port a
+  I_IOA               : in  std_logic_vector(7 downto 0);
+  O_IOA               : out std_logic_vector(7 downto 0);
+  O_IOA_OE_L          : out std_logic;
+  -- port b
+  I_IOB               : in  std_logic_vector(7 downto 0);
+  O_IOB               : out std_logic_vector(7 downto 0);
+  O_IOB_OE_L          : out std_logic;
+
+  ENA                 : in  std_logic; -- clock enable for higher speed operation
+  RESET_L             : in  std_logic;
+  CLK                 : in  std_logic  -- note 6 Mhz
+  );
+end;
+
+architecture RTL of YM2149 is
+  type  array_16x8   is array (0 to 15) of std_logic_vector( 7 downto 0);
+  type  array_3x12   is array (1 to  3) of std_logic_vector(11 downto 0);
+
+  signal cnt_div              : std_logic_vector(3 downto 0) := (others => '0');
+  signal cnt_div_t1           : std_logic_vector(3 downto 0);
+  signal noise_div            : std_logic := '0';
+  signal ena_div              : std_logic;
+  signal ena_div_noise        : std_logic;
+  signal poly17               : std_logic_vector(16 downto 0) := (others => '0');
+
+  -- registers
+  signal addr                 : std_logic_vector(7 downto 0);
+  signal busctrl_addr         : std_logic;
+  signal busctrl_we           : std_logic;
+  signal busctrl_re           : std_logic;
+
+  signal reg                  : array_16x8;
+  signal env_reset            : std_logic;
+  signal ioa_inreg            : std_logic_vector(7 downto 0);
+  signal iob_inreg            : std_logic_vector(7 downto 0);
+
+  signal noise_gen_cnt        : std_logic_vector(4 downto 0);
+  signal noise_gen_op         : std_logic;
+  signal tone_gen_cnt         : array_3x12 := (others => (others => '0'));
+  signal tone_gen_op          : std_logic_vector(3 downto 1) := "000";
+
+  signal env_gen_cnt          : std_logic_vector(15 downto 0);
+  signal env_ena              : std_logic;
+  signal env_hold             : std_logic;
+  signal env_inc              : std_logic;
+  signal env_vol              : std_logic_vector(4 downto 0);
+
+  signal tone_ena_l           : std_logic;
+  signal tone_src             : std_logic;
+  signal noise_ena_l          : std_logic;
+  signal chan_vol             : std_logic_vector(4 downto 0);
+
+  signal dac_amp              : std_logic_vector(7 downto 0);
+begin
+  -- cpu i/f
+  p_busdecode            : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
+    variable cs : std_logic;
+    variable sel : std_logic_vector(2 downto 0);
+  begin
+    -- BDIR BC2 BC1 MODE
+    --   0   0   0  inactive
+    --   0   0   1  address
+    --   0   1   0  inactive
+    --   0   1   1  read
+    --   1   0   0  address
+    --   1   0   1  inactive
+    --   1   1   0  write
+    --   1   1   1  read
+    busctrl_addr <= '0';
+    busctrl_we <= '0';
+    busctrl_re <= '0';
+
+    cs := '0';
+    if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
+      cs := '1';
+    end if;
+
+    sel := (I_BDIR & I_BC2 & I_BC1);
+    case sel is
+      when "000" => null;
+      when "001" => busctrl_addr <= '1';
+      when "010" => null;
+      when "011" => busctrl_re   <= cs;
+      when "100" => busctrl_addr <= '1';
+      when "101" => null;
+      when "110" => busctrl_we   <= cs;
+      when "111" => busctrl_addr <= '1';
+      when others => null;
+    end case;
+  end process;
+
+  p_oe                   : process(busctrl_re)
+  begin
+    -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
+    O_DA_OE_L <= not (busctrl_re);
+  end process;
+
+  --
+  -- CLOCKED
+  --
+  p_waddr                : process(RESET_L, CLK)
+  begin
+    -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+    if (RESET_L = '0') then
+      addr <= (others => '0');
+    elsif rising_edge(CLK) then
+      if (ENA = '1') then
+        if (busctrl_addr = '1') then
+          addr <= I_DA;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_wdata                : process(RESET_L, CLK)
+  begin
+    if (RESET_L = '0') then
+      reg <= (others => (others => '0'));
+      env_reset <= '1';
+    elsif rising_edge(CLK) then
+      if (ENA = '1') then
+        env_reset <= '0';
+        if (busctrl_we = '1') then
+          case addr(3 downto 0) is
+            when x"0" => reg(0)  <= I_DA;
+            when x"1" => reg(1)  <= I_DA;
+            when x"2" => reg(2)  <= I_DA;
+            when x"3" => reg(3)  <= I_DA;
+            when x"4" => reg(4)  <= I_DA;
+            when x"5" => reg(5)  <= I_DA;
+            when x"6" => reg(6)  <= I_DA;
+            when x"7" => reg(7)  <= I_DA;
+            when x"8" => reg(8)  <= I_DA;
+            when x"9" => reg(9)  <= I_DA;
+            when x"A" => reg(10) <= I_DA;
+            when x"B" => reg(11) <= I_DA;
+            when x"C" => reg(12) <= I_DA;
+            when x"D" => reg(13) <= I_DA; env_reset <= '1';
+            when x"E" => reg(14) <= I_DA;
+            when x"F" => reg(15) <= I_DA;
+            when others => null;
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_rdata                : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg)
+  begin
+    O_DA <= (others => '0'); -- 'X'
+    if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
+      case addr(3 downto 0) is
+        when x"0" => O_DA <= reg(0) ;
+        when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
+        when x"2" => O_DA <= reg(2) ;
+        when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
+        when x"4" => O_DA <= reg(4) ;
+        when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
+        when x"6" => O_DA <= "000"  & reg(6)(4 downto 0) ;
+        when x"7" => O_DA <= reg(7) ;
+        when x"8" => O_DA <= "000"  & reg(8)(4 downto 0) ;
+        when x"9" => O_DA <= "000"  & reg(9)(4 downto 0) ;
+        when x"A" => O_DA <= "000"  & reg(10)(4 downto 0) ;
+        when x"B" => O_DA <= reg(11);
+        when x"C" => O_DA <= reg(12);
+        when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
+        when x"E" => if (reg(7)(6) = '0') then -- input
+                       O_DA <= ioa_inreg;
+                     else
+                       O_DA <= reg(14); -- read output reg
+                     end if;
+        when x"F" => if (Reg(7)(7) = '0') then
+                       O_DA <= iob_inreg;
+                     else
+                       O_DA <= reg(15);
+                     end if;
+        when others => null;
+      end case;
+    end if;
+  end process;
+  --
+  p_divider              : process
+  begin
+    wait until rising_edge(CLK);
+    -- / 8 when SEL is high and /16 when SEL is low
+    if (ENA = '1') then
+      ena_div <= '0';
+      ena_div_noise <= '0';
+      if (cnt_div = "0000") then
+        cnt_div <= (not I_SEL_L) & "111";
+        ena_div <= '1';
+
+        noise_div <= not noise_div;
+        if (noise_div = '1') then
+          ena_div_noise <= '1';
+        end if;
+      else
+        cnt_div <= cnt_div - "1";
+      end if;
+    end if;
+  end process;
+
+  p_noise_gen            : process
+    variable noise_gen_comp : std_logic_vector(4 downto 0);
+    variable poly17_zero : std_logic;
+  begin
+    wait until rising_edge(CLK);
+    if (reg(6)(4 downto 0) = "00000") then
+      noise_gen_comp := "00000";
+    else
+      noise_gen_comp := (reg(6)(4 downto 0) - "1");
+    end if;
+
+    poly17_zero := '0';
+    if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
+
+    if (ENA = '1') then
+      if (ena_div_noise = '1') then -- divider ena
+
+        if (noise_gen_cnt >= noise_gen_comp) then
+          noise_gen_cnt <= "00000";
+          poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
+        else
+          noise_gen_cnt <= (noise_gen_cnt + "1");
+        end if;
+      end if;
+    end if;
+  end process;
+  noise_gen_op <= poly17(0);
+
+  p_tone_gens            : process
+    variable tone_gen_freq : array_3x12;
+    variable tone_gen_comp : array_3x12;
+  begin
+    wait until rising_edge(CLK);
+    -- looks like real chips count up - we need to get the Exact behaviour ..
+    tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
+    tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
+    tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
+    -- period 0 = period 1
+    for i in 1 to 3 loop
+      if (tone_gen_freq(i) = x"000") then
+        tone_gen_comp(i) := x"000";
+      else
+        tone_gen_comp(i) := (tone_gen_freq(i) - "1");
+      end if;
+    end loop;
+
+    if (ENA = '1') then
+      for i in 1 to 3 loop
+        if (ena_div = '1') then -- divider ena
+
+          if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
+            tone_gen_cnt(i) <= x"000";
+            tone_gen_op(i) <= not tone_gen_op(i);
+          else
+            tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
+          end if;
+        end if;
+      end loop;
+    end if;
+  end process;
+
+  p_envelope_freq        : process
+    variable env_gen_freq : std_logic_vector(15 downto 0);
+    variable env_gen_comp : std_logic_vector(15 downto 0);
+  begin
+    wait until rising_edge(CLK);
+    env_gen_freq := reg(12) & reg(11);
+    -- envelope freqs 1 and 0 are the same.
+    if (env_gen_freq = x"0000") then
+      env_gen_comp := x"0000";
+    else
+      env_gen_comp := (env_gen_freq - "1");
+    end if;
+
+    if (ENA = '1') then
+      env_ena <= '0';
+      if (ena_div = '1') then -- divider ena
+        if (env_gen_cnt >= env_gen_comp) then
+          env_gen_cnt <= x"0000";
+          env_ena <= '1';
+        else
+          env_gen_cnt <= (env_gen_cnt + "1");
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_envelope_shape       : process(env_reset, reg, CLK)
+    variable is_bot    : boolean;
+    variable is_bot_p1 : boolean;
+    variable is_top_m1 : boolean;
+    variable is_top    : boolean;
+  begin
+        -- envelope shapes
+        -- C AtAlH
+        -- 0 0 x x  \___
+        --
+        -- 0 1 x x  /___
+        --
+        -- 1 0 0 0  \\\\
+        --
+        -- 1 0 0 1  \___
+        --
+        -- 1 0 1 0  \/\/
+        --           ___
+        -- 1 0 1 1  \
+        --
+        -- 1 1 0 0  ////
+        --           ___
+        -- 1 1 0 1  /
+        --
+        -- 1 1 1 0  /\/\
+        --
+        -- 1 1 1 1  /___
+    if (env_reset = '1') then
+      -- load initial state
+      if (reg(13)(2) = '0') then -- attack
+        env_vol <= "11111";
+        env_inc <= '0'; -- -1
+      else
+        env_vol <= "00000";
+        env_inc <= '1'; -- +1
+      end if;
+      env_hold <= '0';
+
+    elsif rising_edge(CLK) then
+      is_bot    := (env_vol = "00000");
+      is_bot_p1 := (env_vol = "00001");
+      is_top_m1 := (env_vol = "11110");
+      is_top    := (env_vol = "11111");
+
+      if (ENA = '1') then
+        if (env_ena = '1') then
+          if (env_hold = '0') then
+            if (env_inc = '1') then
+              env_vol <= (env_vol + "00001");
+            else
+              env_vol <= (env_vol + "11111");
+            end if;
+          end if;
+
+          -- envelope shape control.
+          if (reg(13)(3) = '0') then
+            if (env_inc = '0') then -- down
+              if is_bot_p1 then env_hold <= '1'; end if;
+            else
+              if is_top then env_hold <= '1'; end if;
+            end if;
+          else
+            if (reg(13)(0) = '1') then -- hold = 1
+              if (env_inc = '0') then -- down
+                if (reg(13)(1) = '1') then -- alt
+                  if is_bot    then env_hold <= '1'; end if;
+                else
+                  if is_bot_p1 then env_hold <= '1'; end if;
+                end if;
+              else
+                if (reg(13)(1) = '1') then -- alt
+                  if is_top    then env_hold <= '1'; end if;
+                else
+                  if is_top_m1 then env_hold <= '1'; end if;
+                end if;
+              end if;
+
+            elsif (reg(13)(1) = '1') then -- alternate
+              if (env_inc = '0') then -- down
+                if is_bot_p1 then env_hold <= '1'; end if;
+                if is_bot    then env_hold <= '0'; env_inc <= '1'; end if;
+              else
+                if is_top_m1 then env_hold <= '1'; end if;
+                if is_top    then env_hold <= '0'; env_inc <= '0'; end if;
+              end if;
+            end if;
+
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_chan_mixer           : process(cnt_div, reg, tone_gen_op)
+  begin
+    tone_ena_l  <= '1'; tone_src <= '1';
+    noise_ena_l <= '1'; chan_vol <= "00000";
+    case cnt_div(1 downto 0) is
+      when "00" =>
+        tone_ena_l  <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
+        noise_ena_l <= reg(7)(3);
+      when "01" =>
+        tone_ena_l  <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
+        noise_ena_l <= reg(7)(4);
+      when "10" =>
+        tone_ena_l  <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
+        noise_ena_l <= reg(7)(5);
+      when "11" => null; -- tone gen outputs become valid on this clock
+      when others => null;
+    end case;
+  end process;
+
+  p_op_mixer             : process
+    variable chan_mixed : std_logic;
+    variable chan_amp : std_logic_vector(4 downto 0);
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+
+      chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
+
+      chan_amp := (others => '0');
+      if (chan_mixed = '1') then
+        if (chan_vol(4) = '0') then
+          if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
+            chan_amp := "00000";
+          else
+            chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
+          end if;
+        else
+          chan_amp := env_vol(4 downto 0);
+        end if;
+      end if;
+
+      dac_amp <= x"00";
+      case chan_amp is
+        when "11111" => dac_amp <= x"FF";
+        when "11110" => dac_amp <= x"D9";
+        when "11101" => dac_amp <= x"BA";
+        when "11100" => dac_amp <= x"9F";
+        when "11011" => dac_amp <= x"88";
+        when "11010" => dac_amp <= x"74";
+        when "11001" => dac_amp <= x"63";
+        when "11000" => dac_amp <= x"54";
+        when "10111" => dac_amp <= x"48";
+        when "10110" => dac_amp <= x"3D";
+        when "10101" => dac_amp <= x"34";
+        when "10100" => dac_amp <= x"2C";
+        when "10011" => dac_amp <= x"25";
+        when "10010" => dac_amp <= x"1F";
+        when "10001" => dac_amp <= x"1A";
+        when "10000" => dac_amp <= x"16";
+        when "01111" => dac_amp <= x"13";
+        when "01110" => dac_amp <= x"10";
+        when "01101" => dac_amp <= x"0D";
+        when "01100" => dac_amp <= x"0B";
+        when "01011" => dac_amp <= x"09";
+        when "01010" => dac_amp <= x"08";
+        when "01001" => dac_amp <= x"07";
+        when "01000" => dac_amp <= x"06";
+        when "00111" => dac_amp <= x"05";
+        when "00110" => dac_amp <= x"04";
+        when "00101" => dac_amp <= x"03";
+        when "00100" => dac_amp <= x"03";
+        when "00011" => dac_amp <= x"02";
+        when "00010" => dac_amp <= x"02";
+        when "00001" => dac_amp <= x"01";
+        when "00000" => dac_amp <= x"00";
+        when others => null;
+      end case;
+
+      cnt_div_t1 <= cnt_div;
+    end if;
+  end process;
+
+  p_audio_output         : process(RESET_L, CLK)
+  begin
+    if (RESET_L = '0') then
+      O_AUDIO <= (others => '0');
+      O_CHAN  <= (others => '0');
+    elsif rising_edge(CLK) then
+
+      if (ENA = '1') then
+        O_AUDIO <= dac_amp(7 downto 0);
+        O_CHAN  <= cnt_div_t1(1 downto 0);
+      end if;
+    end if;
+  end process;
+
+  p_io_ports             : process(reg)
+  begin
+    O_IOA      <= reg(14);
+    O_IOA_OE_L <= not reg(7)(6);
+    O_IOB      <= reg(15);
+    O_IOB_OE_L <= not reg(7)(7);
+  end process;
+
+  p_io_ports_inreg       : process
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then -- resync
+      ioa_inreg <= I_IOA;
+      iob_inreg <= I_IOB;
+    end if;
+  end process;
+end architecture RTL;
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/build_id.tcl b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/build_id.tcl
new file mode 100644
index 00000000..938515d8
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/build_id.tcl	
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/cmos_ram.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/cmos_ram.vhd
new file mode 100644
index 00000000..c5e34893
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/cmos_ram.vhd	
@@ -0,0 +1,356 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr) 
+-- http://darfpga.blogspot.fr
+--   Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- gen_rwram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cmos_ram is
+	generic (
+		dWidth : integer := 8;
+		aWidth : integer := 10
+	);
+	port (
+		clk : in std_logic;
+		we : in std_logic;
+		addr : in std_logic_vector((aWidth-1) downto 0);
+		d : in std_logic_vector((dWidth-1) downto 0);
+		q : out std_logic_vector((dWidth-1) downto 0)
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of cmos_ram is
+	subtype addressRange is integer range 0 to ((2**aWidth)-1);
+	type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+	signal ram: ramDef:= (
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --000-00F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --010-01F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --020-02F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --030-03F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --040-04F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --050-05F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --060-06F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --070-07F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --080-08F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --090-09F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --0A0-0AF
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --0B0-0BF
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --0C0-0CF
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --0D0-0DF
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --0E0-0EF
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --0F0-0FF
+
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --100-10F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --1F0-1FF
+
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --200-20F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --2F0-2FF
+
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --300-30F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --3F0-3FF
+
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --400-40F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --4F0-4FF
+
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --500-50F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --5F0-5FF
+
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --600-60F
+	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
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+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --DF0-DFF
+--
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --E00-E0F
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --EF0-EFF
+--
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  --F00-F0F
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",  
+--	X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF"   --FF0-FFF
+);
+
+	signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
+	signal qReg : std_logic_vector((dWidth-1) downto 0);
+begin
+-- -----------------------------------------------------------------------
+-- Signals to entity interface
+-- -----------------------------------------------------------------------
+--	q <= qReg;
+
+-- -----------------------------------------------------------------------
+-- Memory write
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if we = '1' then
+				ram(to_integer(unsigned(addr))) <= d;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- Memory read
+-- -----------------------------------------------------------------------
+process(clk)
+	begin
+		if rising_edge(clk) then
+--			qReg <= ram(to_integer(unsigned(rAddrReg)));
+--			rAddrReg <= addr;
+----			qReg <= ram(to_integer(unsigned(addr)));
+      q <= ram(to_integer(unsigned(addr)));
+		end if;
+	end process;
+--q <= ram(to_integer(unsigned(addr)));
+end architecture;
+
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/ctc_controler.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/ctc_controler.vhd
new file mode 100644
index 00000000..1ff9961d
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/ctc_controler.vhd	
@@ -0,0 +1,106 @@
+---------------------------------------------------------------------------------
+-- Z80-CTC controler by Dar (darfpga@aol.fr) (19/10/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity ctc_controler is
+port(
+ clock     : in std_logic;
+ clock_ena : in std_logic;
+ reset     : in std_logic;
+ 
+ d_in      : in std_logic_vector( 7 downto 0);
+ load_data : in std_logic;
+ int_ack   : in std_logic;
+ 
+ int_pulse_0 : in std_logic;
+ int_pulse_1 : in std_logic;
+ int_pulse_2 : in std_logic;
+ int_pulse_3 : in std_logic;
+
+ d_out : out std_logic_vector( 7 downto 0);
+ int_n : out std_logic
+ 
+);
+end ctc_controler;
+
+architecture struct of ctc_controler is
+
+ signal int_vector : std_logic_vector(4 downto 0);
+ 
+ signal wait_for_time_constant : std_logic;
+ signal load_data_r  : std_logic; -- make sure load_data toggles to get one new data
+ 
+ signal int_reg_0 : std_logic;
+ signal int_reg_1 : std_logic;
+ signal int_reg_2 : std_logic;
+ signal int_reg_3 : std_logic;
+ 
+ signal int_ack_r : std_logic;
+
+begin
+						
+int_n <= '0' when (int_reg_0 or int_reg_1 or int_reg_2 or int_reg_3) = '1' else '1';
+
+d_out <= int_vector & "000" when int_reg_0 = '1' else
+			int_vector & "010" when int_reg_1 = '1' else
+			int_vector & "100" when int_reg_2 = '1' else
+			int_vector & "110" when int_reg_3 = '1' else (others => '0');
+			
+process (reset, clock)
+begin
+
+	if reset = '1' then -- hardware and software reset
+		wait_for_time_constant <= '0';
+		int_reg_0 <= '0';
+		int_reg_1 <= '0';
+		int_reg_2 <= '0';
+		int_reg_3 <= '0';
+		load_data_r <= load_data;
+		int_vector <= (others => '0');
+	else 
+		if rising_edge(clock) then
+			if clock_ena = '1' then
+			
+				load_data_r <= load_data;
+				int_ack_r <= int_ack;
+			
+				if load_data = '1' and load_data_r = '0' then
+				
+					if wait_for_time_constant = '1' then
+						wait_for_time_constant <= '0';
+					else
+						if d_in(0) = '1' then -- check if its a control world
+							wait_for_time_constant <= d_in(2);
+--							if d_in(1) = '1' then -- software reset
+--								wait_for_time_constant <= '0';
+--							end if;	
+						else                  -- its an interrupt vector
+							int_vector <= d_in(7 downto 3);
+						end if;						
+					end if;
+			
+				end if;
+			
+				if int_pulse_0 = '1' then int_reg_0 <= '1'; end if;
+				if int_pulse_1 = '1' then int_reg_1 <= '1'; end if;
+				if int_pulse_2 = '1' then int_reg_2 <= '1'; end if;
+				if int_pulse_3 = '1' then int_reg_3 <= '1'; end if;
+
+				if int_ack_r = '1' and int_ack = '0' then
+					if    int_reg_0 = '1' then int_reg_0 <= '0';
+					elsif int_reg_1 = '1' then int_reg_1 <= '0';
+					elsif int_reg_2 = '1' then int_reg_2 <= '0';
+					elsif int_reg_3 = '1' then int_reg_3 <= '0'; end if;
+				end if;
+				
+			end if;
+		end if;
+	end if;
+end process;
+
+end struct;
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/ctc_counter.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/ctc_counter.vhd
new file mode 100644
index 00000000..25f9a797
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/ctc_counter.vhd	
@@ -0,0 +1,152 @@
+---------------------------------------------------------------------------------
+-- Z80-CTC counter by Dar (darfpga@aol.fr) (19/10/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity ctc_counter is
+port(
+ clock     : in std_logic;
+ clock_ena : in std_logic;
+ reset     : in std_logic;
+ 
+ d_in      : in std_logic_vector( 7 downto 0);
+ load_data : in std_logic;
+ 
+ clk_trg   : in std_logic;       
+ 
+ d_out     : out std_logic_vector(7 downto 0);
+ zc_to     : out std_logic;
+ int_pulse : out std_logic
+ 
+ );
+end ctc_counter;
+
+architecture struct of ctc_counter is
+
+ signal control_word : std_logic_vector(7 downto 0);
+ signal wait_for_time_constant : std_logic;
+ signal time_constant_loaded : std_logic;
+ signal restart_on_next_clock : std_logic;
+ signal restart_on_next_trigger : std_logic;
+
+ signal prescale_max : std_logic_vector(7 downto 0);
+ signal prescale_in  : std_logic_vector(7 downto 0) := (others => '0');
+ signal count_max    : std_logic_vector(8 downto 0);
+ signal count_in     : std_logic_vector(8 downto 0) := (others => '0');
+ signal zc_to_in     : std_logic;
+ signal clk_trg_r    : std_logic;
+ signal trigger      : std_logic;
+ signal count_ena    : std_logic;
+ signal load_data_r  : std_logic; -- make sure load_data toggles to get one new data
+ 
+begin
+
+prescale_max <= 
+	(others => '0') when control_word(6) = '1' else  -- counter mode (prescale max = 0)
+	X"0F" when control_word(6 downto 5) = "00" else  -- timer mode prescale 16
+	X"FF";                                           -- timer mode prescale 256
+			
+trigger <=
+	'1' when (clk_trg = '0' and clk_trg_r = '1' and control_word(4) = '0') or        -- falling edge
+	         (clk_trg = '1' and clk_trg_r = '0' and control_word(4) = '1') else '0'; -- rising edge
+	
+d_out <= count_in(7 downto 0);
+
+zc_to <= zc_to_in;
+int_pulse <= zc_to_in when control_word(7) = '1' else '0';
+			
+process (reset, clock)
+begin
+
+	if reset = '1' then -- hardware reset
+		count_ena <= '0';
+		wait_for_time_constant <= '0';
+		time_constant_loaded <= '0';
+		restart_on_next_clock <= '0';
+		restart_on_next_trigger <= '0';
+		count_in  <= (others=> '0');
+		zc_to_in <= '0';
+		clk_trg_r <= clk_trg;
+	else 
+		if rising_edge(clock) then
+			if clock_ena = '1' then
+			
+				clk_trg_r <= clk_trg;
+				load_data_r <= load_data;
+				
+				if (restart_on_next_trigger = '1' and trigger = '1') or (restart_on_next_clock = '1') then												
+					restart_on_next_clock <= '0';
+					restart_on_next_trigger <= '0';
+					count_ena   <= '1';
+					count_in    <= count_max;
+					prescale_in <= prescale_max;
+				end if;
+			
+				if load_data = '1' and load_data_r = '0' then
+				
+					if wait_for_time_constant = '1' then
+						wait_for_time_constant <= '0';
+						time_constant_loaded   <= '1';
+						
+						if d_in = X"00" then 
+							count_max <= '1'&X"00";
+						else 
+							count_max <= '0'&d_in;
+						end if;
+						
+						if control_word(6) = '0' and count_ena = '0' then -- in timer mode, if count was stooped
+							if control_word(3) = '0' then -- auto start when time_constant loaded
+								restart_on_next_clock <= '1';
+							else                          -- wait for trigger to start
+								restart_on_next_trigger <= '1';
+							end if;
+						end if;
+						
+					else -- not waiting for time constant
+					
+						if d_in(0) = '1' then -- check if its a control world
+							control_word <= d_in;
+							wait_for_time_constant <= d_in(2);
+							restart_on_next_clock <= '0';
+							restart_on_next_trigger <= '0';
+							
+							if d_in(1) = '1' then -- software reset
+								count_ena <= '0';
+								time_constant_loaded <= '0';
+								zc_to_in <= '0';
+--								zc_to_in_r <= '0';
+								clk_trg_r <= clk_trg;
+							end if;
+						end if;
+	
+					end if;
+					
+				end if; -- end load data
+			
+				-- counter 
+				zc_to_in <= '0';
+				if ((control_word(6) = '1' and trigger = '1'  ) or 
+					 (control_word(6) = '0' and count_ena = '1') ) and time_constant_loaded = '1' then				
+					if prescale_in = 0 then
+						prescale_in <= '0'&prescale_max(7 downto 1); -- test divide by 2 !
+						if count_in = 0 then
+							zc_to_in <= '1';
+							count_in <= count_max;
+						else
+							count_in <= count_in - '1';							
+						end if;
+					else
+						prescale_in <= prescale_in - '1';
+					end if;
+				end if; 
+			
+			end if;
+		end if;
+	end if;
+end process;
+
+end struct;
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/gen_ram.vhd
new file mode 100644
index 00000000..f1a95608
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/gen_ram.vhd	
@@ -0,0 +1,84 @@
+-- -----------------------------------------------------------------------
+--
+-- Syntiac's generic VHDL support files.
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+--
+-- Modified April 2016 by Dar (darfpga@aol.fr) 
+-- http://darfpga.blogspot.fr
+--   Remove address register when writing
+--
+-- -----------------------------------------------------------------------
+--
+-- gen_rwram.vhd
+--
+-- -----------------------------------------------------------------------
+--
+-- generic ram.
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity gen_ram is
+	generic (
+		dWidth : integer := 8;
+		aWidth : integer := 10
+	);
+	port (
+		clk : in std_logic;
+		we : in std_logic;
+		addr : in std_logic_vector((aWidth-1) downto 0);
+		d : in std_logic_vector((dWidth-1) downto 0);
+		q : out std_logic_vector((dWidth-1) downto 0)
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of gen_ram is
+	subtype addressRange is integer range 0 to ((2**aWidth)-1);
+	type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
+	signal ram: ramDef;
+
+	signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
+	signal qReg : std_logic_vector((dWidth-1) downto 0);
+begin
+-- -----------------------------------------------------------------------
+-- Signals to entity interface
+-- -----------------------------------------------------------------------
+--	q <= qReg;
+
+-- -----------------------------------------------------------------------
+-- Memory write
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if we = '1' then
+				ram(to_integer(unsigned(addr))) <= d;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- Memory read
+-- -----------------------------------------------------------------------
+process(clk)
+	begin
+		if rising_edge(clk) then
+--			qReg <= ram(to_integer(unsigned(rAddrReg)));
+--			rAddrReg <= addr;
+----			qReg <= ram(to_integer(unsigned(addr)));
+      q <= ram(to_integer(unsigned(addr)));
+		end if;
+	end process;
+--q <= ram(to_integer(unsigned(addr)));
+end architecture;
+
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/pll_mist.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/pll_mist.vhd
new file mode 100644
index 00000000..15c5571c
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/pll_mist.vhd	
@@ -0,0 +1,397 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_mist.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_mist IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll_mist;
+
+
+ARCHITECTURE SYN OF pll_mist IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire6_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire6_bv(0 DOWNTO 0) <= "0";
+	sub_wire6    <= To_stdlogicvector(sub_wire6_bv);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	sub_wire4    <= inclk0;
+	sub_wire5    <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 27,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 40,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 27,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 80,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire5,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "80.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "40"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "80"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "80.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "80"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/rom/midssio_82s123.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/rom/midssio_82s123.vhd
new file mode 100644
index 00000000..daecc05c
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/rom/midssio_82s123.vhd	
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity midssio_82s123 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(4 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of midssio_82s123 is
+	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"FF",X"FF",X"FE",X"FF",X"FF",X"FD",X"FF",X"FE",X"FF",X"F7",
+		X"FB",X"EF",X"6D",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/rom/timber_bg_bits_1.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/rom/timber_bg_bits_1.vhd
new file mode 100644
index 00000000..104c1201
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/rom/timber_bg_bits_1.vhd	
@@ -0,0 +1,1046 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity timber_bg_bits_1 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(13 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of timber_bg_bits_1 is
+	type rom is array(0 to  16383) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"55",X"55",X"84",X"15",X"4A",X"A5",X"46",X"91",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"A9",X"AA",X"A9",X"AA",X"A9",X"AA",X"A9",X"AA",X"A9",X"AA",X"A9",
+		X"97",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"56",X"55",X"56",X"55",X"56",X"55",X"56",X"57",X"56",X"55",X"56",X"55",X"56",X"55",X"56",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AB",
+		X"AB",X"FD",X"AD",X"55",X"AD",X"45",X"B5",X"55",X"B5",X"55",X"D4",X"55",X"D5",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"7F",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"AA",X"AB",X"AA",X"AD",X"AA",X"AD",X"AA",X"B5",X"AA",X"B5",X"AA",X"D4",X"AA",X"D5",X"AB",X"55",
+		X"55",X"55",X"45",X"55",X"5D",X"55",X"5F",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"75",X"55",X"55",X"55",X"55",X"55",
+		X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"AB",X"55",X"AD",X"45",X"AD",X"55",X"B5",X"55",X"B5",X"55",X"D4",X"55",X"D5",X"55",X"D5",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"D5",X"55",X"54",X"55",X"55",X"55",X"55",
+		X"57",X"55",X"17",X"15",X"5D",X"5D",X"5D",X"55",X"75",X"55",X"74",X"55",X"D5",X"55",X"D5",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"D5",X"55",X"55",X"55",X"55",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"0B",X"80",X"02",X"C0",X"A2",X"28",X"2E",X"E0",X"0A",X"B0",X"3E",X"FC",X"FF",X"FF",X"3F",X"F0",
+		X"00",X"00",X"00",X"00",X"02",X"00",X"22",X"EA",X"0A",X"AF",X"3F",X"BF",X"03",X"FC",X"00",X"00",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AB",X"AA",X"AB",X"AA",X"AD",X"AA",X"AD",
+		X"BF",X"FF",X"D5",X"55",X"D4",X"55",X"D5",X"55",X"55",X"55",X"51",X"55",X"55",X"55",X"55",X"55",
+		X"FF",X"FF",X"75",X"55",X"74",X"55",X"D5",X"55",X"D5",X"55",X"51",X"55",X"55",X"55",X"55",X"55",
+		X"FF",X"FF",X"55",X"55",X"55",X"51",X"7D",X"55",X"55",X"55",X"55",X"47",X"55",X"57",X"55",X"55",
+		X"FF",X"FF",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"FF",X"FF",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"75",X"55",X"75",X"15",X"D5",X"55",X"D5",X"55",X"55",X"55",X"45",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"51",X"55",X"55",X"55",X"55",X"55",X"57",X"55",X"17",X"55",X"5D",X"55",X"55",
+		X"55",X"55",X"15",X"55",X"55",X"55",X"55",X"F5",X"55",X"F5",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"AA",X"AD",X"AA",X"B5",X"AA",X"B5",X"AA",X"D5",X"AA",X"D4",X"AA",X"D5",X"AB",X"55",X"AB",X"55",
+		X"AD",X"55",X"AD",X"45",X"AD",X"55",X"B5",X"55",X"B5",X"15",X"D5",X"55",X"D5",X"55",X"D5",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"D5",X"55",X"D5",X"55",X"D5",X"55",X"D5",X"55",X"D5",X"55",X"D5",X"55",X"D5",X"55",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"01",X"40",X"80",X"00",X"06",X"90",X"01",X"40",X"01",X"40",X"04",X"10",X"14",X"14",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"55",X"D5",X"51",X"D5",X"57",X"51",X"57",X"55",X"5D",X"55",X"5D",X"15",X"35",X"55",X"75",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"57",X"55",X"47",X"55",X"57",X"55",X"57",X"55",X"57",X"55",X"47",X"55",X"57",X"55",X"57",
+		X"55",X"55",X"55",X"55",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"FF",X"FF",X"FF",X"FF",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"FF",X"FF",X"FF",X"FF",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"7D",X"55",X"55",
+		X"55",X"55",X"FF",X"FF",X"FF",X"FF",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"D5",X"55",
+		X"55",X"55",X"FF",X"FF",X"FF",X"FF",X"55",X"55",X"75",X"55",X"55",X"55",X"55",X"75",X"55",X"55",
+		X"55",X"55",X"7F",X"FD",X"FF",X"FF",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"AA",X"BF",X"AA",X"FF",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"95",
+		X"AA",X"95",X"AA",X"95",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"F6",X"55",X"00",X"15",
+		X"55",X"55",X"55",X"55",X"55",X"7F",X"55",X"7D",X"55",X"7F",X"55",X"55",X"55",X"5F",X"55",X"5F",
+		X"55",X"55",X"55",X"55",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"A9",X"55",X"69",X"55",X"A9",X"55",X"F5",X"55",X"A5",X"55",X"A5",X"55",
+		X"55",X"55",X"55",X"55",X"56",X"AA",X"56",X"AA",X"56",X"9A",X"56",X"AA",X"54",X"01",X"55",X"A9",
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+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/rom/timber_bg_bits_2.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/rom/timber_bg_bits_2.vhd
new file mode 100644
index 00000000..714cabd5
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/rom/timber_bg_bits_2.vhd	
@@ -0,0 +1,1046 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity timber_bg_bits_2 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(13 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of timber_bg_bits_2 is
+	type rom is array(0 to  16383) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"02",X"80",X"71",X"40",X"30",X"00",X"10",X"04",X"05",X"50",X"04",X"10",X"28",X"28",X"00",X"00",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"A8",X"AA",X"AA",X"AA",X"A9",X"AA",X"A9",X"AA",X"AA",X"AA",X"A9",
+		X"80",X"AA",X"0A",X"AA",X"00",X"00",X"AA",X"AA",X"59",X"55",X"59",X"55",X"AA",X"AA",X"55",X"95",
+		X"A8",X"AA",X"A2",X"AA",X"0A",X"AA",X"AA",X"AA",X"88",X"AA",X"8A",X"AA",X"AA",X"AA",X"5A",X"AA",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"A8",
+		X"A8",X"01",X"A0",X"02",X"A0",X"31",X"80",X"01",X"80",X"02",X"03",X"01",X"00",X"01",X"AA",X"AA",
+		X"55",X"95",X"AA",X"AA",X"59",X"55",X"59",X"55",X"AA",X"AA",X"55",X"95",X"55",X"95",X"AA",X"AA",
+		X"5A",X"80",X"AA",X"80",X"9A",X"00",X"9A",X"00",X"A8",X"00",X"58",X"00",X"50",X"00",X"AA",X"AA",
+		X"AA",X"A8",X"AA",X"A0",X"AA",X"A0",X"AA",X"80",X"AA",X"80",X"AA",X"03",X"AA",X"00",X"A8",X"AA",
+		X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"A8",X"00",X"A0",X"30",X"A0",X"00",X"80",X"00",X"80",X"00",X"03",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"01",X"00",X"51",X"14",X"11",X"10",X"05",X"40",X"01",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"01",X"00",X"11",X"15",X"05",X"50",X"00",X"40",X"00",X"00",X"00",X"00",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"A8",X"AA",X"A8",X"AA",X"A0",X"AA",X"A2",
+		X"80",X"00",X"15",X"55",X"03",X"00",X"00",X"00",X"00",X"00",X"0C",X"00",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"45",X"55",X"03",X"00",X"00",X"00",X"00",X"00",X"0C",X"00",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"55",X"55",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"55",X"55",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"55",X"55",X"00",X"10",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"AA",X"AA",
+		X"00",X"00",X"C0",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"AA",
+		X"AA",X"A0",X"AA",X"80",X"AA",X"80",X"AA",X"00",X"AA",X"03",X"AA",X"00",X"A8",X"00",X"A8",X"AA",
+		X"A0",X"00",X"A0",X"30",X"A0",X"00",X"80",X"00",X"80",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"0A",X"A0",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"0A",X"A0",X"00",X"00",
+		X"0A",X"80",X"02",X"80",X"02",X"80",X"02",X"80",X"02",X"80",X"02",X"80",X"0A",X"A0",X"00",X"00",
+		X"0A",X"A0",X"28",X"A8",X"00",X"28",X"00",X"A0",X"02",X"80",X"0A",X"00",X"2A",X"A8",X"00",X"00",
+		X"0A",X"A0",X"28",X"28",X"00",X"28",X"02",X"A0",X"00",X"28",X"28",X"28",X"0A",X"A0",X"00",X"00",
+		X"02",X"28",X"0A",X"28",X"08",X"28",X"28",X"28",X"2A",X"A8",X"00",X"28",X"00",X"28",X"00",X"00",
+		X"2A",X"A8",X"28",X"00",X"2A",X"A0",X"00",X"28",X"00",X"28",X"2A",X"A8",X"2A",X"A0",X"00",X"00",
+		X"02",X"A0",X"0A",X"08",X"28",X"00",X"2A",X"A0",X"28",X"28",X"28",X"28",X"0A",X"A0",X"00",X"00",
+		X"2A",X"A8",X"20",X"28",X"00",X"A0",X"02",X"80",X"0A",X"80",X"0A",X"00",X"0A",X"00",X"00",X"00",
+		X"0A",X"A0",X"28",X"28",X"28",X"28",X"0A",X"A0",X"28",X"28",X"28",X"28",X"0A",X"A0",X"00",X"00",
+		X"0A",X"A0",X"28",X"28",X"28",X"28",X"0A",X"A8",X"00",X"28",X"00",X"28",X"00",X"28",X"00",X"00",
+		X"2A",X"A0",X"80",X"08",X"8A",X"88",X"88",X"08",X"8A",X"88",X"80",X"08",X"2A",X"A0",X"00",X"00",
+		X"FF",X"FF",X"EA",X"AA",X"EA",X"AA",X"EA",X"AA",X"EA",X"AA",X"EA",X"AA",X"EA",X"AA",X"EA",X"AA",
+		X"00",X"00",X"00",X"00",X"02",X"2A",X"8A",X"20",X"22",X"2A",X"02",X"20",X"02",X"2A",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"0A",X"82",X"02",X"08",X"02",X"08",X"02",X"08",X"02",X"02",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"02",X"82",X"82",X"22",X"82",X"82",X"82",X"22",X"02",X"82",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"82",X"2A",X"08",X"88",X"8A",X"88",X"08",X"88",X"88",X"88",X"00",X"00",
+		X"02",X"80",X"71",X"40",X"30",X"00",X"10",X"04",X"01",X"40",X"04",X"10",X"28",X"28",X"00",X"00",
+		X"0A",X"A0",X"28",X"28",X"28",X"28",X"2A",X"A8",X"28",X"28",X"28",X"28",X"28",X"28",X"00",X"00",
+		X"2A",X"A0",X"28",X"28",X"28",X"28",X"2A",X"A0",X"28",X"28",X"28",X"28",X"2A",X"A0",X"00",X"00",
+		X"0A",X"A0",X"28",X"28",X"28",X"00",X"28",X"00",X"28",X"00",X"28",X"08",X"0A",X"A0",X"00",X"00",
+		X"2A",X"A0",X"28",X"28",X"28",X"08",X"28",X"08",X"28",X"08",X"28",X"28",X"2A",X"A0",X"00",X"00",
+		X"2A",X"A8",X"28",X"00",X"28",X"00",X"2A",X"80",X"28",X"00",X"28",X"00",X"2A",X"A8",X"00",X"00",
+		X"2A",X"A8",X"28",X"00",X"28",X"00",X"2A",X"80",X"28",X"00",X"28",X"00",X"28",X"00",X"00",X"00",
+		X"0A",X"A8",X"28",X"00",X"28",X"00",X"28",X"A8",X"28",X"08",X"2A",X"A8",X"0A",X"88",X"00",X"00",
+		X"28",X"28",X"28",X"28",X"28",X"28",X"2A",X"A8",X"28",X"28",X"28",X"28",X"28",X"28",X"00",X"00",
+		X"0A",X"A0",X"02",X"80",X"02",X"80",X"02",X"80",X"02",X"80",X"02",X"80",X"0A",X"A0",X"00",X"00",
+		X"0A",X"A8",X"00",X"A0",X"00",X"A0",X"00",X"A0",X"28",X"A0",X"2A",X"A0",X"0A",X"80",X"00",X"00",
+		X"28",X"08",X"28",X"28",X"28",X"A0",X"2A",X"A0",X"28",X"28",X"28",X"08",X"28",X"08",X"00",X"00",
+		X"28",X"00",X"28",X"00",X"28",X"00",X"28",X"00",X"28",X"00",X"28",X"00",X"2A",X"A8",X"00",X"00",
+		X"28",X"28",X"28",X"28",X"22",X"88",X"22",X"88",X"20",X"08",X"20",X"08",X"20",X"08",X"00",X"00",
+		X"28",X"08",X"2A",X"08",X"2A",X"08",X"22",X"88",X"20",X"88",X"20",X"A8",X"20",X"28",X"00",X"00",
+		X"0A",X"A0",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"0A",X"A0",X"00",X"00",
+		X"2A",X"A0",X"28",X"28",X"28",X"08",X"2A",X"A8",X"28",X"00",X"28",X"00",X"28",X"00",X"00",X"00",
+		X"0A",X"A0",X"28",X"28",X"20",X"08",X"20",X"08",X"20",X"88",X"28",X"A0",X"0A",X"A8",X"00",X"00",
+		X"2A",X"A0",X"28",X"28",X"28",X"08",X"2A",X"A8",X"28",X"20",X"28",X"28",X"28",X"08",X"00",X"00",
+		X"0A",X"A8",X"28",X"08",X"28",X"00",X"2A",X"A8",X"00",X"28",X"20",X"28",X"2A",X"A0",X"00",X"00",
+		X"2A",X"A8",X"2A",X"A8",X"02",X"80",X"02",X"80",X"02",X"80",X"02",X"80",X"02",X"80",X"00",X"00",
+		X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"28",X"0A",X"A0",X"00",X"00",
+		X"20",X"08",X"20",X"08",X"28",X"28",X"08",X"20",X"0A",X"A0",X"02",X"80",X"02",X"80",X"00",X"00",
+		X"20",X"08",X"20",X"08",X"20",X"08",X"22",X"88",X"22",X"88",X"2A",X"A8",X"08",X"20",X"00",X"00",
+		X"20",X"08",X"28",X"28",X"0A",X"A0",X"02",X"80",X"0A",X"A0",X"28",X"28",X"20",X"08",X"00",X"00",
+		X"20",X"08",X"20",X"08",X"28",X"28",X"0A",X"A0",X"02",X"80",X"02",X"80",X"02",X"80",X"00",X"00",
+		X"2A",X"A8",X"20",X"28",X"00",X"A0",X"02",X"80",X"0A",X"00",X"28",X"08",X"2A",X"A8",X"00",X"00",
+		X"00",X"00",X"0C",X"00",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"C0",X"C0",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"00",X"50",X"01",X"54",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"00",X"00",X"00",X"00",
+		X"AA",X"AA",X"55",X"55",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"AA",
+		X"AA",X"AA",X"00",X"00",X"00",X"00",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",
+		X"AA",X"AA",X"00",X"00",X"00",X"00",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"41",X"55",X"55",
+		X"AA",X"AA",X"00",X"00",X"00",X"00",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"55",X"15",X"55",
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+		X"00",X"AA",X"00",X"AA",X"00",X"AA",X"00",X"AA",X"00",X"AA",X"00",X"2A",X"00",X"0A",X"00",X"0A",
+		X"AA",X"00",X"A8",X"00",X"A0",X"08",X"A0",X"2A",X"80",X"2A",X"80",X"AA",X"00",X"AA",X"00",X"AA",
+		X"0A",X"AA",X"02",X"AA",X"00",X"AA",X"00",X"AA",X"80",X"2A",X"80",X"2A",X"80",X"0A",X"80",X"0A",
+		X"80",X"0A",X"80",X"0A",X"80",X"0A",X"80",X"0A",X"A0",X"0A",X"A0",X"02",X"A0",X"02",X"A0",X"02",
+		X"80",X"02",X"80",X"0A",X"80",X"0A",X"00",X"2A",X"00",X"2A",X"00",X"2A",X"00",X"2A",X"00",X"AA",
+		X"00",X"AA",X"00",X"AA",X"00",X"2A",X"00",X"0A",X"80",X"00",X"80",X"00",X"A0",X"00",X"A8",X"00",
+		X"80",X"0A",X"A0",X"02",X"A0",X"02",X"A8",X"00",X"AA",X"00",X"AA",X"00",X"AA",X"80",X"AA",X"A0",
+		X"AA",X"00",X"AA",X"00",X"AA",X"00",X"AA",X"00",X"A8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"A8",X"00",X"A0",X"00",X"A0",X"00",X"A8",X"00",X"AA",X"00",
+		X"00",X"02",X"00",X"02",X"A0",X"02",X"A8",X"02",X"A8",X"02",X"AA",X"02",X"AA",X"02",X"AA",X"80",
+		X"AA",X"80",X"AA",X"80",X"AA",X"00",X"AA",X"00",X"A8",X"02",X"A8",X"02",X"A8",X"02",X"A8",X"02",
+		X"A0",X"0A",X"A0",X"0A",X"A0",X"0A",X"A0",X"0A",X"A0",X"0A",X"80",X"0A",X"80",X"0A",X"80",X"0A",
+		X"A0",X"00",X"A0",X"00",X"A8",X"00",X"A8",X"00",X"A8",X"00",X"A8",X"00",X"A8",X"00",X"A8",X"00",
+		X"A8",X"00",X"A8",X"00",X"A8",X"00",X"A8",X"00",X"28",X"00",X"28",X"00",X"A8",X"00",X"A8",X"00",
+		X"A8",X"00",X"A8",X"00",X"A8",X"00",X"A8",X"00",X"A8",X"00",X"28",X"00",X"20",X"00",X"A0",X"00",
+		X"AA",X"A0",X"AA",X"A0",X"AA",X"80",X"AA",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"0A",X"00",X"02",X"00",X"02",X"20",X"02",X"A8",X"02",X"AA",X"00",X"AA",X"80",X"AA",X"A0",
+		X"AA",X"A8",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"2A",X"28",X"0A",X"00",X"0A",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"AA",X"00",X"AA",X"00",X"AA",X"80",X"AA",X"A0",X"AA",X"A0",
+		X"A8",X"00",X"A8",X"00",X"28",X"00",X"28",X"02",X"28",X"02",X"28",X"02",X"28",X"0A",X"08",X"0A",
+		X"08",X"2A",X"20",X"2A",X"A0",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"28",X"80",X"28",X"80",X"2A",X"80",X"2A",X"80",X"2A",
+		X"02",X"00",X"02",X"00",X"02",X"80",X"02",X"80",X"02",X"80",X"02",X"80",X"02",X"80",X"82",X"80",
+		X"80",X"80",X"80",X"80",X"A0",X"80",X"AA",X"80",X"AA",X"80",X"AA",X"80",X"AA",X"80",X"AA",X"80",
+		X"80",X"2A",X"80",X"2A",X"80",X"2A",X"80",X"2A",X"80",X"2A",X"00",X"0A",X"00",X"02",X"00",X"02",
+		X"AA",X"80",X"AA",X"80",X"AA",X"80",X"AA",X"80",X"AA",X"80",X"AA",X"80",X"2A",X"00",X"2A",X"00",
+		X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"02",X"A0",X"02",X"A0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",
+		X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",X"0A",X"A8",
+		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"A8",X"AA",X"A8",X"AA",X"A8",X"AA",X"AA",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/sdram.sv b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/sdram.sv
new file mode 100644
index 00000000..49ea563d
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/sdram.sv	
@@ -0,0 +1,343 @@
+//
+// sdram.v
+//
+// sdram controller implementation for the MiST board
+// https://github.com/mist-devel/mist-board
+// 
+// Copyright (c) 2013 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2019 Gyorgy Szombathelyi
+//
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+
+module sdram (
+
+	// interface to the MT48LC16M16 chip
+	inout  reg [15:0] SDRAM_DQ,   // 16 bit bidirectional data bus
+	output reg [12:0] SDRAM_A,    // 13 bit multiplexed address bus
+	output reg        SDRAM_DQML, // two byte masks
+	output reg        SDRAM_DQMH, // two byte masks
+	output reg [1:0]  SDRAM_BA,   // two banks
+	output            SDRAM_nCS,  // a single chip select
+	output            SDRAM_nWE,  // write enable
+	output            SDRAM_nRAS, // row address select
+	output            SDRAM_nCAS, // columns address select
+
+	// cpu/chipset interface
+	input             init_n,     // init signal after FPGA config to initialize RAM
+	input             clk,        // sdram clock
+
+	input             port1_req,
+	output reg        port1_ack,
+	input             port1_we,
+	input      [23:1] port1_a,
+	input       [1:0] port1_ds,
+	input      [15:0] port1_d,
+	output reg [15:0] port1_q,
+
+	input      [16:1] cpu1_addr,
+	output reg [15:0] cpu1_q,
+	input      [16:1] cpu2_addr,
+	output reg [15:0] cpu2_q,
+
+	input             port2_req,
+	output reg        port2_ack,
+	input             port2_we,
+	input      [23:1] port2_a,
+	input       [1:0] port2_ds,
+	input      [15:0] port2_d,
+	output reg [31:0] port2_q,
+	
+	input      [16:2] sp_addr,
+	output reg [31:0] sp_q
+);
+
+localparam RASCAS_DELAY   = 3'd2;   // tRCD=20ns -> 2 cycles@<100MHz
+localparam BURST_LENGTH   = 3'b001; // 000=1, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE    = 1'b0;   // 0=sequential, 1=interleaved
+localparam CAS_LATENCY    = 3'd2;   // 2/3 allowed
+localparam OP_MODE        = 2'b00;  // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1;   // 0= write burst enabled, 1=only single access write
+
+localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 
+
+// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
+localparam RFRSH_CYCLES = 10'd842;
+
+// ---------------------------------------------------------------------
+// ------------------------ cycle state machine ------------------------
+// ---------------------------------------------------------------------
+
+/*
+ SDRAM state machine for 2 bank interleaved access
+ 1 word burst, CL2
+cmd issued  registered
+ 0 RAS0     cas1 - data0 read burst terminated
+ 1          ras0
+ 2          data1 returned
+ 3 CAS0     data1 returned
+ 4 RAS1     cas0
+ 5          ras1
+ 6 CAS1     data0 returned
+*/
+
+localparam STATE_RAS0      = 3'd0;   // first state in cycle
+localparam STATE_RAS1      = 3'd4;   // Second ACTIVE command after RAS0 + tRRD (15ns)
+localparam STATE_CAS0      = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
+localparam STATE_CAS1      = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
+localparam STATE_READ0     = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
+localparam STATE_READ1     = 3'd3;
+localparam STATE_DS1b      = 3'd0;
+localparam STATE_READ1b    = 3'd4;
+localparam STATE_LAST      = 3'd6;
+
+reg [2:0] t;
+
+always @(posedge clk) begin
+	t <= t + 1'd1;
+	if (t == STATE_LAST) t <= STATE_RAS0;
+end
+
+// ---------------------------------------------------------------------
+// --------------------------- startup/reset ---------------------------
+// ---------------------------------------------------------------------
+
+// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
+// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
+reg [4:0]  reset;
+reg        init = 1'b1;
+always @(posedge clk, negedge init_n) begin
+	if(!init_n) begin
+		reset <= 5'h1f;
+		init <= 1'b1;
+	end else begin
+		if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
+		init <= !(reset == 0);
+	end
+end
+
+// ---------------------------------------------------------------------
+// ------------------ generate ram control signals ---------------------
+// ---------------------------------------------------------------------
+
+// all possible commands
+localparam CMD_INHIBIT         = 4'b1111;
+localparam CMD_NOP             = 4'b0111;
+localparam CMD_ACTIVE          = 4'b0011;
+localparam CMD_READ            = 4'b0101;
+localparam CMD_WRITE           = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE       = 4'b0010;
+localparam CMD_AUTO_REFRESH    = 4'b0001;
+localparam CMD_LOAD_MODE       = 4'b0000;
+
+reg [3:0]  sd_cmd;   // current command sent to sd ram
+reg [15:0] sd_din;
+// drive control signals according to current command
+assign SDRAM_nCS  = sd_cmd[3];
+assign SDRAM_nRAS = sd_cmd[2];
+assign SDRAM_nCAS = sd_cmd[1];
+assign SDRAM_nWE  = sd_cmd[0];
+
+reg [24:1] addr_latch[2];
+reg [24:1] addr_latch_next[2];
+reg [16:1] addr_last[2];
+reg [16:2] addr_last2[2];
+reg [15:0] din_latch[2];
+reg  [1:0] oe_latch;
+reg  [1:0] we_latch;
+reg  [1:0] ds[2];
+
+localparam PORT_NONE  = 2'd0;
+localparam PORT_CPU1  = 2'd1;
+localparam PORT_CPU2  = 2'd2;
+localparam PORT_SP    = 2'd1;
+localparam PORT_REQ   = 2'd3;
+
+reg  [1:0] next_port[2];
+reg  [1:0] port[2];
+
+reg        refresh;
+reg [10:0] refresh_cnt;
+wire       need_refresh = (refresh_cnt >= RFRSH_CYCLES);
+
+// PORT1: bank 0,1
+always @(*) begin
+	if (refresh) begin
+		next_port[0] = PORT_NONE;
+		addr_latch_next[0] = addr_latch[0];
+	end else if (port1_req ^ port1_ack) begin
+		next_port[0] = PORT_REQ;
+		addr_latch_next[0] = { 1'b0, port1_a };
+	end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
+		next_port[0] = PORT_CPU1;
+		addr_latch_next[0] = { 8'd0, cpu1_addr };
+	end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
+		next_port[0] = PORT_CPU2;
+		addr_latch_next[0] = { 8'd0, cpu2_addr };
+	end else begin
+		next_port[0] = PORT_NONE;
+		addr_latch_next[0] = addr_latch[0];
+	end
+end
+
+// PORT1: bank 2,3
+always @(*) begin
+	if (port2_req ^ port2_ack) begin
+		next_port[1] = PORT_REQ;
+		addr_latch_next[1] = { 1'b1, port2_a };
+	end else if (sp_addr != addr_last2[PORT_SP]) begin
+		next_port[1] = PORT_SP;
+		addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
+	end else begin
+		next_port[1] = PORT_NONE;
+		addr_latch_next[1] = addr_latch[1];
+	end
+end
+
+always @(posedge clk) begin
+
+	// permanently latch ram data to reduce delays
+	sd_din <= SDRAM_DQ;
+	SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
+	{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
+	sd_cmd <= CMD_NOP;  // default: idle
+	refresh_cnt <= refresh_cnt + 1'd1;
+
+	if(init) begin
+		// initialization takes place at the end of the reset phase
+		if(t == STATE_RAS0) begin
+
+			if(reset == 15) begin
+				sd_cmd <= CMD_PRECHARGE;
+				SDRAM_A[10] <= 1'b1;      // precharge all banks
+			end
+
+			if(reset == 10 || reset == 8) begin
+				sd_cmd <= CMD_AUTO_REFRESH;
+			end
+
+			if(reset == 2) begin
+				sd_cmd <= CMD_LOAD_MODE;
+				SDRAM_A <= MODE;
+				SDRAM_BA <= 2'b00;
+			end
+		end
+	end else begin
+		// RAS phase
+		// bank 0,1
+		if(t == STATE_RAS0) begin
+			addr_latch[0] <= addr_latch_next[0];
+			port[0] <= next_port[0];
+			{ oe_latch[0], we_latch[0] } <= 2'b00;
+
+			if (next_port[0] != PORT_NONE) begin
+				sd_cmd <= CMD_ACTIVE;
+				SDRAM_A <= addr_latch_next[0][22:10];
+				SDRAM_BA <= addr_latch_next[0][24:23];
+				addr_last[next_port[0]] <= addr_latch_next[0][16:1];
+				if (next_port[0] == PORT_REQ) begin
+					{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
+					ds[0] <= port1_ds;
+					din_latch[0] <= port1_d;
+				end else begin
+					{ oe_latch[0], we_latch[0] } <= 2'b10;
+					ds[0] <= 2'b11;
+				end
+			end
+		end
+
+		// bank 2,3
+		if(t == STATE_RAS1) begin
+			refresh <= 1'b0;
+			addr_latch[1] <= addr_latch_next[1];
+			{ oe_latch[1], we_latch[1] } <= 2'b00;
+			port[1] <= next_port[1];
+
+			if (next_port[1] != PORT_NONE) begin
+				sd_cmd <= CMD_ACTIVE;
+				SDRAM_A <= addr_latch_next[1][22:10];
+				SDRAM_BA <= addr_latch_next[1][24:23];
+				addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
+				if (next_port[1] == PORT_REQ) begin
+					{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
+					ds[1] <= port2_ds;
+					din_latch[1] <= port2_d;
+				end else begin
+					{ oe_latch[1], we_latch[1] } <= 2'b10;
+					ds[1] <= 2'b11;
+				end
+			end
+
+			if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
+				refresh <= 1'b1;
+				refresh_cnt <= 0;
+				sd_cmd <= CMD_AUTO_REFRESH;
+			end
+		end
+
+		// CAS phase
+		if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
+			sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
+			{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
+			if (we_latch[0]) begin
+				SDRAM_DQ <= din_latch[0];
+				port1_ack <= port1_req;
+			end
+			SDRAM_A <= { 4'b0010, addr_latch[0][9:1] };  // auto precharge
+			SDRAM_BA <= addr_latch[0][24:23];
+		end
+
+		if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
+			sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
+			{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+			if (we_latch[1]) begin
+				SDRAM_DQ <= din_latch[1];
+				port2_ack <= port2_req;
+			end
+			SDRAM_A <= { 4'b0010, addr_latch[1][9:1] };  // auto precharge
+			SDRAM_BA <= addr_latch[1][24:23];
+		end
+
+		// Data returned
+		if(t == STATE_READ0 && oe_latch[0]) begin
+			case(port[0])
+				PORT_REQ:  begin port1_q <= sd_din; port1_ack <= port1_req; end
+				PORT_CPU1: begin cpu1_q  <= sd_din; end
+				PORT_CPU2: begin cpu2_q  <= sd_din; end
+				default: ;
+			endcase;
+		end
+
+		if(t == STATE_READ1 && oe_latch[1]) begin
+			case(port[1])
+				PORT_REQ:	port2_q[15:0] <= sd_din;
+				PORT_SP :    sp_q[15:0] <= sd_din;
+				default: ;
+			endcase;
+		end
+
+		if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
+
+		if(t == STATE_READ1b && oe_latch[1]) begin
+			case(port[1])
+				PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
+				PORT_SP : begin    sp_q[31:16] <= sd_din; end
+				default: ;
+			endcase;
+		end
+	end
+end
+
+endmodule
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/timber.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/timber.vhd
new file mode 100644
index 00000000..23ce1436
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/timber.vhd	
@@ -0,0 +1,991 @@
+---------------------------------------------------------------------------------
+-- Timber by Dar (darfpga@aol.fr) (22/11/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+--
+-- release rev 00 : initial release
+--  (22/11/2019)
+--
+---------------------------------------------------------------------------------
+-- gen_ram.vhd & io_ps2_keyboard
+-------------------------------- 
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- T80/T80se - Version : 304
+-----------------------------
+-- Z80 compatible microprocessor core
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+---------------------------------------------------------------------------------
+-- YM2149 (AY-3-8910)
+-- Copyright (c) MikeJ - Jan 2005
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+
+--  Features :
+--   Video        : VGA 31Khz/60Hz progressive and TV 15kHz interlaced
+--   Coctail mode : NO
+--   Sound        : OK
+
+--  Use with MAME roms from timber.zip
+--
+--  Use make_timber_proms.bat to build vhd file from binaries
+--  (CRC list included)
+
+--  Timber (midway mcr) Hardware caracteristics :
+--
+--  VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram,
+--    sprite data ram, I/O, sound board register and trigger.
+--		  56Kx8bits program rom
+--
+--    One char/background tile map 30x32
+--      2x8Kx8bits graphics rom 4bits/pixel + 2 bit color set
+--      rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue
+--
+--    128 sprites, up to ~30/line, 32x32 with flip H/V
+--      4x32Kx8bits graphics rom 4bits/pixel + 2 bit color set
+--      rbg programmable ram palette 64 colors 9bits : 3red 3green 3blue 
+--
+--    Working ram : 2Kx8bits
+--    video (char/background) ram  : 2Kx8bits
+--    Sprites ram : 512x8bits + 512x8bits cache buffer
+
+--    Sprites line buffer rams (graphics and colors) : 1 scan line delay flip/flop 2x256x16bits
+--
+--  SOUND : see tron_sound_board.vhd
+
+---------------------------------------------------------------------------------
+--  Schematics remarks :
+--
+--		Display is 512x480 pixels  (video 635x525 lines @ 20MHz )
+
+--       635/20e6  = 31.75us per line  (31.750KHz)
+--       31.75*525 = 16.67ms per frame (59.99Hz)
+--        
+--    Original video is interlaced 240 display lines per 1/2 frame
+--
+--       H0 and V0 are not use for background => each bg tile is 16x16 pixel but 
+--			background graphics is 2x2 pixels defintion.
+--
+--			Sprite are 32x32 pixels with 1x1 pixel definition, 16 lines for odd 1/2
+--       frame and 16 lines for even 2/2 frame thanks to V8 on sprite rom ROMAD2
+--       (look at 74ls86 G1 pin 9 on video genration board schematics)
+--
+--    *H and V stand for Horizontal en Vertical counter (Hcnt, Vcnt in VHDL code)
+--
+--    /!\ For VHDL port interlaced video mode is replaced with progressive video 
+--        mode.
+--
+--    Real hardware uses background ram access after each 1/2 frame (~line 240
+--    and 480). In these areas cpu can access ram since scanlines are out of
+--    visible display. In progessive mode there are video access around lines 240.
+--    These accesses will create video artfacts aound mid display. In VHDL code
+--    ram access is muliplexed between cpu and scanlines by using hcnt(0) in
+--    order to avoid these artefacts.
+--
+--    Sprite data are stored first by cpu into a 'cache' buffer (staging ram at
+--    K6/L6) this buffer is read and write for cpu. After visible display, cache
+--    buffer (512x8) is moved to actual sprite ram buffer (512x8). Actual sprite
+--    buffer is access by transfer address counter during 2 scanlines after 
+--    visible area and only by sprite machine during visible area.
+--
+--    Thus cpu can read and update sprites position during entire frame except
+--    during 2 lines.
+-- 
+--    Sprite data are organised (as seen by cpu F000-F1FF) into 128 * 4bytes.
+--    bytes #1 : Vertical position
+--    bytes #2 : code and attribute
+--    bytes #3 : Horizontal position
+--    bytes #4 : not used
+--
+--		Athough 1x1 pixel defintion sprite position horizontal/vertical is made on
+--    on a 2x2 grid (due to only 8bits for position data)
+--
+--    Z80-CTC : interruption ar managed by CTC chip. ONly channel 3 is trigered
+--    by hardware signal line 493. channel 0 to 2 are in timer mode. Schematic 
+--    show zc/to of channel 0 connected to clk/trg of channel 1. This seems to be
+--    unsued for that (Kick) game. 
+--
+--    Z80-CTC VHDL port keep separated interrupt controler and each counter so 
+--    one can use them on its own. Priority daisy-chain is not done (not used in
+--    that game). clock polarity selection is not done since it has no meaning
+--    with digital clock/enable (e.g cpu_ena signal) method.
+--
+--    Ressource : input clock 40MHz is chosen to allow easy making of 20MHz for
+--    pixel clock and 8MHz signal for amplitude modulation circuit of ssio board
+--
+--  TODO :
+--    Working ram could be initialized to set initial difficulty level and
+--    initial bases (live) number. Otherwise one can set it up by using service
+--    menu at each power up.
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity timber is
+port(
+ clock_40     : in std_logic;
+ reset        : in std_logic;
+ tv15Khz_mode : in std_logic;
+ video_r        : out std_logic_vector(2 downto 0);
+ video_g        : out std_logic_vector(2 downto 0);
+ video_b        : out std_logic_vector(2 downto 0);
+ video_clk      : out std_logic;
+ video_csync    : out std_logic;
+ video_blankn   : out std_logic;
+ video_hs       : out std_logic;
+ video_vs       : out std_logic;
+ 
+ separate_audio : in  std_logic;
+ audio_out_l    : out std_logic_vector(15 downto 0);
+ audio_out_r    : out std_logic_vector(15 downto 0);
+  
+ coin1          : in std_logic;
+ coin2          : in std_logic;
+ start1         : in std_logic; 
+ start2         : in std_logic; 
+ 
+ p1_left        : in std_logic; 
+ p1_right       : in std_logic; 
+ p1_up          : in std_logic; 
+ p1_down        : in std_logic;
+ p1_fire1       : in std_logic;
+ p1_fire2       : in std_logic;
+
+ p2_left        : in std_logic; 
+ p2_right       : in std_logic; 
+ p2_up          : in std_logic; 
+ p2_down        : in std_logic;
+ p2_fire1       : in std_logic;
+ p2_fire2       : in std_logic;
+ 
+ coin_meters    : in std_logic;
+ upright        : in std_logic;
+ demo_sound     : in std_logic;
+ service        : in std_logic;
+
+ cpu_rom_addr   : out std_logic_vector(15 downto 0);
+ cpu_rom_do     : in std_logic_vector(7 downto 0);
+ snd_rom_addr   : out std_logic_vector(13 downto 0);
+ snd_rom_do     : in std_logic_vector(7 downto 0);
+
+ sp_addr        : out std_logic_vector(14 downto 0);
+-- sp_graphx_do   : in std_logic_vector(7 downto 0);
+ sp_graphx32_do : in std_logic_vector(31 downto 0);
+
+ dbg_cpu_addr : out std_logic_vector(15 downto 0)
+ );
+end timber;
+
+architecture struct of timber is
+
+ signal reset_n   : std_logic;
+ signal clock_vid : std_logic;
+ signal clock_vidn: std_logic;
+ signal clock_cnt : std_logic_vector(3 downto 0) := "0000";
+
+ signal hcnt    : std_logic_vector(9 downto 0) := (others=>'0'); -- horizontal counter
+ signal hflip   : std_logic_vector(9 downto 0) := (others=>'0'); -- horizontal counter flip
+ signal vcnt    : std_logic_vector(9 downto 0) := (others=>'0'); -- vertical counter
+ signal vflip   : std_logic_vector(9 downto 0) := (others=>'0'); -- vertical counter flip
+ 
+ signal hs_cnt, vs_cnt :std_logic_vector(9 downto 0) ;
+ signal hsync0, hsync1, hsync2, hsync3, hsync4 : std_logic;
+ signal top_frame : std_logic := '0';
+ 
+ signal pix_ena     : std_logic;
+ signal cpu_ena     : std_logic;
+
+ signal cpu_addr    : std_logic_vector(15 downto 0);
+ signal cpu_di      : std_logic_vector( 7 downto 0);
+ signal cpu_do      : std_logic_vector( 7 downto 0);
+ signal cpu_wr_n    : std_logic;
+ signal cpu_rd_n    : std_logic;
+ signal cpu_mreq_n  : std_logic;
+ signal cpu_ioreq_n : std_logic;
+ signal cpu_irq_n   : std_logic;
+ signal cpu_m1_n    : std_logic;
+ 
+ signal ctc_controler_we  : std_logic;
+ signal ctc_controler_do  : std_logic_vector(7 downto 0);
+ signal ctc_int_ack       : std_logic;
+
+ signal ctc_counter_0_we  : std_logic;
+-- signal ctc_counter_0_trg : std_logic;
+ signal ctc_counter_0_do  : std_logic_vector(7 downto 0);
+ signal ctc_counter_0_int : std_logic;
+
+ signal ctc_counter_1_we  : std_logic;
+-- signal ctc_counter_1_trg : std_logic;
+ signal ctc_counter_1_do  : std_logic_vector(7 downto 0);
+ signal ctc_counter_1_int : std_logic;
+ 
+ signal ctc_counter_2_we  : std_logic;
+-- signal ctc_counter_2_trg : std_logic;
+ signal ctc_counter_2_do  : std_logic_vector(7 downto 0);
+ signal ctc_counter_2_int : std_logic;
+ 
+ signal ctc_counter_3_we  : std_logic;
+ signal ctc_counter_3_trg : std_logic;
+ signal ctc_counter_3_do  : std_logic_vector(7 downto 0);
+ signal ctc_counter_3_int : std_logic;
+ 
+-- signal cpu_rom_do : std_logic_vector( 7 downto 0);
+ 
+ signal wram_we    : std_logic;
+ signal wram_do    : std_logic_vector( 7 downto 0);
+
+ signal bg_ram_addr: std_logic_vector(10 downto 0);
+ signal bg_ram_we  : std_logic;
+ signal bg_ram_do  : std_logic_vector(7 downto 0);
+ signal bg_ram_do_r: std_logic_vector(7 downto 0); -- registred ram data for cpu
+
+ signal bg_code         : std_logic_vector(7 downto 0); 
+ signal bg_code_r       : std_logic_vector(7 downto 0); 
+ signal bg_attr         : std_logic_vector(7 downto 0);
+
+ signal bg_code_line    : std_logic_vector(13 downto 0);
+ signal bg_graphx1_do   : std_logic_vector( 7 downto 0);
+ signal bg_graphx2_do   : std_logic_vector( 7 downto 0);
+ signal bg_palette_addr : std_logic_vector( 5 downto 0);
+ 
+ signal sp_ram_cache_addr       : std_logic_vector(8 downto 0);
+ signal sp_ram_cache_we         : std_logic;
+ signal sp_ram_cache_do         : std_logic_vector(7 downto 0);
+ signal sp_ram_cache_do_r       : std_logic_vector(7 downto 0);-- registred ram data for cpu
+ 
+ signal move_buf          : std_logic;
+ signal sp_ram_addr       : std_logic_vector(8 downto 0);
+ signal sp_ram_we         : std_logic;
+ signal sp_ram_do         : std_logic_vector(7 downto 0);
+
+ signal sp_cnt          : std_logic_vector( 6 downto 0);
+ signal sp_code         : std_logic_vector( 7 downto 0);
+ signal sp_attr         : std_logic_vector( 7 downto 0);
+ signal sp_input_phase  : std_logic_vector( 5 downto 0);
+
+ signal sp_done         : std_logic;
+ signal sp_vcnt         : std_logic_vector( 9 downto 0);
+ signal sp_line         : std_logic_vector( 4 downto 0);
+ signal sp_hcnt         : std_logic_vector( 8 downto 0); -- lsb used to mux rd/wr line buffer
+ signal sp_on_line      : std_logic;
+ signal sp_on_line_r    : std_logic;
+ signal sp_byte_cnt     : std_logic_vector( 1 downto 0);
+ signal sp_code_line_mux: std_logic_vector(16 downto 0);
+ signal sp_hflip        : std_logic_vector( 1 downto 0);
+ signal sp_vflip        : std_logic_vector( 4 downto 0);
+ 
+ signal sp_graphx_do    : std_logic_vector( 7 downto 0);
+ signal sp_graphx32_do_r: std_logic_vector(31 downto 0);
+ signal sp_graphx_mux   : std_logic_vector( 7 downto 0);
+ signal sp_mux_roms     : std_logic_vector( 1 downto 0);
+
+ signal sp_graphx_a     : std_logic_vector( 3 downto 0);
+ signal sp_graphx_b     : std_logic_vector( 3 downto 0);
+ signal sp_graphx_a_ok  : std_logic;
+ signal sp_graphx_b_ok  : std_logic;
+ 
+ signal sp_buffer_ram1_addr : std_logic_vector(7 downto 0);
+ signal sp_buffer_ram1a_we  : std_logic;
+ signal sp_buffer_ram1b_we  : std_logic;
+ signal sp_buffer_ram1a_di  : std_logic_vector( 7 downto 0);
+ signal sp_buffer_ram1b_di  : std_logic_vector( 7 downto 0);
+ signal sp_buffer_ram1a_do  : std_logic_vector( 7 downto 0);
+ signal sp_buffer_ram1b_do  : std_logic_vector( 7 downto 0);
+ signal sp_buffer_ram1_do_r : std_logic_vector(15 downto 0);
+ 
+ signal sp_buffer_ram2_addr : std_logic_vector(7 downto 0);
+ signal sp_buffer_ram2a_we  : std_logic;
+ signal sp_buffer_ram2b_we  : std_logic;
+ signal sp_buffer_ram2a_di  : std_logic_vector( 7 downto 0);
+ signal sp_buffer_ram2b_di  : std_logic_vector( 7 downto 0);
+ signal sp_buffer_ram2a_do  : std_logic_vector( 7 downto 0);
+ signal sp_buffer_ram2b_do  : std_logic_vector( 7 downto 0);
+ signal sp_buffer_ram2_do_r : std_logic_vector(15 downto 0);
+ 
+ signal sp_buffer_sel       : std_logic;
+ 
+ signal sp_vid              : std_logic_vector(3 downto 0);
+ signal sp_col              : std_logic_vector(3 downto 0);
+ signal sp_palette_addr     : std_logic_vector(5 downto 0);
+ 
+ signal palette_addr        : std_logic_vector(5 downto 0);
+ signal palette_we          : std_logic;
+ signal palette_do          : std_logic_vector(8 downto 0);
+
+ signal ssio_iowe : std_logic;
+ signal ssio_do   : std_logic_vector(7 downto 0);
+ 
+ signal input_0   : std_logic_vector(7 downto 0);
+ signal input_1   : std_logic_vector(7 downto 0);
+ signal input_2   : std_logic_vector(7 downto 0);
+ signal input_3   : std_logic_vector(7 downto 0);
+ signal input_4   : std_logic_vector(7 downto 0);
+   
+-- signal max_sprite: std_logic_vector(7 downto 0); -- dbg
+-- signal max_sprite_r: std_logic_vector(7 downto 0); -- dbg
+-- signal max_sprite_rr: std_logic_vector(7 downto 0); -- dbg
+ 
+begin
+
+clock_vid  <= clock_40;
+clock_vidn <= not clock_40;
+reset_n    <= not reset;
+
+-- debug 
+process (reset, clock_vid)
+begin
+ if rising_edge(clock_vid) and cpu_ena ='1' and cpu_mreq_n ='0' then
+   dbg_cpu_addr<= "000000000000000" & service; --cpu_addr;
+--   dbg_cpu_addr<= max_sprite_rr & "0000000" & service; --cpu_addr;
+ end if;
+end process;
+
+-- make enables clock from clock_vid
+process (clock_vid, reset)
+begin
+	if reset='1' then
+		clock_cnt <= (others=>'0');
+	else 
+		if rising_edge(clock_vid) then
+			if clock_cnt = "1111" then  -- divide by 16
+				clock_cnt <= (others=>'0');
+			else
+				clock_cnt <= clock_cnt + 1;
+			end if;
+		end if;
+	end if;   		
+end process;
+--
+cpu_ena <= '1' when clock_cnt(2 downto 0) = "111" else '0'; -- (5MHz for 91490 super cpu board)
+pix_ena <= '1' when (clock_cnt(1 downto 0) = "11" and tv15Khz_mode = '1') or         -- (10MHz)
+						  (clock_cnt(0) = '1'           and tv15Khz_mode = '0') else '0';  -- (20MHz)
+
+-----------------------------------
+-- Video scanner  634x525 @20Mhz --
+-- display 512x480               --
+-----------------------------------
+process (reset, clock_vid)
+begin
+	if reset='1' then
+		hcnt  <= (others=>'0');
+		vcnt  <= (others=>'0');
+		top_frame <= '0';
+	else 
+		if rising_edge(clock_vid) then
+			if pix_ena = '1' then
+		
+				hcnt <= hcnt + 1;
+				if hcnt = 633 then
+					hcnt <= (others=>'0');
+					vcnt <= vcnt + 1;
+					if (vcnt = 524 and tv15Khz_mode = '0') or (vcnt = 263 and tv15Khz_mode = '1') then
+						vcnt <= (others=>'0');
+						top_frame <= not top_frame;
+					end if;
+				end if;
+			
+				if tv15Khz_mode = '0' then 
+							--	progessive mode
+				
+					if vcnt = 490-1 then video_vs <= '0'; end if; -- front porch 10
+					if vcnt = 492-1 then video_vs <= '1'; end if; -- sync pulse   2
+																				 -- back porch  33 
+						
+					if hcnt = 512+13+9+6 then video_hs <= '0'; end if; -- front porch 16/25*20 = 13
+					if hcnt = 512+90+9+6 then video_hs <= '1'; end if; -- sync pulse  96/25*20 = 77
+																				   -- back porch  48/25*20 = 38
+					video_blankn <= '0';
+					if hcnt >= 2+16-1 and  hcnt < 514+16-1 and
+						vcnt >= 2 and  vcnt < 481 then video_blankn <= '1';end if;
+				
+				else    -- interlaced mode
+				 
+				if hcnt = 530+22 then 
+					hs_cnt <= (others => '0');
+					if (vcnt = 240) then
+						vs_cnt <= (others => '0');
+					else
+						vs_cnt <= vs_cnt +1;
+					end if;
+					
+					if vcnt = 240 then video_vs <= '0'; end if;
+					if vcnt = 242 then video_vs <= '1'; end if;
+
+				else 
+					hs_cnt <= hs_cnt + 1;
+				end if;
+				
+				video_blankn <= '0';				
+				if hcnt >= 2+16 and  hcnt < 514+16 and
+					vcnt >= 1 and  vcnt < 241 then video_blankn <= '1';end if;
+
+				
+				if    hs_cnt =  0 then hsync0 <= '0';
+				elsif hs_cnt = 47 then hsync0 <= '1';
+				end if;
+
+				if    hs_cnt =      0  then hsync1 <= '0';
+				elsif hs_cnt =     23  then hsync1 <= '1';
+				elsif hs_cnt = 317+ 0  then hsync1 <= '0';
+				elsif hs_cnt = 317+23  then hsync1 <= '1';
+				end if;
+		
+				if    hs_cnt =      0  then hsync2 <= '0';
+				elsif hs_cnt = 317-47  then hsync2 <= '1';
+				elsif hs_cnt = 317     then hsync2 <= '0';
+				elsif hs_cnt = 634-47  then hsync2 <= '1';
+				end if;
+
+				
+				if    hs_cnt =      0  then hsync3 <= '0';
+				elsif hs_cnt =     23  then hsync3 <= '1';
+				elsif hs_cnt = 317     then hsync3 <= '0';
+				elsif hs_cnt = 634-47  then hsync3 <= '1';
+				end if;
+
+				if    hs_cnt =      0  then hsync4 <= '0';
+				elsif hs_cnt = 317-47  then hsync4 <= '1';
+				elsif hs_cnt = 317     then hsync4 <= '0';
+				elsif hs_cnt = 317+23  then hsync4 <= '1';
+				end if;
+				
+				
+				if     vs_cnt =  1 then video_csync <= hsync1;
+				elsif  vs_cnt =  2 then video_csync <= hsync1;
+				elsif  vs_cnt =  3 then video_csync <= hsync1;
+				elsif  vs_cnt =  4 and top_frame = '1' then video_csync <= hsync3;
+				elsif  vs_cnt =  4 and top_frame = '0' then video_csync <= hsync1;
+				elsif  vs_cnt =  5 then video_csync <= hsync2;
+				elsif  vs_cnt =  6 then video_csync <= hsync2;
+				elsif  vs_cnt =  7 and  top_frame = '1' then video_csync <= hsync4;
+				elsif  vs_cnt =  7 and  top_frame = '0' then video_csync <= hsync2;
+				elsif  vs_cnt =  8 then video_csync <= hsync1;
+				elsif  vs_cnt =  9 then video_csync <= hsync1;
+				elsif  vs_cnt = 10 then video_csync <= hsync1;
+				elsif  vs_cnt = 11 then video_csync <= hsync0;
+				else                    video_csync <= hsync0;
+				end if;	
+				
+				
+				end if;
+
+			end if;
+		end if;
+	end if;
+end process;
+
+--------------------
+-- players inputs --
+--------------------
+-- "111" for test & tilt & unused
+input_0 <= not service & "111" & not start2 & not start1 & not coin2 & not coin1;
+input_1 <= "11" & not p1_fire2 & not p1_fire1 & not p1_up & not p1_down & not p1_left &  not p1_right;
+input_2 <= "11" & not p2_fire2 & not p2_fire1 & not p2_up & not p2_down & not p2_left &  not p2_right;
+input_3 <= coin_meters & upright & "111" & demo_sound & "11";
+input_4 <= x"FF";
+
+------------------------------------------
+-- cpu data input with address decoding --
+------------------------------------------
+cpu_di <= cpu_rom_do   		 when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"E" else    -- 0000-DFFF
+			 wram_do     		 when cpu_mreq_n = '0' and (cpu_addr and X"F800") = x"E000" else -- E000-E7FF
+			 sp_ram_cache_do_r when cpu_mreq_n = '0' and (cpu_addr and x"FC00") = x"E800" else -- sprite ram  E800-E9FF + mirroring 0200
+			 bg_ram_do_r       when cpu_mreq_n = '0' and (cpu_addr and x"F800") = x"F000" else -- video ram   F000-F7FF
+			 ctc_controler_do  when cpu_ioreq_n = '0' and cpu_m1_n = '0'                  else -- ctc ctrl (interrupt vector)
+			 ssio_do           when cpu_ioreq_n = '0' and cpu_addr(7 downto 5) = "000" else  -- 0x00-0x1F
+ 			 ctc_counter_3_do  when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F3" else
+ 			 ctc_counter_2_do  when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F2" else
+ 			 ctc_counter_1_do  when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F1" else
+ 			 ctc_counter_0_do  when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else
+   		 X"FF";
+		 
+------------------------------------------------------------------------
+-- Misc registers : ctc write enable / interrupt acknowledge
+------------------------------------------------------------------------
+ctc_counter_3_trg <= '1' when (vcnt = 246 and tv15Khz_mode = '1') or (vcnt = 493 and tv15Khz_mode = '0')else '0';
+ctc_counter_3_we  <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F3" else '0';
+ctc_counter_2_we  <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F2" else '0';
+ctc_counter_1_we  <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F1" else '0';
+ctc_counter_0_we  <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else '0';
+ctc_controler_we  <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else '0'; -- only channel 0 receive int vector
+ctc_int_ack       <= '1' when cpu_ioreq_n = '0' and cpu_m1_n = '0' else '0';
+
+------------------------------------------
+-- write enable / ram access from CPU --
+------------------------------------------
+wram_we         <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F800") = x"E000" else '0';
+sp_ram_cache_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"FC00") = x"E800" and hcnt(0) = '0' else '0';
+bg_ram_we       <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F800") = x"F000" and hcnt(0) = '0' else '0';
+
+ssio_iowe <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' else '0';
+
+----------------------------------
+--------- sprite machine ---------
+----  91464 Super Video Board ----
+----------------------------------
+--hflip <= not(hcnt);  -- apply mirror horizontal flip
+hflip <= hcnt;       -- do not apply mirror horizontal flip
+
+vflip <= vcnt(8 downto 0) & not top_frame when tv15Khz_mode = '1' else vcnt; -- do not apply mirror flip
+
+sp_buffer_sel <= vflip(1) when tv15Khz_mode = '1' else vflip(0);
+
+process (clock_vid)
+begin
+	if rising_edge(clock_vid) then
+
+-- debug -- max sprite counter
+--	if vcnt = 0 and hcnt = 0 and pix_ena = '1' then 
+--		max_sprite_r <= (others => '0');
+--		if max_sprite_r > max_sprite_rr then
+--			max_sprite_rr <= max_sprite_r;
+--		end if;
+--	end if;
+	
+	if hcnt = 0 then
+		sp_cnt <= (others => '0');
+		sp_input_phase <= (others => '0');
+		sp_on_line <= '0';
+		sp_done <= '0';			
+--		max_sprite <= (others => '0');
+--		if max_sprite > max_sprite_r then
+--			max_sprite_r <= max_sprite;
+--		end if;
+	end if;
+			
+	if sp_done = '0' then
+		sp_input_phase <= sp_input_phase + 1 ;
+		if sp_input_phase >= 10 then sp_hcnt <= sp_hcnt + 1; end if;
+
+		case sp_input_phase is
+			when "000000" => 
+				if sp_vcnt(8 downto 5) = x"F" then -- and sp_ram_do > x"10" then
+					sp_line <= sp_vcnt(4 downto 0);
+				else
+					sp_input_phase <= (others => '0');
+					sp_cnt <= sp_cnt + 1;
+					if sp_cnt = "1111111" then sp_done <= '1'; end if;
+				end if;
+				sp_byte_cnt <= (others => '0');
+			when "000001" => 
+				sp_attr <= sp_ram_do;
+			when "000010" => 
+				sp_code <= sp_ram_do;
+				sp_addr <= sp_ram_do(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt xor sp_hflip); -- graphics rom addr
+			when "000011" => 
+				sp_hcnt <= sp_ram_do & '0';
+			when "001010" => -- 10
+				sp_graphx32_do_r <= sp_graphx32_do; -- latch incoming sprite data
+				sp_addr <= sp_code(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt+1 xor sp_hflip); -- advance graphics rom addr
+				sp_on_line <= '1';
+      when "010010"|"011010"|"100010" => -- 18,26,34
+				sp_graphx32_do_r <= sp_graphx32_do; -- latch incoming sprite data
+				sp_addr <= sp_code(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt+2 xor sp_hflip); -- advance graphics rom addr
+			  sp_byte_cnt <= sp_byte_cnt + 1;
+			when "101010" => -- 42
+				sp_on_line <= '0';
+				sp_input_phase <= (others => '0');
+				sp_cnt <= sp_cnt + 1;
+				if sp_cnt = "1111111" then sp_done <= '1'; end if;
+			when others =>
+				null;
+		end case;
+		sp_mux_roms <= sp_input_phase(2 downto 1);
+	end if;
+		
+	if pix_ena = '1' then 
+		if hcnt(0) = '0' then
+			sp_buffer_ram1_do_r <= sp_buffer_ram1b_do & sp_buffer_ram1a_do;
+			sp_buffer_ram2_do_r <= sp_buffer_ram2b_do & sp_buffer_ram2a_do;
+		end if;		
+	end if;
+
+	end if;
+end process;	
+
+-- sp_ram_cache can be read/write by cpu when hcnt(0) = 0;
+-- sp_ram_cache can be read by sprite machine when hcnt(0) = 1;
+
+sp_ram_cache_addr <= cpu_addr(8 downto 0) when hcnt(0) = '0' else sp_ram_addr;
+
+move_buf    <= '1' when (vcnt(8 downto 1) = 250 and tv15Khz_mode = '0') or (vcnt(7 downto 1) = 125 and tv15Khz_mode = '1') else '0'; -- line 500-501
+sp_ram_addr <= vcnt(0) & hcnt(8 downto 1) when move_buf = '1' else sp_cnt & sp_input_phase(1 downto 0);
+sp_ram_we   <= hcnt(0) when move_buf = '1' else '0';
+
+sp_vcnt <= vflip + (sp_ram_do & '0') -1 ; -- valid when sp_input_phase = 0
+
+sp_hflip <= (others => sp_attr(4));
+sp_vflip <= (others => sp_attr(5));
+
+sp_graphx_do <= sp_graphx32_do_r( 7 downto  0) when (sp_hflip(0) = '0' and sp_mux_roms = "01") or (sp_hflip(0) = '1' and sp_mux_roms = "00") else
+                sp_graphx32_do_r(15 downto  8) when (sp_hflip(0) = '0' and sp_mux_roms = "10") or (sp_hflip(0) = '1' and sp_mux_roms = "11") else
+					      sp_graphx32_do_r(23 downto 16) when (sp_hflip(0) = '0' and sp_mux_roms = "11") or (sp_hflip(0) = '1' and sp_mux_roms = "10") else
+					      sp_graphx32_do_r(31 downto 24);-- when (sp_hflip(0) = '0' and sp_mux_roms = "00") or (sp_hflip(0) = '1' and sp_mux_roms = "01") ;
+											
+sp_graphx_a <= sp_graphx_do(7 downto 4) when sp_hflip(0) = '1' else sp_graphx_do(3 downto 0);
+sp_graphx_b <= sp_graphx_do(3 downto 0) when sp_hflip(0) = '1' else sp_graphx_do(7 downto 4);
+
+sp_graphx_a_ok <= '1' when sp_graphx_a /= x"0" else '0';
+sp_graphx_b_ok <= '1' when sp_graphx_b /= x"0" else '0';
+								
+sp_buffer_ram1a_di  <= sp_attr(3 downto 0) & sp_graphx_a                when sp_buffer_sel = '1' else x"00";
+sp_buffer_ram1b_di  <= sp_attr(3 downto 0) & sp_graphx_b                when sp_buffer_sel = '1' else x"00";
+sp_buffer_ram1_addr <= sp_hcnt(8 downto 1)                              when sp_buffer_sel = '1' else hflip(8 downto 1) - x"04";
+sp_buffer_ram1a_we  <= not sp_hcnt(0) and sp_on_line and sp_graphx_a_ok when sp_buffer_sel = '1' else hcnt(0);
+sp_buffer_ram1b_we  <= not sp_hcnt(0) and sp_on_line and sp_graphx_b_ok when sp_buffer_sel = '1' else hcnt(0);
+
+sp_buffer_ram2a_di  <= sp_attr(3 downto 0) & sp_graphx_a                when sp_buffer_sel = '0' else x"00";
+sp_buffer_ram2b_di  <= sp_attr(3 downto 0) & sp_graphx_b                when sp_buffer_sel = '0' else x"00";
+sp_buffer_ram2_addr <= sp_hcnt(8 downto 1)                              when sp_buffer_sel = '0' else hflip(8 downto 1) - x"04";
+sp_buffer_ram2a_we  <= not sp_hcnt(0) and sp_on_line and sp_graphx_a_ok when sp_buffer_sel = '0' else hcnt(0);
+sp_buffer_ram2b_we  <= not sp_hcnt(0) and sp_on_line and sp_graphx_b_ok when sp_buffer_sel = '0' else hcnt(0);
+
+sp_vid <= sp_buffer_ram1_do_r(11 downto  8) when (sp_buffer_sel = '0') and (hflip(0) = '1') else
+		    sp_buffer_ram1_do_r( 3 downto  0) when (sp_buffer_sel = '0') and (hflip(0) = '0') else
+		    sp_buffer_ram2_do_r(11 downto  8) when (sp_buffer_sel = '1') and (hflip(0) = '1') else
+			 sp_buffer_ram2_do_r( 3 downto  0);-- when (sp_buffer_sel = '1') and (hflip(0) = '0');
+
+sp_col <= sp_buffer_ram1_do_r(15 downto 12) when (sp_buffer_sel = '0') and (hflip(0) = '1') else
+		    sp_buffer_ram1_do_r( 7 downto  4) when (sp_buffer_sel = '0') and (hflip(0) = '0') else
+		    sp_buffer_ram2_do_r(15 downto 12) when (sp_buffer_sel = '1') and (hflip(0) = '1') else
+			 sp_buffer_ram2_do_r( 7 downto  4);-- when (sp_buffer_sel = '1') and (hflip(0) = '0');
+
+--------------------
+--- char machine ---
+--- 91490 Board ----
+--------------------
+bg_ram_addr <= cpu_addr(10 downto 0) when hcnt(0) = '0' else vflip(8 downto 4) & hflip(8 downto 4) & hcnt(1);
+
+bg_code_line <= bg_attr(1 downto 0) & bg_code_r & (vflip(3 downto 1) xor (bg_attr(3) & bg_attr(3) & bg_attr(3) ) ) & (hflip(3) xor bg_attr(2));
+
+process (clock_vid)
+begin
+	if rising_edge(clock_vid) then
+	
+		-- catch ram data for cpu
+		if hcnt(0) = '0' then
+			bg_ram_do_r       <= bg_ram_do;
+			sp_ram_cache_do_r <= sp_ram_cache_do;
+		end if;
+
+		if pix_ena = '1' then
+		
+			if hcnt(0) = '1' then
+				case hcnt(3 downto 1) is
+					when "110" =>  bg_code   <= bg_ram_do;
+					when "111" =>  bg_attr   <= bg_ram_do;		
+										bg_code_r <= bg_code;	
+					when others => null;
+				end case;			
+				
+				case hflip(2 downto 1) xor (bg_attr(2) & bg_attr(2)) is
+					when "00"   => bg_palette_addr <= bg_attr(5 downto 4) & bg_graphx2_do(7 downto 6) & bg_graphx1_do(7 downto 6);
+					when "01"   => bg_palette_addr <= bg_attr(5 downto 4) & bg_graphx2_do(5 downto 4) & bg_graphx1_do(5 downto 4);
+					when "10"   => bg_palette_addr <= bg_attr(5 downto 4) & bg_graphx2_do(3 downto 2) & bg_graphx1_do(3 downto 2);
+					when others => bg_palette_addr <= bg_attr(5 downto 4) & bg_graphx2_do(1 downto 0) & bg_graphx1_do(1 downto 0);
+				end case;
+			end if;
+			
+			sp_palette_addr <= sp_col(1 downto 0) & sp_vid;
+		
+		end if;
+
+	end if;
+end process;
+	
+---------------------------
+-- mux char/sprite video --
+---------------------------
+palette_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and (cpu_addr and x"F800") = x"F800" else '0'; -- 0xF800-F87F + mirroring 0x0780
+
+palette_addr <= cpu_addr(6 downto 1) when palette_we = '1'                    else 
+					 bg_palette_addr      when sp_palette_addr(2 downto 0) = "000" else
+					 sp_palette_addr;
+
+process (clock_vid)
+begin
+	if rising_edge(clock_vid) then
+		video_g <= palette_do(2 downto 0);
+		video_b <= palette_do(5 downto 3);
+		video_r <= palette_do(8 downto 6);
+	end if;
+end process;		
+		
+------------------------------
+-- components & sound board --
+------------------------------
+
+-- microprocessor Z80
+cpu : entity work.T80se
+generic map(Mode => 0, T2Write => 1, IOWait => 1)
+port map(
+  RESET_n => reset_n,
+  CLK_n   => clock_vid,
+  CLKEN   => cpu_ena,
+  WAIT_n  => '1',
+  INT_n   => cpu_irq_n,
+  NMI_n   => '1', --cpu_nmi_n,
+  BUSRQ_n => '1',
+  M1_n    => cpu_m1_n,
+  MREQ_n  => cpu_mreq_n,
+  IORQ_n  => cpu_ioreq_n,
+  RD_n    => cpu_rd_n,
+  WR_n    => cpu_wr_n,
+  RFSH_n  => open,
+  HALT_n  => open,
+  BUSAK_n => open,
+  A       => cpu_addr,
+  DI      => cpu_di,
+  DO      => cpu_do
+);
+
+-- CTC interrupt controler Z80-CTC (MK3882)
+ctc_controler : entity work.ctc_controler
+port map(
+ clock     => clock_vid,
+ clock_ena => cpu_ena,
+ reset     => reset,
+ 
+ d_in      => cpu_do,
+ load_data => ctc_controler_we,
+ int_ack   => ctc_int_ack,
+
+ int_pulse_0 => ctc_counter_0_int,
+ int_pulse_1 => ctc_counter_1_int,
+ int_pulse_2 => ctc_counter_2_int,
+ int_pulse_3 => ctc_counter_3_int,
+ 
+ d_out     => ctc_controler_do,
+ int_n     => cpu_irq_n
+);
+
+ctc_counter_0 : entity work.ctc_counter
+port map(
+ clock     => clock_vid,
+ clock_ena => cpu_ena,
+ reset     => reset,
+ 
+ d_in      => cpu_do,
+ load_data => ctc_counter_0_we,
+ 
+ clk_trg   => '0',
+ 
+ d_out     => ctc_counter_0_do,
+ zc_to     => open, -- zc/to #0 (pin 7) connected to clk_trg #1 (pin 22) on schematics (seems to be not used)
+ int_pulse => ctc_counter_0_int
+ 
+);
+
+ctc_counter_1 : entity work.ctc_counter
+port map(
+ clock     => clock_vid,
+ clock_ena => cpu_ena,
+ reset     => reset,
+ 
+ d_in      => cpu_do,
+ load_data => ctc_counter_1_we,
+ 
+ clk_trg   => '0',
+ 
+ d_out     => ctc_counter_1_do,
+ zc_to     => open,
+ int_pulse => ctc_counter_1_int
+ 
+);
+
+ctc_counter_2 : entity work.ctc_counter
+port map(
+ clock     => clock_vid,
+ clock_ena => cpu_ena,
+ reset     => reset,
+ 
+ d_in      => cpu_do,
+ load_data => ctc_counter_2_we,
+ 
+ clk_trg   => '0',
+ 
+ d_out     => ctc_counter_2_do,
+ zc_to     => open,
+ int_pulse => ctc_counter_2_int
+ 
+);
+
+ctc_counter_3 : entity work.ctc_counter
+port map(
+ clock     => clock_vid,
+ clock_ena => cpu_ena,
+ reset     => reset,
+ 
+ d_in      => cpu_do,
+ load_data => ctc_counter_3_we,
+ 
+ clk_trg   => ctc_counter_3_trg,
+ 
+ d_out     => ctc_counter_3_do,
+ zc_to     => open,
+ int_pulse => ctc_counter_3_int
+ 
+);
+
+-- cpu program ROM 0x0000-0xDFFF
+--rom_cpu : entity work.timber_cpu
+--port map(
+-- clk  => clock_vidn,
+-- addr => cpu_addr(15 downto 0),
+-- data => cpu_rom_do
+--);
+cpu_rom_addr <= cpu_addr(15 downto 0);
+
+-- working RAM   0xE000-0xE7FF
+wram : entity work.cmos_ram
+generic map( dWidth => 8, aWidth => 11)
+port map(
+ clk  => clock_vidn,
+ we   => wram_we,
+ addr => cpu_addr(10 downto 0),
+ d    => cpu_do,
+ q    => wram_do
+);
+
+-- video RAM   0xF000-0xF7FF
+video_ram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 11)
+port map(
+ clk  => clock_vidn,
+ we   => bg_ram_we,
+ addr => bg_ram_addr,
+ d    => cpu_do,
+ q    => bg_ram_do
+);
+
+-- sprite RAM (no cpu access)
+sprite_ram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 9)
+port map(
+ clk  => clock_vidn,
+ we   => sp_ram_we,
+ addr => sp_ram_addr,
+ d    => sp_ram_cache_do,
+ q    => sp_ram_do
+);
+
+-- sprite RAM  0xE800-0xE9FF + mirroring adresses
+sprites_ram_cache : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 9)
+port map(
+ clk  => clock_vidn,
+ we   => sp_ram_cache_we,
+ addr => sp_ram_cache_addr,
+ d    => cpu_do,
+ q    => sp_ram_cache_do
+);
+
+-- sprite line buffer 1a
+sprlinebuf1a : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 8)
+port map(
+ clk  => clock_vidn,
+ we   => sp_buffer_ram1a_we,
+ addr => sp_buffer_ram1_addr,
+ d    => sp_buffer_ram1a_di,
+ q    => sp_buffer_ram1a_do
+);
+
+-- sprite line buffer 1b
+sprlinebuf1b : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 8)
+port map(
+ clk  => clock_vidn,
+ we   => sp_buffer_ram1b_we,
+ addr => sp_buffer_ram1_addr,
+ d    => sp_buffer_ram1b_di,
+ q    => sp_buffer_ram1b_do
+);
+
+-- sprite line buffer 2a
+sprlinebuf2a : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 8)
+port map(
+ clk  => clock_vidn,
+ we   => sp_buffer_ram2a_we,
+ addr => sp_buffer_ram2_addr,
+ d    => sp_buffer_ram2a_di,
+ q    => sp_buffer_ram2a_do
+);
+
+-- sprite line buffer 2b
+sprlinebuf2b : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 8)
+port map(
+ clk  => clock_vidn,
+ we   => sp_buffer_ram2b_we,
+ addr => sp_buffer_ram2_addr,
+ d    => sp_buffer_ram2b_di,
+ q    => sp_buffer_ram2b_do
+);
+
+-- background graphics ROM 6F
+bg_graphics_1 : entity work.timber_bg_bits_1
+port map(
+ clk  => clock_vidn,
+ addr => bg_code_line,
+ data => bg_graphx1_do
+);
+
+-- background graphics ROM 5F
+bg_graphics_2 : entity work.timber_bg_bits_2
+port map(
+ clk  => clock_vidn,
+ addr => bg_code_line,
+ data => bg_graphx2_do
+);
+
+-- timber_sound_board 
+sound_board : entity work.timber_sound_board
+port map(
+ clock_40    => clock_40,
+ reset       => reset,
+ 
+ main_cpu_addr => cpu_addr(7 downto 0),
+ 
+ ssio_iowe => ssio_iowe,
+ ssio_di   => cpu_do,
+ ssio_do   => ssio_do,
+ 
+ input_0 => input_0,
+ input_1 => input_1,
+ input_2 => input_2,
+ input_3 => input_3,
+ input_4 => input_4,
+ 
+ separate_audio => separate_audio,
+ audio_out_l    => audio_out_l,
+ audio_out_r    => audio_out_r,
+
+ cpu_rom_addr => snd_rom_addr,
+ cpu_rom_do => snd_rom_do,
+
+ dbg_cpu_addr => open --dbg_cpu_addr
+);
+ 
+-- background & sprite palette
+palette : entity work.gen_ram
+generic map( dWidth => 9, aWidth => 6)
+port map(
+ clk  => clock_vidn,
+ we   => palette_we,
+ addr => palette_addr,
+ d    => cpu_addr(0) & cpu_do,
+ q    => palette_do
+);
+
+end struct;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/timber_de10_lite.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/timber_de10_lite.vhd
new file mode 100644
index 00000000..5fdbb869
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/timber_de10_lite.vhd	
@@ -0,0 +1,397 @@
+---------------------------------------------------------------------------------
+-- DE10_lite Top level for Timber (Midway MCR) by Dar (darfpga@aol.fr) (22/11/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+--
+-- release rev 00 : initial release
+--  (22/11/2019)
+
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+-- Use timber_de10_lite.sdc to compile (Timequest constraints)
+-- /!\
+-- Don't forget to set device configuration mode with memory initialization 
+--  (Assignments/Device/Pin options/Configuration mode)
+---------------------------------------------------------------------------------
+--
+-- Main features :
+--  PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection) 
+--  Audio pwm output   @gpio pins 1/3 (beware voltage translation/protection) 
+--
+--  Video         : VGA 31kHz/60Hz progressive and TV 15kHz interlaced
+--  Cocktail mode : NO
+--  Sound         : OK
+-- 
+-- For hardware schematic see my other project : NES
+--
+-- Uses 1 pll 40MHz from 50MHz to make 20MHz and 8Mhz 
+--
+-- Board key :
+--   0 : reset game
+--
+-- Keyboard players inputs :
+--
+--   F1 : Add coin
+--   F2 : Start 1 player
+--   F3 : Start 2 players
+--   F4 : Demo sound
+--   F5 : Separate audio
+--   F7 : Service mode
+--   F8 : 15kHz interlaced / 31 kHz progressive
+
+--   SPACE       : bouton 1
+--   v key       : bouton 2
+--   RIGHT arrow : move right
+--   LEFT  arrow : move left
+--   UP    arrow : move up
+--   DOWN  arrow : move down
+--
+-- Other details : see timber.vhd
+-- For USB inputs and SGT5000 audio output see my other project: xevious_de10_lite
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+--use work.usb_report_pkg.all;
+
+entity timber_de10_lite is
+port(
+ max10_clk1_50  : in std_logic;
+-- max10_clk2_50  : in std_logic;
+-- adc_clk_10     : in std_logic;
+ ledr           : out std_logic_vector(9 downto 0);
+ key            : in std_logic_vector(1 downto 0);
+ sw             : in std_logic_vector(9 downto 0);
+
+-- dram_ba    : out std_logic_vector(1 downto 0);
+-- dram_ldqm  : out std_logic;
+-- dram_udqm  : out std_logic;
+-- dram_ras_n : out std_logic;
+-- dram_cas_n : out std_logic;
+-- dram_cke   : out std_logic;
+-- dram_clk   : out std_logic;
+-- dram_we_n  : out std_logic;
+-- dram_cs_n  : out std_logic;
+-- dram_dq    : inout std_logic_vector(15 downto 0);
+-- dram_addr  : out std_logic_vector(12 downto 0);
+
+ hex0 : out std_logic_vector(7 downto 0);
+ hex1 : out std_logic_vector(7 downto 0);
+ hex2 : out std_logic_vector(7 downto 0);
+ hex3 : out std_logic_vector(7 downto 0);
+-- hex4 : out std_logic_vector(7 downto 0);
+-- hex5 : out std_logic_vector(7 downto 0);
+
+ vga_r     : out std_logic_vector(3 downto 0);
+ vga_g     : out std_logic_vector(3 downto 0);
+ vga_b     : out std_logic_vector(3 downto 0);
+ vga_hs    : inout std_logic;
+ vga_vs    : inout std_logic;
+ 
+-- gsensor_cs_n : out   std_logic;
+-- gsensor_int  : in    std_logic_vector(2 downto 0); 
+-- gsensor_sdi  : inout std_logic;
+-- gsensor_sdo  : inout std_logic;
+-- gsensor_sclk : out   std_logic;
+
+-- arduino_io      : inout std_logic_vector(15 downto 0); 
+-- arduino_reset_n : inout std_logic;
+ 
+ gpio          : inout std_logic_vector(35 downto 0)
+);
+end timber_de10_lite;
+
+architecture struct of timber_de10_lite is
+
+ signal clock_40  : std_logic;
+ signal clock_kbd : std_logic;
+ signal reset     : std_logic;
+ 
+ signal clock_div : std_logic_vector(3 downto 0);
+ 
+-- signal max3421e_clk : std_logic;
+ 
+ signal r         : std_logic_vector(2 downto 0);
+ signal g         : std_logic_vector(2 downto 0);
+ signal b         : std_logic_vector(2 downto 0);
+ signal hsync     : std_logic;
+ signal vsync     : std_logic;
+ signal csync     : std_logic;
+ signal blankn    : std_logic;
+ signal tv15Khz_mode : std_logic;
+ 
+ signal audio_l           : std_logic_vector(15 downto 0);
+ signal audio_r           : std_logic_vector(15 downto 0);
+ signal pwm_accumulator_l : std_logic_vector(17 downto 0);
+ signal pwm_accumulator_r : std_logic_vector(17 downto 0);
+
+ alias reset_n         : std_logic is key(0);
+ alias ps2_clk         : std_logic is gpio(35); --gpio(0);
+ alias ps2_dat         : std_logic is gpio(34); --gpio(1);
+ alias pwm_audio_out_l : std_logic is gpio(1);  --gpio(2);
+ alias pwm_audio_out_r : std_logic is gpio(3);  --gpio(3);
+ 
+ signal kbd_intr       : std_logic;
+ signal kbd_scancode   : std_logic_vector(7 downto 0);
+ signal joy_BBBBFRLDU  : std_logic_vector(8 downto 0);
+ signal fn_pulse       : std_logic_vector(7 downto 0);
+ signal fn_toggle      : std_logic_vector(7 downto 0);
+
+ signal vsync_r        : std_logic;
+ signal spin_count     : std_logic_vector(9 downto 0);
+
+-- signal start : std_logic := '0';
+-- signal usb_report : usb_report_t;
+-- signal new_usb_report : std_logic := '0';
+  
+signal dbg_cpu_addr : std_logic_vector(15 downto 0);
+
+begin
+
+reset <= not reset_n;
+
+tv15Khz_mode <= not fn_toggle(7); -- F8
+
+--arduino_io not used pins
+--arduino_io(7) <= '1'; -- to usb host shield max3421e RESET
+--arduino_io(8) <= 'Z'; -- from usb host shield max3421e GPX
+--arduino_io(9) <= 'Z'; -- from usb host shield max3421e INT
+--arduino_io(13) <= 'Z'; -- not used
+--arduino_io(14) <= 'Z'; -- not used
+
+-- Clock 40MHz for kick core and sound_board
+clocks : entity work.max10_pll_40M
+port map(
+ inclk0 => max10_clk1_50,
+ c0 => clock_40,
+ locked => open --pll_locked
+);
+
+-- Timber
+timber : entity work.timber
+port map(
+ clock_40   => clock_40,
+ reset      => reset,
+ 
+ tv15Khz_mode => tv15Khz_mode,
+ video_r      => r,
+ video_g      => g,
+ video_b      => b,
+ video_csync  => csync,
+ video_blankn => blankn,
+ video_hs     => hsync,
+ video_vs     => vsync,
+ 
+ separate_audio => fn_toggle(4), -- F5
+ audio_out_l    => audio_l,
+ audio_out_r    => audio_r,
+   
+ coin1          => fn_pulse(0), -- F1
+ coin2          => '0',
+ start1         => fn_pulse(1), -- F2
+ start2         => fn_pulse(2), -- F3
+ 
+ p1_left        => joy_BBBBFRLDU(2), -- left
+ p1_right       => joy_BBBBFRLDU(3), -- right
+ p1_up          => joy_BBBBFRLDU(0), -- up
+ p1_down        => joy_BBBBFRLDU(1), -- down
+ p1_fire1       => joy_BBBBFRLDU(4), -- space
+ p1_fire2       => joy_BBBBFRLDU(8), -- 'v'
+ 
+ p2_left        => joy_BBBBFRLDU(2), -- left
+ p2_right       => joy_BBBBFRLDU(3), -- right
+ p2_up          => joy_BBBBFRLDU(0), -- up
+ p2_down        => joy_BBBBFRLDU(1), -- down
+ p2_fire1       => joy_BBBBFRLDU(4), -- space
+ p2_fire2       => joy_BBBBFRLDU(8), -- 'v'
+   
+ coin_meters    => '1',
+ upright        => '1',
+ demo_sound     => fn_toggle(3), -- F4
+ service        => fn_toggle(6), -- F7 -- (allow machine settings access)
+  
+ dbg_cpu_addr => dbg_cpu_addr
+);
+
+-- adapt video to 4bits/color only and blank
+vga_r <= r & '0' when blankn = '1' else "0000";
+vga_g <= g & '0' when blankn = '1' else "0000";
+vga_b <= b & '0' when blankn = '1' else "0000";
+
+-- synchro composite/ synchro horizontale
+-- vga_hs <= csync;
+-- vga_hs <= hsync;
+vga_hs <= csync when tv15Khz_mode = '1' else hsync;
+-- commutation rapide / synchro verticale
+-- vga_vs <= '1';
+-- vga_vs <= vsync;
+vga_vs <= '1'   when tv15Khz_mode = '1' else vsync;
+
+--sound_string <= "00" & audio & "000" & "00" & audio & "000";
+
+-- get scancode from keyboard
+process (reset, clock_40)
+begin
+	if reset='1' then
+		clock_div <= (others => '0');
+		clock_kbd  <= '0';
+	else 
+		if rising_edge(clock_40) then
+			if clock_div = "1001" then
+				clock_div <= (others => '0');
+				clock_kbd  <= not clock_kbd;
+			else
+				clock_div <= clock_div + '1';			
+			end if;
+		end if;
+	end if;
+end process;
+
+keyboard : entity work.io_ps2_keyboard
+port map (
+  clk       => clock_kbd, -- synchrounous clock with core
+  kbd_clk   => ps2_clk,
+  kbd_dat   => ps2_dat,
+  interrupt => kbd_intr,
+  scancode  => kbd_scancode
+);
+
+-- translate scancode to joystick
+joystick : entity work.kbd_joystick
+port map (
+  clk           => clock_kbd, -- synchrounous clock with core
+  kbdint        => kbd_intr,
+  kbdscancode   => std_logic_vector(kbd_scancode), 
+  joy_BBBBFRLDU => joy_BBBBFRLDU,
+  fn_pulse      => fn_pulse,
+  fn_toggle     => fn_toggle
+);
+
+
+-- usb host for max3421e arduino shield (modified)
+--max3421e_clk <= clock_11;
+--usb_host : entity work.usb_host_max3421e
+--port map(
+-- clk     => max3421e_clk,
+-- reset   => reset,
+-- start   => start,
+-- 
+-- usb_report => usb_report,
+-- new_usb_report => new_usb_report,
+-- 
+-- spi_cs_n  => arduino_io(10), 
+-- spi_clk   => arduino_io(13),
+-- spi_mosi  => arduino_io(11),
+-- spi_miso  => arduino_io(12)
+--);
+
+-- usb keyboard report decoder
+
+--keyboard_decoder : entity work.usb_keyboard_decoder
+--port map(
+-- clk     => max3421e_clk,
+-- 
+-- usb_report => usb_report,
+-- new_usb_report => new_usb_report,
+-- 
+-- joyBCPPFRLDU  => joyBCPPFRLDU
+--);
+
+-- usb joystick decoder (konix drakkar wireless)
+
+--joystick_decoder : entity work.usb_joystick_decoder
+--port map(
+-- clk     => max3421e_clk,
+-- 
+-- usb_report => usb_report,
+-- new_usb_report => new_usb_report,
+-- 
+-- joyBCPPFRLDU  => open --joyBCPPFRLDU
+--);
+
+-- debug display
+
+--ledr(8 downto 0) <= joyBCPPFRLDU;
+--
+--h0 : entity work.decodeur_7_seg port map(kbd_scancode(3 downto 0), hex0);
+--h1 : entity work.decodeur_7_seg port map(kbd_scancode(7 downto 4), hex1);
+h0 : entity work.decodeur_7_seg port map(dbg_cpu_addr( 3 downto  0),hex0);
+h1 : entity work.decodeur_7_seg port map(dbg_cpu_addr( 7 downto  4),hex1);
+h2 : entity work.decodeur_7_seg port map(dbg_cpu_addr(11 downto  8),hex2);
+h3 : entity work.decodeur_7_seg port map(dbg_cpu_addr(15 downto 12),hex3);
+--h4 : entity work.decodeur_7_seg port map(usb_report(to_integer(unsigned(sw))+0)(3 downto 0),hex4);
+--h5 : entity work.decodeur_7_seg port map(usb_report(to_integer(unsigned(sw))+0)(7 downto 4),hex5);
+
+-- audio for sgtl5000 
+
+--sample_data <= "00" & audio & "000" & "00" & audio & "000";				
+
+-- Clock 1us for ym_8910
+
+--p_clk_1us_p : process(max10_clk1_50)
+--begin
+--	if rising_edge(max10_clk1_50) then
+--		if cnt_1us = 0 then
+--			cnt_1us  <= 49;
+--			clk_1us  <= '1'; 
+--		else
+--			cnt_1us  <= cnt_1us - 1;
+--			clk_1us <= '0'; 
+--		end if;
+--	end if;	
+--end process;	 
+
+-- sgtl5000 (teensy audio shield on top of usb host shield)
+
+--e_sgtl5000 : entity work.sgtl5000_dac
+--port map(
+-- clock_18   => clock_18,
+-- reset      => reset,
+-- i2c_clock  => clk_1us,  
+--
+-- sample_data  => sample_data,
+-- 
+-- i2c_sda   => arduino_io(0), -- i2c_sda, 
+-- i2c_scl   => arduino_io(1), -- i2c_scl, 
+--
+-- tx_data   => arduino_io(2), -- sgtl5000 tx
+-- mclk      => arduino_io(4), -- sgtl5000 mclk 
+-- 
+-- lrclk     => arduino_io(3), -- sgtl5000 lrclk
+-- bclk      => arduino_io(6), -- sgtl5000 bclk   
+-- 
+-- -- debug
+-- hex0_di   => open, -- hex0_di,
+-- hex1_di   => open, -- hex1_di,
+-- hex2_di   => open, -- hex2_di,
+-- hex3_di   => open, -- hex3_di,
+-- 
+-- sw => sw(7 downto 0)
+--);
+
+-- pwm sound output
+process(clock_40)  -- use same clock as kick_sound_board
+begin
+  if rising_edge(clock_40) then
+  
+		if clock_div = "0000" then 
+			pwm_accumulator_l  <=  ('0'&pwm_accumulator_l(16 downto 0)) + ('0'&audio_l&'0');
+			pwm_accumulator_r  <=  ('0'&pwm_accumulator_r(16 downto 0)) + ('0'&audio_r&'0');
+		end if;
+		
+  end if;
+end process;
+
+pwm_audio_out_l <= pwm_accumulator_l(17);
+pwm_audio_out_r <= pwm_accumulator_r(17); 
+
+
+end struct;
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/timber_sound_board.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/timber_sound_board.vhd
new file mode 100644
index 00000000..461a9915
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/timber_sound_board.vhd	
@@ -0,0 +1,556 @@
+---------------------------------------------------------------------------------
+-- Timber sound board by Dar (darfpga@aol.fr) (19/10/2019)
+-- http://darfpga.blogspot.fr
+---------------------------------------------------------------------------------
+-- gen_ram.vhd & io_ps2_keyboard
+-------------------------------- 
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+---------------------------------------------------------------------------------
+-- T80/T80se - Version : 304
+-----------------------------
+-- Z80 compatible microprocessor core
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+---------------------------------------------------------------------------------
+-- YM2149 (AY-3-8910)
+-- Copyright (c) MikeJ - Jan 2005
+---------------------------------------------------------------------------------
+-- Educational use only
+-- Do not redistribute synthetized file with roms
+-- Do not redistribute roms whatever the form
+-- Use at your own risk
+---------------------------------------------------------------------------------
+--
+--  SOUND : 1xZ80 @ 2.0MHz CPU accessing its program rom, working ram, 2x-AY3-8910
+--		  8Kx8bits program rom
+--      1Kx8bits working ram
+--
+--      1xAY-3-8910
+--			3 sound channels
+--
+--      1xAY-3-8910
+--			3 sound channels
+--
+--		  6 sound modulation (required 8MHz signal => 40MHz/5)
+--      2 global volume control (not activated - not sure it was used for kick )
+--
+--  I/O : 
+--		4x8bits command registers from main cpu board (IRAM)
+--		1x8bits status  registers to   main cpu board (STAT)
+--    5x8bits input   buffers   to   main cpu board (IP0-IP5)
+--    2x8bits output  registers from main cpu board (OP0/OP4)
+--
+---------------------------------------------------------------------------------
+--  Schematics remarks :
+--     Not sure global volume are used => both deactivated
+--     Not sure if global channels are mixed together or not => allow for 
+--        external control mixed/separated
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity timber_sound_board is
+port(
+ clock_40     : in std_logic;
+ reset        : in std_logic;
+ 
+ main_cpu_addr : in std_logic_vector(7 downto 0);
+ 
+ ssio_iowe     : in std_logic;
+ ssio_di       : in std_logic_vector(7 downto 0); 
+ ssio_do       : out std_logic_vector(7 downto 0);
+ 
+ input_0 : in std_logic_vector(7 downto 0);
+ input_1 : in std_logic_vector(7 downto 0);
+ input_2 : in std_logic_vector(7 downto 0);
+ input_3 : in std_logic_vector(7 downto 0);
+ input_4 : in std_logic_vector(7 downto 0);
+ 
+ separate_audio : in std_logic;
+ 
+ audio_out_l : out std_logic_vector(15 downto 0);
+ audio_out_r : out std_logic_vector(15 downto 0);
+
+ cpu_rom_addr : out std_logic_vector(13 downto 0);
+ cpu_rom_do : in std_logic_vector(7 downto 0);
+
+ dbg_cpu_addr : out std_logic_vector(15 downto 0)
+ );
+end timber_sound_board;
+
+architecture struct of timber_sound_board is
+
+ signal reset_n   : std_logic;
+ signal clock_snd : std_logic;
+ signal clock_sndn: std_logic;
+ 
+ signal clock_cnt1 : std_logic_vector(4 downto 0) := "00000";
+
+ signal cpu_ena     : std_logic;
+ signal ena_4Mhz    : std_logic;
+ signal clk_8Mhz    : std_logic;
+
+ signal cpu_addr    : std_logic_vector(15 downto 0);
+ signal cpu_di      : std_logic_vector( 7 downto 0);
+ signal cpu_do      : std_logic_vector( 7 downto 0);
+ signal cpu_wr_n    : std_logic;
+ signal cpu_rd_n    : std_logic;
+ signal cpu_mreq_n  : std_logic;
+ signal cpu_ioreq_n : std_logic;
+ signal cpu_irq_n   : std_logic;
+ signal cpu_m1_n    : std_logic;
+ 
+-- signal cpu_rom_do  : std_logic_vector( 7 downto 0);
+ 
+ signal wram_we     : std_logic;
+ signal wram_do     : std_logic_vector( 7 downto 0);
+
+ signal iram_0_do   : std_logic_vector( 7 downto 0);
+ signal iram_1_do   : std_logic_vector( 7 downto 0);
+ signal iram_2_do   : std_logic_vector( 7 downto 0);
+ signal iram_3_do   : std_logic_vector( 7 downto 0);
+ 
+ signal ssio_status : std_logic_vector( 7 downto 0);
+ 
+ signal div_E11 : std_logic_vector(2 downto 0);  -- binary counter 3msb of E11 - 74161
+ signal div_D11 : std_logic_vector(3 downto 0);  -- decade counter - D11 - 74160
+ signal div_C12 : std_logic_vector(6 downto 0);  -- stage ripple counter - C12 - MC140247 
+ signal clr_int : std_logic;
+
+ signal ay1_audio_chan : std_logic_vector( 1 downto 0);
+ signal ay1_audio_muxed: std_logic_vector( 7 downto 0);
+ signal ay1_bc1        : std_logic;
+ signal ay1_bdir       : std_logic;
+ signal ay1_do         : std_logic_vector( 7 downto 0);
+ signal ay1_cs         : std_logic;
+ signal ay1_port_a     : std_logic_vector( 7 downto 0);
+ signal ay1_port_b     : std_logic_vector( 7 downto 0);
+ 
+ signal ay2_audio_chan : std_logic_vector( 1 downto 0);
+ signal ay2_audio_muxed: std_logic_vector( 7 downto 0);
+ signal ay2_bc1        : std_logic;
+ signal ay2_bdir       : std_logic;
+ signal ay2_do         : std_logic_vector( 7 downto 0);
+ signal ay2_cs         : std_logic;
+ signal ay2_port_a     : std_logic_vector( 7 downto 0);
+ signal ay2_port_b     : std_logic_vector( 7 downto 0);
+ 
+ signal ssio_82s123_addr        : std_logic_vector(4 downto 0);
+ signal ssio_82s123_do          : std_logic_vector(7 downto 0);
+ signal ssio_modulation_clock   : std_logic;
+ signal ssio_modulation_clock_r : std_logic;
+ signal ssio_modulation_load    : std_logic;
+ signal modulation_counter_a1   : std_logic_vector(3 downto 0);
+ signal modulation_counter_b1   : std_logic_vector(3 downto 0);
+ signal modulation_counter_c1   : std_logic_vector(3 downto 0);
+ signal modulation_counter_a2   : std_logic_vector(3 downto 0);
+ signal modulation_counter_b2   : std_logic_vector(3 downto 0);
+ signal modulation_counter_c2   : std_logic_vector(3 downto 0);
+
+ signal ch_a1 : std_logic_vector(7 downto 0);
+ signal ch_b1 : std_logic_vector(7 downto 0);
+ signal ch_c1 : std_logic_vector(7 downto 0);
+ signal ch_a2 : std_logic_vector(7 downto 0);
+ signal ch_b2 : std_logic_vector(7 downto 0);
+ signal ch_c2 : std_logic_vector(7 downto 0);
+ 
+ -- K volume data : 148 138 127 112 95 72 42 0
+ type bytes_array is array(0 to  7) of std_logic_vector(7 downto 0);
+ signal K_volume : bytes_array := (X"94",X"8A",X"7F",X"70",X"5F",X"48",X"2A",X"00");
+
+ signal volume_ch1 : std_logic_vector(7 downto 0);
+ signal volume_ch2 : std_logic_vector(7 downto 0);
+ 
+ signal snd_1    : std_logic_vector(17 downto 0);
+ signal snd_2    : std_logic_vector(17 downto 0);
+ signal snd_mono : std_logic_vector(18 downto 0);
+ 
+begin
+
+clock_snd  <= clock_40;
+clock_sndn <= not clock_40;
+reset_n    <= not reset;
+
+-- debug 
+process (reset, clock_snd)
+begin
+ if rising_edge(clock_snd) and cpu_ena ='1' and cpu_mreq_n ='0' then
+  dbg_cpu_addr <= cpu_addr;
+ end if;
+end process;
+
+-- make enables clock from clock_snd
+process (clock_snd, reset)
+begin
+	if reset='1' then
+		clock_cnt1 <= (others=>'0');
+		clk_8Mhz	<= '0';
+	else 
+		if rising_edge(clock_snd) then
+			if clock_cnt1 = "10011" then  -- divide by 20
+				clock_cnt1 <= (others=>'0');
+			else
+				clock_cnt1 <= clock_cnt1 + 1;
+			end if;
+
+			if clock_cnt1 = "10011" or 
+				clock_cnt1 = "00100" or
+				clock_cnt1 = "01001" or
+				clock_cnt1 = "01110" then 
+			
+				clk_8Mhz	<= not clk_8Mhz;  -- (50% duty cycle)
+			end if;
+	
+		end if;
+	end if;   		
+end process;
+--
+cpu_ena  <= '1' when clock_cnt1 = "00000" else '0'; -- (2.0MHz)
+
+ena_4Mhz <= '1' when clock_cnt1 = "00000" or
+							clock_cnt1 = "01010" else '0'; -- (4.0MHz)
+
+------------------------------------------
+-- cpu data input with address decoding --
+------------------------------------------
+cpu_di <= cpu_rom_do  when cpu_mreq_n = '0' and cpu_addr(15 downto 14) = "00" else -- 0x0000-0x3FFF
+			 wram_do     when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"8" else -- 0x8000-0x83FF
+			 iram_0_do   when cpu_mreq_n = '0' and cpu_addr(15 downto  0)=  X"9000" else
+			 iram_1_do   when cpu_mreq_n = '0' and cpu_addr(15 downto  0)=  X"9001" else
+			 iram_2_do   when cpu_mreq_n = '0' and cpu_addr(15 downto  0)=  X"9002" else
+			 iram_3_do   when cpu_mreq_n = '0' and cpu_addr(15 downto  0)=  X"9003" else
+			 ay1_do      when cpu_mreq_n = '0' and cpu_addr(15 downto 12)=  X"A" else
+			 ay2_do      when cpu_mreq_n = '0' and cpu_addr(15 downto 12)=  X"B" else
+			 x"FF"       when cpu_mreq_n = '0' and cpu_addr(15 downto 12)=  X"F" else -- 0xF000  (sw3 dip - D14)
+   		 X"FF";
+
+------------------------------------------
+-- write enable to working ram from CPU --
+-- clear interrupt, cs for AY3-8910     --
+-- ssio output to main cpu (read input) --
+-- ssio status to main cpu              --
+------------------------------------------
+wram_we   <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"8" else '0'; -- 0x8000-0x83FF
+clr_int   <= '1' when cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_addr(15 downto 12) = X"E" else '0'; -- 0xE000-0xEFFF
+
+ay1_cs <= '1' when cpu_mreq_n = '0' and (cpu_rd_n = '0' or cpu_wr_n = '0') and cpu_addr(15 downto 12) = X"A" else '0'; -- 0xA000-0xAFFF
+ay2_cs <= '1' when cpu_mreq_n = '0' and (cpu_rd_n = '0' or cpu_wr_n = '0') and cpu_addr(15 downto 12) = X"B" else '0'; -- 0xB000-0xBFFF
+
+ay1_bdir <= not (not ay1_cs or cpu_addr(0) );
+ay1_bc1  <= not (not ay1_cs or cpu_addr(1) );
+ay2_bdir <= not (not ay2_cs or cpu_addr(0) );
+ay2_bc1  <= not (not ay2_cs or cpu_addr(1) );
+
+ssio_do <= input_0     when main_cpu_addr(2 downto 0) = "000" else -- Input 0 -- players, coins, ...
+           input_1     when main_cpu_addr(2 downto 0) = "001" else -- Input 1 
+           input_2     when main_cpu_addr(2 downto 0) = "010" else -- Input 2
+		   input_3     when main_cpu_addr(2 downto 0) = "011" else -- Input 3 -- sw1 dip 
+		   input_4     when main_cpu_addr(2 downto 0) = "100" else -- Input 4 
+		   ssio_status when main_cpu_addr(2 downto 0) = "111" else -- ssio status
+		   x"FF";
+		
+process (clock_snd)
+begin
+	if rising_edge(clock_snd) then
+		if cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"C" then ssio_status <= cpu_do; end if; -- 0xC000-0xCFFF
+	end if;	
+end process; 
+
+------------------------------------------------------------------------
+-- Misc registers : interrupt, counters E11/D11/C12
+------------------------------------------------------------------------
+process (clock_snd, reset, clr_int, ena_4Mhz)
+begin
+	if reset = '1' then
+		div_E11 <= (others => '0');  -- 3msb of E11
+		div_D11 <= (others => '0');  -- decade counter
+		div_C12 <= (others => '0');  -- MC14024
+	else
+		if rising_edge(clock_snd) then
+		
+			if ena_4Mhz = '1' then 
+		
+				div_E11 <= div_E11 + 1;
+				
+				if div_E11 = "111" then
+					if div_D11 = "1001" then
+						div_D11 <= (others => '0');
+					else
+						div_D11 <= div_D11 + 1;
+					end if;
+					
+					if div_D11 = "0100" then
+						div_C12 <= div_C12 + 1;
+					end if;
+					
+				end if;
+							
+			end if;
+			
+			if clr_int = '1' then
+				div_C12 <= (others => '0');
+			end if;
+			
+		end if;	
+	end if;	
+end process; 
+
+cpu_irq_n <= not div_C12(6);
+
+-------------------------------
+-- sound modulation / volume --
+-------------------------------
+
+ssio_82s123_addr <= div_D11 & div_E11(2);
+
+--74166 8 bits shift register (D13)
+ssio_modulation_clock <= ssio_82s123_do(7-to_integer(unsigned(div_E11(1 downto 0) & clk_8Mhz)));
+ssio_modulation_load <= '1' when div_D11 = "1001" else '0';
+
+-- AY-3-8910 #1 
+-- ch A (pin  4) modulated by counter controled by port A3-0 (pin 18->21)
+-- ch B (pin  3) modulated by counter controled by port A7-4 (pin 14->17)
+-- ch C (pin 38) modulated by counter controled by port B3-0 (pin 10->13)
+-- mute left and right port B7 (pin 6)
+-- volume#1  contoled by port B6-4 (pin 7->9)
+
+-- AY-3-8910 #2
+-- ch A (pin  4) modulated by counter controled by port A3-0 (pin 18->21)
+-- ch B (pin  3) modulated by counter controled by port A7-4 (pin 14->17)
+-- ch C (pin 38) modulated by counter controled by port B3-0 (pin 10->13)
+-- mute global port B7 (pin 6)
+-- volume#2 contoled by port B6-4 (pin 7->9)
+
+-- 4051 cmos mux (D5 and E3)
+--   CBA 
+--   000 => switch X0 (pin 13) ON others OFF
+--   001 => switch X1 (pin 14) ON others OFF
+--   ...
+--   111 => switch X7 (pin  4) ON others OFF
+
+-- Assuming R179 to R187 equivalent to
+--
+--             --------
+--     --------|  R2  |--------        -- with R1 = 24k + n*4.7k
+--     ^   |   --------   |   ^        --      R2 = 24k
+--     |  ---            ---  |        --      R3 = (7-n)*4.7
+--     |  | |            | |  |        --
+-- Vin |  | | R1      R3 | |  | Vout   --   n being 4051 CBA value
+--     |  | |            | |  |        --
+--     |  ---            ---  |        -- which gives  
+--     |   |              |   |        -- Vout = Vin * (7-n)*4.7/(24+(7-n)*4.7)
+--     ------------------------       
+--
+--  let : Vout = Vin * K(n) = Vin * (7-n)*4.7/(24+(7-n)*4.7) * 256
+--   
+--  with K(n) = [148 138 127 112 95 72 42 0]
+--
+
+process (clock_snd, ssio_modulation_clock, ssio_modulation_load)
+begin
+	if rising_edge(clock_snd) then
+		ssio_modulation_clock_r <= ssio_modulation_clock;
+	
+		if ssio_modulation_load = '1' then 
+			modulation_counter_a1 <= ay1_port_a(3 downto 0);
+			modulation_counter_b1 <= ay1_port_a(7 downto 4);
+			modulation_counter_c1 <= ay1_port_b(3 downto 0);
+			modulation_counter_a2 <= ay2_port_a(3 downto 0);
+			modulation_counter_b2 <= ay2_port_a(7 downto 4);
+			modulation_counter_c2 <= ay2_port_b(3 downto 0);
+		else
+			if ssio_modulation_clock = '1' and ssio_modulation_clock_r = '0' then 
+				if modulation_counter_a1 > X"0" then modulation_counter_a1 <= modulation_counter_a1 - 1; end if;
+				if modulation_counter_b1 > X"0" then modulation_counter_b1 <= modulation_counter_b1 - 1; end if;
+				if modulation_counter_c1 > X"0" then modulation_counter_c1 <= modulation_counter_c1 - 1; end if;
+				if modulation_counter_a2 > X"0" then modulation_counter_a2 <= modulation_counter_a2 - 1; end if;
+				if modulation_counter_b2 > X"0" then modulation_counter_b2 <= modulation_counter_b2 - 1; end if;
+				if modulation_counter_c2 > X"0" then modulation_counter_c2 <= modulation_counter_c2 - 1; end if;
+			end if;
+		end if;
+		
+		case ay1_audio_chan is
+		when "00" => if modulation_counter_a1 = x"0" then ch_a1 <= ay1_audio_muxed; else ch_a1 <= (others => '0'); end if;
+		when "01" => if modulation_counter_b1 = x"0" then ch_b1 <= ay1_audio_muxed; else ch_b1 <= (others => '0'); end if;
+		when "10" => if modulation_counter_c1 = x"0" then ch_c1 <= ay1_audio_muxed; else ch_c1 <= (others => '0'); end if;
+		when others => null;
+		end case;
+		
+		case ay2_audio_chan is
+		when "00" => if modulation_counter_a2 = x"0" then ch_a2 <= ay2_audio_muxed; else ch_a2 <= (others => '0'); end if;
+		when "01" => if modulation_counter_b2 = x"0" then ch_b2 <= ay2_audio_muxed; else ch_b2 <= (others => '0'); end if;
+		when "10" => if modulation_counter_c2 = x"0" then ch_c2 <= ay2_audio_muxed; else ch_c2 <= (others => '0'); end if;
+		when others => null;
+		end case;
+		
+--		volume_ch1 <= K_volume(to_integer(unsigned(ay1_port_b(6 downto 4))));
+--		volume_ch2 <= K_volume(to_integer(unsigned(ay2_port_b(6 downto 4))));
+--		volume_ch2 <= K_volume(to_integer(unsigned(ay1_port_b(6 downto 4)))); -- use ch1 control otherwise ch2 is always OFF!
+
+		volume_ch1 <= X"FF"; -- finaly don't use volume controls
+		volume_ch2 <= X"FF";
+
+		if ay1_audio_chan = "00" then
+			snd_1 <= (("00"&ch_a1) + ("00"&ch_b1)  + ("00"&ch_c1)) * volume_ch1;
+		end if;
+
+		if ay2_audio_chan = "00" then
+			snd_2 <= (("00"&ch_a2) + ("00"&ch_b2)  + ("00"&ch_c2)) * volume_ch2; 
+		end if;
+		
+	end if;	
+end process;
+
+snd_mono <= ('0'&snd_1) + ('0'&snd_2);
+
+audio_out_l <= snd_1(17 downto 2) when separate_audio = '1' else snd_mono(18 downto 3);
+audio_out_r <= snd_2(17 downto 2) when separate_audio = '1' else snd_mono(18 downto 3);
+
+------------------------------
+-- components & sound board --
+------------------------------
+
+-- microprocessor Z80
+cpu : entity work.T80se
+generic map(Mode => 0, T2Write => 1, IOWait => 1)
+port map(
+  RESET_n => reset_n,
+  CLK_n   => clock_snd,
+  CLKEN   => cpu_ena,
+  WAIT_n  => '1',
+  INT_n   => cpu_irq_n,
+  NMI_n   => '1', --cpu_nmi_n,
+  BUSRQ_n => '1',
+  M1_n    => cpu_m1_n,
+  MREQ_n  => cpu_mreq_n,
+  IORQ_n  => cpu_ioreq_n,
+  RD_n    => cpu_rd_n,
+  WR_n    => cpu_wr_n,
+  RFSH_n  => open,
+  HALT_n  => open,
+  BUSAK_n => open,
+  A       => cpu_addr,
+  DI      => cpu_di,
+  DO      => cpu_do
+);
+
+-- cpu program ROM 0x0000-0x3FFF
+--rom_cpu : entity work.timber_sound_cpu
+--port map(
+-- clk  => clock_sndn,
+-- addr => cpu_addr(13 downto 0),
+-- data => cpu_rom_do
+--);
+cpu_rom_addr <= cpu_addr(13 downto 0);
+
+-- working RAM   0x8000-0x83FF
+wram : entity work.gen_ram
+generic map( dWidth => 8, aWidth => 10)
+port map(
+ clk  => clock_sndn,
+ we   => wram_we,
+ addr => cpu_addr(9 downto 0),
+ d    => cpu_do,
+ q    => wram_do
+);
+
+-- iram (command from main cpu to sound cpu)
+process (clock_snd, reset, ssio_iowe)
+begin
+	if reset = '1' then
+		iram_0_do <= (others => '0');
+		iram_1_do <= (others => '0');
+		iram_2_do <= (others => '0');
+		iram_3_do <= (others => '0');
+	else
+		if rising_edge(clock_snd) then
+			if ssio_iowe = '1' and main_cpu_addr(7 downto 2) = "000111" then  -- 0x1C - 0x1F
+				case main_cpu_addr(1 downto 0) is
+				when "00" => iram_0_do <= ssio_di;
+				when "01" => iram_1_do <= ssio_di;
+				when "10" => iram_2_do <= ssio_di;
+				when "11" => iram_3_do <= ssio_di;
+				when others => null;
+				end case;
+			end if;
+		end if;
+	end if;
+end process;
+
+-- AY-3-8910 # 1
+ay_3_8910_1 : entity work.YM2149
+port map(
+  -- data bus
+  I_DA       => cpu_do,    -- in  std_logic_vector(7 downto 0); -- pin 37 to 30
+  O_DA       => ay1_do,    -- out std_logic_vector(7 downto 0); -- pin 37 to 30
+  O_DA_OE_L  => open,      -- out std_logic;
+  -- control
+  I_A9_L     => '0',       -- in  std_logic; -- pin 24
+  I_A8       => '1',       -- in  std_logic; -- pin 25
+  I_BDIR     => ay1_bdir,  -- in  std_logic; -- pin 27
+  I_BC2      => '1',       -- in  std_logic; -- pin 28
+  I_BC1      => ay1_bc1,   -- in  std_logic; -- pin 29
+  I_SEL_L    => '0',       -- in  std_logic;
+
+  O_AUDIO    => ay1_audio_muxed, -- out std_logic_vector(7 downto 0);
+  O_CHAN     => ay1_audio_chan,  -- out std_logic_vector(1 downto 0);
+  
+  -- port a
+  I_IOA      => (others => '0'), -- in  std_logic_vector(7 downto 0); -- pin 21 to 14
+  O_IOA      => ay1_port_a,      -- out std_logic_vector(7 downto 0); -- pin 21 to 14
+  O_IOA_OE_L => open,            -- out std_logic;
+  -- port b
+  I_IOB      => (others => '0'), -- in  std_logic_vector(7 downto 0); -- pin 13 to 6
+  O_IOB      => ay1_port_b,     -- out std_logic_vector(7 downto 0); -- pin 13 to 6
+  O_IOB_OE_L => open,            -- out std_logic;
+
+  ENA        => cpu_ena,   -- in  std_logic; -- clock enable for higher speed operation
+  RESET_L    => reset_n,   -- in  std_logic;
+  CLK        => clock_snd  -- in  std_logic  -- note 6 Mhz
+);
+
+
+-- AY-3-8910 # 2
+ay_3_8910_2 : entity work.YM2149
+port map(
+  -- data bus
+  I_DA       => cpu_do,    -- in  std_logic_vector(7 downto 0); -- pin 37 to 30
+  O_DA       => ay2_do,    -- out std_logic_vector(7 downto 0); -- pin 37 to 30
+  O_DA_OE_L  => open,      -- out std_logic;
+  -- control
+  I_A9_L     => '0',       -- in  std_logic; -- pin 24
+  I_A8       => '1',       -- in  std_logic; -- pin 25
+  I_BDIR     => ay2_bdir,  -- in  std_logic; -- pin 27
+  I_BC2      => '1',       -- in  std_logic; -- pin 28
+  I_BC1      => ay2_bc1,   -- in  std_logic; -- pin 29
+  I_SEL_L    => '0',       -- in  std_logic;
+
+  O_AUDIO    => ay2_audio_muxed, -- out std_logic_vector(7 downto 0);
+  O_CHAN     => ay2_audio_chan,  -- out std_logic_vector(1 downto 0);
+  
+  -- port a
+  I_IOA      => (others => '0'), -- in  std_logic_vector(7 downto 0); -- pin 21 to 14
+  O_IOA      => ay2_port_a,      -- out std_logic_vector(7 downto 0); -- pin 21 to 14
+  O_IOA_OE_L => open,            -- out std_logic;
+  -- port b
+  I_IOB      => (others => '0'), -- in  std_logic_vector(7 downto 0); -- pin 13 to 6
+  O_IOB      => ay2_port_b,      -- out std_logic_vector(7 downto 0); -- pin 13 to 6
+  O_IOB_OE_L => open,            -- out std_logic;
+
+  ENA        => cpu_ena,   -- in  std_logic; -- clock enable for higher speed operation
+  RESET_L    => reset_n,   -- in  std_logic;
+  CLK        => clock_snd  -- in  std_logic  -- note 6 Mhz
+);
+
+-- midway ssio sound modulation prom
+midssio : entity work.midssio_82s123
+port map(
+ clk  => clock_sndn,
+ addr => ssio_82s123_addr,
+ data => ssio_82s123_do
+);
+
+end struct;
\ No newline at end of file
diff --git a/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/ym_2149_linmix.vhd b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/ym_2149_linmix.vhd
new file mode 100644
index 00000000..b0573a80
--- /dev/null
+++ b/Arcade_MiST/Midway MCR 3/Timber_MiST/rtl/ym_2149_linmix.vhd	
@@ -0,0 +1,645 @@
+--
+-- A simulation model of YM2149 (AY-3-8910 with bells on)
+
+-- Copyright (c) MikeJ - Jan 2005
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
+--
+-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
+-- vol 15 .. 0
+-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
+-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
+-- to produced all the required values.
+-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
+--
+-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
+-- accurate for designs where the outputs are buffered and not simply wired together.
+-- The ouput level is more complex in that case and requires a larger table.
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_arith.all;
+  use ieee.std_logic_unsigned.all;
+
+entity YM2149 is
+  port (
+  -- data bus
+  I_DA                : in  std_logic_vector(7 downto 0);
+  O_DA                : out std_logic_vector(7 downto 0);
+  O_DA_OE_L           : out std_logic;
+  -- control
+  I_A9_L              : in  std_logic;
+  I_A8                : in  std_logic;
+  I_BDIR              : in  std_logic;
+  I_BC2               : in  std_logic;
+  I_BC1               : in  std_logic;
+  I_SEL_L             : in  std_logic;
+
+  O_AUDIO             : out std_logic_vector(7 downto 0);
+  -- port a
+  I_IOA               : in  std_logic_vector(7 downto 0);
+  O_IOA               : out std_logic_vector(7 downto 0);
+  O_IOA_OE_L          : out std_logic;
+  -- port b
+  I_IOB               : in  std_logic_vector(7 downto 0);
+  O_IOB               : out std_logic_vector(7 downto 0);
+  O_IOB_OE_L          : out std_logic;
+
+  ENA                 : in  std_logic; -- clock enable for higher speed operation
+  RESET_L             : in  std_logic;
+  CLK                 : in  std_logic  -- note 6 Mhz
+  );
+end;
+
+architecture RTL of YM2149 is
+  type  array_16x8   is array (0 to 15) of std_logic_vector(7 downto 0);
+  type  array_3x12   is array (1 to 3) of std_logic_vector(11 downto 0);
+
+  signal cnt_div              : std_logic_vector(3 downto 0) := (others => '0');
+  signal noise_div            : std_logic := '0';
+  signal ena_div              : std_logic;
+  signal ena_div_noise        : std_logic;
+  signal poly17               : std_logic_vector(16 downto 0) := (others => '0');
+
+  -- registers
+  signal addr                 : std_logic_vector(7 downto 0);
+  signal busctrl_addr         : std_logic;
+  signal busctrl_we           : std_logic;
+  signal busctrl_re           : std_logic;
+
+  signal reg                  : array_16x8 ; --:= (
+-- "00000000", -- R0  Period Tone A 8bits lsb
+-- "00000100", -- R1  Period Tone A 4bits msb
+-- "00000000", -- R2  Period Tone B 8bits lsb
+-- "00000010", -- R3  Period Tone B 4bits msb
+-- "00000000", -- R4  Period Tone C 8bits lsb
+-- "00000001", -- R5  Period Tone C 4bits msb
+-- "00001000", -- R6  Period Noise  5bits 
+-- "00111000", -- R7  Mixer Noise CBA 3bits, Tone CBA  3bits
+-- "00000111", -- R8  Amplitude A Mode 1bit, Level 4bits 
+-- "00000111", -- R9  Amplitude B Mode 1bit, Level 4bits 
+-- "00000111", -- R10 Amplitude C Mode 1bit, Level 4bits 
+-- "00000000", -- R11 Period Enveloppe 8bits lsb
+-- "00000000", -- R12 Period Enveloppe 8bits msb
+-- "00000000", -- R13 Shape Enveloppe 4bits
+-- "00000000", -- R14 Port A
+-- "00000000"  -- R15 Port B
+-- );
+ 
+  signal env_reset            : std_logic;
+  signal ioa_inreg            : std_logic_vector(7 downto 0);
+  signal iob_inreg            : std_logic_vector(7 downto 0);
+
+  signal noise_gen_cnt        : std_logic_vector(4 downto 0);
+  signal noise_gen_op         : std_logic;
+  signal tone_gen_cnt         : array_3x12 := (others => (others => '0'));
+  signal tone_gen_op          : std_logic_vector(3 downto 1) := "000";
+
+  signal env_gen_cnt          : std_logic_vector(15 downto 0);
+  signal env_ena              : std_logic;
+  signal env_hold             : std_logic;
+  signal env_inc              : std_logic;
+  signal env_vol              : std_logic_vector(4 downto 0);
+
+  signal tone_ena_l           : std_logic;
+  signal tone_src             : std_logic;
+  signal noise_ena_l          : std_logic;
+  signal chan_vol             : std_logic_vector(4 downto 0);
+
+  signal dac_amp              : std_logic_vector(7 downto 0);
+  signal audio_mix            : std_logic_vector(9 downto 0);
+  signal audio_final          : std_logic_vector(9 downto 0);
+begin
+  -- cpu i/f
+  p_busdecode            : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
+    variable cs : std_logic;
+    variable sel : std_logic_vector(2 downto 0);
+  begin
+    -- BDIR BC2 BC1 MODE
+    --   0   0   0  inactive
+    --   0   0   1  address
+    --   0   1   0  inactive
+    --   0   1   1  read
+    --   1   0   0  address
+    --   1   0   1  inactive
+    --   1   1   0  write
+    --   1   1   1  read
+    busctrl_addr <= '0';
+    busctrl_we <= '0';
+    busctrl_re <= '0';
+
+    cs := '0';
+    if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
+      cs := '1';
+    end if;
+
+    sel := (I_BDIR & I_BC2 & I_BC1);
+    case sel is
+      when "000" => null;
+      when "001" => busctrl_addr <= '1';
+      when "010" => null;
+      when "011" => busctrl_re   <= cs;
+      when "100" => busctrl_addr <= '1';
+      when "101" => null;
+      when "110" => busctrl_we   <= cs;
+      when "111" => busctrl_addr <= '1';
+      when others => null;
+    end case;
+  end process;
+
+  p_oe                   : process(busctrl_re)
+  begin
+    -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
+    O_DA_OE_L <= not (busctrl_re);
+  end process;
+
+  --
+  -- CLOCKED
+  --
+  p_waddr                : process
+  begin
+    ---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+    wait until rising_edge(CLK);
+
+    if (RESET_L = '0') then
+      addr <= (others => '0');
+    else
+      if (busctrl_addr = '1') then
+        addr <= I_DA;
+      end if;
+    end if;
+  end process;
+
+  p_wdata                : process
+  begin
+    ---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+    wait until rising_edge(CLK);
+    env_reset <= '0';
+
+    if (RESET_L = '0') then
+      reg <= (others => (others => '0'));
+      env_reset <= '1';
+    else
+      env_reset <= '0';
+      if (busctrl_we = '1') then
+        case addr(3 downto 0) is
+          when x"0" => reg(0)  <= I_DA;
+          when x"1" => reg(1)  <= I_DA;
+          when x"2" => reg(2)  <= I_DA;
+          when x"3" => reg(3)  <= I_DA;
+          when x"4" => reg(4)  <= I_DA;
+          when x"5" => reg(5)  <= I_DA;
+          when x"6" => reg(6)  <= I_DA;
+          when x"7" => reg(7)  <= I_DA;
+          when x"8" => reg(8)  <= I_DA;
+          when x"9" => reg(9)  <= I_DA;
+          when x"A" => reg(10) <= I_DA;
+          when x"B" => reg(11) <= I_DA;
+          when x"C" => reg(12) <= I_DA;
+          when x"D" => reg(13) <= I_DA; env_reset <= '1';
+          when x"E" => reg(14) <= I_DA;
+          when x"F" => reg(15) <= I_DA;
+          when others => null;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  --
+  -- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
+  --
+--  p_waddr                : process(reset_l, busctrl_addr)
+--  begin
+--    -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+--    if (RESET_L = '0') then
+--      addr <= (others => '0');
+--    elsif falling_edge(busctrl_addr) then -- yuk
+--      addr <= I_DA;
+--    end if;
+--  end process;
+--
+--  p_wdata                : process(reset_l, busctrl_we, addr)
+--  begin
+--    if (RESET_L = '0') then
+--      reg <= (others => (others => '0'));
+--    elsif falling_edge(busctrl_we) then
+--        case addr(3 downto 0) is
+--          when x"0" => reg(0)  <= I_DA;
+--          when x"1" => reg(1)  <= I_DA;
+--          when x"2" => reg(2)  <= I_DA;
+--          when x"3" => reg(3)  <= I_DA;
+--          when x"4" => reg(4)  <= I_DA;
+--          when x"5" => reg(5)  <= I_DA;
+--          when x"6" => reg(6)  <= I_DA;
+--          when x"7" => reg(7)  <= I_DA;
+--          when x"8" => reg(8)  <= I_DA;
+--          when x"9" => reg(9)  <= I_DA;
+--          when x"A" => reg(10) <= I_DA;
+--          when x"B" => reg(11) <= I_DA;
+--          when x"C" => reg(12) <= I_DA;
+--          when x"D" => reg(13) <= I_DA;
+--          when x"E" => reg(14) <= I_DA;
+--          when x"F" => reg(15) <= I_DA;
+--          when others => null;
+--        end case;
+--    end if;
+--
+--    env_reset <= '0';
+--    if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
+--      env_reset <= '1';
+--    end if;
+--  end process;
+
+ --
+ -- END LATCHED
+ --
+  
+  p_rdata                : process(busctrl_re, addr, reg)
+  begin
+    O_DA <= (others => '0'); -- 'X'
+    if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
+      case addr(3 downto 0) is
+        when x"0" => O_DA <= reg(0) ;
+        when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
+        when x"2" => O_DA <= reg(2) ;
+        when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
+        when x"4" => O_DA <= reg(4) ;
+        when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
+        when x"6" => O_DA <= "000"  & reg(6)(4 downto 0) ;
+        when x"7" => O_DA <= reg(7) ;
+        when x"8" => O_DA <= "000"  & reg(8)(4 downto 0) ;
+        when x"9" => O_DA <= "000"  & reg(9)(4 downto 0) ;
+        when x"A" => O_DA <= "000"  & reg(10)(4 downto 0) ;
+        when x"B" => O_DA <= reg(11);
+        when x"C" => O_DA <= reg(12);
+        when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
+        when x"E" => if (reg(7)(6) = '0') then -- input
+                       O_DA <= ioa_inreg;
+                     else
+                       O_DA <= reg(14); -- read output reg
+                     end if;
+        when x"F" => if (Reg(7)(7) = '0') then
+                       O_DA <= iob_inreg;
+                     else
+                       O_DA <= reg(15);
+                     end if;
+        when others => null;
+      end case;
+    end if;
+  end process;
+  --
+  p_divider              : process
+  begin
+    wait until rising_edge(CLK);
+    -- / 8 when SEL is high and /16 when SEL is low
+    if (ENA = '1') then
+      ena_div <= '0';
+      ena_div_noise <= '0';
+      if (cnt_div = "0000") then
+        cnt_div <= (not I_SEL_L) & "111";
+        ena_div <= '1';
+
+        noise_div <= not noise_div;
+        if (noise_div = '1') then
+          ena_div_noise <= '1';
+        end if;
+      else
+        cnt_div <= cnt_div - "1";
+      end if;
+    end if;
+  end process;
+
+  p_noise_gen            : process
+    variable noise_gen_comp : std_logic_vector(4 downto 0);
+    variable poly17_zero : std_logic;
+  begin
+    wait until rising_edge(CLK);
+
+    if (reg(6)(4 downto 0) = "00000") then
+      noise_gen_comp := "00000";
+    else
+      noise_gen_comp := (reg(6)(4 downto 0) - "1");
+    end if;
+
+    poly17_zero := '0';
+    if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
+
+    if (ENA = '1') then
+
+      if (ena_div_noise = '1') then -- divider ena
+
+        if (noise_gen_cnt >= noise_gen_comp) then
+          noise_gen_cnt <= "00000";
+          poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
+        else
+          noise_gen_cnt <= (noise_gen_cnt + "1");
+        end if;
+      end if;
+    end if;
+  end process;
+  noise_gen_op <= poly17(0);
+
+  p_tone_gens            : process
+    variable tone_gen_freq : array_3x12;
+    variable tone_gen_comp : array_3x12;
+  begin
+    wait until rising_edge(CLK);
+
+    -- looks like real chips count up - we need to get the Exact behaviour ..
+    tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
+    tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
+    tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
+    -- period 0 = period 1
+    for i in 1 to 3 loop
+      if (tone_gen_freq(i) = x"000") then
+        tone_gen_comp(i) := x"000";
+      else
+        tone_gen_comp(i) := (tone_gen_freq(i) - "1");
+      end if;
+    end loop;
+
+    if (ENA = '1') then
+      for i in 1 to 3 loop
+        if (ena_div = '1') then -- divider ena
+
+          if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
+            tone_gen_cnt(i) <= x"000";
+            tone_gen_op(i) <= not tone_gen_op(i);
+          else
+            tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
+          end if;
+        end if;
+      end loop;
+    end if;
+  end process;
+
+  p_envelope_freq        : process
+    variable env_gen_freq : std_logic_vector(15 downto 0);
+    variable env_gen_comp : std_logic_vector(15 downto 0);
+  begin
+    wait until rising_edge(CLK);
+    env_gen_freq := reg(12) & reg(11);
+    -- envelope freqs 1 and 0 are the same.
+    if (env_gen_freq = x"0000") then
+      env_gen_comp := x"0000";
+    else
+      env_gen_comp := (env_gen_freq - "1");
+    end if;
+
+    if (ENA = '1') then
+      env_ena <= '0';
+      if (ena_div = '1') then -- divider ena
+        if (env_gen_cnt >= env_gen_comp) then
+          env_gen_cnt <= x"0000";
+          env_ena <= '1';
+        else
+          env_gen_cnt <= (env_gen_cnt + "1");
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_envelope_shape       : process(env_reset, CLK)
+    variable is_bot    : boolean;
+    variable is_bot_p1 : boolean;
+    variable is_top_m1 : boolean;
+    variable is_top    : boolean;
+  begin
+        -- envelope shapes
+        -- C AtAlH
+        -- 0 0 x x  \___
+        --
+        -- 0 1 x x  /___
+        --
+        -- 1 0 0 0  \\\\
+        --
+        -- 1 0 0 1  \___
+        --
+        -- 1 0 1 0  \/\/
+        --           ___
+        -- 1 0 1 1  \
+        --
+        -- 1 1 0 0  ////
+        --           ___
+        -- 1 1 0 1  /
+        --
+        -- 1 1 1 0  /\/\
+        --
+        -- 1 1 1 1  /___
+    if (env_reset = '1') then
+      -- load initial state
+      if (reg(13)(2) = '0') then -- attack
+        env_vol <= "11111";
+        env_inc <= '0'; -- -1
+      else
+        env_vol <= "00000";
+        env_inc <= '1'; -- +1
+      end if;
+      env_hold <= '0';
+
+    elsif rising_edge(CLK) then
+      is_bot    := (env_vol = "00000");
+      is_bot_p1 := (env_vol = "00001");
+      is_top_m1 := (env_vol = "11110");
+      is_top    := (env_vol = "11111");
+
+      if (ENA = '1') then
+        if (env_ena = '1') then
+          if (env_hold = '0') then
+            if (env_inc = '1') then
+              env_vol <= (env_vol + "00001");
+            else
+              env_vol <= (env_vol + "11111");
+            end if;
+          end if;
+
+          -- envelope shape control.
+          if (reg(13)(3) = '0') then
+            if (env_inc = '0') then -- down
+              if is_bot_p1 then env_hold <= '1'; end if;
+            else
+              if is_top then env_hold <= '1'; end if;
+            end if;
+          else
+            if (reg(13)(0) = '1') then -- hold = 1
+              if (env_inc = '0') then -- down
+                if (reg(13)(1) = '1') then -- alt
+                  if is_bot    then env_hold <= '1'; end if;
+                else
+                  if is_bot_p1 then env_hold <= '1'; end if;
+                end if;
+              else
+                if (reg(13)(1) = '1') then -- alt
+                  if is_top    then env_hold <= '1'; end if;
+                else
+                  if is_top_m1 then env_hold <= '1'; end if;
+                end if;
+              end if;
+
+            elsif (reg(13)(1) = '1') then -- alternate
+              if (env_inc = '0') then -- down
+                if is_bot_p1 then env_hold <= '1'; end if;
+                if is_bot    then env_hold <= '0'; env_inc <= '1'; end if;
+              else
+                if is_top_m1 then env_hold <= '1'; end if;
+                if is_top    then env_hold <= '0'; env_inc <= '0'; end if;
+              end if;
+            end if;
+
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_chan_mixer           : process(cnt_div, reg, tone_gen_op)
+  begin
+    tone_ena_l  <= '1'; tone_src <= '1';
+    noise_ena_l <= '1'; chan_vol <= "00000";
+    case cnt_div(1 downto 0) is
+      when "00" =>
+        tone_ena_l  <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <=  reg(8)(4 downto 0);
+        noise_ena_l <= reg(7)(3);
+      when "01" =>
+        tone_ena_l  <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <=  reg(9)(4 downto 0);
+        noise_ena_l <= reg(7)(4);
+      when "10" =>
+        tone_ena_l  <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
+        noise_ena_l <= reg(7)(5);
+      when "11" => null; -- tone gen outputs become valid on this clock
+      when others => null;
+    end case;
+  end process;
+
+  p_op_mixer             : process
+    variable chan_mixed : std_logic;
+    variable chan_amp : std_logic_vector(4 downto 0);
+  begin
+    wait until rising_edge(CLK);
+    if (ENA = '1') then
+
+      chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
+
+      chan_amp := (others => '0');
+      if (chan_mixed = '1') then
+        if (chan_vol(4) = '0') then
+          if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
+            chan_amp := "00000";
+          else
+            chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
+          end if;
+        else
+          chan_amp := env_vol(4 downto 0);
+        end if;
+      end if;
+
+      dac_amp <= x"00";
+      case chan_amp is
+        when "11111" => dac_amp <= x"FF";
+        when "11110" => dac_amp <= x"D9";
+        when "11101" => dac_amp <= x"BA";
+        when "11100" => dac_amp <= x"9F";
+        when "11011" => dac_amp <= x"88";
+        when "11010" => dac_amp <= x"74";
+        when "11001" => dac_amp <= x"63";
+        when "11000" => dac_amp <= x"54";
+        when "10111" => dac_amp <= x"48";
+        when "10110" => dac_amp <= x"3D";
+        when "10101" => dac_amp <= x"34";
+        when "10100" => dac_amp <= x"2C";
+        when "10011" => dac_amp <= x"25";
+        when "10010" => dac_amp <= x"1F";
+        when "10001" => dac_amp <= x"1A";
+        when "10000" => dac_amp <= x"16";
+        when "01111" => dac_amp <= x"13";
+        when "01110" => dac_amp <= x"10";
+        when "01101" => dac_amp <= x"0D";
+        when "01100" => dac_amp <= x"0B";
+        when "01011" => dac_amp <= x"09";
+        when "01010" => dac_amp <= x"08";
+        when "01001" => dac_amp <= x"07";
+        when "01000" => dac_amp <= x"06";
+        when "00111" => dac_amp <= x"05";
+        when "00110" => dac_amp <= x"04";
+        when "00101" => dac_amp <= x"03";
+        when "00100" => dac_amp <= x"03";
+        when "00011" => dac_amp <= x"02";
+        when "00010" => dac_amp <= x"02";
+        when "00001" => dac_amp <= x"01";
+        when "00000" => dac_amp <= x"00";
+        when others => null;
+      end case;
+
+      if (cnt_div(1 downto 0) = "10") then
+        audio_mix   <= (others => '0');
+        audio_final <= audio_mix;
+      else
+        audio_mix   <= audio_mix + ("00" & dac_amp);
+      end if;
+
+      if (RESET_L = '0') then
+        O_AUDIO(7 downto 0) <= "00000000";
+      else
+        if (audio_final(9) = '0') then
+          O_AUDIO(7 downto 0) <= audio_final(8 downto 1);
+        else -- clip
+          O_AUDIO(7 downto 0) <= x"FF";
+        end if;
+      end if;
+    end if;
+  end process;
+
+  p_io_ports             : process(reg)
+  begin
+    O_IOA <= reg(14);
+
+    O_IOA_OE_L <= not reg(7)(6);
+    O_IOB <= reg(15);
+    O_IOB_OE_L <= not reg(7)(7);
+  end process;
+
+  p_io_ports_inreg       : process
+  begin
+    wait until rising_edge(CLK);
+    ioa_inreg <= I_IOA;
+    iob_inreg <= I_IOB;
+  end process;
+end architecture RTL;