From 45d6ea4c283a6d735eeef17fe617ea5158bdf3a8 Mon Sep 17 00:00:00 2001 From: Marcel Date: Thu, 21 Mar 2019 13:22:24 +0100 Subject: [PATCH] New Core --- .../Crazy Climber.jpg | Bin .../CrazyClimber_MiST/CClimber.qpf | 0 .../CrazyClimber_MiST/CClimber.qsf | 0 .../CrazyClimber_MiST/README.txt | 0 .../CrazyClimber_MiST/Release/CClimber.rbf | Bin .../CrazyClimber_MiST/clean.bat | 0 .../CrazyClimber_MiST/rtl/CClimber_mist.sv | 0 .../CrazyClimber_MiST/rtl/T80/T80.vhd | 0 .../CrazyClimber_MiST/rtl/T80/T80_ALU.vhd | 0 .../CrazyClimber_MiST/rtl/T80/T80_MCode.vhd | 0 .../CrazyClimber_MiST/rtl/T80/T80_Pack.vhd | 0 .../CrazyClimber_MiST/rtl/T80/T80_Reg.vhd | 0 .../CrazyClimber_MiST/rtl/T80/T80s.vhd | 0 .../CrazyClimber_MiST/rtl/build_id.sv | 0 .../CrazyClimber_MiST/rtl/build_id.tcl | 0 .../rtl/cclimber_big_sprite_palette.vhd | 0 .../rtl/cclimber_big_sprite_tile_bit0.vhd | 0 .../rtl/cclimber_big_sprite_tile_bit1.vhd | 0 .../rtl/cclimber_palette.vhd | 0 .../rtl/cclimber_program.vhd | 0 .../rtl/cclimber_samples.vhd | 0 .../rtl/cclimber_tile_bit0.vhd | 0 .../rtl/cclimber_tile_bit1.vhd | 0 .../CrazyClimber_MiST/rtl/crazy_climber.vhd | 0 .../rtl/crazy_climber_sound.vhd | 0 .../CrazyClimber_MiST/rtl/dac.sv | 0 .../CrazyClimber_MiST/rtl/gen_ram.vhd | 0 .../rtl/greybox_tmp/cbx_args.txt | 0 .../CrazyClimber_MiST/rtl/hq2x.sv | 0 .../CrazyClimber_MiST/rtl/keyboard.sv | 0 .../CrazyClimber_MiST/rtl/mist_io.sv | 0 .../CrazyClimber_MiST/rtl/osd.sv | 0 .../CrazyClimber_MiST/rtl/pll.qip | 0 .../CrazyClimber_MiST/rtl/pll.v | 0 .../CrazyClimber_MiST/rtl/scandoubler.sv | 0 .../CrazyClimber_MiST/rtl/video_gen.vhd | 0 .../CrazyClimber_MiST/rtl/video_mixer.sv | 0 .../CrazyClimber_MiST/rtl/ym_2149_linmix.vhd | 0 .../Crazy Climbe Hardware/River Patrol.jpg | Bin 0 -> 118780 bytes .../River Patrol_MiST/README.txt | 159 ++ .../River Patrol_MiST/Release/RiverPatrol.rbf | Bin 0 -> 286024 bytes .../River Patrol_MiST/RiverPatrol.qpf | 30 + .../River Patrol_MiST/RiverPatrol.qsf | 174 ++ .../River Patrol_MiST/clean.bat | 38 + .../River Patrol_MiST/rtl/RiverPatrol_mist.sv | 172 ++ .../River Patrol_MiST/rtl/T80/T80.vhd | 1073 +++++++++ .../River Patrol_MiST/rtl/T80/T80_ALU.vhd | 351 +++ .../River Patrol_MiST/rtl/T80/T80_MCode.vhd | 1934 +++++++++++++++++ .../River Patrol_MiST/rtl/T80/T80_Pack.vhd | 208 ++ .../River Patrol_MiST/rtl/T80/T80_Reg.vhd | 105 + .../River Patrol_MiST/rtl/T80/T80s.vhd | 190 ++ .../River Patrol_MiST/rtl/build_id.sv | 2 + .../River Patrol_MiST/rtl/build_id.tcl | 35 + .../rtl/cclimber_big_sprite_palette.vhd | 24 + .../rtl/cclimber_big_sprite_tile_bit0.vhd | 150 ++ .../rtl/cclimber_big_sprite_tile_bit1.vhd | 150 ++ .../rtl/cclimber_palette.vhd | 26 + .../rtl/cclimber_program.vhd | 1302 +++++++++++ .../rtl/cclimber_tile_bit0.vhd | 278 +++ .../rtl/cclimber_tile_bit1.vhd | 278 +++ .../River Patrol_MiST/rtl/crazy_climber.vhd | 816 +++++++ .../rtl/crazy_climber_sound.vhd | 140 ++ .../River Patrol_MiST/rtl/dac.sv | 33 + .../River Patrol_MiST/rtl/gen_ram.vhd | 84 + .../River Patrol_MiST/rtl/hq2x.sv | 454 ++++ .../River Patrol_MiST/rtl/mist_io.sv | 530 +++++ .../River Patrol_MiST/rtl/osd.sv | 194 ++ .../River Patrol_MiST/rtl/pll.qip | 4 + .../River Patrol_MiST/rtl/pll.v | 365 ++++ .../River Patrol_MiST/rtl/scandoubler.sv | 195 ++ .../River Patrol_MiST/rtl/video_gen.vhd | 131 ++ .../River Patrol_MiST/rtl/video_mixer.sv | 243 +++ .../River Patrol_MiST/rtl/ym_2149_linmix.vhd | 645 ++++++ Arcade_MiST/README.txt | 5 +- 74 files changed, 10517 insertions(+), 1 deletion(-) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/Crazy Climber.jpg (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/CClimber.qpf (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/CClimber.qsf (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/README.txt (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/Release/CClimber.rbf (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/clean.bat (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/CClimber_mist.sv (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/T80/T80.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/T80/T80_ALU.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/T80/T80_MCode.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/T80/T80_Pack.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/T80/T80_Reg.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/T80/T80s.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/build_id.sv (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/build_id.tcl (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/cclimber_big_sprite_palette.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/cclimber_palette.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/cclimber_program.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/cclimber_samples.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/cclimber_tile_bit0.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/cclimber_tile_bit1.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/crazy_climber.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/crazy_climber_sound.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/dac.sv (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/gen_ram.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/greybox_tmp/cbx_args.txt (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/hq2x.sv (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/keyboard.sv (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/mist_io.sv (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/osd.sv (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/pll.qip (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/pll.v (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/scandoubler.sv (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/video_gen.vhd (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/video_mixer.sv (100%) rename Arcade_MiST/{Custom Hardware => Crazy Climbe Hardware}/CrazyClimber_MiST/rtl/ym_2149_linmix.vhd (100%) create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol.jpg create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/README.txt create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/Release/RiverPatrol.rbf create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/RiverPatrol.qpf create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/RiverPatrol.qsf create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/clean.bat create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/RiverPatrol_mist.sv create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_ALU.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_MCode.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_Pack.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_Reg.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80s.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/build_id.sv create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/build_id.tcl create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_palette.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_palette.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_program.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_tile_bit0.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_tile_bit1.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/crazy_climber.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/crazy_climber_sound.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/dac.sv create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/gen_ram.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/hq2x.sv create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/mist_io.sv create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/osd.sv create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.qip create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.v create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/scandoubler.sv create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/video_gen.vhd create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/video_mixer.sv create mode 100644 Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/ym_2149_linmix.vhd diff --git a/Arcade_MiST/Custom Hardware/Crazy Climber.jpg b/Arcade_MiST/Crazy Climbe Hardware/Crazy Climber.jpg similarity index 100% rename from Arcade_MiST/Custom Hardware/Crazy Climber.jpg rename to Arcade_MiST/Crazy Climbe Hardware/Crazy Climber.jpg diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/CClimber.qpf b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/CClimber.qpf similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/CClimber.qpf rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/CClimber.qpf diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/CClimber.qsf b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/CClimber.qsf similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/CClimber.qsf rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/CClimber.qsf diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/README.txt b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/README.txt similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/README.txt rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/README.txt diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/Release/CClimber.rbf b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/Release/CClimber.rbf similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/Release/CClimber.rbf rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/Release/CClimber.rbf diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/clean.bat b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/clean.bat similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/clean.bat rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/clean.bat diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/CClimber_mist.sv b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/CClimber_mist.sv similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/CClimber_mist.sv rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/CClimber_mist.sv diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80_ALU.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80_ALU.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80_ALU.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80_MCode.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80_MCode.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80_MCode.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80_Pack.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80_Pack.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80_Pack.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80_Reg.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80_Reg.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80_Reg.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80s.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/T80/T80s.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/T80/T80s.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/build_id.sv b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/build_id.sv similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/build_id.sv rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/build_id.sv diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/build_id.tcl b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/build_id.tcl similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/build_id.tcl rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/build_id.tcl diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_palette.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_palette.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_palette.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_palette.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_palette.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_palette.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_palette.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_palette.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_program.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_program.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_program.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_program.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_samples.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_samples.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_samples.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_samples.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit0.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit0.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit0.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit0.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit1.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit1.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit1.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/cclimber_tile_bit1.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/crazy_climber.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/crazy_climber.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/crazy_climber.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/crazy_climber.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/crazy_climber_sound.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/crazy_climber_sound.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/crazy_climber_sound.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/crazy_climber_sound.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/dac.sv b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/dac.sv similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/dac.sv rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/dac.sv diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/gen_ram.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/gen_ram.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/gen_ram.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/greybox_tmp/cbx_args.txt b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/greybox_tmp/cbx_args.txt similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/greybox_tmp/cbx_args.txt rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/greybox_tmp/cbx_args.txt diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/hq2x.sv b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/hq2x.sv similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/hq2x.sv rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/hq2x.sv diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/keyboard.sv b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/keyboard.sv similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/keyboard.sv rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/keyboard.sv diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/mist_io.sv b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/mist_io.sv similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/mist_io.sv rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/mist_io.sv diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/osd.sv b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/osd.sv similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/osd.sv rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/osd.sv diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/pll.qip b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/pll.qip similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/pll.qip rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/pll.qip diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/pll.v b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/pll.v similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/pll.v rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/pll.v diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/scandoubler.sv b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/scandoubler.sv similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/scandoubler.sv rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/scandoubler.sv diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/video_gen.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/video_gen.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/video_gen.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/video_gen.vhd diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/video_mixer.sv b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/video_mixer.sv similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/video_mixer.sv rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/video_mixer.sv diff --git a/Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/ym_2149_linmix.vhd b/Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/ym_2149_linmix.vhd similarity index 100% rename from Arcade_MiST/Custom Hardware/CrazyClimber_MiST/rtl/ym_2149_linmix.vhd rename to Arcade_MiST/Crazy Climbe Hardware/CrazyClimber_MiST/rtl/ym_2149_linmix.vhd diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol.jpg b/Arcade_MiST/Crazy Climbe Hardware/River Patrol.jpg new file mode 100644 index 0000000000000000000000000000000000000000..40750609c24ed2f4fb3bd8a10cef022b402308b8 GIT binary patch literal 118780 zcmcG#30Mno@`IAFQ9F+Zc-%mtY-~__Q7F_pzT565-T50KDZJms)%(`{!*GWsSms`JHb^~%q%WOo;ZP@th z^{-BTef-y_klzjKq}Tnr;{WWBd_iqq_gm8%l+>!7sNXiPlG?mVQj5YM_qqld(XT=M z>#^!Lsnu)NBDb_&7P+8!6LR}fQokWLyJq!j%pR{yFMqfc)Yt)KFkT12dtpt`DitKh9XOz3c%24B-I zB=530R9E5`Jyoyx6_$q z+cL8la?B*M_XFEMt8t=jUT0;6mvU2AB<2#|6M46nXB@cRQrxvkLt^7|rG>nKYj&bPCTaVP43+iPYJz zD&AAP>j1o@@Zo6iv^3+C$Ki?NMFpN)nQ9f}YjGj9grwx+V&ZDAG)%GRMEaY_L-!@9 zg^r7-Xrspi6#^1<>;-qYd40IP`4lxMT-1hoVRsxQ z|KDwA83S+s`YlrXKeYSbE&uCYOdfpfPIr>0wY)y%H!1Zv7=AGn@cw#bG$1-(?8TFy zY88b*@9#}ZR=R?@g|q#FnWYJrbES`UGcr##ABt6f3vW--RJ9MXznb_n`z+3@1Rb63 zqPnPgnyo#tI;5|j)v3}%VbHEk5<97d{GU?(+v zG-6C-PFj|~J!_Y8CFG?yAvq;D^&Y>wIa z`;3HiyP1Ecc#4mM8Y0zz48feTDzMdX#ZZEh26Z2UWHxT8=Qm#{l&sSmKwhX5)-eQ^ zGwVj`%0JT2?HM&*t^SB{p-3MzIWss!ndWDLXBOCSS=Q9HAXmrZzIqO0^{Y@zql^a3 z+c{~@?XqE@Jrm=$%e|ZC$H%)2rF?&}=Tra#^jq}dX3fO&SOO)UATbkct=%TXlF#<` zW(|0Mc(9>!EOBNKxuGos0eH@uG%D|wwXUn>Jf%l(SCoHaJuY=>eu3*Yqs2w{FqsBZ zY5MJYMp6~xR3dz7$25NL=*OGfPZE>^@#qk%i6#5$%KOok{xi4kt|U?i{M-h1w2vn2 z)A}5Qo*{_rzzjhrm`A$KVeK(eE5BdM(Ee$TdsJ%E7kP))V522R93PY7xj5A*k?u@? z#^yt;2H&plrOEUTTJ1smWKkk4SBA5ksmujfglYZ=P#K}aE_57}gAWBz1^)cTv@*8M zSsQ)Zfu}#I^<`>+0Wms68`NWLx*c<|B~ibyO%UL)KXxldxe)(WznjaU)y;Tu7*YG6 z!1Ue;^48YDkOby({A$=dXF(d4oe&X04M8XvpFW|!tqotKXQ;-%4253U#$g;OCiea$ zJi-@PK7fvLY|ys+Ax0xh1eWQH5PUVlf8i#uc#bWJM7lS{1btPS67b9 z+phYbwzG~B6tfL*jD1`D3$x+k!3X~UZS6=W^#nE3*J`GW_6-bi3-t|7*(p@s?($pY z&yh9%sVU>+k#!91!fCe}vJ4tT*L#kai(WrfqIKcJsVL}*1hu-egh$V2hv>swSaOq_ zGV61KgBOhAo*h>DiF1a}uc-0TIA%T(Fec7oq(1qH%4-qBgf^i*#&vtJC_#0n4cORU zY+16wi_|vHY+)-~0shghhZ}*{0Ab%{M}vlpb$%zDJ1wWv6kDHUUx2;QUjcC6Xi}i) z26Utlj2H?&Y(zkh-+!&2Nm#jh#*|u3muVdnol_7ceGF**0-H!sk9?q$@n2wcDX%h( zIS@CtoEzJXafCE@S45)9DMC6y`P@CPYo~D2m>&zIKN7xe*l;*+kPU>+?OS4PzjVAnFtD>>Yk|7exak=6 z6f7+yg#7NiqHA?qaJJ0Tn&yScxJ_JNqXsuSu_K0;@jRcwa0%)L1#QX2OZU5g@pVC_ zADb`sL(L7l4Vpv`FPU1_NKmmr$yyo)dGS<&l3k?8g15NhTUnlue?(z;n~BblGJh-r z?@HiFR#JXMVvKTSA-dIm{{vDoXiX z;t&Hp5b(H$KkF4-$sDsam?Nr#$u*ZiKaMB{?c6%jx@3KrlzkPLbHn^(Wb1cR1cgl! zl!s5aK=_WTB?zhGkOao)PuC!{Ngjr)1#RsdvW&(O0y(U00bbUkYZO6vX+m{QiEeC2 z9XYoeZ+%ARyC+ln)hXw{TeDU$21%g*le`hrEhG382}+qH%V*Z0*LjeC=dTU-%^DY0 z=kz$^`$?T!YxEOaBA9M5Vb?8f;^9?*Y3|Z~T;oyU@i9pAa597=>IFt0h4t z+1IKQX#x_JeO7|HGL@!Y5^G~`(QXJzP?f&7_%s-+Grup28H;H&K)*lcX-+*PK|LI_ z*UMhF5Whk^6|&Q+(fbnVFn?|S&G=sAZcAecpPL=cbYLUVHhsgYD}R1)$lgBqV`%t> zf#@eKV5^`@8cSt1dtEE)EG=G-RJ9}1Yf$qm%`O^CkaYUJx)%aX4Z<$FrO`VRM|ZVi5tP`ipvmV z4W*m#qy-L7aq1ra$s+@$Y2@^4)cY-G*B%kjLdj;39QaVA9}p&I%v4t^ZJNEcHAq8( z@`sY)DEw7Q?}9bR)5GHPEO&=<lt{16BN&ZiiX5i>c{PH+N=qvEqv1Xu ztZuyCa>;j|wo(@|CL`7=EeTh{G87M+-ky3l=)16zxN3+GRMv)#Y`+^VGLN6{n zI(sCQg5&R8}#uGUoP{xfh4Yr(!I4k=p49_MX zK^(WLN)341T3SH4p6=XLxxY82{3%SXtrS0jcOZ9Z1K~da)vdhi)CY5hCP|CS1)&a& zeod;bO%7c|WxO}y_gvAB5Eqr_3{=~3WuMYndoPjsarXU>(o8!;15^Yb!6eb|0oC{| zq|@=XeCaUAcW-4vg&n|*%m4Dz^p2$?td&uhG`csjW3P2`(e>F=HvP~i{OOm32ho); zTxSJ%9h??WwGVd~`u*}%4q?rJ1a-~hR`2Wz@tHrfr9!1z_Cr7okz!fcI$YYWw`)Fb zm#DY$0I_3jI0ryO-aO+ZwK{r6=HyHEuJ8b#g!27ra-=aXrHdu-6TieYb6MaYi{&A% zgnnP2EhY!5PDf3&#HHbQC}D-0${o7ldKskE$~%5 zylb#-Imn6_xcH9ixPo4PE@AsZunk)4$$S_006$Y>x(o0WyAs8zkQR@{9z+(r9mfWT z$@ly;|JRLzhO{G0X(d_&e&{3h?=0xxr*t-Blhp?oXN0s|NS^H=CVBV9Dz-2P$P=N) zQr8WMGoULznII9~RC(tx&|)OZ=>J%Ou_NvTs=hKd-Nh?T;$$h7?S^8D2FpP~;FH&; z_v!#D=6K)v^PCe~Qk9+a6AgUY50M+|V5vd7}Bhh~Zt(gTH8wj?5!6G7y6M?;+-aECW`}2puZ{?m)KYp*kBr0KP1U-F|QN zTIRyC#t1de1Pyo^f;}BrD>g$GVT_q6!7UeUbu>todlIuD0wLwMufgXjw<73QMin?goH7k^w_(p}LPDsHTmWlcZRAK4A|DmVnJ!=?p^@eC; z->oCRQJJ}<*qSj~)4`Np^egs`=xXcal+P(!DLQ}mXuql4`415x;`7<8fw!+S{kTB? z-k^gSWupc_u21&6)^`$=SXX2@AFTRcTQso|nPSEJg0M-0Gk4s(lw7tAgJ<)%hJR zDTzCO={j-cTG?>t6cgGy1#atOej{vPw1mEeeYieY1o30&1FminU4Ur4s?`_kH8eb`93^ajla5V2kvWr$QzDU%yrW3 z6M(V=Wdf&leFsU0)&~UMS-4F4OwA1-hR2*LJ{-g9wXTA({I!fMNQVbJnc?y_r#%!AoGrPOElwcy+?aT;R^NvT zU*Zqo#Az-jjPvwtRolpNTmpSCX-WO}E9`x$o~)7Kz=p+lEwq8RG(k^FO7ch3a z(5@17%@Bt%ts0?x#?&9a?IAq}=~=TbDz53O=BEyT6n`+0*UHAs;1LoLP30v!Tcv~E zg3CRA0{<$xM+OtbKOhx8^C4^i;bXbgK({bFe0T->_Gw_qfk(K6`7_A;u5NDE!vbzu zAjY|b!VYCZVTRy4xluX_-ymv#&6gg^ip3A5sUx2ENny4B7AsyJGTCoEwnte78)TsWge^yO8RcCLUwK61yAo+Ws z>PUr^$cN-o+PoBH7Ho!>?KiKa*Z2KQ?-B+*C;m0ayExa&s>SfW!YR6{uI3FN5%uMeD|6 zcmqOVWuy}#jQIbF?Oak3X+amk&HNfcKp_$uy0Oa}@fNKdxG7;eUaXdYLS%`(c>%Oe zG`Qm()fXAMDbB>Hm#GYcRK90}(SzDoA9{R_(yDj7n%-R8c+s4e~I&;6ds({1x<5 z(~ye$WX)0@@il#!U~NSvmyRDE?zD_ZQFL)pYWf-wtf+J*`W&@_X5>|zGwEi(9RI?h zyfG_Xyu*D^nk3%?%we_I5|lv}6le)63^7UoXsZEoVy23hOpu#YHct!RRi5NMJDuBd z=!ELR!`2ZRL7WO3Gex!}y;kg%%s-nCLXu9t3P#vA%Eb2n#=j0`4Q z1fU0yz{!R;vk*GJFx}0Jdzt`ODWe`Fm|t`cT3H`56-#4(l-@#6Zy) zODyn8^-Zh;>_Pi#-dCja#ACD~PaT)B#K`Q%bKdfH#5XDF{~I}QtwS_HD4!r!MBL1F z!>AA{dWGJ1x1 zk0A&@`4_Z|1O)vpB@YlJ#;`?`nwXW0M2Qu6xeXv`>pyi~qvnkw9;70jJUp zRwH6A52D}9zeJvMAL2eTi=4$@$EcEYN=iz3_=kwVC1+p54|K@O{^ao#`_kNo)XTwx zyX*6PhF+Udq`=spgPauVyvk>*#Jgov&wDE!!35;t4e{No5W#zbtPQ$-uzVL#Jt)?= zoCq}Di{4@mHUcRNHADUSA5Jjp3cP4e)WTD5%T~$=p5h$f3Pu`o>A1^~clK0NM--eV zA@t7M9ahEHdms7#DO}G7C>TTveTp-i+6HWdmsfxAvetrnXgp={wY zB(H-|N@eUSj+}no%Vp(|vGAFmfhE0zj2=}5vx95>h}sagqSHu%+U}W#1u>b3GG9$r zDK+rgmRIh$93NMPaU5^hZ%~vGOR3@wUiCaTG7_p^T()dE?Iqgi4iqp$hbc2#ypro0 zBGM)&R>vJ<9$ruAU>rtbbOwfJ$J*i!>$c-$y1RRs8JBlYMInG}z*WniBf12X!0V4= z>VU4Ax-?DRV2>eQ-h($CIY4~rab4}y<8Kqhhlpp#X$NF*{cBZHz3TlH6;0coFeEoG8bg~L5k!L5tEDqxB&o6}!;j(s z4{@lARtPz@a?22>S5S)sHGTj$W4%^Bi67!UoX|+H_Pz!3&vyJ4nAHvCMNkvxX`T2` z#yad#5im7RIs!)IA#T4qr`^~(tIOGha;4sq_*X9cJVowlLqMLjqUf_}_wwT507Z<< zP@o21J%Y`8f>|p;xuKtSViXYd{+p2vzHW{|u2UEVWEtoiQRD*{wuOAe*zy844#LNKFVcMqf`GkDUSb{P zDV2Acs`4!hoaHRkrlH$M=8N9va&!fn*bUq)txB?VbXCn}ZSh%#(MhOsUq~B+v9+lv zL>lquyi>U<&IHg(-^j+VZo~D~eR*94P;Txh-HjB zl8BSHTGKLGe@jL14+C~0z;J|D$q=Y9pJMGk?4&37`-tia{GxC5w&ajmKygV7-c=1a z&BNERK6z~kc-TIj$07E2AMe_NdsDgou9uk5+X`bDxf=t|9L$-fe_LeDJmeE$B`JY> zC)PfFLg4!?z3#J0NSZV7j5fL~cqV?c#OPJwx}#+Q}$uEuBlW0z4J#&!$BK8@%ysZN6gU<}I9l`lQww3Cf-r zPe1thCj!;V;tIrFZ2&bm_n-6V0}GD)gtSa{Ao5+!hD-P2PDV(VAX>=zV2n+4FXqf! z4?m!=zB8u81UgjHlI`L=sOUFN>A?u3k*>Uvb*_v{=U8bX;W~~bi0Zz(xW2b^(o)3e zr`54QZObpe6mu#14yOsSEWbXT)BCi)WqIb-HLv?aOXjA@;wn&tX-Z=?M1v2JaG6OYu_{VctW57p8f^xSu{hD*X|7qXh zIpQPnCVo2xbA?B5O-?R%`Ggy+U4H;>NFWxGJ|mH`X1}MY1mzhRNEqAyCi4FGBTg+w zIh9hjqU)ixFa0-*yRUkGEEfNX7%$%Fbt+MSYM#}KvyRYgRS9PN_}O)fkxE_-Hw^Ml zT=o+rfUa3!99}uV-@2qyf_i!OyF!9r?2QFgrySu;Qw)<(;1$`&V zd({d;yjBvK8(QU}Gc3@d%ULp_j?;ny=667kQT&ZLW57j=WWGT!8BX}27RE{{V~{x9 zzA!iAiXif_4t>av!`kj4L2bh7`?~q+T-J1P?{D($>_K?(5TZ2m&H`xU&T(YzDRnje zu9QSfZzAC4^!`rsJE@It=&jK@t*iiC@rDAI7T?I0MzZ@zjVPgVfi6Kk&N%^i0Xn(bg!SLtGRn;~?PFNajt4?!wcTWuCwqo;tY3cg zC@t-t^{_|pIX@O5+=aNC)o8HOID#cUfN9*zgf{KgFG9Z77&?rBisBH*+SEhGBPJ_E zPCAk_a!J?@y4-{>VgR0soAN|Y>F%ww>KQ$B#D6`KCwcM)Lm5LAm2|%YiQV6zQQv}eMDA)l~MEVesuk{q`pMeB>6Z1}QG|I)0G;2X&UJ;Vt3a_u> zKRznXft;?e8Qab26t~;?PH(qg*Ko)GtT-it*K_#`wynb@@l3_E%hfl5#C%9cFnz(I zwma|mhEFA$t|ofPUGpOsUby`TL3A`}UAQw%8j-bJ*_Ha$!nZ*&qt6Y*8E!xFZ&yyu zKZlo`+KL00qE>F{X)fsLsgUvp1Cz7UY{;qABs@X$d-nCV%*L;`&nFr_iqxj1AN&<^ zt3FP4dRV5Y`%P(goSw~AXz)yXW2^*q@Adq3%e#T0OyOv~Z`$JbyMt3slODye{Z&Sk znLm)Ue4q=V_aocwj?1I|r|sOoXapJAx&U_)pX)ya3?N}@vJHwmP!HSalezR z@SBVXs_u6Ji029|t${s^z>>58NM~ias8bJ1c;DyZnHcBdf~+IM0{SRzf^bq?P=OKI zlN;5wJC@LLlX31rL52?Z&(@yL!!7rJ70{T39vUn&=F4}gR%X^wLdlrYX6RQ614rFU zHAv%9GRabl*SUQ;p?)8_Qd+|IIe(=1Q3_HnXrT#R;`rh4VSDKxo@tStn-pU?hkq}n z%xT1YEcQ1sf*Wto28REwuccLS2ZANQT@mWKOf# zGZtTzM3^w>(xHa(wmSt*k52e9|E8r?&v^QGb4wBQySL&Ksje_m;q_RUcL=xa*ZJKq zvO9$6byBR}gdckEI5vHS6Ab)D!j#5yG#$%VJ}k?XRn*j@G$x2wjw4Rltiy=N_m8tzY!7~ayE*ParwOh4vR3`)teTmtET`sK95dTvj;`dO@}hGFNpa>4 zBAh@Sr*a9h2Oqxo@W*V@?cc1Yr?>4;y+Xuc+&jh(%v=9QD{fNl84j{C=jgdhKCSs8 zeHs37=lZjmwsVZDb6r~qDj=Q338&}|w;+bXlAzYXjUD;d#%2X-Ig>s;vK;9e#v=&| zK}1ezymbqN-?=?*&l`0|w^(UU2tp927^w382yX}61JLZs+UMY#fyG6SvrX_=02fkb% z{OqzwDFD2Ho=Y^W<&_Zbr(fTW15QtdSfz;9^AsA1$1V)1Db_ z+vU-tO`p8BsNU|vw2G~5FBx_aMhqoBxJcfZu@rq;oas%e1EV7Lj@rZH-?iT`GSP|u zOoRJp=M->DA;`?E&KH;9_LIL2Zp2>EdH`WC5mybJxtS2Rd75Q_xV;2(f3>(3ytww zw_q@i@0Ot8jnajD%X&FI784@}VY0^k<32b$@A`b}Od#GrQdGjG%u#g=_K};*;b79>_Yxg(0o^p?*ZNs{ zjxSmh2*G({_tDtVT5H+J62p5JdYFSm-gz{*Hylyc)CbJbU&tyvY9!Wfbj28v$F3cp zf2~33pxc5-c(#THHuD~{f$k;r6CwUFl6zOaWP1Ge%L(Q0F$r9$T+(^O3M44;Uv$ib z1XZ+{wgc?U>YP95wQS zEdn!?C{cJRkfYkJIN?M-)T+Bk+3xvL0PrV#ZciwR9t>U3;I+fguDox}Jhmx|m#Cc9 z9DEeXQM>;ybJRzsj?1swGg?mV#tV`<@UHqX7hppkk{C>UIZ^mMNstX$c9beV+t69Z zACtP?XaBN6?}x_h*V!+wV^4CF{~jklL4(@$R1tPNtPlFsCZ_$)&x%x|_rCctl3ubX zy+EVkudzTKMl|*)G6NP|X(WxLpEbEnw3x+gxZ9<~`*Y zu#ZrXv}9RB=w{Smc(w?SR#YB~Gz7pSi{|Q6jRnD)J)h&;z|U@(AuCtdG+88<>#KR^ zQujoVc`8F_akJ-RMtN{&1HvM0eZalwhxk9KVcUeb)Lr!S4}DH6jzO2KM|I1Fe!Fcx z#SiEBKniGXc)c9{T0(#I3wvlg%SSc`b4*k zm59P=!BjDs;mBt5`T+L@&0I~S=))R|79OYx{jl$bE6&5xl^?r{!{2J)Ir= ztGMygL8m@fmCG{BB_lD4T$_xq1|DKo%|L-}ftkIN$@Nr0{~2PD)+?s8hSEb=dTJ6hb?z(o$(ba#RwpeMnw}N39Ks{a9Mq~07n!&(E5FOuOdiet;9c5%_w~!K zDJi=>muCj~enSjIOY>zjo+4dm40vun*!z9rvllrfTTN#{;~&g-O%GqImZHK$Y9tWB z)686VKqUexSvYy+;q#dex-8hsXVg=RmLux(xiMESUlkbjAVI-B>6JQlRq=L^7UkLU z!wa5GNtpfiGoW+T1DASArN#uhXIYSiU^5jx$&kfL?_$Ilnjej#=Lb>g;dI3Xd;%#Z z%TYxZ&`Z7Y&eF%eQLB4Oe4H0t1sSit-kGiEN#VG0$~t_p)g{=cc^R>sfm5O>SgwLU zP+~lD<)eqIZACnRLg;%In3>^%DPa>;;qQY54$%_SO-e*F2viGNfWTQLbYg4}rka6F z)6nz5jj$Tbf=$}67&o?A176*of6!&}7PUMPHCt5&D2w$f9KQLH=y`TeC`Rt)MAz9; zDUG@iPZLT($N`ZV$sbJTQlen(7RZBbvWSOb|&q+!m^MHmL;b16&2h$?TCZAviRqW+EM`Tg|@Lx~f&CbxCZ+MQN@2$ecjb_oA z@n4~l_Y=P=B4<~B!Y5TH;FfmDuPT2_vg|aJ1$MF=+V*kb;j;;j2)xTC)=?J^dLl+6 zzw~3)@Rm_jO-t}w50*yyYYrn)PZuh~9{p&gN)5pwg)`iXdVO;X##VOC$FW8xHwgx& zC+WK2n=W{+R=E}sAdw*VEKohdcN1?Aj=^gfV5k0Z{hSu~57p_i_nw`~m8>4US+J|Ggee~Rh#BO)?MAC+Jwng5_AjCfpH`6LBj~fLJT4BFwirTjc zy%iV-5ZZtC-%H~&sadCe8)cTWcTYHX%`H2oQRerWrMdn~38$&gQtpx=l7rckPpqTn zK&-OZDkN~wuKs@%RsY8V>;Hq-|5m}NX61#%6?S4Th7`;vKz8z<%=en!J7jtf_@LyE zq&EK`8I~aA>GSYRj;6~Cw*kgc;5r^Oj^|{}T;@4g^Xrp7x;x%``FGk)JLj?sy>&r& z=vXFF^%O>tm7oUa;9|1e>yX_Q*oFgVzaVu8F(*&8TzHw>o8PLc>!I_W`ZDGHJ8rU& z1+OV<$?KlD z9_US~QP`lq1>3%R`gu}{vHV}Rgu>4EK+VBPCB!9Dp!=`=MMeXTy%lLd5=G!O|Cx;E zS-j8wNUR%{puUP7vmRjm){{E|_S|7MlA}j(o5$d7%rMq+u{N-HfY?N=L&pG{p;h>r zMsziK1KiiNWW9ZhfZclM!=F-ZcdKY)@h4l6pn$DiSn{`cAYJg*`aaAZdrWL%KwA~7 zeu=H}B=wRKFrQ-`a?JYcRrm+NP-o|#8-TsAfiUD;#@V#X(JqVkMqJ*dZ7*xSH%{Q3 z7WhOR^2eazb)Jdpio5|Nkra~h*<)hU#gRLQSFef$sr85_ybz*4grBbZXvrnWO$6bi zHSS01$~5i$kwr(*(i!eZ1r6e7!xDM)^mMSsx*1Z$Kp~e9ffYEtJXT3I2C71gobcPp zeT5;h^8@oHGq8X7s58W16Km)SJTKOQsZ#KA*%Bk8m{P&H**p2l>J)zSf=@j@+8`m4Jf zKW6Pf=uSvkJ(AH!;oRY7pOF?1;b<9K1x|LGi(-VvFALCee`CK-KfJ4Ut{T! z!^7q;U9DeD)^H}9Kqcz7gk5z|Vxr;}XJ@PBfeU>s$F-)$qcOt{1oUmXQyd%4O|&10 zNOf$@(F=@0Dy0Vw{Igi$e|he%Tco#H2bHTidFb5LijOYV59P__kV$u|Gmup~aDOo^MX43h*;x z*XiKyg41=jf$P%na z>XAX``oULke@lE%Q^c~NjlSV8(HQIGgNHI4?`E=oOUt`Q*xJY3o&Da$bBpEjh96EV z?Oj(yrqh`ReVfi2>$(tSc{sZo{)>Z?&K32qqOT*5x=saIvps&Q>B-t}3Z8AOjQSZa zKgLH#DA!B_yl0-zyJxzG#p!|>XoBw6^5T=uu*vHO^QVQr*{@ngea-fR-`g@8WR!%s z1OZBd!VACCgPP;CF-F0MPgp-`*w3%NqS3HDWohrJJEPA+I^G*;<677Dyhv#Z%2^4&N!Krek;~0C2Aag{Zl1GcK$z#gwR>tpdQ<}$IEwjM=44@OBLaW%XP^o>K8O5sEazw4MVwO(OAS2tR4jY zvmgWhJ4*W0^EV+GjioV{I?dOa>p;%JQvt+{YCk8xW9DJP<&Z&x&92V`CJE@#m-+1g|y86}KCuDv{s(2LPjr#3KHUbS9SG4UziZAB$ zcHDodKWnTYOd9&OB!^+2pkkgHMIAQ!rhCY|xAfvj;`Y_oVuu~rSzQwo3{Tm|3VP(>R zcBHhsnq}EMGhiL{?GGdkGm_#mEKpc>3kQb!Sx?inKb45^(O7*!)D!ebAUg>_d5PaO zmd5KhEHclJ^uZos>UTf_Yt?hBNWoyQg+Pg)HGQ0~PC$ciep(&cy;vS0drWMGgk%AK zJI;OK{@wNc047MbVixdXku{?LLXj>RKa*b34bvNN7+TE`au3AffpTUB)=AV z*<)C)4ov#c%mF^#O6Z)Jz~ebI(N`5u>lc`vTGiXOsa% zR|xbGgRhE7X&SYvVPVBN+Ka}q+dfi$KxZE|hNO$G0afx9fg(l7r1X~Tbc1A7!W#_J9aeYKzqc2&8&@g3PxF$iy}04T#!E4#`3c*X z#$Bf~^SPpcsS^XHo#Q{VC8)J*=#S=EY&k_a;LHGF7RxXmNyc+jkjQFTXj4~DZ@?u9x5P9(c93f(SlULTlkWG{9u>h4hslTb?;s@TJ+Y`MlnG<7D-GH($3vw>=Tf zP4ITaf$IpA5qZLzbWB`ksAg%~JY3Q|y(ngw_Z(a)W4)&ZtEK&U`y!BcRjYx(04%ht zois*H`&!59EZQL?wx6czL|IYCYQP9#xSr?7?SwYzbHb~DCk|=*DZi5Gva1Ist|zJ7 z^6i~+F~VWLj%n8$B^nkP33Dxm*bVlCwOM7K;`&zZSZdy}Tz*c!KzwgBMJ@1|_TmtF zxb^&TA@-#(gux%Y4A1rlEl>2&savBnjz#BOSiV|Z7VWx6-8ArR{3{@V9BmA#B=Yq{ zXG%+3Av<>EG3&c}&Bygdxh1DSeGaX<-<2&LRV;^gE-WpqXdQ8<1}Qi&(>0P;l1YS@ zH{_@6tIv=6MljmPWKUU!J8w8M=y=`gj^AyhMlF`{qvGtTqLx`C^E&PNx7~4t??}$( zzuqPJUtROBdb8!f?ai4()WZsUghd?JMRroA+Qg<3C&Mno6NF}roNjdjytGRpPX|Od z#{uUtJj=NiOGXVtBu!hSy-Um_Ap!I1hj>1X5)KH^3X7BCNu)?0*yd?1zWYOhnnK9? z;yd!=m%!&*2nh=w=UzkhVqk{wLeNLN!GZmNlq_yUPJfi3hQmQLOh>Him;(4`rI(l{ z-1O6rS1wDQhgi=V0m=?UcZaL6&CMagSs2BDF7P{L6oplnJHMb;Fd9N+zYE!ho6z|i zSAzP&YA4A{P;s4l5)|#JFci0Ro-YkO(!=-V7&#yi^z1lOluP7vIM|7U62Zh#pfsu2 zNSt~B-wz0_7VwX*iY%Gta;_58C2`JL{9Hb<0w`im2Yw{|2?B^rrW^n`x9wXZ$WHK` zohAgc=Wp>+(L;nW;)BHf1J0zQpD5Px4Q-kg$4h`&9Q*M~=Zy5Ux9A+{h?p`{p^tPB zO}*KviR=&EP1UV9PXAe<%^D+iVopaIF$xM!pHbn&n3s%u)={h>OuoCX`V4N z$o2N)8b2~3Y$BcHBZBb*?4|UqgzK5d_YjL|*t8%%@wI8l(%92mxZdo(UsX)YnF-5A zAqzUnC=W1+1cvIoOM?3$_l#wc5D`b1=1C@K29jjQZAcExYiRYECq@ ze6PQM{-U$lE0$aoWrxU{m&nelrS!h?fE7ED%(@h^mG_E3_v*e`hD(`vjW2^oB!&U} z{UCu2e6rF?f}=(m1Bft?%FCJw&xF5W{-)H3qGIs26{YR_o?M{1S?tV6T0inPI+yH@ zNWmxdae4s&SNaL$!8fplo0{f!IaMCSa3V}hG{(K4ZsGo5&jF35_ZbamuzmD9?U)kZ z1ncV?4Mdhmj9Y~PHIdy2z*YS&LalJ5BI2W$a#(UF#w&UAsE)$b!>mfOCS)isfPW`# z2N^ybYy2ip|3u}G8VM?+;WjDB;rZhkA_FK$oZ%z(2kvp3_C=)Ln#9c$L2vI{yYnyq zeL*fv&GdO4S)SYv@CZaTxE`o8d+5;U(_MhhH2ArbRX>0thvk+En)YdL+}QguRF_NbxF=>8R}o}gUv z>7xi@q_(mkc?K*G2u7F!GRt_z2_IN;%a@o=d4#P5v~a{7b(E7G_AgII8RYO zN?2hp@OqOvf$t>~!yuAc*V~ubP&$y=l z!cVg(%HosQ3o3MBnk7$MLuAdx;N6JZNWX&&t*|8<5#f17Oq;(4!Bp8{tr<LbfC!`#ZxqHWn9=IOE$Ty)9l^=X*9i?+S8= z=WIJ4^D~>N@G$l871ueZm6-j-=F~ES5g%}m!;BT*g1gL&v4^+qN*xQI)c{u3_~0CG zuRRgOTNC6kjmY?Gays!>5jzsVm=-K1z0cX{5yRW(rR7v-q*xnqO<@4y2tv2QEFpuU zr#n3Z`P_;s@Md4TWqX&ENkY`B)i)3W*wGKS>1ToxRQ=}ezJN1?G&39Sa)o+@u(LRk zf59S(jn8$RxMLTa@>=hDSAC{TJxxNIF{6h0_0&x8u?X+{!kp1P8(Fhy zf;mDgV(_f=L9MWSkqRgeKCVmK*KTBEf3C!#w7Bw4!&X1)7_t}i1SyC|gtm+gouFz4 zDbx)-zwvr!WXqtR{+aJ+KVl-Dca{R0$ktNTD$vO8FYOkrRr)vIGQH84_2*aoT4$H0 zh)Erd2IK=-s%tMDGrU~_7WFQexo)=we;UIZwZSD`VLfIWRv)o3Ey3l{?2P`oO6$9r z1FLRte>md;um?eXVl1A04ycx418Y5!uh$7>FTN{&@sVn4mLf%5+wUHPL^oH|Dn}}r zf_M48%XvEwtmHBCkXkupNj|~>RjU^nVZsny}aKzKl`brrYRP0uWS z%82*s&-0U9{9jh*T7{fSeUUjfdgqF(Of~TbSs(sFt%v}U16CU83rU?tlaw$|@tiAx?>z`x zoO15L5yEB`6nJvChQook|_}I&|?DTRn)d z)m90rh0;{OSiVSoj_2K@LeC^9kp~9Nl=>jFTfISP`HU!vlTLe zJ42*_;m#}O#8FbLH_ZQ~fdN<4FJ>?2RD#HSYxDs`ex3|&$)B+bKYWh@2|I`3!@xJW zS4h{N$k{_Q=w-K$m}J?Cu);|?B0>EgMOpUzf{2?zIW*wwZm#(MqV3z`q1yNU?XA*% zx{wm4QmGUriZE-pRVp!slF00m+(M`f#;k5qxy;TbCCrv2iAe~#Os*4>a=#BVF1ZXd zE@Lrkt$ttoa-Q?-=bY!9^PKbhW53!~tHD~|@Avchyg%>v`&0Q%O3srtHAvx6W=`Ne z7ujPPDfk-tv1wEP^Zg*rSg|2LBS;{BE$Xna44YD#OBc~g;I;Z5BEHx?yi{2W0X^X~ zD!qboblkizN;+E(p>!Wn3Fp%peQ*li5a^AG)utASKY+dR3~?9l!(z1Z{2_tDophhX z4Q*KLUL&{C#Um=6Y!?3Lv~TmPjEyDdlE;r84=u=q%GK8-D_A|ZJLNg$(>t9Z0-f`P zHKGy@Q;F?F9o6^fuF&7>;qXq4NCf=c zV|1S;Y1u74kwebClXml^^IOLT>7wlMj*pYjexu$S?%YgDuArsv&bMf}* zs+hL#Q;V1F`^j=Por?r-t#*hwH%kJ~MaBgRNrC**Q??cqEyyqJ%LEIo?pyZ?H++Sc z50i+1li%aLyz@Zqo6UPS{~&1wxo^5qenUzGQnXO}#aOvbqlD4!_3?rSO}AzZO|>5a zt1y(b4w2^P8Neko0cDBRPo{(K_MUPhETQ~zrXN-G;1O0kHQL!A-oH3|T0Jj)cy+~I z5Y>)pZk_XZf;Abmr`v|5nWE7Aj#e8oTvI%7UiFxGwDp^mxU~raJ)pG}FZ`JjY2)(x zI#-)l2DzMWTNP&9lY@S%w<~Se-tr|uSjvfI8q$j?!V{1@UIHz%YnaI02!x7Hh~$Uo z)29X)ss6^i8bl{_yqxG5Hs0-i$9Ak6=JVb9I)bIcDbW$5yXCsgK_*KquXF_z(R$5J>|D4yE_D0PnetB!WGA8Ok0e>qLaFs(gf8yF8UcWfkT0MQL zKXSpHp2;PE*H}6gx2k@{C>gQrwl=(i z#&;r8T&wB6($%ZWd{2K`R_Q_A(%X>ibt1It>CO5<&jjD2BEufzhQgA!9x)AB^vW|sH40k zqOzy>;v^9#aPqGH`gp{ROsMWFeS28G+CAzf5R#|O1{oP6+7EyvJ3K)}iHQ|TF~;)I zQ!-vJW)`BUDoM$H5( z?z^JIaZQ)6F7~VS53L-$%C9D;GqR$febAA7aO}%0a#r328WXf#!r`d!cygv@NY!Xu zmXKIZ3~J?+!z()mqsw~2e8Muy+;cLob%{^3=9+8N-c$RKRN_OozMVR`WlZv%eL99& z=tBeW%#$ILBojQV@c9!;A4wI-n1mmTPs}nL`^HzF*uVN|$onl%<6g^uJ;iFNNV#6Q zwQMJSto9NwJm`l_vM0>e{@JJHpZfau_M!8>uqK?8Fw;br!FWvMDbPq-Tp7G{1>i>( znxj)k=|K~}Tf(enb&)@Z&%6YO45&COp+Y4^R|jT#3RKJMWZLLj!w^MhjUK_qJ9nje)tbl#1Ts*_2Dua05(rerZ}50yZ+%s*nvBj6ym& z198(koHp6!FNr?c72`W8hlNZOr&dH?2KqgnoqPrDiWDRI80@nVTDR`NBF6ZSC&mgwzfNd|pSqeCHY9(C`^pNPuaPzJ}m_`wwiTD%5Wo%&6M*ef1gKb2@;;lpAws6)vErrib@ z3XnZv@ptKDe=wAfg2Lstq(1yg+OZO>HVLsh(LTP0-I!fp=T!Hr3cG3g#C?1_M*i;% zg_nH*`rG!y|Mf-vS$!>pMrA?oaJjKvZ9mM1d?8sF$L*S1P#DEq z0@*aE)S7LqgYI`1+c_M?X|(--Di@4a|ERn1b?DW-^O-*31@!lD(Y9|=_QaMbG4snS zl-zByVoG9HA|ZVax2MBnY7&)!kQ>GIAI5?&YDCv}i~aX8dHsucn-u$%jzZvQ8KF6e z3{N9Wuo0S(dp<9z%Cl_dckbIdH@3cERew?w8Wyodf=%#Y=&kqgvD5=-X9jg9a!pv`&FX{w-TM#9n*XmL^nU}UV+)`B56iND zDir?7=Inp{H{0HB-ICn*y-`?U7s&M7ZV=y=7i=)EFiC) zWb~4P5p#*h0N@|s5E56zQ@uR_4viW3$s6uT>H*lf>*|KWP2hyb@p@$$?3b&|1)MI- zlY2U>296Oym9c6Q93CikZ*;R;DP4!6+(qYWB! z5_%l3Ldbvz>ghBhvYk$|I-4`e>V==4Ra~XUxcummm*3$I>*t&SMW4Hoi_@OLPYnCB z2TYQ;?E{8fg#Km!?eYKZme_aZqh=A29y{9Pf7h$?-0S#V0pSlKS+( zqqj-;yOfQ;VIul>@BJ;SslU33h58#!rlAB$86-Mj);#fIpuTya0e@l79f`o?zy8jW z+C_QKj8~mJ36_7rH>n7irU$}26_1?g{&bKAa?SsF75D+EEQ7XS%}wI@_U>`BCW4Eey=hVK5FHQ5CKrfoZDu*Maz*FNeNKjV;Rg zCUq_K*V71C_01kfERiLEu4sX?9kyJnBs6FczDb!eCY>k{4v3;k?`GcZ83W{L^@jkl z_Fkqo1<;Xf$>MKPCGX&ivE~+a>KjFylV4ixm}(Kj%ZuJ)YQiusg;C6w-9D)oobT&D zcue9iEltT_e-B^!m0%7Y;H@5H|HgOloe7<=9TdTW?8|GZ)9G<)66t}*rUl0Wwkt!)R%sO}BEdAW?!<)tH>u?rAIgm86mEIAf;8)3V>sJE zJ@bMSwhCIl;{KM@e>E7^o&X1z+RnebKL3@q{CDo%O{2)fCRL15GJsV8J0RNjMi(py zg712|_}+fVB;5nD$^@aGB|onX`^EC4Lima=4+K}Onsa9EL5%rUr-@4d_r`7hi#1o{yAHupSsiJ2`!Gvr@Z8@M9+!Xpohci zV#`v$H}*3yALcqX&`-Rxkda~8$~N_p(N$~3Jpgxe4lyqARj_Wi9*SFg$i%SPBqg68 z=N|ye`L8%<8+DiJb8gzsq(i&!VgDfQs=`&zd%FJN-BZ9G7CPz*zxBL_b^@N%x_|WC z73Z1kaf|5kd0t(c>%kp~ELihDGb8eST>b%#rHEw)XNc>zd>rgHzF?HkP9X zHDx>O#K(z%Kh;IJ17E5|_q)rqxut%7nfAk+Fd3jf>v#hCif&if)ARjPNi{e=0-eEc zLtRl~uDllGW}^r_ol`fWzVW`sa7~QQlb!Q)(S4SaO?Ac{AI6+cP9>~%<#s^jwkxB6 zbezrELBBK&Fw8~vJV=(BP|OvEe1#Wm6df#&cOP?Jm=e=KzCk8UzZ`o*nyKK z=QsQ1JlOMgM2D0$gLRK8TcJN7u=^{gF>8);vYUOTUJHzO)JUwW?L6=Q`XpVX#RzxtVJ(+rEpINg2Il2;hSPEB|Dhl_ZBc&EQGD*#t+N`=jLhcmDi?iu4zo;Eo%( z0VG;)Y*z=;xZ_OG=t20UmAfQ$);P;P2T-93)sU4F%dwMi(R#R-$er!7C_{<~=U;E|`kGC=6mFJ5!eQc&~$TSk-ibZ{sT2FYZ+5*t6 z=ip4jX23e~p=$7w?n4)+wV;rwRi0LZtBx#r&Y|qCY&A;ryN?&lI8+|5)I2JRDj^ht zC8wZsh$2i5WlZ%>2T6Q75dtr880Il#9laH7(_d2Qbr|t@_T@V392vGVevMeVFR4_? z*2LT z9cVvgQO<@!02kjR(HrCBv0%vACB&4;Y~>?lhb3HNf-3!Icg-6zVsTbprtar047 zk~bxb+X?qWwioM3H$f+L0Yv)7Q{k^UwZj-J^(3 zUdbD(HCQT3CL}@k)Hh}XJm~dquL;STnJdwy*CD-;(?ftLa1-(7Hg{kuy%1+7}o6V#Me6uiE>}fnQ-G z7c?1Ylj!W^|EvO^DVmaR{EGtrCzwG-4})5*+1D(4iLF4Q02k@fH`CkSHic1FlCyId zfN^wYYN_Sed)+iY@hgmx?<84E?Sz&fyiaNdKOS&0uRLElxRY?4;6WLjXC3>KbLHy! zCmET+=DmY7iveT4{_~$>qKD{tgq%PD{^h0flD8W#2?R}2GfjDT9aDH1 z3TD0`mn_h?;xAGDWS|V?3qQ88Hxy1>eB8Ha$);PWX1ih!4Cmc;I_gLKOhi{m_Fvf2PY@A3d;+=|x@^R+(y!OHaSv&4s1j;a1R3ky6) z$pr!C&%I~s7c4RRD?~&Zn#q>aOqC~a{$W?$gKoe^%i|TzQWU}roY2$NxN5Lpd~gMg zdynHRnFnM)KpiEj6O3G#4S209J)boNry|`Zu*F6F{ZYM>DrEUnyF5oO7f198naho) z*b7HshcUQYpHWBTQ^?uqGDChAn*?}wLS1lp+!qQ6U5yz+6@G93o&5bu`MwXCkx>=! zE??!q@7bF~;ZW81(uJIo1?JHwZZ%`ZMb5h!Ywfv{BIO?DpiyIr3wKNgl&PMnC(r(Y z!*d_Pg@!1|agRdn!FBk-1{h$m6XAXETqaW3Dvt%61FeEGdKTUxLM;JGTO+iE<^s_f zd~OgqE9Mq7d3wtU#bO3oITB`3_!S6*Z(E^3RA8Ls6b}V(XC_GK}P=b|B6-pE4bEw zzt?n~0bO86josx1fV{Kj(+pwiO~fFDP+sT|E_sJ?%D0i40@7V1N!QM*onHs|J&Kx?(uYnLNdpEbQp~}Y5ru>Rr<$-Y&)LO?{#5DBuQnu9>k2F z|50JM&{9$#!J0~8?EEI>mHf3bwExj>ojKFrFe`RtjHM`PXol&fbo2g}v=iVR{`;Wg zpL=oFWDtP)l?Lo!e09N>XfW_C?yKOYV*GKn7h7nn(d<>u%z_2rdHX?x0dHpW%uOw` z&S%HIwDquT2)+Q#LH6*)xX@_0CWVVYW%4Vm2bI@>9d}@QX_KnH!{9;s0PPG?*R2si zT&k{rF71eeQf!Q^cl7XH*K$)xg;HyCFy^AZLD}fe1f%Ga>*a{iMi1`vBpW|q-iF@* zQ=TLaGo69T<`s*_tU6s34Bol>?>|R6HTba1v`4tK?O&do)3zoMyz@{Z^m<`^(-}oGj{D~1D-Q=pr_4QuC~uj< zt8DavJIEntDL?1gpxi>qIps^X5F`k`PBu5Pm*#wc3=3eoSaB+psI-- zS^P%#M_rCV%JdYHBm{2f=*lE9fH_z(Mx!}~; zv`ZJPd(Ck3Gx)Gdg)r7gTqAJza0gmaq8yDq)2o44#vqEweKW8bDMD3r!ah>J4WfitDvQS!`Xf(=I8W#N54eYZ|5X}}m0@9xO` zq0YquN7BM9@=blt;x03d zqm$&;Ct__dBYRQ~tAy!3KSmF!qMMNHIa(pu!3R1&fj5XrN1@QmKDJIgfuh?|-~ts*o__UM;^q-hb`J3b_KohJk^R5V9U2-gR1y9R zy0yR4;6gM1F19c`*bAihHa>xpSn?qYZ~fxmbn1VYYgzEvArPhh|BnxMeh28n3=>3P zx87T5t=uoP=51syB&j&k*M&lvO3K}Cd%VW^UtNZP?FjIJm@8u73-z>P=qtaV#_rt( zB<}Fks_0APjb3|+RK}$yfN&N8z_aT~p%#`$^Ke&YfJ8+WODujK?~$Lf&6}gxG!#`% zxlfq~ZVF^dISB9Eb64U7YcGQLb*crN8n?Ny!f#R~3#N%QmfKHwoIYc*#g9hWZeckl zVB7V6HD_*TR1sQa_<)muPN3C7fqzBf3d{ zTBr#A7Ib=w6wo6QS(lkWpf+?6GXf<|m67cufjUZi_-krJr>rQ;e~NQG73yNx%{DiD}cfFA5Fm4N4EpHQ*}fviiDc`odk~j7sB5%@K$EOAn%%@M%r{^pO<@i3 zy^>4ujG~`8zQ3#-G1fllBSpH~11&|Ru7HQig zVU$m=e=dG4REU!=Md>K83-WUN2xs#TEiGB9Jf#kCA zL;{vw&F(pCi4w+0<_Z&Ws}Y9l3nOCdMqpfR5j5(){s!j^_61`=j%%S-b{B+hR^Eb; zH~MmJ4L<;hSf({ovpaI$9>7K^8I_qfr@4JWtK%r*2)%5$a4ua)uj2}j&l=7_8F!+T zN*@4vF22*+-A@6bjce95}U8t!e8>lT&p`{YbTd7yMnM{EZkI-hwqs46z z&AH}LQIP*4wa)oz(}sL)*vwxJAMGhlmKEH02Jpw^txW$B9ROSE?{*78YA7F^K1PnFsx9TpzRbs)tQocwd-gIm2+qP$uH1*Y$MPYIHL^46?B~ zUuq{Yz0zn(DWH48t2Fj#zf0)|x>MKIG{=LolLivMTaL8-zfk>375V~sRk|t}To3mP zOh1RSx9-o7&wz&EHhQTv8BEDy>^@$v9ekD=xAvZ~k^D6&yUxN)Y<7_VzEeZtDyBsJ z2%zJZj%Ce{+fZme{-DM=S|2X;(YCUClTRM$cXK-nN$+b>UL!GQq0CO^Hqi4!^j~m>cli@o$~|Ya2wUNM18z&laZ}+b}{P~T@8B$U0hT{K(Bon zR>^B1;#TX%SE&0`T`^D-2QvnY%XAi>TD!B9-BDgy<6|=&-KpG_c=W{W0{%4nZLZ{? ze%ca00xIh+zWfx+M&##sRqVZ<#lcj)P+K|5(8v*VU5Bc|~3gwV=6B|C1CvD<^4Q%HTU2 zZ}FsvzM&_}%amB!1=wb?Pp|&eUvXwPO_Df-!c(^TI{a3Tf2M& z=mL?-uz2R|yX~jUt=mv;S<^&X0={%-Bk-a=O@kV=;PeXR_~ntx8`ma&>deAVQf0zV zR-(3d6jGH>cbXc!t;g#0%l#b!H=T-j=S;V%1{mPx7em;+2y)SnAT#_pqQ4c4HTgkQ z{y;fC0f9;t5+j(Nyw1u)A^7cu4Z!q74@qTAFVjB>gt(e;fFEO+4}O71NRnhHZQpBQ zXP`@br_&5PziGbrUSBY~%8q&W1kC{p(_*g%Gi8}rl8=2qsdTNkC12l_x74-7voGaN zaB}4-251aOO}s|VoFw#mo6R=Oo!*Ywm~=t19Cw9LZ-0`>3j-ugdRYE@{xELAbnM8k zZ1#4W;Mg>MWeJ?Xk5GwZ*@;xkaQW;y6mm~&``DN)3C~fNiSHUeD}yeR!53g%>^3IP zw15XI_&@C%H_Ve?u;Rs7^IQIh0m>2e9p(1ZCyzDhCJyuEs4oibpp@cg)9Yv}-6b2* ztLZn%6P*ASP!Ci%9A*+RfsH>u~4rN>+nRTB;6f$pU z6%d9!t@HHS4aZ&2<_t`-nD9>;h&r*%J(QRU9wlh(FVQO*bMk%lDs1|AY}IwLm+j`2 zA-mC2mKZCr*r??Qh2O~ac=ozJfn+$=R0gcF^_QnqBn>I}_eH@3Zg$RH&IbCtcSITd zQ=vX`BLQ}Fq%Ui_YOG5d7K=5HtQB|NpyWWp%Tegcz3)}J3UftnovlD3Yh6-6uTeO} znlf5v`I#x)?>=w9k|H!^Eory0YN=Qk!1OC!lWjkP|Ck@_9c(cmoYi3Q z@IGbh)V!2%N+N)BFT?1{>>_r0V5pYAU2)+BGisQFBd?D@_c%L8=MMsTuc;bR zH~F9DE$F=ab(&6+ya(ozCyn~TydNKOCIEUdFS25`_XS{(A^uDgKnLc6_;}M1p@5lU z+$7}IX(Z%1)pV>={=l6T#6&wiyv`u!gr2mt35rwo+fNxWfNX zAUSKWyldZUu}mW@G=&ir?oE6#-k?Cdw;kW%_zo*)=Gi9})SK<@39YJemh8rtY6G*& z{+ER5zN)+lRuM?@$pQ@ri9RTVi6WzW+9p35C|5rb5DPBaCahT_X4Nr~?JRVad)KId zA_2qqpyKF~L4~q%Zg{0y-H;7>wj`H5^W|o#savKU?Aw^GbLN5Aj3fZh!T_!`z-M!C z9m~3bsgynfqB4ahaA*4jjfG4AR&^%@QO2xiiDUq*A|k)GxFCjDyPnzgYdq?{hw;$jN zwthg>u;dxJI&qxrxdGNFaTBQc3l8I{Y}Xt>9JzUEh$)@}e1#R*5e6rrx)F%$j6K4F zpssup0bxsY2IFLqsTW2`NiFyX#)?(rPm9*{#3;Lbm?Q+kLb5f`#PIQzOH3hymYK9p ze;w94u)UVw>z2P?bWwJ5dr~zuB}M)&BfGcv!3=l^^BN(LG0ed;W(YklW4G{ymjH5> zNnQ;XvTF-J0EqHtDY_WD4PRKqScEQUBpz?zuiddeav_WU%(C|h&ASl*QotH~+c=nc z5T>hba(vYPaU173J#v~McR{Bq!r`&tv}awijGOD48Ro5q^Eo9u623{1mkZ=9XR#&V zIFaT0Up^G9aSC|azft4f=4PWoFF{R!8&xPoMnrY)k?4C9?ZS)$PUd`SxZ6K^k?jE4 zxg(o7fw&gEO8z0f6X;b%D~~tq&`&XDYaMH~Q}o~xF=zC0V2KFH;Kjy8L63U}<Ee&nXE*M7gu2-0H1foc@>oFw|=LD%cuxu)tBMi%C?3yXAB0cTCP7T~@U+X^KjU zo8+f#J}R;7goTz%WGt`(njz?X8os|~=B!K{`k|;Y2ObdNf7#10lC-{ikbj^TXG4g8aw)2-_ z|0m2N#mI+q>B1CJ|AedLC!BkRGR*E~Xc%WO%A)%)#`D&yz9TC@HItIpm`^F?WXNicF2ssd%v%Ak0vR}{+3(+v=J-9|7y((C1OX^oWOC-r!`gT?Oi>Ba$4q{v@ zjWKZlYT^m65`l8E5ax5h)^miV+uEI`R(Y?mwf-iR*s?wTS$2)Zxz<8gEFIs`f|r6t zHXmdt=)CPcqC2CRE(-pI4OwD@;oT)})CDuqC7)VYDz~u+7MVCjVyQ0QwN!4zgw01EsSEx(bbhizSU0EeFgznodreM_Se8vgpmD!Tu&R zP)N`9dEEqE8kIE`xfeYEGY4gAd5&o$*OWybZ9?tIc9oK4pQu4g79Tt~>0?X}sz|7) z9w)y1ske$qMaaiRq;wI{D*Uu)UcA>!XKxu=wmcy>`ngxNVIo;k{7ot^nV~9&k6tDa zy57Wu-B~Lw97}c0MN2|TO;epr?HqskLUHu?I}I4}BLE>j`)dx=zw-Zc9w~meTJqtSzdhbuo!I}N_ z^EWAH8a2>z&go1hQkx=IPOCxO`K1j39 z%;0-Jh}JL{ljq*)?Yn&F^qH8fTt*t)HFyQM{jh{w%oijUnL~UHWRpHDiv3lCb`PGg zwj6*240%96OIADLD@BLWH^rqV6@L)<7>!;4a!QHP`^SZAZ=Sn-W%}jOmyr(# zwA{B_7$o<@*}$7V`#mTPASdPu>PQ4Kf^x%P3pwB;x+TdY^4xd*!{kcsE*{K$rp!cXi_^xc!q^+ za|Io(wY<4;%%lPMLLIu-Q=$&_^Vcm7r7Bt$Zxm?V?h8+5)oLn+6C%3!*Nf0y&HU6; zCpXmq_bs(XGjcLWiREm60<761zmJ&ouv4J!dpKMf`t>g&r*Bee?x}m&m9PGPHf`&0 z5^tvIznZoe5bv}zRJ*d7i}5e4I4`VPZMJ7vXLmd{Isur_Z-8o6MtlX~ii}F=i^99^ zFdaNzxMoWX4+Q6>4=~Q44}u;Y^kbtdPlzO!0QSm$$gVZrQ1R7HGt$% z=)>{kDw6rk0*uAJz-k#4n_;n81Z5kV#+MO(T^-y~OQak{Ph)S{UB6J~ksx$SxS+q6_F@4nEoiYd$NiC$n>!QCc$Mn45A@i?VfsIsS2vbrdze8Cv#W>in^>m@fEwofr$u)9*g_BtRS@r~+9 zYUnyZM%G&F?ypKF?}o{Fx60^FsL~hp3Bui{onxIqYu+xPCjR&;P^pMDV2RJ?NOmEt zF2XSE0PM4uPe>^jvi&x18<32VYz^fe*@vlMweLyn5A`jZ3t0 zuA=X;!!y1%^T6n&hd*LB$cs4lL`0&7I<;B7?Z9y@D2*n zR|VOMv%JC~PEPj2Q*HTUhZcxg!|u-y$tK0g^ zJ(2JQbX%bkFo|`xCq!JK3W|^$Jwk(gNA6d_D(+sD(FrlDm@q$k3gn|YPWxQmBOLWP3YU;qGPbVKT*5|d!at-M|8yJ;y@n?dY$bK zib7r1^%c>oWkT4Y=2O2iblpnR@g&f1u7qcWf%1~?ar!@L1kTo9%oz8zq z5}D`o+_n{aso*bH6I5JRdLmMRxj5+d^w}C0ECO&0B#c|Fz_%u3N1Fb*E(wTdMzx9X z!+GKw=Shv0C;X(+npTKk&|An5X_CJ~+{tj}nSs$g4P&{bE(5iN055Y+@_Aw7q)-;y zksoG_#o7CRD6^L8nPByRz(8l{>taDc)tWOz!HTxDLWbe6X4;mr;>`8Bk|aUWZT)jV zQoGPVn|W(OQcW%v(^reohoeW9xZ`eq)WuJ6UPuYo=9G>@+fal zfk%Bz69=9Pb-ks0hs)z170$-^_AEzkk?Z7?xx@S`83glaGzrU{Wq@d71^7Du42wL8 za#Ru+r?}7N` zTBwA7QeFp4h)4#?T+XVQ+mr#KLxh$db!fV&haxy4acQSfMRR+ZH@A=I%Xj55Cf`|T zWZ9Dt1GQ4uE5%DC_cq3nN1>10RI)7TARKQ?z?ONAC`B&5=AhwZwlAxXQGwhFRpS?Y z@JnCOp?`x67aaEeLTRgaEDkn^g>Hl8aT&y>Sy=b_fA&8hNcv%6zuc4zy7tCvyme+G z5Tl4MgEj7-KIuObrZS*WvKk0l3PLGJ#Pt(--yXh}+s~$;M)nTu!3@5EwsD98DCY3hj)-c?Z0e ziH$o1Xj?9LI~{L_gL~5S7NUp1o4Sr_AVy%u+LA(su%=Yud9H`!$LPS;=In^(IiB1z zIC*CCxyz>up<+9yO557Kr>5P#CJJ>T&-k1@>>u6&buoy-qk3SJn@sStM)j;ke*V&i zIh0Im%~dXpf^vUNwZR%>$F(e>k$C54sM~4)3>UtV2Tqh#f?nIw8?;xh8~a(l6B>xt zAQ6d20lY_906Kh4)sXNCNG^jLYuQ7U6fBW4aBTNtQzxFh*mi@bSj(<@^>mASJG!QP zXGy1OpVTFVNp5qJm|PECstIj{Z)#ybDv_+KIiDhpw{@*-8?Zf~%X$lUT?f3NB12RI z?_thJTMp}+1gG4pbm475j|Vw+#V>UlV?N_5K^GXeh`?d2xu0CG@6crem3vu2gbO z_l`(fS2r7Ep+~GT+TMy)@B{reqM2FpR%5{t`hvLUn%Qrd8ws6&<$}-80M2hfIpN11E+)mk9H?8>UHR+=StEeE~PRVx9H8x)a`vCylG1qj(D{5Y8L zZnotC;ibe+VI~2ezrGt&2S{X8;0TyYAg|yM6 z3z^z*`ixo12vMB|I+4S(wq5(=YaC2008$XWaqCQGxWo4YGYjLNhcBIoX z^}RS}rg>{Cc0fLgVMaJ#j`g;R2A%$xek$dD)Z6GjFEd}tSvi5-0z2JJmHq&4n!6jj za|LRV;T>e7D)jBZ>Mn7}jNKv-oYs1Xa1>WQsP>IQS7hV!>wwmidzw+Eyd@l84sfag zukERF!w2c@IR=u2NPk!2$7psraWVGP&>KYd`Gw!4M)f33lde4GofTB3cnu&db;K6L zCBJamzkwQI1mKj&5}v%AosOSIao2jw=tTFc^@5J(U;~|oh$NNqe!h3Pdy8t9jDXM$ z`USA?Ce_^>|2%!M{^>!-?w@j}@5%u9Zj6X*W24K#gakNnl(ZF<2e`CRs2n%ZO7(GH zKk-Uv>`+h5a=3^9IV}>{0=D8Fjg1dJxhW4Hu5&0PYfIe0yV!$0LeBxgWyNv?=FI_S zr5!-_HdfVtNh-bEgl6g$-HkX0Y_HqK+1H?AuXCisR1zD(7Z_BO;^(f$t{5*-2!7}r zP*4`z1Jk#fyJ&RV#!J?ML4twr8NrP+{UQ1q#2_syZj?o%#q9hh$3#=WkLehL{T<-g6YcU(8$O6j7czaq_3wDC2~R2p@+JbR4gPgoi1C zASXReZc#A;^O$2dloag?jBtBUOU&2Q(HSaceqztVH&d1Q-RzJ_GNJQ`VwA59*C8@| zBxAAVuX<^|E?D`O9hu@qFc!^zL}-)7O(8HhW|@1BnuxM+{FSTkL+&n9JqZmt?u_(8SrHFpQ^c6iXpDa0H~Q{^uuMd#^~^02i~98i+5+1XDt5x`4iV zQ`|byyj(D9%PphbSR8dW<^r=oK>5mCDY|AI(e1fD;O4?@w3BE{4 zVoH@RgM{QIUgXyzTZXsK#;tF*q%D68I*u;Wk3DWtUYudRCo~`8f6Qj`lJ2IdFnXG& zcE1r#I)k0vW)1*=1n{i`Ey{6w{aS;l59@>k(=ZUZ%CXlJLvsa4+ayC8M}{Uf-&$%rWZS2yqE zQUv7B51CNF=`(aslJTA?4>RZ`0h~u|Lii4JZf#pEq1+b|_ZCLtjNY>ehgrAUw9(-~ zNNBFXkXN`J1{Z%6$&9XrG@`~Z(it$_Wj<)7&50FqP+7`*h0b_hfuGIc;Z5@&ifj(Q z4EpeOwL>Be13$1g7LX4~=HRvI2)QK6J1Uy?a8!LLu>C`c;sr3N?8Rl}BPF?R4);Ig z7Gzy(pA4^oMx7Z7x?;xQ$;W`-O)d*<=l}`@0VT=|u6mO4l&{fX2>|vp@ z#%0lz5U^Gf>05ytYL)+wpN_1&kWT7_Bb1*OZh6zBKGEG<1?zgTy0bwsCYE?!mn;CRiN=WK&e| z6&M7(H-*Vb2(ieUxMcFkj#C<0@8DEV9eP|jo3K4g&4kE{jO~oCjx888Rv#U?6;AmA z#M+XR2$>%^TqI`P2BtIl4O;#NCw9o`XN~{B*Y^S*fTSmK4$8!eTotj(*ynFj@(6?* zQ3qf;{MfiVaJWOH0R{$+^Fj!v@G=y$JKiat2}e^Llcc<&(K%QFI+sV7ORt-HI0F)| z9jKEJX#bQJtF|XnyP~lyq(nsE^@F_rC&t|<=1Q#`6nbTyfIV=UTaFL>a%6LY z*T$$7N3_dFV|!hzfs<|0*Qnyj-SjQVW?6?NVdNy!kBsG_qj9TZH?2Gg{L?j_Ogv+W zJ(;Q*Q-t?7?{9he&ya^^@A{mb3zy|Oud_Y$=$j(gkdYRy;QRu=ip*Ms-$V)Z(f zJfS4lej(Q?;pna?FRR9wgo^c}s#=v>SZ-#0vtvpAisfOJ)cMOC@R|SY_x=a>U7PWc zmM`Ds|FoFx%I*S*&LVxvFEowp1`S-LZOB)tj6FlTw{j$`X`NVA8)18`Xt%Dw1^&GN zcWrg?9><$nfzMSG(JqwZTUyK1xJJwdYjt1Y6WZp)DA>h3Md^wowzq`lox$-_ne^)N z9v%=8x}nn9mkpe7cZZk8t*zf{koF`qJ0eHlE{m=X7oEhnQO$W^IPx#TsggX#+;*$> zeKs~n^XToDbrmfIn&a`{uG zu}e#eJgwWE74$Tn39{Bce3o(pnmutal7iej?PxibxMfu7AtQYTB69HMJyswNtp>-B z#RS}JRJMXjv93iW(2BD!F&4cckk!fW{8i*PiC5DVv6NPgAYau|jisE;OsDad{IBIF zU1JslK|%!<#y(%O0u0E!{r{MI_qZ7MzVExWEJ7G0(QZ%)Nj9aZ=2)~8S{Z~;nng&Z zMv|tQnS*Gf-K(+tpT7#`d~8`n?&goMN15nu~aisCSFv= zsxAu_x|S+A-#bvpJmK@TS8p^u(^kA7!J1aD>=)!jbV5)wqlmi^Xf?krA znf1*6Do@dS9E2+p8DDFa;V|3lizBv`>$$cJ+ciyE_N{Gtq+CU9*V`k46srRzo12A& z;%Cu(m*@`#QfH@UgD$~o8Xutw!u%^N5fP>PygYlzsCHtZ)bCT?FepB9A1jaT+{*FV?>+TJ zt{%E;oQ0%eOJB98ua~n!_6F$1OT6$-<@5<9>eRyWF-5inhJv;wp&%}TS7Mb4X%1_y z#$3VGTTUNK;r6uUnC(1t*rXW1i0fot<;syEHgOlExu;+>5`=;l5p0NyYR;2Ta z6=H(x*K&?u5HYjcywud{flsO4KwQxseyWetsWy|*Y4{DLK&*KFB<$0hR|JP}5z{m~ z-npWdA!nCudB7>JJzk4XXOD6es{wL5Kaac+45w)N@$jqda}a7Hxg#w0>GOJv?hghx zhP}t=?ZAsqZ%bBF0RN$WzMOS*>3iF&q^`EiHbS< z@*l)C>@bBNF(`ZZ0Zi>V6BGUQ#z1 zV4~{rkBwEp%y|7s2NY`}$r^j=eBHorkL1*cF}K_D8*s(qi(hd|Jkec<`b%%B5wn=E zTdDc0`C>XCzI_d?1FrH@ zScxvt?@lW*PA7^>ob}FCD$2X&_p<`ZO{g7u3q{OPBR{`Pr1=+S>)3QgANI}0USBKc zN%qS@X3DaBV5UNpgwzLa-U5kUkEBRoVBqN>&K|SzH|#47j!>+ZxiBQJxM?@5)24r# zYAR<(DQxP+56L?DYa+C6Kx5;?vY9=D0>cK;gCc-Rr?Y+RPZfiWFpMr((`Iin859yM z(GGSV<0_WBOJ?7QXGgOnw0nA%&An~<*TN=zSMJ%%^g_IO1EU&pb+QMLB=E~1!GfHP zte{B)oPXXdTi(;!2aB905dFYt=)x;Ep{odzq-XG!ruOg+w|pJAvR3+T#7%YidBi{R z{E{Rt<~U)=yFEcK6{B&HA!k7hQXMp)SUpuEBgDZVxmo1~8b9S39tDO|7bx|!tDNHi zvbt~yToh5O2CLNpURjl2-IPst^L$tT4+gh8N*_Oy?~|4j!ObX}nPH8F$$xa|@@%78 zBc-y4FjTi|;~?XLzfN3N+>7g~hm}q%wDz3B>uBZH*Xx}w>q6L|pM$u|FI2grjYLFV^ry-xpf#ajgFw7a zR_2sSts61J*U4j3%94qY8HVZHTF6TQ16*K9#Huz5AT81bK_ea`|K4$4|Dw1NI;_MS zHVnPndpd^f?Qh?G$Y2}{5|xPP-|Xk6t^ZvgYTZ8&6h+g+lwpAE#Avd5-+pF|OtYq+ zQ6Bu;pfy;C0qzEtA&_hhqiVD9|BAqgo@PkcgBE|PY%Ea&$Jy2EPn>;(1!r00WrSTo zJ_gE$^Q1*&a2{3nlDSMWJk!hl?95?_yc}D+MR%&<(l}^3pEF!p3Nk*><^@bWhWs$v zwi-1Mxkc;cXDJ^GZk`Dpvw5#vN?Cp85&!zcNwPp6#;o@BDZabA*vGCJxaw#& z#t3C_Y)A`T^h;yMmad=#lF40oW-_S{w-Py-N7h1G{rG^O<2mUm%X-vlwu~G2V|i|^ z&a5e0j{wHS!o)eaxb}6{ z>_>1%JOXTS`W*K{^G}th^sR&MPnNU9@R7n&+Gl17D@v0v@#6>QX+M!V9|{GsX!v`T z+^G`Pj{9OcU0qV_0M8^ZWkPMN$ENeJNVyEF4Et?Pp$0paujRY}Vi@wmrkSP34+@*d zrk`gO-;^e;T4xl6zLfc#O1mDDfW3Uw83>=~cY;oN11y6MYgcutq1+SXpl_g2uAp(b zx8A%q{pM-qH-~3k>n|4{OHcD_0v&WOI%0&&5rcmE-s~E{%%f^2R%z*$j8b%;;5_o| zr4xi_drim61T>Jf=}s$6`KA%mN+N$;nev#E$Rz4BuxFc<*^p;rB(@N)4S~imYC|`{ zrxl({W|pXX^~U(c1#6*Je4N2&%fRjZ;B*CU_V)FCT!w$%aJ^%Vj8LBZ9<~Y&DC_xs z65u>0zxUYB3Lf1oKsEgAjN4&eCcN4j@M$F$rfH>< z;3+H?6D5BAK6~ad+dx;BBQ_R7cOj3Z*y?m0(dA^LxNW=3bBV8wH;B{FwG7d0t*>=s zVb_=Pc{^r3Ki!N8dOHPW7F!rp@CVuIm|*)uBCMo?CW%8b1hfT*_%=@Vw4W*TD_|pb zzV=i{q9GN6dP1=>QK1SF6Sztqi?OBQ6RVR!ZSP>AyvNQzMY&QL4_}2AQ@^dAJPl-E z9-WAw0TTFmuCh8qFe=|O=*?##d(>TuMXV^CE+8(tD4#Txw%AF_uilY5=S-hW%oO-) zE?p>x0zlKkx6s$J?}6h{QwCEF{0MKkB1b%8Vg%}Y-h^;X>>||E)n#xtB?0#6xGHCE zu??XZ_k&Ifa8470KG8hI(KsQ00Ue68hFMg@v z3tky*dgrsL^PNKKmiA)5b;KY`vAn8AD`G5P{!^EW;vhI@cN46_S2##wd;+En*w|Z) z8W`D1tN=cxs>)(ue1Z`0G>0bPFE{SthV$oHGD=yOv7MQy&WwDCm!6u~C|R|d##)fd z3RJwgzBk02dJ1j9zR6?BofQPoArSz7i|1Zzq#NYVGjBnMrxjLw#ieEIYlRu({A|%S zxmQg7ab?SI{;b92+exWBT9iA-dh<)yE3zzB_k*qEs;>hKCqgT8)Ji<>1d=FM8wxJZ z_mf1+8*Co;q4M*&QUfnJ0#b(3WWDbgj1{5+Z{fs4~4w9+WGN|(IiU_Ziu=%QZrhK zSA6=dH=tw@>GDeQY@RureB-}>b7)(ISLa5cs&`t_II@*g<@#8edc zBK!l`3i9733J*?OkrehpYQ!?a3~h>ua0Vt6t4&e0J3(@MG}r*pg$ZAT71uZFP0)9` zhVhmJ-vLJm-3?bnhDoUDSifm>!*LJd^<$Qq>HWwj%f<qljjBNHUfc=_8bqxs zjoP&rj$?1Liw=Qx!wS68!V@l92I2)ZnD;qZt3OAeI+ew=*K_6i*)5~|kcUMV5%{t0 z=)xiJB(5Y?2{)!&L&WDUFV2o92d2~)yVGtma=sMCETB{td^le=`s;9L` zH=P{Vi$N@1BsL;!C5?u~jGNgk>-mCT?xk&xG3t}=SCrXPpRsJM@p2Q;rviC(sE?Nz z!P_&N(C<%oIrJIz5S>QaSPLQE6RhYYW(~EIyZVOm_@q?`1*!_X>|?Gz0qskSA0s@W ziyVPwXj_E*)Z8?yvp9IN)4sIy-qlyTJ+5|BLU_($)#P1teu2)rw*KVT$>t~XI0{Gi zv&m+(YS5a}EXRm{4NgxEGJM>Z_Uv@t2I(1XgNx470pM=lEX z1Z9Q=@!S|FTyi(C_Q1S9U=fiMjl(MJ;|BQi?}9+88||k|&G){^6DKwsa0;pQET${y zhMBelNp3~D{^TpvP${SEqJsEq&&ch;)=|>!=qfSpnB5-j{+E5)+g`U4+hfcw*||yk zCER?t3Iq=GKO}yDMKsV)t28QXkQ*rqyZhABDBdFz$Q~m;l_pA-%zORK%*t}iOdb+; zBFglAX2V^vR7(*;KsM8=F^D%%cc0Tcm#i?LXl)~x73;56cuTbT5n~pjMpUg(ZsCGp zYPGT@aI~HYXLUTT&5mDegze75ZK*H3%Ggowe>KqT`Ozq+kyp&uNADZ1-Gl{|*TMmy z=2=BnMPfZ(lJKXCzfBlCT9K|p9!dKR{fRSU$j5(|SNy5+78>>A%W07*y7b6xP(g}M z)1N9K^)0DhwV@bZN`1`|3t2rL;}mf*>$pX~U(+W}D@|3-H1(p+ z^ExC6kw*eOV;X}wRdXt5TmMwvQ|kCA_tEnaB=4zK;=AeS-+(sazXWssZ|Noy{<16p zaNnGo7WnM=2hd%kBfn?m%RsdH6ZluC6Cy+xFE%xY7a?(tRg+f|$q5ZBE_V-a_nx3F z2X}`hP&4Dh_0FZ|$d8`(q@KNc;(>-6-RUeW@+2rC^^6nIbf~rzFqvTS+nj7FM`lx2 zp7Y$LQ<*?W*c_ENk=#5)_2HI1!cgyM%sY>HlHW&KcHJ=y>u$$8U}P=@uM2yY9K2 z<}7-&yR+=TRcUXRJ$_40-I)`PZrcx4BthKc1NVjj&1w(s8#q4*0W<`@jy4=pnJ z2pa1T^9E48Sh1W{-QYh-1EaJIl?nU9=(FmJdniHjvn`pM1M_RN3gX!1SY-1A8|Veh zce#S?3RXD!LrZb%ys;~BCUq~pWnr~BFI;t-x*TR7q8fd_jhlB<8`-Gw!8wBnslh-6$FMyLrzSXk4zhFJS$_KsItm>&5fu>M$xv#V&g#Y6C_=@1IG=K9$U z2$)0{&)mMPV4X!PWgh4K%qMkH*1)}lcyycS@s;KVaToW?pDMd4G>dQrRt^|TZRTKF zjZk06#J_Ppd-hU_aEcKR`CvOCdu2Y0myX+%hzGjEvI|15jj2$*g=*U75yDYw4R$$d zKqertUyyiLl_c1vruvnH^mb`M2HPOm`FF)J1S{Gvl#Dm^wwQz67s;Fe7{p%|ca{Y7 z-e62|4R1VmH*{8?IPq-a#zg)saQP8Qj>^ws8})8Ka|J5A+4wr5AGRmzWJf)6ig{RO zjH>O*`i{VJEo*HGuE)xXOiM8AC}Y)@2gLXh#+lz5qciB&Vzpjp*VnJ2^`YxOC|$I- z{Bq;i0qP*>e}s1Ve?rRqm)ELfFL=!QxHi+5^OB|U`L`y$Qk+2pRCxV8QpZkBFlq0I z#RWab0*mN{z?l#2ko2r;S?OT2(lV$lX?G=V)}K(o{So5*ah5RlgP7|o!T}Gw{ZN-u3T*Z4+m9A2jRp?*5x-);plstL$ez}^ts@_>Vb+{Tujz6r$liTE~M zF5XRZG-^lfd}`uckh4ro|3Hh0$q>WU^tI$;8}kLR7lfxWr$V~xxU8~PUR1Ss5xDWpN;xJ*wAZr2Sjg5p0Yl>=Ep^7sA z^Vu`i|G@bA?stj+Z4VA!p`8vmR}a4g~9cS)FhFSwf6piH<@s^u^Y@h?zjB0-7yDph`RZs@b{HT@;t$HJ~0*1)Y@>%Xgq2=THZ zy&^RaW}@J7iNW!WY(lr93Y9XJwFQL4x*sbpEiFzE2>8+U#>xTru9mf5wph`SS;mI9 z&UY*MFDPeM&~}CdYrjZHoTcqbMRByY)FX7IKgF{Mb)BQ;IE@Pb?-_&tGrmzSg)6d% zbQMwwS`OEiff&bK+{~LFG3Li-{YXA4@=4Em;gwq67_wd2{a&2L5lkr5o6*HZK)Pw< z7@mOzO%CWN?F3~!`G~W7$ZtBF^>ROI4{nRH47Y_XXk6v;eQ5T<;Kv+aHqla|BPMj@ zRw`~tI_39(S%3?+{Agz#F<(r5kw9pd;2x(2szjq7i>PP(6kk>N8LpO z=!!DEo<>(Ds>(`w6mLfwq_&)@hU z!*lNF6t}<1!`kSw0#F{-1>Wf6+`00wPpR`b@!y+0?gi8f^v(|8cK%nOGr5N;{~S38 z+^I_ba;FNE13+gUFx6T}4=&-}!cO9hS~$H_VD-4-A&8;gQnUYV^$0k`Ip|Z0*ISV8 z&$-2HY1z^G4<=?|5?fh-70}T8z_;Nki@%qF5YPm2BQFtj-#cvqJmV!6e8R!WD#b!@`a%xaTck25?&Fe3C38o&TVihZ?lNGuN8iK;yfxq(iBQ3DzE18yCX zA-6~CXSJ|3j?3^%*?t!vNSs_)6S~{&;C+NPmSbdV+_41byYGDFOR++Wh4phz=zprP zOh1p7uLEJU?Hq_bPKK>gnmUwl3|esZWd+iVqF$9{s%V3&MeUqCMhyfd#49&t1Ggs( z#6R7A;ysZRzVYKod>ojR3^x5h`|b<^$k()6VB%VMH1Q}iwnO0KaMZDB{~l|dL^lht zvus4bmIi+Pwdy_VV?24i&HjUuCvMfLmw&w|>h?x3CROLX-7_69Yp>UL-&gcfy1fdr z?VRMtS`;AC4*dwk=3r`1DNt+JHfdE)ru9^JCKr*XvyIQ-R=-a?7J3LMyn=e=;|=dv zd)pYZPJ<&ABN4@RVGB?64;-S`mmY|d_3S=*Mi;nYy-#2M?{J+0FjaVLE~)t!g~u`c z{r{8M!~f2l;=DWlXQ;-uxcIYPU|15HZd@U_%8=V`&AofQZy?%vcc#+=GJBLhN*6ct zS)lsBOVrb3ioGkYV34yOg(pe!o2kZ(upaq8mB$vh=qjyZZDitBjq zaM2UFq6qm@1!NA(;W1igI@ba8L4IwL5anB0W>#_I*QiPIWInwE!-s1zYrN=~(Qz{+ zFr4Ak6*u=_A8adCu>(W2x&kKV*vF|3DOtEBKBhC#enwMG*cbi5j$CFkySB<6@sNio zpl>sdPWZw${qF;Yr3I+$Tj5usUXm270jh?BH&JXeiv9kbty@<1e(!;m@Q)x)qyT4% z&>Qe~cQ$GyCIFPX?a^Y+iWKe5r=>fVFH>1NV=kQ!ZlPqPPV6sGt%;^U0;34w*Xc5w zM`qc0Damcuw2krf#FG=0?0ahto*(viib|9>Tcf-0yCmZaAna|0h2KjGjhHgH|AogeC6_68pT8AqYdtN;DVHekm*|~25Uk1O zevbfs15A`YP?ThLfi7(&@g5cn{R$KaeF_a80F^^gFQ;vmeQ~rs(V~5E_t0$G%!JFg z+ON40vW7kK$8~*|O}&h{I1t`fm{WIB8*z()W$b1VrH7u$o*lOc?`&oY9YhZ3qAYQ= zBwTbtZ=HyFXTn@}i*WqcmpH1QD|TeH%P5XHCLEQpZ1L_m_U(AP9Rw#Jr;V0?Ds;xO z3G`1DlOXySM!sBeSoy$bbU@4wA2$mL`LZD?ZD+ooF#Bwp>B_!`DdlX8+s@?YA&b)O z0Yj(w!aw?_BeWT_j*UaE?cCYJ=`qE=fa5gcGVJ*V)XX^+ZK;I5-G9Sh6vtJ77jCNj zpWqAr)3$>M0@`E$GU<0181=q5k(d&NK_qjwW}tgoVyoDM1dXp^%;wD55QB*=)_x2y zHd`nK#%7X#%e^lQ~DnV|MkaX5nqX@<4w(0)Z^o2?!<9mV8a-l*I*Dc=@@J@ z%I1&IH5I4cGT-ygoojxa@+G|W+UgCju3p~AoN}1*D5Ew&Z|LCmCBk8Q*&WsvK^~bC za)YWQta!K(T51T8Rlr4Qr%z2&Ge3Eqxv=^FXU|o780X>EcgaEHveuD{r~*;cN`4a2$83lmenCM- zU;&jRc{3*P{{u1L8==;IdU{-5=i?tD-6#>{3DG}k{#wMQK+x?bQiw{t)pRvE!`6>E|ySx-DVhfk0 zz9eyN!LER1cK3G}iFYqs8uTgvyO_F)bVmrq_$VNL>^4WI)1{3`i>X2V@BDf`oervG zmgo_JfbCn;M29`9#vy_hN9bWHfGEVtvb7RoQc4YzUGVuox@kjuY2w^E{&%LxR#dikyg()Z22Gq%%D_J7%9y&;w z0lYQrG5x{Sv5BYyXus={khxG+bOKaNurUykxT-Fj?Wd&kDY#QEaKWcx&Xt>!-IgC2 z#SpLg&?K3tPm$_D%JdR(n$g3HrI_fTFhXz^-RR)R*T@SQ$8%(RK;WVVPL(Hum5d{l z=Pn?@r%TXUxkmH)ZZ(}7&@Dzad>iy+u#wn&O~opCg=|5Nhu@1c?5!_>boJe2>&-Ne zubd$kSSL_5qa09^E`shTOgGYrMiDc3bB3?(m%-nCbU|q6RbHY@#qA|qDPLQg&Rw5n zU}guq0cbyby6V$01|iOsz2pPcuI7pUg3a$Ao)yoMOSD@u4re(HU=hm&riE~YmBL z@8_Y8PLLKVRu}SrVJ%aDJh*5iMfZiYsX=k%!|yyvpRsrfs5k#qF{%@CWpePB1BO(v zFjf?@3g~e-HPV2qcp%Cw$c%*C2#&KFIqc*#umdli(Y=cmvcFBXYSi^XQw>Z!>lD(a1;LzACCeB{rUwF4z~rXoZnI zE)urL9!ylyF@xx;HvLvpvptV}n@k^F__$_3#P}4xHdqPW+O?!g`}eQamkHJJHBmA8 zxYJ8Pt7J6p=wC8%-}?aEn`d36{F0ry1zORs{x_zQudZ@=*5BY_ga=+fY_g$DGs{A>5Kix{$Rn= zIO+tyhjsqEBsCU$B8rO!mleK1NiPG32%K}=(Q`Zqv`PzY%J2C7;rSLIvQmQe9W>s* zjK04IRA_gS{Xy&8PjLu5D;={AV5|xK9>k*@sPFR9F84k##-`55W|tt%_xpF{+OL&A zaw?xVEWgDuY`Pig}NqqtIg#TzPQp%ONA{DMBPvlpQ{*01LwW zNY2)2c}R#ANrDa=EM`@;Q;ehM2_9%imNRcvHk04*x+lbBnuE!Q5bJZBrI|xpYLKu$ zRW{)AfdlWDf`+uUUQpNqYfmrw%sAjpu{KuPC#z${`m?U~BEvx{erT^DD-yR8RJK+~ zAIzqt9M}RdHVy*T6X-UOv)=*C697N!vB83mD}lpiV*T-iEoZW%S@&=Ghk8ppzRi%P z;g~isB2mI*wlp~t$DjKVvLPLX%PSOIT5WVy4|!dS`BHa#k<0}Yohj+Z^D9-fnG~)Q zAwjuk`_3Bn)~v>Q`~yeUfedkvc5Cb&fuSUi(k!=9tP)?QiG(LatXi7-5Oq^A$B?*@ zOXVh(FQC+r6T!IwD`V(gk}bNZiWl7&hEXNF(ywsGcx5j2Qq)4gPxl8?%$fJRO3 z5WGSGy#V#*2c!$#ZYG-zap$Uj^GFlEX53+cq@~@z28%6M@uKVC*6%Zlus)MDj?e!M zm6CL(P=7)tPM0@XY8S9S&)X>_=IOf(Z_{F>KJJy zR=+8|1q@`X=GYEC9ILk+3CtLju_fW}`0|_4PDjo>A5@xc#|LS56F{c;mVwhl?i|XO12xkN&`h7$?P7mY@saVh5n0DltmIVD z-_AyPi0vaypTHHRNWol|-&gp>8D! zrmFSUDbvY#zZY&e>1E1J$`^PdO0FsC%NKDKD-tE^nxBeTVbin~u4mBx^?@o&z6a=} zsVf4ctzcC`ETd~QwUlXrST*aVeRW%MN6$5I(#T1Q<|zKCkkfQ+xZ*eHs-rC+i-_+yh!@=B!K*xP%3P0EkN92M*x$`uBemDj>ID-+ z^tW&gSj5}~^V1##!%^F;O<4hLk0eGN3Z37^go%XbSP?*BZt8+XcudS*C_-T&nyT8H zExCKVq^$aaP3q0*O2BX@Kxh>#av5`%L@J+>A)eBoPrGw33#gO`S>|<2Z-iFUreo zH`(NXIGl)BIs>*Vd$ceM!MKQObAkf1$L$|%l%6|ea6@lq1S=x25Cf09X2gj1tXfAs zq1^N+({bu-XJ=R(v3QRPXD)sCm4FynL_xmr8kZg~8Ks}byQdlAwP-4c6_Sl>ZAj#k zEVL`F6{W?by1JTogvUWirZ4SsW=vyQyr*!X5u2t{Cup$c8AXDEy0}W2v-M*9rSo4y zbK_d?$;n_b@+v(hhWN{p`S4vFMrc>zz=yt}&k-=1d12rWGdW6j4-m1hqZlOan$xt z(xq(UQR7b){PSB@d>-tZ$~i)>XxL-nJB$%+IWE^>3yY?v#UE{O;q@eb*aJo*GY99z6Gle^(;m1n|0td6Cyi zcaC6Jpxf>J_)5qjp!n^Z34l5J2Yfmp(c5=z57k&N6`9dOdb3a>cbK~!d zI((SkrguQr%U8OC^$;w1i|bn6)W6bFzM3%UEi9%@9N409NwJj5BZIRQ+Dg_(@PHLX z#ekTJyz3X2!mcp!mRDMDSVf|O%p;5{3ua^fH)|cJuZ32%+Vy1Yu3w8=$K9EQ%;MtWL}bJM z2I=DONW6%34mluHi=9`Ua;`S{<(aXmSN*lUjW)S&mGO|5RpWPKK@IEP=rqODWwMsd zEIU^pM|nR*cy?jOPTA9ZOJazW{AD5A<>1sS@5;0EFa>LDDQ>dyvz&hAF1ut(BYAT} z8GIPlfPZ6v7`5WWpDGu8Fx6V=$?p8l#)8!1lrQVG^*!R#F~D~FmALA|W)VXW_m2N@ z9QRF+cEhLb6ly-A^yVSNxJ@4IS5Io_oqcoSe#SeF3ug4)Ws>#ZOR|4=3>=tq49sq0 z&*{JZr+iAM057lGq8t254H3&S#d_XWQ-&?7@wqZYV@T#Pce!9qF4|v9r#F9^O0&`^b}W z&?ai5pnq+;~mr#^6=n_3n3yuY!GA6#q)pNY( z#PRaJUxi=g&ac6X{aCzgIzYamHL{5CQX`?7jk{BEXThfO%fgOw*t%AjpXL<7NRksS z8BKH_vM25ws$7vZK_|c!dVi|?o#QrA;XPD18%C}J+XQ$D?gx=~g92Nyb8~bXs|v3P z9-Ot$!1nRClxJv?HJ9?hq5xPC5C8Btjo5w`h+Qu=gI~n(Cgh8&6eAK_&{?%au%NMu z5S0s^h1d^7zDzYR&)6DYWTbGG!oJ8(%Ct9wa%opAnegY zkIuHzKnXZAq3;z-#Sx?HUyxwD_}OE>m#&@!4~H9Y&&3QZm{b`MpB(u9j2Slx#MI&3 zt%o+B?vlqPwSGX=&rd~}k6eyV+Ee@N@wT{6?TsEHEQdb2PwsVv&a|%}Db53(GSS26 zQ)*{Fx}T*AUj>yRp}*FE926!TDW2dY8iBV@C$CecvfLLcECh|K&kV}4N|uTprJQO= zi)wZS)&)z*ORemCpuDWxPa^>U&?DT))gGcbM~iY+HLpRI#F@5zxwD5 z?)6I;3$D+qzY?JdfZj2`dJ3X}g*!?gJkE@pVBSWn^y*etMvpN78^S2+Y+jJ!snx?D0%vIN*&(cgZ)nQLC|q2l{FwUU=zkZ8KkLvrP~_e!RYT z+s{8Gc5%QZ#vg)m`(EEIKi8Nb;wS~Ik|`S_$v(s%AOfJ!fQ9HLQo>UIqf>!Zri))c zqn6J|!TC^Cp?0QkZ3U%yPaQAkH8h) z(0QQmyae9^12C*eQ}cRwrIkYgKbk^cccYH+xjeG<1!LvwmRyGit|j&!*)uZw8Ma?c zK@j#jT#>Cq(yqnMi0EGqOPT1hXsq~A2SFL^0Fp6hP)4Z$j}b4ogFQD3x+q&2*CVWw z^;IhK0(}ZxW(KnLHzT(GlXyis4jTohsW(EV`}f0J-uYy zvD3Tv+n~TRhv^0qO`**NRS%Hc$*o9LY~Z=4*hkFh@=nHj zDkr+H2kPyZVMJAk$~~8@ZP>BvDd?>m*HB)`$zQlW7;p9Azbr3SdRJqa#M)TQX|Tve znVr)UG#EyV&a#503jg>x{ZttZ@e-)ugopk{#*`wrg$>)dHF{f{nj2iA4?67J{84Ie zlTvOC{{IWO4UUakJIM(Mp$5BHab{zNXGX5W*6p88^_-GkTV^>5&;STn*cCcIh#G~A z3c9JFKPL-}%rK9scN`8ho(vio!f*c|cGC>Mc3-p1_Q(}O&xw5KebO0t$0Yl&n!KEk z=>TP?Yi&5}5U38DmF*Yr_I+?+m!A^@_<5@Lf z1fVT$2WJouUw&+gsyD8>f-V;uJPM(0zS*EAuJB!EOjkxuL+t~S<*YXAeMIrR!{SSQ z)zFrn=ZR}nZ>Po0Og{>YRIltKoXowO+_qVscF)S{rsvsO^X;Wg1O1Rbb=ja+L^#fj zA2oaURPC-$}aWJ2ThnP=|GM`u^LUTSz%HcoKLoL8rJWeS@L)(q`z;enQI)~tKfMU%7i zQts|u+<_6oYplo)-#&3v8N<3Xf!NIe`V(gxZnnb&Zk?f~$vIP)ATgsRB|O7`F1qiX ze(@2EfN4W-382Cq10UHL@f5jBPAA$UG$E~UB>od5lwD|OeXl-t7RmYDqjl1Jk+Y;L z4>x)qL>pD*o%!6`dUBHgN5?3aG}ln#mYMoBY4%S z7LQ2zs-#97tIWk#2CAr`0Z-|oaYxlzcxo|m4h2T&#Gps)|BeEaI7|Kjztc*ZC)uKW zUKLT}_BY|SmS`J}FDd7bvbgEu{Imd#&jayPIX7>@2 zkaG!w=cUc&)%Fh_2O8-qgLT`7LSEk%G{dimInSEGwRPp5^#PmSoFsGb|B56NW_J<( zW#VKURxMxYP1mwMmkq{S3xSTb#qf0Eh1Dk-{iBpLWg3eY#|00syD2Cei0#?l6l}HD zQ$I@Pr<*$pwqaD%$Du7Wbm<`^C<95YM2$*Y%u1~4qeGI^w&pLml{62a)Ya6K{_)(nCan}IC(%2m6 zlE#}orL1J9w~wK&nrfsR?sS&u7KiS`R>)a^Mr))1^SGfs2BL@sl+&!`tlopI&`8&uD97bwv{()OCDsWoYea9g zBBz!S#=wfR67sKse{_rJ?Igup>xU%lmoj2=INoF12;33>*f#WTKORyVPnKrAq$!CAR53|;v7$^yHncg1*{PAKCv+y zE-VH&zQO_tA_no57kaR7yIlUD`TksIi6wkuVP!W?#CZ1A*;#iL6jCtvMcfX55ZSB{ zt15Jis&)Pa2a*)SVc2hy-QQjtEuk<2Crpce%!K$FvwJnV*X* zjHcLL3K0K=0t^^d)S}fGu7HBFdd`gKY1%PMijxk%d{uiGr2aFBl3U6rsIg)@vX5_L zTbZr`l)oohx2J?9P&&8%z9S}Bov;#IRj*QPcB5FIua_}b{j+Z|KNQ$qvuYpp>Mj3a zZ^gK5lYk|(scg-~OQk{NWVh_GH2*~oTXO34d+F^F=%QBwT8I9j67jPf4@1@+1t@P^ zDLZr_!23<_uXWicTM=*ZFJ%z?dK|a z7~PS{FOpA=xV~58`Uz|G`SBcY(-!CHAOLdX4?AO5LBHide1qcRHsRJ4c$-k!k-Q@s;s4K5K+Ckx@jBmZP zCdAYS`-TLM#>%&H(KfEen8Nh`VeP%6n%cs=VZ9ctL`6Umhzbfwi3$iR**(j+-nij=4bC?XLNQ4u53r9^53gh-9lKtd-#LJ24B+;?;D%)B$RX4W^e zzW0y2?h?y7=j^?o{ghux8%dx%)~4<41V(qNNl7wnBZGoh1kd{$WpRL;=xUxVsa!(I z{N&tb)^5Zem?E+>VDmj-kR#ji&MGji+rh*t z6nP!jfH2j+#qtJEC9iK2~7U)*>Qam;y=p29Y-C zX`K?{dF2${yeaLxs@m`8^;Z<{6^&Z)!6gO+iR+L%3Sc5a>KDJr>pJovIpS^*s!$C7 z&JkQAmKQ7XL<;Pgh$y3a-pOd_N$=~Go3GO)f0l_A%b$UYW#U2$ree5tNq)VL*6$@Wg3Yja(F;kW}sW zhicsbzR0(gu^+!982Tv#EvtpS%^?2qukbDEHj*Zv8lehjSmweLA18|xH@`G;I)5Sl z?R(?H7rTXGOR1&osyvLMFFVvI!})OO1`1WmTqT4`Y}x;8Q{%zWRtXnkOmQv96uEsC!m#KjB4!occqX_SpQeojZf0PzlE z%ASBkCay+H(UI#G2yMM<4!LW>{rF&cxC#6#Pc*}xA*>ui6(W9b){2<5y|E(r(X~T9 zNeAa7m==MRyL%8R7j0zswHWZwUxJeN`Z-T?AFD|B2unw4#Y7z$UU>R_52!L6T|NBc z)yNgTuf?rnIhlp+j0{{Gy-W?N#Qb8Ge+dAS-d61xE6_Ey*{4(2p9BOkcrKT4cSfv~ z_FsR$Kc}Y`XWL{_-k~G}<M{r=}0nr0wAIxJ#QFL1^jEvX?0zaoKpP<1vSwAO|Cddm%tx8m`0&2*oG5S&mIWQ20W}T8H^B68#o4EHa>; z=g^l=RNnz-^e2!4J;WJ({laS#Sn_zZ8+4QA@Drif#YU!>rLuq)3!e{%Kw3ldxz=dF zxwEyX=+c2l15T}2jXT%V_$VtYmX9WnB6JX;~i!wlO@Q8c!MR+_D+QjG?#fdj{F91k9fSw0feABBD!~(#Q zPm?_YL&bj`fvmKy0_`0y^qz2zD0Uw(;^&BB6;vR~YZ}4)3Oy)U8}P*PfPE9c?+I_* zMweO`ln@Vi(cn2gv_e+_whGUw1Wr$BA>L!W2d^hT>8xaHZ0~LngFf5BE<|6zRh-5fP}HV6JrDg^e4rj)kM6ZFHU2>ZApGT zC`pN@Dv)4J+ltt!w1=^~Z3saxe5CaspyJeZhY|2rJzbdQ|6{H&Yhcc3_e7c zign1|fw1tv_r|`-nWd)l;wI2G${zN#GI+icfqx|-1XB3OLo&G$mM3h!AD^BkKl~n= zcysWszCfom1>LE71gw4qQL^1(Vi5FIf3>o>=*u3$I#12*z|5S~drSAzR>$W>1t%9> z4V+d+SWUThFAWMYkpFW_LY$zLHlbhpgHJI=IVGydd?Dko;83!A;Fc=-?9~>(az(PW zhQ81qUEamrfL%-JZaVA1R+&|qa;7DzYzSPUKNBHh3z@gk?UZuhFRAcg!eFMhPLXrr z%w70X-c>6FA$`!E&^lppHgF62-pA)wpbjU_!GM!N!Ax8ASiSHuwK%AEYxi*^-Z!tp zrPRJ$iX9jszD|_u<)AJ0q1wAK-}e76bdQ1du-?>MSi1e+&;oqs)QRV)Z-;;TcSIWn zQrgKI0J;SoIe5i>xKMW<2c)+_q0;83^FFq{nKQ@vj}wx4+&PKmHqUEk%e_slOmliz zi$^qf3s=64Pwl9_N%oU!g+pO%#l72;@0HsqKcpGBrBn9pd3^t@wQR?Znm)UYJavbm z_);RWIfRxj!)GysAvxr8A6>T&zM8Fd? zNCw@fJn6(#ICUKjHLU2)zL6c{FntTVJ~rUNqXF}_i@%P@TC`@NL%{$!tT9CA#C;f& z0t2$Y3$6vYsxT%2q$?<;7Rrmi52g{IBhM@cfRG=p+W8MQNe$!cwsLRXNsy@)=SFi^ zSj*di;pIwRVgN_ zh^G1_JWJUC!WC=H>X$Qsc_vBF&2ecO*J|Xo7|ym^c5D4&vMp^XsvzW^D_Sbd0!%zI zuy4G>Jv?KJw+`-FJ@&n0&F$S9U)dw^Aj*YkE|3?0G5|Wej4*6lQ0V>f1+}EKd$ZRS z_fW^#6-0qg{C&7r@h4v6SKt#Da*|F&oxhm2@Fu+<^ZKY3xK@^81_oxmb3=#KZxUYU zy?1j%m%4%b7@U@HSf-DO1pZGdLFE~##T~tFcE064)1P8Qv*5B`bs1h~K_+oA_cgTy zX`$K0`_!B=w#4}VxE4_EQ|~2g)q9hNKTjS)M`8crvnG&+h5K6k86>?z(}i5prGu~~ zLg#YHv!k_At1Wc?MO^q9Vf=U0Pr^0{+)7DwqI5f81&48M=Rx$Ud)cR!7Twp`;M%rp z=zMLKQj(RBJ%9s`7>VDEjPY)<)&!*3#hh%#L9IV(R3|IlyfinJ2rXstY7hD=`^)9x zOHaQug{BA5Gm>Cx$o7IO{o&N&({Hn0MsDM(7dP=4ZB%qgF^|yh+*|dMn@&&(AlhU# zZ|CY==-O;V_Kg%0e}?i?-wwfx;fvn5Qval_jYa@+hRez>3EDOY>LcAVm`dClfIqzqN!h{-nF-g* zik`Td?4eqxQPugr6f}*>26@Ct(+#i@VQs+O!+l~WP01m9|4?f3A^KBr)5~c z`aiRRO4@hkwdK+RS$i@Ei!eiq-o8ClnX0iUu%N{VNG^jU%fq9u(&rW~UfYP^q7M6& zY)9-t%*_A|8zmO^0S&xu0HgeCQfRNgdq9TsY~#IeC=Na%>jsHq^bAWOkoHSbm7FG~ z!Th|%mYmr-#}+XCqgANghy&UKzyUfCFLO{OX?r6|M6)=7BF^aM_Gd>4Qj?O3Sbm|7 zuhaR05@S9F*#^|FZ7OMbX5n;`V#UcR8-e-|V~8;O_KISG`VCM78bUpp0Mi*}aojxx zxjQ*^QlQyIy-W+zeB(D`Dj4iac}GvCF6<|5L%&CvOYt1~`_NW*Ry}2u(m@1>{|5lc zaRQVAr{UH3b;Kdy7mfd%^9~_z{z+T=!U%~EeY9Cc`8y&{l)5-K$q-JmN_9*g)qEg z0JU6AGd>{6yE3&RIX-ts2=9?s>}Pq=RjB6?@k=oXN`SJ>IVtR;SvcepO?F&o?jDr3 zh(l;{{ zQ#A9?%LH5JtK*Uv`()lvRZ%$-f(Hp(8Av(qKN&>V{1}%Kdn4T%8E){o2}F-r zPDQqvl}X_Tu&MzspRILYoDo!JK5+Hg$?36C;(eRybcs=MVDHP{T|8#vRs2`WtGzp! zIs^KR++zx*mzv!cNxwctms$lpx34;8Am4$2jAOCfOU;VAXj=wDs?$0;17H{6=H;?C)+;zEU*jMJlvbtI zjB^-}&6b`)!Q8g26)2Su#xScq;-dP`IQPa~iR_tT9w4@@t1;bf;Y8S8&*(~B`)c-h z+zSyth*o^W?vD7LbS?Pnn}P$SzKD+0tvrYs%I9%1!S267t=6FC+#u${vQ@P}h2pp% zgjc1ho!>ZaQVTOg*Zg5)*DUay5%Ng*GVU&*r5&Pf1sLsBm+{!VOH$$sU8zM;^f$TJ z^en2V9|~S%rQ6$U?`7$QVdhee5bmDcekvb5kAILD`i;G*DzY+}j&%poJ5ncd#4J#@A zVC+Hr4`UBgsGK-P`soiCz)Eur-~rCWnuVjp2346Fxcs-q%(Yaova|4Bw^aB5N8si1 z0=|&W0&2)oQ%V*u2STbwpb1=^QXBvY$l5@K76C5zsL)Z`OjU`G{0^h9&xC}iPSaBu zJv@x~FeL+w-QbL1-W(>hnmNP~;D%khZEcN~r-J;vp({?>mIzl+Xs4kHeHcle`IjXA zd?w{zxWNi@P$kBqvcKjPF=dD4qpM}clZOUs?HEY(#wP8_i9W_sPz!Zk?{t^|({`o2 z-cX<>C<1&=g#8JK9+zZZeea+2NCthpie&CVj>dXm$O_=z6?RVMe zj8zX*q2Vja6NcU$$8YnBhnG*7zP^CeUviZ6YeYF4$0Yl>=jXORu`B=;Bc>TouO`S{!E9JF?Q{&-h!wAYo{| z_|gBoU7-AC&e{6(pa0b~V7J8HqhmOG-f@sh20i(2s1s?Vv{fsg>Krlq`BL{0Ae-sU zJ0T_>Idc6*O5Da>|1OjN?V;W&-``cr;!Z_FGta*fCQK>maH;O!q!|oi+~Z2)7S^fk z5^m{>v=|L5xg2sBh>b*-5)K4BFNeC@)wn5NgSxI&i@I-6AvWp;5M0&%O3s{};9kRNBi7NW- zS;mr^9v1AW6m&K=Pr?=#;#YF7YCbR!9y&f-5EDIwQmU@uR$chz=~Q_nICDsfy$$C$ zl;xwCU{Y)Li(9uMfIwM~Jn^eHPo4d&mQCYYdd&b`otIL`6RSp9!t{AH(kAz5p%OOFha|zQ5U867mCE1QthVn|*Bs-OynJ#Xtnhm;1NfXgR z63;4btWG`)I`nvctmG48=kwQZ0>tk|C3eytP;1QZc3rGLghRABV|RK%kZ>10qg80? zWaZ~K&K!P_BHk_beLMuz03e*<^ha39_oh1l0fE#D@XpK{_3sPTvzM?PSz>=xH%>4A zri;-oQx9wt?HleMv|>66&*MUO_`HT0%=+>H`D-q*=-0M6(&X~Jf(f3^J=CD1Gx#Xm zaK?70kR#RGT=gr4%8GR8W+=&)f@e`hzk%7GDNCa>z=%i4Tj|lii<3h$9-pDt14YcV zF+Je|o&`_?lR3SzP908AKWI`brik7q28#h3&P&!H+4|>2%&K?nfdM4tlgOG+;Z?P0 zS-d_z$@n2Ql-PS(e{H^rw$g8)Byg!^&Q+W9UdQ5RjB4h2uN`~ZK2P`Gs>#KG!2WN{ zb$?;grQu^NmTf$0IZD$&hwWustbBi5`bV2Tjer)EWP{d>o)58#_I`H9FHqk0ult{$ zzyF@W{$IE2PW%!PLX(ykA&f|gyjfbm>j;FCtp zdPB&y{k73;iay3rHji0-R}!)~fogd2X+f+MyZcVskACB+D9S3d)9wb6*#n|f=Q-4L z3YM*%`Ud6fdMvf*bO}C+geN2S%BAu3+1Y=7xv4ob6_+mEPH8RU5{#{oaGiR%UpnE7 z$^$|xyWF@cQSVq_2dH^!ZnPTD*W(urnTCdvi9RCH3^v#8dKLUb9n|m4(oG z2k0#e(PGL{*#D3x6Bqo((1+)eQu{zW7Og~8e~w!~qH2@;IPLgAVm$VUWDDH$5w()l zz~UW5p2I`Uc|H{V2;&vD>QLdfCq6A#`p8wz@eYmw(zF_m;3fmmEkUcC2tLvQK&^D> z_4B2A%56b3z7KngArJC`GGH-g5kv+YltLM2$Jcvo%^C3pP7tG&^xA3}4}r@&w-TRO z#l0cjoSMXA_oVF!c)#Dh8U7q9TNA+r2#O7dfib&6^*PYQE@4emc^1-WZb=`q00gl* z`De!YsNZ;h2xt|cUG3+ODIViswJ4N<;s|u5RVcLB0@MRU_(!f+9jHxvAdpF5EpAEe zow|deETLt6XkRXX&UG*h{rlW3qHA44{41S8&Q&TSei?@kMZzzMGb);qZZ;j7`odat z$#dZ-58TM(7S>#rW&q)2ixFN%$4#ym(Vw9UWJ)cNJGCPSTIQvy;;$AG*RSd9*R_G% zeb7y2g?LG=gE#)X&}wlUK(4Hsc+#o5V5tLi$do2sxrE3C+qA&yk000|v zp70R$?H}zIIbDvlKeeuDSZ!q_>1SM@`W;CYN&lFl8=7Kv=`u=s0j2e0un|a{?x2lW zHH!_Y2rwwzG7t~EY|`E2A82KXE2gLE)%Zk53vy84O&5cLz|9js_`#u}ro)F)18l|) z(?s#$uitPDxF-U>hf#PVSEtb=gP&XyzcvCq`pJl2k0`N7NAG9>Zftbcm#12;0g0UC zkru}VJUd|ua<3}MAS|ail7GgViTtiDb?E(++2ifr3x#Pn0OOEO5C6xq?vu4S4<*$4 z65^11rF{s=d45=W?J?rA;mO@Ht8a(4r20~XbImtJ&at=rw9}8nRyX{eBxKFEp8$1Z(3AfgK*REoUy#qFsvXda;!4Rr@ zKOnlt*Vwi^OnE3Jp-T@)H9f!uFmX}XnoJQgdpq9A-YG-u9V|+h{v>^U(I2G(hh<#f zqN4?YZkNS*uVn;i5I(w=mds%&ov z@WgnBr6|ccLi!I(hq35bmOL$ZfjsoXS=PD0v^P&Gx4rGZzSyUlH~vsYD%S)M)G&MQ z{$xT|Dc7)$O{p7!Rk`|~7Vwcc+tY1+^hU2@7z=NmSf-Mvfr<~oqy3(9$wm)&fHckI7n zb^sVJq%~~_*Z(u$?bo?≶r5#t_w|YHg8ZdKq~}02+fpRJ4N&2%kd8u4#rbAMp+q zS*8|oioyeXdL(yl+$ET)3h{TY>eM~Fv2LoA~3SebbsY+Xe zZm9kkd?HKe&Jrn{Z>V@RpQ+i0DvM`8BvqjRimmkRdH{}pnNlAGw5CGW zk4-~S@LIBpF3$@IyAa~L`5Yo5V5&+70Tw-IRpLWV+cJv#4$QWHR3%)*An8s)HP!Sv1 zao$Q_mzJ63Hv?}-+aj!%|0&pw&q30{ENl}5^7ZFcj5McaH`USyk)%(+|6Cq335;`P z8)Ahodi_J_rnYX5g32P5%)mmY+zE-V>lUdJT&j<5rgWj3*ajAQTWKWu9bC+{so>f| zowt}A@;>mz*zyw86l4KRNDwiagl)FK^h$R>H@v#}1xb`39PW5H%Rx+PND!(Nt}X9N zx(@4n^c1?ncYDg;8~SV0$yzlFQ^%~gt74I}TZ|>`U#GM{QWGkyTvi|LiHHwmQk6%)VQ=WsJzb3SO)Px()LeEOw4@_OKG21uS6W1D!z zSkZv+qaVe9ZP-L8{3As7Q-})zO;d^Y-zS*S2R>CyfGe+;RDoI9)(xNQ_(0BJ z1UFsKyk_O9KQgsK8h$-d*?^~{+nRh~ATCO$@fB?YI7pfRlHYG+yr;MGxUQK3nn-a@xEkb$-%qfPuIVVLt1I-d zgys{g>18x*XE08PQn||mc=>bo=Dn-YQP2}jwgOwh7RiMbI)?md7?T$f=G@hLikM!2 z?>aWII)Cr>x{-@5f*Vg$taY@z=y|>ap98`g2L|yz#b8z1DNTpC1mvYHww^-ZPZW$b zmJkt+kXT9EAoB_2LMqli`1gUcsR2jfc+Hksj_ePGRIrV;t;#@fz7LX++w8}bHjd!* zN=QUU>~%uM&~=D^`Srs!9Irc8&z|k({Z>*Q`uW#KL%8c=L)v-|J-rmQFF>>~m+}oe zc~wIEyT)nix#2^|2Vph}t}ow&REI}?n3eWKx>Lq*HcrMIN} zC?I+Y2(%@hDnZy%vVDb0P+`RVKo=`Hd6Xl&1wxe(A{1KLNe>lBw|z?Xk&BOB;e7HE zS}-@!Bpl+dm*%Haj1q^{O$v(dpA*m$i2zd2^OmE@0G;mnE&$)AR@`47f2|`m+;G{1 zT>p{${=QJrqXuAnS}Qx7K8@qL%hocOv?aloThq9NHfP(0Yy_467}ac%^f*+)izy&` zEkor6aIX&aa8?79v+isA8GvVw7?<9182+W!6o}s%t8Q|+Dblscma@3b^QrGLm&p;z z-M=&Azem>a-y>_vX83y)P{J#Ofe_w(fJy1r0t0Jd1iD_V^_~d=-f|6qX8;09@5tHY zmyCQdmq7;VNI}dB)_v?3`Cu5{$V-g^CIy$bWJ@=v?5dpC!xPX;mzr2x5QV#MAbpeC zMa@r?Z-f__;RZ7{Tk_+_KAqWnL;t%te1=|yCdHVa5j5)A*>#}N}irArA9dYjU+4vtl%)0uEcztR z02x?s9iB&M;@PV(#g1|g$x}XoJP=Owa>^&#QUIq$a5gFQ<7J7<(OH$aFqQSrNgJpc z@LnjJ!Q23~$MBSy4-HKWq4Ky%rQG%gimR8HGgSEGd=_3eQt-52T431SV98lET9u@@ z<7tT&^>vbP>L^`QpSW9Z1hxci?$iGR`4GGR^k?4BzOUK{+HHSNs}~W956DN9{?2@} z`{wI)=rwbU*9L?Bm!HJ@(trA!|M_1Un|T8|5XYVVJ;rCgHfReiN0;P)GrZgdlt7?A z`_q+yI|r<$VZlMFcq4uzxHDi9z{u_kLUklTaCK$|YEE(Q(*)AM`u4KpGFCf`=rq!0 z`oqzS`8ad>@AB6S57J8X2Rgrqol_eoi!kBzYb|dR0f7m%^*#B-7GF<@)8Fzmo6;G?7BCn2XkztxSLm2A zbuUx-P%?ZcKWS(0k6oMd3PVFHBoZfD>KBlkRl+L>gcV-hM5zvFKhSOEPZ>R*IUtI9 zvas-<9zapYvcjvF@~eYPE>0JGNo&ekUZ*)YrsDtiD5dQ@Im13wXuM%PI=TGmU-SMj zCcL&CwV0jZh}Rpt2#p za7=Xw22suS>TgWJC-0D2pHat}*>QR&dJD`QtF2lYqr-pAd+BR6{&1LL1Xo*wAM}qV zK{p(v$z`<3EoCq}AGI3VO_HYK1kB0J|G=sp8Z<6J(a%fDD=95-sWAm71B-h19_5Eb zwTv}K8;`LAw!jIjJkP>;f!{Sb-Sn!Jw``<-Nubq36a0?p@FEE1GTI8BfD)fNqIU5W zJf?qB^FsPPwpKf%j`Vi?KxAZ`SFMp_d%YB!9zb%%o)MjpT6IBLm@)4jR@khBQ4TF? z8&Nwu7_!+bz;z50U%2qzcRG`X7*OsAeGeg(SeXIYjnHD!w#E0Y;aliNJ~jYT#<*s& zl1mMtY!_m}On}~O_hla>X515V;m)N)8}HE0$WDXTXh181Lir5g5td_-@KQ3@25>5C z*SNULvFmy+2wNG6_%PG=%!;7xp@lzkZ}BCxK<15tFVBs+OM{vN(%b!FeKLq0?M}=s zl@$|TbYmv=1}&S0*HXY}PQ^m0H_)`$;akuEEu|{Cy}!k8%o5|mmYxe^o_l}HWDtrV z8H>x?zE8g1?)4LL$KF4;(8*rBiTL|E|1)f$@+p2gQ07>kYtm{1Ti7wtpD?=wMFtVbptg?JY(u1@kb&m0@Wxxb#@g;oJf-Ph-#J zTg&1n4@()MaCt%zU|UftKoA$=ySr^qSelJ3*Efs%-iIN+q66Gm4}0Zi&hJ82MKPX* zTJmQWKQ!cT=wI}0pac|2cRzr`cnEJ6>?+6wUAmOguhcTRk!8)JkA)O=nUMJwI#Uk* z)NV>AtO8wJd7uI-_=I9R1E!=0ygILtGn9PUmO<>tp*@LJ>RJ)WV{SO_kDGpEETZ(^ zB8kFi=^Vi+8ghvP)NwSG1hh)B2FbL}KIqI5XHx8}Z;aTX7_k!l(SRd_N)kY+7utmXy==ibp*o{~bKTZ)j<^jyz&)1`|%PC<5-4 zIL938^AEm!d^mrE&{{MIS}}KD%j^&i2^$V%PcCgZdwnmnGrrKR6B%DRP&DV}EC-vw z6Ka?CRwhwNpx3Cmq+xm*@Biy9cFzT$+d)2O*B2jUo0gvV?!K-e?c(~98`Eba3(hT- zx`F)+T8?0Gtb;d6eS`NkOf!}1LnnNMvpQ^;4@~ zQ2v@%Tv$RLZl}ZoI|dbz$Zyic#bsA>IDRTGhf-Z$fZwpSX86zT6J2)(T4)wE0k0m4 z(!urR&Ri}H=%e=1!nLCb&xz;B9O+0An+Y)SrW5zkjWIUDt?_{=Bdg^@MoL}|DWP@S zV+X4by}3B0({^}pNIk)?rW=6;%nGcE#Xfm_Z}H|S$7bxnq+ye zCU{cJ;0?+Dom@0!PA(eQ&&&9XA&HGz%1LWJtw!*8;H=x-K zGn-4U$)5prXA3M4&2)rcQf5oP^!K))Dio_q&ZLR^3_-dNX`Sk|;wuGmHFoU{m{|!O zRr;gDEVyi!CA16;n!zDPX=7_|E~g^z_$gvmP42zELEt`+$4$FE%?O7w4^}^4Miw_ku zF+JCw)wI=_>FJf6H7Yjp;cA_>pT)ceZ<7!LBYOV)1!}?0O}wHQyMt43gDlsVWx;D? zY(zH)&jauwJ}4p<9h=j-&F{-=n4ZNSf$Fl-7^#$3aOnY{-c$l^yt@~?z{rH6irB?# zD&@ z^U2BHZKe5E2_mr;eUZ_XQ@Skf0ABEs7>=FP`bT|Gvivk?fgk?&E$}lXHp|f|phqa; zI|vBXUea4q;F9C|98mL@;>tRJnL^=1`P|XG>n}4#GCxv&%&HNqYHP{+StqkkX8$3+ z;26d-m+1?f%WOfnRZ4(n)Ik1tXc-zMJ0R2oVJmeSS~{w!n=BMy5^JV7Idjl=@tridDPpQI| z$H=2%(B@^h<5p3a#8p=<%(&(~PcFCRx*VK3#Ea&Y*uwkfl0UcS_=S`@ysiMv6k_b2 zSRMz(es=#;dYfv}b3D+&3|vG7&Lh20G~~AOJj+q|mc~6i4h^{FixawvckiB{l`� z)(h=bOLspw>Zj@2lwf^@Oi;eY5yk2PtONFboEfKG1-)p~FV{~-Is{BB#8`OG4y<(O z4A6P-h=WJy=cRPVKQAo%Yo2$o8TUcOZjBX{@^`fQ02!_&{Rs8Eny%$#dan8Y|1iz| zABbwiI0D*- ze)iq`e{E*?Nz59d?qvLo$2{y&xR~%d{5A(?^3eE?MsgDE)eGucuU!(?=cFwI$=5nI zJ;XgvocTsq-Ok!6Q;_yMGG&LFhw9;ZUC*XpZSkkAf-VulXv?QDV}w-!IG4uhzvhXN z1j9`BqLrK^ef7NXokceaw#V{}PJHO~vPZaE)~e}u3|N_iN#?hIeV)1h$8I=BZ-$Z0 zPbWPXS==&v|Jz{g6!rdoJ1hR^xUv>F-~naFk(!)xUh{30B< zbB6mM<4LglGVRLx^p#xIe?}eNZ8U6b%kYAuu-SX9dvIemfR(OfVtpaZuW}S|=wf`q z0YpvNU~i;9b~VI3m+l%YJzxKep*}-@1D%6@3m`fQ>_>pr;;_%iqwSE_;n3&x{Hcc$ zXZU3!<6-cQ>d*O!uS3qA!LB8@G-yd9bR~zHejqjq4|@2xWEPHfK?&(0vT(7b#WqmTDK}H?4a1 zNpthZHuY#P(SfRx6~JcUwGAnK*e~e*>T*U+e%N8gV|v}hLy?3+e~aLAD%LOcU=1U7N}u+WY*0k0_3d7j@^sLANi)+nRc$usqZG?Z ztDFKK`~YY*(DTrnb#dIUq)7GPBduVz+0QuOQYy_sN3I3Ky-G^~$c8s((!C+>uXzQH z;Fg88ciyYipLu7xJbYv5?9CBg=Hv3?FFnXHC5eI033fs(o)|v>&3etGperTvJHbu@ zUezp3$u!&mpa3E?!byzT@Y%0Z#Cxqv}LHar-)+0wm6&o^MSa&;nusp9?@oy#AIu;w1}|91a+a;F^Vhr>tv=KUE;5 zE)>vP`Ux6Z>=HE!Q&R!i#G|eXh$$7p?!v|Sk&{`Sfe)$oqK%nb8ESA(R+1{x@+#OB z_%>ba^G~pd zDb<`WPn{tjs7%ty0ty7lUG%n{6vxc`8=neM#Y6H;3vYot_f&j22Gi9sjA|5pA!Tpd zZ)Se>St(Pw8>q`H2goUh2+L1OGaRBBc!b75D7PdQEEKr6$F>3Yl`8Kw`K(MO5-rro)X0G`dk3RWH;ZT5?8EKw=q#g$j^A4dmd^z(-xCZkbIWSPGq+W$ zApYAZlc1xOr6vm%%*s^VL?LQ&+HJW(@btbZzZp6}AMa5kWK$}^2Vvg?wD(Mh zse;#$0e4w6aR70U7>N)b^%xti5BPD@yg6O(*tm02^j6@Y`Hw zOVOcxhc?KdWJJp@tBF5hI1tFVz9DeK4%z4c1KG-!DNph8s;KRpatgN96sZ4OHETTS zUDGsv?Hb@@Ob`$QoJ`5S7p%}rVR`wa7j2c6pd>Sso1G&zvw2w@UOlA$Ne-COJuea< z*_u(&pUtLV)-OWMgH8Ha{trT7x z?B3GXB-45Asn*{I2O8S#!WWoIR0!W>mPD<{Q6qQLK*9@G_mVW_GgDFaLv%zJuE5=8 zWcyc=@w}c-q3=8-Ntr&mGZ$B6)-dN?vvL_=><6p!oF@3A3oG(KNII3&$kTqa@oGUC zV`;H3b4OXDcl9T4m2-ZRc?kCMpa*V3_fTL*TI~~@WLLOvs%Pr1z9dy>b{AZ;0Fsg` z!KVd^R^q2@52waUU)`w-W<6X#7W~5KTYtXV7tyJ+Z)W3h?{ih2dfFuUK%n7FL(FUW zj2wI@m@NN6A(lrOwj1u(AtdzrP~-c*51LMsn1o-vURb7z5&6@&W_L`4?p%hpwwZUV z_{+`>>sVc;!d4JD7hads7N=i>df_=czP-UOQf7v09Y#aJz)a*Tpz&E!Gpl68tU`q9 zHuaGZ>Cs)Hg-J|}(Z2lh^|2RzZCl3=O;CQ{7Hn)iJ5Vw({l3OtK2ZkmfU{}*UeMxp zvzDKI*!Ek{{4SHFW+ReVq-rje;vda033NbGRA5 z#iPMfb&aDu<@(z$YUkj{YeoXLeR-)LWgf!d+F}S(z_g@0dk0C{5kMayqD$+af&J}! znI>8W@Tf43lQSqwgrgw-M$UJK-V!D52j=P*=XNvv7dJZ`6lx&!5S=>Tf8<}@{)6tK z12&K_ZG^1t2g<@_+j?fLh=_zbdiEEV*92OuYjZ7kLWpP%khTT> z;N&mOfCLqY$2j=sZx)9`$AGE{2x#jj01h^v(^#BaL_n8H0RngK2ZgBe7+~-|%74-I zBOUN&XbtPJ();AqLaa^^?8&xd7fQqW%Kyj;ezm@Oa)d-H0~7 z#~e1QC|{s=z4}U5!{`O%{i&+PfpGvJ##P|Nt8Y^Ol>|ruyYYL>+(-osVHYzNlmq7< zh-)>T&+7RuqY+nkAP`q}CiUA+=U<*)`XA(c{d;o#Su2rCGer?DB@{uuEM-918d>9+ zwBq5~v*W@~g1v4UQ^b%2!^EI?rt{ugVY1r5nUhvls44Cqu`o$bp4H zLFB#~aD};0HjQGxSXHb%(8IYivpj;ZXk__7(XsyL zLaIH}o_GW8BnnO$;(ANyX-G;Lj4_b;lhWQwqa6MueaU<410?w#!@1P4z(A>ga6k-G zHNhpwCGvraHiRR2q89}V%3Ut`C;m(YL}7m%m0e8rkDM9_xMGof#8udbYJ8S1%JI;A zN^g7|zP0EGM>MND3UF-+sUJ;{ZI(H(>D9fc%^x$4XFY#jnQ?`0RFI)~Q06WKESmKH?U`#r|?kB5P@9h-VMA~hs?2A8*$P| z79`RvzjoS6E0|Z$lsu8DR#C%Of{lsU?3Hk~I}Vth+@Ga&OMDR6znJVJ-Hdihh+`VP z(p%*7HZTThB+PuZpyytcEukx5xb8|9OiPO6TAa^#;{K=;Iw>w!#a=wEGi4(LpDF^s zFc@ew7=z9bmviz9tXH-P%z2MY<05F8PzCiiwCo0?9&pcQa@x|zzhd;|cT2!yM59Vf zfzls%=CN^$ z5TIU08_bZ+PDW215gshJ*d_IoCk8ou7uF3@cQTrB3PoqW30se=moFFIoP^ZscP122 zw0^aKTY}+Yar(N7s8YObB6%;>u_$^csn zi{5RK5vD=15aZ@7y8*JK6yaa8LL1K57Q^H-0Y_@XGDaxSX-}S@mnlX;A%M zgmSmW!2?P-Ig0Idf%wY3mS)ZZ1Gegp)Ka@8oh1eIYr@m={72<0HH4vxSC%=opv+$R0h<;hXz=N= z_32}7_qd@(huzN2;-(;{ifh>LY`r5n9+Op;TBUAaANpI# z79{>7T(*z9a{r{cjImRXLO|xz8@+G!)>D0wyReyuLaT9wm+AG`h+KdG5QepC-E6D zyUAgX*Bhh==Jt&eXQpTB*wT(N=$}y?XjACSs5qm;HnJVEkj6Pa!?hUG@tVYKICtaE zIRbYc`ymMT)UZ)5b(t$Udg>|@9bF-D7-REmd6*F32lP#@z>9x4He&;rdA$nlsd@EX z%;-c3yO)xa`tn589}~o6BIs+VkX-T+Lb6OBG;kftk;iGYjKrlQ`sjS^MBWkNwUhD3vNC9{ zs*-_O^*KA!r>VP-&}7fg9|>-=J$9g`@wwoL8@oC5%>DtM!yK0dh`*G9CPT%CD4 zP>YlUf7m@^vFHj*YQHUcTZ^vj*qZ*ln28}6>h0Gpe{vn6)~FuggXnZqsKe(8HJO!~ zAbr)$yqK@WyZ+_z-6eE33(=d9t)4B1fcaGp2DG^rn=W5YHNuG%hDX%)CdRH?2L@xn zyv$+H_`63C(3oUnyB1SR+VF3>#H;+74GzB?Vus;$;7`%MdjAM|07Rw^>a=lS*)7}6 z$qJT7*p=8!_ix0N=ue=L&6h!3s**E8w2c|K749=7V9rZY*hg%neIp?{X=RuNXicst z4#obQ$sgm>E)KRe9*SRZFF{6%((OysGj9mZmh(&2S-%@af~ocx)*0*t88~WpZ^Naf zr_}&{WhJf@UVv{)85VZr6qk4EbW;1jt=9-*KZi?KgD1?;Tq3`1N>gzS7`HsZ84znR=@7W#kR*-AYJc;UULzMN6 zB%DR{Y5j=%gsygX9UU-}(~=+j{!So2s?MuD_IlvOh-6fYI;tc}Yhef+U}PJRmAOo5 zLe+)L@&oUjs(a<*Pl{~O&ts*f>eHq(44IM?Rdi}Z)q{1>TBKSt%_qaTcXM2Km+0$V zvg-OO{qH54u%Opcx{{G4+x;QH%oe%xF5u3Y-f^7W)v(AlJFTRrrfK|2p?wb|Q_d6l zwfrB>-aM|Ut8EvywTd`JMMOb}6%Z9AA|O-9Zi|SB7!?%+Bvn)<1yPXzNp=+w8B;(& z5J?pg5G67RGDXIS2$4x<0tv_%NEpI~B)i|D&-0w$`<>r;zwey$S1UtE_Fj9f`@ZgL zz~eIAXi7p-xB;f`V2K4bC5of{k#j=&_Xq-=VZNUNB3l(#&NHi2Cc^X9r7Z*c%y#9B)DsKLQK#9lcf_WQQVNz_S z6`-PnT{oms?g69>D35y+r3!Muhm~IA*34h>aPC22xo<>*?*Z z-U`E_ph>@E=wa6muIQN}RtK#p00l}Z%;)ir%7{2CCQ0~ViWhvuu!|mR!X+*`}((#&BloL0rIByf` zpT#^*7c%0wg;?oU*II6&ADar*q-w+(>p$CqI9+r&`jqlgY9bB9k2R(5mw!fZtQcSpc2^Y1 zf`Rb3f0rnc?`Bkqzlv_??tg(4NL_UKoz5e`S{G_=#P z`{orH5(utzN0opM|DXJUO_ZOP_p)B7i+eiouB<~YVLLy0j*jdDH79Tp1AEal0VmyF znh$)yP|cEneGk2USsB#vmP|R5JTR+vG9&CzUfKzG{dD@b?za&cHf-)o+D)+3PqI92 zV#JlQ>_Uz*nbyza65Ed4n5~$-ykd;*@tx(O3J(HXTwNgAx{wF-Dww*`vg~u$uk_BZ zJ#69QE+l~rC%_I0c7`zHSmB>AU|LLXPhg&X>G(a41*TD+AIgtQ>^LiD)SNY!ZDL;; z#{=~js!(ga&@%7ZYWX{0vOf7gZfpKmZO~Z&*R$JThv@$#2KU`Z%^=aw)-J6e{PYY~ z8hC~@o^T1BAWC%!%7GzU&s+*-WN_bMq)(gZC?7r{W=}Y4Nmju1rC@kF1&0K>%rl47 z_JD5wt+z;TNd?rRw=zcQVSu2?nAzMyh?3S)E|XkAECn>AmG&>b=9RK!z|KS=Vcbb+ zVkA6tZC9H98PW~P6TA1cN_ghh5(ykRy3TtU0p$!ahC*vLS^mNaArgmL6qaL18h@{# zrH|9wv?lDin_dDFZ7e8na%@1tfO1djJDLVu4*~DczJCnMhk9}4VRR%$CI?C@znH}% z{kw{U?Ak!;Sy*p!iS{b5f@48RMuS*arn~dO?j!*BZlwfA1V(j5dEqTn{ewsHDNjBN zO*>{MFrC2Z%o{vu9{z9_7%6y)!2{-Z9lb+(-@j27i^qr3aF)PlKlTe{8NUkn<_-Oh-QG*lMqsT@ zDUNr%Y$7;uA=b;tjF_t^+?bSMdD$DANOA#B7`5U6*_%ffTn5*(3VP!>5!2OEaJCWC z*Lx&`zCJlryfuGqvuuHu!4~!JKFj|6_}WyBWnA*Lt#%7X2`dMx!uP)U z<-ZQ${`>!b`PZ7!tbL{X7yT zCJKVWrOdj>r;5qKRILrc$Oj^EfA(7YC#PKJ&2NentP!FRYyHh2OdS|hw7iI4kWKo# z+)tgK=}pDU7_i3~Ew*Xrv@^ewdS-Zk7j|+%K*FP+p-qJhFp`M|0$E4LxJq=VaHno< z;8jkEO8Uut9HKeN9Bev7?^P6Egqe<{eM~)2M6XoeUiSV^9~QhfrvGpp7gBks&8 zcd+k{jj|}2EMX?eEJJFkSCXIYowb}L&;g6V171sOLs!t9K)UE?pp>!aTz79kj#>6+ zlt95Dwh~Qp-7Nq8hm3yMY_K|Q&9FSV$x6+-tN{ttrA~>SE7ip{?#52v<@~+kb=m8ScPnz0JLOND zdu?i6GH;@Jfm=i0*FZKLWP^z64DKe4cKk)3oecS_eFsBc5{G(ka?B&uvPs@<1chew zC(0hQp_vaZX|n+Pxu5^;Q$4Wl@kR8ixQfs>!%@&FhT^`uK{#k_z zM|~IpGO*J=&|XiG6UoW+%89ZkcEjU4m6tNaV84C<@Y|q4D$z3TSGrw6+YYQxqNn`uB>f%x=e% zi0$B>Tvk5j`wGHExf_zeZ#e1JQt{(v&~n$I2lDfydHpxELyG$*Ex6QU@@zli&kuIT8_E{8D(x)Mp_mS9H)L0o2Kh;k#W>GsjbleZP!>tW}z%PFU9LYuPrY37=z?8Dp@ z`xw*omi^~5$?i$#KVRNq7p2vZ*M*)(j9cm2A9*t zGoahe@ZT7gcY(7D~h>)=J5*0{!=ZJ=oD4^prt7lMD`4RR=m}9K`q2P{7^XUJ@op} z-M;;sGR*jjivZix?lf8D5_d@pz+BxbHH1x6MN&-k zi;6d3ms_xu0sPnn^TQ}j0f|wI@fnm*yMvER`I$@`ZxB>6BcXx!C3e-AHRA+Ki*$p3 zM(;$)l@brTZ47PG$lEo3%$c51)-hD`thhC?psa<|Py*fKErO#%?{0;{f+?Tg>CGBQ zQO*#EN-i($C3Sk;thl$%E!K{bM;fx;m{KoN9qSipARa5c*mp;4|4m&8N8^D( z70E9C%B=VGKCy-Iys9ztHSERe^aGhA`BHCJUL%$VKg26(#L&e3{chsV$9H_PW8y-boTR93NN3ML=mB?9%>(ytZ-@wQOM9nXC zvGz;BY5QQJ-W$j^RB8ZD6KkwK^Fs2Z=WBpnHpNL+4o<@d6zQfm^e3s_H+9iYKl$?c z9{+obCrMxUs;CPom8Ky&@|?fninZ+Q4F7al@nU+iYi}dc@l}YERcitXR9y& zyzfLxhhZ_86L5b}BRxXhKs8848zsld)o7KsG=XIgvbZJB2;J~@>U(QgugT^$GUqV^ zbpwlNMN2l<5PE_Cd~Fz!&u6gyHKCpk2cf|7T~xnCii5;;UY` z5?=;klU&6N&7vDV->KqBZK17r4t$pm(De}{#wXiDNh$d{eNSKVl`jrze_Tb+18wi} z^JmG&c3Sc*Qb8`cf7YlEC?s2zue>X+27jv}yCyOCVlWvvMs}l;r>T8rI_~qxi7ZR- zVSy>PfWzk;?msSVDCj9aGA(Pltvv;7GfhrI?wGBXT1(9QT6EeE|Q#*W_57_UDjx%A2cl zi`H;JdCGN9Tl`?xRp-y=L>uu5K2(!ghi|%3kSpXVCI*0u6Nf91Fu?;N&o7E?vVsaw zYP6ZsTUwCxW&-E*@(T7?NhD8c#2v>TuwPsX@M8`$`QCz6JUZRku($)XQqDkAk9)cW zUz@<~@)QseO*`qfAbZ&p->pJ8il11Ms@&ddF>=YKbTT5Sr=_fam#_zGzUO0WHK*HJ zUgtXNY0ksPxqm)>Nu!RxZ|Na@iuI4FR~c+ZFE|q&&`1!rV|GfL)On2fz8^Tdx)!~tTJ z>^8SX{?=;Qy?)X>WQ=#o8tQ zgUb{2GVV+Mj5J}c2hHR!cC;{rck*C2v=mM z9U#VPxtXw+H&;BZzu1!-%{n0iY?B87>8-q0W+-A*Z-dvOdiG;8jh2?U3+On7L!vT zfjb+jZ#!FgW2IJ{##`LEPYVXfpoojg+X&@qunL9rt>CHIQD8=BvZA#mQ_ivrkKC`4 z_8Bo5us06TE{Y&%BkGoj-+-hc3TrM*He>d@)md9Ox=58HCeG(LLk-vJiansNhPbYN z+wTz(cFuthx4{<>w0SWt>%-GCz{(7rZ32#21F*$COKl!gi~h=^FDieVcbz+Ci4J0qQY=AD3T`{; z`M(=Z_Ig^p*j1`{g@`;TA1kS$zgH}+w3|uTMiS_Pi9Ga|=&Y=AQ4cUMCTV+-QnjZ(DD!k%4Q|f0 z7XAgwADIjlvc!h6Se*K-&cV5xwkI$88ee}RYYCc~t%V^!lcCh@$TPL9ov>SM!|96& zxaoJ4`=nO{Na$Jzj0NFImd|TP_8YPqw>lsI9O<&3wz^>Z=475T@T>1X+A}7foXW`0 zXlHC5l#!cL_ne{Y$1L_pe2W0WE&ijp7&#;6PLjKV>9>Z9408=e+`4w%%bX`YTpFpu zZ0dDGH9(?z<8QdfwTEwdnYM)=ZkJii`PRRCqNbE?D{uFdac8z-SGF;4n4@+E%wl2l zW0ns9*Wka?s@V<$znp#l#Z?+CgB2(CpYWW^`fh!1)s3j zF6;UK{K60VfmU<1$6q(4{74HseZN3}#*cDWm05a$Lo9#l06*>visLbpcobfa-Gc<3 zD1z4|PS)VghY8+Ks#jhp${%Sq<3MhY;C|X<+xpv`%*)8I&{zKnTyPMa$Jfhz(F;rG zgbanjJH6|D?5Ru7%6u#Br?!7dPvpCxN_`tLZoDLx6PcL=jp*=wV_5x52S0kp&!v4{ zvK>vITKL8C#M|&ok8ivl{-L0QzUP^R#fe)fW=~hPv#v3^xiyS@<6@z#d?*HioZ{ia zo6Qh;jQi6alEoM-JRJpce`}~vB`e>iwvLfL@s!fuwtZH21Sth*x7N^|)6U#p_x?+@ z&uS7Dwh78LExSMU*RkTIN0$tRbvmiq`cY8-#e$MM0a%xK(RITO+ndiq-giN23|!N= z93wB)HglO=!0wpGAPeL_tu|Iq)M3szH%gS@N(dfQ60Ks@(8D&fwQBqg{Y$Yo_EnCo z;8olN&*CohE4*$5`2qWgu$vqNp0Z$G)6Iy$Ok>aBoqTMFKP*+OM%TG$g=@7Fc1TTQ zkMls8@N=nWROts*BVcP~t%hlwT`#7XJ^uRm+P;gdnHlI-v` ziZ;Mg{)*hFN7{;{@mwPb8lCB^M`gs<6Wc`6F~yqN$Jpm@$ZuTU8_048wZ2xo-(0=p zS^LE6QBLEX=}l%O;&WGQ?k*@NT1o!?+Sb~CukfeuNw&~7(*j5AvBQ*%4GEXk zgQ_eObRnH=hx3{o;IpgU_K(E;A7RG6Wm_{radyeES4+p9tJaXHP)pU8(wXR{ zrhe;)Fz%J34F8_5cFoGH$?d7~vL{TuJCC@zXOy<92<~&s|I1xdEk&)6|DAC*+j_i{ z_3%}K=^^{@;(+FwGl>V%UgPsorJM}LJh&V1hARk%XEqY?d~>g>=t_H&@Aq<&_%|8j zE~nd($CRosF&+&Fdui4t#QjtKy&{rIsIWBTa0$2j+^y!w=dWG6uM_tA9D(EysNt0M z*(Qw6m}ob%+`PMhsp|^-Wnb4!2Pdoa#hwF&Ki+pKcUl==xxh35CSEVjWUqZU5?V#0 z?EyPx=Z}EDE@#--=z?SuB^1THGN02PMVoti(3uKSWS&&Va1Ya5NyonUnUTLy8-1U| z0Pr4^%8<=IgMm@FDkY^{B+uF=`LW$?7Paq(u{zK1(}>Q(Bs7QtJg{T&Ib@Pxb1ylj z+wrBpHEw&IUQ1aJDt{il#w?O0N@Fjis(+oDhvd4(#>BzJlI(kbsmb9xEWrN%yDY2h zvM7}F6@Y2<_0DcHWSb2o&b@Ghc*SA}oIqPUR3PlvwHTO?9B)XL&7G8G9H~9!WGoq{ zl(_xe-^2u*N<@5Y7 zX<^N>Kxi{~A}@d>49({4&him}U8^IcK*#({$ z0X-fdhJnzeCLn-p1~oj`Zd=MOgD+txe+FMt0ADKMwv-V-nG|!4cr2hxOCo?o>hrq; zs*w;a>FK2mSs)Aj!}E4PB@zLA){iWoywl4Gv+y3!XY{9`>Pzc3qtog$4$^+iqkd-w z*o9WNLCt@!;NtFgfRY@(%1;Cg8uEgxw_neqLkHsQbo_#4zmF*z)6Z(O{ zaXio>Jz>pVgDtq5VOQ2V=`C3*=tTq(fkyM|sQc8ows&R2X*X?I#v|!8Xl}grbkt5J z<`KPgZ+ReAYj7CT&+}k^Ko&q(wY~o$3H@eb2GZu>{9ecW#oRsZG^Or}9R;R;F}tS2 z0lh{mSPDtxkXie01`W_7<=T?`o^kB#)L%Z))CrMc)tzlc%*>^2qG9D?hZHkxU|iM! zIV4_k;G_@si#u3oXvi_G@4x}fHw5*Y4FZ7_I}#-*vwdQ zY4dXn@cO8{t}uw$BGr1{1-7zPrEl!6cR+5FhiMCMsoH$TPBI2qp8mZeV}hZeA82Z7 z+HkMf`k?tV*qCqmalk{h2a$}~)g(oG3WOWa31{Nd8a&Z`jG}A!m7&j%>AjskXUQ93 zV>($M83i=Po-Bz$*SJY=z)l;T48`u_ti2$QLex^R=i9s|9W!pY%}?mBw9TveL?qYe zekF5MNsN`fA*l3Hei3Pf@`YxMYKbxSb5W@)wdD2O^gPo80n6^ENyJhFS9YhD(J;;Y zvTwVoiCNEjo<5Ue9YzOP>C>Bs3_MP=@0{3D$nrS!-?`t< zE!(7s@6T$_7XdQ)O&tbExT3Pc4LHgdd&wkXvE=Bt*dD>9XNOKr#e>zj>Hs)~31paO z8Cr-5W2~M&FqGfQJC}Ge&!$1=kX{FKHS0w&JeHqm#~ysw$r!8;@Qy*nw0)W2gR^+Dsin7ZGGfxFbR3uz{{ zLr=Q*z90>CE8>mwQ5B7zh4&pZI=|LE@!G}<=-l3r9GUKIE@=qE6TTEn?hBLBG8)1& zRQqQwKUdxgJgeJJD-3jQh4KpJ4}#4Dh&>suXBO?|%Y42js7#ze{Jr4Sym$H4-{RLY zwq6P@j++z%x6Y<=Kk@J2dIm_($@1p{8_hp1VS5ftqOV+GTE zl}49y-_%>?pmm?~`fB*Y@s?SiJ~F=@R1g;d#&fd>Fh@3^ipXIz7t7)vMGzkQVWyp( z6EM%5&1VC>nSsalu%TW(kuAcIn&d87t`!o$U7n95RUf1`GD5L=q)JBDu`0f~EbZ;Q zBfRZ6*wq|0A~RV>2~WP4#fh_I;Tp|lkUvPHe#P+d7k+{24|GKzhgTaLNbX3;9*i}> zD<8lIwQ5Suz_0ofug^WBg4T?~PNIs|Vnc*20muAw1cTA zWyi}jk)k!vlO$Hw3C>G59f#gf>$D%-IuG3{?=!_VzDBAJd-RYW=*m5rmu&>lOhS300@ceOZz@@63-rs-6CYQ;HLF4scBN-z$6qx}}kiFzI>u>s!M-?2e z#M6SP?V=8?4~nu?f67c!gua?#^l1|u;=<2WQ|S_lcTSCwwu~NfB3IWb(?YRJWvKrl*R^N5do%m}Fw2|?h(BS;umXX?q{z=*~1Z)a7Wl6BxC1v79sS4Gd;_n04 z!y=OtuLYyGeZE!fLUM(sAk&;!Gr?Jpyr{A^JKHdw(ci~*)?PSK4Q@6B429n1w@Pus zX=}RqViA(i$E^>`2a*|?_V_bcde0aie9<7&Hv z3*iUn%&?~)TZ=V{Ku2G!O7Qj=hukoTx>hw51vX4@e6B*UPR#pa`F#7b(#_FF!dcDyJkyEr%oP-azgVw~(c*YdPjUw3>Q5+!?9FEhK*j)2s0ilQ1qSXCX|O(Wbvb5; zqEs{&!+%XNtBUvMi(b+H8vOEsubZ2$FmF8=Du6+K*`+SV3RUZJHGrk^Hp2O`3nH&R zo!O|57;y+~xj(%iJtMlqCK$KQ(;p>>MWX=^7w`HV4-Wjw&(WTfh+SoWNVP7DSWa>F zqU#Jk2)4TKP4_afHjRXy*hPn>-uzgDUaZ?$m`kydo?~HzUGMGh< z4;4GlWi;-C_9RI{w_mJ7dtA90{mE6F_h68S?%4z&e{dr;#vk*HyK}&-w%e z`wEu9ts<=OS9<9Cg|n7g?3y{rB2-wq!yKebWJ!f;EhibcuMX-2hfZ2$+ z?w%~dds@$V%C>gLJy&__Rd!DkdCd}*e@bTKb^=K?a|U6y;(}nIx6O2T#ZO}(MJOYB zm+)$0Sh-;8V6{I!=7As6;7SL&#&BR=lC&5#cFVI`u)S(E3z`gv8Q>MQYlzYkx&O}X zF=4~p$<}dS;+K=xkk`PLD&)+f^6erLQP}rASH_e*SNI$|*_H23x-;QyF43c`D+by(!%^D0 zqB63Tz} zh4O2G;7&sn9PlzAK)d|I`ySR*bZPO#Spby_y^rNeTv3h*9IY<8;tp_+HBAXT?!80D z>-_A#uxm~Rjbpo=xeI>7tfaDczWyJKiH(O+#II5dCrO210CN-Y|Kxc0oSym4n5(;6Mc^?#JxPTJrrr2j3Ow`g+o)m{pR_4sd5b z!P;Y1DIMb^AUy1!mP0aXbjJeVI@xai>9{G!^b#+i{!A^Lp-Z9Qx`!;+{7h&wIiQ%i-?LCu430J1$y4KkCUPR~ zbJ~t8!wp{q*s&cg)lC^yG*{+9D_v$gyc&Ge5@l?SFDMv-U3qBI+eU8%DBj!aZReku zY0uegK=nul)>r!EZr}$k+LPqtD)zs)`&sL7@tNM=lV>x1t~(~3eQPdnn|vm!*O&Ax zoa}EQVK@FeNF0p69k{kO%vnP~k6&WAssfxo=gfcT4*%)!{;&S~Z>+$>BMrY{{=;iAtWvzJgRf71%Lt++l7M9|KFnYd#nIT5BeM|vi~*w z((NCC*p8xpWi#OY`jL;W=H&0*2=$Da#Q~yB8IRkHsjAV_jzn&EkhM@2Qg`k#+((sme5u^C%I! z+8~0Ct?vh!x0F}oJTQT$Sr)%w6zvL5Qc&R zMr+_$me8_#K`Bw~km#l5jZ?LW{$m}oap?u5P^bm?3JW#zcpR?*${pV<9cT5E9MH!! zopAOE#2w@?y=bh3X60MuH0VcmoC+jvE~liI+f9ZVIL{gop%0Ip)_l*EX{$r z`tw$o#)HJ1fs&Yvq}CJ(qtsbR7E-1#K<{388i{vRtw|PVEF{|oejO&lM@Ijse2M)uo%*b5y0Xb=msl}O#0I_zYynrKej4!>PMLw0h{iB{Dl1h$ zrv{IiU{7iPN!&!aAu)ms6%oMTYL+V;-Ers@V7beP- z?kpWHvbp7S%u6r5i#S*YCZN$ZxWy}8+}qM z1U15{lL(wiEwRb-1zJ%kPiWQ%P-BGU zd@o)sDk2nq2fVYB;Iv^>(sl_c$ylkn7+u+p?_*p`9KLCu*?-vB81L9w5#ui&F%Zbl%PlgmXg$*e*R9TBZ_U=@Fee;4$yEd%x{MWmzca_7*#bkiQ-^1@1NUX*in*YQt z|C|FKa@{`tmY04GxE+$-sGYWrOFxqGZ0~-pOG3_|6g4VWr`4c(4qQdTI?h1Mh@(`r z^bK3Z*=&_Yeu3@x_c31lRvyGAY{zbX6>T)HX|5&w&RWGw0leYQ#SayjXU|l3&6P;$ zV>)t!PKo%z{a>G3K2?7C*f)Psk+Ray-&6P=diVE=H$9)E9t+hrwl#*zH4LwwVF|0y zxgAxu8iZHKqD>na0y{_;RJGw64_;jVwnL(BASKrNhwShD)m8!X(DsAuX8g4euP(`+ zCA6Q7`YX<$OzQG`{-H_@LjGJ1cbzgKF~tMhRN^ZZSy zKE)LhmVt-2a1IE1VD(Y#>_RjKi_4fGU7@kD@5OY9HFBk&2gG0yPo99r-vV3@=dwBG z!!Hvq!nmb2%|?}rwKwSZQpOsVdO4xuM2@5)gDn@ zH|R|VKt+YI65&X+wRgzRXmdK={z5$bBj&PGkznvSFz!XbAc@y#3mos>=`UhY3lgtr ztOGj|E`h|SWNCOU5q5AjLq=DvNYs4xYN442_dB>~{p34#6fCT>)l|O?YVK_l(pQP% z*vHUgaK7Dux-o;?NsPpBxm|rhL=t=5r!%^aF2+2|jV7Bl!bYfa`$6fi5=Zysbe7bA zTy59I7mG)vuYR$hE@Oyqz(x@9tHg!eCslAw15~Q&!FBILa#WkfK5%|B8r9};Lx0<# z!kZ59($R=E^`!o$6XTA`ho3N*mADn#HS7>V4TN1c+WvYqLv(dGKpocc8 zxmK+UGcbcsi!wOd3c`k zDUcJa{5K+K@qP&>X^#8`MlLiuci0x8i=N=NQyV zf0Sk5FH1I2j^`s6ML+h>I_AenzlpZ8?kN&p-uqth5U3gvV3XRo6e?Ax85If3%NQme zxkfW+lEA5O+{L|P>D6wh=IjpNanDnR3p{^F;41O=NYxVIL4QryP%nGV_w?)X`#?D7 zv@zr%aPf!&rerFZE?yu@bt2XYu5y1{(=zVZTX5^Waot8U&k+`)#bR^TNwG+-&!Fs% zWs&5ndp@eLk9NNNhFGfI4;;lv!ZU9n@qT2p_Z!QMzgKu^J=!b~bZag8SB)4gf`E-9uFix|m?zY669rhHYEUxXBfTN~a?+amMiyZFWX z^GuEeYz~&uZ;-T0ptPM}FIALl&`9Fip5B}2l+97ncLB)uYR;%mPB~bupLS8w8eRe= zle6`grjFPyQ!LOw30DET;~#JBQQ9{0W&BN%x_OHhut>`4xA5W~Gh()2k-aAqvBDEj zs516GL76C~>ap*wzVz#G!}I_gNO;9EC|kwr!f)mu#Mwvd`s_)(mAE!a>UheB^b4pv zEm#B3&!YVS?2wT-OA{0F?bb;y?DzDm>l~Bbl-GLzAFcpLs{Z-%>OH^~a!M$pEr>NLyM=j0M{|VDo77yPz=pyzL*`)ZzTD>9L z*vqml;rYY!;)R^1y$z!6WjIZFYPzqqc>@s>DBF<(&?q zl!nl_6o-&HO3_CRmyC2c1#6RYpzgQFw>hqj$4nX-ndCb`=?Coa>C<;j;c#vqJ(8dl zBQh7e$J&_NihiTM5a=*G1cGV?m>TJcJ4HA)XA|wK+DcG~b$PpbqbaPbGf5iGYsQtv zwZ&*poimoOxm_QUAK!M{+5H|}sq1FX_oADjD_65p;Ybs14b?^5UqoledTi0Gc(l}nAO?=BbAYSi&evw7(?ybNsf<_J z4PM-t_FG0WPd*dT%n)cv@aVVhkh)wDErUTwH3@zjV~+m4;y~krk1^~**yom0mORHqc4H?Sn6yvWyrVP~(a?MG(n|&u+cGutxb(eA>KE-n zGgD$KaCI~~a-0|4Zw+hGoJ|(b&lyU$jfl07dgfRMV-vVP{B!w5tzY4q)IOyJ)-7Kz znddARKB|a*oBhZYo~2^#5qhSTYv!>xiJ&Xf_F5Ala$b@&6f zs%5gj;43QrcqMP(6kC73%|Y6e_=TP^uz@B|4iq0pl6;t5i?ns$ApRgU{O3HsoEjQr zlwzi%G{l_ZB>NHXJl(NF;PDSXRg6{JjD>atc!Cv1?fp zdB*qog$wZ_1xrL7Eart)f%JT)<7nc_<5#fK@$Fkt&fy(5zaFVugsLh4X#BvQ z)&RmZ^}TysD*X~u71|F>3cmX#Ts*y>`N^lBb!#xv7c;N?%O;z4`F%eOpwv`*cz3h=EjOhq*w&f<%|(qS1gv+1LcD2sioj0Mx@8l$OXn zN{c4pM#5e+4NAnbAg3Cg{j_%M0fwBUn z80`k{tv$&)X>#1~@upjNo9c@@-w_v{IEWlTwwtc_{59Dq;|XZ4ZnLF{m|%uj0nH-) z1x^jQByVsJ#@nFDjf4@QPQ z4p(aw`K`eh+kH32OYEjFmF0d_u<$oV=fhd+4g(4Gj$KhrmIrYAi$N)(4tg@nLFAF6 zqGXA&+`o{UNY~Pt@RZUaIi(#Ez*t_)c5w&S4CFO|($q_0Hj)I$k*Re0vjwYRFS^L6 zp4kcla_xda5%b^~T4h3Etn+ZhYeGM0Mzr~HLY(!`QdYa z_kmJ)6Q$y2^?TT6u`C*Vrm3PZFGT5)im6N*(dU?`0F$a+)>TQ5bV+_Kt} z9d_7(sF27LJz=;;hLg6Gkw!15rGH4QRZtOwJ?+6=^cy#q7_DQ#S=BWv>UG*>88-c5 zhPy+xCt99)1pGiPQDRB-eqklbCbqtv>|o?h^ELmOcz5oI>|68|!AU`2`)$}QDLw=MID zjQ+2n!2hA)`?r?wzlR2G04jKNnaKM;xlG+N3tP4g#x5F0;bhe^Kp?7t2N7v|SfVc%Hks=3hAB_71?> z1>a6iTEr>ApXvbL#jXdt-xz)fNV;G-$AyA=wih1KuCqftyWq>vq7nGh_3)p7mctry zbo@Gho3zkP%NSRge*^tj1n|P#e2_>9JxaAj%ejEX3w$g)X1oAx_sl=ET_0>Ew4b84 z^^TO*%8zRRbBOo5`&d(;^H-FuMmof?$mId-!+s^ipV?1MB`S`Ed2Z=G3Wxntzh8T? z|3mYX0T8NkUGn1^ii_K}?IlTqiz}JE-ko}4^{=QL2=`lHDB-O#khq$}7;~NIMCPo; zj89RjKl&R>b?KgM`hMfP;|-JLrVQ=DH|YZH8B2lJWhq&fPTK}o?yA`2k&Jx^44D{P zJRfyzOIT3pxucenB5I@^K)*t&pcAx}o+=i(hN%}t&+wrGdlhYs=9cWn{iI3@;sd}Y z6vozIkdyi{omuOGMg2wi+lgY;)zoYeD2UoECfEJEL*VTFwK^E_)V=*hbo+a)e@d$6 zbt9(dPN@21p@r#}#v`mY%@=u)+CMzV|G(sB@co^ktMe)5o=@S!eM7*Ve(bG6{Yz9? zSRD6r^@uU`PmlT9c<)*P-rZV=j60kdvpHzEDa#5NBVtShUg4eBUPwyUlJfp6A;9qw)21N-3Yy z$LgjU{Dx@dkIDB1X3yknWG}%(pX|Ys!@~pcIwXkHrcu<6lk3*ED=?RI8EKb#7b|{7 zo8Vj=@SqToh$5{zBcKBk^0mZ2s>5#|t=IX5@FXWryhC;$D$w_Yl_^Kd=rzg5p0Dj2 z729F`h~}{-%HGngE75fp1FTNZGc9vwU>3jC=@X;;VgIFUue6=iZgfx8WuMM4_TKu$ zg12g{A=)#CLgiaaP3nDgmuBb&3DL@-i*{Z_TC34(j7Yqp7pp5XT0Q!@s$T35%+D-j z@7d90P>9Z}a3VYO9HqY(9kX8Z{MP3Qw$@Iy6*-W26nw_dz|S!Uzf2nf4a_;AGvoSG z0%u*C|68`1S@tk%3pvdRiR0}sAa3?lGO2rBgc5Wxjie3~fI&#fd)$U6--%u9yGv=a z&YFCXhIqgL8#tqP_xhLZ0q@8G$BWZ_8|;=!<1ecz$)5_Ajag%5u6}V6mRV1G0yIqZ;~@XgpukpixU)!pwoY^ zV8lo{&r!XeZYQ#=qe;G?Fb=XkUOjqgbjy+sf)1UTW?dJD%gR#WLbqf^!t=|s5kjI z|C~dflGFs8yEj`uW9clAoN{aNaIh#lgU*!s)sohF<8@!Kp(T#)uRWw*=S^1*Tf_~H z@;^{B%ookaFn{p&r`SYh|M6YCe_d+NPEIwv#c}`>fnqy!G-6H7fO%hWC*vc=Kw={Y zdv%cB% za?D>%HgFOEn5h7%)&AZ8r68U46#YS>W}9??BPW0rp2+@OcB^4^p?m2(xF*71L)4$i z8oM_sd47smp&c%J4cMBEcf@27Axoq_P?ma~^~Mx-b8Of^=Gb4;bNEwsI?%GCqJ|%%EhTrbRic2>}f^u*A${+ za2dNRLcwmax|kEDo7%1a%*g7X*k|`U9>PK(wIO@)c*LDf zrqH7oov6bJACRrb*b^a8raH_Fv5I5A&w#>h3QNgj_1~K}&;s?6BVJQjr1xo17i%HOp&D<-$6U?S6`F zxVngPOCBwe2k%%+JwPYIT*qF( z>XYbwnl8l;F_bu>^~xEK3~bE52vfoer;aElsq{pOnU7&t#vf`LvW&@_(j95_K3X56 zB)n3}8!o>)U3MS977=hy*+pd55;!;kG+HEZq;J?wo3b05AJv|~bT5cIkmV}48Bx^| zU#eheB)|tN!n`C`?+siXz=8rA^1M9$yAMvQf#rX`eug;=t`04Cz0LkMm+)-i!jX#I zaHUZN7Ga6W`NEZK&GOVl^wqTAbkW8niJ&07m4ryafpr2`E}b6aCXcRT&B7Db*2GDVHU9 z+5r(EJ;$*JsPG*_7j0*lquy(1(bCJw-_j%NXj6EuCwVcAM~;Ymw{?u_OfO&Do(Q`X ziB>;XOVo&U_xa4d<|k=-7G;#WcN1G~spKZi?A48HZ#ewf-lRpGlG`iQ+HBWNd;<2v zC52@+CeY68U6FpFR&(o$v)NZbH0n7?8w6+`DnXyH7BdnzR-KGDuGQER%IY8vD*{mh3Z@G0ZvV^?Y3SeSg3A_rAaD^ZZ`V@A*UGm7Fu@=X@{6`*dTjdkfI~7B7H0~ Ss<~ghf^r>4&4Yo95f=&JI6TY{*1l4Sbc95%Zj^9@(v4YRG znA!7WH5b*5fKJ?l3wxV4zSr>$Jd>=uIy2;Map5%Q*71Guq7g;9Ns!eK46MjPR#{4H z2*D?sk&Qt{F?CJ|3mZEwi~d@iauSynh#m)>`tp@hI>RMv8~Y5PDRGNTO_?1rDd(w1 zYKQDbaU`g04dW(u1@JE3))aJ>_QThEl(OO5q<797xo&nFLmuK}uybXi5FMng&!BO( z{_fPYZPR3Nrj0$5vTDrk%d(bs{)^Rj0d5%KZG4$<>v%FcMv~tjaNmEp>2d!}qzf&u z!$m;(hM%aeeA7DUqnqTD<*MZuznd;c_bPEM6oog29-7&?zH@s@q@HPJ*XKhM>QH6d zMW7Qd*35?$J^{&IwD2e1gzaflbNz~Goh~3p%)a&2?7oQJCTy(RxA~=)`<^sZ!E_qy zvTFnTqbs}~BPy3>7K3MTeGHY`Ylm$TRSfpdpPj5G9x{&(kg39V1&aE`G8{SbdiNAn z!At-#rQP2Xj`w`^paWVdmIz#gG~u&P4KiE-SR49ugk{yfUK?De#{bl+d#FAE7j zFdQ;laOsL=wb21c2GMexBIHOsJ2grQu1>#M{^8JN*i|j|ZNc`TLXv_)s(#?puBlmb ztj9)V!fKE;ZY8lJT2ZI8}7PQ;jS`rG+GHqu*+ zNe(iK*INdTKf7Ut^_jm;ws_^<_+p%jDpd$N1zsOHh|s3h0B+l-pp$PfUAxf%Ocn26 zO+=UH%uz>xa|S0oWeXYi^t<^^w$uE9`RtlaSI4KJfKm{*g71RubM`VZvvLEntQlU1 zPZtMcBb@nX*hS+@CYZ(|!xpHlLpYCKWrpsSZjrLzL42I-b8limvE7;t)n{<_@$tmZ zmquxpbIx5d1DJ6lIHbnn7ZP`InkA4O@yCnEsCrQpcH7n|hI+8{iL+49j;xW9zI?Bj z%a9xPQz2G{d6s-O+Y4%ih|BQ8W|fq>GX+ieS5D~lKkegf=y^}o-AZp37AwcLms`mn zTsJ@yyl4KrSMgk-#E?(#!ifgOX9ZpSYGsnDV7O_lx!&KiZ<}Yah}p)_!+4;&*wyGy zMpd#v>{FMT>yGwTjLyFIeUHrV^d4XVgJLEy#}7-kdu$*bY}FF}?A>F?SU3_oZ&p)n zEc%JD2gpZJSC|X6t|n?!evvGL{{LIfVZPk+$b@F_vQ#vD1Nj)H(!rzi$;YUPxyR$buND@QkrP+ z^@Br_zjq6Nd*!rS>oW_*NwPRRmLHJZcQFLu7@#E+D)Dfi*zo#Ep6hr!4HR1CNRLCu z)NkFtU+|gCMOn|+Wtp%HITtzKC~~I>k?S=#9oLUb*mZQmKZr5vI0AN#7;X7&iMYWO zU2)T_MeU!~LKXkr&h0<_cmJ`q(4w@|q5d~=s>BE`0MzP411Jb_O{M$sCAgbV*+ngIY+}NY zA+de6=UnE3CaBcr*EeCbd6V-Szb^6vZU?>T9|oI_E5Uj%6ZAEU`@I{nCC)4ffE@p} z@T(Ys0YCw)ll275g_{?<|1-MEJRLZ^izdB`|7Wkvn&-vYHzY;*Ce2o=~CL%Ar{N=pT^z5D4~?wQM+(G@U{ zHD!TOMf9hOe(UDr=TzPv9hMI4UQU|$!QKE?gH}2Mn>-)_;^(bJ0!!cH$`^}7nVatt zOlDzSA(i&%X2w7YQ=Ig^FBwY_w4D>h@kRbI6(Rt+)&O^`vS1ELKZokxd_FyrfVqBWcQoB7dZ>GsI}YV0uXp;VF4X5uZsoYFQ( z6H%s8!oq(mmpX&=U1^rOV0Y^!qpQ|W6hQqI@Yc>R{Tns=zxcfDx9JPBwwUoMN8fhx z1bU)nz(1W`??3~t(SFR<^6nGC~2(~rzkLSFRj8&q)iO= zWl080Pb&L?mN#7A&=we>IXj!0<^;BWF=|q(A}x*ptw^fe;&zGSQdFQ%57T>tzOuD} zdmR_G$VEJRj3hmsv~|MHA_!DsUFSd*rn_hJ`oY(q)UO^z%v!d_xS!CHU=|p&aWR_I z*q#GvH7p71(JWpLz~#>3n~o6xGC09~;>M6i*5fV_KAH5()R0ST1PtDaH0ZTOBJc#a z7)tzH#FmBkx8`OYaw_4hr7!IB4d*Y!Gezv5@2DS6EY9Cs zvnQ6KoisqCe*1xd0`Hcin1sz{4uUd)XunPn$*;t8vxnP8H(LxlmwBU-*XUBj6#fr* zDVLq=uYLp4;Y=mW$Luq{j9E_}JFQo9r{iE3;DD|8RpIAE+2S)e+l26-V*n)8CKmvsJ5%)EfVsZKxJ7c?mc3!pKianp#F$&D+zu zr&UPr4b4JVrf3i~K6EDSy|=H!xb}Sn+je!e=QrD(_kes@`%LAAcuX|i&(|%;P$Rl494NtX1OmYZOn;xa_G)SNLn)cESG#;O%LkqPHQ^MgBYnE%17*F~) zI%UdXW-x8 zDBmM4m23moV~^}2Raz_s9RjXw$^nciC)uCQ%cNlMTf8oI;ZvA6B?N?#4fZ*nap|T_t38=juGj6ihXbmnxSHQM;dQt+PuQYG~u#_B@4YP1nD7!V``}PoA56 z-9BS(W`1yIOXD=909@Pe|0SMla?sAL`^Pe)ND1t>2J0a{PKR3h38d~%tl4%t_=$IBiJ!Hi38wJ4~el{#={i3qS&$pMo5c|-U!@x zcZ!JVG(^0mhK#m@chk)Du&!Z~i0g>D8qvPnraR~gs!2Zva542CB71^>`&QUHCt%D+ zQnYQGc$(aOTr~;p4yS_a=s{XZ%fw~x2>3EYuArb8ymuI4N%f3w4($!Sh1`V_ky`;! z@JL-br^Ub&V0z9@(90g14fYvJVi%9}AOlvWbJ)S~mLO#wP}wAzqs|CdWA(ar`|agt zL3^ZY=fS4Sm`)oB>`8)^azBhUzxFQj6|9)tVOVLBW(+N{ z3Lv?`O*#rZp--6ME^OClC&o6G-MaAT%V&{cVW*^Z0VJOl{Uo;Y&(gSJ?{@^Kib8cM z7XJM9(~Ixz#$E^S)9ajHzjL^9lGX#1D0L{iJPXxGQz}x;NaKKbzxbBAxA1=BTdg9W zL5v53!-qN;)$CksqyZG6uGq|PHN&KJ*@#MFj5I!#uaQ*`WgLJw&!R;5ZuS?ToA}+$ z56YQZhdT!J7zNJJE}}bPyEov>EL>qmk4;!ya<-St-bdgPN6^t!!6kI4#TG$yKS@S> z7SDwgoFHcDtM^4&9VsW~J*JZ=%ThRd6u4b2CK>d*N{TkU)3(X2?oAmM1S;rJ0H^)T zWY__8PIb1R)ZD6GXx_gn!t2+XoQZX@kMGfk>WH_+L%ePILY>O}BMV5XcgBbxn#6ON zHX69X9D4#JRH0?a9tUx7mHK9KmCBWZouc>M{#&M-N*Td~)0_355$)wAH9^?)&bsid z@u6=-P-(2FWCAsnk~bhW?&9Y~&D-Lfp|bW5UgEu+d5r%6^Nyd{Z;e zn+~|O*9f1<>nvp^$~^1Q(+By+f#@6GNT$DUi#x76jP9NjWeZT_m^WZGUH^+OB9E|o z2R|Dv^zfI_@(Ab$v!eh}24#Z&E*5lgEZs(SCCtjb0FkLsaGh zw#UF5fekLzjY<$tTjW^=lg+$SX=_2-su3HSVp9mA$i@1pUUghJItVF7eAak z3+e_{y0({(`eG*1c1xWS$P6T%8bE^RS{c8Ij3 z7E-X9-elI_%tw`)X!8c{8uXK`Q$c45Y2#?P4;r3ef+z z>Y;wHn@aZpF@&3o;UDVX3S!!#6}=0taq}|3Gk16GFTMgqkT-!iy;yV(ASxn!2NpSv zw)vBX^Ba8=j!VBGeFSz|c;NSIBS(rY0CxDq6K~m8gJEX`P~R9v2{r#Rj$$Fdw&q=8 zC}8@nfUqeDJ;0#7Mhwk?$#Dd_;W?c{js0|RoDl+`?h$3GaMCs7T{CgnLyv_m(getZ zC6BbAb0ASzMWJS^VLkfPiKn`tlZa0>?vHt4hhwS7rgw{j`NZVpe$tJSzPC@TsqAxN zdUqnVD|2zr@fshTl?O9mGaj$=m={(b-&+eam+5SobBFDRyMt4-Z+NFG?@W5%Hr_Ii zmcLPVu9zm6CYj43MuapT6prB}16IIpiyfWa!vQHwn|l|r$$OcHS=I;%-jcp6f6iSB zK$+lhh8s&6$V)cDMl=9akkGAqX6?D*(e!5epvN?+oITby+dZ?D6FHN7Tap;R|5Gwq zzw%pG4)efn9~-Fq4F=|>kl zfZb0iTF9u1Mwc%zC-|+qH|R-7#r7jI3=6R3;wg+2XI((nDoN5YyPcABe1udw11(PL8(z}4=ShDk#V zN>m-h{N<&2BES5p&`OG`50JBC3+&X;T=D}%-XOuYnygOyu94q8=mp$JH-B|^Nqv4U zWjSeTUk?()|GulvtraQzmN9LYi4M4es)8agC|sFxHD>-Awsy8IGFF0A@&?BsuBJV(-)+B<13#Q~ZiRUeWx4_Y>xs6AUzX+E2X$ z1s)Z!qxzK_^U< zF+}c5*Wd9{*Wm7Kqt&4U_KZ)w1{-`TZ9_Hg$I(rggH%9Vm+r_zI!_?3i(R&oPD| z;l#e|2|X*I^Rex-7K8s+jD-K6>GpptAWCEGzpe&xk!!^__p`W*002}|3GfEc{{M{@ z@DVq^@!YJ{$ntCO5fF$MHKpnHz*$A*Q>HS{>d)pMh>ie9l{7F03|N$umW`xLTqj{W zM}hHyn1O%e3^7Ym-p1M>Bc-;a4uVZN^(O#N{EnamjLI6Y_OqYc`^xq}CGo9&`;$J# z`g_S5>`L^eu^9<)aSDvSpm7i2+NJW)5q0$j1cg)rHVEd0l$t)gXjuHT$8nw^T&Oak zSCf)DA}S<$SLaJ;x;7M{g;hmCjg7*PU>f}xBXA^lxs;=Gq4C4C8jd7l_l#7%*VE{k zZo^XcFix)$@yz+)L7{6OY1eu1{ z8Q+}MtlMR@9djKo*;x9mjWXV5$$V_d|Sk9p0FSQSepwHsZ@?L>MV^6e8)47Q;d$&yr>8{XB zV8FaR7gOCYKAC=k;iA}XlSyiO>e1!ZF$RN-Okz9~=Tv~qxS!{LuF{I%wxEqqT-1A6 z1^aM!t8;3N1L7Fa%28EJqk4$Yh95*)6?$TDKSm>Lr-CJMz^rVh3 z=OQWnZI8Q=#f{3uo`iQFJ-yJgd6XnAOK! z4f+kbbZ358{s#M=9s`f%%On4&$MZk@TE?^fn)o9&C($1>l$eR+6=XeeAZ=^L(S2B)y~S(V8}b-r~0(E51r6(XYbr+lG6Nya^<(E zb%}M`qH%q@ONnG>2MY}YVm^m-yU`B2G@n}c6tf$gix$I$O@As#%OxcQs2{XDXh=!| z@qaUeli0UJ_)P_>B!@e1Yw+5&YX9pvUC++wirADu`zY$r`H%0`XUEz3{-7AvXV^U( zs8gKY{6xBNhk_&klf-d(aD&!L<4Wa&F14B&(%`K*?N^%yrcx$$I9y2F#1BrGV*$C# z&_5^f#~1l}&_jkGin$s0`Ex<bjK)zzfJzA_?4XVzW)uE0`fI%^JIq%V#@~w_8q`95REMQ(@z3_`e#yQq@GXmMpj!ndu|T(K2N&vdL9{^o5ed3Hj5dB^(g0NV z>|4$JX~UJXKL_4Jro%WsxQqa3Ojc+K2nrJ8lW&4-@(UVgqj%R}vUw4q-60(-fBtEI z8)KiDiGeR0ojZK}sWJb`H62&zbMQAMNi&bVgiyg33uMC0WP}QAEP!X+6xo$AMMpUI zS)V+naIgCgUOIW>{*J(p1HP_I!5Y=B;#1memw7~7CovJHiB5`xy}67H4mGZXjq|v1 zy3_33yDglQmGoQ;hfCi$jBJ;_H-N^ZN7(0|_BEy^T%!7YKM;&ls`TxqH8FlKjoOTh zWEo#fsAN()Uj^xGxG^JmK7ZudL$KC6vTOi+`gb+Y{@#r5$C8`%e}aW=K1*}K(M&~V zZ~ioyMm!MNobU@cujt7$e|n%lU-U#@1}dsouQ7dD+G`iH(Z4v3?^yJ@IE3;yN!1#B zam*^m2^Q%m0}%S+p})^)|0jRXn0qUKddigGpHXxX8>u}d&w!_=k57KHuM~$RU#KOJ zN)M2$HYO9Sots`hm;;;MnRP5;b<`MyAh4kdN8%A4fuxXE|IDj1Fr$g~LD@3d6W}oiaN?ux9 z!2OuVQkGfW)koanBMLwACP>!+Zf3Gz=OGP!B3`MUCz^xTD%<3@f~P1|T@|R>n}&-p zwLetFs@e2#$1EZ!rdKSW#T{Xxi+oHlHR%_3<~`wcA;$w8PWflwlVV5qegAH5ek}$} zPdMoEyjUT|3Wy-czd7uW$9tnY*#l5w-tBCu;H|SE1=&8n$jh9!pU(^RxfE`T|3+@4 z7DJn%yxeu&NR#@W7-P5qOkt?~xR>pTjLS2OE-{!X*@#&{MjJd~S^jCW^cl%6%7G0i z$s4$69qh0u`rfcdeJFAQ;|kIWVgP=CPk@a$MW#{p=lF=jG5vT3dBEuybQmB#hrr8$ z*8>Bhyj1Z^9&s5~c%j_0Ai=@vMUPJ`PL3y|fYq)=@>ZS8(0ghFTAUqfU!#B0unFXp9&uB?~5bpD0{&JJMucnw8ER_Bb#z`YHyQ@aITzgv7E8kB-LN zD$#U`>Fwm&gu8T6AAXEP+{&2Bl{qn*;n{a-HZK^iUuPswMq3kT@J6Z{m_>ozMGGD9 z^234-$MDa`m=aa30RK9N=j7Ez7>b<7l@K>c{E;tKBFz?qA_#Cq8S5c;FQ8CyzI))8 zWz=HAV5yIq#{w&CJ165tOU6Ls0Ifl|bJ{163)0BvYyXd?5l!#{+!w=u{X#kg`V7$d z)!5LK#Y?`bGdu(>0ZrUq&SdK&{Nz0l2P{m1^~0tj`_27 zu;Cc>1N5hM!J?Q!9)OB49T?=aCU{=G!OVdWWc6=T%2{WSQUHRZv8XuggazPG$w1&m zR3%7gys&?DzJYfEi*}GwB;knc{60htKjADW2AFT$<-F>pz29Y&Btpq{q(WU$ z3ewPZ>5=bzr&g_|*=PeN=N{`JshYKG3{h900x3Y{XyGOIL^IZy^pMkSMAZIWcczFp zSxJ737Mvq@l5AMZYTgpCHUi|i!bI%_@b9=%YPrp z?LIAzMV2Z~o&(X$l<4_w*{zq6wTHkl-Jz|I9O}xWw>^SMO+-qqhJ%fdi2ij|euN^JXPwmTj+I5?b4p+3?$xv1l#Ud-s z1#?_Aas}ubxAN-1Rqr>5DcUQ0yb zxc?0sa$;?@jEo^45}ago#sYYy5*?+SF!bxBzL^O={r7@+Pln!?GXUJ{X!i&C=Bo75 zEUL@(k^lst*=W?6rdgD1Mt(s-!MRM|p6fBXaJ~SmLqKgz9n)PDQ624Pb@@2?R0{e_ za{c{%EeuJ|x_o9{w=eXQR7@vTW>}pV(MzGsScnk93aOzmV_Z(J!i5}H_H#gB`wPBX zYEHsX6?gdB4(sS!)5kCGx4y3}>vKqIh7sIjG53CHoH1rfxQwLxIB>jzQ%j9K4w_db zB{-AOU29)U`TeljXSj}S^&&z1MvN_e^xc}|$=eRr^nUrXFJmJE zAAo9FcJYxrEXR_-Y`zt&4F~~0>tiOT!N}gV(IIf9@9~6qdY)!ye ziN9eret%*$u~{xbAa4EzzVXM*tf2SzC`(#Eug1AZ_TN!1Z*v z>q|H4E~tw0BpL)eKKNmx`t+Hcd_dhN#VWcj1pl$5E_3X=hY)C&-mqR3Zy!b%@n*+@ zXra03J6ngO{3#t|&EAHY611qG$;+U~BhYwK?*+To_U$+CVWtai%@?RKQ-tNu!HN@X zWFwze01>&7Gv%|LqUK0-ZIb&$jrZZ2PxVDm0t8h zjhfYnu0!lkr68$3L?ho3W$9athrHcU;f*A}cwgTm9`_+G^n8e(M_M}bm>+3oUY_^1 zRpNbXju5CHudk|d7IUTaCsG3&kc+OPJ8)$IuQRkmDgJNVB-aj64J&{Dv=j_JZ`t=V zV5Pvtz=(>%DBPX}OWV#Y%clOGg&S3$Q8T&xr-#5c+5?8*^u}2zav_}&V|Ez$gp~)F zF@!st*HswOoeR87s)E3gklFU5jieULm8K_ocXxM}e+_4pJw^@V25F71>q5gK2!5M< z&S!k!~oGT=N2++e&u=O4QoZxl=S%NN2ElX3ay0k)C3~>ONU@hiqmJGI4f43&^^7K!h>axtcT5W>a%imUN zFTe%sn|bq9<=1q(b{ooue8wY+$T8w^$3%{I2k!kNfwfJ15j{j3lbHe$5$ z+WM@~g>7!LCe%dZ-|u*gqq~4Y-S}HlEoK$qb$Ii~mpR3-CLO;dUMB@F8}#yjUm@BJ zj_T5&L(*J}mEh5Bf)BrT^S%6V|Ev9u6Sse|x-xntuApvv>O-U<%i(zPIJB2|@ilWu zeEDaB;erd;fGf)YktsQ%Z_`7*gpR78$J3RhMGQ_fv=(y>Ei=3@Fwn2A)javf zl9*aHKCYQsdUABwfkWVHR<%a&yg)H1Rf5@sfe`8rVV=pw#HP~c(nk;{`EuBJ*@_Hp zMw9`x+KTp>ws6_Y?JnwYfeVm$+rKCEQAM3%IAxcM^xmGw{>kKoy~lND(G@tsZJkP# zYT4i|#7rO^V9dSD?*)xQ8y@V%c40RX4nmse#T0I!9C^aV6F{==_Futcbb{O2D%w-I z+p7)g$In`a4cgsxTT&mOJib++!54Xp=|CO{EO57JHJAUf%fn9Yeb z2I+u!zoQw(;)SS+0JDIwp1e4teLg*tN;A*DO)n3rU~U4}c>~-RR~5VXaB+BlffBYi4M>nd2i(iDhD6Kb>X0fwpIDCz>5HXPCL;r_MRhwRPn&}`trn<50KjBKBD+ekS$`_E z8<+nFsKrnJlkfj0O6{QdS8rJa;pnqA;6&Z0Aseakdf>OdFTA~df|Lva&xZcq8E6jl zCS`xMM{)U^Jqmup+W*EA@8PS@cH9 z7h~G@dkWLayD-7C*riNYZvDAlJ=HT2X+7D$tRBJ_(reW&_VI>z zrc76FQ6RJBK$R}B#k9as(hgc=PL7aSh62Xj?PmVGudth132+Ola?4K8I%CWq#XXZ6 zXP^Jjaq8!hio{-D2BgV{jfUcPGIkXb`QI%J-~$3^?1@B|5X@DhM(7)2RS4zmpo>$J z^GOpNA2J-kP$>2hgjE9P1Q$#ge3q7sIYS=m01!lp4~_v;3Tl7?Getm36_U>g)KjI| zoH=Qm6uDl&JWQ6xGuAUWuYq0>kumNmadIX+Wm^?A@X333?Hls*@>h=&D>vdIh5q*I zx7*R+Fy+y{RB`*vsX@2&}V;c77cK6X1H zG<^_q9iF44;Mh~YeX14sAlvHpU3Tu?n^~vmZtUM0^g+8?e!Ek`LZAo~Q4g;Y(nP-t zjwUcggJdo_NyBkux8`pGlZt)q(MS`tB#+!l<=GBC$e0g!bO1>9oyh~ri26L)Wz+PK zx*#u3kC*Pqr68vpc6sTDRfgl%>So%wtJ<2?kI&8HtX;b`X~ee&r8{mucNmqeoFXQb zNBY*@_ucv1O&2TYTuymvaUq~l7Qi)_qAU94^hcls%H~Tkmif)QcR{&V&U)>3(Otb0 zdOWn*zRFuCymO7EedkTX`RjgH@509*4)gg?g!)V)&WY535uC&+1OaUdZ{7*`ENJJ~ z5~)KH?KFCFzQ6~!H7Y`HBB&@_E5Cp|35IUEdfs=2B763yw2Dl8x9z8-;S!FE$EZq= z+KO+V%8CcXRgFUH^9A(MbaI8YML(kXt^X>RZ1ubX0OFzljluWnEuaum05sCSH^TYL zl=t7>Nx(3{XIziu@XZ{d3NjIpuX?=dC-P4$MY(To-tcOGo}#VuB=4vg|OV3|pjZj5!&vdNkru)c5^gmnGSc&W+VbaG-P8V1}c^W&(ED z?4llMxxS)fmG@4nPTcKvPjF8`_kcmchr}4k8MgptwAocWU(R>}?$#wFL1}M8v^M(< zG7?K83aad4el*Z+=AJ|iP;g;b&B=lh%5H}pOfCioUB`<-um{nC^8)&KJezN;&}Z&) z{%PI#`?*zqrc1CFb=nxK|5$1!5@|Wn0q{uY)=L?W*HA+WuX4riG+T;GqG$UafX(@*DqR&(sS*i=Uu)BLa z;^!VuRrtAi`95h`{Znr=^h#Z23hY&Yq7r09wn@o%eE-xBlG0!M&P|aBL!UtC$kF|WoQEyLiuNovy~XV*e6B2 z0zgGTR=NsNqFnJ=ohZzwUGNT9Rbu^-o*bniYH?{C7>btZkd`=;>M??gp8Dl}2_Y#N zyHm)>6Z{-*;I?;c;HQS5Jy_~KGik`0`|ZG@8>!k`L+d%| zszq5AST&Wu@YO>QEV?Fk73zz~;$+u!@ornYGbQA zwmPtVkTKTn?+t;4D`y_3M!Pa0p{R&BXx868Oj7EPEgyLP&gcEx<0bu1JH76>Xirum zZyC49GNWivnG!8e0eIwvG{gV3hU2(r)@MetybU6IMS_(-!bh|MXly)Ha?An(T(L&K z@pZgpmoh+)1q#g|4(*p*V`I^-9f^s4pGbLdzdO+E((fu@_dr!AL8z*641ipjdFG`9 zLFh*x>ou*EXDv?S+(h}NdsA5BR16SCk%_igD}D{!H=4|ku+HSpC-m|7-{61*B#yy( z$V3ZHL*N-}-+*mtpT-G+-ZUF55BCsatDlTelqqP^2#;Oo{KdBlvIfe~Za{j?*v!I= zG4G=Dqq?++sg9q$88S{H^!1KieSqu`1NO`ELt-*d4(hI8qFvhzS0b!{l#4ak8p$iL zU~?A3d4$Vng=4(Nfv_fyPu%@|ie;5|-X@ee`7Cr~$!0ijJ_`I72gMj(w58~Wkk&aP ze~v#+d6Rw6F_|vO+pHp8d>Yh9Wh%6>rD=UZr-YvhU0qicx_`_n(ur>fk!PDx6N-#S zCHtIoZDJ|iQ}1npoZ5!3-4Rmqp9rzAG8vIg=RzGg-Wuv#!rcijUugDy(yP|D@{nEi zrG@sPLCX6P6&cvS&&hF~3f10ayrGveIG-Vb9UX=Afy7`S)j!nS|BzkbbFiesqIH&Lr;J-~?Z?kfd%BltHM=#I1VOR7prQ^BM|t+f9b#eD|nE&)~R zEkR5M7u}iWL_YJOIOnMivGeYa>Nv)^YV%GHj3-$U{3)N)&K<9{Zys%o* zs`2dY#KNi!h}Pp~w5^Y4q7jcNjwy0*R|JQfwzJvp6+zg8@!JaObGaC5T`WwdT)NSml&i>#>!EDT*qmbL1|eUupw z;Xonm72tTBZ?RzcM&Zzgb4uj5X`4X|K@gGZmVX z(#nh}uTVU4$zPhaCTX|E`JL6dq?(0$RKXcCn83|!1d0V%M9H#>kx#2Au`FK*DGp%1 z(25_6kkBNR>xL(B3Ek03f-?fttT{t-!CF%;8WA^A&PZm$nLjekSUaF z&y=vbiulW!QThf&=ISRm(mThI5z?Um`)iFnl1x&{i&=UF65f%bRxXsc?tE3~f1Cd; zpiis0$~wfjQGD8@`==KzEeE|)rD-xRF0Q|tDUJKW-_HBNTo+0)xREX1#jl%)1~>EF zx4%EaOX^Po_0?6;Si?1Gpwr8%cyUc9tm1U8#WzQTbfJ2xWC!W1g@N>A=@!Rfl4{e$ zZa@pj-Ray*>&-v)IHhz}aznC}RF7M>m`^t>K))JBANf9Am7)bMdDz=On(^R4jhaXQ zr1-$7O{*dK5n54i#*~~hLRmSC*M*ji9YI+P0^1Yxn1@c8JlaY8LP$q+u?n}myml2+ zi^F9#RY`HkHiDE_?NRxnHE7K~y57ONxh`tm!$V?fLlU||9AvSJ`J1 zu=UJJt73}DSYxGiK%kqENdU%MvPT`{(dHt9GBiN3=SSWEhY;XAhFp}H=pFA z5qkfsArE@DTzZi`(CwsKb+s0^^`Qqk3IukH>}JE%D7jMX0M^3u%DCx0s_AckkcM@95uJ5jte5k?DL zL^uh$>g$Zu?o89nYbdW4!A(BAk4}e-EmS__H(@*+FL92qhg;J<8DJm`AmH`U~*h}sa59@%>D;rRdDwPfEI-TsZE7M z@fRwdX)`-K*KGZH`Gpelw`2F&c>wv83RohFINP5WVQ5po#-?h1e7vzZ4}W`4=0O~+ zFkO`pRvra3Kic#rEcW4D^IO^S1NyIh$kxM<3$9C239MJCcmbZbyaY+*)$PyDyF#ns zo1fT7-z(hU@rcs?vG{uWxt&c7T@GFw-kHZ;b{?MBlmOyDnIf_;XotA|%`If3U_g|U z#yn6L_%5WU7|N>;upie0m#!uZD@S$mErqUOF2&%=wVb_Zw8v1|%!K18E*t#`GtNv! zYSdAnY7-h4KdIG@E1Gzsn!UwUX%O?FEo{+mM85^t6v+FGtD}Tkrxr*F;$DRhGc&`u zR|6Ip?-=!v)i#-Rr{h0&vtbk!2)5iE2KysjFlxxN%hm!3G<}Y+yuBpaR+6t3*|a@% z?LV;aW<7~nkdYX}*F#+rm?tNvWV|~tepqjycl!G5CJ~*bYKf55pm!Ea#6`PJYOY3Q z*u-DKRusf;L+Yyn*INKq4;z*8pY99)Hui^Gt_;R`Mh@7eZG0-l%b(xlmr~K?(Q0IEvm-b-GlX{VyNsV z28X)9ET<~7gqoLH4dyjlvku5sj(^v0J2r8hGTsuv;;8Ms zG;$QVoJ1z5@~Ob;2HDmt>T(NR&`|-ZG4Q055e-t_n3g^-L>D@n%Y%(Kl>1@vld!m*DU-W_O_>!R6d~mX zd|X$9wZ>&a+tJ{$%Pb$fj+;h>LeSl|Gd67 ziP$LZn#Ohj4xBlk+<|89^H5iQYWibB(dDueW@2GoL-6Q=J&SZ>>##!u*XeD_PYySB zu8USK4%j1V9vs4)Ky;z9TA-Z1hj4t_stxdDCE=4AxAIGvFLEsUu8@d7oH50qr6co& zY78KCSi5vKz=WUf z-?|T`gnnGeyH#y4jNe^#+%9AP7`~H<$T>*Pk{bJDCFo#e({R8bh4v<-mmY5@wHv)? zu@hl4a_7oXE1d|jm6)Y4n8$a+Q$55i2Rrto_d3WbKF`(N;_hrbjB#YJLag@dIZ zUwf9#7I+zd&VKyik0rH}LecE;b&DI-&u8$P=b@-mA}F zp!VF*9m0rp^#P80f&e1#f(1ngG!g~DKW=o_O0>HS{M3w%&m8jsVCy2cN}0zP%aLFS z!DYy5;jwBmmnGk$;plK|{q3Ryy1zW#XR?iP9CH=qE*f_T-jL5dDUf*#V?^Y&w?v~u zHu`g4zYBaHz=qQW@AO4K54-L!KXQJ0R#-oYW)0KRFjptV+rJk|)|S25 zMgd-H&Pc<3KZ#p+&Zf!Sg?8{}EC)-?4{-!wY}+bav3+tPYh=sAr-Q)uRj zolqIxOc$c6?B)}~el^qg)0rD6xQUnk#4rpz$JZz}CiqnRmN{PfuCN3*A2(ae{^kb? zOA0fS)n(7C0yNZFc?*_JLCb;3d;nWre7+3pK03&J&=NpcB$7oNV$ZCJf2H zE!PS=&^kRM#_QD$U(@C8IKD4q!vH?lt$xS;Z(!8F=x;;&%i+Fybx0aPW@as6rrfu6b1)2XQUzK!>!2M8$wXc(2(^(W)H!%<)7*NabUM_ z{nBPwZKF7w3lw_6FeNn-NuHsvv=Yj2R!~!GytR`8LgSPeiOPMafRy0WC>OsDL}f)D z5o13Ef1Me9RB#;;H76hs7l$g{RIIcFa+RxtR#(ncA(sr#Ihs^5AC9k~P@r z_g+IHb20jN7!%96S;)iWi({RL!YfW&Js$la47ETz$Dx~mDg8e6D({7vgOJ3-D2hw_ z_|jFQP@Te%G?r`)BFV$tpp63d0|e!PRx&8UWQ&`vx(A%ol53LqfRZ^+;bp~ys)YFa zVCi$8(U~sVvRq(!fDW6&tYdhxJIh(3L(Yo1?4vO_bi=3ln=MQ`2hfX)OX%+m~4E`AAo z2#9ZlkB^P9>*MVarJwdn<%uRjKV%j0jXQe%F22Ay%$0`{mr;yzK5f8vQZtV{kpGpeEhTo`>JQO3(uP5%*)6HA+O*01 zSU|_vD*EY7_jlZFAy=UX14!G}W!3GtNUhKWfr`UrbvpvZ#CvLJu+btsN>K@=-VwU5 zb1Zt_CX>oz>?SF6j*EN2YWDz5l(Y*x=^gYS@J>7+eeK&K-k*6HJ_kfQsaE2Ud+nbh z3#K*f%Qg-5mHG$1(4*zI==D!c==I)+030MMOWY6YLz3!%F?)^BU|&~K>wt2-v{`t1 zd%Z5`-KJZ`E*|J+ohocMx&q1x1C$_OF=AqN*8lY}X`;*b(Xgp@wag)KS3z1jb$=wRR-^rRI#n}35*CtgC#6hIeSF)$ zbV|CMm?zmGPUFhJ>nUgQ#S}L#L;sSXTbi=X53@~n*$0*`Zm8}4Zw6oq(y$N~X?FGfNpIm#!V42H#(Ubzs|VRg|G;o#bfL;15T?sV>n$r2(o4f!wTr4e zrpEg^s+TP5v9BX(f?IlxPytv3a${h?Z+^`b6XlJ}ooQi&a;?s`tLIIl$L)C~;2EcI zmBco9@699wF)1-mF6!~lZ}zLb8}8vI?XxX)(i3kQq_3hDM&$w@;aqr)EN>@Q05fjE z?cxD`9nb<-g{|J6d;?T1?m8EBy}%8eXSojvgHJO)#Fio3TMTR-k;e~S&+;0JF7#WI zYg9|hLw<<$o(?$ptv(ZaaX!tHHR!}&cd>M*-T!LsYGax@!>Dd^6%h$zZWD#N#k6rT zMZPw`ws(sVU<}HFr1Duw)3j0$ItaE{dJ_#6a99O|nRPH_tWX&SnW9eG$wv{GR8**Z zmbOqBU$#K-+S`^rZ2PglOZM;md-LW!?|aU3&pAz-ZDzxa1OG;`|8q?sDfvuA%pE;* zySYx?iii263Lktf?M~=dcDhiKcLOTBjTUEk!R zUuko?9)V-v{shgGl?*3Qq#VI1)d%^di5%@fB;l_2!kX`O$*%TnPs>m`g{Sdl9dE6@ zsMOTN$JZ_q-NBiwK)%RA@4B*IH^baLE^>2PJ40nIknMYe@N^+@9kt4e1EC1V1DxP( z{)Lx`NW0;_fK{>I*vzwaYtA){O(sGP=ghA!OON4?3U8RPR_V1GPJ;g*{nhd@cjk!p zTSoBOL_42xVeWQPu}G|AfOc^Q%q$lqm&u1h!SR;`qI7~z*#e_9&ePr%lD#!DOX1sTJk;pldg-Wy0^fJ zL?1SVmZ`qSk7BnVmz5H{WaOgDR$pv*2*PA43=usbz(iXVnrye@j(h zZ(IaUF&Y4T)3Vy(B;v^8ssWe1k(MTIYa<@Xj(z*E>FJ#-)Y(t^IGryR1M5N}Dry$0 z`ng%Xj^`OTuLdxm;Oo?-5ggYZw za9TjVD#$S>rm9w3lu+rqHtA`wC6W>tlzPgk*!F=#;jEK%0RV-~Q~noRR6r}^X6i 31kHz + +crazy_climber_sound.vhd Music and samples logic + +kbd_joystick.vhd Keyboard key to player/coin input + +rtl_T80/T80s.vhd T80 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +rtl_T80/T80_Reg.vhd +rtl_T80/T80_Pack.vhd +rtl_T80/T80_MCode.vhd +rtl_T80/T80_ALU.vhd +rtl_T80/T80.vhd + +io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) + +ym_2149_linmix.vhd Copyright (c) MikeJ - Jan 2005 + +---------------------- +Quartus project files +---------------------- +de10_lite/crazy_climber_de10_lite.qsf de10_lite settings (files,pins,...) +de10_lite/crazy_climber_de10_lite.qpf de10_lite project + +----------------------------- +Required ROMs (Not included) +----------------------------- +You need the following 16 ROMs from cclimber.zip + +cc11 CRC(217ec4ff) SHA1(334604c3a051d57440a9d0bfc34b809418ef1d2d) +cc10 CRC(b3c26cef) SHA1(f52cb5482c12a9c5fb56e2e2aec7cab0ed23e5a5) +cc09 CRC(6db0879c) SHA1(c0ba1976c1dcd6edadd78073173a26851ae8dd4f) +cc08 CRC(f48c5fe3) SHA1(79072bbbf37387998ffd031afe8eb569a16fa9bd) +cc07 CRC(3e873baf) SHA1(8870dc5948cdd3c8d2fe9e54a20cf6c311c94e53) + +cc06 CRC(481b64cc) SHA1(3f35c545fc784ed4f969aba2d7be6e13a5ae32b7) +cc05 CRC(2c33b760) SHA1(2edea8fe13376fbd51a5586d97aba3b30d78e94b) +cc04 CRC(332347cb) SHA1(4115ca32af73f1791635b7d9e093bf77088a8222) +cc03 CRC(4e4b3658) SHA1(0d39a8cb5cd6cf06008be60707f9b277a8a32a2d) + +cc02 CRC(14f3ecc9) SHA1(a1b5121abfbe8f07580eb3fa6384352d239a3d75) +cc01 CRC(21c0f9fb) SHA1(44fad56d302a439257216ddac9fd62b3666589f1) + +cclimber.pr1 CRC(751c3325) SHA1(edce2bc883996c1d72dc6c1c9f62799b162d415a) +cclimber.pr2 CRC(ab1940fa) SHA1(8d98e05cbaa6f55770c12e0a9a8ed9c73cc54423) +cclimber.pr3 CRC(71317756) SHA1(1195f0a037e379cc1a3c0314cb746f5cd2bffe50) + +cc13 CRC(e0042f75) SHA1(86cb31b110742a0f7ae33052c88f42d00deb5468) +cc12 CRC(5da13aaa) SHA1(b2d41e69435d09c456648a10e33f5e1fbb0bc64c) + +------ +Tools +------ +You need to build vhdl ROM image files from the binary file : + - Unzip the roms file in the tools/cclimber_unzip directory + - Double click (execute) the script tools/cclimber_unzip/make_crazy_climber_proms.bat to get the following files + +cclimber_program.vhd +cclimber_tile_bit0.vhd +cclimber_tile_bit1.vhd +cclimber_big_sprite_tile_bit0.vhd +cclimber_big_sprite_tile_bit1.vhd +cclimber_palette.vhd +cclimber_big_sprite_palette.vhd +cclimber_samples.vhd + +*DO NOT REDISTRIBUTE THESE FILES* + +The script make_crazy_climber_proms uses make_vhdl_prom and and duplicate_byte executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux. + +Source code of make_vhdl_prom.c and and duplicate_byte.c is also delivered. + +--------------------------------- +Compiling for de10_lite +--------------------------------- +You can rebuild the project with ROM image embeded in the sof file. DO NOT REDISTRIBUTE THESE FILES. +4 steps + + - put the VHDL rom files into the project directory + - rebuild crazy_climber_de10_lite + - program crazy_climber_de10_lite.sof into the fpga + +-------------------- +Keyboard and swicth +-------------------- +Use directional key to move, space to change movement, F1/F2 to start 1/2 players and F3 for coins. +de10_lie sw0 allow to switch 15kHz/31kHz + +------------------------ +End of file +------------------------ \ No newline at end of file diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/Release/RiverPatrol.rbf b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/Release/RiverPatrol.rbf new file mode 100644 index 0000000000000000000000000000000000000000..5e6a519efe1d7aa2974e8c981978091663f2a8ae GIT binary patch literal 286024 zcmeFa0eBqOb>BO)fSjcx+dG2=G+0s8%mAW?kSr0Pqptb-lHDblKnh&}lAX|r69H7e z#!1>rjQhRnrC;m4yMu6Hf+iqQDU~=iKq;;qH?gER{oI!}1}G&|9fWe(o3(Le(bMp`pVZ& zef{fSd*Q1ue&ZW|^VOHW`Qlf<_RX(<^Q(XJjc>g8H!r^U;y1tcwXcnjzj8%?=kGeC zI%(xm=U3CK<3M*Ott_48UCvSUB4R-f9*lJaz(-CKE`mCc?N9ZK08Jh$A+ICw58@?R-s&)A1oc|Ln4{>_3T$b8*FZ`?LS3Z^1m+>j%NtVBoHySgQmF%aajK*{4h3>DGc68E8 z8mc6BmE@6hYpRp7$5iImN&880c$D!$ z_e96aqxhga9hI-7^BI!zm6Vs!k+ql2gRH+W9 z?4*_S=v>)4{yUO*8j(bs%4oc^eBIOaA9j+?vy|nX?>Kf&nk98a;jDvbP?9Vt>8AK0 z`o&9)iIT=u*W!teN;==wN$s3=-m{&gTj!85c2?t^i*=;GB8iTb_dnc8$`=iyN%J5Z zyPqOu^Wry1+4;H0FLqLvuXm*(k-z|*OCwEHl>y4?VO!E|Duz!duo68iZs$mF-fPo zrSmNPQYYzph@|63N#euGw30W<{}WPnU;H^p%C2?P98?lL8gr!;Q#U7CG)`(y#}AQ2 zik^8RNo6Gmq9seOBp0iVk=kFG)SgnCqV{h)r~UhDousRbUt+On%TmVkl}GV^WzxNs z*DGnzxyJo`G-P>NQ`BBYn`G;oq>Kg~b$y|9u0B~gS9G4Wx7smlFS{?=)we8P>=F&i z%hH8t(*1Mk&>EY~g>!kMwxv6jbT0jIAL+l7Bx`#~I!Y$9^p~BaYn^8K+3_Edv}UWm zEKl=xWzxNsNqt{=-KOXaO`=t*N#dQ_ z%F;(j(ihpa)}xHJ^Bq4=IzWb};eEKm8LCaF&Gcv~lJA@!V-l$Ryl5)DeCL-v5^ z)beqtleF$=oyn5!W#>Bnf1Px0p6F0|ekt@=JvUnl(=lCJ-Vq~p6tqD4ogcawC?=o8JdA2T|{U!7-jBV&fHrN4BPJtUo` zq`BTtlCArDB+bJt$(~*avN7b(+-YDr@wxf<}=i{BE^N*2qlwJK> zBpv^N^fM%#XL-8Ll4LGRlEEygZKaG3sXJX~JUy2V^-pbQDWgj|;|Y?E`#R~jNk7|3 zS)SC{J)I;TJWSFtOS+|V(V&#sX`;8C)6UDrPQ222c9dPF^ZQA+k#z5!B;{pm=B*^H z=SrHxvNI$DuavT~;)mowvLxBpx}o(&N!J%jS~Hch=Twh$S(bj8l<6xSm7mQU9n~i# zo!?B-@vS7uijwHiQS(_x=?UfOsB0yiD=$mR%hnmuqdv-h?pl$u@yW8@Lb{QZzA&jvt&mr>HLRD?W^|hO8u*`Q~N7Z)}Cm}QkJKq+ELQEXi`6Zmn6B$lCIB9 z$IeN|Nh`Bf(x7w6Ue>;jYEMb$(qWP>=~n3)CC&T)Mp9mubbX;D9<5B8vznV(QhVo1 ze?!vTTX|2mgwpx)l>b~O>HJdC%KEOJU**764qWBH#d1LUPx|z%=j#`Q@>f1yTzSFy zr$211yA`?HSDats>E{oe-kQ0@k}rRJ`TNJu$*fp=?wrhvyIlU8vvm8#6 zFn{Lqvd)Uj&wuu^Dmbg~)v-K_9T#x{#~K&$*hM{3dEpO#{GuMbsE4j-%32rIg^PHo zaQv4vmHfKvcri{1ZU)x#=5#T&g+mvcI;xqRGgzCgInK8H&i2f^x;Hu8=fCYY zfAE%}h-ZKOu)iU_zpOH6ALHk%FaFe(TRc7n?eUTH{^aq&SUtS6b8-D&ui1+1EZ^|) z3r~)VeF9CfX1db(M(JXkz3_8ut->zc;zd4jm9UFs)al1wHym55WwPSl_HSNGVEgpQ zT>8oDW-KqAHLH}k5;HogA zmh$Bc?OA2lQkT50HqKrP)EGcogL7Vs{4z5!=%r{bvzGG}uPi)s73*F@th@O6|MZ5l zrs(BdpvLQKrg^+S|KR1&a(3A(&{k;2UM}zbxw9#~oU8wpy?jNJeE9|YrI5?%+nKVj zn_jM&N%Xo}D$fYY<(#dxL$GFc_thAaOCHvW>wVW_ipXBgU|u_u{7MZnu~5-feR64{ z(_U!4^-OPi`5F;@)%5=BOB112dK&RsvsK}>*dBZ(+AsdzS}&v*-|_{Xyh_*w81%B+ zuN#i7*+S`D#k*f7MX#Lkx{tqGrB7;{Pf%vsxAMnZbJ z!kAUF*P3HjSISjceZCu4vZcIsDt4{+C$C(}*3Ry3uOw>+YOiL&zdqtjUQa&!YXloh zeZ2<8vGdx6nK(UfvF}pamnExltk)|Cp5e8_PgbL6raq8-w9kL+ZRvou`xX7TY4@%kGEG&htyWI6?Zx5#Q*GS zT~7J4%Dy(QRCYplt7kRUxj4;;^W9vL_rJe?#l@>Wy>i1$+C2If?f3l8>EA0xlbrMH znaky;ZaH&txo2x_-kyh^*GDhU)A5VQ`deWCMNn~`N3Iff9;Uov*57%KSsiP3;)$b!|3{MG`yuf9|H_~2T8KXApK<>h|? z+`0El>(&hI?tJ)Z)kWiyZoGU^-hN5t&wBWQKmGQzt}o}}<%C^EZLb@X^fGvKcG1@Z z$6i%Pk`qN9MaMc29t(`7;FLX7^UN3(x z2O&6*eXP*Sm)YZ&_~>%4e~BetZl|wG2bE6<{JdNu&)?)rQ*ZA3;&*4^(Tm2{e?VH=59kqWu=k{lJ>5u13n*H{#=kz`MlZy53dv>e+^EoqL?)>>29iMN! z5ZJ$`v%7Ji{Vnfry-Kjh6}tYR+MVs*aDCSkZ(6gdrcactHVrR1pLMN{NUu$5zo))7 zbzQLw?)eA{SB((Kn8Cz5Z~DZibLY)}HJRt5?A6p`%dGWE^Qs9sx8RjbSh!|W>FW1R z&K>s)TwfLb3oz(qx8c~@$?IBw?*voms(rq8A3brd+UJ*R`d+oquiED?)1l|hxN4uD zmo2Z5c^;e2e}%_i`PPj;{C6e-M(*}1>AGKC<;JVXJ`ej}MJ??jufh&neW;gb{_CqI znC7*RgC)l*zzTq?e|9RYg+kFy=K^d@ypY>s|fm;4T0AfL0|Jf{h+OtHA$~= zT=`|txSEX!P}50g&a#|UkIRR8R=s!0H&&zUOhwWP7nyEb|G#{(Ils|=tg*T;aFKmG z{n%Qsf~PCK+>@(>T`C8!a_rS{?6QrG^V=majQ{gXrDyf$FRa*BFMIBtt8#KKM=o@I zWpm7k{6e<&o`s-jwF_UiSkzq}I+GnZL8p*U=JF4pwCtePLf%&GBj2Ixcb+kIS=NQb zb+VRN>}~5o7`ZE|ZMUJqN_96m@Kk3#?bJ)NwCC4No4`U|j~4QE+`o3BVrxkFsx@oP zhTIUm(!PeS@YD~kw*~o0JBEj?LFW{u`f0ZgX*O9(EBUN+=yDF-0WGwXFJ`EGz|V4N zkh6BBrrpcabf|I|Q_UFPF5dnPob+^sEAt)a-hX!HPeY!zMe6Dv1*ou7y)CW0tR9xOZqB^ZcY}Ywi4*n2+Qbi?S3GyAj z(q?GdX%{j%Q&aRHd$zcIdrPBL7!}1GF{4|OGaJcAAtUk9^_i3vC&#z)%56Wi zRO?AA5Wchg(hKb(*|62AgnMF`5;dPDMAr;eeU6)oAgn{@S*^4msKcbXyZi_d`yB?i z^V?lk{q3m3jMy%8Quq_mHfktR7te%9=dNw_+B~_r4!uI1GLAK<# z?}(jkNz5p3cdk?J6W4V&DriWP8k44NPBNg(4-=7GUt`88S*j@Tebeqxho^opL;sK; zZlMV&0+nziL>s{ppTwz{Ri{!aEI#+wZ=%n%)@in_btQuKS%gATLTePFteK=wmUOu0 z6b?y_jk=(!X~)nWwZo^7qJCWjaD&p+M=hbdeEcJIJNubV_Mbzt?R9=NMA<(t-{zef zbNcf2$U~uLH#<+AU3x`Lg*{&)4tHu-D;#g_51gqWs+pWKSevam;Zq0QolkfrcQzIK3aIXe z+^2M~!B-2;_x3NQCF5=mSPV+8|Dm$uKnmTM>a0LcP@-4!p6~FO#)fmv2s7U5=s(>@ zU8)3$TIQjcGZ<`ByL{kqe073O(fMMR%Xp@t(nRT1vm+HK36&U=!rx*Jjh9ETps zk*&PWP2^g?A%nl*6_#%m!O6U7)0xX63KL3x6tat7x}OPwMUzBc`UU&>*#K zD(JZ78&`Hw@}1A$-7WIr?wKK>8VJ)|u`Hts8f#aOHDjyiA)BvBsHR1~%@Wf%Lj&*p z618ioJ4-=W+M$4FsFrb9QMr1nu@*a^(bjE+q%-7JLNpI)aQV0Ik)B-)U`{b1V-uZ0 zV127JL`yMY5|>=%mzFe2wk@cwm>jK0MoaF_JQK!BLtO*IEjlz?qdavv&IU2<*f-Yc zJa8((DEDp2(AGF3-Kj^4iF&lD8V6+lUi0qy8youJ;yd|v+hcnIMQV+ zlQkw(MMycl|DhuGB5PAen`w*rBArX+)NOsA{y#dg2oyFfkW>_e)mGHet|ka7Esr@> z$p^-Su3@HAyicakv|CBMe3PZm+A}(4Npl&pvh;zQucc@TfhwKS46K=Pxe(p9Q&1F| zD$SD_OpCuxWptEQW-Ym47a8i9(NXks&Wg)8CH8Fj_OCmBVboghDfY;0&~(#aGla+j zu#1;z8{5HjHJ?tqG~c$((08MwheYwrqzOX!6Xy7pfoxl|;s8O|9<&zI8YalU`fGF( zmRq0}Q)3Ek+c0gyH$P3MBQ5DOF1Az}%wQv+q0(U5qd)jy*dVZjOm)VNvq8y(QG{Vm zD~OYf0ohIMzN6)rpZ#k)XyTt~(gBE;*z$mric+cxJ==SHKbs*2@?7emsZ@+a)q!&C zK+!-um#gI;`TLyXQ;lk^u@fS-Ra;4hSosW;C zj9~eTPrxiy(P@ygl)->dy-zEgMu7)%aF~1jCrI29tF^$LZmjIIH_BnTf$iKmf!Ku+FgSpTbzzB22>|u zggX0h>f6<=O)!~rs&_H#o2@>Z@$`gi8KQDKK7D_-QGkkLCPAepWnUg1P(4pT7vsV` zKc!vKDgBc+5mRJ|W_W~*)70|>IhHm(?A-YKd>SGnj2tDZp$JJsVEA7p$kL^iqxM~{ zI?2k7?M_|oE%)5kxzQOSiZhEPob7Jf`lODO*K*U;30bIB3pLw%Y}0|&f@+LgZ58M& zf8u{=ocOO0FySQ%u-%RcOz$+SN>Lq}1fthyunR#V8DVPkFqJVrMm57lm8wIyZ<&kH zR{H&LU0WEqZL48$8AM9fs|2P0#8jfFDF(d}P+}nE0Vlg`ht)Dpcq69m@y7%G@Ua4!|8~pD4&Eq9JzTccqcgj~S zJmIBs$o#3JxU9RTLnMB%j8>UeRnthT7eb++a4Y7tLvBX&3b z(YFCxwWo&siZ+Yn6jUCRWVL0;%zOL1sr<1PRLDcc^E+wWvDOscSL)2jDYNbfzqBAf z4ndPMgyU+tqbs?YV*imJLFSCSm`u90D2kKIK|r@eL`e=HURr>6LD$nd5^8Hy>j!Xu z@z+JJHFs1%KC*3*=MC+1MFko`*7AXW;52BA0!Gi;1cCI?dfQwhjp0)Py-Q7~IgD~B z>}t(>d(D)VT-9bht9CzZL$+(`qpm_kuIm2Ljkagj=WR0+Kh>^H&eZ$bO$W{c0p4h! z-qQyfMiGy-5JojbO>LjGE^$_(0}i#@dTft`G&nDP#~a#eS<^;}g*+wd)}hXob)_wr z9XP9@3g}D0dcxM9RK+AaLv5pC6_4WLaWeLl?Hc`QH)PbyxW^dLNTE^5s^U#|B zo3AY!bSrllMw?=%UjwBffuT0xnBh5qQ%hJ7`n4N$c)@ z^?__|TRK#y!And5Zg$FAl91L21l#)2& z&ZbmSZhdrXq80D@k^EJc^>5#0ts*3sot~V$w$-kL)hNN{=Ay5KQPS3ml2aKdn)R&4 z%&NAXYdEvI6g6t6ndG=V;W#3SHWglY*Z^*xaN}P}UPy5ZaR8Lr^f&+`KCcV9{1#iNr57;MI2$-arPS{`2pt?e98Q20@ zPxTxX&{=2sk9(ak*N9P;c^tRSe~E4X{6G3qXSLGZ`Cw<&sZMNnYEG>>>eLE@+^bc? zVlgVFMQ^*yz3+b-dcBQbY;@0h@!)qKJy=mna3gTgqpqgw(cPHZa;bFQZ4nGFGl_?@0(iRza46;cLl}|j?}j83X+cv zR*$BegSU;|SWOz$bv@4J#(2m6c1{rFvjA1ZopOO`iQpBY_BKvK5basWhX|Vhjak4AJawRqr2t`$CeiUZ-2b$~R$VZgAd0?&DAipj4s*;MWX{eY zgi`V+4265k_wL~wq2v5TupKPxRH$8lnKS2qnj6KaNS36^(=>j3*`QO%CfZnC`N zFLW+LSa+m_Qh11Bkgh;2aA*oov6_J=7o{sqqF-xBl(g!J_IeKRg@Lwpt6y{u79RVn zyp$D$wbf4(TuPPl>loEx3DPN50?JsBO!-u4RggUw2GUkx_LAOULfrAgs>mkXF^-m- zkfRQ?p|AE$H9|9Fw^Pgz%TmZvn*{Ndvm{>r^BJHmI0A*!$Px0SXHCkMTMJ%Dzf&25 zRmt};EdZ2d^an4C-n2Qc0kH&9mZJP7P8^5PseknEorY+a@d8bh z6SGL2A<&2*E{K1qVTC|P+S_%Iva+5d*)2juJG6?Md%`p5W5|zRT>hgpB=~{3CW}g* z@2mz_D_5H~Q)uC~rh$(ii_qET)vWrKrU)^`hD@H3Bq4 zKUf;+K#-~xvaBevm>{Z~;hW|Wu$mSz_AZhnhC=$YxvcSL&)tpVBxF)h4w>a2eBp}P z{UC9YI*ZQ7-)V>24zuRB$nO8R25cMK8qS zimp^UgJ91(KcOp`J8|bV4UtbH8VOD1G+YYkB_*IzbT{1&xMpk(i4=j#avL7_r%x$+ zIx(6fPVpmmvKj3+K~yZ?)fKAhgEy2_Ulwz_qcu{H;4QfL96 z8xH} zNGl-qu;A$wYMA!ZlK#HY#N&CN`LQ{OT=j1K$d_`AQo#3n)$5jlgGti(=q{xa|c|3*H}>Hj15L}NIp?{1LQwAsl} zPD8WF%EpBLtkp^xlb%iIRsGIG{l7(aZ`a|VX^@+GN;BGy2^9*~q z&$g^nUSg*J7$BGivuI--Xm_O7LM=G4__@p%JZ^kkbW#8qBER}X<8E+}hM)Jhf)Ek8 z0Bht`hlhJ`tp%PKcV4pyS3lI8;?{x}?q;KV=x~n{zx07Om)r*ecmyAOKo?bF=Dj}f z0bl~b1)@M$07)%|9{#vd=s@R*6pA<%a8Y`pTu!ll<_Dbl$UZ$UYj97#%*OsFE4E?v2&_91K9=WI~O9SUY5(RNd98(;(F? zCkZ?XAR;IOasWn+XvWy}51nc_vv>z<6TN|sk{fT0#0I~3;$5&oK*N-T1&V2-Pd&73 zhU@lmU?~f9g*fHMT2iPYhH9w~d!x1B)lVgf;}#h`0!g?I>TMg) zVkU=-Qc8G89lmqF4Tmw0AzJL$iok^!2knmY((hj5tGwpHalw13flz-;02}-;@XtQ0 z3gD2CDw^cqlvbk+Wd|t>YZ4fQo8CI=w?<#JP`@;+VplBqXBmc(%Aozi`xk}JFWO#B zjT)coY`DRA%K{{m#$oQ&CGBItJhgx(W^3w&@ERL+a4Thp4v(;OxT)cUIEKePzn)vv z{S*S~kSUeDIl?ImPZeFv#>mhb*3yJ30psEy8~vo(a!4%)|U`PS-V)Jqb6n> zt1rJPr5ndac|-$H%7ru?%=n|M!$U^cPd(R$VYrLvmxZCyxBw%TN)g2(NOQ;j<(q%n zqCYbPD*50$Z7q4I#!3&wgD!+G5XS8ZQ!)1$*0fEjCPLp)dlzjkc<5GXecflI0fFib z;vkYCIITrb+!wOsoQ{KFN?`S%#ogo+|LrZ`Y6#JRyIdEkem7b?Q=F{?#ll2xL5EdE+oY8Jxildu0F|U<_ zq3vOaXcovl#n$F&2TO)MabGAciOGStE0+zocLZ_eAB3TLJ8jAaDVAlCde0r|M&>bO zWzk7H7^KtSn4r&DU)3L@T~ljzVWy-srKdw9orj?-+Y@JDAEAB*OGYX|imB5Y8b(ki zZk@Bda|cs}j$y-F7c^y6NvuQ3(v!*ut>eN&h8$8hI^{6vQd-_5_}A?1aT?N#kj5Dj zx*OP`X}4F0JMjn$?h_HX+vRHt@)4Gmm z>^71C=G{n{RTwEi2@9u)ePkpTrbvLZ{2Ol1ND>XPbZN_;5ur30m{3-d$>Ju8 z9LLi_DJBKb2^VlyV{RbYF*Di{!(3x7N3tR)ZxC9i^8ABL$#zNweW)GmSZY+GDf86I z2vj<(YfPqyLQMXg!=L_5p{+vgu)>d1Br9=7Bm%KqBKoe$1bvC~%^NBV1%eZJNV>1k z9LFyfd%QdDaAh^taWiR|P3E9g%{vSx6o>&~v;cbu$!XDGIl&j9QuIyZ2nYpgsD-S~ zAin7cUFDu&v$!7Rf)VG~L)ZA!?eUBZ-inv^igcs!J`dHv!$kVfA7}xFn}M&)DH~gv z&PPxj)=&}&$6hBdfdF1#8xvoqa z=O7)VH%=u%rNIsZp*U)DC_YT!LQ+GoFt!+jIR1W8%GDe3Qj*GIo55;_k9B-U+g6e= zf))&r`grnA-qVl}(x{w#*vOzc%=xy0hEA>px1_X1t+^pwv!47sazx+b&`)y4>|lu-b$hBVqJR(}9)bal zXrO^s6~=Q)qAUy#6jp*LhRD37+i4z-bVK#K^E_Mc!h6hxU-%jW1MdJCkn0K?2CN(C zUacOq!{ntQ?TMvYOZdNRN)48b#2~xnBt`vKS~=88E{t^ES7=Wf;<{YEt7g5QKpPhVq-v?mL4kD|cI+u?PGJsfU)ePO4E_UJ?B2Lo^ zl~DkpXm>0&k%6Uk*ZKJS)$0P=F4R4Z7}dQz=!0icb=!;e{|)mw&ZsQSWhKJ5T#Rn$33iBb+e?vMB> zO1Xq)4U$a#xQ-IcQI?go3&a-tuuj=J>sOMXUl?IVgeL3gu@Phy$)s5F`TjSp_gnyu zYIQv5Jw%8_HSx;9+*~vAyh*RW>KzaEc%x+xnZxt|ga%ju^*{|XV-y&|bZ-*L(PaH5 zf2P^!Dr2#hMv|sKdMMeDB%mXJD$Rir(6~}O*=RnKG|gc@MceozAPc1jp=XvhoG$X!_zl1f zRuH6uftb|HxPFrz0iWH}z81j991b|5VVW=o6@L4t0<@87Zfp61`JLNa@o*AXgssH> z%(hPjBf$`ZJ8&P^h5x6G;WA1U94Ofr#Z3SDfN2~CMKO&W1jgmSPnPe#H>|oWaD^%X z(wH!q`G_WD8te^DcIoFLAQFp(+=_H18-slLc6kLsiw_y=$2VdZFiHEW{=Bf1*kAFO z#ZZK!to(mAdhVre{~$P>f2>tCgh3EdQo0AP>xH1ye3yq;W$JrocC~gU3!W*U%%_A| zz(QV^c;0&|*p~M<_ zd2j^$Wp87OdgbHJ_oU9yf`?nXbt#yShfWCu*!q|ko+_93dEwz0=ktX!(1YqLHQkto zfD}SGSe(y~ILjaTeW%xLR`b2CDVA(>Nprl_yC9^c*DZ}7g6Nj#g8&IcP>hEB>h^%%7+KTOZpZPEqaQk-#KdVQF0Yiug1HxC4|!<9eY$*wR$%@Gzb~oWzIUO2`BM z9^)O3pBoK5mJ|;=?8yN0-Wy$DSllAcGm46Cz#PFI3?GC06p#QoRGlM2<%Vdb27Npg zBs}i7aVUpvF-ryV)Ma@C#)62=M-C@4xr2RMQdKiQ3^`j5!;!5pa|>dH2|$@sKXAQM z#6&0}R2Y3MrRo79g>T}u1*#21IaCH^;YoDNUY0K;32Xd716-(C%g@6dV65M5(GwOe zXGkGSLvDB~DFY^A0i0~+)C>9v7*+>2LHCwo*5&%CyxvwH!f) zZd;ydzl{(fQY@aSY$@Ofb!k6+DX{Q`wB5zHf#9)*$%^#CxSAizrS)fU5fmvJZ|!p6 zfR+hXhxp64zQLM`fhiJw(}l?fHi5~##L@yybQ!#{4z|I30rxpn1AAbhC7GFQY3heVVMbtz~D)kXWsT|?a(qaxNm?_cl) zCh9u~#?eD1WEH!LP))t#RV-s+rRkh;n{*SAdtO@Eb+T zGec+s^9W$5J2mzt6qJkf@AC~kVCuU~1;0Q6JDWa=Zl3r1j;8bQDj`Q|eBO7!en!o< zpoP-VGoUlVaD-!9J?<|?2fp^ED-o;t6+W=P;^X)~UAw;cxAKMk^FTFs{pFi5b}pQl zX0nN1ITi2UfoUp3?Glp7YLy9QQ=N&_ZO`s~Fb9S(>am~p00B0Ai8tDEr?F5bSVIfJuXaQpzFp-Y33^VT%olp|_3#PT?rA18ge?Em}g;gXx0gpebyKJ_n{ZL4pyc zq?KaKVZkica5Z>gF8&iPB&ITLHknYdT##s?hMhd*#@2x5ZNdBAtndXilIp7*C0O?m zp>9ABuHPH5e8FRMrUAb(b{`e%xlgXJG;oX(Gnm>uzfQIrvu&igEe#N7p%C(_;ifJSpQ= zB9}#o4m(rTb%j<$gLEB&@s@GS!e~jsRwl)NqrS~af?1lPP(T54gpWW1+6rqua;6j7X2SF^;Q=lhqr8>?agK10vx#Us5pc_cq zw8y9ih#ImtjN6&>+3A}hW~4>EcqnMj85XLvl#64`2|wK3=zE``=VCW|0j}VH5F+Y~ zx;Z>JRGo~L_xwGlTmg#%f|+=DGp3gsE&$_HM_VvKyOWmXh*lC|kb2tvG}ChR9D~)I z1h?no{)RamG3X;E>`EUsOwh0k1TKaz(oMiR_{%)zkFXx$=9U$z!=t(7d$vFdEu@N$0HI-6 zkSX%i2sLAUNLr+UaQm<5T2?k#6`@$B}zpMwS3Zww{ z=Wql$VD}VM?*Pb-+*h#UuhvDkFgPYHGHkb#Y<;wB=nmRK1rbuSG2eU$aWxJzi9Ui4 z@P;5_Xm6wNgb~pX$-EW(17H01f*X2wP>H)aC_09z0pYHAvoVcVAR8G z)I3NH^{K;3kR?$g2QD6ho;d$O%UQxFd3)|cdBQ-%h@2^<4M zNpaW}qEnp&$Q%iIVCx$le{K=9yNV5<#Q>FQ*q(t(yUQYm&<}x*3|XBzQvITc>5Nkc zl%}_)p4&L8%^fkMiP?=E2@Z*+aIdfZe&8j544@3U+Z^|dB> zH{dv$v^gH^_j&srLPLXuT-51@?3OLfduR+9vpG;$BHFMxS$(E#v zGHyQRCnIbbxHe=_x&;h}=i>Xfb(cmx(7meH26E;)K#s+4G7x74ki+JXt~THgucM`AF zzOVy?V!E7L_S})bxypM&-tr7Dz5|NugA@BagM`g{k0iTsxIqz)Ke1<&=M+D%`QX&i z^hrWxo-7{*!YQZqF9^XYxga>EmQVIB>`jxK_b5oB=kwFUq%Kq@S{g42xeU(c0bs33(e-QyH{-7yar+$Xy11XXZ} zk}&!Vh9Vj4hZq2g>`OvW3p?60hT|<3m6U1-lHHb%QQ`g&AQ@RPl*KW?j_@R&*g{v@ z=+53oQ1`(k{H=G>^?=Y^0LE>&so?E-zp$>1E~;B*Gx}y6Gd;1!#gG z#eJYD90P8mpccV&`u2tXPs2Sy@I;J`ADLzW@ySwz!chEBFqIGzRJXv5`p^=7p_nwt zED7iG$rYBwIv{#VUGv(m2&?AQ&;6=X1S0c#v4PrAM55!7AQDKUw(W;Co(!}ecOqC6 zTf&Pq4x~9v4NHvILZnd+D^luvtQ8B=5Mt34HtuN|pq+UZJa;xp=VL7e8YwJQK`r2J z+*V}EiGTjaF_=&qhXn%7XdQHGik7DW7iLI@+Gt6*fh)!qGZ9440f~YQfp?&UmLh^H z5RGVSR~;^tVm6BGyG86@+?zpBg;3hmrR)%6^WGDvD z8+s^Um`m=HNrMTXC5|{ITD2xYh;naBS^2&^*=U3*o5%T0Nrs`zd z*06XDc*YcHk0eHeK%|ZQ65u^2xiv9$WVT|2AP&{QG#HG)|C|D{PRPz87a0W<5$d$* z4Xi;s6G(uJlxieJ3iw zp5BQG&oHFn2r-iEDF=I-6_YbVh(xWd4)1K`(l9sU0yfq`RrbYH&*CU}CkC|w8fEP! zGLBES{mBgztsY&|lke#ny z&YwN}>QA+ioy)4^#ZDzJz7i!FvUB&DzgYM)Z)zaH=S^7nXXo3vwzIQVUNOyz-}TvZ z%B+0AsWK)?nl#Qv%&QBf@A{#2rJ!0)ux}Ng(BmZ-M+q*2oPc7XEZ4$i@(}1CHM`0r8ARFY^H*IEz2H3_&o8E_jYae7V$`!7!~?0lM9!v zuVtbtQ^#Mlo7E{G7Z4AYGhRQT&`c3*x2f)#D2lcDN&|QR#xIsJu=rL7T?KHNfrcnI zWS&8br$G!CS?e_30gh(b21l0_FA#s^J#Q5CQ_RGsD?nj3=<5b=nlY~FTL%Z_vqCKW zoyMjk`i>kHf$2#+&hKeB*GFJVkzY>m>l}k#qW;_2^m8`?x4~D3MsZKvu&Qf0x$;}Z z@sYUjg&W^gob?ohfOQtIlxpz;8UW5C}-Fah39n! zc&S)7fIhtPLkAhFWID<HjO#H>3*x~WOLs1Lq2axpJMus=<7TGH z1}2--d+s-ch zY_KuWX6p>yt-A>UAR~nq_Bmq`fdar4Ndf~_ABYCr<>o`e=kf6>hsp?z9AmH@16dmQ z6nqcv$S9vfAmv^_%V&^(!!2cdxZIl)O3p@HIKdo<;zWb^nr4HN&P>!e*@#S|foP;j zbBP6jd2|SI02~4jiMY8C#eSKv`1%0s`E&w&0?d%2V+(;?1YidZyLQM0z0DEH!3E>t zq(*USxO{TG?JHz~$74tg%OJgH&1s`C*16BLs%F)>vOS}IL(~1m{eFdg_`Qc9FOgaLUJV82*!&9 z12CWfOb(ghm)8Ll=h28xeQJH@^OSW4ivC6 z;#AzSD5F)VSpGlLG*L~&UHnf0V%AT#o`SPnmK3I3xYY*&jg>FHcNUC z*NXn)G2<$?yL47=Jf6I@@@ST#Oi}Grp{`G!YNmMHsVOiE$fXOy;TMrS07qIMNA>7!U;? zdugL~Ko&3pm_*{pXemJ^%Td2ej)@J?yDC|aYD|33dp77IkTLARqHq`k6=Am@atZ6i z?MIb1+~~IN1kR-<_J37_`~qTt;x=Je+B2u)$(x9*j1EA?oq%3~&PujW{9Da$P;KGsuF8F=U~x z=~$55yVO;j@I*!*EOd?qE>^9VvbZz9_>r^{+hnMrj@Cx9#oX(fc1oEFt2w5Dc2@wz zVF04y?2GE`!D6^4H9%=vrdue3van$XX#Fd{_8-&(&0O`MFG5xEFbA{^SzJMmBu!!{ z&(ty45r|;Uq;(^Kr_abjJ#vYBqjj-B>>wnIl6uK%#CM(>x^vF+y}oKWsCaYU4ZtPS z?!$YS3~A3KB7<=p^!=!}*Gr2mA~ST6n4Y{*FSO`&L zV6{&|THFv1os5n|xBb~QJwNL8J{a(l;glC?^CLKTL-4S-%REX|*O}%des>>sJ8Qkz ztl^A!8_X4GjMh|-;n;=bTe1e3W04^ngx z;GpVm*Wcbz7E+Y`Kk41{P;}$Rt}TtvoiIS-Y2dB5aX)=0%{`BLr9Htm6qPDI$(13J;6}-CO&s+UxsSo<>se}{Mo2Lm)?Z| z-Xl^FLl2=s$6I&L4K~bcM(~kdk=hp@K$M88E;a7v zZ7an9wGMlIe7)u;fGZlmd=R`zpwGUM3b8pShsWcA7xsUhH-^wiUOF{8&QE?l&Tg;( zGE;E@f27gh+`-nZ@F!N1S~}`fKxE10)UnIxU$Q;v1eh6sSA#H zF~ZDPi~@f-ig^A(8iV4k#vRH*F7s~aWP_j#TyVmY;?Px`jN&SW@Qdl)VDyn&z8!of z?X7zG-Z}dgO7KX(J2UQi-~zo6=j+F?+}p3Hh*IMyC}lS!mGUyIC7TA-sACM#l%;*t@!?*!oV1hb|G})>*k9bjMB)BQ} z`H$rNhGRhDQUHPt5>^KHk$%kXf}!uMtKQTd3-~iYMuG<&baIvV!}K*e`!X0145Q3D zI6ck-Nm&FEPZOoQck{?X90P(3f}jOlP1x{M>?C`Y5Mxd)RaW8U?w2*Fg)@9xJPfRThSRb6TBIt!o^0<;L1 z0{FqGN0H}mjlhd$gT)Bun8$h;c;4dj&Gj*;!Mq4cwr&%Qxd7>XFNz#Otw1Y05qi!E$I9{=YMnsxqPJz7f5bw-ZdAkUt$y$v7 zOKdB$(t%%k!=)Zpir%PMeGq`&z0NN!1+a+T)!k!qD`GRh1&N~NHfA<-7}jGdH?X~& zWP@Knb;CcKFpkr!m7fKqm`vrpV6X9biz!c(*OHc4LcO3|Y^fOHW!iy2`k*W~v5t5F z(i`9flrf-1|B>T8Z{TEM%RcXhsbr`t1&ib5MRa)?Aoa1~snLbuDX`70e6Itp2dIV8Q@x5t>}HTLIiA(8>b{JkdbAQP=HxqK;TZ zhNAJ{9Ut}6BCA9C-a}C+ujNF8{dKrWT<9pFN5qO)+$pi4TS*Lh75mZh!`Dqz|9so^ zgSQ6%y82HzZhSEK;_aWT-q+lp-k*H3I@#Pm^?~H0eFQwc$U9eiyk~jm>Un?C{NlDB zyk+R*(u*IW%+SfIJ>D893g{jxc`-=uFRxk)rGJys9PatSTlV=IX7q=AiMUM9{6XJO zee&#>qKg5IURDViX9Xr*OeGoeR6Bz_ec-d-8_DcCH!+bY!$Ul=5iFfAe%o)>?`C{8Tlezqte^tl7HoU21aJXI0+|Q(*>GO64gxeJTq7QbX zjWWKdhk)bzV@EcZFvCGraM^Lo)9_(7z?(;srdREcPDR1Y$fg)A2k1s zU|=B%b7gSxMFPe{AlMOHs(q1z5r^3m4Rj5e_;3{WyLuP=aOA!8XI=RH0dNmi9kA|V zK*$l_OU0#iI0M>3g#^=kWRRsYpz&grhrxzc0vvOjri(!F+*nXQ5?~cB$Qm3WRwV}M zhz%x;gLelxbci)vuT^n$<{=Y4tzvD4|rW?EM9Y!nm9c|7n&O%&DK`3MsLbj~l=yZF8tOqk9E zL#_dTXT5_&zue&ec%-}`0-?GU%D-#tn~D`;(5I?y+9wpsolCv#*O^%`obhzAzfvui zd!k`4?(4>TuFNIQ;vn89&QcnByl$bE8*b2Z#H-H@(-iR5Qn1~>-k(h>jcU}GG_jLx zOxzKI2VFpj9M(Iri%-B*@uiNJM5n@S#7BMPN3N-RL_}*3Wz0-e@0gRj+nt&ooY3JQ z*iHuuGu7Zw@(k|=_H~zyX@W=$5KhaB$_%B`-&IJqxnpVAxUW%RPp4(D)Cv#A(Iop& zx!4RkgM%rHK$?s)FubG#lNpsb@ykS`h4)2C^4#6mdVoPau6K~AtO+w$d3*7hs&~k% zT;rST%+h`@_%IH~Ac)0wBF&n|t0PIUxwx1ZfcC=Ca>{EUTh<5ZEF^mY?uy^@lo$U* z5zUDovA#NZB%1d(`+iSU`>l5{@O$Ds7IyO1$RJXLgf{4J-xE=rJ5FdCxujfgOh$dV z6ZhRQ?D+-e#X;Wr+mxEA&jgkJqd=FzC~g7B+Gvmfuyq;#bI$~oYwl=N^^M_!I59Iz z2^-~lkpOCvYKyOGL_kf^Y)~w2WDmU&r)l3(|C9Z(f3&E#LVZup(ZZRL&A>JhNWG77T9~xdj4ps*8iX zh(aJ%s+9yp03VQV5!5~NP~gl)X+2_QJA~Vs=D=`2m`TL_fLV)22@s1|QxVJffJV$g zt^?=9)^*Gj;43EPoIX;(v?44am@>FE3@=CmrdcDzCIoGmF*)3=BgrDpxeNl3gPB^w zJ|ge!yBm^?IcNjiW7#K4pzb2L7KKoFT00=hLY>KC94z(erV)S$9(fQ6#1dFAU2n5_MykU$fM#h`o*K+Tx~!E)d?Lvcl?b{4S>vG~ zrpQgFe(}2}AdC096rf`Yn_R&Jm~eRfh4E1*SsXUS-qAcm{ZH%N<=(KlN*e*q`GC zHh?AE^B#A$zv_>H4`DkM*rUVk^HRpG;=LU~aC+QFb7_(kh-#R-u7T!{=c6HaFX(b1 z53mb^nl36J%6Y}JMB3R37rZp<9S-sQDClx2ToDS$r*d^~VN*dz5V`j3MLq>7O*%q7O$v=rcj zqsN+&dke3F8UuGl9AgcJqu5mmo51kGsjqLN6ty5+h;gyfUG%3Sd8NX>s|GPCbVD^z z1~Qf3?8P|e4DfWdJC>yghDA(Z!S~9HC423#+Wtc-30q`%NinPkUa2=u{o;Of5|g|T z2};5a$5J+eQrUOe9yr@2FkTh0Do0E*O2TuZ@Zy<>$poT{NP`o`x%!eHEdTVQjx$FTQ)RS@S?*B`Ia9^EfI3gYv z4l&G6{^@rQd$u?)*is!&Rwn^4L2caB+3EV;W^cNB)Y~QiHsM=d)nFIhUQGJgNJwgf zxo|kyUyPH&`x=BFqex~(h}cO+a44o5PbHH+Vxe}Knpt8$KVocY+;N_pehcEWUifpx zt%iJI4nt&nKCNnmwwL{#_^{KtgG)Fk8X)z}*&ZG##)wE#s?~CcbbqZ2^F1CT#xI^| zEJm~OMC?SNYoz{IxaCe!n3CF~@#Dz9>4h8L&&V2&h&ZxYZ2*FR4=YswPo`c0C<8@@ z{o<9Q&!G3%PRS!uv8YnQ==Ntc@41kGvkX^vyl~ zhuKRWGaJA3&}8EPDCm?q63u)em~33{_utLCC#5f>?vOh@+<$xG{mjkrhN$_lcT4p_ zuM9%vPd&A1c+11@_kS>Wc*MJ|F|?FC{Dt7K|F&d$SoYCApBP^gW7?Py(=Gx~1A<-9 zYpJ{j7%N<>)VMG9-!|}F&%dSUJ?y;$pug~7;C)xF`Nf6ddsPM9KSm`C4EU zvuK-eJQ_^Q$n6gXzJjFv>8}LQ!M$Gp`;&)O(+CHMG^{?ozlZXciOc{%|J+Hw1M>vxL1pYclL z(-UBB-a7}k?g_xlCJW=zor$8bgNdvr9G*1ooO+K#U!5S~} zfrT92^1c1M%EvoY$^NL4#D5$Kmiy!TfExB9J|4k7PX^wu?SvA&^WBlVWBub^bA0E! zEjY&;agg`nTceS?s@3D(^NsfhyLMb3n_s_Hp*?$oUEW=H9|nV|EJR~Q;Z9%j565>^ zz4Z$t;Hxi`%kM1qdP~Vv@YL`hH*0=wubI0(9+|qkb)$c{XRrB=FZm63YHOTK{Q!|& z1A{j`9UmUp0GzV7;jkh)z<5An0(5Ku5MAH|;4By29N+(sL3c_b-z@62G{U-eytg+T z-(GcoeSLQTWHz?__ddo;c-wcp9k%Qb-u-SOuXZwsm`X$-9e?-Xfqh;te=(|5eF2b8 zSfsc0E5+heaiPcWeJXmoJTUHEj~n4#KQJ}wgC%;Nc^Kq@*T$-?+}IqnO#Q$U^CN?i z1GbhAb3l1EoQ-vzXdf6)5F1f2^MC`T0dFM!^bfs(@6Nzjl*WJV`WObfH$+>->f+R{?PL>qwLExJT&h-42jkuiQJnS$3-LRPOTZqtMhBW* zC;THx^`z%L4fDJnD4U^jCcJO z_AQ?ZydU)y`?rqwD;9dD-Hk%0ZjE@WaI*lRr;}W91Rgy>c+~izTO*;RyqK3h@-e;a z_sFKh!($&LcnDJWCx-VJK??6~31lvVFJgpF9Sz1nwh0+C z&e#t*W1oZMoxMP#5`xd9MJNQiGr)?#&o}m95N-&1|BGkQ;aplAs_lC8hG^({2>wlnh&r)dZtut9p`Km+&QvMCwT7tMC`ZD+LdBRPtyr2{!OnmH zi40_s1#*j)Yd;`kwwD+(BDi+FYuR1+!QqXpRqgf9NK6@aNxHs+Qn7uc!)47MupBZmx-C0kLFyHFd%OU%1QF zUdQXLwyIcz_(r3TM8WoIVb{U85hXFTosa0wRQ&_h@m=7z)e|OHz;a7-MDPuH>n4c# z8kGIIf67UBV1^_!+pcAU+24><4BtT+au=(WyBpUL6tjf8Kp5z50DU4T4=cKF1Wm>U zSMX%~c!X)an9lQYjd;>vN-Xz$4&sQS6If^w$JBWGV^-K4HayMr$F*I>{&>WOu+2q6 z`nKg+pT>fB494R@e}gYr9g1RqhXEUKCaQxc00fi5EaWc?ikVc zBe)Fg8kstwZ1!_h`rbI5AzJM)=B0qdcsx!%|J1j=V!+yUX90)*)Vr>Y`2iqq{UiY5 z3gqyYEcys?_))=+LJr^Ya^!GBvVZE{ycVh>D?EeS=q^kL9 ze;a^&xD8|O83w=HyZfJd9UK$r@%KR>+ti$jI}oH!ECzWhwn%114>;l~c<31P5sq|SO=XG^VZg} z+7muTroM?_%#rnrn~I32`?)=v{CsgL8u3Oj^Zbow;32kxyl6`jl*a-L*YL2PymcTc zB&Tv9~rGl6Fz^}j*=KcDTw>f(0-)(b?MZdR&*Fp$Lc|CtfsEPyNgps%1 z^_?A?yw)=b`kOt_zGRQAMBv zSX3~>UcGCx&phCT#GGDXgIPF=PBMa1g|8gpG6((#?g0boZB?tIiUVjqR0Lh@8wCK< zo1KqhVteb|;Evp4Z?Ju4a;Zw&+s$T$x1nJU1#BS4eaU2PXO&nJJRNWff^>kP;yB9H z3egDQK+`qO$aL)IrjG=Cya+!{H1Ps7z8LEe!=30;Q^74YzU1~v;_!-7gYgmog1gO( zkJ6a49`(pefS=XpETSc+kPZ(5yA;zMEp(G{;_cH*{kWdsC%imS{LHa5cl$_Us>vPA z8u3ytTO2{pFc2~@PLVHYm7_W5_@4B*M$$k`MDA4IG`ye1enqFi6R zG{R?hPWAjDQQSoQOnd#?NAo?xEYt5X+xvoRKg*xXs=8yNe4yv;!OqDlkmW>m=Tb4y zUyw1|x9=}jac>7d>(*<@^EG#WF*Lg$3Kol-Z`l#oeuEJ0>XBq{$~zK_#j~+b1OfcH zqY;nzgFv_OBHtK{f^^=W7BG#sKM$Z~hV|!TV#iCC@BAaj^QygNulgvS^`T;L!~f6N z+d#*0U3Z?{z7eBxlZU zLP3hgo5{)U?-l_1BQs~VNrGf|b=9l;?#KWB?|rYfwP_c8a&ms9{mt0Z-b<5havRI5 zY_`1do8fu;*`X7DcYE5KJ7>e9r{=80fop6RrD8fYPHAk`K0dZz9hgnE&y~(z_gcxT z_K7P`*2Btd3ZhwUncF>?vghLJh}HWC))t+bYh8azUC}%8ZfcnH{Xi^a7n88vS4=r` zE#!x3HqDn=bwVdqUge)Pb$;h;m(~4E(+haos+Ycg5)#=7J*xjI}n zI62fR_V~$n7+bN-vgFn96l{LbW+#|wFZ5V#VvNT;p;fyR&q)YMgqLlYQ}mcXM-E*$ zS2VVTR_flcojYTW{aiUeYqtHjcXz}UD5?;`Y*U^Lgq}x6MAKLrQxN*D1Us|;lNoAv zFe^OFNY-jKSM2WH)1G*{aVQbvMRz414#OekF^`A|qFY|p7nV~AT;sMlX)xz9GhTc& zwnXdh3GX;K1Qdv=i#l$ zY(oPMOE`um!{IQlw(n03m@BSqGlufLP-d~owpSjr;inTc7~!?T?i6-smF>J2B#?tq zPUJ`Zd*SXz*_I}+f1eG^^21K6-pUKb%!<@}{;U-@R0hTl_rUH%MyUB7y-(0s{4Q%9 z`|$0iLc$OvkSgrAvaRTEl~t)80L0Jlv)E=-=H7pfe4{9n8s*oNw-dfF@~{XmSy(U>7# zLMpd3t=diUoZy+z3?!V&B*%>4NE?a@&RzCSN(D5ATu-5KO>?uN9PPyC=nD-qDz4`) zq~byZi;qPGP-)^Zb4-OlUQW&a*4ucK3Pmb5&SoGK^;wW+$}8y>qHGkXN4cTeFKX~c%=YSYQbDo~V} z*>3mR31<8m&ej`i#$UAPY>Z_*5nd8PK0{-oC=CZU<7dOJHUK5$Vo;#0s~XOPv9h)K zPU{QU1!A289ND26(mo!bskC&6YPDlVCC>=STzHfY|7e#J%Q1&O-GD}> zlz%R-3>UsvcReRkEPn~natWhEu+7AbVIn0PfFPoQ&&d7|-3h2?6f%QIJt6BUPlaYe zY?Os6F>pjI;9b7Cg77Zq@3(^{k%~&d5qfp$=?30($LY_=jAH#fR)U^A8aP?ci3UZ| z=JIi4*tpYknyZl#pbDWEutV=y5ZW}p1FO0dG(LBSc+-zpW?){QY z4=BcVWbE_aMN@mHhTW3=w5n`wpDhhP>HWy+XGL$gz4WxxJDl(N)0DoJzm~t*iqUcw zmQrWWTm8!Ft%skZOmctznG${ld>DR#HuE@T3P519YZ#GHH6G6Q`tb+%ETp=JQ(vG% zFZO3@GPTVcw&$k3`Q&8kM(}}C=8ZA)Bj>iU0prTm-l;Jvg{j_;c&Vp7ul$+RP|E9d ziz$h2mKRu~M9l+C;b?em{My)}RVwMd=DwvKx0G~8uerCZb7uBRdj4rdcT^{9t>3l2 zTDPn}_>?s~a`t>`u9V(AcfpFM+G*>IH8wmfRdHDdKsgPSpu)l~V@rx%HOLq8`UxxF zHSpK(T3-oTG~53HygMD9t6VjEj~}0;)$jPjZHPxZJZ015v2SIidCImEXHTVU*E>Gu zae(}YngXMLq&PYZQoSFrw_ePv$+qx~Q>FWqJ}{Zv>Kx7Q(!yh2a~7@TC)b$9Ioajw zw}hN5^uc}#)5u0aY3UDqjm5e+*R^KAyDfiMY4mSM2I$6*|Gm-kei*HYzGzo$71H@+ z?ij921?g+~Q=WH0wn{(H6Z3_Fjz`+~|P>&eM8 zl|-xgugpIWzxyjDBunMA>Xa%U7<>qJpz^_)hmtSl%NH$L`Fh@P)JW~j@7Q|e)2Z6; zLKl4d56oNsztYd96)Wnr_ow<6dtB+<_s_%@bkF7;Fjs8t%=6OoEFoost^KTEmG-b_ zGy@)dI?P@y-TEEY+4WpIL&u^l*xb%-O`h@KQiIAe3=qYZN)X#m7F^B;g9b#Fu~2+A z&4GXXhwn&P-knIG*Oi_XO_KsT**_ikl16GAMPPspWlsTwoM!(l^>nzPKmW^bW21K2FwE$tHZhh! z#E22TNk*Fhg{aAI3Ec(+O0>IOXu;I75T?@02oc(jdMG!iy{VpN+}mljR_%1pr<|4i z?UV1;XOEtVMEh@?i&hu(9D|#@k4?I3zopZwskEYfAk$*`F$^x$6C|B*U`Bp~21{8R z%82Q+OwV~xiqr36zJ-*7s)N*|*t;gEP_`9g_#O5u1V#$c$E+WZbh(m15i&6}AMglV z+-4%nbeBh4TP2~-)`C~j-l*N}2^s}Me$WTLsDW`TB;J^H2U3$AzZ}9N8=(n2$+I?< z)M%0At&4+DyQ|*cEC^Tlbhtx^#N&YtVixf{e2>*;!83z0kRsiN68g$whiA;h6F{ys zDK2qQI{of!v(Zc=cp^WRxIb^C2lK8dGej;;D72Y27ul>tkPozR8J=6XQ?TUc28lb; z{mK7WkO|klP&D$=6Ukg!tB>|_MK*z_VOA&QNnR4TRiQp%th9ln*>I2cR3Pu+ebY z%gjK}uytB#d86rVW`CR5ouT)$B;l_`f5tADv@&*zv~rgJVwBy&7R<}-X3-YS2Qe7@ zKMX5a8V^4_ex{Gn$-aKqUfvw7s%21gJU)4ROx~pZj`6}WpTU=ilgPxLJ-YzYMi7gk%21b0S{liDE_0`Oc^2lYDt2e(J<)~~mxU#i?n)Nb92sMaG%B1g)4sg9Oa?e- zCIG3;*porn6*i~CpfACqCLZ-wzE@C$m%!k+>Nw24TZozsj{}%{zt5Juy~pz$FAHXv zei|n8LIke05f)^JdHS^A4QX*y_TN4d`w2o&wgh|Hd%PGiXY-HuUGjv2TVFW(+aKz? z%jEs|*?j-K_PveOr|@_mV|ne9KYfzF`)+=X4&3=91l;o9j$9hQ)p|X({P>?<8jqR) zzqtQ*hu;1Du^&A(!R}-~%K!FySL6RfSL08zctR@v{oSTUdKv#~O^x%9|3TCmxp5L{ zjr_@zM4gd;v`z&Ume3^4?vGi;ZJIUIZa zN57fDm+{KPF z2tBwiJL9p9UsDO+b7bslF4ZQAyhPtm$i5#W;?|tEd7Dz?MjG&_k31Fj4sC_4YX5;Z zb{v$;Zg{}N=L$KREJpuzzL;nKRFXmV8%>cu!!@xO6t~^f4siR)I3VU*A7X?lHV0Ad z-UQ37_l4FM%xmq~`)NKIW;n672WMdf_uFBqZInOKf{oZ0BDYX5wS||qNWih9To7-M zPFpnBb{}trZRFUN``GzVU9EYTNC!xC*xBwFS$t6>%EL1fpRh?t<~BXgeRsE;qc z!I2YF5BH+E0$^) z+g9AH=hLh*xk7)0s1@OZ=aA*Kq?6*0Bt4X#X^>4hzoK`}zw3S)CcNN;f3-K*)b4H3 zPtlw3KBvmDxj0Af)8!Ou>yc0z#;(xFOnWYFE6;jkgZ8i{uwwIB-)1RW>MEN6^pc_< zZ=YC1l=)07W7%=9$sTx5YH#e`a$d!}(9J-VTFqL1!Gkww#e(+Xe{+w~`x)E&fNgDe zS4LyI!gFjS7dAcXTY0at^=jT6r8(}Z+vlZeLGtdkWRvduhhZ+r)28VvthchqL1Ap~ zFc-$hYj)V%2+id}EamD7S=GGhK4bcCzhQ5?u9Nq+*>%d_>?tc)AlE5{PBH)Vs4>@8 zUMV;mYv<2uvmMKaeH}Z@TY0px_wSFVo-@H1a4#&b^~hmY=o0xRbhhwh6klSQ5G80I zX^{c9JR2?xO=us8(avC5h3Sxn!mY1bp;GbOaQc~2fl14Mfpn}l)m~Aamnjy$8T-Xn ztVGuYq(WNLE@^EZZ4n^o-AuPE8ur+-3J*d1rUS3$KdsLCtN({5u1J87v_+v$F)N68 zHr^oS7#KqgM(JfC44TAaGynxM+M+&z5st@TF*u%Bfj`4Ma|yCyPGyayxZHDeD7EoH z?l6xf{E$irODz-}2bS?~lFw4mWiU9J<1NE`j-`MoHzT57I8}~6NrFrJ+FS`5iZ&bKnWusxZBQKCm^$$F=~u)*Fb(^4Ps!t0Nnh)d-FhYlxW<&SpkX4i6%?*xluet zPaJ=+nN^Z9?soYjD5gA4AVdU)#i^Pd8VY&rN>?Txosa&u==@f>#WYcv#~>5(sM97G zPc8{UFg~)o>&_ouDdTP1Z4rm8>6X8dqR?gXr;Gt|t!ul3hr>;5 zH>TQ|cz43($|C%>6XTgoTQvQ<9ISh=M zlXRyyP1fb-+xKu{OQ*}eaA2k{fZnDUG%39js*OZZv_NM*c^Ea zVacl-nu}LkhAMMs_)31h@~3ZS4l_t3r8tlkX@;HGqnnLx)Pb(GSl)1Hw~gUwec9=Y znA05>k@FR!sF@SK0vmQeCypjpdZSI|qv>%fEypXBu{W1N0k8k)qarRhW_cW962)BK zy)Uqh``a(JH<#lf=gnX?-KxeJ$~w5{C;046n{$YMi7}T`^5I-8`gGIUH@ht=K*5i{ zikkSYZy2MS_rGl5lI5EZ9leLY0ONFrcOX!)Lqjv$E~75!wrBk z-&5!qsu7o4^hjz%b?5Fw_o>mnk^_Gw}PX1~>B0+i16Zou+A~Lq0qa%BO*RdRQiNzs&S-UhYJ0RD6|+%U}>#oax7S7%Xq6 zEyXJ0pE~+Z;~>H^ymZVn${j6BMkuWtuLQg)ABcR)bTn`}dH*sODf@CdNkX1A3ryFK zKXLg6OWgRx=7x+HneylxqN(AFACUHD<2lLSE^npPgd_Gu61lu45&4vs3`3Q#nWV4e zIG5xE2mYEdQ9xkeZ9X+@`D)wH>z^VmTvKa#?YoBk`#*8wu>;Ykk?}mV?_LfRFmYEp zqE(R4Y(QGYPlR6c*bXcGr`!9GkowraX{->gv_@9^ZHOZG2}l#g~5#iW<9Vwr0(ald_8a{(DcakLxGC^2C38V6lF` zuc7;^`L$tv6U&;`KGP%i6-qmU#e*I2g!d;krk~3t4A0GMd?c&wHErSY38w0~bi^3p zb9RX0@vTfesp94MiMpJSCsU(A)N@!85Pc1V;`)4cr@EtDxBIF$aziA`-kzX+VEF8T z&EdD$p^?nR`n~Xcv6M1%wCZlxGoc?HtB0=kB}TvRA9%Sv_j0@Y<+CZ!S{r1S-|Eb< zc5v9fAshK``df2-aW53{9iw`dgJbCzdyDz%=%tCbTaa-q zO}9&h+%7?G$OdRFm^5$>>Ox0riWm7pYZ2OVO`Fo8ihhM1 zPG*%Tie}=$KHsbG<)9n{?Q6j~s%@+`RgPXd`Wx+{|Em5=eJi(^+dES^=2kW}CfY#) zyE%f!8w0!ELAwMz;P4$)+?lMIBQL21Yuj}dfA6YN58SZNXT5T~(rd?qN+KoXYdQ=U zRVv-lCBW^HDNL2-6^#x91jMRNsTtC$crHM6rgg=hNEZAynBnEq`o4H{1d3Uajt`ADGhqKG)mj%Hdum0D|Pd{J*iw z&4Njsf3bMMyvXhh$=KF&YK!IOrt9nl;Cp2|u8=}A2K2Vl9VgGDTlGkXmhuty%xP)y zxx54^5U+U-8GR#^k+qSV3b?5tAyefYpr2J{pFMXvEG%`Fwj6&Lmju~K}y*?Y~rX0~23x0vs~X8NP29P^T@`JM_I644O35VmLZpi#EDkQ>IVsi23 zhDne>rP#`tJpoeG8&Z0hr$59CaSxkKa2a$0wHsyZ3ktd;#mrXv%^kk;l-+8b_fMX$ zdi{atOx4jiZ%tgy+242<*TB?hL}oVaok_GV`I5QQtPSq8Y9%{6YM#o)Ptqthr31tB ztb;P2R$4EXGD{#^wYPS~|T z7tsa(?|k2xtPQ_q9|^`|c(MhhGh(drjJS2dr7%Qb*n$kS)zNgTrbdvPj_-A`I%LO% zQr>=ZJeG;+rbC`OHW6Oa4CG@&I=|QbWH3JOBf9;;E|){QMGf+wJ^oHouyoi_)^>HD zlPsF|mD1{bagR3jeY$5}O-5d)TnoH%`;7Z@vxO^>!Yr}B35thNqEG@^1ud~g z7ljMs&5kHs4kKVr1A7X+c-2F$yfWdENp$^6y|;bZ~N0*1~Tveao-*Gt1F8B$nk~mUIa3`lz{A;qn+^(!6P1Gp`TUkSc>b zYX6d-tp!FmH=#R(9jaQI&GaGr?+TIbZJaGOVU1{|7746kz>C`R2pl4h zpaQc=Rf=Y|f<{+IcKwNe$zSz#cGdTHKP3a5%I#`ozgM@vrvbu|OK+|YKg;|`4XtBs zy`W0P=M<0aGIv|AtK2qm`+=bXG`ANI$r?qc3k|cDXrxCC}u-sLCGWgM07m`Il!Xyq2YLwc`2qi?%9S8MEZ1GhnTgm(ekM9%m_Pj13z z(RFI2wwBb^*NesbEW76vx>zgrOrCo9t7=yF5-aG-tr0wJ%!Js4?{(rMv<8e|FliPT zu7_MalOxvqAt^nb;KyNGWta}(C^rf+;(rd!4+oMAJ8{ure+Y^ zR6TpWj^O0=`Co@J5r0)T_nJM^1lyi-=Ew!}ywfw8?3pZXsr3YYu<0b8k2YhXEh1uL z?H0S}kcsfC8IR6Gpe2Ijt%W4+kcr@ZM1aTy5KKu6j39wUm5HU7)bWD7s>!)`=|jW| z->udgCu{Xj5;C&KqQg05bM_^=&_Il-+)c~t6lG7#?w1taxmLF(wO7V&>w*b`KzauW z;=_4>1EP)|ZMP9%r2xP+TM~Fe!W0xA@dYu<uZhq zU}7kkxD>QqiD(j`?)>Uw;tv5DSJbwZB7n?N*-2{`zp}4umG#bPhd|!jYsKYw!XLPS zyTv^&frbFK3=nVn<7@^s2l*-VKW=1H{4(M~V?~)H49KguO`yfIEXmD{#QI4;`-A=u z_s{gZ{q=$Bt?H_Vj(W2i>f8`VqIH~oNam*~3*-0jf^3<>r;oN~C7E*3|M=19o4 z26=O@yH#=;VyWn2DkaDl)6I~)XeV+>R4f?knm{FUK!5l@)p;-zyFEA2z_kyFibCFp zF-bd`<}G!h_QUKYaPKAG&%FsauT^(XRd>%%LAO!NggIQ`rRHVZE8bN9YRdm7q zAzGj@f#Z*y%=Y`$i~3647;_q~s+RnQTp=3Go!4p{LuwaGvtPq~$-^g67DQ{h(G}&yr8f8 zL`uuQ=-+B2KG{Gr?qTw`z?W!c7{B>Hh?hc`!^w_yU&-1FC34dY>*lLG`y#f*7ZVVx zth7xMf&D0$Mb8?bmW+@5skLE`gl>bmqA3iQkc<$z(y9K*e^%@7`Cz@T zk?Z@*#tZHz8;AT42Z#K}gRB0>gHO0WF=4q)#QRkGrr9wg(CCoHhDCNCc~P}$73PXO z54{Z%<2OA~piGB`G|Zj#jFKiJjx}}3D9|_)$C7lVx&)3#;D>t$w1G)YBaKs-fl3mNX?P(*MF78gwd}@%~#FXPPUR@gD{$<^X3z1 zTsE+#8VpX%Djge@2-qRs650eda_x1>42j{}WoU>~lqVid2=0Q(XL8v`x6r~GN1V>1 z`VqHl;)P)11$QiGwJ!N>`y0NGYvE-WfBb(X_&UNONX2kY#C|%v(cEzo3&TSzu+K|& z4Ctu{6AQ%=+*61*MZKd-W~joejw0-}6z)>34TO(GbolZ`NAq2)-+Zj*OlQ?0XeoDe zK6lXnWKg*-nWZlyhAJNThj-$TFkY(!JmFLw9Otyk|6=@qj4Q1;1Y7}C&V6?ro)=!E z%VjRc+iT-!id`cN077A@v;Z;`2%{OOyaXK5?yXtqTsW$$zT~-eFlj@3kIuT*r-M>; zpF3UUSv}DU|JgoFsOyla<#(F#oykS8pH=J~w00KH>z?GS8a?dlbC-mqs2+LaoaTjJg%@PS>$3wV)br}la2bL);kq4vRA z{{y=d&ET|q1BJlLdKI_5rsYQnKKZZz;2n5O&fa0|TVYO5TdDhWv!vYu2^WV;enV!I z3igrT7(6A3T_To>WIu?%wlT0`JCfAE4p91jvx0%{i#4P zlOFOq0Iw8exXJ=J9cP5gLLTcAiKxUo#upqiKO#0iKvnvn8#(4^jEJmjL`b#gCsU6s z2hHW+psNng%=?vNe&vhRPejuwQ-cT$;5snG3}~`QI<$MDwGLIxsarXZ>gBag{}!q9C{2ofB}JyRcRqwZY}l_1y>dZ^)8F| z1%|QHcHQZ_wd-QtZ{2QObq@wJ-wT4F;N!u#T?(*8hSi*Xid_OB28bbfozdEi89+P~ zJt7Wd>_Pg1Esn=1u|&;*zD#nMyw(RKWCe8-LM8?)XgRa~0qTK)mw4ex++8y{?PmOv z9|gH;oa;xEmfR#h3=(IrLXFOwFFH$RUy+PSmv02|%9JZC5fZ7~2;j1Y;K2|g+7vF9 zXn6yY@`~m|$Rmb{@ez4=_%0G8^a^_8FPymO1^5d-W4MsKQtJD9UsX2|Qa1GHLvQ^YhbxvzJW*6^J?<2B?|I$Ja9%N6KI~A!Qw@Rtfe<*zqq(Gq ziFHL#5GLpp^rFTk$SoR?i8a|wC(}^|${*od9P zRP~U^>66g1!3+mV&WRfRZXHA7wq-d^Z!9@&rnakm&jr1zoIAT*H#_C3iWNBqln!l^ zystxAFcKpIahdf9lfpy{9^BY*3_4WtEC3f2Jce{3Q# z=0_53uCDwM!p6le0PH(SLSKR140QgoyVt#+xPl%fj7nmkH)>MUZFZ#=k|T4lGhlK- zyM?>%l93qAIP!}Pb36G6=V78;1vuKIU#JA4>-TyuTDNwchllRFRlnt5uU1b7!KbSY z7YE*ml!+fgZhe$N(by7}irt+-vruBI1h?F}Wz~X*hg?Kdv3(y{a3jD?f+L$9l}1P- zqz0(XnzpQE^gpHcmdiLd!rXGU)@ ztkr7JAVrw5$q;>lsa`L_9RbFBzM?KVwFVkhwftV@ z@t|F49G3#E}5nq#Hsc-%R0cYTNw^{_#~p1jsQ6v>c1PbfbJ_Y8HDDj8!ntNyWN zzi`V<6ry<77hLp%A0vhQ=f8N5z^51tWHp{cgGgCUbK(Y zISo_Bgd?p;lbI<&D6*DFbBp{pAY11z%n>!jhCn@w%E~*BYG>Iq#;WaG{$k)a6Jr?! z!)xb9;95j9z|?#mL^%?-?sN94@{0SMu579#=nxkX$A;N(vy*2X3~Mo?GOhHsIUlx}|dhrUiclCc!8K{p+=MmW-kb!0-X1+UckT z?~x}v?!=~Qd}7hx>t_=CgFeh1H^}R;9|2haF34R0zlcVL6GubtXxFIpPPtwKh9y{* zlme0!5tC(R7K}{YVaknKm^<#H^xXMaLYgePpC}(N+E-_rOqn zJmI~_O-fWn4V$Zv-hem}ddy_+E4>I)ZtRXX_PPiBn%})i5&wx?Hv%&ulU<1AiSEEz zgdu1;x)p#1A2ng3F(hKf`iw!N2X@0_`!O^K&@i&(rI)=4py6%zyxTYujEzmSm(eC- z5OMU-Q)sq|jX)65IMv$%=jW1jKQ~qF28_wX7<9r1NDZMI5E5VsfXMm~#7;0a!Lh?> zr{yqTta-!Xacazn69c}#^1Z(A1w#@*i3~nR$q@eC--~jHnhVF{6kyPt zj;Zo}alNHZo!lk+0jm;X16L6M@~L!}xF5zNI42SY{28Ev)F=fjLsdpM*MNOcU{eA- zos5R4nNeND@z&zhBQJb-Vlj89KC$Y$g-6p9YZeRR>wF%rT6}9qJ`$b!j7hJ(Y5kH6>I6^cu*F+=Od(CkPd|gWBh0!Va%Mt3p zESuaigCb=kZ+%Ux=Xb#(Ig7b`;fua^Iamn%Y9hL`&;Is1nPfKY(gs5b7fmMy!(T4B zlr+S?h2cybw1aW+7~J&;;$tc_76M3%P9a(*B1QmK0V+JL#Rjz}pK`ZC1v0DDFV(8$ zm(mGe`&BC6zHTNAKRQEm^|faht(*t#rXzTG8{Pm_2_BFMIN~#p=@`rvx0Mm(CsX9G zMflyc4_yaBQ5PT-;y~mVgXf%be%@`iT=llheEm6Jk6jJ|KkKgD{^9@f^AK_(O13lP zX>lEu^y51CWnG3g@G2M|_kY@MV+%OT3>z!}mdIe%Z=LZlL%=1}i+(Tmz2VoI+mO>5 ze2Gjo440=qQyaru`1vsx=5;7ID4Ds8?ausnGw6+g@LtjhneYKi$HA?Y#B_HRYo-u6 zYC^Owm?N4Jc#Liogd+wSy)a;0_JSjX#t2Ucz;zrDl1F}BwlQJRl#-Zhp`94(Z#3J% zRo6)@1TO|{l(7ua#wc>X$K*x%J*mZg&@GtOH}R+e2N~+rWa8aOQf_W`^#ai z8PF29EHAP+a3rvfoo`FSlA$vb`?bc%%Lzjks3H=qOHwX3=1(+o^)YXEdngz?knj&A z;QZEn*Wa#0Vi29N3pyEhra{ekiv#{t6}KXMxMU_$q(EU|E6jX}IIGl#NYDX58$k~2 zK#GLQCewNjZ$5pl`A5H>SYn2WOr3?5FjS6)a4P1FpDL5o;m z@I+`Lmqf}affLxsAh&!P7W|O^G46FJc(oC@?W?#k87}*ld=4kn3~!oq@GnWbX~t0p zr33b<53&&Vz_lO&#fVb`Z-~#Jwz8l~&A7fhKPWnMTuAk&Yr{&SK#Q&_{G)7ZC#AF2 zyRC`EV4%trAt6C$84fu|zfbLQY2_#2lIVlM0H7~Y6sKw2C6U{7nne7RSTt5iXtIKE%0nD?VutV;*rFr zm-x#{KkYtW-Mv`%3oa`Ug9-Oi@MhKbQ4C)BKmPl-F(LFpghV$se}r1b^9S@l+P#TJ z8P-1$AyV>%(t;XJYgl6OUmI4-&@tQsMXO|bPPN2{3MH3G!8v$nEmnd?!PFmrB>bNP zf_u;i`iA_BoA4)yeL_|oO;87ik;KY$OhaUMqkwkz3hdaycb z4(O9?F43POjx4$l+z;16s{BR=kS?b!;}kGMW}F*T*dVc|qx=*%KjwR%5T67@mUGJ> z?kw$L1e|4rqzO}7RJ+wpeO})$B_BKn!IvtFO+V5K2py+sjL06`tWKsYWg}h36^qZz z3x&r`;MW~8RQMN>2d)ErCN7XX6;{YfKW`ql{QK+9TY)=Pap%E-j7?w|z^1wS^fwS7 zH?&Y<{H^m=!ED9%YVAsHm5>CK(M$!D1yBdZJc8vmLncS07l{Rv$6^UAUE;-w(c<3m zf7}VZJ=Fce7#oaZv+ee-r=Gg)Ue%TMX*VIYD}I#|Oumu-+w)zLd}0W8a?S}I2Lv9^ z##D}vxjcA^@sz3M5zU%mO9{I)G6!a37rwCqXCvyS&=O>v z5%#h(NTCFRR^JV|1`3N3NV1?724x@){3^d0i%d|YE&1kB5~q4iyXr~zg=#aN30k01 zG!}vI%71-}SPhkQG7lnSS0=7sbbLysTm1l-&P_>en^AZu1dcZ2%;}JO#*1(rdEp3~ z&JqBgq6|Gc^y}!jI>Bv{tfnv_&jizy+Bg zWD%Gd=a;wq^m0%yxNiH3KhbvEH#E^-B*sIof3#UV2tHH4YA%(C>YRo+uJ*W<+dd3{ zJ>`~huTn$t=yWCt?$Q{d97hohm$vR(AvwS?QF99^KiDS|_q5E3Ct^W^q;5@pD$}u{ z03ZaH-Ens)@W(F&h-dV!Gx_$8dn8}SZNI1@n_p7KUfmeK9>k9XSqaP@ZEZ}9f#$0v z`Y{C);kPzmSw;bOD3enXBO4W>B$wFhuIXww`+y+u1*KW?VilHy)Yz-8`p1IdFbZxbvvhQ#3(tBicp{kh_Xq5F3{;fLFw^wehu(#M z6jp@d4Zg5ND>^7dzp7{5UYQ+mQTM#f{_ntT0gCMG4K!ltc#ZW5iX1HE?hYiEtZU~8 zQQ8GP8jtKaD7z|@X_BZD8yjga=O&g>m(xMwU@*~WKu0VGRa~-YdH!&CPjugsIh)(& z7R~!4%d&<`<(7ZdC5br+1jR8Qh#ia=k&w-15e~I)`W2b1b^UF|5D;d?4l>MmGd_BS znG*ZJ>ywS)g9=Xk34d`~GnW2(z1n6FmxW++83nH|e-=u_xJ<_sJP{=4f&_~TI!=BY zA4Pw$1Ez|i3noc#0J}M$r|8AHAq(^n%*6hY=}$S2=mh$M{I@MdZFVM?@Fju6# z%+r;7qaCQYUk!)ID%E%tQ6w5lzb`E44tq2LZ1{H}&g22@5r|%ohN7I3?xVC&$moz@ zw+$e}Gy*&!tpOfXtNMcv`U^QHmr!+QIdIx-7j=pB_RBwd2LKhMF$Y6a5|!<)EB&JO zH;u-#a7NueRW+gUaJkL6A&?Y@D8X*sjAUNmDi*8~7N(j?0%a6`5DD@?mzZ7!!;~&s z57wO9+4KIPx>Jq!t@;ehjmlV`I4yWpAeM3G;_pa|V}`h1OxCj+NfyvwR2J3)d3Gdt z&JIQ)p+cDmlywQ99y*d^Gdy{Tx#B66B03O?F(YG5V$mleGKjH`)vRaxD>JkH6@6l6 zqJ|QWzZpnXZ$5At2sw;I$NaO~BecN9BDyXldFmvsVdFl1WU}CcE^suMMuqGWpH2Xk z$RTDD4Ml!5am)@>Fj zFHLa^crj#xg=C;N^s8db($9VF*34HU{J&?^95x$3WpmeheSr zQE*q_NzTtW9;Dx{)zAyR9+yNkBkneOv1jma-ou@cIA1WkN`)`bqoU*N{@a{YI9o(u z1g`{ii(xwWWZI-)eXJLOhZ1OK33q0ti+5%1qzef|f61p&7OCxl)>G9)z?5T#bFZ0g3tV9KM^ zG{;eFdhH|1kEB@q+?py7oCR5fy9TA6$@BLl3td+eBLdDNiI zlW-qN3f9fI5b!W2QUj+bmEfdINz}z4nu(Qw-{l1?;_Mr*B<_i;s_GJi>!+QD+MjL<~k)ZK*(sEJ~OiRp-i=eRtO3lZ{JDPU#W75 zDedM5^o-74q5s5pu2%N}m!o9Bc>F)S6O|VyaKVJb1xJDrrr`nfUKJcDx!A141bpmO zTTBP}fQ=|5$Hj%QBZ6MngiOrf=14=t_{9BfOdIl%=_%zctKTcB9a3_;($Le{i&cBp zAEGg5PasWROurZhkE@AG0LR%YhoFqF%*EKt*}a$rVF#4FgcU+5!x+ujaV8521PQE9 zhnSAQ{;pvwGl$0jpl3+Im^}FeF9KMC)e2{_mwjE0GnN~!O>@T>#W|pR0*e`aulSl+ zrsHV-VC*!K7zeHgmKzsx+9Tz;?O`z<`b=0O7a4}pg1(h`SbK>?MOURsw`7sUVKEzy z-XJXEw#6G4Iy!Svhj!d??OVP(MNwePIOO}$N$%{sibfMMP9%BoEh*eK&|jU(1gM0t z7x|kVvSk{yDy2R48BBLkr{;FoMghgaTp-CM0uK61G7@QuoLu0xfmZ>~#g)}ZqlP>0 zXB$CQ7EMg~13{yq4n-OQF+(EgzJr87?r4WHwLJc3?mRuQJIyzWPSH))j&AXLrra!r zH9N2v8mkoO2*OpX{76@NvB);*cP$C^jm$urG_YGCaj<+TKZypE6WlXU2$%q;R0!25 zRkZ;(7x>o!{3<(C9YY`SDY&iX>IeThOf`w}IkmNDYP~IdLnkeJkJ>|1`_W%fS-(~- z+f}hEWOmpC6F}lDm6!nf3#3+?*}#(G+0kHDY84p($bg$i%Hl=w*|L_1BCEJT%rFz{ z*Un$LrFwth%=>%k-{{v_`vxmwPFL;L5EjfgBTf3~epFGx^{6C^O*94W{D2Bi4c46O zb*q*&yfv$Z-M#>^N3K_&1%5FScO zV_@(NGmM6s3A@;CxJ30Up3msGB-&+s`pyfOX}2z>nCfv za;$ztO97Pe7>Ro099RX*76>O|JA+;*e=~R^eto>fkb5Lb6K6}?rQa*e?Xipwj=0q z|I;YdE9M~U6yD$ol&_mC86ulug( z{2qNcIIpXxQGn{K|L(x|8F3`qujk)M3eJnZn(alZ4HwJ{=Ih1MfTJdzJIWdQz;(0c z?b4NacB)>9L#Uqc*g!KK8;*p^h4hF6pMQ7E8=g{pk|53u!IqQ~Lkc3uU%5)SVd{y) zGE{DuJAdJq2C`q9{aXEnnaApn%^db``CrrX)dM$zd8#wJMR5=?Uh|jVkB4JP*A69X zF?j}RatAkEOy6WBOOZ|ODBIN|AY?Jq|_#K zJ25VvKfoy>h7z<-gB?0(yI2(?r8J1;o!nLHpBc#A%3ZAAnz>b7b@f2*wtG9cdh`;LBp>zf3akEnUXn5lUIE;%NzST9L z&RO&{U-E;RKH?s%Izz$9Y8?bZt|=PZT>a7mB(lsyQ-)qw(ae_vxCkh?nM??H&bBe6uf8?V1ze6*F?VQyyyi@6u5 zYxU~^b5du|J6Zag-sgJnb9ZUiYoMP9p2QxTr6?vk>A(|Gplr3s-7{;$BrX{|`>+#H zF0lm%F?!>`_cd6SSnDgK3QvpH;^4@t)()$ICSI7??Y^60d1Keip6cPo)oS&6uHgzX zA!0oE7eHyG$l}%x5AU%VtmU3iJ+Cu7m1WV5Yah$0>@hm9Hc1XyaYg3j)sirkhG7$c z8OECJ2>c){Djnmw?L_*>F^!W|fEp9fA!Nh7%m9&rQ1G0eZT09zZg2erUNbusOz-he zey!SQz?zCyFt&erHp*0$S5%}<`5jF2gZdY*nUkt;UKf+KNjDp(g$G0%eS=ya$9L55 zLXwtPDdtJ4v^F$iI+32RKEm+DF`}K~GJ&*GGJK9@nqCA`u%$VyDRs!&UAa!BZ`M!H zd)!-ZR6gw=Bfq3T1qi@IKL5dc092{ei|h{qAC*eIyI$;lw3Mg8Xcuj3bzp#>0Ck`~ z2`gG39BVEX!TQWEm||V?nhXcNL9rSKTSr}B-SQb(0Vxp&#=~O=5*}$uD>8mZO>|7> zB|lr!K4I`=a3dE~>)eB|yOLJ;&o+T(Dz^0~D-3rg>*jXVJf&BYdS}r}9!+NL?^b=k zHsfY{VKMArer=&)hEgE$F5@sWgyuDiSj)s?H(jC(_rC@(yrvo96KRu) z>GUmiPrBD)@t*%hw}1fz)7cxjMuT_(ArJwe>9-6Nq_@aZ)wZ20@;8uT>$G*B&K1?( z>~@;i#QhMZ<#uQm0M^6GTawnm5lfF8masOP84@x)f3u6MUKCOC`rHjz7jRAF#6UCA z-~6OKPntXk=|ZBD4!N7^SX9DS+^8fOFaAT9RB>0#t##9U_XV|r>_+Nl(lfmaias_V zKJl3{h%ig6l^5+HH(DqOVI?qs9gz_Yfj|arH<&;dScX+EcSnH*tPMz(PTmOMVPd3^ z9M61bo=SYgXD6UnG_^rN8*8_K0nGp3q92#dt)u7EUX{FQo#)wF$(yFdztq%rx8MsZ zMPRsqaal-3W-2M`nxY9>T$2~xH!2~~Sjrxn^r^9GAs!rFOEP7Q8>5>F_KBxtSg~~1 zFsb(##m&sTHg>W4lXYZ!(7O%63I@yn;9;V$@hYMBX7YS-+XeNSb;0bYZReDIA6cWh zH+xhcwvVS{?K0q7N**RafyaOXgq8FsbR3jr-IE9%MtVS6Y)XNFlqE`9WFn$4BiW#M z24VZ-S@P||6(Q`700<6Or)H)r77le(gpQd+Lj2D^;8alu#*0ee*D14TX1-z#>YkF? zt9#C6_xaxR$tiYu$l(!!aq|YTRx~3&g2(M*5bI+D^jXNIYXSd@BOuU9LoUt~^)(RO zX`8%)7)xy*`ud`E!3v+R?4I}gru58Iojh+`S}5HpE;G*#tBr%BSOK=ha{^p#&vgc`5)tPw3tgvuz@Tj!UIQ+ z4udG#aCxEtvF0R?u*%+436;IY^xw#_&SlE?4xFw6O`$sl>n zyikN+?KgK>?^6$aN7qbqyzVn0DjSyu>0Z7_2cY z#BjW_tWjHL2W%o4pHOsoFIktBO21SaaG#%?XjA`c_(8TF91KPiyWFu8Vn}jJ#+`ro zM-*m3HCsMTB(8T~FZri5dEVq!5+6b-NuIcsfXo-@%UrUp0fw~k;!Rn*Y_RvP6v#A9 zIbebX4MQcCfEJW-MzThV-UUdG*vRu0R?orPAA$yS8-YyZ#GAhVxcg=x?*>(I!*V;# z)z7?4KLNKvqGXba?lAQZ)7k?YGq}riR+XY;x6MCIcU{Fk=6hMuQgMCJqVx>m8{S>K z*ZK=*$ILQ!Oe@(R1-oYaj_XQ2xSYV50Y+V-vM^ksx$pTBYWCE zzm^OVixJ)(>ms+0SC{eC&D0iC*4yd~KUAvCQd6wWoTPWxiX#kG^T*IO zX@Nuk$YSGbgUeteEdHe=K{1|5Z^rZJ4+E1BP8K7`&-w&7*_6^m}V;fH+Nv zK3P51sNj@vC!`J@iiWz%h;UsHGtmfzVwTau8gkw!l{@SMJPinBYS=r_J5)nxjacTC zRnvV+*^7;=ds@TT*4@4-fBI0BTS8TtCd2sKPu+vDqNF>_-i|ZeD~X&1lper9P9@)P zbT;`Z^56nL3-w!aAZZpvl6y0D_PjH~V{{&GNp4ja ziZ!$FmC~oIQ`W8Gtx}C;Ew}{hSatejuRR5%=34-QN*hOv>yRs?=ek&)ba$n&2op?6 z*$`nxwh~|~ayh7eZc!pGF*i~}y6+gO8tyMX^2023jQU3?sWdR%TJFQF!=vJOT{C53 z$Vl}6{SzL82=8ZF_VyyhuNAI+&3ZjK_=`2Q*Lh&lJX&%qwcN?*w~KPE4VL&Bf{Un< znsj<5rLG~-PF|8~V6k`;nSEk$hBQS`Vw7rnL||dNVVt?ybf@&79?1TkRrANN?0KKN zI#}K39;#+B?&=j^*q$h3`|N*?Gkr>(V_SrsPz-40cJmjC1Nxf!lyx-8K>Kx}mdn)u zaWy@y?y`2%hzJLcHeec+;ViRSHJ1*s#h$lY767QSe0leLnQARVca0qbr+8DN*P2!V0Mzj z7WEVG7nPhm-V(uzXuId(>~;{HnjFT;x)#lagqM@q0e49EfivD@bx}2_-k1r#<}afQ z(VZng`Coen;HhbnzLB|;B#mCf4{bNM*7UAYcJk394cQQ*R`rzlhyx~Tqv_}X7_xSc zB54%n)`m&&k#sO46;eb_)|BxR;}#YqsUNh>;mC$Ul$!*lNM5UET8qx^W177jK>Abl zj|bJa0)HCjE=n=w&J5$*{XCtwxx#)dTar9jFxm{`l(Sk&?$JG;($@#ARma)uPP-?i zh04O|^0obDF9-@ylcL3MK@tzB!!?J5c1jipw4yEwU}g&uLN@dg$nYnzb$6S>1i^ss zHmN_O9^o67o=EJ`${#z7*Z18=kt6(v@a_4}zJ4$FE-6^*L3O8C+;$2e_J!n7zqw`b zJ(fI`U}vfJ@Gr16M72S#d6J}G2Fl|k#5Z>|6fN{;kw1=1>_!;~B!*Y#=fWVeEzyg$ zhR1`*9m)@WAH+Y&rYdsvLcAm^=Z8OL-*PVMAzdIrhWquu=aYY)a0Ok7Q1d%SejdM! zhd+v7w_{0Ll3S7wDesNs;CAPMS+unFXl2T2OtUD7u2wt+I}a1Etp$jhE;dt#>87T< z2)Vc>SAf}?xl>&cht9e(MkZpF-|OfW{4{EkRE46;Xf@WX``TZrEjGpqi!-C`ReGLt z^VLrz#)uG9KN7|(FaI3qOnxWzbu(OLx#D|o7R^}`iS{JlP|h#wUv1P`CtR)N+$iL| zDNCyX_%c{P5AKwmU1c|=jro^8YsN~&l_P+Yyo9G)AL(g9U~)6*#S#-^>5+zdq)oT{ zqOLBwV`J5e{#5;d+mOzUz>u8utv{sZ(=qKH*4}J4;T4Lg>FnUFb<}xJG0W1$>&05o z=O3%0q|;o9{$PHCeb7Hy7>XB?tn_XL39;as;KgW;m4b{kZUq&|O@B(36`(FXVCY9k zdI&FFvN9KIi{6Wp(r>EV3a$pD3ATe8BjJ+OC2Xh#kH+L|W94VzikaGJIVI9T>pR7o z)$^TX?NrZKSuvCidJ$z7v#qcp8?+F&mI*u5HfS^;PH!ZG(TeLxytK24t9r1f!`9=WVWfpaY<)4E1aG8LO=tcT0&XC$AtHGJ& zN?SBFYFQ$NM;Ky3x;U)k6JPaLbYZ#be8X=hqK-`$ljimH({DFGU4?k>>k7b;zc0CM z8j8DRv3u5#gJrNBRazyv(Mz@`2^ADziuxGr3~+JXGNcA1>ZovfQfQT&N(=rGw?RC@a={QB6 z@C+W?qaFVnF70S>3QUCd%W!&J4{cw-Y)879ln3wj!-=${RR$%*|5481=emm|?-ckf zo~Kk|ZC&eOpxT$^+L_Ejjf| zwNn(uPtqtTU4q@GVL*xe%|(a2y#w(g-PJg{AEO3=FUYN{KvVRb03k*c2smAn6wHL^ zkOrJnOH9AelfG1oHdfj+;jU_TKT?uE(a-?dZYI`bhpgn>idk4SSu^XOwH{^DoKY@fhy7z05XwmWFvEra(eKMA$6l4Ck6rpqd)A1uvE;vME$An zhk98T&ilJ*k*BM3Pe5U(jh~PZK{@BY;GnJMO;epRL!23tcYktkvhPzx7SNaU>G9I8 z#!1YN5Ju}BsFjxEc&Y>qQ_yq#iR+Eo!zQsrS}7#4Lcejs>*luRY4O&CIHm>nhOb^q z7M4Z_)SET^n0DBv)-TlSkNZ>X7#)aPmmUtDn%9bD=*GgEZG>BZzfAK2neku=Po{?w6Lxqa6btB7Q?QvzrLlFk!i;Z#Kyl8~)w4Fp_wf=vJ|{)Q+;_QG%OCEtu=em@y2 z&mec)O>HCK~gY!HK^(Yw*~8pLPX`P~Z7%h86Up60n1ZAwy+kt~bct#a9HJM^caWSEokkXm zP_lv%r4_;d*$5n9pkifUc7v*aT3yp$vsV0Gsp%{RnV0Apv z_~^Wk!vUGVcYgaj5`A%PJCNfk6EuUGg15rglcgQWf#RoJ%G|5UCJ-ey zNj~i2p2=YtmZXClFEJ6xS<{_C9(^tiRsR%iixc4{!Hsky^K>XH{XlJ^gW;_D^^e_d zxbwj-xC&;T)>67kMVw51^ZFNlp20%MZAm_1$`+v`Un$-!7LyU?7KuK5?Zb6_l1g4c zHNPerI?COG*F3?nGi3;2}g*UVnwh#Yar$)1S)8T-UxOnfQHtkk?@D= zlJ&gT&xUk=8Mrsxw*oqRoYU1+zdFIzE{RHnEb;#T@_llHypk$psXelLmFOY}7PP}>Y*4}m zwqy`HEcS2kBZ1LrFcchiF9q^zS$4;Y&X@mklINAt*2Clb*kVlFPD|)Rk@y=kd9DoqH|NqV|2TSl}7Z8o0v9&Xp1(y_LVIfF`6(s^z zAkCqeGU`XbF-64C zXT`ye8yy|FT7T|x|9D5|gJ1F?zT61uBmoZt-5-WY3eEE!4bfEKgCTFHlBj(}1R=#9S#Jec0ALTBW=BN?5PH_84R-C(RIx%nY)YT!ED{UyKa6?_TcbObUr966Lqz$ zY(JIrfJy)pP$=HLq}|pnbPp>DrdEVOHVpd?Z&=zC8V=xAIel0Jd_tRJTeg|U87wW2 zOs-P{b1i(sy$Az+9EM=cxe{UrH&}Tn*Z=Ly8sqCKimoM-bf>lAQ{p0ByLZaYE8>bc zEe?yj@|6)Hk!~e0AnEw3Kkc{OP1cSk3YlBV2C9VIvRPDjGrI~o=o*dgHZL3t)qLSz zlZg?PCs%&C1pi&g9^2k`G4Q-$!$nmG!*IV6g?E2Sk+svKn_X{$iEfy3tdy=5`%V+F zx+a4+_MXnCEi2salFQWa)r^t0*lVilj`-l_rg9^88UDp*8Uhf-I6{A%81poi>J;;(0aPU3~~f!qe!PmKCctA?z^BY7ALkx|5Uixkyn z5Us*tF-W{5s)b~_jpjgp41SBjQHL}_R9&_~GK#sI);QtPM0g~emg1OgU|_aaQ~PF> zzGRk`Zlg^%iWq7)1n}7V+0*i=j_-A3KbO6ybUOQf|LNRie#ICc0w9IE5#C4j5VnBQ z8mj=D{h*>4kYpaV7nm7n#1F74;iC318QFi%E&Qq-qC|1ZmWr7RBtk$-hhvFl3MnYT zC6^_H>bd2fjUUbEnX6cls$Hx~z1i78yW;G@egx3xvUjtX{CmGP{-wR>!8%?d<77A0 zj?lq|3_senlLJmeAeEiJMFmP!Dl@o5sklmT&0zlgm*c$8K7#M`nys|y3Y{(S+5FN; zSw*lX3Tycb;dGUT3&G|+pP2oON^`w#iVl|YE*4W67h)g?wvnsZY>E3(_@^n^&ls^s6+P?duYlM7*FmXJJ~8+}_}e-O4qTZ~bO zGC{Ag5_+Hm-@Qn0PdY3-?V=SE!*L=|+KM}U^D!hPNsMNf^%{vw9c$+MqAvFcKls1C_y@Bn+ zkA2@20s(;NQJDRO2WgU32MRIVLPAuJ+0T%PhU1`V|Mq_a!l2hPi9j9DqDlISiCOlP z!a>>P2m0@RzaO!bA(l=pAgjkdV?MHaDs7tz!FE{p*7$JDG;;1WYF2@s{%dLm zW;q4xsX&IR1h%S&o6WGf8VV2A_G$a+e%u}$0&(dnL>HoLSFxiXd1x*c&CcKotUWIF z$Z@1$=Y&8OK199*5t+8b=u@nxoLJO|8q$_GqkML)jR;7P2V+YVDv*V1fEN5211#12TPw60nG z+1&Rm^K;pQ);I|5J*6wP(|afC#I;70*g@SRuSlnBtcXSn1eRglx|EdGR02L+y(~02 zdXa`9>Umoz=OzvMzy*YY;jlvXj)VDc1i|CqfWscY5R&*gVtY2WaPC+^%7+=_*r z-NO02IW#U0W=(2xy)48A$dAo{!NG|9qtkvHg@{;z0!6pfbRb@CGj4#Tx~gFjEh#T=|)YmB_WUzmCT*Qz&o+^ zcgp;g;x$@Tx$Y5JA%q@MI875|eVDj5^g+Y|ypmqx`27rKOOCLy86g2D31mxt-)?xs z>Zl3?wX@jaI57rLtR=F)72J`%5R!;JG7-@2=;LsLq=JL)L@=_sk!lu?2KWyq{^;&v zPjK11M#4x?wDx!G7r9gNl&p2+u3A@u@j$?xISXINCagP(@yYh%_ZsDr*r&fWMoUs(E*{IQAeWSHWH|+$6n5Z&k5@P3JKuVu*M)1J#CqcAAJbqMn<38&|xOplkuKp|LEeckiaq!>8;@cSq>AM#Rxrj$f&E|dBU zZ?+8L^*Hg+zora56(HSw31T0TgmZ?r6&@2QQuD;JTo1oQ_%;;qsZer^w?6ru#AZ_* zFE3sbrZ8#$Ph+O+o>JZFJMAvIGMt%a_jvnJNDF=Gu?AUvYqxF=y#(;NCn8mH!6)h4Q1Z{Q-735zwcVJwsk5Wc44iScxiU zr|YIEdfqI)Y6jEt@OWu2_b5R9*vb|`x{1J@VJ#br_Hd+3O7MBCBWyBV5&f1%Vv%@_ z^^ppt@xsw1SD`5?c&1{BV4%Yc4lk}>>s|`1-PXPl(HIEA-lZTn4u)B=Z2Z(M$>sgA z`DuJ<%X$?LoU=oA60EWMjLy?oB3G=Y^?L52q~DyJ27?K3ipk_skp(!ALK=iNQkxkV zZF#!2bPY&dR8VTnfGcY8z0&B7Ft^#^xJJ0b_A#s)1E2 zYDeE#vs>HAfQAGD>HYp`>kFrQ69@Bu z~k9*iOY)TDKe)#bz9Rop{i@*Ybr7Q0THS4ta#{XCt0Q|@=e zqbTlhdZvtDqf+}2+7$6*S|H{sZg3l@Wa$x}__s8xKo!ZxMc0P`kPNJxD*j6;vq`yI zTDJc*2GTRz_nrtwpU!je0IT+NIDjv!gfTpWfcVzyJMfXwb`VT|k-mgtnEu#iA$Xv8 zAlr2_i-4G(Zd>E5z?4r~i7F0MKo8oBacy1g`Y^CPrD~`sSM-Ij=OH0|^Do&bR29Rd zHUIMXL6N9d_qrd|!$iB4@-b3V)C3Sj)Uf^g&oruq7>2EU2MpvdxzAS~aiy0ik-O z@7kh?M^dVu(Aoex_8XNruZ`bvP}cKgFjYQaC+%kvBhO4QT%-#Grd_}Eub97P_q=Z! zU60|L?&{cA68p$(4_4&B&eJ=`yDYkAF)~e4`RoW-cty3d+uA?%1%O%r?`ULAWPzYE z1|6o54~p`YoMlSGDp!mYOG<-f_xHyUvH24&Y4?AGT@ze8@j*C2`2|9M|44wFQf6d7 z`^|=O=r_brFpUL!y0{{{9LNac@a!u*BM z9loS?MTumj`OTaE30AV4Cr$l8@j8_&9apndR&nYYGvS4b@(Dm|d$ z;81ZBFHWJEpDamKtEc``uY}{LtkwifNxgz9l%`w(LQ~P_zVEsh?CkmQU_LRbx*1bb zyMN?ta5Q`fE@6G)$M^mTMk~QuLiB4S>1H`o&)O;S?+YO9ouz^N<#FpZa@T=2jWGat zazMgZHO7ZH+YQ_(s0Eu|QIc#+&MLwHog>o@d`SwVTERG~N_kXUYah@Nmcf02oyESe z`+EV2F6x|;0n&B>UBlz6Ag}&Gs1u6wb*UOe|jRX|yJjqfh-BO^bO%_kRiSoQHW!X_q;y4dc(&}F7m_KCiloe`DuBuD> zy|x$KY7WTml2t8~g6y@x0=@QU_J?0`r@w%PV*6D>lXiXLBC{-$qD%YrRYA1z^BteV zf0IVfk{Dhh%b!{)*LRhHVJg;Ah^bmBkPhDTNzW4aFhXqbsd3Q_GX`2&nJ}ZK+DCLg zGVWmh#rol!^u%=KCc2e;R)c+S(f2^Gtx2srQDVjaltsov9 za@y*@B5%sQop;N}tdYbFHY;-;6>1;bFe-b2)uwE*A6DREV8F9Vu1g9aWwU9iEv&$1 zO8?QUP#y1r?CmxNQD?(z^%t#uZg1iXvH+o-J~0qh21bOh{CO@VYOnvGPdNuYQOP`8 z%sgh{k$2w&@B3`2Jn~?WGp2pfK3ZknCc_jxg3!nO5lW#$>g`LJJfxEtFw!!`uasL! zK#g_J8;M|nFi5?B#l3w<6-))(qT^V`bu8{~Uc*GH<<`yWKg@NSisM%~668Rq#a z%6pgec4f^j<8XjvJtR8GOLO}IE8)-hE_C8pX$Ss3Xw2i=*GJ#pj_t|CL~x==iQ*Ah69?2W##{4l6bZXEXf`47=CWH^0zaHLYDR56 zE3U@A^;GV~(MaHi490mppLjfP6jnzRl-Ags_4OS!&p;9yUl87u(r5FAx*$BlT|05^bUlGW^C0>iJl6d*C(P3(!))NBb|muVEjm3f7Oz)spS) zE@~772E;a?CG|ueTn0y04iRPuNHos)ZK0yEiab!+Zf&~_jD_V>;)F{LC=2;5mr9xD zuV$C)RkgQdf``b#_9{1S-v8YUG>X8I1UxXdSH&Kyxvletl%3P~bZ+O}Ik(K|m2P`5 zFdI^gL8!qfF1am17zo=6zA2F_vK`k#Ve+ADa}^v`AkX7*cI8BM`2>|;ZHzXvxz*4A zxgsj~iFCOGVi)mExhpGst_jJBO}!U$Ukof2#!y?}kD3ZfM15mbQRGIOxmEmr#erMf zkinvni2STzI4XV)t*FO@KI_C_8Xy316m#MQj zT*)?C10Q3D5el3s5=otgqu2R6zw}?jEOK9lU)Q42_2$pdV*Ey9?1Qql;s3!&nQ!(rnE8h z1>xfZ_0pDSxANi;hxlRS@+r>q2*~qrCCgPc3ww7SjYyN{!mkF$kQv8Z7=r->o7>R1 z`G{)Ch?dx9?TM1ng;s_CAwmoio%OzDs529=Es4C~2~A~WoowzH9mn0e)K)oxvTJWd>=kLVT`?0I@Sf6mr-nY1u$%Ivh9k{?OH zp*ntYnwSh~a)Q8YNKU5;hC3xh4J!H*RIgYMamIWh z10_wjhM~-AfLWxnD6Ccnm+Oxkh5U9|MR{#r|1xU-X^X&us-JWa8&c(X$xrA?hyf{2 zTM2rN zH^m7LXQ6-r8=cMH8aG5Rs+_bCR^QTHjkV&ZnHLerj3^1&aXvdpV{=a_8oG}fEH+kl znbxNi0WwdB!%EAJ2u#lex3@2cOQ;Fb<72ZS6Wjs z+~!-J`1+43KD?{wQ7bOhfBI16mP&nBtSiO3)nSl7lOjEuWr!m>J7Oh8WH%Av8REcH zl~#N^vfGxs%aR&8O>0m;0gtPWHR>C+2n0xx)P*(az9b7A3r{}?>kXoHPpB~Zh^C0IAEDw=lf+=@4c3-D+Q-NrMgo>lOhcAw6Co|TIGs6ZCzoqTJMx$ZX|3gTHER`@(F@KaS;T~-v5-I~0>*MxQ zZ`&3PX5P@%0G3g{nI$YuC~>~N@wu)n`ot+^r|eJ7Ho-Enrd8b zH!YhY<+>oZc|&U@YWH~LD9p4)`f8UqA4h&rT{cLg;44W%KpoX|YI@?q5S^ojM^;S+_d>nZ1^)%kp-TeS(CRg50(i z1=>d_A!(PDJlLEeM1eV`2DUjuY>=(tF+gb`n&5>{>n^slRs=9fW^w#%Fy7mIF{t~; zpXOM(iSTD^+r=|%<5!H*J5NN})XJt<#Ix!kNC7v%pV!bwoxhl)TAA|*T$Gy@LXew- z8)~j}C=sEx$F{X?EDPgPtJBt1Dzh5UQ2|92fJ@7VJ8&o3(J^?9=#kyDx-&mLXdD}#hD%8Ud9=+;nHgkoPF*)STLJBK7zP4-j| zjV-#`+_=J;yQb8y`g8na%#9-|3Wll^STMV-kKENb|F~eez^(RUR9c!@(Nx z%rP6UMZpgWMbhpWR1lAo0ku_aGdZYempE9uEXeK<0|(>*89rd7IIdI9sM1MH0BmDs z(@vLYr;TonkioK#q8VZ64r&Pf1Fq_7stAjxphp>&2Tk_#KYLKV?C-Z8|2b*wJ8{fi zlQe}JbB|590apW>>WM3<~-?BnfARUK%k*?DoHTEJ)4fLjIU)HNVRI+JEsSWJf0 zHdD6tP~j~sfRYxtKkd6uAh0be#B8-yN81FxtjrkJ68p9-p*Cl! z#8R8a@s(&=hw!4so63(J17%eYe8VQhsLu4loG&!TrQBbCd|Vbt;12JV`$s79nQ`5b z?aZPLEqdR2jge(Y-UaW>*JvD-)(=>Fi|)ZvT@p_1sRsx0)IL+#=~8bJ5;<0(CF%-? znw0U-A;|d4+lWztknlJLb&vo#G{rd?o9u+Kg=}QmvBfxbRDovBfznsT`?4SBzftGd z&|h@FJdppw$n*?Hy^RORFm7F-k>Is+X$MwuH%sQ`Cxp61Se; zKp?VNnI^81kzrXpt?hI(ibf@UB#iL{)5>K*?n55)3y%ecUlU|p9$S*7i;oWuoiR`c98P@u%bT!L16bUOUd@M zWGiBc^6@y>8~ZrPx)PVYab#nX9wDp|wQ9-hik2h4s z4L$}|&5*oi6)pF3Rvu8ZYrOd5!FO^pP-1ij#jtLZu1}_#Rzk-BNfe>dTSAEC;ltxZ zG74oR4wPCW3YOcE8BAHlbE5*$s=BTeXrH!L+6eX$H_ZlXvOaS?@8+!ZctF@#Q4H7h z(ci_owU)V4p#L6S!7m0s%{E?>=PTOd-v~b%`R(uu83o9t;R(X=N8CdS z>EOD4{;y@)Fb0`@B~|RSDn+_gFKUf?FiL9;mQ;wGvLe*7;=o9Fo*Z-4#0UYeZUOmX z7obGg70f;L8~7m%)sVti&vmH7G?52afv0pcMb( z{p;vl^3YVJ>xxu}zv@<~5?)oGJ!L@)bQ^+9*@RZ#%EYlt^4O&y^T7;e=FIoQ@MlNJ z^BCEBln;jeVI9p59WECEzlcS=E?U#1^OB=@Kol<#YhbN|yZDvUXFt}NJuv$aKh*&3-qII%6w-VL?2!TnCfsf*+1?_iv|JNea zz`HW^C*tXZ@{zdmA{!@FJ99-CagA-W8c3c`2qlbJmDUWzA?QO!6iD!Ae6+{Ni)w?o zK+;qJZ1<|a>;@iyaAH$bZ$A9d0t!GW+aUvGkzKWjylrCw@>LgV-rRkB1}fta&s<2t z68|CM&Bv(cL{I~Eqq5vpYYGqxiL`9re=De_j;O~)=a| zK*tSC9F=*|J~a>f0Yx87OgzZ4r|4|Qj` zI-7Leq@C=&a%?0dCotb`JBbifaaJ@lZoJWbp7YDp#@{l9lv+Y7ur5lqWmRwCaySzx z!~jz?9G)gqU9DY~nX8hDs8ia~HKc|g0<(f(Lv&=YGX2KQ-oIdW8BmmTk^X8urDFG* zctPy8Fw{7@d?TBuFQn^E({g8o^PezbeIx_QEDOr8O;wDm2=#4vN!h4MqZQSPuPWo- zYh1+FQ%elBC9o^O6`q*nX37oRAlM|Ne-?2I1$9yYS2!(jkHDOE z$=-3X*V;M0OTx{SM2^%VX4+1!Ru#!Sc)8RdPinLO7sBQ?O|f&hMl>E)#Yn0(x3hk<*)m>HW%X`r|>WWQq(n&a12xOnpg%aDOV$ zW|T=#K~;yqzC1xMQRzt{w&JNx8Qq>3&M2ORXtlNh(dsN9T;ABcf5U8_(NNMPhvV6k z*5gRJd{CwTe@GHwW|PPM_?w2(*nDs{Jj`9#hKy;-)9xFt;git8wpS3@Fc=p7rW$~A z1>Wq|Q;0{fe;J5M2{;5s)@a9o)aaB9QshFtg*EgIT3J-Rjg31Ar zIRkzO(~$9d-l#g-uFXmSfLI2KM3lcm@dl|(+*Q|Z?F9O}0X+*^4s7Ev8MO_vy)X@3 zh2dxx$R|Ci9o9C?{>0(sG(I;xOpf%7Ld+J7Sp?e^d_ zUcnJla0dOsF8G6wZ(l~THrvS9*33V60B;)l+~U=Y-ghj*25x!EAY5d zF$$C3yu~-aN9PV=wFq>DgV05_NIzAPX$HrGUGgz1qHG+w0PT%LJmTYtp(!}CO7#{& z%C{|)TMWr4X_Tj;v+4`>oN|}A+D|Hf>@yk`y1g;j;pTXo2?DKJg&HpPSN!P^*i36ezp>8NP zj`*ZZ5k`1RX0dR((n3Q@g#({_6evpzYXf@|8BO8K5w-M6MX2*?1rUiuf=oj0?hXU#RnFosF_ zRLw;FjF04O8xcdur`yZObJZ{T88N5C0@=Z88B`S{+QS(JMnov6UM$P~-QRU*U#mYP zuh;7bDG;OA?93bVx4u85-k1DJkQ}AO6FvzQzyBlb&{dO!)Yk=8MTcA|_A#OUdrCJE z$QRwpjU0Vpq&pUXY^aj2jIKoM3iL$*mQsGy`QKtZC2nC34)*R7!B9CQ><*S*?x~l=eUh#TqB0Tqlrgd(y9wAf2xtlt>%plwlJ^seORX;e zv2qwVLKaboj5PdV6;8sb@KZ0+G63vPDdA#<+UeJV52UX8yX7xJkH=Nt?vba1OCwbr zZJ^TjIPZT4n;oj^5UX-m$?I4x?hz#8P|~pkY;|6S)0L5QS_ycYJZoz>A_#$lXOg3U zb=tPpu!h)?-^HHN^+=LUzPzUI}Pc zWMsqBBX4jB)?SxDw4z-Y+PnYn{3vn(iQV}c>3SW4mNn<);pXLzy0uqj98_M+eMzle zn4Z8B3E67O=&&ykFsxH{xdWs@g-vdol4=o|v9humtw{hBCu6H2uJU~mBk7NQ7E)mf z)Z(2tbF1U~{`yF8E&t3z^{=@11xLclp9VCdo9X>{Mk#ubF9!Op_vva0c`4eWuZgLp z4d74{qIi^|MMb)9ne=U{+02B`HZ_Dgh7Rk0YxxuiBqG7;E7?xZb8rZFd{~t?DLWU8 zM}cb;N+WZHK83~FeL_sRRTr6s-@#?h2Wl`O#% zrh;-}%*)tDEcm86<)8IZ)oPHe9@A4xX^j-kpgP$MW{pQb`{_^Q2fqVUWEtcFTt5HiWV#BDo*;gY+w58stEP1|mOYR8VB=={S{)c+pA)22;blnQYF7 zL6WueQ^{1aY&d~n-o*ba20^>{;6K$(%`I0aP~7D?ohcqqHV>_W9_B`uBQ z2z)|s#ka67QwgY+=Ze(!9K($>ddk@Ey(-n8^R`sg2zd0cK33(Y{G5@$Qxnz99h$F| zjk58rFYnM&NiF5^c29DC4}W19Wu?8eSc@CFCWI6SKbQY%3hh^LvoA_!l`(jmie;;} zWB!9g0d|l8AT;$*UW&DUc$G(K5qDxH;O^Xr3vV_Nx4+|wEJBL0@HVZSC|X78Aoy2L*t2QjQoz0=xNrio+f0VNCB2mx@%OK0**7c zi22-GwDNV?7syhc1kl_>-Su-L>{b~Lw7DJESoQi)UyK`HyLx$^0tPD7}^7emA@f;WsA*!A&mstNr6bA7Gzj{p2d?G>~Q1XX_JAAcG;y2NHX3%axJ5_s2-2FYAC z{B-1;bs)wCE76jHK^Q4Y zef3htVihvJfm0@P2oSP`=uYQp3#fJd(a-Bz+!Oi3PU2ZJOb5v*yo8F6xR*YU@2ORM zKZ&BX#D%3_EW-jf-BWg;No^*_Qtt zX+if|^SZZBob}?ywmx~e8Ci23$#k;S43gSH$(5L4S`<5^G8S$+Gqaa=4eRSaair;-U!~SM`J`QPQc2lTZlFQ> zGP)USEIkt~G-sotweHL-jcr9GNW*K9BNnyHydPhh*`Yh7B0{gDWYqUaX@u! zk_*F^ocZQ?F=%Or=k$`p^6!RVpA(Ie%swU}>tFpvs%YNleA^UvPp*cuRx)O3_V2#S zPXBUO&!Y8pA&O4#sjhMEkkhj_3U=l7&KdvikpY=L?L6)2!iozU-O=pCQgldmPR0w{ z=1r42+jT2bU-gJl$hc4(T**zk7j}F5tav|TG(U7#t^C`fp?B3T&SGP{<`r#u_^{(j zn)D7A-Q(34Nh&{l66RlYN+ZAH$l>4dHcGThXb#HOiZ#Dj>Ta%xDUo+>j$hV}fa-{s zeLFZ-RTOgf2i_^O8u>|WOuXo)exzJA{C<<-?K@p)c{u6D+TP|Ox-nIf6@9iDMa3ci zNo&a|EPC1)`Yis!hajZga|B(;QSqPelt>s*A#g z5;eny)UNNENaIfb=Z-%sXmKXM_ACT`6C)mUfVPIAopmZzYmz5nEG20NfYE^Qv83!`^uJa1;8#b;KmLR5S|y3hHG9;io1&wz{FKTcqNebdCn$Aekd&$Y@>! zo&-QB&l#C%Heg+0zA-am2a*V@B~N1$q(n=^hvdL@KaUX+BzPh!U1a=oc6kTZQ&Nkt zhthYZB45Q`w8n<}rml8AwWHxD)#-Q*i?lYMsPdelnloSwB{OC+T=!zEH6)`px($U3 zy1eNd0#WexYVr`#f9>GE{fxsQU2n4tMZ0Vao7+VS|2qmZ2r(TcL``j6HbK{%WRyx` z9paa>lo6izx;x)AE<~EQ-x+H<#gx%&#dUFAS~2%%VhW{tJV;iu&T7&s0s!4|biI^p zuQdMRH;?cHUVAZ2#byst)#{IF8CXKMB23JUqbL?XQh$SyioKVN(}uI|X<0+Y3eK{9 zFOJ~1>1LeWhPM954+d>$(TTIdpNn)q=3y!46`?4MK!eWeu|TZi^>;h?8iyFJs1Wrl zE%M8Z*iMI*r$^ky^Q(HkPtOz`MPp8D(Tc3~zKk$KFVYWrmACD1VL0hTea2Zi^(Imh ztNRt9tuRojm1lyMmE;Kxvx*GG1CrTh6MldOz0dy*o`y8Z@N-;FMr8LyZaJB$#WKIBx6m%Os#GbhxTAC?6E10#V;U^}kH zHuSpon}0~nK^*t`j*&Ztgu?D_n&VCF5LW)=YKxWG_h6q8q0ZP$DE-ZDy3z7~AX6 z3vA7Z5QPohW=iFxRkrm*J(sjY9@|}J);JI`WYcHx0G=0TOj}2Qa@Px1jQqs&`32pZ zV&pD+lA6;|{m}n53^2aQMCQ$(KBCH-dj7t1-aHvC_;==`3^ z6&!l)hWB~r*9w>84X=Bt+r&mHy(vgFooYR2?H`QxHl-Y^J}aX1MZ57@L7xgLC&dCr zYMg$X6IVoOstH7##nr|336kp6%r!}&*^U3Hr?FvIlJ7sYYo2*h*R{SQbU#o=eIdgSw=mi{B_j-ap|9PjxU+% z$?EZErqS)vNk3fmo%Cd(5}&dshZ@rx-!r~@Z{0e8;9;=Yjm~a+32nG zl9QfjdIy}A*_2nRHFxlEQr*rgOt0|iYGlr>0!Q%Y&fJ=ZjJVd!)@0Yse>JphR(3oe zUH*;Q2{AkQ%JJ`a&;<1O-uglFhBN58`^@=M)yZ&Q?fI2jL3B^Qa`)xn74yFI@t?NH z?77>?UX5zLIa{5q>@p8{X8w}-d{nb5?nd{wFZsRU_#b6%eBF9^&b!f*p8c`;4f~RO zK6-z~zmPrP{r>K7r}cd6fiE8k(yuuWeEErBwfMX^RsDhM4*k(e?T|9!yEZqgruKXbp>xKW{i)Dt)!q%u<0GP*nZJ^AZ`eIov#Z%7Vw%Oj->>EOfk@M( zy@O|09yzh!Jmb)PFu$*3Y_4*lpFbv&v%7oNTV+<4M08&|=biSFjpn#|`T6EH?F>=B zg27~lzNZ3!Kwz0w7C1@tTt460CcJO`+^4MYy5roxQJYa)CO&H})G!<-U(x1k+{Ju; z#T*aI4|j;}%VBM%Xx%SrR&IriF?)7$q4HhxHP1>q42v! z1brI|8O%#R!U2O5qc#ib)5r`*W_I#jMt*~0qOrLNpY54LIB&Nuyqp}Hai!-@6D+Bu z6NSJaYe-fe3Y{@UQ2p^N4z7WOS8@n?!8?;2i_?I9$E6VC!HjlHaCkR zn)3(^uV!bftiP@e8Mb%uE1z)~>mP`k6j6Nq7cFa+Le}TZx4PG?6>~PJ*6#QPbM_eB zFkli{?B1|g^!sc(H92SVhDu_-W@fHNzLOaHH<{NQ?5oL{fV0o7O7S8_a^V@_J08 zBa&x}M1!7>bVa;SFp73~VW_iPGk{`A1%bpoT zHMesDF|ufPR`jRX2gWBIMW~g40F}B_hIx_$78^$6X0Z!vMA<=Ob59SB&ACqM zT)-DC8clX%`srgGHsm|uce0YE&34X8z=p6lK`NH9{*2I$|F$$R7I?gNJS~mf3ni107}CJou$kEw9?*#K)?TBDfRnZUs~IPzB*<~uqv8`z-|8MBFo ze=e}J@FQ{gZRZ(L`vvnO-#>!Py3eV>@Udwx_|?dA?#SrmKnpRoaweWG2dmO~*WBK1 z02U{)^&_bSf6JfCo5{?!ch8Y}UaMkgMpMyqR3=BuW<4;z9CZXQ89`l}!Owbbt zgHGdGQ&+mK8U>h4R@Cb_hesK7WqxI&q{?88Y8aVu6^#{)cyX?asPX6H8`s35lnb}9ZwUg7) zZ+`nH`wDy+=F8QMAN=>jyWGN6zy0-q^Su9qXZS__2TuIN;2Zv9tuyfx-W&dO>&)!e zUin5k&CO;dH~VkhqY?{%(6pFFo43%AkJ!AHIe1{&46GzHk%o z!sd*EW1IKjXLT9`R(8y8M3pLm8USFMvt2?{^GPS?LzNs_q=XqHal+{;?7>CY#O3@f z_3!YLB=7J|>Y-{pqkaR<>wwd#w{gkTTvO<3-?Y?8?BGn(u;2QWVy~?WF5)HiNwHY_ zr%$}fOYH}4y}6te>O0KsPhPK1CwqkMgN&`b_=5kpoKnxFaAST0ufwf4A5>3u$NB<> zV#}{bao4nP{4@Kv0_E?e92kBO`9H0{f=$4>P_bz->{}c z+-Sb$iB${#gR~Aa*)Xh9>D7X1z5f38hVEDPO9jnl^S%fcS-+%W&OT&z@AM!CawHp9`x%- zG#ff!@M;0JW-g$<*#Ts1;jH#WSA$3&y&Nxj7^{a9aZ7(z%m;JL;$UWx>~t!IfoNo3 zw1VH8Y~5J8an{tLc{6Fg=jbg_tHRkJ@{q+m;j**cUcLpzTD3S~I)RUH;nx zC;KbaZIwx;Xn}A$D`!BPtT=k{Xf*B5g2Hs}XcT+n?&k10cgl=*HrH(}J?IU3apvlc zYtco|IfGx5P7Zoq8(lr`JH{C>LESpkoza6=Ng_|)R}D8jc7|0 z%O$MGYRyQy6yu3SWn8Y=gdh9&S`qN4X_XUlRQQP=%bv0P`6bs3tyk^lHuo*vneX=& znlHG|kzli1#GUcB`E3QTB(DWhb8=&BIM#YL<%ph`e?8omKJfc~P1d7u|wh(DA8_NB=xIe7Ra{wUjsSv`(4h_JSFn*s#u0syF&! z?7!hnue>QXaE|;BbHg7vSAq@4f7J|q%{~0dJzaGc?_Ay~!uLxGwFU{&f27-ucV+__X}n-u=y@n4S$1 z>Ew*{PCfF^m?Ae`eZjDCaG$kC#Wr_$_UO3RA)6OvrTXKg(b_TBY2B!KUy9^taM3Bw zs~$UYpCD?qM&kggEvwTT!>@V1Gg!6emz;UOXZQcnT$ImQqfNcldNaMd{%k;U!GPB| zWzC3Jr5OG_8UBOcBW9wffY~MwIW-H&!8g-Md)7{-=QvQZsvq^65dj$|Y3}!O0|TQ= zd1rdvnF@ptau&LA)Ve5?5Cn*edMwY-L=X}Ey36vVHV?s==2%l3%$^t8dsX0(laYi} z(vPnWU#VWSr8c-RQpZdnvm|GTl}0o8!LEOl5@zL+)0rq+cR&%rWbW_j4#Z`fLmH0)Jt(MQ!3cLYMXyA#_{O2ZhCXE-HD0z7-v8)#H5cvjMG<*t z%<`l=KsFL-IEK)=tryab;$W(J&W@w0W+)Jh!Jv1f6Q9}YW5))UrKmC`U`Ty?lg%M45VPgnk+ylC>eX5}2p zG=>1V?COpQY_DQ>ho181WWO7x^|XFQ<|+NX5Jo;y3sfj-SbBPZQw9#1vw9y0Ew=>~ z))$u8g;~FjOU)USns=WVj4dzr&XOiLc-9k{ZM)qk$v-+8v3$PPAcHJO`eARdLpEy7 z>s`N4mYz=Fk*$nUNv7|ocKE*gU^V&PGqs+h0gzzCJW_f(tcH%KAib|!$)o!4#jcoM z3b6#y^LvMzx+YC>otUkDR>X)91&TMLrryvqM#F!5Fy@cJCW{3HDm9RLq$v`W0aWh^ z{jtdr3BiOP-6hVE(e>maTK8 zL$YDa()+|t%B-GC^va7?%1BRm6}gDou%7tm$D|%*!1f}nnG}c_pUOI04R=Ao^zJsK zKSs4b4R($9Ce4$+byoP%112_eY%UZFkyd`iI_q{54r5c1<|)fFcf^?f4c|&e{DNu- zxVm%{vQJ4PFO7^b)=Vc3zO~)#9CtWEe%*}5Twjn5;cQnn48c4-_Bh$*=%O=t$X?&& zXs+cda`hV<;;@}IQVQcMW5}kGnQ=^I5Au>$a^5$S{-p>ih+;|n0T_9_8ehV!?zO7e z+!cf7x4s16J9$xi()Dh({=96A`Sbpcc+AaA)8!5)fDnKl&OU87^;E==H9OL56q404 zfoyY=u|`1fZQJqYFPc$7|DykjwXrkM+%A2v7t7hK!ReUyy4f<#4d@hb(SOnAtG1XDO&uM@Kp^#$C*bYejtHIpl|21s0m*`w&gCvjVan(5)FCPltR~rh15G= zl=li7;Ix`7JLVBSY|9Ho;y$L6;olz-qEJvH{j=ZK`$qWZ8Y`2cf;Q2 zbX{)x&bc0T_>}$2_B;MB_RMVbE%sbGW0${de))1dJ#8(Rf72PB=-EZPzwu!ja5}ra zg?=%(c)nx0xhGic3H@KwW2~;ZN=F80)T>13gF0 z-eQ;V)938j({|NaDc%TRj*1 z{8q_)hb%4Oy|wtcoz0Ho;UldxVz=k~J@?H;$F5m>-m2L*DbnQlGU@Z-Tm7Eu!}4hwpS{_m%4D!pC+0Z>2x< zzSn0Rz=c*>Z^9Az=C$c7RT)?_k^7t|dHcQmg!>1t{8;xF*UW_*4o5A-^EI~(>Gpuq z+Jrc^KF!{+o!J@(XZF1Hf+$S;6+qac<9FAa^X4;;wO)EU-<*!#vM+R`$3OhyYDaqV zt6y9#eLH&TGWlrfNA9|-{Wn-&&a>0U-#6>c==cl8!_HUp7umGg%URwu>D(pu@#U{{ zty;si0%tIvvLEr3-F&?LtXz}7$~7Nry)|(HVwwHJ{Hpcr%Iu47LDcGC%fmH#)=Y04 zZ?1V@)xRzar+OyxT{la=vu>3Y^3YS6fVB6RwYl#UjOU{V<~mnQ_uH|(&p$)RcEx$= zL(_ZBseN&md@c(r^jz_bletE!!qD2_aB{af7*{T2t#4m?G+49VaB6ffe|E0(pVwXi zBYn$VbBs;_XbPtN;LeT%9suPV#TT5HCc|}L#OC-bL1Fc&S%*|snLKFydJ&v?P6A%L zOTeVrXPe-r*`eC+9|`RF+CsQ5JNwn@Id|VvDY}HqzV>;tBFU1R=kTHax1M$> zBNz({+bVzVy4@_zOG8=7U)RjB(eIpDm1Cy&oSc35#61=>iYv3%TES^I@q9G?O7ALt zXLnkK;mKcWBb62vOHcJYGM9SAtXz;o=S`5dGoDLHm}7?VikPKC*X-omK*E&Hd6wJT zti7u}mralV9uw)VohaP=NtC}GEz}-NB|AF|5U!W}#F*I$4jk3KXj=0=pWdx;{B8ek zo4FLh#hU=1VCY~tWD8oBnuHZq9(-`91KBw_T4-JgYY!HJ52;|PAC%Xl{Gd=Qk>y$4h+QwuwFtY>E|rn8jUIMp+0X4Y)-m!+1m z)R@g#vL+|PO3Zyg7n$O~-%z~-I`!F!O9}%HKenvNx#JUNE2yr?i(c7?V@lRgSitTp z?J;|W@zGh(+OZL(@{)~H4j}q6V<-@O=htXkZ|q&Z>#ogsh1!>of9jrplXPq|y4UQy zBPy?1MQ0WOGU;}!^u0<*zVYnC=99L4r^?^8dD@k^+60ffkXz|^zBLS7-0hnyMeD6c zOhqdM7G@`Z3D!wL&13YVWB?;&|lvt_k8mX2TB;Nb(WKzFIcggGdR~xbhAj#SieaC zHRG$jGp~Dt-L=q^t^joyM8goOj^#6L+&TQm-V^Rm-q!uiKv_ z^)W}<&kkBjkx1|MLg+5*%-~|-TTS)%uSjYohPJtcJYtxyE(8YnZ_AsX{ji~%ku!#g zRlM7*(n0E_pDcIp4mkb^-V< zkeuGekqaD%Mxx59q%L@$e7^He?yJ2wr+0Rc)b@h3UfN|Dor}Ze@$cQ8aQDZA!lnnb zu(K0UF<}<;2fr_b6;@itgQ4!&KjTWDE)=nkHKDNvf_quzRz1R8>`m+@|3W{rpn~hl z^8?85)(0@ZV$fC0tYjfbiYM)=F%|+X-~8-9$e7!nGsBv_Fdg}O&3S*q?(UehI};1F z4?Y*FAb|O@IlmFxj`NmiMzso5bcWkv?5C=9bMS#P{<{QdZ+G_c(Q4E*7sa6CN^5q~ z%)@d<4x?~GlxCAZ{){n8NMn6rT8=7eaxfi@OmjFXpX-kXJXtweAB@6%ZQdraCrKJr z28|VEvXIL&-qal1OCE=wnoN6GP3dHBA`QCp_H0Ap=*n`$R)o6;kvrDepdjcqp^css zQ&HqiMYfp-1v}tGc2@vcJnST=qS-}O#Ibk}@J#~}ERrGTzyclB=&>l})}yl{(h50K zG3E{xqrAgQP3GTX$=`9JQ+4fgI>2Y?sah%H~W)`22kL7I6iUC zDDyHPFJ`PpjsxF=5F?We&3^vh>DbbI2f4Q|OlVCR){&+)H-E!-{BoV&ZC-E$*I$B+ zGZ^T%ujp$7pE_7PXFjIycFCh#6#qn||Cag4Gkg6}|H0U=e5g_#!{0O)F8}r^yD%N) zK8!en%5^&4ryg@3Xz7|eO>q4~Uy%M|S5M^uffi1=bG4plJLWlwha5Zc#Z&1|7yRai zxnOlCy{OgPa1MFS!X>A2vh|$!y1xU5KRw;l=A)&7(qoHWSL-P`)4VWG=LOFvjuO48 zFW{>mX|_(g)eoOp5tZu6X6bNT8c3Zh9laKSd4+$ke$V_itC&uHxgV~LqjWMH-ss#& z9iJv)AUyAPhrbR2YmG*0&XVV|9Y;GR|8L6P2R@GTyziVDtdy0aBs(t#tCtYO?ECIu zH2^`1SVHWEcAcHYKwMZ*goQu{vYD8GD2MjBXOXrWUHZrS&d!>E2~_|@rBv!(0Elwv zRQ^PS9LLx8E?5veQ!Vo`Dce^i=Qb8?_i}f>3q>WVllI#C4rI4>K5m;XCHz_J&c5^h zeV*U*dwx$XA>x{kWa>aBzYv`6&S&v>OM5%J#!aUrg7Z}gha|#<3TuhAJ4lkY-4i&8 z36^Ckc%x>!Ln?-ME`W%M&TaaE-tPlMYKvrq>-)45;6|1boxMxE`yK5Fl}E|%Q^vm6Wurt#ghxv+{&>MqbOXIbHt&vftc>e6Y_fmZbjC0rZ#IDGm3+mCbdm3wA zPv|YVc%7gPh+4&45Ykx~od>B~SgBa2DXg0mSLDIP;mQz>Xjw1T05l$tqbFy+6`u?; zm4dBJHA7fIuZn%Ll(|&yHIMk~;*ZNe3I0zUG)a;n-Kk83jaZnD;gu?y1dx+ruMD3o zPwQ)SDkr=7a9WPmvZvkFRQM3Ukv~~~I-iFx_j1X#bz-z$SaBEZ*036y3X)c_3>+|F zhIbh+z#mz-7?^N*7>%b3>aup~xwAp*EniN|B~i6fF^ieqQ1UvJNb01iO>wpsEP=rv zGZh)^bxrub&u@z5zZUmD)h(xFSo(u{BN=zk^+FT6q}*5KvnRz&pIlJ0?yGOa%K|6| zMCHq3cB*wt$)4AfsrJvutu6oVQPUmz?pHtWh9@pr=K1SG!y|+4S#?Go)x&+QEqAcv zmtHrce=x4g4+KzoYFF*ymv`w630*R1ovN7bkI7+w(VQIon1I_>J}*muWCU#Xme_{6 zt5zV9Uz96DtT1IS1xvnUx{WHQ_4sIc`@Yua+*0%>kBDP#elEP%8=L7wFHV2*@@pn+ z)Z5V?gqmXYgs< zwEexUW&MgN%V6}Q<#kn>YZY4E!r$=b;$R@<$`a98_-$XEl1WGI6-gy2?@_1tSoYOf7(-XU1GAp1h1a&n?J68?yANU6OP0!EimV9Oa~hLYi*Y+#Rk}LARrECU*8q4Tg|moEZv@AUUgU*^ zuBpf(jvPN#aF)DMkg3MTUWjgWRMjR7);Ba&r+kZWlkh_g>!8EI-!oOWto=}cHr*fz zOX4YATlOcW5)dd34gtOmE;TIWCYfDU87wIGLB0Ro<4$P$ik-?6Pf4PHc;M$vA+(JE zEYt(cy<5S%AM6odQ$0G(SIc%){_WR?U0N)09nS6W;0LE1=b6;G60{=uzo^Y zPwT<6fWMk0TNFS!*1LD|It%0-!1r8mSHuvB21IL`dO5uReLoqF&CvD{u>^EE3si3J z?KK>(oRoPDBfF<0Y`?XI1dyBzyW`NY3Se0nyn4~B^evDY$yfqvMQ245RwC&Eq$OPm zyiL*rcEKD97%L7`+RTk*qh?uLwGDTL?*OGOvepW7u^#F&?k6Z3CyTb9J1fZwvhv~2 z?6Tb4N%uAB-sVl%{v<=_k1GN!&)b8;Dp20QY`nM9a%(+~^d_ga)qW~9+6uAmAhEn& z0VBH$n$CD3E8iSIoZ#)v(0OY<0XSco>mTD1 z^VI>n(XYaMVa;_{AszME3x`@3L43lRuv@NqKJ!o+Sx9u#{f-syh(Xm?h zuLvPg-(Au9)OhjUvtH=nw6vkoSf&*ugGJnI_1F^ zH!5f6NC}$|b}CIpTsI5O>1LOPv}}^vmUD_u(Jt7gX@d!}6h`2puh4@yw@$H^S@NR7 zYxmw(9RcxeVlNA(X$>lLloiGoNDPxp;_g?=fS47DV>YoeBqA2Cc)qJ7N7Q7v)T2X_ zga3TZ15zZQ5^Dl83UrErj|{h_6*6Kwtss2PMFT1 z%uTz;tJ}kgr4j*DT-|54mMcQIVF0o#&GM!q{mi$NXTeHMN||w>2UTEoWV&JDD_7i(;4YSn=$;lO%QorrC#8B-n!nqoT zXtbsLvzAr0S;cJGnItH*Y^zEt02a`aH!9`|X`A;~%6=P$>q2Z>n<&kd1NZ|=J=T6% zXbk19us$`RDrHA0z>RnV=tlLf<|PKht&Ri(`py4tBv%Wk>V+_i!`NYoBsAPH!v+@k zSu^0IqWJ^|bMv*&iepUgG{-1qV_PmS%t2ia3TjF|L{h1}%6mnjt9l}a7_avWRBiF| zLrZV(hZ<5%oRTL;0;VK{>3xt=3s9o|>|y`W**Eg<@P0?hf9O5;vAgB_T5B&f;(O)E z`<7q4J{a2G^nK>;jyT}%dT*Ihm0|XsulR3jci{2v!z+EWD+?$6r^KwQ{*ij%0wK4f zD+jL(_gxf7)BTn^RomOI?q6{)ic|MxOE{xv51W0vo^7bJrE^|qpWG)Gim)akJLPC33jBFe{;-9^PN!@KjpFqjW7c>^o%<+7^$`NrPV8^C;ffOPu7>)z;dEHzo+%xHT~-BrTmAxgM6Jse!fxv>2Pc0?qc^>S{H{p zLHSAVyKYb(S_u|TmHjsZ@o;eUMp&y1t*Y|q<7U*}*GHMQ=+c|gk6N9PhlA=DL0I*M zSNm!*_xSi0+J0|viV~vx?kCocg-_hmNzvh97lN_33#R6HbJjfPn%T8BrN6<4drV44 zeju4Oe@bzZV0QN7&+2!SK;m1w;Ye&|_VQ}aM?(OvM zT^oUFxVvt|AC=Q1_h^t>Z)~l6aHc-G14Mtmv|i4?cLwM>Kl2Cg148!X>mk1!9SR1~ zHT~4vwB}O*l;=wNra1ku52oOCeTUt=^HpB)!J#kj;LstO4_^wO*buLsxnsBZ__TY* zePp)r(SBD#gxd{Db;E@|{4c@N+D}E^i;dkfTy;OyP=DP3$K@aRQ>6}F5)b^X;zf=; zXrJxup|^tId=r-A`T>lp377@Z3c;Xxz8>**Qxspdk2C=jO0lbSP1O zMjttv@>9qDrhopx8TaR>-#@ic{xd1R_ILW%4*XhUe(*wZ?CAF3MsSN_F_}ZRygsn* zXX4kk8_}U}nyKH505n1MhKB2dD|7I0AF0LVPq#0uA9{3R4BU6!9eYU!@JAo)-kAQW z{1h2;kIcFU-S&KF3rMEGh9KbaK2nR} z93T1Gk@#8pwXZeS-K2d*^*(y_vL8ERBU=BSM^n$}%SWR_uT&aQxH`P5Q_3uqY>2@r z96i5U1nC1s9MizxQQxh1j04dFd|y8vW}tdPTL$2S>iaxAWgK0Iyy4i3K$7e3OO09z zhz~V-z!SxozYcD={g60IlF%c!qB(MroCC z8Do%4sMm)V8b@eS@r?W2$^JDxIj@6U@8KOvn!E z`Fa#<#&f;6bGv}dyms)Ls_}t6`XiTrEbmLu-DtKtbA?;yW+vw^{{(Di&sSt@B!2Ux zmp@NhD-2dT?Yu6@nd1X59BAJOQ0G690N$=ryH8u~+6f{3=N>~%qj0MN7TR+$a8`#Q zh|@FTW$jG5N7^g0=X%3Q+ONCL;czT*j$5U3l8aW4Mym$^ffpMAQ?;FFrU%gon!SoA zn5sjKWd^5$vCJPnbNgg;ZN4$zpBGX(Am>jo7>%n+m?J%kXcPMW4WcM4sJ8X6r(pd~ z(ZJL3w&@{I3u@c4(1G+K191pj{xt7JPQ`uF6=}BHA$+Ls4afO6P~63Cqhzj~Df_ zS6J7)J=&)}F$a2`US0O0X`1y5jft__t)79)<4p z`Kf5+9c7{$$BVWH+&jtqbVU30pVwmM;?HRN#s5h`m56qgee3{|comRBW_?LfL8@H>s@vS4-Yf&RoVr+WMn~aVeccHOE=KuBs zuZYI{ks}}PeM2?M{j8Dq2L0;M<6}qQErY**JjLKeZ)(T|@<`ixM!ApItU^3BUx-EK zmQO`W7A(w zgJ#y`@g7z|MuRut96HYd-R6AfX)tg+qzHSNd@8FNnXV2T?7tDEP#>;InwVIypZrM1 z&*{bmzo~58&1EH08I+#iFXH(wH+t3ey8MiLzWodCG4*2ivlU?H18DDLywqWek^QuLr9f2OqVy3J)d0Uw&Um8F8y#%hjc2e*Pr zFVL5TZ|{J~qk8m8f>B0R0U2v!j{1kmu~)66g~J#%Z8K&@Ik~LpgP@$p%+m>(J!Tar zkQab&7D=Nm+Pr(SCiC@-&c9wy^KLviv#a8C=mn%o&KbH04>J2R_(Q><{dD4{2)NGI z9nD4Dtb_^;NgT*B8u+9NJzoQFTZT`vIH~p;rzelS6(3v0PLw_IN1}xvv#Hl zpYq~{uGWrVdc$>g{g5Y}C%PLW-Pg;F@L|{Wp7Xr$Q4~h{?{vKf92d-F*Hqb^?rxM_ zi!91MyJR;tgcDpFe2;PBBF=d2HfxlKlur&{!NHTsq^_Km7{0LvI?y&X|5p)f{mAeC z7(Tm|I*{Lgq>;7s(cJltAN=+s#l;~!;ljWD`+w%^uYYHJYgxjS+)hTkkN3{c8uP7W zZ@0Pn6=~-yB)kAz$>Ns0H+X5*y|>p@!^LH9|G`Rlug@HvuYCt%%g!(7QlsOGEU64%6gNm_yuP(LK5!r z+TgOElup!=hx%J$rk)Ev5Nl2JD85uFgDO_U?jUHky5!y|BZ7~7{LcKWD!7^a_@i%LWqYMBzpk3f>{=F8H?c`1H{>onNy*AA@O6&W(@S#kjo8$N)u#^( zSZ#Zd09Hjx(*qV_4qgeK6kiSSc*)!&BSH7Y4j67JJLy*<^un+7CBYcXfTbY1&s4AA zLar*X?u9kg!W%|#rQi%X{Xy3w7k*rMyIlGD+0gkg>$H9R@g!f1GW&NCxQwrvlg0P0 zom~vw4LEC~wOzle#!gJV=#0&e&L7Z)VPRTfaLNnE=Zy4Ty`Ef>o1X4ZYMGQR+>W+E zUX|m@#A}ZP$RX6=UmJTfK;W_IZ3pA7ui~jhH=he~(wooEACDKwFg>H#O2Gve%qt=` z#@zN~@aB8|q+mBYV!7XLiA>X8bU!BQS-H!omOVD??FzHz8?(23=p&_k6n90XsNzqk zsd}qXSJ7DZH^S0l$E(Vbf$E$onwXp!2N_6j(u_Lc-L-{U6xi_OS~UV1Zsm+3IuT$; zw2IwkNuzkjYNf$mHl#WAOYe< zG+|r)nV$J!sXI`nPKO{8r)2a-?YgpeE1;{OX_Q)4O*hcP!)55(vZJikkrudFT2s}K zjEQ<%6Fxan8^D7C?5)LkYY-MI^4DT7TP!FC;!I{ZK$vM&!Lx!cSgu%eoE8MS&8_GE zK5p}+hHf{+X|;Gt=I6t4KIwDbSXOp-yh;nQRPP*=q-*szLg-Jm#vo|rfoJ`RVcnXm z9k0Cln(6cnh_ijA+CLpqv!ha0e%k2k=a+X4wBmTf|GcbeLuRRaRf~~fo%e!a7x=07 zwaU5*`m~sL&oTOID%qp7UR)zQa7<5hfzq|M$be}LljShK6%?WK;~udF5pP$)shM6~ zbOx7Q*}B#G^(9xk!Q#nX)cUOq$unSB`4f#NL9myPzNzv-+dDBUKW+ESoM@H(4=;P5 zoUI$iNgfU+R;0eqjD`^|^^*73eeruP_$xG0@k^>ys%4s6N)K)6?UG|HsusBl$HK!c zEp+R(@GZahj9Q#?%VJFw*?e*4b zi6N)Z*x&JQ{rRwmaMt0tigu|Pjg@1Wb|yuCbDx%>S|V1{(T`90qjte5Tg_AQwYr$M zzY)7vBrblM29JK4ezrHo&~j@~37ynx0L%&sHfzQ>8l)O)UbJig9%R3>E&JWiN{-;g zGIcZ4*CeUrT&lk7^xpbg|H9H9q(q0DG*Go%*Jwv}6A>tC=-cODd4l4JeC7$ZcGK2Lb-E`O7D%E${$Q{*2MpjunI(Tp- z*nh$*c+yD<3U=%SDfVR)5o;oG0wu)0=;rZnHXF5OD0gKsn40cc%%OUey+?uTfI0~) ztlD}>M3#VcHe}2G<8k#i4iVQO#bQ+vO6t1LG&O)&ZVRm%0(ofwJ?GH2*`gPuq{FlH zlLdy@v;n?=dpMG+^44Gc1-~Wz0O6$8x*7BVtag+|X|v`hVG<0?Djn@n`5B!Dk-iq& zkAsrZ0oCM&X3jKilu6-BBJiP{V~X^*9B4;+mT}}Yiw@Ur##?ezh+xsgs>V@BwYI=o zg#ZC=tM!|wPaY#^>;VV@hleIKDRP*rtpI-x*-wi4?NGVxL3?!0MAkS*LN+3`Y{hFX zdw|d?1j@|S;@Z4Du$;2L!T797B?uO}7SoTis;7LJ$uTq1LR+-9sd))4 z-rn!z#7xlVLbkT)?E!n!Lz1GJ@uLAZGhTH1>*v6I(_7ls%`Tm0VJJ4S^vF-Uut{re ztEp|{-Ag#4P;(NEHmG$hUS*mQP}oU{qQ5uw&Pe6n{LD*Wq*#>hg4w}w&8K8?tPv--lB%zun=h<{fV9+M!KPP0?=6M}vjaT^r;xU& zP`e@to-7taZL3wG(~*d|XZ~V8yp=XaSp?4cT_ol(peOQD`#Hi&Csf2olxFHlj^s8} zF1VK@v{r=@RVU3_3Zi|2&l`%R>%k9I=!)(3t37^RwfD7rsAOvACtC*K)U|j z2kx>8hRLA(#3~L;hA|g3>I9Q4zhGN>$q%C(zs3rgbSQ{78y^5aaOkg$GKwy_Uyno9;>3KT#%W>HWq~#x?BFok z>mB@p)X&QMba^+9&bzPsqnXxLrHmj{uQ)rD*IQ)!$bIOHAyU2A2hdgzO?1H zKM^Zilff7K@K-$;62rm45$_wOcGj1s(kfmQE8ZEE*O0HUH7dC&6sgu(^#dLG zGjFU6!-$ki!dukW4OX|Vq-OUXRffq~U(%)d&LL5{pppS~piI!SX@pjsOwV%PdXE?! z)>1X~t^cov=nUEe2Sw7JLS15}KDO=hl^E}P>tMWK7hfWuo?mAM2kN`bHg!4NvD-89Gpcn$o7VSfNMTXey@f$|G4()h%sz6Y* zDM&YGo`ZU;C`P8jG^3a~DzcS#v2r02qcD;F#cr;bMUziY|Mz#E`@{L4sDk?SJ|LVS zcSBsCZ~UI_y(mWk0l};eN8z4EZ(}j+UE6idz2H*Bv%P@rQjsMqsGXU9zM=oeRBhAU9_8(G)$)Peq5~*DlzwN_i3*_67Q(n|yof`T-kJ6DZhCm6hJd z6@%9i3MljR8mOUe-VNl#-D1QL4+aTkN#xy>!k2OpTcf!|8nw#+O9@DP^XD9$L6t z6xKDQ()IF?%?VfDU1>X#;n>hS)Z-v+Jr|p; zV<^8*UWugDWAFC18H3TNq-zguXn?u&g1HrdKk(DjhF<%qtiR_-1#0}AlivX&J?T+S z64=;7YhdbXKPKCx2CbX-iwp?mcgP4KzI!Qm`5%%;5y3~dOEe6ZDJ7ZnSTHv zo73q~v(Ot4rq9Xs;?tG3jQQ|%J|i|?fB~v>kYnGcp{x4WU$}#lG*xN<_)hg_6^+cL zaPnOE4bxaJgwv&_a&J$ogw6Z@s_T#4PWa(~OyeHnlZQhRb6$i%}-t61p~Thqw&E+7#^|%&7XM1YPU6bD|w7KC|TZ& zv9n;03EfB~Yfc*k$u5Nbe&{H1x$eg&z3BGx<-3?>5oSRSIt#MtVbSsX8UBa!A#~gK zpo-Br&Sy*=XMB61Ll+5`unX8$dB~->p#K13@qT}q&*ohajd5pS#&48k)(wMqN<%3x zIKEQBP(u%-s|j8JD?6?H`TxFUkqVt5$)FHUiGetzAm02n0M~E-;)C-1=RT=GS5rBC zuyAanu?!d{mg(8rU^q25;P?~gKyLegRqL@|tSLP<{a`To=-oFZ9{tml;fR0*RoaN=<|v}eE)eM+h#Zws;A|7v@6Dpm{|nhetj+@ zB5E$mq>+3p$W8An-0Bm@wLJfFc_Xl&xF|4pWHf;PH15cW>>&{)`n3c_i4`x>mC?{| zIo>WDk#4y($EZ3JLCOlC-{XmTxzI?UPtYI1rO? z1i(l6$r?zM-L#R&@B`?-;07TQJGrD-14K6Cj)(?In&5@FHaD;N!AcZHRO%+6Mqyb^ z-W?P=?NyE=hqq%Gb3oZukRj+f%>;5dv|%i`7)zPwK6fMqRsX@;pz1?!gQ^Grl03wJ zr2D3@=&t}mo=N$>|IMu7zpBc_e^IL9zY*a5OQ`DiRWm;Hp&vk1zsG|9&yj||<=y(f zAhNS&a}HV(8I}@`+C(EUp-jfYuljZvjX7ZiSt`?Xtc6g{14e}=Y1^2hi+WuRx+nC) zln(A&pVSMDbpr~kr}Sx2G-i%x`L7J>8l>Rt+yCyPk#3cw1yS4^OYY`3-t#c-^W^+9slWJ__2wFj%SwsgsJmHlE{z1w0-%9TSOPOLW3;GHQ}vi>IW2%9 zV75kJR#mUQl-7`T^n0}_l`HvRE~Eh5x3p5q+&;ZN#Ai^QxCWMiV^Qd?`36WLF8b`TprZJ2)w6!^yi?C- z4Qb5)jQZsOXA_e0eyXA1=AgM?r>-7f;hB)#uj^LX-2A`)mz4h$8Tz(o!VlwFGtf8> z8%p@qE!kg}zve0VkCfc&j;@JFRSqUb$XH!OuVM*GZ6Fp^wy)T%ac3&u`zvmCcydMpR@;XOQYFtWqYRu6gW-_? z3aD%;^F}x|IJn&R4wWDA3$cDBSPnE&5X%xjt{jwi!!RG@O=$ng38X#B<$Qd=AGo3P zoNmp%u}_{Ep|_9{zylIwDv2R*?_P0Ul}#xlp|yzOoVrFhc<5qa7uEInQGG4Yv8^j$ z&ETOBI>^k_s8xu<$&daN_ms~J*big~HC{3us9@VdylRs?>L%dDi(sYh?FIX=3G+|s zXay>(D9v?1MsS6W$D4hZj9ODDs}xnS7{~Z?;T6ACJ036Sj{kz1?Fc>SPS?;Phv3~3 z9{ic2F1(^UJEG&|U`WSKeKCeGMkhE6Edsy$D2HYj=wbk2&EUuJf#84su-D9T(jhqS zJI6u>47 z=!5;sXeL6_DRgHGj3=PDp$x0I4}?vcXNq?VqJ`+G&10-qMv?JLr5JU49`UfZkxC5tC`@rV9QU&^{8&)%~hO~~=Y3LDdHpkij z)3u+v=UmfnF2j%~RfYc=oL+fX(hM(hq99k#RGOf$OF^*zogxTA=1Ul%Jq|22YA+f) zu)-z3z|NR91pHJ24FVU@msk?)JaoE`(ZZNPZWIHq0HvcBKJta1*m*;84LbQbL~Yst z_uG~gMoH7X4O`2<7MDFMc}OHr%1kMnB0ZQ`=@1gouuwQTg@ODHmm3H*FqLm;Fq!HF_A5TudimcYF0s5{S{_^7CWpX;a_^cj?g`Fu6G0WG zI)R^h@L{U)j{YjD`kpW9sPJcSY_4`)9rnX;ltRHD4nq*CMyF z0-z&b(oX}^Wh$kEW0`{40?5!ef9+X*BgXIE5k=`wnS#yulI9c05H#BgkEP+5f-_+^ zfuc2k(9CG$QYHs|5EgdD#Ze5zV8V$IleJkR%%tkPnu<;OGvOwsRac=aD04RP@s$O_ z2~dg;{ZiHTlIo0XhN*O~l~|Ah60%P8u;fg%RFjn z6r6||X90E6Wj4=aM$zyTfz-eIAMQve4iO9$G9$VBO^5_O+)$-YE4Zrtb8#sXY;#jI zBCr{aYQ_R(O6_8%Su zm^SG$=lbc_iCWzO0+z_)a#L(7Yl@C!cKOFzc%`5CG|bwaT>%!h5R=kPChQ#8J%n-S zzN2=N;98}R0H6g!o+$_UB;vX>TwrfdL_`&w(2Uz1fLI+-%{C^I=w^mGtS?l}s>kPYni z!nb;O1XJ+fgI|qL%I%SS^m=kij`*#v#g%u8(#Sj8{<7C0m_Ffdd%OLn>G-2zWdyhM!tglLx~tGicYhwK$k6LKl(OMpTZdC#xIh4FGH$R4fWarOLd@Aq8y?NnI&*Cf3BOouR9)yjp3k_@l#>O*z{A zu}TDQ1*$FQ9p`->>8H_R>+x6@Ry5L2rO&8i=CnGunLzlQT|AMx792?3_jm4m^>K%K0_e0^hGofPv2Dg#AgvK0(K{fENttwV4frpj!xV5d~q zdbp#v&;|@8Ef}tALmoCSy5rE)OULyZ<$e$lOW}|s>TlMwCuCQ!+R&-ywK>I;6_PWatKydrGQ()}$rlPtK&tV!V*%u^=o z0Pd>-w3$^Y8Y_Hwc`aCRzx(HR^giZ7R|T;nEBU4iTdN;v`l*8dvn88)|m@k=jQ2f17uwqeB~s zz3=>?w>EnWX7EO6->g*rxoe%#et76W zU=Gjip+DVk)i(4Eg<5TGM;qX!qE2yNfWiFqgGxt=(sM2lPHSqO1gvLT_IYVw|S&=vt;#RjQoDaG=}Ke?SO6rea8G17L{dm3UL$^X{m;+PNOTI?}= zb-ioHfueQqH&rNZN!XV+8K#Nz;A)&5@-mXYP=K9Oa)G`8WPGbnhJ$*`3(-(`CJaBh z5eP3y+wjB}1kE0cKCgA?ogeOPyacoeJP01|^?Pv*Nu?lpf-ku*2sDvXyb2cX9!0H+ z-b*sYb{E5WeZz#ne7#{AiuNIdn_W~{>2{`L$=#H zt6r2k1Y`_O_RU0u1<+ie$T!LtK!oCD-x1;1`EH6MHm=H3!MpxI$56}X*N4yd&#$Zedt=z6 z37}r^F1**^bEQ?cdQrY%Y?AcvVIHL(JB{(Cd6g2ceZrM&F1>>-nkqXrEtnprs{j#*- zRkAuIfgoNaHsq|be))5j%Xy4&)Jd5Q(+;&HPfY!05BeFQLM(b-fpBivTt}` zq3aqve1%{MArm#&)h}+KT)6=icODRU21%3yi;W8d@fNb!F;K!Hqki*qUxx;lqJWe0 zRR**z4Vt;&smj`$AU!cajIuftEddG^M7_<&!^s?=flewM+l<4Ri6^PsfMP^=`ySD* zPaPbfo&CazKKRLSsx*N7GN|h}W<#NGtTlo?y3F+4&~vdrwxNr)+Os8l7QF}jlC2cBWCQfME7OHpIY7!=im+mYye*!gQBAb8 zt{UAnK>{1-YM>#|@)jL{Zl-AbzkkQ(d`eVx7hSXyknBZA)6AObfy|@~t*1#glAm<8 z$57?YG{a0KLA7_X4vxC?U?I$;U}$>Yg@N4OIr#7hqGqw{`+V1d&k()GUd|2@jSuf) zUN73Xt{&-Ysh9)DU7>>k4c3o2se(uT?5B1of0?8DpWxK-9kt!>!>NNiaOw}EkCi{6 z75^2@-XFe-2Fm;|Y4-k?(bOLja`;OU4Bt}^el%s=zD-T_OW#Gf_h-Hb52O40L-+H& zmh8n$_>U6AwZBABoqG4iV?TwWSZc_pU(txhn}QL6rAd!6ALz;Sdsxi|SmH=564lSu z<<38-3+M#U-41?pViJr~%xA3ki78!`Pw7wL8JMJnleBm$*b2<<;5T&A+6r1oYh=@$ zL$hcY#wE!a! z#}@EqT~+Q=wSo!f%s}_8Kfm8=hS^CEyZ}_nYAN_MSbeUSwT2*I%fUvX`=QJf+=Nr0 z83v#V`#b_iU8iee72l!Pf$oT7utj3wW&k=O384>rVN-|4YXi<=Y;M=v<9bVeFBhD3>RYfc_{36l|fEw5m8Z3eSoGAIg%pf42L_^s}imDJ$Og zsA1qegl!c?Je{^}@}3IYwX=Z>Og90Cl^SJkV&L6^Z7zUYNLZF(J#hSH?Tf*3K2cf; zrIcLTk7sv`Pf`WDn4)Z56`-=>Tzw z+J{Xvnu5%WMQSXst9C+C5ClWr3&e{91m6?-)@aZb$mVk8SWMz~jVQs8E#MFbt+)jl zn7m4sDTiUx7F8%;_%hGT+01;HIITteH{-7z8(3) zBVx4M%Z#_U4DPE%|3d58FDHs>v>s@Oyxxjz9niZ6lObnFT?F+T7W>7ZOA##;koHN@ zc8ql}3xyLR=I9=E9QueuxM0?Nb`ES5=JlzdOdsx1FRfIX&j#fdRv@XO`3u5&Xdj=+ z^4O-5;1$(!`xZNW*Ai+jZF;TivLh>b+wE?c&5?S3bncEALerFhG)xc%EfX&LFfsdrls<(cI=hk8W9MkVH#^~A}bJQ7p}(rQ9K z7XhXBc zuAVT}Ow*{?F3iTTYccnKaYUce~oKiEnaLD$~GffcYbn9;t zAlE;8_2)Q|s>&V@ml4^@b$z(GLe@{K`=}|K|2+rrA1LjzMvrCZ~ubqlT^utmua|2}Gy7{he1AEd|uFjVN z@~&a%g#bzo!<};{!}Me-fLno#l?jFzhCz{ZoF(KSj;(8Q`MJ37 z6CX+$;bJXF*mnZ3GmIy$kN8Ew)_vyI)GOaG^}6KFp7xg9oKJo>8n-}MJG&YajZ=7u z8zls?-wzK)87im{!~xMHvjPKaw3{hH(gP|a1zV|7P&S8u)Zea8^|b*l?>_AWcB+C5pfN=~6yb!}IA`+aY}YelYAB?x4B z*lEH0)c$*)bTgFFQXK>W5RUNC#XXN~EX5v_ZKYgYz^^pal%irPDPkIL=_N3-R54ng z2WPhFJ5|-Q`sP=Eml_}j(PQbRc87J?xaoA~zWdVAU=gIOiE%b~kKh1?iB(}3!1tT> zb~*#ZGFJO>?(Xp~L;R{eumDY~ z>=ssfsu2a5!BIop+As;hYLjY)I)|A}$*=qU98~RqiB$+;H+KT=VpBJr&2qr#GCme8 z3CmAS%L0(PuN8t^U%U$;?rdt&v6*@eX>ol}{d7CSL$odQU}&KdoS%qb@4~~W>~~ic zCIg$X<)_Qt?CdEC6Pwkmt>zp(uBz$6j-3I=(%e4}$fUmYkuTlx$>m*V$*X$W_0Zqy zn{8}*XudDE-A>Ql=4i+3+3v~Dx_5`&;VkJ`eI2!HHk|Hu!;bsdM*nqhxQD_OqaRb= zpDORMTguzL_uvCPUmxyy*!=}5lY3E!pG+>zjgHQSS5F3K-+8s%7afj2{Lztfhfwsn zB8CL|Bqv&Ww{F#bC2;y@)(sPuy271u<^H&VeKfZ|q%VnfZ7vRU(T(F`Y#t3bG}%mN z6@@q}tyrT2*#Fjd%1f>%mnC{u4|v_P?k+pG-Q%%p#gY1Rt{e7+?y{R-?wM$KH$8Q9 zwjmmu?!qam97h>gvf{eYP)uUUaUOgTv;kTi+H> zA51=bYH%f3yU)B(4w}PoU#exfueWsPWSm(0wHmq+ceFu%7U2hYuqc`h%$gz*XQGrw zYz61{i=vI4HMBK2v{fF8!F^|oU!J(Vw{e!*Z6O)~6YT5whzaz>o)_U}9X&$o@$`{| z{EVIi=o8ta{PeUdcY9+OU4W`FULFCO_ST;3KLiHxTt6Ppbc5WSa|+k7^S1w(W+lE2 zvOa;*tho=isys&rOK78~&5J;x$%_tkAzDs4Xzeh7|{AR#n zwW{lySAGgM-G+N>*Ke-6N5I7^@bPTkpiJdz6BCEHr=>~dmS75mJ6}*Py72(2e^BCbff&QA(T#wM;6@gsuvG^ zC2~o1SCCuup^x@~BHf5^p9C!{Di^Z;#F?XmwxKX~G(ku0s0<$;SQIo8FQLn>y zd|Ag^`1pq&UC{k$9W_)2zNu7Z&qsHQHm@ii4mJ~vFx@++-WJBxzy4dKIe!g!lhva9* zgA!gKx2b3+$QsrPD0Z6dKNkH-3JzxgM0h3i`Prs)rb7}LqP z`qp0zHD`{bJspNAj};wX^p=ja4Kdj@cX|xrUwhRB@Jf5wOMC4+2&UIVet%*|Xez(p z_MrdEgtmKUjVY-(?T1GpUIN;tz~UgvjT>M=Ah&{WMj0xaCFsPZ@+e9>b<2VV+lQg-zKf3VKDNfRJ0)i$tG zTx(~y28MhcUkC|O`mv72vt0yjY+^a@)NkXC1|0=C6uk4s#|t4!(A5xbpSO!W1nGrT zh*w0wLSytSKk`oI1o&~GHr?PgAe5A<>zW3y>NygzVsME0x!^EAwRMQ;SBJ`ZAtkFO zw9>`Trte5&d5ug#kT7F`o_@pFP3F3;I)`kP{)DN?VfBskcg3z}BwNFLPT62_Y!Ip5 zL_;92z-4+uTZBC}J!Ip@P7DGD0WlMc9ecSXJ!oPi&+=yt0#%a|N3i`G1|_yM{4UKY z&&6S>fM!~T+y-t#ENQCB;95)TBZ2+Nx(nvq3?mK?6744u4xauWGWh9YLfQh$s_xp8 zo;zrdxpp*Wis5a8c6<4ktZ5fO5o&LS%=o*&5`ZJ0h*eiVSs(*D0O(}Uv_Fg`Le^TW z9e-6|VVV9Gr=b?$qmy`#*HRXQPVhDQx75%6(rv%`169PrA5w+=e!~0rvdl01)w1Tf z#t){df1gzOy^H+SQtyBJhcEK|;$Lrz!any`%-{b@7x{kX{o579ezXX{kEkH_$Upi? z9AYMOY72`A)$s%epcD}^h#9^N9I)dZG6kE%$Sm(XB7e{0#; zv-r&Eswvnn6P$-r#y>*WZ~x%k{~zvXW(xM(7y5y(=~L+y{^KKEzUe;j1CO`Y;txDQ zmY?(f_hd&QzhUww$@0Tehj0$|%F-1XwG*eW(?^*0y0CjP2aod?43oYQUpK10QN}2D zx=z{VdZvtSDEJPBUklyOS%t{T_S)V6cy_TPS|@`odEYu!BYR^AdN>%+!-(gBx~tzhddGh6X?869=W$$J zxwxkC_2^us33}wwPC=KqU|@B;2mQE)*M}3y46lJ595b2X=w;xhf6vC8>)t2Xq z#3V_fqxyz@;3c!)rQh&rn`W2;JYui2&RSZeEKa91UI(H|U0A2N2D5_>6L*=?7rm)u zJHh_3bo9*(#)07*bGz73e?}yfBZMPSf}GkJW3UoCXI|e4`ER*mmND2wh=lB--J0#34i`HzT%2w6QMAtupK>F}o?`TknjMVE z`m6m309F>Ih@DBj&}E(_l%TEseV)}U+S-E%xacmLMqL=wLk?|ABf=JR09rux(k$b$ z9y$$kVhRmSApC+99(stMbfWHC&2)0gn^djcXWz!Te6q%G)( zDTDxx2C8%l;egoyK?{k3Yr3)%jFYx)t>qjoOu+%r%qP02yK>nwp$=2iT?L0bAgG+$Fso+E-A@l_>@q z*l40=6IFnrWU7(v(yy?0sPhIpo8dI)tri=WF_-vEQkk>tFvi;N(?$Eee)}VTw`;Nv zb)nn+3A0Oq?}gnqdXF*Z23pOOn}Ko#@woOh!gIpzj3@DR7VMpIpsK(j`&7!?W5z#s&A$grbi+ zT`F|^7~ibGr>~t{oKDV(+P1#=b6-g_hj-dK&JdDb~`fZ_L{HPG0`VvhC5>4 zf=a@qrim;o08gmEKy;Jol1l#oC?2l_)k8rJJc}-l0>c!susAYgNy~&x^VqrhcfQng zkKiSG02}P5mfHtpyc~jmM-eluX%}qFo0LdMFq}z6PjItYf^ICw)SjU>1f`)Yt5eOG z=X@KgA5XENBfnJrSO9Af_9hq~uiS*kHtFk+tigZW84Vh5<)V59s~f1CNpma=bC78v z9mBZc9jpzjFSHXriXXiymqvw)iqDa~b1S@pWu<*naMt(}&y9n%F@u;Hg|Oy?pZHfl zR-DHs%hjVkOeyjN7^Z44+>>|hyVI4jz=f&=`?=DROg3Fsv_*8!bhvfq5sRJoWZCKP zg$U86x4)S#QOgi2te&W`238CB29{8_nw*CcYp5{FSNT$k=+^6UbGE5%|6vM3i%%2YaKcDcITy;#da>1;*d zX6^8{#M~XSbyww`{a4)Xctw|v$AnQ6>xJ69s4yS z8#FHk!A;@6@Y?QM;hFv7tDknmnb2!r-u1j1c3YGTaNXR)jq%GTdrpLH_knx6hvju( z(5JnYa?g6NHtLsV!}i$oeee|*X4!!`m%{PuQYk`G$6V2Kg>zE4`(^j6=>}w@Vj9WS zwAt$#?!4HDP5ZdHuaj&i$;;iRg6%-R5EJ-cJ4VsTT2T9EL#VwZO22qKRQ)i_i{bHD zlU`ol?T;VOT2($M%6hN(Nc*o=pErpyQhs%qLb#^MF5EH>C!#wKm6l6 z#-=`_PMd{BvqBr$+Ro ze5$W6V=hleOY*tk25Nzi&I3aI%D6r7r|2lU`xkqzhZj;h;f$N&IM0|h_knWRnEnlM zG3frdo)XECdiN=L>S23edj4{s^9;#sd)wEx8=ryl^vw_=(bPPtuCR|*NF>*91(mP; zZT%i7Yuo!uYG^o$_M9@44-RgeYpm~CKh*W@-8In3L{FaYKdV3T)AsTH-Ek%_w)tToD2GI*e zu^zIosiKseFU+>uzxe+X_cl;&T-Tjv6$mL1O*?pnYOopvNxbSptGY!=M2k||oE^Ig zT@XR36#=cL-InP|H%&V9tTPc6`9ztMOz?n$iI$ocn<6vxMp?0&R6=FsSfuS)?M&vR zL3hWrEgy@tG~t}%j72)0XeXXE$v8PmPR@9L4^8?baXfp@?w&2Ozkov3tM~4E@819Y z-+KXGp7{7Jha7SbPMm(>(I~K-g?kRl2-at1qNyon9))od+ZP8aB+biBdQv%04t622@}L*>S=e4ce{e*5J+F&E)dblC3gzlrFu(A95x`a7 z``)+JIkqd}b=sb*pN{SAGYb(>?t4L{0DRWMyKE=6lM;31UEocB1|?IP1d!>*Pxt_t zUc1wz+>dK{#vgtEo!Q4f@%{`g03KRJ19K&;1=?MyQ;TR9)=j9)W49f~1-X)+6g84P zLhs{=;GrF3gA?R42!-SW3fQxT+^G7%faU1GZ+~JAp@HRBFA-^5F~OQDHeFiBV0*~k zN8Gvfpsx7Ue#JpthQYYqlOvVMLFueSR?`fJzopE5gq}~i5;1v?J6w;*Qb6X@;p>wh z-fEMaks^R~L2&y4K_x1$c;_X!zwYsgmz0ea1z@enUhqA>eFZGtgQwe{{k7Be%Bq&B!>aOo@rW+ zu1waMF=E#U!%-kI-TTGUJ%o_F2sk}KUVimMZ-#YSyR85xHwslDYblb8^LUq1`j;9> z);8I1+=52wr0m-HN|H32pb&ZlPzo86G>{ecf)Q9M0U(yy3(8sAhv3h1Zf+vVg%3D* zBg&`T5hUP>BDVZ4{}h>M+licc3fX1*v=YNt76ff8C*0vH68{dtfY*K_ zy?z8pqe<*tyJ|ASVQ02euTfYH*Vto}g<$OG*!&BjL)1NzO4sGOPTSESA6xW=(>!wA ze$*WZr{3CkpH;heUpArpJGXE5{RnIEQEU6x_v$pV+ppOcNi86IGw5&=$u0pK^ilT? z;hegC58pM=E`Y}&EH1hpLgAK)M+Yu1QxNK|_p*T6K$2jYQQ8a^N}C)}i9y7Nl1ANW zU%HfXSToSBJE(i~XS%8~RlsUUg{%wI{l0L%M^bg-8lWd>VO2ZV6jR>5w)w=qWbpd^ z$?T)U6IHbTL7ol(m}$vB-<8|Nx!i1Hnwxg&ek$Osf*K^AN=U9A#tH^)9_V8YuN zIjApl7DI8AJO@KbdYTDIHQaLW9??{lTHzh55^|u zfTm^|ZH2}e9PfyL>YZ_;?4qL!15k<@Q2wt zZ!#fQnS;lE^ClB=l{t7L&*taffbcy>e$5+sHa{0$X-IF zTU#VdBRx?Kz1p7eg+1!i)@yEe%f19JyQ;XhXmRT8l6`u1;&&td8jNH*y0v&~ku#g=}JMM_5Z(b9~~EbnG~5W)g!`b@V=9r!PB8TSkkY z^W;FrJLh2qe(hhb-KlthIGm+?4TZh7kq;|ke@L~>7~rZx)Ef9+HcBmdV7Uzti8)a% z5&5Wzq79RYVGwt-6~hc4gTFj0n1r4|g(sygXv`Pa1>b;01tEr*ucqk*PnA1+Tu4F5 z^!#@B;j{0U4&jOt#~Y<8ojqLw*c(trF|XnV9-AOON6=>FIEJ?Y0}Ufto4!8Le)f_$ z%nm`vU^cd9nudRZl!s;vkph+5@@E$;)ni4p67JIQk`pV1#!qN&2wm3@I?8_ zR`-;%7U%4oavZxj3Ok40j-a%K8Z=$-T>y_cvj&T9h5K~3X-nE4DU@t$%vIJpa8HPe zJ1L^$&YI(0v@54U_|uXzYwdS^V=zUc!(aH94~t|tXT~~z+BSm6zk%sBhRLPoBWn;K zq#euB&}+bEN&wO`PrzseY_xuLz)J-)O%*wGUhr;rE09iDNbvo&Dl{|9ad3o@c-*w$ z#VL3@j^8p1Az*zxr_RA-abl9_kxG7>F;XxKC{ouJcG=@*R7|C(oJtjjs(Q>hX3v=v z-dRpN&J*HQ{|jL%8zZ!bY-^*_=fI1lUAoVG5q!#N(~ZY{u|Rq^yi?^_^SP4S_av;M zb?qeSu<*CVM)zqsW{n@;HfVQdly7bFM&4|e?CdMHD_feYibeObCsN}J(xq&~2+0LT zoR&rO-*IPEZ?oWeiYG?*hC>V1 zmUCXCSw2mzr=2ry?wpq^Z?k91Z+#vE8VFrO>!~=KOovIa)uL=QpoliC4G4G_6i`Vo zx;kSHg-7}gJOzYvSiVdE^{6dn77HkOS)DL0z^_F)^kz5feUudKNOf{XT z4Fxv4VVYbGt_kzdnPXSa=~Q<%%j7J=L_X_zP1bFDcpXXp2tA6kvD(w3_~KJ|9(5>OreOKZS{C%*0m_LibS>mY6MOdaX<+E7-fZ%b zs_x82Fg;pu93Q6@&OAC)MEss?l*o}qJ=EL+MV%i*`YY>n=B%*KI0af z&$=|!_SEb=G~ZfP&ay>Sz4#Ew3Imfqu8DHY#am^A)#tT1R z1_?|W+?Lbg^iG=^%pK;fRtnN~hfD%{4}nl}b#{?0A%U|&KXsPJ>e9mmZJS5Mtd+`W zNIQ)yT^$v{jM@a~2IYNo_X$D|0bj5)`)YJMYvSyQkdXF5sujY_2o4&=wGhyoeD>ed&fc zM|3ft1sp`x(VAPK=}I#I^L+iU*EIFR8lKXRtqrQ+JoNWQcmOg>L`z8+5OT}J01zh~ z6##I19_cDUsZ(=_E~hBMp&-6Onh-pPl5|y)VOk=$wB%kOYbh5zuwi-z3rqHI#EXVk zNg(USt9ZTkhKMP>uBoYv6;OUMNHDu_+HnVdWtjW)TOg9qA?M8bxUedsn|{^7$40hn zyYE#DkB0esvi*82CPuOoNB=NvQZ#Nr)mw3)?q|aXpLL2~?vL-x#hE zI^$A*?w|~_%lXQAxGKzuNIA>F-f&=|X>}*RyW_#~rQq&a-I~`Cxzow>-a{+=5ncjy?W&FK4)9LOQo~(PJ5eA?TbGfJf0iN zd~DByGMgaZ#Qqj3e`e&XVfpnc85CLvMx*nPirw(ntxIwEopaZIX?!W(w>G9oc-)@! zh{UKwV3{Gm?7F3wEprDk+fH^eFJ?7<2~%;O8=klKJ1 zxb4)aK1&^(sz8ULGI8%>Q*}3P_i@3gU8k%aV9;R`NOTTykC(V)Ww72kWY0KpdmV_} zL`NHz`ios>;RKmxK*fs*aA)^6I z^gXINYhu-H1WipI>QfgY2;V!T1UGo!`aBp(--x?Or@I1}T$UKlvI@F&Za&y)Fd-0rk*0= z{OjXl-R#%B@Hh!L3BgTn{>-`^Gy5zTPA4V>s0wKqvs1dh4c~$Jzy^|(UpFfsB3;5{ zM8Iq@QQQ0R_4kkj&Zr6Ci(2P}M>EdBg%|J}Pq=;hSpaVxjU05KG=Zymvi_&~DHNS# zS#R(RZr!;{V#HIsy0JL$#cty)RZ$4vrEbx>0l1j$-S^)?ym}OEx12}s_u~cQpo-A^ zp%~sM4D`%jtlJ@r*5km$yMan$ZekY5efjDM;-)JR{J{FF+A6F}ewCFb(5d|3l<}0@ zC78(c+6{o|5TPucE%j2L>ROUD2F_+pY@~QRyiVth-MdC-VWFbefZ~m&U&LWpAm3AnGai`L~h} zS-$GJD7 z*m(Gu5W@-kEZ7&S4!*Uf>?;ixT>-rec7{7RNy&=u{m4I|p(ZGyC z$4mipnkPmAYJ=6Hm&s9ENq+aACpTG=lQucno)r(&lCOA`{0C^Fhq|IOx6^r#x-v-g zm2{ZLy(W8_xEGk3+B%ovY2wtVSvVB}GqyM4{zy4F-2Vs`2wPuRB=Lc0!2D#G>6lr1 z$QZV!_L6Xq1?g`G2LtEth^g69|H#8-_lh(hbZg@T(PwbjyhoRLI_3WM3;J$3g3wu(4@ScEQ+n2~`Pm<6t zgf`Hl379`bDpyBmQP`b&*{)Z~h5#?s4L=76>EQ@)gJ)T=&j0crfYb1MgL?@%zdq>s zxo-R*;55xF|Fg({+O@)~)xRcVY6Ek|VR7g>VMVos&6+ZIXN12n3Fk5yl4pP=w-RL& zQN3i?cgTP`x$Wa)Y3GrQGuQnjOM82bW=+h}(RX1jwM;vA&Y3R^fXI5l>aj&Zp>&dD z5HNrIbc|0Cj$-A31?d)!py%IF_G?eMZu`=CzX|7w6nRbJbgukY^Ao!VjW!`3^pnC) zGSo+th&M6V=wMo{lqlk)wk#^w^b9qWMDe_{ZNzl-6jf_9=-%70h|x|n$nQ?F1sjLj z{msx>H_Zf5Uc+RU3R-)Vg7>UTGe1UI(-M$&|^z zS0jkjDeBXY5JG*q`}QXv*-!-Sd;62UYDJnW`9U&kzWpPy)BcUv>7iZ#_TL=qA)tTq zlLN4Sa1mYeNM8g%^2duF{dg32F97?8Ez!8+kF*3x_NQHBwIyF%ZOP4xlppN@pg$-y zH1WXoUloO(q8Mow1i`4$Eto7?bL^?S%sOqfX%kp$oG8k@lljGHPsSva0_s$;4!qe} zukyaCq_p-z4Olf@2FZq$;hCVH(Oh`#?DzG@&|G_#tp0)G`Hvmw!vElCpw~8N8wfh@ zxmOQ-!rNJu^Z813>V+t9@=kImv2R2=k_3IZi@{X8D8f@4?bpJR1LSq5eN+{zm2EnB zvuN5!kH&^@wuG0ga0)64{-(;aV%F`lM5faFTdi>1@y)@V$Ne46z_y_i&dPiIF&N!s z_H)85);FrQ9F6NYK3dr2tc@MM8?ZmjVZ2IOWFK9 zxdUfQn1vlCer!NmG!q0;N10Uz<`uO;;2#Y}Dx7Fqe#4;E#_z(W!6Q znx8IX6a|YMMU5Vv8E}c1U1gMdzoy&F`hq`Fy5eLe6>8CKhWU zjKcO45aK7BJHt_D{-A^=Nj|LoVPCXY?TxMZ^~#IfJM&+)w%P$%$w)a8AFR(^*gx;s zFY*v7RzQQf2{mm6=Or*Y67=eYYFH)DtAcMcXHtnPT40^^yW4`dlun>m{+K%#x}-*% z_g^S$lCdh1EOT~I#!m4Fbq4piBef=C_nR-0(=A`JF*w`5MV-|Un-8o4x+Hb#MQ5f9 zP0V!CuTmUqPCc>(|3Wfj?z-fwlGFE;lphvAe21;#5kE8UoSFq0x2#}Xq=qJ}psBjv zv>MZe7P|dA&k&NF_$BzLLmzH&l2yDyQCaxYe$+ZbsczqqJ2U$iAX5&9-sN)(*6MwDIe}XkYy@xp2Mw*brcq%3Bh1y;{wuH z0zCjfU_O}bWL!Mw+G*#U#j9>;(Ssr(4!;)}m)(djT6%vK!fo))N)zt0~5)^ALQ48cg5Y4jb z#f&ZP3}7Qo!BXSEL1PQR2-)ZOpvGLidHe8aT(FYuL}fpY$Y!~`E^8-9@Q~9U;e-)V zo+5GeZ{}I!d3si9Wn|;9=PY2A21hZ#t9X>Y^V&NBh)YFn!lX5AzL8j6t1U%{tPZ>- zVA2^JC03Sfi})0of=e29Jyk#pJ}pO~d72|j@Nt`6-+0-No@~F18-f)j`3DL`Xaxuw z1Xnm<0p81oNTyAq63ZzPM_sv=dT`Z3oZ~dG@Um;#xJl&CXh)ujF$>f>IOsSKL}tDiuo}2x1@1HW>NnIE6jd z)s0UC$@oiMBHp`3XyF|U-pzDKZ0(2pMMG>a4**eCgiq!BQtgo2&=GJSxhc=qT9bh} zYR)C*@$eF%V*An%Af|OcfS2n+6BAR=u;HfHT~^U|F=`6NYQgmMV-6+mtET>7OhcRo zc$AW6Xc$aKB%PZ^_!@*T1UCxU4k%{??CWt?-P77_#ri?zO(#Qzm%wavQHfb<;o4Dp zXf0)Cl$97T@0OgA@?tK})>wWj!LnyOZT-T?+Smze&A>{Eg+q1}q?T;_VnCuyv~>9c zWfg>pfE!u)*9fKX zOXQTyI@URskZek_3C74)QQYSAi?z5wG#OZpNHkvkKWzfB@N_{4vC|S%M<>N4Mujrt zxS;`hmbn7BV#^Gw6YTb?B@-a`z6y^urWr11YMeSDFkB$ zXMMK*VzSwBtZE8`zjP4X#~IxDs5+YOZg_4?SQJW7u6GZL><2Yl zao~WM%JofIkC8>fE)vEKajoyP#1jyt22-&h?!uYy!-K-kSXF01wiEM9{YMK;xd(sq zs6QqW@xs7_-?E-`r-t$3leeBwh}PKfMgN*_of?~1bnbNi4F%m#CI*_J)_=d=yf*iZ zt9HC^-64%Uf*ZAWe}o8J;Dm7Md}C%oA?8yZ;q2(4l#gzQJy}01=3sRJK~DB4EDc$A z04N`T*Afyqhx%yuTdAY^MQU}Mr`mxx8P-=$i0u2uq}ATN%W9vub^%Zv8@?jc*atI+ zRJD4>`u0No-y08i>PI%l;1s9b6Rd?7I_3ztjJ)@plhaHyz-8 z3b^ekkS*)?@!Ts@I=ZwnIWh!%3BgZ_dI`RkCRLHK(>y5Wd$=Z{%_0qV**7<8epe~%jS8V^53?JELy;OgZx=L6SuHlXx!XZeq#o=qP2L^clx7?AJO#K{^2izV` zJjHVWTKc_U-7CO^-W~G!2j2BiR$g@&)Jh%B+V}*ItsepWNDy{S3^|X`%N|G(cFQt% z$e9z=SlV{4S^Gt5$I$)-VFMf!*bUXS1j6zHpMhbisc_~&Wxb3bd8N&W)oID=?GK7O zD7!AU1G?>iC_FHzMhIHXk#>@7qYacI@=dN`C_6_+bWXZN`+w0@h?GC#%|MJL1>-Cb zlKk!)sU7mesi%n;4n?eXt=FW@R4$zAH>^IAW192G6_LlpvS#-sm$Jo4p<~DQ$=Y5U zLLX3)cdtZ|$z4W>M6R3bVRFZLh`OL8xY*!Ae0+rN3P{5VdY&OQLZB9f{J7V3iY)+^ z6YwhVAMt!*cB@6}mh>$Cqw#gIo&Fdf>jIOb~~c-JO-*Ddjm(3a}dOn~XeVm65~7NV#a*<_!Yjo?(5fJ|$9 zr3L=0M<2v0JEhaj#uDK*`nhYLG~tnYMP6&uieL?77O_1{7^fbSraD1}0sKmiHvn9} zot>$+?85U=ZBSH8qCB!EwNqE`yS*0Gz^*eT=)i1kQ=;N2$dn+@T>Y|3ogshw#A$?5CoUyRD#L9xza>qIZ~=Gj zl@HIYU9R!;W6In`=zYX+)pr%@yMCi$?AkR+gm!K3K1iU;QJ?w65Y*nOeWYmCMuyhd zeR_HyFT)A_VCFIB(nZZjojQI(#A)Etg9;G7T|Fbh>V%bBv#q!&THystvnMA+aPd(G zV_-N;QGhEk>?U4zsZ&SIAAXI=J?Zhwq8NWg=lLwqR%Tlzx#?fk;&wPs==K5I@#^+m zIBAnsvJbHS(m#!+)f-N1zRDYOZ&+q!>Z7!%8dg*Yp~0a(Il-n@-|;ap8v-FNgjHE0 z42cpNo z5jVKxenP+5yzqeUQnl>&8%nIrUh0JI#ZAfILL#^@K5huS$sjcpn~L~i9UbCiSHr_a z72X&=d%#qCOVYAoC($he*ixjc^XTbpa6Zo1>in3|HjUkmi8}-3$7`5gK}=}`B5;nE z3u0|>zG#UIUol3s%XFIf{#Ril$A1G;K9f!5=*b`^I;=ih!y|PSvg&Q)1M+zQ>&%DLrDyiB#V%? ze2uh=N4q0KqFRgSe~^A2z6aysryqJP36ekk9Q|&?H2zs%qu+iK3aM>Zw>jMiAU_ob zn9(1I^Z2~CTp(pn%_)u5A0WBcvSYVGu@i4@fk4r&P|u0~Y zJ56PZ>U^Ha(|lOKASavwo0K~)Ny$iv0b|+( z&CDeZZ7WF0s%^Dq)UbJK^biT|KrC{5Wx<>^uYUJ8sit6Nu!W8~zvB^!6{e=U)5;hJ ziYaNzm+t>Lk($-Wpr zVR#t%ZrT)aJuf0t6=%qsk=QCcqwbNv%ql{|D3~iSu|*Xodojhm10W%lPJIEZEG|aQ zgn|_qP<~+J9;FRpd^Lcxm8oW6r-D&3YNrTLkAt-yI2_}AYRe3e1_=_c{>ASFW;e*B zjH9@Cfc`v$9aFB3!S@_dA+I+R7VIgkKrSjpR*5pPrlaKhNCn|-*u;-m(?X`36MolF zVfucuw*Uf~mc*(|#kD=Ytd*fkr4tL05uCSrhF@irFn0=@J4UhWp852;N+{m3O%%n{ zHX#jJaV2V;C{iD&G9m;kU%ncdx6c>MS3{7fv`9#=Atts!1v?C6-i%v(ftSuv|ZS4f5dLu2soZs{pUdPNd>fl~fzh%L9@B zQkdVrFgL#myMNC@+r4(-6ZWr%dz4)v+<&*7{=iWujlXVNVERxMhk@WMaw^IpRS$>e z?d;m+Z2{!X@I1Ng2TwT;87HY`Wgg1Jz*_S>FF|@FCou+aqJ1m;h^W9`M~;%WtG?Yn z>CC0P+%zrsgtQ`@nyKM#9p#f;jk>Zx#oiP*vK9kj%K6D>WndV{Xb4H zKA!SKP-adSQwDmTUcrF2^{TN|BQqXJd$iWli(>6D*o@wg7EJId-XDVu-C&Xtxtz6A zOZdo)DDX_+Kxj#9VTQXi+(tB?WqkAJ%VDBu0@H+WPD1byL?PLO&q<5m3QJI^Htq@; zF@H&cHH7X#fg5>|DWhslYxx<-&`itdF|5Q z`}Ve8uYq~pI5aA8^H(x!O0EQP44PnEH2X&3FcaoGC-B1vywzcX!Xz!n5IUF9l+-@xrpwmK+jeF^;9Ql;XqSF4NNEQb(_T`!p*s z^SCD_k_m4BT5=x%KE36EFX~ogL;}t$zc?&)h9Y(ZY>*8secWLOq2f>qf*6Yd1E8HM zY^BWoq{8!}yWTp*M6klU-@4U+vQ$iXL4te7lA$C|RYHS5=RnSB8HawlbfTB54>jsG zRu*2+z?LO+fU%LS1Aim(OSFI%63Su^no(nhwj)5C0ZwlG(cNYx5z3m6<52}`*nTvK zrw=Rm@!feSgal52I-nkVP^w=qu8z0>nk}q(as_*1T70H)&R};y7|;z2?vFfEZRNqX z5HZ(4)~^1_uK{?*0EA%$G3w!0w9Sa=#h3vk0XiL;n5R#<35{euG14L1kX-}#H`_{@ zbs(|HbaIJg5h=*NC>@E9hX0%=LW4z&HJ!8-CI`%hevmEK{#BpRHd#HP*7CRFo1{~V zrv8p#>#3k6S2Jk!m}3EvL8D-T;aVnbRV^;VRRw~Fw}6eZ#}IVVQ@)`L$!Oy6tGWCz zo>`%-=uAm15dp~}O`Rl1?+*AT%19q0$i;L*O^AuJCT-CWJqR*Jl)iwz7B|b%CN9z7 zophBXk4{hKFgqJKGp;@LACV}}kW3WPTZ#o3)`$tu!Otm|2E@oF&*r4paK%21rmCqE znx@(&`v4$fpgE3)ZR@EG71dKOSPs+EvdhVEjMw6rrZ};eUKeo#=jzOThKT1QFaEfb z?VFH9t>@NC0Cfp+3H7@v7icYth&@1`qNAW4GF)?|{<(SQxfwEmoG0lciFkEcxTDUr z7>E97vFVJ878qi-#9w#>cBnoS$XO}FCmo_@|JXUT)mgZGK`GfC7w>wA+}{U7>Bxna z#85q8P3+&&wQ-gWbZuqd{q$|2tT+>=+7q!*5!0kxW_xF=^aP8OtvrC^wF72scwUXp z2?%#55PC#R%ivk3?}5}yA))0E)iNI-__~f(RdZpa(#nnbqyIXb6SskdjvvTeTBtkr z!TKR9K4lD{`7IQuhHK4*lLyGP|50HrUQ!L{DU(K^d~Vu=A4C;%ubr)Tw$v@VJtaZl{G;2XcfVORq_x8@UYzjBtOgt~K_!%uv+W-2*^%1` zG=1EK8kn0nZd>jBaR$L;wV5Ma1b5wmaKmk{3Rgi z-B}BYmkwF(@DzufH$FrWpQ$H44)^9*;;Kz6$mZxuNY-&>axX}b=5U5n5tUu)J{+$h zS$}n3vR&oMU%XsN)rh0a)wdL_>$eZoyaS^4k`QWTYF{Y^qY>zktSh?8b8&*~Sw!gG zX!L{?d-op6=yd@vK9RZr!sJZs(qc{1nrEa2N(Yt3#o8(FPTg9-vtu9FW##G>+j?f9 z{@*{2YWX5K&(|*3zjJ~m4!xuXz8L`+?%oS&QdB0PdlIDP&BOIe02o_|9pU8$5v&@c z`ik)6d+%5q?y?@~tV~rzT-#StwE5W70P9{2Xo^OYhSUQTydgE%5%-Q{;Kk`KoF&(# z1KOCY)9xAhLas^C@nXN3ofv_U1UWG+H5_EsW;F+q`PH8I&y_X;l`CD%XII`;sJk%9 zbSG;@-+1NU!bRC@D5YzaKl*I*XKOPy|{MgPhZG(#LR9n@iTcg#I%Axe&#GZ5EaXj<7y~aJQ>` zo42VP-6_mS;-yb}GS*KCo$|DnDq?aqOOiYAGva`_g_y<@s;l;?0OS z+6IPHwZ>8mLtlbEBv+zIgwX1o)Ux-CMvk& zu?;Qr)CqyYtG5*f1we=Tr!+%%5-tbkGD7D|xVQ8Y0JmG~JiH(hcMttc<$b?W1URbn znTn`*Hjz*y_$6J>urVMuPa%QndWT6;haW9;V#gDr*9(1uS@S7@uMC_R!l9m@^wVzF<`T#5_5c}=<8DIw%c9GOV&612(0r%B?RK zt+I3J{$wz5{|RyE6ZD?_E((XUq!6)xeOrqGGY*tUD2kjDZj7_}f}3O;CEFqDj}9;` zE9@LI-4#}V8IQlz5qFNkzr8IuKWD^BM?=H}pwF3}Nor#f5?5=9kWoN zVc!sr;8a_C)UuRm>UOhGCfes>X|OG$Mol~ye-=~c<0o#@|Ms)wYs7ii4Mkato`dv zP&lH-5}Nw>3k&bmoIzrhdz`_YJCL?1y#Pf=7x?cu5EE<@?KuO6M7zx?!{D5O7rq!R^XhXWD%=D$dhs9!Ruc(<_`?fwJO zCSf3fqT#fdhV_Bw$;Sw{QeT4hcAR{`X(hUjvyH24wMUUbP!$4M=Umh+0x>}@91Mqs zDUEiV2&(odk%)2esW1x@uj{DS2+&)E^_GG*jK>@7;FtgS9f29;>s82s=_xNZ3P^I0 zDoXtJ2FrL>B@pX?KR7>*X$cWc_G3lJ!}y(PLeyJArEhh^z_qs*RC=O}KOTvoOsqkO7Vfg4YT74|z!jTzq^Bc?jja z6&ax)l6RLfb*ce8-7?37FFbeNs~qR?U#pTll6s_};VpSzd77@*Kmv0*hHDVTOBnpI zk_;7a4*(1XINgl$Cz8_|3&1KQyB@h)=w8Ag(eE3y!-7V%vd+&MV-(@3! z^h|VTsL8_vrUh=4G;&~6=~RelBZaJ3k>vA474j?pH~k%2ElpK=K1RqkaEUg;x9J-i zMj>pP+)(3k+P394(jw642HE|1%2d{xZ1%(pfeO>(ECbr~4_z>7eimF4TqSY!+;4CP zA~g75f&S7YEVr2Q8;K>WVe$rzgEUtHsYoJd0SmCcm9dvEMG`@iPxp?9tLS%ls-9fO z5jXMT$F?MN9Sj(13Op~-pc}Y^N%nvwMn>HGC=$u^y67fOr4yc~jKf*}mWDB7JY*Ro z4U>^sauuKsHz@GYl-k(@EP-m4PGW1n(1d)K49a%GO-E-x@D7MdN#+5)#o#3L4~zO> zAxn`&@bw+1m42W&^tP~arA;u;8I5tKqjGYIjBX7Puc0Cfchv2RG=c#h#{IZU;*?P& z=l)FKi3BmbFaLo?5LUZ{7WWR_BR77R4bxcdmK*QsAK{JP>Ck_8-2MGq^euZ`NYg>J zxB|kZp*>#Juk-4SqlozEjBz*r?){APg#F>M`tIg~xAA}lt|eTaUzQ7&Sr~~qO>w&d zW`E2ZjB=jE7_QgpZnF(6gqO+Fo+E!(;!yvYD_nF1hRO}Tx{y51)Z ze`|a-<{>?{8NIRU9I^uw!UeI^pHBL&JC=G_JJwPPXPWit&7Ml%iYlFUru_7RtD8y> zA(t2obS(jeE_p9_0f1Z9}ZL2o4I|&y|w^jH_=O3vD{Ma9Nq^ zN8e{DcuPA7Rhw@_Tm9IFSKmZX;V>DG-EL}W;5m9@dSf6~M^uknP5y9re)uX+uG`5A z3^HBz6E2_!^RWGyFFZ8SL5_95OpCkpwT|eI>6oM&J+rDF_g*e0^y{8(wEjTQ{lWPU z#Z2Ugr1eJn6`Qtdjaq*sNJ#w_7Fxmx-)yfTstwVG_7GeUi+uWU`Hsjy8P{D&sJ}i< z>9?1}MoDKHLv$vsc{}DJ@*jP>*Oy#c1`)smDj=VRqqNICw}O%VSkLudjhb|)-o9^M;pVGePhhU@THty=JZdx|(17F*Ut0a`M_yq+ z*MF_PqUDz(?0xrmX5;G5p^kV_#4D$a20Iorj%*~lXL(z{9IIY)?1t4Fbzn)fgx(@j zkb3K2n=sN7E|6b3NpMaTS}Q7(!8*@-o)@sbMhEBhz4Wo#4&89w^4@C=bM-Cl@8&sq znPc@ueSex;)aF>oZWjH>x>YNOtY<;;kN)JH>)pGvN2TlCAAQ8z5#3oXKNeR<<1co` zN8`f~Pe~!C>`l^NFSa+OIO852yYYd&KOcW=zxVL?CD%*t=)_}B&Yh3PQnO0DLjAw< z@+W=7`~U1C<{jmsz3v_N`>wvnrQBMO?LkB(^pF+ycg0?f*MYg0ks#4O`W_x7!?G1V zC3mY}B#gnqAAGK2^PcvB+<0q;TV{_+FmVY7<(hb`Ar)ErQ@nNcp1EL;J#_!;d$vVG z$?(o7zH{yi=i~JGIR|=VTdz#lHbAtzfuE;b5>|IT_K zRQr^Y4+YS z*lfrz92f9u#_IVU<|doXfrT0*XLIJPkY@$o_J|E~uq4-8_IhgrQ$lZSdizp^1I`6; zp`Wyr^U!{6&6wqbP^FTQ0$y^QZ*=DKn}8N+8xKsPgQv*^$?rdG0I4BLPJw5nu%Zd* z)>v&=9FUU^k}7VBsZQ?kArt5j3Y_WZuZfZ`He~u2tqr2@g19K$32~Ry>+n=3R{U#q zxeIP-C=nNgI)h6wBTE`=rq|%e2Fc|xSV#UTqFE)qr06YsM2rS`4~>u3Axe9oRy0ti3QUx$<0=|B=3@T#$|<|J?T!#flFy+ zt3*N`8-;=1Z$2gfVd*a{&2;1>*}X{-KwubWWKRq937+-F5XIcK*1>J2B)rDJ=0 zqes{_DGAjf$9jzzmP5|fXG<^V>&qHa>^M)C+P@~nWg!qOA`e6LhdGj@# zBX84=937-+l|#sGqqiC&YDVBMfPhny5)vij>0=i44)$^WZ`FV`w`+H!9erVtrQ3mjve^%~6KsU<#5vg$zJ71leTkamR3zS-PHu(hkZeP4-GzVYSzj0_` zCdf?B4CH2$GuLb`jtsY2wEag;(P3RWp%VUsC!M$dkG#PmZw!V9r__wMJd>r!qiZ76Nuli9#0Hn?~3{P}aM zy{u~I)v}s9W1DTWIw?m_=th(Gnx57ZFs6?wT7;`-lTSISlLOmNj!@wJ zM2T|b`q09M=;-)wq&8O1Z2uVyEllJCLn186K+`BKewo}Q`bZ%(8LJ35x>AkyhMVxl zrCRF4nGM$S*1Wv0R2mL1h`*FHbr2!CC@eEXvQY&ubwqWW4ZFHT_foHCc2UwuLftf( zmLujcsC9r(X>@pTB-f%$K(4hQbJXOffkCf%8qn9WarM7_xi+3ol0a_J?VFdj@NH(T z7QwuWOAvFi%bK#A#LZ#lsLdi(?;KU@GaE8YwLO{5;y|gSm#IOC7?eS`mPxT_SA9TYSGK$`}dzl~6%HP>`h1}D+=)la8e{HSLjBx5%xh8kE zwCMIX&(c6Gpvh$x$z*%oxJiN7SGd2LX+CY~3LGON+ZTk(LGU`n&z=(6?ktchSxP`M zii$vy%D66PjodhmN9iq3F?H!_GA)05`FGM&%X;-V-iK%c$m>0Wb*Fzq07B7FJ+;WW zS(#j}yk4zG4~O%%p3igj}& zEM_*b4(L4;0n$HEc}>~xf-kR}x4$CdO)N>d3mtsm zPKV{EXSeB2!ze+S*QKv4y`dx0H+OVJ(`p@rfHgKn$3DF6UFwHIpm#xLR$rH8y`P5Z z1RASzaH?bFLRL3~Hv0jwo_`zp64?tqq0voa^#IkKI^SJhxpZEeVUfB3s}$p`I-m?hK?I%fd58H-ySAC1>@G7 zz;wZP#Prl#dRrGeC!kqrr1#jT*vLt7qu3`hb@=o=6Wx~VYOyz3Ga=`vv_tw3Y7U!| zR)cQbU)!3n;~7@f0>;ybX@Pri#563f;m7OfRRvY$m%F#%x9v7W>Ttj4>tfWp`MO|r zu`^e!o`pdiRSLCzjyQ6ie8aK&&mg4X0Uu zbOSc6_<4YeT3Xs*nUw3%I#+?%w#?c-v8-cCIzD)w6#(z$Sc=q|aLdtO9G zGdIfh8HN=dt$$HV8;TPhtL97<$K?CzX9W8WAZ`xdQ9ZOK1hz{C<1Xp(zc3Sisot42 zv%V56GmX_w(Y>$tMg~{c8AeG$^;qq&)uF_SZKob{Qos4#TUL@i^=$BhbDd-{7g1?9 zxNi!kKu=mYNS8t$h zjv|Sw5j~49B=PP=yr~hl*U?G#b{62_v)Cj4eP*7d9!xv-6#Yf~xW--1i`)faZV*{H zBLaOl5*eV+vMV|TDhB9jX6AHLZVV0jF(;u`;{O0_q)|7z08wTIAlG__7=zUFGq(~R z;KXl=P@WsjvF+qalKO{oM7}H&l_xwqsW$KN@lUZ;vOZr*d=|iR@&1>VBAwaFoqDC~(RA-h5D8;kE+fQ%~f{R&8<1OnT zYwCh-y>6v`6SY8*(v(yRD6XTMzNz)XIi1t~OEP=m_+?A)=UG-XXy}K%Gn)YdFLp_Dj2x}7u7 zuJnHFQtIo*IeN!s)nElC13bO_%g-d977yj&80;6DMt^6>*MTa13ljZXUK5gFnZ5(w z>y?S9ryj1Wjkm|w#gr9d=MQJEmE_axvF;UX@t)x^HItzx@}&QeN7PJ|-d(LN!%~QM zgwBHkrYrGx>bma_pY@w3OF90l)t2{q7Mm{hvNNNtGk<}L4mVM{2*o-nZZv)MEWKVj z?4WHzuj1VG{<+{3lf`_~YK}3~7GXWC$JeF2DvRS2q3%AIN>SUct|N7TuD$V!(>yo& zwDj}MBPBccS*VT)FnkTkc3}%YL{(2ktSrj@Y*TbjqIlh~N9kL_m6=s+98>`6{qn>2 zNOsARhnFJ`j(-i_iG4~03)(>LTPXF(v!$}RJ_DROtfz8%cPEZjs1)>Jwl4JLP8~yw z>jG~^k9pn%ofn78s$x$?v-7szPAztJll@Vv{5NKk)>9Nx`n0ePLuq6MWJ^_Qb*gDY zl+6K=r|i~u?^siblEx-6hidYCMzPS{BkUZi@oU-+-D&k{r^mQ6wY)OO_ZN_o*;9a{Xcs52rw-N$nQ4|vR$*WSWz-$?%Ct8$!ge*j9Cn>hYX!N*fxAXqCrkeJ zllM5emTstS>5X=xUiEC~xo@>FtcX=e5zq^B6!ZNI(gKaugO zqZe}j*wA%RdW^ed_E@>Eiv%ijV)a7`C6M)Usxz&E)ImjQnto!N2%cuz=y}e+IW4i3 zISNa~h$KJ&=;h6|T}uFI{5otutQcqv8YWnkQa$wS)~HsP-|fy{Zu=K$PwejG%wxyp zhLQRHvqA`XCgK1gs-hnzEBgc&YY>G`>Xm+6<5)cfQ`ExrEqZ*z<#+}2Redqcj^^Qv z&9mgR#3++Qt5c{>`q1qmMFh$;On?J#~C^ zy>-anKx8G^)r{?l6K2OKHOc z#e`^j$>N-1ch);2H!Uy)w7t_YmdJ!c%@&}Yn;WC6@gd$^awy;;e68j^zqpn)fc=?# zi3O?y59C7bW zKZq|z30fC9kseOvKnMg}y2Rr4T1WMU3hC;NlwST~Cm7YK)L%v^(#zis&_=5?470X_ zXRp6_67Cx{r-`&}HBGjY69bzBbu#c@P1FaUkbBGQ5$UP(>{OlhQDlJ@UKZ-&{1Ja+ ziT|VhYuJW}JuyM+xa1^BA>nq}q{=2_5grE|=!S_H-BhS_vk*9GK25G!+N3q+o07*p z7){31YN!76BX7daTp;H&Wsp%mzm+*7HJD`P*)HaRSo&hpL1-8Rk$2bw;EBY~s6F%X zGXi}p#}}w7!KsycZxY5US_f@|ZKOyaz_@4G>$KkbgI!AN*M`zr>gg?9HFO!O@eMUm ztA8k>?5boY>OB6JYbx=XytXVtfZr2De{-o!ZyC0Rd!~e*M-&)kU2m0o8V6m#;0Sh8 z)&#*;zvru~f zGXSai6t}8Z_vaDaj7wZ?J>qYMdHc0k| z@rph9>dF(O4c&?Pa!rhG7#KcKLUA1#0Tb}~%Vqo0D>##`Rt=)5SE-mp5Ys%;FdM$2 zw>wJhu+opPHRy%@#ya1_hj2ZhXZ!E*hfnH_3k-2YgIzaH>*qhO@moJCrVJEv^sNZHodV0j!zHpDvy5Z)V z*QGan#0z>W4C_lRI-GZA=XIa@+nb+t7E0SsmMm*@dy`VFy@A$EZD2%_uv529jt)21 zG{EC}NE?$F@ng)K#EnEB2-6LImKh?+NCOw(#tz zcoeSggfDIT;Rfp}eDHreAPR}5ft2t*Kx>)61_k?qZsD5&?GC~aqAtxg2S3vGaD4|`MZFi#8eYiNz>p5c={ zRj+p<52BGu9;4kcU&c{k<;2@3pJxFlQN^1olX}{9P7L&$n5P-nI#4`X?18JX(i(N} z`Z7*0y^)a<#%&EO3~XmH9mP{6CqzFZw86zy5jYrnE9)xj&`uu)DPe}YM;uURZGY;@ z=gmZK=pjfWuB_f@yVeOgLL#w6c>}oC4tm-NC|&weI{9F4PtIcm3f2JOqq_LR2|euy z;OI~Zo$;S5If_u)Squ<;o8Ho`{lfT{V%U1Gf%{pF85P6T>FsIy`m3u8`Z~hMylLE= zBwCBnYQt-t>+k;xngl{?XD|@^OO!MdtR-x`_Io6Q%i1k5<=s`_vNp#)|DZUi=3v1e zVy5(_fi}wQ%Bn5YRkf;Gd5*=;Bst-e4p>x5!#cgztTw11FQ6oV0Qe>~Az^_9{iGHo?V$m^xAoKWNIWvORl%IYEYL>n>dJ9(?D{_6cLtPmS9O2g5Tq#1 zO!wRG`@GNdeZJ3+muS`Di%Bxm@o|S!e*z98dcJ^*v}@nQHqEfez#F*^p5sh9!@{B$ z2phb)v>2JQRq0!wP}Jzqvf7o)Le2%eLFpBLi^f3!d?!t1 zbhdYtAQlTdXsT>ae#7gaWSf`)y|}s{EkvkA>o+ zQ#l2Un?MpaLzi#jeyq7g(RMP7c_J9yPrMRfj0t*gkW%cSe&jawm_+M3vB|_ft{6f( zT`;7;lV0FjEvyXop`{;u|3fSb-98K(ruL2poQX=UEbNfnRrS849N7WZ@-@H#Ds9Le z&|}s6K#wURVL)y!E#H^eAt8?~2c-MlQrJWz6iB42AzF;r;P#tH4>Kw<)>MA&J3l#H zb`$GSjYDc9e^F-aEre$OLCYZoGlyrU>5u+rrPpaf^0^XW1mYHFqZX)YGCJ!;yTUFA z8-J<%?o^cJXx!X16$_^|HCi&~q*<>WuSJ707gXP%8*T)WlnvTMNut8hH4!fPBpXil z(Eh=MsYU_|-}N<*yI=fQAE8uC$kP;2knB;$J0m?1VFcryg?w~S+>oGpe*iq2YxnF|sSGGR zmUDnCbOvYG-v}D=fikBR2lASl*l-5VKn~p@H%X(=3yqRCWvlIY3BH*yG}~(mO(2ZH zPDo+9(#o&>$_{#U;gvg3mMiY<8prt%Fhcy(I@5B4*uZU8zI}U@RtXi%LC*_Az}kH# zX+O$rrd$mz1Qlu>Upo?+H(Yc87uz4d63-UlyD=2@Ge3Oq9hB2M=IW_Ghp)d-LGupo zpIajF&8gJ#Yv9-D)$%k^y!m8Pp+9W0b`%!xBpRVn~+S_FSEUJD~Z1`V81gL+Z|8fh?8#D*&}BaN7l z51uFn*4~M%V@p%ZWu(K1H7L0^5E3etW)mQ4gXjv&E_dI9tHU9O7sa19>Bl}slGAiq zmS~T0@b|)X2>PfH?ts~e=$2Zar|ybqNMNQvSAv%r2%KfCd}b1|>P!?pp;k-^H%?P7 zCWQ-T0q}yA#@Q&rWLL9VZj8uBy0RhDNZA{~TR^=v+}c`Q> z7PC_5+W7J89p%il-$#2Ve}2hKKUKo{SYo?)gr$e7ASIkZ3#33OMDqXxCE8bSb)<V$Inr8-if38B>YyX`E{geZ9A{=%Vv|qV@9pc-f`RarTdScjY8Ip8!^CH&cWOHf5f_Mr zL&=%obbxS?-2gU6DPcghvw8aaY zH8*gY*v{t(zM)`yIu@j9)hLyw9y{#$Km5tex4?r##iuz>cB5z(aS+b9l_Dx+Z#kjP zA=&H@lb)Fe#tivTFGM~sExQ*hyRdfVEPsTnVI^vwDl=xJYJMqhznx&Y&`Cj^PJ1A@ z9m9^i4Ta4(gLcU|VoVcHf4#~k?STf7t>hJ;PuU%O<^4}SN?ES|XY!OGg~JmQmAknX zv|T1DWoHh~-!{d0+5m*j3p99o>opg6$(P9j8?RM7pgaqQ_3|qf|G_>s;Ea$eP$3|j zkHnUPOGL)9Tw6sh-J#*~2h1?)r%YNW%??G9gH{ z;l-BRf&LAMQOpJlXB5FY<3dh@Kz7OG@SL-hcf$LpF%d4a3~s`omr-U^P=p#=j}B)d zQ$SIVW1=YL12tjoADSjjE3f~12UOGNp-G%GBbiA<`wY>tq(ms-ep;tEv_cG$vVz2K zL)Np)@al-J`!uau3DH1oY2nD;!={X%Pd24(f$K`dw9`ZQ+wy`+CCZuq)DKv}eQLtc z(7Aa>(?e>f{5#8JxZpg&jc&%%Z#RzmZ*5k6kCea@=u8}LSp`yPNFkDp-;0|bQ3S>X zIlKtvu>r>+M_1cfQH>fclz>s}`AE~+<%ftk4~rtIp@*X^+E*G_?*lvO70e?4?RX}! zI0bVG8mbsZnd?a*QRvyJS!vcU#n+(jt{0skj88Xx2gy9b0p#k$;QN z09~LP4fq*s&H``me~m^Yt8}t0`0C~v*rlX^2wU`u(ti{y{8;0|8VQ8wL_`LVj_h$G zfAAsJ)lvk?M?nyHcB17Z90w8!I!)_Z3EXaj&5_0{RUb%aU=ap#7+1`wy%&Ede-xe> zfiezo1$Ehd2VG#uO2cm)W)FPg@<$9z8W7((0e|Kc7I#FuswxTDD`bKenlANiChf!N z3=I_qN;#5o6+Z^0u8&|ukQNe0SPuaxwwOr?)+A@`Cb8js&%%&M!-rfF1}ReP^#&^G)YVbc#5fI zyVZ_+5uz2!XJBjhZZ(~J|k-c7-J)gs&iZ>Jt+5^n^?1 zAN>c!BQX^C*_3%{^pT#IAt9VN1|-vVRDk)&KsGVE1iX0?6c+HLholfkKpom3jQc{PZ+hqSTQrgw3NBQX)jas{;;}`1jr9VSI~s`=BgM9REDRck z;B4buwKfLPK)N7!FB<6*LpEE7DP`1O|Cw7z;d%i;BD8k~lRPOU^KqxJ&ebrcNRP-4 zMV&4R3z1#RzLyYX{MotLX@!aN^JtCNhzq@uY?;*(N|3h2M4T7{SKZbfT4jI>B$f1( zXucb7F^8kQa@Kl_q|JV1v&DR$tFpuGf=MOPv)Dsf>X z_Se!Tsu?pWAA|HZ{87)^0>q#kTxN6dmUQ`9GH=U@N2)^ZN2 zKPJB~3~uu#$)y|HAdfw+R`3-Kir$l?R42iqi%Gl^KN3%$bC!Tp8;zML`#jW#jtGr1ePrfI}?@R5U#j8bS$DE zB>5to!O{uZ*T+v@3H)iouF9@_=2Q_nc9%o=QM3LB=WPZ8bA-Y zHLMWF(F|2G6B!v1`;slPQ~^p5NIiJ%H~uT4$oE=A+HPzuz8|>n6hOv%*&pE)nb9QA zSYNW;AbVTk60;l^N#0_!>H5R;z37KAuJ@5>MUDqQ%a>+|m#6I4V0j+~Y}nxJb?=U1 zWr~#jA;-%Lh>5b!+nNMfxuIBt!S{dhziT@2vKuVDe7pCG3MSUVLg?%Y6`aeP$IEEX zc5c&v%qwUIbjgXzi?oYecgGF)1L;r~2GN_*Pzfy?c{weIHh9B?qq{W-f?wXlg&`?)30uZM<+1%R1@& z7!I=p4f*mqaK|wO{qP&BC^*@rp2Y-S5_)!|FRuK@zoL0e+Kfqi8k?goV%I(&ZYm}U z3i06X4)2Y6pe#rZ5#3oyE_}iNnm@NhEdy;rYkMa|zoFUijw~iq>e2nQCP3~8Nf9WS zIrQ36bYdU7$_TC1X;ksnNQ6mjL1qos5%Ws57pV)EcpYaN9)NsO$wg#~VL`_tff1S*e0q(*0= zAX#WsyG7Dv=N-~Th=X7M=L@q9lt!0;JF_n{xg#1}i->G{;Y*`a?A<;fTiQuCm+=d6 zidtZ*;~`taQ%QZ_JyU4lzRv7Y3>};Ub))mp((a>+$3r~2kzs_@susDkFOoWfl%n)n zSWr0xVMY?EGW0w#Ryjn?Yrn$<-Nj)R(SW^%hUIz1KsRAOWFfyo^Bfjf9EsS{1yc|HEoQ?dJ5s2@(>M`J3qyA2rMNLy&;SS7bybK-9p;Rvwy;mymOXHz4 z;EXvo7J8dBFl|(^6{uFk#LeG4Mh_$3qiw@AFyCYoQa<(Q$o$N>SmyEm2 zu3`)+0$X|hKW3F1LP8B)hs=94OX3vGwQ2^dTZz5{#Wq&|J17xB)Ez<3{+xA$_E9}DJ4LYzbT34o`XO~5e;BAvz-l;tQ-mM-Yy<>KV=3w zu1lu5PgxibqFnyDsNT0}i;1Xt+B_ED=aV@~#&ixI8~a68D&kLsPRc{eIlx9m49L=f zW1zf=l(i@ueXyE}6~(#lUcH&+ME8=+{Osi8;YM*IT-*{Ah3>2raR*6b#r+g5rKC$9 z`-mY6aA09^4{_|>E+*PN>c)VG{yE>Zc4#whmkv=5vRS&Y=^x-Q6IkMO1^85h+#vd- zNo1z*XvNbjMF)N+T=Sq}fs7J43z!Arjw=}*-oN_A&QA~kCf^zpH~=%mDZm~Jjb6Cq z!aBRy8LE%!Nn*n)fXl6zEkUY``;6HYx`w(+z}etKF8P@Koshi!n{Y8vPDE7>&0LsI zE;sAGq!ghKdsf)mmJ^c4He zn>%D|vXl$tZM<~XLxu5LwMNaX!g3VBPWK^^CAnk`*q&87fL)}c9d!=H*iEWFG+X{Pdz4sJ$ka)zgN38hXFdt^)`k@t={)_1o0``Jk z$K3wnE8&(qwNMy*$?dp96mv|uHi!uS+&DZFcc$krelz}_fuLBGw}i{KgEA_k5oqfO zRa0mK({#j~@o>-za?%F7Z==?MhKL5zc75}&hB?U8IYT{{Uy0n(OKuiwpuQH(#?fp- zt$|)kqN-aiF}aiOT=1o6)xA3eh_6;Nl-L~h=5WvZVp2`o!A#%u{N^{0`fo#QD}v{( zoFcF?0xSe=*_R+SRjEiL@uRK95r?!1uSvvKs|>ucK?+fVZgBmd{VV>>qekSVa6ir) zMtHqidWe~O*Q2I#l#C8CVj15IW?cD^%YZR=wKW%skXm2bl;gGH9oEyj13`QN^px$UMjwP*TaR< z2F}5I1!{;2l(bF7dL)9Tq-7pnVIHPuX4oPMfg%&c6Cg5{HIw|_(c2PvC|}+HWAG>F z=4=T1r#)WH4i!>Z#28`_lh&%|x%wAx-VwwXmWVA3xSv`k35|VCEnK*ROwD-uGa`N= z588)kjJe>WEh(b-JO^oC4=N{HkKbPWK0x?=SN4*MVU-PMr`g>}veR@f1cztZZ_RAQ zm+%Cyi{?LGZMkGehF$t>#2L;?CrRw`$^s(x$5^RLbtgwc{uXv6gxe#XKr-b{X{*PV zzxClik|ojwVD}3BNbU4J3FjpI3Iqz_(AEOE`yH zu8G%dc^1X2p9`sLj$>M)5i2Cjd#`(cr|RRw4Vr8OI~q)~(jzTwtd&K%QiQ$;5GWik z1{vMn^%<}SWLFF{fCIxQej0y2cK zO;!-4x*0oL$@=&Fu`VklLb7MZ3968P$aEqF*S7vWrrs@s`hr~}yIl<4klVjeeHVn` zRzp>S`um}7x?`AsjoRwuPvd(!2i(d6X~d^)TSS2soLwW-&>VHCT>)2mua@sC-#_(u znO1X2J~-S+XuG6pQHE6ocX09&pt4en&_Q6zZtzGFP?rP%g=iPA1i49o$smXosI=|s zU<(94EvM7I{5O5nO!1`exLc;M;O*K+QEwp=ZiQ)V zzwIs*o(l@ss*G*SK@KQDdn_~$d6o^^ zB}7s>DW1;79h1DafDFeVht!K&t+j$}z#?1DMOafC|%D(gLcG^Cs! z)G?qcOa4wZrgxjy?EsM?1m|4UiIQ}7J~%_Bw?Ru*WM=egIq(@Rew>IJIbKZ%?@>Ak zPe!qZF3`AMd6cAG+Nhz#26yO4qr0h$lX!=O%?QADT{%#`^9Efx<^+Qn3-p-_UYlc- zSaJS=$-}r|G>DA^b>uA#dK17Rq#4Hwam-);soz)g zEsq0kC$s(lCq$uIxP`Fm+-*~MCw(Tf*<1}05|S5~oukEXyA;Ok2Iuas?g}|&9x;2< zJ?Qc!Y&^!o2W@hFuQV$sassUIJe5$zT z6f^pK;j>jhE((6+<5yiA+&6FhIu+`UvR_NoEG(nAVTFmElO4A{5>R2+P52RzC6*0a zMu^%*-ov%R)mGG3}fct_UubnY9bpbnnBY+GzLlC z!4%pzab$@^UB+j42P|c-y=!I@uOra5)V~_8`jb1(xHJ@?zMN!_gVSSuq=9i8Ak9qU zPU4sZG24fNFS*Cuy_FK})W=)+jYq~2VG*6E<>eoozOQUWc0QS<2y?!1fh5gM&v@`m$S`EHSVKPQ7rGYj_m6J@UlCJB2{J%a?LYD{a%ZTUc+q^vtnf?&_hS}sL zcokaU+<&k(N-Sz8xtYlY@EfE*Xrki|KJG5KUdikylDIo8WRo%QNP=epD8)nj&PDg| zCgbJr6uK@xUJ1@YMxijV)M7Fb2RT1vYf4$2)SNP#2!gAi_A!vmG$e10S2+7(92o`J|aNjh^wM# zgK;uU2y2-jVjqwH69G3lIR4;1x3uNGsyNKPA@@Zz*BkCb9(nxxJ-c6!K)`!v^B6|& zThx{s)@9)O?UnH`-tx{y1Floq8x{`6#doJ3n$kuz?8OXOIGv7yb7^ls6d$x#5LB6lsPDwZsbiHP)?gHK&Jiqf30Q&icb!)p~*}Is3Ev7 zQ|3NYEr|Aru9QcAehMEQkNYAO+ZU+Pd8gxk2Ru#P_?NF->eYYh4KD!kby=Kf0M>wJQsKchF5ANR zmG*m!(MuD=07%xO#(;zx(6KfX3!kF8@Q&#UG`aZF#0UY%$&nUT4W0;%EPWf;lw{e7 zi8pGZez1LrRe-06Q4zd_R6A~?^Hyv&T?PY>(i3LC;M&Y;@3@bnFNRUG&sE9t?9N#BjG9JKMrh_3N4$|-G zEaM=f!c1%_CYDgymUTVSKy;_Jp8`k>)Do~rffz}FK5|L^16+a7GGPAF>6&}e+bDAD z_grRosESI<+~!TMjt9aVPX=-c0b6@UU}a zTWpd@7K-$2O>r6`kgS4~HZ8gr@@D5}(x#K*1}LoGD@22b=N@c%1$00EE4K_fagcceu&}p^ z4?n)6pKYJ56ft#rD8M6L!vLv}6tZrRDrZ_9R=6ulRAfx&fI*2-&<-a}>dkf{fQ59* zZ}d_E8H(d=J58D(RUZ&u1RG!7`hIgR0m_jNc08gBUd=yKt4ojgnTi`tlLWhSx{-^? zH=v9yjQ^$>K7BPTJ}2J{fTH!YE>Wd$FqwmJCA|+wG{2O#uamdM{BDrsSD~J2Z6rgj zR2DJjg}XsAFM*W$Igra3qFAZvR>+Flb_K$mrX^ zYLVH;%$GS~{1Ul6Zpj>FXeulwg{~uwth$o@r~nFU&9L_22TB0vs);!z3B*BPNp_t_FZ-R*Wj1H3rlZ6c#r}KPho9Xb0X7(d=E$M6L)l zH)Ch-?fE}3}F3G~MlfD_^>C@N7^cN4| z2ZX2WT!o%93q-XAC)4vQlrwS2_|k=6jqjl&3dB5N1V|jLuJw<(oS3k7POwLn(1VCO zQZ*bQV0uigj^!g*OS}Cjvip_a02gf#&eTvVTi*LcqlhJZ5Vt$mz8C0T#(xh>MzE)jXb5HO{p zIJhNZp;(K9dLe()O>Hx@-EP6QY`b9$Tqh>Yo8+?1*qn@=I(U|NDrt0D*zO>(*3@&e zU)UL3k5mL!o#FQ0W@9KdMC5>SqfP{$_z!*EjQ7m0s6<<|mqNUx(vu;{iR)|+)C1cZ zb;Isph`4B%R_BWSm*6_}oA}11uKmoa32CjauH`kz>$T$p-hA` zytKJxtUM}$z`NTIAhLwa`ZTTl;NRU!Ds^Ar53kiYv}wngLVxTG*Fr?G3~$bKvsmPZ zEyROP+PWGPTk*G-7Cg>*+Ndh>q9Iy~)jtQ~L~8RhBu#Y&{y1Q0He>K~1)fH94YQ+# z;Kg2HFlr9P@)C|A=Aqmgy;9W_fuWEr&+Pdpw+_aB%Kl+E?poFFU#n*D6l3k(2n~jk zJG^wBPH}*m6Tz1ex@T6OKlM0c(u`qFp&2nzG}DmSDFZa7WR3E~dtCsbNy*i0B3$4h zh%jwBTr-deY8iB<`66Vot$sy1u&Npu)_C%_W)rqGt!(;n(_J(RdZSvJk`|MT$Hrjl z$TlMcKE(1^!}HAQ%B3Pxw!yBzA+uv+cn`XBD85b`9xO>oPTju>UhNQ_1pP?g-bnTn z?V+q_QnD-3pH#H4f5Yyo;@jj{R@ue&(whfwQE>x@+1wolXQ=QOiZq~XBGRBEk^t*0 zkIc3pMLZE;D4u#|_33Xv%N#OgyV>gl!bt2}H&y_h5vD)_8b<`EB_J$!?I}P+4RTNu zMI4pU@Hcd_bW3+bq>@Ff2L&YU>(BkuW}GZJPkEI)@CWx3oQQm%#2hvCQi@N?%l4OJ z8@#>5$WFSXeVtxDT7<=Rsn-Tf%2;S!=iCQ5K!lGU!Xr?5Fco*D6>KLHc;4;?8wrqH zA@SH(b)#!nLg|wm!$aPrR7haQ{59k2*Pfc4+2jDfC9in!G>1p*+LzhI$t-7R#2^u2 zRrPTcUds3`fjz!Was=z(a7M9TcVgYl-~yyTbPitL;HYuxfL)TSxb2M+1IrI%G(zpz zVdLNqXqeLb`b{rN_K&&pg>Nfg9=ZDpNMmVz#2@|!E(s|bevyC#;Dm(qba)FaaRNW% z8IwM{8emR%x?#9}H*v?x>d!)7HrCp-7El|@W{?=a77*p`HFl#u~`{9n$vNm~H7^m0W7tovYp_o+z*kXyc-f)S~-*;^=Nbb8SK z8@EWh!=ZrvNC*cf1*u~7IQJ~U(S!`aTOx%?Tw47y`brbk?4^-vo~U@FIVCz)dy>MU zo>(zWD(6>$8lL?1k^ebA^HGt~D+iawNA8I3t`3vw6%lMJAo<#ruoNn39_G+d)4l{& z{5F9JHX>@G3NP5z780yE7xPM%6&sR#W=ij#U@fs4GN{`|iYaT-ZeEdj2mc8-3A?Yk zMA|JlqOwGI`^xYA#XIp<%)B-*M1(# zH|)euxzD)8OQ;LaFW@`53=CaCMIeqMK5!%Xd;nU`Q=6v5#Y6lG8$AlOpFfAF;ZE-Kxiq0okJEQQs8*<>_`;P!0F z>4Oe4U@P;Vzi~&&BYGTOT7IcwMqaL-jR-|V)IDV*3hUrj(#;ftMSev7x*O~YR|`+N z&^EYsZo%!oDCG=t9pKlXo4gV@ZT$|Gj7=2Q^Du=VQs*P;}Jy7bEdl zcmcQp>Qn$zI4$~utSC5f5-l#{wo~UcReWfA1z*9T(8l`s5ZHSyhuXvHb|^qwS;aV#2es>XZwK` zM;VpXq&+=4_uzxmBozXnyK`c6bQW`S19YQjND zmCdE#3*Xv-q(GT>g~|3MIFDL=$DotW>%4f@swexFtyx*cxe_xnRQb_2K5`&FU4mk} ziu}T7hKuBkP86fZL;A*$RS@-DHx@rAF(KUs$PB3%AKf0%9PkDU$Y_{M4DX7=65TK^ zAUBTaI~{QR=R1H|0`erWDbQ=@$79M(OG^t6DV+20M7(H%8?$Cd7et3rv$3vrZ|-j%_1RHj02$9-;`> zw-PJYTEpsXNrWkn_E66-(gv^o{%_7UhDxvV0Em{NAT^3csztNmMu3NhyfHV$=Ahfs z*^8W59WS{PuDe?Bs&1hglH_*88;gyaJ6NK9+7B+rmJCp0@i$PO#6GYp+I#Z5(fZ{5 zsVoll**-@K?OH+QO^TxN5$PumerFZ2#3%h*rhn+G&B^jwwXj+xQFi=2QU=IoI}^d8 zR-%~J*;wUF{ShKRq&mzMiFiw#ZY#K~sSSU3KL*ERj_488g$S!{yC`JO$_}7}6&w1$K3#t+Ia)%w#^<7wqFQ%_ z%9s8|NE3Or65)bUh8c|5m7qv-p{M-PQF0Pd^43sWgE+_J3jeknm*WjTzAjS?eqV-v z5$&*TS+M*fah4sD1KANExd}cf0@UsWbcIUjm{hEiT+v_qy_>&9y~=)Nm>x6FK4A71 z_g3+)sp6r#DV2VVkcm^3D^<_&604!yfdesk%f_c?3CUp*momy8fDYvkMuX9ok0H!p z?~Cn0=19bmWlaZ8qdTxY+cTyz7ST4;FSKd)cWwWtGYP&pjN)0ry^ zkh>#8-DgOUfel-swF>+5jBR_MQ49Cw*wZ%2^hEH*KkpmZ1m|Uzuex{bik>EOCS0xV z@-oG66?6lBj@Vd`K6NNk$Psd)R#{017JPQj@>aNKS|=&YrkM*3q5^Nf=8y=ygnZ!z zghq+3&23+UO-=-gMM+8WX1>6NXy5G#Lp3optRmzDd~oG&Ur}lgL7AW#xdiE=+TGRh zhsi^aq5?%VED*i}O91d6W^VrQc9%ISJOto^BnSltsqIFW$pMOk*_23L08ixQnpxel ziHM36f>&n_6*h}=!#kQNavV3!lz5gm6ujgwS6=y>^ZxYLe2~w;TJ^RkNqhSEf;&kP zo?nu*@1@+H0;fi9GqV{0Go1dr$g;?ucl{$SWx2i|lOPFqNOFC(tiTceofm6OFw-?&f1AxbK!4Ve#3^OqYRQCHJGiiL?nBPS4wom&>M+LPGq^7eC zS1h{E=hROkH6Dik9LNDQXh#GZ=a=mdWKz;=u3kQRo?hQ19i4HXefY`U?(;-e=qG0O z6X%{f3LylT*O1tCa8D|vpED)HiVc86OAce|hn%)y&t&%EEJ%h1!U=~iVnMBy)@|8t zx+$EPs!T~$0D!SEKTrg6+aMPV>0?-~*45wnlR9zPbj4f>9tfUU9Dl%_U(7> zVpfG~LW$?0>d2D46wH}tT=z-z6p)H=MI(jx3Kg0&61MKv9 zo*T-)m{@bb2w=Y~|_4at2g!B+8XI`Hw zI`VxjXT`XW0?mt0FM${^(Q(J+bZfW&AB^tLDwc{BoZ0j{DHJ<1k@KRa)^1p`C=sUs zjf3Hrpv$n(DVDdpaFL!GVwsx5&=8-^?MXl4&4i@Pp()3TOJ}PC)hY*u><&q2hvy=s z?+#~Uwx_B4xh92qhL->ITkXf_f%g{3+>YmnobgKxB#9NtiBe}Mpg-LbwzWya8i}zr z$*4-(=gF!i)3SLL%+`&WL}fi;v;A5Gh9^G#gAcVo=YK7rH#p$fJ?VO1A*E`M`*O7w z!kRqfk^i9}5gvuKi*g9?|A}ob6_d0U{dnuAZS=soCjK0ZChn%X8a*=f>-(UFWz#84_|r)4(H@4TDk9rrrE`W zt%XBakQk<(=Jmc7!xB#5O8P41o{hihQf~t=b^1fc&&MS4lJLGWHE}0-(Rc1sNr%EK zGJf5VnpP9r$Tq_fvbwXvdZOi7Q2Ro?;ZdB1a9Tw&uLPA}`{GVmPbJRdfd=8&_3*A^ z9MP~*4Ie7tFn7X;yxK@Q3;mE;frvNFuv)|=eA@9j!Cs)NpGTPMe~?fgj4$enbocW? z=fy5+P~#NX1PdCvW3XtDvSN%$1I%DB+R_yEMF(ccR6cP8PUK?cd6RoRc4#&QY#pjR zT@6bwQw&0m4riuwJV&v{Bq~QwV}t)xM5izp6su^FJ0Ke|GaNMWAQW%H%tE*&o#`*L zq{P8olHds z#FMmeb-`H>EQGc_9Tp{OgzpHNvCE$b{8F{(=W)Y|sxboq&dvAtWo9>VG$>O!uu+Py z`&v<98hMq9bM)M0)+__vmC08&MBZVVxAiKxP{^4B*g9 zyWU!1@^ROMYdU96ZO&fgB#1svL=2JuPJWp(Z8As;TOQhDEM#!Is|ClUAY=N$X{=B} z8U1FwOsn{R!8r%&n+l3sBj`_Fa@dVV+CV}>t_Dbppy*|j9S4VHZBr@DfV7K^8oUE- z1$BGnFTcVO7vIAzSs@!{C@j9|GFR)hUG84=?R$**6d~QIJHsebpI<^?llGVW14rpT z&^#Kvz3QAO-Vqibb_?N~1h)!aJWs(Ns8Hc}a-N7YfNQWm-9JJJKRr5zZ-gZ+GR&-y zeROY08Mz!VlU*YC-p!KqDsVb z=|M(FjvdhzJ6$-J0-ilZGTKY;{miZ3a_{NDUT(SZZ`}1txY!9j^7m_4%(1IsNS9C! zoMPGqGeNj0^Cto~|0tTNjwJUdENiS2zNeF!`OVHI#2p%ymvEPTp}NyHzK*Z}rI`q# zphb6>fbtZFt6l*t2kmp=*B|-NkWPM}aB40Xx{Cl8`_jc&XgPUo}~sz5p6Ch-t$@b@viQMdWbmAs#6)A#9bNavR*Uy!>F!pr&Y5w*C0lO<~n&UPW<(++G6; z|9dusg)>bSodKK({_!X3U-LIga?I1?;qprXO`@-++W5R7W7NI6TYBMmeM z+iC)}#CnrkWV47;2|nnkr_PjS!2wffvpW#Sl?|%mMQYl)5U4YBHN&X4oPpfyzeQKc z`wc3D<9WQj70zQ^E2uRi!U!7>)ykxa)pHl{N8=`Hhtk*82@j1fFHta2MaAUCfze15 znh0K;aLyE@JFMuZ;?*!d@{cI|L$R$Anye@UW52Dz*c<}(E(D8w+~fKluue43VD60ptl3J@wO zC68+)ELpn&E&vuxHK2?czVe-4Kkvsd_!8u?%Os_nhuz6mhlmt;#&Y`g$QfcuPFh-U z2M#!N5cbbQ-VDTXZ-=nS*?$7`+CLVxZtny%3~J1_@N6x}KeS`i^4S+_gRCmC6Qzc< z-v7u)hy~vVJX|INa)Mr6$B_{TRkE8ywU4s;B9(lnP4o-TJ4-$V7$We5rbX;3{k@Jn zK+S8zr7RR5lp=GQz0*AO|XipF3ZdGObioBw09-W0q^p> zqw)159rFUnqW%y+`y!=c=Jn8_? z2duN9d34nQWi*@C;Z+xA0&){z5Mm@4UgnSYq#sa|%rvIPW3NB|y`S)iZV0G6K5>pr z+$!}{oMx|Xa!myR5D}E7)VNo7m(eEgkV@EH8wm*142BD(W4L;6_3cb@WJ7?<`AQIz zw}T?tUKxxUGnH8((w5@^?*AwqL#J~FQ@pp*I#rpNm>A4Xz$s>7jJYI!GJ2fPq8D3p zrie#cP{vllwJ&WQQBKnRXjn~pcMupuG>COnK;O)@i``gNJgfHs=}D{$VN@y!P_EDa z!|ag%m`~7TutpXtb%i9a51Jizw;&xzJRoZr0xon_6$=3CEwC5~jL4(n+lc*duRE6) zyCR)V*cXDFmgQaXWz4)JP8h@GxMB|++>?F?hIQ3HNwUh82{$SaEvi%r^R`Ay4u08s z1zA@WeUY?*Bh0$?#E)yqgB<2`qkz@A@q)R~U08j}fa#LLVo!T))Ae|u0y#s|4r+|u&W*#oxMUP_8A&# zjF2frHgmLisO2@%fZQjme(8O@S+Tg| z*+kiSOogp#$e=rKBO{H6!gsapa6!mAJ_j4fh!EqYEbdHi)>Bk(9s8CN(upbS7TezS z9eeA^`-ZQPf!bkSzWTo_W5K6lgx&yq!wkU}8-GD4F;7h%p>@d>2ENV3fA+ZsXLg8Z zqmiqE21+wTC`2dpCy?sqskL|V&M4-sRaGK0Nnm$AzQrQ-GJ7Ph^N>_y!izI)I;ZN;7eeqgsS7(BY{ z83@s_1(sGPbRS!9>c*T+`Q1x5?KdI6)s0hACPKNxQ* zW_(4ZiizXdhF`FVdNJKN-Pk11wXm*;0lnD6cC*4*5UH*F_kRiCw|C}vvyt8p8Ro14 zKQEQB6_R)OEI;>z4@hql3D;NxDpzF(kRNrTB@YtMHJ+%*1WeMzTvmcf#6~lKwCnwE z87vKn+>Cmd_j}Uy_XqT`U+U{l3B6}%=+JR-n3+TkJr;;25)sB^p*|bj_GG&Hgr(}q zsK(7lf}|Ynk@Td#s~+}Ky5UY&N* zOG%wR#iAb=fsHhBbIf~pJM?C1#Tj^%`cqc$qB;>3K#?$y?*&Y^ zGSM3&sC?kEfit9O_)4Tl+}1I6QCVnY?t?M@_0*4z@v4rIcrHM>i5o0{3YDQT>!Nz) zm>EKHO}sIv*rD4AhK8{*fLEvA@!1&spasdkeTqX!6I!(a32Bb56|=AI6kf!+WN?h| zvYE=Us@t4vZ#ODqj#Ml=fk5dme)cE7VK&IGkT>>>Ikx!x;?)W2dSHfYwXXPyu(l%D zokQRWK8i~+f|m|3Ik<aTvALP909154%`k`QVWvE&VPlac^U2ctD*R_!Fzu+A1 zAuVa*N*EtNXiI=8?=di)o6NDM$t*2p>2w&J_JMYYGn@g_wY_E;h^dw!Fh+a;^&JhEHWH_R8uAUhQl%I(VKN6zF^mfJ4D#5UFf^X^J5-a`h6_Gk{d(<|6aIlJ zU5%+cGObh8QqrSz%^qH1;}xmy6sTH+#1oDB;c*!hh9de8y^4@!^2IS{KAfSV5icc{VQ%r75EzGpwpwZv?`K~8W+00 zh(pTfIz%F?I31qpclLOc0uWo2qVn^dP>Oy!M@AVPX=v*a&nwlBfDmQ>3ix)tW~@Bk z5L^Yh^$3A!G2hG$^VVdlMK#E+&b1sIN%9M?T}bn9C80VB4P4@+y=Simqz1a^C=z)q z_F%LuDQ}F;u&+qQ1t4?;-G-wL*C{x@c3S+FOEW$iH>EKJr2OTy--++X30iT|CbCSx z${HJMZCL0dNHJX~Q!kwq+od(NKticYbojwxYtcGr;z!p$6c71>?h=dgT(IXOE{didgMl0mnxo1fNta+2l+>)ystF4#_5UrOg#G+r+UUa>sezKHYZuZ1^c{)9SyS zywz|ocPv`VFTp>tl-ueUG>U*In}t$p_*e#rvgi&>nK^x& zV$X;q&O-KH+#J%E8=M1_z_28c24Uy+It2yZl*8$(h?K}6R0^j%uW-m<7ePHXfk+LX zg=4Iuc$#?5FnIEWVS@}@Sw%*LkQ*QAE}tCGv|e%A?0(}t{|}vbWp0JK!lB~Ogug;Q zC*5(+y60Vw)27t!80(*C^)QQ&AB|$;mRaJ40prONRwAVbiCR$vVEWJ!b2N<`ATENf zSGDm>wo32Cys050yb_dk=ElB*ML;C9bd^27O0S+FQRA|(#gm2>Da&Nvt3d(jw@Mvd zPz1u)v+x`k466J(f!Duae9s5;?Q-jmpCQ&N9S*Y-%Ryl4>8K86LrGvje%m8L8f~7r zhSvLMY?MC8KM+hBeDB}hG_&S@i}Y0~0l^R?j719uyF*bwJuYU&o63U)GEFM#IA%x@ zG_YCq?!CmS;aT>0PwSuA$=MzVlc8ULyY0~-d&*jZC|clzM}P3#L{5sVsf-atEp!O2w+Gk|zX7L-rL>&Bg#`>s8Ot|X+^n+2N@f-eQm zVah(XyAO+G6TK@F!zK***`7p0PHE`C)M2;9>w`_Z*OuFekrbu@zSwZpjrc^@m$j%L z=cMUqsCq%TEHMvv1TQ{7DDa*bKf+W7U#+xS9FZ{IGRnHlzKAo1q3mG%r-K|;oJ2%? z(on;K)3)9iw-yw92jk$?amGxB-X3yohuI+*ZlOIjt0xf#yTL$uPFSi?w9%2`+CFr2 zdwPTnP=CMsii&rZ*Ta;wjiUNJ{2c-J2|L#e0%_H&b{@}Sw8>1+4hPrqJZ?OL_c zt_HL|E@TJHLxlom28s&XNkmBu!_#)~G2eb3{{k|`y&3l%ShPCfwT*8-)V=iFYQA(grU&~i{*%`L>b>ees&KCe-7a`7_#zM z6Y!UvH(i`?vZ6?-i2iH8@X#G4&X&hC06<#wn4otoxvNIOvW(8~Ws@Rybny@dV;8d# z*cDRu_JVR@UQo67?9y=;=lX_Bri3x!HqVh+9jeib%|1et^oF7FrC0&RmM*_(K74-+ z&1zz?_?%-ymt<`Th34Q9#thI7t#h5IzB``g?4mewNTQ;7d;f(V_aaRwsQlo!ZyEBFc$sk>59xPJh8;&h z&=GS4W>4+i_9MBBBhKey6dR>194j57!&(S$CG$kc4C{JLm!f@nU?g2SQ8VNTx)_sp zY1+EfLeN0pB+4#h^4XyZ<}~>fi!Vb2(qp067T?{QP4;VnfM1GY(JlLoOHS(qWGlm| z?ALcvvJhXO>mSFWFlTb!q8q>i>9d8oM8$MONqDs)!(qdBz3>qx0U!F6AZ9hvmS}8} zrEVxSL{TISh(Nf448%QOzExfSIIY)=JUKCrZZV4^%C5Dvo0dwkJ;Df>G{SqFGtbUs zwR#E;OUwN+`w#}K1eV6?^c!R^fCUeMI;q?-BH*0H0W+njfqj7v5UQYIk9S)zKl-Je z0|}>VRk>F!SY{|YIHPKk-GyIkL!M|Yp>JX{Xm5hf2nD#qUdzJJCO+DrfTZ~9-au{$ z1{0$k6x*xFp5_U2AosRA77@6w1eiOJXmI_jtIbO(|5INoT%4#)aIoJRqlOA(TI?<& zgojN~bs?sv{A{;{F+ic%Ddj^Nv;q%8bjkud&a5(? z;9oBviKhX2h~~g`LOmWQ2)W>v8u@*cc#u)S^;HtD%n-Fw3=tiQSY5dRXhkgv!<$CU zcAErnb-){oYxkU;9@Y!>CpXu6D2$D~Fn!=g6dYxz!~&2zE3TnkOD>Zc4OAq3%{+NK zj>~6hELY|9win&UL-VHV9i_pI%D;Fu7YwzIz70g9{Dhj@#-YLlSu^r-@So!3_ zYd(G8NP|TXdb*OC!*Fsm0-6F3Shx+_0`t9%aIn0ZR!(FT#JVF0-uR81I0gDnpD?Zy zJpHL<)oRm)sTgvS#Z{V9s)3;rZmmS+RzSmO1&Y0(4oY#%tdSazmrU0alBMNlamt22 z6C}!$lo{OKZ9EkigSe2~P^zf4+@MhVxSDS!Y*-|d;M3pszY{OSNaJpdH|;d{xFMYZ z$X*u)7P8P3VW}{xZ-CqfaR}Ab%day<{i=tbO)rpZyOPlV_W(^e*jN^Nb#JC;$z)g- z&Egg{SxWFbb=RK40;1x z%7hjl3l?Plz>EWU!~V4IFe%C+r_PI`xswibmw-pJ2ZMMNb2YE}X@;!rndEST>Vy+YS>k}*Z7pkU6ZxxK%04A6sZf zOLZD^j5}5N`okXr=yyO&vOt`FaxDy&$wofwO^y(EemPV#kyA*W6;|dgM`@u0$o^?S)`Mz=&s8+{#k(wlt?+LwCcFTwv z%piW;?$`1=W*76fCTZMs%IR!at_(XtIpf!wSwEV|&PMrc2+v&agPQe+UyblY-N?D! zo)mMtmmAH7X&L`=ZmRxjRL<0=mg2tQY`u@(f^9qoKgfCq;=X)tC7YQk^o8MQx`R^; zd@svq|Brunv&)BO*J1vNeCH2je~QMVnea^5obo?2#a>%vv{^RP&xPiE7&Z@9GUdDl z|4Al4b!&Z!y}N0e*?L(6X{wDB^S7QUt6AUhLR79VX7TIan9622Cz`M1u9*90qfD63 z5>X89@XzmRXDhziFqHlJt0WS6zBiRkN3#jzDW~axOXL0urD%jFnE6vsV7_;7uyuTJpN`r#HVvs~1l+6QJ5GwGGT z_>R71t%F<1WcqpjkPFd5lyB)($<&>QZ-BtCV`USw3pf;2!0k|D_DD-}M zq;Sw1t&S8Q@}e*-&qihTKA%i{iw-G4G7DiavKp1k(e1Tp>~qo2l^-cjPyMXUlqcrx zb5kt1#b8IhDKcz+nsUjpd!l=|-)QzTQ*^c_MLCHHcU`wRCM>B)EB|NuD|4EOC5xwFYmlj_HLpMsL?imq@7~JC>w$x)IJfd&Hg|J5#@Y_$>1L^psOJ4Deu-_p&ervr#?EKg>?~qsdg32}jK^ zlrq(qevy&kZ8fs|Yg)f0t;Z;x7qok{F=iW?q?`mqTe1L&ge7Aa>CrL^q**t9_=o=m zS}GySdz`1S00)P+kBelQv6CSx%53C!axs&VqQPZTzE!U0 z%5iyfc5yVj8A{cJ`P_7tb!I?e__5KO2~YgOopCwMjAmm$9Chl`L0^~&%XKgKStlI5 zc>&d@DbB}JaRcN67$NAy6yz77@W|DJ3=ZmtQ5$8WPtk3l4zMdb+@hS6r*kjFVa%Ob z!>Js^BhTn%7C!x}|K%bNmgGjK4pz$j*(dzatNW3&Ij}z)g|mxE9wTx-C}wA;9$|`S zqcqHn&Kx&R{@*S#9c#m$m&=>jYxIp4{A^+F)%-=jla$FmU~7}wJmQQdsXx`X&?Y6Q zG5^oZ{`sl$?0OtV)7b+^?oZQSjR%V!+3#jO9_adCoyE4`=os|;6vxr#eb$B<4Kwu} zd5={Z&H9hOP7fu>9rBY(%0@xPQKp84Z%i&~5Z zETWHjO-CI*Gl$F|IIItU=w>OaRMuZe^>3Iff8=Ktsld!;+=Ya@YjN_^64|L-z2PM{ zKQcY#fAUu5R72v@*cVLHD5noQnLCqYQ+MUBbUpEcsY7E4(ppd0I@F*A*kmq;ipa6Z zDbJDF^N%zN$z}dv+xszP+)B6Q-a83v8yP<-{gnR3L#QLiD8c3|-$Ar# z3CfL`0;FFrR+~SWJ_XUx6MeqBnc`^i(OC~2A0vXAHm;RR*#ra=x&J6(h@DA3xA#yc zmcj#4E%;?!&#EBX4SBrU2he=<<#pP8ZKNJ_!iPH+Y`WMmGOR4shn<>>Y{Wq80a=HAyG@dQH(^GS!ce?Gl=!J4D zZJdlAiXLene6(D?aIn(mA={*W-D=A1>_##LqoHF%umsBl+Rz^!!*k znF~1-U_NS3HTv=o{8axZ@5k!{9llWa4~}7Ye|ah$^?!LW&}T0~8S|L}w$Z5m7- zoH_+3^a5A^zuP+>FgdC!(N|SEu`>ke>hxrrATZU`upK1ggb4_IEY+1BGGw!+W+1VR zC?uQUAM^!T*C*@xF*T_UgBwgDu#YFJn7n}(|DrDLbN%xrAW?K#35vTc{sVU3e)=tL zI-pDReVX?>x4L?|XS!#)XF7a=%$=UDs{7~MbI(2Z+;h&ow>nq4`8VFC&1V?-z6+B3 zlbhEio%f%;XxJUhShl;=N3P3#emr_Z#2DSnt1@DQ$BK>TMFf!`yWSFBS?pgTofSxV%*?Ji0kn?58D8(!f6EL=1kBz03>U zgC--IElC>gB6dx!?VDRH?7~~~6X0;!Zo%g17>)&t9~IAA-lLX91z_WiSeioSVYUtR z#nxPXvfz@4^=N(T7J8eyu^nv+7uSDgxn3+>)TzUWniUk+Uq|iNIdMxXu1XH#VDk3f zTQD6LSw5I_27A=+S!s|e2SL`Zo$Kvdt9y@X-rnW9ePDr?*Sv@OApJ`OPt}2b^fty{AEfztu+X?GVNSA2^|a zz{HTva4Q>B*Dv%&AfKC@!;W529tKQ^tgT&pl~x=W@J7ID#HLy4dEmoOIocMTZ1{ca z0C3=K3L)3<_G;dvIQ?iwzHjb%cfShJ)wjs7QTZUurVSSCXfGf516p?FLhl{aw+I~z z9Q*Qg(yAo-81%DkvKN!as82&OR^a23N%s#d#GU38PGw$tv#H(58x0DkcA!I1$EIu0 zed1h%rTUm4g*Nmu6Be4rA)ny-iBf^xn%l65Ah~^gKjuKeK5eFQi#4qFl5k zTEQ^0yB8Yx^0dxDGw^d7?!_OjRr>%sb+kvs9yRCt=4pJ84=~9l5uwbO)SK7Vd}TiM z649x{gnjE&H)#hL0e4<$dXK_d`MibXRO8u7h+YGk>|zJ~(XZRfP1ZFEoWbQOXZA1f zM(#A>t6Njro&B^@SQT7ZyTd~+>;W!&smw{jhcv{tV14QSe@Cw18OUi`w{PItN9r^;6LO zu8U%zk>drv+f82ofO8du)3I9z_I5+Zz1_EG)WGw1x?XnFa=!1TWneh;uXe+Z`2n-X za4zra&YfpLEo$r4_6M{Z{lQ2WY0WCe!9&xQ#84NW+=yC}atds%<@h_oF4yNXsrtcE zH&NJ?Pdu`HgLiIU2V%`hub#JkAe+GAT9);hRH#3ZP8tVSiTZ-*)JkVBymkb@Y4oS7 zc)6qH#FxYptmu5M2qSbb=>?v>Kb_xfBmj{pWSsO}u2VP%^rVkaI5d;9vqB|PyXvMG z$ME+D=uBuk+7Kt-B|*?;V6A4hgzUca#iI)rJ@H2m{GRz9sjb6{q!H z@MQmyZSHBQ3!W?-xn<+K*kDw=Cc9_Rq9_02>j(BE7d?6L16Nt)tSznib@rjyr#N8We@Z^ z<{eqhxg6=3NMB`R)ulVm&iD7b{U{Q-93uux+1P5Pj18!Zi(mNH&IFp|2KX_D>mx6= z8^Z&!!}vky75cSK*{UoJ792E-N};Wj(=k68RZh%DKZzwChF>@2^5~(?YI34S@`a{F z5v(k0lQ{eOlJVE>B?H0<*3VmcESMPecImWmS3Yn12>%>Zj@pWP2OM!1qV@)j_1G|b~*xL#OMp#FAd_&vq{TNB{FzStuK6cuH+CM-qP;C zqRHvv#9>0jT2{Fo<|3tW(}608ZInQsmur`}!0HMyvjb?4eTB(4te1ZDTS3?of~O2; zKBw4BEK?}}Jp&vM+&f4_B2vEPTTB5?hcdl{#H{<^!L+#qWRN!Wi?=yc|Lrc_M^fSg z-kG#Y-}r3G%Ypse?zuyz;pn#6&CVJlFs*JkopTNP3eC4aJvf|5r_%9Ux3C0mYzx&{ z7)47g6#RRfST}FezBeTgPDc)%$VGXM+kPV1VfhKfXJS6lA8^IYJh=uDUlZvfsQA4U?K3^7@DOMX?+ zY5y)adY|4Ulv4(b6mpClE(uEk*Sd&Lhh|0Ym*>r3BEkk zgwh?4Q3Iwx4jU~%@FnBE403`D382Jz4C;)~o1O-!UUNQ?k={gk$LQ<_mof|0E7a6#13yg6nd@{JS`DuL6#5WN7}2oQ$5DxfM)7~Q1U zXMS)F-D61}oH3~05CpH=yp(buNw3E80Y^|uUa?>_%#J9KqJmcG z_m?otvtH49!s;|S)6}f>1o@%?uRLr9-MK>MVb9&|?fEy`JIA&~Hd+?^2A#344OT9f zr>{J#GnpIkQvow`imGgrXs4f;&o7bW85EfE`v-S-y6bn_ zy|_7W`{u65<=}yCJ?M-l2Kb>F8xM%E6}G700HZ5LwV10|ufao(ZMw(#(&tY?CGy0j zAbtTu+dL0?cN;hk)uVV02_xAWj7ibry5{1)E zFZ=5^CB5vu=9~lT&c&mKD`LG^+ONja>cF|N*RmM+S=x*t+=0Dpc4H=DE&JH6woSi! zBc^yFI`!iE4_nMMu!AZFQpHu`5ur1kLGg=x7_*rYEQx%@vW{M0^t~_0myt@DzK>yA zNTO5XCP}Vemnd8ea`&bT+zb4Q-zIS#T+Wvw(fSNa{OpHPzrf*r449qzsMVRnCcIMl zJ3xa9N0wv8Qh$UL^n!eQZLuPSGeK(oUJP4?8K|YKd)|i4<$Ie_e%~V3M2r`Du+{Te z-`%=zb?Zg?{3@DWe53Tn=G5RwAh0lsaj4mr(}5phq4*NIbvz!*>_;Gp!$4d>8g)p$ z=vD0T;9tZ#v|$0xVDl&v&DPF9+xqEG#EviYS>C^O;+(+R-i0$}?R;(R>4vu(TYi*& z(hjULf&;7J7gp^?6u;Qu3vEZ1&v6V`2Ae$IY0iNyk%>@>-*Z&0=ayP6j`34iNjH(H z)+bSW;HIZ7)3~|Q@WdP7^9IzBqI+eM?VX@LxY8T>;lNdVy=g5RmeUWstsgo$_^cjz_!;&|vK~s}$ruei9BdIJ~=JepskFRhFKk0Fv{7u~BeS_Y^xU97819>Jx zAHoJZUFEWQ(gl@HlqG4>U}iaQ#OZ}qZ_m*9oi25n&i6Os3jsGgilCDA?J!;W2egAO zJ2KHpkZ5-4oqz76a|{JDo$u*!T;J$TX{n_-gqyY$3*Q9>K#c7<_=QvkEY1h|cQw7= zgF};PU(Ea7tdlg2JC?-!<*Rgm=|>py9e4r63A;aCWEV!!-Rh<(gQah1OPNjpEG~}H z4>mF1Ik+&8x?9WeZS7!2IUqpM8qzhuL&GI8Y6p2VJ>6R@zFc1y@09%HgtNfd4hm%=#6o+$8n=3aC1P&&(?)FmQJ}SMkI@k@*~ELMqNqkA7Lh zgr?;wPHu4jsxupOW<^PnJhHr16NdEre>i8jCTfz0YFJcKC*1#!b6+EBWkR%nTU(yg z6R}S8chgPlXmbez3;jV+7BPdB{+_Z%F)ngSug2;^ze)L;X(6*wTU5K4AdSl(N~%I} z4gTZz#w_Gacf9AVm_W=>ao8TE*)+UdVm@jm^S-FySWokFg5$N|N(rno*7tH^$wL(% zGa0K^q(C`XmZ&28ULlw1;>w&w?UjbGo-N8got^bruM|C=+9(VP z^a|gg0*jDKmaVa@gm}QjHz2tJ>IHe)1DG|ZMQ#{LqVcitDz^fKtD=K|PyrY|@uJ>? zRT!lzFLMBCrObCB3WkHM{^}tRl`*F#X)p|5FBcM6rzVsJ2_%aufx7HVt+q5wg0zZ2 zl}uju&2zvp<;*35vgJS;0qts7F@QXTBiDj7A%0;NNvQ;3A@%T|=fEk7<)bvIq!N65 z1ff$(b}NA)T`P!kOTURpAh96CMWL#mG^@0wTN~zHal10sLPtoLEDe%G=^skM+2wcu zks?)vZ77qW9IYQpy}FXI{*3@qY@k?A5fK)#Y>AbBdaz7#RUVW}f7z*S#k!0_6)%K# zlu7_v*jj}xMS-gDCpF-nAhxAqoqg|qRp^hPjINTDQCz;0Vihz(n4|z-Y8X}EYse`H z_Kp`6(IBZj)&wdSLrZ9ed<}bq3}KTiG%Rz2Dhc*9{i3VYgM5vHD%zgPBS6ath1Upt zgtjC)A!eHP^i8ZSgrSh1C6#J3NGai zl9CZhcxh$as1+*VEl`ZGRw$^39b6Ihq=imAHp$LA|cc`pk0G^2SV7GdV$WoyJwU>)lq7?bfeZRott~(pdA-pms zuQS5P$2yH^uMhSIER)K-#I9z|`_vzj$nG^+OQ)7^kC3eRj2*t3c@`_}EM@L>(V8>b z%4}%(Ql%K zd<-%%1w-DZZi0mI$0%+58*Lb+UVSE1!umS;JvL0ajxr!FVuM4H z@G6RV6fi7=D?=P;hqugn@d^@Yf{eHEV@@VI$R#fY-dg?XEny09KW zTngISV?R;L_Z-iWRcoAkR3xFy$kKD+f7oh8rx9?GAKBr!Mqw|mDZF^x4(`Eh{WRPm z{?c-~Kg#;9Y^k6s%xWN8V`AJ{?l6Vsb}N38mjV;cm1*@Vq06vg0i%w z+u#^Mm>Kf(_c{2m5;-4@0Su(^<1j$kz_?>d5z8&{h(gWRv>_b^*p-0+i!2DEFdvi^ zYq~T{)4Elfs!==0dbEoZSKNQUdn{Z|hR{9)Rjn#7{0dBPkj`2X15P0EGPo-7mE6^_ zH3&P0-}&6NxnHh0&3;{4EgIWre?YAv|LNA-f-TtxavQeZR=hcTAB)C?BgG7B$e;W6 zTh2X)%L*>fJb2_I6jiIO3PiYOY@dB3Ttt2u0&!QVrEqM$*QKR3?yBd5r@Dl&)xn8{ zPmxHD(tPP|36-1hvHCl8=#NkaCl3xi+g#Z3#M}{dL5_q9S-Ot`muE>xDf%6(r$BGC9zDo!pB#i&)3&mk1Z)^1DawPzlJ6lwQ5Kr|i z_pI)t^Ds>aQescYzt(-^Yg;8o7fq2~Q~Pg;m>48?y)Z7m)caoPdBVn|FsASzTX zsYvEY)i;hi3?*Lw+ejIUipw=5w~7&YSQ9{7ph?xj0TGq8usx1(^ncI{Ld`&6@l~cF z`BKxXMZ0;BAkX4aAX$Ro7zTicQF1B0_|Y)7Tq?>`eU+jiI?`Unf2jS?K~-c$3<+E& z>MkM=eL6&ea`clzczl0J|Ip$xBC0l`Afl|hsvt>~dg&Wq=E}$q`9{7)3^X0YUr`x>igHKLWIU=d zncA`Rq)I7iZiC(tV2)bLtmGyy?w?8noHFxk+GXqFa3lT(X|(J{7yD~M-$=`tKv34= zqh5w5X*~203K)36d_3qXLWv{g$xvTdU8mhDfTOMg_yp>Ll?Z)-h8XHlWG+`RDvk%z zp|Pyg3s0%Rs-#uvn->m6GzuG9pTMIeiU?GZtxq!3Cs19 zrfy$u?sA!ZSEL_j$CM(WvZ%1Ow6Z0(eSd(F!@3!IWtTZ(8a{>^=OIRK39!YA@f(5y z>yezNm7|=p8hKmVwgOqWWUW!{lg7HJSY5O>`N0o@m1x1xin=SG2-ose*2=`ZVs3W| zdu7>7u@PUagrJNg)knq905uLGu>#2=BZE{~NqiI5&6g!9)QcRQ&a}@iFj0NSbrE#{ zTaM<7mBM!93~R7d3K!r)G*o5lsSI0>%2=+#P#%#fN)%o7k-D~Q?dW31ZCHy~7UfUb zqLeHus8&!HHa+h^7HffO-~wu7)si-2IE;vyr&>*fT6-E-TdMTp5}+|aWSpp0mG8q! z)Hm&t;BX8ERH2PjBWyw+C_1Sp7TNkCn1t9H_u&=O-o3)7Cr(v1(Xm{wzmv3+^h3JvS* z;6T`%iV>pBjo`NJ!iE8a;tdYcO|phZv$4X2J)YXges#JFT++N?H%E`My*G&&21-ES z+j%IkWUuk4u;tM|GXh7MVZx4CJOK{X!<1LcAus70Jp1DfCd#F;xEx<*-Oy^2WlxrF zC4p|kZd)aG8=35P7VTjc@_^e%of5;knk5l*uyI1a`m?&d8dlgLQ@Pl_%J(h=BO-u_9rT@Aj zHNr52JDr$_fx1D7$B<=6heagV{O7r#bUHE_$TW=BDI0-gQ=g%k`*zPom;hZ=eL%y$ z^(qkNEdv#%91E=4VEKt8A+S$V&6Ec}dj7 zCmOUaxr-Ov3};5Pp?H@O{bj3*kGtm(HGg@rT~)|ko7Y^81G@=3mUA_&E7m1Dd^stQ z*K^LVzV$07etVB~_8o4J_+mDbsT`0_{Ya30LKrNG>d z?`lOq*v#D@_@!iSb%&ERpK+fYj_ouv_Dhg2(9Z~b^R>CFJDhizPfNu|-xcx2xDK1f zqr6lAowsa$v!zgGMlK4JFnBA$Q46t&=YQVEAOH}b39Jj_P7%f`g=r;}UL0ogByW%j zb#oM6SwrO#POXxEtV~#B;&&OA8q!kEG4}l}`z>X#hUUGjZHEA*uxRjdEr)1bH+l|R zL6!^PRfVl(3M>ku3%LeeRog)|NY*}3tP;Ze9n0`=$?U`C+%P8GO{eUl zYT`dQQq7HHJe})+#S?n3BBE+C1tFo_j)jH|AInm?+gDr>83W~F^nN9^iJNl& zs2NIVUb=i)m&}e}CI6-~Ck4vzghH{JObvm9NL4<%J9W>y1f-=#xsn;>^blw@psIq^ z(c?R^WF=F>vfH*NF{ek^hF!s?XL(64gRe8x4?sf9fahC09 zYJ{kf5`q%k!AvgoLxo@D4HMnT!+-LS7RZj+WefKwdwLQZFq*|GXCV_~Wo6c4qpxfD z*cMuHD3>&3i8Qp!ZA+F&#kRxPmt{^d=&6~Knzka&a*7!94ySo6E8O?X7GhaiWi@C; zArtKkc9NOHZ~S{2ImpT@H3P77@GNjgO0lOAn?;Rn3We)+Tq|wWUD#$2Cnc6}rz?6}ypbBf%C!%C`#q3t1gG!idl1W`` z*V0XwX@9`m?vMiAD^w*Z_DTx6swpATvPUvRT$-UetI{W7ynM^LU8NSmQZ0~*BiUP4 z`p_0JUO99Lmq8CUo;mOwiwcYx*{NFvCInrtB@ia05m|(n)f~Y6jtAJps&SIoNzMTU z4n#1U^~jziC@N%;e+fJ`3T0T*S79ZR85-R4QC|PY@p=A}%XOrsvbh}>JDgr24+SCt z$_-ETD-jxwt!~0Q>QOB;LMO*qvrf*Jb@DE|PEPA5v!0yb#>QQ~P?^~DARbYu@K!i-8H+eS+z{t+`49?(J*Cv>GaP`k!MUpogyO|<5Qo^{X4Q&a?})F>nJSZQ z>Lv?N&b()}4lIQP0GKktT!}HTBa2emfIz`UFvs8vbb(ab_DwO6ydRTIS;5Q zK!Rcv7ywfQX&5_OUbso+>q16I01#h#8I-y({ZRc>cn;~RJZ--?CRSGpJV%I9yFM%U zA|TMN%g_}_MWb@jh8J7A`AxEqRCZXK+YU z?wbhz@h1Allvaa{@{9{3scxsVj2wku2(8vGX$bw$g>&#agNni;m6!unMH;B~N-1e` z^CVUElvdm*vIFD8lb1b7pTbu7A0!oWC@jl_4T&lbQ-?FZ4hOKipEnpPv}CJD#NG!KIc1^8)mm@x&s;1+ulysggcVv!WB7pjwN`rp$1rCTZB&1 zv~b)^Sw-o~-x=!f@#UpVa-Nc*F>sbFdQ_f?s`-pFxTdTiWtV<@iFQYdc-U4lJ#q zU4=Eq$gCJ+;dWIPBIDZYlPe!Y$<}(Y>X`L0r>kql{R01Luo9GH7Bm3@j9rEnM=VV}Pn`Dp8o0FH%+;V2!ea0jx~*i0zpf5)z9Wk6Z< ztk0lC1YVkR+$%Y$cMBlkO^(sQKCH1jvh2qfCO_L0NUXDb*uVhME?qCjo4kc#5k%N7 zm)<#;>(`ZqByStioZB-1Et_MoEweVvUt>;1Mpni0(V`dpILYTX|6Ur?t*6zv-)bOa zWWlq04o!h-;n~C?vEXS8OtsUMF2=lbB8#f&%8Y&Q@0eYYoN7gq-fT}uZ8=re1lki= zS{cG=CB{NswM&LhbHgXZ$2|0}oVOAQJ8l|RS_z}E#jx+Ub14xiU*ii4yjEbYSZ=t%3X#&yN~sx#6fz+SLWX9^=NM-`KH=1pLP@?tNUdO4+RLhkGbdUli%?S6 zDil#+YLXf}aOUj~H%nSA@xt6qL8t|M^QUzplo?W+5H)pt>}1c@{Xb+t^wvjite_a* zO$1B3SvgFuLw{ z>8dZ+>s6JvIl@_S zq!yl{=tKbHV@j)+jgOLN3>r;XO5LmP=DtdQ^F8>fzS?aMp{tKyLjdvSb#$%Ny>dKw zGg9DzgDJquqUhyiwI0=_1?W#dx?o!)VEgaHyGge1Fwn9|&I-xm*rncby+vduk zm?DH?W{ONKi5wU^_%4|nXmV4+Q5i}Xf3CTV&E&edvxa8T4Bbr8iFxk-L7R93(9P*^ z6LF{;Gp?0&^E4ZITqD-5agK}b6E$;Uv(%}Z@3S;_ZMtYoEC*sRPAgvc7L?sXuyxIL*uw;Hp0`b(y#JBNRK{Y2iJ zZVWtKUr(O~z{KO9Z<~~U#cPR(214m$Z=D9A8x%R71!n`4TaRw{B-lCz4NA-+)_^b# zqh~4BkTeYvLW;HEqH87V;er3&pxS9fpHQ+$6gPtM{X`!6Fsl6BoSW+Y>)ShhR-;ve zjyyE!c?-*x&cAd5fGDD6k5}n`{#jIZ##iS{|J2rv3N1ILVGBwZEozw7a>5BUnp&n# zy#i2d*1WApn8tA@1e3LUXH#QxwwU4^{_9ol6vpa`vO8;@yi+aU$AFj@OF z^n>^7&V+5LV=oJ7?_&4i|N40YVoxKw&0MIpt+P)Qfdb#mTotdo&Ry!{CoGR4@K#=c z*`h9gwD{`T744U7Mf8}UsHfdUssQa@rr8UYyvKF=1y4v_F z%!jVw{hw9Qr&7^dd|WO=g?OTQRwHtW>+8eukd$q6|e{XM%TL{2-RjflPCH-v{oZWqPW z0D8}Z)9$$m1>1#~0B)CQqh!m$MQss`f>$c>-s@)_>4@^{i$adJgw(-BZQY^S7NiuA zHgh!Q-OJRGeoQf+-RSa?ZFJGbbF@8^!E*hDGbvqDHgR}e)l4)atbkkkwdk8|3gbyO z6R_=?)|C2Ny0T5ygS6=QY~_iBSi5|jv#)PxeS{vD+Ux8ZOl$JzNV-)tsU%c-^&}c-z|>tnG&%mW5a9d=oJmq8YVPa5=dUw6Khzg)r59S z;a2N!n12?rhNNkbFiWupglQN(ORs^TZgP^)V43~!H9ilwyD%C>DYHaVj7@yY4b$|m&E`M;VRSSzV7Dg9g7gI;>! ztF5$S^1QTiinXfA%U7q)o)oR7MpO5%c-6Jt`@CfXdV3hwln#3AeeGL@eVHB<6*9D2 z*3E926RI{H;OSWvecbOEqN1nPES>!o!Q@NkK$rLHwrk*O@?w}qyF!{C7g5I9Unhwu z(e$<5620k)r^+~s*i;l6pWa4_%^ndQPuwY=U-25cIM%y$21>=0H~dxHEl zYuiGbG@kHHB<*=&O4zm#u>^bCW!KmYL+P2N0wKqXR%YG}U5B6hCBOu=$-p)DYgVj| z1(lyb@&(Bmg{OZh?aR*yMy2p&ch~%!dHv-9yOMqKo6_O;OrD{Y)HZRgR9Vr}6HspE z9kAw`C$-X$N%Ow)^lZ$Fl7I@+xN9r$(v9n9Rrc%yxeZ%yE8d*FZ_%PB3rC8XccEr~`z`05Q>AUM zIL$uincR_&aD82RNAAcrZq7cE4z|4Ef!v>Ny)D?%3=ntKp5z(9q3mcGhP&$d;HfSp z24*bAU=io=-@QBH>X~1em!feis=>^Hd6S5OoB)~mTvB@E_=|?Ut%`^`-i2?6GpUCD}el*%)dfw{O8Or0d}>sUE6W_=~P znW%58%s5>}oyx{X<;O=^ZxSHm7FuZ z33_!tem4bE)N9tbxSOBAoGy>2&|fkx zL(StUJd{rQi9#lIYKA0_EkRBy_DMkZ#a0EGVN3V&{jRoHCpHA< zq~o@wrIW>YUu-C|$3(I0ch511R_Uu^Lze!@k$yLuS*#aFvLp6rMq8Bb?@ei+G&L{( z$+frqn7my^Aa=(Ph?avIzKNJC8l|8d#fMjL7LzKYRM)X2qL{d;Q7fIjG$fGi3UMsS z6G|W2q78-3)+#b0AoGw;@hmkBRYs`P-Zc^>3))) +mist_io( + .clk_sys (clock_24 ), + .conf_str (CONF_STR ), + .SPI_SCK (SPI_SCK ), + .CONF_DATA0 (CONF_DATA0 ), + .SPI_SS2 (SPI_SS2 ), + .SPI_DO (SPI_DO ), + .SPI_DI (SPI_DI ), + .buttons (buttons ), + .switches (switches ), + .scandoublerD (scandoublerD ), + .ypbpr (ypbpr ), + .ps2_key (ps2_key ), + .joystick_0 (joystick_0 ), + .joystick_1 (joystick_1 ), + .status (status ) + ); + +dac #( + .MSBI(15), + .INV(1'b1)) +dac( + .CLK(clock_24), + .RESET(0), + .DACin(audio), + .DACout(AUDIO_L) + ); + +//wire m_up = btn_up | joystick_0[3] | joystick_1[3]; +//wire m_down = btn_down | joystick_0[2] | joystick_1[2]; +wire m_left = btn_left | joystick_0[1] | joystick_1[1]; +wire m_right = btn_right | joystick_0[0] | joystick_1[0]; +wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4]; +//wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5]; + +reg btn_one_player = 0; +reg btn_two_players = 0; +reg btn_left = 0; +reg btn_right = 0; +reg btn_down = 0; +reg btn_up = 0; +reg btn_fire1 = 0; +reg btn_fire2 = 0; +reg btn_fire3 = 0; +reg btn_coin = 0; +wire pressed = ps2_key[9]; +wire [7:0] code = ps2_key[7:0]; + +always @(posedge clock_24) begin + reg old_state; + old_state <= ps2_key[10]; + if(old_state != ps2_key[10]) begin + case(code) + 'h75: btn_up <= pressed; // up + 'h72: btn_down <= pressed; // down + 'h6B: btn_left <= pressed; // left + 'h74: btn_right <= pressed; // right + 'h76: btn_coin <= pressed; // ESC + 'h05: btn_one_player <= pressed; // F1 + 'h06: btn_two_players <= pressed; // F2 + 'h14: btn_fire3 <= pressed; // ctrl + 'h11: btn_fire2 <= pressed; // alt + 'h29: btn_fire1 <= pressed; // Space + endcase + end +end + +endmodule diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80.vhd new file mode 100644 index 00000000..398fa0df --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_ALU.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_ALU.vhd new file mode 100644 index 00000000..86fddce7 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_MCode.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_MCode.vhd new file mode 100644 index 00000000..4cc30f35 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_Pack.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_Pack.vhd new file mode 100644 index 00000000..ac7d34da --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_Reg.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_Reg.vhd new file mode 100644 index 00000000..828485fb --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80s.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80s.vhd new file mode 100644 index 00000000..5b612110 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/T80/T80s.vhd @@ -0,0 +1,190 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed read with wait +-- +-- 0211 : Fixed interrupt cycle +-- +-- 0235 : Updated for T80 interface change +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80s is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80s; + +architecture rtl of T80s is + + signal CEN : std_logic; + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + CEN <= '1'; + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end process; + +end; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/build_id.sv b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/build_id.sv new file mode 100644 index 00000000..58a0fdfa --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/build_id.sv @@ -0,0 +1,2 @@ +`define BUILD_DATE "190321" +`define BUILD_TIME "131156" diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/build_id.tcl b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/build_id.tcl new file mode 100644 index 00000000..be673dac --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "rtl/build_id.sv" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_palette.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_palette.vhd new file mode 100644 index 00000000..3f0d45cf --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_palette.vhd @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cclimber_big_sprite_palette is +port ( + clk : in std_logic; + addr : in std_logic_vector(4 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cclimber_big_sprite_palette is + type rom is array(0 to 31) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"38",X"07",X"F6",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07",X"07"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd new file mode 100644 index 00000000..f0af5adf --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_tile_bit0.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cclimber_big_sprite_tile_bit0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cclimber_big_sprite_tile_bit0 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"00",X"00",X"00",X"1F",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"60",X"FE",X"FE",X"FE",X"FE",X"FE",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"FF",X"FF", + X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"1F",X"00",X"00",X"00", + X"FE",X"FE",X"FE",X"FE",X"FE",X"60",X"00",X"00",X"FF",X"FF",X"F0",X"F0",X"F0",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"01",X"03",X"03",X"01",X"01",X"01",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"F8",X"FC",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"30", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"7F",X"3F",X"3F",X"07",X"03",X"01",X"00", + X"FF",X"FE",X"FE",X"FE",X"FC",X"F9",X"F9",X"1B",X"7C",X"7C",X"7C",X"FE",X"FF",X"FF",X"FF",X"FE", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C2",X"C0",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FC",X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"7F", + X"00",X"80",X"C0",X"E0",X"F0",X"FC",X"FC",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7F",X"3F",X"1F",X"0F",X"07",X"07",X"01",X"00", + X"FF",X"FF",X"FE",X"FC",X"F9",X"F3",X"E7",X"CF",X"00",X"00",X"40",X"E0",X"F0",X"E0",X"C0",X"E0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"1F",X"3F",X"1D",X"08",X"00",X"00",X"00",X"00",X"F0",X"F8",X"F0",X"E0",X"40",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"3F", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F", + X"80",X"C0",X"F0",X"F0",X"F0",X"F8",X"FC",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"1F",X"1F",X"1F",X"1F",X"0F",X"07",X"07", + X"FE",X"FE",X"FE",X"FF",X"FF",X"F8",X"F1",X"87",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"01",X"01",X"00",X"00",X"00",X"00", + X"1F",X"FF",X"FF",X"FF",X"FF",X"FF",X"1F",X"0E",X"C0",X"C0",X"00",X"00",X"00",X"00",X"80",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07", + X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"0F",X"1F",X"1F",X"1F",X"1F",X"1F", + X"F0",X"F0",X"F0",X"F8",X"F8",X"F8",X"F8",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"3F",X"3F",X"1F",X"1F",X"1F",X"1F",X"00", + X"F8",X"FC",X"FC",X"F8",X"F8",X"F8",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"1F",X"1F",X"1F",X"03",X"03",X"03",X"03", + X"F8",X"F8",X"F8",X"F8",X"C0",X"C0",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07", + X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80", + X"00",X"02",X"0C",X"08",X"08",X"10",X"20",X"20",X"0F",X"0F",X"0F",X"1F",X"1F",X"1F",X"9F",X"1F", + X"F0",X"F0",X"F1",X"F8",X"F8",X"F8",X"F8",X"F8",X"60",X"10",X"08",X"C8",X"44",X"42",X"42",X"30", + X"04",X"08",X"10",X"10",X"10",X"20",X"18",X"07",X"1F",X"3F",X"3F",X"1F",X"1D",X"18",X"00",X"00", + X"F8",X"FC",X"FC",X"F8",X"F8",X"78",X"00",X"00",X"08",X"0C",X"04",X"04",X"04",X"08",X"10",X"70", + X"10",X"10",X"0C",X"03",X"00",X"00",X"00",X"00",X"C3",X"3C",X"00",X"0A",X"F5",X"00",X"00",X"00", + X"E3",X"1C",X"00",X"00",X"01",X"E2",X"00",X"00",X"80",X"00",X"10",X"20",X"C0",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"01",X"02",X"1E",X"20",X"00",X"00",X"01",X"00",X"E0",X"00",X"00",X"18", + X"00",X"00",X"C1",X"20",X"00",X"78",X"04",X"02",X"00",X"00",X"C0",X"20",X"20",X"40",X"30",X"0C", + X"20",X"00",X"05",X"04",X"08",X"08",X"08",X"10",X"20",X"C0",X"00",X"00",X"00",X"01",X"03",X"07", + X"01",X"01",X"00",X"02",X"01",X"80",X"C0",X"E0",X"04",X"E0",X"10",X"10",X"08",X"88",X"88",X"80", + X"08",X"10",X"10",X"20",X"10",X"00",X"00",X"20",X"0F",X"0F",X"0F",X"1F",X"1F",X"1F",X"0C",X"00", + X"F0",X"F0",X"F0",X"F8",X"F8",X"08",X"00",X"00",X"40",X"20",X"40",X"00",X"0C",X"04",X"04",X"3C", + X"12",X"11",X"10",X"18",X"04",X"02",X"01",X"00",X"00",X"00",X"C0",X"38",X"07",X"00",X"00",X"00", + X"0E",X"30",X"00",X"23",X"C0",X"00",X"00",X"00",X"20",X"20",X"C0",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"04",X"0C",X"1E",X"00",X"00",X"2E",X"FF",X"3E",X"F8",X"99",X"A7", + X"00",X"00",X"30",X"AE",X"31",X"08",X"88",X"F8",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"20", + X"1E",X"1C",X"28",X"20",X"33",X"24",X"07",X"0F",X"43",X"07",X"7F",X"85",X"0E",X"0E",X"A1",X"BE", + X"FC",X"FC",X"F0",X"F1",X"59",X"47",X"C1",X"30",X"30",X"70",X"F8",X"F8",X"E0",X"E0",X"E0",X"B0", + X"0F",X"0F",X"25",X"25",X"12",X"10",X"10",X"13",X"21",X"D9",X"23",X"3E",X"E1",X"C1",X"43",X"2F", + X"08",X"08",X"3F",X"DE",X"5F",X"1F",X"9F",X"F7",X"A8",X"98",X"10",X"10",X"20",X"88",X"8C",X"8C", + X"0B",X"0B",X"09",X"04",X"02",X"00",X"00",X"00",X"13",X"C9",X"E1",X"F9",X"47",X"20",X"3E",X"00", + X"F0",X"F8",X"F9",X"3B",X"03",X"FE",X"00",X"00",X"14",X"3C",X"F0",X"E0",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"40",X"81",X"41",X"21",X"40",X"40",X"80",X"80",X"98",X"04",X"02",X"02",X"81",X"41",X"21",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"08",X"04",X"08",X"08", + X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"04",X"08",X"10",X"10",X"20",X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"42",X"42",X"84",X"84",X"82",X"00",X"00",X"00",X"42",X"42",X"21",X"21",X"41",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"08",X"04",X"08",X"08", + X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"00",X"01",X"00",X"00",X"00",X"00", + X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"40",X"81",X"41",X"21",X"40",X"40",X"80",X"40",X"98",X"04",X"02",X"02",X"81",X"41",X"21",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"08",X"08",X"10",X"08",X"04",X"04",X"04",X"02",X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"84",X"82",X"81",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"41",X"21",X"11",X"80",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"08",X"08",X"10",X"20",X"20",X"00",X"00",X"00",X"10",X"10",X"08",X"04",X"04",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"84",X"82",X"81",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"41",X"21",X"11",X"80",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"08",X"08",X"10",X"08",X"04",X"04",X"04",X"02",X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd new file mode 100644 index 00000000..1c506c91 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_big_sprite_tile_bit1.vhd @@ -0,0 +1,150 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cclimber_big_sprite_tile_bit1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(10 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cclimber_big_sprite_tile_bit1 is + type rom is array(0 to 2047) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"03",X"0F",X"3F",X"7F",X"FF",X"00",X"3F",X"FF",X"FF",X"FE",X"FC",X"F8",X"F8", + X"00",X"FF",X"9F",X"9F",X"3F",X"7F",X"7F",X"7F",X"00",X"FC",X"FC",X"FC",X"FC",X"FC",X"C0",X"C0", + X"FF",X"7F",X"3F",X"0F",X"03",X"00",X"00",X"00",X"F8",X"F8",X"FC",X"FE",X"FF",X"FF",X"3F",X"00", + X"7F",X"7F",X"7F",X"3F",X"9F",X"9F",X"FF",X"00",X"C0",X"C0",X"FC",X"FC",X"FC",X"FC",X"FC",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"1F",X"3F",X"3F",X"3F",X"3F",X"1F",X"0F",X"0F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FC",X"F8",X"F8", + X"00",X"E0",X"FC",X"FF",X"07",X"1F",X"3F",X"3F",X"00",X"00",X"00",X"00",X"C0",X"F8",X"FE",X"FF", + X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"F8",X"F8",X"FC",X"FC",X"7E",X"1F",X"03",X"00", + X"7F",X"7F",X"FF",X"7F",X"7F",X"7F",X"FF",X"FF",X"FE",X"FE",X"CC",X"80",X"80",X"80",X"C0",X"F0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"7F",X"1F",X"03",X"00",X"00",X"00",X"00",X"00",X"F0",X"E0",X"E0",X"60",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"07",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"80",X"F0",X"FE",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"07",X"07",X"07",X"03",X"03",X"03",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"FC",X"F8",X"F8", + X"E0",X"F0",X"F8",X"FC",X"FE",X"03",X"07",X"3F",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0", + X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"F8",X"F8",X"F9",X"79",X"39",X"1B",X"0F",X"07", + X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"FC",X"E0",X"F0",X"F8",X"FC",X"FE",X"FC",X"38",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"FC",X"FC",X"FE",X"7F",X"3E",X"1C",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"FC",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FC",X"F8",X"F8", + X"F0",X"F8",X"F8",X"FC",X"FC",X"3E",X"0E",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"70",X"73",X"37",X"37",X"1F",X"1F",X"1F", + X"23",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"80",X"80",X"C0",X"C0",X"C0",X"E0",X"E0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"0F",X"07",X"07",X"07",X"03",X"03",X"01", + X"FF",X"E3",X"C1",X"C1",X"E0",X"E0",X"C0",X"00",X"E0",X"F0",X"F0",X"80",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"07",X"0F",X"0F",X"1F",X"1F", + X"80",X"C0",X"E0",X"E0",X"F0",X"F0",X"F8",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3F",X"3F",X"7F",X"7F",X"7F",X"7C",X"78",X"70", + X"FC",X"FC",X"FE",X"FE",X"FE",X"3E",X"1E",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"47",X"4F",X"7F",X"7F",X"7F",X"7F",X"7F", + X"0E",X"E2",X"F2",X"FE",X"FE",X"FE",X"FE",X"FE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7F",X"7F",X"7C",X"7C",X"7C",X"7C",X"00",X"00", + X"FE",X"FE",X"3E",X"3E",X"3E",X"3E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"07",X"0F",X"0F",X"1F",X"1F", + X"80",X"C0",X"E0",X"E0",X"F0",X"F0",X"F8",X"F8",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80", + X"00",X"02",X"0C",X"08",X"08",X"10",X"20",X"23",X"3F",X"3F",X"7F",X"7F",X"7F",X"7C",X"F8",X"70", + X"FC",X"FC",X"FF",X"FE",X"FE",X"3E",X"1E",X"0E",X"60",X"10",X"08",X"C8",X"44",X"42",X"42",X"30", + X"04",X"08",X"10",X"10",X"10",X"20",X"18",X"07",X"70",X"47",X"4F",X"7F",X"7D",X"78",X"00",X"00", + X"0E",X"E2",X"F2",X"FE",X"FE",X"7E",X"00",X"00",X"08",X"0C",X"04",X"04",X"04",X"08",X"10",X"70", + X"10",X"10",X"0C",X"03",X"00",X"00",X"00",X"00",X"C3",X"3C",X"00",X"0A",X"F5",X"00",X"00",X"00", + X"E3",X"1C",X"00",X"00",X"01",X"E2",X"00",X"00",X"80",X"00",X"10",X"20",X"C0",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"01",X"02",X"1E",X"20",X"00",X"00",X"01",X"00",X"E0",X"00",X"00",X"18", + X"00",X"00",X"C1",X"20",X"00",X"78",X"04",X"02",X"00",X"00",X"C0",X"20",X"20",X"40",X"30",X"0C", + X"20",X"00",X"05",X"04",X"08",X"08",X"08",X"10",X"20",X"C1",X"03",X"07",X"07",X"0F",X"0F",X"1F", + X"01",X"81",X"C0",X"E2",X"E1",X"F0",X"F0",X"F8",X"04",X"E0",X"10",X"10",X"08",X"88",X"88",X"80", + X"08",X"10",X"10",X"20",X"10",X"00",X"00",X"20",X"1F",X"3F",X"3F",X"7F",X"7F",X"3F",X"0C",X"00", + X"F8",X"FC",X"FC",X"FE",X"FE",X"0E",X"00",X"00",X"40",X"20",X"40",X"00",X"0C",X"04",X"04",X"3C", + X"12",X"11",X"10",X"18",X"04",X"02",X"01",X"00",X"00",X"00",X"C0",X"38",X"07",X"00",X"80",X"00", + X"FE",X"30",X"00",X"23",X"C0",X"00",X"00",X"00",X"20",X"20",X"C0",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"03",X"07",X"0F",X"1E",X"00",X"00",X"3E",X"FF",X"FF",X"FF",X"9E",X"A6", + X"00",X"00",X"30",X"CE",X"C1",X"F1",X"30",X"3E",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"20", + X"1E",X"1C",X"38",X"30",X"33",X"27",X"07",X"0F",X"62",X"07",X"78",X"FD",X"FF",X"FF",X"FF",X"FE", + X"C2",X"05",X"00",X"F0",X"D8",X"C6",X"C1",X"30",X"D0",X"D0",X"C8",X"08",X"00",X"E0",X"E0",X"D0", + X"0F",X"0F",X"3C",X"3D",X"1F",X"1F",X"1F",X"1C",X"E1",X"D9",X"23",X"9E",X"11",X"8D",X"41",X"3F", + X"08",X"48",X"2F",X"9B",X"51",X"10",X"98",X"7F",X"C8",X"E8",X"90",X"90",X"F0",X"F8",X"F4",X"F4", + X"0C",X"0E",X"0D",X"04",X"02",X"00",X"00",X"00",X"12",X"49",X"21",X"99",X"47",X"20",X"3E",X"00", + X"1F",X"0F",X"CE",X"FC",X"FD",X"FE",X"00",X"00",X"E4",X"CC",X"10",X"60",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"40",X"81",X"41",X"21",X"40",X"40",X"80",X"40",X"98",X"04",X"02",X"02",X"81",X"41",X"21",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"08",X"04",X"08",X"08", + X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"00",X"01",X"00",X"00",X"00",X"00", + X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"04",X"08",X"10",X"10",X"20",X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"42",X"42",X"84",X"84",X"82",X"00",X"00",X"00",X"42",X"42",X"21",X"21",X"41",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"08",X"04",X"08",X"08", + X"00",X"00",X"00",X"20",X"10",X"08",X"08",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"00",X"01",X"00",X"00",X"00",X"00", + X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"40",X"81",X"41",X"21",X"40",X"40",X"80",X"40",X"98",X"04",X"02",X"02",X"81",X"41",X"21",X"10", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"08",X"08",X"10",X"08",X"04",X"04",X"04",X"02",X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"84",X"82",X"81",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"41",X"21",X"11",X"80",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"14",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"28", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"08",X"08",X"10",X"20",X"20",X"00",X"00",X"00",X"10",X"10",X"08",X"04",X"04",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"84",X"82",X"81",X"80",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"41",X"21",X"11",X"80",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"08",X"08",X"10",X"08",X"04",X"04",X"04",X"02",X"00",X"00",X"20",X"10",X"10",X"08",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_palette.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_palette.vhd new file mode 100644 index 00000000..58966443 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_palette.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cclimber_palette is +port ( + clk : in std_logic; + addr : in std_logic_vector(5 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cclimber_palette is + type rom is array(0 to 63) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"80",X"F7",X"F7",X"F6",X"00",X"F4",X"01",X"01",X"00",X"31",X"07",X"00",X"00",X"7F",X"66",X"00", + X"00",X"FA",X"F6",X"00",X"00",X"B8",X"00",X"3F",X"00",X"FC",X"B7",X"FA",X"00",X"4E",X"AF",X"00", + X"00",X"00",X"9C",X"7E",X"00",X"00",X"9C",X"07",X"00",X"00",X"00",X"00",X"00",X"FF",X"BE",X"00", + X"00",X"FA",X"76",X"00",X"00",X"87",X"87",X"00",X"00",X"B7",X"6F",X"00",X"00",X"FA",X"FA",X"07"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_program.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_program.vhd new file mode 100644 index 00000000..7c88881b --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_program.vhd @@ -0,0 +1,1302 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cclimber_program is +port ( + clk : in std_logic; + addr : in std_logic_vector(14 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cclimber_program is + type rom is array(0 to 20479) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"08",X"D9",X"ED",X"56",X"C3",X"52",X"00",X"0B",X"F5",X"E5",X"D5",X"C5",X"C3",X"2D",X"04",X"2A", + X"F5",X"E5",X"D5",X"C5",X"C3",X"8A",X"04",X"32",X"8F",X"0B",X"21",X"9F",X"0B",X"06",X"B1",X"36", + X"F5",X"E5",X"D5",X"C5",X"C3",X"3A",X"05",X"0B",X"F5",X"E5",X"D5",X"C5",X"C3",X"5F",X"05",X"5E", + X"22",X"09",X"80",X"C3",X"69",X"05",X"C1",X"0B",X"CD",X"28",X"09",X"CD",X"64",X"09",X"C1",X"CB", + X"40",X"20",X"0D",X"E5",X"21",X"C1",X"0B",X"11",X"3A",X"00",X"B8",X"C3",X"D1",X"02",X"B0",X"E1", + X"06",X"01",X"01",X"00",X"00",X"3A",X"00",X"B8",X"3E",X"05",X"3D",X"20",X"FD",X"10",X"F9",X"0D", + X"20",X"F3",X"C3",X"48",X"00",X"28",X"08",X"D9",X"FD",X"E5",X"DD",X"E5",X"AF",X"32",X"00",X"A0", + X"3A",X"13",X"80",X"FE",X"FF",X"C2",X"EC",X"00",X"21",X"04",X"80",X"3A",X"00",X"B8",X"CB",X"47", + X"28",X"04",X"36",X"01",X"18",X"0F",X"7E",X"36",X"00",X"B7",X"28",X"09",X"2B",X"7E",X"3C",X"3C", + X"FE",X"C8",X"30",X"01",X"77",X"CD",X"25",X"01",X"CD",X"E7",X"47",X"2A",X"09",X"80",X"7C",X"B5", + X"28",X"04",X"2B",X"22",X"09",X"80",X"21",X"11",X"80",X"35",X"3E",X"18",X"86",X"20",X"3D",X"36", + X"00",X"11",X"14",X"80",X"EB",X"CB",X"7E",X"20",X"30",X"23",X"3E",X"05",X"BE",X"20",X"2A",X"13", + X"1A",X"EE",X"01",X"12",X"20",X"15",X"3A",X"16",X"80",X"CB",X"77",X"20",X"07",X"3E",X"12",X"CD", + X"12",X"0D",X"18",X"15",X"3E",X"13",X"CD",X"12",X"0D",X"18",X"0E",X"3A",X"16",X"80",X"CB",X"77", + X"3E",X"02",X"20",X"02",X"3E",X"00",X"CD",X"12",X"0D",X"CD",X"07",X"01",X"21",X"11",X"80",X"3E", + X"01",X"CB",X"46",X"28",X"02",X"3E",X"02",X"32",X"06",X"80",X"3E",X"01",X"32",X"00",X"A0",X"DD", + X"E1",X"FD",X"E1",X"D9",X"08",X"ED",X"45",X"21",X"24",X"24",X"22",X"BB",X"93",X"22",X"BD",X"93", + X"21",X"BD",X"93",X"3A",X"03",X"80",X"0F",X"0E",X"00",X"0C",X"D6",X"0A",X"30",X"FB",X"0D",X"C6", + X"0A",X"77",X"2B",X"71",X"C9",X"06",X"08",X"11",X"80",X"98",X"21",X"47",X"82",X"0E",X"04",X"7E", + X"CB",X"7F",X"20",X"14",X"23",X"B7",X"28",X"07",X"13",X"23",X"0D",X"20",X"FB",X"18",X"12",X"AF", + X"12",X"23",X"13",X"0D",X"20",X"FA",X"18",X"09",X"CB",X"BE",X"23",X"ED",X"A0",X"AF",X"B1",X"20", + X"FA",X"10",X"DA",X"C9",X"E5",X"21",X"47",X"82",X"06",X"08",X"3A",X"00",X"80",X"4F",X"16",X"00", + X"7E",X"E6",X"7F",X"B9",X"20",X"02",X"16",X"01",X"23",X"23",X"23",X"23",X"23",X"10",X"F1",X"E1", + X"7A",X"B7",X"C0",X"7D",X"45",X"21",X"05",X"80",X"86",X"FE",X"09",X"3F",X"D8",X"77",X"21",X"47", + X"82",X"7E",X"B7",X"20",X"07",X"3A",X"00",X"80",X"77",X"10",X"F6",X"C9",X"11",X"05",X"00",X"19", + X"18",X"EF",X"7C",X"C6",X"20",X"67",X"7D",X"C6",X"10",X"6F",X"D5",X"FD",X"E1",X"50",X"59",X"DD", + X"21",X"47",X"82",X"06",X"08",X"3A",X"00",X"80",X"4F",X"DD",X"7E",X"00",X"E6",X"7F",X"B9",X"20", + X"21",X"DD",X"72",X"01",X"14",X"DD",X"73",X"02",X"7C",X"FD",X"86",X"00",X"DD",X"77",X"04",X"FD", + X"23",X"7D",X"FD",X"86",X"00",X"DD",X"77",X"03",X"FD",X"23",X"78",X"FE",X"06",X"30",X"03",X"DD", + X"35",X"03",X"D5",X"11",X"05",X"00",X"DD",X"19",X"D1",X"10",X"CE",X"3E",X"00",X"32",X"00",X"A0", + X"21",X"47",X"82",X"06",X"08",X"11",X"05",X"00",X"3A",X"00",X"80",X"4F",X"7E",X"E6",X"7F",X"B9", + X"20",X"02",X"CB",X"FE",X"19",X"10",X"F5",X"3E",X"01",X"32",X"00",X"A0",X"C9",X"21",X"47",X"82", + X"06",X"08",X"3A",X"00",X"80",X"4F",X"7E",X"E6",X"7F",X"B9",X"20",X"08",X"36",X"00",X"11",X"05", + X"80",X"1A",X"3D",X"12",X"11",X"05",X"00",X"19",X"10",X"EC",X"C9",X"3A",X"23",X"80",X"E6",X"F8", + X"32",X"23",X"80",X"3A",X"14",X"80",X"CB",X"47",X"20",X"20",X"CB",X"7F",X"20",X"35",X"3A",X"16", + X"80",X"CB",X"77",X"20",X"05",X"3A",X"00",X"A8",X"18",X"03",X"3A",X"00",X"A0",X"E6",X"C1",X"07", + X"07",X"47",X"3A",X"23",X"80",X"B0",X"32",X"23",X"80",X"C9",X"2A",X"0B",X"80",X"11",X"0F",X"80", + X"CD",X"B7",X"02",X"22",X"0B",X"80",X"30",X"E9",X"21",X"7C",X"02",X"22",X"0B",X"80",X"EB",X"36", + X"00",X"18",X"E7",X"2A",X"0D",X"80",X"11",X"10",X"80",X"CD",X"B7",X"02",X"22",X"0D",X"80",X"30", + X"D0",X"21",X"85",X"02",X"22",X"0D",X"80",X"EB",X"36",X"00",X"18",X"E7",X"A4",X"F4",X"65",X"F4", + X"F4",X"84",X"F6",X"F4",X"FF",X"F5",X"55",X"F4",X"64",X"72",X"66",X"F6",X"52",X"80",X"F5",X"45", + X"F4",X"F4",X"24",X"86",X"A2",X"F6",X"26",X"F4",X"A4",X"F5",X"F4",X"F4",X"F4",X"86",X"F2",X"82", + X"66",X"F4",X"F5",X"55",X"F4",X"11",X"F4",X"F4",X"F6",X"F4",X"80",X"F4",X"F0",X"F4",X"F0",X"F4", + X"F0",X"F4",X"F0",X"F4",X"F4",X"F4",X"FF",X"1A",X"47",X"3C",X"12",X"7E",X"FE",X"FF",X"37",X"C8", + X"E6",X"F0",X"0F",X"0F",X"0F",X"0F",X"4E",X"B8",X"20",X"03",X"23",X"AF",X"12",X"79",X"E6",X"07", + X"C9",X"AF",X"A7",X"DD",X"21",X"D9",X"02",X"18",X"1C",X"08",X"3C",X"DD",X"21",X"E1",X"02",X"18", + X"14",X"08",X"AF",X"37",X"DD",X"21",X"EA",X"02",X"18",X"0B",X"08",X"3C",X"DD",X"21",X"F2",X"02", + X"18",X"03",X"C3",X"D0",X"03",X"11",X"B6",X"03",X"21",X"1F",X"03",X"28",X"03",X"21",X"33",X"03", + X"38",X"05",X"08",X"1A",X"2F",X"18",X"02",X"08",X"1A",X"FD",X"21",X"14",X"03",X"4F",X"13",X"1A", + X"47",X"13",X"1A",X"E9",X"13",X"1A",X"FE",X"ED",X"28",X"03",X"08",X"18",X"DB",X"DD",X"E9",X"67", + X"2E",X"00",X"3A",X"00",X"B8",X"71",X"2C",X"20",X"FC",X"24",X"10",X"F6",X"1A",X"67",X"79",X"2F", + X"77",X"FD",X"E9",X"67",X"2E",X"00",X"7E",X"2F",X"A9",X"20",X"1F",X"2C",X"3A",X"00",X"B8",X"7E", + X"A9",X"20",X"17",X"1A",X"FE",X"98",X"20",X"0A",X"2C",X"CB",X"6D",X"28",X"04",X"7D",X"C6",X"20", + X"6F",X"2D",X"2C",X"20",X"EA",X"24",X"10",X"E4",X"FD",X"E9",X"4F",X"D9",X"AF",X"37",X"DD",X"21", + X"64",X"03",X"18",X"91",X"21",X"18",X"91",X"D9",X"EB",X"79",X"21",X"6F",X"03",X"18",X"30",X"D9", + X"2D",X"D9",X"7B",X"21",X"78",X"03",X"18",X"27",X"7A",X"21",X"7E",X"03",X"18",X"21",X"D9",X"21", + X"B0",X"03",X"11",X"08",X"91",X"01",X"06",X"00",X"ED",X"B0",X"D9",X"3A",X"00",X"B0",X"CB",X"7F", + X"CA",X"00",X"00",X"3A",X"00",X"B8",X"AF",X"12",X"1A",X"3E",X"FF",X"12",X"1A",X"18",X"EC",X"D9", + X"4F",X"E6",X"0F",X"77",X"2D",X"79",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"77",X"2B",X"D9",X"E9", + X"0B",X"0A",X"0D",X"1B",X"0A",X"16",X"00",X"04",X"80",X"FF",X"01",X"88",X"24",X"04",X"90",X"00", + X"08",X"98",X"ED",X"00",X"0B",X"0A",X"0D",X"1B",X"18",X"16",X"90",X"01",X"0C",X"00",X"ED",X"B0", + X"21",X"00",X"00",X"01",X"00",X"0A",X"11",X"F4",X"03",X"79",X"86",X"4F",X"3A",X"00",X"B8",X"2C", + X"20",X"F7",X"24",X"3E",X"07",X"A4",X"20",X"F1",X"1A",X"B9",X"00",X"00",X"0E",X"00",X"13",X"10", + X"E8",X"C3",X"74",X"05",X"0C",X"6A",X"29",X"F3",X"DC",X"B6",X"FD",X"44",X"63",X"D5",X"F4",X"D9", + X"21",X"C4",X"03",X"11",X"A6",X"90",X"01",X"06",X"00",X"ED",X"B0",X"D9",X"EB",X"21",X"B0",X"90", + X"3E",X"F8",X"A2",X"0F",X"0F",X"0F",X"77",X"79",X"D9",X"21",X"BA",X"90",X"D9",X"21",X"23",X"04", + X"C3",X"9F",X"03",X"00",X"00",X"00",X"00",X"3A",X"00",X"B8",X"1A",X"18",X"FA",X"E6",X"1F",X"5F", + X"21",X"70",X"04",X"06",X"0D",X"BE",X"28",X"07",X"23",X"23",X"10",X"F9",X"37",X"18",X"25",X"23", + X"7E",X"06",X"01",X"B7",X"28",X"01",X"47",X"7B",X"CD",X"AB",X"04",X"CB",X"7E",X"28",X"06",X"1C", + X"10",X"F5",X"37",X"18",X"0F",X"73",X"CB",X"FE",X"23",X"36",X"00",X"01",X"0E",X"00",X"54",X"5D", + X"13",X"ED",X"B0",X"B7",X"C1",X"D1",X"E1",X"C1",X"C9",X"C1",X"D1",X"E1",X"E3",X"7C",X"E1",X"C9", + X"00",X"00",X"01",X"00",X"02",X"00",X"03",X"03",X"06",X"03",X"09",X"03",X"0C",X"00",X"0D",X"00", + X"0E",X"00",X"0F",X"00",X"10",X"03",X"13",X"00",X"14",X"00",X"E6",X"1F",X"5F",X"CD",X"AB",X"04", + X"CB",X"BE",X"CB",X"F6",X"7B",X"D5",X"CD",X"31",X"06",X"D1",X"CB",X"76",X"28",X"F4",X"36",X"00", + X"4B",X"21",X"47",X"82",X"06",X"08",X"CD",X"06",X"02",X"18",X"BE",X"21",X"00",X"B8",X"BE",X"21", + X"00",X"80",X"BE",X"21",X"2F",X"80",X"C8",X"26",X"00",X"D5",X"6F",X"29",X"29",X"29",X"29",X"11", + X"3F",X"80",X"19",X"D1",X"C9",X"C5",X"D5",X"AF",X"ED",X"A0",X"B1",X"20",X"FA",X"3A",X"00",X"B8", + X"11",X"20",X"00",X"E3",X"19",X"EB",X"E1",X"C1",X"10",X"EB",X"C9",X"C5",X"D5",X"AF",X"ED",X"A0", + X"B1",X"20",X"FA",X"3A",X"00",X"B8",X"11",X"10",X"00",X"E3",X"19",X"EB",X"E1",X"C1",X"10",X"EB", + X"C9",X"C5",X"D5",X"12",X"13",X"0D",X"20",X"FB",X"21",X"00",X"B8",X"BE",X"11",X"20",X"00",X"E1", + X"19",X"EB",X"C1",X"10",X"EC",X"C9",X"E5",X"62",X"6B",X"13",X"0B",X"77",X"ED",X"B0",X"E1",X"3A", + X"00",X"B8",X"C9",X"E5",X"EB",X"1E",X"20",X"57",X"7A",X"77",X"16",X"00",X"19",X"57",X"0B",X"78", + X"B1",X"20",X"F5",X"E1",X"3A",X"00",X"B8",X"C9",X"06",X"05",X"1A",X"BE",X"C0",X"23",X"13",X"10", + X"F9",X"C9",X"CB",X"D2",X"CB",X"DA",X"CD",X"F1",X"04",X"C9",X"E6",X"1F",X"06",X"00",X"4F",X"EB", + X"21",X"31",X"82",X"09",X"34",X"06",X"28",X"21",X"B9",X"81",X"7E",X"B7",X"28",X"09",X"23",X"23", + X"23",X"10",X"F7",X"37",X"C3",X"69",X"04",X"71",X"23",X"73",X"23",X"72",X"C3",X"69",X"04",X"E6", + X"1F",X"CD",X"AB",X"04",X"CB",X"F6",X"C3",X"69",X"04",X"2A",X"09",X"80",X"7C",X"B5",X"C8",X"3A", + X"00",X"B8",X"18",X"F5",X"31",X"00",X"84",X"AF",X"32",X"07",X"A0",X"3E",X"07",X"D3",X"08",X"3E", + X"3F",X"D3",X"09",X"11",X"00",X"90",X"3E",X"24",X"CD",X"76",X"08",X"11",X"00",X"9C",X"3E",X"00", + X"CD",X"76",X"08",X"21",X"00",X"80",X"3E",X"00",X"01",X"F0",X"04",X"CD",X"79",X"08",X"11",X"00", + X"98",X"3E",X"00",X"CD",X"76",X"08",X"11",X"00",X"88",X"3E",X"FF",X"CD",X"76",X"08",X"3E",X"3F", + X"32",X"A0",X"81",X"3E",X"FF",X"32",X"00",X"80",X"21",X"7C",X"02",X"22",X"0B",X"80",X"21",X"85", + X"02",X"22",X"0D",X"80",X"21",X"2F",X"80",X"22",X"07",X"80",X"3E",X"81",X"32",X"14",X"80",X"3E", + X"00",X"CF",X"3E",X"01",X"32",X"00",X"A0",X"01",X"10",X"00",X"09",X"EB",X"21",X"00",X"80",X"34", + X"7E",X"FE",X"15",X"20",X"05",X"36",X"00",X"11",X"3F",X"80",X"3A",X"00",X"B8",X"EB",X"CB",X"7E", + X"28",X"E5",X"22",X"07",X"80",X"CB",X"76",X"3A",X"00",X"80",X"C4",X"31",X"06",X"CB",X"76",X"20", + X"D6",X"11",X"2F",X"80",X"01",X"10",X"00",X"ED",X"B0",X"26",X"00",X"3A",X"00",X"80",X"87",X"6F", + X"01",X"63",X"06",X"09",X"5E",X"23",X"56",X"EB",X"01",X"1D",X"06",X"C5",X"E9",X"3A",X"00",X"B8", + X"11",X"2F",X"80",X"2A",X"07",X"80",X"01",X"10",X"00",X"EB",X"ED",X"B0",X"2A",X"07",X"80",X"18", + X"A6",X"E5",X"EB",X"21",X"31",X"82",X"06",X"00",X"4F",X"09",X"7E",X"B7",X"28",X"23",X"35",X"06", + X"28",X"21",X"B9",X"81",X"79",X"BE",X"20",X"14",X"1A",X"E6",X"9F",X"12",X"36",X"00",X"23",X"13", + X"7E",X"36",X"00",X"12",X"23",X"13",X"7E",X"36",X"00",X"12",X"18",X"05",X"23",X"23",X"23",X"10", + X"E4",X"E1",X"C9",X"8D",X"06",X"6D",X"35",X"6F",X"0F",X"3D",X"3D",X"3D",X"3D",X"3D",X"3D",X"6B", + X"42",X"6B",X"42",X"6B",X"42",X"6B",X"42",X"6B",X"42",X"6B",X"42",X"9F",X"34",X"BC",X"33",X"12", + X"33",X"68",X"3F",X"CD",X"44",X"CD",X"44",X"CD",X"44",X"6E",X"46",X"7F",X"0A",X"21",X"32",X"80", + X"CB",X"7E",X"C2",X"26",X"07",X"CB",X"FE",X"21",X"00",X"00",X"22",X"BC",X"93",X"01",X"00",X"12", + X"C5",X"79",X"CD",X"12",X"0D",X"C1",X"0C",X"10",X"F7",X"3E",X"E4",X"11",X"A1",X"90",X"01",X"18", + X"00",X"CD",X"13",X"05",X"3E",X"08",X"11",X"A1",X"90",X"01",X"01",X"18",X"CD",X"32",X"05",X"3E", + X"E4",X"11",X"A3",X"90",X"01",X"18",X"00",X"CD",X"13",X"05",X"3E",X"09",X"11",X"A3",X"90",X"01", + X"01",X"18",X"CD",X"32",X"05",X"3A",X"00",X"B0",X"E6",X"0C",X"0F",X"0F",X"C6",X"03",X"32",X"01", + X"80",X"3A",X"00",X"B0",X"E6",X"03",X"21",X"02",X"80",X"36",X"00",X"FE",X"03",X"28",X"0E",X"36", + X"04",X"FE",X"02",X"28",X"08",X"36",X"01",X"FE",X"01",X"28",X"02",X"36",X"02",X"3E",X"FF",X"32", + X"13",X"80",X"3E",X"81",X"32",X"14",X"80",X"3E",X"00",X"CD",X"12",X"0D",X"3A",X"16",X"80",X"CB", + X"7F",X"28",X"05",X"3E",X"02",X"CD",X"12",X"0D",X"AF",X"32",X"01",X"A0",X"32",X"02",X"A0",X"32", + X"15",X"80",X"3E",X"14",X"CF",X"C9",X"21",X"14",X"80",X"CB",X"7E",X"28",X"33",X"3A",X"03",X"80", + X"21",X"02",X"80",X"BE",X"3E",X"03",X"38",X"28",X"32",X"15",X"80",X"21",X"14",X"80",X"CB",X"BE", + X"21",X"7C",X"02",X"22",X"0B",X"80",X"21",X"85",X"02",X"22",X"0D",X"80",X"21",X"0F",X"80",X"36", + X"00",X"23",X"36",X"00",X"06",X"14",X"3E",X"01",X"D7",X"3C",X"10",X"FC",X"3E",X"14",X"CF",X"C9", + X"3A",X"15",X"80",X"FE",X"05",X"20",X"0D",X"3A",X"00",X"B8",X"3A",X"06",X"80",X"B7",X"28",X"F0", + X"3D",X"32",X"06",X"80",X"21",X"14",X"80",X"7E",X"E6",X"60",X"C8",X"EB",X"21",X"7C",X"02",X"22", + X"0B",X"80",X"21",X"85",X"02",X"22",X"0D",X"80",X"21",X"0F",X"80",X"36",X"00",X"23",X"36",X"00", + X"06",X"14",X"3E",X"01",X"D7",X"3C",X"10",X"FC",X"EB",X"CB",X"7E",X"C2",X"FD",X"06",X"CB",X"76", + X"20",X"16",X"CB",X"AE",X"21",X"17",X"80",X"3A",X"16",X"80",X"CB",X"77",X"28",X"01",X"23",X"7E", + X"C6",X"01",X"27",X"77",X"3E",X"05",X"18",X"80",X"CB",X"B6",X"3A",X"16",X"80",X"21",X"19",X"80", + X"01",X"10",X"20",X"CB",X"77",X"28",X"04",X"01",X"20",X"10",X"23",X"7E",X"B7",X"20",X"1B",X"C5", + X"CD",X"0D",X"08",X"3E",X"21",X"CD",X"12",X"0D",X"21",X"64",X"00",X"F7",X"C1",X"21",X"16",X"80", + X"7E",X"B0",X"77",X"E6",X"30",X"FE",X"30",X"CA",X"8A",X"08",X"21",X"16",X"80",X"7E",X"EE",X"40", + X"47",X"A1",X"20",X"14",X"70",X"78",X"07",X"07",X"E6",X"01",X"21",X"00",X"B0",X"CB",X"66",X"28", + X"01",X"AF",X"32",X"01",X"A0",X"32",X"02",X"A0",X"3E",X"04",X"C3",X"38",X"07",X"3A",X"00",X"B8", + X"21",X"00",X"88",X"11",X"01",X"88",X"01",X"FF",X"00",X"36",X"FF",X"ED",X"B0",X"3A",X"00",X"B8", + X"21",X"00",X"98",X"11",X"01",X"98",X"01",X"1F",X"00",X"36",X"00",X"ED",X"B0",X"3A",X"00",X"B8", + X"3E",X"00",X"11",X"04",X"90",X"01",X"16",X"20",X"CD",X"32",X"05",X"11",X"04",X"90",X"01",X"16", + X"20",X"3E",X"24",X"CD",X"F1",X"04",X"3A",X"00",X"B8",X"3E",X"E4",X"11",X"A1",X"90",X"01",X"18", + X"00",X"CD",X"13",X"05",X"3E",X"08",X"11",X"A1",X"90",X"01",X"01",X"18",X"CD",X"32",X"05",X"3E", + X"E4",X"11",X"A3",X"90",X"01",X"18",X"00",X"CD",X"13",X"05",X"3E",X"09",X"11",X"A3",X"90",X"01", + X"01",X"18",X"CD",X"32",X"05",X"C9",X"01",X"FF",X"03",X"62",X"6B",X"77",X"13",X"ED",X"A0",X"AF", + X"B1",X"20",X"FA",X"B0",X"C8",X"3A",X"00",X"B8",X"18",X"F3",X"CD",X"0D",X"08",X"AF",X"32",X"01", + X"A0",X"32",X"02",X"A0",X"21",X"2B",X"80",X"7E",X"B7",X"CA",X"2A",X"09",X"32",X"39",X"80",X"11", + X"00",X"A8",X"21",X"34",X"80",X"CB",X"46",X"28",X"03",X"11",X"00",X"A0",X"ED",X"53",X"37",X"80", + X"21",X"00",X"F0",X"22",X"3D",X"80",X"01",X"10",X"00",X"11",X"67",X"91",X"21",X"59",X"0A",X"ED", + X"B0",X"01",X"10",X"00",X"11",X"07",X"92",X"21",X"69",X"0A",X"ED",X"B0",X"3A",X"39",X"80",X"FE", + X"01",X"20",X"05",X"11",X"9B",X"92",X"18",X"0C",X"FE",X"02",X"20",X"05",X"11",X"1B",X"92",X"18", + X"03",X"11",X"9B",X"91",X"ED",X"53",X"35",X"80",X"3E",X"25",X"12",X"21",X"6E",X"92",X"3E",X"0A", + X"77",X"2A",X"3D",X"80",X"23",X"22",X"3D",X"80",X"CD",X"6A",X"09",X"3A",X"34",X"80",X"CB",X"5F", + X"20",X"28",X"2A",X"3D",X"80",X"7C",X"B5",X"28",X"21",X"21",X"3A",X"80",X"34",X"7E",X"E6",X"0F", + X"20",X"DF",X"21",X"34",X"80",X"CB",X"4E",X"20",X"06",X"CB",X"CE",X"3E",X"24",X"18",X"04",X"CB", + X"8E",X"3E",X"25",X"ED",X"5B",X"35",X"80",X"12",X"18",X"C7",X"21",X"34",X"80",X"CB",X"46",X"20", + X"29",X"CB",X"C6",X"01",X"09",X"00",X"21",X"35",X"80",X"11",X"36",X"80",X"36",X"00",X"ED",X"B0", + X"21",X"34",X"80",X"CB",X"9E",X"21",X"00",X"B0",X"CB",X"66",X"20",X"08",X"3E",X"01",X"32",X"01", + X"A0",X"32",X"02",X"A0",X"21",X"2C",X"80",X"C3",X"97",X"08",X"01",X"0A",X"00",X"11",X"35",X"80", + X"21",X"34",X"80",X"36",X"00",X"ED",X"B0",X"C3",X"FD",X"06",X"3A",X"00",X"B8",X"3A",X"03",X"80", + X"B7",X"28",X"07",X"3A",X"00",X"B8",X"E6",X"0C",X"20",X"3D",X"21",X"3B",X"80",X"34",X"20",X"EA", + X"2A",X"37",X"80",X"7E",X"CB",X"47",X"28",X"52",X"21",X"34",X"80",X"CB",X"7E",X"C0",X"CB",X"FE", + X"3A",X"3C",X"80",X"FE",X"1C",X"28",X"20",X"FE",X"1B",X"28",X"28",X"FE",X"1A",X"28",X"08",X"C6", + X"0A",X"2A",X"35",X"80",X"77",X"18",X"06",X"3E",X"26",X"2A",X"35",X"80",X"77",X"23",X"7E",X"FE", + X"28",X"28",X"0A",X"22",X"35",X"80",X"C9",X"3E",X"24",X"2A",X"35",X"80",X"77",X"21",X"34",X"80", + X"CB",X"DE",X"C9",X"2A",X"35",X"80",X"2B",X"7E",X"FE",X"27",X"20",X"03",X"23",X"18",X"03",X"3E", + X"24",X"77",X"22",X"35",X"80",X"23",X"3E",X"24",X"77",X"C9",X"21",X"34",X"80",X"CB",X"BE",X"21", + X"3C",X"80",X"CB",X"77",X"20",X"05",X"CB",X"7F",X"20",X"0B",X"C9",X"34",X"7E",X"FE",X"1D",X"20", + X"0B",X"AF",X"77",X"18",X"07",X"35",X"CB",X"7E",X"28",X"02",X"36",X"1C",X"E5",X"21",X"3B",X"80", + X"E5",X"21",X"01",X"00",X"F7",X"E1",X"34",X"3A",X"00",X"B8",X"7E",X"E6",X"0F",X"20",X"F1",X"36", + X"00",X"3E",X"24",X"11",X"6E",X"92",X"01",X"03",X"00",X"CD",X"06",X"05",X"E1",X"7E",X"FE",X"1B", + X"28",X"13",X"30",X"16",X"FE",X"1A",X"28",X"24",X"C6",X"0A",X"21",X"6E",X"92",X"77",X"21",X"00", + X"F0",X"22",X"3D",X"80",X"C9",X"21",X"79",X"0A",X"18",X"03",X"21",X"7C",X"0A",X"11",X"6E",X"92", + X"01",X"03",X"00",X"ED",X"B0",X"21",X"00",X"F0",X"22",X"3D",X"80",X"C9",X"3E",X"26",X"21",X"6E", + X"92",X"77",X"21",X"00",X"F0",X"22",X"3D",X"80",X"C9",X"17",X"0A",X"16",X"0E",X"24",X"1B",X"0E", + X"10",X"12",X"1C",X"1D",X"0A",X"1D",X"12",X"18",X"17",X"1C",X"0E",X"15",X"0E",X"0C",X"1D",X"24", + X"0C",X"11",X"0A",X"1B",X"0A",X"0C",X"1D",X"0E",X"1B",X"1B",X"1E",X"0B",X"0E",X"17",X"0D",X"21", + X"15",X"80",X"7E",X"FE",X"00",X"C2",X"B2",X"0A",X"CD",X"0D",X"08",X"01",X"19",X"00",X"21",X"15", + X"80",X"11",X"16",X"80",X"36",X"00",X"ED",X"B0",X"21",X"01",X"01",X"22",X"17",X"80",X"3A",X"01", + X"80",X"32",X"19",X"80",X"32",X"1A",X"80",X"CD",X"DC",X"0C",X"21",X"15",X"80",X"34",X"23",X"36", + X"30",X"C9",X"7E",X"FE",X"01",X"C2",X"3A",X"0B",X"21",X"32",X"80",X"7E",X"34",X"B7",X"20",X"4F", + X"CD",X"0D",X"08",X"01",X"13",X"06",X"21",X"5A",X"0C",X"11",X"86",X"90",X"CD",X"C5",X"04",X"01", + X"13",X"06",X"11",X"86",X"90",X"3E",X"12",X"CD",X"32",X"05",X"3E",X"15",X"CD",X"12",X"0D",X"3E", + X"16",X"CD",X"12",X"0D",X"3E",X"17",X"CD",X"12",X"0D",X"01",X"04",X"04",X"21",X"CC",X"0C",X"11", + X"4C",X"92",X"CD",X"C5",X"04",X"11",X"4C",X"92",X"3E",X"10",X"01",X"04",X"04",X"CD",X"32",X"05", + X"3E",X"18",X"CD",X"12",X"0D",X"3E",X"19",X"CD",X"12",X"0D",X"21",X"32",X"00",X"F7",X"C9",X"7E", + X"FE",X"08",X"28",X"1E",X"CB",X"47",X"20",X"0A",X"3E",X"15",X"CD",X"12",X"0D",X"21",X"32",X"00", + X"F7",X"C9",X"3E",X"24",X"11",X"49",X"91",X"01",X"0B",X"00",X"CD",X"06",X"05",X"21",X"32",X"00", + X"F7",X"C9",X"36",X"00",X"21",X"15",X"80",X"36",X"05",X"C9",X"FE",X"03",X"C2",X"BB",X"0B",X"21", + X"32",X"80",X"7E",X"B7",X"20",X"0F",X"36",X"01",X"CD",X"0D",X"08",X"3E",X"1D",X"CD",X"12",X"0D", + X"3E",X"20",X"CD",X"12",X"0D",X"3A",X"03",X"80",X"21",X"02",X"80",X"4E",X"B7",X"CB",X"11",X"B9", + X"30",X"1F",X"3E",X"1E",X"CD",X"12",X"0D",X"3A",X"00",X"B8",X"CB",X"57",X"C8",X"3A",X"03",X"80", + X"21",X"02",X"80",X"96",X"32",X"03",X"80",X"CD",X"07",X"01",X"21",X"16",X"80",X"36",X"10",X"18", + X"22",X"3E",X"1F",X"CD",X"12",X"0D",X"3A",X"00",X"B8",X"CB",X"57",X"20",X"E0",X"CB",X"5F",X"C8", + X"3A",X"03",X"80",X"21",X"02",X"80",X"96",X"96",X"32",X"03",X"80",X"CD",X"07",X"01",X"21",X"16", + X"80",X"36",X"80",X"21",X"2E",X"80",X"36",X"00",X"3A",X"01",X"80",X"67",X"6F",X"22",X"19",X"80", + X"21",X"01",X"01",X"22",X"17",X"80",X"21",X"15",X"80",X"34",X"C9",X"FE",X"04",X"20",X"1B",X"CD", + X"0D",X"08",X"21",X"16",X"80",X"3E",X"1B",X"CB",X"76",X"28",X"02",X"3E",X"1C",X"CD",X"12",X"0D", + X"3E",X"1A",X"CD",X"12",X"0D",X"21",X"15",X"80",X"34",X"C9",X"FE",X"05",X"C0",X"CD",X"DC",X"0C", + X"21",X"C8",X"00",X"F7",X"21",X"14",X"80",X"CB",X"C6",X"CB",X"96",X"23",X"23",X"7E",X"E6",X"F0", + X"77",X"CD",X"0D",X"08",X"21",X"14",X"80",X"CB",X"7E",X"20",X"16",X"3E",X"13",X"CD",X"12",X"0D", + X"3E",X"00",X"CD",X"12",X"0D",X"3A",X"16",X"80",X"CB",X"7F",X"28",X"05",X"3E",X"02",X"CD",X"12", + X"0D",X"AF",X"32",X"A1",X"81",X"32",X"A9",X"81",X"32",X"B1",X"81",X"32",X"9F",X"81",X"CD",X"DC", + X"0C",X"3E",X"07",X"D3",X"08",X"3E",X"3F",X"32",X"A0",X"81",X"D3",X"09",X"3E",X"14",X"D7",X"3E", + X"01",X"CF",X"3E",X"02",X"CF",X"3E",X"0E",X"CF",X"3E",X"0D",X"CF",X"3E",X"0F",X"CF",X"21",X"14", + X"80",X"CB",X"7E",X"C0",X"3E",X"13",X"CD",X"12",X"0D",X"3E",X"00",X"CD",X"12",X"0D",X"3A",X"16", + X"80",X"CB",X"7F",X"C8",X"3E",X"02",X"CD",X"12",X"0D",X"C9",X"91",X"92",X"93",X"94",X"95",X"96", + X"97",X"98",X"99",X"9A",X"9B",X"9C",X"9D",X"9E",X"9F",X"A0",X"A1",X"A2",X"A3",X"A4",X"A5",X"A6", + X"A7",X"A8",X"A9",X"AA",X"AB",X"AC",X"AD",X"AE",X"AF",X"B0",X"B1",X"B2",X"B3",X"B4",X"B5",X"B6", + X"B7",X"B8",X"B9",X"BA",X"BB",X"BC",X"BD",X"BE",X"BF",X"C0",X"C1",X"C2",X"C3",X"C4",X"C5",X"C6", + X"C7",X"C8",X"C9",X"CA",X"CB",X"CC",X"CD",X"CE",X"CF",X"D0",X"D1",X"D2",X"D3",X"D4",X"D5",X"D6", + X"D7",X"D8",X"D9",X"DA",X"DB",X"DC",X"DD",X"DE",X"DF",X"E0",X"E1",X"E2",X"E3",X"E4",X"E5",X"E6", + X"E7",X"E8",X"E9",X"EA",X"EB",X"EC",X"ED",X"EE",X"EF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"75",X"76",X"77",X"78", + X"79",X"7A",X"7B",X"7C",X"7D",X"7E",X"7F",X"80",X"81",X"82",X"83",X"84",X"21",X"5B",X"93",X"36", + X"85",X"11",X"20",X"00",X"19",X"36",X"FF",X"11",X"00",X"0C",X"19",X"36",X"10",X"21",X"5D",X"93", + X"11",X"19",X"80",X"01",X"17",X"80",X"3A",X"16",X"80",X"CB",X"77",X"28",X"02",X"13",X"03",X"1A", + X"77",X"0A",X"21",X"1C",X"93",X"E6",X"F0",X"0F",X"0F",X"0F",X"0F",X"77",X"23",X"0A",X"E6",X"0F", + X"77",X"C9",X"21",X"4F",X"0D",X"16",X"00",X"87",X"5F",X"87",X"83",X"5F",X"19",X"46",X"23",X"4E", + X"C5",X"23",X"4E",X"23",X"46",X"23",X"5E",X"23",X"56",X"60",X"69",X"C1",X"7E",X"FE",X"FF",X"C8", + X"12",X"3A",X"00",X"B8",X"23",X"E5",X"CB",X"D2",X"CB",X"DA",X"EB",X"71",X"EB",X"CB",X"92",X"CB", + X"9A",X"21",X"20",X"00",X"CB",X"40",X"20",X"02",X"2E",X"01",X"19",X"EB",X"E1",X"18",X"DD",X"00", + X"00",X"27",X"0E",X"7B",X"90",X"00",X"00",X"2B",X"0E",X"BA",X"90",X"00",X"00",X"32",X"0E",X"FB", + X"90",X"00",X"00",X"2B",X"0E",X"3A",X"91",X"00",X"00",X"36",X"0E",X"7B",X"91",X"00",X"00",X"3A", + X"0E",X"9A",X"91",X"00",X"00",X"41",X"0E",X"BA",X"91",X"00",X"00",X"48",X"0E",X"FB",X"91",X"00", + X"00",X"3A",X"0E",X"1A",X"92",X"00",X"00",X"41",X"0E",X"3A",X"92",X"00",X"00",X"4C",X"0E",X"7B", + X"92",X"00",X"00",X"3A",X"0E",X"9A",X"92",X"00",X"00",X"41",X"0E",X"BA",X"92",X"00",X"00",X"50", + X"0E",X"FA",X"92",X"00",X"00",X"57",X"0E",X"1B",X"93",X"00",X"00",X"5C",X"0E",X"9A",X"93",X"01", + X"00",X"63",X"0E",X"40",X"91",X"01",X"00",X"6E",X"0E",X"42",X"91",X"00",X"00",X"7A",X"0E",X"7B", + X"90",X"00",X"00",X"7A",X"0E",X"FB",X"90",X"00",X"00",X"7E",X"0E",X"BB",X"93",X"00",X"00",X"83", + X"0E",X"49",X"91",X"00",X"00",X"8F",X"0E",X"85",X"91",X"00",X"00",X"A4",X"0E",X"C5",X"91",X"00", + X"00",X"BA",X"0E",X"29",X"93",X"00",X"00",X"CA",X"0E",X"65",X"93",X"00",X"00",X"E0",X"0E",X"0A", + X"92",X"00",X"00",X"EB",X"0E",X"28",X"91",X"00",X"00",X"FC",X"0E",X"28",X"91",X"00",X"00",X"0D", + X"0F",X"4D",X"91",X"00",X"00",X"12",X"0F",X"87",X"91",X"00",X"00",X"22",X"0F",X"86",X"91",X"00", + X"00",X"34",X"0F",X"C8",X"91",X"00",X"00",X"41",X"0F",X"CB",X"91",X"00",X"00",X"4B",X"0F",X"68", + X"91",X"00",X"00",X"5B",X"0F",X"A6",X"91",X"01",X"1E",X"19",X"FF",X"00",X"00",X"00",X"00",X"00", + X"00",X"FF",X"02",X"1E",X"19",X"FF",X"1D",X"18",X"19",X"FF",X"27",X"11",X"12",X"1B",X"18",X"28", + X"FF",X"00",X"01",X"00",X"00",X"00",X"00",X"FF",X"02",X"17",X"0D",X"FF",X"03",X"1B",X"0D",X"FF", + X"1B",X"18",X"1E",X"17",X"0D",X"1C",X"FF",X"27",X"00",X"01",X"28",X"FF",X"0C",X"1B",X"0E",X"0D", + X"12",X"1D",X"FF",X"20",X"0A",X"1D",X"0E",X"1B",X"24",X"10",X"0A",X"10",X"0E",X"FF",X"10",X"18", + X"0A",X"15",X"24",X"24",X"16",X"0E",X"1D",X"0E",X"1B",X"FF",X"24",X"24",X"24",X"FF",X"0F",X"1B", + X"0E",X"0E",X"FF",X"12",X"17",X"1C",X"0E",X"1B",X"1D",X"24",X"0C",X"18",X"12",X"17",X"FF",X"18", + X"17",X"0E",X"24",X"0C",X"18",X"12",X"17",X"24",X"24",X"18",X"17",X"0E",X"24",X"19",X"15",X"0A", + X"22",X"0E",X"1B",X"FF",X"1D",X"20",X"18",X"24",X"0C",X"18",X"12",X"17",X"1C",X"24",X"1D",X"20", + X"18",X"24",X"19",X"15",X"0A",X"22",X"0E",X"1B",X"1C",X"FF",X"24",X"24",X"24",X"24",X"24",X"24", + X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"FF",X"24",X"24",X"24",X"24",X"24",X"24", + X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"24",X"FF", + X"0B",X"18",X"17",X"24",X"1F",X"18",X"22",X"0A",X"10",X"0E",X"FF",X"19",X"15",X"0A",X"22",X"0E", + X"1B",X"24",X"18",X"17",X"0E",X"24",X"1C",X"1D",X"0A",X"1B",X"1D",X"FF",X"19",X"15",X"0A",X"22", + X"0E",X"1B",X"24",X"1D",X"20",X"18",X"24",X"1C",X"1D",X"0A",X"1B",X"1D",X"FF",X"19",X"1E",X"1C", + X"11",X"FF",X"18",X"17",X"15",X"22",X"24",X"18",X"17",X"0E",X"24",X"19",X"15",X"0A",X"22",X"0E", + X"1B",X"FF",X"18",X"17",X"0E",X"24",X"18",X"1B",X"24",X"1D",X"20",X"18",X"24",X"19",X"15",X"0A", + X"22",X"0E",X"1B",X"FF",X"1C",X"1D",X"0A",X"1B",X"1D",X"24",X"0B",X"1E",X"1D",X"1D",X"18",X"17", + X"FF",X"10",X"0A",X"16",X"0E",X"24",X"18",X"1F",X"0E",X"1B",X"FF",X"0C",X"18",X"17",X"10",X"1B", + X"0A",X"1D",X"1E",X"15",X"0A",X"1D",X"12",X"18",X"17",X"1C",X"FF",X"0C",X"18",X"16",X"19",X"15", + X"0E",X"1D",X"0E",X"0D",X"24",X"22",X"18",X"1E",X"1B",X"24",X"0D",X"1E",X"1D",X"22",X"FF",X"21", + X"32",X"80",X"CB",X"7E",X"C2",X"45",X"10",X"CB",X"FE",X"CB",X"EE",X"21",X"17",X"80",X"3A",X"16", + X"80",X"CB",X"77",X"28",X"01",X"23",X"3A",X"14",X"80",X"CB",X"7F",X"3E",X"0A",X"20",X"07",X"7E", + X"FE",X"0A",X"38",X"02",X"3E",X"0A",X"3D",X"0F",X"E6",X"7F",X"32",X"33",X"80",X"32",X"28",X"80", + X"ED",X"44",X"C6",X"A8",X"32",X"29",X"80",X"3A",X"14",X"80",X"CB",X"7F",X"11",X"BC",X"31",X"20", + X"2A",X"7E",X"0F",X"0F",X"0F",X"0F",X"E6",X"0F",X"28",X"06",X"47",X"AF",X"C6",X"0A",X"10",X"FC", + X"47",X"7E",X"E6",X"0F",X"80",X"FE",X"11",X"38",X"04",X"D6",X"07",X"18",X"F8",X"3D",X"E6",X"0F", + X"6F",X"26",X"00",X"29",X"11",X"0C",X"13",X"19",X"5E",X"23",X"56",X"ED",X"53",X"38",X"80",X"11", + X"04",X"90",X"01",X"16",X"20",X"3E",X"35",X"CD",X"F1",X"04",X"11",X"04",X"9C",X"01",X"16",X"20", + X"3E",X"1E",X"CD",X"F1",X"04",X"ED",X"5F",X"E6",X"03",X"28",X"02",X"EE",X"03",X"07",X"07",X"C6", + X"00",X"32",X"3C",X"80",X"21",X"00",X"00",X"22",X"3D",X"80",X"01",X"00",X"20",X"11",X"04",X"90", + X"21",X"19",X"90",X"C5",X"06",X"00",X"79",X"E6",X"0F",X"4F",X"DD",X"21",X"85",X"12",X"DD",X"09", + X"DD",X"7E",X"00",X"12",X"77",X"CB",X"D4",X"CB",X"DC",X"36",X"5E",X"CB",X"94",X"CB",X"9C",X"EB", + X"CB",X"D4",X"CB",X"DC",X"36",X"1E",X"CB",X"94",X"CB",X"9C",X"01",X"20",X"00",X"09",X"EB",X"09", + X"C1",X"0C",X"10",X"CF",X"C9",X"3A",X"21",X"80",X"21",X"36",X"80",X"96",X"21",X"32",X"80",X"CA", + X"E8",X"10",X"FA",X"71",X"10",X"CB",X"EE",X"CD",X"F8",X"12",X"2A",X"21",X"80",X"11",X"E0",X"00", + X"19",X"22",X"3A",X"80",X"45",X"2A",X"21",X"80",X"B7",X"ED",X"52",X"68",X"38",X"14",X"68",X"18", + X"11",X"CB",X"AE",X"CD",X"F8",X"12",X"2A",X"21",X"80",X"11",X"08",X"00",X"B7",X"ED",X"52",X"22", + X"3A",X"80",X"3A",X"3A",X"80",X"E6",X"07",X"20",X"5F",X"26",X"00",X"CD",X"46",X"46",X"ED",X"53", + X"34",X"80",X"01",X"16",X"00",X"3E",X"35",X"CD",X"06",X"05",X"ED",X"5B",X"34",X"80",X"01",X"16", + X"01",X"3E",X"1E",X"CD",X"32",X"05",X"16",X"00",X"3A",X"3A",X"80",X"E6",X"78",X"0F",X"0F",X"0F", + X"5F",X"21",X"85",X"12",X"19",X"4E",X"2A",X"34",X"80",X"3A",X"33",X"80",X"B7",X"47",X"28",X"05", + X"36",X"34",X"23",X"10",X"FB",X"71",X"C5",X"11",X"15",X"0C",X"2A",X"34",X"80",X"19",X"EB",X"2A", + X"34",X"80",X"01",X"15",X"00",X"09",X"C1",X"3A",X"33",X"80",X"B7",X"28",X"07",X"47",X"36",X"34", + X"2B",X"1B",X"10",X"FA",X"71",X"EB",X"36",X"5E",X"21",X"30",X"80",X"34",X"3E",X"03",X"A6",X"20", + X"32",X"3A",X"1F",X"80",X"6F",X"3A",X"33",X"80",X"07",X"07",X"07",X"D6",X"06",X"67",X"01",X"08", + X"20",X"C5",X"CD",X"D0",X"3E",X"C1",X"38",X"16",X"3A",X"33",X"80",X"ED",X"44",X"C6",X"15",X"07", + X"07",X"07",X"C6",X"06",X"67",X"3A",X"1F",X"80",X"6F",X"CD",X"D0",X"3E",X"30",X"05",X"21",X"16", + X"80",X"CB",X"DE",X"21",X"36",X"80",X"3A",X"21",X"80",X"BE",X"C8",X"77",X"2A",X"3D",X"80",X"ED", + X"5B",X"3A",X"80",X"B7",X"ED",X"52",X"30",X"04",X"ED",X"53",X"3D",X"80",X"3A",X"3A",X"80",X"E6", + X"07",X"C0",X"21",X"32",X"80",X"CB",X"66",X"C2",X"DB",X"11",X"CD",X"95",X"12",X"11",X"C0",X"0E", + X"2A",X"21",X"80",X"B7",X"ED",X"52",X"38",X"0D",X"21",X"32",X"80",X"CB",X"E6",X"21",X"14",X"80", + X"CB",X"D6",X"C3",X"DB",X"11",X"CD",X"C2",X"12",X"D8",X"DD",X"7E",X"01",X"E6",X"F8",X"0F",X"0F", + X"0F",X"FE",X"00",X"20",X"2C",X"DD",X"7E",X"02",X"E6",X"1F",X"5F",X"16",X"00",X"2A",X"34",X"80", + X"19",X"DD",X"7E",X"02",X"E6",X"E0",X"07",X"07",X"07",X"47",X"3A",X"3C",X"80",X"57",X"3A",X"3A", + X"80",X"CB",X"5F",X"20",X"02",X"14",X"14",X"7A",X"77",X"23",X"3C",X"77",X"23",X"10",X"F8",X"18", + X"C4",X"2A",X"3D",X"80",X"ED",X"5B",X"3A",X"80",X"B7",X"ED",X"52",X"28",X"02",X"30",X"B6",X"21", + X"32",X"80",X"CB",X"6E",X"28",X"AF",X"21",X"3A",X"80",X"CB",X"5E",X"20",X"A8",X"FE",X"13",X"20", + X"07",X"21",X"16",X"80",X"CB",X"56",X"20",X"9D",X"CF",X"38",X"9A",X"2E",X"E0",X"F5",X"DD",X"7E", + X"02",X"E6",X"1F",X"07",X"07",X"07",X"67",X"F1",X"E7",X"18",X"8A",X"2A",X"21",X"80",X"11",X"C0", + X"0E",X"B7",X"ED",X"52",X"3E",X"F8",X"A5",X"0F",X"0F",X"FE",X"10",X"D0",X"6F",X"11",X"1D",X"12", + X"19",X"5E",X"23",X"56",X"2A",X"34",X"80",X"06",X"0B",X"1A",X"77",X"13",X"23",X"10",X"FA",X"06", + X"0B",X"1B",X"1A",X"77",X"23",X"10",X"FA",X"11",X"00",X"0C",X"2A",X"34",X"80",X"19",X"06",X"0B", + X"36",X"1E",X"23",X"10",X"FB",X"06",X"0B",X"36",X"5E",X"23",X"10",X"FB",X"C9",X"2D",X"12",X"38", + X"12",X"43",X"12",X"4E",X"12",X"59",X"12",X"64",X"12",X"6F",X"12",X"7A",X"12",X"3A",X"35",X"35", + X"35",X"35",X"41",X"4F",X"3F",X"39",X"38",X"38",X"3A",X"35",X"41",X"4F",X"3F",X"3A",X"3A",X"3A", + X"3B",X"3A",X"3A",X"3A",X"46",X"3D",X"3A",X"3A",X"3A",X"3A",X"3A",X"3C",X"3A",X"3A",X"3A",X"3A", + X"3E",X"3A",X"3A",X"3A",X"44",X"43",X"42",X"38",X"38",X"3D",X"3A",X"4D",X"44",X"43",X"42",X"3A", + X"3A",X"3A",X"3A",X"3A",X"3E",X"3A",X"47",X"3A",X"3A",X"3A",X"4E",X"40",X"50",X"48",X"48",X"4D", + X"47",X"3A",X"3A",X"4A",X"49",X"35",X"35",X"35",X"35",X"35",X"35",X"35",X"35",X"35",X"35",X"35", + X"35",X"35",X"35",X"35",X"35",X"2C",X"2D",X"2E",X"2F",X"2F",X"30",X"31",X"32",X"32",X"2C",X"2D", + X"31",X"32",X"33",X"30",X"31",X"3A",X"00",X"B8",X"01",X"FD",X"FF",X"ED",X"5B",X"3A",X"80",X"CB", + X"9B",X"DD",X"2A",X"38",X"80",X"DD",X"7E",X"01",X"E6",X"07",X"67",X"DD",X"6E",X"00",X"29",X"29", + X"29",X"7C",X"B5",X"C8",X"ED",X"52",X"D8",X"DD",X"09",X"DD",X"22",X"38",X"80",X"3A",X"00",X"B8", + X"18",X"E3",X"3A",X"00",X"B8",X"01",X"03",X"00",X"ED",X"5B",X"3A",X"80",X"CB",X"9B",X"DD",X"2A", + X"38",X"80",X"DD",X"7E",X"01",X"E6",X"07",X"67",X"DD",X"6E",X"00",X"29",X"29",X"29",X"B7",X"ED", + X"52",X"28",X"0D",X"3F",X"D8",X"DD",X"09",X"DD",X"22",X"38",X"80",X"3A",X"00",X"B8",X"18",X"E2", + X"2A",X"38",X"80",X"09",X"22",X"38",X"80",X"C9",X"ED",X"44",X"4F",X"3A",X"37",X"80",X"81",X"32", + X"37",X"80",X"06",X"16",X"21",X"04",X"98",X"77",X"23",X"10",X"FC",X"C9",X"2C",X"13",X"E2",X"14", + X"E9",X"16",X"E1",X"18",X"D0",X"1A",X"07",X"1D",X"FC",X"1E",X"B5",X"20",X"E0",X"22",X"B4",X"24", + X"2B",X"26",X"5F",X"28",X"87",X"2A",X"2E",X"2C",X"C9",X"2D",X"D3",X"2F",X"00",X"00",X"00",X"20", + X"00",X"42",X"20",X"00",X"2A",X"20",X"00",X"32",X"22",X"00",X"6C",X"26",X"00",X"26",X"28",X"00", + X"64",X"36",X"00",X"24",X"3C",X"80",X"0C",X"42",X"80",X"03",X"42",X"00",X"27",X"44",X"00",X"47", + X"44",X"48",X"10",X"4C",X"00",X"51",X"4E",X"00",X"6F",X"50",X"00",X"31",X"58",X"30",X"03",X"5C", + X"00",X"48",X"62",X"00",X"22",X"64",X"00",X"41",X"66",X"00",X"41",X"66",X"98",X"0E",X"66",X"80", + X"12",X"70",X"00",X"23",X"7A",X"48",X"08",X"7A",X"80",X"0B",X"7A",X"00",X"4F",X"7C",X"00",X"4F", + X"7E",X"00",X"31",X"80",X"00",X"33",X"86",X"00",X"22",X"8A",X"00",X"2D",X"92",X"00",X"51",X"94", + X"00",X"33",X"98",X"00",X"25",X"98",X"80",X"0A",X"9C",X"48",X"0C",X"A2",X"00",X"45",X"A2",X"00", + X"2B",X"A8",X"80",X"12",X"AA",X"00",X"21",X"AC",X"00",X"21",X"AC",X"00",X"30",X"AE",X"00",X"4E", + X"B6",X"30",X"05",X"B8",X"00",X"29",X"BE",X"00",X"23",X"C0",X"00",X"23",X"C2",X"80",X"0E",X"C6", + X"00",X"6C",X"C8",X"00",X"8A",X"CA",X"00",X"6C",X"CC",X"00",X"2E",X"DA",X"00",X"51",X"DC",X"80", + X"0A",X"DE",X"00",X"25",X"E0",X"00",X"27",X"E2",X"00",X"29",X"E2",X"60",X"02",X"F2",X"00",X"22", + X"F2",X"48",X"11",X"F8",X"00",X"2B",X"FA",X"00",X"2D",X"FA",X"00",X"33",X"FC",X"98",X"06",X"FC", + X"00",X"33",X"06",X"01",X"24",X"0E",X"81",X"11",X"10",X"01",X"24",X"12",X"01",X"44",X"14",X"01", + X"44",X"1A",X"01",X"27",X"1A",X"01",X"4C",X"1C",X"01",X"2E",X"1E",X"61",X"0C",X"26",X"01",X"27", + X"2E",X"01",X"22",X"2E",X"01",X"51",X"2E",X"81",X"0A",X"30",X"01",X"33",X"34",X"01",X"25",X"36", + X"01",X"25",X"38",X"01",X"2D",X"3A",X"01",X"2F",X"48",X"01",X"27",X"48",X"81",X"12",X"4A",X"01", + X"27",X"4C",X"01",X"29",X"4C",X"01",X"30",X"4E",X"01",X"29",X"4E",X"01",X"30",X"50",X"01",X"27", + X"50",X"31",X"13",X"56",X"01",X"21",X"5A",X"01",X"2E",X"5C",X"01",X"6C",X"5E",X"01",X"6C",X"60", + X"99",X"04",X"60",X"01",X"2E",X"68",X"01",X"33",X"6A",X"01",X"45",X"6A",X"01",X"33",X"6C",X"01", + X"45",X"6E",X"01",X"65",X"70",X"01",X"67",X"72",X"01",X"49",X"74",X"61",X"0F",X"78",X"01",X"21", + X"7A",X"01",X"41",X"7A",X"01",X"2F",X"7C",X"01",X"4D",X"7E",X"01",X"2D",X"7E",X"81",X"07",X"82", + X"01",X"23",X"8A",X"01",X"2A",X"8A",X"31",X"0E",X"8A",X"01",X"33",X"92",X"99",X"0B",X"94",X"01", + X"25",X"9C",X"01",X"21",X"9E",X"49",X"07",X"9E",X"01",X"6F",X"A8",X"01",X"49",X"AC",X"81",X"11", + X"B0",X"01",X"31",X"B2",X"01",X"23",X"B2",X"01",X"30",X"B4",X"01",X"25",X"B4",X"01",X"2E",X"B6", + X"01",X"27",X"B6",X"01",X"2C",X"BA",X"81",X"09",X"BC",X"01",X"33",X"C2",X"01",X"21",X"C2",X"01", + X"26",X"C2",X"01",X"2E",X"C4",X"01",X"28",X"C4",X"01",X"2C",X"C6",X"01",X"2A",X"CC",X"81",X"10", + X"D0",X"99",X"05",X"D4",X"01",X"2F",X"D6",X"01",X"2F",X"DC",X"81",X"05",X"DE",X"31",X"0A",X"FF", + X"FF",X"FF",X"00",X"00",X"00",X"20",X"00",X"42",X"20",X"00",X"4A",X"20",X"00",X"32",X"22",X"00", + X"6C",X"26",X"00",X"26",X"28",X"00",X"64",X"3C",X"00",X"29",X"3E",X"00",X"4D",X"3E",X"30",X"03", + X"40",X"00",X"2F",X"44",X"00",X"22",X"44",X"80",X"07",X"46",X"00",X"42",X"48",X"00",X"42",X"4A", + X"00",X"22",X"52",X"00",X"2E",X"54",X"00",X"2E",X"56",X"00",X"4C",X"56",X"48",X"13",X"58",X"00", + X"2C",X"5C",X"00",X"41",X"5E",X"00",X"41",X"5E",X"80",X"07",X"66",X"00",X"48",X"68",X"00",X"46", + X"6A",X"00",X"46",X"70",X"00",X"2F",X"72",X"00",X"4D",X"74",X"98",X"04",X"74",X"00",X"2D",X"80", + X"80",X"02",X"88",X"00",X"23",X"8A",X"00",X"43",X"8A",X"30",X"0C",X"8C",X"00",X"63",X"8E",X"00", + X"43",X"90",X"00",X"23",X"96",X"00",X"2A",X"98",X"00",X"68",X"9A",X"00",X"68",X"9C",X"00",X"2A", + X"9E",X"80",X"13",X"A0",X"98",X"11",X"A8",X"60",X"0D",X"AC",X"00",X"29",X"AE",X"00",X"2F",X"B0", + X"00",X"23",X"B4",X"80",X"0C",X"B4",X"00",X"51",X"B6",X"00",X"21",X"B6",X"00",X"28",X"BA",X"00", + X"2D",X"BE",X"00",X"27",X"C0",X"00",X"33",X"C4",X"00",X"23",X"C4",X"00",X"2D",X"CC",X"00",X"24", + X"CE",X"00",X"44",X"D0",X"00",X"64",X"D0",X"00",X"31",X"D2",X"00",X"64",X"D4",X"00",X"46",X"D4", + X"00",X"31",X"D6",X"00",X"28",X"DA",X"00",X"21",X"DE",X"00",X"2B",X"E0",X"00",X"4B",X"E2",X"30", + X"11",X"EA",X"00",X"25",X"EA",X"80",X"10",X"EC",X"00",X"63",X"EE",X"00",X"63",X"F0",X"00",X"63", + X"F2",X"00",X"26",X"F8",X"00",X"33",X"FA",X"00",X"6F",X"FC",X"80",X"09",X"FC",X"00",X"8D",X"FE", + X"00",X"8D",X"00",X"01",X"6F",X"02",X"01",X"26",X"0C",X"01",X"26",X"0E",X"01",X"45",X"0E",X"01", + X"2F",X"10",X"01",X"64",X"10",X"81",X"0B",X"10",X"01",X"4E",X"12",X"61",X"01",X"12",X"01",X"45", + X"12",X"01",X"2F",X"14",X"01",X"26",X"1A",X"01",X"21",X"1E",X"01",X"2D",X"20",X"01",X"69",X"22", + X"01",X"49",X"22",X"99",X"02",X"24",X"01",X"2A",X"2A",X"81",X"13",X"2E",X"01",X"2E",X"30",X"01", + X"4D",X"32",X"01",X"2E",X"36",X"01",X"25",X"38",X"61",X"11",X"3A",X"01",X"63",X"3C",X"01",X"64", + X"3C",X"81",X"13",X"3E",X"01",X"46",X"42",X"31",X"0D",X"48",X"01",X"29",X"4A",X"01",X"2A",X"4C", + X"01",X"2B",X"4E",X"01",X"2C",X"4E",X"01",X"33",X"54",X"81",X"03",X"58",X"01",X"64",X"5A",X"01", + X"65",X"5C",X"01",X"66",X"5C",X"49",X"0F",X"62",X"01",X"21",X"64",X"01",X"22",X"6C",X"01",X"26", + X"6C",X"01",X"2D",X"6E",X"01",X"25",X"6E",X"01",X"2E",X"70",X"01",X"44",X"70",X"01",X"2F",X"70", + X"81",X"09",X"72",X"01",X"25",X"7C",X"01",X"29",X"7E",X"01",X"67",X"7E",X"81",X"11",X"80",X"01", + X"24",X"82",X"01",X"25",X"84",X"01",X"26",X"86",X"01",X"87",X"8C",X"01",X"21",X"90",X"99",X"0F", + X"94",X"01",X"45",X"9E",X"01",X"41",X"9E",X"61",X"10",X"9E",X"01",X"33",X"A8",X"01",X"2A",X"AA", + X"01",X"2A",X"AC",X"01",X"2C",X"AE",X"01",X"2E",X"B0",X"01",X"2E",X"B0",X"81",X"12",X"B2",X"61", + X"09",X"B2",X"01",X"2E",X"B4",X"01",X"2E",X"B6",X"01",X"25",X"B6",X"01",X"2F",X"B8",X"01",X"30", + X"BA",X"01",X"30",X"BC",X"01",X"21",X"BC",X"61",X"05",X"BC",X"01",X"31",X"BE",X"01",X"31",X"C0", + X"01",X"31",X"C2",X"61",X"0A",X"C2",X"01",X"31",X"C4",X"01",X"31",X"C6",X"99",X"05",X"C6",X"01", + X"31",X"CE",X"01",X"21",X"CE",X"01",X"33",X"D0",X"01",X"49",X"D2",X"31",X"05",X"D4",X"01",X"30", + X"D8",X"01",X"69",X"DA",X"01",X"41",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"20",X"00",X"42",X"20", + X"00",X"2A",X"20",X"00",X"32",X"22",X"00",X"6C",X"26",X"00",X"26",X"28",X"00",X"64",X"32",X"00", + X"49",X"34",X"00",X"49",X"3A",X"00",X"31",X"3A",X"60",X"0E",X"3C",X"00",X"50",X"3E",X"00",X"31", + X"46",X"80",X"0B",X"4E",X"80",X"03",X"4E",X"00",X"2A",X"50",X"00",X"68",X"52",X"00",X"68",X"54", + X"00",X"2A",X"56",X"30",X"03",X"5C",X"00",X"42",X"5E",X"00",X"62",X"60",X"00",X"42",X"62",X"00", + X"22",X"64",X"00",X"22",X"64",X"00",X"6D",X"66",X"00",X"6D",X"6E",X"00",X"49",X"70",X"00",X"48", + X"72",X"00",X"29",X"76",X"30",X"10",X"7A",X"00",X"25",X"7C",X"00",X"24",X"7E",X"00",X"43",X"7E", + X"80",X"12",X"80",X"00",X"62",X"82",X"00",X"62",X"84",X"00",X"42",X"84",X"80",X"12",X"86",X"00", + X"22",X"88",X"00",X"29",X"8A",X"00",X"49",X"8C",X"00",X"2B",X"92",X"00",X"50",X"98",X"00",X"49", + X"9A",X"00",X"2A",X"9C",X"00",X"2A",X"9E",X"00",X"2B",X"A2",X"98",X"02",X"A2",X"80",X"0F",X"AA", + X"00",X"4B",X"AA",X"48",X"11",X"AC",X"00",X"69",X"AE",X"00",X"4A",X"B2",X"60",X"02",X"B6",X"00", + X"44",X"B6",X"80",X"08",X"B8",X"00",X"25",X"BE",X"00",X"42",X"C0",X"00",X"62",X"C2",X"00",X"22", + X"C4",X"00",X"23",X"C4",X"80",X"13",X"C6",X"00",X"23",X"CC",X"00",X"49",X"CE",X"30",X"06",X"D4", + X"00",X"32",X"D6",X"00",X"50",X"D8",X"00",X"6E",X"D8",X"80",X"04",X"DA",X"00",X"8C",X"DC",X"00", + X"4F",X"DE",X"00",X"4F",X"E2",X"00",X"22",X"E4",X"00",X"42",X"E6",X"00",X"22",X"EC",X"80",X"10", + X"F8",X"80",X"12",X"FA",X"00",X"29",X"FC",X"00",X"46",X"FC",X"98",X"0E",X"FE",X"00",X"46",X"00", + X"61",X"02",X"00",X"01",X"24",X"0A",X"01",X"6B",X"0C",X"49",X"06",X"0C",X"01",X"6B",X"0E",X"01", + X"6B",X"16",X"81",X"08",X"18",X"01",X"32",X"1A",X"01",X"50",X"1C",X"01",X"46",X"1C",X"01",X"32", + X"1E",X"01",X"46",X"1E",X"01",X"32",X"20",X"01",X"45",X"20",X"01",X"32",X"22",X"01",X"45",X"22", + X"01",X"50",X"24",X"01",X"50",X"26",X"01",X"6E",X"28",X"01",X"50",X"28",X"31",X"0B",X"2A",X"01", + X"32",X"2C",X"01",X"22",X"2E",X"01",X"22",X"2E",X"99",X"0A",X"34",X"81",X"12",X"38",X"01",X"49", + X"3A",X"01",X"49",X"3C",X"01",X"67",X"40",X"61",X"03",X"40",X"01",X"31",X"46",X"01",X"4B",X"48", + X"01",X"4B",X"4A",X"01",X"22",X"4C",X"01",X"42",X"4E",X"01",X"42",X"4E",X"81",X"0B",X"50",X"01", + X"43",X"5C",X"01",X"23",X"5E",X"01",X"42",X"5E",X"01",X"2C",X"60",X"01",X"42",X"60",X"01",X"4B", + X"62",X"01",X"42",X"62",X"01",X"2C",X"64",X"01",X"42",X"64",X"49",X"08",X"68",X"99",X"0E",X"6C", + X"81",X"07",X"6E",X"01",X"27",X"70",X"01",X"46",X"72",X"01",X"27",X"72",X"01",X"50",X"74",X"01", + X"4F",X"74",X"31",X"0B",X"80",X"01",X"82",X"80",X"81",X"0F",X"88",X"81",X"04",X"88",X"01",X"A8", + X"92",X"01",X"82",X"92",X"81",X"0F",X"9A",X"81",X"04",X"9A",X"01",X"A8",X"A2",X"01",X"28",X"A4", + X"99",X"04",X"A8",X"01",X"2C",X"A8",X"01",X"31",X"AC",X"01",X"25",X"B0",X"01",X"30",X"B2",X"01", + X"22",X"B4",X"01",X"29",X"B4",X"01",X"2D",X"BA",X"01",X"2E",X"BC",X"81",X"04",X"BE",X"01",X"2A", + X"BE",X"01",X"32",X"C0",X"49",X"04",X"C6",X"01",X"44",X"CA",X"01",X"2B",X"CE",X"01",X"22",X"CE", + X"81",X"0F",X"D2",X"99",X"0B",X"D8",X"01",X"24",X"D8",X"01",X"28",X"D8",X"01",X"4F",X"FF",X"FF", + X"FF",X"00",X"00",X"00",X"20",X"00",X"42",X"20",X"00",X"2A",X"20",X"00",X"32",X"22",X"00",X"6C", + X"26",X"00",X"26",X"28",X"00",X"64",X"2E",X"00",X"2E",X"30",X"00",X"2D",X"32",X"00",X"2B",X"3C", + X"80",X"0B",X"3C",X"00",X"32",X"3E",X"00",X"50",X"40",X"00",X"50",X"42",X"00",X"46",X"42",X"00", + X"50",X"44",X"00",X"27",X"44",X"00",X"32",X"4A",X"30",X"0E",X"4E",X"80",X"06",X"52",X"00",X"22", + X"54",X"00",X"42",X"56",X"00",X"42",X"58",X"00",X"22",X"58",X"00",X"2B",X"58",X"80",X"12",X"60", + X"98",X"0F",X"64",X"00",X"47",X"66",X"00",X"46",X"68",X"48",X"0C",X"6E",X"00",X"4A",X"70",X"00", + X"4A",X"72",X"00",X"22",X"72",X"00",X"4A",X"74",X"00",X"42",X"76",X"00",X"22",X"76",X"60",X"0F", + X"7A",X"80",X"08",X"7C",X"00",X"4C",X"7E",X"00",X"6A",X"80",X"00",X"4B",X"84",X"00",X"26",X"86", + X"00",X"28",X"90",X"00",X"22",X"90",X"80",X"10",X"96",X"00",X"27",X"96",X"00",X"30",X"98",X"00", + X"27",X"98",X"00",X"31",X"9A",X"00",X"50",X"9C",X"30",X"02",X"9C",X"00",X"4F",X"A0",X"00",X"2B", + X"A2",X"00",X"24",X"A2",X"00",X"4C",X"A8",X"80",X"07",X"AC",X"00",X"42",X"AC",X"98",X"08",X"AE", + X"00",X"24",X"AE",X"48",X"11",X"B4",X"00",X"50",X"B6",X"00",X"50",X"B8",X"00",X"6E",X"B8",X"80", + X"07",X"C0",X"00",X"2B",X"C2",X"00",X"22",X"C4",X"00",X"42",X"C4",X"00",X"32",X"C6",X"00",X"62", + X"C8",X"00",X"82",X"CE",X"00",X"2E",X"D2",X"48",X"08",X"D4",X"00",X"32",X"DC",X"80",X"0B",X"E0", + X"00",X"2B",X"E0",X"60",X"10",X"E2",X"00",X"2B",X"E4",X"00",X"2A",X"E4",X"98",X"10",X"E6",X"00", + X"49",X"E8",X"00",X"48",X"EA",X"00",X"47",X"EC",X"00",X"26",X"FC",X"00",X"22",X"FC",X"00",X"2C", + X"FC",X"80",X"10",X"FE",X"00",X"2C",X"00",X"01",X"4B",X"02",X"01",X"4B",X"04",X"01",X"4B",X"06", + X"61",X"06",X"06",X"01",X"6A",X"08",X"01",X"2B",X"0A",X"01",X"2C",X"0C",X"01",X"2D",X"14",X"81", + X"08",X"18",X"01",X"26",X"1A",X"01",X"64",X"1C",X"01",X"45",X"1C",X"01",X"32",X"1E",X"01",X"32", + X"30",X"01",X"2F",X"30",X"81",X"13",X"32",X"01",X"2E",X"34",X"01",X"4D",X"36",X"01",X"27",X"36", + X"01",X"4D",X"3C",X"01",X"22",X"3E",X"49",X"09",X"48",X"99",X"0B",X"4C",X"01",X"22",X"4E",X"01", + X"42",X"4E",X"81",X"10",X"52",X"01",X"4D",X"54",X"01",X"6D",X"56",X"81",X"07",X"56",X"01",X"8C", + X"58",X"01",X"8C",X"5A",X"01",X"23",X"5A",X"01",X"6E",X"5C",X"01",X"42",X"5E",X"01",X"22",X"64", + X"01",X"28",X"64",X"01",X"32",X"66",X"01",X"29",X"66",X"01",X"32",X"66",X"81",X"0E",X"68",X"01", + X"32",X"6A",X"01",X"32",X"6C",X"01",X"42",X"6C",X"01",X"50",X"6E",X"01",X"42",X"6E",X"01",X"6E", + X"70",X"31",X"0B",X"70",X"01",X"6E",X"72",X"01",X"6E",X"74",X"81",X"06",X"74",X"01",X"50",X"80", + X"01",X"24",X"80",X"49",X"09",X"84",X"01",X"2D",X"88",X"31",X"11",X"8A",X"01",X"27",X"92",X"49", + X"07",X"94",X"01",X"2E",X"9A",X"61",X"02",X"9E",X"01",X"25",X"A0",X"49",X"0D",X"A8",X"01",X"2A", + X"A8",X"61",X"10",X"AC",X"01",X"22",X"B0",X"01",X"2E",X"B2",X"31",X"03",X"B6",X"81",X"0A",X"BC", + X"01",X"25",X"BC",X"49",X"09",X"C0",X"01",X"32",X"C6",X"01",X"22",X"C6",X"01",X"2C",X"C8",X"31", + X"0F",X"D0",X"81",X"07",X"D4",X"01",X"25",X"D6",X"61",X"09",X"D8",X"01",X"2D",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"20",X"00",X"24",X"20",X"00",X"2A",X"20",X"00",X"31",X"22",X"00",X"6C",X"26", + X"00",X"26",X"28",X"00",X"64",X"34",X"00",X"2C",X"36",X"00",X"4A",X"38",X"00",X"68",X"3A",X"00", + X"86",X"3C",X"00",X"86",X"3E",X"00",X"68",X"40",X"00",X"4A",X"40",X"30",X"11",X"42",X"80",X"03", + X"42",X"00",X"2C",X"46",X"00",X"23",X"48",X"00",X"23",X"48",X"98",X"0E",X"54",X"00",X"2D",X"56", + X"00",X"69",X"58",X"00",X"69",X"5A",X"00",X"4B",X"5C",X"00",X"23",X"5E",X"00",X"23",X"60",X"00", + X"23",X"64",X"60",X"0E",X"66",X"00",X"48",X"68",X"00",X"66",X"6A",X"00",X"46",X"6C",X"00",X"46", + X"6C",X"18",X"14",X"6E",X"80",X"10",X"74",X"00",X"31",X"76",X"00",X"4F",X"78",X"00",X"6D",X"7A", + X"00",X"6D",X"7C",X"00",X"6D",X"80",X"00",X"4F",X"82",X"98",X"03",X"82",X"00",X"31",X"86",X"00", + X"2C",X"88",X"00",X"2B",X"8A",X"00",X"2A",X"8C",X"80",X"11",X"90",X"80",X"11",X"92",X"00",X"6A", + X"94",X"00",X"68",X"98",X"30",X"04",X"9C",X"00",X"27",X"9E",X"00",X"28",X"A0",X"00",X"29",X"A2", + X"00",X"2A",X"A6",X"00",X"23",X"A8",X"00",X"23",X"A8",X"80",X"05",X"AA",X"00",X"23",X"AB",X"30", + X"11",X"AE",X"00",X"28",X"B0",X"00",X"27",X"B2",X"00",X"26",X"B2",X"98",X"0D",X"B8",X"80",X"11", + X"C0",X"00",X"23",X"C2",X"00",X"23",X"C4",X"00",X"23",X"C4",X"00",X"29",X"C6",X"00",X"23",X"C6", + X"00",X"2A",X"C8",X"00",X"49",X"CA",X"00",X"4A",X"CE",X"80",X"10",X"DA",X"00",X"31",X"DA",X"48", + X"09",X"DC",X"00",X"4F",X"DE",X"00",X"4F",X"E0",X"00",X"4F",X"E2",X"00",X"4F",X"E4",X"00",X"4F", + X"E6",X"00",X"29",X"E6",X"00",X"4F",X"E8",X"00",X"47",X"E8",X"00",X"4F",X"E9",X"60",X"03",X"EA", + X"00",X"47",X"EC",X"00",X"47",X"EE",X"00",X"67",X"F0",X"00",X"67",X"F2",X"00",X"49",X"F6",X"80", + X"11",X"FC",X"00",X"23",X"FC",X"00",X"30",X"FE",X"00",X"23",X"FE",X"00",X"30",X"00",X"01",X"23", + X"00",X"01",X"31",X"00",X"61",X"0C",X"02",X"01",X"23",X"02",X"01",X"29",X"04",X"01",X"23",X"04", + X"01",X"29",X"06",X"01",X"23",X"06",X"99",X"0E",X"0A",X"31",X"0F",X"10",X"01",X"2B",X"12",X"81", + X"04",X"12",X"01",X"2B",X"14",X"01",X"2B",X"16",X"01",X"2B",X"18",X"01",X"4B",X"1A",X"01",X"4B", + X"1C",X"01",X"4C",X"20",X"49",X"0A",X"22",X"01",X"26",X"24",X"01",X"26",X"26",X"01",X"27",X"28", + X"01",X"28",X"2A",X"01",X"29",X"2A",X"01",X"2F",X"2A",X"01",X"31",X"2E",X"01",X"23",X"3E",X"81", + X"04",X"40",X"01",X"2A",X"42",X"01",X"49",X"44",X"01",X"68",X"46",X"01",X"87",X"48",X"01",X"87", + X"4A",X"01",X"87",X"4C",X"01",X"87",X"4E",X"01",X"87",X"50",X"01",X"87",X"52",X"01",X"68",X"54", + X"01",X"49",X"56",X"01",X"2A",X"58",X"01",X"31",X"58",X"19",X"00",X"5E",X"81",X"04",X"5E",X"01", + X"48",X"60",X"01",X"49",X"62",X"01",X"48",X"62",X"31",X"10",X"64",X"01",X"47",X"66",X"01",X"46", + X"68",X"01",X"27",X"6A",X"01",X"27",X"6A",X"01",X"31",X"6C",X"01",X"27",X"6C",X"01",X"4F",X"6E", + X"01",X"4E",X"70",X"81",X"0A",X"74",X"01",X"23",X"74",X"01",X"29",X"7A",X"99",X"05",X"7A",X"01", + X"2E",X"80",X"99",X"05",X"80",X"61",X"0F",X"88",X"01",X"25",X"8A",X"61",X"0A",X"8A",X"01",X"2E", + X"90",X"01",X"31",X"94",X"01",X"43",X"94",X"31",X"0F",X"9C",X"01",X"2D",X"9E",X"61",X"07",X"A2", + X"01",X"2A",X"A2",X"81",X"0F",X"A8",X"01",X"24",X"A8",X"99",X"09",X"A8",X"01",X"30",X"B2",X"81", + X"05",X"B2",X"01",X"2A",X"B2",X"61",X"0F",X"B6",X"01",X"27",X"BA",X"01",X"24",X"BC",X"49",X"0A", + X"BC",X"01",X"2F",X"C4",X"01",X"2A",X"C6",X"61",X"08",X"CA",X"01",X"24",X"CA",X"81",X"0C",X"CA", + X"01",X"31",X"CE",X"99",X"0C",X"D0",X"61",X"05",X"D8",X"01",X"25",X"D8",X"01",X"29",X"D8",X"01", + X"2E",X"DA",X"01",X"2F",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"20",X"00",X"24",X"20",X"00",X"8A", + X"22",X"00",X"6C",X"26",X"00",X"25",X"28",X"00",X"63",X"2A",X"00",X"43",X"2C",X"00",X"23",X"2E", + X"00",X"31",X"34",X"00",X"25",X"3C",X"00",X"2D",X"3E",X"00",X"2B",X"3E",X"80",X"06",X"42",X"00", + X"2B",X"44",X"60",X"06",X"44",X"00",X"2D",X"46",X"00",X"4F",X"4C",X"00",X"23",X"4C",X"80",X"08", + X"4E",X"48",X"0F",X"50",X"00",X"2A",X"54",X"00",X"2A",X"54",X"80",X"0F",X"58",X"00",X"29",X"5C", + X"80",X"03",X"5C",X"00",X"28",X"60",X"00",X"27",X"60",X"18",X"14",X"62",X"00",X"25",X"64",X"00", + X"23",X"64",X"80",X"0A",X"6A",X"30",X"11",X"6C",X"00",X"2D",X"70",X"00",X"2A",X"74",X"00",X"27", + X"76",X"60",X"0F",X"78",X"00",X"26",X"7C",X"00",X"26",X"7E",X"80",X"0D",X"82",X"00",X"6D",X"84", + X"00",X"6D",X"86",X"60",X"08",X"8C",X"80",X"06",X"8E",X"00",X"2C",X"90",X"30",X"05",X"90",X"00", + X"2E",X"92",X"00",X"30",X"98",X"98",X"05",X"9A",X"80",X"0F",X"9E",X"80",X"05",X"A2",X"00",X"4A", + X"A4",X"00",X"4C",X"A6",X"00",X"4E",X"A8",X"00",X"4F",X"AC",X"18",X"00",X"AE",X"00",X"2A",X"B0", + X"00",X"28",X"B4",X"48",X"05",X"B4",X"00",X"28",X"B6",X"00",X"2A",X"B6",X"80",X"0F",X"B8",X"00", + X"2C",X"BA",X"00",X"2E",X"BC",X"00",X"30",X"BE",X"00",X"23",X"C0",X"00",X"43",X"C2",X"00",X"63", + X"C4",X"00",X"83",X"C6",X"00",X"A3",X"C8",X"00",X"A3",X"C8",X"80",X"11",X"CA",X"00",X"83",X"D0", + X"80",X"0A",X"D0",X"60",X"0F",X"D4",X"00",X"2B",X"D6",X"00",X"2E",X"DA",X"00",X"31",X"DC",X"30", + X"03",X"DC",X"80",X"0A",X"E2",X"00",X"2A",X"E4",X"00",X"2C",X"EA",X"00",X"30",X"EE",X"00",X"29", + X"F0",X"80",X"06",X"F2",X"00",X"26",X"F6",X"00",X"2F",X"F8",X"00",X"23",X"F8",X"80",X"0D",X"FA", + X"00",X"2A",X"FC",X"00",X"2F",X"FE",X"00",X"28",X"00",X"01",X"2A",X"02",X"01",X"2D",X"04",X"01", + X"23",X"06",X"01",X"43",X"06",X"01",X"30",X"08",X"01",X"63",X"0A",X"01",X"43",X"0C",X"01",X"23", + X"0E",X"81",X"0D",X"12",X"61",X"07",X"14",X"01",X"6D",X"1C",X"01",X"29",X"1E",X"01",X"2B",X"20", + X"01",X"83",X"22",X"81",X"0F",X"26",X"49",X"05",X"28",X"01",X"2A",X"2A",X"01",X"28",X"32",X"01", + X"2B",X"34",X"31",X"05",X"34",X"01",X"2D",X"36",X"01",X"30",X"3C",X"81",X"05",X"40",X"01",X"23", + X"42",X"01",X"43",X"44",X"01",X"63",X"46",X"01",X"43",X"4A",X"81",X"03",X"4C",X"01",X"49",X"4C", + X"81",X"11",X"4E",X"01",X"29",X"50",X"01",X"47",X"52",X"01",X"63",X"54",X"01",X"43",X"54",X"19", + X"14",X"56",X"99",X"0B",X"5C",X"01",X"31",X"5E",X"81",X"07",X"5E",X"01",X"4F",X"60",X"01",X"8B", + X"62",X"01",X"A9",X"64",X"01",X"31",X"6C",X"49",X"0F",X"6E",X"81",X"03",X"70",X"01",X"2A",X"72", + X"01",X"28",X"72",X"81",X"10",X"74",X"01",X"26",X"76",X"01",X"25",X"78",X"01",X"23",X"7C",X"01", + X"A9",X"7E",X"01",X"8B",X"84",X"01",X"2D",X"8C",X"01",X"29",X"8C",X"81",X"0F",X"94",X"01",X"25", + X"98",X"01",X"2A",X"98",X"81",X"0F",X"9E",X"01",X"23",X"A2",X"01",X"2F",X"A4",X"31",X"05",X"A6", + X"01",X"2A",X"AC",X"01",X"2D",X"B0",X"81",X"08",X"B2",X"01",X"23",X"B8",X"81",X"07",X"B8",X"01", + X"2F",X"BE",X"01",X"29",X"C2",X"01",X"27",X"C6",X"01",X"27",X"CA",X"01",X"25",X"D4",X"01",X"2A", + X"D8",X"81",X"0F",X"DA",X"01",X"2A",X"DC",X"49",X"09",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"20", + X"00",X"24",X"20",X"00",X"4A",X"22",X"00",X"6C",X"26",X"00",X"26",X"28",X"00",X"64",X"2A",X"00", + X"44",X"30",X"00",X"4D",X"32",X"00",X"2C",X"3E",X"80",X"07",X"42",X"00",X"2A",X"42",X"60",X"0F", + X"44",X"00",X"28",X"48",X"00",X"27",X"4A",X"00",X"24",X"4A",X"48",X"10",X"4E",X"00",X"2A",X"50", + X"80",X"0E",X"52",X"00",X"2A",X"56",X"00",X"2A",X"58",X"00",X"4C",X"5A",X"00",X"30",X"5E",X"00", + X"28",X"60",X"00",X"2A",X"62",X"00",X"2C",X"64",X"00",X"2C",X"66",X"80",X"07",X"66",X"00",X"2C", + X"68",X"00",X"2C",X"6A",X"00",X"2A",X"6C",X"00",X"28",X"6C",X"80",X"0F",X"6E",X"00",X"25",X"74", + X"30",X"05",X"74",X"00",X"2A",X"78",X"00",X"2C",X"7C",X"00",X"2E",X"7E",X"00",X"30",X"80",X"00", + X"26",X"82",X"80",X"09",X"86",X"00",X"2B",X"8A",X"00",X"2D",X"8C",X"00",X"30",X"90",X"00",X"29", + X"96",X"80",X"05",X"98",X"60",X"0A",X"9A",X"00",X"30",X"9E",X"00",X"2B",X"A2",X"80",X"0D",X"A6", + X"00",X"27",X"AA",X"00",X"24",X"AE",X"80",X"07",X"B0",X"00",X"2C",X"B2",X"48",X"08",X"B4",X"00", + X"2E",X"BA",X"00",X"28",X"BC",X"00",X"25",X"C0",X"80",X"0E",X"C2",X"00",X"2A",X"C6",X"00",X"2C", + X"CA",X"00",X"2E",X"CE",X"80",X"05",X"CE",X"00",X"30",X"D4",X"98",X"07",X"DA",X"60",X"10",X"DC", + X"00",X"24",X"DE",X"00",X"84",X"E4",X"00",X"29",X"EA",X"80",X"0F",X"EC",X"00",X"2A",X"F0",X"00", + X"2C",X"F4",X"00",X"4D",X"F6",X"80",X"07",X"FA",X"00",X"28",X"FE",X"00",X"44",X"FE",X"60",X"0D", + X"04",X"01",X"2A",X"04",X"81",X"0F",X"06",X"01",X"2C",X"0A",X"01",X"2F",X"0C",X"81",X"07",X"10", + X"01",X"24",X"10",X"01",X"28",X"12",X"01",X"44",X"14",X"31",X"0F",X"18",X"01",X"2A",X"1A",X"01", + X"6C",X"20",X"01",X"44",X"22",X"81",X"0F",X"24",X"61",X"08",X"26",X"01",X"4B",X"2A",X"81",X"08", + X"2A",X"01",X"30",X"2E",X"01",X"28",X"30",X"49",X"0D",X"32",X"01",X"26",X"34",X"01",X"24",X"36", + X"01",X"2D",X"38",X"01",X"2F",X"3C",X"61",X"0D",X"3E",X"81",X"05",X"3E",X"01",X"2A",X"42",X"01", + X"2A",X"46",X"81",X"06",X"46",X"01",X"2A",X"4A",X"01",X"2A",X"4E",X"01",X"2A",X"4E",X"81",X"0F", + X"52",X"01",X"28",X"52",X"31",X"10",X"54",X"01",X"24",X"54",X"31",X"06",X"58",X"81",X"0F",X"5A", + X"01",X"2B",X"5E",X"01",X"2C",X"60",X"81",X"09",X"62",X"01",X"4E",X"66",X"61",X"05",X"68",X"01", + X"2A",X"6C",X"01",X"2A",X"6E",X"01",X"26",X"74",X"99",X"0C",X"7C",X"01",X"64",X"7E",X"01",X"84", + X"86",X"01",X"29",X"8C",X"01",X"28",X"8E",X"81",X"0C",X"90",X"01",X"26",X"94",X"01",X"24",X"98", + X"01",X"2C",X"9C",X"81",X"0F",X"9E",X"81",X"06",X"A4",X"01",X"24",X"A4",X"49",X"0F",X"AE",X"81", + X"05",X"B2",X"01",X"4D",X"B8",X"61",X"06",X"BA",X"81",X"0D",X"C2",X"99",X"07",X"CA",X"01",X"2A", + X"CC",X"01",X"28",X"CE",X"01",X"26",X"D0",X"01",X"24",X"D8",X"01",X"2A",X"DC",X"01",X"2C",X"DE", + X"01",X"4E",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"20",X"00",X"24",X"20",X"00",X"8A",X"22",X"00", + X"6C",X"26",X"00",X"26",X"28",X"00",X"64",X"2A",X"00",X"44",X"2C",X"00",X"24",X"30",X"00",X"30", + X"32",X"00",X"30",X"34",X"00",X"2E",X"3C",X"00",X"26",X"3E",X"00",X"44",X"40",X"00",X"44",X"40", + X"80",X"0E",X"42",X"00",X"26",X"46",X"00",X"2E",X"48",X"00",X"6C",X"4A",X"00",X"6C",X"4C",X"80", + X"08",X"4C",X"00",X"4E",X"50",X"00",X"26",X"52",X"00",X"44",X"52",X"18",X"14",X"54",X"00",X"44", + X"56",X"00",X"64",X"58",X"00",X"84",X"5A",X"00",X"84",X"5A",X"48",X"0E",X"5C",X"00",X"64",X"5E", + X"00",X"44",X"60",X"00",X"30",X"62",X"00",X"4E",X"64",X"80",X"06",X"64",X"00",X"6C",X"66",X"00", + X"8A",X"68",X"00",X"4E",X"6C",X"00",X"24",X"6E",X"00",X"44",X"70",X"00",X"44",X"72",X"00",X"64", + X"72",X"80",X"0E",X"74",X"00",X"64",X"76",X"00",X"44",X"7C",X"00",X"44",X"7E",X"00",X"44",X"80", + X"00",X"64",X"80",X"48",X"0E",X"82",X"00",X"44",X"86",X"80",X"0E",X"88",X"00",X"2A",X"88",X"18", + X"14",X"8A",X"00",X"2A",X"8C",X"00",X"4A",X"8E",X"00",X"4A",X"90",X"00",X"6A",X"92",X"00",X"4A", + X"94",X"00",X"4A",X"96",X"00",X"6A",X"98",X"00",X"4E",X"9A",X"80",X"06",X"9A",X"00",X"30",X"9E", + X"00",X"24",X"A0",X"00",X"44",X"A2",X"00",X"44",X"A4",X"00",X"64",X"A6",X"00",X"64",X"A6",X"48", + X"0E",X"A8",X"00",X"84",X"AA",X"00",X"64",X"AC",X"00",X"44",X"AE",X"00",X"24",X"B2",X"00",X"6C", + X"B4",X"00",X"8A",X"B6",X"00",X"6C",X"BA",X"80",X"0C",X"BC",X"00",X"2C",X"BE",X"00",X"6A",X"C0", + X"00",X"6A",X"C0",X"18",X"14",X"C2",X"00",X"4C",X"C6",X"80",X"04",X"CC",X"00",X"26",X"CE",X"00", + X"44",X"D0",X"00",X"64",X"D2",X"00",X"66",X"D2",X"30",X"10",X"D4",X"00",X"2A",X"DA",X"00",X"46", + X"DC",X"00",X"48",X"DE",X"18",X"14",X"E0",X"60",X"08",X"E4",X"80",X"0A",X"E6",X"00",X"26",X"E8", + X"00",X"46",X"EA",X"00",X"66",X"EC",X"00",X"84",X"EE",X"00",X"64",X"EE",X"80",X"10",X"F4",X"00", + X"4E",X"F6",X"00",X"6C",X"F8",X"00",X"6C",X"FA",X"00",X"6A",X"FE",X"80",X"06",X"04",X"01",X"4C", + X"06",X"01",X"6C",X"08",X"49",X"06",X"08",X"01",X"4C",X"0E",X"19",X"00",X"12",X"01",X"44",X"14", + X"01",X"A4",X"16",X"01",X"A4",X"18",X"01",X"A4",X"1A",X"01",X"84",X"1C",X"01",X"64",X"1E",X"01", + X"64",X"20",X"01",X"44",X"20",X"81",X"0E",X"22",X"01",X"24",X"26",X"01",X"30",X"28",X"01",X"4E", + X"2A",X"81",X"06",X"2A",X"01",X"6C",X"2C",X"01",X"8A",X"2E",X"01",X"8A",X"30",X"01",X"8A",X"32", + X"01",X"6C",X"36",X"19",X"00",X"3A",X"81",X"08",X"3C",X"01",X"24",X"3E",X"01",X"24",X"40",X"01", + X"44",X"42",X"01",X"64",X"44",X"01",X"64",X"46",X"01",X"64",X"46",X"49",X"0C",X"46",X"81",X"10", + X"48",X"01",X"44",X"4E",X"31",X"06",X"50",X"01",X"4C",X"52",X"01",X"6A",X"54",X"01",X"6A",X"56", + X"01",X"6C",X"5A",X"81",X"08",X"5E",X"01",X"24",X"60",X"01",X"24",X"60",X"61",X"0C",X"62",X"01", + X"44",X"62",X"19",X"14",X"64",X"01",X"44",X"66",X"01",X"64",X"66",X"81",X"10",X"6C",X"99",X"0A", + X"72",X"01",X"44",X"74",X"01",X"64",X"76",X"01",X"64",X"78",X"01",X"44",X"7A",X"19",X"00",X"7A", + X"81",X"0E",X"7E",X"49",X"08",X"82",X"81",X"0F",X"84",X"01",X"2A",X"88",X"01",X"2C",X"8C",X"81", + X"06",X"90",X"01",X"30",X"92",X"01",X"47",X"9A",X"81",X"08",X"9E",X"01",X"2A",X"A0",X"49",X"05", + X"A2",X"01",X"4D",X"A6",X"81",X"08",X"A8",X"01",X"24",X"AC",X"61",X"0D",X"AE",X"99",X"06",X"B2", + X"01",X"4D",X"BA",X"01",X"49",X"BC",X"01",X"44",X"BE",X"81",X"0F",X"C6",X"01",X"2A",X"C8",X"01", + X"2E",X"CA",X"81",X"06",X"D0",X"01",X"64",X"DA",X"01",X"2C",X"DC",X"01",X"30",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"20",X"00",X"6A",X"22",X"00",X"4C",X"26",X"00",X"25",X"28",X"00",X"45",X"2A", + X"00",X"25",X"2C",X"00",X"25",X"2E",X"00",X"2F",X"30",X"00",X"4D",X"32",X"00",X"6B",X"34",X"00", + X"4D",X"36",X"00",X"2F",X"3A",X"00",X"25",X"3C",X"00",X"2B",X"3E",X"80",X"07",X"42",X"00",X"29", + X"44",X"00",X"2A",X"48",X"48",X"07",X"48",X"00",X"2F",X"4E",X"00",X"27",X"50",X"00",X"25",X"50", + X"80",X"0B",X"54",X"00",X"2B",X"56",X"00",X"2D",X"58",X"00",X"2F",X"5E",X"00",X"2A",X"5E",X"80", + X"05",X"64",X"80",X"05",X"66",X"00",X"29",X"6A",X"00",X"27",X"6C",X"60",X"0A",X"6C",X"00",X"2F", + X"70",X"80",X"0D",X"72",X"00",X"28",X"74",X"00",X"2A",X"78",X"00",X"2C",X"7C",X"80",X"08",X"80", + X"00",X"2A",X"82",X"80",X"0F",X"84",X"00",X"28",X"86",X"00",X"2F",X"88",X"00",X"29",X"8C",X"00", + X"2D",X"8E",X"00",X"25",X"90",X"18",X"00",X"94",X"00",X"29",X"94",X"80",X"0D",X"98",X"00",X"28", + X"98",X"18",X"14",X"9A",X"00",X"25",X"9C",X"48",X"0D",X"A2",X"80",X"08",X"A4",X"00",X"2D",X"A6", + X"00",X"25",X"A6",X"00",X"2F",X"A8",X"00",X"45",X"AC",X"60",X"0A",X"B4",X"80",X"08",X"B4",X"00", + X"2B",X"B6",X"00",X"2D",X"B8",X"00",X"2F",X"BA",X"98",X"07",X"C2",X"00",X"2B",X"C4",X"00",X"65", + X"C6",X"00",X"45",X"C8",X"00",X"25",X"CC",X"80",X"08",X"CE",X"00",X"4D",X"D0",X"00",X"2F",X"D2", + X"00",X"28",X"DA",X"00",X"47",X"DA",X"48",X"0D",X"DC",X"00",X"45",X"E2",X"00",X"28",X"E4",X"00", + X"29",X"E6",X"30",X"06",X"E8",X"00",X"4D",X"EC",X"00",X"28",X"F0",X"80",X"0D",X"F2",X"00",X"25", + X"F4",X"00",X"45",X"F4",X"98",X"0B",X"F6",X"00",X"45",X"F8",X"00",X"25",X"FA",X"60",X"0F",X"FE", + X"00",X"29",X"02",X"01",X"2B",X"04",X"81",X"0F",X"06",X"01",X"25",X"06",X"01",X"2C",X"0A",X"81", + X"08",X"0A",X"01",X"2C",X"0E",X"61",X"06",X"10",X"01",X"2F",X"12",X"81",X"0B",X"16",X"01",X"28", + X"18",X"01",X"2A",X"1C",X"01",X"2F",X"1E",X"81",X"06",X"22",X"01",X"2A",X"26",X"01",X"25",X"26", + X"81",X"0E",X"2A",X"01",X"2D",X"2C",X"31",X"08",X"30",X"01",X"2B",X"32",X"01",X"29",X"36",X"01", + X"2F",X"38",X"61",X"09",X"3E",X"01",X"27",X"40",X"01",X"25",X"40",X"81",X"0D",X"44",X"01",X"2C", + X"48",X"81",X"08",X"4C",X"01",X"27",X"4E",X"01",X"2F",X"50",X"01",X"25",X"56",X"01",X"2A",X"58", + X"01",X"68",X"5A",X"01",X"2A",X"5C",X"01",X"68",X"5E",X"01",X"2A",X"60",X"31",X"0D",X"66",X"81", + X"0A",X"66",X"01",X"2D",X"68",X"01",X"2F",X"6C",X"01",X"27",X"6E",X"01",X"25",X"74",X"81",X"07", + X"74",X"01",X"2F",X"78",X"01",X"29",X"7C",X"99",X"0A",X"82",X"01",X"2A",X"88",X"81",X"08",X"8C", + X"01",X"2D",X"90",X"81",X"05",X"94",X"01",X"28",X"94",X"81",X"0D",X"9A",X"81",X"0D",X"9C",X"01", + X"25",X"A0",X"01",X"2D",X"A2",X"81",X"06",X"A6",X"01",X"2A",X"AC",X"01",X"2F",X"AE",X"81",X"07", + X"B6",X"81",X"08",X"B8",X"81",X"0E",X"BC",X"81",X"06",X"C0",X"01",X"2B",X"C6",X"01",X"2F",X"C8", + X"01",X"2F",X"CC",X"01",X"25",X"CC",X"81",X"0B",X"D2",X"01",X"2D",X"D6",X"81",X"08",X"DA",X"01", + X"27",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"20",X"00",X"2A",X"22",X"00",X"4C",X"26",X"00",X"25", + X"28",X"00",X"45",X"30",X"00",X"2A",X"34",X"00",X"25",X"36",X"00",X"2D",X"38",X"00",X"26",X"3A", + X"00",X"2B",X"3E",X"00",X"2F",X"46",X"00",X"2A",X"4C",X"00",X"2E",X"4E",X"60",X"08",X"50",X"00", + X"25",X"52",X"00",X"2F",X"56",X"00",X"28",X"5C",X"00",X"2C",X"60",X"80",X"08",X"62",X"00",X"25", + X"62",X"00",X"2A",X"66",X"00",X"2F",X"6A",X"00",X"29",X"6C",X"00",X"2D",X"70",X"00",X"25",X"74", + X"60",X"0D",X"76",X"00",X"2B",X"78",X"00",X"25",X"7E",X"00",X"28",X"7E",X"00",X"4D",X"84",X"00", + X"25",X"84",X"00",X"2C",X"8E",X"60",X"0D",X"90",X"00",X"2A",X"9A",X"98",X"05",X"A0",X"00",X"2D", + X"A6",X"80",X"0A",X"AC",X"00",X"2D",X"AE",X"00",X"27",X"B4",X"80",X"0D",X"BA",X"00",X"2E",X"BE", + X"80",X"06",X"C2",X"00",X"2A",X"C8",X"80",X"0D",X"CC",X"00",X"28",X"D0",X"00",X"25",X"D2",X"80", + X"07",X"D4",X"00",X"2F",X"D8",X"80",X"0C",X"DC",X"00",X"2B",X"DE",X"80",X"06",X"E4",X"00",X"27", + X"E8",X"80",X"0B",X"EA",X"00",X"4D",X"F0",X"98",X"09",X"F6",X"00",X"27",X"F8",X"00",X"25",X"FA", + X"80",X"0A",X"FA",X"00",X"2F",X"FE",X"00",X"2A",X"00",X"01",X"2A",X"02",X"01",X"2A",X"04",X"01", + X"2A",X"06",X"81",X"06",X"06",X"01",X"2A",X"08",X"01",X"2A",X"0A",X"01",X"2A",X"0C",X"01",X"2A", + X"0C",X"81",X"0E",X"0E",X"01",X"2A",X"10",X"01",X"2A",X"12",X"01",X"68",X"14",X"01",X"2A",X"18", + X"49",X"0A",X"24",X"01",X"2B",X"26",X"01",X"2B",X"2A",X"01",X"2B",X"2C",X"01",X"2A",X"2E",X"01", + X"29",X"30",X"01",X"29",X"30",X"31",X"0E",X"32",X"01",X"27",X"34",X"01",X"25",X"34",X"01",X"2E", + X"3A",X"01",X"2A",X"3C",X"01",X"2A",X"3E",X"01",X"2A",X"40",X"01",X"2B",X"42",X"01",X"2C",X"44", + X"99",X"06",X"4E",X"01",X"2F",X"54",X"01",X"28",X"54",X"49",X"0D",X"56",X"01",X"26",X"60",X"31", + X"09",X"60",X"01",X"2C",X"68",X"01",X"2F",X"6A",X"61",X"05",X"6E",X"31",X"0E",X"70",X"01",X"27", + X"7A",X"01",X"28",X"7A",X"31",X"0F",X"7C",X"01",X"2A",X"80",X"01",X"2A",X"84",X"61",X"0D",X"8A", + X"81",X"07",X"8C",X"01",X"2D",X"92",X"81",X"0E",X"96",X"01",X"28",X"9C",X"31",X"08",X"A4",X"49", + X"0D",X"AA",X"81",X"06",X"AC",X"01",X"2A",X"B0",X"01",X"2C",X"B6",X"01",X"2E",X"BC",X"81",X"0D", + X"BE",X"61",X"07",X"C6",X"01",X"25",X"C8",X"99",X"0A",X"D0",X"01",X"2A",X"D2",X"01",X"2A",X"D4", + X"81",X"08",X"DA",X"01",X"25",X"DC",X"01",X"45",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"20",X"00", + X"6A",X"22",X"00",X"2C",X"26",X"00",X"25",X"28",X"00",X"45",X"2A",X"00",X"45",X"2C",X"00",X"25", + X"30",X"00",X"2F",X"32",X"00",X"2F",X"34",X"00",X"4D",X"3C",X"00",X"45",X"3E",X"00",X"45",X"3E", + X"80",X"0C",X"40",X"00",X"45",X"42",X"00",X"65",X"44",X"48",X"0E",X"44",X"00",X"45",X"4A",X"80", + X"08",X"4C",X"00",X"2F",X"4E",X"00",X"4D",X"50",X"00",X"4D",X"52",X"00",X"6B",X"5A",X"00",X"25", + X"5C",X"00",X"45",X"5C",X"80",X"0E",X"5E",X"00",X"65",X"60",X"00",X"65",X"62",X"00",X"65",X"62", + X"18",X"14",X"64",X"00",X"45",X"64",X"48",X"0C",X"66",X"00",X"25",X"6A",X"00",X"2F",X"6C",X"00", + X"4D",X"6E",X"00",X"6B",X"70",X"00",X"6B",X"74",X"60",X"0C",X"78",X"00",X"29",X"7A",X"00",X"29", + X"7C",X"00",X"47",X"7C",X"80",X"0E",X"7E",X"00",X"45",X"80",X"00",X"45",X"82",X"00",X"25",X"86", + X"00",X"25",X"88",X"48",X"06",X"88",X"00",X"4D",X"8A",X"00",X"4D",X"8C",X"18",X"00",X"8C",X"00", + X"6B",X"8E",X"00",X"6B",X"90",X"00",X"4D",X"92",X"80",X"08",X"92",X"00",X"2F",X"94",X"00",X"2F", + X"98",X"00",X"29",X"9A",X"00",X"49",X"9A",X"80",X"0E",X"9C",X"00",X"49",X"9E",X"00",X"49",X"A0", + X"00",X"69",X"A2",X"00",X"4B",X"A4",X"00",X"4B",X"A6",X"00",X"4D",X"A8",X"80",X"06",X"AC",X"00", + X"25",X"AE",X"00",X"25",X"B0",X"00",X"45",X"B2",X"00",X"45",X"B2",X"30",X"0C",X"B4",X"00",X"25", + X"B4",X"18",X"14",X"B8",X"00",X"2F",X"BA",X"00",X"4D",X"BC",X"00",X"4D",X"BE",X"00",X"4D",X"C0", + X"80",X"08",X"C4",X"00",X"25",X"C6",X"00",X"25",X"C8",X"00",X"45",X"CA",X"00",X"45",X"CC",X"00", + X"45",X"CE",X"00",X"25",X"D2",X"80",X"08",X"D2",X"00",X"2F",X"D6",X"00",X"6B",X"D8",X"00",X"4D", + X"DA",X"30",X"08",X"E0",X"00",X"29",X"E2",X"00",X"49",X"E2",X"80",X"0E",X"E4",X"00",X"49",X"E6", + X"00",X"49",X"E8",X"00",X"49",X"EA",X"00",X"4B",X"EC",X"00",X"4B",X"EE",X"00",X"4D",X"F0",X"80", + X"06",X"F0",X"00",X"2F",X"F4",X"60",X"08",X"F8",X"00",X"25",X"FA",X"00",X"45",X"FC",X"00",X"45", + X"FE",X"00",X"45",X"00",X"01",X"45",X"02",X"01",X"25",X"04",X"81",X"0E",X"08",X"49",X"0E",X"0A", + X"01",X"65",X"0C",X"01",X"65",X"0E",X"01",X"45",X"16",X"01",X"2F",X"16",X"19",X"00",X"18",X"01", + X"6B",X"1A",X"01",X"6B",X"1C",X"01",X"6B",X"1E",X"01",X"4D",X"20",X"01",X"2F",X"22",X"81",X"08", + X"26",X"01",X"25",X"28",X"01",X"45",X"2A",X"01",X"45",X"2C",X"01",X"45",X"2C",X"31",X"0E",X"2E", + X"01",X"45",X"30",X"01",X"65",X"32",X"01",X"65",X"34",X"01",X"45",X"36",X"01",X"25",X"3A",X"81", + X"0E",X"3C",X"99",X"0A",X"40",X"19",X"14",X"44",X"01",X"2F",X"46",X"49",X"06",X"46",X"01",X"4D", + X"48",X"01",X"6B",X"4A",X"01",X"6B",X"4C",X"01",X"89",X"4E",X"01",X"6B",X"50",X"81",X"06",X"50", + X"01",X"4D",X"58",X"01",X"69",X"5A",X"01",X"49",X"5C",X"01",X"49",X"5C",X"81",X"0F",X"5E",X"01", + X"69",X"60",X"01",X"2D",X"64",X"19",X"00",X"64",X"81",X"08",X"66",X"81",X"0E",X"68",X"01",X"25", + X"6A",X"01",X"45",X"6C",X"01",X"45",X"70",X"01",X"2F",X"72",X"01",X"2F",X"74",X"01",X"4D",X"76", + X"01",X"4D",X"76",X"31",X"08",X"78",X"01",X"4D",X"7A",X"01",X"2F",X"7C",X"81",X"0A",X"7C",X"01", + X"25",X"7E",X"01",X"25",X"80",X"19",X"14",X"80",X"01",X"45",X"86",X"61",X"0E",X"88",X"01",X"27", + X"8E",X"01",X"2A",X"92",X"01",X"2A",X"96",X"81",X"0E",X"9C",X"81",X"06",X"9E",X"01",X"2E",X"A2", + X"01",X"2A",X"A8",X"81",X"09",X"AE",X"31",X"0F",X"B0",X"01",X"28",X"B4",X"81",X"0C",X"B8",X"99", + X"0C",X"BC",X"49",X"07",X"C2",X"01",X"2D",X"CA",X"01",X"45",X"CC",X"01",X"25",X"CE",X"81",X"0E", + X"D4",X"01",X"2B",X"D8",X"61",X"06",X"DA",X"01",X"2E",X"DE",X"01",X"25",X"FF",X"FF",X"FF",X"00", + X"00",X"00",X"20",X"00",X"6A",X"22",X"00",X"4C",X"26",X"00",X"25",X"28",X"00",X"45",X"2A",X"00", + X"45",X"2C",X"00",X"25",X"2E",X"00",X"2F",X"30",X"00",X"2F",X"32",X"00",X"4D",X"3A",X"00",X"25", + X"3C",X"00",X"45",X"3E",X"00",X"45",X"40",X"00",X"25",X"42",X"00",X"2F",X"44",X"00",X"4D",X"46", + X"00",X"4D",X"48",X"80",X"08",X"48",X"00",X"2F",X"4C",X"00",X"2C",X"4E",X"00",X"4A",X"50",X"00", + X"6A",X"52",X"00",X"2C",X"54",X"30",X"08",X"58",X"80",X"0E",X"5A",X"00",X"2B",X"5C",X"00",X"49", + X"5E",X"00",X"49",X"60",X"00",X"49",X"62",X"00",X"2B",X"64",X"00",X"4B",X"66",X"00",X"4B",X"68", + X"18",X"00",X"68",X"00",X"4D",X"6A",X"80",X"06",X"6A",X"00",X"4D",X"6E",X"00",X"25",X"6E",X"48", + X"0E",X"70",X"00",X"25",X"72",X"00",X"65",X"74",X"00",X"65",X"76",X"00",X"45",X"78",X"00",X"45", + X"7E",X"18",X"14",X"80",X"00",X"2F",X"82",X"00",X"4D",X"84",X"00",X"6B",X"86",X"00",X"6B",X"88", + X"00",X"4D",X"8A",X"80",X"08",X"8A",X"00",X"2F",X"8E",X"80",X"0E",X"92",X"00",X"2B",X"94",X"00", + X"49",X"96",X"00",X"49",X"98",X"00",X"2B",X"9C",X"30",X"08",X"9E",X"80",X"0E",X"A0",X"00",X"2B", + X"A2",X"00",X"2B",X"A4",X"00",X"4B",X"A6",X"00",X"4B",X"A8",X"00",X"4B",X"AA",X"00",X"4D",X"AC", + X"00",X"4D",X"B0",X"48",X"0E",X"B4",X"80",X"08",X"B6",X"18",X"00",X"B6",X"00",X"29",X"B8",X"00", + X"47",X"BA",X"00",X"47",X"BC",X"00",X"47",X"BE",X"00",X"65",X"C0",X"00",X"45",X"C2",X"60",X"08", + X"C2",X"80",X"0E",X"C6",X"00",X"2F",X"C8",X"00",X"4D",X"CA",X"00",X"4D",X"CC",X"00",X"6B",X"CE", + X"00",X"6B",X"D0",X"00",X"4D",X"D2",X"00",X"2F",X"D4",X"48",X"0A",X"D8",X"00",X"2A",X"DA",X"00", + X"4A",X"DA",X"80",X"0E",X"DC",X"00",X"4A",X"DE",X"00",X"6A",X"E0",X"00",X"6A",X"E4",X"98",X"0C", + X"EE",X"18",X"14",X"F0",X"00",X"27",X"F2",X"00",X"65",X"F4",X"00",X"65",X"F6",X"00",X"65",X"F8", + X"00",X"25",X"FC",X"18",X"00",X"00",X"01",X"2F",X"02",X"81",X"08",X"02",X"01",X"4D",X"04",X"01", + X"4D",X"06",X"01",X"6B",X"08",X"01",X"4D",X"0A",X"01",X"4D",X"0C",X"01",X"2F",X"0E",X"31",X"08", + X"12",X"01",X"25",X"14",X"01",X"45",X"16",X"01",X"65",X"16",X"81",X"0E",X"18",X"01",X"45",X"1E", + X"01",X"2F",X"20",X"01",X"4D",X"22",X"01",X"4D",X"24",X"01",X"6B",X"26",X"01",X"4D",X"28",X"01", + X"4D",X"2A",X"01",X"2F",X"2C",X"49",X"08",X"2C",X"81",X"0A",X"30",X"01",X"29",X"32",X"01",X"49", + X"34",X"01",X"49",X"36",X"19",X"00",X"36",X"01",X"2B",X"38",X"01",X"4B",X"3A",X"01",X"6B",X"3C", + X"01",X"4D",X"3E",X"61",X"2F",X"3E",X"01",X"2F",X"42",X"01",X"25",X"44",X"01",X"45",X"46",X"01", + X"65",X"48",X"01",X"65",X"48",X"81",X"0E",X"4A",X"01",X"45",X"4C",X"01",X"25",X"50",X"49",X"08", + X"54",X"01",X"2F",X"56",X"01",X"4D",X"58",X"81",X"0A",X"58",X"01",X"4D",X"5A",X"01",X"6B",X"5C", + X"01",X"6B",X"5E",X"01",X"4D",X"60",X"01",X"2F",X"66",X"01",X"2D",X"68",X"81",X"06",X"68",X"01", + X"4D",X"6A",X"01",X"4D",X"72",X"01",X"2B",X"74",X"81",X"06",X"74",X"01",X"6B",X"76",X"01",X"4D", + X"7C",X"01",X"25",X"7E",X"01",X"25",X"80",X"01",X"45",X"80",X"81",X"0C",X"84",X"01",X"2B",X"86", + X"01",X"47",X"88",X"01",X"27",X"8A",X"01",X"25",X"8E",X"81",X"0E",X"94",X"99",X"08",X"9C",X"61", + X"0F",X"9E",X"81",X"08",X"A4",X"49",X"0D",X"A8",X"01",X"28",X"AC",X"81",X"0D",X"B0",X"81",X"09", + X"B6",X"01",X"2A",X"B8",X"61",X"07",X"B8",X"01",X"2C",X"BA",X"01",X"2E",X"C0",X"01",X"27",X"C4", + X"81",X"0F",X"C8",X"81",X"07",X"C8",X"49",X"0F",X"CC",X"99",X"08",X"D4",X"01",X"29",X"D6",X"01", + X"25",X"DA",X"81",X"0B",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"6A", + X"22",X"00",X"4C",X"26",X"00",X"25",X"28",X"00",X"45",X"2A",X"00",X"45",X"2C",X"00",X"25",X"32", + X"98",X"0A",X"38",X"00",X"2F",X"3A",X"80",X"06",X"3E",X"00",X"4A",X"46",X"00",X"45",X"48",X"00", + X"45",X"4A",X"00",X"25",X"4A",X"80",X"0D",X"52",X"00",X"2F",X"54",X"30",X"0B",X"58",X"80",X"08", + X"5E",X"00",X"28",X"5E",X"00",X"2D",X"64",X"00",X"25",X"64",X"00",X"2A",X"64",X"00",X"2F",X"6C", + X"00",X"29",X"70",X"00",X"2D",X"72",X"80",X"06",X"7A",X"00",X"25",X"7C",X"48",X"0B",X"80",X"00", + X"27",X"84",X"98",X"0A",X"8C",X"80",X"07",X"90",X"00",X"27",X"92",X"00",X"2F",X"94",X"30",X"0B", + X"9A",X"00",X"25",X"9E",X"00",X"2A",X"A4",X"00",X"68",X"A6",X"00",X"68",X"AE",X"60",X"06",X"AE", + X"00",X"2F",X"B2",X"00",X"29",X"B8",X"00",X"25",X"BA",X"00",X"2D",X"C0",X"00",X"2D",X"C2",X"00", + X"2B",X"C4",X"00",X"29",X"CA",X"00",X"2F",X"CE",X"00",X"29",X"D0",X"00",X"29",X"D2",X"00",X"27", + X"D4",X"00",X"25",X"D6",X"00",X"2F",X"D8",X"00",X"4D",X"DA",X"80",X"08",X"DE",X"00",X"28",X"E4", + X"00",X"2B",X"EA",X"98",X"06",X"EA",X"00",X"2F",X"F0",X"80",X"0B",X"F4",X"00",X"68",X"FC",X"00", + X"2A",X"FC",X"00",X"2F",X"06",X"01",X"25",X"06",X"01",X"2A",X"08",X"81",X"0E",X"10",X"01",X"89", + X"12",X"49",X"06",X"12",X"01",X"6B",X"14",X"01",X"4D",X"16",X"01",X"2F",X"1A",X"01",X"27",X"1C", + X"01",X"47",X"1E",X"01",X"67",X"20",X"01",X"67",X"22",X"01",X"47",X"24",X"01",X"27",X"26",X"61", + X"0E",X"2C",X"99",X"0B",X"30",X"01",X"28",X"34",X"01",X"2F",X"3A",X"01",X"65",X"3C",X"01",X"65", + X"3E",X"01",X"45",X"40",X"01",X"25",X"42",X"81",X"0D",X"48",X"81",X"0B",X"4C",X"01",X"4A",X"4E", + X"31",X"06",X"4E",X"01",X"2C",X"52",X"01",X"2F",X"58",X"01",X"27",X"58",X"01",X"2D",X"5A",X"01", + X"25",X"5A",X"01",X"2F",X"62",X"01",X"68",X"64",X"01",X"2A",X"6C",X"01",X"65",X"70",X"81",X"0B", + X"74",X"01",X"89",X"7A",X"81",X"06",X"7E",X"01",X"29",X"80",X"01",X"48",X"82",X"01",X"28",X"84", + X"01",X"29",X"86",X"01",X"2A",X"88",X"01",X"2B",X"8A",X"01",X"2C",X"8C",X"01",X"2C",X"8E",X"01", + X"2C",X"90",X"01",X"2C",X"90",X"81",X"0F",X"92",X"01",X"27",X"92",X"01",X"2C",X"94",X"01",X"26", + X"94",X"01",X"2D",X"9C",X"01",X"48",X"9C",X"01",X"2F",X"A0",X"99",X"06",X"A6",X"01",X"2C",X"AC", + X"01",X"27",X"B0",X"01",X"2F",X"B2",X"61",X"08",X"B2",X"01",X"4D",X"B4",X"01",X"4D",X"BA",X"01", + X"25",X"BC",X"01",X"45",X"BC",X"01",X"2C",X"BE",X"01",X"45",X"C4",X"01",X"2A",X"C8",X"99",X"0C", + X"CC",X"01",X"45",X"CE",X"01",X"25",X"D0",X"61",X"0A",X"D8",X"01",X"25",X"D8",X"01",X"29",X"DA", + X"81",X"0D",X"DE",X"01",X"49",X"DE",X"01",X"2F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00", + X"00",X"00",X"00",X"00",X"20",X"00",X"6A",X"22",X"00",X"4C",X"26",X"00",X"25",X"26",X"00",X"45", + X"2A",X"00",X"45",X"2C",X"00",X"25",X"30",X"00",X"29",X"32",X"00",X"2A",X"34",X"00",X"2B",X"3C", + X"80",X"07",X"3C",X"00",X"2F",X"40",X"98",X"07",X"48",X"00",X"25",X"4A",X"00",X"2B",X"4C",X"00", + X"2C",X"4E",X"00",X"2D",X"54",X"00",X"26",X"54",X"48",X"0B",X"54",X"00",X"2F",X"56",X"00",X"27", + X"58",X"00",X"28",X"5A",X"00",X"26",X"5C",X"00",X"25",X"62",X"80",X"0C",X"66",X"00",X"68",X"68", + X"00",X"49",X"6A",X"00",X"2A",X"72",X"30",X"0C",X"72",X"00",X"2F",X"74",X"00",X"28",X"76",X"00", + X"29",X"78",X"00",X"2A",X"7A",X"00",X"2B",X"7C",X"00",X"2C",X"7E",X"00",X"26",X"82",X"00",X"2F", + X"86",X"00",X"28",X"8C",X"00",X"2B",X"90",X"00",X"2F",X"92",X"00",X"4D",X"96",X"80",X"08",X"98", + X"00",X"26",X"9A",X"00",X"26",X"9C",X"00",X"25",X"9E",X"80",X"0D",X"A4",X"00",X"46",X"A4",X"80", + X"0D",X"AC",X"80",X"08",X"AE",X"00",X"4C",X"B4",X"80",X"0D",X"B8",X"00",X"2A",X"BE",X"80",X"07", + X"C2",X"00",X"46",X"C4",X"80",X"0D",X"CC",X"00",X"2A",X"CC",X"60",X"0D",X"D0",X"80",X"06",X"D6", + X"00",X"4C",X"DC",X"80",X"08",X"E0",X"00",X"2A",X"E2",X"80",X"0E",X"EA",X"00",X"46",X"F0",X"80", + X"0A",X"F4",X"00",X"2A",X"FC",X"80",X"06",X"FE",X"00",X"4C",X"06",X"81",X"0C",X"08",X"01",X"2A", + X"0E",X"81",X"06",X"12",X"01",X"46",X"12",X"61",X"0D",X"1C",X"01",X"28",X"1C",X"31",X"0C",X"26", + X"49",X"07",X"26",X"01",X"2C",X"2E",X"01",X"2F",X"30",X"01",X"26",X"30",X"31",X"0B",X"38",X"49", + X"07",X"38",X"01",X"2D",X"42",X"31",X"0C",X"44",X"01",X"26",X"4A",X"01",X"2F",X"52",X"01",X"29", + X"52",X"01",X"2E",X"56",X"81",X"06",X"58",X"01",X"27",X"58",X"01",X"2C",X"5E",X"01",X"29",X"5E", + X"01",X"2E",X"62",X"01",X"25",X"66",X"01",X"2D",X"68",X"01",X"29",X"6C",X"01",X"25",X"6E",X"01", + X"45",X"72",X"99",X"0B",X"7A",X"01",X"29",X"7C",X"01",X"29",X"80",X"01",X"29",X"84",X"01",X"29", + X"88",X"01",X"29",X"8A",X"61",X"0C",X"8E",X"01",X"29",X"92",X"01",X"29",X"94",X"61",X"0E",X"96", + X"01",X"29",X"98",X"61",X"06",X"9A",X"01",X"29",X"9E",X"99",X"06",X"A6",X"01",X"27",X"A8",X"81", + X"06",X"AE",X"61",X"0E",X"B0",X"01",X"49",X"B6",X"81",X"0E",X"B8",X"01",X"27",X"B8",X"01",X"2D", + X"BE",X"01",X"2A",X"C0",X"01",X"2A",X"C0",X"81",X"0D",X"C4",X"01",X"25",X"C6",X"01",X"45",X"C6", + X"01",X"2D",X"C8",X"01",X"25",X"C8",X"01",X"2D",X"CA",X"01",X"2C",X"CC",X"01",X"2B",X"D2",X"01", + X"27",X"D4",X"01",X"29",X"D4",X"01",X"2F",X"D6",X"81",X"0C",X"C2",X"01",X"2F",X"DA",X"01",X"27", + X"DA",X"01",X"2C",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"20", + X"00",X"6A",X"22",X"00",X"4C",X"26",X"00",X"25",X"28",X"00",X"45",X"2A",X"00",X"45",X"2C",X"00", + X"25",X"30",X"00",X"2F",X"32",X"00",X"4D",X"34",X"00",X"6B",X"36",X"80",X"06",X"36",X"00",X"89", + X"38",X"00",X"6B",X"3A",X"00",X"4D",X"3C",X"00",X"2F",X"3E",X"00",X"28",X"40",X"00",X"29",X"42", + X"00",X"2A",X"44",X"80",X"0D",X"46",X"00",X"25",X"48",X"00",X"45",X"4E",X"00",X"2A",X"50",X"80", + X"0E",X"52",X"00",X"2A",X"56",X"00",X"2A",X"5C",X"80",X"06",X"5E",X"00",X"2A",X"62",X"00",X"2A", + X"64",X"48",X"06",X"66",X"00",X"2A",X"6A",X"00",X"2C",X"6C",X"00",X"26",X"6E",X"00",X"25",X"76", + X"00",X"48",X"76",X"80",X"0E",X"7A",X"00",X"2A",X"7E",X"00",X"25",X"7E",X"00",X"2A",X"82",X"00", + X"2A",X"8A",X"80",X"06",X"8A",X"00",X"2A",X"8E",X"00",X"2A",X"92",X"00",X"2C",X"94",X"00",X"2F", + X"96",X"80",X"07",X"9A",X"00",X"25",X"9C",X"98",X"07",X"9E",X"60",X"0D",X"A2",X"00",X"2A",X"A4", + X"00",X"4A",X"A4",X"80",X"0F",X"AA",X"00",X"2F",X"AE",X"00",X"25",X"B0",X"00",X"45",X"B2",X"00", + X"25",X"B2",X"00",X"2F",X"B4",X"00",X"4D",X"B6",X"00",X"89",X"B8",X"00",X"6B",X"BA",X"00",X"4D", + X"BC",X"00",X"25",X"BC",X"00",X"2F",X"C2",X"98",X"0A",X"C8",X"00",X"25",X"CA",X"00",X"45",X"CC", + X"00",X"45",X"CE",X"00",X"45",X"CE",X"00",X"2C",X"D0",X"00",X"25",X"D6",X"00",X"2A",X"D6",X"00", + X"2F",X"D8",X"00",X"25",X"DC",X"00",X"45",X"DE",X"00",X"2C",X"E2",X"00",X"2D",X"E6",X"00",X"29", + X"EA",X"00",X"25",X"EA",X"80",X"0B",X"EC",X"00",X"45",X"EE",X"00",X"65",X"F0",X"00",X"65",X"F2", + X"00",X"65",X"F4",X"00",X"65",X"F6",X"00",X"45",X"F6",X"00",X"2F",X"F8",X"00",X"25",X"F8",X"00", + X"4D",X"FA",X"00",X"6B",X"FC",X"00",X"6B",X"FE",X"00",X"6B",X"00",X"01",X"6B",X"02",X"81",X"06", + X"02",X"01",X"4D",X"04",X"01",X"2F",X"06",X"01",X"29",X"08",X"01",X"48",X"0A",X"01",X"48",X"0C", + X"01",X"67",X"0E",X"01",X"67",X"10",X"01",X"67",X"12",X"01",X"48",X"14",X"01",X"29",X"18",X"01", + X"25",X"1A",X"01",X"25",X"1A",X"99",X"0C",X"1C",X"01",X"25",X"1E",X"01",X"45",X"20",X"01",X"45", + X"22",X"01",X"45",X"22",X"49",X"0D",X"24",X"01",X"65",X"26",X"01",X"65",X"28",X"01",X"85",X"2A", + X"01",X"65",X"2C",X"01",X"65",X"2E",X"01",X"45",X"2E",X"01",X"2F",X"30",X"01",X"25",X"30",X"01", + X"4D",X"32",X"01",X"6B",X"34",X"01",X"4D",X"36",X"01",X"2F",X"3A",X"01",X"25",X"3C",X"01",X"45", + X"3C",X"01",X"4D",X"3E",X"01",X"25",X"3E",X"01",X"2F",X"44",X"01",X"26",X"48",X"61",X"0C",X"4E", + X"61",X"07",X"50",X"01",X"2C",X"56",X"61",X"0C",X"5C",X"01",X"28",X"5E",X"61",X"0E",X"62",X"99", + X"09",X"64",X"61",X"06",X"6C",X"61",X"0B",X"6C",X"01",X"2F",X"6E",X"01",X"26",X"74",X"61",X"06", + X"76",X"01",X"2C",X"7C",X"61",X"0E",X"7E",X"01",X"2A",X"82",X"61",X"07",X"88",X"01",X"25",X"88", + X"01",X"2F",X"8A",X"01",X"45",X"8A",X"01",X"4D",X"8C",X"01",X"25",X"8C",X"01",X"2F",X"94",X"81", + X"08",X"98",X"31",X"0D",X"9E",X"49",X"07",X"A6",X"31",X"0B",X"AC",X"01",X"2D",X"AE",X"01",X"25", + X"B2",X"99",X"07",X"B2",X"49",X"0D",X"B8",X"49",X"0B",X"BC",X"01",X"27",X"C0",X"01",X"2F",X"C2", + X"31",X"07",X"C2",X"01",X"4D",X"C4",X"01",X"2F",X"CA",X"01",X"26",X"CA",X"49",X"0D",X"D0",X"61", + X"07",X"D0",X"01",X"2C",X"D6",X"61",X"0B",X"C2",X"01",X"2F",X"D8",X"01",X"25",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"6A",X"22",X"00",X"4C",X"26", + X"00",X"25",X"28",X"00",X"45",X"2A",X"00",X"45",X"2C",X"00",X"25",X"32",X"00",X"2F",X"36",X"00", + X"4D",X"38",X"00",X"29",X"38",X"00",X"2F",X"40",X"98",X"05",X"40",X"00",X"2C",X"42",X"00",X"2D", + X"44",X"00",X"2E",X"46",X"80",X"09",X"46",X"00",X"2F",X"4A",X"00",X"29",X"4C",X"00",X"29",X"4E", + X"00",X"2A",X"4E",X"00",X"2F",X"50",X"00",X"2A",X"54",X"00",X"25",X"56",X"00",X"25",X"58",X"00", + X"2F",X"5A",X"80",X"0A",X"5A",X"00",X"2E",X"5E",X"00",X"28",X"62",X"00",X"2C",X"66",X"98",X"07", + X"6A",X"00",X"2F",X"6E",X"00",X"25",X"74",X"00",X"28",X"7A",X"00",X"25",X"7E",X"00",X"2F",X"80", + X"00",X"28",X"84",X"80",X"0B",X"86",X"00",X"2C",X"88",X"00",X"2A",X"8E",X"00",X"25",X"90",X"00", + X"45",X"90",X"98",X"09",X"90",X"80",X"0F",X"92",X"00",X"25",X"98",X"00",X"2F",X"9C",X"00",X"2B", + X"9E",X"80",X"06",X"A2",X"00",X"28",X"A2",X"00",X"2D",X"A8",X"00",X"25",X"A8",X"00",X"2F",X"AE", + X"00",X"27",X"B2",X"00",X"2C",X"B6",X"00",X"29",X"B8",X"00",X"2F",X"BA",X"48",X"0C",X"BC",X"00", + X"25",X"C4",X"98",X"0C",X"C6",X"00",X"28",X"CC",X"00",X"26",X"CC",X"00",X"2F",X"D0",X"00",X"2A", + X"D6",X"30",X"0F",X"D8",X"00",X"49",X"DC",X"00",X"25",X"DE",X"00",X"2F",X"E0",X"00",X"2F",X"E4", + X"00",X"27",X"E8",X"00",X"2D",X"EC",X"00",X"29",X"EE",X"00",X"2B",X"F2",X"00",X"25",X"F2",X"00", + X"2F",X"F4",X"80",X"0A",X"F8",X"00",X"27",X"FA",X"00",X"2C",X"FE",X"00",X"25",X"FE",X"98",X"09", + X"FE",X"80",X"0F",X"04",X"01",X"2F",X"08",X"01",X"28",X"0C",X"01",X"2C",X"10",X"01",X"25",X"12", + X"49",X"0A",X"14",X"01",X"2F",X"16",X"01",X"27",X"1A",X"61",X"0C",X"20",X"61",X"08",X"26",X"31", + X"0C",X"2A",X"01",X"68",X"30",X"01",X"25",X"30",X"01",X"2F",X"34",X"01",X"2A",X"34",X"81",X"0F", + X"38",X"01",X"25",X"38",X"01",X"2F",X"3E",X"01",X"28",X"3E",X"01",X"2C",X"40",X"81",X"0F",X"44", + X"01",X"25",X"44",X"01",X"2F",X"48",X"81",X"05",X"48",X"01",X"2A",X"4C",X"01",X"25",X"4C",X"01", + X"2F",X"52",X"01",X"28",X"52",X"01",X"2C",X"54",X"81",X"0F",X"58",X"01",X"25",X"58",X"01",X"2F", + X"5C",X"01",X"2A",X"60",X"01",X"25",X"60",X"01",X"2F",X"62",X"81",X"08",X"66",X"01",X"2A",X"6C", + X"01",X"25",X"6C",X"99",X"0B",X"74",X"01",X"25",X"74",X"81",X"09",X"76",X"01",X"45",X"80",X"81", + X"07",X"80",X"01",X"2B",X"84",X"01",X"2B",X"88",X"81",X"06",X"88",X"01",X"2B",X"8C",X"01",X"2B", + X"90",X"01",X"2B",X"94",X"01",X"2B",X"98",X"01",X"2B",X"9C",X"01",X"2B",X"A0",X"01",X"29",X"A4", + X"01",X"26",X"AC",X"61",X"07",X"AE",X"99",X"0A",X"B2",X"01",X"25",X"B4",X"01",X"25",X"B4",X"01", + X"2D",X"B6",X"01",X"45",X"B8",X"01",X"65",X"BA",X"01",X"85",X"BC",X"01",X"65",X"BE",X"01",X"45", + X"BE",X"01",X"2F",X"C0",X"01",X"45",X"C0",X"01",X"4D",X"C2",X"01",X"45",X"C2",X"01",X"2F",X"C4", + X"01",X"45",X"C4",X"01",X"2F",X"C6",X"01",X"45",X"C8",X"01",X"85",X"CA",X"01",X"65",X"CC",X"01", + X"45",X"CC",X"01",X"2F",X"CE",X"01",X"25",X"CE",X"01",X"4D",X"D0",X"01",X"2F",X"D4",X"01",X"2A", + X"D8",X"61",X"07",X"DA",X"01",X"2F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00", + X"00",X"00",X"20",X"00",X"6A",X"22",X"00",X"4C",X"26",X"00",X"25",X"28",X"00",X"45",X"2A",X"00", + X"45",X"2C",X"00",X"25",X"34",X"00",X"2B",X"36",X"00",X"49",X"38",X"00",X"49",X"3A",X"00",X"49", + X"3C",X"00",X"2B",X"3C",X"30",X"0E",X"40",X"00",X"25",X"40",X"80",X"08",X"40",X"00",X"6B",X"42", + X"00",X"25",X"42",X"00",X"4D",X"44",X"00",X"45",X"44",X"00",X"2F",X"46",X"00",X"65",X"46",X"00", + X"2F",X"48",X"00",X"65",X"48",X"00",X"2F",X"4A",X"00",X"45",X"4A",X"80",X"0C",X"4A",X"00",X"2F", + X"4C",X"00",X"25",X"4C",X"00",X"4D",X"4E",X"00",X"25",X"4E",X"00",X"6B",X"50",X"00",X"6B",X"52", + X"00",X"6B",X"54",X"80",X"07",X"54",X"00",X"4D",X"56",X"00",X"2F",X"5A",X"00",X"29",X"5C",X"00", + X"29",X"5E",X"80",X"07",X"5E",X"00",X"29",X"60",X"00",X"2A",X"62",X"00",X"2B",X"64",X"00",X"25", + X"64",X"00",X"2C",X"66",X"00",X"26",X"66",X"00",X"2D",X"68",X"00",X"28",X"68",X"80",X"0B",X"68", + X"00",X"2F",X"6E",X"00",X"2B",X"70",X"00",X"2B",X"72",X"98",X"05",X"72",X"80",X"0E",X"74",X"00", + X"2A",X"78",X"00",X"28",X"78",X"00",X"2F",X"7A",X"00",X"27",X"7A",X"00",X"2E",X"7C",X"80",X"0A", + X"7E",X"00",X"26",X"80",X"00",X"25",X"80",X"00",X"2C",X"82",X"00",X"25",X"84",X"00",X"25",X"84", + X"00",X"2B",X"86",X"00",X"25",X"86",X"80",X"08",X"86",X"00",X"2B",X"8A",X"00",X"2B",X"8C",X"00", + X"25",X"8C",X"00",X"2B",X"8E",X"00",X"2C",X"90",X"00",X"26",X"90",X"80",X"09",X"90",X"00",X"2C", + X"92",X"00",X"4D",X"94",X"00",X"27",X"94",X"00",X"2F",X"98",X"00",X"2A",X"98",X"00",X"2F",X"9A", + X"00",X"2A",X"9A",X"80",X"0C",X"9C",X"00",X"2A",X"9E",X"00",X"2A",X"A0",X"00",X"2A",X"A2",X"00", + X"2A",X"A2",X"80",X"0D",X"AA",X"00",X"25",X"AA",X"00",X"2A",X"AC",X"00",X"25",X"AC",X"00",X"29", + X"AE",X"00",X"25",X"AE",X"00",X"29",X"B0",X"00",X"25",X"B0",X"00",X"29",X"B2",X"00",X"25",X"B2", + X"00",X"29",X"B4",X"00",X"25",X"B4",X"00",X"29",X"B6",X"00",X"25",X"B6",X"00",X"29",X"B8",X"00", + X"25",X"B8",X"80",X"07",X"B8",X"00",X"29",X"BC",X"00",X"2F",X"C0",X"00",X"26",X"C2",X"00",X"26", + X"C2",X"98",X"0B",X"D0",X"00",X"2C",X"D2",X"00",X"2B",X"D4",X"00",X"48",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"21",X"32",X"80",X"CB",X"7E",X"20",X"20",X"CB",X"FE",X"3E",X"E4",X"11",X"A1",X"90", + X"01",X"18",X"00",X"CD",X"13",X"05",X"11",X"A1",X"90",X"3E",X"08",X"01",X"01",X"18",X"CD",X"32", + X"05",X"21",X"00",X"03",X"22",X"1B",X"80",X"18",X"7F",X"21",X"36",X"80",X"CB",X"76",X"C0",X"3A", + X"30",X"80",X"FE",X"06",X"20",X"05",X"21",X"32",X"80",X"CB",X"EE",X"2A",X"30",X"80",X"ED",X"5B", + X"33",X"80",X"19",X"22",X"33",X"80",X"11",X"03",X"00",X"B7",X"ED",X"52",X"28",X"02",X"38",X"58", + X"2A",X"1B",X"80",X"2B",X"22",X"1B",X"80",X"11",X"C0",X"00",X"B7",X"ED",X"52",X"20",X"0D",X"21", + X"32",X"80",X"CB",X"6E",X"20",X"06",X"01",X"0D",X"01",X"CD",X"75",X"48",X"2A",X"1B",X"80",X"7D", + X"0F",X"0F",X"E6",X"07",X"C6",X"DC",X"F5",X"3E",X"03",X"A4",X"67",X"3E",X"E0",X"A5",X"6F",X"01", + X"A1",X"90",X"09",X"F1",X"77",X"2A",X"1B",X"80",X"7C",X"B5",X"20",X"10",X"21",X"36",X"80",X"CB", + X"F6",X"21",X"23",X"80",X"CB",X"5E",X"C0",X"21",X"16",X"80",X"CB",X"DE",X"2A",X"33",X"80",X"11", + X"03",X"00",X"B7",X"ED",X"52",X"22",X"33",X"80",X"3E",X"0E",X"EF",X"C9",X"21",X"30",X"80",X"CB", + X"7E",X"20",X"24",X"CB",X"FE",X"2A",X"21",X"80",X"22",X"31",X"80",X"3E",X"C0",X"32",X"36",X"80", + X"11",X"A3",X"90",X"01",X"18",X"00",X"3E",X"E4",X"CD",X"13",X"05",X"11",X"A3",X"90",X"01",X"01", + X"18",X"3E",X"09",X"CD",X"32",X"05",X"C9",X"3A",X"36",X"80",X"B7",X"20",X"27",X"21",X"23",X"80", + X"CB",X"DE",X"AF",X"32",X"A1",X"81",X"32",X"A9",X"81",X"32",X"B1",X"81",X"32",X"9F",X"81",X"3E", + X"07",X"D3",X"08",X"3E",X"3F",X"32",X"A0",X"81",X"D3",X"09",X"01",X"03",X"03",X"CD",X"75",X"48", + X"3E",X"0D",X"D7",X"C9",X"2A",X"21",X"80",X"ED",X"5B",X"33",X"80",X"44",X"4D",X"ED",X"52",X"C8", + X"38",X"16",X"3E",X"07",X"BD",X"30",X"11",X"ED",X"43",X"33",X"80",X"21",X"14",X"80",X"CB",X"46", + X"20",X"06",X"3E",X"0F",X"21",X"01",X"00",X"E7",X"ED",X"5B",X"31",X"80",X"2A",X"21",X"80",X"22", + X"31",X"80",X"01",X"1C",X"00",X"B7",X"ED",X"42",X"30",X"05",X"21",X"14",X"80",X"CB",X"C6",X"2A", + X"31",X"80",X"B7",X"ED",X"52",X"C8",X"21",X"35",X"80",X"38",X"03",X"34",X"18",X"01",X"35",X"3E", + X"14",X"86",X"20",X"12",X"77",X"21",X"36",X"80",X"34",X"7E",X"E6",X"07",X"20",X"13",X"3E",X"E4", + X"F5",X"7E",X"D6",X"08",X"18",X"12",X"FE",X"28",X"C0",X"AF",X"32",X"35",X"80",X"21",X"36",X"80", + X"35",X"3E",X"07",X"A6",X"C6",X"DC",X"F5",X"7E",X"E6",X"F8",X"6F",X"26",X"00",X"29",X"29",X"11", + X"A3",X"90",X"19",X"F1",X"77",X"EB",X"01",X"01",X"01",X"3E",X"09",X"CD",X"32",X"05",X"C9",X"21", + X"32",X"80",X"CB",X"46",X"20",X"07",X"CB",X"C6",X"3A",X"2F",X"80",X"EF",X"C9",X"CB",X"4E",X"20", + X"2D",X"CB",X"CE",X"2A",X"30",X"80",X"22",X"34",X"80",X"21",X"07",X"27",X"22",X"36",X"80",X"3A", + X"21",X"80",X"32",X"38",X"80",X"2E",X"02",X"CD",X"54",X"01",X"38",X"0E",X"2A",X"34",X"80",X"ED", + X"4B",X"36",X"80",X"11",X"65",X"35",X"CD",X"92",X"01",X"C9",X"3E",X"0C",X"D7",X"C9",X"3A",X"33", + X"80",X"E6",X"03",X"20",X"27",X"21",X"32",X"80",X"CB",X"6E",X"20",X"20",X"2A",X"34",X"80",X"11", + X"04",X"04",X"19",X"01",X"08",X"18",X"CD",X"D0",X"3E",X"30",X"11",X"21",X"32",X"80",X"CB",X"EE", + X"3E",X"0E",X"21",X"00",X"01",X"E7",X"01",X"08",X"01",X"CD",X"75",X"48",X"21",X"33",X"80",X"34", + X"7E",X"E6",X"03",X"21",X"32",X"80",X"20",X"04",X"CB",X"DE",X"18",X"02",X"CB",X"9E",X"CD",X"70", + X"43",X"21",X"32",X"80",X"CB",X"76",X"C2",X"36",X"35",X"21",X"34",X"80",X"3E",X"50",X"BE",X"38", + X"13",X"21",X"32",X"80",X"CB",X"F6",X"3A",X"30",X"80",X"ED",X"44",X"21",X"34",X"80",X"86",X"28", + X"99",X"3D",X"28",X"96",X"3A",X"33",X"80",X"E6",X"0F",X"C2",X"C5",X"34",X"21",X"3D",X"80",X"34", + X"7E",X"E6",X"03",X"4F",X"06",X"00",X"21",X"69",X"35",X"09",X"3E",X"9C",X"86",X"0F",X"0F",X"32", + X"37",X"80",X"C3",X"C5",X"34",X"00",X"00",X"00",X"10",X"00",X"08",X"10",X"18",X"21",X"32",X"80", + X"CB",X"5E",X"20",X"4B",X"CB",X"DE",X"01",X"00",X"03",X"CD",X"75",X"48",X"21",X"00",X"00",X"22", + X"1D",X"80",X"22",X"21",X"80",X"21",X"18",X"00",X"22",X"1F",X"80",X"3E",X"48",X"32",X"1D",X"80", + X"CD",X"EA",X"38",X"3E",X"20",X"32",X"39",X"80",X"3E",X"02",X"11",X"BE",X"39",X"CD",X"51",X"39", + X"3E",X"20",X"32",X"39",X"80",X"32",X"3A",X"80",X"AF",X"32",X"2D",X"80",X"32",X"2A",X"80",X"21", + X"16",X"80",X"CB",X"76",X"21",X"19",X"80",X"28",X"01",X"23",X"35",X"CD",X"DC",X"0C",X"C9",X"2A", + X"21",X"80",X"11",X"10",X"01",X"B7",X"ED",X"52",X"38",X"05",X"21",X"14",X"80",X"CB",X"86",X"21", + X"16",X"80",X"CB",X"5E",X"28",X"23",X"21",X"3E",X"80",X"CB",X"56",X"20",X"36",X"CB",X"D6",X"AF", + X"32",X"9F",X"81",X"32",X"A1",X"81",X"32",X"A9",X"81",X"32",X"B1",X"81",X"3E",X"07",X"D3",X"08", + X"3E",X"3F",X"32",X"A0",X"81",X"D3",X"09",X"18",X"1A",X"21",X"3E",X"80",X"CB",X"5E",X"20",X"13", + X"3A",X"9F",X"81",X"B7",X"20",X"0D",X"01",X"06",X"02",X"CD",X"75",X"48",X"38",X"05",X"21",X"3E", + X"80",X"CB",X"DE",X"21",X"14",X"80",X"CB",X"56",X"28",X"0F",X"3A",X"23",X"80",X"E6",X"FC",X"CB", + X"D7",X"32",X"23",X"80",X"21",X"32",X"80",X"CB",X"EE",X"21",X"23",X"80",X"CB",X"5E",X"28",X"23", + X"CB",X"9E",X"3E",X"FF",X"11",X"A5",X"88",X"01",X"16",X"00",X"CD",X"06",X"05",X"3E",X"0F",X"21", + X"00",X"00",X"E7",X"3E",X"01",X"D7",X"21",X"16",X"80",X"CB",X"76",X"21",X"19",X"80",X"28",X"01", + X"23",X"34",X"C9",X"21",X"16",X"80",X"CB",X"5E",X"C2",X"75",X"37",X"21",X"32",X"80",X"CB",X"7E", + X"C2",X"ED",X"37",X"21",X"33",X"80",X"7E",X"E6",X"03",X"20",X"1A",X"2B",X"CB",X"6E",X"CC",X"1B", + X"02",X"21",X"14",X"80",X"CB",X"46",X"20",X"0D",X"3A",X"33",X"80",X"E6",X"04",X"20",X"06",X"3E", + X"0E",X"21",X"01",X"00",X"E7",X"21",X"23",X"80",X"CB",X"56",X"11",X"A7",X"3C",X"21",X"93",X"3C", + X"20",X"06",X"11",X"F2",X"3C",X"21",X"9D",X"3C",X"06",X"04",X"3A",X"1F",X"80",X"BE",X"30",X"04", + X"23",X"23",X"10",X"F9",X"06",X"00",X"23",X"4E",X"EB",X"09",X"3A",X"2D",X"80",X"4F",X"87",X"81", + X"4F",X"09",X"EB",X"CD",X"60",X"3C",X"B7",X"28",X"05",X"21",X"3E",X"80",X"CB",X"FE",X"2A",X"21", + X"80",X"06",X"00",X"CB",X"7F",X"28",X"01",X"05",X"4F",X"09",X"22",X"21",X"80",X"13",X"CD",X"60", + X"3C",X"B7",X"28",X"05",X"21",X"3E",X"80",X"CB",X"FE",X"21",X"1F",X"80",X"86",X"77",X"13",X"CD", + X"60",X"3C",X"B7",X"28",X"05",X"21",X"3E",X"80",X"CB",X"FE",X"21",X"1D",X"80",X"86",X"77",X"21", + X"3E",X"80",X"CB",X"7E",X"28",X"0C",X"CB",X"BE",X"3A",X"33",X"80",X"E6",X"03",X"20",X"03",X"CD", + X"16",X"3B",X"21",X"23",X"80",X"CB",X"56",X"28",X"12",X"CB",X"4E",X"28",X"05",X"CD",X"34",X"39", + X"18",X"0C",X"CB",X"46",X"28",X"05",X"CD",X"29",X"39",X"18",X"03",X"CD",X"0F",X"39",X"11",X"BE", + X"39",X"CD",X"51",X"39",X"21",X"23",X"80",X"CB",X"56",X"28",X"0B",X"3A",X"2D",X"80",X"11",X"B4", + X"39",X"CD",X"80",X"39",X"18",X"0B",X"3E",X"FF",X"11",X"A5",X"88",X"01",X"16",X"00",X"CD",X"06", + X"05",X"CD",X"EA",X"38",X"21",X"16",X"80",X"CB",X"4E",X"28",X"25",X"21",X"32",X"80",X"CB",X"FE", + X"3E",X"FF",X"11",X"A5",X"88",X"01",X"16",X"00",X"CD",X"06",X"05",X"AF",X"32",X"33",X"80",X"3A", + X"23",X"80",X"E6",X"F8",X"32",X"23",X"80",X"3A",X"32",X"80",X"E6",X"F8",X"32",X"32",X"80",X"C9", + X"21",X"33",X"80",X"35",X"C9",X"3E",X"FF",X"11",X"A5",X"88",X"01",X"16",X"00",X"CD",X"06",X"05", + X"21",X"3E",X"80",X"CB",X"66",X"20",X"08",X"CB",X"E6",X"01",X"08",X"01",X"CD",X"75",X"48",X"21", + X"31",X"80",X"CB",X"7E",X"20",X"0D",X"21",X"33",X"80",X"34",X"7E",X"E6",X"0F",X"C0",X"21",X"31", + X"80",X"CB",X"FE",X"21",X"3E",X"80",X"CB",X"6E",X"20",X"08",X"CB",X"EE",X"01",X"09",X"01",X"CD", + X"75",X"48",X"3A",X"36",X"80",X"E6",X"E0",X"07",X"07",X"07",X"21",X"3A",X"80",X"BE",X"28",X"06", + X"11",X"12",X"3A",X"CD",X"56",X"39",X"06",X"60",X"3A",X"36",X"80",X"B8",X"20",X"1A",X"21",X"14", + X"80",X"CB",X"F6",X"3E",X"01",X"D7",X"21",X"00",X"88",X"11",X"01",X"88",X"01",X"FF",X"00",X"36", + X"FF",X"ED",X"B0",X"21",X"32",X"00",X"F7",X"C9",X"21",X"36",X"80",X"34",X"C9",X"CD",X"1B",X"02", + X"3A",X"34",X"80",X"E6",X"03",X"20",X"06",X"3E",X"0E",X"21",X"02",X"00",X"E7",X"21",X"34",X"80", + X"34",X"21",X"32",X"80",X"CB",X"76",X"20",X"6B",X"CD",X"EA",X"38",X"11",X"BE",X"39",X"3E",X"02", + X"CD",X"51",X"39",X"ED",X"5B",X"21",X"80",X"2A",X"1F",X"80",X"19",X"ED",X"5B",X"26",X"80",X"B7", + X"ED",X"52",X"28",X"12",X"30",X"09",X"2A",X"21",X"80",X"23",X"22",X"21",X"80",X"18",X"07",X"2A", + X"21",X"80",X"2B",X"22",X"21",X"80",X"ED",X"5B",X"24",X"80",X"2A",X"1D",X"80",X"B7",X"ED",X"52", + X"28",X"0C",X"30",X"06",X"21",X"1D",X"80",X"34",X"18",X"04",X"21",X"1D",X"80",X"35",X"2A",X"24", + X"80",X"ED",X"5B",X"1D",X"80",X"B7",X"ED",X"52",X"C0",X"ED",X"5B",X"26",X"80",X"2A",X"1F",X"80", + X"ED",X"4B",X"21",X"80",X"09",X"B7",X"ED",X"52",X"C0",X"21",X"32",X"80",X"CB",X"F6",X"AF",X"32", + X"34",X"80",X"C9",X"3A",X"34",X"80",X"E6",X"78",X"0F",X"0F",X"0F",X"32",X"37",X"80",X"21",X"34", + X"80",X"34",X"21",X"30",X"80",X"CB",X"66",X"20",X"06",X"FE",X"0F",X"20",X"40",X"CB",X"E6",X"C6", + X"02",X"E6",X"0F",X"FE",X"05",X"30",X"36",X"3A",X"23",X"80",X"E6",X"04",X"28",X"2F",X"47",X"3A", + X"32",X"80",X"E6",X"04",X"B8",X"28",X"26",X"21",X"32",X"80",X"CB",X"BE",X"CB",X"B6",X"21",X"16", + X"80",X"CB",X"8E",X"AF",X"32",X"34",X"80",X"32",X"37",X"80",X"32",X"2D",X"80",X"21",X"23",X"80", + X"CB",X"EE",X"3E",X"20",X"32",X"39",X"80",X"21",X"30",X"80",X"CB",X"A6",X"C9",X"21",X"23",X"80", + X"CB",X"56",X"20",X"07",X"21",X"32",X"80",X"CB",X"96",X"18",X"05",X"21",X"32",X"80",X"CB",X"D6", + X"3A",X"37",X"80",X"11",X"D2",X"39",X"CD",X"51",X"39",X"C9",X"3A",X"1D",X"80",X"C6",X"68",X"21", + X"00",X"B0",X"CB",X"66",X"20",X"07",X"21",X"16",X"80",X"CB",X"76",X"20",X"0E",X"ED",X"44",X"32", + X"DF",X"98",X"3A",X"1F",X"80",X"D6",X"20",X"32",X"DE",X"98",X"C9",X"C6",X"90",X"18",X"F0",X"3A", + X"33",X"80",X"E6",X"01",X"21",X"39",X"80",X"20",X"27",X"7E",X"FE",X"20",X"38",X"05",X"20",X"06", + X"3E",X"02",X"C9",X"34",X"18",X"1A",X"35",X"18",X"17",X"21",X"39",X"80",X"7E",X"B7",X"20",X"01", + X"C9",X"35",X"18",X"0C",X"21",X"39",X"80",X"7E",X"FE",X"40",X"20",X"03",X"3E",X"04",X"C9",X"34", + X"3E",X"07",X"86",X"4F",X"3E",X"01",X"FE",X"10",X"28",X"05",X"07",X"CB",X"19",X"18",X"F7",X"79", + X"C9",X"21",X"2D",X"80",X"BE",X"C8",X"77",X"26",X"00",X"6F",X"29",X"29",X"19",X"5E",X"23",X"56", + X"23",X"7E",X"21",X"00",X"B0",X"CB",X"66",X"20",X"09",X"21",X"16",X"80",X"CB",X"76",X"28",X"02", + X"EE",X"10",X"EB",X"32",X"DD",X"98",X"11",X"66",X"88",X"01",X"04",X"04",X"CD",X"DB",X"04",X"C9", + X"21",X"23",X"80",X"CB",X"56",X"C8",X"26",X"00",X"6F",X"29",X"19",X"5E",X"23",X"56",X"EB",X"3A", + X"3B",X"80",X"E6",X"03",X"20",X"19",X"3A",X"3B",X"80",X"CB",X"5F",X"20",X"09",X"11",X"3C",X"00", + X"19",X"3E",X"10",X"32",X"3B",X"80",X"11",X"A5",X"88",X"01",X"06",X"02",X"CD",X"DB",X"04",X"21", + X"3B",X"80",X"35",X"C9",X"9E",X"3A",X"AA",X"3A",X"B6",X"3A",X"C2",X"3A",X"CE",X"3A",X"3E",X"3A", + X"00",X"00",X"4E",X"3A",X"00",X"00",X"5E",X"3A",X"00",X"00",X"4E",X"3A",X"10",X"00",X"3E",X"3A", + X"10",X"00",X"5E",X"3A",X"00",X"00",X"4E",X"3A",X"10",X"00",X"3E",X"3A",X"10",X"00",X"2E",X"3A", + X"10",X"00",X"1E",X"3A",X"10",X"00",X"2E",X"3A",X"30",X"00",X"3E",X"3A",X"30",X"00",X"4E",X"3A", + X"30",X"00",X"5E",X"3A",X"20",X"00",X"4E",X"3A",X"20",X"00",X"3E",X"3A",X"20",X"00",X"2E",X"3A", + X"20",X"00",X"1E",X"3A",X"00",X"00",X"2E",X"3A",X"00",X"00",X"3E",X"3A",X"00",X"00",X"4E",X"3A", + X"00",X"00",X"6E",X"3A",X"00",X"00",X"7E",X"3A",X"00",X"00",X"8E",X"3A",X"00",X"00",X"00",X"01", + X"02",X"03",X"04",X"05",X"06",X"07",X"08",X"09",X"0A",X"0B",X"0C",X"0D",X"0E",X"0F",X"10",X"11", + X"12",X"13",X"14",X"15",X"16",X"17",X"18",X"19",X"1A",X"1B",X"1C",X"1D",X"1E",X"1F",X"20",X"21", + X"22",X"23",X"24",X"25",X"26",X"27",X"28",X"29",X"2A",X"2B",X"2C",X"2D",X"2E",X"2F",X"30",X"31", + X"32",X"33",X"34",X"35",X"36",X"37",X"38",X"39",X"3A",X"3B",X"3C",X"3D",X"3E",X"3F",X"40",X"41", + X"42",X"43",X"44",X"45",X"46",X"47",X"48",X"49",X"4A",X"4B",X"4C",X"4D",X"4E",X"4F",X"50",X"51", + X"52",X"53",X"54",X"55",X"56",X"57",X"58",X"59",X"5A",X"5B",X"5C",X"5D",X"5E",X"5F",X"60",X"61", + X"62",X"63",X"64",X"65",X"66",X"67",X"68",X"69",X"6A",X"6B",X"6C",X"6D",X"6E",X"6F",X"70",X"71", + X"72",X"73",X"74",X"75",X"76",X"77",X"78",X"79",X"7A",X"7B",X"7C",X"7D",X"7E",X"7F",X"80",X"81", + X"82",X"83",X"84",X"85",X"86",X"87",X"88",X"89",X"8A",X"8B",X"8C",X"8D",X"8E",X"8F",X"90",X"91", + X"92",X"93",X"94",X"95",X"96",X"97",X"98",X"99",X"9A",X"9B",X"9C",X"9D",X"9E",X"9F",X"A0",X"A1", + X"A2",X"A3",X"A4",X"A5",X"A6",X"A7",X"A8",X"A9",X"AA",X"AB",X"AC",X"AD",X"AE",X"AF",X"B0",X"B1", + X"B2",X"B3",X"B4",X"B5",X"B6",X"B7",X"B8",X"B9",X"BA",X"BB",X"BC",X"BD",X"BE",X"BF",X"C0",X"C1", + X"C2",X"C3",X"C4",X"C5",X"C6",X"C7",X"C8",X"C9",X"CA",X"CB",X"CC",X"CD",X"CE",X"CF",X"D0",X"D1", + X"D2",X"D3",X"D4",X"D5",X"D6",X"D7",X"D8",X"D9",X"DA",X"DB",X"DC",X"DD",X"DE",X"DF",X"E0",X"E1", + X"E2",X"E3",X"E4",X"E5",X"E6",X"E7",X"E8",X"E9",X"EA",X"EB",X"EC",X"ED",X"EE",X"EF",X"F0",X"F1", + X"F2",X"F3",X"F4",X"F5",X"F6",X"F7",X"3A",X"2D",X"80",X"B7",X"20",X"4C",X"21",X"1D",X"80",X"46", + X"21",X"1F",X"80",X"6E",X"3E",X"08",X"80",X"67",X"3E",X"10",X"85",X"6F",X"01",X"06",X"06",X"CD", + X"D9",X"41",X"DA",X"5A",X"3C",X"21",X"1D",X"80",X"46",X"21",X"1F",X"80",X"6E",X"3E",X"0E",X"80", + X"67",X"3E",X"0F",X"85",X"6F",X"01",X"06",X"05",X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"21",X"1D", + X"80",X"66",X"3A",X"1F",X"80",X"6F",X"3E",X"10",X"84",X"67",X"3E",X"08",X"85",X"6F",X"01",X"09", + X"07",X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"C9",X"FE",X"01",X"20",X"46",X"21",X"1D",X"80",X"66", + X"3A",X"1F",X"80",X"C6",X"10",X"6F",X"3E",X"09",X"84",X"67",X"01",X"07",X"08",X"CD",X"D9",X"41", + X"DA",X"5A",X"3C",X"21",X"1D",X"80",X"66",X"3A",X"1F",X"80",X"C6",X"0E",X"6F",X"3E",X"0B",X"84", + X"67",X"01",X"09",X"07",X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"21",X"1D",X"80",X"66",X"3A",X"1F", + X"80",X"C6",X"04",X"6F",X"3E",X"0E",X"84",X"67",X"01",X"0A",X"09",X"CD",X"D9",X"41",X"DA",X"5A", + X"3C",X"C9",X"FE",X"02",X"20",X"28",X"3A",X"1D",X"80",X"C6",X"0B",X"67",X"3A",X"1F",X"80",X"6F", + X"01",X"0A",X"16",X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"3A",X"1D",X"80",X"C6",X"0D",X"67",X"3A", + X"1F",X"80",X"C6",X"16",X"6F",X"01",X"06",X"08",X"CD",X"D9",X"41",X"38",X"7D",X"C9",X"FE",X"03", + X"20",X"3D",X"3A",X"1D",X"80",X"C6",X"08",X"67",X"3A",X"1F",X"80",X"C6",X"04",X"6F",X"01",X"0A", + X"09",X"CD",X"D9",X"41",X"38",X"64",X"3A",X"1D",X"80",X"C6",X"0C",X"67",X"3A",X"1F",X"80",X"C6", + X"0E",X"6F",X"01",X"09",X"07",X"CD",X"D9",X"41",X"38",X"50",X"3A",X"1D",X"80",X"C6",X"11",X"67", + X"3A",X"1F",X"80",X"C6",X"15",X"6F",X"01",X"06",X"08",X"CD",X"D9",X"41",X"38",X"3C",X"C9",X"3A", + X"1D",X"80",X"C6",X"06",X"67",X"3A",X"1F",X"80",X"C6",X"08",X"6F",X"01",X"0B",X"07",X"CD",X"D9", + X"41",X"38",X"27",X"3A",X"1D",X"80",X"C6",X"0B",X"67",X"3A",X"1F",X"80",X"C6",X"0F",X"6F",X"01", + X"07",X"04",X"CD",X"D9",X"41",X"38",X"13",X"3A",X"1D",X"80",X"C6",X"12",X"67",X"3A",X"1F",X"80", + X"C6",X"10",X"6F",X"01",X"06",X"07",X"CD",X"D9",X"41",X"D0",X"21",X"16",X"80",X"CB",X"DE",X"C9", + X"1A",X"B7",X"C8",X"21",X"33",X"80",X"CB",X"6F",X"20",X"1A",X"E6",X"0F",X"A6",X"3E",X"00",X"C0", + X"1A",X"FE",X"C3",X"20",X"15",X"21",X"23",X"80",X"7E",X"E6",X"03",X"C8",X"3E",X"01",X"CB",X"4E", + X"C0",X"3E",X"FF",X"C9",X"E6",X"0F",X"A6",X"3E",X"00",X"C8",X"1A",X"CB",X"7F",X"3E",X"01",X"C0", + X"3E",X"FF",X"C9",X"40",X"00",X"38",X"0F",X"30",X"1E",X"20",X"2D",X"00",X"3C",X"38",X"00",X"30", + X"0F",X"20",X"1E",X"19",X"2D",X"18",X"3C",X"81",X"00",X"41",X"A3",X"00",X"43",X"80",X"00",X"00", + X"A3",X"00",X"83",X"81",X"00",X"81",X"81",X"83",X"41",X"A3",X"83",X"43",X"80",X"83",X"00",X"A3", + X"83",X"83",X"81",X"83",X"81",X"83",X"83",X"41",X"81",X"83",X"43",X"81",X"83",X"00",X"81",X"83", + X"83",X"83",X"83",X"81",X"87",X"83",X"43",X"83",X"83",X"47",X"83",X"83",X"00",X"83",X"83",X"87", + X"87",X"83",X"83",X"00",X"83",X"47",X"00",X"83",X"4F",X"00",X"83",X"00",X"00",X"83",X"8F",X"00", + X"83",X"87",X"83",X"47",X"47",X"81",X"47",X"4F",X"81",X"47",X"C3",X"81",X"47",X"8F",X"83",X"47", + X"87",X"87",X"43",X"43",X"83",X"43",X"47",X"83",X"43",X"C3",X"83",X"43",X"87",X"87",X"43",X"8F", + X"00",X"43",X"43",X"00",X"43",X"47",X"00",X"43",X"C3",X"00",X"43",X"87",X"00",X"43",X"83",X"00", + X"43",X"47",X"00",X"43",X"4F",X"00",X"43",X"00",X"00",X"43",X"8F",X"00",X"43",X"87",X"43",X"00", + X"00",X"43",X"00",X"00",X"43",X"00",X"00",X"43",X"00",X"00",X"43",X"00",X"00",X"21",X"39",X"80", + X"CB",X"66",X"20",X"46",X"CB",X"7E",X"20",X"07",X"CB",X"FE",X"3A",X"2F",X"80",X"EF",X"C9",X"CB", + X"E6",X"21",X"1D",X"06",X"22",X"34",X"80",X"2A",X"30",X"80",X"22",X"32",X"80",X"7C",X"B7",X"20", + X"05",X"21",X"39",X"80",X"CB",X"DE",X"AF",X"11",X"AB",X"3E",X"CD",X"15",X"42",X"21",X"01",X"06", + X"CD",X"54",X"01",X"DA",X"33",X"3E",X"2A",X"32",X"80",X"ED",X"4B",X"34",X"80",X"11",X"72",X"3E", + X"CD",X"92",X"01",X"3A",X"21",X"80",X"32",X"37",X"80",X"C9",X"21",X"39",X"80",X"CB",X"56",X"C2", + X"12",X"3E",X"3A",X"32",X"80",X"D6",X"D0",X"30",X"05",X"21",X"39",X"80",X"CB",X"CE",X"2A",X"32", + X"80",X"11",X"03",X"03",X"19",X"01",X"0A",X"0A",X"CD",X"D0",X"3E",X"30",X"07",X"21",X"16",X"80", + X"CB",X"DE",X"18",X"7F",X"21",X"38",X"80",X"34",X"7E",X"E6",X"03",X"20",X"7F",X"3E",X"01",X"11", + X"AB",X"3E",X"CD",X"15",X"42",X"B7",X"C8",X"4F",X"CB",X"41",X"28",X"10",X"CD",X"74",X"3E",X"21", + X"39",X"80",X"CB",X"4E",X"28",X"06",X"B7",X"28",X"5A",X"3C",X"28",X"57",X"CB",X"49",X"28",X"19", + X"CD",X"91",X"3E",X"2A",X"32",X"80",X"11",X"03",X"03",X"19",X"01",X"0A",X"0A",X"CD",X"D9",X"41", + X"38",X"07",X"21",X"39",X"80",X"CB",X"D6",X"18",X"19",X"CB",X"51",X"CA",X"6D",X"3D",X"CD",X"9F", + X"3E",X"21",X"39",X"80",X"CB",X"4E",X"CA",X"6D",X"3D",X"B7",X"28",X"27",X"3C",X"28",X"24",X"C3", + X"6D",X"3D",X"21",X"36",X"80",X"34",X"46",X"3E",X"10",X"B8",X"38",X"17",X"78",X"E6",X"03",X"28", + X"08",X"3E",X"0A",X"32",X"35",X"80",X"C3",X"6D",X"3D",X"3E",X"0A",X"CB",X"F7",X"32",X"35",X"80", + X"C3",X"6D",X"3D",X"AF",X"32",X"39",X"80",X"3A",X"2F",X"80",X"D7",X"C9",X"21",X"3A",X"80",X"34", + X"7E",X"E6",X"0C",X"20",X"08",X"3E",X"06",X"32",X"35",X"80",X"C3",X"6D",X"3D",X"FE",X"04",X"20", + X"08",X"3E",X"07",X"32",X"35",X"80",X"C3",X"6D",X"3D",X"FE",X"08",X"20",X"08",X"3E",X"08",X"32", + X"35",X"80",X"C3",X"6D",X"3D",X"FE",X"0C",X"C2",X"6D",X"3D",X"3E",X"09",X"32",X"35",X"80",X"C3", + X"6D",X"3D",X"00",X"00",X"3A",X"21",X"80",X"47",X"3A",X"37",X"80",X"21",X"32",X"80",X"90",X"78", + X"32",X"37",X"80",X"38",X"03",X"35",X"18",X"01",X"34",X"46",X"3A",X"30",X"80",X"ED",X"44",X"80", + X"C9",X"21",X"33",X"80",X"3A",X"39",X"80",X"CB",X"5F",X"28",X"02",X"34",X"C9",X"35",X"C9",X"21", + X"32",X"80",X"35",X"46",X"3A",X"30",X"80",X"ED",X"44",X"80",X"C9",X"B3",X"3E",X"C3",X"3E",X"B3", + X"3E",X"C3",X"3E",X"F4",X"F5",X"F4",X"F5",X"F6",X"F6",X"F7",X"F7",X"F7",X"F7",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"F4",X"F4",X"F7",X"F4",X"F5",X"F4",X"F5",X"F6",X"F7",X"FF",X"FF",X"FF",X"FF", + X"3A",X"2D",X"80",X"FE",X"05",X"38",X"02",X"3E",X"02",X"57",X"87",X"87",X"82",X"87",X"5F",X"16", + X"00",X"FD",X"21",X"36",X"3F",X"FD",X"19",X"3A",X"1D",X"80",X"FD",X"86",X"00",X"57",X"3A",X"1F", + X"80",X"FD",X"86",X"01",X"95",X"30",X"0B",X"ED",X"44",X"FD",X"BE",X"02",X"30",X"20",X"1E",X"01", + X"18",X"05",X"B8",X"30",X"19",X"1E",X"01",X"7A",X"94",X"30",X"09",X"ED",X"44",X"FD",X"BE",X"03", + X"30",X"0C",X"18",X"03",X"B9",X"30",X"07",X"3E",X"01",X"A3",X"28",X"02",X"37",X"C9",X"FD",X"7E", + X"04",X"B7",X"C8",X"3A",X"2D",X"80",X"FE",X"05",X"38",X"02",X"3E",X"02",X"57",X"87",X"87",X"82", + X"87",X"C6",X"05",X"5F",X"18",X"A9",X"06",X"0E",X"0B",X"0A",X"01",X"0E",X"06",X"0A",X"0B",X"00", + X"08",X"0A",X"10",X"07",X"01",X"0D",X"02",X"11",X"08",X"00",X"08",X"02",X"14",X"0C",X"01",X"0B", + X"16",X"07",X"06",X"00",X"05",X"02",X"11",X"08",X"01",X"0D",X"0A",X"10",X"07",X"00",X"03",X"06", + X"0A",X"0B",X"01",X"0C",X"0E",X"0B",X"0A",X"00",X"3A",X"00",X"B8",X"21",X"32",X"80",X"CB",X"66", + X"C2",X"B1",X"3F",X"CB",X"E6",X"3A",X"14",X"80",X"CB",X"7F",X"20",X"31",X"21",X"14",X"80",X"CB", + X"4E",X"20",X"2A",X"CB",X"CE",X"11",X"BA",X"90",X"AF",X"01",X"06",X"00",X"CD",X"06",X"05",X"3A", + X"16",X"80",X"CB",X"7F",X"20",X"0D",X"11",X"3A",X"91",X"3E",X"24",X"01",X"06",X"00",X"CD",X"06", + X"05",X"18",X"0A",X"11",X"3A",X"91",X"AF",X"01",X"06",X"00",X"CD",X"06",X"05",X"3E",X"0F",X"EF", + X"C9",X"3A",X"14",X"80",X"CB",X"7F",X"20",X"F5",X"21",X"32",X"80",X"CB",X"46",X"C2",X"A0",X"40", + X"2A",X"30",X"80",X"7C",X"B5",X"CA",X"7B",X"40",X"3A",X"16",X"80",X"CB",X"77",X"20",X"0E",X"11", + X"BE",X"90",X"CD",X"36",X"41",X"21",X"BA",X"90",X"3A",X"2B",X"80",X"18",X"0C",X"11",X"3E",X"91", + X"CD",X"36",X"41",X"21",X"3A",X"91",X"3A",X"2C",X"80",X"F5",X"E5",X"CD",X"60",X"41",X"E1",X"F1", + X"B7",X"20",X"21",X"E5",X"11",X"BA",X"92",X"CD",X"28",X"05",X"E1",X"D2",X"71",X"40",X"11",X"BA", + X"92",X"CD",X"05",X"41",X"0E",X"04",X"3E",X"24",X"11",X"9B",X"92",X"CD",X"06",X"05",X"CD",X"21", + X"41",X"C3",X"71",X"40",X"FE",X"01",X"20",X"28",X"E5",X"11",X"BA",X"92",X"CD",X"05",X"41",X"E1", + X"11",X"3A",X"92",X"CD",X"28",X"05",X"D2",X"71",X"40",X"21",X"3A",X"92",X"11",X"BA",X"92",X"CD", + X"10",X"41",X"21",X"1B",X"92",X"11",X"9B",X"92",X"CD",X"14",X"41",X"CD",X"21",X"41",X"18",X"31", + X"FE",X"02",X"20",X"27",X"E5",X"11",X"3A",X"92",X"CD",X"05",X"41",X"E1",X"11",X"BA",X"91",X"CD", + X"28",X"05",X"30",X"1D",X"21",X"BA",X"91",X"11",X"3A",X"92",X"CD",X"10",X"41",X"21",X"9B",X"91", + X"11",X"1B",X"92",X"CD",X"14",X"41",X"CD",X"21",X"41",X"18",X"06",X"11",X"BA",X"91",X"CD",X"05", + X"41",X"21",X"32",X"80",X"CB",X"46",X"C0",X"3E",X"0F",X"EF",X"C9",X"3E",X"22",X"CD",X"12",X"0D", + X"3E",X"23",X"CD",X"12",X"0D",X"3E",X"24",X"01",X"0F",X"00",X"11",X"48",X"91",X"CD",X"06",X"05", + X"3E",X"24",X"01",X"13",X"00",X"11",X"86",X"91",X"CD",X"06",X"05",X"21",X"32",X"80",X"CB",X"C6", + X"2A",X"1B",X"80",X"EB",X"21",X"32",X"80",X"CB",X"76",X"20",X"06",X"CB",X"F6",X"ED",X"53",X"35", + X"80",X"7B",X"B2",X"20",X"22",X"11",X"80",X"00",X"B7",X"2A",X"35",X"80",X"ED",X"52",X"30",X"05", + X"21",X"18",X"01",X"18",X"03",X"21",X"50",X"00",X"F7",X"21",X"14",X"80",X"CB",X"EE",X"21",X"16", + X"80",X"CB",X"86",X"3E",X"0F",X"D7",X"C9",X"3E",X"0E",X"21",X"03",X"00",X"E7",X"21",X"34",X"80", + X"7E",X"34",X"E6",X"01",X"C0",X"21",X"17",X"80",X"3A",X"16",X"80",X"CB",X"77",X"28",X"01",X"23", + X"7E",X"FE",X"0A",X"38",X"02",X"3E",X"0A",X"21",X"56",X"41",X"3D",X"5F",X"16",X"00",X"19",X"6E", + X"26",X"00",X"C3",X"C8",X"3F",X"01",X"05",X"00",X"18",X"03",X"01",X"04",X"00",X"ED",X"B0",X"C9", + X"06",X"05",X"18",X"02",X"06",X"04",X"4E",X"1A",X"77",X"EB",X"71",X"EB",X"23",X"13",X"10",X"F6", + X"C9",X"3A",X"16",X"80",X"21",X"2B",X"80",X"11",X"2C",X"80",X"CB",X"77",X"28",X"01",X"EB",X"34", + X"1A",X"BE",X"C0",X"EB",X"35",X"C9",X"01",X"00",X"05",X"EB",X"3E",X"0F",X"A3",X"81",X"0E",X"00", + X"86",X"77",X"C6",X"F6",X"30",X"02",X"77",X"0C",X"2B",X"3E",X"04",X"B7",X"CB",X"1A",X"CB",X"1B", + X"3D",X"20",X"F8",X"10",X"E5",X"C9",X"01",X"01",X"02",X"02",X"03",X"04",X"05",X"07",X"07",X"10", + X"EB",X"01",X"2E",X"80",X"0A",X"21",X"16",X"80",X"CB",X"76",X"20",X"09",X"CB",X"7F",X"C0",X"CB", + X"77",X"28",X"09",X"18",X"18",X"CB",X"6F",X"C0",X"CB",X"67",X"20",X"11",X"21",X"CF",X"41",X"EB", + X"01",X"00",X"B0",X"0A",X"CB",X"5F",X"28",X"09",X"11",X"D4",X"41",X"18",X"04",X"21",X"CA",X"41", + X"EB",X"CD",X"28",X"05",X"D0",X"01",X"0A",X"01",X"CD",X"75",X"48",X"21",X"19",X"80",X"3A",X"16", + X"80",X"CB",X"77",X"20",X"11",X"34",X"CD",X"DC",X"0C",X"21",X"2E",X"80",X"CB",X"76",X"20",X"03", + X"CB",X"F6",X"C9",X"CB",X"FE",X"C9",X"21",X"1A",X"80",X"34",X"CD",X"DC",X"0C",X"21",X"2E",X"80", + X"CB",X"66",X"20",X"03",X"CB",X"E6",X"C9",X"CB",X"EE",X"C9",X"01",X"00",X"00",X"00",X"00",X"00", + X"02",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"7C",X"E6",X"07",X"81",X"C6",X"07",X"E6", + X"F8",X"0F",X"0F",X"0F",X"4F",X"7D",X"80",X"47",X"E5",X"C5",X"CD",X"F8",X"41",X"C1",X"E1",X"D8", + X"7D",X"C6",X"08",X"6F",X"B8",X"38",X"F1",X"C9",X"3A",X"21",X"80",X"85",X"6F",X"CD",X"46",X"46", + X"1A",X"FE",X"35",X"28",X"0B",X"FE",X"86",X"30",X"07",X"FE",X"5C",X"D8",X"FE",X"9C",X"3F",X"D8", + X"13",X"0D",X"20",X"EC",X"C9",X"B7",X"20",X"0E",X"ED",X"5F",X"E6",X"03",X"11",X"3C",X"80",X"12", + X"AF",X"13",X"12",X"13",X"12",X"C9",X"42",X"4B",X"2A",X"3C",X"80",X"26",X"00",X"29",X"19",X"5E", + X"23",X"56",X"EB",X"ED",X"5B",X"3D",X"80",X"16",X"00",X"19",X"3A",X"3E",X"80",X"B7",X"28",X"08", + X"3D",X"32",X"3E",X"80",X"7E",X"E6",X"0F",X"C9",X"7E",X"FE",X"FF",X"28",X"12",X"E6",X"F0",X"0F", + X"0F",X"0F",X"0F",X"32",X"3E",X"80",X"23",X"11",X"3D",X"80",X"1A",X"3C",X"12",X"18",X"C7",X"21", + X"3D",X"80",X"36",X"00",X"23",X"36",X"00",X"50",X"59",X"18",X"BB",X"3A",X"00",X"B8",X"21",X"16", + X"80",X"CB",X"5E",X"C0",X"21",X"32",X"80",X"CB",X"46",X"20",X"30",X"CB",X"C6",X"21",X"37",X"80", + X"3A",X"2F",X"80",X"E6",X"1F",X"FE",X"09",X"28",X"16",X"3E",X"04",X"32",X"36",X"80",X"36",X"0F", + X"ED",X"5F",X"CB",X"47",X"28",X"10",X"3E",X"05",X"32",X"36",X"80",X"36",X"13",X"18",X"07",X"3E", + X"03",X"32",X"36",X"80",X"36",X"0B",X"3A",X"2F",X"80",X"EF",X"C9",X"CB",X"4E",X"20",X"26",X"CB", + X"CE",X"AF",X"32",X"33",X"80",X"3A",X"21",X"80",X"32",X"38",X"80",X"21",X"02",X"07",X"CD",X"54", + X"01",X"DA",X"5C",X"43",X"11",X"61",X"43",X"2A",X"30",X"80",X"22",X"34",X"80",X"ED",X"4B",X"36", + X"80",X"CD",X"92",X"01",X"C9",X"21",X"33",X"80",X"34",X"7E",X"21",X"32",X"80",X"CB",X"9E",X"E6", + X"07",X"20",X"02",X"CB",X"DE",X"21",X"02",X"07",X"CD",X"54",X"01",X"DA",X"5C",X"43",X"2A",X"34", + X"80",X"CD",X"70",X"43",X"11",X"61",X"43",X"ED",X"4B",X"36",X"80",X"3A",X"39",X"80",X"B7",X"28", + X"11",X"11",X"65",X"43",X"3A",X"39",X"80",X"04",X"04",X"FE",X"01",X"28",X"05",X"CB",X"F0",X"11", + X"69",X"43",X"2A",X"34",X"80",X"CD",X"92",X"01",X"3A",X"33",X"80",X"E6",X"03",X"20",X"33",X"2A", + X"34",X"80",X"11",X"04",X"04",X"19",X"01",X"08",X"0C",X"CD",X"D0",X"3E",X"38",X"1E",X"21",X"6D", + X"43",X"3A",X"39",X"80",X"5F",X"16",X"00",X"19",X"7E",X"2A",X"34",X"80",X"84",X"C6",X"04",X"67", + X"7D",X"C6",X"10",X"6F",X"01",X"08",X"0C",X"CD",X"D0",X"3E",X"30",X"06",X"21",X"16",X"80",X"CB", + X"DE",X"C9",X"3A",X"34",X"80",X"C6",X"1E",X"B7",X"28",X"02",X"3D",X"C0",X"3A",X"2F",X"80",X"D7", + X"C9",X"00",X"00",X"00",X"10",X"00",X"00",X"04",X"10",X"00",X"00",X"FC",X"10",X"00",X"04",X"FC", + X"21",X"38",X"80",X"46",X"3A",X"21",X"80",X"77",X"4F",X"78",X"91",X"21",X"34",X"80",X"86",X"77", + X"3A",X"32",X"80",X"CB",X"5F",X"C8",X"CB",X"57",X"20",X"06",X"21",X"34",X"80",X"35",X"18",X"5C", + X"3A",X"35",X"80",X"C6",X"08",X"47",X"3A",X"28",X"80",X"C6",X"08",X"4F",X"3A",X"29",X"80",X"91", + X"E6",X"FE",X"0F",X"21",X"32",X"80",X"CB",X"E6",X"81",X"B8",X"28",X"4E",X"CB",X"A6",X"3A",X"3A", + X"80",X"B8",X"28",X"46",X"01",X"08",X"10",X"3A",X"39",X"80",X"FE",X"01",X"20",X"17",X"2A",X"34", + X"80",X"11",X"00",X"F8",X"19",X"CD",X"D9",X"41",X"30",X"06",X"3E",X"02",X"32",X"39",X"80",X"C9", + X"21",X"35",X"80",X"35",X"C9",X"2A",X"34",X"80",X"11",X"00",X"10",X"19",X"CD",X"D9",X"41",X"30", + X"06",X"3E",X"01",X"32",X"39",X"80",X"C9",X"21",X"35",X"80",X"34",X"C9",X"21",X"3B",X"80",X"34", + X"7E",X"E6",X"1F",X"28",X"05",X"3A",X"39",X"80",X"18",X"09",X"ED",X"5F",X"E6",X"03",X"FE",X"03", + X"20",X"01",X"AF",X"06",X"03",X"32",X"39",X"80",X"4F",X"87",X"87",X"81",X"5F",X"16",X"00",X"21", + X"BE",X"44",X"19",X"C5",X"E5",X"46",X"23",X"4E",X"23",X"7E",X"23",X"66",X"6F",X"3A",X"34",X"80", + X"85",X"6F",X"3A",X"35",X"80",X"84",X"67",X"CD",X"D9",X"41",X"D1",X"C1",X"30",X"70",X"3A",X"39", + X"80",X"3C",X"FE",X"03",X"20",X"01",X"AF",X"32",X"39",X"80",X"10",X"CC",X"21",X"32",X"80",X"CB", + X"D6",X"CB",X"66",X"20",X"49",X"3A",X"28",X"80",X"C6",X"08",X"47",X"3A",X"29",X"80",X"90",X"E6", + X"FC",X"0F",X"0F",X"4F",X"80",X"57",X"3A",X"35",X"80",X"C6",X"08",X"5F",X"92",X"28",X"10",X"38", + X"0E",X"79",X"87",X"81",X"47",X"7B",X"90",X"30",X"14",X"ED",X"5F",X"CB",X"5F",X"20",X"0E",X"79", + X"87",X"81",X"32",X"3A",X"80",X"21",X"35",X"80",X"34",X"3E",X"02",X"18",X"0A",X"79",X"32",X"3A", + X"80",X"21",X"35",X"80",X"35",X"3E",X"01",X"32",X"39",X"80",X"32",X"3C",X"80",X"C9",X"3A",X"3C", + X"80",X"32",X"39",X"80",X"21",X"35",X"80",X"FE",X"01",X"20",X"01",X"35",X"34",X"C9",X"21",X"32", + X"80",X"CB",X"96",X"CB",X"A6",X"3E",X"04",X"83",X"5F",X"3E",X"00",X"8A",X"57",X"1A",X"32",X"39", + X"80",X"B7",X"C8",X"21",X"35",X"80",X"FE",X"01",X"20",X"02",X"35",X"C9",X"34",X"C9",X"18",X"10", + X"F0",X"00",X"00",X"18",X"08",X"F0",X"F8",X"01",X"18",X"08",X"F0",X"10",X"02",X"3A",X"00",X"B8", + X"21",X"16",X"80",X"CB",X"5E",X"C0",X"21",X"32",X"80",X"CB",X"46",X"20",X"07",X"CB",X"C6",X"3A", + X"2F",X"80",X"EF",X"C9",X"CB",X"4E",X"20",X"2A",X"CB",X"CE",X"AF",X"32",X"33",X"80",X"21",X"01", + X"05",X"CD",X"54",X"01",X"DA",X"F3",X"45",X"06",X"03",X"0E",X"1C",X"ED",X"43",X"36",X"80",X"3A", + X"21",X"80",X"32",X"38",X"80",X"2A",X"30",X"80",X"22",X"34",X"80",X"11",X"6C",X"46",X"CD",X"92", + X"01",X"C9",X"CB",X"6E",X"C2",X"09",X"46",X"CB",X"76",X"C2",X"13",X"46",X"21",X"33",X"80",X"34", + X"7E",X"21",X"32",X"80",X"CB",X"9E",X"E6",X"07",X"20",X"02",X"CB",X"DE",X"21",X"01",X"05",X"CD", + X"54",X"01",X"DA",X"F3",X"45",X"CD",X"70",X"43",X"CD",X"33",X"46",X"11",X"6C",X"46",X"2A",X"34", + X"80",X"ED",X"4B",X"36",X"80",X"CD",X"92",X"01",X"3A",X"33",X"80",X"E6",X"03",X"C2",X"E9",X"45", + X"2A",X"34",X"80",X"11",X"02",X"01",X"19",X"01",X"0C",X"0E",X"CD",X"D0",X"3E",X"D2",X"E9",X"45", + X"3A",X"2D",X"80",X"FE",X"02",X"20",X"2F",X"3A",X"1F",X"80",X"C6",X"18",X"47",X"3A",X"34",X"80", + X"90",X"38",X"23",X"3A",X"35",X"80",X"C6",X"08",X"47",X"3A",X"1D",X"80",X"C6",X"0C",X"B8",X"30", + X"15",X"C6",X"06",X"B8",X"38",X"10",X"01",X"0C",X"01",X"CD",X"75",X"48",X"21",X"32",X"80",X"CB", + X"F6",X"AF",X"32",X"2A",X"80",X"C9",X"21",X"32",X"80",X"CB",X"EE",X"CD",X"FD",X"01",X"01",X"0B", + X"01",X"CD",X"75",X"48",X"AF",X"32",X"33",X"80",X"3A",X"2A",X"80",X"3C",X"FE",X"0A",X"30",X"09", + X"07",X"07",X"07",X"07",X"6F",X"26",X"00",X"18",X"04",X"26",X"01",X"2E",X"00",X"3E",X"0F",X"E7", + X"3A",X"34",X"80",X"2A",X"21",X"80",X"85",X"6F",X"3A",X"35",X"80",X"67",X"CD",X"46",X"46",X"3E", + X"86",X"21",X"2A",X"80",X"86",X"3C",X"12",X"13",X"3E",X"86",X"12",X"21",X"2A",X"80",X"7E",X"FE", + X"09",X"30",X"01",X"34",X"AF",X"32",X"33",X"80",X"C9",X"3A",X"34",X"80",X"C6",X"10",X"B7",X"28", + X"02",X"3D",X"C0",X"3A",X"32",X"80",X"CB",X"77",X"20",X"06",X"3E",X"0E",X"21",X"20",X"00",X"E7", + X"AF",X"32",X"2A",X"80",X"3A",X"2F",X"80",X"D7",X"C9",X"21",X"33",X"80",X"34",X"7E",X"FE",X"40", + X"28",X"F2",X"C9",X"21",X"01",X"05",X"CD",X"54",X"01",X"38",X"D8",X"21",X"35",X"80",X"56",X"2B", + X"7E",X"3D",X"32",X"34",X"80",X"5F",X"EB",X"0E",X"1C",X"06",X"05",X"11",X"6C",X"46",X"CD",X"92", + X"01",X"18",X"B6",X"21",X"3D",X"80",X"34",X"7E",X"E6",X"0F",X"C0",X"21",X"37",X"80",X"34",X"7E", + X"FE",X"05",X"C0",X"36",X"03",X"C9",X"7D",X"C6",X"18",X"ED",X"44",X"E6",X"F8",X"5F",X"16",X"00", + X"CB",X"13",X"CB",X"12",X"CB",X"13",X"CB",X"12",X"7A",X"E6",X"03",X"57",X"7C",X"C6",X"20",X"E6", + X"F8",X"0F",X"0F",X"0F",X"B3",X"5F",X"21",X"00",X"90",X"19",X"EB",X"C9",X"00",X"00",X"3A",X"00", + X"B8",X"21",X"32",X"80",X"CB",X"7E",X"20",X"11",X"CB",X"FE",X"3E",X"13",X"EF",X"21",X"23",X"80", + X"CB",X"AE",X"2A",X"21",X"80",X"22",X"37",X"80",X"C9",X"CB",X"76",X"20",X"3F",X"CB",X"F6",X"21", + X"16",X"80",X"CB",X"D6",X"21",X"36",X"80",X"36",X"00",X"2A",X"31",X"80",X"26",X"00",X"22",X"24", + X"80",X"2A",X"30",X"80",X"26",X"00",X"ED",X"5B",X"37",X"80",X"19",X"22",X"26",X"80",X"22",X"37", + X"80",X"3A",X"24",X"80",X"67",X"CD",X"46",X"46",X"D5",X"21",X"A8",X"47",X"01",X"04",X"01",X"CD", + X"C5",X"04",X"D1",X"3E",X"06",X"01",X"04",X"01",X"CD",X"32",X"05",X"C9",X"21",X"34",X"80",X"34", + X"7E",X"E6",X"03",X"C0",X"CD",X"26",X"47",X"28",X"36",X"21",X"16",X"80",X"CB",X"8E",X"21",X"23", + X"80",X"CB",X"6E",X"20",X"1B",X"2A",X"26",X"80",X"ED",X"5B",X"21",X"80",X"B7",X"ED",X"52",X"3A", + X"24",X"80",X"67",X"01",X"20",X"20",X"CD",X"D0",X"3E",X"30",X"05",X"21",X"16",X"80",X"CB",X"CE", + X"21",X"35",X"80",X"34",X"7E",X"E6",X"01",X"C0",X"23",X"34",X"7E",X"E6",X"03",X"77",X"C9",X"3E", + X"13",X"D7",X"21",X"16",X"80",X"CB",X"96",X"21",X"23",X"80",X"CB",X"AE",X"21",X"00",X"00",X"22", + X"24",X"80",X"22",X"26",X"80",X"C9",X"21",X"33",X"80",X"36",X"00",X"21",X"33",X"80",X"7E",X"CB", + X"BF",X"6F",X"26",X"00",X"29",X"29",X"29",X"ED",X"5B",X"37",X"80",X"19",X"ED",X"5B",X"21",X"80", + X"EB",X"01",X"10",X"00",X"B7",X"ED",X"42",X"B7",X"ED",X"52",X"30",X"23",X"2A",X"21",X"80",X"01", + X"E8",X"00",X"09",X"ED",X"52",X"38",X"18",X"CD",X"7D",X"47",X"D5",X"01",X"04",X"01",X"CD",X"C5", + X"04",X"D1",X"3E",X"06",X"01",X"04",X"01",X"CD",X"32",X"05",X"21",X"33",X"80",X"CB",X"FE",X"21", + X"33",X"80",X"34",X"7E",X"CB",X"BF",X"FE",X"04",X"20",X"B1",X"CB",X"7E",X"C9",X"6B",X"3A",X"24", + X"80",X"67",X"CD",X"46",X"46",X"D5",X"3A",X"36",X"80",X"11",X"A0",X"47",X"26",X"00",X"6F",X"29", + X"19",X"5E",X"23",X"56",X"2A",X"33",X"80",X"CB",X"BD",X"26",X"00",X"29",X"29",X"19",X"D1",X"C9", + X"A8",X"47",X"B8",X"47",X"C7",X"47",X"D7",X"47",X"5C",X"5D",X"5E",X"5F",X"60",X"61",X"62",X"63", + X"64",X"65",X"66",X"67",X"68",X"69",X"6A",X"6B",X"6C",X"6D",X"6E",X"6F",X"70",X"71",X"72",X"73", + X"74",X"75",X"76",X"77",X"78",X"7A",X"7B",X"7C",X"7D",X"7E",X"7F",X"80",X"81",X"82",X"83",X"84", + X"85",X"86",X"87",X"88",X"89",X"8A",X"8B",X"8C",X"8D",X"8E",X"8F",X"90",X"91",X"92",X"93",X"94", + X"95",X"96",X"97",X"98",X"99",X"9A",X"9B",X"DD",X"21",X"A1",X"81",X"DD",X"CB",X"00",X"7E",X"C4", + X"09",X"48",X"DD",X"21",X"A9",X"81",X"DD",X"CB",X"00",X"7E",X"C4",X"09",X"48",X"DD",X"21",X"B1", + X"81",X"DD",X"CB",X"00",X"7E",X"C4",X"09",X"48",X"C9",X"DD",X"7E",X"02",X"B7",X"28",X"04",X"DD", + X"35",X"02",X"C9",X"DD",X"7E",X"03",X"DD",X"77",X"02",X"DD",X"7E",X"04",X"B7",X"28",X"04",X"DD", + X"35",X"04",X"C9",X"DD",X"6E",X"06",X"DD",X"66",X"07",X"06",X"00",X"DD",X"4E",X"05",X"09",X"7E", + X"FE",X"FF",X"20",X"1B",X"DD",X"CB",X"00",X"6E",X"20",X"0C",X"DD",X"CB",X"00",X"76",X"28",X"06", + X"DD",X"36",X"05",X"00",X"18",X"DD",X"DD",X"36",X"00",X"00",X"21",X"9F",X"81",X"35",X"C9",X"0F", + X"0F",X"0F",X"0F",X"E6",X"0F",X"DD",X"77",X"04",X"7E",X"E6",X"0F",X"07",X"01",X"EE",X"49",X"EB", + X"26",X"00",X"6F",X"09",X"4E",X"23",X"46",X"60",X"69",X"01",X"72",X"48",X"C5",X"13",X"DD",X"34", + X"05",X"E9",X"38",X"AF",X"C9",X"21",X"14",X"80",X"CB",X"7E",X"C0",X"C5",X"79",X"CD",X"85",X"48", + X"C1",X"0C",X"10",X"F1",X"C9",X"21",X"A1",X"81",X"11",X"08",X"00",X"06",X"03",X"4F",X"E6",X"7F", + X"CB",X"79",X"20",X"42",X"3A",X"9F",X"81",X"3C",X"FE",X"04",X"3F",X"D8",X"32",X"9F",X"81",X"AF", + X"BE",X"28",X"05",X"19",X"10",X"FA",X"37",X"C9",X"E5",X"05",X"70",X"23",X"71",X"EB",X"69",X"67", + X"47",X"29",X"09",X"01",X"C4",X"49",X"09",X"EB",X"1A",X"CB",X"47",X"28",X"04",X"2B",X"CB",X"F6", + X"23",X"AF",X"23",X"77",X"23",X"77",X"23",X"77",X"23",X"77",X"23",X"13",X"1A",X"77",X"23",X"13", + X"1A",X"77",X"E1",X"CB",X"FE",X"C9",X"23",X"4F",X"7E",X"B9",X"28",X"05",X"19",X"10",X"F9",X"37", + X"C9",X"2B",X"CB",X"EE",X"C9",X"37",X"C9",X"DD",X"7E",X"00",X"E6",X"03",X"07",X"D3",X"08",X"47", + X"1A",X"D3",X"09",X"04",X"78",X"D3",X"08",X"13",X"1A",X"D3",X"09",X"DD",X"34",X"05",X"DD",X"34", + X"05",X"37",X"C9",X"DD",X"7E",X"00",X"E6",X"03",X"C6",X"08",X"D3",X"08",X"1A",X"D3",X"09",X"DD", + X"34",X"05",X"37",X"C9",X"3E",X"0B",X"D3",X"08",X"1A",X"D3",X"09",X"13",X"3E",X"0C",X"D3",X"08", + X"1A",X"D3",X"09",X"DD",X"34",X"05",X"DD",X"34",X"05",X"37",X"C9",X"3E",X"0D",X"D3",X"08",X"1A", + X"D3",X"09",X"DD",X"34",X"05",X"37",X"C9",X"3E",X"07",X"D3",X"08",X"DD",X"7E",X"00",X"E6",X"03", + X"3C",X"47",X"3E",X"80",X"07",X"10",X"FD",X"21",X"A0",X"81",X"B6",X"77",X"D3",X"09",X"B7",X"C9", + X"1A",X"DD",X"77",X"03",X"DD",X"34",X"05",X"37",X"C9",X"3E",X"07",X"D3",X"08",X"DD",X"7E",X"00", + X"E6",X"03",X"3C",X"47",X"3E",X"80",X"07",X"10",X"FD",X"21",X"A0",X"81",X"2F",X"A6",X"77",X"D3", + X"09",X"B7",X"C9",X"1A",X"07",X"21",X"21",X"4E",X"16",X"00",X"5F",X"19",X"EB",X"CD",X"E7",X"48", + X"DD",X"35",X"05",X"18",X"D4",X"3E",X"07",X"D3",X"08",X"DD",X"7E",X"00",X"E6",X"03",X"3C",X"47", + X"3E",X"04",X"07",X"10",X"FD",X"21",X"A0",X"81",X"2F",X"A6",X"77",X"D3",X"09",X"B7",X"C9",X"3E", + X"07",X"D3",X"08",X"DD",X"7E",X"00",X"E6",X"03",X"3C",X"47",X"3E",X"04",X"07",X"10",X"FD",X"21", + X"A0",X"81",X"B6",X"77",X"D3",X"09",X"B7",X"C9",X"3E",X"06",X"D3",X"08",X"1A",X"D3",X"09",X"DD", + X"34",X"05",X"37",X"C9",X"00",X"0C",X"4A",X"00",X"6F",X"4A",X"00",X"AD",X"4A",X"00",X"E2",X"4A", + X"00",X"22",X"4B",X"00",X"61",X"4B",X"01",X"A0",X"4B",X"01",X"89",X"4C",X"00",X"48",X"4D",X"00", + X"9C",X"4D",X"00",X"BE",X"4D",X"00",X"D8",X"4D",X"00",X"EA",X"4D",X"00",X"10",X"4E",X"E5",X"48", + X"E7",X"48",X"03",X"49",X"37",X"49",X"50",X"49",X"14",X"49",X"2B",X"49",X"59",X"49",X"73",X"49", + X"85",X"49",X"9F",X"49",X"B8",X"49",X"E5",X"48",X"E5",X"48",X"E5",X"48",X"04",X"02",X"02",X"0B", + X"28",X"05",X"03",X"28",X"05",X"03",X"18",X"05",X"18",X"04",X"18",X"05",X"18",X"07",X"28",X"09", + X"03",X"28",X"09",X"03",X"18",X"09",X"18",X"07",X"18",X"09",X"18",X"0A",X"28",X"0C",X"03",X"28", + X"0C",X"03",X"18",X"0C",X"18",X"0B",X"18",X"0C",X"18",X"11",X"78",X"0C",X"33",X"00",X"28",X"0C", + X"03",X"28",X"0E",X"03",X"28",X"0C",X"03",X"28",X"0A",X"03",X"28",X"09",X"03",X"28",X"07",X"03", + X"28",X"05",X"03",X"28",X"04",X"03",X"28",X"05",X"03",X"28",X"07",X"03",X"08",X"09",X"03",X"08", + X"0A",X"03",X"28",X"09",X"03",X"28",X"07",X"03",X"78",X"05",X"73",X"00",X"02",X"00",X"FF",X"04", + X"02",X"02",X"0C",X"68",X"05",X"03",X"68",X"00",X"03",X"68",X"09",X"03",X"68",X"05",X"43",X"28", + X"00",X"03",X"68",X"05",X"03",X"08",X"05",X"03",X"08",X"05",X"03",X"28",X"04",X"03",X"28",X"02", + X"03",X"28",X"00",X"03",X"68",X"0A",X"03",X"68",X"07",X"03",X"68",X"04",X"03",X"68",X"00",X"03", + X"68",X"07",X"03",X"68",X"00",X"03",X"68",X"05",X"03",X"02",X"00",X"73",X"FF",X"04",X"02",X"02", + X"09",X"33",X"08",X"11",X"63",X"08",X"11",X"63",X"08",X"11",X"63",X"08",X"11",X"63",X"08",X"11", + X"63",X"08",X"11",X"63",X"08",X"11",X"63",X"08",X"11",X"63",X"08",X"11",X"63",X"08",X"11",X"63", + X"08",X"11",X"63",X"08",X"11",X"63",X"08",X"11",X"63",X"08",X"11",X"23",X"08",X"11",X"02",X"00", + X"43",X"FF",X"04",X"02",X"02",X"0C",X"88",X"0C",X"03",X"08",X"0C",X"03",X"08",X"0C",X"03",X"28", + X"0C",X"03",X"28",X"07",X"03",X"28",X"04",X"03",X"28",X"07",X"03",X"28",X"0C",X"03",X"28",X"07", + X"03",X"28",X"0C",X"03",X"28",X"10",X"03",X"68",X"0C",X"03",X"48",X"13",X"03",X"08",X"13",X"03", + X"E8",X"13",X"03",X"A8",X"10",X"03",X"28",X"07",X"03",X"E8",X"0C",X"38",X"0C",X"02",X"00",X"B3", + X"00",X"FF",X"04",X"02",X"02",X"0C",X"88",X"07",X"03",X"08",X"07",X"03",X"08",X"07",X"03",X"28", + X"07",X"03",X"28",X"04",X"03",X"28",X"04",X"03",X"28",X"07",X"03",X"28",X"07",X"03",X"28",X"04", + X"03",X"28",X"07",X"03",X"28",X"0C",X"03",X"68",X"07",X"03",X"48",X"10",X"03",X"08",X"10",X"03", + X"E8",X"10",X"03",X"A8",X"0C",X"03",X"28",X"07",X"03",X"E8",X"07",X"38",X"07",X"02",X"00",X"B3", + X"FF",X"04",X"02",X"02",X"0C",X"88",X"04",X"03",X"08",X"04",X"03",X"08",X"04",X"03",X"28",X"04", + X"03",X"28",X"00",X"03",X"28",X"00",X"03",X"28",X"04",X"03",X"28",X"04",X"03",X"28",X"00",X"03", + X"28",X"04",X"03",X"28",X"07",X"03",X"68",X"04",X"03",X"48",X"0C",X"03",X"08",X"0C",X"03",X"E8", + X"0C",X"03",X"A8",X"07",X"03",X"28",X"04",X"03",X"E8",X"00",X"38",X"00",X"02",X"00",X"B3",X"FF", + X"04",X"05",X"02",X"08",X"08",X"0C",X"08",X"10",X"08",X"13",X"08",X"10",X"08",X"13",X"03",X"08", + X"18",X"03",X"08",X"17",X"03",X"08",X"15",X"03",X"08",X"13",X"03",X"08",X"11",X"03",X"08",X"10", + X"08",X"11",X"08",X"13",X"08",X"10",X"08",X"11",X"08",X"0E",X"08",X"10",X"08",X"0C",X"08",X"0B", + X"08",X"0E",X"08",X"13",X"08",X"17",X"08",X"13",X"08",X"11",X"08",X"10",X"08",X"0E",X"08",X"0C", + X"08",X"10",X"08",X"13",X"08",X"10",X"08",X"13",X"03",X"08",X"18",X"03",X"08",X"17",X"03",X"08", + X"15",X"03",X"08",X"13",X"03",X"08",X"11",X"03",X"08",X"10",X"08",X"11",X"08",X"13",X"08",X"10", + X"08",X"11",X"08",X"0E",X"08",X"10",X"08",X"0C",X"08",X"0E",X"08",X"13",X"08",X"17",X"08",X"13", + X"28",X"18",X"03",X"08",X"15",X"08",X"17",X"08",X"18",X"08",X"15",X"08",X"17",X"08",X"15",X"08", + X"13",X"08",X"11",X"08",X"13",X"08",X"15",X"08",X"17",X"08",X"13",X"08",X"15",X"08",X"13",X"08", + X"11",X"08",X"10",X"08",X"11",X"08",X"13",X"08",X"15",X"08",X"11",X"08",X"13",X"08",X"11",X"08", + X"10",X"08",X"0E",X"08",X"11",X"08",X"0E",X"08",X"11",X"08",X"15",X"08",X"13",X"08",X"11",X"08", + X"10",X"08",X"0E",X"08",X"0C",X"08",X"10",X"08",X"13",X"08",X"10",X"08",X"13",X"03",X"08",X"18", + X"03",X"08",X"17",X"03",X"08",X"15",X"03",X"08",X"13",X"03",X"08",X"11",X"03",X"08",X"10",X"08", + X"11",X"08",X"13",X"08",X"10",X"08",X"11",X"08",X"0E",X"08",X"10",X"08",X"0C",X"08",X"0B",X"08", + X"0E",X"08",X"13",X"08",X"17",X"28",X"18",X"03",X"FF",X"04",X"05",X"02",X"08",X"08",X"00",X"03", + X"08",X"07",X"03",X"08",X"00",X"03",X"08",X"07",X"03",X"08",X"00",X"03",X"08",X"07",X"03",X"08", + X"00",X"03",X"08",X"07",X"03",X"08",X"02",X"03",X"08",X"05",X"03",X"08",X"02",X"03",X"08",X"05", + X"03",X"08",X"02",X"03",X"08",X"05",X"03",X"08",X"07",X"03",X"08",X"02",X"03",X"08",X"00",X"03", + X"08",X"07",X"03",X"08",X"00",X"03",X"08",X"07",X"03",X"08",X"00",X"03",X"08",X"07",X"03",X"08", + X"00",X"03",X"08",X"07",X"03",X"08",X"05",X"03",X"08",X"02",X"03",X"08",X"05",X"03",X"08",X"02", + X"03",X"08",X"07",X"03",X"08",X"07",X"03",X"28",X"00",X"03",X"08",X"09",X"03",X"08",X"05",X"03", + X"08",X"09",X"03",X"08",X"05",X"03",X"08",X"07",X"03",X"08",X"04",X"03",X"08",X"07",X"03",X"08", + X"04",X"03",X"08",X"09",X"03",X"08",X"05",X"03",X"08",X"09",X"03",X"08",X"05",X"03",X"08",X"07", + X"03",X"08",X"05",X"03",X"08",X"04",X"03",X"08",X"02",X"03",X"08",X"00",X"03",X"08",X"07",X"03", + X"08",X"00",X"03",X"08",X"07",X"03",X"08",X"00",X"03",X"08",X"07",X"03",X"08",X"00",X"03",X"08", + X"07",X"03",X"08",X"05",X"03",X"08",X"02",X"03",X"08",X"05",X"03",X"08",X"02",X"03",X"08",X"07", + X"03",X"08",X"07",X"03",X"28",X"00",X"03",X"FF",X"04",X"01",X"02",X"0C",X"01",X"8E",X"01",X"27", + X"01",X"C6",X"00",X"27",X"01",X"9F",X"00",X"27",X"01",X"49",X"00",X"27",X"01",X"4C",X"00",X"27", + X"01",X"51",X"00",X"27",X"01",X"56",X"00",X"37",X"02",X"0A",X"01",X"5E",X"00",X"37",X"02",X"09", + X"01",X"68",X"00",X"37",X"02",X"08",X"01",X"79",X"00",X"37",X"01",X"99",X"00",X"37",X"02",X"07", + X"01",X"F2",X"00",X"37",X"02",X"06",X"01",X"1D",X"01",X"37",X"02",X"05",X"01",X"3C",X"01",X"37", + X"02",X"03",X"01",X"65",X"01",X"37",X"01",X"9E",X"01",X"37",X"03",X"FF",X"04",X"05",X"02",X"0C", + X"07",X"61",X"63",X"00",X"61",X"6B",X"00",X"61",X"75",X"00",X"61",X"7F",X"00",X"61",X"8E",X"00", + X"61",X"7F",X"00",X"61",X"75",X"00",X"61",X"6B",X"00",X"61",X"63",X"00",X"33",X"FF",X"04",X"02", + X"02",X"0C",X"08",X"0C",X"08",X"10",X"08",X"13",X"08",X"10",X"08",X"13",X"08",X"10",X"08",X"13", + X"08",X"10",X"38",X"0A",X"02",X"00",X"63",X"FF",X"04",X"00",X"02",X"0C",X"18",X"12",X"18",X"13", + X"18",X"14",X"18",X"16",X"38",X"17",X"02",X"00",X"73",X"FF",X"04",X"01",X"02",X"0A",X"68",X"09", + X"03",X"48",X"09",X"03",X"08",X"09",X"03",X"68",X"09",X"03",X"48",X"0C",X"03",X"08",X"0B",X"03", + X"48",X"0B",X"03",X"08",X"09",X"03",X"48",X"09",X"03",X"08",X"08",X"03",X"68",X"09",X"03",X"FF", + X"02",X"0C",X"04",X"05",X"58",X"15",X"23",X"58",X"15",X"23",X"58",X"15",X"23",X"58",X"15",X"23", + X"FF",X"4E",X"01",X"3C",X"01",X"2A",X"01",X"19",X"01",X"09",X"01",X"FB",X"00",X"EC",X"00",X"DF", + X"00",X"D3",X"00",X"C7",X"00",X"BC",X"00",X"B1",X"00",X"A7",X"00",X"9E",X"00",X"95",X"00",X"8D", + X"00",X"85",X"00",X"7D",X"00",X"76",X"00",X"70",X"00",X"69",X"00",X"63",X"00",X"5E",X"00",X"59", + X"00",X"54",X"00",X"01",X"00",X"00",X"3A",X"00",X"B8",X"E5",X"E1",X"E5",X"E1",X"10",X"FA",X"0D", + X"20",X"F4",X"C3",X"D1",X"02",X"E2",X"E3",X"E4",X"E5",X"E6",X"E7",X"E8",X"E9",X"EA",X"EB",X"EC", + X"ED",X"EE",X"EF",X"F0",X"F1",X"F2",X"F3",X"F4",X"F5",X"F6",X"F7",X"3A",X"2D",X"80",X"B7",X"20", + X"4C",X"21",X"1D",X"80",X"46",X"21",X"1F",X"80",X"6E",X"3E",X"08",X"80",X"67",X"3E",X"10",X"85", + X"6F",X"01",X"06",X"06",X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"21",X"1D",X"80",X"46",X"21",X"1F", + X"80",X"6E",X"3E",X"0E",X"80",X"67",X"3E",X"0F",X"85",X"6F",X"01",X"06",X"05",X"CD",X"D9",X"41", + X"DA",X"5A",X"3C",X"21",X"1D",X"80",X"66",X"3A",X"1F",X"80",X"6F",X"3E",X"10",X"84",X"67",X"3E", + X"08",X"85",X"6F",X"01",X"09",X"07",X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"C9",X"FE",X"01",X"20", + X"46",X"21",X"1D",X"80",X"66",X"3A",X"1F",X"80",X"C6",X"10",X"6F",X"3E",X"09",X"84",X"67",X"01", + X"07",X"08",X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"21",X"1D",X"80",X"66",X"3A",X"1F",X"80",X"C6", + X"0E",X"6F",X"3E",X"0B",X"84",X"67",X"01",X"09",X"07",X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"21", + X"1D",X"80",X"66",X"3A",X"1F",X"80",X"C6",X"04",X"6F",X"3E",X"0E",X"84",X"67",X"01",X"0A",X"09", + X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"C9",X"FE",X"02",X"20",X"28",X"3A",X"1D",X"80",X"C6",X"0B", + X"67",X"3A",X"1F",X"80",X"6F",X"01",X"0A",X"16",X"CD",X"D9",X"41",X"DA",X"5A",X"3C",X"3A",X"1D", + X"80",X"C6",X"0D",X"67",X"3A",X"1F",X"80",X"C6",X"16",X"6F",X"01",X"06",X"08",X"CD",X"D9",X"41", + X"38",X"7D",X"C9",X"FE",X"03",X"20",X"3D",X"3A",X"1D",X"80",X"C6",X"08",X"67",X"3A",X"1F",X"80", + X"C6",X"04",X"6F",X"01",X"0A",X"09",X"CD",X"D9",X"41",X"38",X"64",X"3A",X"1D",X"80",X"C6",X"0C", + X"67",X"3A",X"1F",X"80",X"C6",X"0E",X"6F",X"01",X"09",X"07",X"CD",X"D9",X"41",X"38",X"50",X"3A", + X"1D",X"80",X"C6",X"11",X"67",X"3A",X"1F",X"80",X"C6",X"15",X"6F",X"01",X"06",X"08",X"CD",X"D9", + X"41",X"38",X"3C",X"C9",X"3A",X"1D",X"80",X"C6",X"06",X"67",X"3A",X"1F",X"80",X"C6",X"08",X"6F", + X"01",X"0B",X"07",X"CD",X"D9",X"41",X"38",X"27",X"3A",X"1D",X"80",X"C6",X"0B",X"67",X"3A",X"1F", + X"80",X"C6",X"0F",X"6F",X"01",X"07",X"04",X"CD",X"D9",X"41",X"38",X"13",X"3A",X"1D",X"80",X"C6", + X"12",X"67",X"3A",X"1F",X"80",X"C6",X"10",X"6F",X"01",X"06",X"07",X"CD",X"D9",X"41",X"D0",X"21", + X"16",X"80",X"CB",X"DE",X"C9",X"1A",X"B7",X"C8",X"21",X"33",X"80",X"CB",X"6F",X"20",X"1A",X"E6", + X"0F",X"A6",X"3E",X"00",X"C0",X"1A",X"FE",X"C3",X"20",X"15",X"21",X"23",X"80",X"7E",X"E6",X"03", + X"C8",X"3E",X"01",X"CB",X"4E",X"C0",X"3E",X"FF",X"C9",X"E6",X"0F",X"A6",X"3E",X"00",X"C8",X"1A", + X"CB",X"7F",X"3E",X"01",X"C0",X"3E",X"FF",X"C9",X"40",X"00",X"38",X"0F",X"30",X"1E",X"20",X"2D"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_tile_bit0.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_tile_bit0.vhd new file mode 100644 index 00000000..ecf6b92e --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_tile_bit0.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cclimber_tile_bit0 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cclimber_tile_bit0 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"1C",X"26",X"63",X"63",X"63",X"32",X"1C",X"00",X"0C",X"1C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00", + X"3E",X"63",X"07",X"1E",X"3C",X"70",X"7F",X"00",X"3F",X"06",X"0C",X"1E",X"03",X"63",X"3E",X"00", + X"0E",X"1E",X"36",X"66",X"7F",X"06",X"06",X"00",X"3E",X"30",X"3E",X"03",X"03",X"33",X"1E",X"00", + X"1E",X"30",X"60",X"7E",X"63",X"63",X"3E",X"00",X"3F",X"23",X"06",X"0C",X"18",X"18",X"18",X"00", + X"3C",X"62",X"72",X"3C",X"4F",X"43",X"3E",X"00",X"3E",X"63",X"63",X"3F",X"03",X"06",X"3C",X"00", + X"1C",X"36",X"63",X"63",X"7F",X"63",X"63",X"00",X"7E",X"63",X"63",X"7E",X"63",X"63",X"7E",X"00", + X"1E",X"33",X"60",X"60",X"60",X"33",X"1E",X"00",X"7C",X"66",X"63",X"63",X"63",X"66",X"7C",X"00", + X"3F",X"30",X"30",X"3E",X"30",X"30",X"3F",X"00",X"7F",X"60",X"60",X"7E",X"60",X"60",X"60",X"00", + X"1F",X"30",X"60",X"67",X"63",X"33",X"1F",X"00",X"63",X"63",X"63",X"7F",X"63",X"63",X"63",X"00", + X"3F",X"0C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00",X"03",X"03",X"03",X"03",X"03",X"63",X"3E",X"00", + X"63",X"66",X"6C",X"78",X"7C",X"6E",X"67",X"00",X"30",X"30",X"30",X"30",X"30",X"30",X"3F",X"00", + X"63",X"77",X"7F",X"7F",X"6B",X"63",X"63",X"00",X"63",X"73",X"7B",X"7F",X"6F",X"67",X"63",X"00", + X"3E",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"7E",X"63",X"63",X"63",X"7E",X"60",X"60",X"00", + X"3E",X"63",X"63",X"63",X"6F",X"66",X"3D",X"00",X"7E",X"63",X"63",X"67",X"7C",X"6E",X"67",X"00", + X"3C",X"66",X"60",X"3E",X"03",X"63",X"3E",X"00",X"3F",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"00", + X"63",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"63",X"63",X"63",X"77",X"3E",X"1C",X"08",X"00", + X"63",X"63",X"6B",X"7F",X"7F",X"36",X"22",X"00",X"63",X"77",X"3E",X"1C",X"3E",X"77",X"63",X"00", + X"33",X"33",X"12",X"1E",X"0C",X"0C",X"0C",X"00",X"7F",X"07",X"0E",X"1C",X"38",X"70",X"7F",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"06",X"06",X"00",X"00",X"18",X"30",X"30",X"30",X"30",X"30",X"18",X"00", + X"18",X"0C",X"0C",X"0C",X"0C",X"0C",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E", + X"00",X"00",X"00",X"18",X"1C",X"04",X"08",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"02",X"02",X"02",X"02",X"02",X"02",X"04",X"04",X"20",X"00",X"20",X"20",X"20",X"20",X"20",X"20", + X"04",X"00",X"01",X"06",X"0C",X"09",X"09",X"00",X"10",X"10",X"80",X"60",X"30",X"90",X"90",X"00", + X"00",X"00",X"00",X"00",X"08",X"02",X"02",X"02",X"00",X"00",X"00",X"00",X"20",X"20",X"00",X"00", + X"02",X"02",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"40",X"40",X"40",X"40",X"00",X"00",X"20", + X"02",X"02",X"02",X"02",X"04",X"04",X"00",X"00",X"80",X"00",X"20",X"20",X"20",X"40",X"40",X"40", + X"00",X"03",X"0F",X"18",X"16",X"06",X"00",X"00",X"00",X"00",X"80",X"C0",X"40",X"40",X"40",X"00", + X"00",X"00",X"00",X"04",X"00",X"00",X"04",X"04",X"00",X"00",X"00",X"00",X"20",X"20",X"00",X"00", + X"04",X"04",X"04",X"00",X"01",X"01",X"21",X"24",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"00", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"07",X"03",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"E0",X"C0", + X"00",X"00",X"00",X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"80",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"04",X"04",X"04",X"04",X"00",X"00",X"00",X"00",X"20",X"20",X"20",X"20", + X"05",X"05",X"00",X"00",X"07",X"0F",X"0F",X"0F",X"A0",X"A0",X"00",X"00",X"E0",X"F0",X"F0",X"F0", + X"03",X"03",X"07",X"07",X"03",X"03",X"00",X"00",X"FC",X"F8",X"F8",X"F8",X"F8",X"F0",X"60",X"00", + X"00",X"04",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"01",X"02",X"02",X"02",X"04",X"04",X"00",X"00",X"00",X"08",X"10",X"10",X"D0",X"D0", + X"00",X"00",X"08",X"1F",X"1F",X"1F",X"1F",X"3F",X"20",X"00",X"00",X"00",X"C0",X"E0",X"C0",X"C0", + X"01",X"06",X"08",X"00",X"00",X"00",X"01",X"07",X"C0",X"30",X"08",X"00",X"00",X"00",X"C0",X"F0", + X"0F",X"0F",X"0F",X"07",X"03",X"00",X"00",X"00",X"F8",X"F8",X"F8",X"F0",X"E0",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"01",X"06",X"08",X"00",X"00",X"00",X"00",X"00",X"C0",X"30",X"08",X"00", + X"00",X"00",X"01",X"06",X"08",X"00",X"00",X"00",X"00",X"00",X"C0",X"30",X"08",X"00",X"00",X"00", + X"07",X"00",X"00",X"00",X"00",X"1F",X"3F",X"3F",X"C0",X"20",X"10",X"08",X"00",X"00",X"80",X"C0", + X"7F",X"3F",X"3F",X"1F",X"07",X"00",X"00",X"00",X"E0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"08",X"08", + X"00",X"00",X"00",X"0F",X"00",X"00",X"00",X"00",X"04",X"02",X"02",X"80",X"40",X"20",X"10",X"00", + X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"80",X"BC",X"00",X"00",X"00", + X"08",X"00",X"00",X"01",X"3D",X"00",X"00",X"00",X"40",X"80",X"80",X"00",X"00",X"00",X"00",X"00", + X"11",X"11",X"01",X"00",X"00",X"04",X"04",X"04",X"00",X"10",X"10",X"88",X"84",X"80",X"30",X"20", + X"00",X"08",X"08",X"11",X"21",X"01",X"06",X"04",X"88",X"88",X"80",X"00",X"00",X"20",X"20",X"20", + X"04",X"04",X"04",X"00",X"00",X"01",X"11",X"11",X"20",X"60",X"80",X"84",X"88",X"10",X"10",X"00", + X"04",X"06",X"01",X"21",X"11",X"08",X"08",X"00",X"20",X"20",X"20",X"00",X"00",X"80",X"88",X"88", + X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"00",X"00",X"00",X"BC",X"80",X"00",X"00",X"10", + X"00",X"00",X"00",X"3D",X"01",X"00",X"00",X"08",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"40", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"00",X"C0",X"18",X"01",X"00",X"00", + X"E0",X"00",X"00",X"03",X"18",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"08",X"08",X"10",X"00",X"00",X"80",X"88",X"02",X"00",X"00",X"C0",X"00",X"30", + X"01",X"11",X"40",X"00",X"00",X"03",X"00",X"0C",X"00",X"00",X"00",X"10",X"10",X"08",X"00",X"00", + X"00",X"00",X"10",X"08",X"08",X"00",X"00",X"00",X"30",X"00",X"C0",X"00",X"00",X"02",X"88",X"80", + X"0C",X"00",X"03",X"00",X"00",X"40",X"11",X"01",X"00",X"00",X"08",X"01",X"01",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"18",X"C0",X"00",X"00",X"07", + X"00",X"00",X"80",X"18",X"03",X"00",X"00",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"80",X"90",X"10",X"06",X"00",X"00", + X"40",X"00",X"01",X"09",X"00",X"60",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"01",X"01",X"10",X"18",X"08",X"00",X"00",X"0C",X"00",X"00",X"84",X"80",X"00",X"00",X"20",X"40", + X"00",X"00",X"21",X"01",X"00",X"00",X"04",X"20",X"80",X"80",X"08",X"18",X"10",X"00",X"00",X"30", + X"0C",X"00",X"00",X"08",X"18",X"10",X"01",X"01",X"04",X"20",X"00",X"00",X"80",X"84",X"00",X"00", + X"20",X"04",X"00",X"00",X"01",X"21",X"00",X"00",X"30",X"00",X"00",X"10",X"18",X"08",X"80",X"80", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"06",X"10",X"90",X"80",X"00",X"02", + X"00",X"00",X"60",X"08",X"09",X"01",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40", + X"12",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"04",X"12",X"00",X"20",X"10",X"01",X"00",X"00", + X"20",X"48",X"00",X"04",X"08",X"80",X"00",X"00",X"48",X"00",X"C0",X"00",X"00",X"00",X"00",X"00", + X"00",X"01",X"00",X"10",X"10",X"00",X"08",X"08",X"00",X"08",X"04",X"00",X"81",X"40",X"00",X"00", + X"00",X"10",X"20",X"00",X"81",X"02",X"00",X"00",X"00",X"80",X"00",X"08",X"08",X"00",X"10",X"10", + X"08",X"08",X"00",X"10",X"10",X"00",X"01",X"00",X"00",X"00",X"40",X"81",X"00",X"04",X"08",X"00", + X"00",X"00",X"02",X"81",X"00",X"20",X"10",X"00",X"10",X"10",X"00",X"08",X"08",X"00",X"80",X"00", + X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"12",X"00",X"00",X"01",X"10",X"20",X"00",X"12",X"04", + X"00",X"00",X"80",X"08",X"04",X"00",X"48",X"20",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"48", + X"01",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00", + X"06",X"06",X"00",X"00",X"00",X"00",X"02",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"40",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"01",X"00",X"01",X"00",X"01",X"00",X"01",X"00",X"80",X"00",X"80",X"00",X"80",X"00",X"80",X"00", + X"06",X"00",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60", + X"00",X"06",X"06",X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"00",X"00",X"00",X"08",X"00",X"20", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"06",X"00",X"06",X"00",X"06",X"00",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"01",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"80",X"00",X"00",X"00",X"00",X"00", + X"06",X"06",X"00",X"00",X"00",X"00",X"02",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"40",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"01",X"00",X"01",X"00",X"01",X"00",X"01",X"00",X"80",X"00",X"80",X"00",X"80",X"00",X"80",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"60",X"00",X"60",X"00",X"00",X"00",X"00",X"00", + X"06",X"00",X"00",X"00",X"00",X"10",X"00",X"04",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"60",X"00",X"60",X"00",X"60",X"00", + X"47",X"E6",X"E0",X"4F",X"2A",X"57",X"39",X"3E",X"60",X"08",X"DD",X"7E",X"01",X"BC",X"20",X"06", + X"DD",X"7E",X"00",X"BD",X"28",X"0C",X"5E",X"23",X"7E",X"57",X"E6",X"E0",X"23",X"B9",X"30",X"19", + X"2B",X"2B",X"78",X"A7",X"28",X"87",X"2B",X"77",X"E5",X"2A",X"2D",X"39",X"AF",X"CD",X"11",X"21", + X"E1",X"2B",X"77",X"22",X"57",X"39",X"AF",X"3C",X"C9",X"C5",X"E5",X"DD",X"73",X"52",X"7A",X"E6", + X"1F",X"87",X"87",X"5F",X"16",X"00",X"21",X"62",X"23",X"19",X"E5",X"FD",X"E3",X"FD",X"CB",X"FE", + X"7E",X"28",X"0C",X"2A",X"59",X"39",X"36",X"00",X"23",X"36",X"00",X"23",X"22",X"59",X"39",X"CD", + X"C6",X"20",X"2B",X"46",X"E5",X"2B",X"CB",X"7B",X"28",X"02",X"CB",X"FE",X"4E",X"78",X"07",X"AA", + X"E6",X"01",X"AA",X"07",X"E6",X"03",X"67",X"FD",X"7E",X"FF",X"24",X"25",X"28",X"04",X"0F",X"0F", + X"18",X"F9",X"E6",X"03",X"28",X"14",X"FE",X"02",X"38",X"0A",X"28",X"0C",X"D5",X"DD",X"5E",X"52", + X"CD",X"FC",X"20",X"D1",X"CB",X"B8",X"18",X"02",X"CB",X"F8",X"E1",X"70",X"FD",X"46",X"FE",X"CB", + X"68",X"20",X"10",X"DD",X"CB",X"08",X"4E",X"28",X"08",X"CB",X"76",X"28",X"04",X"CB",X"72",X"20", + X"02",X"CB",X"E8",X"21",X"BC",X"21",X"FD",X"5E",X"00",X"16",X"00",X"FD",X"19",X"FD",X"E3",X"E3", + X"E5",X"CD",X"C6",X"20",X"22",X"59",X"39",X"CB",X"79",X"C2",X"B7",X"21",X"CB",X"68",X"28",X"3C", + X"CD",X"DA",X"20",X"CB",X"60",X"28",X"0F",X"AF",X"BA",X"20",X"05",X"7B",X"FE",X"11",X"38",X"06", + X"CD",X"1E",X"24",X"11",X"11",X"00",X"D5",X"CD",X"C6",X"20",X"CD",X"DA",X"20",X"21",X"00",X"00", + X"78",X"C1",X"CB",X"77",X"20",X"0E",X"CB",X"5F",X"20",X"03",X"79",X"B0",X"C9",X"CB",X"FC",X"19", + X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C", + X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C", + X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C", + X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C", + X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"4C",X"A9",X"C2",X"20",X"FC",X"E4",X"C2",X"20", + X"FC",X"BB",X"62",X"20",X"FC",X"A2",X"62",X"20",X"FC",X"AC",X"81",X"08",X"50",X"48",X"81",X"08", + X"50",X"3C",X"81",X"08",X"50",X"31",X"81",X"60",X"50",X"34",X"81",X"60",X"50",X"29",X"62",X"20", + X"FC",X"3E",X"62",X"30",X"FC",X"4B",X"62",X"30",X"FC",X"51",X"62",X"20",X"FC",X"81",X"81",X"08", + X"50",X"27",X"81",X"08",X"50",X"15",X"81",X"08",X"50",X"17",X"63",X"30",X"FC",X"33",X"05",X"00", + X"00",X"00",X"06",X"00",X"00",X"00",X"C8",X"D8",X"2B",X"C9",X"D8",X"2B",X"C9",X"D0",X"2B",X"C9", + X"28",X"FC",X"D0",X"2B",X"C9",X"C0",X"2B",X"C9",X"C8",X"2B",X"C9",X"2B",X"ED",X"52",X"C9",X"C8", + X"D5",X"C5",X"CD",X"3F",X"24",X"C1",X"EB",X"CD",X"59",X"24",X"EB",X"E1",X"A7",X"ED",X"52",X"C9", + X"41",X"EB",X"C8",X"CB",X"3C",X"CB",X"1D",X"10",X"FA",X"C9",X"41",X"EB",X"C8",X"CB",X"25",X"CB", + X"14",X"DC",X"1E",X"24",X"10",X"F7",X"C9",X"2E",X"01",X"C8",X"EB",X"4D",X"44",X"3D",X"C8",X"F5", + X"C5",X"EB",X"CD",X"59",X"24",X"C1",X"F1",X"18",X"F4",X"EB",X"ED",X"4A",X"E0",X"08",X"F6",X"0D", + X"08",X"C9",X"EB",X"ED",X"42",X"18",X"F5",X"7B",X"B1",X"6F",X"7A",X"B0",X"67",X"C9",X"7B",X"A9", + X"6F",X"7A",X"A8",X"67",X"C9",X"7B",X"A1",X"6F",X"7A",X"A0",X"67",X"C9",X"28",X"DF",X"21",X"00", + X"00",X"3E",X"10",X"CB",X"23",X"CB",X"12",X"CB",X"15",X"CB",X"14",X"13",X"A7",X"ED",X"42",X"30", + X"01",X"0F",X"0F",X"1F",X"7F",X"FF",X"FF",X"FF",X"E0",X"E0",X"F0",X"FC",X"FF",X"FF",X"FE",X"FF", + X"FF",X"FF",X"7F",X"3F",X"1F",X"0F",X"03",X"01",X"FF",X"FE",X"FE",X"FC",X"FE",X"DE",X"C0",X"80", + X"1F",X"3F",X"7F",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"E8",X"FC",X"FE",X"FF",X"FF",X"FE",X"FE", + X"FF",X"7F",X"7F",X"3F",X"07",X"07",X"07",X"03",X"FC",X"FC",X"FE",X"FC",X"F8",X"E0",X"80",X"80", + X"0C",X"1F",X"3F",X"7F",X"7F",X"FF",X"FF",X"FF",X"C0",X"F0",X"FC",X"FC",X"FE",X"FE",X"FF",X"FF", + X"FF",X"7F",X"3F",X"1F",X"3F",X"1F",X"09",X"00",X"FF",X"FE",X"FE",X"FC",X"F8",X"F0",X"F0",X"60", + X"00",X"00",X"70",X"71",X"23",X"27",X"25",X"37",X"00",X"00",X"0E",X"8E",X"C4",X"E4",X"A4",X"EC", + X"12",X"11",X"1F",X"0F",X"07",X"5C",X"00",X"00",X"48",X"88",X"F8",X"F2",X"E0",X"46",X"00",X"00", + X"00",X"00",X"00",X"01",X"03",X"E7",X"E5",X"47",X"00",X"00",X"00",X"80",X"C0",X"E7",X"A7",X"E2", + X"42",X"41",X"7F",X"0F",X"46",X"17",X"0E",X"00",X"42",X"82",X"FE",X"F0",X"E4",X"E8",X"14",X"00", + X"00",X"00",X"00",X"01",X"03",X"07",X"05",X"07",X"00",X"00",X"00",X"80",X"C0",X"E0",X"A0",X"E0", + X"02",X"01",X"0F",X"1F",X"1F",X"1F",X"1F",X"07",X"40",X"80",X"F0",X"F8",X"F8",X"F8",X"F8",X"E0", + X"03",X"07",X"0F",X"1F",X"7F",X"FF",X"FF",X"7F",X"B0",X"F0",X"FC",X"FE",X"FF",X"FE",X"FF",X"FF", + X"7F",X"3F",X"7F",X"3F",X"7F",X"3F",X"17",X"02",X"FE",X"FE",X"FF",X"FF",X"FE",X"F4",X"E0",X"80", + X"0C",X"1F",X"3F",X"7F",X"7F",X"FF",X"FF",X"FF",X"C0",X"F0",X"FC",X"FC",X"FE",X"FE",X"FF",X"FF", + X"FF",X"7F",X"3F",X"1F",X"3F",X"1F",X"09",X"00",X"FF",X"FE",X"FE",X"FC",X"F8",X"F0",X"F0",X"60", + X"01",X"07",X"2F",X"7F",X"FF",X"FF",X"7F",X"7F",X"40",X"E8",X"FC",X"FE",X"FC",X"FE",X"FC",X"FE", + X"FF",X"FF",X"7F",X"FF",X"7F",X"3F",X"0F",X"0D",X"FE",X"FF",X"FF",X"FE",X"F8",X"F0",X"E0",X"C0", + X"06",X"0F",X"0F",X"1F",X"3F",X"7F",X"FF",X"FF",X"00",X"A8",X"FC",X"FE",X"FC",X"FE",X"FF",X"FE", + X"FF",X"7F",X"FF",X"FF",X"3F",X"3F",X"1F",X"0B",X"FF",X"FE",X"FE",X"FC",X"F8",X"FC",X"F8",X"30", + X"00",X"00",X"01",X"03",X"03",X"03",X"02",X"E0",X"40",X"C6",X"CE",X"DC",X"80",X"80",X"30",X"00", + X"79",X"70",X"20",X"08",X"18",X"30",X"70",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FC",X"FC",X"F8",X"F8",X"F8",X"F8",X"F0",X"F0",X"FC",X"FC",X"F8",X"F0",X"F0",X"F8",X"F8",X"FC", + X"FF",X"FE",X"FC",X"FC",X"FE",X"FE",X"FE",X"FC",X"FF",X"FE",X"FE",X"FE",X"FF",X"FF",X"FF",X"FF", + X"FC",X"FC",X"F8",X"F8",X"F8",X"FE",X"FE",X"FF",X"F0",X"F0",X"F8",X"F8",X"F8",X"F8",X"FC",X"FC", + X"F0",X"F0",X"F0",X"F0",X"E0",X"E0",X"E0",X"F0",X"FE",X"FE",X"FC",X"FC",X"F8",X"F8",X"F0",X"F0", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0F",X"39",X"22",X"2B",X"39",X"CD",X"49",X"1F",X"38",X"56",X"DD",X"CB",X"54",X"5E",X"28",X"45", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"3F",X"07", + X"00",X"00",X"80",X"F0",X"FE",X"FF",X"FF",X"FF",X"FF",X"1F",X"03",X"00",X"00",X"00",X"00",X"00", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FF",X"7F",X"3F",X"1F",X"0F",X"07",X"03",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"C0",X"F0",X"FC",X"FF", + X"C0",X"F0",X"FC",X"FF",X"FF",X"FF",X"FF",X"FF",X"01",X"02",X"04",X"08",X"10",X"08",X"04",X"03", + X"80",X"40",X"20",X"10",X"08",X"04",X"02",X"01",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"E0",X"FC",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"7F",X"0F",X"01",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"C0",X"F8",X"FF",X"24",X"03",X"02",X"26",X"37",X"00",X"DF",X"0E", + X"2C",X"18",X"27",X"3E",X"01",X"CF",X"18",X"10",X"AF",X"CF",X"0E",X"0C",X"18",X"1C",X"3E",X"81", + X"CF",X"0E",X"2D",X"18",X"15",X"3E",X"81",X"CF",X"0E",X"0D",X"18",X"0E",X"3E",X"40",X"CF",X"18", + X"E9",X"3E",X"41",X"CF",X"18",X"F2",X"AF",X"FE",X"01",X"C9",X"79",X"08",X"79",X"CB",X"71",X"28", + X"1D",X"21",X"A8",X"17",X"CD",X"30",X"00",X"D8",X"08",X"47",X"08",X"78",X"E6",X"20",X"B1",X"DD", + X"77",X"06",X"0E",X"01",X"FE",X"06",X"30",X"06",X"DD",X"CB",X"54",X"76",X"20",X"0F",X"2A",X"77", + X"39",X"11",X"06",X"39",X"E6",X"3F",X"12",X"D7",X"20",X"CC",X"22",X"77",X"39",X"DD",X"71",X"51", + X"CB",X"71",X"20",X"20",X"CB",X"69",X"28",X"1C",X"DD",X"CB",X"51",X"FE",X"3E",X"20",X"B9",X"20", + X"13",X"0E",X"C0",X"21",X"FC",X"0F",X"18",X"E2",X"CB",X"71",X"C2",X"1D",X"16",X"DD",X"7E",X"51", + X"E6",X"1F",X"3D",X"E7",X"08",X"CB",X"77",X"28",X"EF",X"DD",X"7E",X"06",X"FE",X"38",X"38",X"08", + X"FE",X"3B",X"30",X"04",X"DD",X"36",X"06",X"06",X"E6",X"1F",X"FE",X"19",X"20",X"0A",X"DD",X"CB", + X"0E",X"6E",X"DD",X"CB",X"0E",X"EE",X"18",X"0C",X"FE",X"1A",X"20",X"0B",X"DD",X"CB",X"0E",X"76", + X"DD",X"CB",X"0E",X"F6",X"CC",X"49",X"18",X"DD",X"7E",X"06",X"CB",X"67",X"28",X"07",X"07",X"07", + X"E6",X"30",X"DD",X"77",X"06",X"BF",X"C9",X"AB",X"41",X"42",X"43",X"44",X"45",X"48",X"4C",X"46", + X"49",X"52",X"53",X"CB",X"CE",X"01",X"D0",X"03",X"D2",X"05",X"06",X"D3",X"09",X"D7",X"81",X"46", + X"1D",X"07",X"81",X"43",X"10",X"00",X"81",X"45",X"14",X"02",X"81",X"4C",X"18",X"04",X"82",X"58", + X"59",X"19",X"1A",X"08",X"A1",X"50",X"1C",X"DD",X"CB",X"08",X"86",X"DD",X"CB",X"09",X"AE",X"21", + X"00",X"00",X"22",X"37",X"39",X"21",X"3F",X"3B",X"22",X"59",X"39",X"C9",X"2A",X"25",X"39",X"E5", + X"11",X"7F",X"3A",X"A7",X"ED",X"52",X"ED",X"5B",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"38",X"7C",X"7C",X"44",X"44",X"7C",X"7C", + X"77",X"55",X"55",X"55",X"55",X"55",X"77",X"00",X"06",X"02",X"02",X"02",X"02",X"02",X"07",X"00", + X"06",X"09",X"01",X"01",X"06",X"08",X"0F",X"00",X"06",X"09",X"01",X"06",X"01",X"09",X"06",X"00", + X"02",X"06",X"0A",X"12",X"12",X"1F",X"02",X"00",X"0F",X"08",X"08",X"07",X"01",X"09",X"0F",X"00", + X"06",X"09",X"08",X"0E",X"09",X"09",X"06",X"00",X"0F",X"01",X"02",X"04",X"08",X"08",X"08",X"00", + X"06",X"09",X"09",X"06",X"09",X"09",X"06",X"00",X"06",X"09",X"09",X"07",X"01",X"09",X"06",X"00", + X"67",X"25",X"25",X"25",X"25",X"25",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"1E",X"72",X"00",X"00",X"00",X"00",X"3F",X"61",X"40",X"40", + X"00",X"00",X"00",X"00",X"00",X"C0",X"60",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"03",X"0E",X"18",X"30",X"63",X"47",X"4D",X"00",X"FE",X"03",X"01",X"00",X"8E",X"9A",X"13", + X"00",X"00",X"00",X"81",X"C3",X"66",X"24",X"2C",X"00",X"00",X"00",X"F0",X"18",X"0D",X"07",X"C6", + X"00",X"00",X"00",X"00",X"00",X"F8",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"9E", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07", + X"00",X"00",X"00",X"00",X"00",X"07",X"04",X"C6",X"00",X"00",X"1C",X"74",X"46",X"C2",X"63",X"31", + X"3F",X"23",X"67",X"45",X"45",X"47",X"46",X"C7",X"C2",X"02",X"1E",X"1E",X"1A",X"02",X"06",X"1C", + X"4E",X"4B",X"49",X"49",X"49",X"4B",X"4E",X"4C",X"10",X"10",X"10",X"10",X"10",X"10",X"30",X"60", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C9",X"89",X"89",X"89",X"CF",X"46",X"64",X"34", + X"13",X"12",X"16",X"3C",X"01",X"03",X"0E",X"38",X"38",X"61",X"70",X"D0",X"B3",X"22",X"26",X"64", + X"E7",X"E4",X"04",X"0C",X"89",X"C9",X"CB",X"9A",X"C0",X"4F",X"C8",X"98",X"90",X"10",X"31",X"41", + X"B3",X"A0",X"60",X"44",X"CF",X"89",X"89",X"1B",X"80",X"C0",X"60",X"40",X"30",X"10",X"11",X"17", + X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"E0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"02",X"06",X"04",X"04", + X"18",X"E0",X"80",X"07",X"26",X"62",X"63",X"F1",X"72",X"1A",X"0F",X"85",X"C5",X"45",X"45",X"44", + X"30",X"38",X"38",X"1C",X"16",X"16",X"9B",X"89",X"C5",X"C4",X"44",X"0C",X"08",X"08",X"08",X"08", + X"90",X"90",X"90",X"90",X"98",X"98",X"8F",X"89",X"40",X"41",X"41",X"48",X"4C",X"4E",X"4B",X"49", + X"C0",X"80",X"80",X"C0",X"60",X"30",X"10",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"0E",X"04",X"04",X"04",X"0C",X"09",X"0B",X"0E",X"60",X"40",X"40",X"40",X"40",X"C0",X"00",X"00", + X"45",X"4D",X"C9",X"89",X"8B",X"8A",X"FA",X"03",X"92",X"16",X"34",X"24",X"2C",X"68",X"48",X"CD", + X"23",X"62",X"46",X"C4",X"8C",X"98",X"91",X"11",X"12",X"3E",X"38",X"00",X"07",X"1C",X"88",X"88", + X"3C",X"38",X"73",X"E2",X"C6",X"CC",X"8C",X"88",X"00",X"FE",X"83",X"00",X"00",X"00",X"00",X"00", + X"30",X"18",X"8C",X"C4",X"46",X"42",X"42",X"42",X"00",X"00",X"00",X"00",X"38",X"6C",X"C4",X"8C", + X"04",X"04",X"04",X"04",X"04",X"06",X"03",X"01",X"91",X"91",X"D1",X"58",X"78",X"18",X"0C",X"84", + X"C4",X"8C",X"18",X"10",X"1C",X"06",X"C3",X"70",X"89",X"88",X"CC",X"44",X"44",X"44",X"C4",X"DC", + X"88",X"88",X"C8",X"58",X"70",X"00",X"00",X"00",X"C1",X"41",X"5F",X"70",X"00",X"00",X"00",X"00", + X"78",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1B",X"0E",X"00",X"00",X"00",X"00",X"00",X"00", + X"88",X"CC",X"44",X"74",X"1C",X"00",X"00",X"00",X"88",X"8C",X"C4",X"46",X"63",X"30",X"18",X"0E", + X"00",X"00",X"01",X"03",X"DE",X"70",X"01",X"07",X"47",X"C7",X"8E",X"1C",X"38",X"F1",X"B3",X"62", + X"98",X"30",X"20",X"60",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"FC",X"02",X"02",X"02",X"02",X"03",X"00",X"00",X"78",X"2F",X"20",X"60",X"C0",X"80",X"00",X"00", + X"70",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FC",X"01",X"01",X"01",X"00",X"00",X"00",X"00", + X"C6",X"8C",X"06",X"82",X"E2",X"3E",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"18",X"01",X"B6",X"77",X"3C",X"C9",X"1E",X"08",X"DD",X"36",X"0C",X"06",X"DD",X"CB",X"50",X"DE", + X"53",X"CD",X"83",X"1C",X"21",X"12",X"10",X"ED",X"7B",X"4B",X"39",X"DD",X"21",X"FF",X"38",X"E9", + X"21",X"6E",X"10",X"30",X"F2",X"C2",X"69",X"1B",X"EB",X"E5",X"2B",X"36",X"0D",X"22",X"0F",X"39", + X"16",X"10",X"CD",X"83",X"1C",X"D1",X"C3",X"8E",X"2B",X"21",X"FA",X"10",X"18",X"E5",X"21",X"52", + X"45",X"3E",X"4C",X"DD",X"CB",X"0F",X"76",X"28",X"05",X"21",X"41",X"42",X"3E",X"53",X"22",X"E3", + X"38",X"32",X"E5",X"38",X"3E",X"32",X"32",X"CC",X"38",X"AF",X"32",X"09",X"39",X"21",X"00",X"00", + X"22",X"65",X"39",X"22",X"75",X"39",X"22",X"5F",X"39",X"22",X"67",X"39",X"22",X"1D",X"39",X"22", + X"3B",X"39",X"22",X"3D",X"39",X"22",X"1F",X"39",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_tile_bit1.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_tile_bit1.vhd new file mode 100644 index 00000000..4fd7d795 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/cclimber_tile_bit1.vhd @@ -0,0 +1,278 @@ +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity cclimber_tile_bit1 is +port ( + clk : in std_logic; + addr : in std_logic_vector(11 downto 0); + data : out std_logic_vector(7 downto 0) +); +end entity; + +architecture prom of cclimber_tile_bit1 is + type rom is array(0 to 4095) of std_logic_vector(7 downto 0); + signal rom_data: rom := ( + X"1C",X"26",X"63",X"63",X"63",X"32",X"1C",X"00",X"0C",X"1C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00", + X"3E",X"63",X"07",X"1E",X"3C",X"70",X"7F",X"00",X"3F",X"06",X"0C",X"1E",X"03",X"63",X"3E",X"00", + X"0E",X"1E",X"36",X"66",X"7F",X"06",X"06",X"00",X"3E",X"30",X"3E",X"03",X"03",X"33",X"1E",X"00", + X"1E",X"30",X"60",X"7E",X"63",X"63",X"3E",X"00",X"3F",X"23",X"06",X"0C",X"18",X"18",X"18",X"00", + X"3C",X"62",X"72",X"3C",X"4F",X"43",X"3E",X"00",X"3E",X"63",X"63",X"3F",X"03",X"06",X"3C",X"00", + X"1C",X"36",X"63",X"63",X"7F",X"63",X"63",X"00",X"7E",X"63",X"63",X"7E",X"63",X"63",X"7E",X"00", + X"1E",X"33",X"60",X"60",X"60",X"33",X"1E",X"00",X"7C",X"66",X"63",X"63",X"63",X"66",X"7C",X"00", + X"3F",X"30",X"30",X"3E",X"30",X"30",X"3F",X"00",X"7F",X"60",X"60",X"7E",X"60",X"60",X"60",X"00", + X"1F",X"30",X"60",X"67",X"63",X"33",X"1F",X"00",X"63",X"63",X"63",X"7F",X"63",X"63",X"63",X"00", + X"3F",X"0C",X"0C",X"0C",X"0C",X"0C",X"3F",X"00",X"03",X"03",X"03",X"03",X"03",X"63",X"3E",X"00", + X"63",X"66",X"6C",X"78",X"7C",X"6E",X"67",X"00",X"30",X"30",X"30",X"30",X"30",X"30",X"3F",X"00", + X"63",X"77",X"7F",X"7F",X"6B",X"63",X"63",X"00",X"63",X"73",X"7B",X"7F",X"6F",X"67",X"63",X"00", + X"3E",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"7E",X"63",X"63",X"63",X"7E",X"60",X"60",X"00", + X"3E",X"63",X"63",X"63",X"6F",X"66",X"3D",X"00",X"7E",X"63",X"63",X"67",X"7C",X"6E",X"67",X"00", + X"3C",X"66",X"60",X"3E",X"03",X"63",X"3E",X"00",X"3F",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"00", + X"63",X"63",X"63",X"63",X"63",X"63",X"3E",X"00",X"63",X"63",X"63",X"77",X"3E",X"1C",X"08",X"00", + X"63",X"63",X"6B",X"7F",X"7F",X"36",X"22",X"00",X"63",X"77",X"3E",X"1C",X"3E",X"77",X"63",X"00", + X"33",X"33",X"12",X"1E",X"0C",X"0C",X"0C",X"00",X"7F",X"07",X"0E",X"1C",X"38",X"70",X"7F",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"06",X"06",X"00",X"00",X"18",X"30",X"30",X"30",X"30",X"30",X"18",X"00", + X"18",X"0C",X"0C",X"0C",X"0C",X"0C",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E", + X"00",X"00",X"00",X"18",X"1C",X"04",X"08",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"0F",X"0E",X"09",X"03",X"06",X"02",X"00",X"F0",X"F0",X"70",X"90",X"C0",X"60",X"20",X"00", + X"00",X"01",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"00",X"80",X"E0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0", + X"07",X"07",X"0F",X"0F",X"0F",X"0F",X"0F",X"1F",X"F8",X"F8",X"F8",X"F0",X"F0",X"F0",X"F0",X"E0", + X"1F",X"1C",X"10",X"27",X"29",X"01",X"00",X"00",X"E0",X"E0",X"60",X"20",X"A0",X"A0",X"A0",X"00", + X"00",X"01",X"0F",X"0F",X"1F",X"1F",X"1F",X"1F",X"00",X"80",X"E0",X"E0",X"F0",X"F0",X"E0",X"E0", + X"3F",X"3F",X"3F",X"3F",X"7F",X"7F",X"7F",X"7F",X"E0",X"E0",X"C0",X"C0",X"C0",X"C0",X"00",X"C0", + X"10",X"10",X"10",X"10",X"10",X"18",X"1F",X"1F",X"08",X"08",X"08",X"08",X"08",X"18",X"F8",X"F8", + X"0F",X"0F",X"07",X"07",X"03",X"03",X"01",X"00",X"F0",X"F0",X"E0",X"E0",X"C0",X"C0",X"80",X"00", + X"00",X"00",X"0F",X"1F",X"1F",X"1F",X"1F",X"1F",X"00",X"00",X"F0",X"F8",X"F8",X"F8",X"F8",X"F8", + X"1F",X"1F",X"1F",X"1F",X"18",X"10",X"10",X"10",X"F8",X"F8",X"F8",X"F8",X"18",X"08",X"08",X"08", + X"04",X"0C",X"0C",X"1E",X"1F",X"0F",X"0F",X"0F",X"02",X"06",X"04",X"04",X"84",X"FC",X"F8",X"F8", + X"0F",X"0F",X"0F",X"0F",X"07",X"02",X"00",X"00",X"F0",X"E0",X"C0",X"80",X"80",X"00",X"00",X"00", + X"00",X"03",X"07",X"0F",X"0F",X"0F",X"0F",X"1F",X"00",X"C0",X"F8",X"FC",X"FC",X"FC",X"FC",X"FC", + X"1F",X"1F",X"37",X"20",X"20",X"20",X"60",X"40",X"F8",X"F8",X"F8",X"F0",X"30",X"10",X"20",X"20", + X"0E",X"09",X"07",X"0F",X"0F",X"0F",X"0E",X"09",X"38",X"C8",X"F0",X"F8",X"F8",X"F8",X"38",X"C8", + X"07",X"07",X"07",X"03",X"01",X"00",X"00",X"00",X"70",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"01",X"07",X"0F",X"00",X"00",X"00",X"00",X"00",X"C0",X"F0",X"F8", + X"0F",X"0F",X"0E",X"09",X"07",X"0F",X"0F",X"0F",X"F8",X"F8",X"38",X"C8",X"F0",X"F8",X"F8",X"F8", + X"00",X"07",X"0F",X"0F",X"1F",X"00",X"1F",X"1D",X"3E",X"DE",X"EC",X"F4",X"F8",X"F8",X"70",X"B0", + X"3F",X"1F",X"1F",X"1F",X"07",X"00",X"00",X"00",X"C0",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"F0", + X"07",X"07",X"0F",X"00",X"1F",X"1F",X"3F",X"3F",X"F8",X"FC",X"FC",X"7C",X"B8",X"D8",X"E0",X"F0", + X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"08",X"06",X"03",X"00",X"00",X"00", + X"00",X"00",X"01",X"0E",X"F0",X"00",X"00",X"00",X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00", + X"10",X"10",X"10",X"10",X"08",X"08",X"08",X"04",X"08",X"08",X"84",X"82",X"40",X"40",X"30",X"0C", + X"00",X"10",X"21",X"C1",X"02",X"02",X"0C",X"30",X"88",X"88",X"00",X"00",X"00",X"10",X"10",X"20", + X"04",X"01",X"01",X"00",X"00",X"00",X"11",X"11",X"0C",X"30",X"40",X"40",X"83",X"84",X"08",X"00", + X"30",X"0C",X"02",X"02",X"41",X"21",X"10",X"10",X"20",X"10",X"10",X"10",X"08",X"08",X"08",X"08", + X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"02",X"00",X"00",X"00",X"0F",X"70",X"80",X"00",X"00", + X"00",X"00",X"00",X"C0",X"06",X"01",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"80",X"F0",X"1E",X"01",X"00",X"00", + X"E0",X"00",X"01",X"0F",X"78",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"10",X"08",X"10",X"08",X"08",X"04",X"04",X"00",X"88",X"88",X"00",X"07",X"80",X"40",X"30",X"08", + X"11",X"11",X"00",X"E0",X"01",X"02",X"0C",X"10",X"08",X"10",X"08",X"10",X"10",X"20",X"20",X"00", + X"00",X"04",X"04",X"08",X"08",X"10",X"08",X"10",X"08",X"30",X"40",X"80",X"07",X"00",X"88",X"88", + X"10",X"0C",X"02",X"01",X"E0",X"00",X"11",X"11",X"00",X"20",X"20",X"10",X"10",X"08",X"10",X"08", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"1E",X"F0",X"80",X"00",X"07", + X"00",X"00",X"80",X"71",X"0F",X"01",X"00",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"02",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"80",X"00",X"18",X"07",X"00",X"00", + X"C0",X"00",X"01",X"00",X"18",X"E0",X"00",X"00",X"40",X"80",X"00",X"00",X"00",X"00",X"00",X"00", + X"11",X"10",X"10",X"10",X"00",X"00",X"00",X"04",X"08",X"88",X"84",X"C3",X"00",X"00",X"20",X"1C", + X"10",X"11",X"21",X"C3",X"00",X"00",X"04",X"31",X"88",X"08",X"08",X"08",X"10",X"10",X"10",X"20", + X"04",X"08",X"08",X"08",X"10",X"10",X"10",X"11",X"1C",X"20",X"00",X"00",X"C3",X"84",X"88",X"08", + X"38",X"04",X"00",X"00",X"C3",X"21",X"11",X"10",X"20",X"10",X"10",X"10",X"08",X"08",X"08",X"88", + X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"00",X"00",X"07",X"18",X"00",X"80",X"00",X"03", + X"00",X"00",X"E0",X"18",X"00",X"01",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40", + X"06",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"0F",X"00",X"80",X"70",X"00",X"01",X"00",X"00", + X"F0",X"00",X"01",X"0E",X"00",X"80",X"00",X"00",X"60",X"00",X"80",X"00",X"00",X"00",X"00",X"00", + X"11",X"11",X"11",X"10",X"10",X"08",X"08",X"08",X"08",X"08",X"04",X"84",X"81",X"60",X"00",X"00", + X"10",X"10",X"20",X"21",X"81",X"06",X"00",X"00",X"88",X"88",X"88",X"08",X"08",X"10",X"10",X"10", + X"08",X"08",X"08",X"10",X"10",X"11",X"11",X"11",X"00",X"00",X"60",X"81",X"84",X"04",X"08",X"08", + X"00",X"00",X"06",X"81",X"21",X"20",X"10",X"10",X"10",X"10",X"10",X"08",X"08",X"88",X"88",X"88", + X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"06",X"00",X"00",X"01",X"00",X"70",X"80",X"00",X"0F", + X"00",X"00",X"80",X"00",X"0E",X"01",X"00",X"F0",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"60", + X"07",X"07",X"07",X"3F",X"23",X"77",X"2F",X"0F",X"E8",X"FC",X"E8",X"F8",X"C0",X"E0",X"F0",X"F0", + X"09",X"01",X"07",X"03",X"03",X"03",X"03",X"01",X"90",X"80",X"E0",X"C0",X"C0",X"C0",X"C0",X"80", + X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"03",X"30",X"60",X"60",X"C0",X"C0",X"80",X"C0",X"C0", + X"13",X"3B",X"13",X"1F",X"07",X"07",X"07",X"07",X"C0",X"C0",X"C4",X"FE",X"E4",X"E0",X"E0",X"E0", + X"1F",X"1F",X"1F",X"3F",X"2F",X"77",X"2F",X"0F",X"A0",X"F0",X"A0",X"E0",X"80",X"E0",X"F0",X"90", + X"1F",X"09",X"09",X"03",X"01",X"00",X"00",X"00",X"80",X"E0",X"E0",X"F0",X"F0",X"F8",X"70",X"20", + X"30",X"18",X"18",X"0C",X"0C",X"06",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"4F",X"EF",X"4F",X"7F",X"1F",X"1F",X"1F",X"1F",X"00",X"00",X"20",X"F0",X"A0",X"80",X"80",X"80", + X"17",X"3F",X"17",X"1F",X"03",X"07",X"0F",X"0F",X"E0",X"E0",X"E0",X"FC",X"C4",X"EE",X"F4",X"F0", + X"09",X"01",X"07",X"03",X"03",X"03",X"03",X"01",X"90",X"80",X"E0",X"C0",X"C0",X"C0",X"C0",X"80", + X"0C",X"06",X"06",X"03",X"03",X"01",X"03",X"03",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"C0", + X"03",X"03",X"43",X"7F",X"47",X"07",X"07",X"07",X"C8",X"DC",X"C8",X"F8",X"E0",X"E0",X"E0",X"E0", + X"01",X"01",X"09",X"1F",X"09",X"07",X"0F",X"09",X"FA",X"FF",X"FA",X"FE",X"F0",X"E0",X"E0",X"F0", + X"01",X"07",X"07",X"0F",X"0F",X"1F",X"0E",X"04",X"F8",X"90",X"90",X"C0",X"80",X"00",X"00",X"00", + X"03",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"C0",X"C0",X"60",X"F0",X"F0", + X"04",X"0E",X"04",X"07",X"01",X"01",X"01",X"01",X"F0",X"F0",X"F2",X"FF",X"FA",X"F8",X"F8",X"F8", + X"8C",X"08",X"DD",X"CB",X"0A",X"76",X"28",X"05",X"CD",X"E7",X"31",X"28",X"0F",X"01",X"04",X"00", + X"21",X"11",X"39",X"11",X"15",X"39",X"ED",X"B0",X"DD",X"CB",X"09",X"C6",X"DD",X"CB",X"0E",X"5E", + X"20",X"C7",X"CD",X"F9",X"18",X"28",X"C5",X"18",X"62",X"DD",X"CB",X"0E",X"E6",X"CD",X"49",X"1F", + X"DA",X"F6",X"11",X"EF",X"3A",X"CA",X"DD",X"11",X"CD",X"0D",X"19",X"0E",X"01",X"CD",X"C0",X"2D", + X"0E",X"13",X"DD",X"CB",X"0F",X"56",X"20",X"1E",X"21",X"FB",X"0C",X"CD",X"30",X"00",X"38",X"14", + X"DD",X"CB",X"09",X"D6",X"CD",X"0D",X"19",X"0E",X"00",X"CD",X"D8",X"18",X"0E",X"82",X"CD",X"C0", + X"2D",X"C3",X"8C",X"08",X"0E",X"07",X"CD",X"73",X"24",X"2E",X"2D",X"41",X"2B",X"DD",X"CB",X"0F", + X"56",X"28",X"08",X"21",X"FB",X"0C",X"CD",X"30",X"00",X"28",X"D5",X"0E",X"11",X"CD",X"73",X"19", + X"18",X"15",X"DD",X"CB",X"0E",X"66",X"20",X"0F",X"CD",X"F9",X"18",X"16",X"E1",X"CD",X"83",X"1C", + X"DD",X"CB",X"09",X"D6",X"C3",X"1D",X"12",X"0E",X"01",X"CD",X"C0",X"2D",X"16",X"E2",X"CD",X"83", + X"1C",X"DD",X"CB",X"09",X"F6",X"DD",X"CB",X"09",X"D6",X"C3",X"1C",X"10",X"2A",X"37",X"39",X"DD", + X"CB",X"76",X"66",X"C2",X"2C",X"12",X"E5",X"CD",X"E5",X"04",X"E1",X"22",X"37",X"39",X"DD",X"CB", + X"0A",X"6E",X"20",X"E1",X"DD",X"36",X"0C",X"07",X"DD",X"CB",X"0A",X"76",X"28",X"05",X"0E",X"6B", + X"CD",X"56",X"2B",X"0E",X"6D",X"CD",X"56",X"2B",X"0E",X"02",X"CD",X"59",X"1A",X"CD",X"B8",X"34", + X"CD",X"E3",X"18",X"28",X"C0",X"EF",X"2C",X"28",X"14",X"CD",X"F1",X"34",X"CD",X"9E",X"33",X"CD", + X"E3",X"18",X"28",X"B1",X"EF",X"2C",X"38",X"F1",X"CD",X"E3",X"18",X"38",X"E8",X"CD",X"8F",X"31", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7C",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"7C",X"7C",X"00",X"00",X"00",X"00",X"00",X"00",X"7C",X"7C",X"7C",X"00",X"00",X"00",X"00",X"00", + X"7C",X"7C",X"7C",X"7C",X"00",X"00",X"00",X"00",X"7C",X"7C",X"7C",X"7C",X"7C",X"00",X"00",X"00", + X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"00",X"00",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"00", + X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"7C",X"CB",X"0A",X"5E",X"20",X"05",X"16",X"49",X"CD", + X"83",X"1C",X"DD",X"7E",X"07",X"CD",X"21",X"00",X"18",X"1F",X"26",X"48",X"4B",X"B3",X"9D",X"CB", + X"77",X"28",X"3C",X"DD",X"CB",X"08",X"F6",X"DD",X"CB",X"09",X"EE",X"CD",X"49",X"1F",X"28",X"48", + X"21",X"8F",X"14",X"CD",X"61",X"14",X"28",X"C2",X"21",X"9A",X"14",X"CD",X"61",X"14",X"28",X"BA", + X"CD",X"49",X"1F",X"28",X"33",X"EF",X"24",X"28",X"25",X"CD",X"22",X"1E",X"28",X"25",X"EF",X"28", + X"28",X"02",X"37",X"DF",X"CD",X"46",X"13",X"EF",X"29",X"DF",X"CD",X"5E",X"14",X"28",X"9B",X"AF", + X"C3",X"31",X"22",X"1E",X"08",X"18",X"02",X"1E",X"FF",X"CD",X"15",X"20",X"18",X"EC",X"CD",X"BA", + X"1F",X"18",X"E7",X"CD",X"0D",X"20",X"18",X"E2",X"DD",X"CB",X"08",X"FE",X"0E",X"02",X"CD",X"73", + X"24",X"30",X"2F",X"33",X"0B",X"0E",X"11",X"CD",X"73",X"19",X"CD",X"04",X"20",X"18",X"CB",X"DD", + X"CB",X"08",X"56",X"20",X"1C",X"DD",X"CB",X"08",X"C6",X"DD",X"CB",X"0A",X"5E",X"20",X"12",X"DD", + X"7E",X"03",X"E6",X"0F",X"20",X"06",X"DD",X"CB",X"09",X"6E",X"28",X"05",X"16",X"29",X"CD",X"83", + X"1C",X"CD",X"F3",X"1F",X"18",X"A4",X"CD",X"15",X"25",X"18",X"CF",X"CD",X"46",X"13",X"CD",X"3F", + X"20",X"EF",X"2C",X"38",X"06",X"CD",X"46",X"13",X"CD",X"5C",X"20",X"EF",X"5D",X"DF",X"18",X"8A", + X"CD",X"49",X"1F",X"DF",X"DD",X"CB",X"08",X"FE",X"0E",X"0A",X"CD",X"73",X"24",X"0A",X"09",X"08", + X"01",X"0E",X"08",X"11",X"68",X"84",X"92",X"A1",X"E0",X"20",X"10",X"2C",X"43",X"91",X"0A",X"21", + X"92",X"85",X"48",X"21",X"12",X"0C",X"02",X"01",X"11",X"0A",X"92",X"04",X"22",X"5E",X"40",X"80", + X"19",X"26",X"40",X"92",X"A5",X"88",X"80",X"94",X"00",X"E8",X"34",X"02",X"09",X"91",X"22",X"42", + X"AA",X"41",X"50",X"2D",X"02",X"04",X"04",X"03",X"24",X"54",X"8A",X"04",X"18",X"60",X"80",X"80", + X"0C",X"13",X"20",X"45",X"4A",X"91",X"80",X"89",X"C0",X"30",X"8C",X"04",X"22",X"12",X"49",X"11", + X"92",X"44",X"2A",X"11",X"20",X"16",X"09",X"00",X"29",X"02",X"22",X"44",X"88",X"10",X"90",X"60", + X"00",X"00",X"00",X"01",X"03",X"04",X"02",X"00",X"00",X"00",X"00",X"80",X"C0",X"20",X"40",X"04", + X"01",X"00",X"04",X"40",X"80",X"1B",X"24",X"00",X"80",X"00",X"20",X"42",X"00",X"A2",X"5C",X"00", + X"00",X"00",X"00",X"01",X"03",X"04",X"02",X"00",X"00",X"00",X"00",X"80",X"C0",X"20",X"40",X"00", + X"01",X"00",X"00",X"04",X"01",X"4B",X"10",X"00",X"80",X"00",X"00",X"40",X"00",X"66",X"92",X"00", + X"00",X"07",X"08",X"11",X"0F",X"04",X"22",X"70",X"00",X"E0",X"10",X"88",X"F0",X"20",X"44",X"0E", + X"F9",X"FC",X"F0",X"E0",X"F1",X"F1",X"DF",X"80",X"9F",X"3F",X"0F",X"07",X"8F",X"8F",X"FB",X"01", + X"03",X"04",X"09",X"14",X"63",X"A4",X"9C",X"42",X"B0",X"50",X"0C",X"B2",X"45",X"3A",X"C5",X"11", + X"4A",X"24",X"43",X"2D",X"42",X"28",X"15",X"02",X"8A",X"66",X"19",X"85",X"EA",X"14",X"60",X"80", + X"0C",X"13",X"2A",X"15",X"24",X"A2",X"A2",X"99",X"D0",X"28",X"54",X"24",X"AB",X"29",X"52",X"49", + X"4C",X"95",X"4A",X"29",X"40",X"2A",X"15",X"00",X"15",X"91",X"6A",X"44",X"48",X"30",X"90",X"60", + X"01",X"06",X"28",X"57",X"A1",X"98",X"66",X"51",X"40",X"A8",X"14",X"42",X"B4",X"C2",X"24",X"52", + X"88",X"A3",X"5C",X"A2",X"4D",X"30",X"0A",X"0D",X"42",X"39",X"25",X"C6",X"28",X"90",X"20",X"C0", + X"06",X"09",X"0C",X"12",X"22",X"56",X"89",X"A8",X"00",X"A8",X"54",X"02",X"94",X"52",X"A9",X"32", + X"92",X"4A",X"94",X"D5",X"24",X"2A",X"14",X"0B",X"99",X"4A",X"4A",X"24",X"A8",X"54",X"C8",X"30", + X"00",X"00",X"60",X"F0",X"70",X"38",X"18",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"60",X"00", + X"79",X"70",X"20",X"02",X"00",X"01",X"03",X"00",X"72",X"3E",X"1C",X"8C",X"C4",X"90",X"88",X"84", + X"84",X"14",X"48",X"08",X"28",X"88",X"10",X"50",X"8C",X"24",X"08",X"50",X"90",X"08",X"58",X"04", + X"89",X"22",X"04",X"54",X"4A",X"82",X"26",X"04",X"15",X"22",X"82",X"0A",X"05",X"A1",X"45",X"01", + X"2C",X"84",X"08",X"28",X"88",X"06",X"2A",X"01",X"90",X"50",X"28",X"08",X"28",X"C8",X"14",X"84", + X"50",X"10",X"B0",X"10",X"20",X"60",X"A0",X"10",X"4A",X"06",X"94",X"04",X"58",X"28",X"10",X"90", + X"84",X"20",X"02",X"90",X"4A",X"04",X"91",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"DD",X"CB",X"09",X"46",X"CD",X"BF",X"26",X"CD",X"09",X"27",X"DD",X"CB",X"09",X"66",X"CD",X"BF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"40",X"40",X"40",X"40",X"80",X"80",X"80",X"FF", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"10",X"10",X"10",X"20",X"20",X"20",X"20", + X"04",X"04",X"04",X"04",X"08",X"08",X"08",X"08",X"20",X"20",X"40",X"40",X"40",X"80",X"80",X"80", + X"04",X"08",X"08",X"08",X"10",X"10",X"10",X"20",X"00",X"00",X"00",X"00",X"00",X"C0",X"38",X"07", + X"00",X"00",X"80",X"70",X"0E",X"01",X"00",X"00",X"E0",X"1C",X"03",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"C0",X"38",X"07",X"00",X"00",X"80",X"70",X"0E",X"01",X"00",X"00", + X"E0",X"1C",X"03",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF", + X"80",X"40",X"20",X"10",X"08",X"04",X"02",X"01",X"80",X"40",X"20",X"10",X"08",X"04",X"02",X"01", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"C0",X"30",X"0C",X"03", + X"C0",X"30",X"0C",X"03",X"00",X"00",X"00",X"00",X"FF",X"FE",X"FC",X"F8",X"F0",X"F8",X"FC",X"FF", + X"80",X"C0",X"E0",X"F0",X"F8",X"FC",X"FE",X"FF",X"01",X"01",X"01",X"02",X"02",X"02",X"04",X"04", + X"E0",X"1C",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"70",X"0E",X"01",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"C0",X"38",X"07",X"4F",X"41",X"79",X"A7",X"28",X"EF",X"3E",X"20", + X"77",X"23",X"10",X"FC",X"C9",X"3A",X"06",X"00",X"5F",X"C6",X"10",X"CD",X"D0",X"26",X"3A",X"07", + X"00",X"93",X"4F",X"11",X"18",X"39",X"E5",X"21",X"13",X"39",X"CD",X"EA",X"27",X"E1",X"A7",X"C8", + X"4F",X"06",X"00",X"EB",X"ED",X"B0",X"EB",X"C9",X"11",X"17",X"39",X"E5",X"0E",X"04",X"21",X"15", + X"39",X"CD",X"EA",X"27",X"E1",X"18",X"02",X"3E",X"22",X"4F",X"E6",X"1F",X"C3",X"07",X"01",X"2A", + X"47",X"39",X"3E",X"84",X"5E",X"BB",X"C8",X"23",X"56",X"ED",X"53",X"11",X"39",X"23",X"22",X"47", + X"39",X"21",X"7F",X"39",X"3E",X"09",X"11",X"01",X"28",X"CD",X"FF",X"26",X"3A",X"11",X"39",X"57", + X"3E",X"E1",X"CD",X"1A",X"27",X"36",X"20",X"23",X"E5",X"11",X"0E",X"00",X"21",X"0A",X"28",X"3A", + X"11",X"39",X"D6",X"3F",X"28",X"15",X"47",X"19",X"7E",X"FE",X"04",X"28",X"07",X"A7",X"20",X"09", + X"05",X"23",X"18",X"F4",X"21",X"43",X"29",X"18",X"02",X"10",X"EC",X"7B",X"EB",X"E1",X"CD",X"FF", + X"26",X"E5",X"21",X"07",X"00",X"7E",X"2B",X"96",X"4F",X"2B",X"2B",X"11",X"40",X"39",X"3A",X"12", + X"39",X"A7",X"ED",X"52",X"EB",X"06",X"04",X"BE",X"28",X"14",X"38",X"11",X"23",X"10",X"F8",X"2B", + X"96",X"19",X"2B",X"91",X"28",X"03",X"30",X"FB",X"81",X"1E",X"23",X"18",X"05",X"2B",X"96",X"19", + X"1E",X"2A",X"86",X"E1",X"CD",X"D7",X"26",X"01",X"0A",X"00",X"B7",X"ED",X"42",X"73",X"23",X"C3", + X"AE",X"26",X"3A",X"07",X"39",X"A1",X"28",X"0C",X"79",X"FE",X"08",X"0E",X"72",X"28",X"02",X"0E", + X"44",X"CD",X"56",X"2B",X"3C",X"C9",X"2A",X"17",X"39",X"BF",X"DD",X"CB",X"08",X"56",X"C8",X"AF", + X"BD",X"20",X"05",X"BC",X"C8",X"3C",X"BC",X"C8",X"21",X"7F",X"39",X"0E",X"05",X"CD",X"DA",X"26", + X"CD",X"09",X"27",X"CD",X"E6",X"26",X"C3",X"AE",X"26",X"1A",X"B9",X"30",X"01",X"4F",X"91",X"12", + X"5E",X"23",X"56",X"79",X"E5",X"69",X"26",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"38",X"38",X"38",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"1E",X"3F",X"3F", + X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"01",X"07",X"0F",X"1C",X"38",X"30",X"00",X"00",X"FC",X"FE",X"FF",X"71",X"61",X"E0", + X"00",X"00",X"00",X"00",X"00",X"81",X"C3",X"C3",X"00",X"00",X"00",X"00",X"E0",X"F0",X"F8",X"39", + X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"00",X"08",X"38",X"3C",X"DC",X"CE", + X"00",X"1C",X"18",X"38",X"38",X"38",X"39",X"38",X"3C",X"FC",X"E0",X"E0",X"E4",X"FC",X"F8",X"E0", + X"31",X"30",X"30",X"30",X"30",X"30",X"31",X"33",X"E0",X"E0",X"E0",X"E0",X"E0",X"E0",X"C0",X"80", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"70",X"70",X"70",X"30",X"39",X"1D",X"0D", + X"E0",X"E1",X"E1",X"C3",X"FE",X"FC",X"F0",X"C0",X"C7",X"9E",X"8F",X"0F",X"0C",X"1C",X"18",X"18", + X"18",X"18",X"F8",X"F0",X"70",X"30",X"30",X"61",X"3F",X"30",X"30",X"60",X"60",X"E0",X"C0",X"C0", + X"0C",X"1F",X"1F",X"3B",X"30",X"70",X"70",X"E0",X"00",X"00",X"80",X"C0",X"C0",X"E0",X"E0",X"E0", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"03",X"03", + X"07",X"1F",X"7F",X"F8",X"D8",X"9C",X"9C",X"0E",X"81",X"E1",X"F0",X"78",X"38",X"38",X"38",X"38", + X"CF",X"C7",X"C7",X"E3",X"E1",X"E1",X"60",X"70",X"38",X"38",X"A8",X"F0",X"F0",X"F0",X"F0",X"F0", + X"60",X"60",X"60",X"60",X"60",X"70",X"70",X"76",X"3F",X"3E",X"3E",X"37",X"33",X"31",X"30",X"30", + X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"01",X"03",X"03",X"03",X"03",X"06",X"04",X"00",X"80",X"80",X"80",X"80",X"80",X"00",X"00",X"00", + X"38",X"30",X"30",X"70",X"70",X"71",X"01",X"00",X"61",X"E1",X"C3",X"C3",X"C3",X"87",X"86",X"01", + X"C0",X"81",X"81",X"03",X"03",X"07",X"0E",X"0E",X"E1",X"C1",X"C7",X"FF",X"F8",X"60",X"70",X"70", + X"C3",X"C7",X"8C",X"1C",X"38",X"30",X"70",X"70",X"FF",X"01",X"00",X"00",X"00",X"00",X"00",X"00", + X"C0",X"E0",X"70",X"38",X"38",X"3C",X"3C",X"3C",X"00",X"00",X"00",X"00",X"00",X"10",X"38",X"70", + X"03",X"03",X"03",X"03",X"03",X"01",X"00",X"00",X"0E",X"0E",X"0E",X"87",X"87",X"E7",X"F3",X"7B", + X"38",X"70",X"E0",X"E0",X"E0",X"F8",X"3C",X"8F",X"70",X"70",X"30",X"38",X"38",X"38",X"38",X"20", + X"70",X"70",X"30",X"20",X"00",X"00",X"00",X"00",X"3E",X"3E",X"20",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"70",X"30",X"38",X"08",X"00",X"00",X"00",X"00",X"70",X"70",X"38",X"38",X"1C",X"0F",X"07",X"01", + X"00",X"00",X"00",X"00",X"01",X"8F",X"FE",X"F8",X"38",X"38",X"71",X"E3",X"C7",X"0E",X"0C",X"1C", + X"60",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"03",X"01",X"01",X"01",X"01",X"00",X"00",X"00",X"87",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00", + X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"38",X"70",X"F8",X"7C",X"1C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", + X"2C",X"7E",X"4F",X"3C",X"C8",X"E5",X"CD",X"56",X"2B",X"E1",X"23",X"18",X"F4",X"CD",X"4E",X"1A", + X"2A",X"6F",X"39",X"EB",X"CD",X"AE",X"2D",X"C4",X"60",X"2D",X"3E",X"C0",X"CD",X"E5",X"33",X"11", + X"AF",X"3B",X"18",X"63",X"CD",X"7C",X"2D",X"2A",X"73",X"39",X"73",X"23",X"72",X"C9",X"2A",X"9C", + X"37",X"3E",X"67",X"CD",X"E0",X"33",X"2A",X"C0",X"37",X"3E",X"69",X"CD",X"E0",X"33",X"2A",X"61", + X"39",X"3E",X"6D",X"CD",X"E0",X"33",X"CD",X"7C",X"2D",X"ED",X"53",X"61",X"39",X"C9",X"ED",X"5B", + X"6F",X"39",X"2A",X"61",X"39",X"CD",X"60",X"2D",X"3E",X"CD",X"CD",X"E5",X"33",X"22",X"61",X"39", + X"3E",X"C7",X"CD",X"E5",X"33",X"EB",X"3E",X"C9",X"CD",X"E5",X"33",X"18",X"1A",X"18",X"48",X"FD", + X"6E",X"02",X"FD",X"66",X"03",X"2B",X"22",X"5F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"); +begin +process(clk) +begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; +end process; +end architecture; diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/crazy_climber.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/crazy_climber.vhd new file mode 100644 index 00000000..f3941ac8 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/crazy_climber.vhd @@ -0,0 +1,816 @@ +---------------------------------------------------------------------------------- +-- Crazy climber - Dar - June 2018 +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity crazy_climber is +port( + clock_12 : in std_logic; + reset : in std_logic; + video_r : out std_logic_vector(2 downto 0); + video_g : out std_logic_vector(2 downto 0); + video_b : out std_logic_vector(1 downto 0); + video_hb : out std_logic; + video_vb : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + audio_out : out std_logic_vector(15 downto 0); + start2 : in std_logic; + start1 : in std_logic; + coin1 : in std_logic; + right1 : in std_logic; + left1 : in std_logic; + fire1 : in std_logic; + right2 : in std_logic; + left2 : in std_logic; + fire2 : in std_logic +); +end crazy_climber; + +architecture struct of crazy_climber is + +-- clocks +signal clock_12n : std_logic; +signal reset_n : std_logic; + +-- video syncs +signal hsync : std_logic; +signal vsync : std_logic; +signal hblank : std_logic; +signal vblank : std_logic; + +-- global synchronisation +signal ena_pixel : std_logic := '0'; +signal is_sprite : std_logic; +signal sprite : std_logic_vector(2 downto 0); +signal x_tile : std_logic_vector(4 downto 0); +signal y_tile : std_logic_vector(4 downto 0); +signal x_pixel : std_logic_vector(2 downto 0); +signal y_pixel : std_logic_vector(2 downto 0); +signal y_line : std_logic_vector(7 downto 0); + +signal y_sp_bg : std_logic_vector(7 downto 0); +signal y_line_shift : std_logic_vector(7 downto 0); +signal attr_sp : std_logic_vector(7 downto 0); +signal attr_sp_bg : std_logic_vector(7 downto 0); +signal bg_tile_code : std_logic_vector(7 downto 0); + +signal tile_graph_rom_addr : std_logic_vector(12 downto 0); +signal tile_graph_rom_addr_mod: std_logic_vector(11 downto 0); +signal tile_graph_rom_bit0_do : std_logic_vector(7 downto 0); +signal tile_graph_rom_bit1_do : std_logic_vector(7 downto 0); + +signal big_sprite_tile_rom_addr : std_logic_vector(10 downto 0); +signal big_sprite_tile_rom_bit0_do : std_logic_vector(7 downto 0); +signal big_sprite_tile_rom_bit1_do : std_logic_vector(7 downto 0); + +-- background and sprite tiles and graphics +signal tile_code : std_logic_vector(12 downto 0); +signal tile_color : std_logic_vector(3 downto 0); +signal tile_graph1 : std_logic_vector(7 downto 0); +signal tile_graph2 : std_logic_vector(7 downto 0); +signal x_sprite : std_logic_vector(7 downto 0); +signal y_sprite : std_logic_vector(7 downto 0); +signal keep_sprite : std_logic; + +signal tile_color_r : std_logic_vector(3 downto 0); +signal tile_graph1_r : std_logic_vector(7 downto 0); +signal tile_graph2_r : std_logic_vector(7 downto 0); + +signal pixel_color : std_logic_vector(5 downto 0); +signal pixel_color_r : std_logic_vector(5 downto 0); + +signal sprite_pixel_color : std_logic_vector(5 downto 0); +signal do_palette : std_logic_vector(7 downto 0); + +signal addr_ram_sprite : std_logic_vector(8 downto 0); +signal is_sprite_r : std_logic; + +type ram_256x6 is array(0 to 255) of std_logic_vector(5 downto 0); +signal ram_sprite : ram_256x6; + +-- big sprite tiles and graphics +signal x_big_sprite : std_logic_vector(7 downto 0); +signal y_big_sprite : std_logic_vector(7 downto 0); +signal y_line_big_sprite_shift: std_logic_vector(7 downto 0); +signal attr_big_sprite : std_logic_vector(5 downto 0); + +signal big_sprite_graph1 : std_logic_vector(7 downto 0); +signal big_sprite_graph2 : std_logic_vector(7 downto 0); +signal xy_big_sprite : std_logic_vector(7 downto 0); +signal big_sprite_tile_code : std_logic_vector(7 downto 0); +signal big_sprite_tile_code_r : std_logic_vector(7 downto 0); +signal is_big_sprite_on : std_logic; +signal x_big_sprite_counter : std_logic_vector(7 downto 0); +signal big_sprite_graph1_delay : std_logic_vector(7 downto 0); +signal big_sprite_graph2_delay : std_logic_vector(7 downto 0); + +signal do_big_sprite_palette : std_logic_vector(7 downto 0); +signal big_sprite_pixel_color : std_logic_vector(4 downto 0); +signal big_sprite_pixel_color_r: std_logic_vector(4 downto 0); + +signal video_mux : std_logic_vector(7 downto 0); + +-- Z80 interface +signal cpu_clock : std_logic; +signal cpu_wr_n : std_logic; +signal cpu_addr : std_logic_vector(15 downto 0); +signal cpu_do : std_logic_vector(7 downto 0); +signal cpu_di : std_logic_vector(7 downto 0); +signal cpu_mreq_n : std_logic; +signal cpu_m1_n : std_logic; +signal cpu_int_n : std_logic; +signal cpu_iorq_n : std_logic; +signal cpu_di_mem : std_logic_vector(7 downto 0); +signal cpu_addr_mod : std_logic_vector(9 downto 0); + +-- misc +signal reg4_we_n : std_logic; +signal reg5_we_n : std_logic; +signal reg6_we_n : std_logic; +signal raz_int_n : std_logic; + +signal prog_do : std_logic_vector(7 downto 0); +signal wram1_do : std_logic_vector(7 downto 0); +signal wram1_we : std_logic; +signal wram2_do : std_logic_vector(7 downto 0); +signal wram2_we : std_logic; + +signal tile_ram_addr : std_logic_vector(9 downto 0); +signal tile_ram_do : std_logic_vector(7 downto 0); +signal tile_ram_we : std_logic; +signal tile_ram_cs : std_logic; + +signal color_ram_addr: std_logic_vector(9 downto 0); +signal color_ram_do : std_logic_vector(7 downto 0); +signal color_ram_we : std_logic; +signal color_ram_cs : std_logic; + +signal big_sprite_ram_addr : std_logic_vector(7 downto 0); +signal big_sprite_ram_do : std_logic_vector(7 downto 0); +signal big_sprite_ram_we : std_logic; +signal big_sprite_ram_cs : std_logic; + +-- data bus from AY-3-8910 +signal ym_8910_data : std_logic_vector(7 downto 0); + +-- player I/O +signal player1 : std_logic_vector(7 downto 0); +signal player2 : std_logic_vector(7 downto 0); +signal coins : std_logic_vector(7 downto 0); + +signal video_i : std_logic_vector (7 downto 0); + +-- decryption tool +signal prog_do_decrypted : std_logic_vector(7 downto 0); +signal index : integer range 0 to 127; +signal index_vector : std_logic_vector(6 downto 0); +type convtable_t is array(0 to 127) of std_logic_vector(7 downto 0); +signal convtable: convtable_t:= ( + X"44",X"14",X"54",X"10",X"11",X"41",X"05",X"50",X"51",X"00",X"40",X"55",X"45",X"04",X"01",X"15", + X"44",X"10",X"15",X"55",X"00",X"41",X"40",X"51",X"14",X"45",X"11",X"50",X"01",X"54",X"04",X"05", + X"45",X"10",X"11",X"44",X"05",X"50",X"51",X"04",X"41",X"14",X"15",X"40",X"01",X"54",X"55",X"00", + X"04",X"51",X"45",X"00",X"44",X"10",X"ff",X"55",X"11",X"54",X"50",X"40",X"05",X"ff",X"14",X"01", + X"54",X"51",X"15",X"45",X"44",X"01",X"11",X"41",X"04",X"55",X"50",X"ff",X"00",X"10",X"40",X"ff", + X"ff",X"54",X"14",X"50",X"51",X"01",X"ff",X"40",X"41",X"10",X"00",X"55",X"05",X"44",X"11",X"45", + X"51",X"04",X"10",X"ff",X"50",X"40",X"00",X"ff",X"41",X"01",X"05",X"15",X"11",X"14",X"44",X"54", + X"ff",X"ff",X"54",X"01",X"15",X"40",X"45",X"41",X"51",X"04",X"50",X"05",X"11",X"44",X"10",X"14"); + +begin + +clock_12n <= not clock_12; +reset_n <= not reset; + + +----------------------- +-- Enable pixel counter +----------------------- +process(clock_12) +begin + if rising_edge(clock_12) then + ena_pixel <= not ena_pixel; + end if; +end process; + +------------------ +-- video output +------------------ +video_mux <= do_palette when is_big_sprite_on = '0' else do_big_sprite_palette; + +process(clock_12) +begin + if rising_edge(clock_12) then + if ena_pixel = '1' then + if hblank = '0' then + video_i <= video_mux; + else + video_i <= (others => '0'); + end if; + end if; + end if; +end process; + +video_r <= video_i(2 downto 0); +video_g <= video_i(5 downto 3); +video_b <= video_i(7 downto 6); +video_hb <= hblank; +video_vb <= vblank; +video_hs <= hsync; +video_vs <= vsync; + +------------------ +-- player controls +------------------ +player1 <= right1 & left1 & "00000" & fire1; +player2 <= right2 & left2 & "00000" & fire2; +coins <= ("0001" & start2 & start1 & '0' & coin1); -- upright cabinet + +----------------------- +-- cpu write addressing +----------------------- +wram2_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "01100" else '0'; -- 6000-67ff (ckong) +--wram1_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "01101" else '0'; -- 6800-6bff (ckong) +wram1_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "10000" else '0'; -- 8000-87ff (cclimber) + +tile_ram_cs <= '1' when cpu_addr(15 downto 11) = "10010" else '0'; -- 9000-93ff mirror 9400-97ff +color_ram_cs <= '1' when cpu_addr(15 downto 11) = "10011" else '0'; -- 9800-9bff +big_sprite_ram_cs <= '1' when cpu_addr(15 downto 8) = "10001000" else '0'; -- 8800-88ff + +reg4_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "10100" else '1'; +reg5_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "10101" else '1'; +reg6_we_n <= '0' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "10110" else '1'; + +--------------------------- +-- enable/disable interrupt +--------------------------- +process (cpu_clock) +begin + if falling_edge(cpu_clock) then + if cpu_addr(2 downto 0) = "000" and reg4_we_n = '0' then + raz_int_n <= cpu_do(0); + end if; +end if; +end process; + +------------------------------- +-- latch interrupt at last line +------------------------------- +process(clock_12, raz_int_n) +begin + if raz_int_n = '0' then + cpu_int_n <= '1'; + else + if rising_edge(clock_12) then + if y_tile = "11100" and y_pixel = "000" then + cpu_int_n <= '0'; + end if; + end if; + end if; +end process; + +------------------------------------ +-- mux cpu data mem read and io read +------------------------------------ +index_vector <= prog_do(7) & prog_do(1) & cpu_addr(0) & prog_do(6) & prog_do(4) & prog_do(2) & prog_do(0); +index <= to_integer(unsigned(index_vector)); + +with cpu_m1_n select + prog_do_decrypted <= + prog_do when '1', + (prog_do and X"AA") or convtable(index) when others; + +with cpu_addr(15 downto 11) select + cpu_di_mem <= + prog_do when "00000", -- 0000-07ff + prog_do when "00001", -- 0800-0fff + prog_do when "00010", -- 1000-17ff + prog_do when "00011", -- 1800-1fff + prog_do when "00100", -- 2000-27ff + prog_do when "00101", -- 2800-2fff + prog_do when "00110", -- 3000-37ff + prog_do when "00111", -- 3800-3fff + prog_do when "01000", -- 4000-47ff + prog_do when "01001", -- 4800-4fff + prog_do when "01010", -- 5000-57ff + prog_do when "01011", -- 5800-5fff + +-- prog_do_decrypted when "00000", -- 0000-07ff +-- prog_do_decrypted when "00001", -- 0800-0fff +-- prog_do_decrypted when "00010", -- 1000-17ff +-- prog_do_decrypted when "00011", -- 1800-1fff +-- prog_do_decrypted when "00100", -- 2000-27ff +-- prog_do_decrypted when "00101", -- 2800-2fff +-- prog_do_decrypted when "00110", -- 3000-37ff +-- prog_do_decrypted when "00111", -- 3800-3fff +-- prog_do_decrypted when "01000", -- 4000-47ff +-- prog_do_decrypted when "01001", -- 4800-4fff +-- prog_do_decrypted when "01010", -- 5000-57ff +-- prog_do_decrypted when "01011", -- 5800-5fff +-- wram2_do when "01100", -- 6000-67ff ckong only +-- wram1_do when "01101", -- 6800-6fff (ram only at 6800-6bff) ckong only + wram1_do when "10000", -- 8000-87ff (ram only at 8000-83ff) cclimber only + big_sprite_ram_do when "10001", -- 8800-8fff (ram only at 8800-88ff) + tile_ram_do when "10010", -- 9000-97ff (ram only at 9000-93ff) + color_ram_do when "10011", -- 9800-9fff (ram only at 9800-9bff) + player1 when "10100", -- a000 + player2 when "10101", -- a800 + "00000000" when "10110", -- b000 - dip switch (upright cabinet) + coins when "10111", -- b800 + "00000000" when others; + +cpu_di <= ym_8910_data when cpu_iorq_n = '0' else cpu_di_mem; + +------------------------------------------------------ +-- big_sprite_registers (ckong) +------------------------------------------------------ +process(clock_12) +begin + if rising_edge(clock_12) then + if cpu_wr_n = '0' and cpu_mreq_n ='0' then + if cpu_addr = X"98DD" then attr_big_sprite <= cpu_do(5 downto 0); end if; + if cpu_addr = X"98DE" then y_big_sprite <= cpu_do; end if; + if cpu_addr = X"98DF" then x_big_sprite <= cpu_do; end if; + end if; + end if; +end process; + +------------------------------------------------------ +-- cpu addressing mode for color ram 98XX (ckong) +------------------------------------------------------ +cpu_addr_mod <= cpu_addr(10 downto 6) & cpu_addr(4 downto 0); + +------------------------------------- +-- color ram addressing scheme +------------------------------------- +process(clock_12) +begin + if rising_edge(clock_12) then + color_ram_we <= '0'; + case x_pixel is + + when "000" => + if is_sprite = '1' then + color_ram_addr <= "00010" & sprite & "10"; -- y sprite -- ckong (color ram 040-05f) + else + color_ram_addr <= "00000" & x_tile;-- bg scroll column -- ckong (color ram 000-01f) + end if; + if ena_pixel = '1' then y_sp_bg <= color_ram_do; end if; + + when "010" => + if is_sprite = '1' then + color_ram_addr <= "00010" & sprite & "01"; -- color sprite -- ckong (color ram 040-05f) + else + color_ram_addr <= '1' & y_line_shift(7 downto 4) & x_tile; -- color background -- ckong (color ram 040-05f) + end if; + if ena_pixel = '1' then attr_sp_bg <= color_ram_do; end if; + + when "100" => + if is_sprite = '1' then + color_ram_addr <= "00010" & sprite & "00"; -- tile sprite -- ckong (color ram 040-05f) + else + color_ram_addr <= (others => '0'); + end if; + if ena_pixel = '1' then attr_sp <= color_ram_do; end if; + + when "110" => + if is_sprite = '1' then + color_ram_addr <= "00010" & sprite & "11"; -- x sprite -- ckong (color ram 040-05f) + else + color_ram_addr <= (others => '0'); + end if; + if ena_pixel = '1' then x_sprite <= color_ram_do; end if; + + when others => + color_ram_addr <= cpu_addr_mod; + color_ram_we <= not(cpu_wr_n) and not(cpu_mreq_n) and color_ram_cs; + + end case; + end if; +end process; + +------------------------------------- +-- tile ram addressing scheme +------------------------------------- +process(clock_12) +begin + if rising_edge(clock_12) then + tile_ram_we <= '0'; + case x_pixel is + + when "100" => + tile_ram_addr <= y_line_shift(7 downto 3) & x_tile;-- bg tile code + + when others => + tile_ram_addr <= cpu_addr(9 downto 0); + tile_ram_we <= not(cpu_wr_n) and not(cpu_mreq_n) and tile_ram_cs; + + end case; + end if; +end process; + +------------------------------------- +-- tile graph rom addressing scheme +------------------------------------- +process(clock_12) +begin + if rising_edge(clock_12) then + case x_pixel is + + when "100" => + if ena_pixel = '1' then + bg_tile_code <= tile_ram_do; + end if; + + when "110" => + if is_sprite = '1' then + case attr_sp(7 downto 6) is + when "00" => tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & attr_sp(5 downto 0) & ((y_line_shift(3) & x_tile(0) & y_line_shift(2 downto 0)) xor "00000"); + when "01" => tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & attr_sp(5 downto 0) & ((y_line_shift(3) & x_tile(0) & y_line_shift(2 downto 0)) xor "01000"); + when "10" => tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & attr_sp(5 downto 0) & ((y_line_shift(3) & x_tile(0) & y_line_shift(2 downto 0)) xor "10111"); + when others => tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & attr_sp(5 downto 0) & ((y_line_shift(3) & x_tile(0) & y_line_shift(2 downto 0)) xor "11111"); + end case; + else + if attr_sp_bg(7) = '0' then + tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & bg_tile_code & y_line_shift(2 downto 0); + else + tile_graph_rom_addr <= attr_sp_bg(4) & attr_sp_bg(5) & bg_tile_code & not(y_line_shift(2 downto 0)); + end if; + end if; + + when "111" => + if ena_pixel = '1' then + tile_graph1_r <= tile_graph_rom_bit0_do; + tile_graph2_r <= tile_graph_rom_bit1_do; + tile_color_r <= attr_sp_bg(3 downto 0); + + if (is_sprite = '1' and attr_sp(6) = '1') or (is_sprite = '0' and attr_sp_bg(6) = '1' ) then + for i in 0 to 7 loop + tile_graph1_r(i) <= tile_graph_rom_bit0_do(7-i); + tile_graph2_r(i) <= tile_graph_rom_bit1_do(7-i); + end loop; + end if; + + is_sprite_r <= is_sprite; + + keep_sprite <= '0'; + if (y_line_shift(7 downto 4) = "1111") and (x_sprite /= X"00") and (y_sp_bg /= X"00") then + keep_sprite <= '1'; + end if; + + end if; + + when others => null; + + end case; + end if; +end process; + +-------------------------------- +-- sprite/ big sprite y position +-------------------------------- +y_line <= y_tile & y_pixel; +y_line_shift <= std_logic_vector(unsigned(y_line) + unsigned(y_sp_bg) + 1); +y_line_big_sprite_shift <= std_logic_vector(unsigned(y_line) + unsigned(y_big_sprite) + 1); + +------------------------------------------ +-- read/write sprite line-memory addresing +------------------------------------------ +process (clock_12) +begin + if rising_edge(clock_12) then + + if ena_pixel = '1' then + addr_ram_sprite <= addr_ram_sprite + '1'; + end if; + + if is_sprite = '1' and x_pixel = "111" and ena_pixel = '1' and x_tile(0) = '0' then + addr_ram_sprite <= '0' & x_sprite; + end if; + + if is_sprite = '0' and x_pixel = "111" and ena_pixel = '1' and x_tile = "00000" then + addr_ram_sprite <= "000000001"; + end if; + + end if; +end process; + +------------------------------------- +-- read/write sprite line-memory data +------------------------------------- +process (clock_12) +begin + if rising_edge(clock_12) then + if ena_pixel = '0' then + sprite_pixel_color <= ram_sprite(to_integer(unsigned(addr_ram_sprite))); + else + if sprite_pixel_color(1 downto 0) = "00" then + pixel_color_r <= pixel_color; + else + pixel_color_r <= sprite_pixel_color; + end if; + + if is_sprite_r = '1' then + if (keep_sprite = '1') and (addr_ram_sprite(8) = '0') then + if sprite_pixel_color(1 downto 0) = "00" then + ram_sprite(to_integer(unsigned(addr_ram_sprite))) <= pixel_color; + else + ram_sprite(to_integer(unsigned(addr_ram_sprite))) <= sprite_pixel_color; + end if; + + end if; + else + ram_sprite(to_integer(unsigned(addr_ram_sprite))) <= (others => '0'); + end if; + end if; + end if; +end process; + +----------------------------------------------------------------- +-- serialize background/sprite graph to pixel + concatenate color +----------------------------------------------------------------- +pixel_color <= tile_color_r & + tile_graph1_r(to_integer(unsigned(not x_pixel))) & + tile_graph2_r(to_integer(unsigned(not x_pixel))); + +------------------------------------- +-- select big sprite ram tile address +------------------------------------- +with attr_big_sprite(5 downto 4) select +xy_big_sprite <= y_line_big_sprite_shift(6 downto 3) & not(x_big_sprite_counter(6 downto 3)) when "01", + not (y_line_big_sprite_shift(6 downto 3)) & not(x_big_sprite_counter(6 downto 3)) when "11", + y_line_big_sprite_shift(6 downto 3) & (x_big_sprite_counter(6 downto 3)) when "00", + not (y_line_big_sprite_shift(6 downto 3)) & (x_big_sprite_counter(6 downto 3)) when others; + +---------------------------------------- +-- select big sprite graphic rom address +---------------------------------------- +with attr_big_sprite(5) select +big_sprite_tile_rom_addr <= big_sprite_tile_code_r & y_line_big_sprite_shift(2 downto 0) when '0', + big_sprite_tile_code_r & not (y_line_big_sprite_shift(2 downto 0)) when others; + +------------------------------------- +-- big sprite ram addressing scheme +------------------------------------- +process(clock_12) +begin + if rising_edge(clock_12) then + big_sprite_ram_we <= '0'; + case x_pixel is + + when "000" => + big_sprite_ram_addr <= xy_big_sprite; + if ena_pixel = '1' then + big_sprite_tile_code <= big_sprite_ram_do; + end if; + + when others => + big_sprite_ram_addr <= cpu_addr(7 downto 0); + big_sprite_ram_we <= not(cpu_wr_n) and not(cpu_mreq_n) and big_sprite_ram_cs; + + end case; + end if; +end process; + +------------------------------------ +-- big sprite tile graph rom reading +------------------------------------- +process(clock_12) +begin + if rising_edge(clock_12) then + + if ena_pixel = '1' then + x_big_sprite_counter <= x_big_sprite_counter + '1'; + end if; + + if is_sprite = '1' and sprite = "110" and ena_pixel = '1' then + x_big_sprite_counter <= std_logic_vector(to_unsigned(120,8) + unsigned(x_big_sprite and X"F8")); + end if; + + + if x_big_sprite_counter(2 downto 0) = "111" and ena_pixel = '1' then + big_sprite_tile_code_r <= big_sprite_tile_code; + + big_sprite_graph1 <= big_sprite_tile_rom_bit0_do; + big_sprite_graph2 <= big_sprite_tile_rom_bit1_do; + if attr_big_sprite(4) = '0' then + for i in 0 to 7 loop + big_sprite_graph1(i) <= big_sprite_tile_rom_bit0_do(7-i); + big_sprite_graph2(i) <= big_sprite_tile_rom_bit1_do(7-i); + end loop; + end if; + + end if; + + end if; +end process; + +----------------------------------------------------------------- +-- serialize big sprite graph to pixel + concatenate color +-- clip big sprite display +----------------------------------------------------------------- +process(clock_12) +begin + if rising_edge(clock_12) then + if ena_pixel = '1' then + big_sprite_graph1_delay <= big_sprite_graph1_delay(6 downto 0) & big_sprite_graph1(to_integer(unsigned(x_big_sprite_counter(2 downto 0)))); + big_sprite_graph2_delay <= big_sprite_graph2_delay(6 downto 0) & big_sprite_graph2(to_integer(unsigned(x_big_sprite_counter(2 downto 0)))); + end if; + end if; +end process; + +big_sprite_pixel_color <= attr_big_sprite(2 downto 0) & + big_sprite_graph1_delay(to_integer(unsigned(not x_big_sprite(2 downto 0)))) & + big_sprite_graph2_delay(to_integer(unsigned(not x_big_sprite(2 downto 0)))) ; + +process (clock_12) +begin + if rising_edge(clock_12) then + big_sprite_pixel_color_r <= big_sprite_pixel_color; + + if big_sprite_pixel_color_r(1 downto 0) /= "00" and y_line_big_sprite_shift(7) = '1' and + x_big_sprite_counter >= (X"1F") and + x_big_sprite_counter < (X"9F") then + is_big_sprite_on <= '1'; + else + is_big_sprite_on <= '0'; + end if; + end if; +end process; + +-- Sync and video counters +video : entity work.video_gen +port map ( + clock_12 => clock_12, + ena_pixel => ena_pixel, + hsync => hsync, + vsync => vsync, + csync => open, + hblank => hblank, + vblank => vblank, + + is_sprite => is_sprite, + sprite => sprite, + x_tile => x_tile, + y_tile => y_tile, + x_pixel => x_pixel, + y_pixel => y_pixel, + + cpu_clock => cpu_clock +); + +-- sprite palette rom +palette : entity work.cclimber_palette +port map ( + addr => pixel_color_r, + clk => clock_12, + data => do_palette +); + +-- big sprite palette rom +big_sprite_palette : entity work.cclimber_big_sprite_palette +port map ( + addr => big_sprite_pixel_color_r, + clk => clock_12, + data => do_big_sprite_palette +); + +-- Z80 +Z80 : entity work.T80s +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => cpu_clock, + WAIT_n => '1', + INT_n => '1', + NMI_n => cpu_int_n, + BUSRQ_n => '1', + M1_n => cpu_m1_n, + MREQ_n => cpu_mreq_n, + IORQ_n => cpu_iorq_n, + RD_n => open, + WR_n => cpu_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu_addr, + DI => cpu_di, + DO => cpu_do +); + + +-- program rom +program : entity work.cclimber_program +port map ( + addr => cpu_addr(14 downto 0), + clk => clock_12n, + data => prog_do +); + +-- working ram1 - 6800-6bff (ckong) +-- working ram1 - 8000-83ff (cclimber) +wram1 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_12n, + we => wram1_we, + addr => cpu_addr( 10 downto 0), + d => cpu_do, + q => wram1_do +); + +---- working ram2 - 6000-67ff (ckong only) +--wram2 : entity work.gen_ram +--generic map( dWidth => 8, aWidth => 11) +--port map( +-- clk => clock_12n, +-- we => wram2_we, +-- addr => cpu_addr( 10 downto 0), +-- d => cpu_do, +-- q => wram2_do +--); + +-- tile_ram - 9000-93ff +tile_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_12n, + we => tile_ram_we, + addr => tile_ram_addr, + d => cpu_do, + q => tile_ram_do +); + +-- color_ram - 9800-9bff (9800-981F = 9820-983f ...) +color_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 10) +port map( + clk => clock_12n, + we => color_ram_we, + addr => color_ram_addr, + d => cpu_do, + q => color_ram_do +); + +-- big_sprite_tile_ram - 8800-88ff +big_sprite_tile_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 8) +port map( + clk => clock_12n, + we => big_sprite_ram_we, + addr => big_sprite_ram_addr, + d => cpu_do, + q => big_sprite_ram_do +); + +-- sprite and background graphics rom +tile_graph_rom_addr_mod <= tile_graph_rom_addr(12) & tile_graph_rom_addr(10 downto 0); + +tile_bit0 : entity work.cclimber_tile_bit0 +port map ( + addr => tile_graph_rom_addr_mod, + clk => clock_12n, + data => tile_graph_rom_bit0_do +); + +-- sprite and background graphics rom +tile_bit1 : entity work.cclimber_tile_bit1 +port map ( + addr => tile_graph_rom_addr_mod, + clk => clock_12n, + data => tile_graph_rom_bit1_do +); + +-- big sprite graphics rom +big_sprite_tile_bit0 : entity work.cclimber_big_sprite_tile_bit0 +port map ( + addr => big_sprite_tile_rom_addr, + clk => clock_12n, + data => big_sprite_tile_rom_bit0_do +); + +-- big sprite graphics rom +big_sprite_tile_bit1 : entity work.cclimber_big_sprite_tile_bit1 +port map ( + addr => big_sprite_tile_rom_addr, + clk => clock_12n, + data => big_sprite_tile_rom_bit1_do +); + +-- sound +cclimber_sound : entity work.crazy_climber_sound +port map( + cpu_clock => cpu_clock, + cpu_addr => cpu_addr, + cpu_data => cpu_do, + cpu_iorq_n => cpu_iorq_n, + reg4_we_n => reg4_we_n, + reg5_we_n => reg5_we_n, + reg6_we_n => reg6_we_n, + ym_2149_data => ym_8910_data, + sound_sample => audio_out +); +------------------------------------------ +end architecture; \ No newline at end of file diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/crazy_climber_sound.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/crazy_climber_sound.vhd new file mode 100644 index 00000000..5ce5478d --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/crazy_climber_sound.vhd @@ -0,0 +1,140 @@ +--------------------------------------------------------------------------------- +-- Crazy climber sound AY-3-8910 and samples - Dar - June 2018 +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity crazy_climber_sound is +port ( + cpu_clock : in std_logic; + cpu_addr : in std_logic_vector(15 downto 0); + cpu_data : in std_logic_vector( 7 downto 0); + cpu_iorq_n : in std_logic; + reg4_we_n : in std_logic; + reg5_we_n : in std_logic; + reg6_we_n : in std_logic; + ym_2149_data : out std_logic_vector(7 downto 0); + sound_sample : out std_logic_vector(15 downto 0) +); +end crazy_climber_sound; + +architecture struct of crazy_climber_sound is + +signal hdiv : std_logic_vector(1 downto 0); +signal clock_1_5mhz : std_logic; -- 1.50Mhz +signal clock_750khz : std_logic; -- 0.75MHz + +signal ym_2149_audio : std_logic_vector(7 downto 0); + +signal vctr_n : std_logic; +signal scs_n : std_logic; +signal frequency_div : std_logic_vector( 7 downto 0); + +signal frequency_cnt : std_logic_vector( 7 downto 0); +signal frequency_tick : std_logic; +signal sample_volume : std_logic_vector( 7 downto 0); +signal sample_start1 : std_logic_vector( 7 downto 0); +signal sample_start2 : std_logic_vector( 7 downto 0); +signal sample_cnt : std_logic_vector(11 downto 0); +signal sample_rom_addr : std_logic_vector(12 downto 0); +signal sound_data : std_logic_vector( 7 downto 0); +signal sample_data : std_logic_vector(3 downto 0); + +begin + +clock_1_5mhz <= hdiv(0); +clock_750khz <= hdiv(1); + +process(cpu_clock) +begin + if falling_edge(cpu_clock) then + + if hdiv = "11" then + hdiv <= "00"; + else + hdiv <= std_logic_vector(unsigned(hdiv) + 1); + end if; + + if cpu_addr(2 downto 0) = "100" and reg4_we_n = '0' then + vctr_n <= cpu_data(0); + end if; + + if cpu_addr(2 downto 0) = "111" and reg4_we_n = '0' then + scs_n <= cpu_data(0); + end if; + + if reg5_we_n = '0' then + frequency_div<= cpu_data(7 downto 0); + end if; + + if reg6_we_n = '0' then + sample_volume<= cpu_data(7 downto 0); + end if; + + end if; +end process; + +-- Sample machine + +process(clock_750khz) +begin + if rising_edge(clock_750khz) then + if frequency_cnt = "11111111" then + frequency_cnt <= frequency_div; + frequency_tick <= '1'; + else + frequency_cnt <= std_logic_vector(unsigned(frequency_cnt) + 1); + frequency_tick <= '0'; + end if; + end if; +end process; + +process(frequency_tick) +begin + if rising_edge(frequency_tick) then + if vctr_n = '0' then + sample_cnt <= sample_start1(5 downto 0) & "000000"; + else + if sound_data = "01110000" then + sample_cnt <= sample_cnt; + else + sample_cnt <= std_logic_vector(unsigned(sample_cnt) + 1); + end if; + end if; + end if; +end process; + + +sound_sample <= std_logic_vector( unsigned(ym_2149_audio) & unsigned(ym_2149_audio)); + + +ym2149 : entity work.ym2149 +port map ( +-- data bus + I_DA => cpu_data, --: in std_logic_vector(7 downto 0); + O_DA => ym_2149_data, --: out std_logic_vector(7 downto 0); + O_DA_OE_L => open, --: out std_logic; +-- control + I_A9_L => '0', --scs_n, --: in std_logic; + I_A8 => cpu_iorq_n or cpu_addr(3), --: in std_logic; + I_BDIR => not(cpu_iorq_n or cpu_addr(2)), --: in std_logic; + I_BC2 => not(cpu_iorq_n or cpu_addr(1)), --: in std_logic; + I_BC1 => not(cpu_iorq_n or cpu_addr(0)), --: in std_logic; + I_SEL_L => '1', --: in std_logic; +-- audio + O_AUDIO => ym_2149_audio, --: out std_logic_vector(7 downto 0); +-- port a + I_IOA => "11111111", --: in std_logic_vector(7 downto 0); + O_IOA => sample_start1, --: out std_logic_vector(7 downto 0); + O_IOA_OE_L => open, --: out std_logic; +-- port b + I_IOB => "11111111", --: in std_logic_vector(7 downto 0); + O_IOB => sample_start2, --: out std_logic_vector(7 downto 0); + O_IOB_OE_L => open, --: out std_logic; + + ENA => '1', --: in std_logic; -- clock enable for higher speed operation + RESET_L => '1', --: in std_logic; + CLK => clock_1_5mhz --: in std_logic -- note 6 Mhz! +); + +end architecture; \ No newline at end of file diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/dac.sv b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/dac.sv new file mode 100644 index 00000000..5dea333e --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/dac.sv @@ -0,0 +1,33 @@ +// +// PWM DAC +// +// MSBI is the highest bit number. NOT amount of bits! +// +module dac #(parameter MSBI=15, parameter INV=1'b1) +( + output reg DACout, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= INV; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= SigmaLatch[MSBI+2] ^ INV; + end +end + +endmodule diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/gen_ram.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/gen_ram.vhd new file mode 100644 index 00000000..f1a95608 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/hq2x.sv b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/hq2x.sv new file mode 100644 index 00000000..f17732b6 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/hq2x.sv @@ -0,0 +1,454 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output [DWIDTH:0] q +); + + altsyncram altsyncram_component ( + .address_a (wraddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .address_b (rdaddress), + .q_b(q), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({(DWIDTH+1){1'b1}}), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_b = "NONE", + altsyncram_component.address_reg_b = "CLOCK0", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.intended_device_family = "Cyclone III", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = NUMWORDS, + altsyncram_component.numwords_b = NUMWORDS, + altsyncram_component.operation_mode = "DUAL_PORT", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_b = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altsyncram_component.widthad_a = AWIDTH+1, + altsyncram_component.widthad_b = AWIDTH+1, + altsyncram_component.width_a = DWIDTH+1, + altsyncram_component.width_b = DWIDTH+1, + altsyncram_component.width_byteena_a = 1; + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [17:0] rgb1, + input [17:0] rgb2, + output result +); + + wire [5:0] r = rgb1[5:1] - rgb2[5:1]; + wire [5:0] g = rgb1[11:7] - rgb2[11:7]; + wire [5:0] b = rgb1[17:13] - rgb2[17:13]; + wire [6:0] t = $signed(r) + $signed(b); + wire [6:0] gx = {g[5], g}; + wire [7:0] y = $signed(t) + $signed(gx); + wire [6:0] u = $signed(r) - $signed(b); + wire [7:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-24..24) + wire y_inside = (y < 8'h18 || y >= 8'he8); + + // if u is inside (-4, 4) + wire u_inside = (u < 7'h4 || u >= 7'h7c); + + // if v is inside (-6, 6) + wire v_inside = (v < 8'h6 || v >= 8'hfA); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [5:0] A, + input [5:0] B, + input [5:0] C, + output [5:0] O +); + + function [8:0] mul6x3; + input [5:0] op1; + input [2:0] op2; + begin + mul6x3 = 9'd0; + if(op2[0]) mul6x3 = mul6x3 + op1; + if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; + if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [8:0] Amul = mul6x3(A, Op[7:5]); + wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); + wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); + wire [8:0] At = Amul; + wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [9:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[9:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [17:0] E, + input [17:0] A, + input [17:0] B, + input [17:0] D, + input [17:0] F, + input [17:0] H, + output [17:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = 11'bx; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [17:0] Input1 = E; + wire [17:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [17:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); + InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); + InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); +endmodule + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 8 : 17; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [17:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [17:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [17:0] h2rgb; + input [8:0] v; +begin + h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; +end +endfunction + +function [8:0] rgb2h; + input [17:0] v; +begin + rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule // Hq2x diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/mist_io.sv b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/mist_io.sv new file mode 100644 index 00000000..2f41221f --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/mist_io.sv @@ -0,0 +1,530 @@ +// +// mist_io.v +// +// mist_io for the MiST board +// http://code.google.com/p/mist-board/ +// +// Copyright (c) 2014 Till Harbaum +// Copyright (c) 2015-2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK +// (Sorgelig) +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = clk_sys/(PS2DIV*2) +// + +module mist_io #(parameter STRLEN=0, parameter PS2DIV=100) +( + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + // Global clock. It should be around 100MHz (higher is better). + input clk_sys, + + // Global SPI clock from ARM. 24MHz + input SPI_SCK, + + input CONF_DATA0, + input SPI_SS2, + output SPI_DO, + input SPI_DI, + + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, +// output reg [31:0] joystick_2, +// output reg [31:0] joystick_3, +// output reg [31:0] joystick_4, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoublerD, + output ypbpr, + + output reg [31:0] status, + + // SD config + input sd_conf, + input sd_sdhc, + output [1:0] img_mounted, // signaling that new image has been mounted + output reg [31:0] img_size, // size of image in bytes + + // SD block level access + input [31:0] sd_lba, + input [1:0] sd_rd, + input [1:0] sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [8:0] sd_buff_addr, + output reg [7:0] sd_buff_dout, + input [7:0] sd_buff_din, + output reg sd_buff_wr, + + // ps2 keyboard emulation + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + + // ps2 alternative interface. + + // [8] - extended, [9] - pressed, [10] - toggles with every press/release + output reg [10:0] ps2_key = 0, + + // [24] - toggles with every event + output reg [24:0] ps2_mouse = 0, + + // ARM -> FPGA download + input ioctl_ce, + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output reg ioctl_wr = 0, + output reg [24:0] ioctl_addr, + output reg [7:0] ioctl_dout +); + +reg [7:0] but_sw; +reg [2:0] stick_idx; + +reg [1:0] mount_strobe = 0; +assign img_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; +assign scandoublerD = but_sw[4]; +assign ypbpr = but_sw[5]; + +// this variant of user_io is for 8 bit cores (type == a4) only +wire [7:0] core_type = 8'ha4; + +// command byte read by the io controller +wire drive_sel = sd_rd[1] | sd_wr[1]; +wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] }; + +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [9:0] byte_cnt; // counts bytes + +reg spi_do; +assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do; + +reg [7:0] spi_data_out; + +// SPI transmitter +always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt]; + +reg [7:0] spi_data_in; +reg spi_data_ready = 0; + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + reg [6:0] sbuf; + reg [31:0] sd_lba_r; + reg drive_sel_r; + + if(CONF_DATA0) begin + bit_cnt <= 0; + byte_cnt <= 0; + spi_data_out <= core_type; + end + else + begin + bit_cnt <= bit_cnt + 1'd1; + sbuf <= {sbuf[5:0], SPI_DI}; + + // finished reading command byte + if(bit_cnt == 7) begin + if(!byte_cnt) cmd <= {sbuf, SPI_DI}; + + spi_data_in <= {sbuf, SPI_DI}; + spi_data_ready <= ~spi_data_ready; + if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1; + + spi_data_out <= 0; + case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd}) + // reading config string + 8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; + + // reading sd card status + 8'h16: if(byte_cnt == 0) begin + spi_data_out <= sd_cmd; + sd_lba_r <= sd_lba; + drive_sel_r <= drive_sel; + end else if (byte_cnt == 1) begin + spi_data_out <= drive_sel_r; + end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8]; + + // reading sd card write data + 8'h18: spi_data_out <= sd_buff_din; + endcase + end + end +end + +reg [31:0] ps2_key_raw = 0; +wire pressed = (ps2_key_raw[15:8] != 8'hf0); +wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); + +// transfer to clk_sys domain +always@(posedge clk_sys) begin + reg old_ss1, old_ss2; + reg old_ready1, old_ready2; + reg [2:0] b_wr; + reg got_ps2 = 0; + + old_ss1 <= CONF_DATA0; + old_ss2 <= old_ss1; + old_ready1 <= spi_data_ready; + old_ready2 <= old_ready1; + + sd_buff_wr <= b_wr[0]; + if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; + b_wr <= (b_wr<<1); + + if(old_ss2) begin + got_ps2 <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + sd_buff_addr <= 0; + if(got_ps2) begin + if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; + if(cmd == 5) begin + ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]}; + if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed + if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released + if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed + end + end + end + else + if(old_ready2 ^ old_ready1) begin + + if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; + + if(byte_cnt < 2) begin + + if (cmd == 8'h19) sd_ack_conf <= 1; + if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1; + mount_strobe <= 0; + + if(cmd == 5) ps2_key_raw <= 0; + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= spi_data_in; + 8'h02: joystick_0 <= spi_data_in; + 8'h03: joystick_1 <= spi_data_in; +// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in; +// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in; + // store incoming ps2 mouse bytes + 8'h04: begin + got_ps2 <= 1; + case(byte_cnt) + 2: ps2_mouse[7:0] <= spi_data_in; + 3: ps2_mouse[15:8] <= spi_data_in; + 4: ps2_mouse[23:16] <= spi_data_in; + endcase + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + got_ps2 <= 1; + ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + 8'h15: status[7:0] <= spi_data_in; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_buff_dout <= spi_data_in; + b_wr <= 1; + end + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 2) stick_idx <= spi_data_in[2:0]; + else if(byte_cnt == 3) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in; + else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in; + end else if(byte_cnt == 4) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in; + else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in; + end + end + + // notify image selection + 8'h1c: mount_strobe[spi_data_in[0]] <= 1; + + // send image info + 8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in; + + // status, 32bit version + 8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in; + default: ; + endcase + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +// 8 byte fifos to store ps2 bytes +localparam PS2_FIFO_BITS = 3; + +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +// keyboard +reg [7:0] ps2_kbd_fifo[1<= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1; + else ps2_kbd_tx_state <= 0; + end + end +end + +// mouse +reg [7:0] ps2_mouse_fifo[1<= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1; + else ps2_mouse_tx_state <= 0; + end + end +end + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +reg [7:0] data_w; +reg [24:0] addr_w; +reg rclk = 0; + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +reg rdownload = 0; + +// data_io has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS2) begin + reg [6:0] sbuf; + reg [7:0] cmd; + reg [4:0] cnt; + reg [24:0] addr; + + if(SPI_SS2) cnt <= 0; + else begin + // don't shift in last bit. It is evaluated directly + // when writing to ram + if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; + + // count 0-7 8-15 8-15 ... + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + // finished command byte + if(cnt == 7) cmd <= {sbuf, SPI_DI}; + + // prepare/end transmission + if((cmd == UIO_FILE_TX) && (cnt == 15)) begin + // prepare + if(SPI_DI) begin + case(ioctl_index[4:0]) + 1: addr <= 25'h200000; // TRD buffer at 2MB + 2: addr <= 25'h400000; // tape buffer at 4MB + default: addr <= 25'h150000; // boot rom + endcase + rdownload <= 1; + end else begin + addr_w <= addr; + rdownload <= 0; + end + end + + // command 0x54: UIO_FILE_TX + if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin + addr_w <= addr; + data_w <= {sbuf, SPI_DI}; + addr <= addr + 1'd1; + rclk <= ~rclk; + end + + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + end +end + +// transfer to ioctl_clk domain. +// ioctl_index is set before ioctl_download, so it's stable already +always@(posedge clk_sys) begin + reg rclkD, rclkD2; + + if(ioctl_ce) begin + ioctl_download <= rdownload; + + rclkD <= rclk; + rclkD2 <= rclkD; + ioctl_wr <= 0; + + if(rclkD != rclkD2) begin + ioctl_dout <= data_w; + ioctl_addr <= addr_w; + ioctl_wr <= 1; + end + end +end + +endmodule \ No newline at end of file diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/osd.sv b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/osd.sv new file mode 100644 index 00000000..b9181763 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/osd.sv @@ -0,0 +1,194 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd ( + // OSDs pixel clock, should be synchronous to cores pixel clock to + // avoid jitter. + input clk_sys, + + // SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + input [1:0] rotate, //[0] - rotate [1] - left or right + + // VGA signals coming from core + input [5:0] R_in, + input [5:0] G_in, + input [5:0] B_in, + input HSync, + input VSync, + + // VGA signals going to video connector + output [5:0] R_out, + output [5:0] G_out, + output [5:0] B_out +); + +parameter OSD_X_OFFSET = 10'd0; +parameter OSD_Y_OFFSET = 10'd0; +parameter OSD_COLOR = 3'd0; + +localparam OSD_WIDTH = 10'd256; +localparam OSD_HEIGHT = 10'd128; + +// ********************************************************************************* +// spi client +// ********************************************************************************* + +// this core supports only the display related OSD commands +// of the minimig +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself + +// the OSD has its own SPI interface to the io controller +always@(posedge SPI_SCK, posedge SPI_SS3) begin + reg [4:0] cnt; + reg [10:0] bcnt; + reg [7:0] sbuf; + reg [7:0] cmd; + + if(SPI_SS3) begin + cnt <= 0; + bcnt <= 0; + end else begin + sbuf <= {sbuf[6:0], SPI_DI}; + + // 0:7 is command, rest payload + if(cnt < 15) cnt <= cnt + 1'd1; + else cnt <= 8; + + if(cnt == 7) begin + cmd <= {sbuf[6:0], SPI_DI}; + + // lower three command bits are line address + bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; + + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; + end + + // command 0x20: OSDCMDWRITE + if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin + osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; + bcnt <= bcnt + 1'd1; + end + end +end + +// ********************************************************************************* +// video timing and sync polarity anaylsis +// ********************************************************************************* + +// horizontal counter +reg [9:0] h_cnt; +reg [9:0] hs_low, hs_high; +wire hs_pol = hs_high < hs_low; +wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; + +// vertical counter +reg [9:0] v_cnt; +reg [9:0] vs_low, vs_high; +wire vs_pol = vs_high < vs_low; +wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; + +wire doublescan = (dsp_height>350); + +reg ce_pix; +always @(negedge clk_sys) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg hs; + + cnt <= cnt + 1; + hs <= HSync; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(hs && ~HSync) begin + cnt <= 0; + pixsz <= (cnt >> 9) - 1; + pixcnt <= 0; + ce_pix <= 1; + end +end + +always @(posedge clk_sys) begin + reg hsD, hsD2; + reg vsD, vsD2; + + if(ce_pix) begin + // bring hsync into local clock domain + hsD <= HSync; + hsD2 <= hsD; + + // falling edge of HSync + if(!hsD && hsD2) begin + h_cnt <= 0; + hs_high <= h_cnt; + end + + // rising edge of HSync + else if(hsD && !hsD2) begin + h_cnt <= 0; + hs_low <= h_cnt; + v_cnt <= v_cnt + 1'd1; + end else begin + h_cnt <= h_cnt + 1'd1; + end + + vsD <= VSync; + vsD2 <= vsD; + + // falling edge of VSync + if(!vsD && vsD2) begin + v_cnt <= 0; + vs_high <= v_cnt; + end + + // rising edge of VSync + else if(vsD && !vsD2) begin + v_cnt <= 0; + vs_low <= v_cnt; + end + end +end + +// area in which OSD is being displayed +wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; +wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; +wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && + (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +reg [10:0] osd_buffer_addr; +wire [7:0] osd_byte = osd_buffer[osd_buffer_addr]; +reg osd_pixel; + +always @(posedge clk_sys) begin + if(ce_pix) begin + osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5], + rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) : + (doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} : + {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]}; + + osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] : + osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; + end +end + +assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; +assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; +assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; + +endmodule diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.qip b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.qip new file mode 100644 index 00000000..aaef684a --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.v b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.v new file mode 100644 index 00000000..c4b8675a --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/pll.v @@ -0,0 +1,365 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + c1, + c2, + locked); + + input inclk0; + output c0; + output c1; + output c2; + output locked; + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .inclk (sub_wire6), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 52, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 47, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 104, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 47, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 208, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 47, + altpll_component.clk2_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 37037, + altpll_component.intended_device_family = "Cyclone III", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "52" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "104" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "208" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.403847" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.201923" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.100962" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "47" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "47" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "47" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.39200000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.19600000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.09800000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "52" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "47" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "104" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "47" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "208" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "47" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/scandoubler.sv b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/scandoubler.sv new file mode 100644 index 00000000..0213d20c --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/scandoubler.sv @@ -0,0 +1,195 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + input ce_pix_actual, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input line_start, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +assign vs_out = vs_in; + +reg [2:0] phase; +reg [2:0] ce_div; +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +wire ls_in = hs_in | line_start; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + phase <= phase + 1'd1; + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + phase <= phase + 1'd1; + + ce_cnt <= ce_cnt + 1'd1; + if(ce_pix_actual) begin + phase <= 0; + ce_div <= ce_cnt + 1'd1; + ce_cnt <= 0; + req_line_reset <= 0; + end + + if(ls_in) req_line_reset <= 1; + end +end + +reg ce_sd; +always @(*) begin + case(ce_div) + 2: ce_sd = !phase[0]; + 4: ce_sd = !phase[1:0]; + default: ce_sd <= 1; + endcase +end + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <=1024 ? 9 : 10 ) + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4 & ce_sd), + .inputpixel({b_in,g_in,r_in}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h_actual), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h_actual; +always @(*) begin + case(ce_div) + 2: sd_h_actual = sd_h[10:1]; + 4: sd_h_actual = sd_h[10:2]; + default: sd_h_actual = sd_h; + endcase +end + +reg [10:0] sd_h; +reg [1:0] sd_line; +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise,hs_ls; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + + reg hs, hs2, vs, ls; + + if(ce_x1) begin + hs <= hs_in; + ls <= ls_in; + + if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + sd_h <= sd_h + 1'd1; + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + + if(sd_hcnt == hs_ls) sd_h <= 0; + if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; + end +end + +endmodule diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/video_gen.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/video_gen.vhd new file mode 100644 index 00000000..2abe45d1 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/video_gen.vhd @@ -0,0 +1,131 @@ +--------------------------------------------------------------------------------- +-- Video generator - Dar - Feb 2014 +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all,ieee.numeric_std.all; + +entity video_gen is +port( + clock_12 : in std_logic; + ena_pixel : in std_logic; + hsync : out std_logic; + vsync : out std_logic; + csync : out std_logic; + hblank : out std_logic; + vblank : out std_logic; + + is_sprite : out std_logic; + sprite : out std_logic_vector(2 downto 0); + x_tile : out std_logic_vector(4 downto 0); + y_tile : out std_logic_vector(4 downto 0); + x_pixel : out std_logic_vector(2 downto 0); + y_pixel : out std_logic_vector(2 downto 0); + + cpu_clock : out std_logic +); +end video_gen; + +architecture struct of video_gen is +signal hcnt : unsigned (8 downto 0) := to_unsigned(511,9); +signal vcnt : unsigned (8 downto 0) := to_unsigned(511,9); +signal vcnt_r : unsigned (8 downto 0) := to_unsigned(511,9); + +signal hsync0 : std_logic; +signal hsync1 : std_logic; +signal hsync2 : std_logic; + +signal enable_clk : std_logic := '0'; + +begin + +cpu_clock <= not hcnt(0); +is_sprite <= not hcnt(8); +sprite <= std_logic_vector(hcnt(6 downto 4)); +x_tile <= std_logic_vector(hcnt(7 downto 3)); +y_tile <= std_logic_vector(vcnt_r(7 downto 3)); +x_pixel <= std_logic_vector(hcnt(2 downto 0)); +y_pixel <= std_logic_vector(vcnt_r(2 downto 0)); + +hsync <= hsync0; + +-- Compteur horizontal : 511-128+1=384 pixels +-- 128 à 175 : 48 pixels fin de ligne +-- 176 à 255 : 80 pixels debut de ligne +-- 256 à 511 : 256 pixels affichés (32 tiles) + +-- Compteur vertical : 511-248+1=264 lignes +-- 496 à 511 : 16 lignes fin de trame +-- 248 à 271 : 24 lignes debut de trame +-- 272 à 495 : 224 lignes affichées (28 tiles) + +-- Synchro horizontale : hcnt=[176 à 207] (32 pixels) +-- Synchro verticale : vcnt=[248 à 255] ( 8 lignes) + +process(clock_12) +begin + + if rising_edge(clock_12) then + +-- enable_clk <= not enable_clk; +-- cpu_clock <= not hcnt(0); + + if ena_pixel = '1' then + + if hcnt = 511 then + hcnt <= to_unsigned (128,9); + vcnt_r <= vcnt; + else + hcnt <= hcnt + 1; + end if; + + if hcnt = 175 then + if vcnt = 511 then + vcnt <= to_unsigned(248,9); + else + vcnt <= vcnt + 1; + end if; + end if; + + if hcnt = (175+ 0) then hsync0 <= '0'; + elsif hcnt = (175+29) then hsync0 <= '1'; + end if; + + if hcnt = (175) then hsync1 <= '0'; + elsif hcnt = (175+13) then hsync1 <= '1'; + elsif hcnt = (175 +192) then hsync1 <= '0'; + elsif hcnt = (175+13+192) then hsync1 <= '1'; + end if; + + if hcnt = (175) then hsync2 <= '0'; + elsif hcnt = (175-28) then hsync2 <= '1'; + end if; + + if vcnt = 509 then csync <= hsync1; + elsif vcnt = 510 then csync <= hsync1; + elsif vcnt = 511 then csync <= hsync1; + elsif vcnt = 248 then csync <= hsync2; + elsif vcnt = 249 then csync <= hsync2; + elsif vcnt = 250 then csync <= hsync2; + elsif vcnt = 251 then csync <= hsync1; + elsif vcnt = 252 then csync <= hsync1; + elsif vcnt = 253 then csync <= hsync1; + else csync <= hsync0; + end if; + + if vcnt = 511 then vsync <= '0'; + elsif vcnt = 250 then vsync <= '1';-- + end if; + + if hcnt = (127+8+1) then hblank <= '1'; -- +8 = retard du shift_register + 1 pixel-- + elsif hcnt = (255+8+1) then hblank <= '0'; -- +8 = retard du shift_register + 1 pixel-- + end if; + + if vcnt = (495+1+0) then vblank <= '1'; + elsif vcnt = (271+1+1) then vblank <= '0'; + end if; + + end if; + end if; +end process; + +end architecture; \ No newline at end of file diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/video_mixer.sv b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/video_mixer.sv new file mode 100644 index 00000000..79d8ca03 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/video_mixer.sv @@ -0,0 +1,243 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 3 bits per component +// For half depth 6 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 480, + parameter HALF_DEPTH = 1, + + parameter OSD_COLOR = 3'd4, + parameter OSD_X_OFFSET = 10'd0, + parameter OSD_Y_OFFSET = 10'd0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + + // Some systems have multiple resolutions. + // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, + // thus half or qurter resolutions can be used without brake video sync while switching resolutions. + // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. + input ce_pix_actual, + + // OSD SPI interface + input SPI_SCK, + input SPI_SS3, + input SPI_DI, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // 0 = HVSync 31KHz, 1 = CSync 15KHz + input scandoublerD, + + // High quality 2x scaling + input hq2x, + + // YPbPr always uses composite sync + input ypbpr, + + // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) + input ypbpr_full, + input [1:0] rotate, //[0] - rotate [1] - left or right + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // interlace sync. Positive pulses. + input HSync, + input VSync, + + // Falling of this signal means start of informative part of line. + // It can be horizontal blank signal. + // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler + // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. + // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. + // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel + // before first informative pixel. + input line_start, + + // MiST video output signals + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_VS, + output VGA_HS +); + +localparam DWIDTH = HALF_DEPTH ? 2 : 5; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .r_in(R), + .g_in(G), + .b_in(B), + + .hs_out(hs_sd), + .vs_out(vs_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd); +wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd); +wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd); + +generate + if(HALF_DEPTH) begin + wire [5:0] r = mono ? {gt,rt} : {rt,rt}; + wire [5:0] g = mono ? {gt,rt} : {gt,gt}; + wire [5:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [5:0] r = rt; + wire [5:0] g = gt; + wire [5:0] b = bt; + end +endgenerate + +wire hs = (scandoublerD ? HSync : hs_sd); +wire vs = (scandoublerD ? VSync : vs_sd); + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire [5:0] r_out, g_out, b_out; +always @(*) begin + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; + g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; + b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; + end + + 2: begin // reduce 50% = 1/2 + r_out = {1'b0, r[5:1]}; + g_out = {1'b0, g[5:1]}; + b_out = {1'b0, b[5:1]}; + end + + 3: begin // reduce 75% = 1/4 + r_out = {2'b00, r[5:2]}; + g_out = {2'b00, g[5:2]}; + b_out = {2'b00, b[5:2]}; + end + + default: begin + r_out = r; + g_out = g; + b_out = b; + end + endcase +end + +wire [5:0] red, green, blue; +osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd +( + .*, + + .R_in(r_out), + .G_in(g_out), + .B_in(b_out), + .HSync(hs), + .VSync(vs), + .rotate(rotate), + + .R_out(red), + .G_out(green), + .B_out(blue) +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; +assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; +assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; +assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd; +assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; + +endmodule diff --git a/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/ym_2149_linmix.vhd b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/ym_2149_linmix.vhd new file mode 100644 index 00000000..b0573a80 --- /dev/null +++ b/Arcade_MiST/Crazy Climbe Hardware/River Patrol_MiST/rtl/ym_2149_linmix.vhd @@ -0,0 +1,645 @@ +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only +-- accurate for designs where the outputs are buffered and not simply wired together. +-- The ouput level is more complex in that case and requires a larger table. + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8 ; --:= ( +-- "00000000", -- R0 Period Tone A 8bits lsb +-- "00000100", -- R1 Period Tone A 4bits msb +-- "00000000", -- R2 Period Tone B 8bits lsb +-- "00000010", -- R3 Period Tone B 4bits msb +-- "00000000", -- R4 Period Tone C 8bits lsb +-- "00000001", -- R5 Period Tone C 4bits msb +-- "00001000", -- R6 Period Noise 5bits +-- "00111000", -- R7 Mixer Noise CBA 3bits, Tone CBA 3bits +-- "00000111", -- R8 Amplitude A Mode 1bit, Level 4bits +-- "00000111", -- R9 Amplitude B Mode 1bit, Level 4bits +-- "00000111", -- R10 Amplitude C Mode 1bit, Level 4bits +-- "00000000", -- R11 Period Enveloppe 8bits lsb +-- "00000000", -- R12 Period Enveloppe 8bits msb +-- "00000000", -- R13 Shape Enveloppe 4bits +-- "00000000", -- R14 Port A +-- "00000000" -- R15 Port B +-- ); + + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal tone_ena_l : std_logic; + signal tone_src : std_logic; + signal noise_ena_l : std_logic; + signal chan_vol : std_logic_vector(4 downto 0); + + signal dac_amp : std_logic_vector(7 downto 0); + signal audio_mix : std_logic_vector(9 downto 0); + signal audio_final : std_logic_vector(9 downto 0); +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- + -- CLOCKED + -- + p_waddr : process + begin + ---- looks like registers are latches in real chip, but the address is caught at the end of the address state. + wait until rising_edge(CLK); + + if (RESET_L = '0') then + addr <= (others => '0'); + else + if (busctrl_addr = '1') then + addr <= I_DA; + end if; + end if; + end process; + + p_wdata : process + begin + ---- looks like registers are latches in real chip, but the address is caught at the end of the address state. + wait until rising_edge(CLK); + env_reset <= '0'; + + if (RESET_L = '0') then + reg <= (others => (others => '0')); + env_reset <= '1'; + else + env_reset <= '0'; + if (busctrl_we = '1') then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; env_reset <= '1'; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + end if; + end process; + + -- + -- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock. + -- +-- p_waddr : process(reset_l, busctrl_addr) +-- begin +-- -- looks like registers are latches in real chip, but the address is caught at the end of the address state. +-- if (RESET_L = '0') then +-- addr <= (others => '0'); +-- elsif falling_edge(busctrl_addr) then -- yuk +-- addr <= I_DA; +-- end if; +-- end process; +-- +-- p_wdata : process(reset_l, busctrl_we, addr) +-- begin +-- if (RESET_L = '0') then +-- reg <= (others => (others => '0')); +-- elsif falling_edge(busctrl_we) then +-- case addr(3 downto 0) is +-- when x"0" => reg(0) <= I_DA; +-- when x"1" => reg(1) <= I_DA; +-- when x"2" => reg(2) <= I_DA; +-- when x"3" => reg(3) <= I_DA; +-- when x"4" => reg(4) <= I_DA; +-- when x"5" => reg(5) <= I_DA; +-- when x"6" => reg(6) <= I_DA; +-- when x"7" => reg(7) <= I_DA; +-- when x"8" => reg(8) <= I_DA; +-- when x"9" => reg(9) <= I_DA; +-- when x"A" => reg(10) <= I_DA; +-- when x"B" => reg(11) <= I_DA; +-- when x"C" => reg(12) <= I_DA; +-- when x"D" => reg(13) <= I_DA; +-- when x"E" => reg(14) <= I_DA; +-- when x"F" => reg(15) <= I_DA; +-- when others => null; +-- end case; +-- end if; +-- +-- env_reset <= '0'; +-- if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then +-- env_reset <= '1'; +-- end if; +-- end process; + + -- + -- END LATCHED + -- + + p_rdata : process(busctrl_re, addr, reg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer : process(cnt_div, reg, tone_gen_op) + begin + tone_ena_l <= '1'; tone_src <= '1'; + noise_ena_l <= '1'; chan_vol <= "00000"; + case cnt_div(1 downto 0) is + when "00" => + tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0); + noise_ena_l <= reg(7)(3); + when "01" => + tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0); + noise_ena_l <= reg(7)(4); + when "10" => + tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0); + noise_ena_l <= reg(7)(5); + when "11" => null; -- tone gen outputs become valid on this clock + when others => null; + end case; + end process; + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + + chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op); + + chan_amp := (others => '0'); + if (chan_mixed = '1') then + if (chan_vol(4) = '0') then + if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet + chan_amp := "00000"; + else + chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone) + end if; + else + chan_amp := env_vol(4 downto 0); + end if; + end if; + + dac_amp <= x"00"; + case chan_amp is + when "11111" => dac_amp <= x"FF"; + when "11110" => dac_amp <= x"D9"; + when "11101" => dac_amp <= x"BA"; + when "11100" => dac_amp <= x"9F"; + when "11011" => dac_amp <= x"88"; + when "11010" => dac_amp <= x"74"; + when "11001" => dac_amp <= x"63"; + when "11000" => dac_amp <= x"54"; + when "10111" => dac_amp <= x"48"; + when "10110" => dac_amp <= x"3D"; + when "10101" => dac_amp <= x"34"; + when "10100" => dac_amp <= x"2C"; + when "10011" => dac_amp <= x"25"; + when "10010" => dac_amp <= x"1F"; + when "10001" => dac_amp <= x"1A"; + when "10000" => dac_amp <= x"16"; + when "01111" => dac_amp <= x"13"; + when "01110" => dac_amp <= x"10"; + when "01101" => dac_amp <= x"0D"; + when "01100" => dac_amp <= x"0B"; + when "01011" => dac_amp <= x"09"; + when "01010" => dac_amp <= x"08"; + when "01001" => dac_amp <= x"07"; + when "01000" => dac_amp <= x"06"; + when "00111" => dac_amp <= x"05"; + when "00110" => dac_amp <= x"04"; + when "00101" => dac_amp <= x"03"; + when "00100" => dac_amp <= x"03"; + when "00011" => dac_amp <= x"02"; + when "00010" => dac_amp <= x"02"; + when "00001" => dac_amp <= x"01"; + when "00000" => dac_amp <= x"00"; + when others => null; + end case; + + if (cnt_div(1 downto 0) = "10") then + audio_mix <= (others => '0'); + audio_final <= audio_mix; + else + audio_mix <= audio_mix + ("00" & dac_amp); + end if; + + if (RESET_L = '0') then + O_AUDIO(7 downto 0) <= "00000000"; + else + if (audio_final(9) = '0') then + O_AUDIO(7 downto 0) <= audio_final(8 downto 1); + else -- clip + O_AUDIO(7 downto 0) <= x"FF"; + end if; + end if; + end if; + end process; + + p_io_ports : process(reg) + begin + O_IOA <= reg(14); + + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end process; +end architecture RTL; diff --git a/Arcade_MiST/README.txt b/Arcade_MiST/README.txt index 49f66142..582c34eb 100644 --- a/Arcade_MiST/README.txt +++ b/Arcade_MiST/README.txt @@ -17,10 +17,13 @@ Aviable Arcade Cores #Custom Hardware Bagman Berzerk - Crazy Climber Crazy Kong Galaga +#Crazy Climber Hardware + Crazy Climber + River Patrol + #Data East Burger Time Hardware #Setup 1 Burnin Rubber