diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.qsf b/Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.qsf index 64d627a2..3c79563c 100644 --- a/Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.qsf +++ b/Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.qsf @@ -215,5 +215,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" - # ---------------------- set_global_assignment -name VHDL_FILE rtl/spram.vhd set_global_assignment -name SYSTEMVERILOG_FILE rtl/Color_Card.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/HighResCard.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/TTL74LS245.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/TTL74LS373.sv set_global_assignment -name VHDL_FILE rtl/CPLD_74LS245.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/Color_Card.sv b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/Color_Card.sv index de3b09cb..f6a84689 100644 --- a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/Color_Card.sv +++ b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/Color_Card.sv @@ -18,14 +18,10 @@ output [1:0] B assign Synco_n = ~Sync; assign CSDo = CSX_n & CSD_n; -//Note should be "Video ~& Video" + assign R = {Bout[7] & Video & ~Video, Bout[1] & Video}; assign G = {Bout[6] & Video & ~Video, Bout[2] & Video}; assign B = {Bout[5] & Video & ~Video, Bout[3] & Video}; -/* -assign R = {Bout[7], Bout[1]}; -assign G = {Bout[6], Bout[2]}; -assign B = {Bout[5], Bout[3]};*/ wire [7:0] Ain, Bin, Aout, Bout; CPLD_74LS245 IC2 ( diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/HighResCard.sv b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/HighResCard.sv new file mode 100644 index 00000000..acbf2f79 --- /dev/null +++ b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/HighResCard.sv @@ -0,0 +1,78 @@ +module HighResBoard( + input [7:0] Din, + output [7:0] Dout, + input CS0_n, + input CS1_n, + input CS2_n, + input WR_n, + input Clk, + output[10:0] VAin, + output[10:0] VAout +); + +TTL74LS245 IC1( + .OE(CS2_n), + .DIR(1'b0), + .Ain(Din), + .Aout(), + .Bin(), + .Bout() + ); + +TTL74LS373 IC2( + .LE(CS0_n), + .D({Din[4],Din[5],Din[6],1'b0,Din[3],Din[2],Din[1],Din[0]}), + .OE_n(~CS2_n),//inverted test + .Q() +); + +TTL74LS373 IC3( + .LE(CS1_n), + .D({1'b0,1'b0,1'b0,1'b0,1'b0,Din[2],Din[1],Din[0]}), + .OE_n(~CS2_n),//inverted test + .Q() +); + +wire [9:0]addr; +wire ram_we = WR_n | CS2_n; +wire [7:0]din; +wire [7:0]out; +spram #( + .addr_width_g(10), + .data_width_g(8)) +IC4( + .clk_i(Clk), + .we_i(ram_we), + .addr_i(addr), + .data_i(din), + .data_o(out) + ); + +TTL74LS245 IC5( + .OE(~VAin[10]), + .DIR(1'b1), + .Ain(), + .Aout(), + .Bin(), + .Bout() + ); + +TTL74LS245 IC6( + .OE(CS2_n), + .DIR(1'b0), + .Ain(), + .Aout(), + .Bin(), + .Bout() + ); + +TTL74LS245 IC7( + .OE(CS2_n), + .DIR(1'b0), + .Ain(), + .Aout(), + .Bin(), + .Bout() + ); + +endmodule \ No newline at end of file diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS245.sv b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS245.sv new file mode 100644 index 00000000..8a026487 --- /dev/null +++ b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS245.sv @@ -0,0 +1,16 @@ +module TTL74LS245 ( + input OE, + input DIR, + input [7:0] Ain, + output [7:0]Aout, + input [7:0] Bin, + output [7:0]Bout + ); + +always @ (OE, DIR, Ain,Bin) begin + if (OE== 1'b0 & DIR == 1'b1) + Bout = Ain; + else if (OE== 1'b0 & DIR == 1'b0) + Aout = Bin; +end +endmodule \ No newline at end of file diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS373.sv b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS373.sv new file mode 100644 index 00000000..fef4e1a8 --- /dev/null +++ b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/TTL74LS373.sv @@ -0,0 +1,84 @@ +module TTL74LS373 ( +input LE, +input [8:1] D, +input OE_n, +output [8:1] Q +); + +reg SYNTHESIZED_WIRE_0; +reg SYNTHESIZED_WIRE_2; +reg SYNTHESIZED_WIRE_4; +reg SYNTHESIZED_WIRE_6; +reg SYNTHESIZED_WIRE_8; +reg SYNTHESIZED_WIRE_10; +reg SYNTHESIZED_WIRE_12; +reg SYNTHESIZED_WIRE_14; + + + +always@(LE or D[1]) +begin +if (LE) + SYNTHESIZED_WIRE_0 <= D[1]; +end + + +always@(LE or D[2]) +begin +if (LE) + SYNTHESIZED_WIRE_2 <= D[2]; +end + + +always@(LE or D[3]) +begin +if (LE) + SYNTHESIZED_WIRE_4 <= D[3]; +end + + +always@(LE or D[4]) +begin +if (LE) + SYNTHESIZED_WIRE_6 <= D[4]; +end + + +always@(LE or D[5]) +begin +if (LE) + SYNTHESIZED_WIRE_8 <= D[5]; +end + + +always@(LE or D[6]) +begin +if (LE) + SYNTHESIZED_WIRE_10 <= D[6]; +end + + +always@(LE or D[7]) +begin +if (LE) + SYNTHESIZED_WIRE_12 <= D[7]; +end + + +always@(LE or D[8]) +begin +if (LE) + SYNTHESIZED_WIRE_14 <= D[8]; +end + +assign Q[1] = OE_n ? SYNTHESIZED_WIRE_0 : 1'bz; +assign Q[2] = OE_n ? SYNTHESIZED_WIRE_2 : 1'bz; +assign Q[3] = OE_n ? SYNTHESIZED_WIRE_4 : 1'bz; +assign Q[4] = OE_n ? SYNTHESIZED_WIRE_6 : 1'bz; +assign Q[5] = OE_n ? SYNTHESIZED_WIRE_8 : 1'bz; +assign Q[6] = OE_n ? SYNTHESIZED_WIRE_10 : 1'bz; +assign Q[7] = OE_n ? SYNTHESIZED_WIRE_12 : 1'bz; +assign Q[8] = OE_n ? SYNTHESIZED_WIRE_14 : 1'bz; + + +endmodule diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/build_id.v b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/build_id.v index 1a73ebcb..b04cd4ab 100644 --- a/Computer_MiST/Sharp - MZ-80K_MiST/rtl/build_id.v +++ b/Computer_MiST/Sharp - MZ-80K_MiST/rtl/build_id.v @@ -1,2 +1,2 @@ -`define BUILD_DATE "180930" -`define BUILD_TIME "151025" +`define BUILD_DATE "181212" +`define BUILD_TIME "194439" diff --git a/Computer_MiST/Sharp - MZ-80K_MiST/suc_hires2.jpg b/Computer_MiST/Sharp - MZ-80K_MiST/suc_hires2.jpg new file mode 100644 index 00000000..026e351b Binary files /dev/null and b/Computer_MiST/Sharp - MZ-80K_MiST/suc_hires2.jpg differ